Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 16:28:58.195941 lava-dispatcher, installed at version: 2024.03
2 16:28:58.196151 start: 0 validate
3 16:28:58.196265 Start time: 2024-06-17 16:28:58.196260+00:00 (UTC)
4 16:28:58.196391 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:28:58.196530 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 16:28:58.472236 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:28:58.472463 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:28:58.738325 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:28:58.739089 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:29:59.069891 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:29:59.070623 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:29:59.601360 validate duration: 61.41
14 16:29:59.601630 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:29:59.601739 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:29:59.601833 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:29:59.601986 Not decompressing ramdisk as can be used compressed.
18 16:29:59.602081 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 16:29:59.602179 saving as /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/ramdisk/rootfs.cpio.gz
20 16:29:59.602330 total size: 39026414 (37 MB)
21 16:30:03.162588 progress 0 % (0 MB)
22 16:30:03.206744 progress 5 % (1 MB)
23 16:30:03.223169 progress 10 % (3 MB)
24 16:30:03.234526 progress 15 % (5 MB)
25 16:30:03.244434 progress 20 % (7 MB)
26 16:30:03.254001 progress 25 % (9 MB)
27 16:30:03.263914 progress 30 % (11 MB)
28 16:30:03.273508 progress 35 % (13 MB)
29 16:30:03.283341 progress 40 % (14 MB)
30 16:30:03.292863 progress 45 % (16 MB)
31 16:30:03.302644 progress 50 % (18 MB)
32 16:30:03.312456 progress 55 % (20 MB)
33 16:30:03.322102 progress 60 % (22 MB)
34 16:30:03.332034 progress 65 % (24 MB)
35 16:30:03.341574 progress 70 % (26 MB)
36 16:30:03.351225 progress 75 % (27 MB)
37 16:30:03.361032 progress 80 % (29 MB)
38 16:30:03.371674 progress 85 % (31 MB)
39 16:30:03.381510 progress 90 % (33 MB)
40 16:30:03.391384 progress 95 % (35 MB)
41 16:30:03.402331 progress 100 % (37 MB)
42 16:30:03.402681 37 MB downloaded in 3.80 s (9.79 MB/s)
43 16:30:03.402900 end: 1.1.1 http-download (duration 00:00:04) [common]
45 16:30:03.403142 end: 1.1 download-retry (duration 00:00:04) [common]
46 16:30:03.403234 start: 1.2 download-retry (timeout 00:09:56) [common]
47 16:30:03.403393 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 16:30:03.403639 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:30:03.403821 saving as /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/kernel/Image
50 16:30:03.403920 total size: 54813184 (52 MB)
51 16:30:03.404004 No compression specified
52 16:30:24.179975 progress 0 % (0 MB)
53 16:30:24.221885 progress 5 % (2 MB)
54 16:30:24.236491 progress 10 % (5 MB)
55 16:30:24.250741 progress 15 % (7 MB)
56 16:30:24.265029 progress 20 % (10 MB)
57 16:30:24.279218 progress 25 % (13 MB)
58 16:30:24.292817 progress 30 % (15 MB)
59 16:30:24.306632 progress 35 % (18 MB)
60 16:30:24.320317 progress 40 % (20 MB)
61 16:30:24.334023 progress 45 % (23 MB)
62 16:30:24.347904 progress 50 % (26 MB)
63 16:30:24.361806 progress 55 % (28 MB)
64 16:30:24.375492 progress 60 % (31 MB)
65 16:30:24.389315 progress 65 % (34 MB)
66 16:30:24.402792 progress 70 % (36 MB)
67 16:30:24.416455 progress 75 % (39 MB)
68 16:30:24.430123 progress 80 % (41 MB)
69 16:30:24.443765 progress 85 % (44 MB)
70 16:30:24.457511 progress 90 % (47 MB)
71 16:30:24.471175 progress 95 % (49 MB)
72 16:30:24.484401 progress 100 % (52 MB)
73 16:30:24.484612 52 MB downloaded in 21.08 s (2.48 MB/s)
74 16:30:24.484762 end: 1.2.1 http-download (duration 00:00:21) [common]
76 16:30:24.484969 end: 1.2 download-retry (duration 00:00:21) [common]
77 16:30:24.485051 start: 1.3 download-retry (timeout 00:09:35) [common]
78 16:30:24.485127 start: 1.3.1 http-download (timeout 00:09:35) [common]
79 16:30:24.485256 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:30:24.485317 saving as /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/dtb/mt8192-asurada-spherion-r0.dtb
81 16:30:24.485370 total size: 47258 (0 MB)
82 16:30:24.485423 No compression specified
83 16:30:24.750296 progress 69 % (0 MB)
84 16:30:24.751880 progress 100 % (0 MB)
85 16:30:24.752781 0 MB downloaded in 0.27 s (0.17 MB/s)
86 16:30:24.753526 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:30:24.754939 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:30:24.755447 start: 1.4 download-retry (timeout 00:09:35) [common]
90 16:30:24.755956 start: 1.4.1 http-download (timeout 00:09:35) [common]
91 16:30:24.756626 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:30:24.756994 saving as /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/modules/modules.tar
93 16:30:24.757395 total size: 8628772 (8 MB)
94 16:30:24.757794 Using unxz to decompress xz
95 16:30:25.020145 progress 0 % (0 MB)
96 16:30:25.046694 progress 5 % (0 MB)
97 16:30:25.069905 progress 10 % (0 MB)
98 16:30:25.092661 progress 15 % (1 MB)
99 16:30:25.115561 progress 20 % (1 MB)
100 16:30:25.139317 progress 25 % (2 MB)
101 16:30:25.162469 progress 30 % (2 MB)
102 16:30:25.187547 progress 35 % (2 MB)
103 16:30:25.210956 progress 40 % (3 MB)
104 16:30:25.234288 progress 45 % (3 MB)
105 16:30:25.258952 progress 50 % (4 MB)
106 16:30:25.282282 progress 55 % (4 MB)
107 16:30:25.305760 progress 60 % (4 MB)
108 16:30:25.332320 progress 65 % (5 MB)
109 16:30:25.356077 progress 70 % (5 MB)
110 16:30:25.378937 progress 75 % (6 MB)
111 16:30:25.402055 progress 80 % (6 MB)
112 16:30:25.428059 progress 85 % (7 MB)
113 16:30:25.453795 progress 90 % (7 MB)
114 16:30:25.478618 progress 95 % (7 MB)
115 16:30:25.502226 progress 100 % (8 MB)
116 16:30:25.507094 8 MB downloaded in 0.75 s (10.98 MB/s)
117 16:30:25.507255 end: 1.4.1 http-download (duration 00:00:01) [common]
119 16:30:25.507492 end: 1.4 download-retry (duration 00:00:01) [common]
120 16:30:25.507587 start: 1.5 prepare-tftp-overlay (timeout 00:09:34) [common]
121 16:30:25.507679 start: 1.5.1 extract-nfsrootfs (timeout 00:09:34) [common]
122 16:30:25.507767 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:30:25.507877 start: 1.5.2 lava-overlay (timeout 00:09:34) [common]
124 16:30:25.508083 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv
125 16:30:25.508233 makedir: /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin
126 16:30:25.508359 makedir: /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/tests
127 16:30:25.508481 makedir: /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/results
128 16:30:25.508580 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-add-keys
129 16:30:25.508721 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-add-sources
130 16:30:25.508855 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-background-process-start
131 16:30:25.509008 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-background-process-stop
132 16:30:25.509146 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-common-functions
133 16:30:25.509279 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-echo-ipv4
134 16:30:25.509431 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-install-packages
135 16:30:25.509581 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-installed-packages
136 16:30:25.509707 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-os-build
137 16:30:25.509843 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-probe-channel
138 16:30:25.509970 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-probe-ip
139 16:30:25.510102 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-target-ip
140 16:30:25.510294 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-target-mac
141 16:30:25.510445 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-target-storage
142 16:30:25.510578 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-case
143 16:30:25.510731 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-event
144 16:30:25.510883 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-feedback
145 16:30:25.511034 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-raise
146 16:30:25.511190 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-reference
147 16:30:25.511386 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-runner
148 16:30:25.511538 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-set
149 16:30:25.511690 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-test-shell
150 16:30:25.511844 Updating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-install-packages (oe)
151 16:30:25.512022 Updating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/bin/lava-installed-packages (oe)
152 16:30:25.512170 Creating /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/environment
153 16:30:25.512291 LAVA metadata
154 16:30:25.512388 - LAVA_JOB_ID=14396103
155 16:30:25.512481 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:30:25.512614 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:34) [common]
157 16:30:25.512699 skipped lava-vland-overlay
158 16:30:25.512807 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:30:25.512921 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:34) [common]
160 16:30:25.513008 skipped lava-multinode-overlay
161 16:30:25.513115 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:30:25.513222 start: 1.5.2.3 test-definition (timeout 00:09:34) [common]
163 16:30:25.513315 Loading test definitions
164 16:30:25.513430 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:34) [common]
165 16:30:25.513520 Using /lava-14396103 at stage 0
166 16:30:25.513919 uuid=14396103_1.5.2.3.1 testdef=None
167 16:30:25.514033 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:30:25.514144 start: 1.5.2.3.2 test-overlay (timeout 00:09:34) [common]
169 16:30:25.514652 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:30:25.514875 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:34) [common]
172 16:30:25.515439 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:30:25.515672 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:34) [common]
175 16:30:25.516213 runner path: /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/0/tests/0_cros-ec test_uuid 14396103_1.5.2.3.1
176 16:30:25.516366 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:30:25.516571 Creating lava-test-runner.conf files
179 16:30:25.516662 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396103/lava-overlay-df0ibirv/lava-14396103/0 for stage 0
180 16:30:25.516783 - 0_cros-ec
181 16:30:25.516909 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:30:25.517024 start: 1.5.2.4 compress-overlay (timeout 00:09:34) [common]
183 16:30:25.525405 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:30:25.525529 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
185 16:30:25.525621 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:30:25.525715 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:30:25.525806 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
188 16:30:26.707183 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 16:30:26.707334 start: 1.5.4 extract-modules (timeout 00:09:33) [common]
190 16:30:26.707409 extracting modules file /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396103/extract-overlay-ramdisk-gd2uc7cx/ramdisk
191 16:30:26.931454 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:30:26.931596 start: 1.5.5 apply-overlay-tftp (timeout 00:09:33) [common]
193 16:30:26.931681 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396103/compress-overlay-g_fz5m9e/overlay-1.5.2.4.tar.gz to ramdisk
194 16:30:26.931745 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396103/compress-overlay-g_fz5m9e/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396103/extract-overlay-ramdisk-gd2uc7cx/ramdisk
195 16:30:26.937985 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:30:26.938079 start: 1.5.6 configure-preseed-file (timeout 00:09:33) [common]
197 16:30:26.938160 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:30:26.938247 start: 1.5.7 compress-ramdisk (timeout 00:09:33) [common]
199 16:30:26.938315 Building ramdisk /var/lib/lava/dispatcher/tmp/14396103/extract-overlay-ramdisk-gd2uc7cx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396103/extract-overlay-ramdisk-gd2uc7cx/ramdisk
200 16:30:27.811268 >> 336002 blocks
201 16:30:33.005649 rename /var/lib/lava/dispatcher/tmp/14396103/extract-overlay-ramdisk-gd2uc7cx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/ramdisk/ramdisk.cpio.gz
202 16:30:33.005826 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 16:30:33.005918 start: 1.5.8 prepare-kernel (timeout 00:09:27) [common]
204 16:30:33.005997 start: 1.5.8.1 prepare-fit (timeout 00:09:27) [common]
205 16:30:33.006069 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/kernel/Image']
206 16:30:46.441174 Returned 0 in 13 seconds
207 16:30:46.541740 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/kernel/image.itb
208 16:30:47.414520 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:30:47.414657 output: Created: Mon Jun 17 17:30:47 2024
210 16:30:47.414725 output: Image 0 (kernel-1)
211 16:30:47.414788 output: Description:
212 16:30:47.414846 output: Created: Mon Jun 17 17:30:47 2024
213 16:30:47.414909 output: Type: Kernel Image
214 16:30:47.414968 output: Compression: lzma compressed
215 16:30:47.415030 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
216 16:30:47.415089 output: Architecture: AArch64
217 16:30:47.415148 output: OS: Linux
218 16:30:47.415206 output: Load Address: 0x00000000
219 16:30:47.415259 output: Entry Point: 0x00000000
220 16:30:47.415313 output: Hash algo: crc32
221 16:30:47.415366 output: Hash value: 106ffd6f
222 16:30:47.415420 output: Image 1 (fdt-1)
223 16:30:47.415468 output: Description: mt8192-asurada-spherion-r0
224 16:30:47.415516 output: Created: Mon Jun 17 17:30:47 2024
225 16:30:47.415567 output: Type: Flat Device Tree
226 16:30:47.415616 output: Compression: uncompressed
227 16:30:47.415664 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 16:30:47.415715 output: Architecture: AArch64
229 16:30:47.415764 output: Hash algo: crc32
230 16:30:47.415811 output: Hash value: 0f8e4d2e
231 16:30:47.415858 output: Image 2 (ramdisk-1)
232 16:30:47.415938 output: Description: unavailable
233 16:30:47.416003 output: Created: Mon Jun 17 17:30:47 2024
234 16:30:47.416052 output: Type: RAMDisk Image
235 16:30:47.416102 output: Compression: uncompressed
236 16:30:47.416151 output: Data Size: 52152721 Bytes = 50930.39 KiB = 49.74 MiB
237 16:30:47.416200 output: Architecture: AArch64
238 16:30:47.416248 output: OS: Linux
239 16:30:47.416296 output: Load Address: unavailable
240 16:30:47.416344 output: Entry Point: unavailable
241 16:30:47.416392 output: Hash algo: crc32
242 16:30:47.416440 output: Hash value: 78bd9b11
243 16:30:47.416488 output: Default Configuration: 'conf-1'
244 16:30:47.416536 output: Configuration 0 (conf-1)
245 16:30:47.416584 output: Description: mt8192-asurada-spherion-r0
246 16:30:47.416631 output: Kernel: kernel-1
247 16:30:47.416679 output: Init Ramdisk: ramdisk-1
248 16:30:47.416728 output: FDT: fdt-1
249 16:30:47.416776 output: Loadables: kernel-1
250 16:30:47.416825 output:
251 16:30:47.416967 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 16:30:47.417054 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 16:30:47.417141 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 16:30:47.417220 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:12) [common]
255 16:30:47.417295 No LXC device requested
256 16:30:47.417367 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:30:47.417445 start: 1.7 deploy-device-env (timeout 00:09:12) [common]
258 16:30:47.417515 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:30:47.417577 Checking files for TFTP limit of 4294967296 bytes.
260 16:30:47.418072 end: 1 tftp-deploy (duration 00:00:48) [common]
261 16:30:47.418174 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:30:47.418267 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:30:47.418373 substitutions:
264 16:30:47.418432 - {DTB}: 14396103/tftp-deploy-kg8v5wn8/dtb/mt8192-asurada-spherion-r0.dtb
265 16:30:47.418490 - {INITRD}: 14396103/tftp-deploy-kg8v5wn8/ramdisk/ramdisk.cpio.gz
266 16:30:47.418542 - {KERNEL}: 14396103/tftp-deploy-kg8v5wn8/kernel/Image
267 16:30:47.418593 - {LAVA_MAC}: None
268 16:30:47.418643 - {PRESEED_CONFIG}: None
269 16:30:47.418693 - {PRESEED_LOCAL}: None
270 16:30:47.418742 - {RAMDISK}: 14396103/tftp-deploy-kg8v5wn8/ramdisk/ramdisk.cpio.gz
271 16:30:47.418797 - {ROOT_PART}: None
272 16:30:47.418847 - {ROOT}: None
273 16:30:47.418896 - {SERVER_IP}: 192.168.201.1
274 16:30:47.418945 - {TEE}: None
275 16:30:47.418993 Parsed boot commands:
276 16:30:47.419040 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:30:47.419188 Parsed boot commands: tftpboot 192.168.201.1 14396103/tftp-deploy-kg8v5wn8/kernel/image.itb 14396103/tftp-deploy-kg8v5wn8/kernel/cmdline
278 16:30:47.419270 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:30:47.419343 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:30:47.419419 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:30:47.419494 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:30:47.419556 Not connected, no need to disconnect.
283 16:30:47.419622 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:30:47.419696 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:30:47.419755 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 16:30:47.423214 Setting prompt string to ['lava-test: # ']
287 16:30:47.423535 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:30:47.423624 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:30:47.423738 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:30:47.423866 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:30:47.424163 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
292 16:31:01.001615 Returned 0 in 13 seconds
293 16:31:01.102312 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 16:31:01.102781 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 16:31:01.102952 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 16:31:01.103111 Setting prompt string to 'Starting depthcharge on Spherion...'
298 16:31:01.103224 Changing prompt to 'Starting depthcharge on Spherion...'
299 16:31:01.103344 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 16:31:01.104130 [Enter `^Ec?' for help]
301 16:31:01.104364
302 16:31:01.104569
303 16:31:01.104735 F0: 102B 0000
304 16:31:01.104895
305 16:31:01.105047 F3: 1001 0000 [0200]
306 16:31:01.105205
307 16:31:01.105366 F3: 1001 0000
308 16:31:01.105516
309 16:31:01.105625 F7: 102D 0000
310 16:31:01.105722
311 16:31:01.105816 F1: 0000 0000
312 16:31:01.105913
313 16:31:01.106020 V0: 0000 0000 [0001]
314 16:31:01.106111
315 16:31:01.106206 00: 0007 8000
316 16:31:01.106301
317 16:31:01.106378 01: 0000 0000
318 16:31:01.106457
319 16:31:01.106532 BP: 0C00 0209 [0000]
320 16:31:01.106606
321 16:31:01.106680 G0: 1182 0000
322 16:31:01.106755
323 16:31:01.106830 EC: 0000 0021 [4000]
324 16:31:01.106905
325 16:31:01.106980 S7: 0000 0000 [0000]
326 16:31:01.107055
327 16:31:01.107129 CC: 0000 0000 [0001]
328 16:31:01.107203
329 16:31:01.107278 T0: 0000 0040 [010F]
330 16:31:01.107354
331 16:31:01.107428 Jump to BL
332 16:31:01.107501
333 16:31:01.107576
334 16:31:01.107650
335 16:31:01.107725 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 16:31:01.107807 ARM64: Exception handlers installed.
337 16:31:01.107886 ARM64: Testing exception
338 16:31:01.107963 ARM64: Done test exception
339 16:31:01.108040 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 16:31:01.108117 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 16:31:01.108196 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 16:31:01.108273 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 16:31:01.108351 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 16:31:01.108428 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 16:31:01.108506 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 16:31:01.108584 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 16:31:01.108661 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 16:31:01.108738 WDT: Last reset was cold boot
349 16:31:01.108813 SPI1(PAD0) initialized at 2873684 Hz
350 16:31:01.108896 SPI5(PAD0) initialized at 992727 Hz
351 16:31:01.108975 VBOOT: Loading verstage.
352 16:31:01.109050 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 16:31:01.109137 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 16:31:01.109216 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 16:31:01.109293 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 16:31:01.109370 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 16:31:01.109448 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 16:31:01.109524 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 16:31:01.109611
360 16:31:01.109687
361 16:31:01.109763 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 16:31:01.109843 ARM64: Exception handlers installed.
363 16:31:01.109920 ARM64: Testing exception
364 16:31:01.109996 ARM64: Done test exception
365 16:31:01.110073 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 16:31:01.110150 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 16:31:01.110237 Probing TPM: . done!
368 16:31:01.110315 TPM ready after 0 ms
369 16:31:01.110391 Connected to device vid:did:rid of 1ae0:0028:00
370 16:31:01.110468 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
371 16:31:01.110546 Initialized TPM device CR50 revision 0
372 16:31:01.110623 tlcl_send_startup: Startup return code is 0
373 16:31:01.110699 TPM: setup succeeded
374 16:31:01.110775 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 16:31:01.110853 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 16:31:01.110929 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 16:31:01.111006 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:31:01.111082 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 16:31:01.111169 in-header: 03 07 00 00 08 00 00 00
380 16:31:01.111237 in-data: aa e4 47 04 13 02 00 00
381 16:31:01.111305 Chrome EC: UHEPI supported
382 16:31:01.111371 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 16:31:01.111439 in-header: 03 a9 00 00 08 00 00 00
384 16:31:01.111505 in-data: 84 60 60 08 00 00 00 00
385 16:31:01.111572 Phase 1
386 16:31:01.111638 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 16:31:01.111705 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 16:31:01.111772 VB2:vb2_check_recovery() Recovery was requested manually
389 16:31:01.111839 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 16:31:01.111907 Recovery requested (1009000e)
391 16:31:01.111972 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 16:31:01.112044 tlcl_extend: response is 0
393 16:31:01.112114 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 16:31:01.112181 tlcl_extend: response is 0
395 16:31:01.112248 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 16:31:01.112316 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 16:31:01.112383 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 16:31:01.112450
399 16:31:01.112516
400 16:31:01.112582 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 16:31:01.112661 ARM64: Exception handlers installed.
402 16:31:01.112730 ARM64: Testing exception
403 16:31:01.112796 ARM64: Done test exception
404 16:31:01.112863 pmic_efuse_setting: Set efuses in 11 msecs
405 16:31:01.112930 pmwrap_interface_init: Select PMIF_VLD_RDY
406 16:31:01.112997 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 16:31:01.113065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 16:31:01.113342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 16:31:01.113418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 16:31:01.113486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 16:31:01.113553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 16:31:01.113619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 16:31:01.113689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 16:31:01.113756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 16:31:01.113824 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 16:31:01.113891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 16:31:01.113957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 16:31:01.114024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 16:31:01.114090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 16:31:01.114156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 16:31:01.114235 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 16:31:01.114305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 16:31:01.114372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 16:31:01.114440 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 16:31:01.114507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 16:31:01.114574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 16:31:01.114641 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 16:31:01.114708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 16:31:01.114775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 16:31:01.114841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 16:31:01.114908 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 16:31:01.114974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 16:31:01.115041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 16:31:01.115107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 16:31:01.115174 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 16:31:01.115242 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 16:31:01.115310 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 16:31:01.115376 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 16:31:01.115442 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 16:31:01.115508 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 16:31:01.115575 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 16:31:01.115642 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 16:31:01.115709 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 16:31:01.115775 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 16:31:01.115842 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 16:31:01.115908 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 16:31:01.115973 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 16:31:01.116039 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 16:31:01.116167 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 16:31:01.116257 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 16:31:01.116320 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 16:31:01.116381 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 16:31:01.116440 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 16:31:01.116500 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 16:31:01.116559 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 16:31:01.116618 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 16:31:01.116678 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 16:31:01.116738 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 16:31:01.116799 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 16:31:01.116859 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 16:31:01.116919 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 16:31:01.116978 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 16:31:01.117038 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 16:31:01.117098 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:31:01.117157 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x12
466 16:31:01.117217 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 16:31:01.117278 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 16:31:01.117338 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 16:31:01.117397 [RTC]rtc_get_frequency_meter,154: input=15, output=766
470 16:31:01.117457 [RTC]rtc_get_frequency_meter,154: input=23, output=950
471 16:31:01.117516 [RTC]rtc_get_frequency_meter,154: input=19, output=857
472 16:31:01.117576 [RTC]rtc_get_frequency_meter,154: input=17, output=811
473 16:31:01.117635 [RTC]rtc_get_frequency_meter,154: input=16, output=787
474 16:31:01.117694 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 16:31:01.117754 [RTC]rtc_get_frequency_meter,154: input=17, output=811
476 16:31:01.117813 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 16:31:01.117874 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 16:31:01.118133 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 16:31:01.118275 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 16:31:01.118398 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 16:31:01.118520 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 16:31:01.118638 ADC[4]: Raw value=669695 ID=5
483 16:31:01.118742 ADC[3]: Raw value=212549 ID=1
484 16:31:01.118842 RAM Code: 0x51
485 16:31:01.118937 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 16:31:01.119033 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 16:31:01.119113 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 16:31:01.119175 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 16:31:01.119235 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 16:31:01.119296 in-header: 03 07 00 00 08 00 00 00
491 16:31:01.119356 in-data: aa e4 47 04 13 02 00 00
492 16:31:01.119415 Chrome EC: UHEPI supported
493 16:31:01.119474 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 16:31:01.119534 in-header: 03 a9 00 00 08 00 00 00
495 16:31:01.119593 in-data: 84 60 60 08 00 00 00 00
496 16:31:01.119652 MRC: failed to locate region type 0.
497 16:31:01.119712 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 16:31:01.119772 DRAM-K: Running full calibration
499 16:31:01.119831 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 16:31:01.119890 header.status = 0x0
501 16:31:01.119950 header.version = 0x6 (expected: 0x6)
502 16:31:01.120010 header.size = 0xd00 (expected: 0xd00)
503 16:31:01.120070 header.flags = 0x0
504 16:31:01.120129 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 16:31:01.120190 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 16:31:01.120251 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 16:31:01.120311 dram_init: ddr_geometry: 0
508 16:31:01.120372 [EMI] MDL number = 0
509 16:31:01.120432 [EMI] Get MDL freq = 0
510 16:31:01.120494 dram_init: ddr_type: 0
511 16:31:01.120555 is_discrete_lpddr4: 1
512 16:31:01.120614 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 16:31:01.120674
514 16:31:01.120732
515 16:31:01.120791 [Bian_co] ETT version 0.0.0.1
516 16:31:01.120850 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 16:31:01.120910
518 16:31:01.120969 dramc_set_vcore_voltage set vcore to 650000
519 16:31:01.121029 Read voltage for 800, 4
520 16:31:01.121088 Vio18 = 0
521 16:31:01.121147 Vcore = 650000
522 16:31:01.121217 Vdram = 0
523 16:31:01.121270 Vddq = 0
524 16:31:01.121323 Vmddr = 0
525 16:31:01.121375 dram_init: config_dvfs: 1
526 16:31:01.121428 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 16:31:01.121482 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 16:31:01.121536 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 16:31:01.121590 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 16:31:01.121643 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 16:31:01.121696 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 16:31:01.121749 MEM_TYPE=3, freq_sel=18
533 16:31:01.121802 sv_algorithm_assistance_LP4_1600
534 16:31:01.121855 ============ PULL DRAM RESETB DOWN ============
535 16:31:01.121915 ========== PULL DRAM RESETB DOWN end =========
536 16:31:01.121972 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 16:31:01.122026 ===================================
538 16:31:01.122080 LPDDR4 DRAM CONFIGURATION
539 16:31:01.122134 ===================================
540 16:31:01.122188 EX_ROW_EN[0] = 0x0
541 16:31:01.122253 EX_ROW_EN[1] = 0x0
542 16:31:01.122307 LP4Y_EN = 0x0
543 16:31:01.122361 WORK_FSP = 0x0
544 16:31:01.122414 WL = 0x2
545 16:31:01.122466 RL = 0x2
546 16:31:01.122519 BL = 0x2
547 16:31:01.122572 RPST = 0x0
548 16:31:01.122625 RD_PRE = 0x0
549 16:31:01.122678 WR_PRE = 0x1
550 16:31:01.122731 WR_PST = 0x0
551 16:31:01.122785 DBI_WR = 0x0
552 16:31:01.122838 DBI_RD = 0x0
553 16:31:01.122890 OTF = 0x1
554 16:31:01.122944 ===================================
555 16:31:01.122998 ===================================
556 16:31:01.123051 ANA top config
557 16:31:01.123103 ===================================
558 16:31:01.123157 DLL_ASYNC_EN = 0
559 16:31:01.123210 ALL_SLAVE_EN = 1
560 16:31:01.123264 NEW_RANK_MODE = 1
561 16:31:01.123318 DLL_IDLE_MODE = 1
562 16:31:01.123371 LP45_APHY_COMB_EN = 1
563 16:31:01.123424 TX_ODT_DIS = 1
564 16:31:01.123477 NEW_8X_MODE = 1
565 16:31:01.123531 ===================================
566 16:31:01.123584 ===================================
567 16:31:01.123638 data_rate = 1600
568 16:31:01.123691 CKR = 1
569 16:31:01.123744 DQ_P2S_RATIO = 8
570 16:31:01.123797 ===================================
571 16:31:01.123850 CA_P2S_RATIO = 8
572 16:31:01.123903 DQ_CA_OPEN = 0
573 16:31:01.123956 DQ_SEMI_OPEN = 0
574 16:31:01.124009 CA_SEMI_OPEN = 0
575 16:31:01.124063 CA_FULL_RATE = 0
576 16:31:01.124115 DQ_CKDIV4_EN = 1
577 16:31:01.124167 CA_CKDIV4_EN = 1
578 16:31:01.124220 CA_PREDIV_EN = 0
579 16:31:01.124273 PH8_DLY = 0
580 16:31:01.124326 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 16:31:01.124380 DQ_AAMCK_DIV = 4
582 16:31:01.124432 CA_AAMCK_DIV = 4
583 16:31:01.124497 CA_ADMCK_DIV = 4
584 16:31:01.124553 DQ_TRACK_CA_EN = 0
585 16:31:01.124607 CA_PICK = 800
586 16:31:01.124660 CA_MCKIO = 800
587 16:31:01.124712 MCKIO_SEMI = 0
588 16:31:01.124765 PLL_FREQ = 3068
589 16:31:01.124819 DQ_UI_PI_RATIO = 32
590 16:31:01.124873 CA_UI_PI_RATIO = 0
591 16:31:01.124926 ===================================
592 16:31:01.124980 ===================================
593 16:31:01.125034 memory_type:LPDDR4
594 16:31:01.125087 GP_NUM : 10
595 16:31:01.125140 SRAM_EN : 1
596 16:31:01.125192 MD32_EN : 0
597 16:31:01.125245 ===================================
598 16:31:01.125511 [ANA_INIT] >>>>>>>>>>>>>>
599 16:31:01.125579 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 16:31:01.125641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 16:31:01.125695 ===================================
602 16:31:01.125749 data_rate = 1600,PCW = 0X7600
603 16:31:01.125803 ===================================
604 16:31:01.125856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 16:31:01.125909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 16:31:01.125989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 16:31:01.126076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 16:31:01.126173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 16:31:01.126247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 16:31:01.126298 [ANA_INIT] flow start
611 16:31:01.126347 [ANA_INIT] PLL >>>>>>>>
612 16:31:01.126395 [ANA_INIT] PLL <<<<<<<<
613 16:31:01.126443 [ANA_INIT] MIDPI >>>>>>>>
614 16:31:01.126492 [ANA_INIT] MIDPI <<<<<<<<
615 16:31:01.126541 [ANA_INIT] DLL >>>>>>>>
616 16:31:01.126589 [ANA_INIT] flow end
617 16:31:01.126638 ============ LP4 DIFF to SE enter ============
618 16:31:01.126688 ============ LP4 DIFF to SE exit ============
619 16:31:01.126737 [ANA_INIT] <<<<<<<<<<<<<
620 16:31:01.126787 [Flow] Enable top DCM control >>>>>
621 16:31:01.126837 [Flow] Enable top DCM control <<<<<
622 16:31:01.126885 Enable DLL master slave shuffle
623 16:31:01.126933 ==============================================================
624 16:31:01.126982 Gating Mode config
625 16:31:01.127030 ==============================================================
626 16:31:01.127080 Config description:
627 16:31:01.127129 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 16:31:01.127178 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 16:31:01.127228 SELPH_MODE 0: By rank 1: By Phase
630 16:31:01.127276 ==============================================================
631 16:31:01.127325 GAT_TRACK_EN = 1
632 16:31:01.127373 RX_GATING_MODE = 2
633 16:31:01.127421 RX_GATING_TRACK_MODE = 2
634 16:31:01.127470 SELPH_MODE = 1
635 16:31:01.127519 PICG_EARLY_EN = 1
636 16:31:01.127567 VALID_LAT_VALUE = 1
637 16:31:01.127615 ==============================================================
638 16:31:01.127664 Enter into Gating configuration >>>>
639 16:31:01.127713 Exit from Gating configuration <<<<
640 16:31:01.127761 Enter into DVFS_PRE_config >>>>>
641 16:31:01.127810 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 16:31:01.127862 Exit from DVFS_PRE_config <<<<<
643 16:31:01.127912 Enter into PICG configuration >>>>
644 16:31:01.127961 Exit from PICG configuration <<<<
645 16:31:01.128010 [RX_INPUT] configuration >>>>>
646 16:31:01.128058 [RX_INPUT] configuration <<<<<
647 16:31:01.128107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 16:31:01.128156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 16:31:01.128204 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 16:31:01.128253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 16:31:01.128303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 16:31:01.128355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 16:31:01.128418 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 16:31:01.128468 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 16:31:01.128517 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 16:31:01.128566 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 16:31:01.128615 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 16:31:01.128663 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 16:31:01.128719 ===================================
660 16:31:01.128772 LPDDR4 DRAM CONFIGURATION
661 16:31:01.128822 ===================================
662 16:31:01.128871 EX_ROW_EN[0] = 0x0
663 16:31:01.128920 EX_ROW_EN[1] = 0x0
664 16:31:01.128968 LP4Y_EN = 0x0
665 16:31:01.129016 WORK_FSP = 0x0
666 16:31:01.129065 WL = 0x2
667 16:31:01.129112 RL = 0x2
668 16:31:01.129160 BL = 0x2
669 16:31:01.129208 RPST = 0x0
670 16:31:01.129255 RD_PRE = 0x0
671 16:31:01.129304 WR_PRE = 0x1
672 16:31:01.129352 WR_PST = 0x0
673 16:31:01.129401 DBI_WR = 0x0
674 16:31:01.129449 DBI_RD = 0x0
675 16:31:01.129498 OTF = 0x1
676 16:31:01.129546 ===================================
677 16:31:01.129596 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 16:31:01.129644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 16:31:01.129693 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 16:31:01.129742 ===================================
681 16:31:01.129791 LPDDR4 DRAM CONFIGURATION
682 16:31:01.129839 ===================================
683 16:31:01.129888 EX_ROW_EN[0] = 0x10
684 16:31:01.129936 EX_ROW_EN[1] = 0x0
685 16:31:01.129985 LP4Y_EN = 0x0
686 16:31:01.130033 WORK_FSP = 0x0
687 16:31:01.130082 WL = 0x2
688 16:31:01.130130 RL = 0x2
689 16:31:01.130178 BL = 0x2
690 16:31:01.130234 RPST = 0x0
691 16:31:01.130285 RD_PRE = 0x0
692 16:31:01.130334 WR_PRE = 0x1
693 16:31:01.130383 WR_PST = 0x0
694 16:31:01.130431 DBI_WR = 0x0
695 16:31:01.130479 DBI_RD = 0x0
696 16:31:01.130527 OTF = 0x1
697 16:31:01.130576 ===================================
698 16:31:01.130624 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 16:31:01.130672 nWR fixed to 40
700 16:31:01.130720 [ModeRegInit_LP4] CH0 RK0
701 16:31:01.130769 [ModeRegInit_LP4] CH0 RK1
702 16:31:01.130817 [ModeRegInit_LP4] CH1 RK0
703 16:31:01.130865 [ModeRegInit_LP4] CH1 RK1
704 16:31:01.130913 match AC timing 12
705 16:31:01.130960 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 16:31:01.131009 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 16:31:01.131253 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 16:31:01.131322 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 16:31:01.131419 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 16:31:01.131513 [EMI DOE] emi_dcm 0
711 16:31:01.131609 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 16:31:01.131703 ==
713 16:31:01.131799 Dram Type= 6, Freq= 0, CH_0, rank 0
714 16:31:01.131895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 16:31:01.131990 ==
716 16:31:01.132083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 16:31:01.132171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 16:31:01.132255 [CA 0] Center 37 (7~68) winsize 62
719 16:31:01.132337 [CA 1] Center 37 (7~68) winsize 62
720 16:31:01.132392 [CA 2] Center 35 (5~66) winsize 62
721 16:31:01.132441 [CA 3] Center 35 (5~66) winsize 62
722 16:31:01.132493 [CA 4] Center 34 (4~65) winsize 62
723 16:31:01.132571 [CA 5] Center 33 (3~64) winsize 62
724 16:31:01.132645
725 16:31:01.132721 [CmdBusTrainingLP45] Vref(ca) range 1: 30
726 16:31:01.132796
727 16:31:01.132871 [CATrainingPosCal] consider 1 rank data
728 16:31:01.132947 u2DelayCellTimex100 = 270/100 ps
729 16:31:01.133023 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 16:31:01.133099 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 16:31:01.133175 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 16:31:01.133251 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
733 16:31:01.133327 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 16:31:01.133403 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 16:31:01.133477
736 16:31:01.133552 CA PerBit enable=1, Macro0, CA PI delay=33
737 16:31:01.133627
738 16:31:01.133702 [CBTSetCACLKResult] CA Dly = 33
739 16:31:01.133777 CS Dly: 5 (0~36)
740 16:31:01.133851 ==
741 16:31:01.133927 Dram Type= 6, Freq= 0, CH_0, rank 1
742 16:31:01.134002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 16:31:01.134080 ==
744 16:31:01.134156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 16:31:01.134268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 16:31:01.134319 [CA 0] Center 37 (7~68) winsize 62
747 16:31:01.134368 [CA 1] Center 37 (6~68) winsize 63
748 16:31:01.134416 [CA 2] Center 35 (4~66) winsize 63
749 16:31:01.134480 [CA 3] Center 34 (4~65) winsize 62
750 16:31:01.134531 [CA 4] Center 33 (3~64) winsize 62
751 16:31:01.134578 [CA 5] Center 33 (3~64) winsize 62
752 16:31:01.134626
753 16:31:01.134672 [CmdBusTrainingLP45] Vref(ca) range 1: 30
754 16:31:01.134720
755 16:31:01.134766 [CATrainingPosCal] consider 2 rank data
756 16:31:01.134814 u2DelayCellTimex100 = 270/100 ps
757 16:31:01.134862 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 16:31:01.134910 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 16:31:01.134958 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 16:31:01.135005 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
761 16:31:01.135052 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
762 16:31:01.135100 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 16:31:01.135147
764 16:31:01.135194 CA PerBit enable=1, Macro0, CA PI delay=33
765 16:31:01.135241
766 16:31:01.135288 [CBTSetCACLKResult] CA Dly = 33
767 16:31:01.135335 CS Dly: 6 (0~38)
768 16:31:01.135389
769 16:31:01.135437 ----->DramcWriteLeveling(PI) begin...
770 16:31:01.135487 ==
771 16:31:01.135535 Dram Type= 6, Freq= 0, CH_0, rank 0
772 16:31:01.135584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 16:31:01.135632 ==
774 16:31:01.135683 Write leveling (Byte 0): 30 => 30
775 16:31:01.135733 Write leveling (Byte 1): 29 => 29
776 16:31:01.135780 DramcWriteLeveling(PI) end<-----
777 16:31:01.135827
778 16:31:01.135874 ==
779 16:31:01.135921 Dram Type= 6, Freq= 0, CH_0, rank 0
780 16:31:01.135969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 16:31:01.136017 ==
782 16:31:01.136064 [Gating] SW mode calibration
783 16:31:01.136111 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 16:31:01.136159 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 16:31:01.136207 0 6 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
786 16:31:01.136255 0 6 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
787 16:31:01.136302 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 16:31:01.136350 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 16:31:01.136397 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:31:01.136445 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:31:01.136495 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:31:01.136542 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:31:01.136590 0 7 0 | B1->B0 | 2626 2b2b | 1 1 | (0 0) (0 0)
794 16:31:01.136637 0 7 4 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
795 16:31:01.136685 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 16:31:01.136732 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 16:31:01.136779 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 16:31:01.136827 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 16:31:01.136875 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 16:31:01.136922 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 16:31:01.136969 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
802 16:31:01.137017 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
803 16:31:01.137064 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 16:31:01.137111 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 16:31:01.137159 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 16:31:01.137207 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 16:31:01.137256 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 16:31:01.137304 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 16:31:01.137352 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 16:31:01.137400 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 16:31:01.137448 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 16:31:01.137495 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 16:31:01.137543 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 16:31:01.137795 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 16:31:01.137872 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 16:31:01.137968 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 16:31:01.138064 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
818 16:31:01.138159 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
819 16:31:01.138297 Total UI for P1: 0, mck2ui 16
820 16:31:01.138375 best dqsien dly found for B0: ( 0, 10, 0)
821 16:31:01.138451 Total UI for P1: 0, mck2ui 16
822 16:31:01.138527 best dqsien dly found for B1: ( 0, 10, 0)
823 16:31:01.138603 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
824 16:31:01.138679 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
825 16:31:01.138758
826 16:31:01.138817 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
827 16:31:01.138866 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 16:31:01.138919 [Gating] SW calibration Done
829 16:31:01.138967 ==
830 16:31:01.139016 Dram Type= 6, Freq= 0, CH_0, rank 0
831 16:31:01.139064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
832 16:31:01.139112 ==
833 16:31:01.139159 RX Vref Scan: 0
834 16:31:01.139207
835 16:31:01.139254 RX Vref 0 -> 0, step: 1
836 16:31:01.139301
837 16:31:01.139348 RX Delay -130 -> 252, step: 16
838 16:31:01.139395 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
839 16:31:01.139442 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
840 16:31:01.139489 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
841 16:31:01.139538 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
842 16:31:01.139585 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
843 16:31:01.139632 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
844 16:31:01.139681 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
845 16:31:01.139728 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
846 16:31:01.139776 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
847 16:31:01.139823 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
848 16:31:01.139870 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
849 16:31:01.139918 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
850 16:31:01.139966 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
851 16:31:01.140013 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
852 16:31:01.140061 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
853 16:31:01.140108 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
854 16:31:01.140154 ==
855 16:31:01.140202 Dram Type= 6, Freq= 0, CH_0, rank 0
856 16:31:01.140249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
857 16:31:01.140296 ==
858 16:31:01.140344 DQS Delay:
859 16:31:01.140390 DQS0 = 0, DQS1 = 0
860 16:31:01.140438 DQM Delay:
861 16:31:01.140509 DQM0 = 82, DQM1 = 73
862 16:31:01.140592 DQ Delay:
863 16:31:01.140644 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
864 16:31:01.140692 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
865 16:31:01.140740 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
866 16:31:01.140788 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
867 16:31:01.140835
868 16:31:01.140882
869 16:31:01.140929 ==
870 16:31:01.140976 Dram Type= 6, Freq= 0, CH_0, rank 0
871 16:31:01.141024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
872 16:31:01.141072 ==
873 16:31:01.141118
874 16:31:01.141164
875 16:31:01.141211 TX Vref Scan disable
876 16:31:01.141258 == TX Byte 0 ==
877 16:31:01.141306 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
878 16:31:01.141355 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
879 16:31:01.141402 == TX Byte 1 ==
880 16:31:01.141450 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
881 16:31:01.141497 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
882 16:31:01.141544 ==
883 16:31:01.141592 Dram Type= 6, Freq= 0, CH_0, rank 0
884 16:31:01.246221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
885 16:31:01.246373 ==
886 16:31:01.246433 TX Vref=22, minBit 4, minWin=27, winSum=446
887 16:31:01.246489 TX Vref=24, minBit 0, minWin=27, winSum=450
888 16:31:01.246542 TX Vref=26, minBit 0, minWin=27, winSum=448
889 16:31:01.246597 TX Vref=28, minBit 0, minWin=28, winSum=455
890 16:31:01.246649 TX Vref=30, minBit 0, minWin=28, winSum=455
891 16:31:01.246698 TX Vref=32, minBit 0, minWin=28, winSum=454
892 16:31:01.246747 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
893 16:31:01.246798
894 16:31:01.246848 Final TX Range 1 Vref 28
895 16:31:01.246897
896 16:31:01.246946 ==
897 16:31:01.246995 Dram Type= 6, Freq= 0, CH_0, rank 0
898 16:31:01.247043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 16:31:01.247092 ==
900 16:31:01.247140
901 16:31:01.247188
902 16:31:01.247235 TX Vref Scan disable
903 16:31:01.247283 == TX Byte 0 ==
904 16:31:01.247332 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
905 16:31:01.247381 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
906 16:31:01.247430 == TX Byte 1 ==
907 16:31:01.247477 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
908 16:31:01.247525 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
909 16:31:01.247573
910 16:31:01.247620 [DATLAT]
911 16:31:01.247668 Freq=800, CH0 RK0
912 16:31:01.247717
913 16:31:01.247764 DATLAT Default: 0xa
914 16:31:01.247813 0, 0xFFFF, sum = 0
915 16:31:01.247862 1, 0xFFFF, sum = 0
916 16:31:01.247911 2, 0xFFFF, sum = 0
917 16:31:01.247959 3, 0xFFFF, sum = 0
918 16:31:01.248011 4, 0xFFFF, sum = 0
919 16:31:01.248060 5, 0xFFFF, sum = 0
920 16:31:01.248109 6, 0xFFFF, sum = 0
921 16:31:01.248157 7, 0xFFFF, sum = 0
922 16:31:01.248205 8, 0x0, sum = 1
923 16:31:01.248254 9, 0x0, sum = 2
924 16:31:01.248302 10, 0x0, sum = 3
925 16:31:01.248352 11, 0x0, sum = 4
926 16:31:01.248400 best_step = 9
927 16:31:01.248448
928 16:31:01.248494 ==
929 16:31:01.248541 Dram Type= 6, Freq= 0, CH_0, rank 0
930 16:31:01.248597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
931 16:31:01.248710 ==
932 16:31:01.248781 RX Vref Scan: 1
933 16:31:01.248831
934 16:31:01.248879 Set Vref Range= 32 -> 127
935 16:31:01.248926
936 16:31:01.248974 RX Vref 32 -> 127, step: 1
937 16:31:01.249021
938 16:31:01.249069 RX Delay -111 -> 252, step: 8
939 16:31:01.249116
940 16:31:01.249164 Set Vref, RX VrefLevel [Byte0]: 32
941 16:31:01.249211 [Byte1]: 32
942 16:31:01.249258
943 16:31:01.249305 Set Vref, RX VrefLevel [Byte0]: 33
944 16:31:01.249353 [Byte1]: 33
945 16:31:01.249400
946 16:31:01.249447 Set Vref, RX VrefLevel [Byte0]: 34
947 16:31:01.249495 [Byte1]: 34
948 16:31:01.249543
949 16:31:01.249590 Set Vref, RX VrefLevel [Byte0]: 35
950 16:31:01.249637 [Byte1]: 35
951 16:31:01.249684
952 16:31:01.249730 Set Vref, RX VrefLevel [Byte0]: 36
953 16:31:01.249778 [Byte1]: 36
954 16:31:01.249825
955 16:31:01.249872 Set Vref, RX VrefLevel [Byte0]: 37
956 16:31:01.249919 [Byte1]: 37
957 16:31:01.249966
958 16:31:01.250012 Set Vref, RX VrefLevel [Byte0]: 38
959 16:31:01.250059 [Byte1]: 38
960 16:31:01.250106
961 16:31:01.250153 Set Vref, RX VrefLevel [Byte0]: 39
962 16:31:01.250200 [Byte1]: 39
963 16:31:01.250257
964 16:31:01.250511 Set Vref, RX VrefLevel [Byte0]: 40
965 16:31:01.250566 [Byte1]: 40
966 16:31:01.250636
967 16:31:01.250718 Set Vref, RX VrefLevel [Byte0]: 41
968 16:31:01.250768 [Byte1]: 41
969 16:31:01.250848
970 16:31:01.250910 Set Vref, RX VrefLevel [Byte0]: 42
971 16:31:01.250957 [Byte1]: 42
972 16:31:01.251005
973 16:31:01.251080 Set Vref, RX VrefLevel [Byte0]: 43
974 16:31:01.251143 [Byte1]: 43
975 16:31:01.251191
976 16:31:01.251239 Set Vref, RX VrefLevel [Byte0]: 44
977 16:31:01.251288 [Byte1]: 44
978 16:31:01.251336
979 16:31:01.251384 Set Vref, RX VrefLevel [Byte0]: 45
980 16:31:01.251432 [Byte1]: 45
981 16:31:01.251480
982 16:31:01.251528 Set Vref, RX VrefLevel [Byte0]: 46
983 16:31:01.251577 [Byte1]: 46
984 16:31:01.251624
985 16:31:01.251672 Set Vref, RX VrefLevel [Byte0]: 47
986 16:31:01.251720 [Byte1]: 47
987 16:31:01.251768
988 16:31:01.251816 Set Vref, RX VrefLevel [Byte0]: 48
989 16:31:01.251864 [Byte1]: 48
990 16:31:01.251911
991 16:31:01.251958 Set Vref, RX VrefLevel [Byte0]: 49
992 16:31:01.252006 [Byte1]: 49
993 16:31:01.252053
994 16:31:01.252100 Set Vref, RX VrefLevel [Byte0]: 50
995 16:31:01.252148 [Byte1]: 50
996 16:31:01.252195
997 16:31:01.252242 Set Vref, RX VrefLevel [Byte0]: 51
998 16:31:01.252290 [Byte1]: 51
999 16:31:01.252337
1000 16:31:01.252384 Set Vref, RX VrefLevel [Byte0]: 52
1001 16:31:01.252432 [Byte1]: 52
1002 16:31:01.252479
1003 16:31:01.252527 Set Vref, RX VrefLevel [Byte0]: 53
1004 16:31:01.252574 [Byte1]: 53
1005 16:31:01.252621
1006 16:31:01.252668 Set Vref, RX VrefLevel [Byte0]: 54
1007 16:31:01.252715 [Byte1]: 54
1008 16:31:01.252763
1009 16:31:01.252812 Set Vref, RX VrefLevel [Byte0]: 55
1010 16:31:01.252860 [Byte1]: 55
1011 16:31:01.252908
1012 16:31:01.252955 Set Vref, RX VrefLevel [Byte0]: 56
1013 16:31:01.253003 [Byte1]: 56
1014 16:31:01.253051
1015 16:31:01.253099 Set Vref, RX VrefLevel [Byte0]: 57
1016 16:31:01.253147 [Byte1]: 57
1017 16:31:01.253195
1018 16:31:01.253242 Set Vref, RX VrefLevel [Byte0]: 58
1019 16:31:01.253290 [Byte1]: 58
1020 16:31:01.253337
1021 16:31:01.253386 Set Vref, RX VrefLevel [Byte0]: 59
1022 16:31:01.253435 [Byte1]: 59
1023 16:31:01.253484
1024 16:31:01.253531 Set Vref, RX VrefLevel [Byte0]: 60
1025 16:31:01.253579 [Byte1]: 60
1026 16:31:01.253627
1027 16:31:01.253674 Set Vref, RX VrefLevel [Byte0]: 61
1028 16:31:01.253722 [Byte1]: 61
1029 16:31:01.253769
1030 16:31:01.253818 Set Vref, RX VrefLevel [Byte0]: 62
1031 16:31:01.253866 [Byte1]: 62
1032 16:31:01.253914
1033 16:31:01.253961 Set Vref, RX VrefLevel [Byte0]: 63
1034 16:31:01.254009 [Byte1]: 63
1035 16:31:01.254057
1036 16:31:01.254104 Set Vref, RX VrefLevel [Byte0]: 64
1037 16:31:01.254152 [Byte1]: 64
1038 16:31:01.254248
1039 16:31:01.254316 Set Vref, RX VrefLevel [Byte0]: 65
1040 16:31:01.254365 [Byte1]: 65
1041 16:31:01.254413
1042 16:31:01.254461 Set Vref, RX VrefLevel [Byte0]: 66
1043 16:31:01.254509 [Byte1]: 66
1044 16:31:01.254557
1045 16:31:01.254604 Set Vref, RX VrefLevel [Byte0]: 67
1046 16:31:01.254652 [Byte1]: 67
1047 16:31:01.254699
1048 16:31:01.254747 Set Vref, RX VrefLevel [Byte0]: 68
1049 16:31:01.254795 [Byte1]: 68
1050 16:31:01.254844
1051 16:31:01.254891 Set Vref, RX VrefLevel [Byte0]: 69
1052 16:31:01.254940 [Byte1]: 69
1053 16:31:01.254987
1054 16:31:01.255035 Set Vref, RX VrefLevel [Byte0]: 70
1055 16:31:01.255083 [Byte1]: 70
1056 16:31:01.255130
1057 16:31:01.255178 Set Vref, RX VrefLevel [Byte0]: 71
1058 16:31:01.255226 [Byte1]: 71
1059 16:31:01.255274
1060 16:31:01.255322 Set Vref, RX VrefLevel [Byte0]: 72
1061 16:31:01.255370 [Byte1]: 72
1062 16:31:01.255418
1063 16:31:01.255466 Set Vref, RX VrefLevel [Byte0]: 73
1064 16:31:01.255514 [Byte1]: 73
1065 16:31:01.255562
1066 16:31:01.255610 Set Vref, RX VrefLevel [Byte0]: 74
1067 16:31:01.255657 [Byte1]: 74
1068 16:31:01.255705
1069 16:31:01.255753 Final RX Vref Byte 0 = 49 to rank0
1070 16:31:01.255801 Final RX Vref Byte 1 = 54 to rank0
1071 16:31:01.255867 Final RX Vref Byte 0 = 49 to rank1
1072 16:31:01.255952 Final RX Vref Byte 1 = 54 to rank1==
1073 16:31:01.256009 Dram Type= 6, Freq= 0, CH_0, rank 0
1074 16:31:01.256058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1075 16:31:01.256107 ==
1076 16:31:01.256156 DQS Delay:
1077 16:31:01.256204 DQS0 = 0, DQS1 = 0
1078 16:31:01.256251 DQM Delay:
1079 16:31:01.256299 DQM0 = 84, DQM1 = 73
1080 16:31:01.256347 DQ Delay:
1081 16:31:01.256395 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1082 16:31:01.256444 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1083 16:31:01.256491 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1084 16:31:01.256539 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1085 16:31:01.256587
1086 16:31:01.256633
1087 16:31:01.256682 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1088 16:31:01.256731 CH0 RK0: MR19=606, MR18=3939
1089 16:31:01.256779 CH0_RK0: MR19=0x606, MR18=0x3939, DQSOSC=395, MR23=63, INC=94, DEC=63
1090 16:31:01.256827
1091 16:31:01.256875 ----->DramcWriteLeveling(PI) begin...
1092 16:31:01.256924 ==
1093 16:31:01.256972 Dram Type= 6, Freq= 0, CH_0, rank 1
1094 16:31:01.257020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1095 16:31:01.257069 ==
1096 16:31:01.257117 Write leveling (Byte 0): 31 => 31
1097 16:31:01.257165 Write leveling (Byte 1): 27 => 27
1098 16:31:01.257213 DramcWriteLeveling(PI) end<-----
1099 16:31:01.257261
1100 16:31:01.257309 ==
1101 16:31:01.257357 Dram Type= 6, Freq= 0, CH_0, rank 1
1102 16:31:01.257405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1103 16:31:01.257453 ==
1104 16:31:01.257500 [Gating] SW mode calibration
1105 16:31:01.257548 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1106 16:31:01.257598 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1107 16:31:01.257647 0 6 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
1108 16:31:01.257695 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
1109 16:31:01.257744 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 16:31:01.257792 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 16:31:01.257841 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 16:31:01.258084 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 16:31:01.258138 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 16:31:01.258188 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 16:31:01.258291 0 7 0 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (1 1)
1116 16:31:01.258384 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1117 16:31:01.258462 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 16:31:01.258554 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 16:31:01.258617 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 16:31:01.258696 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 16:31:01.258746 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 16:31:01.258794 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 16:31:01.258842 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1124 16:31:01.258891 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 16:31:01.258938 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 16:31:01.258986 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 16:31:01.259034 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 16:31:01.259082 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 16:31:01.259130 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 16:31:01.259178 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 16:31:01.259227 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 16:31:01.259275 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 16:31:01.259323 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 16:31:01.259371 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 16:31:01.259419 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 16:31:01.259467 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 16:31:01.259515 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 16:31:01.259563 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 16:31:01.259612 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1140 16:31:01.259660 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1141 16:31:01.259708 Total UI for P1: 0, mck2ui 16
1142 16:31:01.259757 best dqsien dly found for B1: ( 0, 10, 0)
1143 16:31:01.259805 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1144 16:31:01.259853 Total UI for P1: 0, mck2ui 16
1145 16:31:01.259900 best dqsien dly found for B0: ( 0, 10, 2)
1146 16:31:01.259949 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1147 16:31:01.259997 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1148 16:31:01.260045
1149 16:31:01.260093 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1150 16:31:01.260142 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1151 16:31:01.260189 [Gating] SW calibration Done
1152 16:31:01.260237 ==
1153 16:31:01.260285 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 16:31:01.260333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1155 16:31:01.260382 ==
1156 16:31:01.260430 RX Vref Scan: 0
1157 16:31:01.260478
1158 16:31:01.260526 RX Vref 0 -> 0, step: 1
1159 16:31:01.260573
1160 16:31:01.260621 RX Delay -130 -> 252, step: 16
1161 16:31:01.260669 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1162 16:31:01.260717 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1163 16:31:01.260785 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1164 16:31:01.260871 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1165 16:31:01.260919 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1166 16:31:01.260967 iDelay=222, Bit 5, Center 77 (-50 ~ 205) 256
1167 16:31:01.261016 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1168 16:31:01.261064 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1169 16:31:01.261112 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1170 16:31:01.261160 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1171 16:31:01.261208 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1172 16:31:01.261255 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1173 16:31:01.261303 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1174 16:31:01.261350 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1175 16:31:01.261398 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1176 16:31:01.261445 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1177 16:31:01.261494 ==
1178 16:31:01.261543 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 16:31:01.261591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1180 16:31:01.261639 ==
1181 16:31:01.261688 DQS Delay:
1182 16:31:01.261735 DQS0 = 0, DQS1 = 0
1183 16:31:01.261783 DQM Delay:
1184 16:31:01.261830 DQM0 = 81, DQM1 = 73
1185 16:31:01.261878 DQ Delay:
1186 16:31:01.261926 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1187 16:31:01.261975 DQ4 =85, DQ5 =77, DQ6 =85, DQ7 =93
1188 16:31:01.262022 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1189 16:31:01.262070 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1190 16:31:01.262117
1191 16:31:01.262166
1192 16:31:01.262219 ==
1193 16:31:01.262271 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 16:31:01.262319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1195 16:31:01.262368 ==
1196 16:31:01.262415
1197 16:31:01.262463
1198 16:31:01.262510 TX Vref Scan disable
1199 16:31:01.262558 == TX Byte 0 ==
1200 16:31:01.262606 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1201 16:31:01.262654 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1202 16:31:01.262702 == TX Byte 1 ==
1203 16:31:01.262749 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1204 16:31:01.262797 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1205 16:31:01.262845 ==
1206 16:31:01.262893 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 16:31:01.262941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1208 16:31:01.262990 ==
1209 16:31:01.263037 TX Vref=22, minBit 0, minWin=27, winSum=444
1210 16:31:01.263086 TX Vref=24, minBit 10, minWin=27, winSum=449
1211 16:31:01.263135 TX Vref=26, minBit 2, minWin=28, winSum=456
1212 16:31:01.263183 TX Vref=28, minBit 2, minWin=28, winSum=457
1213 16:31:01.263231 TX Vref=30, minBit 2, minWin=28, winSum=457
1214 16:31:01.263279 TX Vref=32, minBit 1, minWin=28, winSum=454
1215 16:31:01.263328 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
1216 16:31:01.263376
1217 16:31:01.263424 Final TX Range 1 Vref 28
1218 16:31:01.263472
1219 16:31:01.263519 ==
1220 16:31:01.263568 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 16:31:01.263616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 16:31:01.263664 ==
1223 16:31:01.263711
1224 16:31:01.263759
1225 16:31:01.263806 TX Vref Scan disable
1226 16:31:01.263855 == TX Byte 0 ==
1227 16:31:01.264099 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1228 16:31:01.264154 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1229 16:31:01.264204 == TX Byte 1 ==
1230 16:31:01.264252 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1231 16:31:01.264301 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1232 16:31:01.264349
1233 16:31:01.264398 [DATLAT]
1234 16:31:01.264447 Freq=800, CH0 RK1
1235 16:31:01.264495
1236 16:31:01.264543 DATLAT Default: 0x9
1237 16:31:01.264592 0, 0xFFFF, sum = 0
1238 16:31:01.264642 1, 0xFFFF, sum = 0
1239 16:31:01.264691 2, 0xFFFF, sum = 0
1240 16:31:01.264768 3, 0xFFFF, sum = 0
1241 16:31:01.264850 4, 0xFFFF, sum = 0
1242 16:31:01.264902 5, 0xFFFF, sum = 0
1243 16:31:01.264951 6, 0xFFFF, sum = 0
1244 16:31:01.265000 7, 0xFFFF, sum = 0
1245 16:31:01.265049 8, 0x0, sum = 1
1246 16:31:01.265098 9, 0x0, sum = 2
1247 16:31:01.265148 10, 0x0, sum = 3
1248 16:31:01.265197 11, 0x0, sum = 4
1249 16:31:01.265246 best_step = 9
1250 16:31:01.265295
1251 16:31:01.265343 ==
1252 16:31:01.265390 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 16:31:01.265439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1254 16:31:01.265487 ==
1255 16:31:01.265535 RX Vref Scan: 0
1256 16:31:01.265583
1257 16:31:01.265631 RX Vref 0 -> 0, step: 1
1258 16:31:01.265679
1259 16:31:01.265727 RX Delay -95 -> 252, step: 8
1260 16:31:01.265776 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1261 16:31:01.265825 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1262 16:31:01.265874 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1263 16:31:01.265922 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1264 16:31:01.265970 iDelay=209, Bit 4, Center 88 (-31 ~ 208) 240
1265 16:31:01.266018 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1266 16:31:01.266067 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1267 16:31:01.266115 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1268 16:31:01.266163 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1269 16:31:01.266222 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1270 16:31:01.266307 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1271 16:31:01.266356 iDelay=209, Bit 11, Center 64 (-47 ~ 176) 224
1272 16:31:01.266404 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1273 16:31:01.266452 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1274 16:31:01.266500 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1275 16:31:01.266549 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1276 16:31:01.266597 ==
1277 16:31:01.266646 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 16:31:01.266710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 16:31:01.266774 ==
1280 16:31:01.266822 DQS Delay:
1281 16:31:01.266869 DQS0 = 0, DQS1 = 0
1282 16:31:01.266917 DQM Delay:
1283 16:31:01.266965 DQM0 = 86, DQM1 = 74
1284 16:31:01.267013 DQ Delay:
1285 16:31:01.267061 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1286 16:31:01.267109 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1287 16:31:01.267158 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1288 16:31:01.267206 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1289 16:31:01.267254
1290 16:31:01.267302
1291 16:31:01.267350 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1292 16:31:01.267399 CH0 RK1: MR19=606, MR18=4343
1293 16:31:01.267448 CH0_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1294 16:31:01.267497 [RxdqsGatingPostProcess] freq 800
1295 16:31:01.267545 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1296 16:31:01.267594 Pre-setting of DQS Precalculation
1297 16:31:01.267641 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1298 16:31:01.267689 ==
1299 16:31:01.267738 Dram Type= 6, Freq= 0, CH_1, rank 0
1300 16:31:01.267786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1301 16:31:01.267833 ==
1302 16:31:01.267914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1303 16:31:01.267963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1304 16:31:01.268011 [CA 0] Center 37 (6~68) winsize 63
1305 16:31:01.268059 [CA 1] Center 37 (6~68) winsize 63
1306 16:31:01.268107 [CA 2] Center 34 (4~65) winsize 62
1307 16:31:01.268154 [CA 3] Center 34 (4~65) winsize 62
1308 16:31:01.268202 [CA 4] Center 33 (3~64) winsize 62
1309 16:31:01.268248 [CA 5] Center 33 (3~64) winsize 62
1310 16:31:01.268296
1311 16:31:01.268343 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1312 16:31:01.268391
1313 16:31:01.268439 [CATrainingPosCal] consider 1 rank data
1314 16:31:01.268487 u2DelayCellTimex100 = 270/100 ps
1315 16:31:01.268535 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1316 16:31:01.268583 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1317 16:31:01.268631 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1318 16:31:01.268679 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 16:31:01.268726 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1320 16:31:01.268808 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 16:31:01.268855
1322 16:31:01.268903 CA PerBit enable=1, Macro0, CA PI delay=33
1323 16:31:01.268951
1324 16:31:01.268998 [CBTSetCACLKResult] CA Dly = 33
1325 16:31:01.269045 CS Dly: 4 (0~35)
1326 16:31:01.269093 ==
1327 16:31:01.269140 Dram Type= 6, Freq= 0, CH_1, rank 1
1328 16:31:01.269188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1329 16:31:01.269235 ==
1330 16:31:01.269282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1331 16:31:01.269330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1332 16:31:01.269380 [CA 0] Center 37 (6~68) winsize 63
1333 16:31:01.269428 [CA 1] Center 37 (6~68) winsize 63
1334 16:31:01.269475 [CA 2] Center 34 (4~65) winsize 62
1335 16:31:01.269523 [CA 3] Center 34 (4~65) winsize 62
1336 16:31:01.269570 [CA 4] Center 33 (3~64) winsize 62
1337 16:31:01.269618 [CA 5] Center 33 (3~64) winsize 62
1338 16:31:01.269665
1339 16:31:01.269712 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1340 16:31:01.269758
1341 16:31:01.269805 [CATrainingPosCal] consider 2 rank data
1342 16:31:01.269853 u2DelayCellTimex100 = 270/100 ps
1343 16:31:01.269900 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1344 16:31:01.269948 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1345 16:31:01.269996 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1346 16:31:01.270043 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 16:31:01.270091 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1348 16:31:01.270139 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 16:31:01.270186
1350 16:31:01.270273 CA PerBit enable=1, Macro0, CA PI delay=33
1351 16:31:01.270321
1352 16:31:01.270369 [CBTSetCACLKResult] CA Dly = 33
1353 16:31:01.270418 CS Dly: 4 (0~36)
1354 16:31:01.270465
1355 16:31:01.270513 ----->DramcWriteLeveling(PI) begin...
1356 16:31:01.270562 ==
1357 16:31:01.270610 Dram Type= 6, Freq= 0, CH_1, rank 0
1358 16:31:01.270659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 16:31:01.270708 ==
1360 16:31:01.270755 Write leveling (Byte 0): 25 => 25
1361 16:31:01.270994 Write leveling (Byte 1): 26 => 26
1362 16:31:01.271093 DramcWriteLeveling(PI) end<-----
1363 16:31:01.271142
1364 16:31:01.271191 ==
1365 16:31:01.271239 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 16:31:01.271288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 16:31:01.271338 ==
1368 16:31:01.271386 [Gating] SW mode calibration
1369 16:31:01.271435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1370 16:31:01.271485 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1371 16:31:01.271534 0 6 0 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 0)
1372 16:31:01.271597 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 16:31:01.271645 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 16:31:01.271694 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 16:31:01.271741 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 16:31:01.271788 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 16:31:01.271836 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 16:31:01.271883 0 6 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1379 16:31:01.271931 0 7 0 | B1->B0 | 2f2f 4141 | 0 0 | (0 0) (0 0)
1380 16:31:01.271979 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 16:31:01.272026 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 16:31:01.272074 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 16:31:01.272122 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 16:31:01.272169 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 16:31:01.272216 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 16:31:01.272263 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1387 16:31:01.272310 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1388 16:31:01.272357 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 16:31:01.272405 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 16:31:01.272452 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 16:31:01.272500 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 16:31:01.272547 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 16:31:01.272595 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 16:31:01.272643 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 16:31:01.272691 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 16:31:01.272738 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 16:31:01.272786 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 16:31:01.272834 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 16:31:01.272882 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 16:31:01.272929 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 16:31:01.272977 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1402 16:31:01.273024 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1403 16:31:01.273071 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1404 16:31:01.273119 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1405 16:31:01.273167 Total UI for P1: 0, mck2ui 16
1406 16:31:01.273215 best dqsien dly found for B0: ( 0, 9, 28)
1407 16:31:01.273264 Total UI for P1: 0, mck2ui 16
1408 16:31:01.273311 best dqsien dly found for B1: ( 0, 10, 0)
1409 16:31:01.273359 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1410 16:31:01.273406 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1411 16:31:01.273454
1412 16:31:01.273500 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1413 16:31:01.273548 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1414 16:31:01.273595 [Gating] SW calibration Done
1415 16:31:01.273643 ==
1416 16:31:01.273691 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 16:31:01.273738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1418 16:31:01.273787 ==
1419 16:31:01.273834 RX Vref Scan: 0
1420 16:31:01.273880
1421 16:31:01.273928 RX Vref 0 -> 0, step: 1
1422 16:31:01.273974
1423 16:31:01.274021 RX Delay -130 -> 252, step: 16
1424 16:31:01.274068 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1425 16:31:01.274116 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1426 16:31:01.274163 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1427 16:31:01.274237 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1428 16:31:01.274306 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1429 16:31:01.274355 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1430 16:31:01.274402 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1431 16:31:01.274450 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1432 16:31:01.274497 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1433 16:31:01.274544 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1434 16:31:01.274591 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1435 16:31:01.274639 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1436 16:31:01.274688 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1437 16:31:01.274735 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1438 16:31:01.274783 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1439 16:31:01.274830 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1440 16:31:01.274877 ==
1441 16:31:01.274925 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 16:31:01.274973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1443 16:31:01.275022 ==
1444 16:31:01.275070 DQS Delay:
1445 16:31:01.275118 DQS0 = 0, DQS1 = 0
1446 16:31:01.275165 DQM Delay:
1447 16:31:01.275212 DQM0 = 84, DQM1 = 74
1448 16:31:01.275259 DQ Delay:
1449 16:31:01.275307 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1450 16:31:01.275355 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1451 16:31:01.275402 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1452 16:31:01.275450 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1453 16:31:01.275496
1454 16:31:01.275543
1455 16:31:01.275590 ==
1456 16:31:01.275637 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 16:31:01.275685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1458 16:31:01.275732 ==
1459 16:31:01.275779
1460 16:31:01.275826
1461 16:31:01.275873 TX Vref Scan disable
1462 16:31:01.275920 == TX Byte 0 ==
1463 16:31:01.275967 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1464 16:31:01.276015 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1465 16:31:01.276062 == TX Byte 1 ==
1466 16:31:01.276110 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1467 16:31:01.276158 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1468 16:31:01.276205 ==
1469 16:31:01.276252 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 16:31:01.276489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1471 16:31:01.276544 ==
1472 16:31:01.276592 TX Vref=22, minBit 3, minWin=27, winSum=447
1473 16:31:01.276641 TX Vref=24, minBit 3, minWin=27, winSum=448
1474 16:31:01.276690 TX Vref=26, minBit 9, minWin=27, winSum=450
1475 16:31:01.276766 TX Vref=28, minBit 0, minWin=28, winSum=457
1476 16:31:01.276860 TX Vref=30, minBit 0, minWin=28, winSum=458
1477 16:31:01.276937 TX Vref=32, minBit 0, minWin=28, winSum=458
1478 16:31:01.277015 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1479 16:31:01.277080
1480 16:31:01.277129 Final TX Range 1 Vref 30
1481 16:31:01.277178
1482 16:31:01.277226 ==
1483 16:31:01.277274 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 16:31:01.277322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 16:31:01.277372 ==
1486 16:31:01.277419
1487 16:31:01.277466
1488 16:31:01.277513 TX Vref Scan disable
1489 16:31:01.277560 == TX Byte 0 ==
1490 16:31:01.277609 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1491 16:31:01.277656 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1492 16:31:01.277704 == TX Byte 1 ==
1493 16:31:01.277752 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1494 16:31:01.277800 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1495 16:31:01.277847
1496 16:31:01.277894 [DATLAT]
1497 16:31:01.277940 Freq=800, CH1 RK0
1498 16:31:01.277988
1499 16:31:01.278036 DATLAT Default: 0xa
1500 16:31:01.278084 0, 0xFFFF, sum = 0
1501 16:31:01.278133 1, 0xFFFF, sum = 0
1502 16:31:01.278181 2, 0xFFFF, sum = 0
1503 16:31:01.278271 3, 0xFFFF, sum = 0
1504 16:31:01.278321 4, 0xFFFF, sum = 0
1505 16:31:01.278370 5, 0xFFFF, sum = 0
1506 16:31:01.278418 6, 0xFFFF, sum = 0
1507 16:31:01.278466 7, 0xFFFF, sum = 0
1508 16:31:01.278514 8, 0x0, sum = 1
1509 16:31:01.278563 9, 0x0, sum = 2
1510 16:31:01.278611 10, 0x0, sum = 3
1511 16:31:01.278660 11, 0x0, sum = 4
1512 16:31:01.278708 best_step = 9
1513 16:31:01.278756
1514 16:31:01.278803 ==
1515 16:31:01.278850 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 16:31:01.278897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1517 16:31:01.278945 ==
1518 16:31:01.278993 RX Vref Scan: 1
1519 16:31:01.279041
1520 16:31:01.279088 Set Vref Range= 32 -> 127
1521 16:31:01.279135
1522 16:31:01.279183 RX Vref 32 -> 127, step: 1
1523 16:31:01.279230
1524 16:31:01.279277 RX Delay -111 -> 252, step: 8
1525 16:31:01.279324
1526 16:31:01.279371 Set Vref, RX VrefLevel [Byte0]: 32
1527 16:31:01.279419 [Byte1]: 32
1528 16:31:01.279467
1529 16:31:01.279514 Set Vref, RX VrefLevel [Byte0]: 33
1530 16:31:01.279563 [Byte1]: 33
1531 16:31:01.279611
1532 16:31:01.279657 Set Vref, RX VrefLevel [Byte0]: 34
1533 16:31:01.279705 [Byte1]: 34
1534 16:31:01.279753
1535 16:31:01.279801 Set Vref, RX VrefLevel [Byte0]: 35
1536 16:31:01.279848 [Byte1]: 35
1537 16:31:01.279895
1538 16:31:01.279942 Set Vref, RX VrefLevel [Byte0]: 36
1539 16:31:01.279990 [Byte1]: 36
1540 16:31:01.280037
1541 16:31:01.280085 Set Vref, RX VrefLevel [Byte0]: 37
1542 16:31:01.280133 [Byte1]: 37
1543 16:31:01.280181
1544 16:31:01.280228 Set Vref, RX VrefLevel [Byte0]: 38
1545 16:31:01.280276 [Byte1]: 38
1546 16:31:01.280323
1547 16:31:01.280369 Set Vref, RX VrefLevel [Byte0]: 39
1548 16:31:01.280417 [Byte1]: 39
1549 16:31:01.280464
1550 16:31:01.280511 Set Vref, RX VrefLevel [Byte0]: 40
1551 16:31:01.280559 [Byte1]: 40
1552 16:31:01.280607
1553 16:31:01.280654 Set Vref, RX VrefLevel [Byte0]: 41
1554 16:31:01.280702 [Byte1]: 41
1555 16:31:01.280750
1556 16:31:01.280796 Set Vref, RX VrefLevel [Byte0]: 42
1557 16:31:01.280842 [Byte1]: 42
1558 16:31:01.280889
1559 16:31:01.280936 Set Vref, RX VrefLevel [Byte0]: 43
1560 16:31:01.280984 [Byte1]: 43
1561 16:31:01.281032
1562 16:31:01.281079 Set Vref, RX VrefLevel [Byte0]: 44
1563 16:31:01.281127 [Byte1]: 44
1564 16:31:01.281174
1565 16:31:01.281222 Set Vref, RX VrefLevel [Byte0]: 45
1566 16:31:01.281270 [Byte1]: 45
1567 16:31:01.281317
1568 16:31:01.281363 Set Vref, RX VrefLevel [Byte0]: 46
1569 16:31:01.281411 [Byte1]: 46
1570 16:31:01.281458
1571 16:31:01.281506 Set Vref, RX VrefLevel [Byte0]: 47
1572 16:31:01.281554 [Byte1]: 47
1573 16:31:01.281602
1574 16:31:01.281649 Set Vref, RX VrefLevel [Byte0]: 48
1575 16:31:01.281697 [Byte1]: 48
1576 16:31:01.281744
1577 16:31:01.281791 Set Vref, RX VrefLevel [Byte0]: 49
1578 16:31:01.281838 [Byte1]: 49
1579 16:31:01.281885
1580 16:31:01.281932 Set Vref, RX VrefLevel [Byte0]: 50
1581 16:31:01.281979 [Byte1]: 50
1582 16:31:01.282026
1583 16:31:01.282074 Set Vref, RX VrefLevel [Byte0]: 51
1584 16:31:01.282121 [Byte1]: 51
1585 16:31:01.282169
1586 16:31:01.282224 Set Vref, RX VrefLevel [Byte0]: 52
1587 16:31:01.282309 [Byte1]: 52
1588 16:31:01.282357
1589 16:31:01.282404 Set Vref, RX VrefLevel [Byte0]: 53
1590 16:31:01.282451 [Byte1]: 53
1591 16:31:01.282499
1592 16:31:01.282547 Set Vref, RX VrefLevel [Byte0]: 54
1593 16:31:01.282595 [Byte1]: 54
1594 16:31:01.282643
1595 16:31:01.282690 Set Vref, RX VrefLevel [Byte0]: 55
1596 16:31:01.282737 [Byte1]: 55
1597 16:31:01.282817
1598 16:31:01.282865 Set Vref, RX VrefLevel [Byte0]: 56
1599 16:31:01.282912 [Byte1]: 56
1600 16:31:01.282959
1601 16:31:01.283006 Set Vref, RX VrefLevel [Byte0]: 57
1602 16:31:01.283054 [Byte1]: 57
1603 16:31:01.283101
1604 16:31:01.283149 Set Vref, RX VrefLevel [Byte0]: 58
1605 16:31:01.283197 [Byte1]: 58
1606 16:31:01.283244
1607 16:31:01.283290 Set Vref, RX VrefLevel [Byte0]: 59
1608 16:31:01.283338 [Byte1]: 59
1609 16:31:01.283385
1610 16:31:01.283431 Set Vref, RX VrefLevel [Byte0]: 60
1611 16:31:01.283478 [Byte1]: 60
1612 16:31:01.283526
1613 16:31:01.283573 Set Vref, RX VrefLevel [Byte0]: 61
1614 16:31:01.283622 [Byte1]: 61
1615 16:31:01.283669
1616 16:31:01.283717 Set Vref, RX VrefLevel [Byte0]: 62
1617 16:31:01.283766 [Byte1]: 62
1618 16:31:01.283815
1619 16:31:01.283862 Set Vref, RX VrefLevel [Byte0]: 63
1620 16:31:01.283909 [Byte1]: 63
1621 16:31:01.283956
1622 16:31:01.284003 Set Vref, RX VrefLevel [Byte0]: 64
1623 16:31:01.284050 [Byte1]: 64
1624 16:31:01.284097
1625 16:31:01.284144 Set Vref, RX VrefLevel [Byte0]: 65
1626 16:31:01.284192 [Byte1]: 65
1627 16:31:01.284239
1628 16:31:01.284285 Set Vref, RX VrefLevel [Byte0]: 66
1629 16:31:01.284333 [Byte1]: 66
1630 16:31:01.284380
1631 16:31:01.284427 Set Vref, RX VrefLevel [Byte0]: 67
1632 16:31:01.284474 [Byte1]: 67
1633 16:31:01.284521
1634 16:31:01.284568 Set Vref, RX VrefLevel [Byte0]: 68
1635 16:31:01.284617 [Byte1]: 68
1636 16:31:01.284664
1637 16:31:01.284711 Set Vref, RX VrefLevel [Byte0]: 69
1638 16:31:01.284952 [Byte1]: 69
1639 16:31:01.285040
1640 16:31:01.285088 Set Vref, RX VrefLevel [Byte0]: 70
1641 16:31:01.285135 [Byte1]: 70
1642 16:31:01.285183
1643 16:31:01.285231 Set Vref, RX VrefLevel [Byte0]: 71
1644 16:31:01.285278 [Byte1]: 71
1645 16:31:01.285325
1646 16:31:01.285373 Set Vref, RX VrefLevel [Byte0]: 72
1647 16:31:01.285421 [Byte1]: 72
1648 16:31:01.285468
1649 16:31:01.285515 Set Vref, RX VrefLevel [Byte0]: 73
1650 16:31:01.285564 [Byte1]: 73
1651 16:31:01.285611
1652 16:31:01.285658 Set Vref, RX VrefLevel [Byte0]: 74
1653 16:31:01.285706 [Byte1]: 74
1654 16:31:01.285753
1655 16:31:01.285801 Final RX Vref Byte 0 = 60 to rank0
1656 16:31:01.285849 Final RX Vref Byte 1 = 54 to rank0
1657 16:31:01.285897 Final RX Vref Byte 0 = 60 to rank1
1658 16:31:01.285945 Final RX Vref Byte 1 = 54 to rank1==
1659 16:31:01.285993 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 16:31:01.286040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1661 16:31:01.286087 ==
1662 16:31:01.286134 DQS Delay:
1663 16:31:01.286181 DQS0 = 0, DQS1 = 0
1664 16:31:01.286242 DQM Delay:
1665 16:31:01.286292 DQM0 = 81, DQM1 = 75
1666 16:31:01.286340 DQ Delay:
1667 16:31:01.286388 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1668 16:31:01.286435 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1669 16:31:01.286483 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1670 16:31:01.286531 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1671 16:31:01.286578
1672 16:31:01.286624
1673 16:31:01.286672 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1674 16:31:01.286721 CH1 RK0: MR19=606, MR18=4D4D
1675 16:31:01.286783 CH1_RK0: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1676 16:31:01.286840
1677 16:31:01.286924 ----->DramcWriteLeveling(PI) begin...
1678 16:31:01.286980 ==
1679 16:31:01.287029 Dram Type= 6, Freq= 0, CH_1, rank 1
1680 16:31:01.287078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1681 16:31:01.287127 ==
1682 16:31:01.287175 Write leveling (Byte 0): 24 => 24
1683 16:31:01.287224 Write leveling (Byte 1): 24 => 24
1684 16:31:01.287271 DramcWriteLeveling(PI) end<-----
1685 16:31:01.287319
1686 16:31:01.287366 ==
1687 16:31:01.287414 Dram Type= 6, Freq= 0, CH_1, rank 1
1688 16:31:01.287461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1689 16:31:01.287509 ==
1690 16:31:01.287557 [Gating] SW mode calibration
1691 16:31:01.287605 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1692 16:31:01.287653 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1693 16:31:01.287701 0 6 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
1694 16:31:01.287749 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1695 16:31:01.287797 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 16:31:01.287845 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 16:31:01.287893 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 16:31:01.287941 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 16:31:01.287988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 16:31:01.288036 0 6 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
1701 16:31:01.288084 0 7 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
1702 16:31:01.288132 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 16:31:01.288180 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 16:31:01.288228 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 16:31:01.288275 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 16:31:01.288322 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 16:31:01.288370 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 16:31:01.288417 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 16:31:01.288465 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 16:31:01.288513 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 16:31:01.288561 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 16:31:01.288608 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 16:31:01.288656 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 16:31:01.288703 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 16:31:01.288750 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 16:31:01.288798 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 16:31:01.288846 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 16:31:01.288894 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 16:31:01.288942 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 16:31:01.288989 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 16:31:01.289036 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 16:31:01.289083 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 16:31:01.289131 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1724 16:31:01.289178 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1725 16:31:01.289226 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1726 16:31:01.289273 Total UI for P1: 0, mck2ui 16
1727 16:31:01.289321 best dqsien dly found for B0: ( 0, 9, 26)
1728 16:31:01.289369 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 16:31:01.289417 Total UI for P1: 0, mck2ui 16
1730 16:31:01.289465 best dqsien dly found for B1: ( 0, 9, 30)
1731 16:31:01.289514 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1732 16:31:01.289561 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1733 16:31:01.289608
1734 16:31:01.289655 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1735 16:31:01.289703 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1736 16:31:01.289751 [Gating] SW calibration Done
1737 16:31:01.289799 ==
1738 16:31:01.289847 Dram Type= 6, Freq= 0, CH_1, rank 1
1739 16:31:01.289895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1740 16:31:01.289943 ==
1741 16:31:01.289991 RX Vref Scan: 0
1742 16:31:01.290037
1743 16:31:01.290084 RX Vref 0 -> 0, step: 1
1744 16:31:01.290131
1745 16:31:01.290178 RX Delay -130 -> 252, step: 16
1746 16:31:01.290250 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1747 16:31:01.290313 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1748 16:31:01.290361 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1749 16:31:01.290409 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1750 16:31:01.290456 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1751 16:31:01.290694 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1752 16:31:01.290748 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1753 16:31:01.290796 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1754 16:31:01.290844 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1755 16:31:01.290892 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1756 16:31:01.290939 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1757 16:31:01.290986 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1758 16:31:01.291034 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1759 16:31:01.291082 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1760 16:31:01.291129 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1761 16:31:01.291176 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1762 16:31:01.291223 ==
1763 16:31:01.291271 Dram Type= 6, Freq= 0, CH_1, rank 1
1764 16:31:01.291382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1765 16:31:01.291457 ==
1766 16:31:01.291506 DQS Delay:
1767 16:31:01.291554 DQS0 = 0, DQS1 = 0
1768 16:31:01.291601 DQM Delay:
1769 16:31:01.291649 DQM0 = 86, DQM1 = 73
1770 16:31:01.291697 DQ Delay:
1771 16:31:01.291744 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1772 16:31:01.291792 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1773 16:31:01.291839 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1774 16:31:01.291886 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1775 16:31:01.291934
1776 16:31:01.291981
1777 16:31:01.292028 ==
1778 16:31:01.292076 Dram Type= 6, Freq= 0, CH_1, rank 1
1779 16:31:01.292124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1780 16:31:01.292172 ==
1781 16:31:01.292219
1782 16:31:01.292266
1783 16:31:01.292313 TX Vref Scan disable
1784 16:31:01.292361 == TX Byte 0 ==
1785 16:31:01.292409 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1786 16:31:01.292456 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1787 16:31:01.292505 == TX Byte 1 ==
1788 16:31:01.292552 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1789 16:31:01.292600 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1790 16:31:01.292649 ==
1791 16:31:01.292697 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 16:31:01.292744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 16:31:01.292793 ==
1794 16:31:01.292841 TX Vref=22, minBit 8, minWin=27, winSum=449
1795 16:31:01.292889 TX Vref=24, minBit 0, minWin=28, winSum=452
1796 16:31:01.292937 TX Vref=26, minBit 5, minWin=28, winSum=458
1797 16:31:01.292985 TX Vref=28, minBit 9, minWin=28, winSum=460
1798 16:31:01.293032 TX Vref=30, minBit 0, minWin=28, winSum=460
1799 16:31:01.293080 TX Vref=32, minBit 0, minWin=28, winSum=455
1800 16:31:01.293127 [TxChooseVref] Worse bit 9, Min win 28, Win sum 460, Final Vref 28
1801 16:31:01.293175
1802 16:31:01.293223 Final TX Range 1 Vref 28
1803 16:31:01.293271
1804 16:31:01.293317 ==
1805 16:31:01.293365 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 16:31:01.293412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 16:31:01.293461 ==
1808 16:31:01.293508
1809 16:31:01.293564
1810 16:31:01.293614 TX Vref Scan disable
1811 16:31:01.293662 == TX Byte 0 ==
1812 16:31:01.293710 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1813 16:31:01.293758 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1814 16:31:01.293807 == TX Byte 1 ==
1815 16:31:01.293855 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1816 16:31:01.293903 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1817 16:31:01.293951
1818 16:31:01.293998 [DATLAT]
1819 16:31:01.294046 Freq=800, CH1 RK1
1820 16:31:01.294094
1821 16:31:01.294141 DATLAT Default: 0x9
1822 16:31:01.294188 0, 0xFFFF, sum = 0
1823 16:31:01.294282 1, 0xFFFF, sum = 0
1824 16:31:01.294332 2, 0xFFFF, sum = 0
1825 16:31:01.294381 3, 0xFFFF, sum = 0
1826 16:31:01.294430 4, 0xFFFF, sum = 0
1827 16:31:01.294478 5, 0xFFFF, sum = 0
1828 16:31:01.294526 6, 0xFFFF, sum = 0
1829 16:31:01.294574 7, 0xFFFF, sum = 0
1830 16:31:01.294622 8, 0x0, sum = 1
1831 16:31:01.294671 9, 0x0, sum = 2
1832 16:31:01.294719 10, 0x0, sum = 3
1833 16:31:01.294768 11, 0x0, sum = 4
1834 16:31:01.294816 best_step = 9
1835 16:31:01.294864
1836 16:31:01.294911 ==
1837 16:31:01.294958 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 16:31:01.295006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1839 16:31:01.295053 ==
1840 16:31:01.295100 RX Vref Scan: 0
1841 16:31:01.295148
1842 16:31:01.295196 RX Vref 0 -> 0, step: 1
1843 16:31:01.295243
1844 16:31:01.295290 RX Delay -111 -> 252, step: 8
1845 16:31:01.295338 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1846 16:31:01.295386 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1847 16:31:01.295433 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1848 16:31:01.295480 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1849 16:31:01.295528 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1850 16:31:01.295576 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1851 16:31:01.295623 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1852 16:31:01.295671 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1853 16:31:01.295720 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1854 16:31:01.295768 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1855 16:31:01.295816 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1856 16:31:01.295863 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1857 16:31:01.295911 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1858 16:31:01.295959 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1859 16:31:01.296006 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1860 16:31:01.296053 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1861 16:31:01.296100 ==
1862 16:31:01.296148 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 16:31:01.296196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1864 16:31:01.296244 ==
1865 16:31:01.296291 DQS Delay:
1866 16:31:01.296339 DQS0 = 0, DQS1 = 0
1867 16:31:01.296387 DQM Delay:
1868 16:31:01.296434 DQM0 = 83, DQM1 = 73
1869 16:31:01.296481 DQ Delay:
1870 16:31:01.296529 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1871 16:31:01.296577 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1872 16:31:01.296625 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1873 16:31:01.296673 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1874 16:31:01.296720
1875 16:31:01.296767
1876 16:31:01.296814 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1877 16:31:01.296863 CH1 RK1: MR19=606, MR18=4141
1878 16:31:01.296911 CH1_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1879 16:31:01.296959 [RxdqsGatingPostProcess] freq 800
1880 16:31:01.297007 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1881 16:31:01.297055 Pre-setting of DQS Precalculation
1882 16:31:01.297103 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1883 16:31:01.297151 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1884 16:31:01.297199 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1885 16:31:01.297247
1886 16:31:01.297294
1887 16:31:01.297531 [Calibration Summary] 1600 Mbps
1888 16:31:01.297585 CH 0, Rank 0
1889 16:31:01.297634 SW Impedance : PASS
1890 16:31:01.297682 DUTY Scan : NO K
1891 16:31:01.297730 ZQ Calibration : PASS
1892 16:31:01.297797 Jitter Meter : NO K
1893 16:31:01.297859 CBT Training : PASS
1894 16:31:01.297907 Write leveling : PASS
1895 16:31:01.297954 RX DQS gating : PASS
1896 16:31:01.298002 RX DQ/DQS(RDDQC) : PASS
1897 16:31:01.298049 TX DQ/DQS : PASS
1898 16:31:01.298097 RX DATLAT : PASS
1899 16:31:01.298145 RX DQ/DQS(Engine): PASS
1900 16:31:01.298192 TX OE : NO K
1901 16:31:01.298277 All Pass.
1902 16:31:01.298325
1903 16:31:01.298372 CH 0, Rank 1
1904 16:31:01.298419 SW Impedance : PASS
1905 16:31:01.298467 DUTY Scan : NO K
1906 16:31:01.298514 ZQ Calibration : PASS
1907 16:31:01.298561 Jitter Meter : NO K
1908 16:31:01.298608 CBT Training : PASS
1909 16:31:01.298655 Write leveling : PASS
1910 16:31:01.298703 RX DQS gating : PASS
1911 16:31:01.298750 RX DQ/DQS(RDDQC) : PASS
1912 16:31:01.298797 TX DQ/DQS : PASS
1913 16:31:01.298845 RX DATLAT : PASS
1914 16:31:01.298892 RX DQ/DQS(Engine): PASS
1915 16:31:01.298939 TX OE : NO K
1916 16:31:01.298987 All Pass.
1917 16:31:01.299033
1918 16:31:01.299079 CH 1, Rank 0
1919 16:31:01.299126 SW Impedance : PASS
1920 16:31:01.299174 DUTY Scan : NO K
1921 16:31:01.299222 ZQ Calibration : PASS
1922 16:31:01.299270 Jitter Meter : NO K
1923 16:31:01.299318 CBT Training : PASS
1924 16:31:01.299365 Write leveling : PASS
1925 16:31:01.299412 RX DQS gating : PASS
1926 16:31:01.299459 RX DQ/DQS(RDDQC) : PASS
1927 16:31:01.299507 TX DQ/DQS : PASS
1928 16:31:01.299554 RX DATLAT : PASS
1929 16:31:01.299601 RX DQ/DQS(Engine): PASS
1930 16:31:01.299648 TX OE : NO K
1931 16:31:01.299694 All Pass.
1932 16:31:01.299741
1933 16:31:01.299788 CH 1, Rank 1
1934 16:31:01.299836 SW Impedance : PASS
1935 16:31:01.465639 DUTY Scan : NO K
1936 16:31:01.465759 ZQ Calibration : PASS
1937 16:31:01.465821 Jitter Meter : NO K
1938 16:31:01.465876 CBT Training : PASS
1939 16:31:01.465929 Write leveling : PASS
1940 16:31:01.466006 RX DQS gating : PASS
1941 16:31:01.466083 RX DQ/DQS(RDDQC) : PASS
1942 16:31:01.466156 TX DQ/DQS : PASS
1943 16:31:01.466268 RX DATLAT : PASS
1944 16:31:01.466320 RX DQ/DQS(Engine): PASS
1945 16:31:01.466368 TX OE : NO K
1946 16:31:01.466423 All Pass.
1947 16:31:01.466473
1948 16:31:01.466522 DramC Write-DBI off
1949 16:31:01.466571 PER_BANK_REFRESH: Hybrid Mode
1950 16:31:01.466620 TX_TRACKING: ON
1951 16:31:01.466668 [GetDramInforAfterCalByMRR] Vendor 6.
1952 16:31:01.466718 [GetDramInforAfterCalByMRR] Revision 606.
1953 16:31:01.466766 [GetDramInforAfterCalByMRR] Revision 2 0.
1954 16:31:01.466822 MR0 0x3939
1955 16:31:01.466871 MR8 0x1111
1956 16:31:01.466919 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1957 16:31:01.466967
1958 16:31:01.467015 MR0 0x3939
1959 16:31:01.467063 MR8 0x1111
1960 16:31:01.467111 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1961 16:31:01.467159
1962 16:31:01.467207 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1963 16:31:01.467260 [FAST_K] Save calibration result to emmc
1964 16:31:01.467311 [FAST_K] Save calibration result to emmc
1965 16:31:01.467358 dram_init: config_dvfs: 1
1966 16:31:01.467406 dramc_set_vcore_voltage set vcore to 662500
1967 16:31:01.467454 Read voltage for 1200, 2
1968 16:31:01.467501 Vio18 = 0
1969 16:31:01.467549 Vcore = 662500
1970 16:31:01.467596 Vdram = 0
1971 16:31:01.467645 Vddq = 0
1972 16:31:01.467726 Vmddr = 0
1973 16:31:01.467797 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1974 16:31:01.467869 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1975 16:31:01.467926 MEM_TYPE=3, freq_sel=15
1976 16:31:01.467974 sv_algorithm_assistance_LP4_1600
1977 16:31:01.468023 ============ PULL DRAM RESETB DOWN ============
1978 16:31:01.468078 ========== PULL DRAM RESETB DOWN end =========
1979 16:31:01.468126 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1980 16:31:01.468175 ===================================
1981 16:31:01.468223 LPDDR4 DRAM CONFIGURATION
1982 16:31:01.468271 ===================================
1983 16:31:01.468319 EX_ROW_EN[0] = 0x0
1984 16:31:01.468366 EX_ROW_EN[1] = 0x0
1985 16:31:01.468414 LP4Y_EN = 0x0
1986 16:31:01.468491 WORK_FSP = 0x0
1987 16:31:01.468566 WL = 0x4
1988 16:31:01.468642 RL = 0x4
1989 16:31:01.468717 BL = 0x2
1990 16:31:01.468792 RPST = 0x0
1991 16:31:01.468871 RD_PRE = 0x0
1992 16:31:01.468947 WR_PRE = 0x1
1993 16:31:01.469026 WR_PST = 0x0
1994 16:31:01.469101 DBI_WR = 0x0
1995 16:31:01.469176 DBI_RD = 0x0
1996 16:31:01.469259 OTF = 0x1
1997 16:31:01.469337 ===================================
1998 16:31:01.469408 ===================================
1999 16:31:01.469477 ANA top config
2000 16:31:01.469526 ===================================
2001 16:31:01.469573 DLL_ASYNC_EN = 0
2002 16:31:01.469625 ALL_SLAVE_EN = 0
2003 16:31:01.469674 NEW_RANK_MODE = 1
2004 16:31:01.469723 DLL_IDLE_MODE = 1
2005 16:31:01.469771 LP45_APHY_COMB_EN = 1
2006 16:31:01.469818 TX_ODT_DIS = 1
2007 16:31:01.469865 NEW_8X_MODE = 1
2008 16:31:01.469913 ===================================
2009 16:31:01.469961 ===================================
2010 16:31:01.470017 data_rate = 2400
2011 16:31:01.470093 CKR = 1
2012 16:31:01.470168 DQ_P2S_RATIO = 8
2013 16:31:01.470264 ===================================
2014 16:31:01.470329 CA_P2S_RATIO = 8
2015 16:31:01.470378 DQ_CA_OPEN = 0
2016 16:31:01.470425 DQ_SEMI_OPEN = 0
2017 16:31:01.470480 CA_SEMI_OPEN = 0
2018 16:31:01.470528 CA_FULL_RATE = 0
2019 16:31:01.470576 DQ_CKDIV4_EN = 0
2020 16:31:01.470623 CA_CKDIV4_EN = 0
2021 16:31:01.470672 CA_PREDIV_EN = 0
2022 16:31:01.470719 PH8_DLY = 17
2023 16:31:01.470806 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2024 16:31:01.470854 DQ_AAMCK_DIV = 4
2025 16:31:01.470936 CA_AAMCK_DIV = 4
2026 16:31:01.471012 CA_ADMCK_DIV = 4
2027 16:31:01.471083 DQ_TRACK_CA_EN = 0
2028 16:31:01.471149 CA_PICK = 1200
2029 16:31:01.471198 CA_MCKIO = 1200
2030 16:31:01.471247 MCKIO_SEMI = 0
2031 16:31:01.471336 PLL_FREQ = 2366
2032 16:31:01.471385 DQ_UI_PI_RATIO = 32
2033 16:31:01.471433 CA_UI_PI_RATIO = 0
2034 16:31:01.471481 ===================================
2035 16:31:01.471546 ===================================
2036 16:31:01.471610 memory_type:LPDDR4
2037 16:31:01.471659 GP_NUM : 10
2038 16:31:01.471707 SRAM_EN : 1
2039 16:31:01.471763 MD32_EN : 0
2040 16:31:01.472029 ===================================
2041 16:31:01.472116 [ANA_INIT] >>>>>>>>>>>>>>
2042 16:31:01.472180 <<<<<< [CONFIGURE PHASE]: ANA_TX
2043 16:31:01.472236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2044 16:31:01.472286 ===================================
2045 16:31:01.472337 data_rate = 2400,PCW = 0X5b00
2046 16:31:01.472386 ===================================
2047 16:31:01.472435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2048 16:31:01.472484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2049 16:31:01.472548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2050 16:31:01.472612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2051 16:31:01.472696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2052 16:31:01.472768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2053 16:31:01.472840 [ANA_INIT] flow start
2054 16:31:01.472919 [ANA_INIT] PLL >>>>>>>>
2055 16:31:01.473003 [ANA_INIT] PLL <<<<<<<<
2056 16:31:01.473098 [ANA_INIT] MIDPI >>>>>>>>
2057 16:31:01.473203 [ANA_INIT] MIDPI <<<<<<<<
2058 16:31:01.473280 [ANA_INIT] DLL >>>>>>>>
2059 16:31:01.473357 [ANA_INIT] DLL <<<<<<<<
2060 16:31:01.473433 [ANA_INIT] flow end
2061 16:31:01.473509 ============ LP4 DIFF to SE enter ============
2062 16:31:01.473635 ============ LP4 DIFF to SE exit ============
2063 16:31:01.473726 [ANA_INIT] <<<<<<<<<<<<<
2064 16:31:01.473802 [Flow] Enable top DCM control >>>>>
2065 16:31:01.473879 [Flow] Enable top DCM control <<<<<
2066 16:31:01.473955 Enable DLL master slave shuffle
2067 16:31:01.474032 ==============================================================
2068 16:31:01.474128 Gating Mode config
2069 16:31:01.474206 ==============================================================
2070 16:31:01.474284 Config description:
2071 16:31:01.474333 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2072 16:31:01.474383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2073 16:31:01.474433 SELPH_MODE 0: By rank 1: By Phase
2074 16:31:01.474482 ==============================================================
2075 16:31:01.474548 GAT_TRACK_EN = 1
2076 16:31:01.474597 RX_GATING_MODE = 2
2077 16:31:01.474647 RX_GATING_TRACK_MODE = 2
2078 16:31:01.474696 SELPH_MODE = 1
2079 16:31:01.474760 PICG_EARLY_EN = 1
2080 16:31:01.474808 VALID_LAT_VALUE = 1
2081 16:31:01.474856 ==============================================================
2082 16:31:01.474905 Enter into Gating configuration >>>>
2083 16:31:01.474984 Exit from Gating configuration <<<<
2084 16:31:01.475032 Enter into DVFS_PRE_config >>>>>
2085 16:31:01.475081 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2086 16:31:01.475130 Exit from DVFS_PRE_config <<<<<
2087 16:31:01.475180 Enter into PICG configuration >>>>
2088 16:31:01.475228 Exit from PICG configuration <<<<
2089 16:31:01.475275 [RX_INPUT] configuration >>>>>
2090 16:31:01.475339 [RX_INPUT] configuration <<<<<
2091 16:31:01.475420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2092 16:31:01.475499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2093 16:31:01.475563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2094 16:31:01.475612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2095 16:31:01.475661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2096 16:31:01.475710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2097 16:31:01.475759 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2098 16:31:01.475806 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2099 16:31:01.475872 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2100 16:31:01.475936 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2101 16:31:01.475985 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2102 16:31:01.476033 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2103 16:31:01.476082 ===================================
2104 16:31:01.476130 LPDDR4 DRAM CONFIGURATION
2105 16:31:01.476178 ===================================
2106 16:31:01.476226 EX_ROW_EN[0] = 0x0
2107 16:31:01.476292 EX_ROW_EN[1] = 0x0
2108 16:31:01.476340 LP4Y_EN = 0x0
2109 16:31:01.476389 WORK_FSP = 0x0
2110 16:31:01.476439 WL = 0x4
2111 16:31:01.476502 RL = 0x4
2112 16:31:01.476550 BL = 0x2
2113 16:31:01.476597 RPST = 0x0
2114 16:31:01.476645 RD_PRE = 0x0
2115 16:31:01.476693 WR_PRE = 0x1
2116 16:31:01.476788 WR_PST = 0x0
2117 16:31:01.476869 DBI_WR = 0x0
2118 16:31:01.476948 DBI_RD = 0x0
2119 16:31:01.477012 OTF = 0x1
2120 16:31:01.477077 ===================================
2121 16:31:01.477227 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2122 16:31:01.477317 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2123 16:31:01.477418 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 16:31:01.477515 ===================================
2125 16:31:01.477644 LPDDR4 DRAM CONFIGURATION
2126 16:31:01.477771 ===================================
2127 16:31:01.477896 EX_ROW_EN[0] = 0x10
2128 16:31:01.478017 EX_ROW_EN[1] = 0x0
2129 16:31:01.478114 LP4Y_EN = 0x0
2130 16:31:01.478216 WORK_FSP = 0x0
2131 16:31:01.478316 WL = 0x4
2132 16:31:01.478404 RL = 0x4
2133 16:31:01.478482 BL = 0x2
2134 16:31:01.478560 RPST = 0x0
2135 16:31:01.478637 RD_PRE = 0x0
2136 16:31:01.478715 WR_PRE = 0x1
2137 16:31:01.478792 WR_PST = 0x0
2138 16:31:01.478873 DBI_WR = 0x0
2139 16:31:01.478950 DBI_RD = 0x0
2140 16:31:01.479007 OTF = 0x1
2141 16:31:01.479057 ===================================
2142 16:31:01.479107 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2143 16:31:01.479157 ==
2144 16:31:01.479207 Dram Type= 6, Freq= 0, CH_0, rank 0
2145 16:31:01.479256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2146 16:31:01.479306 ==
2147 16:31:01.479355 [Duty_Offset_Calibration]
2148 16:31:01.479405 B0:0 B1:2 CA:1
2149 16:31:01.479454
2150 16:31:01.479699 [DutyScan_Calibration_Flow] k_type=0
2151 16:31:01.479794
2152 16:31:01.479891 ==CLK 0==
2153 16:31:01.479989 Final CLK duty delay cell = 0
2154 16:31:01.480089 [0] MAX Duty = 5093%(X100), DQS PI = 12
2155 16:31:01.480187 [0] MIN Duty = 4938%(X100), DQS PI = 54
2156 16:31:01.480284 [0] AVG Duty = 5015%(X100)
2157 16:31:01.480412
2158 16:31:01.480509 CH0 CLK Duty spec in!! Max-Min= 155%
2159 16:31:01.480607 [DutyScan_Calibration_Flow] ====Done====
2160 16:31:01.480693
2161 16:31:01.480777 [DutyScan_Calibration_Flow] k_type=1
2162 16:31:01.480854
2163 16:31:01.480931 ==DQS 0 ==
2164 16:31:01.481009 Final DQS duty delay cell = 0
2165 16:31:01.481089 [0] MAX Duty = 5125%(X100), DQS PI = 30
2166 16:31:01.481142 [0] MIN Duty = 5031%(X100), DQS PI = 4
2167 16:31:01.481192 [0] AVG Duty = 5078%(X100)
2168 16:31:01.481242
2169 16:31:01.481291 ==DQS 1 ==
2170 16:31:01.481340 Final DQS duty delay cell = 0
2171 16:31:01.481390 [0] MAX Duty = 5031%(X100), DQS PI = 54
2172 16:31:01.481439 [0] MIN Duty = 4875%(X100), DQS PI = 22
2173 16:31:01.481487 [0] AVG Duty = 4953%(X100)
2174 16:31:01.481535
2175 16:31:01.481584 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2176 16:31:01.481632
2177 16:31:01.481687 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2178 16:31:01.481777 [DutyScan_Calibration_Flow] ====Done====
2179 16:31:01.481874
2180 16:31:01.481999 [DutyScan_Calibration_Flow] k_type=3
2181 16:31:01.482126
2182 16:31:01.482229 ==DQM 0 ==
2183 16:31:01.482383 Final DQM duty delay cell = 0
2184 16:31:01.482463 [0] MAX Duty = 5156%(X100), DQS PI = 20
2185 16:31:01.482543 [0] MIN Duty = 4969%(X100), DQS PI = 40
2186 16:31:01.482622 [0] AVG Duty = 5062%(X100)
2187 16:31:01.482699
2188 16:31:01.482809 ==DQM 1 ==
2189 16:31:01.482917 Final DQM duty delay cell = 4
2190 16:31:01.483009 [4] MAX Duty = 5187%(X100), DQS PI = 54
2191 16:31:01.483103 [4] MIN Duty = 5000%(X100), DQS PI = 18
2192 16:31:01.483181 [4] AVG Duty = 5093%(X100)
2193 16:31:01.483259
2194 16:31:01.483336 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2195 16:31:01.483414
2196 16:31:01.483491 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2197 16:31:01.483570 [DutyScan_Calibration_Flow] ====Done====
2198 16:31:01.483647
2199 16:31:01.483725 [DutyScan_Calibration_Flow] k_type=2
2200 16:31:01.483802
2201 16:31:01.483879 ==DQ 0 ==
2202 16:31:01.483957 Final DQ duty delay cell = -4
2203 16:31:01.484036 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2204 16:31:01.484114 [-4] MIN Duty = 4813%(X100), DQS PI = 6
2205 16:31:01.484192 [-4] AVG Duty = 4937%(X100)
2206 16:31:01.484270
2207 16:31:01.484346 ==DQ 1 ==
2208 16:31:01.484424 Final DQ duty delay cell = -4
2209 16:31:01.484503 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2210 16:31:01.484580 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2211 16:31:01.484658 [-4] AVG Duty = 4969%(X100)
2212 16:31:01.484735
2213 16:31:01.484813 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2214 16:31:01.484890
2215 16:31:01.484968 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2216 16:31:01.485046 [DutyScan_Calibration_Flow] ====Done====
2217 16:31:01.485123 ==
2218 16:31:01.485201 Dram Type= 6, Freq= 0, CH_1, rank 0
2219 16:31:01.485280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2220 16:31:01.485415 ==
2221 16:31:01.485507 [Duty_Offset_Calibration]
2222 16:31:01.485583 B0:0 B1:5 CA:-5
2223 16:31:01.485658
2224 16:31:01.485734 [DutyScan_Calibration_Flow] k_type=0
2225 16:31:01.485810
2226 16:31:01.485902 ==CLK 0==
2227 16:31:01.485980 Final CLK duty delay cell = 0
2228 16:31:01.486059 [0] MAX Duty = 5125%(X100), DQS PI = 24
2229 16:31:01.486138 [0] MIN Duty = 4907%(X100), DQS PI = 44
2230 16:31:01.486221 [0] AVG Duty = 5016%(X100)
2231 16:31:01.486330
2232 16:31:01.486419 CH1 CLK Duty spec in!! Max-Min= 218%
2233 16:31:01.486496 [DutyScan_Calibration_Flow] ====Done====
2234 16:31:01.486571
2235 16:31:01.486647 [DutyScan_Calibration_Flow] k_type=1
2236 16:31:01.486737
2237 16:31:01.486826 ==DQS 0 ==
2238 16:31:01.486902 Final DQS duty delay cell = 0
2239 16:31:01.486979 [0] MAX Duty = 5125%(X100), DQS PI = 16
2240 16:31:01.487055 [0] MIN Duty = 4907%(X100), DQS PI = 24
2241 16:31:01.487131 [0] AVG Duty = 5016%(X100)
2242 16:31:01.487240
2243 16:31:01.487315 ==DQS 1 ==
2244 16:31:01.487391 Final DQS duty delay cell = -4
2245 16:31:01.487468 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2246 16:31:01.487544 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2247 16:31:01.487637 [-4] AVG Duty = 4953%(X100)
2248 16:31:01.487714
2249 16:31:01.487806 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2250 16:31:01.487881
2251 16:31:01.487957 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2252 16:31:01.488063 [DutyScan_Calibration_Flow] ====Done====
2253 16:31:01.488139
2254 16:31:01.488233 [DutyScan_Calibration_Flow] k_type=3
2255 16:31:01.488327
2256 16:31:01.488421 ==DQM 0 ==
2257 16:31:01.488514 Final DQM duty delay cell = -4
2258 16:31:01.488628 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2259 16:31:01.488708 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2260 16:31:01.488787 [-4] AVG Duty = 4953%(X100)
2261 16:31:01.488863
2262 16:31:01.488938 ==DQM 1 ==
2263 16:31:01.489031 Final DQM duty delay cell = -4
2264 16:31:01.489121 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2265 16:31:01.489198 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2266 16:31:01.489274 [-4] AVG Duty = 4968%(X100)
2267 16:31:01.489349
2268 16:31:01.489425 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2269 16:31:01.489518
2270 16:31:01.489596 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2271 16:31:01.489688 [DutyScan_Calibration_Flow] ====Done====
2272 16:31:01.489763
2273 16:31:01.489839 [DutyScan_Calibration_Flow] k_type=2
2274 16:31:01.489947
2275 16:31:01.490022 ==DQ 0 ==
2276 16:31:01.490098 Final DQ duty delay cell = 0
2277 16:31:01.490175 [0] MAX Duty = 5062%(X100), DQS PI = 0
2278 16:31:01.490289 [0] MIN Duty = 4938%(X100), DQS PI = 44
2279 16:31:01.490396 [0] AVG Duty = 5000%(X100)
2280 16:31:01.490474
2281 16:31:01.490550 ==DQ 1 ==
2282 16:31:01.490626 Final DQ duty delay cell = 0
2283 16:31:01.490703 [0] MAX Duty = 5031%(X100), DQS PI = 8
2284 16:31:01.490797 [0] MIN Duty = 4907%(X100), DQS PI = 0
2285 16:31:01.490888 [0] AVG Duty = 4969%(X100)
2286 16:31:01.490963
2287 16:31:01.491039 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2288 16:31:01.491114
2289 16:31:01.491205 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2290 16:31:01.491287 [DutyScan_Calibration_Flow] ====Done====
2291 16:31:01.491369 nWR fixed to 30
2292 16:31:01.491464 [ModeRegInit_LP4] CH0 RK0
2293 16:31:01.491544 [ModeRegInit_LP4] CH0 RK1
2294 16:31:01.491638 [ModeRegInit_LP4] CH1 RK0
2295 16:31:01.491717 [ModeRegInit_LP4] CH1 RK1
2296 16:31:01.491766 match AC timing 6
2297 16:31:01.491814 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2298 16:31:01.491862 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2299 16:31:01.491910 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2300 16:31:01.491977 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2301 16:31:01.492074 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2302 16:31:01.492168 ==
2303 16:31:01.492245 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 16:31:01.492322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2305 16:31:01.492398 ==
2306 16:31:01.492474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2307 16:31:01.492769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2308 16:31:01.492864 [CA 0] Center 39 (9~70) winsize 62
2309 16:31:01.492964 [CA 1] Center 39 (9~70) winsize 62
2310 16:31:01.493079 [CA 2] Center 36 (5~67) winsize 63
2311 16:31:01.493165 [CA 3] Center 35 (5~66) winsize 62
2312 16:31:01.493237 [CA 4] Center 34 (3~65) winsize 63
2313 16:31:01.493288 [CA 5] Center 33 (3~64) winsize 62
2314 16:31:01.493335
2315 16:31:01.493383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2316 16:31:01.493440
2317 16:31:01.493488 [CATrainingPosCal] consider 1 rank data
2318 16:31:01.493536 u2DelayCellTimex100 = 270/100 ps
2319 16:31:01.493585 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2320 16:31:01.493633 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2321 16:31:01.493681 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2322 16:31:01.493729 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2323 16:31:01.493777 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2324 16:31:01.493848 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2325 16:31:01.493911
2326 16:31:01.493958 CA PerBit enable=1, Macro0, CA PI delay=33
2327 16:31:01.494006
2328 16:31:01.494053 [CBTSetCACLKResult] CA Dly = 33
2329 16:31:01.494101 CS Dly: 7 (0~38)
2330 16:31:01.494148 ==
2331 16:31:01.494195 Dram Type= 6, Freq= 0, CH_0, rank 1
2332 16:31:01.494290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2333 16:31:01.494342 ==
2334 16:31:01.494391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2335 16:31:01.494439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2336 16:31:01.494487 [CA 0] Center 39 (9~70) winsize 62
2337 16:31:01.494535 [CA 1] Center 39 (8~70) winsize 63
2338 16:31:01.494582 [CA 2] Center 35 (5~66) winsize 62
2339 16:31:01.494630 [CA 3] Center 35 (4~66) winsize 63
2340 16:31:01.494689 [CA 4] Center 33 (3~64) winsize 62
2341 16:31:01.494766 [CA 5] Center 33 (3~64) winsize 62
2342 16:31:01.494837
2343 16:31:01.494907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2344 16:31:01.494956
2345 16:31:01.495003 [CATrainingPosCal] consider 2 rank data
2346 16:31:01.495051 u2DelayCellTimex100 = 270/100 ps
2347 16:31:01.495127 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2348 16:31:01.495183 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2349 16:31:01.495248 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2350 16:31:01.495295 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2351 16:31:01.495343 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2352 16:31:01.495391 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2353 16:31:01.495439
2354 16:31:01.495487 CA PerBit enable=1, Macro0, CA PI delay=33
2355 16:31:01.495542
2356 16:31:01.495590 [CBTSetCACLKResult] CA Dly = 33
2357 16:31:01.495638 CS Dly: 7 (0~39)
2358 16:31:01.495686
2359 16:31:01.495733 ----->DramcWriteLeveling(PI) begin...
2360 16:31:01.495782 ==
2361 16:31:01.495830 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 16:31:01.495878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2363 16:31:01.495928 ==
2364 16:31:01.495977 Write leveling (Byte 0): 27 => 27
2365 16:31:01.496025 Write leveling (Byte 1): 25 => 25
2366 16:31:01.496073 DramcWriteLeveling(PI) end<-----
2367 16:31:01.496121
2368 16:31:01.496168 ==
2369 16:31:01.496216 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 16:31:01.496263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 16:31:01.496311 ==
2372 16:31:01.496391 [Gating] SW mode calibration
2373 16:31:01.496465 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2374 16:31:01.496538 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2375 16:31:01.496596 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 16:31:01.496645 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2377 16:31:01.496693 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 16:31:01.496749 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 16:31:01.496797 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2380 16:31:01.496844 0 11 20 | B1->B0 | 3131 2c2c | 0 0 | (1 0) (1 0)
2381 16:31:01.496892 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 16:31:01.496940 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 16:31:01.496988 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 16:31:01.497036 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 16:31:01.497084 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 16:31:01.497153 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 16:31:01.497216 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 16:31:01.497263 0 12 20 | B1->B0 | 3333 3b3b | 1 0 | (0 0) (0 0)
2389 16:31:01.497311 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 16:31:01.497358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 16:31:01.497406 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 16:31:01.497454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 16:31:01.497501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 16:31:01.497548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 16:31:01.497601 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 16:31:01.497649 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2397 16:31:01.497697 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 16:31:01.497744 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 16:31:01.497792 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 16:31:01.497839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 16:31:01.497887 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 16:31:01.497936 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 16:31:01.498013 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 16:31:01.498085 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 16:31:01.498155 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 16:31:01.498252 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 16:31:01.498316 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 16:31:01.498364 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 16:31:01.498418 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 16:31:01.498467 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 16:31:01.498514 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 16:31:01.498756 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2413 16:31:01.498816 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2414 16:31:01.498868 Total UI for P1: 0, mck2ui 16
2415 16:31:01.498961 best dqsien dly found for B0: ( 0, 15, 20)
2416 16:31:01.499044 Total UI for P1: 0, mck2ui 16
2417 16:31:01.499131 best dqsien dly found for B1: ( 0, 15, 20)
2418 16:31:01.499194 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2419 16:31:01.499249 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2420 16:31:01.499325
2421 16:31:01.499401 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2422 16:31:01.499477 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2423 16:31:01.499553 [Gating] SW calibration Done
2424 16:31:01.499630 ==
2425 16:31:01.499719 Dram Type= 6, Freq= 0, CH_0, rank 0
2426 16:31:01.499792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2427 16:31:01.499863 ==
2428 16:31:01.499920 RX Vref Scan: 0
2429 16:31:01.499969
2430 16:31:01.500016 RX Vref 0 -> 0, step: 1
2431 16:31:01.500076
2432 16:31:01.500123 RX Delay -40 -> 252, step: 8
2433 16:31:01.500171 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2434 16:31:01.500218 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2435 16:31:01.500266 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2436 16:31:01.500314 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2437 16:31:01.500363 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2438 16:31:01.500410 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2439 16:31:01.500467 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2440 16:31:01.500515 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2441 16:31:01.500563 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2442 16:31:01.500611 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2443 16:31:01.500659 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2444 16:31:01.500707 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2445 16:31:01.500755 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2446 16:31:01.500803 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2447 16:31:01.500855 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2448 16:31:01.500905 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2449 16:31:01.500952 ==
2450 16:31:01.501000 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 16:31:01.501048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2452 16:31:01.501096 ==
2453 16:31:01.501182 DQS Delay:
2454 16:31:01.501230 DQS0 = 0, DQS1 = 0
2455 16:31:01.501277 DQM Delay:
2456 16:31:01.501354 DQM0 = 115, DQM1 = 106
2457 16:31:01.501427 DQ Delay:
2458 16:31:01.501497 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2459 16:31:01.501559 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2460 16:31:01.501608 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2461 16:31:01.501655 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2462 16:31:01.501710
2463 16:31:01.501758
2464 16:31:01.501806 ==
2465 16:31:01.501855 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 16:31:01.501903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2467 16:31:01.501951 ==
2468 16:31:01.501999
2469 16:31:01.502046
2470 16:31:01.502113 TX Vref Scan disable
2471 16:31:01.502188 == TX Byte 0 ==
2472 16:31:01.502289 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2473 16:31:01.502339 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2474 16:31:01.502388 == TX Byte 1 ==
2475 16:31:01.502436 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2476 16:31:01.502484 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2477 16:31:01.502531 ==
2478 16:31:01.502585 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 16:31:01.502634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 16:31:01.502681 ==
2481 16:31:01.502729 TX Vref=22, minBit 8, minWin=24, winSum=411
2482 16:31:01.502777 TX Vref=24, minBit 9, minWin=25, winSum=424
2483 16:31:01.502825 TX Vref=26, minBit 10, minWin=25, winSum=428
2484 16:31:01.502874 TX Vref=28, minBit 13, minWin=25, winSum=430
2485 16:31:01.502925 TX Vref=30, minBit 8, minWin=26, winSum=436
2486 16:31:01.503008 TX Vref=32, minBit 8, minWin=26, winSum=433
2487 16:31:01.503081 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
2488 16:31:01.503176
2489 16:31:01.503261 Final TX Range 1 Vref 30
2490 16:31:01.503325
2491 16:31:01.503372 ==
2492 16:31:01.503424 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 16:31:01.503473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2494 16:31:01.503522 ==
2495 16:31:01.503569
2496 16:31:01.503616
2497 16:31:01.503663 TX Vref Scan disable
2498 16:31:01.503710 == TX Byte 0 ==
2499 16:31:01.503758 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2500 16:31:01.503810 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2501 16:31:01.503860 == TX Byte 1 ==
2502 16:31:01.503908 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2503 16:31:01.503955 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2504 16:31:01.504002
2505 16:31:01.504048 [DATLAT]
2506 16:31:01.504095 Freq=1200, CH0 RK0
2507 16:31:01.504143
2508 16:31:01.504189 DATLAT Default: 0xd
2509 16:31:01.504243 0, 0xFFFF, sum = 0
2510 16:31:01.504293 1, 0xFFFF, sum = 0
2511 16:31:01.504342 2, 0xFFFF, sum = 0
2512 16:31:01.504390 3, 0xFFFF, sum = 0
2513 16:31:01.504439 4, 0xFFFF, sum = 0
2514 16:31:01.504488 5, 0xFFFF, sum = 0
2515 16:31:01.504536 6, 0xFFFF, sum = 0
2516 16:31:01.504583 7, 0xFFFF, sum = 0
2517 16:31:01.504643 8, 0xFFFF, sum = 0
2518 16:31:01.504720 9, 0xFFFF, sum = 0
2519 16:31:01.504791 10, 0xFFFF, sum = 0
2520 16:31:01.504863 11, 0x0, sum = 1
2521 16:31:01.504913 12, 0x0, sum = 2
2522 16:31:01.504962 13, 0x0, sum = 3
2523 16:31:01.505010 14, 0x0, sum = 4
2524 16:31:01.505063 best_step = 12
2525 16:31:01.505111
2526 16:31:01.505159 ==
2527 16:31:01.505205 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 16:31:01.505254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 16:31:01.505302 ==
2530 16:31:01.505368 RX Vref Scan: 1
2531 16:31:01.505428
2532 16:31:01.505474 Set Vref Range= 32 -> 127
2533 16:31:01.505525
2534 16:31:01.505573 RX Vref 32 -> 127, step: 1
2535 16:31:01.505621
2536 16:31:01.505669 RX Delay -21 -> 252, step: 4
2537 16:31:01.505717
2538 16:31:01.505764 Set Vref, RX VrefLevel [Byte0]: 32
2539 16:31:01.505811 [Byte1]: 32
2540 16:31:01.505858
2541 16:31:01.505906 Set Vref, RX VrefLevel [Byte0]: 33
2542 16:31:01.505959 [Byte1]: 33
2543 16:31:01.506007
2544 16:31:01.506053 Set Vref, RX VrefLevel [Byte0]: 34
2545 16:31:01.506101 [Byte1]: 34
2546 16:31:01.506148
2547 16:31:01.506195 Set Vref, RX VrefLevel [Byte0]: 35
2548 16:31:01.506270 [Byte1]: 35
2549 16:31:01.506332
2550 16:31:01.506414 Set Vref, RX VrefLevel [Byte0]: 36
2551 16:31:01.506490 [Byte1]: 36
2552 16:31:01.506559
2553 16:31:01.506625 Set Vref, RX VrefLevel [Byte0]: 37
2554 16:31:01.506674 [Byte1]: 37
2555 16:31:01.506721
2556 16:31:01.506776 Set Vref, RX VrefLevel [Byte0]: 38
2557 16:31:01.506825 [Byte1]: 38
2558 16:31:01.506873
2559 16:31:01.506920 Set Vref, RX VrefLevel [Byte0]: 39
2560 16:31:01.506969 [Byte1]: 39
2561 16:31:01.507016
2562 16:31:01.507062 Set Vref, RX VrefLevel [Byte0]: 40
2563 16:31:01.507111 [Byte1]: 40
2564 16:31:01.507168
2565 16:31:01.507431 Set Vref, RX VrefLevel [Byte0]: 41
2566 16:31:01.507485 [Byte1]: 41
2567 16:31:01.507534
2568 16:31:01.507587 Set Vref, RX VrefLevel [Byte0]: 42
2569 16:31:01.507637 [Byte1]: 42
2570 16:31:01.507684
2571 16:31:01.507732 Set Vref, RX VrefLevel [Byte0]: 43
2572 16:31:01.507780 [Byte1]: 43
2573 16:31:01.507829
2574 16:31:01.507877 Set Vref, RX VrefLevel [Byte0]: 44
2575 16:31:01.507925 [Byte1]: 44
2576 16:31:01.507986
2577 16:31:01.508062 Set Vref, RX VrefLevel [Byte0]: 45
2578 16:31:01.508132 [Byte1]: 45
2579 16:31:01.508203
2580 16:31:01.508251 Set Vref, RX VrefLevel [Byte0]: 46
2581 16:31:01.508300 [Byte1]: 46
2582 16:31:01.508348
2583 16:31:01.508429 Set Vref, RX VrefLevel [Byte0]: 47
2584 16:31:01.508492 [Byte1]: 47
2585 16:31:01.508540
2586 16:31:01.508587 Set Vref, RX VrefLevel [Byte0]: 48
2587 16:31:01.508635 [Byte1]: 48
2588 16:31:01.508682
2589 16:31:01.508728 Set Vref, RX VrefLevel [Byte0]: 49
2590 16:31:01.508776 [Byte1]: 49
2591 16:31:01.508824
2592 16:31:01.508871 Set Vref, RX VrefLevel [Byte0]: 50
2593 16:31:01.508925 [Byte1]: 50
2594 16:31:01.508973
2595 16:31:01.509020 Set Vref, RX VrefLevel [Byte0]: 51
2596 16:31:01.509068 [Byte1]: 51
2597 16:31:01.509132
2598 16:31:01.509196 Set Vref, RX VrefLevel [Byte0]: 52
2599 16:31:01.509258 [Byte1]: 52
2600 16:31:01.509307
2601 16:31:01.509355 Set Vref, RX VrefLevel [Byte0]: 53
2602 16:31:01.509432 [Byte1]: 53
2603 16:31:01.509509
2604 16:31:01.509562 Set Vref, RX VrefLevel [Byte0]: 54
2605 16:31:01.509613 [Byte1]: 54
2606 16:31:01.509662
2607 16:31:01.509711 Set Vref, RX VrefLevel [Byte0]: 55
2608 16:31:01.509760 [Byte1]: 55
2609 16:31:01.509822
2610 16:31:01.509869 Set Vref, RX VrefLevel [Byte0]: 56
2611 16:31:01.509916 [Byte1]: 56
2612 16:31:01.509963
2613 16:31:01.510010 Set Vref, RX VrefLevel [Byte0]: 57
2614 16:31:01.510058 [Byte1]: 57
2615 16:31:01.510131
2616 16:31:01.510205 Set Vref, RX VrefLevel [Byte0]: 58
2617 16:31:01.510314 [Byte1]: 58
2618 16:31:01.510394
2619 16:31:01.510458 Set Vref, RX VrefLevel [Byte0]: 59
2620 16:31:01.510506 [Byte1]: 59
2621 16:31:01.510554
2622 16:31:01.510602 Set Vref, RX VrefLevel [Byte0]: 60
2623 16:31:01.510649 [Byte1]: 60
2624 16:31:01.510701
2625 16:31:01.510750 Set Vref, RX VrefLevel [Byte0]: 61
2626 16:31:01.510798 [Byte1]: 61
2627 16:31:01.510845
2628 16:31:01.510892 Set Vref, RX VrefLevel [Byte0]: 62
2629 16:31:01.510939 [Byte1]: 62
2630 16:31:01.510986
2631 16:31:01.511033 Set Vref, RX VrefLevel [Byte0]: 63
2632 16:31:01.511080 [Byte1]: 63
2633 16:31:01.511133
2634 16:31:01.511182 Set Vref, RX VrefLevel [Byte0]: 64
2635 16:31:01.511229 [Byte1]: 64
2636 16:31:01.511277
2637 16:31:01.511324 Set Vref, RX VrefLevel [Byte0]: 65
2638 16:31:01.511371 [Byte1]: 65
2639 16:31:01.511418
2640 16:31:01.511465 Final RX Vref Byte 0 = 48 to rank0
2641 16:31:01.511513 Final RX Vref Byte 1 = 47 to rank0
2642 16:31:01.511569 Final RX Vref Byte 0 = 48 to rank1
2643 16:31:01.511618 Final RX Vref Byte 1 = 47 to rank1==
2644 16:31:01.511666 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 16:31:01.511713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2646 16:31:01.511761 ==
2647 16:31:01.511809 DQS Delay:
2648 16:31:01.511857 DQS0 = 0, DQS1 = 0
2649 16:31:01.511904 DQM Delay:
2650 16:31:01.511981 DQM0 = 114, DQM1 = 105
2651 16:31:01.512053 DQ Delay:
2652 16:31:01.512123 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2653 16:31:01.512184 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2654 16:31:01.512249 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2655 16:31:01.512311 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2656 16:31:01.512365
2657 16:31:01.512414
2658 16:31:01.512462 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2659 16:31:01.512511 CH0 RK0: MR19=404, MR18=A0A
2660 16:31:01.512558 CH0_RK0: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
2661 16:31:01.512607
2662 16:31:01.512654 ----->DramcWriteLeveling(PI) begin...
2663 16:31:01.512703 ==
2664 16:31:01.512756 Dram Type= 6, Freq= 0, CH_0, rank 1
2665 16:31:01.512805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2666 16:31:01.512853 ==
2667 16:31:01.512901 Write leveling (Byte 0): 28 => 28
2668 16:31:01.512948 Write leveling (Byte 1): 24 => 24
2669 16:31:01.512996 DramcWriteLeveling(PI) end<-----
2670 16:31:01.513043
2671 16:31:01.513091 ==
2672 16:31:01.513146 Dram Type= 6, Freq= 0, CH_0, rank 1
2673 16:31:01.513195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2674 16:31:01.513243 ==
2675 16:31:01.513291 [Gating] SW mode calibration
2676 16:31:01.513339 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2677 16:31:01.513388 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2678 16:31:01.513435 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2679 16:31:01.513484 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2680 16:31:01.513556 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2681 16:31:01.513634 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2682 16:31:01.513706 0 11 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2683 16:31:01.513775 0 11 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2684 16:31:01.513824 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2685 16:31:01.513872 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2686 16:31:01.513938 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2687 16:31:01.514047 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 16:31:01.514123 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 16:31:01.514200 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 16:31:01.514317 0 12 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2691 16:31:01.514396 0 12 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2692 16:31:01.514473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2693 16:31:01.514550 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2694 16:31:01.514627 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2695 16:31:01.514703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 16:31:01.514782 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 16:31:01.514860 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 16:31:01.515128 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2699 16:31:01.515214 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2700 16:31:01.515296 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2701 16:31:01.515367 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2702 16:31:01.515441 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 16:31:01.515519 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 16:31:01.515597 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 16:31:01.515675 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 16:31:01.515751 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 16:31:01.515828 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 16:31:01.515904 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 16:31:01.515980 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 16:31:01.516060 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 16:31:01.516137 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 16:31:01.516213 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 16:31:01.516289 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 16:31:01.516365 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2715 16:31:01.516445 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2716 16:31:01.516521 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2717 16:31:01.516597 Total UI for P1: 0, mck2ui 16
2718 16:31:01.516674 best dqsien dly found for B0: ( 0, 15, 18)
2719 16:31:01.516750 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2720 16:31:01.516832 Total UI for P1: 0, mck2ui 16
2721 16:31:01.516922 best dqsien dly found for B1: ( 0, 15, 22)
2722 16:31:01.516995 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2723 16:31:01.517056 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2724 16:31:01.517119
2725 16:31:01.517167 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2726 16:31:01.517226 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2727 16:31:01.517295 [Gating] SW calibration Done
2728 16:31:01.517357 ==
2729 16:31:01.517405 Dram Type= 6, Freq= 0, CH_0, rank 1
2730 16:31:01.517454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2731 16:31:01.517502 ==
2732 16:31:01.517550 RX Vref Scan: 0
2733 16:31:01.517598
2734 16:31:01.517648 RX Vref 0 -> 0, step: 1
2735 16:31:01.517697
2736 16:31:01.517744 RX Delay -40 -> 252, step: 8
2737 16:31:01.517792 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2738 16:31:01.517840 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2739 16:31:01.517888 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2740 16:31:01.517936 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2741 16:31:01.517984 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2742 16:31:01.518031 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2743 16:31:01.518111 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2744 16:31:01.518186 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2745 16:31:01.518288 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2746 16:31:01.518337 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2747 16:31:01.518386 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2748 16:31:01.518434 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2749 16:31:01.518498 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2750 16:31:01.518625 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2751 16:31:01.518710 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2752 16:31:01.518779 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2753 16:31:01.518861 ==
2754 16:31:01.518909 Dram Type= 6, Freq= 0, CH_0, rank 1
2755 16:31:01.518960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2756 16:31:01.519012 ==
2757 16:31:01.519059 DQS Delay:
2758 16:31:01.519106 DQS0 = 0, DQS1 = 0
2759 16:31:01.519155 DQM Delay:
2760 16:31:01.519202 DQM0 = 116, DQM1 = 107
2761 16:31:01.519249 DQ Delay:
2762 16:31:01.519296 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2763 16:31:01.519344 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2764 16:31:01.519399 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2765 16:31:01.519448 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2766 16:31:01.519497
2767 16:31:01.519544
2768 16:31:01.519591 ==
2769 16:31:01.519638 Dram Type= 6, Freq= 0, CH_0, rank 1
2770 16:31:01.519685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2771 16:31:01.519733 ==
2772 16:31:01.519787
2773 16:31:01.519836
2774 16:31:01.519883 TX Vref Scan disable
2775 16:31:01.519932 == TX Byte 0 ==
2776 16:31:01.519979 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2777 16:31:01.520028 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2778 16:31:01.520075 == TX Byte 1 ==
2779 16:31:01.520122 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2780 16:31:01.520204 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2781 16:31:01.520280 ==
2782 16:31:01.520351 Dram Type= 6, Freq= 0, CH_0, rank 1
2783 16:31:01.520418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2784 16:31:01.520466 ==
2785 16:31:01.520545 TX Vref=22, minBit 8, minWin=25, winSum=420
2786 16:31:01.520601 TX Vref=24, minBit 8, minWin=25, winSum=422
2787 16:31:01.520651 TX Vref=26, minBit 8, minWin=25, winSum=426
2788 16:31:01.520698 TX Vref=28, minBit 8, minWin=25, winSum=430
2789 16:31:01.520746 TX Vref=30, minBit 10, minWin=25, winSum=435
2790 16:31:01.520795 TX Vref=32, minBit 8, minWin=26, winSum=435
2791 16:31:01.520843 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 32
2792 16:31:01.520892
2793 16:31:01.520939 Final TX Range 1 Vref 32
2794 16:31:01.520993
2795 16:31:01.521041 ==
2796 16:31:01.521089 Dram Type= 6, Freq= 0, CH_0, rank 1
2797 16:31:01.521137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2798 16:31:01.521184 ==
2799 16:31:01.521231
2800 16:31:01.521277
2801 16:31:01.521325 TX Vref Scan disable
2802 16:31:01.521379 == TX Byte 0 ==
2803 16:31:01.521428 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2804 16:31:01.521476 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2805 16:31:01.521524 == TX Byte 1 ==
2806 16:31:01.521572 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2807 16:31:01.521620 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2808 16:31:01.521668
2809 16:31:01.521731 [DATLAT]
2810 16:31:01.521819 Freq=1200, CH0 RK1
2811 16:31:01.521893
2812 16:31:01.521963 DATLAT Default: 0xc
2813 16:31:01.522027 0, 0xFFFF, sum = 0
2814 16:31:01.522077 1, 0xFFFF, sum = 0
2815 16:31:01.522141 2, 0xFFFF, sum = 0
2816 16:31:01.522203 3, 0xFFFF, sum = 0
2817 16:31:01.522282 4, 0xFFFF, sum = 0
2818 16:31:01.522332 5, 0xFFFF, sum = 0
2819 16:31:01.522381 6, 0xFFFF, sum = 0
2820 16:31:01.522429 7, 0xFFFF, sum = 0
2821 16:31:01.522478 8, 0xFFFF, sum = 0
2822 16:31:01.522526 9, 0xFFFF, sum = 0
2823 16:31:01.522594 10, 0xFFFF, sum = 0
2824 16:31:01.522654 11, 0x0, sum = 1
2825 16:31:01.522927 12, 0x0, sum = 2
2826 16:31:01.523012 13, 0x0, sum = 3
2827 16:31:01.523063 14, 0x0, sum = 4
2828 16:31:01.523118 best_step = 12
2829 16:31:01.523167
2830 16:31:01.523215 ==
2831 16:31:01.523264 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 16:31:01.523312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2833 16:31:01.523362 ==
2834 16:31:01.523411 RX Vref Scan: 0
2835 16:31:01.523459
2836 16:31:01.523529 RX Vref 0 -> 0, step: 1
2837 16:31:01.523606
2838 16:31:01.523676 RX Delay -21 -> 252, step: 4
2839 16:31:01.523745 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2840 16:31:01.523796 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2841 16:31:01.523845 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2842 16:31:01.523899 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2843 16:31:01.523950 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2844 16:31:01.523999 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2845 16:31:01.524048 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2846 16:31:01.524097 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2847 16:31:01.524146 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2848 16:31:01.524194 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2849 16:31:01.524244 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2850 16:31:01.524293 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2851 16:31:01.524348 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2852 16:31:01.524398 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2853 16:31:01.524446 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2854 16:31:01.524495 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2855 16:31:01.524544 ==
2856 16:31:01.524592 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 16:31:01.524641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2858 16:31:01.524690 ==
2859 16:31:01.524746 DQS Delay:
2860 16:31:01.524795 DQS0 = 0, DQS1 = 0
2861 16:31:01.524844 DQM Delay:
2862 16:31:01.524893 DQM0 = 115, DQM1 = 105
2863 16:31:01.524942 DQ Delay:
2864 16:31:01.524991 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2865 16:31:01.525040 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2866 16:31:01.525119 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2867 16:31:01.525202 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2868 16:31:01.525305
2869 16:31:01.525375
2870 16:31:01.525442 [DQSOSCAuto] RK1, (LSB)MR18= 0x1212, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2871 16:31:01.525492 CH0 RK1: MR19=404, MR18=1212
2872 16:31:01.525541 CH0_RK1: MR19=0x404, MR18=0x1212, DQSOSC=403, MR23=63, INC=40, DEC=26
2873 16:31:01.525593 [RxdqsGatingPostProcess] freq 1200
2874 16:31:01.525642 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2875 16:31:01.525690 Pre-setting of DQS Precalculation
2876 16:31:01.525737 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2877 16:31:01.525786 ==
2878 16:31:01.525834 Dram Type= 6, Freq= 0, CH_1, rank 0
2879 16:31:01.525882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2880 16:31:01.525930 ==
2881 16:31:01.525980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2882 16:31:01.526032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2883 16:31:01.526080 [CA 0] Center 37 (7~68) winsize 62
2884 16:31:01.526127 [CA 1] Center 37 (7~68) winsize 62
2885 16:31:01.526175 [CA 2] Center 34 (4~65) winsize 62
2886 16:31:01.526251 [CA 3] Center 33 (3~64) winsize 62
2887 16:31:01.526315 [CA 4] Center 32 (1~63) winsize 63
2888 16:31:01.526363 [CA 5] Center 32 (2~63) winsize 62
2889 16:31:01.526411
2890 16:31:01.526465 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2891 16:31:01.526513
2892 16:31:01.526561 [CATrainingPosCal] consider 1 rank data
2893 16:31:01.526610 u2DelayCellTimex100 = 270/100 ps
2894 16:31:01.526657 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2895 16:31:01.526705 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2896 16:31:01.526753 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2897 16:31:01.526800 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2898 16:31:01.526856 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2899 16:31:01.526942 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2900 16:31:01.527013
2901 16:31:01.527083 CA PerBit enable=1, Macro0, CA PI delay=32
2902 16:31:01.527137
2903 16:31:01.527184 [CBTSetCACLKResult] CA Dly = 32
2904 16:31:01.527232 CS Dly: 5 (0~36)
2905 16:31:01.527288 ==
2906 16:31:01.527336 Dram Type= 6, Freq= 0, CH_1, rank 1
2907 16:31:01.527385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2908 16:31:01.527433 ==
2909 16:31:01.527480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2910 16:31:01.527529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2911 16:31:01.527577 [CA 0] Center 37 (7~68) winsize 62
2912 16:31:01.527625 [CA 1] Center 37 (7~68) winsize 62
2913 16:31:01.527680 [CA 2] Center 34 (3~65) winsize 63
2914 16:31:01.527728 [CA 3] Center 33 (3~64) winsize 62
2915 16:31:01.527776 [CA 4] Center 32 (2~63) winsize 62
2916 16:31:01.527823 [CA 5] Center 31 (1~62) winsize 62
2917 16:31:01.527870
2918 16:31:01.527918 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2919 16:31:01.527965
2920 16:31:01.528012 [CATrainingPosCal] consider 2 rank data
2921 16:31:01.528064 u2DelayCellTimex100 = 270/100 ps
2922 16:31:01.528113 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2923 16:31:01.528161 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2924 16:31:01.528209 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2925 16:31:01.528257 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2926 16:31:01.700268 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2927 16:31:01.700381 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2928 16:31:01.700446
2929 16:31:01.700506 CA PerBit enable=1, Macro0, CA PI delay=32
2930 16:31:01.700577
2931 16:31:01.700644 [CBTSetCACLKResult] CA Dly = 32
2932 16:31:01.700694 CS Dly: 6 (0~38)
2933 16:31:01.700744
2934 16:31:01.700792 ----->DramcWriteLeveling(PI) begin...
2935 16:31:01.700842 ==
2936 16:31:01.700891 Dram Type= 6, Freq= 0, CH_1, rank 0
2937 16:31:01.700940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2938 16:31:01.700989 ==
2939 16:31:01.701037 Write leveling (Byte 0): 23 => 23
2940 16:31:01.701086 Write leveling (Byte 1): 23 => 23
2941 16:31:01.701135 DramcWriteLeveling(PI) end<-----
2942 16:31:01.701183
2943 16:31:01.701231 ==
2944 16:31:01.701278 Dram Type= 6, Freq= 0, CH_1, rank 0
2945 16:31:01.701326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2946 16:31:01.701374 ==
2947 16:31:01.701422 [Gating] SW mode calibration
2948 16:31:01.701471 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2949 16:31:01.701521 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2950 16:31:01.701569 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2951 16:31:01.701818 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 16:31:01.701889 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 16:31:01.701987 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 16:31:01.702083 0 11 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (1 0)
2955 16:31:01.702179 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 16:31:01.702317 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 16:31:01.702401 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 16:31:01.702482 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 16:31:01.702558 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 16:31:01.702634 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 16:31:01.702710 0 12 12 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
2962 16:31:01.702787 0 12 16 | B1->B0 | 3737 4242 | 0 0 | (1 1) (1 1)
2963 16:31:01.702863 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 16:31:01.702939 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 16:31:01.703015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 16:31:01.703091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 16:31:01.703167 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 16:31:01.703242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 16:31:01.703319 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 16:31:01.703374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2971 16:31:01.703423 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2972 16:31:01.703470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 16:31:01.703518 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 16:31:01.703565 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 16:31:01.703613 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 16:31:01.703660 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 16:31:01.703708 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 16:31:01.703761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 16:31:01.703813 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 16:31:01.703863 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 16:31:01.703910 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 16:31:01.703964 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 16:31:01.704013 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 16:31:01.704061 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 16:31:01.704108 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2986 16:31:01.704156 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2987 16:31:01.704204 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2988 16:31:01.704251 Total UI for P1: 0, mck2ui 16
2989 16:31:01.704299 best dqsien dly found for B0: ( 0, 15, 14)
2990 16:31:01.704347 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2991 16:31:01.704395 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 16:31:01.704443 Total UI for P1: 0, mck2ui 16
2993 16:31:01.704491 best dqsien dly found for B1: ( 0, 15, 22)
2994 16:31:01.704539 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2995 16:31:01.704587 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2996 16:31:01.704634
2997 16:31:01.704683 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
2998 16:31:01.704730 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2999 16:31:01.704778 [Gating] SW calibration Done
3000 16:31:01.704825 ==
3001 16:31:01.704874 Dram Type= 6, Freq= 0, CH_1, rank 0
3002 16:31:01.704922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3003 16:31:01.704971 ==
3004 16:31:01.705018 RX Vref Scan: 0
3005 16:31:01.705065
3006 16:31:01.705113 RX Vref 0 -> 0, step: 1
3007 16:31:01.705159
3008 16:31:01.705206 RX Delay -40 -> 252, step: 8
3009 16:31:01.705254 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3010 16:31:01.705302 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3011 16:31:01.705350 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3012 16:31:01.705397 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3013 16:31:01.705445 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3014 16:31:01.705493 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3015 16:31:01.705541 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3016 16:31:01.705588 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3017 16:31:01.705637 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3018 16:31:01.705685 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3019 16:31:01.705733 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3020 16:31:01.705780 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3021 16:31:01.705828 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3022 16:31:01.705876 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3023 16:31:01.705924 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3024 16:31:01.705972 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3025 16:31:01.706021 ==
3026 16:31:01.706069 Dram Type= 6, Freq= 0, CH_1, rank 0
3027 16:31:01.706117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3028 16:31:01.706165 ==
3029 16:31:01.706215 DQS Delay:
3030 16:31:01.706307 DQS0 = 0, DQS1 = 0
3031 16:31:01.706356 DQM Delay:
3032 16:31:01.706403 DQM0 = 116, DQM1 = 107
3033 16:31:01.706451 DQ Delay:
3034 16:31:01.706499 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3035 16:31:01.706547 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3036 16:31:01.706594 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3037 16:31:01.706642 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3038 16:31:01.706689
3039 16:31:01.706737
3040 16:31:01.706788 ==
3041 16:31:01.706837 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 16:31:01.706891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3043 16:31:01.706940 ==
3044 16:31:01.706988
3045 16:31:01.707036
3046 16:31:01.707083 TX Vref Scan disable
3047 16:31:01.707131 == TX Byte 0 ==
3048 16:31:01.707178 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3049 16:31:01.707226 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3050 16:31:01.707274 == TX Byte 1 ==
3051 16:31:01.707321 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3052 16:31:01.707368 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3053 16:31:01.707416 ==
3054 16:31:01.707464 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 16:31:01.707517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3056 16:31:01.707567 ==
3057 16:31:01.707614 TX Vref=22, minBit 8, minWin=25, winSum=410
3058 16:31:01.707856 TX Vref=24, minBit 8, minWin=25, winSum=421
3059 16:31:01.707945 TX Vref=26, minBit 15, minWin=25, winSum=426
3060 16:31:01.708043 TX Vref=28, minBit 8, minWin=26, winSum=432
3061 16:31:01.708140 TX Vref=30, minBit 8, minWin=26, winSum=432
3062 16:31:01.708237 TX Vref=32, minBit 8, minWin=26, winSum=432
3063 16:31:01.708329 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3064 16:31:01.708413
3065 16:31:01.708481 Final TX Range 1 Vref 28
3066 16:31:01.708531
3067 16:31:01.708580 ==
3068 16:31:01.708629 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 16:31:01.708677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3070 16:31:01.708726 ==
3071 16:31:01.708774
3072 16:31:01.708823
3073 16:31:01.708870 TX Vref Scan disable
3074 16:31:01.708919 == TX Byte 0 ==
3075 16:31:01.708967 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3076 16:31:01.709015 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3077 16:31:01.709064 == TX Byte 1 ==
3078 16:31:01.709112 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3079 16:31:01.709160 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3080 16:31:01.709207
3081 16:31:01.709255 [DATLAT]
3082 16:31:01.709303 Freq=1200, CH1 RK0
3083 16:31:01.709354
3084 16:31:01.709402 DATLAT Default: 0xd
3085 16:31:01.709450 0, 0xFFFF, sum = 0
3086 16:31:01.709500 1, 0xFFFF, sum = 0
3087 16:31:01.709550 2, 0xFFFF, sum = 0
3088 16:31:01.709599 3, 0xFFFF, sum = 0
3089 16:31:01.709648 4, 0xFFFF, sum = 0
3090 16:31:01.709697 5, 0xFFFF, sum = 0
3091 16:31:01.709745 6, 0xFFFF, sum = 0
3092 16:31:01.709794 7, 0xFFFF, sum = 0
3093 16:31:01.709842 8, 0xFFFF, sum = 0
3094 16:31:01.709891 9, 0xFFFF, sum = 0
3095 16:31:01.709940 10, 0xFFFF, sum = 0
3096 16:31:01.709989 11, 0x0, sum = 1
3097 16:31:01.710037 12, 0x0, sum = 2
3098 16:31:01.710086 13, 0x0, sum = 3
3099 16:31:01.710143 14, 0x0, sum = 4
3100 16:31:01.710228 best_step = 12
3101 16:31:01.710317
3102 16:31:01.710370 ==
3103 16:31:01.710419 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 16:31:01.710467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3105 16:31:01.710515 ==
3106 16:31:01.710562 RX Vref Scan: 1
3107 16:31:01.710609
3108 16:31:01.710657 Set Vref Range= 32 -> 127
3109 16:31:01.710705
3110 16:31:01.710753 RX Vref 32 -> 127, step: 1
3111 16:31:01.710800
3112 16:31:01.710847 RX Delay -29 -> 252, step: 4
3113 16:31:01.710895
3114 16:31:01.710942 Set Vref, RX VrefLevel [Byte0]: 32
3115 16:31:01.710990 [Byte1]: 32
3116 16:31:01.711037
3117 16:31:01.711085 Set Vref, RX VrefLevel [Byte0]: 33
3118 16:31:01.711132 [Byte1]: 33
3119 16:31:01.711180
3120 16:31:01.711227 Set Vref, RX VrefLevel [Byte0]: 34
3121 16:31:01.711281 [Byte1]: 34
3122 16:31:01.711329
3123 16:31:01.711377 Set Vref, RX VrefLevel [Byte0]: 35
3124 16:31:01.711425 [Byte1]: 35
3125 16:31:01.711473
3126 16:31:01.711520 Set Vref, RX VrefLevel [Byte0]: 36
3127 16:31:01.711567 [Byte1]: 36
3128 16:31:01.711614
3129 16:31:01.711662 Set Vref, RX VrefLevel [Byte0]: 37
3130 16:31:01.711710 [Byte1]: 37
3131 16:31:01.711757
3132 16:31:01.711805 Set Vref, RX VrefLevel [Byte0]: 38
3133 16:31:01.711853 [Byte1]: 38
3134 16:31:01.711901
3135 16:31:01.711948 Set Vref, RX VrefLevel [Byte0]: 39
3136 16:31:01.711996 [Byte1]: 39
3137 16:31:01.712044
3138 16:31:01.712091 Set Vref, RX VrefLevel [Byte0]: 40
3139 16:31:01.712139 [Byte1]: 40
3140 16:31:01.712187
3141 16:31:01.712234 Set Vref, RX VrefLevel [Byte0]: 41
3142 16:31:01.712282 [Byte1]: 41
3143 16:31:01.712330
3144 16:31:01.712377 Set Vref, RX VrefLevel [Byte0]: 42
3145 16:31:01.712424 [Byte1]: 42
3146 16:31:01.712472
3147 16:31:01.712519 Set Vref, RX VrefLevel [Byte0]: 43
3148 16:31:01.712566 [Byte1]: 43
3149 16:31:01.712613
3150 16:31:01.712660 Set Vref, RX VrefLevel [Byte0]: 44
3151 16:31:01.712708 [Byte1]: 44
3152 16:31:01.712755
3153 16:31:01.712803 Set Vref, RX VrefLevel [Byte0]: 45
3154 16:31:01.712851 [Byte1]: 45
3155 16:31:01.712899
3156 16:31:01.712946 Set Vref, RX VrefLevel [Byte0]: 46
3157 16:31:01.712994 [Byte1]: 46
3158 16:31:01.713042
3159 16:31:01.713090 Set Vref, RX VrefLevel [Byte0]: 47
3160 16:31:01.713137 [Byte1]: 47
3161 16:31:01.713185
3162 16:31:01.713233 Set Vref, RX VrefLevel [Byte0]: 48
3163 16:31:01.713287 [Byte1]: 48
3164 16:31:01.713335
3165 16:31:01.713384 Set Vref, RX VrefLevel [Byte0]: 49
3166 16:31:01.713432 [Byte1]: 49
3167 16:31:01.713479
3168 16:31:01.713528 Set Vref, RX VrefLevel [Byte0]: 50
3169 16:31:01.713575 [Byte1]: 50
3170 16:31:01.713623
3171 16:31:01.713670 Set Vref, RX VrefLevel [Byte0]: 51
3172 16:31:01.713722 [Byte1]: 51
3173 16:31:01.713771
3174 16:31:01.713825 Set Vref, RX VrefLevel [Byte0]: 52
3175 16:31:01.713878 [Byte1]: 52
3176 16:31:01.713926
3177 16:31:01.713974 Set Vref, RX VrefLevel [Byte0]: 53
3178 16:31:01.714022 [Byte1]: 53
3179 16:31:01.714070
3180 16:31:01.714117 Set Vref, RX VrefLevel [Byte0]: 54
3181 16:31:01.714165 [Byte1]: 54
3182 16:31:01.714216
3183 16:31:01.714294 Set Vref, RX VrefLevel [Byte0]: 55
3184 16:31:01.714342 [Byte1]: 55
3185 16:31:01.714390
3186 16:31:01.714437 Set Vref, RX VrefLevel [Byte0]: 56
3187 16:31:01.714484 [Byte1]: 56
3188 16:31:01.714531
3189 16:31:01.714578 Set Vref, RX VrefLevel [Byte0]: 57
3190 16:31:01.714626 [Byte1]: 57
3191 16:31:01.714673
3192 16:31:01.714719 Set Vref, RX VrefLevel [Byte0]: 58
3193 16:31:01.714768 [Byte1]: 58
3194 16:31:01.714815
3195 16:31:01.714863 Set Vref, RX VrefLevel [Byte0]: 59
3196 16:31:01.714911 [Byte1]: 59
3197 16:31:01.714959
3198 16:31:01.715005 Set Vref, RX VrefLevel [Byte0]: 60
3199 16:31:01.715053 [Byte1]: 60
3200 16:31:01.715100
3201 16:31:01.715147 Set Vref, RX VrefLevel [Byte0]: 61
3202 16:31:01.715194 [Byte1]: 61
3203 16:31:01.715241
3204 16:31:01.715288 Set Vref, RX VrefLevel [Byte0]: 62
3205 16:31:01.715335 [Byte1]: 62
3206 16:31:01.715383
3207 16:31:01.715431 Set Vref, RX VrefLevel [Byte0]: 63
3208 16:31:01.715479 [Byte1]: 63
3209 16:31:01.715527
3210 16:31:01.715574 Set Vref, RX VrefLevel [Byte0]: 64
3211 16:31:01.715622 [Byte1]: 64
3212 16:31:01.715670
3213 16:31:01.715717 Set Vref, RX VrefLevel [Byte0]: 65
3214 16:31:01.715765 [Byte1]: 65
3215 16:31:01.715812
3216 16:31:01.715859 Set Vref, RX VrefLevel [Byte0]: 66
3217 16:31:01.715907 [Byte1]: 66
3218 16:31:01.715955
3219 16:31:01.716002 Final RX Vref Byte 0 = 57 to rank0
3220 16:31:01.716051 Final RX Vref Byte 1 = 51 to rank0
3221 16:31:01.716100 Final RX Vref Byte 0 = 57 to rank1
3222 16:31:01.716148 Final RX Vref Byte 1 = 51 to rank1==
3223 16:31:01.716196 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 16:31:01.716437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3225 16:31:01.716513 ==
3226 16:31:01.716610 DQS Delay:
3227 16:31:01.716705 DQS0 = 0, DQS1 = 0
3228 16:31:01.716793 DQM Delay:
3229 16:31:01.716874 DQM0 = 115, DQM1 = 105
3230 16:31:01.716953 DQ Delay:
3231 16:31:01.717009 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3232 16:31:01.717059 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3233 16:31:01.717107 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3234 16:31:01.717203 DQ12 =112, DQ13 =118, DQ14 =114, DQ15 =116
3235 16:31:01.717313
3236 16:31:01.717404
3237 16:31:01.717482 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3238 16:31:01.717578 CH1 RK0: MR19=404, MR18=1616
3239 16:31:01.717671 CH1_RK0: MR19=0x404, MR18=0x1616, DQSOSC=401, MR23=63, INC=40, DEC=27
3240 16:31:01.717747
3241 16:31:01.717823 ----->DramcWriteLeveling(PI) begin...
3242 16:31:01.717900 ==
3243 16:31:01.717977 Dram Type= 6, Freq= 0, CH_1, rank 1
3244 16:31:01.718054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3245 16:31:01.718130 ==
3246 16:31:01.718207 Write leveling (Byte 0): 21 => 21
3247 16:31:01.718298 Write leveling (Byte 1): 21 => 21
3248 16:31:01.718347 DramcWriteLeveling(PI) end<-----
3249 16:31:01.718396
3250 16:31:01.718443 ==
3251 16:31:01.718492 Dram Type= 6, Freq= 0, CH_1, rank 1
3252 16:31:01.718539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3253 16:31:01.718588 ==
3254 16:31:01.718635 [Gating] SW mode calibration
3255 16:31:01.718684 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3256 16:31:01.718732 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3257 16:31:01.718780 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3258 16:31:01.718828 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3259 16:31:01.718911 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3260 16:31:01.718959 0 11 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
3261 16:31:01.719007 0 11 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
3262 16:31:01.719055 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3263 16:31:01.719103 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 16:31:01.719150 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 16:31:01.719198 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3266 16:31:01.719245 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3267 16:31:01.719293 0 12 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3268 16:31:01.719341 0 12 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
3269 16:31:01.719390 0 12 16 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3270 16:31:01.719437 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 16:31:01.719485 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 16:31:01.719536 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 16:31:01.719590 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 16:31:01.719638 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 16:31:01.719685 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 16:31:01.719733 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3277 16:31:01.719787 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3278 16:31:01.719836 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3279 16:31:01.719884 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 16:31:01.719932 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 16:31:01.719980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 16:31:01.720028 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 16:31:01.720075 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 16:31:01.720123 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 16:31:01.720170 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 16:31:01.720224 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 16:31:01.720278 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 16:31:01.720326 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 16:31:01.720395 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 16:31:01.720449 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 16:31:01.720512 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 16:31:01.720560 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3293 16:31:01.720608 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3294 16:31:01.720656 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3295 16:31:01.720703 Total UI for P1: 0, mck2ui 16
3296 16:31:01.720752 best dqsien dly found for B0: ( 0, 15, 14)
3297 16:31:01.720799 Total UI for P1: 0, mck2ui 16
3298 16:31:01.720847 best dqsien dly found for B1: ( 0, 15, 16)
3299 16:31:01.720894 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3300 16:31:01.720942 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3301 16:31:01.720989
3302 16:31:01.721035 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3303 16:31:01.721083 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3304 16:31:01.721129 [Gating] SW calibration Done
3305 16:31:01.721177 ==
3306 16:31:01.721224 Dram Type= 6, Freq= 0, CH_1, rank 1
3307 16:31:01.721272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3308 16:31:01.721319 ==
3309 16:31:01.721366 RX Vref Scan: 0
3310 16:31:01.721413
3311 16:31:01.721459 RX Vref 0 -> 0, step: 1
3312 16:31:01.721506
3313 16:31:01.721552 RX Delay -40 -> 252, step: 8
3314 16:31:01.721599 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3315 16:31:01.721647 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
3316 16:31:01.721694 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3317 16:31:01.721742 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3318 16:31:01.721788 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3319 16:31:01.721836 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3320 16:31:01.721884 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3321 16:31:01.721930 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3322 16:31:01.721977 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3323 16:31:01.722025 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3324 16:31:01.722072 iDelay=200, Bit 10, Center 103 (24 ~ 183) 160
3325 16:31:01.722120 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3326 16:31:01.722168 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3327 16:31:01.722220 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3328 16:31:01.722494 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3329 16:31:01.722548 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3330 16:31:01.722597 ==
3331 16:31:01.722645 Dram Type= 6, Freq= 0, CH_1, rank 1
3332 16:31:01.722695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3333 16:31:01.722745 ==
3334 16:31:01.722792 DQS Delay:
3335 16:31:01.722839 DQS0 = 0, DQS1 = 0
3336 16:31:01.722886 DQM Delay:
3337 16:31:01.722950 DQM0 = 116, DQM1 = 105
3338 16:31:01.722999 DQ Delay:
3339 16:31:01.723059 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3340 16:31:01.723106 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3341 16:31:01.723159 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3342 16:31:01.723207 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3343 16:31:01.723255
3344 16:31:01.723302
3345 16:31:01.723348 ==
3346 16:31:01.723395 Dram Type= 6, Freq= 0, CH_1, rank 1
3347 16:31:01.723443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3348 16:31:01.723491 ==
3349 16:31:01.723538
3350 16:31:01.723588
3351 16:31:01.723635 TX Vref Scan disable
3352 16:31:01.723721 == TX Byte 0 ==
3353 16:31:01.723836 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3354 16:31:01.723913 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3355 16:31:01.723964 == TX Byte 1 ==
3356 16:31:01.724012 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3357 16:31:01.724059 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3358 16:31:01.724106 ==
3359 16:31:01.724154 Dram Type= 6, Freq= 0, CH_1, rank 1
3360 16:31:01.724202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3361 16:31:01.724252 ==
3362 16:31:01.724299 TX Vref=22, minBit 9, minWin=25, winSum=422
3363 16:31:01.724347 TX Vref=24, minBit 3, minWin=26, winSum=427
3364 16:31:01.724395 TX Vref=26, minBit 3, minWin=26, winSum=428
3365 16:31:01.724442 TX Vref=28, minBit 11, minWin=25, winSum=429
3366 16:31:01.724489 TX Vref=30, minBit 3, minWin=26, winSum=433
3367 16:31:01.724536 TX Vref=32, minBit 9, minWin=26, winSum=435
3368 16:31:01.724584 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 32
3369 16:31:01.724632
3370 16:31:01.724680 Final TX Range 1 Vref 32
3371 16:31:01.724727
3372 16:31:01.724773 ==
3373 16:31:01.724820 Dram Type= 6, Freq= 0, CH_1, rank 1
3374 16:31:01.724869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3375 16:31:01.724917 ==
3376 16:31:01.724964
3377 16:31:01.725010
3378 16:31:01.725057 TX Vref Scan disable
3379 16:31:01.725104 == TX Byte 0 ==
3380 16:31:01.725152 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3381 16:31:01.725200 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3382 16:31:01.725247 == TX Byte 1 ==
3383 16:31:01.725295 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3384 16:31:01.725342 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3385 16:31:01.725390
3386 16:31:01.725436 [DATLAT]
3387 16:31:01.725482 Freq=1200, CH1 RK1
3388 16:31:01.725530
3389 16:31:01.725577 DATLAT Default: 0xc
3390 16:31:01.725625 0, 0xFFFF, sum = 0
3391 16:31:01.725674 1, 0xFFFF, sum = 0
3392 16:31:01.725722 2, 0xFFFF, sum = 0
3393 16:31:01.725769 3, 0xFFFF, sum = 0
3394 16:31:01.725817 4, 0xFFFF, sum = 0
3395 16:31:01.725865 5, 0xFFFF, sum = 0
3396 16:31:01.725913 6, 0xFFFF, sum = 0
3397 16:31:01.725960 7, 0xFFFF, sum = 0
3398 16:31:01.726009 8, 0xFFFF, sum = 0
3399 16:31:01.726058 9, 0xFFFF, sum = 0
3400 16:31:01.726106 10, 0xFFFF, sum = 0
3401 16:31:01.726154 11, 0x0, sum = 1
3402 16:31:01.726202 12, 0x0, sum = 2
3403 16:31:01.726292 13, 0x0, sum = 3
3404 16:31:01.726341 14, 0x0, sum = 4
3405 16:31:01.726389 best_step = 12
3406 16:31:01.726436
3407 16:31:01.726483 ==
3408 16:31:01.726531 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 16:31:01.726579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3410 16:31:01.726627 ==
3411 16:31:01.726707 RX Vref Scan: 0
3412 16:31:01.726754
3413 16:31:01.726801 RX Vref 0 -> 0, step: 1
3414 16:31:01.726848
3415 16:31:01.726895 RX Delay -29 -> 252, step: 4
3416 16:31:01.726942 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3417 16:31:01.726989 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3418 16:31:01.727038 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3419 16:31:01.727086 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3420 16:31:01.727133 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3421 16:31:01.727181 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3422 16:31:01.727229 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3423 16:31:01.727276 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3424 16:31:01.727322 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3425 16:31:01.727370 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3426 16:31:01.727417 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3427 16:31:01.727505 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3428 16:31:01.727553 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3429 16:31:01.727602 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3430 16:31:01.727650 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3431 16:31:01.727697 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3432 16:31:01.727744 ==
3433 16:31:01.727791 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 16:31:01.727838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3435 16:31:01.727885 ==
3436 16:31:01.727932 DQS Delay:
3437 16:31:01.727979 DQS0 = 0, DQS1 = 0
3438 16:31:01.728026 DQM Delay:
3439 16:31:01.728073 DQM0 = 114, DQM1 = 103
3440 16:31:01.728120 DQ Delay:
3441 16:31:01.728166 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3442 16:31:01.728214 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3443 16:31:01.728290 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3444 16:31:01.728337 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =110
3445 16:31:01.728384
3446 16:31:01.728431
3447 16:31:01.728478 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3448 16:31:01.728526 CH1 RK1: MR19=404, MR18=909
3449 16:31:01.728573 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3450 16:31:01.728621 [RxdqsGatingPostProcess] freq 1200
3451 16:31:01.728668 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3452 16:31:01.728716 Pre-setting of DQS Precalculation
3453 16:31:01.728763 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3454 16:31:01.728811 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3455 16:31:01.728861 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3456 16:31:01.728910
3457 16:31:01.728957
3458 16:31:01.729003 [Calibration Summary] 2400 Mbps
3459 16:31:01.729051 CH 0, Rank 0
3460 16:31:01.729099 SW Impedance : PASS
3461 16:31:01.729147 DUTY Scan : NO K
3462 16:31:01.729194 ZQ Calibration : PASS
3463 16:31:01.729241 Jitter Meter : NO K
3464 16:31:01.729288 CBT Training : PASS
3465 16:31:01.729336 Write leveling : PASS
3466 16:31:01.729383 RX DQS gating : PASS
3467 16:31:01.729431 RX DQ/DQS(RDDQC) : PASS
3468 16:31:01.729478 TX DQ/DQS : PASS
3469 16:31:01.729526 RX DATLAT : PASS
3470 16:31:01.729573 RX DQ/DQS(Engine): PASS
3471 16:31:01.729811 TX OE : NO K
3472 16:31:01.729865 All Pass.
3473 16:31:01.729913
3474 16:31:01.729960 CH 0, Rank 1
3475 16:31:01.730008 SW Impedance : PASS
3476 16:31:01.730055 DUTY Scan : NO K
3477 16:31:01.730102 ZQ Calibration : PASS
3478 16:31:01.730149 Jitter Meter : NO K
3479 16:31:01.730217 CBT Training : PASS
3480 16:31:01.730279 Write leveling : PASS
3481 16:31:01.730326 RX DQS gating : PASS
3482 16:31:01.730373 RX DQ/DQS(RDDQC) : PASS
3483 16:31:01.730420 TX DQ/DQS : PASS
3484 16:31:01.730468 RX DATLAT : PASS
3485 16:31:01.730515 RX DQ/DQS(Engine): PASS
3486 16:31:01.730562 TX OE : NO K
3487 16:31:01.730610 All Pass.
3488 16:31:01.730657
3489 16:31:01.730704 CH 1, Rank 0
3490 16:31:01.730752 SW Impedance : PASS
3491 16:31:01.730799 DUTY Scan : NO K
3492 16:31:01.730847 ZQ Calibration : PASS
3493 16:31:01.730893 Jitter Meter : NO K
3494 16:31:01.730941 CBT Training : PASS
3495 16:31:01.730988 Write leveling : PASS
3496 16:31:01.731036 RX DQS gating : PASS
3497 16:31:01.731084 RX DQ/DQS(RDDQC) : PASS
3498 16:31:01.731133 TX DQ/DQS : PASS
3499 16:31:01.731180 RX DATLAT : PASS
3500 16:31:01.731227 RX DQ/DQS(Engine): PASS
3501 16:31:01.731274 TX OE : NO K
3502 16:31:01.731322 All Pass.
3503 16:31:01.731369
3504 16:31:01.731415 CH 1, Rank 1
3505 16:31:01.731462 SW Impedance : PASS
3506 16:31:01.731509 DUTY Scan : NO K
3507 16:31:01.731556 ZQ Calibration : PASS
3508 16:31:01.731621 Jitter Meter : NO K
3509 16:31:01.731684 CBT Training : PASS
3510 16:31:01.731731 Write leveling : PASS
3511 16:31:01.731777 RX DQS gating : PASS
3512 16:31:01.731824 RX DQ/DQS(RDDQC) : PASS
3513 16:31:01.731871 TX DQ/DQS : PASS
3514 16:31:01.731918 RX DATLAT : PASS
3515 16:31:01.731965 RX DQ/DQS(Engine): PASS
3516 16:31:01.732012 TX OE : NO K
3517 16:31:01.732059 All Pass.
3518 16:31:01.732107
3519 16:31:01.732153 DramC Write-DBI off
3520 16:31:01.732201 PER_BANK_REFRESH: Hybrid Mode
3521 16:31:01.732248 TX_TRACKING: ON
3522 16:31:01.732296 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3523 16:31:01.732344 [FAST_K] Save calibration result to emmc
3524 16:31:01.732392 dramc_set_vcore_voltage set vcore to 650000
3525 16:31:01.732440 Read voltage for 600, 5
3526 16:31:01.732486 Vio18 = 0
3527 16:31:01.732533 Vcore = 650000
3528 16:31:01.732579 Vdram = 0
3529 16:31:01.732628 Vddq = 0
3530 16:31:01.732675 Vmddr = 0
3531 16:31:01.732722 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3532 16:31:01.732770 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3533 16:31:01.732818 MEM_TYPE=3, freq_sel=19
3534 16:31:01.732865 sv_algorithm_assistance_LP4_1600
3535 16:31:01.732913 ============ PULL DRAM RESETB DOWN ============
3536 16:31:01.732961 ========== PULL DRAM RESETB DOWN end =========
3537 16:31:01.733009 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3538 16:31:01.733057 ===================================
3539 16:31:01.733106 LPDDR4 DRAM CONFIGURATION
3540 16:31:01.733153 ===================================
3541 16:31:01.733219 EX_ROW_EN[0] = 0x0
3542 16:31:01.733281 EX_ROW_EN[1] = 0x0
3543 16:31:01.733329 LP4Y_EN = 0x0
3544 16:31:01.733376 WORK_FSP = 0x0
3545 16:31:01.733423 WL = 0x2
3546 16:31:01.733470 RL = 0x2
3547 16:31:01.733516 BL = 0x2
3548 16:31:01.733564 RPST = 0x0
3549 16:31:01.733611 RD_PRE = 0x0
3550 16:31:01.733659 WR_PRE = 0x1
3551 16:31:01.733706 WR_PST = 0x0
3552 16:31:01.733754 DBI_WR = 0x0
3553 16:31:01.733800 DBI_RD = 0x0
3554 16:31:01.733847 OTF = 0x1
3555 16:31:01.733894 ===================================
3556 16:31:01.733941 ===================================
3557 16:31:01.733989 ANA top config
3558 16:31:01.734053 ===================================
3559 16:31:01.734102 DLL_ASYNC_EN = 0
3560 16:31:01.734151 ALL_SLAVE_EN = 1
3561 16:31:01.734199 NEW_RANK_MODE = 1
3562 16:31:01.734265 DLL_IDLE_MODE = 1
3563 16:31:01.734312 LP45_APHY_COMB_EN = 1
3564 16:31:01.734359 TX_ODT_DIS = 1
3565 16:31:01.734407 NEW_8X_MODE = 1
3566 16:31:01.734455 ===================================
3567 16:31:01.734502 ===================================
3568 16:31:01.734550 data_rate = 1200
3569 16:31:01.734598 CKR = 1
3570 16:31:01.734645 DQ_P2S_RATIO = 8
3571 16:31:01.734693 ===================================
3572 16:31:01.734740 CA_P2S_RATIO = 8
3573 16:31:01.734788 DQ_CA_OPEN = 0
3574 16:31:01.734835 DQ_SEMI_OPEN = 0
3575 16:31:01.734899 CA_SEMI_OPEN = 0
3576 16:31:01.734947 CA_FULL_RATE = 0
3577 16:31:01.735009 DQ_CKDIV4_EN = 1
3578 16:31:01.735056 CA_CKDIV4_EN = 1
3579 16:31:01.735104 CA_PREDIV_EN = 0
3580 16:31:01.735153 PH8_DLY = 0
3581 16:31:01.735200 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3582 16:31:01.735249 DQ_AAMCK_DIV = 4
3583 16:31:01.735296 CA_AAMCK_DIV = 4
3584 16:31:01.735343 CA_ADMCK_DIV = 4
3585 16:31:01.735391 DQ_TRACK_CA_EN = 0
3586 16:31:01.735438 CA_PICK = 600
3587 16:31:01.735484 CA_MCKIO = 600
3588 16:31:01.735531 MCKIO_SEMI = 0
3589 16:31:01.735579 PLL_FREQ = 2288
3590 16:31:01.735626 DQ_UI_PI_RATIO = 32
3591 16:31:01.735673 CA_UI_PI_RATIO = 0
3592 16:31:01.735720 ===================================
3593 16:31:01.735767 ===================================
3594 16:31:01.735815 memory_type:LPDDR4
3595 16:31:01.735862 GP_NUM : 10
3596 16:31:01.735909 SRAM_EN : 1
3597 16:31:01.735955 MD32_EN : 0
3598 16:31:01.736002 ===================================
3599 16:31:01.736050 [ANA_INIT] >>>>>>>>>>>>>>
3600 16:31:01.736097 <<<<<< [CONFIGURE PHASE]: ANA_TX
3601 16:31:01.736145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3602 16:31:01.736192 ===================================
3603 16:31:01.736240 data_rate = 1200,PCW = 0X5800
3604 16:31:01.736287 ===================================
3605 16:31:01.736334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3606 16:31:01.736382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3607 16:31:01.736429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3608 16:31:01.736477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3609 16:31:01.736525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3610 16:31:01.736572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3611 16:31:01.736619 [ANA_INIT] flow start
3612 16:31:01.736666 [ANA_INIT] PLL >>>>>>>>
3613 16:31:01.736714 [ANA_INIT] PLL <<<<<<<<
3614 16:31:01.736952 [ANA_INIT] MIDPI >>>>>>>>
3615 16:31:01.737005 [ANA_INIT] MIDPI <<<<<<<<
3616 16:31:01.737052 [ANA_INIT] DLL >>>>>>>>
3617 16:31:01.737100 [ANA_INIT] flow end
3618 16:31:01.737147 ============ LP4 DIFF to SE enter ============
3619 16:31:01.737197 ============ LP4 DIFF to SE exit ============
3620 16:31:01.737245 [ANA_INIT] <<<<<<<<<<<<<
3621 16:31:01.737293 [Flow] Enable top DCM control >>>>>
3622 16:31:01.737340 [Flow] Enable top DCM control <<<<<
3623 16:31:01.737387 Enable DLL master slave shuffle
3624 16:31:01.737434 ==============================================================
3625 16:31:01.737481 Gating Mode config
3626 16:31:01.737529 ==============================================================
3627 16:31:01.737577 Config description:
3628 16:31:01.737625 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3629 16:31:01.737674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3630 16:31:01.737722 SELPH_MODE 0: By rank 1: By Phase
3631 16:31:01.737770 ==============================================================
3632 16:31:01.737818 GAT_TRACK_EN = 1
3633 16:31:01.737865 RX_GATING_MODE = 2
3634 16:31:01.737913 RX_GATING_TRACK_MODE = 2
3635 16:31:01.737961 SELPH_MODE = 1
3636 16:31:01.738009 PICG_EARLY_EN = 1
3637 16:31:01.738056 VALID_LAT_VALUE = 1
3638 16:31:01.738104 ==============================================================
3639 16:31:01.738152 Enter into Gating configuration >>>>
3640 16:31:01.738199 Exit from Gating configuration <<<<
3641 16:31:01.738276 Enter into DVFS_PRE_config >>>>>
3642 16:31:01.738337 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3643 16:31:01.738386 Exit from DVFS_PRE_config <<<<<
3644 16:31:01.738433 Enter into PICG configuration >>>>
3645 16:31:01.738480 Exit from PICG configuration <<<<
3646 16:31:01.738528 [RX_INPUT] configuration >>>>>
3647 16:31:01.738575 [RX_INPUT] configuration <<<<<
3648 16:31:01.738622 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3649 16:31:01.738670 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3650 16:31:01.738717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3651 16:31:01.738765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3652 16:31:01.738813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3653 16:31:01.738863 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3654 16:31:01.738911 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3655 16:31:01.738959 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3656 16:31:01.739007 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3657 16:31:01.739055 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3658 16:31:01.739103 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3659 16:31:01.739150 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3660 16:31:01.739198 ===================================
3661 16:31:01.739245 LPDDR4 DRAM CONFIGURATION
3662 16:31:01.739293 ===================================
3663 16:31:01.739341 EX_ROW_EN[0] = 0x0
3664 16:31:01.739388 EX_ROW_EN[1] = 0x0
3665 16:31:01.739435 LP4Y_EN = 0x0
3666 16:31:01.739482 WORK_FSP = 0x0
3667 16:31:01.739529 WL = 0x2
3668 16:31:01.739576 RL = 0x2
3669 16:31:01.739623 BL = 0x2
3670 16:31:01.739669 RPST = 0x0
3671 16:31:01.739716 RD_PRE = 0x0
3672 16:31:01.739763 WR_PRE = 0x1
3673 16:31:01.739810 WR_PST = 0x0
3674 16:31:01.739857 DBI_WR = 0x0
3675 16:31:01.739903 DBI_RD = 0x0
3676 16:31:01.739950 OTF = 0x1
3677 16:31:01.739997 ===================================
3678 16:31:01.740044 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3679 16:31:01.740091 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3680 16:31:01.740138 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3681 16:31:01.740185 ===================================
3682 16:31:01.740232 LPDDR4 DRAM CONFIGURATION
3683 16:31:01.740280 ===================================
3684 16:31:01.740328 EX_ROW_EN[0] = 0x10
3685 16:31:01.740375 EX_ROW_EN[1] = 0x0
3686 16:31:01.740422 LP4Y_EN = 0x0
3687 16:31:01.740470 WORK_FSP = 0x0
3688 16:31:01.740517 WL = 0x2
3689 16:31:01.740564 RL = 0x2
3690 16:31:01.740613 BL = 0x2
3691 16:31:01.740660 RPST = 0x0
3692 16:31:01.740706 RD_PRE = 0x0
3693 16:31:01.740754 WR_PRE = 0x1
3694 16:31:01.740801 WR_PST = 0x0
3695 16:31:01.740848 DBI_WR = 0x0
3696 16:31:01.740895 DBI_RD = 0x0
3697 16:31:01.740943 OTF = 0x1
3698 16:31:01.740990 ===================================
3699 16:31:01.741038 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3700 16:31:01.741086 nWR fixed to 30
3701 16:31:01.741133 [ModeRegInit_LP4] CH0 RK0
3702 16:31:01.741180 [ModeRegInit_LP4] CH0 RK1
3703 16:31:01.741227 [ModeRegInit_LP4] CH1 RK0
3704 16:31:01.741274 [ModeRegInit_LP4] CH1 RK1
3705 16:31:01.741321 match AC timing 16
3706 16:31:01.741368 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3707 16:31:01.741416 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3708 16:31:01.741463 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3709 16:31:01.741511 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3710 16:31:01.741559 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3711 16:31:01.741606 ==
3712 16:31:01.741653 Dram Type= 6, Freq= 0, CH_0, rank 0
3713 16:31:01.741700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3714 16:31:01.741748 ==
3715 16:31:01.741795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3716 16:31:01.741843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3717 16:31:01.741891 [CA 0] Center 35 (5~66) winsize 62
3718 16:31:01.741938 [CA 1] Center 35 (5~66) winsize 62
3719 16:31:01.741986 [CA 2] Center 34 (4~65) winsize 62
3720 16:31:01.742032 [CA 3] Center 34 (4~65) winsize 62
3721 16:31:01.742079 [CA 4] Center 33 (3~64) winsize 62
3722 16:31:01.742327 [CA 5] Center 33 (3~64) winsize 62
3723 16:31:01.742380
3724 16:31:01.742428 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3725 16:31:01.742476
3726 16:31:01.742524 [CATrainingPosCal] consider 1 rank data
3727 16:31:01.742572 u2DelayCellTimex100 = 270/100 ps
3728 16:31:01.742619 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3729 16:31:01.742667 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3730 16:31:01.742714 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3731 16:31:01.742761 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3732 16:31:01.742810 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3733 16:31:01.742858 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3734 16:31:01.742905
3735 16:31:01.742952 CA PerBit enable=1, Macro0, CA PI delay=33
3736 16:31:01.743000
3737 16:31:01.743047 [CBTSetCACLKResult] CA Dly = 33
3738 16:31:01.743095 CS Dly: 4 (0~35)
3739 16:31:01.743142 ==
3740 16:31:01.743188 Dram Type= 6, Freq= 0, CH_0, rank 1
3741 16:31:01.743236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3742 16:31:01.743283 ==
3743 16:31:01.743331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3744 16:31:01.743379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3745 16:31:01.743427 [CA 0] Center 36 (6~66) winsize 61
3746 16:31:01.743475 [CA 1] Center 35 (5~66) winsize 62
3747 16:31:01.743523 [CA 2] Center 34 (4~65) winsize 62
3748 16:31:01.743570 [CA 3] Center 34 (4~65) winsize 62
3749 16:31:01.743616 [CA 4] Center 33 (3~64) winsize 62
3750 16:31:01.743663 [CA 5] Center 33 (3~64) winsize 62
3751 16:31:01.743710
3752 16:31:01.743758 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3753 16:31:01.743805
3754 16:31:01.743852 [CATrainingPosCal] consider 2 rank data
3755 16:31:01.743899 u2DelayCellTimex100 = 270/100 ps
3756 16:31:01.743946 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3757 16:31:01.743994 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3758 16:31:01.744042 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3759 16:31:01.744089 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3760 16:31:01.744136 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3761 16:31:01.744183 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3762 16:31:01.744230
3763 16:31:01.744277 CA PerBit enable=1, Macro0, CA PI delay=33
3764 16:31:01.744325
3765 16:31:01.744372 [CBTSetCACLKResult] CA Dly = 33
3766 16:31:01.744419 CS Dly: 5 (0~37)
3767 16:31:01.744465
3768 16:31:01.744512 ----->DramcWriteLeveling(PI) begin...
3769 16:31:01.744560 ==
3770 16:31:01.744607 Dram Type= 6, Freq= 0, CH_0, rank 0
3771 16:31:01.744655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3772 16:31:01.744704 ==
3773 16:31:01.744751 Write leveling (Byte 0): 29 => 29
3774 16:31:01.744799 Write leveling (Byte 1): 29 => 29
3775 16:31:01.744847 DramcWriteLeveling(PI) end<-----
3776 16:31:01.744894
3777 16:31:01.744940 ==
3778 16:31:01.744987 Dram Type= 6, Freq= 0, CH_0, rank 0
3779 16:31:01.745035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3780 16:31:01.745082 ==
3781 16:31:01.745130 [Gating] SW mode calibration
3782 16:31:01.745178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3783 16:31:01.745226 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3784 16:31:01.745274 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3785 16:31:01.745322 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3786 16:31:01.745369 0 5 8 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
3787 16:31:01.745417 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3788 16:31:01.745464 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3789 16:31:01.745511 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3790 16:31:01.745557 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 16:31:01.745605 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 16:31:01.745653 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3793 16:31:01.745701 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 16:31:01.745748 0 6 8 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
3795 16:31:01.745797 0 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3796 16:31:01.745845 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 16:31:01.745892 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 16:31:01.745939 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 16:31:01.745986 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 16:31:01.746034 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 16:31:01.746081 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 16:31:01.746129 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3803 16:31:01.746177 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3804 16:31:01.746252 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3805 16:31:01.746315 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 16:31:01.746361 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 16:31:01.746409 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 16:31:01.746457 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 16:31:01.746505 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 16:31:01.746553 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 16:31:01.746600 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 16:31:01.746647 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 16:31:01.746695 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 16:31:01.746742 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 16:31:01.746789 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 16:31:01.746836 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 16:31:01.746883 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3818 16:31:01.746930 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3819 16:31:01.746978 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3820 16:31:01.747025 Total UI for P1: 0, mck2ui 16
3821 16:31:01.747073 best dqsien dly found for B0: ( 0, 9, 6)
3822 16:31:01.747120 Total UI for P1: 0, mck2ui 16
3823 16:31:01.747169 best dqsien dly found for B1: ( 0, 9, 8)
3824 16:31:01.747216 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3825 16:31:01.747263 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3826 16:31:01.747311
3827 16:31:01.747359 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3828 16:31:01.747406 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3829 16:31:01.747454 [Gating] SW calibration Done
3830 16:31:01.747688 ==
3831 16:31:01.747743 Dram Type= 6, Freq= 0, CH_0, rank 0
3832 16:31:01.747791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3833 16:31:01.747839 ==
3834 16:31:01.747887 RX Vref Scan: 0
3835 16:31:01.747933
3836 16:31:01.747981 RX Vref 0 -> 0, step: 1
3837 16:31:01.748028
3838 16:31:01.748075 RX Delay -230 -> 252, step: 16
3839 16:31:01.748123 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3840 16:31:01.748171 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3841 16:31:01.748219 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3842 16:31:01.748266 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3843 16:31:01.748313 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3844 16:31:01.748362 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3845 16:31:01.748410 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3846 16:31:01.748458 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3847 16:31:01.748506 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3848 16:31:01.748553 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3849 16:31:01.748600 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3850 16:31:01.748647 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3851 16:31:01.748695 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3852 16:31:01.748741 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3853 16:31:01.748789 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3854 16:31:01.748836 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3855 16:31:01.748883 ==
3856 16:31:01.748931 Dram Type= 6, Freq= 0, CH_0, rank 0
3857 16:31:01.748978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3858 16:31:01.749026 ==
3859 16:31:01.749073 DQS Delay:
3860 16:31:01.749120 DQS0 = 0, DQS1 = 0
3861 16:31:01.749166 DQM Delay:
3862 16:31:01.749213 DQM0 = 38, DQM1 = 33
3863 16:31:01.749259 DQ Delay:
3864 16:31:01.749306 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3865 16:31:01.749354 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3866 16:31:01.749402 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3867 16:31:01.749449 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3868 16:31:01.749497
3869 16:31:01.749543
3870 16:31:01.749590 ==
3871 16:31:01.749637 Dram Type= 6, Freq= 0, CH_0, rank 0
3872 16:31:01.749684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3873 16:31:01.749731 ==
3874 16:31:01.749778
3875 16:31:01.749857
3876 16:31:01.749903 TX Vref Scan disable
3877 16:31:01.749951 == TX Byte 0 ==
3878 16:31:01.749998 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3879 16:31:01.750046 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3880 16:31:01.750093 == TX Byte 1 ==
3881 16:31:01.750140 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3882 16:31:01.750188 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3883 16:31:01.750256 ==
3884 16:31:01.750318 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 16:31:01.750366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 16:31:01.750414 ==
3887 16:31:01.750461
3888 16:31:01.750507
3889 16:31:01.750554 TX Vref Scan disable
3890 16:31:01.750601 == TX Byte 0 ==
3891 16:31:01.750648 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3892 16:31:01.750696 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3893 16:31:01.750744 == TX Byte 1 ==
3894 16:31:01.750791 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3895 16:31:01.750838 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3896 16:31:01.750885
3897 16:31:01.750932 [DATLAT]
3898 16:31:01.750979 Freq=600, CH0 RK0
3899 16:31:01.751026
3900 16:31:01.751073 DATLAT Default: 0x9
3901 16:31:01.751120 0, 0xFFFF, sum = 0
3902 16:31:01.751169 1, 0xFFFF, sum = 0
3903 16:31:01.751217 2, 0xFFFF, sum = 0
3904 16:31:01.751264 3, 0xFFFF, sum = 0
3905 16:31:01.751311 4, 0xFFFF, sum = 0
3906 16:31:01.751359 5, 0xFFFF, sum = 0
3907 16:31:01.751408 6, 0xFFFF, sum = 0
3908 16:31:01.751457 7, 0x0, sum = 1
3909 16:31:01.751504 8, 0x0, sum = 2
3910 16:31:01.751552 9, 0x0, sum = 3
3911 16:31:01.751600 10, 0x0, sum = 4
3912 16:31:01.751647 best_step = 8
3913 16:31:01.751694
3914 16:31:01.751741 ==
3915 16:31:01.751789 Dram Type= 6, Freq= 0, CH_0, rank 0
3916 16:31:01.751837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3917 16:31:01.751884 ==
3918 16:31:01.751931 RX Vref Scan: 1
3919 16:31:01.751978
3920 16:31:01.752025 RX Vref 0 -> 0, step: 1
3921 16:31:01.752073
3922 16:31:01.752119 RX Delay -195 -> 252, step: 8
3923 16:31:01.752166
3924 16:31:01.752213 Set Vref, RX VrefLevel [Byte0]: 48
3925 16:31:01.752260 [Byte1]: 47
3926 16:31:01.752308
3927 16:31:01.752354 Final RX Vref Byte 0 = 48 to rank0
3928 16:31:01.752402 Final RX Vref Byte 1 = 47 to rank0
3929 16:31:02.021985 Final RX Vref Byte 0 = 48 to rank1
3930 16:31:02.022119 Final RX Vref Byte 1 = 47 to rank1==
3931 16:31:02.022184 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 16:31:02.022265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3933 16:31:02.022332 ==
3934 16:31:02.022384 DQS Delay:
3935 16:31:02.022434 DQS0 = 0, DQS1 = 0
3936 16:31:02.022484 DQM Delay:
3937 16:31:02.022533 DQM0 = 39, DQM1 = 30
3938 16:31:02.022581 DQ Delay:
3939 16:31:02.022630 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =32
3940 16:31:02.022680 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
3941 16:31:02.022729 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3942 16:31:02.022777 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3943 16:31:02.022825
3944 16:31:02.022873
3945 16:31:02.022920 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3946 16:31:02.022970 CH0 RK0: MR19=808, MR18=5050
3947 16:31:02.023018 CH0_RK0: MR19=0x808, MR18=0x5050, DQSOSC=394, MR23=63, INC=168, DEC=112
3948 16:31:02.023066
3949 16:31:02.023115 ----->DramcWriteLeveling(PI) begin...
3950 16:31:02.023164 ==
3951 16:31:02.023211 Dram Type= 6, Freq= 0, CH_0, rank 1
3952 16:31:02.023260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3953 16:31:02.023308 ==
3954 16:31:02.023356 Write leveling (Byte 0): 30 => 30
3955 16:31:02.023405 Write leveling (Byte 1): 28 => 28
3956 16:31:02.023470 DramcWriteLeveling(PI) end<-----
3957 16:31:02.023533
3958 16:31:02.023580 ==
3959 16:31:02.023627 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 16:31:02.023675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3961 16:31:02.023722 ==
3962 16:31:02.023769 [Gating] SW mode calibration
3963 16:31:02.023816 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 16:31:02.023865 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3965 16:31:02.023912 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 16:31:02.023959 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 16:31:02.024007 0 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
3968 16:31:02.024053 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3969 16:31:02.024101 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 16:31:02.024149 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 16:31:02.024196 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 16:31:02.024244 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 16:31:02.024482 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 16:31:02.024536 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 16:31:02.024657 0 6 8 | B1->B0 | 2c2c 302f | 0 1 | (0 0) (0 0)
3976 16:31:02.024705 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3977 16:31:02.024753 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 16:31:02.024801 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 16:31:02.024848 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 16:31:02.024896 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 16:31:02.024943 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 16:31:02.024990 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 16:31:02.025037 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3984 16:31:02.025084 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 16:31:02.025132 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 16:31:02.025179 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 16:31:02.025227 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 16:31:02.025274 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 16:31:02.025322 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 16:31:02.025368 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 16:31:02.025416 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 16:31:02.025462 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 16:31:02.025510 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 16:31:02.025557 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 16:31:02.025605 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 16:31:02.025652 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 16:31:02.025699 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 16:31:02.025746 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 16:31:02.025793 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4000 16:31:02.025840 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 16:31:02.025886 Total UI for P1: 0, mck2ui 16
4002 16:31:02.025935 best dqsien dly found for B0: ( 0, 9, 8)
4003 16:31:02.025982 Total UI for P1: 0, mck2ui 16
4004 16:31:02.026029 best dqsien dly found for B1: ( 0, 9, 8)
4005 16:31:02.026077 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4006 16:31:02.026124 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4007 16:31:02.026171
4008 16:31:02.026225 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4009 16:31:02.026314 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4010 16:31:02.027864 [Gating] SW calibration Done
4011 16:31:02.027920 ==
4012 16:31:02.031725 Dram Type= 6, Freq= 0, CH_0, rank 1
4013 16:31:02.035202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4014 16:31:02.035279 ==
4015 16:31:02.037947 RX Vref Scan: 0
4016 16:31:02.038023
4017 16:31:02.038081 RX Vref 0 -> 0, step: 1
4018 16:31:02.038136
4019 16:31:02.041637 RX Delay -230 -> 252, step: 16
4020 16:31:02.047900 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4021 16:31:02.051377 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4022 16:31:02.054891 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4023 16:31:02.057823 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4024 16:31:02.061283 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4025 16:31:02.068133 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4026 16:31:02.070992 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4027 16:31:02.074487 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4028 16:31:02.078054 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4029 16:31:02.084335 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4030 16:31:02.087796 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4031 16:31:02.091141 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4032 16:31:02.094778 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4033 16:31:02.101025 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4034 16:31:02.103974 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4035 16:31:02.107280 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4036 16:31:02.107358 ==
4037 16:31:02.110774 Dram Type= 6, Freq= 0, CH_0, rank 1
4038 16:31:02.114072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4039 16:31:02.114172 ==
4040 16:31:02.117255 DQS Delay:
4041 16:31:02.117332 DQS0 = 0, DQS1 = 0
4042 16:31:02.120715 DQM Delay:
4043 16:31:02.120793 DQM0 = 42, DQM1 = 32
4044 16:31:02.120851 DQ Delay:
4045 16:31:02.123977 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4046 16:31:02.127687 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4047 16:31:02.130421 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4048 16:31:02.133757 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4049 16:31:02.133834
4050 16:31:02.133894
4051 16:31:02.137068 ==
4052 16:31:02.140761 Dram Type= 6, Freq= 0, CH_0, rank 1
4053 16:31:02.143872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4054 16:31:02.143950 ==
4055 16:31:02.144009
4056 16:31:02.144063
4057 16:31:02.146952 TX Vref Scan disable
4058 16:31:02.147028 == TX Byte 0 ==
4059 16:31:02.153774 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4060 16:31:02.157372 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4061 16:31:02.157481 == TX Byte 1 ==
4062 16:31:02.163573 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4063 16:31:02.167158 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4064 16:31:02.167235 ==
4065 16:31:02.170535 Dram Type= 6, Freq= 0, CH_0, rank 1
4066 16:31:02.173494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4067 16:31:02.173571 ==
4068 16:31:02.173630
4069 16:31:02.173684
4070 16:31:02.176961 TX Vref Scan disable
4071 16:31:02.180534 == TX Byte 0 ==
4072 16:31:02.183675 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4073 16:31:02.186862 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4074 16:31:02.190350 == TX Byte 1 ==
4075 16:31:02.193804 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4076 16:31:02.196595 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4077 16:31:02.196673
4078 16:31:02.200198 [DATLAT]
4079 16:31:02.200276 Freq=600, CH0 RK1
4080 16:31:02.200336
4081 16:31:02.203672 DATLAT Default: 0x8
4082 16:31:02.203748 0, 0xFFFF, sum = 0
4083 16:31:02.206620 1, 0xFFFF, sum = 0
4084 16:31:02.206698 2, 0xFFFF, sum = 0
4085 16:31:02.210103 3, 0xFFFF, sum = 0
4086 16:31:02.210181 4, 0xFFFF, sum = 0
4087 16:31:02.213684 5, 0xFFFF, sum = 0
4088 16:31:02.213762 6, 0xFFFF, sum = 0
4089 16:31:02.216708 7, 0x0, sum = 1
4090 16:31:02.216785 8, 0x0, sum = 2
4091 16:31:02.220178 9, 0x0, sum = 3
4092 16:31:02.220262 10, 0x0, sum = 4
4093 16:31:02.222969 best_step = 8
4094 16:31:02.223047
4095 16:31:02.223106 ==
4096 16:31:02.226476 Dram Type= 6, Freq= 0, CH_0, rank 1
4097 16:31:02.229974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4098 16:31:02.230052 ==
4099 16:31:02.233324 RX Vref Scan: 0
4100 16:31:02.233399
4101 16:31:02.233458 RX Vref 0 -> 0, step: 1
4102 16:31:02.233513
4103 16:31:02.236358 RX Delay -195 -> 252, step: 8
4104 16:31:02.243375 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4105 16:31:02.246549 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4106 16:31:02.249921 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4107 16:31:02.253133 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4108 16:31:02.260240 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4109 16:31:02.263395 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4110 16:31:02.266485 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4111 16:31:02.269878 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4112 16:31:02.273274 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4113 16:31:02.279890 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4114 16:31:02.282902 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4115 16:31:02.286571 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4116 16:31:02.289591 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4117 16:31:02.296270 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4118 16:31:02.299678 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4119 16:31:02.302796 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4120 16:31:02.302873 ==
4121 16:31:02.306092 Dram Type= 6, Freq= 0, CH_0, rank 1
4122 16:31:02.312980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4123 16:31:02.313074 ==
4124 16:31:02.313135 DQS Delay:
4125 16:31:02.313190 DQS0 = 0, DQS1 = 0
4126 16:31:02.316447 DQM Delay:
4127 16:31:02.316557 DQM0 = 41, DQM1 = 33
4128 16:31:02.319649 DQ Delay:
4129 16:31:02.322973 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4130 16:31:02.326101 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4131 16:31:02.329309 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4132 16:31:02.332983 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4133 16:31:02.333060
4134 16:31:02.333120
4135 16:31:02.339470 [DQSOSCAuto] RK1, (LSB)MR18= 0x7070, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4136 16:31:02.342356 CH0 RK1: MR19=808, MR18=7070
4137 16:31:02.349265 CH0_RK1: MR19=0x808, MR18=0x7070, DQSOSC=388, MR23=63, INC=174, DEC=116
4138 16:31:02.352381 [RxdqsGatingPostProcess] freq 600
4139 16:31:02.355858 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4140 16:31:02.359250 Pre-setting of DQS Precalculation
4141 16:31:02.365475 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4142 16:31:02.365554 ==
4143 16:31:02.369040 Dram Type= 6, Freq= 0, CH_1, rank 0
4144 16:31:02.372313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4145 16:31:02.372391 ==
4146 16:31:02.378809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4147 16:31:02.385409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4148 16:31:02.389010 [CA 0] Center 35 (5~66) winsize 62
4149 16:31:02.392157 [CA 1] Center 35 (5~66) winsize 62
4150 16:31:02.395223 [CA 2] Center 33 (3~64) winsize 62
4151 16:31:02.398787 [CA 3] Center 33 (3~64) winsize 62
4152 16:31:02.402064 [CA 4] Center 33 (2~64) winsize 63
4153 16:31:02.405230 [CA 5] Center 33 (2~64) winsize 63
4154 16:31:02.405308
4155 16:31:02.408578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4156 16:31:02.408655
4157 16:31:02.412264 [CATrainingPosCal] consider 1 rank data
4158 16:31:02.415129 u2DelayCellTimex100 = 270/100 ps
4159 16:31:02.418485 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4160 16:31:02.422044 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4161 16:31:02.424984 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4162 16:31:02.428665 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4163 16:31:02.431584 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4164 16:31:02.434998 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4165 16:31:02.435086
4166 16:31:02.441391 CA PerBit enable=1, Macro0, CA PI delay=33
4167 16:31:02.441477
4168 16:31:02.441555 [CBTSetCACLKResult] CA Dly = 33
4169 16:31:02.444981 CS Dly: 3 (0~34)
4170 16:31:02.445048 ==
4171 16:31:02.448461 Dram Type= 6, Freq= 0, CH_1, rank 1
4172 16:31:02.451318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4173 16:31:02.451411 ==
4174 16:31:02.458401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4175 16:31:02.465048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4176 16:31:02.468319 [CA 0] Center 35 (4~66) winsize 63
4177 16:31:02.471545 [CA 1] Center 34 (4~65) winsize 62
4178 16:31:02.475059 [CA 2] Center 33 (3~64) winsize 62
4179 16:31:02.478037 [CA 3] Center 33 (3~64) winsize 62
4180 16:31:02.481208 [CA 4] Center 32 (2~63) winsize 62
4181 16:31:02.484573 [CA 5] Center 32 (2~63) winsize 62
4182 16:31:02.484650
4183 16:31:02.488441 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4184 16:31:02.488518
4185 16:31:02.491535 [CATrainingPosCal] consider 2 rank data
4186 16:31:02.494692 u2DelayCellTimex100 = 270/100 ps
4187 16:31:02.497815 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4188 16:31:02.501215 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4189 16:31:02.504438 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4190 16:31:02.507897 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4191 16:31:02.511258 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4192 16:31:02.517663 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4193 16:31:02.517742
4194 16:31:02.521346 CA PerBit enable=1, Macro0, CA PI delay=32
4195 16:31:02.521423
4196 16:31:02.524726 [CBTSetCACLKResult] CA Dly = 32
4197 16:31:02.524804 CS Dly: 3 (0~35)
4198 16:31:02.524863
4199 16:31:02.527459 ----->DramcWriteLeveling(PI) begin...
4200 16:31:02.527538 ==
4201 16:31:02.531118 Dram Type= 6, Freq= 0, CH_1, rank 0
4202 16:31:02.534495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4203 16:31:02.537792 ==
4204 16:31:02.541299 Write leveling (Byte 0): 28 => 28
4205 16:31:02.541376 Write leveling (Byte 1): 28 => 28
4206 16:31:02.544142 DramcWriteLeveling(PI) end<-----
4207 16:31:02.544219
4208 16:31:02.544278 ==
4209 16:31:02.547743 Dram Type= 6, Freq= 0, CH_1, rank 0
4210 16:31:02.554309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4211 16:31:02.554388 ==
4212 16:31:02.557647 [Gating] SW mode calibration
4213 16:31:02.563922 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 16:31:02.567401 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4215 16:31:02.574363 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 16:31:02.577272 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
4217 16:31:02.580701 0 5 8 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
4218 16:31:02.587233 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 16:31:02.590456 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 16:31:02.593971 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 16:31:02.600645 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 16:31:02.603709 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 16:31:02.606941 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 16:31:02.613666 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4225 16:31:02.617064 0 6 8 | B1->B0 | 3534 3c3c | 1 0 | (0 0) (0 0)
4226 16:31:02.620146 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 16:31:02.627094 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 16:31:02.630475 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 16:31:02.633337 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 16:31:02.639889 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 16:31:02.643731 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 16:31:02.646490 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4233 16:31:02.653631 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4234 16:31:02.656525 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 16:31:02.660112 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 16:31:02.663092 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 16:31:02.669799 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 16:31:02.673403 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 16:31:02.676872 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 16:31:02.683237 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 16:31:02.686675 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 16:31:02.689787 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 16:31:02.696521 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 16:31:02.700037 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 16:31:02.703013 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 16:31:02.709884 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 16:31:02.712896 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 16:31:02.716516 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4249 16:31:02.719862 Total UI for P1: 0, mck2ui 16
4250 16:31:02.722769 best dqsien dly found for B0: ( 0, 9, 2)
4251 16:31:02.729773 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4252 16:31:02.732691 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 16:31:02.736156 Total UI for P1: 0, mck2ui 16
4254 16:31:02.739322 best dqsien dly found for B1: ( 0, 9, 8)
4255 16:31:02.742681 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4256 16:31:02.745748 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4257 16:31:02.745824
4258 16:31:02.749375 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4259 16:31:02.752619 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4260 16:31:02.756126 [Gating] SW calibration Done
4261 16:31:02.756202 ==
4262 16:31:02.759547 Dram Type= 6, Freq= 0, CH_1, rank 0
4263 16:31:02.765906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4264 16:31:02.766007 ==
4265 16:31:02.766093 RX Vref Scan: 0
4266 16:31:02.766174
4267 16:31:02.768975 RX Vref 0 -> 0, step: 1
4268 16:31:02.769052
4269 16:31:02.772456 RX Delay -230 -> 252, step: 16
4270 16:31:02.775961 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4271 16:31:02.778855 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4272 16:31:02.782398 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4273 16:31:02.788744 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4274 16:31:02.792361 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4275 16:31:02.795532 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4276 16:31:02.799068 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4277 16:31:02.805679 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4278 16:31:02.808822 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4279 16:31:02.811781 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4280 16:31:02.815253 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4281 16:31:02.818758 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4282 16:31:02.825151 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4283 16:31:02.828727 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4284 16:31:02.831805 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4285 16:31:02.835361 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4286 16:31:02.838286 ==
4287 16:31:02.842041 Dram Type= 6, Freq= 0, CH_1, rank 0
4288 16:31:02.844930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4289 16:31:02.845007 ==
4290 16:31:02.845067 DQS Delay:
4291 16:31:02.848193 DQS0 = 0, DQS1 = 0
4292 16:31:02.848270 DQM Delay:
4293 16:31:02.851675 DQM0 = 38, DQM1 = 30
4294 16:31:02.851781 DQ Delay:
4295 16:31:02.855131 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4296 16:31:02.858176 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4297 16:31:02.861569 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4298 16:31:02.864987 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4299 16:31:02.865063
4300 16:31:02.865121
4301 16:31:02.865174 ==
4302 16:31:02.868227 Dram Type= 6, Freq= 0, CH_1, rank 0
4303 16:31:02.871693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4304 16:31:02.871770 ==
4305 16:31:02.871828
4306 16:31:02.871882
4307 16:31:02.875137 TX Vref Scan disable
4308 16:31:02.878141 == TX Byte 0 ==
4309 16:31:02.881244 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4310 16:31:02.884801 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4311 16:31:02.888083 == TX Byte 1 ==
4312 16:31:02.891493 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4313 16:31:02.894500 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4314 16:31:02.894578 ==
4315 16:31:02.898016 Dram Type= 6, Freq= 0, CH_1, rank 0
4316 16:31:02.904768 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4317 16:31:02.904845 ==
4318 16:31:02.904903
4319 16:31:02.904957
4320 16:31:02.905008 TX Vref Scan disable
4321 16:31:02.909466 == TX Byte 0 ==
4322 16:31:02.912064 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4323 16:31:02.918712 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4324 16:31:02.918788 == TX Byte 1 ==
4325 16:31:02.922063 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4326 16:31:02.928707 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4327 16:31:02.928783
4328 16:31:02.928842 [DATLAT]
4329 16:31:02.928896 Freq=600, CH1 RK0
4330 16:31:02.928949
4331 16:31:02.932195 DATLAT Default: 0x9
4332 16:31:02.932270 0, 0xFFFF, sum = 0
4333 16:31:02.935183 1, 0xFFFF, sum = 0
4334 16:31:02.938668 2, 0xFFFF, sum = 0
4335 16:31:02.938747 3, 0xFFFF, sum = 0
4336 16:31:02.942257 4, 0xFFFF, sum = 0
4337 16:31:02.942336 5, 0xFFFF, sum = 0
4338 16:31:02.945453 6, 0xFFFF, sum = 0
4339 16:31:02.945529 7, 0x0, sum = 1
4340 16:31:02.945588 8, 0x0, sum = 2
4341 16:31:02.948885 9, 0x0, sum = 3
4342 16:31:02.948961 10, 0x0, sum = 4
4343 16:31:02.951756 best_step = 8
4344 16:31:02.951841
4345 16:31:02.951904 ==
4346 16:31:02.955227 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 16:31:02.958457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4348 16:31:02.958534 ==
4349 16:31:02.961907 RX Vref Scan: 1
4350 16:31:02.961982
4351 16:31:02.962040 RX Vref 0 -> 0, step: 1
4352 16:31:02.962094
4353 16:31:02.965356 RX Delay -195 -> 252, step: 8
4354 16:31:02.965431
4355 16:31:02.968613 Set Vref, RX VrefLevel [Byte0]: 57
4356 16:31:02.971820 [Byte1]: 51
4357 16:31:02.976019
4358 16:31:02.976095 Final RX Vref Byte 0 = 57 to rank0
4359 16:31:02.979130 Final RX Vref Byte 1 = 51 to rank0
4360 16:31:02.982739 Final RX Vref Byte 0 = 57 to rank1
4361 16:31:02.986000 Final RX Vref Byte 1 = 51 to rank1==
4362 16:31:02.989112 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 16:31:02.995879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4364 16:31:02.995956 ==
4365 16:31:02.996014 DQS Delay:
4366 16:31:02.996067 DQS0 = 0, DQS1 = 0
4367 16:31:02.999094 DQM Delay:
4368 16:31:02.999170 DQM0 = 37, DQM1 = 30
4369 16:31:03.002203 DQ Delay:
4370 16:31:03.005706 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4371 16:31:03.009054 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4372 16:31:03.012733 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =24
4373 16:31:03.015707 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4374 16:31:03.015781
4375 16:31:03.015839
4376 16:31:03.022696 [DQSOSCAuto] RK0, (LSB)MR18= 0x7575, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4377 16:31:03.025480 CH1 RK0: MR19=808, MR18=7575
4378 16:31:03.032478 CH1_RK0: MR19=0x808, MR18=0x7575, DQSOSC=387, MR23=63, INC=175, DEC=116
4379 16:31:03.032631
4380 16:31:03.035828 ----->DramcWriteLeveling(PI) begin...
4381 16:31:03.035905 ==
4382 16:31:03.038784 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 16:31:03.042378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4384 16:31:03.042478 ==
4385 16:31:03.045772 Write leveling (Byte 0): 29 => 29
4386 16:31:03.049040 Write leveling (Byte 1): 30 => 30
4387 16:31:03.052452 DramcWriteLeveling(PI) end<-----
4388 16:31:03.052528
4389 16:31:03.052586 ==
4390 16:31:03.055505 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 16:31:03.059067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4392 16:31:03.059144 ==
4393 16:31:03.062492 [Gating] SW mode calibration
4394 16:31:03.068776 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4395 16:31:03.075591 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4396 16:31:03.079029 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4397 16:31:03.082127 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4398 16:31:03.088965 0 5 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4399 16:31:03.092205 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 16:31:03.095326 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 16:31:03.102437 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 16:31:03.105687 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 16:31:03.108825 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 16:31:03.115396 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 16:31:03.118698 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4406 16:31:03.122071 0 6 8 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4407 16:31:03.128326 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 16:31:03.132523 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 16:31:03.135330 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 16:31:03.141881 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 16:31:03.144916 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 16:31:03.148341 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 16:31:03.155070 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4414 16:31:03.158062 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4415 16:31:03.161474 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 16:31:03.168348 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 16:31:03.171312 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 16:31:03.174948 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 16:31:03.181210 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 16:31:03.184756 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 16:31:03.188021 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 16:31:03.194466 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 16:31:03.197835 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 16:31:03.201239 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 16:31:03.207799 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 16:31:03.211148 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 16:31:03.214511 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 16:31:03.221197 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 16:31:03.224179 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 16:31:03.227630 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4431 16:31:03.234375 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 16:31:03.234458 Total UI for P1: 0, mck2ui 16
4433 16:31:03.240723 best dqsien dly found for B0: ( 0, 9, 8)
4434 16:31:03.240802 Total UI for P1: 0, mck2ui 16
4435 16:31:03.247786 best dqsien dly found for B1: ( 0, 9, 8)
4436 16:31:03.250635 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4437 16:31:03.254203 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4438 16:31:03.254320
4439 16:31:03.257887 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4440 16:31:03.260594 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4441 16:31:03.264198 [Gating] SW calibration Done
4442 16:31:03.264276 ==
4443 16:31:03.267291 Dram Type= 6, Freq= 0, CH_1, rank 1
4444 16:31:03.270689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4445 16:31:03.270785 ==
4446 16:31:03.274026 RX Vref Scan: 0
4447 16:31:03.274092
4448 16:31:03.274148 RX Vref 0 -> 0, step: 1
4449 16:31:03.274201
4450 16:31:03.277231 RX Delay -230 -> 252, step: 16
4451 16:31:03.283907 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4452 16:31:03.287283 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4453 16:31:03.290737 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4454 16:31:03.294157 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4455 16:31:03.297039 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4456 16:31:03.303598 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4457 16:31:03.307054 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4458 16:31:03.310446 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4459 16:31:03.313705 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4460 16:31:03.320383 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4461 16:31:03.323559 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4462 16:31:03.326677 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4463 16:31:03.330415 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4464 16:31:03.336841 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4465 16:31:03.340409 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4466 16:31:03.343569 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4467 16:31:03.343647 ==
4468 16:31:03.346507 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 16:31:03.350028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4470 16:31:03.350107 ==
4471 16:31:03.353560 DQS Delay:
4472 16:31:03.353637 DQS0 = 0, DQS1 = 0
4473 16:31:03.356469 DQM Delay:
4474 16:31:03.356580 DQM0 = 40, DQM1 = 35
4475 16:31:03.360013 DQ Delay:
4476 16:31:03.360090 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4477 16:31:03.363081 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4478 16:31:03.366843 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4479 16:31:03.369855 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4480 16:31:03.369931
4481 16:31:03.373297
4482 16:31:03.373373 ==
4483 16:31:03.376058 Dram Type= 6, Freq= 0, CH_1, rank 1
4484 16:31:03.379496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4485 16:31:03.379574 ==
4486 16:31:03.379634
4487 16:31:03.379688
4488 16:31:03.383098 TX Vref Scan disable
4489 16:31:03.383176 == TX Byte 0 ==
4490 16:31:03.389560 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4491 16:31:03.392855 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4492 16:31:03.392932 == TX Byte 1 ==
4493 16:31:03.399630 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4494 16:31:03.402626 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4495 16:31:03.402705 ==
4496 16:31:03.406354 Dram Type= 6, Freq= 0, CH_1, rank 1
4497 16:31:03.409153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4498 16:31:03.409232 ==
4499 16:31:03.409331
4500 16:31:03.409385
4501 16:31:03.412638 TX Vref Scan disable
4502 16:31:03.416095 == TX Byte 0 ==
4503 16:31:03.419074 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4504 16:31:03.425640 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4505 16:31:03.425725 == TX Byte 1 ==
4506 16:31:03.429129 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4507 16:31:03.435551 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4508 16:31:03.435679
4509 16:31:03.435740 [DATLAT]
4510 16:31:03.435795 Freq=600, CH1 RK1
4511 16:31:03.435848
4512 16:31:03.439059 DATLAT Default: 0x8
4513 16:31:03.441992 0, 0xFFFF, sum = 0
4514 16:31:03.442104 1, 0xFFFF, sum = 0
4515 16:31:03.445617 2, 0xFFFF, sum = 0
4516 16:31:03.445720 3, 0xFFFF, sum = 0
4517 16:31:03.448943 4, 0xFFFF, sum = 0
4518 16:31:03.449022 5, 0xFFFF, sum = 0
4519 16:31:03.452094 6, 0xFFFF, sum = 0
4520 16:31:03.452173 7, 0x0, sum = 1
4521 16:31:03.455314 8, 0x0, sum = 2
4522 16:31:03.455392 9, 0x0, sum = 3
4523 16:31:03.455453 10, 0x0, sum = 4
4524 16:31:03.458880 best_step = 8
4525 16:31:03.458957
4526 16:31:03.459016 ==
4527 16:31:03.462260 Dram Type= 6, Freq= 0, CH_1, rank 1
4528 16:31:03.465599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4529 16:31:03.465701 ==
4530 16:31:03.469057 RX Vref Scan: 0
4531 16:31:03.469134
4532 16:31:03.469193 RX Vref 0 -> 0, step: 1
4533 16:31:03.469248
4534 16:31:03.471770 RX Delay -195 -> 252, step: 8
4535 16:31:03.479191 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4536 16:31:03.483036 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4537 16:31:03.486127 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4538 16:31:03.489584 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4539 16:31:03.496153 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4540 16:31:03.499385 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4541 16:31:03.502843 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4542 16:31:03.505784 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4543 16:31:03.512844 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4544 16:31:03.515754 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4545 16:31:03.519287 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4546 16:31:03.522162 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4547 16:31:03.525760 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4548 16:31:03.532434 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4549 16:31:03.535839 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4550 16:31:03.539257 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4551 16:31:03.539337 ==
4552 16:31:03.542588 Dram Type= 6, Freq= 0, CH_1, rank 1
4553 16:31:03.549003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4554 16:31:03.549084 ==
4555 16:31:03.549170 DQS Delay:
4556 16:31:03.549256 DQS0 = 0, DQS1 = 0
4557 16:31:03.552338 DQM Delay:
4558 16:31:03.552447 DQM0 = 37, DQM1 = 29
4559 16:31:03.555810 DQ Delay:
4560 16:31:03.558891 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4561 16:31:03.562517 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4562 16:31:03.565172 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4563 16:31:03.568739 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4564 16:31:03.568842
4565 16:31:03.568928
4566 16:31:03.575141 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4567 16:31:03.578685 CH1 RK1: MR19=808, MR18=5C5C
4568 16:31:03.585318 CH1_RK1: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4569 16:31:03.588725 [RxdqsGatingPostProcess] freq 600
4570 16:31:03.591993 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4571 16:31:03.595519 Pre-setting of DQS Precalculation
4572 16:31:03.601854 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4573 16:31:03.608385 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4574 16:31:03.614909 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4575 16:31:03.614989
4576 16:31:03.615049
4577 16:31:03.618416 [Calibration Summary] 1200 Mbps
4578 16:31:03.618494 CH 0, Rank 0
4579 16:31:03.621930 SW Impedance : PASS
4580 16:31:03.624818 DUTY Scan : NO K
4581 16:31:03.624897 ZQ Calibration : PASS
4582 16:31:03.628319 Jitter Meter : NO K
4583 16:31:03.631831 CBT Training : PASS
4584 16:31:03.631908 Write leveling : PASS
4585 16:31:03.634898 RX DQS gating : PASS
4586 16:31:03.638154 RX DQ/DQS(RDDQC) : PASS
4587 16:31:03.638289 TX DQ/DQS : PASS
4588 16:31:03.641546 RX DATLAT : PASS
4589 16:31:03.644897 RX DQ/DQS(Engine): PASS
4590 16:31:03.644974 TX OE : NO K
4591 16:31:03.645062 All Pass.
4592 16:31:03.648450
4593 16:31:03.648528 CH 0, Rank 1
4594 16:31:03.651435 SW Impedance : PASS
4595 16:31:03.651511 DUTY Scan : NO K
4596 16:31:03.654725 ZQ Calibration : PASS
4597 16:31:03.654805 Jitter Meter : NO K
4598 16:31:03.658406 CBT Training : PASS
4599 16:31:03.661691 Write leveling : PASS
4600 16:31:03.661770 RX DQS gating : PASS
4601 16:31:03.664724 RX DQ/DQS(RDDQC) : PASS
4602 16:31:03.668382 TX DQ/DQS : PASS
4603 16:31:03.668460 RX DATLAT : PASS
4604 16:31:03.671697 RX DQ/DQS(Engine): PASS
4605 16:31:03.674967 TX OE : NO K
4606 16:31:03.675045 All Pass.
4607 16:31:03.675105
4608 16:31:03.675161 CH 1, Rank 0
4609 16:31:03.678174 SW Impedance : PASS
4610 16:31:03.681482 DUTY Scan : NO K
4611 16:31:03.681559 ZQ Calibration : PASS
4612 16:31:03.684541 Jitter Meter : NO K
4613 16:31:03.688445 CBT Training : PASS
4614 16:31:03.688524 Write leveling : PASS
4615 16:31:03.691483 RX DQS gating : PASS
4616 16:31:03.694967 RX DQ/DQS(RDDQC) : PASS
4617 16:31:03.695045 TX DQ/DQS : PASS
4618 16:31:03.698014 RX DATLAT : PASS
4619 16:31:03.701380 RX DQ/DQS(Engine): PASS
4620 16:31:03.701458 TX OE : NO K
4621 16:31:03.701519 All Pass.
4622 16:31:03.701574
4623 16:31:03.704984 CH 1, Rank 1
4624 16:31:03.707971 SW Impedance : PASS
4625 16:31:03.708048 DUTY Scan : NO K
4626 16:31:03.711358 ZQ Calibration : PASS
4627 16:31:03.711437 Jitter Meter : NO K
4628 16:31:03.714791 CBT Training : PASS
4629 16:31:03.717913 Write leveling : PASS
4630 16:31:03.717991 RX DQS gating : PASS
4631 16:31:03.720931 RX DQ/DQS(RDDQC) : PASS
4632 16:31:03.724525 TX DQ/DQS : PASS
4633 16:31:03.724603 RX DATLAT : PASS
4634 16:31:03.728057 RX DQ/DQS(Engine): PASS
4635 16:31:03.730981 TX OE : NO K
4636 16:31:03.731059 All Pass.
4637 16:31:03.731120
4638 16:31:03.734604 DramC Write-DBI off
4639 16:31:03.734681 PER_BANK_REFRESH: Hybrid Mode
4640 16:31:03.737553 TX_TRACKING: ON
4641 16:31:03.744573 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4642 16:31:03.751083 [FAST_K] Save calibration result to emmc
4643 16:31:03.754034 dramc_set_vcore_voltage set vcore to 662500
4644 16:31:03.754111 Read voltage for 933, 3
4645 16:31:03.757645 Vio18 = 0
4646 16:31:03.757723 Vcore = 662500
4647 16:31:03.757782 Vdram = 0
4648 16:31:03.761407 Vddq = 0
4649 16:31:03.761485 Vmddr = 0
4650 16:31:03.764458 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4651 16:31:03.770872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4652 16:31:03.774088 MEM_TYPE=3, freq_sel=17
4653 16:31:03.777829 sv_algorithm_assistance_LP4_1600
4654 16:31:03.780963 ============ PULL DRAM RESETB DOWN ============
4655 16:31:03.784394 ========== PULL DRAM RESETB DOWN end =========
4656 16:31:03.791075 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4657 16:31:03.794171 ===================================
4658 16:31:03.794298 LPDDR4 DRAM CONFIGURATION
4659 16:31:03.797504 ===================================
4660 16:31:03.800871 EX_ROW_EN[0] = 0x0
4661 16:31:03.800949 EX_ROW_EN[1] = 0x0
4662 16:31:03.804364 LP4Y_EN = 0x0
4663 16:31:03.804442 WORK_FSP = 0x0
4664 16:31:03.807235 WL = 0x3
4665 16:31:03.807313 RL = 0x3
4666 16:31:03.811044 BL = 0x2
4667 16:31:03.813803 RPST = 0x0
4668 16:31:03.813880 RD_PRE = 0x0
4669 16:31:03.817038 WR_PRE = 0x1
4670 16:31:03.817116 WR_PST = 0x0
4671 16:31:03.820386 DBI_WR = 0x0
4672 16:31:03.820477 DBI_RD = 0x0
4673 16:31:03.824002 OTF = 0x1
4674 16:31:03.827465 ===================================
4675 16:31:03.830337 ===================================
4676 16:31:03.830418 ANA top config
4677 16:31:03.833984 ===================================
4678 16:31:03.837337 DLL_ASYNC_EN = 0
4679 16:31:03.840693 ALL_SLAVE_EN = 1
4680 16:31:03.840770 NEW_RANK_MODE = 1
4681 16:31:03.843514 DLL_IDLE_MODE = 1
4682 16:31:03.846914 LP45_APHY_COMB_EN = 1
4683 16:31:03.850505 TX_ODT_DIS = 1
4684 16:31:03.853312 NEW_8X_MODE = 1
4685 16:31:03.856893 ===================================
4686 16:31:03.860480 ===================================
4687 16:31:03.860558 data_rate = 1866
4688 16:31:03.863474 CKR = 1
4689 16:31:03.866962 DQ_P2S_RATIO = 8
4690 16:31:03.869919 ===================================
4691 16:31:03.873225 CA_P2S_RATIO = 8
4692 16:31:03.876680 DQ_CA_OPEN = 0
4693 16:31:03.880104 DQ_SEMI_OPEN = 0
4694 16:31:03.880182 CA_SEMI_OPEN = 0
4695 16:31:03.883273 CA_FULL_RATE = 0
4696 16:31:03.886971 DQ_CKDIV4_EN = 1
4697 16:31:03.889862 CA_CKDIV4_EN = 1
4698 16:31:03.893527 CA_PREDIV_EN = 0
4699 16:31:03.896790 PH8_DLY = 0
4700 16:31:03.896869 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4701 16:31:03.900067 DQ_AAMCK_DIV = 4
4702 16:31:03.903166 CA_AAMCK_DIV = 4
4703 16:31:03.906639 CA_ADMCK_DIV = 4
4704 16:31:03.909565 DQ_TRACK_CA_EN = 0
4705 16:31:03.913088 CA_PICK = 933
4706 16:31:03.916138 CA_MCKIO = 933
4707 16:31:03.916215 MCKIO_SEMI = 0
4708 16:31:03.919658 PLL_FREQ = 3732
4709 16:31:03.922863 DQ_UI_PI_RATIO = 32
4710 16:31:03.926185 CA_UI_PI_RATIO = 0
4711 16:31:03.929739 ===================================
4712 16:31:03.932561 ===================================
4713 16:31:03.936322 memory_type:LPDDR4
4714 16:31:03.936402 GP_NUM : 10
4715 16:31:03.939557 SRAM_EN : 1
4716 16:31:03.942561 MD32_EN : 0
4717 16:31:03.945964 ===================================
4718 16:31:03.946042 [ANA_INIT] >>>>>>>>>>>>>>
4719 16:31:03.949623 <<<<<< [CONFIGURE PHASE]: ANA_TX
4720 16:31:03.953128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4721 16:31:03.956150 ===================================
4722 16:31:03.959451 data_rate = 1866,PCW = 0X8f00
4723 16:31:03.962942 ===================================
4724 16:31:03.965882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4725 16:31:03.972663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4726 16:31:03.975911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4727 16:31:03.982953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4728 16:31:03.985749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4729 16:31:03.989239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4730 16:31:03.989318 [ANA_INIT] flow start
4731 16:31:03.992404 [ANA_INIT] PLL >>>>>>>>
4732 16:31:03.995854 [ANA_INIT] PLL <<<<<<<<
4733 16:31:03.995933 [ANA_INIT] MIDPI >>>>>>>>
4734 16:31:03.999230 [ANA_INIT] MIDPI <<<<<<<<
4735 16:31:04.002364 [ANA_INIT] DLL >>>>>>>>
4736 16:31:04.002441 [ANA_INIT] flow end
4737 16:31:04.008925 ============ LP4 DIFF to SE enter ============
4738 16:31:04.012773 ============ LP4 DIFF to SE exit ============
4739 16:31:04.016000 [ANA_INIT] <<<<<<<<<<<<<
4740 16:31:04.018962 [Flow] Enable top DCM control >>>>>
4741 16:31:04.022659 [Flow] Enable top DCM control <<<<<
4742 16:31:04.025434 Enable DLL master slave shuffle
4743 16:31:04.029097 ==============================================================
4744 16:31:04.032196 Gating Mode config
4745 16:31:04.035411 ==============================================================
4746 16:31:04.039125 Config description:
4747 16:31:04.048940 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4748 16:31:04.055254 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4749 16:31:04.058625 SELPH_MODE 0: By rank 1: By Phase
4750 16:31:04.065449 ==============================================================
4751 16:31:04.068484 GAT_TRACK_EN = 1
4752 16:31:04.072042 RX_GATING_MODE = 2
4753 16:31:04.075728 RX_GATING_TRACK_MODE = 2
4754 16:31:04.078692 SELPH_MODE = 1
4755 16:31:04.082067 PICG_EARLY_EN = 1
4756 16:31:04.082145 VALID_LAT_VALUE = 1
4757 16:31:04.088702 ==============================================================
4758 16:31:04.092226 Enter into Gating configuration >>>>
4759 16:31:04.095549 Exit from Gating configuration <<<<
4760 16:31:04.098781 Enter into DVFS_PRE_config >>>>>
4761 16:31:04.108559 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4762 16:31:04.112266 Exit from DVFS_PRE_config <<<<<
4763 16:31:04.115451 Enter into PICG configuration >>>>
4764 16:31:04.118737 Exit from PICG configuration <<<<
4765 16:31:04.121961 [RX_INPUT] configuration >>>>>
4766 16:31:04.125054 [RX_INPUT] configuration <<<<<
4767 16:31:04.128523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4768 16:31:04.134967 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4769 16:31:04.141499 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4770 16:31:04.148612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4771 16:31:04.155092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4772 16:31:04.161858 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4773 16:31:04.164541 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4774 16:31:04.168105 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4775 16:31:04.171395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4776 16:31:04.177816 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4777 16:31:04.181262 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4778 16:31:04.184669 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4779 16:31:04.188071 ===================================
4780 16:31:04.191529 LPDDR4 DRAM CONFIGURATION
4781 16:31:04.194398 ===================================
4782 16:31:04.194476 EX_ROW_EN[0] = 0x0
4783 16:31:04.198109 EX_ROW_EN[1] = 0x0
4784 16:31:04.201134 LP4Y_EN = 0x0
4785 16:31:04.201211 WORK_FSP = 0x0
4786 16:31:04.204671 WL = 0x3
4787 16:31:04.204748 RL = 0x3
4788 16:31:04.208028 BL = 0x2
4789 16:31:04.208106 RPST = 0x0
4790 16:31:04.210997 RD_PRE = 0x0
4791 16:31:04.211075 WR_PRE = 0x1
4792 16:31:04.214725 WR_PST = 0x0
4793 16:31:04.214804 DBI_WR = 0x0
4794 16:31:04.217448 DBI_RD = 0x0
4795 16:31:04.217526 OTF = 0x1
4796 16:31:04.221054 ===================================
4797 16:31:04.224069 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4798 16:31:04.230738 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4799 16:31:04.234121 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4800 16:31:04.237345 ===================================
4801 16:31:04.240727 LPDDR4 DRAM CONFIGURATION
4802 16:31:04.243784 ===================================
4803 16:31:04.243867 EX_ROW_EN[0] = 0x10
4804 16:31:04.247662 EX_ROW_EN[1] = 0x0
4805 16:31:04.250798 LP4Y_EN = 0x0
4806 16:31:04.250877 WORK_FSP = 0x0
4807 16:31:04.253927 WL = 0x3
4808 16:31:04.254004 RL = 0x3
4809 16:31:04.257258 BL = 0x2
4810 16:31:04.257336 RPST = 0x0
4811 16:31:04.260818 RD_PRE = 0x0
4812 16:31:04.260953 WR_PRE = 0x1
4813 16:31:04.264265 WR_PST = 0x0
4814 16:31:04.264356 DBI_WR = 0x0
4815 16:31:04.267105 DBI_RD = 0x0
4816 16:31:04.267305 OTF = 0x1
4817 16:31:04.270353 ===================================
4818 16:31:04.276927 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4819 16:31:04.281667 nWR fixed to 30
4820 16:31:04.284677 [ModeRegInit_LP4] CH0 RK0
4821 16:31:04.284754 [ModeRegInit_LP4] CH0 RK1
4822 16:31:04.288096 [ModeRegInit_LP4] CH1 RK0
4823 16:31:04.291212 [ModeRegInit_LP4] CH1 RK1
4824 16:31:04.291306 match AC timing 8
4825 16:31:04.297979 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4826 16:31:04.301729 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4827 16:31:04.304621 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4828 16:31:04.311489 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4829 16:31:04.314454 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4830 16:31:04.314534 ==
4831 16:31:04.318110 Dram Type= 6, Freq= 0, CH_0, rank 0
4832 16:31:04.321142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4833 16:31:04.321220 ==
4834 16:31:04.327911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4835 16:31:04.334273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4836 16:31:04.337638 [CA 0] Center 38 (8~69) winsize 62
4837 16:31:04.341186 [CA 1] Center 38 (8~69) winsize 62
4838 16:31:04.344359 [CA 2] Center 36 (6~67) winsize 62
4839 16:31:04.347541 [CA 3] Center 36 (6~66) winsize 61
4840 16:31:04.350940 [CA 4] Center 34 (4~65) winsize 62
4841 16:31:04.354675 [CA 5] Center 34 (4~65) winsize 62
4842 16:31:04.354754
4843 16:31:04.357281 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4844 16:31:04.357357
4845 16:31:04.360589 [CATrainingPosCal] consider 1 rank data
4846 16:31:04.364290 u2DelayCellTimex100 = 270/100 ps
4847 16:31:04.367600 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4848 16:31:04.370996 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4849 16:31:04.374284 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4850 16:31:04.377597 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4851 16:31:04.381069 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4852 16:31:04.387525 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4853 16:31:04.387604
4854 16:31:04.390516 CA PerBit enable=1, Macro0, CA PI delay=34
4855 16:31:04.390594
4856 16:31:04.394052 [CBTSetCACLKResult] CA Dly = 34
4857 16:31:04.394129 CS Dly: 7 (0~38)
4858 16:31:04.394188 ==
4859 16:31:04.397342 Dram Type= 6, Freq= 0, CH_0, rank 1
4860 16:31:04.400923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4861 16:31:04.403909 ==
4862 16:31:04.407500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4863 16:31:04.414251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4864 16:31:04.417293 [CA 0] Center 38 (8~69) winsize 62
4865 16:31:04.420765 [CA 1] Center 38 (8~69) winsize 62
4866 16:31:04.424210 [CA 2] Center 36 (6~67) winsize 62
4867 16:31:04.427055 [CA 3] Center 36 (6~66) winsize 61
4868 16:31:04.430801 [CA 4] Center 34 (4~64) winsize 61
4869 16:31:04.433917 [CA 5] Center 34 (4~65) winsize 62
4870 16:31:04.433996
4871 16:31:04.437489 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4872 16:31:04.437567
4873 16:31:04.440747 [CATrainingPosCal] consider 2 rank data
4874 16:31:04.443783 u2DelayCellTimex100 = 270/100 ps
4875 16:31:04.447216 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4876 16:31:04.450153 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4877 16:31:04.453520 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4878 16:31:04.460468 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4879 16:31:04.463510 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4880 16:31:04.467161 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4881 16:31:04.467239
4882 16:31:04.470448 CA PerBit enable=1, Macro0, CA PI delay=34
4883 16:31:04.470525
4884 16:31:04.473675 [CBTSetCACLKResult] CA Dly = 34
4885 16:31:04.473744 CS Dly: 7 (0~39)
4886 16:31:04.473801
4887 16:31:04.477042 ----->DramcWriteLeveling(PI) begin...
4888 16:31:04.477111 ==
4889 16:31:04.480373 Dram Type= 6, Freq= 0, CH_0, rank 0
4890 16:31:04.486762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4891 16:31:04.486842 ==
4892 16:31:04.490227 Write leveling (Byte 0): 29 => 29
4893 16:31:04.493941 Write leveling (Byte 1): 29 => 29
4894 16:31:04.494018 DramcWriteLeveling(PI) end<-----
4895 16:31:04.496686
4896 16:31:04.496762 ==
4897 16:31:04.500295 Dram Type= 6, Freq= 0, CH_0, rank 0
4898 16:31:04.503689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4899 16:31:04.503767 ==
4900 16:31:04.506821 [Gating] SW mode calibration
4901 16:31:04.513399 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4902 16:31:04.520114 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4903 16:31:04.522958 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4904 16:31:04.526515 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4905 16:31:04.530110 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4906 16:31:04.536420 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4907 16:31:04.539567 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 16:31:04.543139 0 10 20 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (0 0)
4909 16:31:04.550099 0 10 24 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (0 0)
4910 16:31:04.553298 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 16:31:04.556449 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4912 16:31:04.563128 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4913 16:31:04.566557 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 16:31:04.569557 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 16:31:04.576218 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 16:31:04.579424 0 11 20 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (1 1)
4917 16:31:04.582914 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4918 16:31:04.589575 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 16:31:04.592608 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 16:31:04.596082 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4921 16:31:04.602522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 16:31:04.605876 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 16:31:04.609225 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 16:31:04.615952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 16:31:04.619331 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4926 16:31:04.622392 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 16:31:04.629544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 16:31:04.632589 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 16:31:04.635672 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 16:31:04.642467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 16:31:04.645775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 16:31:04.648963 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 16:31:04.655529 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 16:31:04.659015 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 16:31:04.662436 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 16:31:04.668908 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 16:31:04.671908 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 16:31:04.675504 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 16:31:04.682154 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 16:31:04.685114 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4941 16:31:04.688531 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4942 16:31:04.694973 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4943 16:31:04.695052 Total UI for P1: 0, mck2ui 16
4944 16:31:04.701845 best dqsien dly found for B0: ( 0, 14, 22)
4945 16:31:04.701923 Total UI for P1: 0, mck2ui 16
4946 16:31:04.708081 best dqsien dly found for B1: ( 0, 14, 24)
4947 16:31:04.711557 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4948 16:31:04.715112 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
4949 16:31:04.715189
4950 16:31:04.718159 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4951 16:31:04.721540 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
4952 16:31:04.724912 [Gating] SW calibration Done
4953 16:31:04.724989 ==
4954 16:31:04.728373 Dram Type= 6, Freq= 0, CH_0, rank 0
4955 16:31:04.731728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4956 16:31:04.731806 ==
4957 16:31:04.734904 RX Vref Scan: 0
4958 16:31:04.734982
4959 16:31:04.735043 RX Vref 0 -> 0, step: 1
4960 16:31:04.735098
4961 16:31:04.738288 RX Delay -80 -> 252, step: 8
4962 16:31:04.745042 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4963 16:31:04.747832 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
4964 16:31:04.751462 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4965 16:31:04.754745 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4966 16:31:04.758156 iDelay=208, Bit 4, Center 95 (-8 ~ 199) 208
4967 16:31:04.761250 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4968 16:31:04.767726 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4969 16:31:04.771389 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4970 16:31:04.774345 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4971 16:31:04.777718 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4972 16:31:04.781415 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4973 16:31:04.787789 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4974 16:31:04.791153 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4975 16:31:04.794822 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4976 16:31:04.797833 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4977 16:31:04.801188 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4978 16:31:04.801265 ==
4979 16:31:04.804176 Dram Type= 6, Freq= 0, CH_0, rank 0
4980 16:31:04.810660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4981 16:31:04.810739 ==
4982 16:31:04.810800 DQS Delay:
4983 16:31:04.814190 DQS0 = 0, DQS1 = 0
4984 16:31:04.814316 DQM Delay:
4985 16:31:04.814378 DQM0 = 93, DQM1 = 85
4986 16:31:04.817556 DQ Delay:
4987 16:31:04.820811 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
4988 16:31:04.824406 DQ4 =95, DQ5 =83, DQ6 =103, DQ7 =103
4989 16:31:04.827303 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
4990 16:31:04.830848 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
4991 16:31:04.830931
4992 16:31:04.830993
4993 16:31:04.831048 ==
4994 16:31:04.833860 Dram Type= 6, Freq= 0, CH_0, rank 0
4995 16:31:04.837457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4996 16:31:04.837535 ==
4997 16:31:04.837595
4998 16:31:04.837650
4999 16:31:04.840498 TX Vref Scan disable
5000 16:31:04.843982 == TX Byte 0 ==
5001 16:31:04.847622 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5002 16:31:04.850715 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5003 16:31:04.854152 == TX Byte 1 ==
5004 16:31:04.857130 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5005 16:31:04.860693 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5006 16:31:04.860770 ==
5007 16:31:04.863739 Dram Type= 6, Freq= 0, CH_0, rank 0
5008 16:31:04.867261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5009 16:31:04.870550 ==
5010 16:31:04.870628
5011 16:31:04.870687
5012 16:31:04.870742 TX Vref Scan disable
5013 16:31:04.873733 == TX Byte 0 ==
5014 16:31:04.877517 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5015 16:31:04.883901 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5016 16:31:04.883984 == TX Byte 1 ==
5017 16:31:04.887475 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5018 16:31:04.893626 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5019 16:31:04.893706
5020 16:31:04.893766 [DATLAT]
5021 16:31:04.893822 Freq=933, CH0 RK0
5022 16:31:04.893876
5023 16:31:04.896948 DATLAT Default: 0xd
5024 16:31:04.897025 0, 0xFFFF, sum = 0
5025 16:31:04.900418 1, 0xFFFF, sum = 0
5026 16:31:04.903851 2, 0xFFFF, sum = 0
5027 16:31:04.903930 3, 0xFFFF, sum = 0
5028 16:31:04.907272 4, 0xFFFF, sum = 0
5029 16:31:04.907350 5, 0xFFFF, sum = 0
5030 16:31:04.910460 6, 0xFFFF, sum = 0
5031 16:31:04.910539 7, 0xFFFF, sum = 0
5032 16:31:04.914063 8, 0xFFFF, sum = 0
5033 16:31:04.914141 9, 0xFFFF, sum = 0
5034 16:31:04.917370 10, 0x0, sum = 1
5035 16:31:04.917449 11, 0x0, sum = 2
5036 16:31:04.920419 12, 0x0, sum = 3
5037 16:31:04.920497 13, 0x0, sum = 4
5038 16:31:04.920558 best_step = 11
5039 16:31:04.920613
5040 16:31:04.923735 ==
5041 16:31:04.923815 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 16:31:04.930451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5043 16:31:04.930555 ==
5044 16:31:04.930642 RX Vref Scan: 1
5045 16:31:04.930724
5046 16:31:04.933842 RX Vref 0 -> 0, step: 1
5047 16:31:04.933920
5048 16:31:04.936989 RX Delay -69 -> 252, step: 4
5049 16:31:04.937065
5050 16:31:04.940137 Set Vref, RX VrefLevel [Byte0]: 48
5051 16:31:04.943613 [Byte1]: 47
5052 16:31:04.943690
5053 16:31:04.947282 Final RX Vref Byte 0 = 48 to rank0
5054 16:31:04.950095 Final RX Vref Byte 1 = 47 to rank0
5055 16:31:04.953603 Final RX Vref Byte 0 = 48 to rank1
5056 16:31:04.957082 Final RX Vref Byte 1 = 47 to rank1==
5057 16:31:04.959941 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 16:31:04.963651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5059 16:31:04.966543 ==
5060 16:31:04.966638 DQS Delay:
5061 16:31:04.966700 DQS0 = 0, DQS1 = 0
5062 16:31:04.969901 DQM Delay:
5063 16:31:04.969978 DQM0 = 96, DQM1 = 86
5064 16:31:04.973262 DQ Delay:
5065 16:31:04.976985 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5066 16:31:04.980103 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5067 16:31:04.983450 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =80
5068 16:31:04.986608 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =98
5069 16:31:04.986687
5070 16:31:04.986747
5071 16:31:04.993483 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5072 16:31:04.996277 CH0 RK0: MR19=505, MR18=2121
5073 16:31:05.002988 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5074 16:31:05.003089
5075 16:31:05.006510 ----->DramcWriteLeveling(PI) begin...
5076 16:31:05.006607 ==
5077 16:31:05.009657 Dram Type= 6, Freq= 0, CH_0, rank 1
5078 16:31:05.013090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5079 16:31:05.013193 ==
5080 16:31:05.016450 Write leveling (Byte 0): 27 => 27
5081 16:31:05.019651 Write leveling (Byte 1): 27 => 27
5082 16:31:05.022961 DramcWriteLeveling(PI) end<-----
5083 16:31:05.023075
5084 16:31:05.023146 ==
5085 16:31:05.026605 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 16:31:05.029587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5087 16:31:05.029660 ==
5088 16:31:05.033044 [Gating] SW mode calibration
5089 16:31:05.039674 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 16:31:05.046320 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5091 16:31:05.049204 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 16:31:05.056217 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 16:31:05.059723 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 16:31:05.062703 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 16:31:05.069154 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5096 16:31:05.072543 0 10 20 | B1->B0 | 3333 3030 | 0 0 | (0 1) (1 1)
5097 16:31:05.076207 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
5098 16:31:05.082789 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 16:31:05.085507 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 16:31:05.089098 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 16:31:05.096046 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 16:31:05.099126 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 16:31:05.102476 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5104 16:31:05.108781 0 11 20 | B1->B0 | 3030 3434 | 0 0 | (1 1) (0 0)
5105 16:31:05.112330 0 11 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5106 16:31:05.115275 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 16:31:05.121962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 16:31:05.125342 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 16:31:05.128966 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 16:31:05.135573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 16:31:05.138494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 16:31:05.141816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5113 16:31:05.148700 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 16:31:05.151850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 16:31:05.155142 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 16:31:05.158717 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 16:31:05.165161 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 16:31:05.168608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 16:31:05.171744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 16:31:05.178221 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 16:31:05.181623 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 16:31:05.185019 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 16:31:05.191803 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 16:31:05.195159 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 16:31:05.198061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 16:31:05.204911 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 16:31:05.208443 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 16:31:05.211405 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5129 16:31:05.218356 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5130 16:31:05.221250 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 16:31:05.224772 Total UI for P1: 0, mck2ui 16
5132 16:31:05.228073 best dqsien dly found for B0: ( 0, 14, 22)
5133 16:31:05.231396 Total UI for P1: 0, mck2ui 16
5134 16:31:05.234414 best dqsien dly found for B1: ( 0, 14, 22)
5135 16:31:05.238032 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5136 16:31:05.241006 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5137 16:31:05.241083
5138 16:31:05.244409 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5139 16:31:05.251128 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5140 16:31:05.251208 [Gating] SW calibration Done
5141 16:31:05.251268 ==
5142 16:31:05.254319 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 16:31:05.260757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5144 16:31:05.260838 ==
5145 16:31:05.260898 RX Vref Scan: 0
5146 16:31:05.260954
5147 16:31:05.263764 RX Vref 0 -> 0, step: 1
5148 16:31:05.263843
5149 16:31:05.267805 RX Delay -80 -> 252, step: 8
5150 16:31:05.271088 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5151 16:31:05.273948 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5152 16:31:05.277626 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5153 16:31:05.284111 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5154 16:31:05.287161 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5155 16:31:05.290418 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5156 16:31:05.293789 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5157 16:31:05.297223 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5158 16:31:05.300277 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5159 16:31:05.307255 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5160 16:31:05.310504 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5161 16:31:05.313962 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5162 16:31:05.316891 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5163 16:31:05.320242 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5164 16:31:05.326794 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5165 16:31:05.330130 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5166 16:31:05.330267 ==
5167 16:31:05.333588 Dram Type= 6, Freq= 0, CH_0, rank 1
5168 16:31:05.337036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5169 16:31:05.337116 ==
5170 16:31:05.337182 DQS Delay:
5171 16:31:05.340031 DQS0 = 0, DQS1 = 0
5172 16:31:05.340110 DQM Delay:
5173 16:31:05.343570 DQM0 = 95, DQM1 = 87
5174 16:31:05.343647 DQ Delay:
5175 16:31:05.346970 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5176 16:31:05.349894 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5177 16:31:05.353193 DQ8 =75, DQ9 =71, DQ10 =91, DQ11 =79
5178 16:31:05.356830 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5179 16:31:05.356908
5180 16:31:05.356967
5181 16:31:05.357022 ==
5182 16:31:05.360150 Dram Type= 6, Freq= 0, CH_0, rank 1
5183 16:31:05.363406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5184 16:31:05.366625 ==
5185 16:31:05.366703
5186 16:31:05.366763
5187 16:31:05.366818 TX Vref Scan disable
5188 16:31:05.369777 == TX Byte 0 ==
5189 16:31:05.373371 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5190 16:31:05.376844 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5191 16:31:05.379805 == TX Byte 1 ==
5192 16:31:05.383399 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5193 16:31:05.386340 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5194 16:31:05.389792 ==
5195 16:31:05.392965 Dram Type= 6, Freq= 0, CH_0, rank 1
5196 16:31:05.396140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5197 16:31:05.396218 ==
5198 16:31:05.396278
5199 16:31:05.396333
5200 16:31:05.399444 TX Vref Scan disable
5201 16:31:05.399521 == TX Byte 0 ==
5202 16:31:05.406073 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5203 16:31:05.409231 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5204 16:31:05.409308 == TX Byte 1 ==
5205 16:31:05.416414 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5206 16:31:05.419374 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5207 16:31:05.419451
5208 16:31:05.419511 [DATLAT]
5209 16:31:05.422615 Freq=933, CH0 RK1
5210 16:31:05.422693
5211 16:31:05.422753 DATLAT Default: 0xb
5212 16:31:05.425914 0, 0xFFFF, sum = 0
5213 16:31:05.425994 1, 0xFFFF, sum = 0
5214 16:31:05.429554 2, 0xFFFF, sum = 0
5215 16:31:05.429634 3, 0xFFFF, sum = 0
5216 16:31:05.432841 4, 0xFFFF, sum = 0
5217 16:31:05.435866 5, 0xFFFF, sum = 0
5218 16:31:05.435946 6, 0xFFFF, sum = 0
5219 16:31:05.439012 7, 0xFFFF, sum = 0
5220 16:31:05.439090 8, 0xFFFF, sum = 0
5221 16:31:05.442446 9, 0xFFFF, sum = 0
5222 16:31:05.442525 10, 0x0, sum = 1
5223 16:31:05.446120 11, 0x0, sum = 2
5224 16:31:05.446198 12, 0x0, sum = 3
5225 16:31:05.446304 13, 0x0, sum = 4
5226 16:31:05.449070 best_step = 11
5227 16:31:05.449147
5228 16:31:05.449207 ==
5229 16:31:05.452553 Dram Type= 6, Freq= 0, CH_0, rank 1
5230 16:31:05.455985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5231 16:31:05.456063 ==
5232 16:31:05.458963 RX Vref Scan: 0
5233 16:31:05.459040
5234 16:31:05.462646 RX Vref 0 -> 0, step: 1
5235 16:31:05.462723
5236 16:31:05.462782 RX Delay -69 -> 252, step: 4
5237 16:31:05.469741 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5238 16:31:05.473248 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5239 16:31:05.476781 iDelay=199, Bit 2, Center 98 (7 ~ 190) 184
5240 16:31:05.480095 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5241 16:31:05.483179 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5242 16:31:05.486652 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5243 16:31:05.493499 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5244 16:31:05.496530 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5245 16:31:05.499954 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5246 16:31:05.503413 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5247 16:31:05.506484 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5248 16:31:05.513189 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5249 16:31:05.516429 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5250 16:31:05.520029 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5251 16:31:05.523203 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5252 16:31:05.526633 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5253 16:31:05.526714 ==
5254 16:31:05.529504 Dram Type= 6, Freq= 0, CH_0, rank 1
5255 16:31:05.536722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5256 16:31:05.536822 ==
5257 16:31:05.536911 DQS Delay:
5258 16:31:05.539521 DQS0 = 0, DQS1 = 0
5259 16:31:05.539591 DQM Delay:
5260 16:31:05.539650 DQM0 = 97, DQM1 = 86
5261 16:31:05.543096 DQ Delay:
5262 16:31:05.546568 DQ0 =94, DQ1 =98, DQ2 =98, DQ3 =92
5263 16:31:05.550022 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5264 16:31:05.552751 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =80
5265 16:31:05.556607 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =96
5266 16:31:05.556699
5267 16:31:05.556760
5268 16:31:05.563110 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5269 16:31:05.566510 CH0 RK1: MR19=505, MR18=2E2E
5270 16:31:05.572903 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5271 16:31:05.576268 [RxdqsGatingPostProcess] freq 933
5272 16:31:05.579922 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5273 16:31:05.582759 Pre-setting of DQS Precalculation
5274 16:31:05.589240 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5275 16:31:05.589319 ==
5276 16:31:05.592663 Dram Type= 6, Freq= 0, CH_1, rank 0
5277 16:31:05.596331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5278 16:31:05.596409 ==
5279 16:31:05.602686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5280 16:31:05.609198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5281 16:31:05.612567 [CA 0] Center 37 (7~68) winsize 62
5282 16:31:05.615921 [CA 1] Center 37 (7~68) winsize 62
5283 16:31:05.619574 [CA 2] Center 34 (4~65) winsize 62
5284 16:31:05.622759 [CA 3] Center 34 (4~65) winsize 62
5285 16:31:05.625755 [CA 4] Center 33 (2~64) winsize 63
5286 16:31:05.629068 [CA 5] Center 33 (2~64) winsize 63
5287 16:31:05.629146
5288 16:31:05.632657 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5289 16:31:05.632735
5290 16:31:05.635642 [CATrainingPosCal] consider 1 rank data
5291 16:31:05.639422 u2DelayCellTimex100 = 270/100 ps
5292 16:31:05.642345 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5293 16:31:05.645554 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5294 16:31:05.649081 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5295 16:31:05.652415 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5296 16:31:05.655811 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5297 16:31:05.659205 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5298 16:31:05.659282
5299 16:31:05.665881 CA PerBit enable=1, Macro0, CA PI delay=33
5300 16:31:05.665960
5301 16:31:05.666020 [CBTSetCACLKResult] CA Dly = 33
5302 16:31:05.668695 CS Dly: 5 (0~36)
5303 16:31:05.668771 ==
5304 16:31:05.672145 Dram Type= 6, Freq= 0, CH_1, rank 1
5305 16:31:05.675749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5306 16:31:05.675821 ==
5307 16:31:05.681933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5308 16:31:05.688677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5309 16:31:05.691927 [CA 0] Center 37 (6~68) winsize 63
5310 16:31:05.695404 [CA 1] Center 37 (6~68) winsize 63
5311 16:31:05.698452 [CA 2] Center 34 (4~65) winsize 62
5312 16:31:05.701935 [CA 3] Center 34 (4~64) winsize 61
5313 16:31:05.704844 [CA 4] Center 33 (3~64) winsize 62
5314 16:31:05.708245 [CA 5] Center 33 (2~64) winsize 63
5315 16:31:05.708313
5316 16:31:05.711831 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5317 16:31:05.711900
5318 16:31:05.715101 [CATrainingPosCal] consider 2 rank data
5319 16:31:05.718353 u2DelayCellTimex100 = 270/100 ps
5320 16:31:05.721592 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5321 16:31:05.724699 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5322 16:31:05.728116 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5323 16:31:05.731597 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5324 16:31:05.735052 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5325 16:31:05.741638 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5326 16:31:05.741716
5327 16:31:05.744851 CA PerBit enable=1, Macro0, CA PI delay=33
5328 16:31:05.744928
5329 16:31:05.748226 [CBTSetCACLKResult] CA Dly = 33
5330 16:31:05.748302 CS Dly: 5 (0~37)
5331 16:31:05.748362
5332 16:31:05.751185 ----->DramcWriteLeveling(PI) begin...
5333 16:31:05.751263 ==
5334 16:31:05.754802 Dram Type= 6, Freq= 0, CH_1, rank 0
5335 16:31:05.761366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5336 16:31:05.761445 ==
5337 16:31:05.764442 Write leveling (Byte 0): 25 => 25
5338 16:31:05.764521 Write leveling (Byte 1): 25 => 25
5339 16:31:05.767970 DramcWriteLeveling(PI) end<-----
5340 16:31:05.768047
5341 16:31:05.771838 ==
5342 16:31:05.771915 Dram Type= 6, Freq= 0, CH_1, rank 0
5343 16:31:05.778042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5344 16:31:05.778120 ==
5345 16:31:05.780991 [Gating] SW mode calibration
5346 16:31:05.787827 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 16:31:05.791301 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5348 16:31:05.798013 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 16:31:05.800917 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 16:31:05.804478 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 16:31:05.811135 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5352 16:31:05.814501 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5353 16:31:05.818041 0 10 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5354 16:31:05.824373 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5355 16:31:05.827679 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 16:31:05.830983 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 16:31:05.837501 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 16:31:05.840821 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 16:31:05.844369 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 16:31:05.850948 0 11 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
5361 16:31:05.854123 0 11 20 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
5362 16:31:05.857301 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5363 16:31:05.864377 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 16:31:05.867263 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 16:31:05.870554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 16:31:05.877147 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 16:31:05.880717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 16:31:05.883597 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5369 16:31:05.890508 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5370 16:31:05.893972 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 16:31:05.896956 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 16:31:05.903642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 16:31:05.907084 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 16:31:05.910112 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 16:31:05.916993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 16:31:05.919992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 16:31:05.923566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 16:31:05.930001 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 16:31:05.933388 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 16:31:05.936581 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 16:31:05.940414 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 16:31:05.946799 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 16:31:05.949871 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 16:31:05.953278 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5385 16:31:05.959899 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5386 16:31:05.963165 Total UI for P1: 0, mck2ui 16
5387 16:31:05.966876 best dqsien dly found for B0: ( 0, 14, 16)
5388 16:31:05.970274 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 16:31:05.973523 Total UI for P1: 0, mck2ui 16
5390 16:31:05.976717 best dqsien dly found for B1: ( 0, 14, 18)
5391 16:31:05.979789 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5392 16:31:05.983388 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5393 16:31:05.983466
5394 16:31:05.986685 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5395 16:31:05.990088 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5396 16:31:05.993512 [Gating] SW calibration Done
5397 16:31:05.993589 ==
5398 16:31:05.996220 Dram Type= 6, Freq= 0, CH_1, rank 0
5399 16:31:06.002805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5400 16:31:06.002884 ==
5401 16:31:06.002944 RX Vref Scan: 0
5402 16:31:06.002999
5403 16:31:06.006226 RX Vref 0 -> 0, step: 1
5404 16:31:06.006303
5405 16:31:06.009663 RX Delay -80 -> 252, step: 8
5406 16:31:06.013036 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5407 16:31:06.016624 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5408 16:31:06.019583 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5409 16:31:06.022938 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5410 16:31:06.029381 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5411 16:31:06.033027 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5412 16:31:06.035930 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5413 16:31:06.039494 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5414 16:31:06.042994 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5415 16:31:06.049370 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5416 16:31:06.052636 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5417 16:31:06.056159 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5418 16:31:06.059141 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5419 16:31:06.062613 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5420 16:31:06.066111 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5421 16:31:06.072969 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5422 16:31:06.073051 ==
5423 16:31:06.075827 Dram Type= 6, Freq= 0, CH_1, rank 0
5424 16:31:06.079460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5425 16:31:06.079538 ==
5426 16:31:06.079598 DQS Delay:
5427 16:31:06.082682 DQS0 = 0, DQS1 = 0
5428 16:31:06.082759 DQM Delay:
5429 16:31:06.086016 DQM0 = 95, DQM1 = 88
5430 16:31:06.086092 DQ Delay:
5431 16:31:06.089144 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5432 16:31:06.092416 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5433 16:31:06.095975 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5434 16:31:06.099352 DQ12 =99, DQ13 =103, DQ14 =95, DQ15 =95
5435 16:31:06.099456
5436 16:31:06.099544
5437 16:31:06.099626 ==
5438 16:31:06.102466 Dram Type= 6, Freq= 0, CH_1, rank 0
5439 16:31:06.108897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5440 16:31:06.109004 ==
5441 16:31:06.109093
5442 16:31:06.109178
5443 16:31:06.109263 TX Vref Scan disable
5444 16:31:06.112317 == TX Byte 0 ==
5445 16:31:06.116076 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5446 16:31:06.119360 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5447 16:31:06.122794 == TX Byte 1 ==
5448 16:31:06.125764 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5449 16:31:06.129163 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5450 16:31:06.132623 ==
5451 16:31:06.135596 Dram Type= 6, Freq= 0, CH_1, rank 0
5452 16:31:06.139211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5453 16:31:06.139289 ==
5454 16:31:06.139349
5455 16:31:06.139403
5456 16:31:06.142456 TX Vref Scan disable
5457 16:31:06.142533 == TX Byte 0 ==
5458 16:31:06.148951 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5459 16:31:06.152634 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5460 16:31:06.152711 == TX Byte 1 ==
5461 16:31:06.158786 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5462 16:31:06.162119 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5463 16:31:06.162198
5464 16:31:06.162296 [DATLAT]
5465 16:31:06.165568 Freq=933, CH1 RK0
5466 16:31:06.165645
5467 16:31:06.165704 DATLAT Default: 0xd
5468 16:31:06.168991 0, 0xFFFF, sum = 0
5469 16:31:06.169069 1, 0xFFFF, sum = 0
5470 16:31:06.171963 2, 0xFFFF, sum = 0
5471 16:31:06.172042 3, 0xFFFF, sum = 0
5472 16:31:06.175251 4, 0xFFFF, sum = 0
5473 16:31:06.178651 5, 0xFFFF, sum = 0
5474 16:31:06.178728 6, 0xFFFF, sum = 0
5475 16:31:06.181807 7, 0xFFFF, sum = 0
5476 16:31:06.181902 8, 0xFFFF, sum = 0
5477 16:31:06.185021 9, 0xFFFF, sum = 0
5478 16:31:06.185090 10, 0x0, sum = 1
5479 16:31:06.188648 11, 0x0, sum = 2
5480 16:31:06.188717 12, 0x0, sum = 3
5481 16:31:06.188775 13, 0x0, sum = 4
5482 16:31:06.191582 best_step = 11
5483 16:31:06.191649
5484 16:31:06.191708 ==
5485 16:31:06.195411 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 16:31:06.198590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5487 16:31:06.198666 ==
5488 16:31:06.201754 RX Vref Scan: 1
5489 16:31:06.201830
5490 16:31:06.204866 RX Vref 0 -> 0, step: 1
5491 16:31:06.204941
5492 16:31:06.204999 RX Delay -69 -> 252, step: 4
5493 16:31:06.205053
5494 16:31:06.208232 Set Vref, RX VrefLevel [Byte0]: 57
5495 16:31:06.211533 [Byte1]: 51
5496 16:31:06.216514
5497 16:31:06.216589 Final RX Vref Byte 0 = 57 to rank0
5498 16:31:06.219602 Final RX Vref Byte 1 = 51 to rank0
5499 16:31:06.223189 Final RX Vref Byte 0 = 57 to rank1
5500 16:31:06.226044 Final RX Vref Byte 1 = 51 to rank1==
5501 16:31:06.229618 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 16:31:06.235949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5503 16:31:06.236027 ==
5504 16:31:06.236086 DQS Delay:
5505 16:31:06.236142 DQS0 = 0, DQS1 = 0
5506 16:31:06.239476 DQM Delay:
5507 16:31:06.239551 DQM0 = 94, DQM1 = 88
5508 16:31:06.242946 DQ Delay:
5509 16:31:06.245922 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5510 16:31:06.249394 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5511 16:31:06.252376 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5512 16:31:06.256375 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5513 16:31:06.256450
5514 16:31:06.256510
5515 16:31:06.262442 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5516 16:31:06.266112 CH1 RK0: MR19=505, MR18=3939
5517 16:31:06.272741 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5518 16:31:06.272818
5519 16:31:06.276159 ----->DramcWriteLeveling(PI) begin...
5520 16:31:06.276236 ==
5521 16:31:06.279013 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 16:31:06.282409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5523 16:31:06.282486 ==
5524 16:31:06.285626 Write leveling (Byte 0): 25 => 25
5525 16:31:06.288976 Write leveling (Byte 1): 25 => 25
5526 16:31:06.292313 DramcWriteLeveling(PI) end<-----
5527 16:31:06.292389
5528 16:31:06.292447 ==
5529 16:31:06.295765 Dram Type= 6, Freq= 0, CH_1, rank 1
5530 16:31:06.299408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5531 16:31:06.299485 ==
5532 16:31:06.302480 [Gating] SW mode calibration
5533 16:31:06.308905 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5534 16:31:06.315380 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5535 16:31:06.318894 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5536 16:31:06.325401 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5537 16:31:06.328882 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5538 16:31:06.332225 0 10 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5539 16:31:06.338835 0 10 16 | B1->B0 | 3434 2323 | 0 0 | (1 0) (0 0)
5540 16:31:06.342249 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5541 16:31:06.345189 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5542 16:31:06.352105 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 16:31:06.355152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 16:31:06.358540 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 16:31:06.365506 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 16:31:06.368425 0 11 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5547 16:31:06.371749 0 11 16 | B1->B0 | 2424 3a3a | 0 1 | (0 0) (0 0)
5548 16:31:06.378413 0 11 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5549 16:31:06.381777 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 16:31:06.385338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 16:31:06.392043 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 16:31:06.395219 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 16:31:06.398381 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 16:31:06.402026 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 16:31:06.408418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5556 16:31:06.411794 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5557 16:31:06.414796 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 16:31:06.421360 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 16:31:06.424992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 16:31:06.428045 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 16:31:06.434919 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 16:31:06.438259 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 16:31:06.441581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 16:31:06.447823 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 16:31:06.451504 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 16:31:06.454467 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 16:31:06.460863 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 16:31:06.464581 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 16:31:06.471308 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 16:31:06.474094 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 16:31:06.477550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5572 16:31:06.480886 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 16:31:06.484303 Total UI for P1: 0, mck2ui 16
5574 16:31:06.487803 best dqsien dly found for B0: ( 0, 14, 16)
5575 16:31:06.490626 Total UI for P1: 0, mck2ui 16
5576 16:31:06.494421 best dqsien dly found for B1: ( 0, 14, 16)
5577 16:31:06.497462 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5578 16:31:06.503721 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5579 16:31:06.503799
5580 16:31:06.507499 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5581 16:31:06.510536 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5582 16:31:06.514054 [Gating] SW calibration Done
5583 16:31:06.514126 ==
5584 16:31:06.516990 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 16:31:06.520537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5586 16:31:06.520614 ==
5587 16:31:06.524574 RX Vref Scan: 0
5588 16:31:06.524651
5589 16:31:06.524710 RX Vref 0 -> 0, step: 1
5590 16:31:06.524765
5591 16:31:06.527244 RX Delay -80 -> 252, step: 8
5592 16:31:06.530872 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5593 16:31:06.533567 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5594 16:31:06.540531 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5595 16:31:06.544165 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5596 16:31:06.546855 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5597 16:31:06.550191 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5598 16:31:06.553749 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5599 16:31:06.556955 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5600 16:31:06.563909 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5601 16:31:06.566788 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5602 16:31:06.570229 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5603 16:31:06.573581 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5604 16:31:06.576622 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5605 16:31:06.583340 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5606 16:31:06.586854 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5607 16:31:06.589836 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5608 16:31:06.589917 ==
5609 16:31:06.593333 Dram Type= 6, Freq= 0, CH_1, rank 1
5610 16:31:06.596766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5611 16:31:06.596844 ==
5612 16:31:06.600174 DQS Delay:
5613 16:31:06.600250 DQS0 = 0, DQS1 = 0
5614 16:31:06.600309 DQM Delay:
5615 16:31:06.603330 DQM0 = 97, DQM1 = 88
5616 16:31:06.603420 DQ Delay:
5617 16:31:06.606777 DQ0 =99, DQ1 =95, DQ2 =91, DQ3 =95
5618 16:31:06.610075 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5619 16:31:06.613153 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5620 16:31:06.616740 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5621 16:31:06.616812
5622 16:31:06.616874
5623 16:31:06.616933 ==
5624 16:31:06.619959 Dram Type= 6, Freq= 0, CH_1, rank 1
5625 16:31:06.626183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5626 16:31:06.626300 ==
5627 16:31:06.626404
5628 16:31:06.626511
5629 16:31:06.626583 TX Vref Scan disable
5630 16:31:06.630453 == TX Byte 0 ==
5631 16:31:06.633821 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5632 16:31:06.640281 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5633 16:31:06.640360 == TX Byte 1 ==
5634 16:31:06.643616 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5635 16:31:06.650011 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5636 16:31:06.650090 ==
5637 16:31:06.653474 Dram Type= 6, Freq= 0, CH_1, rank 1
5638 16:31:06.656978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5639 16:31:06.657054 ==
5640 16:31:06.657113
5641 16:31:06.657167
5642 16:31:06.659833 TX Vref Scan disable
5643 16:31:06.659909 == TX Byte 0 ==
5644 16:31:06.666467 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5645 16:31:06.669817 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5646 16:31:06.669894 == TX Byte 1 ==
5647 16:31:06.677011 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5648 16:31:06.680122 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5649 16:31:06.680222
5650 16:31:06.680308 [DATLAT]
5651 16:31:06.683430 Freq=933, CH1 RK1
5652 16:31:06.683511
5653 16:31:06.683571 DATLAT Default: 0xb
5654 16:31:06.686179 0, 0xFFFF, sum = 0
5655 16:31:06.686302 1, 0xFFFF, sum = 0
5656 16:31:06.689662 2, 0xFFFF, sum = 0
5657 16:31:06.692908 3, 0xFFFF, sum = 0
5658 16:31:06.693010 4, 0xFFFF, sum = 0
5659 16:31:06.696605 5, 0xFFFF, sum = 0
5660 16:31:06.696683 6, 0xFFFF, sum = 0
5661 16:31:06.699514 7, 0xFFFF, sum = 0
5662 16:31:06.699592 8, 0xFFFF, sum = 0
5663 16:31:06.702759 9, 0xFFFF, sum = 0
5664 16:31:06.702836 10, 0x0, sum = 1
5665 16:31:06.706187 11, 0x0, sum = 2
5666 16:31:06.706306 12, 0x0, sum = 3
5667 16:31:06.709956 13, 0x0, sum = 4
5668 16:31:06.710034 best_step = 11
5669 16:31:06.710093
5670 16:31:06.710148 ==
5671 16:31:06.712980 Dram Type= 6, Freq= 0, CH_1, rank 1
5672 16:31:06.716397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5673 16:31:06.716474 ==
5674 16:31:06.719324 RX Vref Scan: 0
5675 16:31:06.719412
5676 16:31:06.722798 RX Vref 0 -> 0, step: 1
5677 16:31:06.722873
5678 16:31:06.722932 RX Delay -69 -> 252, step: 4
5679 16:31:06.730491 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5680 16:31:06.733860 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5681 16:31:06.737351 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5682 16:31:06.740489 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5683 16:31:06.743892 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5684 16:31:06.747165 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5685 16:31:06.753832 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5686 16:31:06.756944 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5687 16:31:06.760781 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5688 16:31:06.764073 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5689 16:31:06.767020 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5690 16:31:06.773958 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5691 16:31:06.777258 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5692 16:31:06.780276 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5693 16:31:06.783689 iDelay=203, Bit 14, Center 96 (-1 ~ 194) 196
5694 16:31:06.787103 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5695 16:31:06.790356 ==
5696 16:31:06.790432 Dram Type= 6, Freq= 0, CH_1, rank 1
5697 16:31:06.796805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5698 16:31:06.796882 ==
5699 16:31:06.796942 DQS Delay:
5700 16:31:06.800300 DQS0 = 0, DQS1 = 0
5701 16:31:06.800375 DQM Delay:
5702 16:31:06.803283 DQM0 = 96, DQM1 = 87
5703 16:31:06.803358 DQ Delay:
5704 16:31:06.806648 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5705 16:31:06.809934 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5706 16:31:06.813174 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5707 16:31:06.816595 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5708 16:31:06.816671
5709 16:31:06.816729
5710 16:31:06.823571 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5711 16:31:06.826538 CH1 RK1: MR19=505, MR18=2424
5712 16:31:06.833133 CH1_RK1: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5713 16:31:06.836670 [RxdqsGatingPostProcess] freq 933
5714 16:31:06.843188 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5715 16:31:06.843265 Pre-setting of DQS Precalculation
5716 16:31:06.849617 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5717 16:31:06.856471 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5718 16:31:06.863145 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5719 16:31:06.863222
5720 16:31:06.863280
5721 16:31:06.866142 [Calibration Summary] 1866 Mbps
5722 16:31:06.869394 CH 0, Rank 0
5723 16:31:06.869460 SW Impedance : PASS
5724 16:31:06.873022 DUTY Scan : NO K
5725 16:31:06.876096 ZQ Calibration : PASS
5726 16:31:06.876164 Jitter Meter : NO K
5727 16:31:06.879333 CBT Training : PASS
5728 16:31:06.883024 Write leveling : PASS
5729 16:31:06.883100 RX DQS gating : PASS
5730 16:31:06.886231 RX DQ/DQS(RDDQC) : PASS
5731 16:31:06.889764 TX DQ/DQS : PASS
5732 16:31:06.889842 RX DATLAT : PASS
5733 16:31:06.892533 RX DQ/DQS(Engine): PASS
5734 16:31:06.892608 TX OE : NO K
5735 16:31:06.895951 All Pass.
5736 16:31:06.896026
5737 16:31:06.896084 CH 0, Rank 1
5738 16:31:06.899330 SW Impedance : PASS
5739 16:31:06.899406 DUTY Scan : NO K
5740 16:31:06.902814 ZQ Calibration : PASS
5741 16:31:06.906053 Jitter Meter : NO K
5742 16:31:06.906128 CBT Training : PASS
5743 16:31:06.909553 Write leveling : PASS
5744 16:31:06.912399 RX DQS gating : PASS
5745 16:31:06.912475 RX DQ/DQS(RDDQC) : PASS
5746 16:31:06.915886 TX DQ/DQS : PASS
5747 16:31:06.919528 RX DATLAT : PASS
5748 16:31:06.919627 RX DQ/DQS(Engine): PASS
5749 16:31:06.922697 TX OE : NO K
5750 16:31:06.922795 All Pass.
5751 16:31:06.922887
5752 16:31:06.926120 CH 1, Rank 0
5753 16:31:06.926196 SW Impedance : PASS
5754 16:31:06.929159 DUTY Scan : NO K
5755 16:31:06.932703 ZQ Calibration : PASS
5756 16:31:06.932780 Jitter Meter : NO K
5757 16:31:06.936167 CBT Training : PASS
5758 16:31:06.939199 Write leveling : PASS
5759 16:31:06.939275 RX DQS gating : PASS
5760 16:31:06.942556 RX DQ/DQS(RDDQC) : PASS
5761 16:31:06.942632 TX DQ/DQS : PASS
5762 16:31:06.946143 RX DATLAT : PASS
5763 16:31:06.949127 RX DQ/DQS(Engine): PASS
5764 16:31:06.949203 TX OE : NO K
5765 16:31:06.952610 All Pass.
5766 16:31:06.952686
5767 16:31:06.952745 CH 1, Rank 1
5768 16:31:06.955493 SW Impedance : PASS
5769 16:31:06.955569 DUTY Scan : NO K
5770 16:31:06.958973 ZQ Calibration : PASS
5771 16:31:06.962517 Jitter Meter : NO K
5772 16:31:06.962594 CBT Training : PASS
5773 16:31:06.965522 Write leveling : PASS
5774 16:31:06.968954 RX DQS gating : PASS
5775 16:31:06.969030 RX DQ/DQS(RDDQC) : PASS
5776 16:31:06.972507 TX DQ/DQS : PASS
5777 16:31:06.975831 RX DATLAT : PASS
5778 16:31:06.975908 RX DQ/DQS(Engine): PASS
5779 16:31:06.978982 TX OE : NO K
5780 16:31:06.979057 All Pass.
5781 16:31:06.979117
5782 16:31:06.982033 DramC Write-DBI off
5783 16:31:06.985379 PER_BANK_REFRESH: Hybrid Mode
5784 16:31:06.985454 TX_TRACKING: ON
5785 16:31:06.995578 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5786 16:31:06.998943 [FAST_K] Save calibration result to emmc
5787 16:31:07.002421 dramc_set_vcore_voltage set vcore to 650000
5788 16:31:07.005468 Read voltage for 400, 6
5789 16:31:07.005545 Vio18 = 0
5790 16:31:07.005604 Vcore = 650000
5791 16:31:07.008673 Vdram = 0
5792 16:31:07.008750 Vddq = 0
5793 16:31:07.008809 Vmddr = 0
5794 16:31:07.015458 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5795 16:31:07.018822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5796 16:31:07.021906 MEM_TYPE=3, freq_sel=20
5797 16:31:07.025226 sv_algorithm_assistance_LP4_800
5798 16:31:07.028541 ============ PULL DRAM RESETB DOWN ============
5799 16:31:07.031860 ========== PULL DRAM RESETB DOWN end =========
5800 16:31:07.038555 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5801 16:31:07.041902 ===================================
5802 16:31:07.044871 LPDDR4 DRAM CONFIGURATION
5803 16:31:07.048649 ===================================
5804 16:31:07.048726 EX_ROW_EN[0] = 0x0
5805 16:31:07.051559 EX_ROW_EN[1] = 0x0
5806 16:31:07.051635 LP4Y_EN = 0x0
5807 16:31:07.055014 WORK_FSP = 0x0
5808 16:31:07.055091 WL = 0x2
5809 16:31:07.058097 RL = 0x2
5810 16:31:07.058173 BL = 0x2
5811 16:31:07.061642 RPST = 0x0
5812 16:31:07.061718 RD_PRE = 0x0
5813 16:31:07.065071 WR_PRE = 0x1
5814 16:31:07.065148 WR_PST = 0x0
5815 16:31:07.068105 DBI_WR = 0x0
5816 16:31:07.071586 DBI_RD = 0x0
5817 16:31:07.071663 OTF = 0x1
5818 16:31:07.075136 ===================================
5819 16:31:07.078072 ===================================
5820 16:31:07.078149 ANA top config
5821 16:31:07.081688 ===================================
5822 16:31:07.084573 DLL_ASYNC_EN = 0
5823 16:31:07.087982 ALL_SLAVE_EN = 1
5824 16:31:07.091200 NEW_RANK_MODE = 1
5825 16:31:07.094483 DLL_IDLE_MODE = 1
5826 16:31:07.094594 LP45_APHY_COMB_EN = 1
5827 16:31:07.098197 TX_ODT_DIS = 1
5828 16:31:07.101092 NEW_8X_MODE = 1
5829 16:31:07.104678 ===================================
5830 16:31:07.107811 ===================================
5831 16:31:07.111105 data_rate = 800
5832 16:31:07.114626 CKR = 1
5833 16:31:07.114702 DQ_P2S_RATIO = 4
5834 16:31:07.117854 ===================================
5835 16:31:07.121008 CA_P2S_RATIO = 4
5836 16:31:07.124201 DQ_CA_OPEN = 0
5837 16:31:07.128151 DQ_SEMI_OPEN = 1
5838 16:31:07.131142 CA_SEMI_OPEN = 1
5839 16:31:07.134431 CA_FULL_RATE = 0
5840 16:31:07.134508 DQ_CKDIV4_EN = 0
5841 16:31:07.137946 CA_CKDIV4_EN = 1
5842 16:31:07.141005 CA_PREDIV_EN = 0
5843 16:31:07.144600 PH8_DLY = 0
5844 16:31:07.147676 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5845 16:31:07.151134 DQ_AAMCK_DIV = 0
5846 16:31:07.151212 CA_AAMCK_DIV = 0
5847 16:31:07.154052 CA_ADMCK_DIV = 4
5848 16:31:07.157515 DQ_TRACK_CA_EN = 0
5849 16:31:07.161012 CA_PICK = 800
5850 16:31:07.164652 CA_MCKIO = 400
5851 16:31:07.167921 MCKIO_SEMI = 400
5852 16:31:07.170879 PLL_FREQ = 3016
5853 16:31:07.170956 DQ_UI_PI_RATIO = 32
5854 16:31:07.174259 CA_UI_PI_RATIO = 32
5855 16:31:07.177869 ===================================
5856 16:31:07.181245 ===================================
5857 16:31:07.184127 memory_type:LPDDR4
5858 16:31:07.187697 GP_NUM : 10
5859 16:31:07.187774 SRAM_EN : 1
5860 16:31:07.191000 MD32_EN : 0
5861 16:31:07.194149 ===================================
5862 16:31:07.197565 [ANA_INIT] >>>>>>>>>>>>>>
5863 16:31:07.197641 <<<<<< [CONFIGURE PHASE]: ANA_TX
5864 16:31:07.201215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5865 16:31:07.204293 ===================================
5866 16:31:07.207989 data_rate = 800,PCW = 0X7400
5867 16:31:07.210701 ===================================
5868 16:31:07.214050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5869 16:31:07.220926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5870 16:31:07.230588 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5871 16:31:07.237009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5872 16:31:07.240498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5873 16:31:07.243868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5874 16:31:07.247133 [ANA_INIT] flow start
5875 16:31:07.247211 [ANA_INIT] PLL >>>>>>>>
5876 16:31:07.250339 [ANA_INIT] PLL <<<<<<<<
5877 16:31:07.253530 [ANA_INIT] MIDPI >>>>>>>>
5878 16:31:07.253606 [ANA_INIT] MIDPI <<<<<<<<
5879 16:31:07.257048 [ANA_INIT] DLL >>>>>>>>
5880 16:31:07.260578 [ANA_INIT] flow end
5881 16:31:07.263705 ============ LP4 DIFF to SE enter ============
5882 16:31:07.267040 ============ LP4 DIFF to SE exit ============
5883 16:31:07.269937 [ANA_INIT] <<<<<<<<<<<<<
5884 16:31:07.273468 [Flow] Enable top DCM control >>>>>
5885 16:31:07.277026 [Flow] Enable top DCM control <<<<<
5886 16:31:07.279939 Enable DLL master slave shuffle
5887 16:31:07.283562 ==============================================================
5888 16:31:07.287000 Gating Mode config
5889 16:31:07.293592 ==============================================================
5890 16:31:07.293668 Config description:
5891 16:31:07.303160 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5892 16:31:07.309832 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5893 16:31:07.313234 SELPH_MODE 0: By rank 1: By Phase
5894 16:31:07.319692 ==============================================================
5895 16:31:07.323014 GAT_TRACK_EN = 0
5896 16:31:07.326541 RX_GATING_MODE = 2
5897 16:31:07.329520 RX_GATING_TRACK_MODE = 2
5898 16:31:07.332831 SELPH_MODE = 1
5899 16:31:07.336336 PICG_EARLY_EN = 1
5900 16:31:07.339858 VALID_LAT_VALUE = 1
5901 16:31:07.343022 ==============================================================
5902 16:31:07.345922 Enter into Gating configuration >>>>
5903 16:31:07.349227 Exit from Gating configuration <<<<
5904 16:31:07.352766 Enter into DVFS_PRE_config >>>>>
5905 16:31:07.366074 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5906 16:31:07.369305 Exit from DVFS_PRE_config <<<<<
5907 16:31:07.372924 Enter into PICG configuration >>>>
5908 16:31:07.373002 Exit from PICG configuration <<<<
5909 16:31:07.376309 [RX_INPUT] configuration >>>>>
5910 16:31:07.379049 [RX_INPUT] configuration <<<<<
5911 16:31:07.386117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5912 16:31:07.389010 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5913 16:31:07.396171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5914 16:31:07.402207 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5915 16:31:07.408930 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5916 16:31:07.415986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5917 16:31:07.419386 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5918 16:31:07.422140 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5919 16:31:07.425790 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5920 16:31:07.432386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5921 16:31:07.435828 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5922 16:31:07.438648 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5923 16:31:07.441937 ===================================
5924 16:31:07.445460 LPDDR4 DRAM CONFIGURATION
5925 16:31:07.448895 ===================================
5926 16:31:07.452332 EX_ROW_EN[0] = 0x0
5927 16:31:07.452410 EX_ROW_EN[1] = 0x0
5928 16:31:07.455642 LP4Y_EN = 0x0
5929 16:31:07.455720 WORK_FSP = 0x0
5930 16:31:07.458936 WL = 0x2
5931 16:31:07.459013 RL = 0x2
5932 16:31:07.462164 BL = 0x2
5933 16:31:07.462289 RPST = 0x0
5934 16:31:07.465616 RD_PRE = 0x0
5935 16:31:07.465692 WR_PRE = 0x1
5936 16:31:07.468656 WR_PST = 0x0
5937 16:31:07.468733 DBI_WR = 0x0
5938 16:31:07.472047 DBI_RD = 0x0
5939 16:31:07.472123 OTF = 0x1
5940 16:31:07.475495 ===================================
5941 16:31:07.482176 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5942 16:31:07.485346 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5943 16:31:07.488394 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5944 16:31:07.491800 ===================================
5945 16:31:07.495264 LPDDR4 DRAM CONFIGURATION
5946 16:31:07.498154 ===================================
5947 16:31:07.501947 EX_ROW_EN[0] = 0x10
5948 16:31:07.502024 EX_ROW_EN[1] = 0x0
5949 16:31:07.504832 LP4Y_EN = 0x0
5950 16:31:07.504908 WORK_FSP = 0x0
5951 16:31:07.508306 WL = 0x2
5952 16:31:07.508383 RL = 0x2
5953 16:31:07.511661 BL = 0x2
5954 16:31:07.511745 RPST = 0x0
5955 16:31:07.515135 RD_PRE = 0x0
5956 16:31:07.515220 WR_PRE = 0x1
5957 16:31:07.518064 WR_PST = 0x0
5958 16:31:07.518164 DBI_WR = 0x0
5959 16:31:07.521655 DBI_RD = 0x0
5960 16:31:07.521731 OTF = 0x1
5961 16:31:07.524940 ===================================
5962 16:31:07.531502 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5963 16:31:07.536064 nWR fixed to 30
5964 16:31:07.539530 [ModeRegInit_LP4] CH0 RK0
5965 16:31:07.539607 [ModeRegInit_LP4] CH0 RK1
5966 16:31:07.542919 [ModeRegInit_LP4] CH1 RK0
5967 16:31:07.546383 [ModeRegInit_LP4] CH1 RK1
5968 16:31:07.546460 match AC timing 18
5969 16:31:07.552840 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5970 16:31:07.556128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5971 16:31:07.559492 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5972 16:31:07.566134 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5973 16:31:07.569649 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5974 16:31:07.569725 ==
5975 16:31:07.572618 Dram Type= 6, Freq= 0, CH_0, rank 0
5976 16:31:07.576033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5977 16:31:07.576122 ==
5978 16:31:07.582813 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5979 16:31:07.589383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5980 16:31:07.592485 [CA 0] Center 36 (8~64) winsize 57
5981 16:31:07.596024 [CA 1] Center 36 (8~64) winsize 57
5982 16:31:07.599049 [CA 2] Center 36 (8~64) winsize 57
5983 16:31:07.602470 [CA 3] Center 36 (8~64) winsize 57
5984 16:31:07.602541 [CA 4] Center 36 (8~64) winsize 57
5985 16:31:07.605839 [CA 5] Center 36 (8~64) winsize 57
5986 16:31:07.605915
5987 16:31:07.612563 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5988 16:31:07.612638
5989 16:31:07.615983 [CATrainingPosCal] consider 1 rank data
5990 16:31:07.618833 u2DelayCellTimex100 = 270/100 ps
5991 16:31:07.622386 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 16:31:07.625331 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 16:31:07.628885 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5994 16:31:07.632028 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5995 16:31:07.635357 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 16:31:07.638745 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 16:31:07.638827
5998 16:31:07.642060 CA PerBit enable=1, Macro0, CA PI delay=36
5999 16:31:07.642136
6000 16:31:07.645557 [CBTSetCACLKResult] CA Dly = 36
6001 16:31:07.648994 CS Dly: 1 (0~32)
6002 16:31:07.649064 ==
6003 16:31:07.652376 Dram Type= 6, Freq= 0, CH_0, rank 1
6004 16:31:07.655849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6005 16:31:07.655927 ==
6006 16:31:07.661962 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6007 16:31:07.668739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6008 16:31:07.668814 [CA 0] Center 36 (8~64) winsize 57
6009 16:31:07.672074 [CA 1] Center 36 (8~64) winsize 57
6010 16:31:07.675613 [CA 2] Center 36 (8~64) winsize 57
6011 16:31:07.678447 [CA 3] Center 36 (8~64) winsize 57
6012 16:31:07.681817 [CA 4] Center 36 (8~64) winsize 57
6013 16:31:07.685660 [CA 5] Center 36 (8~64) winsize 57
6014 16:31:07.685730
6015 16:31:07.688785 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6016 16:31:07.688851
6017 16:31:07.691762 [CATrainingPosCal] consider 2 rank data
6018 16:31:07.695237 u2DelayCellTimex100 = 270/100 ps
6019 16:31:07.698737 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 16:31:07.705178 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 16:31:07.708234 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 16:31:07.711796 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 16:31:07.715379 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 16:31:07.718180 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 16:31:07.718271
6026 16:31:07.721568 CA PerBit enable=1, Macro0, CA PI delay=36
6027 16:31:07.721643
6028 16:31:07.724935 [CBTSetCACLKResult] CA Dly = 36
6029 16:31:07.725002 CS Dly: 1 (0~32)
6030 16:31:07.728494
6031 16:31:07.731472 ----->DramcWriteLeveling(PI) begin...
6032 16:31:07.731547 ==
6033 16:31:07.734917 Dram Type= 6, Freq= 0, CH_0, rank 0
6034 16:31:07.738446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6035 16:31:07.738516 ==
6036 16:31:07.741648 Write leveling (Byte 0): 32 => 0
6037 16:31:07.744857 Write leveling (Byte 1): 32 => 0
6038 16:31:07.748430 DramcWriteLeveling(PI) end<-----
6039 16:31:07.748507
6040 16:31:07.748565 ==
6041 16:31:07.751553 Dram Type= 6, Freq= 0, CH_0, rank 0
6042 16:31:07.755128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6043 16:31:07.755199 ==
6044 16:31:07.757930 [Gating] SW mode calibration
6045 16:31:07.764659 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6046 16:31:07.771176 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6047 16:31:07.774528 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6048 16:31:07.778066 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6049 16:31:07.784469 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6050 16:31:07.787784 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6051 16:31:07.791165 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6052 16:31:07.798032 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6053 16:31:07.801142 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6054 16:31:07.804305 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6055 16:31:07.811229 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6056 16:31:07.811301 Total UI for P1: 0, mck2ui 16
6057 16:31:07.814415 best dqsien dly found for B0: ( 0, 10, 16)
6058 16:31:07.817703 Total UI for P1: 0, mck2ui 16
6059 16:31:07.821081 best dqsien dly found for B1: ( 0, 10, 24)
6060 16:31:07.824231 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6061 16:31:07.831257 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6062 16:31:07.831338
6063 16:31:07.834097 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6064 16:31:07.837541 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6065 16:31:07.841084 [Gating] SW calibration Done
6066 16:31:07.841156 ==
6067 16:31:07.844034 Dram Type= 6, Freq= 0, CH_0, rank 0
6068 16:31:07.847575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6069 16:31:07.847649 ==
6070 16:31:07.850946 RX Vref Scan: 0
6071 16:31:07.851016
6072 16:31:07.851081 RX Vref 0 -> 0, step: 1
6073 16:31:07.851138
6074 16:31:07.854033 RX Delay -410 -> 252, step: 16
6075 16:31:07.861059 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6076 16:31:07.864271 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6077 16:31:07.867494 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6078 16:31:07.870439 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6079 16:31:07.877374 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6080 16:31:07.880735 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6081 16:31:07.884183 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6082 16:31:07.887182 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6083 16:31:07.893853 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6084 16:31:07.897215 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6085 16:31:07.900515 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6086 16:31:07.903891 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6087 16:31:07.910676 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6088 16:31:07.914022 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6089 16:31:07.916899 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6090 16:31:07.920398 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6091 16:31:07.923794 ==
6092 16:31:07.926756 Dram Type= 6, Freq= 0, CH_0, rank 0
6093 16:31:07.930198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6094 16:31:07.930316 ==
6095 16:31:07.930377 DQS Delay:
6096 16:31:07.933681 DQS0 = 43, DQS1 = 59
6097 16:31:07.933758 DQM Delay:
6098 16:31:07.936604 DQM0 = 5, DQM1 = 15
6099 16:31:07.936682 DQ Delay:
6100 16:31:07.940178 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6101 16:31:07.943647 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6102 16:31:07.946560 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6103 16:31:07.949938 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6104 16:31:07.950016
6105 16:31:07.950098
6106 16:31:07.950154 ==
6107 16:31:07.953474 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 16:31:07.956942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 16:31:07.957020 ==
6110 16:31:07.957080
6111 16:31:07.957135
6112 16:31:07.959897 TX Vref Scan disable
6113 16:31:07.959973 == TX Byte 0 ==
6114 16:31:07.966521 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6115 16:31:07.970112 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6116 16:31:07.970207 == TX Byte 1 ==
6117 16:31:07.976439 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6118 16:31:07.979945 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6119 16:31:07.980059 ==
6120 16:31:07.982921 Dram Type= 6, Freq= 0, CH_0, rank 0
6121 16:31:07.986243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6122 16:31:07.986334 ==
6123 16:31:07.986393
6124 16:31:07.986448
6125 16:31:07.989601 TX Vref Scan disable
6126 16:31:07.993050 == TX Byte 0 ==
6127 16:31:07.996528 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6128 16:31:07.999346 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6129 16:31:08.002927 == TX Byte 1 ==
6130 16:31:08.006443 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6131 16:31:08.009222 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6132 16:31:08.009299
6133 16:31:08.009359 [DATLAT]
6134 16:31:08.012752 Freq=400, CH0 RK0
6135 16:31:08.012829
6136 16:31:08.015993 DATLAT Default: 0xf
6137 16:31:08.016069 0, 0xFFFF, sum = 0
6138 16:31:08.019444 1, 0xFFFF, sum = 0
6139 16:31:08.019523 2, 0xFFFF, sum = 0
6140 16:31:08.022692 3, 0xFFFF, sum = 0
6141 16:31:08.022785 4, 0xFFFF, sum = 0
6142 16:31:08.026073 5, 0xFFFF, sum = 0
6143 16:31:08.026151 6, 0xFFFF, sum = 0
6144 16:31:08.029288 7, 0xFFFF, sum = 0
6145 16:31:08.029387 8, 0xFFFF, sum = 0
6146 16:31:08.032732 9, 0xFFFF, sum = 0
6147 16:31:08.032814 10, 0xFFFF, sum = 0
6148 16:31:08.035625 11, 0xFFFF, sum = 0
6149 16:31:08.035706 12, 0x0, sum = 1
6150 16:31:08.039303 13, 0x0, sum = 2
6151 16:31:08.039385 14, 0x0, sum = 3
6152 16:31:08.042811 15, 0x0, sum = 4
6153 16:31:08.042892 best_step = 13
6154 16:31:08.042971
6155 16:31:08.043045 ==
6156 16:31:08.045668 Dram Type= 6, Freq= 0, CH_0, rank 0
6157 16:31:08.052326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6158 16:31:08.052412 ==
6159 16:31:08.052491 RX Vref Scan: 1
6160 16:31:08.052565
6161 16:31:08.055869 RX Vref 0 -> 0, step: 1
6162 16:31:08.055948
6163 16:31:08.059359 RX Delay -359 -> 252, step: 8
6164 16:31:08.059445
6165 16:31:08.062411 Set Vref, RX VrefLevel [Byte0]: 48
6166 16:31:08.065439 [Byte1]: 47
6167 16:31:08.065519
6168 16:31:08.068825 Final RX Vref Byte 0 = 48 to rank0
6169 16:31:08.072168 Final RX Vref Byte 1 = 47 to rank0
6170 16:31:08.075604 Final RX Vref Byte 0 = 48 to rank1
6171 16:31:08.078866 Final RX Vref Byte 1 = 47 to rank1==
6172 16:31:08.082154 Dram Type= 6, Freq= 0, CH_0, rank 0
6173 16:31:08.085579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6174 16:31:08.088977 ==
6175 16:31:08.089057 DQS Delay:
6176 16:31:08.089135 DQS0 = 52, DQS1 = 68
6177 16:31:08.092093 DQM Delay:
6178 16:31:08.092207 DQM0 = 9, DQM1 = 17
6179 16:31:08.095285 DQ Delay:
6180 16:31:08.095385 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6181 16:31:08.098824 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6182 16:31:08.101904 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6183 16:31:08.105150 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6184 16:31:08.105227
6185 16:31:08.105287
6186 16:31:08.115521 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6187 16:31:08.118347 CH0 RK0: MR19=C0C, MR18=A0A0
6188 16:31:08.125119 CH0_RK0: MR19=0xC0C, MR18=0xA0A0, DQSOSC=389, MR23=63, INC=390, DEC=260
6189 16:31:08.125216 ==
6190 16:31:08.128495 Dram Type= 6, Freq= 0, CH_0, rank 1
6191 16:31:08.131952 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6192 16:31:08.132031 ==
6193 16:31:08.135034 [Gating] SW mode calibration
6194 16:31:08.141978 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6195 16:31:08.144872 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6196 16:31:08.151498 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6197 16:31:08.155038 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6198 16:31:08.157916 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6199 16:31:08.165009 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6200 16:31:08.167917 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6201 16:31:08.171227 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6202 16:31:08.178413 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6203 16:31:08.181261 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6204 16:31:08.184751 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6205 16:31:08.188036 Total UI for P1: 0, mck2ui 16
6206 16:31:08.191523 best dqsien dly found for B0: ( 0, 10, 16)
6207 16:31:08.194639 Total UI for P1: 0, mck2ui 16
6208 16:31:08.198181 best dqsien dly found for B1: ( 0, 10, 24)
6209 16:31:08.201731 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6210 16:31:08.204483 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6211 16:31:08.204561
6212 16:31:08.211223 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6213 16:31:08.214544 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6214 16:31:08.217617 [Gating] SW calibration Done
6215 16:31:08.217694 ==
6216 16:31:08.220944 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 16:31:08.224080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6218 16:31:08.224158 ==
6219 16:31:08.227790 RX Vref Scan: 0
6220 16:31:08.227870
6221 16:31:08.227944 RX Vref 0 -> 0, step: 1
6222 16:31:08.227999
6223 16:31:08.230797 RX Delay -410 -> 252, step: 16
6224 16:31:08.234079 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6225 16:31:08.240711 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6226 16:31:08.244100 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6227 16:31:08.247602 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6228 16:31:08.250716 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6229 16:31:08.257754 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6230 16:31:08.260754 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6231 16:31:08.264246 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6232 16:31:08.267767 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6233 16:31:08.274421 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6234 16:31:08.277256 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6235 16:31:08.280784 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6236 16:31:08.284240 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6237 16:31:08.290378 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6238 16:31:08.294072 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6239 16:31:08.297150 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6240 16:31:08.297229 ==
6241 16:31:08.300822 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 16:31:08.307274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6243 16:31:08.307356 ==
6244 16:31:08.307416 DQS Delay:
6245 16:31:08.310617 DQS0 = 51, DQS1 = 59
6246 16:31:08.310694 DQM Delay:
6247 16:31:08.310753 DQM0 = 13, DQM1 = 15
6248 16:31:08.314206 DQ Delay:
6249 16:31:08.317017 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6250 16:31:08.320434 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6251 16:31:08.320511 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6252 16:31:08.324022 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6253 16:31:08.327379
6254 16:31:08.327455
6255 16:31:08.327514 ==
6256 16:31:08.330753 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 16:31:08.333814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6258 16:31:08.333893 ==
6259 16:31:08.333984
6260 16:31:08.334093
6261 16:31:08.337098 TX Vref Scan disable
6262 16:31:08.337176 == TX Byte 0 ==
6263 16:31:08.340354 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6264 16:31:08.346757 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6265 16:31:08.346838 == TX Byte 1 ==
6266 16:31:08.350327 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6267 16:31:08.357499 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6268 16:31:08.357582 ==
6269 16:31:08.360314 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 16:31:08.363888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6271 16:31:08.363967 ==
6272 16:31:08.364027
6273 16:31:08.364083
6274 16:31:08.367463 TX Vref Scan disable
6275 16:31:08.367541 == TX Byte 0 ==
6276 16:31:08.370406 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6277 16:31:08.377144 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6278 16:31:08.377240 == TX Byte 1 ==
6279 16:31:08.380688 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6280 16:31:08.386724 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6281 16:31:08.386797
6282 16:31:08.386859 [DATLAT]
6283 16:31:08.386922 Freq=400, CH0 RK1
6284 16:31:08.386975
6285 16:31:08.390026 DATLAT Default: 0xd
6286 16:31:08.393657 0, 0xFFFF, sum = 0
6287 16:31:08.393763 1, 0xFFFF, sum = 0
6288 16:31:08.396566 2, 0xFFFF, sum = 0
6289 16:31:08.396662 3, 0xFFFF, sum = 0
6290 16:31:08.400128 4, 0xFFFF, sum = 0
6291 16:31:08.400227 5, 0xFFFF, sum = 0
6292 16:31:08.403806 6, 0xFFFF, sum = 0
6293 16:31:08.403876 7, 0xFFFF, sum = 0
6294 16:31:08.406442 8, 0xFFFF, sum = 0
6295 16:31:08.406539 9, 0xFFFF, sum = 0
6296 16:31:08.410542 10, 0xFFFF, sum = 0
6297 16:31:08.410632 11, 0xFFFF, sum = 0
6298 16:31:08.413194 12, 0x0, sum = 1
6299 16:31:08.413270 13, 0x0, sum = 2
6300 16:31:08.416850 14, 0x0, sum = 3
6301 16:31:08.416946 15, 0x0, sum = 4
6302 16:31:08.419948 best_step = 13
6303 16:31:08.420055
6304 16:31:08.420145 ==
6305 16:31:08.423375 Dram Type= 6, Freq= 0, CH_0, rank 1
6306 16:31:08.426236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6307 16:31:08.426345 ==
6308 16:31:08.429701 RX Vref Scan: 0
6309 16:31:08.429790
6310 16:31:08.429884 RX Vref 0 -> 0, step: 1
6311 16:31:08.429996
6312 16:31:08.433201 RX Delay -359 -> 252, step: 8
6313 16:31:08.440913 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6314 16:31:08.444391 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6315 16:31:08.447862 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6316 16:31:08.454061 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6317 16:31:08.457498 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6318 16:31:08.460902 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6319 16:31:08.464169 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6320 16:31:08.467315 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6321 16:31:08.474366 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6322 16:31:08.477329 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6323 16:31:08.480584 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6324 16:31:08.487064 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6325 16:31:08.490572 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6326 16:31:08.493940 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6327 16:31:08.496923 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6328 16:31:08.504131 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6329 16:31:08.504201 ==
6330 16:31:08.506993 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 16:31:08.510556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 16:31:08.510644 ==
6333 16:31:08.510733 DQS Delay:
6334 16:31:08.513481 DQS0 = 52, DQS1 = 64
6335 16:31:08.513572 DQM Delay:
6336 16:31:08.516896 DQM0 = 10, DQM1 = 13
6337 16:31:08.516971 DQ Delay:
6338 16:31:08.520250 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6339 16:31:08.523423 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6340 16:31:08.527070 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6341 16:31:08.529906 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6342 16:31:08.530006
6343 16:31:08.530097
6344 16:31:08.536983 [DQSOSCAuto] RK1, (LSB)MR18= 0xc2c2, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6345 16:31:08.539795 CH0 RK1: MR19=C0C, MR18=C2C2
6346 16:31:08.546692 CH0_RK1: MR19=0xC0C, MR18=0xC2C2, DQSOSC=385, MR23=63, INC=398, DEC=265
6347 16:31:08.550074 [RxdqsGatingPostProcess] freq 400
6348 16:31:08.556513 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6349 16:31:08.560015 Pre-setting of DQS Precalculation
6350 16:31:08.563046 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6351 16:31:08.563123 ==
6352 16:31:08.566703 Dram Type= 6, Freq= 0, CH_1, rank 0
6353 16:31:08.569836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6354 16:31:08.572926 ==
6355 16:31:08.576193 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6356 16:31:08.583006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6357 16:31:08.586410 [CA 0] Center 36 (8~64) winsize 57
6358 16:31:08.589406 [CA 1] Center 36 (8~64) winsize 57
6359 16:31:08.592987 [CA 2] Center 36 (8~64) winsize 57
6360 16:31:08.596313 [CA 3] Center 36 (8~64) winsize 57
6361 16:31:08.599630 [CA 4] Center 36 (8~64) winsize 57
6362 16:31:08.602689 [CA 5] Center 36 (8~64) winsize 57
6363 16:31:08.602771
6364 16:31:08.606129 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6365 16:31:08.606218
6366 16:31:08.609627 [CATrainingPosCal] consider 1 rank data
6367 16:31:08.612696 u2DelayCellTimex100 = 270/100 ps
6368 16:31:08.616278 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 16:31:08.619889 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 16:31:08.623126 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 16:31:08.625995 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 16:31:08.629409 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 16:31:08.632727 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 16:31:08.632806
6375 16:31:08.639116 CA PerBit enable=1, Macro0, CA PI delay=36
6376 16:31:08.639196
6377 16:31:08.639256 [CBTSetCACLKResult] CA Dly = 36
6378 16:31:08.642417 CS Dly: 1 (0~32)
6379 16:31:08.642494 ==
6380 16:31:08.645794 Dram Type= 6, Freq= 0, CH_1, rank 1
6381 16:31:08.649362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6382 16:31:08.649464 ==
6383 16:31:08.655653 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6384 16:31:08.662545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6385 16:31:08.665720 [CA 0] Center 36 (8~64) winsize 57
6386 16:31:08.669274 [CA 1] Center 36 (8~64) winsize 57
6387 16:31:08.672218 [CA 2] Center 36 (8~64) winsize 57
6388 16:31:08.672394 [CA 3] Center 36 (8~64) winsize 57
6389 16:31:08.675728 [CA 4] Center 36 (8~64) winsize 57
6390 16:31:08.679055 [CA 5] Center 36 (8~64) winsize 57
6391 16:31:08.679134
6392 16:31:08.685725 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6393 16:31:08.685805
6394 16:31:08.689121 [CATrainingPosCal] consider 2 rank data
6395 16:31:08.692345 u2DelayCellTimex100 = 270/100 ps
6396 16:31:08.695187 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 16:31:08.698898 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 16:31:08.702324 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 16:31:08.705726 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 16:31:08.708758 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 16:31:08.712109 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 16:31:08.712187
6403 16:31:08.715449 CA PerBit enable=1, Macro0, CA PI delay=36
6404 16:31:08.715527
6405 16:31:08.718585 [CBTSetCACLKResult] CA Dly = 36
6406 16:31:08.721882 CS Dly: 1 (0~32)
6407 16:31:08.721985
6408 16:31:08.725280 ----->DramcWriteLeveling(PI) begin...
6409 16:31:08.725359 ==
6410 16:31:08.728518 Dram Type= 6, Freq= 0, CH_1, rank 0
6411 16:31:08.732134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6412 16:31:08.732214 ==
6413 16:31:08.735017 Write leveling (Byte 0): 32 => 0
6414 16:31:08.738519 Write leveling (Byte 1): 32 => 0
6415 16:31:08.741880 DramcWriteLeveling(PI) end<-----
6416 16:31:08.741975
6417 16:31:08.742059 ==
6418 16:31:08.745167 Dram Type= 6, Freq= 0, CH_1, rank 0
6419 16:31:08.748893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6420 16:31:08.748994 ==
6421 16:31:08.751850 [Gating] SW mode calibration
6422 16:31:08.758770 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 16:31:08.765109 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6424 16:31:08.768865 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 16:31:08.771708 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 16:31:08.778823 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 16:31:08.781632 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6428 16:31:08.784911 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 16:31:08.791612 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 16:31:08.795073 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 16:31:08.798582 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6432 16:31:08.805206 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 16:31:08.805286 Total UI for P1: 0, mck2ui 16
6434 16:31:08.811775 best dqsien dly found for B0: ( 0, 10, 16)
6435 16:31:08.811854 Total UI for P1: 0, mck2ui 16
6436 16:31:08.818333 best dqsien dly found for B1: ( 0, 10, 16)
6437 16:31:08.821828 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6438 16:31:08.824766 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6439 16:31:08.824844
6440 16:31:08.828227 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6441 16:31:08.831146 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6442 16:31:08.835009 [Gating] SW calibration Done
6443 16:31:08.835087 ==
6444 16:31:08.838133 Dram Type= 6, Freq= 0, CH_1, rank 0
6445 16:31:08.841021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6446 16:31:08.841099 ==
6447 16:31:08.844750 RX Vref Scan: 0
6448 16:31:08.844827
6449 16:31:08.848062 RX Vref 0 -> 0, step: 1
6450 16:31:08.848153
6451 16:31:08.848213 RX Delay -410 -> 252, step: 16
6452 16:31:08.854379 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6453 16:31:08.857765 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6454 16:31:08.861083 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6455 16:31:08.867742 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6456 16:31:08.870957 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6457 16:31:08.874472 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6458 16:31:08.877890 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6459 16:31:08.880859 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6460 16:31:08.887967 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6461 16:31:08.890976 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6462 16:31:08.894412 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6463 16:31:08.901057 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6464 16:31:08.904138 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6465 16:31:08.907551 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6466 16:31:08.910952 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6467 16:31:08.917451 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6468 16:31:08.917530 ==
6469 16:31:08.920652 Dram Type= 6, Freq= 0, CH_1, rank 0
6470 16:31:08.924141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6471 16:31:08.924223 ==
6472 16:31:08.924283 DQS Delay:
6473 16:31:08.927243 DQS0 = 43, DQS1 = 59
6474 16:31:08.927321 DQM Delay:
6475 16:31:08.930650 DQM0 = 6, DQM1 = 15
6476 16:31:08.930765 DQ Delay:
6477 16:31:08.934187 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6478 16:31:08.937568 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6479 16:31:08.940485 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6480 16:31:08.944136 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6481 16:31:08.944219
6482 16:31:08.944279
6483 16:31:08.944334 ==
6484 16:31:08.947242 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 16:31:08.950484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 16:31:08.950564 ==
6487 16:31:08.950624
6488 16:31:08.950679
6489 16:31:08.954053 TX Vref Scan disable
6490 16:31:08.954129 == TX Byte 0 ==
6491 16:31:08.960385 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6492 16:31:08.964006 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6493 16:31:08.966802 == TX Byte 1 ==
6494 16:31:08.970092 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6495 16:31:08.973423 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6496 16:31:08.973501 ==
6497 16:31:08.976915 Dram Type= 6, Freq= 0, CH_1, rank 0
6498 16:31:08.980157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6499 16:31:08.983661 ==
6500 16:31:08.983738
6501 16:31:08.983797
6502 16:31:08.983853 TX Vref Scan disable
6503 16:31:08.986989 == TX Byte 0 ==
6504 16:31:08.990387 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6505 16:31:08.993621 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6506 16:31:08.997043 == TX Byte 1 ==
6507 16:31:08.999863 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6508 16:31:09.003144 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6509 16:31:09.003222
6510 16:31:09.006413 [DATLAT]
6511 16:31:09.006491 Freq=400, CH1 RK0
6512 16:31:09.006551
6513 16:31:09.009913 DATLAT Default: 0xf
6514 16:31:09.009990 0, 0xFFFF, sum = 0
6515 16:31:09.013244 1, 0xFFFF, sum = 0
6516 16:31:09.013322 2, 0xFFFF, sum = 0
6517 16:31:09.016678 3, 0xFFFF, sum = 0
6518 16:31:09.016758 4, 0xFFFF, sum = 0
6519 16:31:09.019581 5, 0xFFFF, sum = 0
6520 16:31:09.019659 6, 0xFFFF, sum = 0
6521 16:31:09.022909 7, 0xFFFF, sum = 0
6522 16:31:09.022989 8, 0xFFFF, sum = 0
6523 16:31:09.026096 9, 0xFFFF, sum = 0
6524 16:31:09.029837 10, 0xFFFF, sum = 0
6525 16:31:09.029916 11, 0xFFFF, sum = 0
6526 16:31:09.032854 12, 0x0, sum = 1
6527 16:31:09.032933 13, 0x0, sum = 2
6528 16:31:09.033020 14, 0x0, sum = 3
6529 16:31:09.036142 15, 0x0, sum = 4
6530 16:31:09.036221 best_step = 13
6531 16:31:09.036280
6532 16:31:09.036336 ==
6533 16:31:09.039451 Dram Type= 6, Freq= 0, CH_1, rank 0
6534 16:31:09.046017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6535 16:31:09.046101 ==
6536 16:31:09.046162 RX Vref Scan: 1
6537 16:31:09.046239
6538 16:31:09.049520 RX Vref 0 -> 0, step: 1
6539 16:31:09.049598
6540 16:31:09.053053 RX Delay -359 -> 252, step: 8
6541 16:31:09.053122
6542 16:31:09.055936 Set Vref, RX VrefLevel [Byte0]: 57
6543 16:31:09.059466 [Byte1]: 51
6544 16:31:09.062821
6545 16:31:09.062914 Final RX Vref Byte 0 = 57 to rank0
6546 16:31:09.066356 Final RX Vref Byte 1 = 51 to rank0
6547 16:31:09.069739 Final RX Vref Byte 0 = 57 to rank1
6548 16:31:09.073054 Final RX Vref Byte 1 = 51 to rank1==
6549 16:31:09.075969 Dram Type= 6, Freq= 0, CH_1, rank 0
6550 16:31:09.082981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6551 16:31:09.083060 ==
6552 16:31:09.083127 DQS Delay:
6553 16:31:09.086416 DQS0 = 52, DQS1 = 64
6554 16:31:09.086493 DQM Delay:
6555 16:31:09.086554 DQM0 = 11, DQM1 = 15
6556 16:31:09.089707 DQ Delay:
6557 16:31:09.092954 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6558 16:31:09.096045 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6559 16:31:09.096123 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6560 16:31:09.102591 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6561 16:31:09.102692
6562 16:31:09.102784
6563 16:31:09.109255 [DQSOSCAuto] RK0, (LSB)MR18= 0xd5d5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6564 16:31:09.112784 CH1 RK0: MR19=C0C, MR18=D5D5
6565 16:31:09.119189 CH1_RK0: MR19=0xC0C, MR18=0xD5D5, DQSOSC=383, MR23=63, INC=402, DEC=268
6566 16:31:09.119286 ==
6567 16:31:09.122867 Dram Type= 6, Freq= 0, CH_1, rank 1
6568 16:31:09.125761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6569 16:31:09.125854 ==
6570 16:31:09.129068 [Gating] SW mode calibration
6571 16:31:09.136330 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6572 16:31:09.142328 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6573 16:31:09.145482 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6574 16:31:09.149124 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6575 16:31:09.155930 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6576 16:31:09.158715 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6577 16:31:09.162111 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6578 16:31:09.169020 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6579 16:31:09.172104 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6580 16:31:09.175460 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6581 16:31:09.179075 Total UI for P1: 0, mck2ui 16
6582 16:31:09.181913 best dqsien dly found for B0: ( 0, 10, 8)
6583 16:31:09.188744 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6584 16:31:09.188824 Total UI for P1: 0, mck2ui 16
6585 16:31:09.192334 best dqsien dly found for B1: ( 0, 10, 16)
6586 16:31:09.198703 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6587 16:31:09.202012 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6588 16:31:09.202091
6589 16:31:09.204923 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6590 16:31:09.208624 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6591 16:31:09.211726 [Gating] SW calibration Done
6592 16:31:09.211805 ==
6593 16:31:09.215309 Dram Type= 6, Freq= 0, CH_1, rank 1
6594 16:31:09.218520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6595 16:31:09.218600 ==
6596 16:31:09.221977 RX Vref Scan: 0
6597 16:31:09.222054
6598 16:31:09.222114 RX Vref 0 -> 0, step: 1
6599 16:31:09.222171
6600 16:31:09.224982 RX Delay -410 -> 252, step: 16
6601 16:31:09.231573 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6602 16:31:09.234936 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6603 16:31:09.238108 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6604 16:31:09.242069 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6605 16:31:09.248689 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6606 16:31:09.251525 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6607 16:31:09.255066 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6608 16:31:09.258028 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6609 16:31:09.264932 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6610 16:31:09.268610 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6611 16:31:09.271500 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6612 16:31:09.275050 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6613 16:31:09.281790 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6614 16:31:09.284600 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6615 16:31:09.287928 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6616 16:31:09.291323 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6617 16:31:09.294936 ==
6618 16:31:09.297775 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 16:31:09.301408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6620 16:31:09.301486 ==
6621 16:31:09.301547 DQS Delay:
6622 16:31:09.304822 DQS0 = 43, DQS1 = 59
6623 16:31:09.304900 DQM Delay:
6624 16:31:09.307699 DQM0 = 10, DQM1 = 17
6625 16:31:09.307777 DQ Delay:
6626 16:31:09.311099 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6627 16:31:09.314295 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6628 16:31:09.317839 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6629 16:31:09.321071 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6630 16:31:09.321148
6631 16:31:09.321207
6632 16:31:09.321263 ==
6633 16:31:09.324406 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 16:31:09.327799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6635 16:31:09.327876 ==
6636 16:31:09.327936
6637 16:31:09.327992
6638 16:31:09.331053 TX Vref Scan disable
6639 16:31:09.331154 == TX Byte 0 ==
6640 16:31:09.337390 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6641 16:31:09.340830 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6642 16:31:09.340908 == TX Byte 1 ==
6643 16:31:09.347825 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6644 16:31:09.350689 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6645 16:31:09.350800 ==
6646 16:31:09.354149 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 16:31:09.357612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6648 16:31:09.357731 ==
6649 16:31:09.357855
6650 16:31:09.357911
6651 16:31:09.360839 TX Vref Scan disable
6652 16:31:09.360926 == TX Byte 0 ==
6653 16:31:09.367420 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6654 16:31:09.370774 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6655 16:31:09.370854 == TX Byte 1 ==
6656 16:31:09.377714 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6657 16:31:09.380480 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6658 16:31:09.380560
6659 16:31:09.380621 [DATLAT]
6660 16:31:09.383905 Freq=400, CH1 RK1
6661 16:31:09.383983
6662 16:31:09.384044 DATLAT Default: 0xd
6663 16:31:09.387364 0, 0xFFFF, sum = 0
6664 16:31:09.387442 1, 0xFFFF, sum = 0
6665 16:31:09.390476 2, 0xFFFF, sum = 0
6666 16:31:09.390555 3, 0xFFFF, sum = 0
6667 16:31:09.393704 4, 0xFFFF, sum = 0
6668 16:31:09.393782 5, 0xFFFF, sum = 0
6669 16:31:09.397228 6, 0xFFFF, sum = 0
6670 16:31:09.397307 7, 0xFFFF, sum = 0
6671 16:31:09.400326 8, 0xFFFF, sum = 0
6672 16:31:09.400420 9, 0xFFFF, sum = 0
6673 16:31:09.403788 10, 0xFFFF, sum = 0
6674 16:31:09.407372 11, 0xFFFF, sum = 0
6675 16:31:09.407451 12, 0x0, sum = 1
6676 16:31:09.410343 13, 0x0, sum = 2
6677 16:31:09.410421 14, 0x0, sum = 3
6678 16:31:09.410483 15, 0x0, sum = 4
6679 16:31:09.413541 best_step = 13
6680 16:31:09.413617
6681 16:31:09.413676 ==
6682 16:31:09.416899 Dram Type= 6, Freq= 0, CH_1, rank 1
6683 16:31:09.420508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6684 16:31:09.420586 ==
6685 16:31:09.423696 RX Vref Scan: 0
6686 16:31:09.423773
6687 16:31:09.427102 RX Vref 0 -> 0, step: 1
6688 16:31:09.427179
6689 16:31:09.427239 RX Delay -359 -> 252, step: 8
6690 16:31:09.435573 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6691 16:31:09.438968 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6692 16:31:09.442149 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6693 16:31:09.445318 iDelay=225, Bit 3, Center -40 (-287 ~ 208) 496
6694 16:31:09.452240 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6695 16:31:09.455418 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6696 16:31:09.458885 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6697 16:31:09.462174 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6698 16:31:09.468768 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6699 16:31:09.472003 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6700 16:31:09.475309 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6701 16:31:09.482053 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6702 16:31:09.485037 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6703 16:31:09.488447 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6704 16:31:09.491794 iDelay=225, Bit 14, Center -36 (-287 ~ 216) 504
6705 16:31:09.498629 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6706 16:31:09.498708 ==
6707 16:31:09.501646 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 16:31:09.505144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 16:31:09.505222 ==
6710 16:31:09.505283 DQS Delay:
6711 16:31:09.508596 DQS0 = 48, DQS1 = 64
6712 16:31:09.508704 DQM Delay:
6713 16:31:09.511579 DQM0 = 10, DQM1 = 16
6714 16:31:09.511656 DQ Delay:
6715 16:31:09.515048 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6716 16:31:09.518657 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6717 16:31:09.521557 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6718 16:31:09.524896 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6719 16:31:09.524974
6720 16:31:09.525033
6721 16:31:09.531557 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6722 16:31:09.535077 CH1 RK1: MR19=C0C, MR18=A4A4
6723 16:31:09.541564 CH1_RK1: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6724 16:31:09.544968 [RxdqsGatingPostProcess] freq 400
6725 16:31:09.551835 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6726 16:31:09.551942 Pre-setting of DQS Precalculation
6727 16:31:09.557830 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6728 16:31:09.564629 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6729 16:31:09.571399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6730 16:31:09.571478
6731 16:31:09.571538
6732 16:31:09.574810 [Calibration Summary] 800 Mbps
6733 16:31:09.578060 CH 0, Rank 0
6734 16:31:09.578137 SW Impedance : PASS
6735 16:31:09.581183 DUTY Scan : NO K
6736 16:31:09.584731 ZQ Calibration : PASS
6737 16:31:09.584808 Jitter Meter : NO K
6738 16:31:09.587683 CBT Training : PASS
6739 16:31:09.590858 Write leveling : PASS
6740 16:31:09.590936 RX DQS gating : PASS
6741 16:31:09.594394 RX DQ/DQS(RDDQC) : PASS
6742 16:31:09.597353 TX DQ/DQS : PASS
6743 16:31:09.597431 RX DATLAT : PASS
6744 16:31:09.600847 RX DQ/DQS(Engine): PASS
6745 16:31:09.604418 TX OE : NO K
6746 16:31:09.604497 All Pass.
6747 16:31:09.604557
6748 16:31:09.604612 CH 0, Rank 1
6749 16:31:09.607319 SW Impedance : PASS
6750 16:31:09.611185 DUTY Scan : NO K
6751 16:31:09.611278 ZQ Calibration : PASS
6752 16:31:09.614125 Jitter Meter : NO K
6753 16:31:09.614205 CBT Training : PASS
6754 16:31:09.617786 Write leveling : NO K
6755 16:31:09.620723 RX DQS gating : PASS
6756 16:31:09.620816 RX DQ/DQS(RDDQC) : PASS
6757 16:31:09.624138 TX DQ/DQS : PASS
6758 16:31:09.627760 RX DATLAT : PASS
6759 16:31:09.627859 RX DQ/DQS(Engine): PASS
6760 16:31:09.630478 TX OE : NO K
6761 16:31:09.630571 All Pass.
6762 16:31:09.630657
6763 16:31:09.633907 CH 1, Rank 0
6764 16:31:09.634002 SW Impedance : PASS
6765 16:31:09.637056 DUTY Scan : NO K
6766 16:31:09.640980 ZQ Calibration : PASS
6767 16:31:09.641090 Jitter Meter : NO K
6768 16:31:09.644049 CBT Training : PASS
6769 16:31:09.647710 Write leveling : PASS
6770 16:31:09.647802 RX DQS gating : PASS
6771 16:31:09.650510 RX DQ/DQS(RDDQC) : PASS
6772 16:31:09.653889 TX DQ/DQS : PASS
6773 16:31:09.653966 RX DATLAT : PASS
6774 16:31:09.657467 RX DQ/DQS(Engine): PASS
6775 16:31:09.660348 TX OE : NO K
6776 16:31:09.660447 All Pass.
6777 16:31:09.660535
6778 16:31:09.660617 CH 1, Rank 1
6779 16:31:09.663915 SW Impedance : PASS
6780 16:31:09.667387 DUTY Scan : NO K
6781 16:31:09.667478 ZQ Calibration : PASS
6782 16:31:09.670399 Jitter Meter : NO K
6783 16:31:09.670473 CBT Training : PASS
6784 16:31:09.673574 Write leveling : NO K
6785 16:31:09.677326 RX DQS gating : PASS
6786 16:31:09.677424 RX DQ/DQS(RDDQC) : PASS
6787 16:31:09.680769 TX DQ/DQS : PASS
6788 16:31:09.684014 RX DATLAT : PASS
6789 16:31:09.684082 RX DQ/DQS(Engine): PASS
6790 16:31:09.687424 TX OE : NO K
6791 16:31:09.687502 All Pass.
6792 16:31:09.687564
6793 16:31:09.690363 DramC Write-DBI off
6794 16:31:09.693645 PER_BANK_REFRESH: Hybrid Mode
6795 16:31:09.693721 TX_TRACKING: ON
6796 16:31:09.703640 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6797 16:31:09.707000 [FAST_K] Save calibration result to emmc
6798 16:31:09.709932 dramc_set_vcore_voltage set vcore to 725000
6799 16:31:09.713491 Read voltage for 1600, 0
6800 16:31:09.713580 Vio18 = 0
6801 16:31:09.716588 Vcore = 725000
6802 16:31:09.716677 Vdram = 0
6803 16:31:09.716758 Vddq = 0
6804 16:31:09.716836 Vmddr = 0
6805 16:31:09.723099 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6806 16:31:09.726848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6807 16:31:09.730069 MEM_TYPE=3, freq_sel=13
6808 16:31:09.733350 sv_algorithm_assistance_LP4_3733
6809 16:31:09.736967 ============ PULL DRAM RESETB DOWN ============
6810 16:31:09.743270 ========== PULL DRAM RESETB DOWN end =========
6811 16:31:09.746526 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6812 16:31:09.749992 ===================================
6813 16:31:09.753011 LPDDR4 DRAM CONFIGURATION
6814 16:31:09.756255 ===================================
6815 16:31:09.756332 EX_ROW_EN[0] = 0x0
6816 16:31:09.759844 EX_ROW_EN[1] = 0x0
6817 16:31:09.759921 LP4Y_EN = 0x0
6818 16:31:09.763326 WORK_FSP = 0x1
6819 16:31:09.763421 WL = 0x5
6820 16:31:09.766301 RL = 0x5
6821 16:31:09.766407 BL = 0x2
6822 16:31:09.769907 RPST = 0x0
6823 16:31:09.772749 RD_PRE = 0x0
6824 16:31:09.772826 WR_PRE = 0x1
6825 16:31:09.776189 WR_PST = 0x1
6826 16:31:09.776281 DBI_WR = 0x0
6827 16:31:09.779474 DBI_RD = 0x0
6828 16:31:09.779551 OTF = 0x1
6829 16:31:09.782859 ===================================
6830 16:31:09.785984 ===================================
6831 16:31:09.789280 ANA top config
6832 16:31:09.792558 ===================================
6833 16:31:09.792634 DLL_ASYNC_EN = 0
6834 16:31:09.795864 ALL_SLAVE_EN = 0
6835 16:31:09.799527 NEW_RANK_MODE = 1
6836 16:31:09.802689 DLL_IDLE_MODE = 1
6837 16:31:09.802767 LP45_APHY_COMB_EN = 1
6838 16:31:09.806122 TX_ODT_DIS = 0
6839 16:31:09.809232 NEW_8X_MODE = 1
6840 16:31:09.812613 ===================================
6841 16:31:09.815731 ===================================
6842 16:31:09.819372 data_rate = 3200
6843 16:31:09.822378 CKR = 1
6844 16:31:09.825776 DQ_P2S_RATIO = 8
6845 16:31:09.829498 ===================================
6846 16:31:09.829576 CA_P2S_RATIO = 8
6847 16:31:09.832320 DQ_CA_OPEN = 0
6848 16:31:09.835848 DQ_SEMI_OPEN = 0
6849 16:31:09.839426 CA_SEMI_OPEN = 0
6850 16:31:09.842191 CA_FULL_RATE = 0
6851 16:31:09.845923 DQ_CKDIV4_EN = 0
6852 16:31:09.846001 CA_CKDIV4_EN = 0
6853 16:31:09.848822 CA_PREDIV_EN = 0
6854 16:31:09.852169 PH8_DLY = 12
6855 16:31:09.855795 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6856 16:31:09.858876 DQ_AAMCK_DIV = 4
6857 16:31:09.862188 CA_AAMCK_DIV = 4
6858 16:31:09.862291 CA_ADMCK_DIV = 4
6859 16:31:09.865617 DQ_TRACK_CA_EN = 0
6860 16:31:09.869038 CA_PICK = 1600
6861 16:31:09.871973 CA_MCKIO = 1600
6862 16:31:09.875630 MCKIO_SEMI = 0
6863 16:31:09.878874 PLL_FREQ = 3068
6864 16:31:09.882199 DQ_UI_PI_RATIO = 32
6865 16:31:09.885564 CA_UI_PI_RATIO = 0
6866 16:31:09.885640 ===================================
6867 16:31:09.888622 ===================================
6868 16:31:09.892017 memory_type:LPDDR4
6869 16:31:09.895438 GP_NUM : 10
6870 16:31:09.895516 SRAM_EN : 1
6871 16:31:09.898540 MD32_EN : 0
6872 16:31:09.901995 ===================================
6873 16:31:09.905560 [ANA_INIT] >>>>>>>>>>>>>>
6874 16:31:09.908638 <<<<<< [CONFIGURE PHASE]: ANA_TX
6875 16:31:09.911826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6876 16:31:09.914707 ===================================
6877 16:31:09.918087 data_rate = 3200,PCW = 0X7600
6878 16:31:09.921743 ===================================
6879 16:31:09.924844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6880 16:31:09.928363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6881 16:31:09.934967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6882 16:31:09.938027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6883 16:31:09.941532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6884 16:31:09.944501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6885 16:31:09.947985 [ANA_INIT] flow start
6886 16:31:09.951595 [ANA_INIT] PLL >>>>>>>>
6887 16:31:09.951671 [ANA_INIT] PLL <<<<<<<<
6888 16:31:09.954689 [ANA_INIT] MIDPI >>>>>>>>
6889 16:31:09.957972 [ANA_INIT] MIDPI <<<<<<<<
6890 16:31:09.961079 [ANA_INIT] DLL >>>>>>>>
6891 16:31:09.961156 [ANA_INIT] DLL <<<<<<<<
6892 16:31:09.964833 [ANA_INIT] flow end
6893 16:31:09.967679 ============ LP4 DIFF to SE enter ============
6894 16:31:09.971202 ============ LP4 DIFF to SE exit ============
6895 16:31:09.974999 [ANA_INIT] <<<<<<<<<<<<<
6896 16:31:09.977661 [Flow] Enable top DCM control >>>>>
6897 16:31:09.981279 [Flow] Enable top DCM control <<<<<
6898 16:31:09.984618 Enable DLL master slave shuffle
6899 16:31:09.991170 ==============================================================
6900 16:31:09.991262 Gating Mode config
6901 16:31:09.997966 ==============================================================
6902 16:31:09.998072 Config description:
6903 16:31:10.007310 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6904 16:31:10.013889 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6905 16:31:10.020923 SELPH_MODE 0: By rank 1: By Phase
6906 16:31:10.024055 ==============================================================
6907 16:31:10.027150 GAT_TRACK_EN = 1
6908 16:31:10.030409 RX_GATING_MODE = 2
6909 16:31:10.033900 RX_GATING_TRACK_MODE = 2
6910 16:31:10.037076 SELPH_MODE = 1
6911 16:31:10.040470 PICG_EARLY_EN = 1
6912 16:31:10.043849 VALID_LAT_VALUE = 1
6913 16:31:10.050542 ==============================================================
6914 16:31:10.053342 Enter into Gating configuration >>>>
6915 16:31:10.056750 Exit from Gating configuration <<<<
6916 16:31:10.060303 Enter into DVFS_PRE_config >>>>>
6917 16:31:10.069939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6918 16:31:10.073134 Exit from DVFS_PRE_config <<<<<
6919 16:31:10.076671 Enter into PICG configuration >>>>
6920 16:31:10.079964 Exit from PICG configuration <<<<
6921 16:31:10.083532 [RX_INPUT] configuration >>>>>
6922 16:31:10.083632 [RX_INPUT] configuration <<<<<
6923 16:31:10.089815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6924 16:31:10.096615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6925 16:31:10.099730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6926 16:31:10.106455 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6927 16:31:10.112892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6928 16:31:10.119662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6929 16:31:10.123100 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6930 16:31:10.126254 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6931 16:31:10.132952 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6932 16:31:10.136338 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6933 16:31:10.139225 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6934 16:31:10.146287 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6935 16:31:10.149416 ===================================
6936 16:31:10.149493 LPDDR4 DRAM CONFIGURATION
6937 16:31:10.152876 ===================================
6938 16:31:10.155770 EX_ROW_EN[0] = 0x0
6939 16:31:10.159312 EX_ROW_EN[1] = 0x0
6940 16:31:10.159389 LP4Y_EN = 0x0
6941 16:31:10.162833 WORK_FSP = 0x1
6942 16:31:10.162911 WL = 0x5
6943 16:31:10.165656 RL = 0x5
6944 16:31:10.165732 BL = 0x2
6945 16:31:10.169377 RPST = 0x0
6946 16:31:10.169455 RD_PRE = 0x0
6947 16:31:10.172532 WR_PRE = 0x1
6948 16:31:10.172608 WR_PST = 0x1
6949 16:31:10.175703 DBI_WR = 0x0
6950 16:31:10.175779 DBI_RD = 0x0
6951 16:31:10.179090 OTF = 0x1
6952 16:31:10.182629 ===================================
6953 16:31:10.185953 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6954 16:31:10.188990 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6955 16:31:10.195750 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6956 16:31:10.199159 ===================================
6957 16:31:10.199237 LPDDR4 DRAM CONFIGURATION
6958 16:31:10.202087 ===================================
6959 16:31:10.205893 EX_ROW_EN[0] = 0x10
6960 16:31:10.208666 EX_ROW_EN[1] = 0x0
6961 16:31:10.208743 LP4Y_EN = 0x0
6962 16:31:10.212078 WORK_FSP = 0x1
6963 16:31:10.212155 WL = 0x5
6964 16:31:10.215605 RL = 0x5
6965 16:31:10.215699 BL = 0x2
6966 16:31:10.218793 RPST = 0x0
6967 16:31:10.218869 RD_PRE = 0x0
6968 16:31:10.221927 WR_PRE = 0x1
6969 16:31:10.222003 WR_PST = 0x1
6970 16:31:10.225186 DBI_WR = 0x0
6971 16:31:10.225278 DBI_RD = 0x0
6972 16:31:10.228589 OTF = 0x1
6973 16:31:10.232010 ===================================
6974 16:31:10.238917 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6975 16:31:10.239021 ==
6976 16:31:10.242319 Dram Type= 6, Freq= 0, CH_0, rank 0
6977 16:31:10.245199 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6978 16:31:10.245294 ==
6979 16:31:10.248640 [Duty_Offset_Calibration]
6980 16:31:10.248741 B0:0 B1:2 CA:1
6981 16:31:10.248798
6982 16:31:10.252110 [DutyScan_Calibration_Flow] k_type=0
6983 16:31:10.262624
6984 16:31:10.262706 ==CLK 0==
6985 16:31:10.265589 Final CLK duty delay cell = 0
6986 16:31:10.269001 [0] MAX Duty = 5156%(X100), DQS PI = 22
6987 16:31:10.272040 [0] MIN Duty = 4938%(X100), DQS PI = 50
6988 16:31:10.275399 [0] AVG Duty = 5047%(X100)
6989 16:31:10.275479
6990 16:31:10.279014 CH0 CLK Duty spec in!! Max-Min= 218%
6991 16:31:10.281857 [DutyScan_Calibration_Flow] ====Done====
6992 16:31:10.281953
6993 16:31:10.285460 [DutyScan_Calibration_Flow] k_type=1
6994 16:31:10.302572
6995 16:31:10.302669 ==DQS 0 ==
6996 16:31:10.305593 Final DQS duty delay cell = 0
6997 16:31:10.309037 [0] MAX Duty = 5156%(X100), DQS PI = 34
6998 16:31:10.312168 [0] MIN Duty = 5031%(X100), DQS PI = 8
6999 16:31:10.315582 [0] AVG Duty = 5093%(X100)
7000 16:31:10.315663
7001 16:31:10.315724 ==DQS 1 ==
7002 16:31:10.319149 Final DQS duty delay cell = 0
7003 16:31:10.321978 [0] MAX Duty = 5031%(X100), DQS PI = 2
7004 16:31:10.325521 [0] MIN Duty = 4844%(X100), DQS PI = 18
7005 16:31:10.328964 [0] AVG Duty = 4937%(X100)
7006 16:31:10.329082
7007 16:31:10.332160 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7008 16:31:10.332247
7009 16:31:10.335535 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7010 16:31:10.338424 [DutyScan_Calibration_Flow] ====Done====
7011 16:31:10.338527
7012 16:31:10.342021 [DutyScan_Calibration_Flow] k_type=3
7013 16:31:10.359186
7014 16:31:10.359288 ==DQM 0 ==
7015 16:31:10.362528 Final DQM duty delay cell = 0
7016 16:31:10.366054 [0] MAX Duty = 5187%(X100), DQS PI = 22
7017 16:31:10.368999 [0] MIN Duty = 4907%(X100), DQS PI = 42
7018 16:31:10.372549 [0] AVG Duty = 5047%(X100)
7019 16:31:10.372646
7020 16:31:10.372730 ==DQM 1 ==
7021 16:31:10.375933 Final DQM duty delay cell = 0
7022 16:31:10.379448 [0] MAX Duty = 5031%(X100), DQS PI = 50
7023 16:31:10.382402 [0] MIN Duty = 4782%(X100), DQS PI = 14
7024 16:31:10.385873 [0] AVG Duty = 4906%(X100)
7025 16:31:10.385959
7026 16:31:10.388994 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7027 16:31:10.389070
7028 16:31:10.392324 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7029 16:31:10.395674 [DutyScan_Calibration_Flow] ====Done====
7030 16:31:10.395755
7031 16:31:10.398874 [DutyScan_Calibration_Flow] k_type=2
7032 16:31:10.415701
7033 16:31:10.415817 ==DQ 0 ==
7034 16:31:10.419182 Final DQ duty delay cell = 0
7035 16:31:10.422579 [0] MAX Duty = 5218%(X100), DQS PI = 18
7036 16:31:10.425480 [0] MIN Duty = 4938%(X100), DQS PI = 56
7037 16:31:10.425563 [0] AVG Duty = 5078%(X100)
7038 16:31:10.428938
7039 16:31:10.429016 ==DQ 1 ==
7040 16:31:10.432380 Final DQ duty delay cell = -4
7041 16:31:10.435958 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7042 16:31:10.439035 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7043 16:31:10.442407 [-4] AVG Duty = 4953%(X100)
7044 16:31:10.442492
7045 16:31:10.445813 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7046 16:31:10.445892
7047 16:31:10.449234 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7048 16:31:10.452056 [DutyScan_Calibration_Flow] ====Done====
7049 16:31:10.452136 ==
7050 16:31:10.455375 Dram Type= 6, Freq= 0, CH_1, rank 0
7051 16:31:10.458773 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7052 16:31:10.458858 ==
7053 16:31:10.462355 [Duty_Offset_Calibration]
7054 16:31:10.462425 B0:0 B1:5 CA:-5
7055 16:31:10.462483
7056 16:31:10.465379 [DutyScan_Calibration_Flow] k_type=0
7057 16:31:10.476454
7058 16:31:10.476550 ==CLK 0==
7059 16:31:10.479985 Final CLK duty delay cell = 0
7060 16:31:10.483236 [0] MAX Duty = 5156%(X100), DQS PI = 20
7061 16:31:10.486289 [0] MIN Duty = 4906%(X100), DQS PI = 50
7062 16:31:10.489719 [0] AVG Duty = 5031%(X100)
7063 16:31:10.489796
7064 16:31:10.493258 CH1 CLK Duty spec in!! Max-Min= 250%
7065 16:31:10.496165 [DutyScan_Calibration_Flow] ====Done====
7066 16:31:10.496241
7067 16:31:10.499358 [DutyScan_Calibration_Flow] k_type=1
7068 16:31:10.515158
7069 16:31:10.515297 ==DQS 0 ==
7070 16:31:10.518457 Final DQS duty delay cell = 0
7071 16:31:10.522061 [0] MAX Duty = 5156%(X100), DQS PI = 18
7072 16:31:10.525093 [0] MIN Duty = 4876%(X100), DQS PI = 42
7073 16:31:10.528599 [0] AVG Duty = 5016%(X100)
7074 16:31:10.528677
7075 16:31:10.528736 ==DQS 1 ==
7076 16:31:10.531844 Final DQS duty delay cell = -4
7077 16:31:10.535307 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7078 16:31:10.538183 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7079 16:31:10.541848 [-4] AVG Duty = 4922%(X100)
7080 16:31:10.541943
7081 16:31:10.545374 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7082 16:31:10.545468
7083 16:31:10.548371 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7084 16:31:10.551701 [DutyScan_Calibration_Flow] ====Done====
7085 16:31:10.551779
7086 16:31:10.555123 [DutyScan_Calibration_Flow] k_type=3
7087 16:31:10.570857
7088 16:31:10.570940 ==DQM 0 ==
7089 16:31:10.574053 Final DQM duty delay cell = -4
7090 16:31:10.577832 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7091 16:31:10.581018 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7092 16:31:10.583916 [-4] AVG Duty = 4937%(X100)
7093 16:31:10.583993
7094 16:31:10.584053 ==DQM 1 ==
7095 16:31:10.587246 Final DQM duty delay cell = -4
7096 16:31:10.590761 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7097 16:31:10.594343 [-4] MIN Duty = 4876%(X100), DQS PI = 38
7098 16:31:10.597234 [-4] AVG Duty = 4969%(X100)
7099 16:31:10.597304
7100 16:31:10.600656 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7101 16:31:10.600732
7102 16:31:10.603697 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7103 16:31:10.607218 [DutyScan_Calibration_Flow] ====Done====
7104 16:31:10.607292
7105 16:31:10.610600 [DutyScan_Calibration_Flow] k_type=2
7106 16:31:10.628557
7107 16:31:10.628645 ==DQ 0 ==
7108 16:31:10.631805 Final DQ duty delay cell = 0
7109 16:31:10.635210 [0] MAX Duty = 5093%(X100), DQS PI = 18
7110 16:31:10.638722 [0] MIN Duty = 4938%(X100), DQS PI = 46
7111 16:31:10.638801 [0] AVG Duty = 5015%(X100)
7112 16:31:10.641683
7113 16:31:10.641750 ==DQ 1 ==
7114 16:31:10.645110 Final DQ duty delay cell = 0
7115 16:31:10.648753 [0] MAX Duty = 5031%(X100), DQS PI = 4
7116 16:31:10.651868 [0] MIN Duty = 4875%(X100), DQS PI = 30
7117 16:31:10.651943 [0] AVG Duty = 4953%(X100)
7118 16:31:10.655018
7119 16:31:10.658365 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7120 16:31:10.658439
7121 16:31:10.661767 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7122 16:31:10.664732 [DutyScan_Calibration_Flow] ====Done====
7123 16:31:10.668206 nWR fixed to 30
7124 16:31:10.668277 [ModeRegInit_LP4] CH0 RK0
7125 16:31:10.671682 [ModeRegInit_LP4] CH0 RK1
7126 16:31:10.675016 [ModeRegInit_LP4] CH1 RK0
7127 16:31:10.678324 [ModeRegInit_LP4] CH1 RK1
7128 16:31:10.678400 match AC timing 4
7129 16:31:10.681697 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7130 16:31:10.688033 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7131 16:31:10.691575 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7132 16:31:10.698340 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7133 16:31:10.701836 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7134 16:31:10.701915 [MiockJmeterHQA]
7135 16:31:10.701975
7136 16:31:10.704867 [DramcMiockJmeter] u1RxGatingPI = 0
7137 16:31:10.708208 0 : 4365, 4138
7138 16:31:10.708280 4 : 4362, 4137
7139 16:31:10.711690 8 : 4252, 4027
7140 16:31:10.711761 12 : 4253, 4026
7141 16:31:10.711828 16 : 4252, 4026
7142 16:31:10.714567 20 : 4253, 4027
7143 16:31:10.714668 24 : 4253, 4026
7144 16:31:10.718234 28 : 4252, 4027
7145 16:31:10.718318 32 : 4365, 4140
7146 16:31:10.721182 36 : 4252, 4027
7147 16:31:10.721260 40 : 4254, 4029
7148 16:31:10.721317 44 : 4252, 4027
7149 16:31:10.724697 48 : 4360, 4138
7150 16:31:10.724766 52 : 4252, 4027
7151 16:31:10.728134 56 : 4361, 4137
7152 16:31:10.728229 60 : 4249, 4027
7153 16:31:10.731536 64 : 4250, 4026
7154 16:31:10.731617 68 : 4250, 4027
7155 16:31:10.734926 72 : 4252, 4029
7156 16:31:10.735007 76 : 4250, 4027
7157 16:31:10.735068 80 : 4249, 4027
7158 16:31:10.738001 84 : 4363, 4139
7159 16:31:10.738104 88 : 4250, 4027
7160 16:31:10.741224 92 : 4252, 4029
7161 16:31:10.741303 96 : 4250, 4027
7162 16:31:10.744807 100 : 4360, 2017
7163 16:31:10.744886 104 : 4249, 0
7164 16:31:10.744947 108 : 4252, 0
7165 16:31:10.747722 112 : 4250, 0
7166 16:31:10.747799 116 : 4252, 0
7167 16:31:10.751166 120 : 4363, 0
7168 16:31:10.751244 124 : 4250, 0
7169 16:31:10.751305 128 : 4250, 0
7170 16:31:10.754698 132 : 4249, 0
7171 16:31:10.754775 136 : 4360, 0
7172 16:31:10.757582 140 : 4250, 0
7173 16:31:10.757666 144 : 4250, 0
7174 16:31:10.757727 148 : 4250, 0
7175 16:31:10.760992 152 : 4250, 0
7176 16:31:10.761070 156 : 4253, 0
7177 16:31:10.764729 160 : 4250, 0
7178 16:31:10.764807 164 : 4250, 0
7179 16:31:10.764868 168 : 4252, 0
7180 16:31:10.767773 172 : 4360, 0
7181 16:31:10.767851 176 : 4250, 0
7182 16:31:10.771243 180 : 4250, 0
7183 16:31:10.771321 184 : 4250, 0
7184 16:31:10.771382 188 : 4361, 0
7185 16:31:10.774167 192 : 4361, 0
7186 16:31:10.774284 196 : 4250, 0
7187 16:31:10.774346 200 : 4250, 0
7188 16:31:10.777704 204 : 4250, 0
7189 16:31:10.777782 208 : 4252, 0
7190 16:31:10.780957 212 : 4249, 0
7191 16:31:10.781036 216 : 4250, 0
7192 16:31:10.784457 220 : 4252, 496
7193 16:31:10.784539 224 : 4360, 3998
7194 16:31:10.784601 228 : 4250, 4027
7195 16:31:10.787505 232 : 4250, 4027
7196 16:31:10.787582 236 : 4252, 4029
7197 16:31:10.790609 240 : 4250, 4027
7198 16:31:10.790687 244 : 4250, 4027
7199 16:31:10.794011 248 : 4250, 4027
7200 16:31:10.794089 252 : 4252, 4029
7201 16:31:10.797403 256 : 4250, 4027
7202 16:31:10.797481 260 : 4360, 4138
7203 16:31:10.800688 264 : 4360, 4138
7204 16:31:10.800766 268 : 4250, 4026
7205 16:31:10.803845 272 : 4363, 4139
7206 16:31:10.803924 276 : 4360, 4138
7207 16:31:10.807743 280 : 4250, 4027
7208 16:31:10.807823 284 : 4249, 4027
7209 16:31:10.807884 288 : 4252, 4029
7210 16:31:10.810572 292 : 4250, 4027
7211 16:31:10.810651 296 : 4250, 4027
7212 16:31:10.814008 300 : 4250, 4027
7213 16:31:10.814106 304 : 4252, 4029
7214 16:31:10.817468 308 : 4250, 4027
7215 16:31:10.817536 312 : 4360, 4138
7216 16:31:10.820744 316 : 4360, 4138
7217 16:31:10.820818 320 : 4250, 4026
7218 16:31:10.824029 324 : 4363, 4139
7219 16:31:10.824105 328 : 4360, 4138
7220 16:31:10.827329 332 : 4250, 4027
7221 16:31:10.827397 336 : 4249, 3968
7222 16:31:10.830497 340 : 4253, 2264
7223 16:31:10.830571 344 : 4250, 0
7224 16:31:10.830626
7225 16:31:10.833909 MIOCK jitter meter ch=0
7226 16:31:10.833982
7227 16:31:10.837452 1T = (344-100) = 244 dly cells
7228 16:31:10.840257 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 266/100 ps
7229 16:31:10.840333 ==
7230 16:31:10.843536 Dram Type= 6, Freq= 0, CH_0, rank 0
7231 16:31:10.850405 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7232 16:31:10.850499 ==
7233 16:31:10.853981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7234 16:31:10.860446 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7235 16:31:10.863342 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7236 16:31:10.870108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7237 16:31:10.877158 [CA 0] Center 42 (12~72) winsize 61
7238 16:31:10.880591 [CA 1] Center 41 (11~72) winsize 62
7239 16:31:10.883847 [CA 2] Center 37 (7~68) winsize 62
7240 16:31:10.886962 [CA 3] Center 37 (7~67) winsize 61
7241 16:31:10.890366 [CA 4] Center 35 (5~66) winsize 62
7242 16:31:10.893562 [CA 5] Center 35 (5~65) winsize 61
7243 16:31:10.893678
7244 16:31:10.897017 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7245 16:31:10.897137
7246 16:31:10.900222 [CATrainingPosCal] consider 1 rank data
7247 16:31:10.903863 u2DelayCellTimex100 = 266/100 ps
7248 16:31:10.910028 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7249 16:31:10.913432 CA1 delay=41 (11~72),Diff = 6 PI (22 cell)
7250 16:31:10.916849 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7251 16:31:10.919913 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7252 16:31:10.923343 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7253 16:31:10.926722 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7254 16:31:10.926858
7255 16:31:10.930034 CA PerBit enable=1, Macro0, CA PI delay=35
7256 16:31:10.930147
7257 16:31:10.933382 [CBTSetCACLKResult] CA Dly = 35
7258 16:31:10.936799 CS Dly: 11 (0~42)
7259 16:31:10.939677 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7260 16:31:10.943286 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7261 16:31:10.943388 ==
7262 16:31:10.946664 Dram Type= 6, Freq= 0, CH_0, rank 1
7263 16:31:10.953304 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7264 16:31:10.953402 ==
7265 16:31:10.956342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7266 16:31:10.959698 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7267 16:31:10.966169 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7268 16:31:10.973011 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7269 16:31:10.979777 [CA 0] Center 42 (12~73) winsize 62
7270 16:31:10.983035 [CA 1] Center 41 (11~72) winsize 62
7271 16:31:10.986585 [CA 2] Center 38 (8~68) winsize 61
7272 16:31:10.989523 [CA 3] Center 37 (7~67) winsize 61
7273 16:31:10.992904 [CA 4] Center 35 (5~65) winsize 61
7274 16:31:10.996300 [CA 5] Center 35 (5~66) winsize 62
7275 16:31:10.996402
7276 16:31:10.999824 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7277 16:31:10.999902
7278 16:31:11.002984 [CATrainingPosCal] consider 2 rank data
7279 16:31:11.006296 u2DelayCellTimex100 = 266/100 ps
7280 16:31:11.009590 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7281 16:31:11.016243 CA1 delay=41 (11~72),Diff = 6 PI (22 cell)
7282 16:31:11.019339 CA2 delay=38 (8~68),Diff = 3 PI (11 cell)
7283 16:31:11.022704 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7284 16:31:11.026204 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7285 16:31:11.029516 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7286 16:31:11.029595
7287 16:31:11.032871 CA PerBit enable=1, Macro0, CA PI delay=35
7288 16:31:11.032967
7289 16:31:11.036346 [CBTSetCACLKResult] CA Dly = 35
7290 16:31:11.039772 CS Dly: 11 (0~43)
7291 16:31:11.043156 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7292 16:31:11.046383 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7293 16:31:11.046478
7294 16:31:11.049430 ----->DramcWriteLeveling(PI) begin...
7295 16:31:11.049500 ==
7296 16:31:11.052792 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 16:31:11.056164 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7298 16:31:11.059657 ==
7299 16:31:11.059736 Write leveling (Byte 0): 30 => 30
7300 16:31:11.062587 Write leveling (Byte 1): 26 => 26
7301 16:31:11.065800 DramcWriteLeveling(PI) end<-----
7302 16:31:11.065878
7303 16:31:11.065935 ==
7304 16:31:11.069334 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 16:31:11.075925 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7306 16:31:11.076003 ==
7307 16:31:11.076067 [Gating] SW mode calibration
7308 16:31:11.085972 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7309 16:31:11.089215 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7310 16:31:11.096080 0 12 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7311 16:31:11.099201 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7312 16:31:11.102791 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7313 16:31:11.109180 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7314 16:31:11.112488 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7315 16:31:11.116142 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7316 16:31:11.123045 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 16:31:11.125804 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7318 16:31:11.129168 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7319 16:31:11.132583 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7320 16:31:11.138885 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7321 16:31:11.142285 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7322 16:31:11.145869 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7323 16:31:11.152152 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7324 16:31:11.155821 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7325 16:31:11.159280 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 16:31:11.165702 0 14 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7327 16:31:11.168942 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7328 16:31:11.172722 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7329 16:31:11.178917 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 16:31:11.182547 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7331 16:31:11.186067 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7332 16:31:11.192399 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 16:31:11.195773 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7334 16:31:11.198854 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 16:31:11.205544 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7336 16:31:11.209142 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7337 16:31:11.211965 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 16:31:11.218824 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 16:31:11.222295 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 16:31:11.225567 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 16:31:11.231931 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 16:31:11.235422 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 16:31:11.238841 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 16:31:11.245333 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 16:31:11.248375 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 16:31:11.252191 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 16:31:11.258328 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 16:31:11.261980 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 16:31:11.264768 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7350 16:31:11.271851 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7351 16:31:11.274640 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7352 16:31:11.278539 Total UI for P1: 0, mck2ui 16
7353 16:31:11.281560 best dqsien dly found for B0: ( 1, 0, 30)
7354 16:31:11.284930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7355 16:31:11.287867 Total UI for P1: 0, mck2ui 16
7356 16:31:11.291421 best dqsien dly found for B1: ( 1, 1, 2)
7357 16:31:11.294393 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7358 16:31:11.298048 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7359 16:31:11.298135
7360 16:31:11.304361 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7361 16:31:11.307653 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7362 16:31:11.307736 [Gating] SW calibration Done
7363 16:31:11.310821 ==
7364 16:31:11.310906 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 16:31:11.317968 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 16:31:11.318067 ==
7367 16:31:11.318128 RX Vref Scan: 0
7368 16:31:11.318182
7369 16:31:11.320867 RX Vref 0 -> 0, step: 1
7370 16:31:11.320928
7371 16:31:11.324095 RX Delay 0 -> 252, step: 8
7372 16:31:11.328067 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7373 16:31:11.331041 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7374 16:31:11.334357 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7375 16:31:11.340996 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7376 16:31:11.343950 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7377 16:31:11.347474 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7378 16:31:11.350861 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7379 16:31:11.353809 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7380 16:31:11.360500 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7381 16:31:11.363921 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7382 16:31:11.367470 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7383 16:31:11.370330 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7384 16:31:11.373863 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7385 16:31:11.380355 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7386 16:31:11.383558 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7387 16:31:11.387192 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7388 16:31:11.387268 ==
7389 16:31:11.390716 Dram Type= 6, Freq= 0, CH_0, rank 0
7390 16:31:11.393584 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7391 16:31:11.397069 ==
7392 16:31:11.397138 DQS Delay:
7393 16:31:11.397196 DQS0 = 0, DQS1 = 0
7394 16:31:11.400544 DQM Delay:
7395 16:31:11.400611 DQM0 = 130, DQM1 = 124
7396 16:31:11.403485 DQ Delay:
7397 16:31:11.406969 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7398 16:31:11.410628 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7399 16:31:11.413423 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7400 16:31:11.416804 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7401 16:31:11.416888
7402 16:31:11.416953
7403 16:31:11.417013 ==
7404 16:31:11.420459 Dram Type= 6, Freq= 0, CH_0, rank 0
7405 16:31:11.423291 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7406 16:31:11.426528 ==
7407 16:31:11.426663
7408 16:31:11.426781
7409 16:31:11.426880 TX Vref Scan disable
7410 16:31:11.430174 == TX Byte 0 ==
7411 16:31:11.433496 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7412 16:31:11.437000 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7413 16:31:11.440007 == TX Byte 1 ==
7414 16:31:11.443761 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7415 16:31:11.446890 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7416 16:31:11.449846 ==
7417 16:31:11.449959 Dram Type= 6, Freq= 0, CH_0, rank 0
7418 16:31:11.456450 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7419 16:31:11.456563 ==
7420 16:31:11.468896
7421 16:31:11.472030 TX Vref early break, caculate TX vref
7422 16:31:11.475421 TX Vref=16, minBit 9, minWin=21, winSum=368
7423 16:31:11.478368 TX Vref=18, minBit 8, minWin=22, winSum=378
7424 16:31:11.481992 TX Vref=20, minBit 8, minWin=23, winSum=387
7425 16:31:11.485357 TX Vref=22, minBit 8, minWin=23, winSum=393
7426 16:31:11.488259 TX Vref=24, minBit 8, minWin=23, winSum=404
7427 16:31:11.495274 TX Vref=26, minBit 3, minWin=25, winSum=413
7428 16:31:11.498294 TX Vref=28, minBit 3, minWin=25, winSum=414
7429 16:31:11.501708 TX Vref=30, minBit 0, minWin=25, winSum=410
7430 16:31:11.505323 TX Vref=32, minBit 6, minWin=24, winSum=401
7431 16:31:11.508224 TX Vref=34, minBit 8, minWin=23, winSum=390
7432 16:31:11.515164 [TxChooseVref] Worse bit 3, Min win 25, Win sum 414, Final Vref 28
7433 16:31:11.515248
7434 16:31:11.518081 Final TX Range 0 Vref 28
7435 16:31:11.518154
7436 16:31:11.518234 ==
7437 16:31:11.521729 Dram Type= 6, Freq= 0, CH_0, rank 0
7438 16:31:11.525028 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7439 16:31:11.525103 ==
7440 16:31:11.525162
7441 16:31:11.525223
7442 16:31:11.528131 TX Vref Scan disable
7443 16:31:11.534836 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7444 16:31:11.534951 == TX Byte 0 ==
7445 16:31:11.538159 u2DelayCellOfst[0]=11 cells (3 PI)
7446 16:31:11.541586 u2DelayCellOfst[1]=18 cells (5 PI)
7447 16:31:11.544959 u2DelayCellOfst[2]=11 cells (3 PI)
7448 16:31:11.547983 u2DelayCellOfst[3]=11 cells (3 PI)
7449 16:31:11.551287 u2DelayCellOfst[4]=7 cells (2 PI)
7450 16:31:11.554567 u2DelayCellOfst[5]=0 cells (0 PI)
7451 16:31:11.558427 u2DelayCellOfst[6]=18 cells (5 PI)
7452 16:31:11.561359 u2DelayCellOfst[7]=18 cells (5 PI)
7453 16:31:11.564640 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7454 16:31:11.568086 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7455 16:31:11.571435 == TX Byte 1 ==
7456 16:31:11.571515 u2DelayCellOfst[8]=3 cells (1 PI)
7457 16:31:11.574689 u2DelayCellOfst[9]=0 cells (0 PI)
7458 16:31:11.578304 u2DelayCellOfst[10]=11 cells (3 PI)
7459 16:31:11.581145 u2DelayCellOfst[11]=3 cells (1 PI)
7460 16:31:11.584799 u2DelayCellOfst[12]=18 cells (5 PI)
7461 16:31:11.588228 u2DelayCellOfst[13]=18 cells (5 PI)
7462 16:31:11.591468 u2DelayCellOfst[14]=18 cells (5 PI)
7463 16:31:11.594576 u2DelayCellOfst[15]=14 cells (4 PI)
7464 16:31:11.598050 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7465 16:31:11.604586 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7466 16:31:11.604667 DramC Write-DBI on
7467 16:31:11.604727 ==
7468 16:31:11.607962 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 16:31:11.614321 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7470 16:31:11.614412 ==
7471 16:31:11.614473
7472 16:31:11.614528
7473 16:31:11.614580 TX Vref Scan disable
7474 16:31:11.618000 == TX Byte 0 ==
7475 16:31:11.621594 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7476 16:31:11.624584 == TX Byte 1 ==
7477 16:31:11.628228 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7478 16:31:11.631169 DramC Write-DBI off
7479 16:31:11.631248
7480 16:31:11.631308 [DATLAT]
7481 16:31:11.631363 Freq=1600, CH0 RK0
7482 16:31:11.631417
7483 16:31:11.634567 DATLAT Default: 0xf
7484 16:31:11.634668 0, 0xFFFF, sum = 0
7485 16:31:11.637903 1, 0xFFFF, sum = 0
7486 16:31:11.641251 2, 0xFFFF, sum = 0
7487 16:31:11.641328 3, 0xFFFF, sum = 0
7488 16:31:11.644482 4, 0xFFFF, sum = 0
7489 16:31:11.644586 5, 0xFFFF, sum = 0
7490 16:31:11.647546 6, 0xFFFF, sum = 0
7491 16:31:11.647651 7, 0xFFFF, sum = 0
7492 16:31:11.651647 8, 0xFFFF, sum = 0
7493 16:31:11.651726 9, 0xFFFF, sum = 0
7494 16:31:11.654332 10, 0xFFFF, sum = 0
7495 16:31:11.654398 11, 0xFFFF, sum = 0
7496 16:31:11.657526 12, 0xBFF, sum = 0
7497 16:31:11.657595 13, 0x0, sum = 1
7498 16:31:11.661305 14, 0x0, sum = 2
7499 16:31:11.661379 15, 0x0, sum = 3
7500 16:31:11.664075 16, 0x0, sum = 4
7501 16:31:11.664147 best_step = 14
7502 16:31:11.664204
7503 16:31:11.664258 ==
7504 16:31:11.667602 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 16:31:11.674672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7506 16:31:11.674792 ==
7507 16:31:11.674854 RX Vref Scan: 1
7508 16:31:11.674927
7509 16:31:11.677572 Set Vref Range= 24 -> 127
7510 16:31:11.677648
7511 16:31:11.680793 RX Vref 24 -> 127, step: 1
7512 16:31:11.680898
7513 16:31:11.680956 RX Delay 11 -> 252, step: 4
7514 16:31:11.681011
7515 16:31:11.684042 Set Vref, RX VrefLevel [Byte0]: 24
7516 16:31:11.687655 [Byte1]: 24
7517 16:31:11.691681
7518 16:31:11.691753 Set Vref, RX VrefLevel [Byte0]: 25
7519 16:31:11.694713 [Byte1]: 25
7520 16:31:11.699344
7521 16:31:11.699415 Set Vref, RX VrefLevel [Byte0]: 26
7522 16:31:11.702124 [Byte1]: 26
7523 16:31:11.706771
7524 16:31:11.706855 Set Vref, RX VrefLevel [Byte0]: 27
7525 16:31:11.710106 [Byte1]: 27
7526 16:31:11.714085
7527 16:31:11.714156 Set Vref, RX VrefLevel [Byte0]: 28
7528 16:31:11.717746 [Byte1]: 28
7529 16:31:11.722149
7530 16:31:11.722229 Set Vref, RX VrefLevel [Byte0]: 29
7531 16:31:11.725101 [Byte1]: 29
7532 16:31:11.729589
7533 16:31:11.729682 Set Vref, RX VrefLevel [Byte0]: 30
7534 16:31:11.732543 [Byte1]: 30
7535 16:31:11.737295
7536 16:31:11.737378 Set Vref, RX VrefLevel [Byte0]: 31
7537 16:31:11.739997 [Byte1]: 31
7538 16:31:11.744585
7539 16:31:11.744688 Set Vref, RX VrefLevel [Byte0]: 32
7540 16:31:11.747995 [Byte1]: 32
7541 16:31:11.752284
7542 16:31:11.752378 Set Vref, RX VrefLevel [Byte0]: 33
7543 16:31:11.755749 [Byte1]: 33
7544 16:31:11.759701
7545 16:31:11.759789 Set Vref, RX VrefLevel [Byte0]: 34
7546 16:31:11.763176 [Byte1]: 34
7547 16:31:11.767376
7548 16:31:11.767464 Set Vref, RX VrefLevel [Byte0]: 35
7549 16:31:11.770768 [Byte1]: 35
7550 16:31:11.775599
7551 16:31:11.775705 Set Vref, RX VrefLevel [Byte0]: 36
7552 16:31:11.778561 [Byte1]: 36
7553 16:31:11.782882
7554 16:31:11.782964 Set Vref, RX VrefLevel [Byte0]: 37
7555 16:31:11.785977 [Byte1]: 37
7556 16:31:11.790446
7557 16:31:11.790527 Set Vref, RX VrefLevel [Byte0]: 38
7558 16:31:11.793852 [Byte1]: 38
7559 16:31:11.798070
7560 16:31:11.798145 Set Vref, RX VrefLevel [Byte0]: 39
7561 16:31:11.801516 [Byte1]: 39
7562 16:31:11.805584
7563 16:31:11.805685 Set Vref, RX VrefLevel [Byte0]: 40
7564 16:31:11.808656 [Byte1]: 40
7565 16:31:11.812923
7566 16:31:11.813004 Set Vref, RX VrefLevel [Byte0]: 41
7567 16:31:11.816220 [Byte1]: 41
7568 16:31:11.820869
7569 16:31:11.820942 Set Vref, RX VrefLevel [Byte0]: 42
7570 16:31:11.824011 [Byte1]: 42
7571 16:31:11.828226
7572 16:31:11.828296 Set Vref, RX VrefLevel [Byte0]: 43
7573 16:31:11.831714 [Byte1]: 43
7574 16:31:11.835851
7575 16:31:11.835934 Set Vref, RX VrefLevel [Byte0]: 44
7576 16:31:11.839237 [Byte1]: 44
7577 16:31:11.843340
7578 16:31:11.843417 Set Vref, RX VrefLevel [Byte0]: 45
7579 16:31:11.846625 [Byte1]: 45
7580 16:31:11.851219
7581 16:31:11.851301 Set Vref, RX VrefLevel [Byte0]: 46
7582 16:31:11.854771 [Byte1]: 46
7583 16:31:11.858670
7584 16:31:11.858786 Set Vref, RX VrefLevel [Byte0]: 47
7585 16:31:11.862239 [Byte1]: 47
7586 16:31:11.866347
7587 16:31:11.866463 Set Vref, RX VrefLevel [Byte0]: 48
7588 16:31:11.869808 [Byte1]: 48
7589 16:31:11.873719
7590 16:31:11.873807 Set Vref, RX VrefLevel [Byte0]: 49
7591 16:31:11.877140 [Byte1]: 49
7592 16:31:11.881780
7593 16:31:11.881868 Set Vref, RX VrefLevel [Byte0]: 50
7594 16:31:11.885116 [Byte1]: 50
7595 16:31:11.889428
7596 16:31:11.889504 Set Vref, RX VrefLevel [Byte0]: 51
7597 16:31:11.892351 [Byte1]: 51
7598 16:31:11.896848
7599 16:31:11.896921 Set Vref, RX VrefLevel [Byte0]: 52
7600 16:31:11.899978 [Byte1]: 52
7601 16:31:11.904301
7602 16:31:11.904385 Set Vref, RX VrefLevel [Byte0]: 53
7603 16:31:11.907977 [Byte1]: 53
7604 16:31:11.912035
7605 16:31:11.912112 Set Vref, RX VrefLevel [Byte0]: 54
7606 16:31:11.915175 [Byte1]: 54
7607 16:31:11.919660
7608 16:31:11.919732 Set Vref, RX VrefLevel [Byte0]: 55
7609 16:31:11.922760 [Byte1]: 55
7610 16:31:11.927272
7611 16:31:11.927345 Set Vref, RX VrefLevel [Byte0]: 56
7612 16:31:11.930768 [Byte1]: 56
7613 16:31:11.934839
7614 16:31:11.934922 Set Vref, RX VrefLevel [Byte0]: 57
7615 16:31:11.938204 [Byte1]: 57
7616 16:31:11.942345
7617 16:31:11.942428 Set Vref, RX VrefLevel [Byte0]: 58
7618 16:31:11.945877 [Byte1]: 58
7619 16:31:11.949907
7620 16:31:11.949990 Set Vref, RX VrefLevel [Byte0]: 59
7621 16:31:11.953211 [Byte1]: 59
7622 16:31:11.957848
7623 16:31:11.957927 Set Vref, RX VrefLevel [Byte0]: 60
7624 16:31:11.961347 [Byte1]: 60
7625 16:31:11.965824
7626 16:31:11.965907 Set Vref, RX VrefLevel [Byte0]: 61
7627 16:31:11.968432 [Byte1]: 61
7628 16:31:11.972821
7629 16:31:11.972912 Set Vref, RX VrefLevel [Byte0]: 62
7630 16:31:11.976197 [Byte1]: 62
7631 16:31:11.980794
7632 16:31:11.980871 Set Vref, RX VrefLevel [Byte0]: 63
7633 16:31:11.983920 [Byte1]: 63
7634 16:31:11.988248
7635 16:31:11.988326 Set Vref, RX VrefLevel [Byte0]: 64
7636 16:31:11.991830 [Byte1]: 64
7637 16:31:11.996065
7638 16:31:11.996146 Set Vref, RX VrefLevel [Byte0]: 65
7639 16:31:11.999005 [Byte1]: 65
7640 16:31:12.003554
7641 16:31:12.003629 Set Vref, RX VrefLevel [Byte0]: 66
7642 16:31:12.006774 [Byte1]: 66
7643 16:31:12.011226
7644 16:31:12.011296 Set Vref, RX VrefLevel [Byte0]: 67
7645 16:31:12.014388 [Byte1]: 67
7646 16:31:12.018893
7647 16:31:12.018973 Set Vref, RX VrefLevel [Byte0]: 68
7648 16:31:12.021802 [Byte1]: 68
7649 16:31:12.026091
7650 16:31:12.026191 Set Vref, RX VrefLevel [Byte0]: 69
7651 16:31:12.029407 [Byte1]: 69
7652 16:31:12.033874
7653 16:31:12.033955 Set Vref, RX VrefLevel [Byte0]: 70
7654 16:31:12.036971 [Byte1]: 70
7655 16:31:12.041664
7656 16:31:12.041752 Set Vref, RX VrefLevel [Byte0]: 71
7657 16:31:12.044585 [Byte1]: 71
7658 16:31:12.049218
7659 16:31:12.049295 Final RX Vref Byte 0 = 53 to rank0
7660 16:31:12.052308 Final RX Vref Byte 1 = 56 to rank0
7661 16:31:12.055642 Final RX Vref Byte 0 = 53 to rank1
7662 16:31:12.059104 Final RX Vref Byte 1 = 56 to rank1==
7663 16:31:12.062437 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 16:31:12.069177 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7665 16:31:12.069264 ==
7666 16:31:12.069326 DQS Delay:
7667 16:31:12.072031 DQS0 = 0, DQS1 = 0
7668 16:31:12.072110 DQM Delay:
7669 16:31:12.072172 DQM0 = 126, DQM1 = 120
7670 16:31:12.075522 DQ Delay:
7671 16:31:12.079043 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7672 16:31:12.081949 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7673 16:31:12.085759 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7674 16:31:12.089016 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =132
7675 16:31:12.089096
7676 16:31:12.089156
7677 16:31:12.089211
7678 16:31:12.092113 [DramC_TX_OE_Calibration] TA2
7679 16:31:12.095968 Original DQ_B0 (3 6) =30, OEN = 27
7680 16:31:12.099069 Original DQ_B1 (3 6) =30, OEN = 27
7681 16:31:12.102380 24, 0x0, End_B0=24 End_B1=24
7682 16:31:12.102463 25, 0x0, End_B0=25 End_B1=25
7683 16:31:12.105227 26, 0x0, End_B0=26 End_B1=26
7684 16:31:12.108747 27, 0x0, End_B0=27 End_B1=27
7685 16:31:12.112003 28, 0x0, End_B0=28 End_B1=28
7686 16:31:12.115321 29, 0x0, End_B0=29 End_B1=29
7687 16:31:12.115405 30, 0x0, End_B0=30 End_B1=30
7688 16:31:12.118417 31, 0x4141, End_B0=30 End_B1=30
7689 16:31:12.121916 Byte0 end_step=30 best_step=27
7690 16:31:12.125195 Byte1 end_step=30 best_step=27
7691 16:31:12.128581 Byte0 TX OE(2T, 0.5T) = (3, 3)
7692 16:31:12.131870 Byte1 TX OE(2T, 0.5T) = (3, 3)
7693 16:31:12.131941
7694 16:31:12.132000
7695 16:31:12.138655 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7696 16:31:12.141724 CH0 RK0: MR19=303, MR18=1B1B
7697 16:31:12.148303 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7698 16:31:12.148385
7699 16:31:12.151690 ----->DramcWriteLeveling(PI) begin...
7700 16:31:12.151763 ==
7701 16:31:12.155102 Dram Type= 6, Freq= 0, CH_0, rank 1
7702 16:31:12.158624 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7703 16:31:12.158697 ==
7704 16:31:12.161379 Write leveling (Byte 0): 29 => 29
7705 16:31:12.165083 Write leveling (Byte 1): 27 => 27
7706 16:31:12.168047 DramcWriteLeveling(PI) end<-----
7707 16:31:12.168118
7708 16:31:12.168176 ==
7709 16:31:12.171621 Dram Type= 6, Freq= 0, CH_0, rank 1
7710 16:31:12.175102 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7711 16:31:12.175175 ==
7712 16:31:12.178035 [Gating] SW mode calibration
7713 16:31:12.184550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7714 16:31:12.191420 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7715 16:31:12.194987 0 12 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7716 16:31:12.201767 0 12 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7717 16:31:12.204540 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7718 16:31:12.208298 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7719 16:31:12.214989 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7720 16:31:12.217885 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 16:31:12.221447 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7722 16:31:12.228041 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7723 16:31:12.231230 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
7724 16:31:12.234254 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7725 16:31:12.241440 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7726 16:31:12.244509 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 16:31:12.247950 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7728 16:31:12.254422 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7729 16:31:12.257421 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 16:31:12.261123 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7731 16:31:12.267594 0 14 0 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7732 16:31:12.271008 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7733 16:31:12.273994 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 16:31:12.280972 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 16:31:12.284091 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7736 16:31:12.287326 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 16:31:12.294139 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 16:31:12.297524 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 16:31:12.300773 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7740 16:31:12.304214 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7741 16:31:12.310474 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7742 16:31:12.313515 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 16:31:12.320336 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 16:31:12.323366 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 16:31:12.326886 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 16:31:12.330359 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 16:31:12.336520 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 16:31:12.339784 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 16:31:12.343701 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 16:31:12.350219 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 16:31:12.353513 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 16:31:12.356425 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 16:31:12.362941 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7754 16:31:12.366496 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7755 16:31:12.369664 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7756 16:31:12.376256 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7757 16:31:12.379697 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 16:31:12.383337 Total UI for P1: 0, mck2ui 16
7759 16:31:12.386747 best dqsien dly found for B0: ( 1, 0, 30)
7760 16:31:12.389749 Total UI for P1: 0, mck2ui 16
7761 16:31:12.393047 best dqsien dly found for B1: ( 1, 1, 2)
7762 16:31:12.396840 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7763 16:31:12.399907 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7764 16:31:12.400001
7765 16:31:12.402881 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7766 16:31:12.406320 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7767 16:31:12.409647 [Gating] SW calibration Done
7768 16:31:12.409718 ==
7769 16:31:12.413147 Dram Type= 6, Freq= 0, CH_0, rank 1
7770 16:31:12.419422 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7771 16:31:12.419498 ==
7772 16:31:12.419558 RX Vref Scan: 0
7773 16:31:12.419614
7774 16:31:12.423071 RX Vref 0 -> 0, step: 1
7775 16:31:12.423149
7776 16:31:12.426449 RX Delay 0 -> 252, step: 8
7777 16:31:12.429524 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7778 16:31:12.432766 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7779 16:31:12.436214 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7780 16:31:12.439824 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7781 16:31:12.445846 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7782 16:31:12.449113 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7783 16:31:12.452825 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7784 16:31:12.456289 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7785 16:31:12.459039 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7786 16:31:12.465993 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7787 16:31:12.468834 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7788 16:31:12.472641 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7789 16:31:12.475672 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7790 16:31:12.482149 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7791 16:31:12.485342 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7792 16:31:12.488972 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7793 16:31:12.489052 ==
7794 16:31:12.492304 Dram Type= 6, Freq= 0, CH_0, rank 1
7795 16:31:12.495748 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7796 16:31:12.495828 ==
7797 16:31:12.498829 DQS Delay:
7798 16:31:12.498907 DQS0 = 0, DQS1 = 0
7799 16:31:12.502040 DQM Delay:
7800 16:31:12.502142 DQM0 = 130, DQM1 = 124
7801 16:31:12.502236 DQ Delay:
7802 16:31:12.505546 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7803 16:31:12.511919 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7804 16:31:12.515214 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7805 16:31:12.518660 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7806 16:31:12.518740
7807 16:31:12.518801
7808 16:31:12.518858 ==
7809 16:31:12.522162 Dram Type= 6, Freq= 0, CH_0, rank 1
7810 16:31:12.525027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7811 16:31:12.525108 ==
7812 16:31:12.525169
7813 16:31:12.525226
7814 16:31:12.528661 TX Vref Scan disable
7815 16:31:12.531927 == TX Byte 0 ==
7816 16:31:12.534974 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7817 16:31:12.538387 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7818 16:31:12.541797 == TX Byte 1 ==
7819 16:31:12.545002 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7820 16:31:12.548452 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7821 16:31:12.548533 ==
7822 16:31:12.551838 Dram Type= 6, Freq= 0, CH_0, rank 1
7823 16:31:12.554877 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7824 16:31:12.558242 ==
7825 16:31:12.570618
7826 16:31:12.574071 TX Vref early break, caculate TX vref
7827 16:31:12.577440 TX Vref=16, minBit 9, minWin=21, winSum=373
7828 16:31:12.580856 TX Vref=18, minBit 11, minWin=22, winSum=387
7829 16:31:12.583698 TX Vref=20, minBit 11, minWin=22, winSum=394
7830 16:31:12.587009 TX Vref=22, minBit 1, minWin=24, winSum=399
7831 16:31:12.590524 TX Vref=24, minBit 1, minWin=24, winSum=408
7832 16:31:12.597207 TX Vref=26, minBit 8, minWin=24, winSum=415
7833 16:31:12.600559 TX Vref=28, minBit 1, minWin=24, winSum=413
7834 16:31:12.603866 TX Vref=30, minBit 0, minWin=25, winSum=413
7835 16:31:12.607004 TX Vref=32, minBit 7, minWin=24, winSum=405
7836 16:31:12.610345 TX Vref=34, minBit 8, minWin=23, winSum=398
7837 16:31:12.616681 TX Vref=36, minBit 1, minWin=23, winSum=389
7838 16:31:12.619987 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 30
7839 16:31:12.620066
7840 16:31:12.623673 Final TX Range 0 Vref 30
7841 16:31:12.623754
7842 16:31:12.623815 ==
7843 16:31:12.626672 Dram Type= 6, Freq= 0, CH_0, rank 1
7844 16:31:12.629928 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7845 16:31:12.633425 ==
7846 16:31:12.633504
7847 16:31:12.633565
7848 16:31:12.633636 TX Vref Scan disable
7849 16:31:12.640140 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7850 16:31:12.640234 == TX Byte 0 ==
7851 16:31:12.643274 u2DelayCellOfst[0]=14 cells (4 PI)
7852 16:31:12.646942 u2DelayCellOfst[1]=18 cells (5 PI)
7853 16:31:12.650185 u2DelayCellOfst[2]=14 cells (4 PI)
7854 16:31:12.653267 u2DelayCellOfst[3]=14 cells (4 PI)
7855 16:31:12.656452 u2DelayCellOfst[4]=11 cells (3 PI)
7856 16:31:12.659920 u2DelayCellOfst[5]=0 cells (0 PI)
7857 16:31:12.663564 u2DelayCellOfst[6]=22 cells (6 PI)
7858 16:31:12.666767 u2DelayCellOfst[7]=18 cells (5 PI)
7859 16:31:12.669674 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7860 16:31:12.673238 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7861 16:31:12.676246 == TX Byte 1 ==
7862 16:31:12.679780 u2DelayCellOfst[8]=3 cells (1 PI)
7863 16:31:12.683224 u2DelayCellOfst[9]=0 cells (0 PI)
7864 16:31:12.686217 u2DelayCellOfst[10]=11 cells (3 PI)
7865 16:31:12.689723 u2DelayCellOfst[11]=7 cells (2 PI)
7866 16:31:12.693020 u2DelayCellOfst[12]=14 cells (4 PI)
7867 16:31:12.696856 u2DelayCellOfst[13]=14 cells (4 PI)
7868 16:31:12.696934 u2DelayCellOfst[14]=18 cells (5 PI)
7869 16:31:12.699787 u2DelayCellOfst[15]=14 cells (4 PI)
7870 16:31:12.706964 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7871 16:31:12.709422 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7872 16:31:12.712730 DramC Write-DBI on
7873 16:31:12.712807 ==
7874 16:31:12.716193 Dram Type= 6, Freq= 0, CH_0, rank 1
7875 16:31:12.719334 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7876 16:31:12.719413 ==
7877 16:31:12.719473
7878 16:31:12.719529
7879 16:31:12.722675 TX Vref Scan disable
7880 16:31:12.722778 == TX Byte 0 ==
7881 16:31:12.729603 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7882 16:31:12.729682 == TX Byte 1 ==
7883 16:31:12.732574 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7884 16:31:12.736055 DramC Write-DBI off
7885 16:31:12.736133
7886 16:31:12.736195 [DATLAT]
7887 16:31:12.739079 Freq=1600, CH0 RK1
7888 16:31:12.739159
7889 16:31:12.739220 DATLAT Default: 0xe
7890 16:31:12.742586 0, 0xFFFF, sum = 0
7891 16:31:12.742666 1, 0xFFFF, sum = 0
7892 16:31:12.745934 2, 0xFFFF, sum = 0
7893 16:31:12.746045 3, 0xFFFF, sum = 0
7894 16:31:12.749254 4, 0xFFFF, sum = 0
7895 16:31:12.749351 5, 0xFFFF, sum = 0
7896 16:31:12.752515 6, 0xFFFF, sum = 0
7897 16:31:12.755869 7, 0xFFFF, sum = 0
7898 16:31:12.755951 8, 0xFFFF, sum = 0
7899 16:31:12.759026 9, 0xFFFF, sum = 0
7900 16:31:12.759108 10, 0xFFFF, sum = 0
7901 16:31:12.762244 11, 0xFFFF, sum = 0
7902 16:31:12.762326 12, 0x8FFF, sum = 0
7903 16:31:12.765766 13, 0x0, sum = 1
7904 16:31:12.765847 14, 0x0, sum = 2
7905 16:31:12.769184 15, 0x0, sum = 3
7906 16:31:12.769265 16, 0x0, sum = 4
7907 16:31:12.772850 best_step = 14
7908 16:31:12.772929
7909 16:31:12.772990 ==
7910 16:31:12.775701 Dram Type= 6, Freq= 0, CH_0, rank 1
7911 16:31:12.779248 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7912 16:31:12.779358 ==
7913 16:31:12.779427 RX Vref Scan: 0
7914 16:31:12.779484
7915 16:31:12.782194 RX Vref 0 -> 0, step: 1
7916 16:31:12.782282
7917 16:31:12.785860 RX Delay 11 -> 252, step: 4
7918 16:31:12.788867 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7919 16:31:12.795368 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
7920 16:31:12.798849 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7921 16:31:12.802003 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7922 16:31:12.805287 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7923 16:31:12.808825 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7924 16:31:12.815372 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7925 16:31:12.818601 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7926 16:31:12.821793 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7927 16:31:12.825666 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7928 16:31:12.828881 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7929 16:31:12.835323 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7930 16:31:12.838854 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7931 16:31:12.841979 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7932 16:31:12.845655 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7933 16:31:12.852015 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7934 16:31:12.852111 ==
7935 16:31:12.855198 Dram Type= 6, Freq= 0, CH_0, rank 1
7936 16:31:12.858398 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7937 16:31:12.858477 ==
7938 16:31:12.858538 DQS Delay:
7939 16:31:12.861603 DQS0 = 0, DQS1 = 0
7940 16:31:12.861681 DQM Delay:
7941 16:31:12.864954 DQM0 = 128, DQM1 = 120
7942 16:31:12.865032 DQ Delay:
7943 16:31:12.868185 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
7944 16:31:12.871552 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7945 16:31:12.874967 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7946 16:31:12.878163 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7947 16:31:12.878264
7948 16:31:12.878340
7949 16:31:12.881336
7950 16:31:12.881438 [DramC_TX_OE_Calibration] TA2
7951 16:31:12.884933 Original DQ_B0 (3 6) =30, OEN = 27
7952 16:31:12.887955 Original DQ_B1 (3 6) =30, OEN = 27
7953 16:31:12.891566 24, 0x0, End_B0=24 End_B1=24
7954 16:31:12.894992 25, 0x0, End_B0=25 End_B1=25
7955 16:31:12.897993 26, 0x0, End_B0=26 End_B1=26
7956 16:31:12.898097 27, 0x0, End_B0=27 End_B1=27
7957 16:31:12.901515 28, 0x0, End_B0=28 End_B1=28
7958 16:31:12.904463 29, 0x0, End_B0=29 End_B1=29
7959 16:31:12.907990 30, 0x0, End_B0=30 End_B1=30
7960 16:31:12.911041 31, 0x4141, End_B0=30 End_B1=30
7961 16:31:12.911121 Byte0 end_step=30 best_step=27
7962 16:31:12.914493 Byte1 end_step=30 best_step=27
7963 16:31:12.918410 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 16:31:12.921190 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 16:31:12.921288
7966 16:31:12.921378
7967 16:31:12.927890 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7968 16:31:12.931403 CH0 RK1: MR19=303, MR18=2323
7969 16:31:12.937731 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7970 16:31:12.940691 [RxdqsGatingPostProcess] freq 1600
7971 16:31:12.947414 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7972 16:31:12.950904 Pre-setting of DQS Precalculation
7973 16:31:12.954464 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7974 16:31:12.954565 ==
7975 16:31:12.957367 Dram Type= 6, Freq= 0, CH_1, rank 0
7976 16:31:12.960771 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7977 16:31:12.963950 ==
7978 16:31:12.967395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7979 16:31:12.970498 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7980 16:31:12.976981 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7981 16:31:12.983673 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7982 16:31:12.990036 [CA 0] Center 41 (11~72) winsize 62
7983 16:31:12.993693 [CA 1] Center 41 (10~72) winsize 63
7984 16:31:12.996793 [CA 2] Center 37 (8~67) winsize 60
7985 16:31:13.000385 [CA 3] Center 36 (6~66) winsize 61
7986 16:31:13.003244 [CA 4] Center 34 (4~64) winsize 61
7987 16:31:13.006756 [CA 5] Center 34 (4~64) winsize 61
7988 16:31:13.006849
7989 16:31:13.009897 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7990 16:31:13.009975
7991 16:31:13.013617 [CATrainingPosCal] consider 1 rank data
7992 16:31:13.016448 u2DelayCellTimex100 = 266/100 ps
7993 16:31:13.020091 CA0 delay=41 (11~72),Diff = 7 PI (25 cell)
7994 16:31:13.026822 CA1 delay=41 (10~72),Diff = 7 PI (25 cell)
7995 16:31:13.029699 CA2 delay=37 (8~67),Diff = 3 PI (11 cell)
7996 16:31:13.033206 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
7997 16:31:13.036235 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
7998 16:31:13.039869 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
7999 16:31:13.039948
8000 16:31:13.043242 CA PerBit enable=1, Macro0, CA PI delay=34
8001 16:31:13.043343
8002 16:31:13.046499 [CBTSetCACLKResult] CA Dly = 34
8003 16:31:13.049844 CS Dly: 8 (0~39)
8004 16:31:13.052936 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8005 16:31:13.056107 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8006 16:31:13.056186 ==
8007 16:31:13.059566 Dram Type= 6, Freq= 0, CH_1, rank 1
8008 16:31:13.065932 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8009 16:31:13.066013 ==
8010 16:31:13.069197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8011 16:31:13.076176 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8012 16:31:13.079138 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8013 16:31:13.085831 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8014 16:31:13.092627 [CA 0] Center 40 (10~70) winsize 61
8015 16:31:13.095774 [CA 1] Center 39 (9~70) winsize 62
8016 16:31:13.099575 [CA 2] Center 35 (6~65) winsize 60
8017 16:31:13.102417 [CA 3] Center 35 (6~65) winsize 60
8018 16:31:13.105721 [CA 4] Center 33 (4~63) winsize 60
8019 16:31:13.109336 [CA 5] Center 33 (4~62) winsize 59
8020 16:31:13.109415
8021 16:31:13.112268 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8022 16:31:13.112347
8023 16:31:13.116001 [CATrainingPosCal] consider 2 rank data
8024 16:31:13.119314 u2DelayCellTimex100 = 266/100 ps
8025 16:31:13.122176 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8026 16:31:13.129192 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8027 16:31:13.132733 CA2 delay=36 (8~65),Diff = 3 PI (11 cell)
8028 16:31:13.135572 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8029 16:31:13.139089 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8030 16:31:13.142569 CA5 delay=33 (4~62),Diff = 0 PI (0 cell)
8031 16:31:13.142648
8032 16:31:13.145412 CA PerBit enable=1, Macro0, CA PI delay=33
8033 16:31:13.145491
8034 16:31:13.149034 [CBTSetCACLKResult] CA Dly = 33
8035 16:31:13.152024 CS Dly: 9 (0~41)
8036 16:31:13.155544 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8037 16:31:13.159070 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8038 16:31:13.159150
8039 16:31:13.161864 ----->DramcWriteLeveling(PI) begin...
8040 16:31:13.161945 ==
8041 16:31:13.165299 Dram Type= 6, Freq= 0, CH_1, rank 0
8042 16:31:13.172072 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8043 16:31:13.172155 ==
8044 16:31:13.175327 Write leveling (Byte 0): 23 => 23
8045 16:31:13.175406 Write leveling (Byte 1): 23 => 23
8046 16:31:13.178546 DramcWriteLeveling(PI) end<-----
8047 16:31:13.178648
8048 16:31:13.178738 ==
8049 16:31:13.181969 Dram Type= 6, Freq= 0, CH_1, rank 0
8050 16:31:13.188838 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8051 16:31:13.188946 ==
8052 16:31:13.191909 [Gating] SW mode calibration
8053 16:31:13.198624 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8054 16:31:13.201812 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8055 16:31:13.208435 0 12 0 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
8056 16:31:13.211756 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8057 16:31:13.215166 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 16:31:13.222017 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 16:31:13.225085 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 16:31:13.228325 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 16:31:13.234793 0 12 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8062 16:31:13.238204 0 12 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
8063 16:31:13.241687 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8064 16:31:13.248097 0 13 4 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
8065 16:31:13.251761 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 16:31:13.254609 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 16:31:13.261561 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 16:31:13.264464 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 16:31:13.267981 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8070 16:31:13.274688 0 13 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8071 16:31:13.277519 0 14 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8072 16:31:13.281276 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 16:31:13.287766 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 16:31:13.291289 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 16:31:13.294269 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 16:31:13.300926 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 16:31:13.304194 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8078 16:31:13.307572 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8079 16:31:13.313863 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8080 16:31:13.317449 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 16:31:13.320531 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 16:31:13.327128 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 16:31:13.330735 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 16:31:13.333918 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 16:31:13.340410 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 16:31:13.343439 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 16:31:13.347060 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 16:31:13.353568 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 16:31:13.357131 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 16:31:13.360686 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 16:31:13.367146 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 16:31:13.370624 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 16:31:13.373515 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8094 16:31:13.380364 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 16:31:13.383348 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8096 16:31:13.386808 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8097 16:31:13.390389 Total UI for P1: 0, mck2ui 16
8098 16:31:13.393186 best dqsien dly found for B0: ( 1, 0, 28)
8099 16:31:13.396844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 16:31:13.403255 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 16:31:13.406524 Total UI for P1: 0, mck2ui 16
8102 16:31:13.409959 best dqsien dly found for B1: ( 1, 1, 4)
8103 16:31:13.413276 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8104 16:31:13.416945 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8105 16:31:13.417027
8106 16:31:13.419765 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8107 16:31:13.422764 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8108 16:31:13.426516 [Gating] SW calibration Done
8109 16:31:13.426623 ==
8110 16:31:13.429649 Dram Type= 6, Freq= 0, CH_1, rank 0
8111 16:31:13.433213 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8112 16:31:13.433315 ==
8113 16:31:13.436372 RX Vref Scan: 0
8114 16:31:13.436475
8115 16:31:13.439535 RX Vref 0 -> 0, step: 1
8116 16:31:13.439665
8117 16:31:13.439752 RX Delay 0 -> 252, step: 8
8118 16:31:13.446291 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8119 16:31:13.449754 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8120 16:31:13.452788 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8121 16:31:13.456105 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8122 16:31:13.459659 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8123 16:31:13.466174 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8124 16:31:13.469045 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8125 16:31:13.472552 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8126 16:31:13.475555 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8127 16:31:13.479280 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8128 16:31:13.485489 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8129 16:31:13.488980 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8130 16:31:13.492014 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8131 16:31:13.495465 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8132 16:31:13.502080 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8133 16:31:13.505612 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8134 16:31:13.505726 ==
8135 16:31:13.508913 Dram Type= 6, Freq= 0, CH_1, rank 0
8136 16:31:13.512270 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8137 16:31:13.512385 ==
8138 16:31:13.515342 DQS Delay:
8139 16:31:13.515441 DQS0 = 0, DQS1 = 0
8140 16:31:13.515527 DQM Delay:
8141 16:31:13.518948 DQM0 = 130, DQM1 = 125
8142 16:31:13.519049 DQ Delay:
8143 16:31:13.521767 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8144 16:31:13.525289 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8145 16:31:13.529003 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8146 16:31:13.535309 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8147 16:31:13.535417
8148 16:31:13.535505
8149 16:31:13.535588 ==
8150 16:31:13.538629 Dram Type= 6, Freq= 0, CH_1, rank 0
8151 16:31:13.541478 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8152 16:31:13.541582 ==
8153 16:31:13.541669
8154 16:31:13.541752
8155 16:31:13.544981 TX Vref Scan disable
8156 16:31:13.545082 == TX Byte 0 ==
8157 16:31:13.551410 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8158 16:31:13.554930 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8159 16:31:13.555037 == TX Byte 1 ==
8160 16:31:13.561655 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8161 16:31:13.565173 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8162 16:31:13.565279 ==
8163 16:31:13.568117 Dram Type= 6, Freq= 0, CH_1, rank 0
8164 16:31:13.571490 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8165 16:31:13.571592 ==
8166 16:31:13.584809
8167 16:31:13.588184 TX Vref early break, caculate TX vref
8168 16:31:13.591330 TX Vref=16, minBit 3, minWin=21, winSum=365
8169 16:31:13.594742 TX Vref=18, minBit 0, minWin=22, winSum=375
8170 16:31:13.598121 TX Vref=20, minBit 0, minWin=23, winSum=385
8171 16:31:13.601477 TX Vref=22, minBit 3, minWin=23, winSum=393
8172 16:31:13.605120 TX Vref=24, minBit 0, minWin=24, winSum=399
8173 16:31:13.611621 TX Vref=26, minBit 3, minWin=24, winSum=408
8174 16:31:13.614765 TX Vref=28, minBit 0, minWin=25, winSum=413
8175 16:31:13.618145 TX Vref=30, minBit 0, minWin=24, winSum=406
8176 16:31:13.621587 TX Vref=32, minBit 3, minWin=23, winSum=394
8177 16:31:13.624849 TX Vref=34, minBit 3, minWin=22, winSum=383
8178 16:31:13.631408 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8179 16:31:13.631492
8180 16:31:13.634754 Final TX Range 0 Vref 28
8181 16:31:13.634855
8182 16:31:13.634942 ==
8183 16:31:13.638088 Dram Type= 6, Freq= 0, CH_1, rank 0
8184 16:31:13.641525 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8185 16:31:13.641626 ==
8186 16:31:13.641724
8187 16:31:13.641810
8188 16:31:13.644744 TX Vref Scan disable
8189 16:31:13.651075 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8190 16:31:13.651184 == TX Byte 0 ==
8191 16:31:13.654354 u2DelayCellOfst[0]=14 cells (4 PI)
8192 16:31:13.657437 u2DelayCellOfst[1]=7 cells (2 PI)
8193 16:31:13.661083 u2DelayCellOfst[2]=0 cells (0 PI)
8194 16:31:13.664223 u2DelayCellOfst[3]=7 cells (2 PI)
8195 16:31:13.667792 u2DelayCellOfst[4]=7 cells (2 PI)
8196 16:31:13.670675 u2DelayCellOfst[5]=14 cells (4 PI)
8197 16:31:13.673937 u2DelayCellOfst[6]=14 cells (4 PI)
8198 16:31:13.677351 u2DelayCellOfst[7]=7 cells (2 PI)
8199 16:31:13.681037 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8200 16:31:13.684036 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8201 16:31:13.687331 == TX Byte 1 ==
8202 16:31:13.687411 u2DelayCellOfst[8]=0 cells (0 PI)
8203 16:31:13.690759 u2DelayCellOfst[9]=7 cells (2 PI)
8204 16:31:13.693835 u2DelayCellOfst[10]=11 cells (3 PI)
8205 16:31:13.697094 u2DelayCellOfst[11]=3 cells (1 PI)
8206 16:31:13.700875 u2DelayCellOfst[12]=18 cells (5 PI)
8207 16:31:13.703614 u2DelayCellOfst[13]=22 cells (6 PI)
8208 16:31:13.707125 u2DelayCellOfst[14]=22 cells (6 PI)
8209 16:31:13.710948 u2DelayCellOfst[15]=22 cells (6 PI)
8210 16:31:13.713471 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8211 16:31:13.720263 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8212 16:31:13.720367 DramC Write-DBI on
8213 16:31:13.720455 ==
8214 16:31:13.723863 Dram Type= 6, Freq= 0, CH_1, rank 0
8215 16:31:13.730043 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8216 16:31:13.730142 ==
8217 16:31:13.730233
8218 16:31:13.730291
8219 16:31:13.730350 TX Vref Scan disable
8220 16:31:13.734037 == TX Byte 0 ==
8221 16:31:13.737367 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8222 16:31:13.740444 == TX Byte 1 ==
8223 16:31:13.743726 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8224 16:31:13.747635 DramC Write-DBI off
8225 16:31:13.747757
8226 16:31:13.747846 [DATLAT]
8227 16:31:13.747937 Freq=1600, CH1 RK0
8228 16:31:13.748023
8229 16:31:13.750757 DATLAT Default: 0xf
8230 16:31:13.750904 0, 0xFFFF, sum = 0
8231 16:31:13.753771 1, 0xFFFF, sum = 0
8232 16:31:13.756935 2, 0xFFFF, sum = 0
8233 16:31:13.757070 3, 0xFFFF, sum = 0
8234 16:31:13.760442 4, 0xFFFF, sum = 0
8235 16:31:13.760590 5, 0xFFFF, sum = 0
8236 16:31:13.764072 6, 0xFFFF, sum = 0
8237 16:31:13.764220 7, 0xFFFF, sum = 0
8238 16:31:13.767381 8, 0xFFFF, sum = 0
8239 16:31:13.767544 9, 0xFFFF, sum = 0
8240 16:31:13.770321 10, 0xFFFF, sum = 0
8241 16:31:13.770457 11, 0xFFFF, sum = 0
8242 16:31:13.773650 12, 0xF7F, sum = 0
8243 16:31:13.773780 13, 0x0, sum = 1
8244 16:31:13.776831 14, 0x0, sum = 2
8245 16:31:13.776921 15, 0x0, sum = 3
8246 16:31:13.780861 16, 0x0, sum = 4
8247 16:31:13.780979 best_step = 14
8248 16:31:13.781066
8249 16:31:13.781146 ==
8250 16:31:13.783902 Dram Type= 6, Freq= 0, CH_1, rank 0
8251 16:31:13.787057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8252 16:31:13.790620 ==
8253 16:31:13.790700 RX Vref Scan: 1
8254 16:31:13.790761
8255 16:31:13.793367 Set Vref Range= 24 -> 127
8256 16:31:13.793448
8257 16:31:13.796980 RX Vref 24 -> 127, step: 1
8258 16:31:13.797059
8259 16:31:13.797120 RX Delay 3 -> 252, step: 4
8260 16:31:13.797178
8261 16:31:13.800619 Set Vref, RX VrefLevel [Byte0]: 24
8262 16:31:13.803502 [Byte1]: 24
8263 16:31:13.807175
8264 16:31:13.807283 Set Vref, RX VrefLevel [Byte0]: 25
8265 16:31:13.810346 [Byte1]: 25
8266 16:31:13.815076
8267 16:31:13.815183 Set Vref, RX VrefLevel [Byte0]: 26
8268 16:31:13.818019 [Byte1]: 26
8269 16:31:13.822722
8270 16:31:13.822813 Set Vref, RX VrefLevel [Byte0]: 27
8271 16:31:13.826071 [Byte1]: 27
8272 16:31:13.830345
8273 16:31:13.830440 Set Vref, RX VrefLevel [Byte0]: 28
8274 16:31:13.833701 [Byte1]: 28
8275 16:31:13.838091
8276 16:31:13.838221 Set Vref, RX VrefLevel [Byte0]: 29
8277 16:31:13.840976 [Byte1]: 29
8278 16:31:13.845716
8279 16:31:13.845805 Set Vref, RX VrefLevel [Byte0]: 30
8280 16:31:13.849083 [Byte1]: 30
8281 16:31:13.853167
8282 16:31:13.853260 Set Vref, RX VrefLevel [Byte0]: 31
8283 16:31:13.856793 [Byte1]: 31
8284 16:31:13.860949
8285 16:31:13.861028 Set Vref, RX VrefLevel [Byte0]: 32
8286 16:31:13.864083 [Byte1]: 32
8287 16:31:13.868452
8288 16:31:13.868532 Set Vref, RX VrefLevel [Byte0]: 33
8289 16:31:13.871806 [Byte1]: 33
8290 16:31:13.875987
8291 16:31:13.876065 Set Vref, RX VrefLevel [Byte0]: 34
8292 16:31:13.879467 [Byte1]: 34
8293 16:31:13.883889
8294 16:31:13.884005 Set Vref, RX VrefLevel [Byte0]: 35
8295 16:31:13.887456 [Byte1]: 35
8296 16:31:13.891276
8297 16:31:13.891362 Set Vref, RX VrefLevel [Byte0]: 36
8298 16:31:13.894680 [Byte1]: 36
8299 16:31:13.899115
8300 16:31:13.899190 Set Vref, RX VrefLevel [Byte0]: 37
8301 16:31:13.902737 [Byte1]: 37
8302 16:31:13.906740
8303 16:31:13.906822 Set Vref, RX VrefLevel [Byte0]: 38
8304 16:31:13.910306 [Byte1]: 38
8305 16:31:13.914817
8306 16:31:13.914897 Set Vref, RX VrefLevel [Byte0]: 39
8307 16:31:13.917895 [Byte1]: 39
8308 16:31:13.921862
8309 16:31:13.921940 Set Vref, RX VrefLevel [Byte0]: 40
8310 16:31:13.925353 [Byte1]: 40
8311 16:31:13.929934
8312 16:31:13.930014 Set Vref, RX VrefLevel [Byte0]: 41
8313 16:31:13.932724 [Byte1]: 41
8314 16:31:13.937515
8315 16:31:13.937621 Set Vref, RX VrefLevel [Byte0]: 42
8316 16:31:13.941015 [Byte1]: 42
8317 16:31:13.944925
8318 16:31:13.945027 Set Vref, RX VrefLevel [Byte0]: 43
8319 16:31:13.948158 [Byte1]: 43
8320 16:31:13.952539
8321 16:31:13.952624 Set Vref, RX VrefLevel [Byte0]: 44
8322 16:31:13.956154 [Byte1]: 44
8323 16:31:13.960397
8324 16:31:13.960488 Set Vref, RX VrefLevel [Byte0]: 45
8325 16:31:13.963807 [Byte1]: 45
8326 16:31:13.968150
8327 16:31:13.971191 Set Vref, RX VrefLevel [Byte0]: 46
8328 16:31:13.974553 [Byte1]: 46
8329 16:31:13.974632
8330 16:31:13.977440 Set Vref, RX VrefLevel [Byte0]: 47
8331 16:31:13.981027 [Byte1]: 47
8332 16:31:13.981099
8333 16:31:13.984538 Set Vref, RX VrefLevel [Byte0]: 48
8334 16:31:13.987287 [Byte1]: 48
8335 16:31:13.990716
8336 16:31:13.990786 Set Vref, RX VrefLevel [Byte0]: 49
8337 16:31:13.994149 [Byte1]: 49
8338 16:31:13.998505
8339 16:31:13.998574 Set Vref, RX VrefLevel [Byte0]: 50
8340 16:31:14.001756 [Byte1]: 50
8341 16:31:14.006201
8342 16:31:14.006319 Set Vref, RX VrefLevel [Byte0]: 51
8343 16:31:14.009736 [Byte1]: 51
8344 16:31:14.013909
8345 16:31:14.014024 Set Vref, RX VrefLevel [Byte0]: 52
8346 16:31:14.017119 [Byte1]: 52
8347 16:31:14.021332
8348 16:31:14.021410 Set Vref, RX VrefLevel [Byte0]: 53
8349 16:31:14.024817 [Byte1]: 53
8350 16:31:14.029397
8351 16:31:14.029506 Set Vref, RX VrefLevel [Byte0]: 54
8352 16:31:14.032288 [Byte1]: 54
8353 16:31:14.036849
8354 16:31:14.036930 Set Vref, RX VrefLevel [Byte0]: 55
8355 16:31:14.040269 [Byte1]: 55
8356 16:31:14.044416
8357 16:31:14.044514 Set Vref, RX VrefLevel [Byte0]: 56
8358 16:31:14.047580 [Byte1]: 56
8359 16:31:14.051854
8360 16:31:14.051926 Set Vref, RX VrefLevel [Byte0]: 57
8361 16:31:14.055676 [Byte1]: 57
8362 16:31:14.059900
8363 16:31:14.059978 Set Vref, RX VrefLevel [Byte0]: 58
8364 16:31:14.063283 [Byte1]: 58
8365 16:31:14.067196
8366 16:31:14.067299 Set Vref, RX VrefLevel [Byte0]: 59
8367 16:31:14.070508 [Byte1]: 59
8368 16:31:14.075187
8369 16:31:14.075261 Set Vref, RX VrefLevel [Byte0]: 60
8370 16:31:14.078387 [Byte1]: 60
8371 16:31:14.082927
8372 16:31:14.083022 Set Vref, RX VrefLevel [Byte0]: 61
8373 16:31:14.086080 [Byte1]: 61
8374 16:31:14.090582
8375 16:31:14.090661 Set Vref, RX VrefLevel [Byte0]: 62
8376 16:31:14.093675 [Byte1]: 62
8377 16:31:14.098173
8378 16:31:14.098301 Set Vref, RX VrefLevel [Byte0]: 63
8379 16:31:14.101579 [Byte1]: 63
8380 16:31:14.105577
8381 16:31:14.105708 Set Vref, RX VrefLevel [Byte0]: 64
8382 16:31:14.109161 [Byte1]: 64
8383 16:31:14.113404
8384 16:31:14.113516 Set Vref, RX VrefLevel [Byte0]: 65
8385 16:31:14.116628 [Byte1]: 65
8386 16:31:14.120751
8387 16:31:14.120855 Set Vref, RX VrefLevel [Byte0]: 66
8388 16:31:14.124165 [Byte1]: 66
8389 16:31:14.128869
8390 16:31:14.128978 Set Vref, RX VrefLevel [Byte0]: 67
8391 16:31:14.131929 [Byte1]: 67
8392 16:31:14.136442
8393 16:31:14.136592 Set Vref, RX VrefLevel [Byte0]: 68
8394 16:31:14.139704 [Byte1]: 68
8395 16:31:14.144000
8396 16:31:14.144116 Set Vref, RX VrefLevel [Byte0]: 69
8397 16:31:14.147573 [Byte1]: 69
8398 16:31:14.151813
8399 16:31:14.151939 Set Vref, RX VrefLevel [Byte0]: 70
8400 16:31:14.154740 [Byte1]: 70
8401 16:31:14.159277
8402 16:31:14.159363 Set Vref, RX VrefLevel [Byte0]: 71
8403 16:31:14.162501 [Byte1]: 71
8404 16:31:14.167144
8405 16:31:14.167225 Final RX Vref Byte 0 = 60 to rank0
8406 16:31:14.170544 Final RX Vref Byte 1 = 54 to rank0
8407 16:31:14.173726 Final RX Vref Byte 0 = 60 to rank1
8408 16:31:14.177089 Final RX Vref Byte 1 = 54 to rank1==
8409 16:31:14.180076 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 16:31:14.186777 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8411 16:31:14.186860 ==
8412 16:31:14.186922 DQS Delay:
8413 16:31:14.186980 DQS0 = 0, DQS1 = 0
8414 16:31:14.190150 DQM Delay:
8415 16:31:14.190279 DQM0 = 129, DQM1 = 122
8416 16:31:14.193609 DQ Delay:
8417 16:31:14.196625 DQ0 =134, DQ1 =124, DQ2 =116, DQ3 =126
8418 16:31:14.200028 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8419 16:31:14.203478 DQ8 =104, DQ9 =114, DQ10 =126, DQ11 =112
8420 16:31:14.207080 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8421 16:31:14.207174
8422 16:31:14.207236
8423 16:31:14.207293
8424 16:31:14.209981 [DramC_TX_OE_Calibration] TA2
8425 16:31:14.213363 Original DQ_B0 (3 6) =30, OEN = 27
8426 16:31:14.216726 Original DQ_B1 (3 6) =30, OEN = 27
8427 16:31:14.219905 24, 0x0, End_B0=24 End_B1=24
8428 16:31:14.219997 25, 0x0, End_B0=25 End_B1=25
8429 16:31:14.223667 26, 0x0, End_B0=26 End_B1=26
8430 16:31:14.226787 27, 0x0, End_B0=27 End_B1=27
8431 16:31:14.230256 28, 0x0, End_B0=28 End_B1=28
8432 16:31:14.233352 29, 0x0, End_B0=29 End_B1=29
8433 16:31:14.233473 30, 0x0, End_B0=30 End_B1=30
8434 16:31:14.236806 31, 0x4141, End_B0=30 End_B1=30
8435 16:31:14.239813 Byte0 end_step=30 best_step=27
8436 16:31:14.243228 Byte1 end_step=30 best_step=27
8437 16:31:14.246653 Byte0 TX OE(2T, 0.5T) = (3, 3)
8438 16:31:14.249803 Byte1 TX OE(2T, 0.5T) = (3, 3)
8439 16:31:14.249895
8440 16:31:14.249957
8441 16:31:14.256669 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8442 16:31:14.260124 CH1 RK0: MR19=303, MR18=2525
8443 16:31:14.266510 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8444 16:31:14.266634
8445 16:31:14.269803 ----->DramcWriteLeveling(PI) begin...
8446 16:31:14.269932 ==
8447 16:31:14.273559 Dram Type= 6, Freq= 0, CH_1, rank 1
8448 16:31:14.276613 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8449 16:31:14.276732 ==
8450 16:31:14.279821 Write leveling (Byte 0): 23 => 23
8451 16:31:14.283083 Write leveling (Byte 1): 21 => 21
8452 16:31:14.286395 DramcWriteLeveling(PI) end<-----
8453 16:31:14.286494
8454 16:31:14.286568 ==
8455 16:31:14.289945 Dram Type= 6, Freq= 0, CH_1, rank 1
8456 16:31:14.293334 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8457 16:31:14.293423 ==
8458 16:31:14.296167 [Gating] SW mode calibration
8459 16:31:14.303196 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8460 16:31:14.309389 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8461 16:31:14.312900 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8462 16:31:14.316108 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 16:31:14.322889 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8464 16:31:14.326353 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 16:31:14.329686 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 16:31:14.336271 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8467 16:31:14.339187 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8468 16:31:14.342608 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8469 16:31:14.349376 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8470 16:31:14.352890 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8471 16:31:14.355941 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8472 16:31:14.362450 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 16:31:14.365941 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 16:31:14.368820 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 16:31:14.375722 0 13 24 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8476 16:31:14.379058 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8477 16:31:14.382448 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8478 16:31:14.388857 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8479 16:31:14.391986 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 16:31:14.395496 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 16:31:14.401827 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 16:31:14.405371 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 16:31:14.408513 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8484 16:31:14.415066 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8485 16:31:14.418807 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8486 16:31:14.422082 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 16:31:14.428639 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 16:31:14.432020 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 16:31:14.435444 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 16:31:14.442204 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 16:31:14.445302 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 16:31:14.448660 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 16:31:14.455126 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 16:31:14.458652 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 16:31:14.461671 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 16:31:14.468373 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 16:31:14.471833 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 16:31:14.474802 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 16:31:14.481645 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8500 16:31:14.485178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8501 16:31:14.488568 Total UI for P1: 0, mck2ui 16
8502 16:31:14.491653 best dqsien dly found for B0: ( 1, 0, 24)
8503 16:31:14.495177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8504 16:31:14.501685 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8505 16:31:14.501782 Total UI for P1: 0, mck2ui 16
8506 16:31:14.505093 best dqsien dly found for B1: ( 1, 0, 30)
8507 16:31:14.511516 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8508 16:31:14.514978 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8509 16:31:14.515071
8510 16:31:14.518188 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8511 16:31:14.521542 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8512 16:31:14.524533 [Gating] SW calibration Done
8513 16:31:14.524614 ==
8514 16:31:14.527922 Dram Type= 6, Freq= 0, CH_1, rank 1
8515 16:31:14.531458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8516 16:31:14.531539 ==
8517 16:31:14.534412 RX Vref Scan: 0
8518 16:31:14.534494
8519 16:31:14.534580 RX Vref 0 -> 0, step: 1
8520 16:31:14.534640
8521 16:31:14.537714 RX Delay 0 -> 252, step: 8
8522 16:31:14.541345 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8523 16:31:14.547747 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8524 16:31:14.551110 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8525 16:31:14.554430 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8526 16:31:14.557472 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8527 16:31:14.560945 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8528 16:31:14.567433 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8529 16:31:14.571096 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8530 16:31:14.574518 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8531 16:31:14.577853 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8532 16:31:14.580737 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8533 16:31:14.587411 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8534 16:31:14.590804 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8535 16:31:14.594470 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8536 16:31:14.597394 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8537 16:31:14.600864 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8538 16:31:14.603710 ==
8539 16:31:14.607021 Dram Type= 6, Freq= 0, CH_1, rank 1
8540 16:31:14.610656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8541 16:31:14.610762 ==
8542 16:31:14.610850 DQS Delay:
8543 16:31:14.613682 DQS0 = 0, DQS1 = 0
8544 16:31:14.613783 DQM Delay:
8545 16:31:14.617046 DQM0 = 131, DQM1 = 125
8546 16:31:14.617146 DQ Delay:
8547 16:31:14.620538 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8548 16:31:14.623852 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8549 16:31:14.627117 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8550 16:31:14.630543 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8551 16:31:14.630641
8552 16:31:14.630734
8553 16:31:14.634125 ==
8554 16:31:14.634222 Dram Type= 6, Freq= 0, CH_1, rank 1
8555 16:31:14.640428 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8556 16:31:14.640523 ==
8557 16:31:14.640609
8558 16:31:14.640700
8559 16:31:14.643364 TX Vref Scan disable
8560 16:31:14.643452 == TX Byte 0 ==
8561 16:31:14.646789 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8562 16:31:14.653404 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8563 16:31:14.653502 == TX Byte 1 ==
8564 16:31:14.656831 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8565 16:31:14.663631 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8566 16:31:14.663703 ==
8567 16:31:14.666460 Dram Type= 6, Freq= 0, CH_1, rank 1
8568 16:31:14.670013 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8569 16:31:14.670113 ==
8570 16:31:14.683999
8571 16:31:14.687425 TX Vref early break, caculate TX vref
8572 16:31:14.690763 TX Vref=16, minBit 1, minWin=22, winSum=375
8573 16:31:14.694161 TX Vref=18, minBit 0, minWin=22, winSum=385
8574 16:31:14.696992 TX Vref=20, minBit 0, minWin=23, winSum=398
8575 16:31:14.700582 TX Vref=22, minBit 0, minWin=23, winSum=406
8576 16:31:14.703984 TX Vref=24, minBit 0, minWin=23, winSum=412
8577 16:31:14.710473 TX Vref=26, minBit 0, minWin=24, winSum=417
8578 16:31:14.713752 TX Vref=28, minBit 0, minWin=24, winSum=420
8579 16:31:14.716948 TX Vref=30, minBit 0, minWin=23, winSum=414
8580 16:31:14.720113 TX Vref=32, minBit 0, minWin=22, winSum=410
8581 16:31:14.723767 TX Vref=34, minBit 0, minWin=22, winSum=400
8582 16:31:14.727140 TX Vref=36, minBit 0, minWin=22, winSum=390
8583 16:31:14.733795 [TxChooseVref] Worse bit 0, Min win 24, Win sum 420, Final Vref 28
8584 16:31:14.733885
8585 16:31:14.736686 Final TX Range 0 Vref 28
8586 16:31:14.736787
8587 16:31:14.736878 ==
8588 16:31:14.740254 Dram Type= 6, Freq= 0, CH_1, rank 1
8589 16:31:14.743693 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8590 16:31:14.743805 ==
8591 16:31:14.743896
8592 16:31:14.746740
8593 16:31:14.746846 TX Vref Scan disable
8594 16:31:14.753704 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8595 16:31:14.753786 == TX Byte 0 ==
8596 16:31:14.756659 u2DelayCellOfst[0]=18 cells (5 PI)
8597 16:31:14.760151 u2DelayCellOfst[1]=11 cells (3 PI)
8598 16:31:14.763128 u2DelayCellOfst[2]=0 cells (0 PI)
8599 16:31:14.766851 u2DelayCellOfst[3]=7 cells (2 PI)
8600 16:31:14.770072 u2DelayCellOfst[4]=7 cells (2 PI)
8601 16:31:14.773570 u2DelayCellOfst[5]=18 cells (5 PI)
8602 16:31:14.776898 u2DelayCellOfst[6]=14 cells (4 PI)
8603 16:31:14.780129 u2DelayCellOfst[7]=3 cells (1 PI)
8604 16:31:14.783176 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8605 16:31:14.786510 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8606 16:31:14.790076 == TX Byte 1 ==
8607 16:31:14.793429 u2DelayCellOfst[8]=0 cells (0 PI)
8608 16:31:14.796457 u2DelayCellOfst[9]=3 cells (1 PI)
8609 16:31:14.800224 u2DelayCellOfst[10]=11 cells (3 PI)
8610 16:31:14.800309 u2DelayCellOfst[11]=0 cells (0 PI)
8611 16:31:14.803199 u2DelayCellOfst[12]=14 cells (4 PI)
8612 16:31:14.806868 u2DelayCellOfst[13]=18 cells (5 PI)
8613 16:31:14.809722 u2DelayCellOfst[14]=18 cells (5 PI)
8614 16:31:14.813376 u2DelayCellOfst[15]=18 cells (5 PI)
8615 16:31:14.819779 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8616 16:31:14.823036 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8617 16:31:14.823118 DramC Write-DBI on
8618 16:31:14.823180 ==
8619 16:31:14.826636 Dram Type= 6, Freq= 0, CH_1, rank 1
8620 16:31:14.832966 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8621 16:31:14.833065 ==
8622 16:31:14.833141
8623 16:31:14.833196
8624 16:31:14.833249 TX Vref Scan disable
8625 16:31:14.837282 == TX Byte 0 ==
8626 16:31:14.840161 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8627 16:31:14.844002 == TX Byte 1 ==
8628 16:31:14.847027 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8629 16:31:14.850248 DramC Write-DBI off
8630 16:31:14.850344
8631 16:31:14.850404 [DATLAT]
8632 16:31:14.850460 Freq=1600, CH1 RK1
8633 16:31:14.850514
8634 16:31:14.853845 DATLAT Default: 0xe
8635 16:31:14.853923 0, 0xFFFF, sum = 0
8636 16:31:14.857236 1, 0xFFFF, sum = 0
8637 16:31:14.857316 2, 0xFFFF, sum = 0
8638 16:31:14.860575 3, 0xFFFF, sum = 0
8639 16:31:14.863853 4, 0xFFFF, sum = 0
8640 16:31:14.863931 5, 0xFFFF, sum = 0
8641 16:31:14.866889 6, 0xFFFF, sum = 0
8642 16:31:14.866967 7, 0xFFFF, sum = 0
8643 16:31:14.870390 8, 0xFFFF, sum = 0
8644 16:31:14.870469 9, 0xFFFF, sum = 0
8645 16:31:14.873434 10, 0xFFFF, sum = 0
8646 16:31:14.873513 11, 0xFFFF, sum = 0
8647 16:31:14.876873 12, 0xFFF, sum = 0
8648 16:31:14.876951 13, 0x0, sum = 1
8649 16:31:14.880282 14, 0x0, sum = 2
8650 16:31:14.880362 15, 0x0, sum = 3
8651 16:31:14.883515 16, 0x0, sum = 4
8652 16:31:14.883595 best_step = 14
8653 16:31:14.883656
8654 16:31:14.883711 ==
8655 16:31:14.886873 Dram Type= 6, Freq= 0, CH_1, rank 1
8656 16:31:14.890088 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8657 16:31:14.893584 ==
8658 16:31:14.893662 RX Vref Scan: 0
8659 16:31:14.893722
8660 16:31:14.896655 RX Vref 0 -> 0, step: 1
8661 16:31:14.896732
8662 16:31:14.896793 RX Delay 3 -> 252, step: 4
8663 16:31:14.904207 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8664 16:31:14.907630 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8665 16:31:14.910402 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8666 16:31:14.913969 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8667 16:31:14.917431 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8668 16:31:14.923938 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8669 16:31:14.927341 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8670 16:31:14.930432 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8671 16:31:14.933863 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8672 16:31:14.937082 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8673 16:31:14.944070 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8674 16:31:14.947400 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8675 16:31:14.950722 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8676 16:31:14.954092 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8677 16:31:14.960637 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8678 16:31:14.963545 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8679 16:31:14.963623 ==
8680 16:31:14.966865 Dram Type= 6, Freq= 0, CH_1, rank 1
8681 16:31:14.970490 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8682 16:31:14.970569 ==
8683 16:31:14.973449 DQS Delay:
8684 16:31:14.973527 DQS0 = 0, DQS1 = 0
8685 16:31:14.973587 DQM Delay:
8686 16:31:14.977026 DQM0 = 126, DQM1 = 123
8687 16:31:14.977104 DQ Delay:
8688 16:31:14.979939 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =122
8689 16:31:14.983389 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =124
8690 16:31:14.986854 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =114
8691 16:31:14.993217 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8692 16:31:14.993295
8693 16:31:14.993355
8694 16:31:14.993410
8695 16:31:14.996626 [DramC_TX_OE_Calibration] TA2
8696 16:31:14.999977 Original DQ_B0 (3 6) =30, OEN = 27
8697 16:31:15.000056 Original DQ_B1 (3 6) =30, OEN = 27
8698 16:31:15.003448 24, 0x0, End_B0=24 End_B1=24
8699 16:31:15.007111 25, 0x0, End_B0=25 End_B1=25
8700 16:31:15.009816 26, 0x0, End_B0=26 End_B1=26
8701 16:31:15.013153 27, 0x0, End_B0=27 End_B1=27
8702 16:31:15.013232 28, 0x0, End_B0=28 End_B1=28
8703 16:31:15.016525 29, 0x0, End_B0=29 End_B1=29
8704 16:31:15.020166 30, 0x0, End_B0=30 End_B1=30
8705 16:31:15.023115 31, 0x4141, End_B0=30 End_B1=30
8706 16:31:15.026798 Byte0 end_step=30 best_step=27
8707 16:31:15.029591 Byte1 end_step=30 best_step=27
8708 16:31:15.029668 Byte0 TX OE(2T, 0.5T) = (3, 3)
8709 16:31:15.033147 Byte1 TX OE(2T, 0.5T) = (3, 3)
8710 16:31:15.033224
8711 16:31:15.033283
8712 16:31:15.042902 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8713 16:31:15.046399 CH1 RK1: MR19=303, MR18=2020
8714 16:31:15.049768 CH1_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8715 16:31:15.052991 [RxdqsGatingPostProcess] freq 1600
8716 16:31:15.059793 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8717 16:31:15.063150 Pre-setting of DQS Precalculation
8718 16:31:15.065961 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8719 16:31:15.076337 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8720 16:31:15.082447 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8721 16:31:15.082528
8722 16:31:15.082588
8723 16:31:15.085795 [Calibration Summary] 3200 Mbps
8724 16:31:15.085872 CH 0, Rank 0
8725 16:31:15.089326 SW Impedance : PASS
8726 16:31:15.089404 DUTY Scan : NO K
8727 16:31:15.092788 ZQ Calibration : PASS
8728 16:31:15.095754 Jitter Meter : NO K
8729 16:31:15.095832 CBT Training : PASS
8730 16:31:15.099197 Write leveling : PASS
8731 16:31:15.102518 RX DQS gating : PASS
8732 16:31:15.102596 RX DQ/DQS(RDDQC) : PASS
8733 16:31:15.106002 TX DQ/DQS : PASS
8734 16:31:15.108981 RX DATLAT : PASS
8735 16:31:15.109059 RX DQ/DQS(Engine): PASS
8736 16:31:15.112497 TX OE : PASS
8737 16:31:15.112575 All Pass.
8738 16:31:15.112635
8739 16:31:15.115786 CH 0, Rank 1
8740 16:31:15.115864 SW Impedance : PASS
8741 16:31:15.119098 DUTY Scan : NO K
8742 16:31:15.122021 ZQ Calibration : PASS
8743 16:31:15.122121 Jitter Meter : NO K
8744 16:31:15.125497 CBT Training : PASS
8745 16:31:15.129179 Write leveling : PASS
8746 16:31:15.129257 RX DQS gating : PASS
8747 16:31:15.132350 RX DQ/DQS(RDDQC) : PASS
8748 16:31:15.132428 TX DQ/DQS : PASS
8749 16:31:15.135609 RX DATLAT : PASS
8750 16:31:15.138807 RX DQ/DQS(Engine): PASS
8751 16:31:15.138885 TX OE : PASS
8752 16:31:15.142180 All Pass.
8753 16:31:15.142280
8754 16:31:15.142341 CH 1, Rank 0
8755 16:31:15.145213 SW Impedance : PASS
8756 16:31:15.145290 DUTY Scan : NO K
8757 16:31:15.148946 ZQ Calibration : PASS
8758 16:31:15.152258 Jitter Meter : NO K
8759 16:31:15.152339 CBT Training : PASS
8760 16:31:15.155195 Write leveling : PASS
8761 16:31:15.158807 RX DQS gating : PASS
8762 16:31:15.158884 RX DQ/DQS(RDDQC) : PASS
8763 16:31:15.162069 TX DQ/DQS : PASS
8764 16:31:15.165401 RX DATLAT : PASS
8765 16:31:15.165479 RX DQ/DQS(Engine): PASS
8766 16:31:15.168538 TX OE : PASS
8767 16:31:15.168616 All Pass.
8768 16:31:15.168676
8769 16:31:15.172015 CH 1, Rank 1
8770 16:31:15.172094 SW Impedance : PASS
8771 16:31:15.175344 DUTY Scan : NO K
8772 16:31:15.178379 ZQ Calibration : PASS
8773 16:31:15.178456 Jitter Meter : NO K
8774 16:31:15.181873 CBT Training : PASS
8775 16:31:15.185308 Write leveling : PASS
8776 16:31:15.185401 RX DQS gating : PASS
8777 16:31:15.188274 RX DQ/DQS(RDDQC) : PASS
8778 16:31:15.191525 TX DQ/DQS : PASS
8779 16:31:15.191627 RX DATLAT : PASS
8780 16:31:15.195051 RX DQ/DQS(Engine): PASS
8781 16:31:15.195145 TX OE : PASS
8782 16:31:15.198590 All Pass.
8783 16:31:15.198697
8784 16:31:15.198756 DramC Write-DBI on
8785 16:31:15.201442 PER_BANK_REFRESH: Hybrid Mode
8786 16:31:15.204947 TX_TRACKING: ON
8787 16:31:15.211283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8788 16:31:15.221343 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8789 16:31:15.228215 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8790 16:31:15.231225 [FAST_K] Save calibration result to emmc
8791 16:31:15.234765 sync common calibartion params.
8792 16:31:15.234860 sync cbt_mode0:0, 1:0
8793 16:31:15.238379 dram_init: ddr_geometry: 0
8794 16:31:15.241290 dram_init: ddr_geometry: 0
8795 16:31:15.244939 dram_init: ddr_geometry: 0
8796 16:31:15.245065 0:dram_rank_size:80000000
8797 16:31:15.247799 1:dram_rank_size:80000000
8798 16:31:15.254614 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8799 16:31:15.254694 DFS_SHUFFLE_HW_MODE: ON
8800 16:31:15.261189 dramc_set_vcore_voltage set vcore to 725000
8801 16:31:15.261267 Read voltage for 1600, 0
8802 16:31:15.261328 Vio18 = 0
8803 16:31:15.264607 Vcore = 725000
8804 16:31:15.264685 Vdram = 0
8805 16:31:15.264744 Vddq = 0
8806 16:31:15.267646 Vmddr = 0
8807 16:31:15.267740 switch to 3200 Mbps bootup
8808 16:31:15.271239 [DramcRunTimeConfig]
8809 16:31:15.271331 PHYPLL
8810 16:31:15.274715 DPM_CONTROL_AFTERK: ON
8811 16:31:15.274793 PER_BANK_REFRESH: ON
8812 16:31:15.277888 REFRESH_OVERHEAD_REDUCTION: ON
8813 16:31:15.280988 CMD_PICG_NEW_MODE: OFF
8814 16:31:15.281082 XRTWTW_NEW_MODE: ON
8815 16:31:15.284442 XRTRTR_NEW_MODE: ON
8816 16:31:15.284520 TX_TRACKING: ON
8817 16:31:15.287818 RDSEL_TRACKING: OFF
8818 16:31:15.291347 DQS Precalculation for DVFS: ON
8819 16:31:15.291424 RX_TRACKING: OFF
8820 16:31:15.294442 HW_GATING DBG: ON
8821 16:31:15.294520 ZQCS_ENABLE_LP4: ON
8822 16:31:15.297810 RX_PICG_NEW_MODE: ON
8823 16:31:15.297887 TX_PICG_NEW_MODE: ON
8824 16:31:15.300815 ENABLE_RX_DCM_DPHY: ON
8825 16:31:15.304359 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8826 16:31:15.308114 DUMMY_READ_FOR_TRACKING: OFF
8827 16:31:15.310815 !!! SPM_CONTROL_AFTERK: OFF
8828 16:31:15.310913 !!! SPM could not control APHY
8829 16:31:15.314148 IMPEDANCE_TRACKING: ON
8830 16:31:15.314252 TEMP_SENSOR: ON
8831 16:31:15.317534 HW_SAVE_FOR_SR: OFF
8832 16:31:15.321087 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8833 16:31:15.324021 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8834 16:31:15.327303 Read ODT Tracking: ON
8835 16:31:15.327381 Refresh Rate DeBounce: ON
8836 16:31:15.331042 DFS_NO_QUEUE_FLUSH: ON
8837 16:31:15.334031 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8838 16:31:15.337659 ENABLE_DFS_RUNTIME_MRW: OFF
8839 16:31:15.337736 DDR_RESERVE_NEW_MODE: ON
8840 16:31:15.341083 MR_CBT_SWITCH_FREQ: ON
8841 16:31:15.344139 =========================
8842 16:31:15.361518 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8843 16:31:15.364893 dram_init: ddr_geometry: 0
8844 16:31:15.382969 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8845 16:31:15.386116 dram_init: dram init end (result: 0)
8846 16:31:15.392822 DRAM-K: Full calibration passed in 23390 msecs
8847 16:31:15.396504 MRC: failed to locate region type 0.
8848 16:31:15.396583 DRAM rank0 size:0x80000000,
8849 16:31:15.399404 DRAM rank1 size=0x80000000
8850 16:31:15.409301 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8851 16:31:15.415828 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8852 16:31:15.422717 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8853 16:31:15.429234 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8854 16:31:15.432714 DRAM rank0 size:0x80000000,
8855 16:31:15.436043 DRAM rank1 size=0x80000000
8856 16:31:15.436136 CBMEM:
8857 16:31:15.439447 IMD: root @ 0xfffff000 254 entries.
8858 16:31:15.442711 IMD: root @ 0xffffec00 62 entries.
8859 16:31:15.445801 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8860 16:31:15.449225 WARNING: RO_VPD is uninitialized or empty.
8861 16:31:15.455574 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8862 16:31:15.462792 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8863 16:31:15.475362 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8864 16:31:15.486829 BS: romstage times (exec / console): total (unknown) / 22937 ms
8865 16:31:15.486913
8866 16:31:15.486974
8867 16:31:15.496469 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8868 16:31:15.499886 ARM64: Exception handlers installed.
8869 16:31:15.503151 ARM64: Testing exception
8870 16:31:15.506867 ARM64: Done test exception
8871 16:31:15.506945 Enumerating buses...
8872 16:31:15.510012 Show all devs... Before device enumeration.
8873 16:31:15.513271 Root Device: enabled 1
8874 16:31:15.516307 CPU_CLUSTER: 0: enabled 1
8875 16:31:15.516385 CPU: 00: enabled 1
8876 16:31:15.519833 Compare with tree...
8877 16:31:15.519911 Root Device: enabled 1
8878 16:31:15.522758 CPU_CLUSTER: 0: enabled 1
8879 16:31:15.526127 CPU: 00: enabled 1
8880 16:31:15.526205 Root Device scanning...
8881 16:31:15.529853 scan_static_bus for Root Device
8882 16:31:15.533187 CPU_CLUSTER: 0 enabled
8883 16:31:15.536289 scan_static_bus for Root Device done
8884 16:31:15.539626 scan_bus: bus Root Device finished in 8 msecs
8885 16:31:15.539704 done
8886 16:31:15.546164 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8887 16:31:15.549686 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8888 16:31:15.555937 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8889 16:31:15.559486 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8890 16:31:15.563047 Allocating resources...
8891 16:31:15.565998 Reading resources...
8892 16:31:15.569485 Root Device read_resources bus 0 link: 0
8893 16:31:15.569617 DRAM rank0 size:0x80000000,
8894 16:31:15.572562 DRAM rank1 size=0x80000000
8895 16:31:15.575984 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8896 16:31:15.579292 CPU: 00 missing read_resources
8897 16:31:15.586222 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8898 16:31:15.589084 Root Device read_resources bus 0 link: 0 done
8899 16:31:15.589162 Done reading resources.
8900 16:31:15.595948 Show resources in subtree (Root Device)...After reading.
8901 16:31:15.598950 Root Device child on link 0 CPU_CLUSTER: 0
8902 16:31:15.602427 CPU_CLUSTER: 0 child on link 0 CPU: 00
8903 16:31:15.612362 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8904 16:31:15.612460 CPU: 00
8905 16:31:15.615710 Root Device assign_resources, bus 0 link: 0
8906 16:31:15.618966 CPU_CLUSTER: 0 missing set_resources
8907 16:31:15.625400 Root Device assign_resources, bus 0 link: 0 done
8908 16:31:15.625478 Done setting resources.
8909 16:31:15.631890 Show resources in subtree (Root Device)...After assigning values.
8910 16:31:15.635110 Root Device child on link 0 CPU_CLUSTER: 0
8911 16:31:15.638717 CPU_CLUSTER: 0 child on link 0 CPU: 00
8912 16:31:15.648721 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8913 16:31:15.648829 CPU: 00
8914 16:31:15.652060 Done allocating resources.
8915 16:31:15.658429 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8916 16:31:15.658504 Enabling resources...
8917 16:31:15.658566 done.
8918 16:31:15.665287 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8919 16:31:15.665416 Initializing devices...
8920 16:31:15.668199 Root Device init
8921 16:31:15.671636 init hardware done!
8922 16:31:15.671739 0x00000018: ctrlr->caps
8923 16:31:15.675219 52.000 MHz: ctrlr->f_max
8924 16:31:15.678103 0.400 MHz: ctrlr->f_min
8925 16:31:15.678201 0x40ff8080: ctrlr->voltages
8926 16:31:15.681667 sclk: 390625
8927 16:31:15.681780 Bus Width = 1
8928 16:31:15.681863 sclk: 390625
8929 16:31:15.684911 Bus Width = 1
8930 16:31:15.685001 Early init status = 3
8931 16:31:15.691362 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8932 16:31:15.694902 in-header: 03 fc 00 00 01 00 00 00
8933 16:31:15.698311 in-data: 00
8934 16:31:15.701156 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8935 16:31:15.706515 in-header: 03 fd 00 00 00 00 00 00
8936 16:31:15.709413 in-data:
8937 16:31:15.712983 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8938 16:31:15.716514 in-header: 03 fc 00 00 01 00 00 00
8939 16:31:15.720130 in-data: 00
8940 16:31:15.723119 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8941 16:31:15.728083 in-header: 03 fd 00 00 00 00 00 00
8942 16:31:15.731819 in-data:
8943 16:31:15.735308 [SSUSB] Setting up USB HOST controller...
8944 16:31:15.738037 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8945 16:31:15.741420 [SSUSB] phy power-on done.
8946 16:31:15.744555 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8947 16:31:15.751561 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8948 16:31:15.754532 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8949 16:31:15.760900 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8950 16:31:15.767721 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8951 16:31:15.774195 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8952 16:31:15.781091 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8953 16:31:15.787577 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8954 16:31:15.790992 SPM: binary array size = 0x9dc
8955 16:31:15.794374 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8956 16:31:15.801092 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8957 16:31:15.807716 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8958 16:31:15.814172 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8959 16:31:15.817550 configure_display: Starting display init
8960 16:31:15.851214 anx7625_power_on_init: Init interface.
8961 16:31:15.855097 anx7625_disable_pd_protocol: Disabled PD feature.
8962 16:31:15.858144 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8963 16:31:15.885885 anx7625_start_dp_work: Secure OCM version=00
8964 16:31:15.889424 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8965 16:31:15.903965 sp_tx_get_edid_block: EDID Block = 1
8966 16:31:16.006393 Extracted contents:
8967 16:31:16.009773 header: 00 ff ff ff ff ff ff 00
8968 16:31:16.013194 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8969 16:31:16.016323 version: 01 04
8970 16:31:16.019963 basic params: 95 1f 11 78 0a
8971 16:31:16.023484 chroma info: 76 90 94 55 54 90 27 21 50 54
8972 16:31:16.026835 established: 00 00 00
8973 16:31:16.033388 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8974 16:31:16.036484 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8975 16:31:16.042953 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8976 16:31:16.049978 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8977 16:31:16.056386 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8978 16:31:16.059505 extensions: 00
8979 16:31:16.059585 checksum: fb
8980 16:31:16.059644
8981 16:31:16.063280 Manufacturer: IVO Model 57d Serial Number 0
8982 16:31:16.066389 Made week 0 of 2020
8983 16:31:16.066467 EDID version: 1.4
8984 16:31:16.069480 Digital display
8985 16:31:16.072782 6 bits per primary color channel
8986 16:31:16.072861 DisplayPort interface
8987 16:31:16.076360 Maximum image size: 31 cm x 17 cm
8988 16:31:16.079212 Gamma: 220%
8989 16:31:16.079291 Check DPMS levels
8990 16:31:16.082673 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8991 16:31:16.089117 First detailed timing is preferred timing
8992 16:31:16.089199 Established timings supported:
8993 16:31:16.092718 Standard timings supported:
8994 16:31:16.096065 Detailed timings
8995 16:31:16.099403 Hex of detail: 383680a07038204018303c0035ae10000019
8996 16:31:16.102346 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
8997 16:31:16.109326 0780 0798 07c8 0820 hborder 0
8998 16:31:16.112382 0438 043b 0447 0458 vborder 0
8999 16:31:16.115753 -hsync -vsync
9000 16:31:16.115833 Did detailed timing
9001 16:31:16.122101 Hex of detail: 000000000000000000000000000000000000
9002 16:31:16.125843 Manufacturer-specified data, tag 0
9003 16:31:16.128828 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9004 16:31:16.132539 ASCII string: InfoVision
9005 16:31:16.135535 Hex of detail: 000000fe00523134304e574635205248200a
9006 16:31:16.138740 ASCII string: R140NWF5 RH
9007 16:31:16.138823 Checksum
9008 16:31:16.142414 Checksum: 0xfb (valid)
9009 16:31:16.145427 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9010 16:31:16.149010 DSI data_rate: 832800000 bps
9011 16:31:16.155202 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9012 16:31:16.158779 anx7625_parse_edid: pixelclock(138800).
9013 16:31:16.161884 hactive(1920), hsync(48), hfp(24), hbp(88)
9014 16:31:16.165642 vactive(1080), vsync(12), vfp(3), vbp(17)
9015 16:31:16.168477 anx7625_dsi_config: config dsi.
9016 16:31:16.175601 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9017 16:31:16.188376 anx7625_dsi_config: success to config DSI
9018 16:31:16.191964 anx7625_dp_start: MIPI phy setup OK.
9019 16:31:16.195581 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9020 16:31:16.198453 mtk_ddp_mode_set invalid vrefresh 60
9021 16:31:16.201669 main_disp_path_setup
9022 16:31:16.201777 ovl_layer_smi_id_en
9023 16:31:16.205123 ovl_layer_smi_id_en
9024 16:31:16.205216 ccorr_config
9025 16:31:16.205292 aal_config
9026 16:31:16.208260 gamma_config
9027 16:31:16.208340 postmask_config
9028 16:31:16.211854 dither_config
9029 16:31:16.214865 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9030 16:31:16.221414 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9031 16:31:16.224924 Root Device init finished in 553 msecs
9032 16:31:16.228381 CPU_CLUSTER: 0 init
9033 16:31:16.234815 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9034 16:31:16.238412 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9035 16:31:16.241494 APU_MBOX 0x190000b0 = 0x10001
9036 16:31:16.244856 APU_MBOX 0x190001b0 = 0x10001
9037 16:31:16.248028 APU_MBOX 0x190005b0 = 0x10001
9038 16:31:16.251733 APU_MBOX 0x190006b0 = 0x10001
9039 16:31:16.254893 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9040 16:31:16.267493 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9041 16:31:16.279709 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9042 16:31:16.286426 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9043 16:31:16.298185 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9044 16:31:16.307529 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9045 16:31:16.310371 CPU_CLUSTER: 0 init finished in 81 msecs
9046 16:31:16.313786 Devices initialized
9047 16:31:16.317120 Show all devs... After init.
9048 16:31:16.317216 Root Device: enabled 1
9049 16:31:16.320846 CPU_CLUSTER: 0: enabled 1
9050 16:31:16.323827 CPU: 00: enabled 1
9051 16:31:16.327475 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9052 16:31:16.330985 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9053 16:31:16.333818 ELOG: NV offset 0x57f000 size 0x1000
9054 16:31:16.340272 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9055 16:31:16.347458 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9056 16:31:16.350596 ELOG: Event(17) added with size 13 at 2024-06-17 16:31:16 UTC
9057 16:31:16.353529 out: cmd=0x121: 03 db 21 01 00 00 00 00
9058 16:31:16.357237 in-header: 03 48 00 00 2c 00 00 00
9059 16:31:16.370779 in-data: fb 6c 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9060 16:31:16.377317 ELOG: Event(A1) added with size 10 at 2024-06-17 16:31:16 UTC
9061 16:31:16.384347 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9062 16:31:16.390608 ELOG: Event(A0) added with size 9 at 2024-06-17 16:31:16 UTC
9063 16:31:16.394038 elog_add_boot_reason: Logged dev mode boot
9064 16:31:16.397191 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9065 16:31:16.400880 Finalize devices...
9066 16:31:16.400979 Devices finalized
9067 16:31:16.407183 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9068 16:31:16.410752 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9069 16:31:16.414219 in-header: 03 07 00 00 08 00 00 00
9070 16:31:16.417128 in-data: aa e4 47 04 13 02 00 00
9071 16:31:16.417225 Chrome EC: UHEPI supported
9072 16:31:16.423775 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9073 16:31:16.427394 in-header: 03 a9 00 00 08 00 00 00
9074 16:31:16.430941 in-data: 84 60 60 08 00 00 00 00
9075 16:31:16.437288 ELOG: Event(91) added with size 10 at 2024-06-17 16:31:16 UTC
9076 16:31:16.440946 Chrome EC: clear events_b mask to 0x0000000020004000
9077 16:31:16.447274 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9078 16:31:16.452668 in-header: 03 fd 00 00 00 00 00 00
9079 16:31:16.455497 in-data:
9080 16:31:16.458938 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9081 16:31:16.462188 Writing coreboot table at 0xffe64000
9082 16:31:16.465347 0. 000000000010a000-0000000000113fff: RAMSTAGE
9083 16:31:16.472175 1. 0000000040000000-00000000400fffff: RAM
9084 16:31:16.475417 2. 0000000040100000-000000004032afff: RAMSTAGE
9085 16:31:16.478996 3. 000000004032b000-00000000545fffff: RAM
9086 16:31:16.482128 4. 0000000054600000-000000005465ffff: BL31
9087 16:31:16.485225 5. 0000000054660000-00000000ffe63fff: RAM
9088 16:31:16.492309 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9089 16:31:16.495817 7. 0000000100000000-000000013fffffff: RAM
9090 16:31:16.498782 Passing 5 GPIOs to payload:
9091 16:31:16.502096 NAME | PORT | POLARITY | VALUE
9092 16:31:16.509155 EC in RW | 0x000000aa | low | undefined
9093 16:31:16.511953 EC interrupt | 0x00000005 | low | undefined
9094 16:31:16.515487 TPM interrupt | 0x000000ab | high | undefined
9095 16:31:16.522069 SD card detect | 0x00000011 | high | undefined
9096 16:31:16.525642 speaker enable | 0x00000093 | high | undefined
9097 16:31:16.528977 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9098 16:31:16.532243 in-header: 03 f8 00 00 02 00 00 00
9099 16:31:16.535735 in-data: 03 00
9100 16:31:16.538577 ADC[4]: Raw value=669327 ID=5
9101 16:31:16.538672 ADC[3]: Raw value=212549 ID=1
9102 16:31:16.542148 RAM Code: 0x51
9103 16:31:16.545605 ADC[6]: Raw value=74410 ID=0
9104 16:31:16.545704 ADC[5]: Raw value=211444 ID=1
9105 16:31:16.548525 SKU Code: 0x1
9106 16:31:16.555429 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e843
9107 16:31:16.555504 coreboot table: 964 bytes.
9108 16:31:16.558293 IMD ROOT 0. 0xfffff000 0x00001000
9109 16:31:16.561968 IMD SMALL 1. 0xffffe000 0x00001000
9110 16:31:16.564844 RO MCACHE 2. 0xffffc000 0x00001104
9111 16:31:16.568273 CONSOLE 3. 0xfff7c000 0x00080000
9112 16:31:16.571694 FMAP 4. 0xfff7b000 0x00000452
9113 16:31:16.575050 TIME STAMP 5. 0xfff7a000 0x00000910
9114 16:31:16.578373 VBOOT WORK 6. 0xfff66000 0x00014000
9115 16:31:16.581557 RAMOOPS 7. 0xffe66000 0x00100000
9116 16:31:16.584787 COREBOOT 8. 0xffe64000 0x00002000
9117 16:31:16.588396 IMD small region:
9118 16:31:16.591684 IMD ROOT 0. 0xffffec00 0x00000400
9119 16:31:16.594632 VPD 1. 0xffffeb80 0x0000006c
9120 16:31:16.598080 MMC STATUS 2. 0xffffeb60 0x00000004
9121 16:31:16.601672 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9122 16:31:16.608242 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9123 16:31:16.648899 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9124 16:31:16.652512 Checking segment from ROM address 0x40100000
9125 16:31:16.655977 Checking segment from ROM address 0x4010001c
9126 16:31:16.662472 Loading segment from ROM address 0x40100000
9127 16:31:16.662577 code (compression=0)
9128 16:31:16.672364 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9129 16:31:16.679329 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9130 16:31:16.679412 it's not compressed!
9131 16:31:16.686010 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9132 16:31:16.692021 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9133 16:31:16.709365 Loading segment from ROM address 0x4010001c
9134 16:31:16.709469 Entry Point 0x80000000
9135 16:31:16.713013 Loaded segments
9136 16:31:16.716461 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9137 16:31:16.722634 Jumping to boot code at 0x80000000(0xffe64000)
9138 16:31:16.729662 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9139 16:31:16.736015 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9140 16:31:16.744056 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9141 16:31:16.747249 Checking segment from ROM address 0x40100000
9142 16:31:16.750546 Checking segment from ROM address 0x4010001c
9143 16:31:16.757036 Loading segment from ROM address 0x40100000
9144 16:31:16.757119 code (compression=1)
9145 16:31:16.764210 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9146 16:31:16.773514 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9147 16:31:16.773602 using LZMA
9148 16:31:16.782629 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9149 16:31:16.789126 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9150 16:31:16.792523 Loading segment from ROM address 0x4010001c
9151 16:31:16.792629 Entry Point 0x54601000
9152 16:31:16.795358 Loaded segments
9153 16:31:16.798943 NOTICE: MT8192 bl31_setup
9154 16:31:16.806274 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9155 16:31:16.809341 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9156 16:31:16.812811 WARNING: region 0:
9157 16:31:16.815758 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9158 16:31:16.815838 WARNING: region 1:
9159 16:31:16.822656 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9160 16:31:16.825944 WARNING: region 2:
9161 16:31:16.829131 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9162 16:31:16.832679 WARNING: region 3:
9163 16:31:16.836096 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9164 16:31:16.839071 WARNING: region 4:
9165 16:31:16.845681 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9166 16:31:16.845761 WARNING: region 5:
9167 16:31:16.849197 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9168 16:31:16.852625 WARNING: region 6:
9169 16:31:16.855844 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9170 16:31:16.859183 WARNING: region 7:
9171 16:31:16.862685 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9172 16:31:16.869264 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9173 16:31:16.872538 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9174 16:31:16.875538 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9175 16:31:16.882393 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9176 16:31:16.885365 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9177 16:31:16.892367 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9178 16:31:16.895642 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9179 16:31:16.898811 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9180 16:31:16.905389 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9181 16:31:16.908659 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9182 16:31:16.911998 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9183 16:31:16.918298 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9184 16:31:16.921797 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9185 16:31:16.928161 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9186 16:31:16.931833 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9187 16:31:16.935081 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9188 16:31:16.941480 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9189 16:31:16.945052 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9190 16:31:16.951522 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9191 16:31:16.955063 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9192 16:31:16.958496 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9193 16:31:16.965109 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9194 16:31:16.968455 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9195 16:31:16.971797 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9196 16:31:16.978227 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9197 16:31:16.981767 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9198 16:31:16.988319 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9199 16:31:16.991345 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9200 16:31:16.997710 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9201 16:31:17.001216 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9202 16:31:17.004684 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9203 16:31:17.010802 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9204 16:31:17.014675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9205 16:31:17.017765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9206 16:31:17.020888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9207 16:31:17.027856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9208 16:31:17.031319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9209 16:31:17.034196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9210 16:31:17.037746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9211 16:31:17.044426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9212 16:31:17.047315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9213 16:31:17.050945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9214 16:31:17.053972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9215 16:31:17.061009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9216 16:31:17.063912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9217 16:31:17.067423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9218 16:31:17.074126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9219 16:31:17.077648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9220 16:31:17.080809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9221 16:31:17.087061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9222 16:31:17.090483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9223 16:31:17.097520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9224 16:31:17.100493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9225 16:31:17.103902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9226 16:31:17.110712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9227 16:31:17.113881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9228 16:31:17.120425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9229 16:31:17.123991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9230 16:31:17.130752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9231 16:31:17.134135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9232 16:31:17.140494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9233 16:31:17.143935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9234 16:31:17.146883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9235 16:31:17.153735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9236 16:31:17.156863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9237 16:31:17.163862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9238 16:31:17.166693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9239 16:31:17.173202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9240 16:31:17.176837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9241 16:31:17.183519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9242 16:31:17.186550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9243 16:31:17.190008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9244 16:31:17.196793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9245 16:31:17.199949 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9246 16:31:17.206327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9247 16:31:17.209884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9248 16:31:17.216215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9249 16:31:17.219726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9250 16:31:17.226356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9251 16:31:17.229700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9252 16:31:17.232827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9253 16:31:17.239539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9254 16:31:17.242973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9255 16:31:17.249398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9256 16:31:17.252756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9257 16:31:17.259225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9258 16:31:17.262747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9259 16:31:17.265847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9260 16:31:17.272699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9261 16:31:17.275729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9262 16:31:17.282683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9263 16:31:17.286235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9264 16:31:17.292280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9265 16:31:17.295742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9266 16:31:17.302232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9267 16:31:17.305524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9268 16:31:17.308886 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9269 16:31:17.315540 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9270 16:31:17.318823 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9271 16:31:17.322258 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9272 16:31:17.325732 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9273 16:31:17.332496 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9274 16:31:17.335384 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9275 16:31:17.341981 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9276 16:31:17.345543 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9277 16:31:17.348478 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9278 16:31:17.355030 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9279 16:31:17.358393 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9280 16:31:17.365242 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9281 16:31:17.368272 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9282 16:31:17.371799 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9283 16:31:17.378228 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9284 16:31:17.381727 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9285 16:31:17.388508 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9286 16:31:17.391703 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9287 16:31:17.394730 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9288 16:31:17.401492 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9289 16:31:17.404810 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9290 16:31:17.408502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9291 16:31:17.414915 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9292 16:31:17.417992 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9293 16:31:17.421386 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9294 16:31:17.424979 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9295 16:31:17.431497 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9296 16:31:17.434608 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9297 16:31:17.437973 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9298 16:31:17.444336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9299 16:31:17.448165 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9300 16:31:17.458876 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9301 16:31:17.459139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9302 16:31:17.461395 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9303 16:31:17.467590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9304 16:31:17.470639 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9305 16:31:17.477718 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9306 16:31:17.480719 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9307 16:31:17.484170 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9308 16:31:17.490705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9309 16:31:17.494058 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9310 16:31:17.500356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9311 16:31:17.503911 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9312 16:31:17.507516 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9313 16:31:17.513746 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9314 16:31:17.517095 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9315 16:31:17.523904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9316 16:31:17.527171 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9317 16:31:17.530755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9318 16:31:17.537101 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9319 16:31:17.540185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9320 16:31:17.546898 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9321 16:31:17.550394 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9322 16:31:17.553408 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9323 16:31:17.560257 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9324 16:31:17.563514 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9325 16:31:17.570409 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9326 16:31:17.573330 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9327 16:31:17.577164 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9328 16:31:17.583729 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9329 16:31:17.587295 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9330 16:31:17.590182 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9331 16:31:17.596880 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9332 16:31:17.600264 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9333 16:31:17.606712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9334 16:31:17.610010 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9335 16:31:17.613482 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9336 16:31:17.619827 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9337 16:31:17.623592 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9338 16:31:17.629788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9339 16:31:17.633480 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9340 16:31:17.636740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9341 16:31:17.643213 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9342 16:31:17.646426 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9343 16:31:17.653200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9344 16:31:17.656580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9345 16:31:17.659758 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9346 16:31:17.666670 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9347 16:31:17.670178 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9348 16:31:17.676510 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9349 16:31:17.679731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9350 16:31:17.682995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9351 16:31:17.689954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9352 16:31:17.692905 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9353 16:31:17.696309 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9354 16:31:17.702823 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9355 16:31:17.706358 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9356 16:31:17.713117 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9357 16:31:17.716040 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9358 16:31:17.719536 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9359 16:31:17.726481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9360 16:31:17.729475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9361 16:31:17.736319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9362 16:31:17.739333 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9363 16:31:17.745858 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9364 16:31:17.749340 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9365 16:31:17.752702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9366 16:31:17.759682 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9367 16:31:17.762661 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9368 16:31:17.769385 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9369 16:31:17.772766 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9370 16:31:17.776403 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9371 16:31:17.782791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9372 16:31:17.785989 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9373 16:31:17.792835 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9374 16:31:17.795694 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9375 16:31:17.802745 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9376 16:31:17.805729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9377 16:31:17.809298 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9378 16:31:17.815844 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9379 16:31:17.819394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9380 16:31:17.825828 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9381 16:31:17.829292 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9382 16:31:17.832219 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9383 16:31:17.838738 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9384 16:31:17.842206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9385 16:31:17.848718 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9386 16:31:17.852195 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9387 16:31:17.855630 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9388 16:31:17.862370 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9389 16:31:17.865638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9390 16:31:17.872156 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9391 16:31:17.875407 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9392 16:31:17.881908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9393 16:31:17.885943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9394 16:31:17.888963 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9395 16:31:17.895590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9396 16:31:17.898995 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9397 16:31:17.905714 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9398 16:31:17.909232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9399 16:31:17.915574 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9400 16:31:17.919050 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9401 16:31:17.922002 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9402 16:31:17.925509 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9403 16:31:17.931917 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9404 16:31:17.935431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9405 16:31:17.939017 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9406 16:31:17.941915 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9407 16:31:17.948784 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9408 16:31:17.952165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9409 16:31:17.958466 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9410 16:31:17.962095 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9411 16:31:17.965359 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9412 16:31:17.971669 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9413 16:31:17.975278 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9414 16:31:17.978217 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9415 16:31:17.984929 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9416 16:31:17.988838 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9417 16:31:17.991966 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9418 16:31:17.998491 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9419 16:31:18.001914 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9420 16:31:18.008193 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9421 16:31:18.011769 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9422 16:31:18.014986 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9423 16:31:18.021846 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9424 16:31:18.024803 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9425 16:31:18.028719 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9426 16:31:18.035013 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9427 16:31:18.038388 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9428 16:31:18.041699 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9429 16:31:18.048270 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9430 16:31:18.051763 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9431 16:31:18.058146 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9432 16:31:18.061677 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9433 16:31:18.064878 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9434 16:31:18.071349 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9435 16:31:18.074831 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9436 16:31:18.077831 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9437 16:31:18.085022 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9438 16:31:18.087911 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9439 16:31:18.094823 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9440 16:31:18.098046 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9441 16:31:18.101323 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9442 16:31:18.104793 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9443 16:31:18.107722 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9444 16:31:18.114672 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9445 16:31:18.117988 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9446 16:31:18.121023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9447 16:31:18.124526 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9448 16:31:18.131406 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9449 16:31:18.134297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9450 16:31:18.137696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9451 16:31:18.141069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9452 16:31:18.147604 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9453 16:31:18.150888 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9454 16:31:18.154068 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9455 16:31:18.161102 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9456 16:31:18.163975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9457 16:31:18.170874 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9458 16:31:18.174114 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9459 16:31:18.180436 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9460 16:31:18.184121 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9461 16:31:18.187741 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9462 16:31:18.194496 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9463 16:31:18.197302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9464 16:31:18.204178 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9465 16:31:18.207468 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9466 16:31:18.211099 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9467 16:31:18.217546 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9468 16:31:18.220559 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9469 16:31:18.227411 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9470 16:31:18.230718 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9471 16:31:18.234106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9472 16:31:18.240409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9473 16:31:18.244081 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9474 16:31:18.250440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9475 16:31:18.253917 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9476 16:31:18.260291 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9477 16:31:18.263825 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9478 16:31:18.266832 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9479 16:31:18.273865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9480 16:31:18.277247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9481 16:31:18.283927 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9482 16:31:18.286880 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9483 16:31:18.290403 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9484 16:31:18.296863 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9485 16:31:18.300379 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9486 16:31:18.306802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9487 16:31:18.310158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9488 16:31:18.313406 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9489 16:31:18.320166 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9490 16:31:18.323192 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9491 16:31:18.329692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9492 16:31:18.333173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9493 16:31:18.336616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9494 16:31:18.343449 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9495 16:31:18.346941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9496 16:31:18.353201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9497 16:31:18.356637 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9498 16:31:18.362940 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9499 16:31:18.366498 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9500 16:31:18.369485 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9501 16:31:18.376454 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9502 16:31:18.379993 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9503 16:31:18.386790 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9504 16:31:18.389811 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9505 16:31:18.393330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9506 16:31:18.399628 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9507 16:31:18.403038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9508 16:31:18.409540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9509 16:31:18.413098 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9510 16:31:18.416106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9511 16:31:18.422761 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9512 16:31:18.426106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9513 16:31:18.432638 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9514 16:31:18.436354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9515 16:31:18.442732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9516 16:31:18.446239 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9517 16:31:18.449334 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9518 16:31:18.456595 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9519 16:31:18.459241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9520 16:31:18.465775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9521 16:31:18.468948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9522 16:31:18.472507 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9523 16:31:18.478995 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9524 16:31:18.482698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9525 16:31:18.488894 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9526 16:31:18.492286 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9527 16:31:18.498958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9528 16:31:18.502472 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9529 16:31:18.505468 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9530 16:31:18.512431 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9531 16:31:18.515419 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9532 16:31:18.521885 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9533 16:31:18.525379 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9534 16:31:18.531921 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9535 16:31:18.535194 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9536 16:31:18.538792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9537 16:31:18.545212 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9538 16:31:18.548753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9539 16:31:18.555487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9540 16:31:18.558228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9541 16:31:18.564777 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9542 16:31:18.568481 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9543 16:31:18.574926 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9544 16:31:18.578624 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9545 16:31:18.581730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9546 16:31:18.588552 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9547 16:31:18.591503 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9548 16:31:18.597872 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9549 16:31:18.601233 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9550 16:31:18.608206 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9551 16:31:18.611032 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9552 16:31:18.618060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9553 16:31:18.621011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9554 16:31:18.624729 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9555 16:31:18.631322 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9556 16:31:18.634733 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9557 16:31:18.641389 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9558 16:31:18.644178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9559 16:31:18.651082 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9560 16:31:18.654668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9561 16:31:18.660936 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9562 16:31:18.664257 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9563 16:31:18.667754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9564 16:31:18.674465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9565 16:31:18.677333 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9566 16:31:18.684175 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9567 16:31:18.687542 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9568 16:31:18.693900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9569 16:31:18.697423 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9570 16:31:18.703791 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9571 16:31:18.707069 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9572 16:31:18.710480 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9573 16:31:18.716875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9574 16:31:18.720377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9575 16:31:18.724059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9576 16:31:18.730792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9577 16:31:18.733873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9578 16:31:18.740267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9579 16:31:18.743792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9580 16:31:18.750300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9581 16:31:18.753374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9582 16:31:18.760248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9583 16:31:18.763162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9584 16:31:18.770106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9585 16:31:18.773695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9586 16:31:18.779984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9587 16:31:18.783129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9588 16:31:18.790109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9589 16:31:18.792833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9590 16:31:18.799797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9591 16:31:18.803028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9592 16:31:18.809644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9593 16:31:18.813151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9594 16:31:18.819670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9595 16:31:18.822873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9596 16:31:18.829567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9597 16:31:18.832689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9598 16:31:18.839541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9599 16:31:18.842453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9600 16:31:18.849065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9601 16:31:18.852463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9602 16:31:18.859280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9603 16:31:18.862792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9604 16:31:18.868916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9605 16:31:18.872375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9606 16:31:18.879058 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9607 16:31:18.879166 INFO: [APUAPC] vio 0
9608 16:31:18.885963 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9609 16:31:18.888979 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9610 16:31:18.892515 INFO: [APUAPC] D0_APC_0: 0x400510
9611 16:31:18.896339 INFO: [APUAPC] D0_APC_1: 0x0
9612 16:31:18.899005 INFO: [APUAPC] D0_APC_2: 0x1540
9613 16:31:18.902554 INFO: [APUAPC] D0_APC_3: 0x0
9614 16:31:18.905939 INFO: [APUAPC] D1_APC_0: 0xffffffff
9615 16:31:18.909432 INFO: [APUAPC] D1_APC_1: 0xffffffff
9616 16:31:18.912446 INFO: [APUAPC] D1_APC_2: 0x3fffff
9617 16:31:18.915924 INFO: [APUAPC] D1_APC_3: 0x0
9618 16:31:18.919014 INFO: [APUAPC] D2_APC_0: 0xffffffff
9619 16:31:18.922568 INFO: [APUAPC] D2_APC_1: 0xffffffff
9620 16:31:18.925947 INFO: [APUAPC] D2_APC_2: 0x3fffff
9621 16:31:18.928788 INFO: [APUAPC] D2_APC_3: 0x0
9622 16:31:18.932143 INFO: [APUAPC] D3_APC_0: 0xffffffff
9623 16:31:18.935352 INFO: [APUAPC] D3_APC_1: 0xffffffff
9624 16:31:18.939245 INFO: [APUAPC] D3_APC_2: 0x3fffff
9625 16:31:18.942065 INFO: [APUAPC] D3_APC_3: 0x0
9626 16:31:18.945747 INFO: [APUAPC] D4_APC_0: 0xffffffff
9627 16:31:18.948674 INFO: [APUAPC] D4_APC_1: 0xffffffff
9628 16:31:18.952165 INFO: [APUAPC] D4_APC_2: 0x3fffff
9629 16:31:18.952243 INFO: [APUAPC] D4_APC_3: 0x0
9630 16:31:18.958827 INFO: [APUAPC] D5_APC_0: 0xffffffff
9631 16:31:18.961880 INFO: [APUAPC] D5_APC_1: 0xffffffff
9632 16:31:18.965227 INFO: [APUAPC] D5_APC_2: 0x3fffff
9633 16:31:18.965306 INFO: [APUAPC] D5_APC_3: 0x0
9634 16:31:18.968674 INFO: [APUAPC] D6_APC_0: 0xffffffff
9635 16:31:18.971827 INFO: [APUAPC] D6_APC_1: 0xffffffff
9636 16:31:18.974995 INFO: [APUAPC] D6_APC_2: 0x3fffff
9637 16:31:18.978715 INFO: [APUAPC] D6_APC_3: 0x0
9638 16:31:18.981816 INFO: [APUAPC] D7_APC_0: 0xffffffff
9639 16:31:18.985442 INFO: [APUAPC] D7_APC_1: 0xffffffff
9640 16:31:18.988647 INFO: [APUAPC] D7_APC_2: 0x3fffff
9641 16:31:18.991688 INFO: [APUAPC] D7_APC_3: 0x0
9642 16:31:18.995129 INFO: [APUAPC] D8_APC_0: 0xffffffff
9643 16:31:18.998172 INFO: [APUAPC] D8_APC_1: 0xffffffff
9644 16:31:19.001788 INFO: [APUAPC] D8_APC_2: 0x3fffff
9645 16:31:19.004737 INFO: [APUAPC] D8_APC_3: 0x0
9646 16:31:19.008390 INFO: [APUAPC] D9_APC_0: 0xffffffff
9647 16:31:19.011828 INFO: [APUAPC] D9_APC_1: 0xffffffff
9648 16:31:19.014893 INFO: [APUAPC] D9_APC_2: 0x3fffff
9649 16:31:19.018343 INFO: [APUAPC] D9_APC_3: 0x0
9650 16:31:19.021447 INFO: [APUAPC] D10_APC_0: 0xffffffff
9651 16:31:19.025091 INFO: [APUAPC] D10_APC_1: 0xffffffff
9652 16:31:19.028038 INFO: [APUAPC] D10_APC_2: 0x3fffff
9653 16:31:19.031634 INFO: [APUAPC] D10_APC_3: 0x0
9654 16:31:19.034581 INFO: [APUAPC] D11_APC_0: 0xffffffff
9655 16:31:19.038003 INFO: [APUAPC] D11_APC_1: 0xffffffff
9656 16:31:19.041318 INFO: [APUAPC] D11_APC_2: 0x3fffff
9657 16:31:19.045202 INFO: [APUAPC] D11_APC_3: 0x0
9658 16:31:19.048189 INFO: [APUAPC] D12_APC_0: 0xffffffff
9659 16:31:19.051548 INFO: [APUAPC] D12_APC_1: 0xffffffff
9660 16:31:19.054532 INFO: [APUAPC] D12_APC_2: 0x3fffff
9661 16:31:19.058093 INFO: [APUAPC] D12_APC_3: 0x0
9662 16:31:19.061157 INFO: [APUAPC] D13_APC_0: 0xffffffff
9663 16:31:19.064806 INFO: [APUAPC] D13_APC_1: 0xffffffff
9664 16:31:19.067773 INFO: [APUAPC] D13_APC_2: 0x3fffff
9665 16:31:19.071270 INFO: [APUAPC] D13_APC_3: 0x0
9666 16:31:19.074806 INFO: [APUAPC] D14_APC_0: 0xffffffff
9667 16:31:19.077704 INFO: [APUAPC] D14_APC_1: 0xffffffff
9668 16:31:19.080973 INFO: [APUAPC] D14_APC_2: 0x3fffff
9669 16:31:19.084301 INFO: [APUAPC] D14_APC_3: 0x0
9670 16:31:19.087825 INFO: [APUAPC] D15_APC_0: 0xffffffff
9671 16:31:19.091222 INFO: [APUAPC] D15_APC_1: 0xffffffff
9672 16:31:19.094425 INFO: [APUAPC] D15_APC_2: 0x3fffff
9673 16:31:19.097792 INFO: [APUAPC] D15_APC_3: 0x0
9674 16:31:19.101268 INFO: [APUAPC] APC_CON: 0x4
9675 16:31:19.104417 INFO: [NOCDAPC] D0_APC_0: 0x0
9676 16:31:19.107397 INFO: [NOCDAPC] D0_APC_1: 0x0
9677 16:31:19.110875 INFO: [NOCDAPC] D1_APC_0: 0x0
9678 16:31:19.114327 INFO: [NOCDAPC] D1_APC_1: 0xfff
9679 16:31:19.117821 INFO: [NOCDAPC] D2_APC_0: 0x0
9680 16:31:19.120753 INFO: [NOCDAPC] D2_APC_1: 0xfff
9681 16:31:19.124001 INFO: [NOCDAPC] D3_APC_0: 0x0
9682 16:31:19.124100 INFO: [NOCDAPC] D3_APC_1: 0xfff
9683 16:31:19.127347 INFO: [NOCDAPC] D4_APC_0: 0x0
9684 16:31:19.130780 INFO: [NOCDAPC] D4_APC_1: 0xfff
9685 16:31:19.134231 INFO: [NOCDAPC] D5_APC_0: 0x0
9686 16:31:19.137302 INFO: [NOCDAPC] D5_APC_1: 0xfff
9687 16:31:19.140705 INFO: [NOCDAPC] D6_APC_0: 0x0
9688 16:31:19.143786 INFO: [NOCDAPC] D6_APC_1: 0xfff
9689 16:31:19.147185 INFO: [NOCDAPC] D7_APC_0: 0x0
9690 16:31:19.150637 INFO: [NOCDAPC] D7_APC_1: 0xfff
9691 16:31:19.154084 INFO: [NOCDAPC] D8_APC_0: 0x0
9692 16:31:19.157220 INFO: [NOCDAPC] D8_APC_1: 0xfff
9693 16:31:19.157299 INFO: [NOCDAPC] D9_APC_0: 0x0
9694 16:31:19.160647 INFO: [NOCDAPC] D9_APC_1: 0xfff
9695 16:31:19.163770 INFO: [NOCDAPC] D10_APC_0: 0x0
9696 16:31:19.166800 INFO: [NOCDAPC] D10_APC_1: 0xfff
9697 16:31:19.170063 INFO: [NOCDAPC] D11_APC_0: 0x0
9698 16:31:19.173822 INFO: [NOCDAPC] D11_APC_1: 0xfff
9699 16:31:19.177253 INFO: [NOCDAPC] D12_APC_0: 0x0
9700 16:31:19.180154 INFO: [NOCDAPC] D12_APC_1: 0xfff
9701 16:31:19.183390 INFO: [NOCDAPC] D13_APC_0: 0x0
9702 16:31:19.186636 INFO: [NOCDAPC] D13_APC_1: 0xfff
9703 16:31:19.190456 INFO: [NOCDAPC] D14_APC_0: 0x0
9704 16:31:19.193354 INFO: [NOCDAPC] D14_APC_1: 0xfff
9705 16:31:19.196974 INFO: [NOCDAPC] D15_APC_0: 0x0
9706 16:31:19.200407 INFO: [NOCDAPC] D15_APC_1: 0xfff
9707 16:31:19.203489 INFO: [NOCDAPC] APC_CON: 0x4
9708 16:31:19.206900 INFO: [APUAPC] set_apusys_apc done
9709 16:31:19.206983 INFO: [DEVAPC] devapc_init done
9710 16:31:19.213253 INFO: GICv3 without legacy support detected.
9711 16:31:19.216450 INFO: ARM GICv3 driver initialized in EL3
9712 16:31:19.219736 INFO: Maximum SPI INTID supported: 639
9713 16:31:19.223283 INFO: BL31: Initializing runtime services
9714 16:31:19.229975 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9715 16:31:19.233343 INFO: SPM: enable CPC mode
9716 16:31:19.236726 INFO: mcdi ready for mcusys-off-idle and system suspend
9717 16:31:19.243264 INFO: BL31: Preparing for EL3 exit to normal world
9718 16:31:19.246686 INFO: Entry point address = 0x80000000
9719 16:31:19.246780 INFO: SPSR = 0x8
9720 16:31:19.253936
9721 16:31:19.254042
9722 16:31:19.254127
9723 16:31:19.257397 Starting depthcharge on Spherion...
9724 16:31:19.257488
9725 16:31:19.257575 Wipe memory regions:
9726 16:31:19.257654
9727 16:31:19.258383 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9728 16:31:19.258500 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9729 16:31:19.258604 Setting prompt string to ['asurada:']
9730 16:31:19.258710 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9731 16:31:19.260269 [0x00000040000000, 0x00000054600000)
9732 16:31:19.382610
9733 16:31:19.382729 [0x00000054660000, 0x00000080000000)
9734 16:31:19.643002
9735 16:31:19.643115 [0x000000821a7280, 0x000000ffe64000)
9736 16:31:20.387893
9737 16:31:20.388086 [0x00000100000000, 0x00000140000000)
9738 16:31:20.768982
9739 16:31:20.772393 Initializing XHCI USB controller at 0x11200000.
9740 16:31:21.810024
9741 16:31:21.813232 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9742 16:31:21.813350
9743 16:31:21.813442
9744 16:31:21.813745 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9746 16:31:21.914143 asurada: tftpboot 192.168.201.1 14396103/tftp-deploy-kg8v5wn8/kernel/image.itb 14396103/tftp-deploy-kg8v5wn8/kernel/cmdline
9747 16:31:21.914396 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9748 16:31:21.914482 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
9749 16:31:21.918793 tftpboot 192.168.201.1 14396103/tftp-deploy-kg8v5wn8/kernel/image.itp-deploy-kg8v5wn8/kernel/cmdline
9750 16:31:21.918874
9751 16:31:21.918935 Waiting for link
9752 16:31:22.077225
9753 16:31:22.077360 R8152: Initializing
9754 16:31:22.077449
9755 16:31:22.079929 Version 9 (ocp_data = 6010)
9756 16:31:22.080001
9757 16:31:22.082914 R8152: Done initializing
9758 16:31:22.082985
9759 16:31:22.083042 Adding net device
9760 16:31:24.150294
9761 16:31:24.150443 done.
9762 16:31:24.150534
9763 16:31:24.150619 MAC: 00:e0:4c:68:03:bd
9764 16:31:24.150702
9765 16:31:24.153784 Sending DHCP discover... done.
9766 16:31:24.153887
9767 16:31:28.423550 Waiting for reply... done.
9768 16:31:28.423669
9769 16:31:28.423730 Sending DHCP request... done.
9770 16:31:28.427294
9771 16:31:28.427378 Waiting for reply... done.
9772 16:31:28.427438
9773 16:31:28.430873 My ip is 192.168.201.16
9774 16:31:28.430951
9775 16:31:28.434004 The DHCP server ip is 192.168.201.1
9776 16:31:28.434085
9777 16:31:28.436986 TFTP server IP predefined by user: 192.168.201.1
9778 16:31:28.437067
9779 16:31:28.443788 Bootfile predefined by user: 14396103/tftp-deploy-kg8v5wn8/kernel/image.itb
9780 16:31:28.443872
9781 16:31:28.446984 Sending tftp read request... done.
9782 16:31:28.447064
9783 16:31:28.450150 Waiting for the transfer...
9784 16:31:28.450299
9785 16:31:28.735603 00000000 ################################################################
9786 16:31:28.735724
9787 16:31:29.012332 00080000 ################################################################
9788 16:31:29.012455
9789 16:31:29.291110 00100000 ################################################################
9790 16:31:29.291238
9791 16:31:29.586864 00180000 ################################################################
9792 16:31:29.586995
9793 16:31:29.865226 00200000 ################################################################
9794 16:31:29.865342
9795 16:31:30.148440 00280000 ################################################################
9796 16:31:30.148560
9797 16:31:30.408406 00300000 ################################################################
9798 16:31:30.408524
9799 16:31:30.660830 00380000 ################################################################
9800 16:31:30.660962
9801 16:31:30.913885 00400000 ################################################################
9802 16:31:30.914000
9803 16:31:31.169631 00480000 ################################################################
9804 16:31:31.169793
9805 16:31:31.417279 00500000 ################################################################
9806 16:31:31.417397
9807 16:31:31.667887 00580000 ################################################################
9808 16:31:31.667999
9809 16:31:31.925959 00600000 ################################################################
9810 16:31:31.926110
9811 16:31:32.181324 00680000 ################################################################
9812 16:31:32.181484
9813 16:31:32.431057 00700000 ################################################################
9814 16:31:32.431217
9815 16:31:32.682287 00780000 ################################################################
9816 16:31:32.682407
9817 16:31:32.928542 00800000 ################################################################
9818 16:31:32.928662
9819 16:31:33.177436 00880000 ################################################################
9820 16:31:33.177554
9821 16:31:33.424396 00900000 ################################################################
9822 16:31:33.424521
9823 16:31:33.669272 00980000 ################################################################
9824 16:31:33.669389
9825 16:31:33.943521 00a00000 ################################################################
9826 16:31:33.943679
9827 16:31:34.221589 00a80000 ################################################################
9828 16:31:34.221709
9829 16:31:34.481593 00b00000 ################################################################
9830 16:31:34.481706
9831 16:31:34.745008 00b80000 ################################################################
9832 16:31:34.745114
9833 16:31:35.008296 00c00000 ################################################################
9834 16:31:35.008413
9835 16:31:35.276814 00c80000 ################################################################
9836 16:31:35.276931
9837 16:31:35.523907 00d00000 ################################################################
9838 16:31:35.524049
9839 16:31:35.768975 00d80000 ################################################################
9840 16:31:35.769092
9841 16:31:36.027430 00e00000 ################################################################
9842 16:31:36.027566
9843 16:31:36.286488 00e80000 ################################################################
9844 16:31:36.286600
9845 16:31:36.533489 00f00000 ################################################################
9846 16:31:36.533631
9847 16:31:36.790963 00f80000 ################################################################
9848 16:31:36.791102
9849 16:31:37.060788 01000000 ################################################################
9850 16:31:37.060928
9851 16:31:37.343656 01080000 ################################################################
9852 16:31:37.343798
9853 16:31:37.618561 01100000 ################################################################
9854 16:31:37.618700
9855 16:31:37.885245 01180000 ################################################################
9856 16:31:37.885384
9857 16:31:38.147708 01200000 ################################################################
9858 16:31:38.147846
9859 16:31:38.398170 01280000 ################################################################
9860 16:31:38.398296
9861 16:31:38.652745 01300000 ################################################################
9862 16:31:38.652886
9863 16:31:38.900220 01380000 ################################################################
9864 16:31:38.900337
9865 16:31:39.146379 01400000 ################################################################
9866 16:31:39.146492
9867 16:31:39.390982 01480000 ################################################################
9868 16:31:39.391096
9869 16:31:39.649728 01500000 ################################################################
9870 16:31:39.649846
9871 16:31:39.911699 01580000 ################################################################
9872 16:31:39.911818
9873 16:31:40.182404 01600000 ################################################################
9874 16:31:40.182516
9875 16:31:40.444932 01680000 ################################################################
9876 16:31:40.445064
9877 16:31:40.690566 01700000 ################################################################
9878 16:31:40.690704
9879 16:31:40.936544 01780000 ################################################################
9880 16:31:40.936682
9881 16:31:41.180474 01800000 ################################################################
9882 16:31:41.180622
9883 16:31:41.424825 01880000 ################################################################
9884 16:31:41.424958
9885 16:31:41.668887 01900000 ################################################################
9886 16:31:41.669025
9887 16:31:41.907232 01980000 ################################################################
9888 16:31:41.907373
9889 16:31:42.152804 01a00000 ################################################################
9890 16:31:42.152917
9891 16:31:42.387545 01a80000 ################################################################
9892 16:31:42.387658
9893 16:31:42.628196 01b00000 ################################################################
9894 16:31:42.628331
9895 16:31:42.881004 01b80000 ################################################################
9896 16:31:42.881121
9897 16:31:43.140279 01c00000 ################################################################
9898 16:31:43.140395
9899 16:31:43.391347 01c80000 ################################################################
9900 16:31:43.391464
9901 16:31:43.663090 01d00000 ################################################################
9902 16:31:43.663224
9903 16:31:43.909857 01d80000 ################################################################
9904 16:31:43.909996
9905 16:31:44.178846 01e00000 ################################################################
9906 16:31:44.178961
9907 16:31:44.439616 01e80000 ################################################################
9908 16:31:44.439759
9909 16:31:44.702609 01f00000 ################################################################
9910 16:31:44.702726
9911 16:31:44.955850 01f80000 ################################################################
9912 16:31:44.955985
9913 16:31:45.217022 02000000 ################################################################
9914 16:31:45.217157
9915 16:31:45.476631 02080000 ################################################################
9916 16:31:45.476741
9917 16:31:45.735564 02100000 ################################################################
9918 16:31:45.735675
9919 16:31:45.995052 02180000 ################################################################
9920 16:31:45.995182
9921 16:31:46.247818 02200000 ################################################################
9922 16:31:46.247931
9923 16:31:46.502687 02280000 ################################################################
9924 16:31:46.502816
9925 16:31:46.761127 02300000 ################################################################
9926 16:31:46.761245
9927 16:31:47.023297 02380000 ################################################################
9928 16:31:47.023405
9929 16:31:47.276221 02400000 ################################################################
9930 16:31:47.276357
9931 16:31:47.530028 02480000 ################################################################
9932 16:31:47.530172
9933 16:31:47.789843 02500000 ################################################################
9934 16:31:47.789975
9935 16:31:48.058075 02580000 ################################################################
9936 16:31:48.058247
9937 16:31:48.339651 02600000 ################################################################
9938 16:31:48.339765
9939 16:31:48.592853 02680000 ################################################################
9940 16:31:48.592989
9941 16:31:48.845239 02700000 ################################################################
9942 16:31:48.845391
9943 16:31:49.131131 02780000 ################################################################
9944 16:31:49.131275
9945 16:31:49.417605 02800000 ################################################################
9946 16:31:49.417720
9947 16:31:49.706517 02880000 ################################################################
9948 16:31:49.706633
9949 16:31:49.967767 02900000 ################################################################
9950 16:31:49.967915
9951 16:31:50.246102 02980000 ################################################################
9952 16:31:50.246245
9953 16:31:50.520949 02a00000 ################################################################
9954 16:31:50.521065
9955 16:31:50.786405 02a80000 ################################################################
9956 16:31:50.786522
9957 16:31:51.052241 02b00000 ################################################################
9958 16:31:51.052435
9959 16:31:51.316792 02b80000 ################################################################
9960 16:31:51.316947
9961 16:31:51.593416 02c00000 ################################################################
9962 16:31:51.593532
9963 16:31:51.875249 02c80000 ################################################################
9964 16:31:51.875390
9965 16:31:52.145255 02d00000 ################################################################
9966 16:31:52.145395
9967 16:31:52.404695 02d80000 ################################################################
9968 16:31:52.404864
9969 16:31:52.666556 02e00000 ################################################################
9970 16:31:52.666667
9971 16:31:52.944743 02e80000 ################################################################
9972 16:31:52.944879
9973 16:31:53.205419 02f00000 ################################################################
9974 16:31:53.205599
9975 16:31:53.462753 02f80000 ################################################################
9976 16:31:53.462888
9977 16:31:53.733894 03000000 ################################################################
9978 16:31:53.734010
9979 16:31:54.003307 03080000 ################################################################
9980 16:31:54.003422
9981 16:31:54.283707 03100000 ################################################################
9982 16:31:54.283845
9983 16:31:54.558385 03180000 ################################################################
9984 16:31:54.558524
9985 16:31:54.822616 03200000 ################################################################
9986 16:31:54.822732
9987 16:31:55.076685 03280000 ################################################################
9988 16:31:55.076796
9989 16:31:55.334448 03300000 ################################################################
9990 16:31:55.334564
9991 16:31:55.597685 03380000 ################################################################
9992 16:31:55.597797
9993 16:31:55.896026 03400000 ################################################################
9994 16:31:55.896166
9995 16:31:56.253490 03480000 ################################################################
9996 16:31:56.253602
9997 16:31:56.610555 03500000 ################################################################
9998 16:31:56.610673
9999 16:31:56.966466 03580000 ################################################################
10000 16:31:56.966579
10001 16:31:57.274133 03600000 ################################################################
10002 16:31:57.274318
10003 16:31:57.568211 03680000 ################################################################
10004 16:31:57.568351
10005 16:31:57.842854 03700000 ################################################################
10006 16:31:57.842995
10007 16:31:58.118011 03780000 ################################################################
10008 16:31:58.118177
10009 16:31:58.419335 03800000 ################################################################
10010 16:31:58.419496
10011 16:31:58.718253 03880000 ################################################################
10012 16:31:58.718373
10013 16:31:58.994243 03900000 ################################################################
10014 16:31:58.994363
10015 16:31:59.272997 03980000 ################################################################
10016 16:31:59.273154
10017 16:31:59.523950 03a00000 ################################################################
10018 16:31:59.524068
10019 16:31:59.810361 03a80000 ################################################################
10020 16:31:59.810498
10021 16:32:00.090074 03b00000 ################################################################
10022 16:32:00.090218
10023 16:32:00.370127 03b80000 ################################################################
10024 16:32:00.370264
10025 16:32:00.626626 03c00000 ################################################################
10026 16:32:00.626741
10027 16:32:00.901178 03c80000 ################################################################
10028 16:32:00.901296
10029 16:32:01.169577 03d00000 ################################################################
10030 16:32:01.169694
10031 16:32:01.433957 03d80000 ################################################################
10032 16:32:01.434097
10033 16:32:01.591372 03e00000 ####################################### done.
10034 16:32:01.591502
10035 16:32:01.595054 The bootfile was 65330762 bytes long.
10036 16:32:01.595152
10037 16:32:01.598093 Sending tftp read request... done.
10038 16:32:01.598194
10039 16:32:01.598317 Waiting for the transfer...
10040 16:32:01.598389
10041 16:32:01.601858 00000000 # done.
10042 16:32:01.601940
10043 16:32:01.608096 Command line loaded dynamically from TFTP file: 14396103/tftp-deploy-kg8v5wn8/kernel/cmdline
10044 16:32:01.608201
10045 16:32:01.621724 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10046 16:32:01.621811
10047 16:32:01.624735 Loading FIT.
10048 16:32:01.624832
10049 16:32:01.627861 Image ramdisk-1 has 52152721 bytes.
10050 16:32:01.627961
10051 16:32:01.631451 Image fdt-1 has 47258 bytes.
10052 16:32:01.631528
10053 16:32:01.631589 Image kernel-1 has 13128753 bytes.
10054 16:32:01.634969
10055 16:32:01.641573 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10056 16:32:01.641652
10057 16:32:01.657534 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10058 16:32:01.661221
10059 16:32:01.664317 Choosing best match conf-1 for compat google,spherion-rev3.
10060 16:32:01.669104
10061 16:32:01.673488 Connected to device vid:did:rid of 1ae0:0028:00
10062 16:32:01.680264
10063 16:32:01.683947 tpm_get_response: command 0x17b, return code 0x0
10064 16:32:01.684025
10065 16:32:01.687071 ec_init: CrosEC protocol v3 supported (256, 248)
10066 16:32:01.691285
10067 16:32:01.694879 tpm_cleanup: add release locality here.
10068 16:32:01.694956
10069 16:32:01.695017 Shutting down all USB controllers.
10070 16:32:01.695072
10071 16:32:01.698586 Removing current net device
10072 16:32:01.698664
10073 16:32:01.704901 Exiting depthcharge with code 4 at timestamp: 70651930
10074 16:32:01.704984
10075 16:32:01.708226 LZMA decompressing kernel-1 to 0x821a6718
10076 16:32:01.708315
10077 16:32:01.711981 LZMA decompressing kernel-1 to 0x40000000
10078 16:32:03.327374
10079 16:32:03.327493 jumping to kernel
10080 16:32:03.328006 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10081 16:32:03.328098 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10082 16:32:03.328165 Setting prompt string to ['Linux version [0-9]']
10083 16:32:03.328227 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 16:32:03.328291 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10085 16:32:03.377936
10086 16:32:03.381090 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10087 16:32:03.384766 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10088 16:32:03.384862 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10089 16:32:03.384929 Setting prompt string to []
10090 16:32:03.385004 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10091 16:32:03.385075 Using line separator: #'\n'#
10092 16:32:03.385131 No login prompt set.
10093 16:32:03.385188 Parsing kernel messages
10094 16:32:03.385239 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10095 16:32:03.385333 [login-action] Waiting for messages, (timeout 00:03:44)
10096 16:32:03.385425 Waiting using forced prompt support (timeout 00:01:52)
10097 16:32:03.404147 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10098 16:32:03.407053 [ 0.000000] random: crng init done
10099 16:32:03.413609 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10100 16:32:03.416890 [ 0.000000] efi: UEFI not found.
10101 16:32:03.423882 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10102 16:32:03.433779 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10103 16:32:03.443573 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10104 16:32:03.449884 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10105 16:32:03.456724 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10106 16:32:03.463604 [ 0.000000] printk: bootconsole [mtk8250] enabled
10107 16:32:03.469751 [ 0.000000] NUMA: No NUMA configuration found
10108 16:32:03.476321 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10109 16:32:03.483049 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10110 16:32:03.483142 [ 0.000000] Zone ranges:
10111 16:32:03.489944 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10112 16:32:03.492965 [ 0.000000] DMA32 empty
10113 16:32:03.499611 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10114 16:32:03.502890 [ 0.000000] Movable zone start for each node
10115 16:32:03.506572 [ 0.000000] Early memory node ranges
10116 16:32:03.512961 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10117 16:32:03.519369 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10118 16:32:03.525860 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10119 16:32:03.532768 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10120 16:32:03.539083 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10121 16:32:03.545974 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10122 16:32:03.575612 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10123 16:32:03.582388 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10124 16:32:03.588901 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10125 16:32:03.592376 [ 0.000000] psci: probing for conduit method from DT.
10126 16:32:03.599173 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10127 16:32:03.602262 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10128 16:32:03.608860 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10129 16:32:03.611897 [ 0.000000] psci: SMC Calling Convention v1.2
10130 16:32:03.619065 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10131 16:32:03.622402 [ 0.000000] Detected VIPT I-cache on CPU0
10132 16:32:03.628620 [ 0.000000] CPU features: detected: GIC system register CPU interface
10133 16:32:03.635066 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10134 16:32:03.641751 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10135 16:32:03.648535 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10136 16:32:03.658412 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10137 16:32:03.664573 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10138 16:32:03.668253 [ 0.000000] alternatives: applying boot alternatives
10139 16:32:03.674810 [ 0.000000] Fallback order for Node 0: 0
10140 16:32:03.681730 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10141 16:32:03.684793 [ 0.000000] Policy zone: Normal
10142 16:32:03.697960 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10143 16:32:03.708012 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10144 16:32:03.718589 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10145 16:32:03.728580 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10146 16:32:03.735143 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10147 16:32:03.738624 <6>[ 0.000000] software IO TLB: area num 8.
10148 16:32:03.794545 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10149 16:32:03.874862 <6>[ 0.000000] Memory: 3798712K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 359752K reserved, 32768K cma-reserved)
10150 16:32:03.881043 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10151 16:32:03.887766 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10152 16:32:03.890791 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10153 16:32:03.897618 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10154 16:32:03.904276 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10155 16:32:03.907417 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10156 16:32:03.917122 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10157 16:32:03.924042 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10158 16:32:03.930694 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10159 16:32:03.936898 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10160 16:32:03.940435 <6>[ 0.000000] GICv3: 608 SPIs implemented
10161 16:32:03.943682 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10162 16:32:03.950020 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10163 16:32:03.953444 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10164 16:32:03.960305 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10165 16:32:03.973541 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10166 16:32:03.986859 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10167 16:32:03.992894 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10168 16:32:04.000886 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10169 16:32:04.014145 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10170 16:32:04.020910 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10171 16:32:04.027719 <6>[ 0.009170] Console: colour dummy device 80x25
10172 16:32:04.037731 <6>[ 0.013896] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10173 16:32:04.043730 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10174 16:32:04.047329 <6>[ 0.029273] LSM: Security Framework initializing
10175 16:32:04.053651 <6>[ 0.034216] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10176 16:32:04.063751 <6>[ 0.041824] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10177 16:32:04.070223 <6>[ 0.051061] cblist_init_generic: Setting adjustable number of callback queues.
10178 16:32:04.076708 <6>[ 0.058504] cblist_init_generic: Setting shift to 3 and lim to 1.
10179 16:32:04.086964 <6>[ 0.064842] cblist_init_generic: Setting adjustable number of callback queues.
10180 16:32:04.093524 <6>[ 0.072269] cblist_init_generic: Setting shift to 3 and lim to 1.
10181 16:32:04.096933 <6>[ 0.078669] rcu: Hierarchical SRCU implementation.
10182 16:32:04.103625 <6>[ 0.083715] rcu: Max phase no-delay instances is 1000.
10183 16:32:04.109696 <6>[ 0.090765] EFI services will not be available.
10184 16:32:04.113154 <6>[ 0.095720] smp: Bringing up secondary CPUs ...
10185 16:32:04.121521 <6>[ 0.100797] Detected VIPT I-cache on CPU1
10186 16:32:04.128279 <6>[ 0.100866] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10187 16:32:04.134393 <6>[ 0.100895] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10188 16:32:04.138129 <6>[ 0.101228] Detected VIPT I-cache on CPU2
10189 16:32:04.144296 <6>[ 0.101280] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10190 16:32:04.154642 <6>[ 0.101299] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10191 16:32:04.157926 <6>[ 0.101556] Detected VIPT I-cache on CPU3
10192 16:32:04.164644 <6>[ 0.101604] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10193 16:32:04.170764 <6>[ 0.101619] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10194 16:32:04.177538 <6>[ 0.101921] CPU features: detected: Spectre-v4
10195 16:32:04.180548 <6>[ 0.101927] CPU features: detected: Spectre-BHB
10196 16:32:04.183985 <6>[ 0.101932] Detected PIPT I-cache on CPU4
10197 16:32:04.190936 <6>[ 0.101992] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10198 16:32:04.197345 <6>[ 0.102009] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10199 16:32:04.203648 <6>[ 0.102300] Detected PIPT I-cache on CPU5
10200 16:32:04.210655 <6>[ 0.102362] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10201 16:32:04.217218 <6>[ 0.102378] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10202 16:32:04.220682 <6>[ 0.102661] Detected PIPT I-cache on CPU6
10203 16:32:04.226894 <6>[ 0.102723] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10204 16:32:04.233542 <6>[ 0.102739] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10205 16:32:04.240386 <6>[ 0.103041] Detected PIPT I-cache on CPU7
10206 16:32:04.247024 <6>[ 0.103107] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10207 16:32:04.253662 <6>[ 0.103123] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10208 16:32:04.256687 <6>[ 0.103170] smp: Brought up 1 node, 8 CPUs
10209 16:32:04.263486 <6>[ 0.244578] SMP: Total of 8 processors activated.
10210 16:32:04.266561 <6>[ 0.249529] CPU features: detected: 32-bit EL0 Support
10211 16:32:04.276629 <6>[ 0.254893] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10212 16:32:04.282854 <6>[ 0.263748] CPU features: detected: Common not Private translations
10213 16:32:04.289650 <6>[ 0.270224] CPU features: detected: CRC32 instructions
10214 16:32:04.296528 <6>[ 0.275576] CPU features: detected: RCpc load-acquire (LDAPR)
10215 16:32:04.299501 <6>[ 0.281536] CPU features: detected: LSE atomic instructions
10216 16:32:04.306233 <6>[ 0.287353] CPU features: detected: Privileged Access Never
10217 16:32:04.312687 <6>[ 0.293132] CPU features: detected: RAS Extension Support
10218 16:32:04.319474 <6>[ 0.298741] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10219 16:32:04.322870 <6>[ 0.305963] CPU: All CPU(s) started at EL2
10220 16:32:04.329562 <6>[ 0.310280] alternatives: applying system-wide alternatives
10221 16:32:04.338630 <6>[ 0.320274] devtmpfs: initialized
10222 16:32:04.353552 <6>[ 0.328373] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10223 16:32:04.359493 <6>[ 0.338335] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10224 16:32:04.366108 <6>[ 0.346353] pinctrl core: initialized pinctrl subsystem
10225 16:32:04.369891 <6>[ 0.353024] DMI not present or invalid.
10226 16:32:04.376547 <6>[ 0.357426] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10227 16:32:04.386064 <6>[ 0.364242] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10228 16:32:04.392452 <6>[ 0.371694] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10229 16:32:04.402125 <6>[ 0.379789] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10230 16:32:04.405820 <6>[ 0.387943] audit: initializing netlink subsys (disabled)
10231 16:32:04.415700 <5>[ 0.393638] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10232 16:32:04.422069 <6>[ 0.394341] thermal_sys: Registered thermal governor 'step_wise'
10233 16:32:04.428761 <6>[ 0.401603] thermal_sys: Registered thermal governor 'power_allocator'
10234 16:32:04.432043 <6>[ 0.407855] cpuidle: using governor menu
10235 16:32:04.438792 <6>[ 0.418813] NET: Registered PF_QIPCRTR protocol family
10236 16:32:04.445515 <6>[ 0.424288] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10237 16:32:04.451841 <6>[ 0.431392] ASID allocator initialised with 32768 entries
10238 16:32:04.454836 <6>[ 0.437947] Serial: AMBA PL011 UART driver
10239 16:32:04.465037 <4>[ 0.446760] Trying to register duplicate clock ID: 134
10240 16:32:04.522988 <6>[ 0.508122] KASLR enabled
10241 16:32:04.537266 <6>[ 0.515753] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10242 16:32:04.544112 <6>[ 0.522767] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10243 16:32:04.550559 <6>[ 0.529258] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10244 16:32:04.557441 <6>[ 0.536266] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10245 16:32:04.563959 <6>[ 0.542754] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10246 16:32:04.570760 <6>[ 0.549760] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10247 16:32:04.576969 <6>[ 0.556248] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10248 16:32:04.583636 <6>[ 0.563252] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10249 16:32:04.586718 <6>[ 0.570681] ACPI: Interpreter disabled.
10250 16:32:04.595185 <6>[ 0.577085] iommu: Default domain type: Translated
10251 16:32:04.601989 <6>[ 0.582233] iommu: DMA domain TLB invalidation policy: strict mode
10252 16:32:04.604918 <5>[ 0.588888] SCSI subsystem initialized
10253 16:32:04.611604 <6>[ 0.593135] usbcore: registered new interface driver usbfs
10254 16:32:04.618556 <6>[ 0.598866] usbcore: registered new interface driver hub
10255 16:32:04.621616 <6>[ 0.604419] usbcore: registered new device driver usb
10256 16:32:04.628701 <6>[ 0.610527] pps_core: LinuxPPS API ver. 1 registered
10257 16:32:04.638823 <6>[ 0.615721] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10258 16:32:04.641778 <6>[ 0.625064] PTP clock support registered
10259 16:32:04.645161 <6>[ 0.629304] EDAC MC: Ver: 3.0.0
10260 16:32:04.652727 <6>[ 0.634478] FPGA manager framework
10261 16:32:04.659132 <6>[ 0.638156] Advanced Linux Sound Architecture Driver Initialized.
10262 16:32:04.662960 <6>[ 0.644924] vgaarb: loaded
10263 16:32:04.669544 <6>[ 0.648055] clocksource: Switched to clocksource arch_sys_counter
10264 16:32:04.672552 <5>[ 0.654497] VFS: Disk quotas dquot_6.6.0
10265 16:32:04.679330 <6>[ 0.658682] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10266 16:32:04.682232 <6>[ 0.665874] pnp: PnP ACPI: disabled
10267 16:32:04.691059 <6>[ 0.672546] NET: Registered PF_INET protocol family
10268 16:32:04.697620 <6>[ 0.677927] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10269 16:32:04.709313 <6>[ 0.687944] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10270 16:32:04.719322 <6>[ 0.696729] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10271 16:32:04.725856 <6>[ 0.704695] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10272 16:32:04.732487 <6>[ 0.713099] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10273 16:32:04.743129 <6>[ 0.721752] TCP: Hash tables configured (established 32768 bind 32768)
10274 16:32:04.749690 <6>[ 0.728610] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10275 16:32:04.756444 <6>[ 0.735630] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10276 16:32:04.762971 <6>[ 0.743156] NET: Registered PF_UNIX/PF_LOCAL protocol family
10277 16:32:04.769666 <6>[ 0.749299] RPC: Registered named UNIX socket transport module.
10278 16:32:04.772611 <6>[ 0.755452] RPC: Registered udp transport module.
10279 16:32:04.779288 <6>[ 0.760383] RPC: Registered tcp transport module.
10280 16:32:04.786149 <6>[ 0.765316] RPC: Registered tcp NFSv4.1 backchannel transport module.
10281 16:32:04.789219 <6>[ 0.771984] PCI: CLS 0 bytes, default 64
10282 16:32:04.792965 <6>[ 0.776384] Unpacking initramfs...
10283 16:32:04.802477 <6>[ 0.780075] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10284 16:32:04.809250 <6>[ 0.788700] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10285 16:32:04.815965 <6>[ 0.797494] kvm [1]: IPA Size Limit: 40 bits
10286 16:32:04.819075 <6>[ 0.802021] kvm [1]: GICv3: no GICV resource entry
10287 16:32:04.825818 <6>[ 0.807043] kvm [1]: disabling GICv2 emulation
10288 16:32:04.832218 <6>[ 0.811730] kvm [1]: GIC system register CPU interface enabled
10289 16:32:04.835671 <6>[ 0.817901] kvm [1]: vgic interrupt IRQ18
10290 16:32:04.841854 <6>[ 0.822267] kvm [1]: VHE mode initialized successfully
10291 16:32:04.845064 <5>[ 0.828622] Initialise system trusted keyrings
10292 16:32:04.851825 <6>[ 0.833442] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10293 16:32:04.861775 <6>[ 0.843477] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10294 16:32:04.867899 <5>[ 0.849877] NFS: Registering the id_resolver key type
10295 16:32:04.871336 <5>[ 0.855177] Key type id_resolver registered
10296 16:32:04.877891 <5>[ 0.859592] Key type id_legacy registered
10297 16:32:04.884620 <6>[ 0.863872] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10298 16:32:04.891633 <6>[ 0.870793] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10299 16:32:04.898067 <6>[ 0.878506] 9p: Installing v9fs 9p2000 file system support
10300 16:32:04.933804 <5>[ 0.915976] Key type asymmetric registered
10301 16:32:04.937502 <5>[ 0.920309] Asymmetric key parser 'x509' registered
10302 16:32:04.947499 <6>[ 0.925461] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10303 16:32:04.950928 <6>[ 0.933072] io scheduler mq-deadline registered
10304 16:32:04.953790 <6>[ 0.937833] io scheduler kyber registered
10305 16:32:04.972578 <6>[ 0.954704] EINJ: ACPI disabled.
10306 16:32:05.004919 <4>[ 0.980477] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10307 16:32:05.015162 <4>[ 0.991095] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10308 16:32:05.029949 <6>[ 1.011835] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10309 16:32:05.038019 <6>[ 1.019779] printk: console [ttyS0] disabled
10310 16:32:05.065756 <6>[ 1.044407] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10311 16:32:05.072302 <6>[ 1.053879] printk: console [ttyS0] enabled
10312 16:32:05.076110 <6>[ 1.053879] printk: console [ttyS0] enabled
10313 16:32:05.082496 <6>[ 1.062777] printk: bootconsole [mtk8250] disabled
10314 16:32:05.085710 <6>[ 1.062777] printk: bootconsole [mtk8250] disabled
10315 16:32:05.092638 <6>[ 1.073816] SuperH (H)SCI(F) driver initialized
10316 16:32:05.095635 <6>[ 1.079096] msm_serial: driver initialized
10317 16:32:05.109333 <6>[ 1.088009] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10318 16:32:05.119098 <6>[ 1.096560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10319 16:32:05.125918 <6>[ 1.105102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10320 16:32:05.136055 <6>[ 1.113732] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10321 16:32:05.146036 <6>[ 1.122440] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10322 16:32:05.152753 <6>[ 1.131161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10323 16:32:05.162659 <6>[ 1.139701] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10324 16:32:05.168863 <6>[ 1.148493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10325 16:32:05.178858 <6>[ 1.157035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10326 16:32:05.190244 <6>[ 1.172455] loop: module loaded
10327 16:32:05.197114 <6>[ 1.178534] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10328 16:32:05.219381 <4>[ 1.201635] mtk-pmic-keys: Failed to locate of_node [id: -1]
10329 16:32:05.226953 <6>[ 1.208439] megasas: 07.719.03.00-rc1
10330 16:32:05.236197 <6>[ 1.217969] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10331 16:32:05.246049 <6>[ 1.227431] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10332 16:32:05.261341 <6>[ 1.243351] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10333 16:32:05.316326 <6>[ 1.291546] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10334 16:32:07.017211 <6>[ 2.999316] Freeing initrd memory: 50928K
10335 16:32:07.028984 <6>[ 3.011019] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10336 16:32:07.039667 <6>[ 3.021883] tun: Universal TUN/TAP device driver, 1.6
10337 16:32:07.043224 <6>[ 3.027939] thunder_xcv, ver 1.0
10338 16:32:07.046646 <6>[ 3.031444] thunder_bgx, ver 1.0
10339 16:32:07.049749 <6>[ 3.034940] nicpf, ver 1.0
10340 16:32:07.060560 <6>[ 3.038947] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10341 16:32:07.063634 <6>[ 3.046422] hns3: Copyright (c) 2017 Huawei Corporation.
10342 16:32:07.070097 <6>[ 3.052007] hclge is initializing
10343 16:32:07.073335 <6>[ 3.055589] e1000: Intel(R) PRO/1000 Network Driver
10344 16:32:07.080030 <6>[ 3.060719] e1000: Copyright (c) 1999-2006 Intel Corporation.
10345 16:32:07.083157 <6>[ 3.066734] e1000e: Intel(R) PRO/1000 Network Driver
10346 16:32:07.090034 <6>[ 3.071950] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10347 16:32:07.096655 <6>[ 3.078134] igb: Intel(R) Gigabit Ethernet Network Driver
10348 16:32:07.103591 <6>[ 3.083783] igb: Copyright (c) 2007-2014 Intel Corporation.
10349 16:32:07.110051 <6>[ 3.089618] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10350 16:32:07.116288 <6>[ 3.096136] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10351 16:32:07.119827 <6>[ 3.102601] sky2: driver version 1.30
10352 16:32:07.126785 <6>[ 3.107520] usbcore: registered new device driver r8152-cfgselector
10353 16:32:07.133190 <6>[ 3.114057] usbcore: registered new interface driver r8152
10354 16:32:07.139584 <6>[ 3.119873] VFIO - User Level meta-driver version: 0.3
10355 16:32:07.146151 <6>[ 3.128097] usbcore: registered new interface driver usb-storage
10356 16:32:07.152953 <6>[ 3.134540] usbcore: registered new device driver onboard-usb-hub
10357 16:32:07.161298 <6>[ 3.143641] mt6397-rtc mt6359-rtc: registered as rtc0
10358 16:32:07.171266 <6>[ 3.149109] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:32:07 UTC (1718641927)
10359 16:32:07.174897 <6>[ 3.158664] i2c_dev: i2c /dev entries driver
10360 16:32:07.188350 <4>[ 3.170585] cpu cpu0: supply cpu not found, using dummy regulator
10361 16:32:07.195035 <4>[ 3.177012] cpu cpu1: supply cpu not found, using dummy regulator
10362 16:32:07.201660 <4>[ 3.183412] cpu cpu2: supply cpu not found, using dummy regulator
10363 16:32:07.208513 <4>[ 3.189819] cpu cpu3: supply cpu not found, using dummy regulator
10364 16:32:07.215132 <4>[ 3.196215] cpu cpu4: supply cpu not found, using dummy regulator
10365 16:32:07.221596 <4>[ 3.202626] cpu cpu5: supply cpu not found, using dummy regulator
10366 16:32:07.227927 <4>[ 3.209024] cpu cpu6: supply cpu not found, using dummy regulator
10367 16:32:07.234927 <4>[ 3.215420] cpu cpu7: supply cpu not found, using dummy regulator
10368 16:32:07.254787 <6>[ 3.237052] cpu cpu0: EM: created perf domain
10369 16:32:07.258382 <6>[ 3.241959] cpu cpu4: EM: created perf domain
10370 16:32:07.265660 <6>[ 3.247470] sdhci: Secure Digital Host Controller Interface driver
10371 16:32:07.272098 <6>[ 3.253901] sdhci: Copyright(c) Pierre Ossman
10372 16:32:07.278868 <6>[ 3.258810] Synopsys Designware Multimedia Card Interface Driver
10373 16:32:07.285357 <6>[ 3.265408] sdhci-pltfm: SDHCI platform and OF driver helper
10374 16:32:07.288889 <6>[ 3.265571] mmc0: CQHCI version 5.10
10375 16:32:07.294879 <6>[ 3.275367] ledtrig-cpu: registered to indicate activity on CPUs
10376 16:32:07.301685 <6>[ 3.282261] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10377 16:32:07.308415 <6>[ 3.289287] usbcore: registered new interface driver usbhid
10378 16:32:07.311596 <6>[ 3.295108] usbhid: USB HID core driver
10379 16:32:07.318136 <6>[ 3.299296] spi_master spi0: will run message pump with realtime priority
10380 16:32:07.365444 <6>[ 3.341124] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10381 16:32:07.385008 <6>[ 3.356930] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10382 16:32:07.388464 <6>[ 3.371060] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10383 16:32:07.395153 <6>[ 3.371753] cros-ec-spi spi0.0: Chrome EC device registered
10384 16:32:07.401852 <6>[ 3.383162] mmc0: Command Queue Engine enabled
10385 16:32:07.408517 <6>[ 3.387897] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10386 16:32:07.411775 <6>[ 3.395303] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10387 16:32:07.421595 <6>[ 3.395467] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10388 16:32:07.428398 <6>[ 3.404166] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10389 16:32:07.434653 <6>[ 3.410357] NET: Registered PF_PACKET protocol family
10390 16:32:07.438009 <6>[ 3.416758] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10391 16:32:07.444620 <6>[ 3.420713] 9pnet: Installing 9P2000 support
10392 16:32:07.448187 <6>[ 3.426485] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10393 16:32:07.454347 <5>[ 3.430398] Key type dns_resolver registered
10394 16:32:07.461544 <6>[ 3.436286] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10395 16:32:07.464685 <6>[ 3.440634] registered taskstats version 1
10396 16:32:07.467566 <5>[ 3.450994] Loading compiled-in X.509 certificates
10397 16:32:07.499091 <4>[ 3.474372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10398 16:32:07.508906 <4>[ 3.485075] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10399 16:32:07.522278 <6>[ 3.504689] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10400 16:32:07.529174 <6>[ 3.511513] xhci-mtk 11200000.usb: xHCI Host Controller
10401 16:32:07.535797 <6>[ 3.517039] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10402 16:32:07.546285 <6>[ 3.524904] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10403 16:32:07.552751 <6>[ 3.534350] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10404 16:32:07.559017 <6>[ 3.540549] xhci-mtk 11200000.usb: xHCI Host Controller
10405 16:32:07.565640 <6>[ 3.546039] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10406 16:32:07.572291 <6>[ 3.553695] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10407 16:32:07.579478 <6>[ 3.561544] hub 1-0:1.0: USB hub found
10408 16:32:07.582682 <6>[ 3.565584] hub 1-0:1.0: 1 port detected
10409 16:32:07.592399 <6>[ 3.569882] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10410 16:32:07.595914 <6>[ 3.578666] hub 2-0:1.0: USB hub found
10411 16:32:07.598944 <6>[ 3.582724] hub 2-0:1.0: 1 port detected
10412 16:32:07.608282 <6>[ 3.590574] mtk-msdc 11f70000.mmc: Got CD GPIO
10413 16:32:07.626334 <6>[ 3.604823] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10414 16:32:07.632611 <6>[ 3.613204] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10415 16:32:07.642803 <6>[ 3.621547] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10416 16:32:07.652432 <6>[ 3.629886] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10417 16:32:07.658917 <6>[ 3.638225] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10418 16:32:07.668860 <6>[ 3.646562] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10419 16:32:07.675609 <6>[ 3.654900] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10420 16:32:07.685939 <6>[ 3.663237] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10421 16:32:07.692009 <6>[ 3.671578] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10422 16:32:07.702125 <6>[ 3.679916] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10423 16:32:07.708688 <6>[ 3.688254] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10424 16:32:07.718677 <6>[ 3.696592] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10425 16:32:07.725009 <6>[ 3.704930] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10426 16:32:07.734792 <6>[ 3.713267] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10427 16:32:07.741528 <6>[ 3.721605] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10428 16:32:07.748277 <6>[ 3.730269] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10429 16:32:07.755405 <6>[ 3.737419] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10430 16:32:07.762062 <6>[ 3.744177] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10431 16:32:07.772021 <6>[ 3.750920] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10432 16:32:07.778604 <6>[ 3.757895] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10433 16:32:07.785237 <6>[ 3.764735] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10434 16:32:07.795695 <6>[ 3.773870] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10435 16:32:07.805051 <6>[ 3.782988] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10436 16:32:07.814815 <6>[ 3.792283] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10437 16:32:07.825150 <6>[ 3.801750] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10438 16:32:07.831604 <6>[ 3.811217] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10439 16:32:07.841398 <6>[ 3.820336] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10440 16:32:07.851321 <6>[ 3.829801] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10441 16:32:07.861796 <6>[ 3.838919] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10442 16:32:07.871481 <6>[ 3.848214] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10443 16:32:07.880968 <6>[ 3.858374] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10444 16:32:07.891188 <6>[ 3.870312] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10445 16:32:07.989459 <6>[ 3.968542] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10446 16:32:08.017277 <6>[ 3.999585] hub 2-1:1.0: USB hub found
10447 16:32:08.020919 <6>[ 4.004032] hub 2-1:1.0: 3 ports detected
10448 16:32:08.030034 <6>[ 4.012371] hub 2-1:1.0: USB hub found
10449 16:32:08.033518 <6>[ 4.016886] hub 2-1:1.0: 3 ports detected
10450 16:32:08.141185 <6>[ 4.120184] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10451 16:32:08.296242 <6>[ 4.278236] hub 1-1:1.0: USB hub found
10452 16:32:08.299174 <6>[ 4.282740] hub 1-1:1.0: 4 ports detected
10453 16:32:08.312171 <6>[ 4.294548] hub 1-1:1.0: USB hub found
10454 16:32:08.315945 <6>[ 4.298892] hub 1-1:1.0: 4 ports detected
10455 16:32:08.373309 <6>[ 4.352441] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10456 16:32:08.481791 <6>[ 4.460738] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10457 16:32:08.529180 <6>[ 4.508272] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10458 16:32:08.566836 <6>[ 4.549272] r8152 2-1.3:1.0 eth0: v1.12.13
10459 16:32:08.641257 <6>[ 4.620370] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10460 16:32:08.774064 <6>[ 4.756299] hub 1-1.4:1.0: USB hub found
10461 16:32:08.777229 <6>[ 4.760970] hub 1-1.4:1.0: 2 ports detected
10462 16:32:08.789828 <6>[ 4.772006] hub 1-1.4:1.0: USB hub found
10463 16:32:08.793181 <6>[ 4.776649] hub 1-1.4:1.0: 2 ports detected
10464 16:32:09.088953 <6>[ 5.068366] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10465 16:32:09.285563 <6>[ 5.264389] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10466 16:32:10.222297 <6>[ 6.204920] r8152 2-1.3:1.0 eth0: carrier on
10467 16:32:12.833848 <5>[ 6.232167] Sending DHCP requests .., OK
10468 16:32:12.839985 <6>[ 8.820569] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10469 16:32:12.843473 <6>[ 8.828862] IP-Config: Complete:
10470 16:32:12.856889 <6>[ 8.832354] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10471 16:32:12.863672 <6>[ 8.843075] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10472 16:32:12.869745 <6>[ 8.851701] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10473 16:32:12.876580 <6>[ 8.851711] nameserver0=192.168.201.1
10474 16:32:12.880293 <6>[ 8.863881] clk: Disabling unused clocks
10475 16:32:12.883345 <6>[ 8.869455] ALSA device list:
10476 16:32:12.890145 <6>[ 8.872725] No soundcards found.
10477 16:32:12.897441 <6>[ 8.880351] Freeing unused kernel memory: 8512K
10478 16:32:12.900967 <6>[ 8.885333] Run /init as init process
10479 16:32:12.931606 <6>[ 8.914591] NET: Registered PF_INET6 protocol family
10480 16:32:12.938920 <6>[ 8.921440] Segment Routing with IPv6
10481 16:32:12.941795 <6>[ 8.925400] In-situ OAM (IOAM) with IPv6
10482 16:32:12.986378 <30>[ 8.942506] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10483 16:32:12.992991 <30>[ 8.975642] systemd[1]: Detected architecture arm64.
10484 16:32:12.993090
10485 16:32:12.999512 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10486 16:32:12.999585
10487 16:32:13.013494 <30>[ 8.996430] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10488 16:32:13.159034 <30>[ 9.138271] systemd[1]: Queued start job for default target graphical.target.
10489 16:32:13.186865 <30>[ 9.166269] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10490 16:32:13.193335 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10491 16:32:13.213794 <30>[ 9.193088] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10492 16:32:13.223032 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10493 16:32:13.242516 <30>[ 9.222053] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10494 16:32:13.252366 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10495 16:32:13.270190 <30>[ 9.249866] systemd[1]: Created slice user.slice - User and Session Slice.
10496 16:32:13.276847 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10497 16:32:13.301068 <30>[ 9.277115] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10498 16:32:13.310712 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10499 16:32:13.328472 <30>[ 9.304600] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10500 16:32:13.334856 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10501 16:32:13.362919 <30>[ 9.332906] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10502 16:32:13.373308 <30>[ 9.352833] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10503 16:32:13.379824 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10504 16:32:13.397500 <30>[ 9.376741] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10505 16:32:13.407255 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10506 16:32:13.425113 <30>[ 9.404505] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10507 16:32:13.434867 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10508 16:32:13.450215 <30>[ 9.432862] systemd[1]: Reached target paths.target - Path Units.
10509 16:32:13.460047 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10510 16:32:13.477209 <30>[ 9.456814] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10511 16:32:13.484076 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10512 16:32:13.497296 <30>[ 9.480389] systemd[1]: Reached target slices.target - Slice Units.
10513 16:32:13.507571 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10514 16:32:13.521996 <30>[ 9.504836] systemd[1]: Reached target swap.target - Swaps.
10515 16:32:13.528658 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10516 16:32:13.549531 <30>[ 9.528847] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10517 16:32:13.558985 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10518 16:32:13.578025 <30>[ 9.557332] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10519 16:32:13.587413 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10520 16:32:13.606393 <30>[ 9.585738] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10521 16:32:13.615773 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10522 16:32:13.633451 <30>[ 9.613048] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10523 16:32:13.643746 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10524 16:32:13.661287 <30>[ 9.640968] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10525 16:32:13.668073 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10526 16:32:13.685473 <30>[ 9.665064] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10527 16:32:13.695306 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10528 16:32:13.713759 <30>[ 9.693675] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10529 16:32:13.723998 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10530 16:32:13.741181 <30>[ 9.720895] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10531 16:32:13.750983 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10532 16:32:13.805064 <30>[ 9.784704] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10533 16:32:13.811759 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10534 16:32:13.836049 <30>[ 9.815708] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10535 16:32:13.842749 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10536 16:32:13.880721 <30>[ 9.860537] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10537 16:32:13.887435 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10538 16:32:13.911584 <30>[ 9.884596] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10539 16:32:13.924362 <30>[ 9.903876] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10540 16:32:13.934032 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10541 16:32:13.958109 <30>[ 9.937478] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10542 16:32:13.964400 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10543 16:32:13.991412 <30>[ 9.970978] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10544 16:32:14.001326 Startin<6>[ 9.980383] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10545 16:32:14.008113 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10546 16:32:14.027904 <30>[ 10.007247] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10547 16:32:14.033998 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10548 16:32:14.056459 <30>[ 10.035984] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10549 16:32:14.066087 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10550 16:32:14.093748 <30>[ 10.073469] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10551 16:32:14.100662 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10552 16:32:14.173561 <30>[ 10.153157] systemd[1]: Starting systemd-journald.service - Journal Service...
10553 16:32:14.180251 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10554 16:32:14.203773 <30>[ 10.183308] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10555 16:32:14.210321 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10556 16:32:14.253090 <30>[ 10.229261] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10557 16:32:14.259670 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10558 16:32:14.281651 <30>[ 10.261423] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10559 16:32:14.291921 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10560 16:32:14.312742 <30>[ 10.292163] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10561 16:32:14.319413 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10562 16:32:14.346900 <30>[ 10.326780] systemd[1]: Started systemd-journald.service - Journal Service.
10563 16:32:14.353920 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10564 16:32:14.377679 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10565 16:32:14.397773 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10566 16:32:14.417659 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10567 16:32:14.438289 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10568 16:32:14.457970 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10569 16:32:14.483551 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10570 16:32:14.504255 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10571 16:32:14.524955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10572 16:32:14.545159 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10573 16:32:14.562547 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10574 16:32:14.582307 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10575 16:32:14.603141 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10576 16:32:14.609737 See 'systemctl status systemd-remount-fs.service' for details.
10577 16:32:14.619527 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10578 16:32:14.639813 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10579 16:32:14.693872 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10580 16:32:14.715668 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10581 16:32:14.725287 <46>[ 10.705183] systemd-journald[185]: Received client request to flush runtime journal.
10582 16:32:14.737715 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10583 16:32:14.759911 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10584 16:32:14.781095 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10585 16:32:14.807863 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10586 16:32:14.830433 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10587 16:32:14.850999 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10588 16:32:14.870387 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10589 16:32:14.890010 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10590 16:32:14.945760 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10591 16:32:14.982457 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10592 16:32:15.001231 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10593 16:32:15.020707 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10594 16:32:15.065340 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10595 16:32:15.089910 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10596 16:32:15.111753 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10597 16:32:15.136673 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10598 16:32:15.160347 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10599 16:32:15.178063 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10600 16:32:15.227554 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10601 16:32:15.248287 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10602 16:32:15.273352 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10603 16:32:15.377944 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10604 16:32:15.397278 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10605 16:32:15.413566 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10606 16:32:15.434290 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10607 16:32:15.454368 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10608 16:32:15.471150 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10609 16:32:15.490523 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10610 16:32:15.517860 <3>[ 11.497355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 16:32:15.523957 <3>[ 11.505472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10612 16:32:15.534471 <3>[ 11.514050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10613 16:32:15.545107 <3>[ 11.524725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10614 16:32:15.551739 <6>[ 11.524808] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10615 16:32:15.561441 <3>[ 11.532934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10616 16:32:15.568162 <6>[ 11.546966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10617 16:32:15.578163 <3>[ 11.548935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10618 16:32:15.584431 <3>[ 11.548946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 16:32:15.591110 <6>[ 11.556945] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10620 16:32:15.601612 <6>[ 11.557499] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10621 16:32:15.607739 <3>[ 11.565096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 16:32:15.614448 <6>[ 11.565428] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10623 16:32:15.624097 <6>[ 11.565484] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10624 16:32:15.634079 <6>[ 11.565505] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10625 16:32:15.641034 <4>[ 11.573718] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10626 16:32:15.650620 <3>[ 11.589289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 16:32:15.657183 <6>[ 11.597093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10628 16:32:15.664004 <6>[ 11.606085] remoteproc remoteproc0: scp is available
10629 16:32:15.670812 <6>[ 11.612697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10630 16:32:15.677034 <6>[ 11.621510] remoteproc remoteproc0: powering up scp
10631 16:32:15.684108 <3>[ 11.622057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10632 16:32:15.693854 <3>[ 11.622091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 16:32:15.700517 <3>[ 11.622104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 16:32:15.710191 <3>[ 11.622262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10635 16:32:15.716967 <3>[ 11.622272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 16:32:15.726678 <3>[ 11.622279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 16:32:15.733653 <3>[ 11.622292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 16:32:15.743557 <3>[ 11.622298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 16:32:15.750166 <3>[ 11.623732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 16:32:15.756441 <6>[ 11.632524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10641 16:32:15.766361 <4>[ 11.634714] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10642 16:32:15.770045 <6>[ 11.636339] mc: Linux media interface: v0.10
10643 16:32:15.776262 <4>[ 11.636930] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10644 16:32:15.786410 <6>[ 11.638527] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10645 16:32:15.792717 <6>[ 11.638544] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10646 16:32:15.799840 <6>[ 11.646616] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10647 16:32:15.805856 <6>[ 11.648487] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10648 16:32:15.816104 <4>[ 11.674589] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10649 16:32:15.819418 <4>[ 11.674589] Fallback method does not support PEC.
10650 16:32:15.829216 <6>[ 11.681148] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10651 16:32:15.835919 <6>[ 11.686388] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10652 16:32:15.842403 <6>[ 11.686394] pci_bus 0000:00: root bus resource [bus 00-ff]
10653 16:32:15.849213 <6>[ 11.686399] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10654 16:32:15.859303 <6>[ 11.686401] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10655 16:32:15.863059 <6>[ 11.686436] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10656 16:32:15.872891 <6>[ 11.686451] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10657 16:32:15.876438 <6>[ 11.686523] pci 0000:00:00.0: supports D1 D2
10658 16:32:15.883177 <6>[ 11.686525] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10659 16:32:15.892573 <6>[ 11.687502] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10660 16:32:15.899396 <6>[ 11.687591] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10661 16:32:15.906015 <6>[ 11.687619] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10662 16:32:15.912390 <6>[ 11.687637] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10663 16:32:15.919472 <6>[ 11.687651] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10664 16:32:15.926013 <6>[ 11.687756] pci 0000:01:00.0: supports D1 D2
10665 16:32:15.932250 <6>[ 11.687757] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10666 16:32:15.938922 <6>[ 11.689864] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10667 16:32:15.949209 <6>[ 11.697586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10668 16:32:15.952601 <6>[ 11.698958] videodev: Linux video capture interface: v2.00
10669 16:32:15.962817 <6>[ 11.705985] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10670 16:32:15.969208 <5>[ 11.811423] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10671 16:32:15.976487 <6>[ 11.816581] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10672 16:32:15.983077 <6>[ 11.816610] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10673 16:32:15.993797 <6>[ 11.816649] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10674 16:32:16.000541 <6>[ 11.816653] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10675 16:32:16.006611 <6>[ 11.816661] remoteproc remoteproc0: remote processor scp is now up
10676 16:32:16.016755 <6>[ 11.816662] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10677 16:32:16.023557 <6>[ 11.816675] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10678 16:32:16.027604 <6>[ 11.816689] pci 0000:00:00.0: PCI bridge to [bus 01]
10679 16:32:16.037401 <6>[ 11.816695] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10680 16:32:16.044102 <6>[ 11.816857] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10681 16:32:16.050854 <6>[ 11.817321] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10682 16:32:16.053883 <6>[ 11.817749] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10683 16:32:16.064109 <6>[ 11.823577] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10684 16:32:16.074396 <6>[ 11.830763] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10685 16:32:16.084498 <3>[ 11.850042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 16:32:16.094395 <6>[ 11.853614] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10687 16:32:16.101101 <5>[ 11.864305] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10688 16:32:16.104906 <6>[ 11.918567] Bluetooth: Core ver 2.22
10689 16:32:16.111732 <5>[ 11.921035] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10690 16:32:16.117642 <6>[ 11.927085] NET: Registered PF_BLUETOOTH protocol family
10691 16:32:16.127840 <4>[ 11.936143] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10692 16:32:16.134153 <6>[ 11.936203] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10693 16:32:16.141232 <6>[ 11.941801] Bluetooth: HCI device and connection manager initialized
10694 16:32:16.147579 <6>[ 11.941818] Bluetooth: HCI socket layer initialized
10695 16:32:16.151101 <6>[ 11.949908] cfg80211: failed to load regulatory.db
10696 16:32:16.157700 <6>[ 11.957879] Bluetooth: L2CAP socket layer initialized
10697 16:32:16.164457 <6>[ 11.960410] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10698 16:32:16.171333 <6>[ 11.961649] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10699 16:32:16.184260 <6>[ 11.963056] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10700 16:32:16.191094 <6>[ 11.965166] usbcore: registered new interface driver uvcvideo
10701 16:32:16.194231 <6>[ 11.972928] Bluetooth: SCO socket layer initialized
10702 16:32:16.204210 <3>[ 12.004439] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10703 16:32:16.210928 <6>[ 12.004591] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10704 16:32:16.217296 <3>[ 12.007891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 16:32:16.227708 <3>[ 12.012465] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10706 16:32:16.237329 <3>[ 12.031731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 16:32:16.244033 <6>[ 12.052864] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10708 16:32:16.253819 <3>[ 12.055375] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10709 16:32:16.260312 <6>[ 12.063362] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10710 16:32:16.263680 <6>[ 12.063753] usbcore: registered new interface driver btusb
10711 16:32:16.274196 <4>[ 12.064629] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10712 16:32:16.281188 <3>[ 12.064664] Bluetooth: hci0: Failed to load firmware file (-2)
10713 16:32:16.287425 <3>[ 12.064670] Bluetooth: hci0: Failed to set up firmware (-2)
10714 16:32:16.297260 <4>[ 12.064678] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10715 16:32:16.307436 <3>[ 12.092125] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 16:32:16.310662 <6>[ 12.120219] mt7921e 0000:01:00.0: ASIC revision: 79610010
10717 16:32:16.320405 <3>[ 12.142196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 16:32:16.330220 <6>[ 12.240027] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10719 16:32:16.330300 <6>[ 12.240027]
10720 16:32:16.340172 <3>[ 12.259313] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10721 16:32:16.346720 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10722 16:32:16.370497 [[0;32m OK [0m] Reached targ<3>[ 12.348103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 16:32:16.373800 et [0;1;39mbasic.target[0m - Basic System.
10724 16:32:16.438864 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10725 16:32:16.467999 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10726 16:32:16.488575 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10727 16:32:16.512812 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10728 16:32:16.542769 <6>[ 12.522512] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10729 16:32:16.575903 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10730 16:32:16.600474 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10731 16:32:16.617557 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10732 16:32:16.639612 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10733 16:32:16.659433 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10734 16:32:16.722570 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10735 16:32:16.748657 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10736 16:32:16.772273 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10737 16:32:16.794790 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10738 16:32:16.859753 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10739 16:32:16.896738 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10740 16:32:16.916972 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10741 16:32:16.937901 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10742 16:32:16.954825 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10743 16:32:17.005534 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10744 16:32:17.032529 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10745 16:32:17.054653 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10746 16:32:17.097460 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10747 16:32:17.150574
10748 16:32:17.153700 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10749 16:32:17.153772
10750 16:32:17.156665 debian-bookworm-arm64 login: root (automatic login)
10751 16:32:17.156733
10752 16:32:17.168604 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
10753 16:32:17.168679
10754 16:32:17.175202 The programs included with the Debian GNU/Linux system are free software;
10755 16:32:17.182024 the exact distribution terms for each program are described in the
10756 16:32:17.185036 individual files in /usr/share/doc/*/copyright.
10757 16:32:17.185113
10758 16:32:17.191959 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10759 16:32:17.195059 permitted by applicable law.
10760 16:32:17.195413 Matched prompt #10: / #
10762 16:32:17.195597 Setting prompt string to ['/ #']
10763 16:32:17.195685 end: 2.2.5.1 login-action (duration 00:00:14) [common]
10765 16:32:17.195859 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
10766 16:32:17.195943 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10767 16:32:17.196008 Setting prompt string to ['/ #']
10768 16:32:17.196061 Forcing a shell prompt, looking for ['/ #']
10770 16:32:17.246244 / #
10771 16:32:17.246423 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10772 16:32:17.246492 Waiting using forced prompt support (timeout 00:02:30)
10773 16:32:17.251037
10774 16:32:17.251297 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10775 16:32:17.251390 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
10776 16:32:17.251472 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10777 16:32:17.251553 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
10778 16:32:17.251630 end: 2 depthcharge-action (duration 00:01:30) [common]
10779 16:32:17.251709 start: 3 lava-test-retry (timeout 00:05:00) [common]
10780 16:32:17.251791 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10781 16:32:17.251855 Using namespace: common
10783 16:32:17.352114 / # #
10784 16:32:17.352293 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10785 16:32:17.357140 #
10786 16:32:17.357419 Using /lava-14396103
10788 16:32:17.457728 / # export SHELL=/bin/sh
10789 16:32:17.457924 <6>[ 13.395066] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10790 16:32:17.462297 export SHELL=/bin/sh
10792 16:32:17.562758 / # . /lava-14396103/environment
10793 16:32:17.567600 . /lava-14396103/environment
10795 16:32:17.668061 / # /lava-14396103/bin/lava-test-runner /lava-14396103/0
10796 16:32:17.668232 Test shell timeout: 10s (minimum of the action and connection timeout)
10797 16:32:17.673214 /lava-14396103/bin/lava-test-runner /lava-14396103/0
10798 16:32:17.692946 + export TESTRUN_ID=0_cros-ec
10799 16:32:17.700142 +<8>[ 13.682009] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14396103_1.5.2.3.1>
10800 16:32:17.700397 Received signal: <STARTRUN> 0_cros-ec 14396103_1.5.2.3.1
10801 16:32:17.700468 Starting test lava.0_cros-ec (14396103_1.5.2.3.1)
10802 16:32:17.700548 Skipping test definition patterns.
10803 16:32:17.703271 cd /lava-14396103/0/tests/0_cros-ec
10804 16:32:17.706391 + cat uuid
10805 16:32:17.706477 + UUID=14396103_1.5.2.3.1
10806 16:32:17.706557 + set +x
10807 16:32:17.713119 + python3 -m cros.runners.lava_runner -v
10808 16:32:18.099786 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
10809 16:32:18.106606 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10810 16:32:18.106696
10811 16:32:18.113119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10812 16:32:18.113422 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10814 16:32:18.122498 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
10815 16:32:18.133050 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10816 16:32:18.133129
10817 16:32:18.139636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
10818 16:32:18.139885 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
10820 16:32:18.149502 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
10821 16:32:18.155550 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10822 16:32:18.155637
10823 16:32:18.162083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10824 16:32:18.162369 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10826 16:32:18.169051 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
10827 16:32:18.172208 Checks the standard ABI for the main Embedded Controller. ... ok
10828 16:32:18.175819
10829 16:32:18.178977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10830 16:32:18.179228 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10832 16:32:18.185540 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
10833 16:32:18.192469 Checks the main Embedded controller character device. ... ok
10834 16:32:18.192576
10835 16:32:18.198513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10836 16:32:18.198791 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10838 16:32:18.205156 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
10839 16:32:18.211894 Checks basic comunication with the main Embedded controller. ... ok
10840 16:32:18.211970
10841 16:32:18.218546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10842 16:32:18.218785 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10844 16:32:18.224836 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
10845 16:32:18.231613 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10846 16:32:18.231718
10847 16:32:18.238159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10848 16:32:18.238458 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10850 16:32:18.244752 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
10851 16:32:18.251887 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10852 16:32:18.251994
10853 16:32:18.257941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10854 16:32:18.258207 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10856 16:32:18.264635 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
10857 16:32:18.271082 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10858 16:32:18.271157
10859 16:32:18.277981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10860 16:32:18.278256 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10862 16:32:18.284450 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
10863 16:32:18.291309 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10864 16:32:18.294168
10865 16:32:18.297854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10866 16:32:18.298122 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10868 16:32:18.304725 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
10869 16:32:18.314288 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10870 16:32:18.314386
10871 16:32:18.321181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10872 16:32:18.321460 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10874 16:32:18.327541 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
10875 16:32:18.333975 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10876 16:32:18.334089
10877 16:32:18.340862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10878 16:32:18.341151 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10880 16:32:18.347188 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
10881 16:32:18.353626 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10882 16:32:18.353718
10883 16:32:18.360708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10884 16:32:18.360960 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10886 16:32:18.370083 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
10887 16:32:18.377175 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10888 16:32:18.377271
10889 16:32:18.383470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10890 16:32:18.383769 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10892 16:32:18.393218 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
10893 16:32:18.396720 Check the cros battery ABI. ... skipped 'No BAT found'
10894 16:32:18.396821
10895 16:32:18.403540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10896 16:32:18.403813 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10898 16:32:18.413286 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
10899 16:32:18.420136 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10900 16:32:18.420240
10901 16:32:18.426839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10902 16:32:18.427097 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10904 16:32:18.432735 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
10905 16:32:18.439648 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10906 16:32:18.442854
10907 16:32:18.445945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10908 16:32:18.446224 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10910 16:32:18.456019 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
10911 16:32:18.462804 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10912 16:32:18.462904
10913 16:32:18.470023 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8
10914 16:32:18.470128 Bad test result: ski<8
10915 16:32:18.475769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8>[ 14.457552] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14396103_1.5.2.3.1>
10916 16:32:18.475847 p>
10917 16:32:18.475915
10918 16:32:18.476145 Received signal: <ENDRUN> 0_cros-ec 14396103_1.5.2.3.1
10919 16:32:18.476219 Ending use of test pattern.
10920 16:32:18.476276 Ending test lava.0_cros-ec (14396103_1.5.2.3.1), duration 0.78
10922 16:32:18.482577 ----------------------------------------------------------------------
10923 16:32:18.485624 Ran 18 tests in 0.329s
10924 16:32:18.485696
10925 16:32:18.485756 OK (skipped=15)
10926 16:32:18.485814 + set +x
10927 16:32:18.488820 <LAVA_TEST_RUNNER EXIT>
10928 16:32:18.489057 ok: lava_test_shell seems to have completed
10929 16:32:18.489218 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10930 16:32:18.489324 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10931 16:32:18.489406 end: 3 lava-test-retry (duration 00:00:01) [common]
10932 16:32:18.489492 start: 4 finalize (timeout 00:07:41) [common]
10933 16:32:18.489594 start: 4.1 power-off (timeout 00:00:30) [common]
10934 16:32:18.489774 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10935 16:32:18.687043 >> Command sent successfully.
10936 16:32:18.690485 Returned 0 in 0 seconds
10937 16:32:18.790841 end: 4.1 power-off (duration 00:00:00) [common]
10939 16:32:18.791142 start: 4.2 read-feedback (timeout 00:07:41) [common]
10940 16:32:18.791393 Listened to connection for namespace 'common' for up to 1s
10941 16:32:19.792312 Finalising connection for namespace 'common'
10942 16:32:19.792464 Disconnecting from shell: Finalise
10943 16:32:19.792541 / #
10944 16:32:19.892777 end: 4.2 read-feedback (duration 00:00:01) [common]
10945 16:32:19.892940 end: 4 finalize (duration 00:00:01) [common]
10946 16:32:19.893057 Cleaning after the job
10947 16:32:19.893157 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/ramdisk
10948 16:32:19.899076 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/kernel
10949 16:32:19.913952 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/dtb
10950 16:32:19.914166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396103/tftp-deploy-kg8v5wn8/modules
10951 16:32:19.920164 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396103
10952 16:32:20.009921 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396103
10953 16:32:20.010071 Job finished correctly