Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 16:33:15.422588 lava-dispatcher, installed at version: 2024.03
2 16:33:15.422831 start: 0 validate
3 16:33:15.422976 Start time: 2024-06-17 16:33:15.422966+00:00 (UTC)
4 16:33:15.423138 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:33:15.423319 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 16:33:15.693721 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:33:15.694677 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:33:15.701879 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:33:15.703051 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:33:15.965208 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:33:15.965920 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:33:16.226063 validate duration: 0.80
14 16:33:16.226408 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:33:16.226595 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:33:16.226731 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:33:16.226924 Not decompressing ramdisk as can be used compressed.
18 16:33:16.227043 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 16:33:16.227140 saving as /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/ramdisk/rootfs.cpio.gz
20 16:33:16.227236 total size: 47897469 (45 MB)
21 16:33:16.228731 progress 0 % (0 MB)
22 16:33:16.241619 progress 5 % (2 MB)
23 16:33:16.253641 progress 10 % (4 MB)
24 16:33:16.265889 progress 15 % (6 MB)
25 16:33:16.279014 progress 20 % (9 MB)
26 16:33:16.291700 progress 25 % (11 MB)
27 16:33:16.304650 progress 30 % (13 MB)
28 16:33:16.316617 progress 35 % (16 MB)
29 16:33:16.328521 progress 40 % (18 MB)
30 16:33:16.340835 progress 45 % (20 MB)
31 16:33:16.353265 progress 50 % (22 MB)
32 16:33:16.365481 progress 55 % (25 MB)
33 16:33:16.377704 progress 60 % (27 MB)
34 16:33:16.389990 progress 65 % (29 MB)
35 16:33:16.402295 progress 70 % (32 MB)
36 16:33:16.414544 progress 75 % (34 MB)
37 16:33:16.426810 progress 80 % (36 MB)
38 16:33:16.439583 progress 85 % (38 MB)
39 16:33:16.451764 progress 90 % (41 MB)
40 16:33:16.463811 progress 95 % (43 MB)
41 16:33:16.476024 progress 100 % (45 MB)
42 16:33:16.476265 45 MB downloaded in 0.25 s (183.43 MB/s)
43 16:33:16.476421 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:33:16.476639 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:33:16.476758 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:33:16.476832 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:33:16.476961 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:33:16.477021 saving as /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/kernel/Image
50 16:33:16.477073 total size: 54813184 (52 MB)
51 16:33:16.477125 No compression specified
52 16:33:16.478128 progress 0 % (0 MB)
53 16:33:16.492319 progress 5 % (2 MB)
54 16:33:16.507046 progress 10 % (5 MB)
55 16:33:16.521495 progress 15 % (7 MB)
56 16:33:16.535674 progress 20 % (10 MB)
57 16:33:16.549600 progress 25 % (13 MB)
58 16:33:16.563421 progress 30 % (15 MB)
59 16:33:16.577541 progress 35 % (18 MB)
60 16:33:16.591983 progress 40 % (20 MB)
61 16:33:16.606445 progress 45 % (23 MB)
62 16:33:16.620594 progress 50 % (26 MB)
63 16:33:16.634714 progress 55 % (28 MB)
64 16:33:16.648732 progress 60 % (31 MB)
65 16:33:16.662670 progress 65 % (34 MB)
66 16:33:16.676335 progress 70 % (36 MB)
67 16:33:16.690134 progress 75 % (39 MB)
68 16:33:16.704029 progress 80 % (41 MB)
69 16:33:16.717998 progress 85 % (44 MB)
70 16:33:16.732176 progress 90 % (47 MB)
71 16:33:16.746232 progress 95 % (49 MB)
72 16:33:16.759655 progress 100 % (52 MB)
73 16:33:16.759922 52 MB downloaded in 0.28 s (184.81 MB/s)
74 16:33:16.760158 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:33:16.760535 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:33:16.760662 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:33:16.760790 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:33:16.760940 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:33:16.761061 saving as /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/dtb/mt8192-asurada-spherion-r0.dtb
81 16:33:16.761150 total size: 47258 (0 MB)
82 16:33:16.761240 No compression specified
83 16:33:16.762772 progress 69 % (0 MB)
84 16:33:16.763056 progress 100 % (0 MB)
85 16:33:16.763243 0 MB downloaded in 0.00 s (21.56 MB/s)
86 16:33:16.763398 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:33:16.763741 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:33:16.763852 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:33:16.763963 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:33:16.764103 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:33:16.764204 saving as /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/modules/modules.tar
93 16:33:16.764321 total size: 8628772 (8 MB)
94 16:33:16.764402 Using unxz to decompress xz
95 16:33:16.766298 progress 0 % (0 MB)
96 16:33:16.787970 progress 5 % (0 MB)
97 16:33:16.812881 progress 10 % (0 MB)
98 16:33:16.836828 progress 15 % (1 MB)
99 16:33:16.861145 progress 20 % (1 MB)
100 16:33:16.887036 progress 25 % (2 MB)
101 16:33:16.911606 progress 30 % (2 MB)
102 16:33:16.938276 progress 35 % (2 MB)
103 16:33:16.962744 progress 40 % (3 MB)
104 16:33:16.987048 progress 45 % (3 MB)
105 16:33:17.012196 progress 50 % (4 MB)
106 16:33:17.036057 progress 55 % (4 MB)
107 16:33:17.060986 progress 60 % (4 MB)
108 16:33:17.088598 progress 65 % (5 MB)
109 16:33:17.113040 progress 70 % (5 MB)
110 16:33:17.136870 progress 75 % (6 MB)
111 16:33:17.160048 progress 80 % (6 MB)
112 16:33:17.186247 progress 85 % (7 MB)
113 16:33:17.212583 progress 90 % (7 MB)
114 16:33:17.237260 progress 95 % (7 MB)
115 16:33:17.262168 progress 100 % (8 MB)
116 16:33:17.267135 8 MB downloaded in 0.50 s (16.37 MB/s)
117 16:33:17.267299 end: 1.4.1 http-download (duration 00:00:01) [common]
119 16:33:17.267506 end: 1.4 download-retry (duration 00:00:01) [common]
120 16:33:17.267584 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:33:17.267660 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:33:17.267735 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:33:17.267807 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:33:17.267963 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre
125 16:33:17.268086 makedir: /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin
126 16:33:17.268189 makedir: /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/tests
127 16:33:17.268312 makedir: /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/results
128 16:33:17.268430 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-add-keys
129 16:33:17.268593 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-add-sources
130 16:33:17.268779 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-background-process-start
131 16:33:17.268910 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-background-process-stop
132 16:33:17.269050 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-common-functions
133 16:33:17.269179 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-echo-ipv4
134 16:33:17.269330 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-install-packages
135 16:33:17.269479 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-installed-packages
136 16:33:17.269627 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-os-build
137 16:33:17.269777 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-probe-channel
138 16:33:17.269928 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-probe-ip
139 16:33:17.270077 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-target-ip
140 16:33:17.270226 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-target-mac
141 16:33:17.270376 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-target-storage
142 16:33:17.270525 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-case
143 16:33:17.270682 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-event
144 16:33:17.270830 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-feedback
145 16:33:17.270984 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-raise
146 16:33:17.271132 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-reference
147 16:33:17.271283 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-runner
148 16:33:17.271430 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-set
149 16:33:17.271580 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-test-shell
150 16:33:17.271728 Updating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-install-packages (oe)
151 16:33:17.271875 Updating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/bin/lava-installed-packages (oe)
152 16:33:17.272000 Creating /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/environment
153 16:33:17.272167 LAVA metadata
154 16:33:17.272262 - LAVA_JOB_ID=14396141
155 16:33:17.272352 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:33:17.272483 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:33:17.272567 skipped lava-vland-overlay
158 16:33:17.272719 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:33:17.272834 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:33:17.272918 skipped lava-multinode-overlay
161 16:33:17.273023 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:33:17.273129 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:33:17.273223 Loading test definitions
164 16:33:17.273335 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:33:17.273424 Using /lava-14396141 at stage 0
166 16:33:17.273830 uuid=14396141_1.5.2.3.1 testdef=None
167 16:33:17.273942 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:33:17.274053 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:33:17.274670 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:33:17.275012 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:33:17.275808 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:33:17.276162 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:33:17.276888 runner path: /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/0/tests/0_igt-gpu-panfrost test_uuid 14396141_1.5.2.3.1
176 16:33:17.277043 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:33:17.277315 Creating lava-test-runner.conf files
179 16:33:17.277406 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396141/lava-overlay-63e6cpre/lava-14396141/0 for stage 0
180 16:33:17.277525 - 0_igt-gpu-panfrost
181 16:33:17.277650 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:33:17.277760 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:33:17.286131 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:33:17.286260 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:33:17.286373 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:33:17.286486 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:33:17.286599 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:33:19.003738 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 16:33:19.003878 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 16:33:19.003968 extracting modules file /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396141/extract-overlay-ramdisk-pq9q6tud/ramdisk
191 16:33:19.271974 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:33:19.272135 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 16:33:19.272246 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396141/compress-overlay-h75yxb3f/overlay-1.5.2.4.tar.gz to ramdisk
194 16:33:19.272339 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396141/compress-overlay-h75yxb3f/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396141/extract-overlay-ramdisk-pq9q6tud/ramdisk
195 16:33:19.281222 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:33:19.281331 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 16:33:19.281447 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:33:19.281559 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 16:33:19.281657 Building ramdisk /var/lib/lava/dispatcher/tmp/14396141/extract-overlay-ramdisk-pq9q6tud/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396141/extract-overlay-ramdisk-pq9q6tud/ramdisk
200 16:33:20.388659 >> 466049 blocks
201 16:33:26.961045 rename /var/lib/lava/dispatcher/tmp/14396141/extract-overlay-ramdisk-pq9q6tud/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/ramdisk/ramdisk.cpio.gz
202 16:33:26.961211 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 16:33:26.961298 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 16:33:26.961377 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 16:33:26.961457 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/kernel/Image']
206 16:33:41.250617 Returned 0 in 14 seconds
207 16:33:41.351150 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/kernel/image.itb
208 16:33:42.288499 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:33:42.288700 output: Created: Mon Jun 17 17:33:42 2024
210 16:33:42.288784 output: Image 0 (kernel-1)
211 16:33:42.288846 output: Description:
212 16:33:42.288902 output: Created: Mon Jun 17 17:33:42 2024
213 16:33:42.288960 output: Type: Kernel Image
214 16:33:42.289016 output: Compression: lzma compressed
215 16:33:42.289075 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
216 16:33:42.289128 output: Architecture: AArch64
217 16:33:42.289183 output: OS: Linux
218 16:33:42.289256 output: Load Address: 0x00000000
219 16:33:42.289323 output: Entry Point: 0x00000000
220 16:33:42.289378 output: Hash algo: crc32
221 16:33:42.289431 output: Hash value: 106ffd6f
222 16:33:42.289487 output: Image 1 (fdt-1)
223 16:33:42.289540 output: Description: mt8192-asurada-spherion-r0
224 16:33:42.289593 output: Created: Mon Jun 17 17:33:42 2024
225 16:33:42.289645 output: Type: Flat Device Tree
226 16:33:42.289696 output: Compression: uncompressed
227 16:33:42.289747 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 16:33:42.289794 output: Architecture: AArch64
229 16:33:42.289841 output: Hash algo: crc32
230 16:33:42.289888 output: Hash value: 0f8e4d2e
231 16:33:42.289935 output: Image 2 (ramdisk-1)
232 16:33:42.289982 output: Description: unavailable
233 16:33:42.290028 output: Created: Mon Jun 17 17:33:42 2024
234 16:33:42.290075 output: Type: RAMDisk Image
235 16:33:42.290122 output: Compression: uncompressed
236 16:33:42.290168 output: Data Size: 61023671 Bytes = 59593.43 KiB = 58.20 MiB
237 16:33:42.290242 output: Architecture: AArch64
238 16:33:42.290291 output: OS: Linux
239 16:33:42.290356 output: Load Address: unavailable
240 16:33:42.290405 output: Entry Point: unavailable
241 16:33:42.290453 output: Hash algo: crc32
242 16:33:42.290500 output: Hash value: b28b6010
243 16:33:42.290547 output: Default Configuration: 'conf-1'
244 16:33:42.290595 output: Configuration 0 (conf-1)
245 16:33:42.290643 output: Description: mt8192-asurada-spherion-r0
246 16:33:42.290691 output: Kernel: kernel-1
247 16:33:42.290738 output: Init Ramdisk: ramdisk-1
248 16:33:42.290786 output: FDT: fdt-1
249 16:33:42.290833 output: Loadables: kernel-1
250 16:33:42.290881 output:
251 16:33:42.291090 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 16:33:42.291187 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 16:33:42.291298 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
254 16:33:42.291403 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 16:33:42.291511 No LXC device requested
256 16:33:42.291608 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:33:42.291712 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 16:33:42.291785 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:33:42.291891 Checking files for TFTP limit of 4294967296 bytes.
260 16:33:42.292340 end: 1 tftp-deploy (duration 00:00:26) [common]
261 16:33:42.292439 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:33:42.292523 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:33:42.292630 substitutions:
264 16:33:42.292743 - {DTB}: 14396141/tftp-deploy-9j6kryo5/dtb/mt8192-asurada-spherion-r0.dtb
265 16:33:42.292807 - {INITRD}: 14396141/tftp-deploy-9j6kryo5/ramdisk/ramdisk.cpio.gz
266 16:33:42.292861 - {KERNEL}: 14396141/tftp-deploy-9j6kryo5/kernel/Image
267 16:33:42.292912 - {LAVA_MAC}: None
268 16:33:42.292963 - {PRESEED_CONFIG}: None
269 16:33:42.293014 - {PRESEED_LOCAL}: None
270 16:33:42.293064 - {RAMDISK}: 14396141/tftp-deploy-9j6kryo5/ramdisk/ramdisk.cpio.gz
271 16:33:42.293122 - {ROOT_PART}: None
272 16:33:42.293173 - {ROOT}: None
273 16:33:42.293222 - {SERVER_IP}: 192.168.201.1
274 16:33:42.293287 - {TEE}: None
275 16:33:42.293351 Parsed boot commands:
276 16:33:42.293399 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:33:42.293552 Parsed boot commands: tftpboot 192.168.201.1 14396141/tftp-deploy-9j6kryo5/kernel/image.itb 14396141/tftp-deploy-9j6kryo5/kernel/cmdline
278 16:33:42.293634 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:33:42.293721 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:33:42.293818 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:33:42.293902 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:33:42.293963 Not connected, no need to disconnect.
283 16:33:42.294029 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:33:42.294103 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:33:42.294162 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 16:33:42.297783 Setting prompt string to ['lava-test: # ']
287 16:33:42.298156 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:33:42.298290 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:33:42.298454 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:33:42.298597 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:33:42.298882 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
292 16:33:56.085244 Returned 0 in 13 seconds
293 16:33:56.185865 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 16:33:56.186271 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 16:33:56.186414 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 16:33:56.186542 Setting prompt string to 'Starting depthcharge on Spherion...'
298 16:33:56.186636 Changing prompt to 'Starting depthcharge on Spherion...'
299 16:33:56.186733 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 16:33:56.187238 [Enter `^Ec?' for help]
301 16:33:56.187347
302 16:33:56.187435
303 16:33:56.187521 F0: 102B 0000
304 16:33:56.187607
305 16:33:56.187690 F3: 1001 0000 [0200]
306 16:33:56.187773
307 16:33:56.187862 F3: 1001 0000
308 16:33:56.187950
309 16:33:56.188040 F7: 102D 0000
310 16:33:56.188127
311 16:33:56.188215 F1: 0000 0000
312 16:33:56.188297
313 16:33:56.188385 V0: 0000 0000 [0001]
314 16:33:56.188475
315 16:33:56.188557 00: 0007 8000
316 16:33:56.188661
317 16:33:56.188749 01: 0000 0000
318 16:33:56.188834
319 16:33:56.188915 BP: 0C00 0209 [0000]
320 16:33:56.188993
321 16:33:56.189073 G0: 1182 0000
322 16:33:56.189153
323 16:33:56.189235 EC: 0000 0021 [4000]
324 16:33:56.189315
325 16:33:56.189396 S7: 0000 0000 [0000]
326 16:33:56.189475
327 16:33:56.189554 CC: 0000 0000 [0001]
328 16:33:56.189634
329 16:33:56.189714 T0: 0000 0040 [010F]
330 16:33:56.189793
331 16:33:56.189873 Jump to BL
332 16:33:56.189954
333 16:33:56.190033
334 16:33:56.190112
335 16:33:56.190192 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 16:33:56.190276 ARM64: Exception handlers installed.
337 16:33:56.190357 ARM64: Testing exception
338 16:33:56.190436 ARM64: Done test exception
339 16:33:56.190517 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 16:33:56.190600 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 16:33:56.190683 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 16:33:56.190766 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 16:33:56.190849 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 16:33:56.190930 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 16:33:56.191011 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 16:33:56.191091 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 16:33:56.191171 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 16:33:56.191251 WDT: Last reset was cold boot
349 16:33:56.191329 SPI1(PAD0) initialized at 2873684 Hz
350 16:33:56.191410 SPI5(PAD0) initialized at 992727 Hz
351 16:33:56.191491 VBOOT: Loading verstage.
352 16:33:56.191572 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 16:33:56.191654 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 16:33:56.191737 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 16:33:56.191819 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 16:33:56.191900 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 16:33:56.191980 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 16:33:56.192060 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 16:33:56.192138
360 16:33:56.192217
361 16:33:56.192297 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 16:33:56.192381 ARM64: Exception handlers installed.
363 16:33:56.192463 ARM64: Testing exception
364 16:33:56.192544 ARM64: Done test exception
365 16:33:56.192626 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 16:33:56.192713 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 16:33:56.192795 Probing TPM: . done!
368 16:33:56.192876 TPM ready after 0 ms
369 16:33:56.192957 Connected to device vid:did:rid of 1ae0:0028:00
370 16:33:56.193039 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 16:33:56.193122 Initialized TPM device CR50 revision 0
372 16:33:56.193204 tlcl_send_startup: Startup return code is 0
373 16:33:56.193284 TPM: setup succeeded
374 16:33:56.193365 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 16:33:56.193446 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 16:33:56.193526 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 16:33:56.193606 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:33:56.193685 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 16:33:56.193767 in-header: 03 07 00 00 08 00 00 00
380 16:33:56.193848 in-data: aa e4 47 04 13 02 00 00
381 16:33:56.193927 Chrome EC: UHEPI supported
382 16:33:56.194006 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 16:33:56.194086 in-header: 03 a9 00 00 08 00 00 00
384 16:33:56.194166 in-data: 84 60 60 08 00 00 00 00
385 16:33:56.194247 Phase 1
386 16:33:56.194328 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 16:33:56.194411 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 16:33:56.194494 VB2:vb2_check_recovery() Recovery was requested manually
389 16:33:56.194576 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 16:33:56.194658 Recovery requested (1009000e)
391 16:33:56.194739 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 16:33:56.194821 tlcl_extend: response is 0
393 16:33:56.194901 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 16:33:56.194980 tlcl_extend: response is 0
395 16:33:56.195057 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 16:33:56.195137 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 16:33:56.195216 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 16:33:56.195295
399 16:33:56.195375
400 16:33:56.195456 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 16:33:56.195540 ARM64: Exception handlers installed.
402 16:33:56.195622 ARM64: Testing exception
403 16:33:56.195703 ARM64: Done test exception
404 16:33:56.195783 pmic_efuse_setting: Set efuses in 11 msecs
405 16:33:56.195863 pmwrap_interface_init: Select PMIF_VLD_RDY
406 16:33:56.195944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 16:33:56.196026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 16:33:56.196319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 16:33:56.196414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 16:33:56.196499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 16:33:56.196582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 16:33:56.196672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 16:33:56.196757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 16:33:56.196839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 16:33:56.196922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 16:33:56.197005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 16:33:56.197088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 16:33:56.197169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 16:33:56.197251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 16:33:56.197335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 16:33:56.197420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 16:33:56.197504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 16:33:56.197587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 16:33:56.197671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 16:33:56.197753 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 16:33:56.197836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 16:33:56.197919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 16:33:56.198000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 16:33:56.198081 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 16:33:56.198162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 16:33:56.198244 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 16:33:56.198326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 16:33:56.198407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 16:33:56.198488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 16:33:56.198570 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 16:33:56.198651 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 16:33:56.198733 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 16:33:56.198814 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 16:33:56.198895 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 16:33:56.198975 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 16:33:56.199054 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 16:33:56.199133 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 16:33:56.199212 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 16:33:56.199293 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 16:33:56.199374 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 16:33:56.199455 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 16:33:56.199533 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 16:33:56.199613 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 16:33:56.199694 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 16:33:56.199777 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 16:33:56.199859 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 16:33:56.199940 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 16:33:56.200022 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 16:33:56.200104 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 16:33:56.200185 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 16:33:56.200266 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 16:33:56.200345 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 16:33:56.200429 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 16:33:56.200512 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 16:33:56.200595 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 16:33:56.200683 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 16:33:56.200763 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 16:33:56.200844 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 16:33:56.200924 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:33:56.201006 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1
466 16:33:56.201088 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 16:33:56.201169 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 16:33:56.201250 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 16:33:56.201332 [RTC]rtc_get_frequency_meter,154: input=15, output=793
470 16:33:56.201414 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 16:33:56.201496 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 16:33:56.201577 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
473 16:33:56.201659 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 16:33:56.201741 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
475 16:33:56.201822 ADC[4]: Raw value=896670 ID=7
476 16:33:56.201904 ADC[3]: Raw value=213440 ID=1
477 16:33:56.201983 RAM Code: 0x71
478 16:33:56.202063 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 16:33:56.202145 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 16:33:56.202431 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 16:33:56.202528 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 16:33:56.202613 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 16:33:56.202697 in-header: 03 07 00 00 08 00 00 00
484 16:33:56.202779 in-data: aa e4 47 04 13 02 00 00
485 16:33:56.202860 Chrome EC: UHEPI supported
486 16:33:56.202938 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 16:33:56.203019 in-header: 03 a9 00 00 08 00 00 00
488 16:33:56.203100 in-data: 84 60 60 08 00 00 00 00
489 16:33:56.203180 MRC: failed to locate region type 0.
490 16:33:56.203260 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 16:33:56.203343 DRAM-K: Running full calibration
492 16:33:56.203424 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 16:33:56.203507 header.status = 0x0
494 16:33:56.203587 header.version = 0x6 (expected: 0x6)
495 16:33:56.203668 header.size = 0xd00 (expected: 0xd00)
496 16:33:56.203749 header.flags = 0x0
497 16:33:56.203830 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 16:33:56.203912 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
499 16:33:56.203993 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 16:33:56.204073 dram_init: ddr_geometry: 2
501 16:33:56.204152 [EMI] MDL number = 2
502 16:33:56.204230 [EMI] Get MDL freq = 0
503 16:33:56.204307 dram_init: ddr_type: 0
504 16:33:56.204387 is_discrete_lpddr4: 1
505 16:33:56.204470 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 16:33:56.204551
507 16:33:56.204632
508 16:33:56.204730 [Bian_co] ETT version 0.0.0.1
509 16:33:56.204812 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 16:33:56.204896
511 16:33:56.204979 dramc_set_vcore_voltage set vcore to 650000
512 16:33:56.205062 Read voltage for 800, 4
513 16:33:56.205143 Vio18 = 0
514 16:33:56.205225 Vcore = 650000
515 16:33:56.205306 Vdram = 0
516 16:33:56.205387 Vddq = 0
517 16:33:56.205467 Vmddr = 0
518 16:33:56.205547 dram_init: config_dvfs: 1
519 16:33:56.205624 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 16:33:56.205705 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 16:33:56.205786 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 16:33:56.205868 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 16:33:56.205949 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 16:33:56.206031 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 16:33:56.206113 MEM_TYPE=3, freq_sel=18
526 16:33:56.206194 sv_algorithm_assistance_LP4_1600
527 16:33:56.206277 ============ PULL DRAM RESETB DOWN ============
528 16:33:56.206363 ========== PULL DRAM RESETB DOWN end =========
529 16:33:56.206443 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 16:33:56.206520 ===================================
531 16:33:56.206596 LPDDR4 DRAM CONFIGURATION
532 16:33:56.206672 ===================================
533 16:33:56.206751 EX_ROW_EN[0] = 0x0
534 16:33:56.206831 EX_ROW_EN[1] = 0x0
535 16:33:56.206912 LP4Y_EN = 0x0
536 16:33:56.206994 WORK_FSP = 0x0
537 16:33:56.207075 WL = 0x2
538 16:33:56.207155 RL = 0x2
539 16:33:56.207232 BL = 0x2
540 16:33:56.207311 RPST = 0x0
541 16:33:56.207390 RD_PRE = 0x0
542 16:33:56.207469 WR_PRE = 0x1
543 16:33:56.207548 WR_PST = 0x0
544 16:33:56.207629 DBI_WR = 0x0
545 16:33:56.207710 DBI_RD = 0x0
546 16:33:56.207790 OTF = 0x1
547 16:33:56.207871 ===================================
548 16:33:56.207951 ===================================
549 16:33:56.208033 ANA top config
550 16:33:56.208113 ===================================
551 16:33:56.208195 DLL_ASYNC_EN = 0
552 16:33:56.208277 ALL_SLAVE_EN = 1
553 16:33:56.208356 NEW_RANK_MODE = 1
554 16:33:56.208439 DLL_IDLE_MODE = 1
555 16:33:56.208520 LP45_APHY_COMB_EN = 1
556 16:33:56.208601 TX_ODT_DIS = 1
557 16:33:56.208688 NEW_8X_MODE = 1
558 16:33:56.208772 ===================================
559 16:33:56.208854 ===================================
560 16:33:56.208936 data_rate = 1600
561 16:33:56.209018 CKR = 1
562 16:33:56.209098 DQ_P2S_RATIO = 8
563 16:33:56.209178 ===================================
564 16:33:56.209259 CA_P2S_RATIO = 8
565 16:33:56.209338 DQ_CA_OPEN = 0
566 16:33:56.209416 DQ_SEMI_OPEN = 0
567 16:33:56.209495 CA_SEMI_OPEN = 0
568 16:33:56.209574 CA_FULL_RATE = 0
569 16:33:56.209654 DQ_CKDIV4_EN = 1
570 16:33:56.209734 CA_CKDIV4_EN = 1
571 16:33:56.209815 CA_PREDIV_EN = 0
572 16:33:56.209896 PH8_DLY = 0
573 16:33:56.209975 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 16:33:56.210055 DQ_AAMCK_DIV = 4
575 16:33:56.210138 CA_AAMCK_DIV = 4
576 16:33:56.210219 CA_ADMCK_DIV = 4
577 16:33:56.210298 DQ_TRACK_CA_EN = 0
578 16:33:56.210378 CA_PICK = 800
579 16:33:56.210457 CA_MCKIO = 800
580 16:33:56.210534 MCKIO_SEMI = 0
581 16:33:56.210612 PLL_FREQ = 3068
582 16:33:56.210691 DQ_UI_PI_RATIO = 32
583 16:33:56.210771 CA_UI_PI_RATIO = 0
584 16:33:56.210851 ===================================
585 16:33:56.210931 ===================================
586 16:33:56.211012 memory_type:LPDDR4
587 16:33:56.211091 GP_NUM : 10
588 16:33:56.211169 SRAM_EN : 1
589 16:33:56.211248 MD32_EN : 0
590 16:33:56.211325 ===================================
591 16:33:56.211405 [ANA_INIT] >>>>>>>>>>>>>>
592 16:33:56.211485 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 16:33:56.211573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 16:33:56.211654 ===================================
595 16:33:56.211735 data_rate = 1600,PCW = 0X7600
596 16:33:56.211816 ===================================
597 16:33:56.211899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 16:33:56.211980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 16:33:56.212062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 16:33:56.212369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 16:33:56.212461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 16:33:56.212546 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 16:33:56.212629 [ANA_INIT] flow start
604 16:33:56.212721 [ANA_INIT] PLL >>>>>>>>
605 16:33:56.212803 [ANA_INIT] PLL <<<<<<<<
606 16:33:56.212884 [ANA_INIT] MIDPI >>>>>>>>
607 16:33:56.212965 [ANA_INIT] MIDPI <<<<<<<<
608 16:33:56.213045 [ANA_INIT] DLL >>>>>>>>
609 16:33:56.213125 [ANA_INIT] flow end
610 16:33:56.213205 ============ LP4 DIFF to SE enter ============
611 16:33:56.213284 ============ LP4 DIFF to SE exit ============
612 16:33:56.213360 [ANA_INIT] <<<<<<<<<<<<<
613 16:33:56.213438 [Flow] Enable top DCM control >>>>>
614 16:33:56.213517 [Flow] Enable top DCM control <<<<<
615 16:33:56.213598 Enable DLL master slave shuffle
616 16:33:56.213679 ==============================================================
617 16:33:56.213760 Gating Mode config
618 16:33:56.213840 ==============================================================
619 16:33:56.213920 Config description:
620 16:33:56.214001 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 16:33:56.214083 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 16:33:56.214165 SELPH_MODE 0: By rank 1: By Phase
623 16:33:56.214246 ==============================================================
624 16:33:56.214326 GAT_TRACK_EN = 1
625 16:33:56.214407 RX_GATING_MODE = 2
626 16:33:56.214485 RX_GATING_TRACK_MODE = 2
627 16:33:56.214565 SELPH_MODE = 1
628 16:33:56.214644 PICG_EARLY_EN = 1
629 16:33:56.214724 VALID_LAT_VALUE = 1
630 16:33:56.214803 ==============================================================
631 16:33:56.214883 Enter into Gating configuration >>>>
632 16:33:56.214962 Exit from Gating configuration <<<<
633 16:33:56.215040 Enter into DVFS_PRE_config >>>>>
634 16:33:56.215119 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 16:33:56.215204 Exit from DVFS_PRE_config <<<<<
636 16:33:56.215284 Enter into PICG configuration >>>>
637 16:33:56.215364 Exit from PICG configuration <<<<
638 16:33:56.215443 [RX_INPUT] configuration >>>>>
639 16:33:56.215522 [RX_INPUT] configuration <<<<<
640 16:33:56.215599 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 16:33:56.215677 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 16:33:56.215754 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 16:33:56.215833 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 16:33:56.215911 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 16:33:56.215990 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 16:33:56.216071 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 16:33:56.216150 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 16:33:56.216228 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 16:33:56.216308 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 16:33:56.216388 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 16:33:56.216467 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 16:33:56.216546 ===================================
653 16:33:56.216625 LPDDR4 DRAM CONFIGURATION
654 16:33:56.216709 ===================================
655 16:33:56.216789 EX_ROW_EN[0] = 0x0
656 16:33:56.216867 EX_ROW_EN[1] = 0x0
657 16:33:56.216942 LP4Y_EN = 0x0
658 16:33:56.217018 WORK_FSP = 0x0
659 16:33:56.217096 WL = 0x2
660 16:33:56.217174 RL = 0x2
661 16:33:56.217250 BL = 0x2
662 16:33:56.217326 RPST = 0x0
663 16:33:56.217402 RD_PRE = 0x0
664 16:33:56.217477 WR_PRE = 0x1
665 16:33:56.217551 WR_PST = 0x0
666 16:33:56.217626 DBI_WR = 0x0
667 16:33:56.217702 DBI_RD = 0x0
668 16:33:56.217780 OTF = 0x1
669 16:33:56.217859 ===================================
670 16:33:56.217941 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 16:33:56.218022 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 16:33:56.218102 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 16:33:56.218183 ===================================
674 16:33:56.218262 LPDDR4 DRAM CONFIGURATION
675 16:33:56.218341 ===================================
676 16:33:56.218422 EX_ROW_EN[0] = 0x10
677 16:33:56.218503 EX_ROW_EN[1] = 0x0
678 16:33:56.218585 LP4Y_EN = 0x0
679 16:33:56.218667 WORK_FSP = 0x0
680 16:33:56.218747 WL = 0x2
681 16:33:56.218827 RL = 0x2
682 16:33:56.218907 BL = 0x2
683 16:33:56.218987 RPST = 0x0
684 16:33:56.219067 RD_PRE = 0x0
685 16:33:56.219146 WR_PRE = 0x1
686 16:33:56.219225 WR_PST = 0x0
687 16:33:56.219304 DBI_WR = 0x0
688 16:33:56.219381 DBI_RD = 0x0
689 16:33:56.219461 OTF = 0x1
690 16:33:56.219542 ===================================
691 16:33:56.219664 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 16:33:56.219762 nWR fixed to 40
693 16:33:56.219843 [ModeRegInit_LP4] CH0 RK0
694 16:33:56.219921 [ModeRegInit_LP4] CH0 RK1
695 16:33:56.219997 [ModeRegInit_LP4] CH1 RK0
696 16:33:56.220073 [ModeRegInit_LP4] CH1 RK1
697 16:33:56.220148 match AC timing 13
698 16:33:56.220223 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 16:33:56.220300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 16:33:56.220380 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 16:33:56.220463 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 16:33:56.220545 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 16:33:56.220626 [EMI DOE] emi_dcm 0
704 16:33:56.220713 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 16:33:56.220795 ==
706 16:33:56.220876 Dram Type= 6, Freq= 0, CH_0, rank 0
707 16:33:56.220957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 16:33:56.221039 ==
709 16:33:56.221336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 16:33:56.221435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 16:33:56.221519 [CA 0] Center 38 (7~69) winsize 63
712 16:33:56.221601 [CA 1] Center 38 (7~69) winsize 63
713 16:33:56.221682 [CA 2] Center 35 (5~66) winsize 62
714 16:33:56.221763 [CA 3] Center 35 (5~66) winsize 62
715 16:33:56.221845 [CA 4] Center 34 (4~65) winsize 62
716 16:33:56.221926 [CA 5] Center 34 (3~65) winsize 63
717 16:33:56.222007
718 16:33:56.222089 [CmdBusTrainingLP45] Vref(ca) range 1: 34
719 16:33:56.222170
720 16:33:56.222248 [CATrainingPosCal] consider 1 rank data
721 16:33:56.222328 u2DelayCellTimex100 = 270/100 ps
722 16:33:56.222407 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 16:33:56.222488 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
724 16:33:56.222568 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 16:33:56.222650 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 16:33:56.222731 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 16:33:56.222812 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
728 16:33:56.222893
729 16:33:56.222973 CA PerBit enable=1, Macro0, CA PI delay=34
730 16:33:56.223052
731 16:33:56.223132 [CBTSetCACLKResult] CA Dly = 34
732 16:33:56.223211 CS Dly: 6 (0~37)
733 16:33:56.223289 ==
734 16:33:56.223368 Dram Type= 6, Freq= 0, CH_0, rank 1
735 16:33:56.223451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 16:33:56.223533 ==
737 16:33:56.223614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 16:33:56.223696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 16:33:56.223777 [CA 0] Center 38 (7~69) winsize 63
740 16:33:56.223858 [CA 1] Center 38 (7~69) winsize 63
741 16:33:56.223939 [CA 2] Center 35 (5~66) winsize 62
742 16:33:56.224019 [CA 3] Center 35 (5~66) winsize 62
743 16:33:56.224099 [CA 4] Center 34 (4~65) winsize 62
744 16:33:56.224180 [CA 5] Center 34 (4~65) winsize 62
745 16:33:56.224262
746 16:33:56.224343 [CmdBusTrainingLP45] Vref(ca) range 1: 32
747 16:33:56.224423
748 16:33:56.224503 [CATrainingPosCal] consider 2 rank data
749 16:33:56.224582 u2DelayCellTimex100 = 270/100 ps
750 16:33:56.224709 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 16:33:56.224815 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
752 16:33:56.224909 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 16:33:56.225000 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 16:33:56.225089 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 16:33:56.225178 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 16:33:56.225265
757 16:33:56.225352 CA PerBit enable=1, Macro0, CA PI delay=34
758 16:33:56.225438
759 16:33:56.225524 [CBTSetCACLKResult] CA Dly = 34
760 16:33:56.225610 CS Dly: 6 (0~37)
761 16:33:56.225697
762 16:33:56.225783 ----->DramcWriteLeveling(PI) begin...
763 16:33:56.225872 ==
764 16:33:56.225958 Dram Type= 6, Freq= 0, CH_0, rank 0
765 16:33:56.226043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 16:33:56.226128 ==
767 16:33:56.226214 Write leveling (Byte 0): 31 => 31
768 16:33:56.226299 Write leveling (Byte 1): 30 => 30
769 16:33:56.226384 DramcWriteLeveling(PI) end<-----
770 16:33:56.226469
771 16:33:56.226553 ==
772 16:33:56.226638 Dram Type= 6, Freq= 0, CH_0, rank 0
773 16:33:56.226724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 16:33:56.226810 ==
775 16:33:56.226890 [Gating] SW mode calibration
776 16:33:56.226983 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 16:33:56.227082 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 16:33:56.227180 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 16:33:56.227278 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 16:33:56.227373 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
781 16:33:56.227459 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 16:33:56.227560 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 16:33:56.227648 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 16:33:56.227733 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 16:33:56.227819 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 16:33:56.227904 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 16:33:56.227989 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 16:33:56.228073 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 16:33:56.228158 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:33:56.228242 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:33:56.228327 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:33:56.228411 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:33:56.228496 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 16:33:56.228580 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 16:33:56.228674 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 16:33:56.228760 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
797 16:33:56.228846 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
798 16:33:56.228931 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 16:33:56.229016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 16:33:56.229103 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 16:33:56.229188 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 16:33:56.229274 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 16:33:56.229363 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 16:33:56.229449 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 16:33:56.229533 0 9 12 | B1->B0 | 2a2a 3030 | 1 1 | (1 1) (1 1)
806 16:33:56.229618 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 16:33:56.229703 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 16:33:56.229787 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 16:33:56.229872 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 16:33:56.229957 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 16:33:56.230042 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 16:33:56.230126 0 10 8 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)
813 16:33:56.230211 0 10 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
814 16:33:56.230296 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 16:33:56.230593 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 16:33:56.230679 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 16:33:56.230766 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 16:33:56.230851 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 16:33:56.230936 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 16:33:56.231025 0 11 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
821 16:33:56.231099 0 11 12 | B1->B0 | 3434 4545 | 1 0 | (0 0) (0 0)
822 16:33:56.231172 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 16:33:56.231248 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 16:33:56.231319 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 16:33:56.231396 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 16:33:56.231469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 16:33:56.231541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 16:33:56.231619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
829 16:33:56.231693 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
830 16:33:56.231768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 16:33:56.231848 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 16:33:56.231921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 16:33:56.231993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 16:33:56.232071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 16:33:56.232150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 16:33:56.232239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 16:33:56.232331 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 16:33:56.232419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 16:33:56.232505 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 16:33:56.232592 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 16:33:56.232692 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 16:33:56.232779 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 16:33:56.232865 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 16:33:56.232950 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 16:33:56.233034 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 16:33:56.233119 Total UI for P1: 0, mck2ui 16
847 16:33:56.233205 best dqsien dly found for B0: ( 0, 14, 10)
848 16:33:56.233291 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 16:33:56.233376 Total UI for P1: 0, mck2ui 16
850 16:33:56.233462 best dqsien dly found for B1: ( 0, 14, 12)
851 16:33:56.233549 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
852 16:33:56.233634 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
853 16:33:56.233719
854 16:33:56.233803 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
855 16:33:56.233888 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
856 16:33:56.233973 [Gating] SW calibration Done
857 16:33:56.234057 ==
858 16:33:56.234142 Dram Type= 6, Freq= 0, CH_0, rank 0
859 16:33:56.234227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 16:33:56.234312 ==
861 16:33:56.234398 RX Vref Scan: 0
862 16:33:56.234483
863 16:33:56.234569 RX Vref 0 -> 0, step: 1
864 16:33:56.234655
865 16:33:56.234741 RX Delay -130 -> 252, step: 16
866 16:33:56.234827 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 16:33:56.234914 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 16:33:56.234999 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 16:33:56.235084 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 16:33:56.235170 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 16:33:56.235257 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 16:33:56.235344 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 16:33:56.235431 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 16:33:56.235515 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 16:33:56.235599 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 16:33:56.235686 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 16:33:56.235773 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 16:33:56.235857 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 16:33:56.235944 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 16:33:56.236029 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 16:33:56.236115 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 16:33:56.236202 ==
883 16:33:56.236287 Dram Type= 6, Freq= 0, CH_0, rank 0
884 16:33:56.236373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 16:33:56.236459 ==
886 16:33:56.236544 DQS Delay:
887 16:33:56.236628 DQS0 = 0, DQS1 = 0
888 16:33:56.236718 DQM Delay:
889 16:33:56.236803 DQM0 = 81, DQM1 = 70
890 16:33:56.236888 DQ Delay:
891 16:33:56.236972 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
892 16:33:56.237056 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 16:33:56.237140 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 16:33:56.237225 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 16:33:56.237309
896 16:33:56.237395
897 16:33:56.237480 ==
898 16:33:56.237564 Dram Type= 6, Freq= 0, CH_0, rank 0
899 16:33:56.237650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 16:33:56.237735 ==
901 16:33:56.237821
902 16:33:56.237905
903 16:33:56.237988 TX Vref Scan disable
904 16:33:56.238076 == TX Byte 0 ==
905 16:33:56.238160 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 16:33:56.238247 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 16:33:56.238333 == TX Byte 1 ==
908 16:33:56.238418 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 16:33:56.238504 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 16:33:56.238590 ==
911 16:33:56.238675 Dram Type= 6, Freq= 0, CH_0, rank 0
912 16:33:56.238763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 16:33:56.238849 ==
914 16:33:56.238935 TX Vref=22, minBit 1, minWin=26, winSum=437
915 16:33:56.239020 TX Vref=24, minBit 14, minWin=26, winSum=438
916 16:33:56.239105 TX Vref=26, minBit 7, minWin=27, winSum=442
917 16:33:56.239190 TX Vref=28, minBit 10, minWin=27, winSum=444
918 16:33:56.239275 TX Vref=30, minBit 9, minWin=27, winSum=441
919 16:33:56.239361 TX Vref=32, minBit 12, minWin=26, winSum=441
920 16:33:56.239447 [TxChooseVref] Worse bit 10, Min win 27, Win sum 444, Final Vref 28
921 16:33:56.239533
922 16:33:56.239617 Final TX Range 1 Vref 28
923 16:33:56.239701
924 16:33:56.239785 ==
925 16:33:56.239872 Dram Type= 6, Freq= 0, CH_0, rank 0
926 16:33:56.240160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 16:33:56.240245 ==
928 16:33:56.240331
929 16:33:56.240426
930 16:33:56.240514 TX Vref Scan disable
931 16:33:56.240599 == TX Byte 0 ==
932 16:33:56.240705 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 16:33:56.240804 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 16:33:56.240900 == TX Byte 1 ==
935 16:33:56.240997 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 16:33:56.241095 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 16:33:56.241194
938 16:33:56.241288 [DATLAT]
939 16:33:56.241380 Freq=800, CH0 RK0
940 16:33:56.241476
941 16:33:56.241570 DATLAT Default: 0xa
942 16:33:56.241666 0, 0xFFFF, sum = 0
943 16:33:56.241765 1, 0xFFFF, sum = 0
944 16:33:56.241990 2, 0xFFFF, sum = 0
945 16:33:56.242075 3, 0xFFFF, sum = 0
946 16:33:56.242158 4, 0xFFFF, sum = 0
947 16:33:56.242240 5, 0xFFFF, sum = 0
948 16:33:56.242319 6, 0xFFFF, sum = 0
949 16:33:56.242400 7, 0xFFFF, sum = 0
950 16:33:56.242481 8, 0xFFFF, sum = 0
951 16:33:56.242559 9, 0x0, sum = 1
952 16:33:56.242638 10, 0x0, sum = 2
953 16:33:56.242719 11, 0x0, sum = 3
954 16:33:56.242805 12, 0x0, sum = 4
955 16:33:56.242886 best_step = 10
956 16:33:56.242965
957 16:33:56.243045 ==
958 16:33:56.243126 Dram Type= 6, Freq= 0, CH_0, rank 0
959 16:33:56.243203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 16:33:56.243281 ==
961 16:33:56.243357 RX Vref Scan: 1
962 16:33:56.243434
963 16:33:56.243514 Set Vref Range= 32 -> 127
964 16:33:56.243590
965 16:33:56.243666 RX Vref 32 -> 127, step: 1
966 16:33:56.243742
967 16:33:56.243817 RX Delay -111 -> 252, step: 8
968 16:33:56.243871
969 16:33:56.243925 Set Vref, RX VrefLevel [Byte0]: 32
970 16:33:56.244005 [Byte1]: 32
971 16:33:56.244081
972 16:33:56.244159 Set Vref, RX VrefLevel [Byte0]: 33
973 16:33:56.244237 [Byte1]: 33
974 16:33:56.244318
975 16:33:56.244400 Set Vref, RX VrefLevel [Byte0]: 34
976 16:33:56.244479 [Byte1]: 34
977 16:33:56.244555
978 16:33:56.244632 Set Vref, RX VrefLevel [Byte0]: 35
979 16:33:56.244696 [Byte1]: 35
980 16:33:56.244745
981 16:33:56.244826 Set Vref, RX VrefLevel [Byte0]: 36
982 16:33:56.244903 [Byte1]: 36
983 16:33:56.244978
984 16:33:56.245055 Set Vref, RX VrefLevel [Byte0]: 37
985 16:33:56.245132 [Byte1]: 37
986 16:33:56.245210
987 16:33:56.245287 Set Vref, RX VrefLevel [Byte0]: 38
988 16:33:56.245363 [Byte1]: 38
989 16:33:56.245441
990 16:33:56.245518 Set Vref, RX VrefLevel [Byte0]: 39
991 16:33:56.245598 [Byte1]: 39
992 16:33:56.245674
993 16:33:56.245750 Set Vref, RX VrefLevel [Byte0]: 40
994 16:33:56.245826 [Byte1]: 40
995 16:33:56.245902
996 16:33:56.245982 Set Vref, RX VrefLevel [Byte0]: 41
997 16:33:56.246061 [Byte1]: 41
998 16:33:56.246137
999 16:33:56.246213 Set Vref, RX VrefLevel [Byte0]: 42
1000 16:33:56.246291 [Byte1]: 42
1001 16:33:56.246369
1002 16:33:56.246449 Set Vref, RX VrefLevel [Byte0]: 43
1003 16:33:56.246526 [Byte1]: 43
1004 16:33:56.246601
1005 16:33:56.246677 Set Vref, RX VrefLevel [Byte0]: 44
1006 16:33:56.246753 [Byte1]: 44
1007 16:33:56.246829
1008 16:33:56.246905 Set Vref, RX VrefLevel [Byte0]: 45
1009 16:33:56.246982 [Byte1]: 45
1010 16:33:56.247058
1011 16:33:56.247134 Set Vref, RX VrefLevel [Byte0]: 46
1012 16:33:56.247211 [Byte1]: 46
1013 16:33:56.247286
1014 16:33:56.247363 Set Vref, RX VrefLevel [Byte0]: 47
1015 16:33:56.247440 [Byte1]: 47
1016 16:33:56.247517
1017 16:33:56.247593 Set Vref, RX VrefLevel [Byte0]: 48
1018 16:33:56.247670 [Byte1]: 48
1019 16:33:56.247745
1020 16:33:56.247824 Set Vref, RX VrefLevel [Byte0]: 49
1021 16:33:56.247901 [Byte1]: 49
1022 16:33:56.247978
1023 16:33:56.248055 Set Vref, RX VrefLevel [Byte0]: 50
1024 16:33:56.248132 [Byte1]: 50
1025 16:33:56.248207
1026 16:33:56.248283 Set Vref, RX VrefLevel [Byte0]: 51
1027 16:33:56.248360 [Byte1]: 51
1028 16:33:56.248435
1029 16:33:56.248511 Set Vref, RX VrefLevel [Byte0]: 52
1030 16:33:56.248588 [Byte1]: 52
1031 16:33:56.248669
1032 16:33:56.248747 Set Vref, RX VrefLevel [Byte0]: 53
1033 16:33:56.248836 [Byte1]: 53
1034 16:33:56.248913
1035 16:33:56.248989 Set Vref, RX VrefLevel [Byte0]: 54
1036 16:33:56.249066 [Byte1]: 54
1037 16:33:56.249142
1038 16:33:56.249219 Set Vref, RX VrefLevel [Byte0]: 55
1039 16:33:56.249296 [Byte1]: 55
1040 16:33:56.249371
1041 16:33:56.249447 Set Vref, RX VrefLevel [Byte0]: 56
1042 16:33:56.249524 [Byte1]: 56
1043 16:33:56.249600
1044 16:33:56.249678 Set Vref, RX VrefLevel [Byte0]: 57
1045 16:33:56.249761 [Byte1]: 57
1046 16:33:56.249852
1047 16:33:56.249945 Set Vref, RX VrefLevel [Byte0]: 58
1048 16:33:56.250040 [Byte1]: 58
1049 16:33:56.250133
1050 16:33:56.250224 Set Vref, RX VrefLevel [Byte0]: 59
1051 16:33:56.250304 [Byte1]: 59
1052 16:33:56.250395
1053 16:33:56.250491 Set Vref, RX VrefLevel [Byte0]: 60
1054 16:33:56.250581 [Byte1]: 60
1055 16:33:56.250663
1056 16:33:56.250738 Set Vref, RX VrefLevel [Byte0]: 61
1057 16:33:56.250789 [Byte1]: 61
1058 16:33:56.250837
1059 16:33:56.250885 Set Vref, RX VrefLevel [Byte0]: 62
1060 16:33:56.250934 [Byte1]: 62
1061 16:33:56.250986
1062 16:33:56.251037 Set Vref, RX VrefLevel [Byte0]: 63
1063 16:33:56.251086 [Byte1]: 63
1064 16:33:56.251134
1065 16:33:56.251181 Set Vref, RX VrefLevel [Byte0]: 64
1066 16:33:56.251229 [Byte1]: 64
1067 16:33:56.251277
1068 16:33:56.251325 Set Vref, RX VrefLevel [Byte0]: 65
1069 16:33:56.251380 [Byte1]: 65
1070 16:33:56.251432
1071 16:33:56.251483 Set Vref, RX VrefLevel [Byte0]: 66
1072 16:33:56.251531 [Byte1]: 66
1073 16:33:56.251579
1074 16:33:56.251626 Set Vref, RX VrefLevel [Byte0]: 67
1075 16:33:56.251676 [Byte1]: 67
1076 16:33:56.251753
1077 16:33:56.251830 Set Vref, RX VrefLevel [Byte0]: 68
1078 16:33:56.251909 [Byte1]: 68
1079 16:33:56.251988
1080 16:33:56.252065 Set Vref, RX VrefLevel [Byte0]: 69
1081 16:33:56.252141 [Byte1]: 69
1082 16:33:56.252217
1083 16:33:56.252292 Set Vref, RX VrefLevel [Byte0]: 70
1084 16:33:56.252369 [Byte1]: 70
1085 16:33:56.252444
1086 16:33:56.252523 Set Vref, RX VrefLevel [Byte0]: 71
1087 16:33:56.252600 [Byte1]: 71
1088 16:33:56.252684
1089 16:33:56.252738 Set Vref, RX VrefLevel [Byte0]: 72
1090 16:33:56.252800 [Byte1]: 72
1091 16:33:56.252877
1092 16:33:56.252966 Set Vref, RX VrefLevel [Byte0]: 73
1093 16:33:56.253045 [Byte1]: 73
1094 16:33:56.253121
1095 16:33:56.253178 Set Vref, RX VrefLevel [Byte0]: 74
1096 16:33:56.253257 [Byte1]: 74
1097 16:33:56.253336
1098 16:33:56.253619 Set Vref, RX VrefLevel [Byte0]: 75
1099 16:33:56.253719 [Byte1]: 75
1100 16:33:56.253806
1101 16:33:56.253888 Set Vref, RX VrefLevel [Byte0]: 76
1102 16:33:56.253966 [Byte1]: 76
1103 16:33:56.254034
1104 16:33:56.254085 Set Vref, RX VrefLevel [Byte0]: 77
1105 16:33:56.254133 [Byte1]: 77
1106 16:33:56.254181
1107 16:33:56.254230 Set Vref, RX VrefLevel [Byte0]: 78
1108 16:33:56.254278 [Byte1]: 78
1109 16:33:56.254326
1110 16:33:56.254375 Set Vref, RX VrefLevel [Byte0]: 79
1111 16:33:56.254423 [Byte1]: 79
1112 16:33:56.254471
1113 16:33:56.254524 Final RX Vref Byte 0 = 59 to rank0
1114 16:33:56.254608 Final RX Vref Byte 1 = 58 to rank0
1115 16:33:56.254687 Final RX Vref Byte 0 = 59 to rank1
1116 16:33:56.254776 Final RX Vref Byte 1 = 58 to rank1==
1117 16:33:56.254871 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 16:33:56.254966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 16:33:56.255058 ==
1120 16:33:56.255139 DQS Delay:
1121 16:33:56.255217 DQS0 = 0, DQS1 = 0
1122 16:33:56.255298 DQM Delay:
1123 16:33:56.255381 DQM0 = 82, DQM1 = 67
1124 16:33:56.255459 DQ Delay:
1125 16:33:56.255536 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 16:33:56.255613 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1127 16:33:56.255692 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1128 16:33:56.255772 DQ12 =72, DQ13 =68, DQ14 =80, DQ15 =76
1129 16:33:56.255849
1130 16:33:56.255928
1131 16:33:56.256007 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1132 16:33:56.256087 CH0 RK0: MR19=606, MR18=2A2A
1133 16:33:56.256168 CH0_RK0: MR19=0x606, MR18=0x2A2A, DQSOSC=399, MR23=63, INC=92, DEC=61
1134 16:33:56.256247
1135 16:33:56.256325 ----->DramcWriteLeveling(PI) begin...
1136 16:33:56.256408 ==
1137 16:33:56.256486 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 16:33:56.256563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 16:33:56.256639 ==
1140 16:33:56.256731 Write leveling (Byte 0): 30 => 30
1141 16:33:56.256812 Write leveling (Byte 1): 30 => 30
1142 16:33:56.256890 DramcWriteLeveling(PI) end<-----
1143 16:33:56.256966
1144 16:33:56.257044 ==
1145 16:33:56.257138 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 16:33:56.257220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 16:33:56.257298 ==
1148 16:33:56.257376 [Gating] SW mode calibration
1149 16:33:56.257457 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 16:33:56.257538 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 16:33:56.257617 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 16:33:56.257695 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 16:33:56.257772 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 16:33:56.257850 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 16:33:56.257933 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 16:33:56.258011 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 16:33:56.258089 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 16:33:56.258167 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 16:33:56.258244 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 16:33:56.258323 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 16:33:56.258405 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 16:33:56.258484 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 16:33:56.258566 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 16:33:56.258644 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 16:33:56.258724 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 16:33:56.258801 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 16:33:56.258878 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 16:33:56.258958 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 16:33:56.259039 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1170 16:33:56.259117 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 16:33:56.259194 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 16:33:56.259272 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 16:33:56.259349 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 16:33:56.259428 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 16:33:56.259508 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 16:33:56.259589 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 16:33:56.259675 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1178 16:33:56.259755 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1179 16:33:56.259832 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 16:33:56.259913 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 16:33:56.259993 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 16:33:56.260071 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 16:33:56.260159 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 16:33:56.260255 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
1185 16:33:56.260353 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
1186 16:33:56.260439 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1187 16:33:56.260519 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 16:33:56.260596 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 16:33:56.260683 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 16:33:56.260765 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 16:33:56.260846 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 16:33:56.260923 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1193 16:33:56.261000 0 11 8 | B1->B0 | 2d2d 4141 | 1 0 | (0 0) (0 0)
1194 16:33:56.261078 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1195 16:33:56.261155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 16:33:56.261233 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 16:33:56.261317 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 16:33:56.261402 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 16:33:56.261486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 16:33:56.261569 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1201 16:33:56.261856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 16:33:56.261949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 16:33:56.262034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 16:33:56.262121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 16:33:56.262207 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 16:33:56.262292 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 16:33:56.262377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 16:33:56.262462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 16:33:56.262545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 16:33:56.262629 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 16:33:56.262712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 16:33:56.262795 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 16:33:56.262876 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 16:33:56.262957 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 16:33:56.263038 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 16:33:56.263120 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 16:33:56.263205 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 16:33:56.263287 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 16:33:56.263369 Total UI for P1: 0, mck2ui 16
1220 16:33:56.263451 best dqsien dly found for B0: ( 0, 14, 8)
1221 16:33:56.263533 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 16:33:56.263615 Total UI for P1: 0, mck2ui 16
1223 16:33:56.263699 best dqsien dly found for B1: ( 0, 14, 10)
1224 16:33:56.263783 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 16:33:56.263868 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1226 16:33:56.263954
1227 16:33:56.264038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 16:33:56.264122 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1229 16:33:56.264209 [Gating] SW calibration Done
1230 16:33:56.264293 ==
1231 16:33:56.264377 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 16:33:56.264460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 16:33:56.264545 ==
1234 16:33:56.264628 RX Vref Scan: 0
1235 16:33:56.264721
1236 16:33:56.264803 RX Vref 0 -> 0, step: 1
1237 16:33:56.264885
1238 16:33:56.264964 RX Delay -130 -> 252, step: 16
1239 16:33:56.265042 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1240 16:33:56.265121 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 16:33:56.265203 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1242 16:33:56.265284 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1243 16:33:56.265377 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1244 16:33:56.265461 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1245 16:33:56.265544 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1246 16:33:56.265626 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1247 16:33:56.265709 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1248 16:33:56.265799 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1249 16:33:56.265883 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 16:33:56.265965 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1251 16:33:56.266047 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1252 16:33:56.266129 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1253 16:33:56.266212 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1254 16:33:56.266294 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1255 16:33:56.266377 ==
1256 16:33:56.266460 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 16:33:56.266554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 16:33:56.266638 ==
1259 16:33:56.266726 DQS Delay:
1260 16:33:56.266806 DQS0 = 0, DQS1 = 0
1261 16:33:56.266884 DQM Delay:
1262 16:33:56.266961 DQM0 = 81, DQM1 = 70
1263 16:33:56.267037 DQ Delay:
1264 16:33:56.267119 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1265 16:33:56.267202 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
1266 16:33:56.267279 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1267 16:33:56.267356 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1268 16:33:56.267432
1269 16:33:56.267508
1270 16:33:56.267584 ==
1271 16:33:56.267661 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 16:33:56.267738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 16:33:56.267819 ==
1274 16:33:56.267901
1275 16:33:56.267978
1276 16:33:56.268058 TX Vref Scan disable
1277 16:33:56.268141 == TX Byte 0 ==
1278 16:33:56.268220 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1279 16:33:56.268298 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1280 16:33:56.268374 == TX Byte 1 ==
1281 16:33:56.268451 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 16:33:56.268528 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 16:33:56.268604 ==
1284 16:33:56.268680 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 16:33:56.268731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 16:33:56.268782 ==
1287 16:33:56.268831 TX Vref=22, minBit 11, minWin=26, winSum=436
1288 16:33:56.268880 TX Vref=24, minBit 1, minWin=26, winSum=434
1289 16:33:56.268929 TX Vref=26, minBit 1, minWin=27, winSum=444
1290 16:33:56.268978 TX Vref=28, minBit 1, minWin=27, winSum=441
1291 16:33:56.269027 TX Vref=30, minBit 3, minWin=27, winSum=444
1292 16:33:56.269076 TX Vref=32, minBit 15, minWin=26, winSum=440
1293 16:33:56.269126 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 26
1294 16:33:56.269175
1295 16:33:56.269222 Final TX Range 1 Vref 26
1296 16:33:56.269270
1297 16:33:56.269318 ==
1298 16:33:56.269366 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 16:33:56.269418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 16:33:56.269473 ==
1301 16:33:56.269521
1302 16:33:56.269568
1303 16:33:56.269616 TX Vref Scan disable
1304 16:33:56.269664 == TX Byte 0 ==
1305 16:33:56.269712 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1306 16:33:56.269760 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1307 16:33:56.269807 == TX Byte 1 ==
1308 16:33:56.269855 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 16:33:56.269903 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 16:33:56.269950
1311 16:33:56.269997 [DATLAT]
1312 16:33:56.270044 Freq=800, CH0 RK1
1313 16:33:56.270092
1314 16:33:56.270139 DATLAT Default: 0xa
1315 16:33:56.270186 0, 0xFFFF, sum = 0
1316 16:33:56.270234 1, 0xFFFF, sum = 0
1317 16:33:56.270283 2, 0xFFFF, sum = 0
1318 16:33:56.270330 3, 0xFFFF, sum = 0
1319 16:33:56.270378 4, 0xFFFF, sum = 0
1320 16:33:56.270426 5, 0xFFFF, sum = 0
1321 16:33:56.270474 6, 0xFFFF, sum = 0
1322 16:33:56.270542 7, 0xFFFF, sum = 0
1323 16:33:56.270602 8, 0xFFFF, sum = 0
1324 16:33:56.270657 9, 0x0, sum = 1
1325 16:33:56.270739 10, 0x0, sum = 2
1326 16:33:56.270822 11, 0x0, sum = 3
1327 16:33:56.270903 12, 0x0, sum = 4
1328 16:33:56.270985 best_step = 10
1329 16:33:56.271065
1330 16:33:56.271154 ==
1331 16:33:56.271237 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 16:33:56.271522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 16:33:56.271607 ==
1334 16:33:56.271693 RX Vref Scan: 0
1335 16:33:56.271774
1336 16:33:56.271854 RX Vref 0 -> 0, step: 1
1337 16:33:56.271934
1338 16:33:56.272013 RX Delay -111 -> 252, step: 8
1339 16:33:56.272095 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1340 16:33:56.272176 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1341 16:33:56.272266 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1342 16:33:56.272346 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1343 16:33:56.272422 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1344 16:33:56.272499 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1345 16:33:56.272576 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1346 16:33:56.272662 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1347 16:33:56.272741 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1348 16:33:56.272817 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1349 16:33:56.272896 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 16:33:56.272981 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1351 16:33:56.273064 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1352 16:33:56.273147 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1353 16:33:56.273229 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 16:33:56.273312 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1355 16:33:56.273393 ==
1356 16:33:56.273473 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 16:33:56.273554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 16:33:56.273634 ==
1359 16:33:56.273715 DQS Delay:
1360 16:33:56.273796 DQS0 = 0, DQS1 = 0
1361 16:33:56.273877 DQM Delay:
1362 16:33:56.273956 DQM0 = 79, DQM1 = 69
1363 16:33:56.274035 DQ Delay:
1364 16:33:56.274115 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1365 16:33:56.274197 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1366 16:33:56.274278 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1367 16:33:56.274360 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1368 16:33:56.274441
1369 16:33:56.274523
1370 16:33:56.274606 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1371 16:33:56.274691 CH0 RK1: MR19=606, MR18=4D28
1372 16:33:56.274775 CH0_RK1: MR19=0x606, MR18=0x4D28, DQSOSC=390, MR23=63, INC=97, DEC=64
1373 16:33:56.274854 [RxdqsGatingPostProcess] freq 800
1374 16:33:56.274931 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 16:33:56.275008 Pre-setting of DQS Precalculation
1376 16:33:56.275092 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 16:33:56.275174 ==
1378 16:33:56.275264 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 16:33:56.275348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 16:33:56.275429 ==
1381 16:33:56.275512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 16:33:56.275596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 16:33:56.275679 [CA 0] Center 36 (6~66) winsize 61
1384 16:33:56.275762 [CA 1] Center 36 (6~67) winsize 62
1385 16:33:56.275844 [CA 2] Center 34 (4~65) winsize 62
1386 16:33:56.275927 [CA 3] Center 34 (4~64) winsize 61
1387 16:33:56.276009 [CA 4] Center 34 (4~65) winsize 62
1388 16:33:56.276092 [CA 5] Center 34 (4~64) winsize 61
1389 16:33:56.276173
1390 16:33:56.276256 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 16:33:56.276338
1392 16:33:56.276420 [CATrainingPosCal] consider 1 rank data
1393 16:33:56.276504 u2DelayCellTimex100 = 270/100 ps
1394 16:33:56.276586 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1395 16:33:56.276679 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 16:33:56.276761 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 16:33:56.276843 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 16:33:56.276933 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 16:33:56.277013 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 16:33:56.277089
1401 16:33:56.277165 CA PerBit enable=1, Macro0, CA PI delay=34
1402 16:33:56.277241
1403 16:33:56.277317 [CBTSetCACLKResult] CA Dly = 34
1404 16:33:56.277393 CS Dly: 5 (0~36)
1405 16:33:56.277479 ==
1406 16:33:56.277558 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 16:33:56.277635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 16:33:56.277711 ==
1409 16:33:56.277788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 16:33:56.277866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 16:33:56.277942 [CA 0] Center 36 (6~67) winsize 62
1412 16:33:56.278018 [CA 1] Center 36 (6~67) winsize 62
1413 16:33:56.278094 [CA 2] Center 34 (4~65) winsize 62
1414 16:33:56.278170 [CA 3] Center 33 (3~64) winsize 62
1415 16:33:56.278246 [CA 4] Center 34 (4~65) winsize 62
1416 16:33:56.278323 [CA 5] Center 33 (3~64) winsize 62
1417 16:33:56.278399
1418 16:33:56.278475 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 16:33:56.278550
1420 16:33:56.278626 [CATrainingPosCal] consider 2 rank data
1421 16:33:56.278702 u2DelayCellTimex100 = 270/100 ps
1422 16:33:56.278778 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1423 16:33:56.278855 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 16:33:56.278931 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 16:33:56.279007 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 16:33:56.279094 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 16:33:56.279173 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 16:33:56.279249
1429 16:33:56.279326 CA PerBit enable=1, Macro0, CA PI delay=34
1430 16:33:56.279402
1431 16:33:56.279477 [CBTSetCACLKResult] CA Dly = 34
1432 16:33:56.279561 CS Dly: 6 (0~38)
1433 16:33:56.279640
1434 16:33:56.279716 ----->DramcWriteLeveling(PI) begin...
1435 16:33:56.279794 ==
1436 16:33:56.279871 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 16:33:56.279948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 16:33:56.280024 ==
1439 16:33:56.280101 Write leveling (Byte 0): 26 => 26
1440 16:33:56.280186 Write leveling (Byte 1): 30 => 30
1441 16:33:56.280265 DramcWriteLeveling(PI) end<-----
1442 16:33:56.280340
1443 16:33:56.280416 ==
1444 16:33:56.280492 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 16:33:56.280569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 16:33:56.280651 ==
1447 16:33:56.280704 [Gating] SW mode calibration
1448 16:33:56.280753 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 16:33:56.280803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 16:33:56.280852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 16:33:56.280900 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1452 16:33:56.280948 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 16:33:56.281196 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 16:33:56.281256 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 16:33:56.281307 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 16:33:56.281356 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 16:33:56.281404 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 16:33:56.281453 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 16:33:56.281501 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 16:33:56.281549 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 16:33:56.281597 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 16:33:56.281644 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 16:33:56.281692 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 16:33:56.281740 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 16:33:56.281788 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 16:33:56.281835 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 16:33:56.281883 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 16:33:56.281931 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 16:33:56.281978 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 16:33:56.282025 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 16:33:56.282074 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 16:33:56.282121 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 16:33:56.282169 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 16:33:56.282216 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 16:33:56.282263 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 16:33:56.282311 0 9 8 | B1->B0 | 2828 2929 | 1 1 | (1 1) (1 1)
1477 16:33:56.282358 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 16:33:56.282405 0 9 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1479 16:33:56.282453 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 16:33:56.282501 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 16:33:56.282548 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 16:33:56.282596 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 16:33:56.282643 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1484 16:33:56.282691 0 10 8 | B1->B0 | 2828 2d2d | 1 0 | (1 0) (1 0)
1485 16:33:56.282739 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 16:33:56.282786 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 16:33:56.282833 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 16:33:56.282881 0 10 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1489 16:33:56.282929 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 16:33:56.282977 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 16:33:56.283047 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 16:33:56.283127 0 11 8 | B1->B0 | 3434 3535 | 1 0 | (0 0) (0 0)
1493 16:33:56.283204 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 16:33:56.283291 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 16:33:56.283370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 16:33:56.283447 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 16:33:56.283535 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 16:33:56.283618 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 16:33:56.283699 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 16:33:56.283776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 16:33:56.283852 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 16:33:56.283929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 16:33:56.284014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 16:33:56.284094 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 16:33:56.284171 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 16:33:56.284248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 16:33:56.284324 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 16:33:56.284400 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 16:33:56.284477 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 16:33:56.284553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 16:33:56.284631 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 16:33:56.284708 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 16:33:56.284785 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 16:33:56.284862 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 16:33:56.284939 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 16:33:56.285016 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 16:33:56.285099 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 16:33:56.285183 Total UI for P1: 0, mck2ui 16
1519 16:33:56.285261 best dqsien dly found for B0: ( 0, 14, 8)
1520 16:33:56.285339 Total UI for P1: 0, mck2ui 16
1521 16:33:56.285419 best dqsien dly found for B1: ( 0, 14, 8)
1522 16:33:56.285512 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1523 16:33:56.285593 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1524 16:33:56.285672
1525 16:33:56.285760 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1526 16:33:56.285839 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 16:33:56.285915 [Gating] SW calibration Done
1528 16:33:56.285991 ==
1529 16:33:56.286067 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 16:33:56.286144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 16:33:56.286220 ==
1532 16:33:56.286301 RX Vref Scan: 0
1533 16:33:56.286385
1534 16:33:56.286461 RX Vref 0 -> 0, step: 1
1535 16:33:56.286537
1536 16:33:56.286617 RX Delay -130 -> 252, step: 16
1537 16:33:56.286693 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 16:33:56.286782 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 16:33:56.286861 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 16:33:56.286948 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 16:33:56.287028 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 16:33:56.287105 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 16:33:56.287376 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 16:33:56.287457 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 16:33:56.287549 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 16:33:56.287646 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 16:33:56.287742 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 16:33:56.287838 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1549 16:33:56.287933 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1550 16:33:56.288028 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1551 16:33:56.288123 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1552 16:33:56.288218 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1553 16:33:56.288312 ==
1554 16:33:56.288407 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 16:33:56.288503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 16:33:56.288595 ==
1557 16:33:56.288690 DQS Delay:
1558 16:33:56.288746 DQS0 = 0, DQS1 = 0
1559 16:33:56.288799 DQM Delay:
1560 16:33:56.288876 DQM0 = 81, DQM1 = 71
1561 16:33:56.288957 DQ Delay:
1562 16:33:56.289008 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1563 16:33:56.289056 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 16:33:56.289104 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1565 16:33:56.289153 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1566 16:33:56.289201
1567 16:33:56.289249
1568 16:33:56.289295 ==
1569 16:33:56.289343 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 16:33:56.289393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 16:33:56.289442 ==
1572 16:33:56.289492
1573 16:33:56.289539
1574 16:33:56.289586 TX Vref Scan disable
1575 16:33:56.289633 == TX Byte 0 ==
1576 16:33:56.289681 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 16:33:56.289738 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 16:33:56.289793 == TX Byte 1 ==
1579 16:33:56.289840 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 16:33:56.289888 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 16:33:56.289967 ==
1582 16:33:56.290034 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 16:33:56.290095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 16:33:56.290177 ==
1585 16:33:56.290266 TX Vref=22, minBit 5, minWin=27, winSum=444
1586 16:33:56.290345 TX Vref=24, minBit 1, minWin=27, winSum=446
1587 16:33:56.290443 TX Vref=26, minBit 1, minWin=27, winSum=446
1588 16:33:56.290524 TX Vref=28, minBit 5, minWin=27, winSum=450
1589 16:33:56.290601 TX Vref=30, minBit 4, minWin=28, winSum=454
1590 16:33:56.290683 TX Vref=32, minBit 5, minWin=27, winSum=451
1591 16:33:56.290762 [TxChooseVref] Worse bit 4, Min win 28, Win sum 454, Final Vref 30
1592 16:33:56.290838
1593 16:33:56.290914 Final TX Range 1 Vref 30
1594 16:33:56.290989
1595 16:33:56.291064 ==
1596 16:33:56.291140 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 16:33:56.291218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 16:33:56.291294 ==
1599 16:33:56.291369
1600 16:33:56.291444
1601 16:33:56.291520 TX Vref Scan disable
1602 16:33:56.291596 == TX Byte 0 ==
1603 16:33:56.291673 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 16:33:56.291751 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 16:33:56.291827 == TX Byte 1 ==
1606 16:33:56.291904 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 16:33:56.291980 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 16:33:56.292055
1609 16:33:56.292130 [DATLAT]
1610 16:33:56.292206 Freq=800, CH1 RK0
1611 16:33:56.292281
1612 16:33:56.292357 DATLAT Default: 0xa
1613 16:33:56.292433 0, 0xFFFF, sum = 0
1614 16:33:56.292511 1, 0xFFFF, sum = 0
1615 16:33:56.292589 2, 0xFFFF, sum = 0
1616 16:33:56.292676 3, 0xFFFF, sum = 0
1617 16:33:56.292728 4, 0xFFFF, sum = 0
1618 16:33:56.292778 5, 0xFFFF, sum = 0
1619 16:33:56.292827 6, 0xFFFF, sum = 0
1620 16:33:56.292876 7, 0xFFFF, sum = 0
1621 16:33:56.292924 8, 0xFFFF, sum = 0
1622 16:33:56.292998 9, 0x0, sum = 1
1623 16:33:56.293052 10, 0x0, sum = 2
1624 16:33:56.293101 11, 0x0, sum = 3
1625 16:33:56.293150 12, 0x0, sum = 4
1626 16:33:56.293199 best_step = 10
1627 16:33:56.293247
1628 16:33:56.293293 ==
1629 16:33:56.293341 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 16:33:56.293389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 16:33:56.293437 ==
1632 16:33:56.293484 RX Vref Scan: 1
1633 16:33:56.293532
1634 16:33:56.293579 Set Vref Range= 32 -> 127
1635 16:33:56.293631
1636 16:33:56.293698 RX Vref 32 -> 127, step: 1
1637 16:33:56.293747
1638 16:33:56.293794 RX Delay -111 -> 252, step: 8
1639 16:33:56.293842
1640 16:33:56.293889 Set Vref, RX VrefLevel [Byte0]: 32
1641 16:33:56.293937 [Byte1]: 32
1642 16:33:56.293984
1643 16:33:56.294030 Set Vref, RX VrefLevel [Byte0]: 33
1644 16:33:56.294078 [Byte1]: 33
1645 16:33:56.294126
1646 16:33:56.294174 Set Vref, RX VrefLevel [Byte0]: 34
1647 16:33:56.294245 [Byte1]: 34
1648 16:33:56.294295
1649 16:33:56.294343 Set Vref, RX VrefLevel [Byte0]: 35
1650 16:33:56.294392 [Byte1]: 35
1651 16:33:56.294439
1652 16:33:56.294486 Set Vref, RX VrefLevel [Byte0]: 36
1653 16:33:56.294534 [Byte1]: 36
1654 16:33:56.294582
1655 16:33:56.294629 Set Vref, RX VrefLevel [Byte0]: 37
1656 16:33:56.294676 [Byte1]: 37
1657 16:33:56.294723
1658 16:33:56.294771 Set Vref, RX VrefLevel [Byte0]: 38
1659 16:33:56.294829 [Byte1]: 38
1660 16:33:56.294893
1661 16:33:56.294977 Set Vref, RX VrefLevel [Byte0]: 39
1662 16:33:56.295053 [Byte1]: 39
1663 16:33:56.295128
1664 16:33:56.295204 Set Vref, RX VrefLevel [Byte0]: 40
1665 16:33:56.295280 [Byte1]: 40
1666 16:33:56.295355
1667 16:33:56.295431 Set Vref, RX VrefLevel [Byte0]: 41
1668 16:33:56.295509 [Byte1]: 41
1669 16:33:56.295595
1670 16:33:56.295672 Set Vref, RX VrefLevel [Byte0]: 42
1671 16:33:56.295748 [Byte1]: 42
1672 16:33:56.295823
1673 16:33:56.295899 Set Vref, RX VrefLevel [Byte0]: 43
1674 16:33:56.295975 [Byte1]: 43
1675 16:33:56.296057
1676 16:33:56.296135 Set Vref, RX VrefLevel [Byte0]: 44
1677 16:33:56.296222 [Byte1]: 44
1678 16:33:56.296299
1679 16:33:56.296375 Set Vref, RX VrefLevel [Byte0]: 45
1680 16:33:56.296451 [Byte1]: 45
1681 16:33:56.296527
1682 16:33:56.296603 Set Vref, RX VrefLevel [Byte0]: 46
1683 16:33:56.296679 [Byte1]: 46
1684 16:33:56.296729
1685 16:33:56.296799 Set Vref, RX VrefLevel [Byte0]: 47
1686 16:33:56.296851 [Byte1]: 47
1687 16:33:56.296899
1688 16:33:56.296947 Set Vref, RX VrefLevel [Byte0]: 48
1689 16:33:56.296996 [Byte1]: 48
1690 16:33:56.297043
1691 16:33:56.297091 Set Vref, RX VrefLevel [Byte0]: 49
1692 16:33:56.297138 [Byte1]: 49
1693 16:33:56.297185
1694 16:33:56.297232 Set Vref, RX VrefLevel [Byte0]: 50
1695 16:33:56.297280 [Byte1]: 50
1696 16:33:56.297327
1697 16:33:56.297382 Set Vref, RX VrefLevel [Byte0]: 51
1698 16:33:56.297443 [Byte1]: 51
1699 16:33:56.297492
1700 16:33:56.297539 Set Vref, RX VrefLevel [Byte0]: 52
1701 16:33:56.297587 [Byte1]: 52
1702 16:33:56.297634
1703 16:33:56.297879 Set Vref, RX VrefLevel [Byte0]: 53
1704 16:33:56.297933 [Byte1]: 53
1705 16:33:56.297982
1706 16:33:56.298057 Set Vref, RX VrefLevel [Byte0]: 54
1707 16:33:56.298108 [Byte1]: 54
1708 16:33:56.298156
1709 16:33:56.298204 Set Vref, RX VrefLevel [Byte0]: 55
1710 16:33:56.298252 [Byte1]: 55
1711 16:33:56.298300
1712 16:33:56.298348 Set Vref, RX VrefLevel [Byte0]: 56
1713 16:33:56.298396 [Byte1]: 56
1714 16:33:56.298443
1715 16:33:56.298490 Set Vref, RX VrefLevel [Byte0]: 57
1716 16:33:56.298538 [Byte1]: 57
1717 16:33:56.298586
1718 16:33:56.298640 Set Vref, RX VrefLevel [Byte0]: 58
1719 16:33:56.298702 [Byte1]: 58
1720 16:33:56.298750
1721 16:33:56.298797 Set Vref, RX VrefLevel [Byte0]: 59
1722 16:33:56.298845 [Byte1]: 59
1723 16:33:56.298892
1724 16:33:56.298940 Set Vref, RX VrefLevel [Byte0]: 60
1725 16:33:56.298987 [Byte1]: 60
1726 16:33:56.299034
1727 16:33:56.299081 Set Vref, RX VrefLevel [Byte0]: 61
1728 16:33:56.299131 [Byte1]: 61
1729 16:33:56.299179
1730 16:33:56.299241 Set Vref, RX VrefLevel [Byte0]: 62
1731 16:33:56.299302 [Byte1]: 62
1732 16:33:56.299350
1733 16:33:56.299397 Set Vref, RX VrefLevel [Byte0]: 63
1734 16:33:56.299445 [Byte1]: 63
1735 16:33:56.299492
1736 16:33:56.299539 Set Vref, RX VrefLevel [Byte0]: 64
1737 16:33:56.299586 [Byte1]: 64
1738 16:33:56.299633
1739 16:33:56.299679 Set Vref, RX VrefLevel [Byte0]: 65
1740 16:33:56.299726 [Byte1]: 65
1741 16:33:56.299774
1742 16:33:56.299826 Set Vref, RX VrefLevel [Byte0]: 66
1743 16:33:56.299911 [Byte1]: 66
1744 16:33:56.299987
1745 16:33:56.300063 Set Vref, RX VrefLevel [Byte0]: 67
1746 16:33:56.300139 [Byte1]: 67
1747 16:33:56.300213
1748 16:33:56.300289 Set Vref, RX VrefLevel [Byte0]: 68
1749 16:33:56.300364 [Byte1]: 68
1750 16:33:56.300439
1751 16:33:56.300525 Set Vref, RX VrefLevel [Byte0]: 69
1752 16:33:56.300605 [Byte1]: 69
1753 16:33:56.300695
1754 16:33:56.300772 Set Vref, RX VrefLevel [Byte0]: 70
1755 16:33:56.300848 [Byte1]: 70
1756 16:33:56.300923
1757 16:33:56.300999 Set Vref, RX VrefLevel [Byte0]: 71
1758 16:33:56.301083 [Byte1]: 71
1759 16:33:56.301175
1760 16:33:56.301264 Set Vref, RX VrefLevel [Byte0]: 72
1761 16:33:56.301343 [Byte1]: 72
1762 16:33:56.301418
1763 16:33:56.301494 Set Vref, RX VrefLevel [Byte0]: 73
1764 16:33:56.301570 [Byte1]: 73
1765 16:33:56.301646
1766 16:33:56.301722 Set Vref, RX VrefLevel [Byte0]: 74
1767 16:33:56.301808 [Byte1]: 74
1768 16:33:56.301886
1769 16:33:56.301962 Set Vref, RX VrefLevel [Byte0]: 75
1770 16:33:56.302038 [Byte1]: 75
1771 16:33:56.302113
1772 16:33:56.302189 Set Vref, RX VrefLevel [Byte0]: 76
1773 16:33:56.302267 [Byte1]: 76
1774 16:33:56.302343
1775 16:33:56.302428 Final RX Vref Byte 0 = 57 to rank0
1776 16:33:56.302507 Final RX Vref Byte 1 = 57 to rank0
1777 16:33:56.302583 Final RX Vref Byte 0 = 57 to rank1
1778 16:33:56.302660 Final RX Vref Byte 1 = 57 to rank1==
1779 16:33:56.302738 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 16:33:56.302818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 16:33:56.302895 ==
1782 16:33:56.302972 DQS Delay:
1783 16:33:56.303057 DQS0 = 0, DQS1 = 0
1784 16:33:56.303139 DQM Delay:
1785 16:33:56.303222 DQM0 = 81, DQM1 = 71
1786 16:33:56.303299 DQ Delay:
1787 16:33:56.303375 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1788 16:33:56.303451 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1789 16:33:56.303527 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1790 16:33:56.303610 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1791 16:33:56.303688
1792 16:33:56.303778
1793 16:33:56.303861 [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1794 16:33:56.303954 CH1 RK0: MR19=606, MR18=101A
1795 16:33:56.304039 CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60
1796 16:33:56.304122
1797 16:33:56.304200 ----->DramcWriteLeveling(PI) begin...
1798 16:33:56.304277 ==
1799 16:33:56.304371 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 16:33:56.304456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 16:33:56.304537 ==
1802 16:33:56.304614 Write leveling (Byte 0): 28 => 28
1803 16:33:56.304699 Write leveling (Byte 1): 29 => 29
1804 16:33:56.304776 DramcWriteLeveling(PI) end<-----
1805 16:33:56.304851
1806 16:33:56.304915 ==
1807 16:33:56.304998 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 16:33:56.305076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 16:33:56.305152 ==
1810 16:33:56.305228 [Gating] SW mode calibration
1811 16:33:56.305306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 16:33:56.305384 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 16:33:56.305462 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 16:33:56.305544 0 6 4 | B1->B0 | 2323 2322 | 0 1 | (1 0) (1 0)
1815 16:33:56.305604 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 16:33:56.305653 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 16:33:56.305701 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 16:33:56.305750 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 16:33:56.305798 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 16:33:56.305846 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 16:33:56.305894 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 16:33:56.305941 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 16:33:56.305989 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 16:33:56.306037 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 16:33:56.306090 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 16:33:56.306141 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 16:33:56.306190 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 16:33:56.306260 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 16:33:56.306310 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1830 16:33:56.306358 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1831 16:33:56.306412 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1832 16:33:56.306463 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 16:33:56.306511 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 16:33:56.306558 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 16:33:56.306804 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 16:33:56.306897 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 16:33:56.306976 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 16:33:56.307053 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1839 16:33:56.307131 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1840 16:33:56.307208 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 16:33:56.307285 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 16:33:56.307379 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 16:33:56.307478 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 16:33:56.307574 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 16:33:56.307670 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1846 16:33:56.307767 0 10 4 | B1->B0 | 3333 2b2b | 1 1 | (1 1) (1 0)
1847 16:33:56.307861 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 16:33:56.307960 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 16:33:56.308058 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 16:33:56.308143 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 16:33:56.308226 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 16:33:56.308308 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 16:33:56.308386 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1854 16:33:56.308464 0 11 4 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
1855 16:33:56.308541 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1856 16:33:56.308624 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 16:33:56.308712 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 16:33:56.308786 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 16:33:56.308853 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 16:33:56.308909 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 16:33:56.308958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 16:33:56.309007 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 16:33:56.309056 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 16:33:56.309103 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 16:33:56.309154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 16:33:56.309210 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 16:33:56.309258 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 16:33:56.309311 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 16:33:56.309361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 16:33:56.309428 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 16:33:56.309508 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 16:33:56.309585 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 16:33:56.309644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 16:33:56.309697 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 16:33:56.309745 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 16:33:56.309800 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 16:33:56.309849 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 16:33:56.309897 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 16:33:56.309949 Total UI for P1: 0, mck2ui 16
1880 16:33:56.310006 best dqsien dly found for B0: ( 0, 14, 2)
1881 16:33:56.310090 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1882 16:33:56.310169 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 16:33:56.310246 Total UI for P1: 0, mck2ui 16
1884 16:33:56.310323 best dqsien dly found for B1: ( 0, 14, 6)
1885 16:33:56.310400 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1886 16:33:56.310479 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1887 16:33:56.310556
1888 16:33:56.310635 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1889 16:33:56.310711 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 16:33:56.310791 [Gating] SW calibration Done
1891 16:33:56.310869 ==
1892 16:33:56.310954 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 16:33:56.311038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 16:33:56.311124 ==
1895 16:33:56.311205 RX Vref Scan: 0
1896 16:33:56.311286
1897 16:33:56.311364 RX Vref 0 -> 0, step: 1
1898 16:33:56.311442
1899 16:33:56.311525 RX Delay -130 -> 252, step: 16
1900 16:33:56.311605 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1901 16:33:56.311685 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1902 16:33:56.311762 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1903 16:33:56.311838 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1904 16:33:56.311918 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1905 16:33:56.311995 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1906 16:33:56.312075 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1907 16:33:56.312154 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1908 16:33:56.312232 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1909 16:33:56.312308 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1910 16:33:56.312385 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1911 16:33:56.312464 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1912 16:33:56.312546 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1913 16:33:56.312631 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1914 16:33:56.312695 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1915 16:33:56.312747 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1916 16:33:56.312795 ==
1917 16:33:56.470808 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 16:33:56.470932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 16:33:56.470994 ==
1920 16:33:56.471048 DQS Delay:
1921 16:33:56.471100 DQS0 = 0, DQS1 = 0
1922 16:33:56.471151 DQM Delay:
1923 16:33:56.471201 DQM0 = 79, DQM1 = 74
1924 16:33:56.471250 DQ Delay:
1925 16:33:56.471299 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1926 16:33:56.471348 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1927 16:33:56.471397 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1928 16:33:56.471445 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1929 16:33:56.471493
1930 16:33:56.471565
1931 16:33:56.471614 ==
1932 16:33:56.471663 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 16:33:56.471714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 16:33:56.471763 ==
1935 16:33:56.471811
1936 16:33:56.471858
1937 16:33:56.471923 TX Vref Scan disable
1938 16:33:56.471977 == TX Byte 0 ==
1939 16:33:56.472304 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1940 16:33:56.472407 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1941 16:33:56.472490 == TX Byte 1 ==
1942 16:33:56.472578 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1943 16:33:56.472664 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1944 16:33:56.472717 ==
1945 16:33:56.472767 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 16:33:56.472816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 16:33:56.472951 ==
1948 16:33:56.473059 TX Vref=22, minBit 1, minWin=27, winSum=447
1949 16:33:56.473150 TX Vref=24, minBit 0, minWin=28, winSum=451
1950 16:33:56.473203 TX Vref=26, minBit 0, minWin=28, winSum=457
1951 16:33:56.473253 TX Vref=28, minBit 0, minWin=28, winSum=459
1952 16:33:56.473302 TX Vref=30, minBit 5, minWin=27, winSum=458
1953 16:33:56.473350 TX Vref=32, minBit 5, minWin=27, winSum=458
1954 16:33:56.473398 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1955 16:33:56.473447
1956 16:33:56.473495 Final TX Range 1 Vref 28
1957 16:33:56.473543
1958 16:33:56.473590 ==
1959 16:33:56.473637 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 16:33:56.473685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 16:33:56.473733 ==
1962 16:33:56.473781
1963 16:33:56.473827
1964 16:33:56.473874 TX Vref Scan disable
1965 16:33:56.473921 == TX Byte 0 ==
1966 16:33:56.473969 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1967 16:33:56.474017 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1968 16:33:56.474064 == TX Byte 1 ==
1969 16:33:56.474110 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1970 16:33:56.474158 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1971 16:33:56.474206
1972 16:33:56.474252 [DATLAT]
1973 16:33:56.474299 Freq=800, CH1 RK1
1974 16:33:56.474347
1975 16:33:56.474402 DATLAT Default: 0xa
1976 16:33:56.474464 0, 0xFFFF, sum = 0
1977 16:33:56.474519 1, 0xFFFF, sum = 0
1978 16:33:56.474568 2, 0xFFFF, sum = 0
1979 16:33:56.474617 3, 0xFFFF, sum = 0
1980 16:33:56.474665 4, 0xFFFF, sum = 0
1981 16:33:56.474713 5, 0xFFFF, sum = 0
1982 16:33:56.474762 6, 0xFFFF, sum = 0
1983 16:33:56.474810 7, 0xFFFF, sum = 0
1984 16:33:56.474858 8, 0xFFFF, sum = 0
1985 16:33:56.474907 9, 0x0, sum = 1
1986 16:33:56.474956 10, 0x0, sum = 2
1987 16:33:56.475004 11, 0x0, sum = 3
1988 16:33:56.475051 12, 0x0, sum = 4
1989 16:33:56.475100 best_step = 10
1990 16:33:56.475148
1991 16:33:56.475194 ==
1992 16:33:56.475242 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 16:33:56.475290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 16:33:56.475338 ==
1995 16:33:56.475384 RX Vref Scan: 0
1996 16:33:56.475431
1997 16:33:56.475477 RX Vref 0 -> 0, step: 1
1998 16:33:56.475551
1999 16:33:56.475628 RX Delay -95 -> 252, step: 8
2000 16:33:56.475705 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2001 16:33:56.475782 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2002 16:33:56.475858 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2003 16:33:56.475935 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2004 16:33:56.476011 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2005 16:33:56.476088 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2006 16:33:56.476164 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2007 16:33:56.476241 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2008 16:33:56.476317 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2009 16:33:56.476394 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2010 16:33:56.476470 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2011 16:33:56.476547 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2012 16:33:56.476624 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2013 16:33:56.476696 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2014 16:33:56.476746 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2015 16:33:56.476794 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2016 16:33:56.476842 ==
2017 16:33:56.476890 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 16:33:56.476938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 16:33:56.476985 ==
2020 16:33:56.477033 DQS Delay:
2021 16:33:56.477080 DQS0 = 0, DQS1 = 0
2022 16:33:56.477127 DQM Delay:
2023 16:33:56.477175 DQM0 = 77, DQM1 = 74
2024 16:33:56.477222 DQ Delay:
2025 16:33:56.477268 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2026 16:33:56.477316 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2027 16:33:56.477363 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2028 16:33:56.477410 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2029 16:33:56.477457
2030 16:33:56.477504
2031 16:33:56.477552 [DQSOSCAuto] RK1, (LSB)MR18= 0x233b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2032 16:33:56.477601 CH1 RK1: MR19=606, MR18=233B
2033 16:33:56.477648 CH1_RK1: MR19=0x606, MR18=0x233B, DQSOSC=394, MR23=63, INC=95, DEC=63
2034 16:33:56.477697 [RxdqsGatingPostProcess] freq 800
2035 16:33:56.477766 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 16:33:56.477819 Pre-setting of DQS Precalculation
2037 16:33:56.477870 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 16:33:56.477920 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 16:33:56.477969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 16:33:56.478017
2041 16:33:56.478064
2042 16:33:56.478111 [Calibration Summary] 1600 Mbps
2043 16:33:56.478159 CH 0, Rank 0
2044 16:33:56.478220 SW Impedance : PASS
2045 16:33:56.478278 DUTY Scan : NO K
2046 16:33:56.478330 ZQ Calibration : PASS
2047 16:33:56.478379 Jitter Meter : NO K
2048 16:33:56.478427 CBT Training : PASS
2049 16:33:56.478475 Write leveling : PASS
2050 16:33:56.478524 RX DQS gating : PASS
2051 16:33:56.478572 RX DQ/DQS(RDDQC) : PASS
2052 16:33:56.478619 TX DQ/DQS : PASS
2053 16:33:56.478667 RX DATLAT : PASS
2054 16:33:56.478716 RX DQ/DQS(Engine): PASS
2055 16:33:56.478764 TX OE : NO K
2056 16:33:56.478812 All Pass.
2057 16:33:56.478859
2058 16:33:56.478906 CH 0, Rank 1
2059 16:33:56.478954 SW Impedance : PASS
2060 16:33:56.479024 DUTY Scan : NO K
2061 16:33:56.479077 ZQ Calibration : PASS
2062 16:33:56.479155 Jitter Meter : NO K
2063 16:33:56.479231 CBT Training : PASS
2064 16:33:56.479308 Write leveling : PASS
2065 16:33:56.479384 RX DQS gating : PASS
2066 16:33:56.479467 RX DQ/DQS(RDDQC) : PASS
2067 16:33:56.479550 TX DQ/DQS : PASS
2068 16:33:56.479631 RX DATLAT : PASS
2069 16:33:56.479712 RX DQ/DQS(Engine): PASS
2070 16:33:56.479789 TX OE : NO K
2071 16:33:56.479874 All Pass.
2072 16:33:56.480027
2073 16:33:56.480118 CH 1, Rank 0
2074 16:33:56.480209 SW Impedance : PASS
2075 16:33:56.480293 DUTY Scan : NO K
2076 16:33:56.480382 ZQ Calibration : PASS
2077 16:33:56.480528 Jitter Meter : NO K
2078 16:33:56.480640 CBT Training : PASS
2079 16:33:56.480738 Write leveling : PASS
2080 16:33:56.480817 RX DQS gating : PASS
2081 16:33:56.480893 RX DQ/DQS(RDDQC) : PASS
2082 16:33:56.481018 TX DQ/DQS : PASS
2083 16:33:56.481156 RX DATLAT : PASS
2084 16:33:56.481249 RX DQ/DQS(Engine): PASS
2085 16:33:56.481530 TX OE : NO K
2086 16:33:56.481611 All Pass.
2087 16:33:56.481693
2088 16:33:56.481770 CH 1, Rank 1
2089 16:33:56.481847 SW Impedance : PASS
2090 16:33:56.481924 DUTY Scan : NO K
2091 16:33:56.482000 ZQ Calibration : PASS
2092 16:33:56.482072 Jitter Meter : NO K
2093 16:33:56.482128 CBT Training : PASS
2094 16:33:56.482205 Write leveling : PASS
2095 16:33:56.482281 RX DQS gating : PASS
2096 16:33:56.482357 RX DQ/DQS(RDDQC) : PASS
2097 16:33:56.482434 TX DQ/DQS : PASS
2098 16:33:56.482510 RX DATLAT : PASS
2099 16:33:56.482587 RX DQ/DQS(Engine): PASS
2100 16:33:56.482663 TX OE : NO K
2101 16:33:56.482743 All Pass.
2102 16:33:56.482821
2103 16:33:56.482897 DramC Write-DBI off
2104 16:33:56.482974 PER_BANK_REFRESH: Hybrid Mode
2105 16:33:56.483050 TX_TRACKING: ON
2106 16:33:56.483127 [GetDramInforAfterCalByMRR] Vendor 6.
2107 16:33:56.483205 [GetDramInforAfterCalByMRR] Revision 606.
2108 16:33:56.483282 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 16:33:56.483358 MR0 0x3b3b
2110 16:33:56.483443 MR8 0x5151
2111 16:33:56.483521 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 16:33:56.483598
2113 16:33:56.483674 MR0 0x3b3b
2114 16:33:56.483750 MR8 0x5151
2115 16:33:56.483832 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 16:33:56.483909
2117 16:33:56.483987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 16:33:56.484066 [FAST_K] Save calibration result to emmc
2119 16:33:56.484143 [FAST_K] Save calibration result to emmc
2120 16:33:56.484220 dram_init: config_dvfs: 1
2121 16:33:56.484297 dramc_set_vcore_voltage set vcore to 662500
2122 16:33:56.484374 Read voltage for 1200, 2
2123 16:33:56.484450 Vio18 = 0
2124 16:33:56.484525 Vcore = 662500
2125 16:33:56.484601 Vdram = 0
2126 16:33:56.484679 Vddq = 0
2127 16:33:56.484729 Vmddr = 0
2128 16:33:56.484778 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 16:33:56.484828 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 16:33:56.484877 MEM_TYPE=3, freq_sel=15
2131 16:33:56.484926 sv_algorithm_assistance_LP4_1600
2132 16:33:56.484974 ============ PULL DRAM RESETB DOWN ============
2133 16:33:56.485023 ========== PULL DRAM RESETB DOWN end =========
2134 16:33:56.485072 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 16:33:56.485121 ===================================
2136 16:33:56.485169 LPDDR4 DRAM CONFIGURATION
2137 16:33:56.485217 ===================================
2138 16:33:56.485266 EX_ROW_EN[0] = 0x0
2139 16:33:56.485314 EX_ROW_EN[1] = 0x0
2140 16:33:56.485363 LP4Y_EN = 0x0
2141 16:33:56.485411 WORK_FSP = 0x0
2142 16:33:56.485458 WL = 0x4
2143 16:33:56.485507 RL = 0x4
2144 16:33:56.485555 BL = 0x2
2145 16:33:56.485603 RPST = 0x0
2146 16:33:56.485651 RD_PRE = 0x0
2147 16:33:56.485699 WR_PRE = 0x1
2148 16:33:56.485746 WR_PST = 0x0
2149 16:33:56.485795 DBI_WR = 0x0
2150 16:33:56.485843 DBI_RD = 0x0
2151 16:33:56.485892 OTF = 0x1
2152 16:33:56.485940 ===================================
2153 16:33:56.485988 ===================================
2154 16:33:56.486037 ANA top config
2155 16:33:56.486086 ===================================
2156 16:33:56.486134 DLL_ASYNC_EN = 0
2157 16:33:56.486182 ALL_SLAVE_EN = 0
2158 16:33:56.486230 NEW_RANK_MODE = 1
2159 16:33:56.486278 DLL_IDLE_MODE = 1
2160 16:33:56.486326 LP45_APHY_COMB_EN = 1
2161 16:33:56.486378 TX_ODT_DIS = 1
2162 16:33:56.486427 NEW_8X_MODE = 1
2163 16:33:56.486475 ===================================
2164 16:33:56.486523 ===================================
2165 16:33:56.486572 data_rate = 2400
2166 16:33:56.486620 CKR = 1
2167 16:33:56.486709 DQ_P2S_RATIO = 8
2168 16:33:56.486763 ===================================
2169 16:33:56.486816 CA_P2S_RATIO = 8
2170 16:33:56.486867 DQ_CA_OPEN = 0
2171 16:33:56.486916 DQ_SEMI_OPEN = 0
2172 16:33:56.486965 CA_SEMI_OPEN = 0
2173 16:33:56.487044 CA_FULL_RATE = 0
2174 16:33:56.487122 DQ_CKDIV4_EN = 0
2175 16:33:56.487199 CA_CKDIV4_EN = 0
2176 16:33:56.487275 CA_PREDIV_EN = 0
2177 16:33:56.487352 PH8_DLY = 17
2178 16:33:56.487428 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 16:33:56.487504 DQ_AAMCK_DIV = 4
2180 16:33:56.487580 CA_AAMCK_DIV = 4
2181 16:33:56.487656 CA_ADMCK_DIV = 4
2182 16:33:56.487733 DQ_TRACK_CA_EN = 0
2183 16:33:56.487809 CA_PICK = 1200
2184 16:33:56.487886 CA_MCKIO = 1200
2185 16:33:56.487963 MCKIO_SEMI = 0
2186 16:33:56.488040 PLL_FREQ = 2366
2187 16:33:56.488117 DQ_UI_PI_RATIO = 32
2188 16:33:56.488193 CA_UI_PI_RATIO = 0
2189 16:33:56.488270 ===================================
2190 16:33:56.488347 ===================================
2191 16:33:56.488424 memory_type:LPDDR4
2192 16:33:56.488505 GP_NUM : 10
2193 16:33:56.488587 SRAM_EN : 1
2194 16:33:56.488667 MD32_EN : 0
2195 16:33:56.488719 ===================================
2196 16:33:56.488768 [ANA_INIT] >>>>>>>>>>>>>>
2197 16:33:56.488818 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 16:33:56.488889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 16:33:56.488941 ===================================
2200 16:33:56.488990 data_rate = 2400,PCW = 0X5b00
2201 16:33:56.489039 ===================================
2202 16:33:56.489088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 16:33:56.489139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 16:33:56.489198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 16:33:56.489270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 16:33:56.489350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 16:33:56.489427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 16:33:56.489505 [ANA_INIT] flow start
2209 16:33:56.489581 [ANA_INIT] PLL >>>>>>>>
2210 16:33:56.489657 [ANA_INIT] PLL <<<<<<<<
2211 16:33:56.489733 [ANA_INIT] MIDPI >>>>>>>>
2212 16:33:56.489809 [ANA_INIT] MIDPI <<<<<<<<
2213 16:33:56.489886 [ANA_INIT] DLL >>>>>>>>
2214 16:33:56.489962 [ANA_INIT] DLL <<<<<<<<
2215 16:33:56.490038 [ANA_INIT] flow end
2216 16:33:56.490115 ============ LP4 DIFF to SE enter ============
2217 16:33:56.490193 ============ LP4 DIFF to SE exit ============
2218 16:33:56.490270 [ANA_INIT] <<<<<<<<<<<<<
2219 16:33:56.490347 [Flow] Enable top DCM control >>>>>
2220 16:33:56.490623 [Flow] Enable top DCM control <<<<<
2221 16:33:56.490704 Enable DLL master slave shuffle
2222 16:33:56.490782 ==============================================================
2223 16:33:56.490860 Gating Mode config
2224 16:33:56.490938 ==============================================================
2225 16:33:56.491015 Config description:
2226 16:33:56.491094 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 16:33:56.491174 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 16:33:56.491252 SELPH_MODE 0: By rank 1: By Phase
2229 16:33:56.491330 ==============================================================
2230 16:33:56.491422 GAT_TRACK_EN = 1
2231 16:33:56.491497 RX_GATING_MODE = 2
2232 16:33:56.491572 RX_GATING_TRACK_MODE = 2
2233 16:33:56.491664 SELPH_MODE = 1
2234 16:33:56.491753 PICG_EARLY_EN = 1
2235 16:33:56.491828 VALID_LAT_VALUE = 1
2236 16:33:56.491903 ==============================================================
2237 16:33:56.491978 Enter into Gating configuration >>>>
2238 16:33:56.492054 Exit from Gating configuration <<<<
2239 16:33:56.492129 Enter into DVFS_PRE_config >>>>>
2240 16:33:56.492206 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 16:33:56.492283 Exit from DVFS_PRE_config <<<<<
2242 16:33:56.492358 Enter into PICG configuration >>>>
2243 16:33:56.492433 Exit from PICG configuration <<<<
2244 16:33:56.492508 [RX_INPUT] configuration >>>>>
2245 16:33:56.492602 [RX_INPUT] configuration <<<<<
2246 16:33:56.492682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 16:33:56.492747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 16:33:56.492795 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 16:33:56.492844 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 16:33:56.492892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 16:33:56.492940 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 16:33:56.492987 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 16:33:56.493034 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 16:33:56.493082 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 16:33:56.493130 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 16:33:56.493177 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 16:33:56.493224 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 16:33:56.493272 ===================================
2259 16:33:56.493319 LPDDR4 DRAM CONFIGURATION
2260 16:33:56.493366 ===================================
2261 16:33:56.493412 EX_ROW_EN[0] = 0x0
2262 16:33:56.493459 EX_ROW_EN[1] = 0x0
2263 16:33:56.493506 LP4Y_EN = 0x0
2264 16:33:56.493554 WORK_FSP = 0x0
2265 16:33:56.493617 WL = 0x4
2266 16:33:56.493665 RL = 0x4
2267 16:33:56.493713 BL = 0x2
2268 16:33:56.493774 RPST = 0x0
2269 16:33:56.493822 RD_PRE = 0x0
2270 16:33:56.493869 WR_PRE = 0x1
2271 16:33:56.493916 WR_PST = 0x0
2272 16:33:56.493962 DBI_WR = 0x0
2273 16:33:56.494008 DBI_RD = 0x0
2274 16:33:56.494055 OTF = 0x1
2275 16:33:56.494102 ===================================
2276 16:33:56.494149 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 16:33:56.494196 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 16:33:56.494244 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 16:33:56.494291 ===================================
2280 16:33:56.494339 LPDDR4 DRAM CONFIGURATION
2281 16:33:56.494385 ===================================
2282 16:33:56.494432 EX_ROW_EN[0] = 0x10
2283 16:33:56.494479 EX_ROW_EN[1] = 0x0
2284 16:33:56.494526 LP4Y_EN = 0x0
2285 16:33:56.494573 WORK_FSP = 0x0
2286 16:33:56.494620 WL = 0x4
2287 16:33:56.494666 RL = 0x4
2288 16:33:56.494712 BL = 0x2
2289 16:33:56.494759 RPST = 0x0
2290 16:33:56.494806 RD_PRE = 0x0
2291 16:33:56.494852 WR_PRE = 0x1
2292 16:33:56.494899 WR_PST = 0x0
2293 16:33:56.494944 DBI_WR = 0x0
2294 16:33:56.494990 DBI_RD = 0x0
2295 16:33:56.495035 OTF = 0x1
2296 16:33:56.495081 ===================================
2297 16:33:56.495128 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 16:33:56.495175 ==
2299 16:33:56.495221 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 16:33:56.495269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 16:33:56.495315 ==
2302 16:33:56.495361 [Duty_Offset_Calibration]
2303 16:33:56.495408 B0:2 B1:0 CA:3
2304 16:33:56.495454
2305 16:33:56.495500 [DutyScan_Calibration_Flow] k_type=0
2306 16:33:56.495564
2307 16:33:56.495625 ==CLK 0==
2308 16:33:56.495671 Final CLK duty delay cell = 0
2309 16:33:56.495718 [0] MAX Duty = 5062%(X100), DQS PI = 12
2310 16:33:56.495781 [0] MIN Duty = 4906%(X100), DQS PI = 54
2311 16:33:56.495842 [0] AVG Duty = 4984%(X100)
2312 16:33:56.495889
2313 16:33:56.495934 CH0 CLK Duty spec in!! Max-Min= 156%
2314 16:33:56.495980 [DutyScan_Calibration_Flow] ====Done====
2315 16:33:56.496027
2316 16:33:56.496073 [DutyScan_Calibration_Flow] k_type=1
2317 16:33:56.496119
2318 16:33:56.496165 ==DQS 0 ==
2319 16:33:56.496212 Final DQS duty delay cell = 0
2320 16:33:56.496259 [0] MAX Duty = 5062%(X100), DQS PI = 12
2321 16:33:56.496331 [0] MIN Duty = 4876%(X100), DQS PI = 50
2322 16:33:56.496422 [0] AVG Duty = 4969%(X100)
2323 16:33:56.496496
2324 16:33:56.496569 ==DQS 1 ==
2325 16:33:56.496664 Final DQS duty delay cell = -4
2326 16:33:56.496731 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2327 16:33:56.496778 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2328 16:33:56.496825 [-4] AVG Duty = 4922%(X100)
2329 16:33:56.496871
2330 16:33:56.496917 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2331 16:33:56.496964
2332 16:33:56.497009 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2333 16:33:56.497058 [DutyScan_Calibration_Flow] ====Done====
2334 16:33:56.497105
2335 16:33:56.497151 [DutyScan_Calibration_Flow] k_type=3
2336 16:33:56.497199
2337 16:33:56.497246 ==DQM 0 ==
2338 16:33:56.497292 Final DQM duty delay cell = 0
2339 16:33:56.497339 [0] MAX Duty = 5124%(X100), DQS PI = 28
2340 16:33:56.497386 [0] MIN Duty = 4876%(X100), DQS PI = 0
2341 16:33:56.497432 [0] AVG Duty = 5000%(X100)
2342 16:33:56.497477
2343 16:33:56.497523 ==DQM 1 ==
2344 16:33:56.497800 Final DQM duty delay cell = 4
2345 16:33:56.497870 [4] MAX Duty = 5124%(X100), DQS PI = 52
2346 16:33:56.497919 [4] MIN Duty = 5000%(X100), DQS PI = 12
2347 16:33:56.497966 [4] AVG Duty = 5062%(X100)
2348 16:33:56.498012
2349 16:33:56.498059 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2350 16:33:56.498107
2351 16:33:56.498153 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2352 16:33:56.498199 [DutyScan_Calibration_Flow] ====Done====
2353 16:33:56.498245
2354 16:33:56.498292 [DutyScan_Calibration_Flow] k_type=2
2355 16:33:56.498338
2356 16:33:56.498385 ==DQ 0 ==
2357 16:33:56.498432 Final DQ duty delay cell = -4
2358 16:33:56.498479 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2359 16:33:56.498526 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2360 16:33:56.498573 [-4] AVG Duty = 4953%(X100)
2361 16:33:56.498619
2362 16:33:56.498665 ==DQ 1 ==
2363 16:33:56.498711 Final DQ duty delay cell = -4
2364 16:33:56.498758 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2365 16:33:56.498804 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2366 16:33:56.498851 [-4] AVG Duty = 4938%(X100)
2367 16:33:56.498897
2368 16:33:56.498943 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2369 16:33:56.498990
2370 16:33:56.499071 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2371 16:33:56.499117 [DutyScan_Calibration_Flow] ====Done====
2372 16:33:56.499163 ==
2373 16:33:56.499209 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 16:33:56.499256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 16:33:56.499303 ==
2376 16:33:56.499350 [Duty_Offset_Calibration]
2377 16:33:56.499432 B0:1 B1:-2 CA:1
2378 16:33:56.499497
2379 16:33:56.499544 [DutyScan_Calibration_Flow] k_type=0
2380 16:33:56.499590
2381 16:33:56.499696 ==CLK 0==
2382 16:33:56.499874 Final CLK duty delay cell = 0
2383 16:33:56.499980 [0] MAX Duty = 5031%(X100), DQS PI = 0
2384 16:33:56.500065 [0] MIN Duty = 4844%(X100), DQS PI = 26
2385 16:33:56.500147 [0] AVG Duty = 4937%(X100)
2386 16:33:56.500226
2387 16:33:56.500273 CH1 CLK Duty spec in!! Max-Min= 187%
2388 16:33:56.500321 [DutyScan_Calibration_Flow] ====Done====
2389 16:33:56.500368
2390 16:33:56.500414 [DutyScan_Calibration_Flow] k_type=1
2391 16:33:56.500461
2392 16:33:56.500507 ==DQS 0 ==
2393 16:33:56.500591 Final DQS duty delay cell = -4
2394 16:33:56.500687 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2395 16:33:56.500754 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2396 16:33:56.500801 [-4] AVG Duty = 4953%(X100)
2397 16:33:56.500852
2398 16:33:56.500901 ==DQS 1 ==
2399 16:33:56.500949 Final DQS duty delay cell = 0
2400 16:33:56.500997 [0] MAX Duty = 5093%(X100), DQS PI = 34
2401 16:33:56.501044 [0] MIN Duty = 4844%(X100), DQS PI = 60
2402 16:33:56.501091 [0] AVG Duty = 4968%(X100)
2403 16:33:56.501138
2404 16:33:56.501184 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2405 16:33:56.501232
2406 16:33:56.501278 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2407 16:33:56.501325 [DutyScan_Calibration_Flow] ====Done====
2408 16:33:56.501371
2409 16:33:56.501417 [DutyScan_Calibration_Flow] k_type=3
2410 16:33:56.501464
2411 16:33:56.501509 ==DQM 0 ==
2412 16:33:56.501556 Final DQM duty delay cell = 0
2413 16:33:56.501603 [0] MAX Duty = 5000%(X100), DQS PI = 54
2414 16:33:56.501649 [0] MIN Duty = 4876%(X100), DQS PI = 20
2415 16:33:56.501696 [0] AVG Duty = 4938%(X100)
2416 16:33:56.501742
2417 16:33:56.501788 ==DQM 1 ==
2418 16:33:56.501834 Final DQM duty delay cell = 0
2419 16:33:56.501880 [0] MAX Duty = 5031%(X100), DQS PI = 4
2420 16:33:56.501926 [0] MIN Duty = 4907%(X100), DQS PI = 10
2421 16:33:56.501974 [0] AVG Duty = 4969%(X100)
2422 16:33:56.502020
2423 16:33:56.502066 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2424 16:33:56.502112
2425 16:33:56.502161 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2426 16:33:56.502208 [DutyScan_Calibration_Flow] ====Done====
2427 16:33:56.502273
2428 16:33:56.502486 [DutyScan_Calibration_Flow] k_type=2
2429 16:33:56.502575
2430 16:33:56.502652 ==DQ 0 ==
2431 16:33:56.502703 Final DQ duty delay cell = 0
2432 16:33:56.502759 [0] MAX Duty = 5062%(X100), DQS PI = 0
2433 16:33:56.502837 [0] MIN Duty = 4938%(X100), DQS PI = 24
2434 16:33:56.502913 [0] AVG Duty = 5000%(X100)
2435 16:33:56.502987
2436 16:33:56.503060 ==DQ 1 ==
2437 16:33:56.503136 Final DQ duty delay cell = 0
2438 16:33:56.503212 [0] MAX Duty = 5093%(X100), DQS PI = 2
2439 16:33:56.503287 [0] MIN Duty = 4938%(X100), DQS PI = 58
2440 16:33:56.503361 [0] AVG Duty = 5015%(X100)
2441 16:33:56.503434
2442 16:33:56.503509 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2443 16:33:56.503583
2444 16:33:56.503657 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2445 16:33:56.503770 [DutyScan_Calibration_Flow] ====Done====
2446 16:33:56.503856 nWR fixed to 30
2447 16:33:56.503935 [ModeRegInit_LP4] CH0 RK0
2448 16:33:56.504012 [ModeRegInit_LP4] CH0 RK1
2449 16:33:56.504088 [ModeRegInit_LP4] CH1 RK0
2450 16:33:56.504162 [ModeRegInit_LP4] CH1 RK1
2451 16:33:56.504237 match AC timing 7
2452 16:33:56.504312 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 16:33:56.504387 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 16:33:56.504478 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 16:33:56.504558 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 16:33:56.504637 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 16:33:56.504716 ==
2458 16:33:56.504765 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 16:33:56.504812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 16:33:56.504859 ==
2461 16:33:56.504906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 16:33:56.504955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 16:33:56.505004 [CA 0] Center 40 (10~71) winsize 62
2464 16:33:56.505057 [CA 1] Center 39 (9~70) winsize 62
2465 16:33:56.505134 [CA 2] Center 36 (6~66) winsize 61
2466 16:33:56.505209 [CA 3] Center 35 (5~66) winsize 62
2467 16:33:56.505284 [CA 4] Center 34 (4~65) winsize 62
2468 16:33:56.505358 [CA 5] Center 33 (3~63) winsize 61
2469 16:33:56.505432
2470 16:33:56.505507 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2471 16:33:56.505581
2472 16:33:56.505655 [CATrainingPosCal] consider 1 rank data
2473 16:33:56.505730 u2DelayCellTimex100 = 270/100 ps
2474 16:33:56.505804 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2475 16:33:56.505897 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2476 16:33:56.505988 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2477 16:33:56.506064 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 16:33:56.506139 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 16:33:56.506214 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 16:33:56.506289
2481 16:33:56.506339 CA PerBit enable=1, Macro0, CA PI delay=33
2482 16:33:56.506386
2483 16:33:56.506433 [CBTSetCACLKResult] CA Dly = 33
2484 16:33:56.506480 CS Dly: 7 (0~38)
2485 16:33:56.506530 ==
2486 16:33:56.506580 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 16:33:56.506628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 16:33:56.506675 ==
2489 16:33:56.506723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 16:33:56.506984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 16:33:56.507056 [CA 0] Center 40 (10~71) winsize 62
2492 16:33:56.507157 [CA 1] Center 40 (10~70) winsize 61
2493 16:33:56.507274 [CA 2] Center 35 (5~66) winsize 62
2494 16:33:56.507351 [CA 3] Center 35 (5~66) winsize 62
2495 16:33:56.507399 [CA 4] Center 34 (4~65) winsize 62
2496 16:33:56.507447 [CA 5] Center 33 (3~63) winsize 61
2497 16:33:56.507494
2498 16:33:56.507542 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2499 16:33:56.507590
2500 16:33:56.507637 [CATrainingPosCal] consider 2 rank data
2501 16:33:56.507686 u2DelayCellTimex100 = 270/100 ps
2502 16:33:56.507734 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2503 16:33:56.507781 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2504 16:33:56.507828 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2505 16:33:56.507875 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 16:33:56.507928 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 16:33:56.507978 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2508 16:33:56.508027
2509 16:33:56.508074 CA PerBit enable=1, Macro0, CA PI delay=33
2510 16:33:56.508122
2511 16:33:56.508168 [CBTSetCACLKResult] CA Dly = 33
2512 16:33:56.508216 CS Dly: 7 (0~39)
2513 16:33:56.508263
2514 16:33:56.508309 ----->DramcWriteLeveling(PI) begin...
2515 16:33:56.508357 ==
2516 16:33:56.508405 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 16:33:56.508453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 16:33:56.508500 ==
2519 16:33:56.508547 Write leveling (Byte 0): 33 => 33
2520 16:33:56.508594 Write leveling (Byte 1): 29 => 29
2521 16:33:56.508652 DramcWriteLeveling(PI) end<-----
2522 16:33:56.508703
2523 16:33:56.508750 ==
2524 16:33:56.508798 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 16:33:56.508846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 16:33:56.508894 ==
2527 16:33:56.508942 [Gating] SW mode calibration
2528 16:33:56.508993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 16:33:56.509043 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 16:33:56.509091 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 16:33:56.509140 0 15 4 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2532 16:33:56.509188 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 16:33:56.509236 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 16:33:56.509283 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 16:33:56.509332 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 16:33:56.509379 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 16:33:56.509427 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2538 16:33:56.509475 1 0 0 | B1->B0 | 3232 2626 | 0 0 | (0 0) (0 0)
2539 16:33:56.509524 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
2540 16:33:56.509572 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 16:33:56.509620 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 16:33:56.509668 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 16:33:56.509716 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 16:33:56.509764 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 16:33:56.509811 1 0 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2546 16:33:56.509859 1 1 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2547 16:33:56.509907 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2548 16:33:56.509954 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 16:33:56.510003 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 16:33:56.510050 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 16:33:56.510097 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 16:33:56.510145 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 16:33:56.510193 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 16:33:56.510241 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 16:33:56.510288 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 16:33:56.510335 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 16:33:56.510383 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 16:33:56.510430 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 16:33:56.510478 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 16:33:56.510539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 16:33:56.510585 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 16:33:56.510632 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 16:33:56.510679 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 16:33:56.510725 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 16:33:56.510772 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 16:33:56.510818 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 16:33:56.510867 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 16:33:56.510914 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 16:33:56.510963 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 16:33:56.511009 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 16:33:56.511071 Total UI for P1: 0, mck2ui 16
2572 16:33:56.511132 best dqsien dly found for B0: ( 1, 3, 28)
2573 16:33:56.511180 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 16:33:56.511228 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 16:33:56.511274 Total UI for P1: 0, mck2ui 16
2576 16:33:56.511321 best dqsien dly found for B1: ( 1, 4, 2)
2577 16:33:56.511370 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2578 16:33:56.511421 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2579 16:33:56.511467
2580 16:33:56.511514 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2581 16:33:56.511561 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2582 16:33:56.511607 [Gating] SW calibration Done
2583 16:33:56.511654 ==
2584 16:33:56.511700 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 16:33:56.511746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 16:33:56.511792 ==
2587 16:33:56.511838 RX Vref Scan: 0
2588 16:33:56.511884
2589 16:33:56.511929 RX Vref 0 -> 0, step: 1
2590 16:33:56.511975
2591 16:33:56.512021 RX Delay -40 -> 252, step: 8
2592 16:33:56.512068 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2593 16:33:56.512114 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2594 16:33:56.512161 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2595 16:33:56.512413 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2596 16:33:56.512467 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2597 16:33:56.512515 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2598 16:33:56.512563 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2599 16:33:56.512612 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2600 16:33:56.512669 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2601 16:33:56.512731 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2602 16:33:56.512778 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2603 16:33:56.512824 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2604 16:33:56.512871 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2605 16:33:56.512918 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2606 16:33:56.512964 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2607 16:33:56.513010 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2608 16:33:56.513057 ==
2609 16:33:56.513103 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 16:33:56.513150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 16:33:56.513198 ==
2612 16:33:56.513244 DQS Delay:
2613 16:33:56.513290 DQS0 = 0, DQS1 = 0
2614 16:33:56.513336 DQM Delay:
2615 16:33:56.513382 DQM0 = 112, DQM1 = 102
2616 16:33:56.513428 DQ Delay:
2617 16:33:56.513473 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2618 16:33:56.513520 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2619 16:33:56.513567 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2620 16:33:56.513613 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2621 16:33:56.513675
2622 16:33:56.513729
2623 16:33:56.513812 ==
2624 16:33:56.513957 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 16:33:56.514027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 16:33:56.514095 ==
2627 16:33:56.514164
2628 16:33:56.514216
2629 16:33:56.514279 TX Vref Scan disable
2630 16:33:56.514335 == TX Byte 0 ==
2631 16:33:56.514414 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2632 16:33:56.514490 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2633 16:33:56.514566 == TX Byte 1 ==
2634 16:33:56.514644 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2635 16:33:56.514721 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2636 16:33:56.514795 ==
2637 16:33:56.514870 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 16:33:56.514946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 16:33:56.515020 ==
2640 16:33:56.515095 TX Vref=22, minBit 4, minWin=25, winSum=416
2641 16:33:56.515188 TX Vref=24, minBit 14, minWin=25, winSum=424
2642 16:33:56.515281 TX Vref=26, minBit 2, minWin=26, winSum=430
2643 16:33:56.515357 TX Vref=28, minBit 10, minWin=26, winSum=433
2644 16:33:56.515432 TX Vref=30, minBit 8, minWin=26, winSum=435
2645 16:33:56.515508 TX Vref=32, minBit 3, minWin=26, winSum=432
2646 16:33:56.515584 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2647 16:33:56.515659
2648 16:33:56.515733 Final TX Range 1 Vref 30
2649 16:33:56.515807
2650 16:33:56.515897 ==
2651 16:33:56.515985 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 16:33:56.516060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 16:33:56.516136 ==
2654 16:33:56.516210
2655 16:33:56.516283
2656 16:33:56.516388 TX Vref Scan disable
2657 16:33:56.516468 == TX Byte 0 ==
2658 16:33:56.516545 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2659 16:33:56.516623 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2660 16:33:56.516728 == TX Byte 1 ==
2661 16:33:56.516785 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2662 16:33:56.516862 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2663 16:33:56.516941
2664 16:33:56.517021 [DATLAT]
2665 16:33:56.517101 Freq=1200, CH0 RK0
2666 16:33:56.517181
2667 16:33:56.517260 DATLAT Default: 0xd
2668 16:33:56.517339 0, 0xFFFF, sum = 0
2669 16:33:56.517422 1, 0xFFFF, sum = 0
2670 16:33:56.517504 2, 0xFFFF, sum = 0
2671 16:33:56.517583 3, 0xFFFF, sum = 0
2672 16:33:56.517665 4, 0xFFFF, sum = 0
2673 16:33:56.517743 5, 0xFFFF, sum = 0
2674 16:33:56.517825 6, 0xFFFF, sum = 0
2675 16:33:56.517904 7, 0xFFFF, sum = 0
2676 16:33:56.517983 8, 0xFFFF, sum = 0
2677 16:33:56.518065 9, 0xFFFF, sum = 0
2678 16:33:56.518151 10, 0xFFFF, sum = 0
2679 16:33:56.518232 11, 0xFFFF, sum = 0
2680 16:33:56.518316 12, 0x0, sum = 1
2681 16:33:56.518397 13, 0x0, sum = 2
2682 16:33:56.518481 14, 0x0, sum = 3
2683 16:33:56.518563 15, 0x0, sum = 4
2684 16:33:56.518644 best_step = 13
2685 16:33:56.518722
2686 16:33:56.518798 ==
2687 16:33:56.518875 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 16:33:56.518956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 16:33:56.519035 ==
2690 16:33:56.519148 RX Vref Scan: 1
2691 16:33:56.519226
2692 16:33:56.519301 Set Vref Range= 32 -> 127
2693 16:33:56.519381
2694 16:33:56.519460 RX Vref 32 -> 127, step: 1
2695 16:33:56.519538
2696 16:33:56.519613 RX Delay -37 -> 252, step: 4
2697 16:33:56.519691
2698 16:33:56.519772 Set Vref, RX VrefLevel [Byte0]: 32
2699 16:33:56.519853 [Byte1]: 32
2700 16:33:56.519931
2701 16:33:56.520012 Set Vref, RX VrefLevel [Byte0]: 33
2702 16:33:56.520093 [Byte1]: 33
2703 16:33:56.520173
2704 16:33:56.520254 Set Vref, RX VrefLevel [Byte0]: 34
2705 16:33:56.520334 [Byte1]: 34
2706 16:33:56.520412
2707 16:33:56.520488 Set Vref, RX VrefLevel [Byte0]: 35
2708 16:33:56.520567 [Byte1]: 35
2709 16:33:56.520670
2710 16:33:56.520764 Set Vref, RX VrefLevel [Byte0]: 36
2711 16:33:56.520842 [Byte1]: 36
2712 16:33:56.520922
2713 16:33:56.521000 Set Vref, RX VrefLevel [Byte0]: 37
2714 16:33:56.521079 [Byte1]: 37
2715 16:33:56.521159
2716 16:33:56.521237 Set Vref, RX VrefLevel [Byte0]: 38
2717 16:33:56.521311 [Byte1]: 38
2718 16:33:56.521385
2719 16:33:56.521459 Set Vref, RX VrefLevel [Byte0]: 39
2720 16:33:56.521534 [Byte1]: 39
2721 16:33:56.521607
2722 16:33:56.521684 Set Vref, RX VrefLevel [Byte0]: 40
2723 16:33:56.521760 [Byte1]: 40
2724 16:33:56.521833
2725 16:33:56.521907 Set Vref, RX VrefLevel [Byte0]: 41
2726 16:33:56.521982 [Byte1]: 41
2727 16:33:56.522056
2728 16:33:56.522130 Set Vref, RX VrefLevel [Byte0]: 42
2729 16:33:56.522205 [Byte1]: 42
2730 16:33:56.522310
2731 16:33:56.522384 Set Vref, RX VrefLevel [Byte0]: 43
2732 16:33:56.522459 [Byte1]: 43
2733 16:33:56.522533
2734 16:33:56.522607 Set Vref, RX VrefLevel [Byte0]: 44
2735 16:33:56.522684 [Byte1]: 44
2736 16:33:56.522759
2737 16:33:56.522833 Set Vref, RX VrefLevel [Byte0]: 45
2738 16:33:56.522909 [Byte1]: 45
2739 16:33:56.522985
2740 16:33:56.523059 Set Vref, RX VrefLevel [Byte0]: 46
2741 16:33:56.523135 [Byte1]: 46
2742 16:33:56.523212
2743 16:33:56.523286 Set Vref, RX VrefLevel [Byte0]: 47
2744 16:33:56.523360 [Byte1]: 47
2745 16:33:56.523434
2746 16:33:56.523508 Set Vref, RX VrefLevel [Byte0]: 48
2747 16:33:56.523582 [Byte1]: 48
2748 16:33:56.523656
2749 16:33:56.523733 Set Vref, RX VrefLevel [Byte0]: 49
2750 16:33:56.523808 [Byte1]: 49
2751 16:33:56.523881
2752 16:33:56.523955 Set Vref, RX VrefLevel [Byte0]: 50
2753 16:33:56.524228 [Byte1]: 50
2754 16:33:56.524306
2755 16:33:56.524380 Set Vref, RX VrefLevel [Byte0]: 51
2756 16:33:56.524455 [Byte1]: 51
2757 16:33:56.524528
2758 16:33:56.524602 Set Vref, RX VrefLevel [Byte0]: 52
2759 16:33:56.524722 [Byte1]: 52
2760 16:33:56.524796
2761 16:33:56.524870 Set Vref, RX VrefLevel [Byte0]: 53
2762 16:33:56.524948 [Byte1]: 53
2763 16:33:56.525023
2764 16:33:56.525096 Set Vref, RX VrefLevel [Byte0]: 54
2765 16:33:56.525174 [Byte1]: 54
2766 16:33:56.525224
2767 16:33:56.525271 Set Vref, RX VrefLevel [Byte0]: 55
2768 16:33:56.525317 [Byte1]: 55
2769 16:33:56.525364
2770 16:33:56.525410 Set Vref, RX VrefLevel [Byte0]: 56
2771 16:33:56.525460 [Byte1]: 56
2772 16:33:56.525509
2773 16:33:56.525557 Set Vref, RX VrefLevel [Byte0]: 57
2774 16:33:56.525604 [Byte1]: 57
2775 16:33:56.525651
2776 16:33:56.525697 Set Vref, RX VrefLevel [Byte0]: 58
2777 16:33:56.525743 [Byte1]: 58
2778 16:33:56.525789
2779 16:33:56.525835 Set Vref, RX VrefLevel [Byte0]: 59
2780 16:33:56.525928 [Byte1]: 59
2781 16:33:56.525990
2782 16:33:56.526038 Set Vref, RX VrefLevel [Byte0]: 60
2783 16:33:56.526112 [Byte1]: 60
2784 16:33:56.526188
2785 16:33:56.526263 Set Vref, RX VrefLevel [Byte0]: 61
2786 16:33:56.526338 [Byte1]: 61
2787 16:33:56.526412
2788 16:33:56.526517 Set Vref, RX VrefLevel [Byte0]: 62
2789 16:33:56.526594 [Byte1]: 62
2790 16:33:56.526668
2791 16:33:56.526741 Set Vref, RX VrefLevel [Byte0]: 63
2792 16:33:56.526816 [Byte1]: 63
2793 16:33:56.526889
2794 16:33:56.526963 Set Vref, RX VrefLevel [Byte0]: 64
2795 16:33:56.527039 [Byte1]: 64
2796 16:33:56.527115
2797 16:33:56.527188 Set Vref, RX VrefLevel [Byte0]: 65
2798 16:33:56.527263 [Byte1]: 65
2799 16:33:56.527336
2800 16:33:56.527410 Set Vref, RX VrefLevel [Byte0]: 66
2801 16:33:56.527485 [Byte1]: 66
2802 16:33:56.527558
2803 16:33:56.527635 Set Vref, RX VrefLevel [Byte0]: 67
2804 16:33:56.527710 [Byte1]: 67
2805 16:33:56.527784
2806 16:33:56.527858 Set Vref, RX VrefLevel [Byte0]: 68
2807 16:33:56.527931 [Byte1]: 68
2808 16:33:56.527981
2809 16:33:56.528028 Set Vref, RX VrefLevel [Byte0]: 69
2810 16:33:56.528078 [Byte1]: 69
2811 16:33:56.528154
2812 16:33:56.528230 Set Vref, RX VrefLevel [Byte0]: 70
2813 16:33:56.528307 [Byte1]: 70
2814 16:33:56.528412
2815 16:33:56.528497 Set Vref, RX VrefLevel [Byte0]: 71
2816 16:33:56.528569 [Byte1]: 71
2817 16:33:56.528652
2818 16:33:56.528735 Set Vref, RX VrefLevel [Byte0]: 72
2819 16:33:56.528809 [Byte1]: 72
2820 16:33:56.528904
2821 16:33:56.529023 Set Vref, RX VrefLevel [Byte0]: 73
2822 16:33:56.529093 [Byte1]: 73
2823 16:33:56.529167
2824 16:33:56.529240 Set Vref, RX VrefLevel [Byte0]: 74
2825 16:33:56.529313 [Byte1]: 74
2826 16:33:56.529391
2827 16:33:56.529505 Final RX Vref Byte 0 = 61 to rank0
2828 16:33:56.529583 Final RX Vref Byte 1 = 45 to rank0
2829 16:33:56.529659 Final RX Vref Byte 0 = 61 to rank1
2830 16:33:56.529713 Final RX Vref Byte 1 = 45 to rank1==
2831 16:33:56.529789 Dram Type= 6, Freq= 0, CH_0, rank 0
2832 16:33:56.529864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 16:33:56.529939 ==
2834 16:33:56.530014 DQS Delay:
2835 16:33:56.530088 DQS0 = 0, DQS1 = 0
2836 16:33:56.530162 DQM Delay:
2837 16:33:56.530236 DQM0 = 112, DQM1 = 98
2838 16:33:56.530308 DQ Delay:
2839 16:33:56.530359 DQ0 =112, DQ1 =110, DQ2 =112, DQ3 =108
2840 16:33:56.530413 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2841 16:33:56.530489 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =90
2842 16:33:56.530564 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2843 16:33:56.530638
2844 16:33:56.530711
2845 16:33:56.530786 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2846 16:33:56.530862 CH0 RK0: MR19=303, MR18=FFFE
2847 16:33:56.530946 CH0_RK0: MR19=0x303, MR18=0xFFFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2848 16:33:56.531023
2849 16:33:56.531097 ----->DramcWriteLeveling(PI) begin...
2850 16:33:56.531173 ==
2851 16:33:56.531247 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 16:33:56.531322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 16:33:56.531397 ==
2854 16:33:56.531471 Write leveling (Byte 0): 32 => 32
2855 16:33:56.531545 Write leveling (Byte 1): 32 => 32
2856 16:33:56.531619 DramcWriteLeveling(PI) end<-----
2857 16:33:56.531694
2858 16:33:56.531767 ==
2859 16:33:56.531841 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 16:33:56.531916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 16:33:56.531990 ==
2862 16:33:56.532064 [Gating] SW mode calibration
2863 16:33:56.532140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2864 16:33:56.532217 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2865 16:33:56.532293 0 15 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2866 16:33:56.532369 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 16:33:56.532445 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 16:33:56.532520 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 16:33:56.532594 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 16:33:56.532692 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 16:33:56.532756 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2872 16:33:56.532803 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2873 16:33:56.532850 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2874 16:33:56.532897 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 16:33:56.532944 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 16:33:56.532990 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 16:33:56.533037 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 16:33:56.533084 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 16:33:56.533131 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2880 16:33:56.533177 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2881 16:33:56.533223 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
2882 16:33:56.533270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 16:33:56.533316 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 16:33:56.533362 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 16:33:56.533608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 16:33:56.533665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 16:33:56.533762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 16:33:56.533895 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2889 16:33:56.533992 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2890 16:33:56.534086 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 16:33:56.534180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 16:33:56.534273 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 16:33:56.534367 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 16:33:56.534461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 16:33:56.534556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 16:33:56.534650 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 16:33:56.534744 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 16:33:56.534839 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 16:33:56.534968 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 16:33:56.535061 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 16:33:56.535154 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 16:33:56.535231 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 16:33:56.535309 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2904 16:33:56.535385 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2905 16:33:56.535459 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 16:33:56.535534 Total UI for P1: 0, mck2ui 16
2907 16:33:56.535610 best dqsien dly found for B0: ( 1, 3, 26)
2908 16:33:56.535685 Total UI for P1: 0, mck2ui 16
2909 16:33:56.535761 best dqsien dly found for B1: ( 1, 3, 30)
2910 16:33:56.535839 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2911 16:33:56.535914 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2912 16:33:56.535990
2913 16:33:56.536065 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2914 16:33:56.536140 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2915 16:33:56.536215 [Gating] SW calibration Done
2916 16:33:56.536289 ==
2917 16:33:56.536364 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 16:33:56.536439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 16:33:56.536513 ==
2920 16:33:56.536587 RX Vref Scan: 0
2921 16:33:56.536685
2922 16:33:56.536749 RX Vref 0 -> 0, step: 1
2923 16:33:56.536796
2924 16:33:56.536842 RX Delay -40 -> 252, step: 8
2925 16:33:56.536913 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2926 16:33:56.537030 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2927 16:33:56.537145 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2928 16:33:56.537207 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2929 16:33:56.537254 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2930 16:33:56.537300 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2931 16:33:56.537346 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2932 16:33:56.537392 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2933 16:33:56.537438 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2934 16:33:56.537485 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2935 16:33:56.537532 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2936 16:33:56.763186 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2937 16:33:56.763325 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2938 16:33:56.763411 iDelay=200, Bit 13, Center 103 (32 ~ 175) 144
2939 16:33:56.763494 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2940 16:33:56.763575 iDelay=200, Bit 15, Center 107 (40 ~ 175) 136
2941 16:33:56.763654 ==
2942 16:33:56.763732 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 16:33:56.763810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 16:33:56.763885 ==
2945 16:33:56.763961 DQS Delay:
2946 16:33:56.764036 DQS0 = 0, DQS1 = 0
2947 16:33:56.764114 DQM Delay:
2948 16:33:56.764191 DQM0 = 112, DQM1 = 99
2949 16:33:56.764266 DQ Delay:
2950 16:33:56.764342 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2951 16:33:56.764417 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2952 16:33:56.764538 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =91
2953 16:33:56.764617 DQ12 =107, DQ13 =103, DQ14 =111, DQ15 =107
2954 16:33:56.764717
2955 16:33:56.764793
2956 16:33:56.764867 ==
2957 16:33:56.764974 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 16:33:56.765028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 16:33:56.765132 ==
2960 16:33:56.765184
2961 16:33:56.765258
2962 16:33:56.765332 TX Vref Scan disable
2963 16:33:56.765424 == TX Byte 0 ==
2964 16:33:56.765502 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2965 16:33:56.765553 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2966 16:33:56.765601 == TX Byte 1 ==
2967 16:33:56.765648 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2968 16:33:56.765694 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2969 16:33:56.765742 ==
2970 16:33:56.765789 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 16:33:56.765836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 16:33:56.765883 ==
2973 16:33:56.765929 TX Vref=22, minBit 1, minWin=26, winSum=423
2974 16:33:56.765977 TX Vref=24, minBit 5, minWin=26, winSum=428
2975 16:33:56.766024 TX Vref=26, minBit 5, minWin=26, winSum=431
2976 16:33:56.766071 TX Vref=28, minBit 13, minWin=26, winSum=437
2977 16:33:56.766118 TX Vref=30, minBit 1, minWin=27, winSum=441
2978 16:33:56.766166 TX Vref=32, minBit 13, minWin=26, winSum=437
2979 16:33:56.766213 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
2980 16:33:56.766260
2981 16:33:56.766306 Final TX Range 1 Vref 30
2982 16:33:56.766353
2983 16:33:56.766400 ==
2984 16:33:56.766446 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 16:33:56.766494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 16:33:56.766540 ==
2987 16:33:56.766586
2988 16:33:56.766632
2989 16:33:56.766679 TX Vref Scan disable
2990 16:33:56.766726 == TX Byte 0 ==
2991 16:33:56.766773 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2992 16:33:56.766820 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2993 16:33:56.766867 == TX Byte 1 ==
2994 16:33:56.766913 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2995 16:33:56.766960 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2996 16:33:56.767006
2997 16:33:56.767051 [DATLAT]
2998 16:33:56.767097 Freq=1200, CH0 RK1
2999 16:33:56.767143
3000 16:33:56.767189 DATLAT Default: 0xd
3001 16:33:56.767236 0, 0xFFFF, sum = 0
3002 16:33:56.767283 1, 0xFFFF, sum = 0
3003 16:33:56.767331 2, 0xFFFF, sum = 0
3004 16:33:56.767378 3, 0xFFFF, sum = 0
3005 16:33:56.767425 4, 0xFFFF, sum = 0
3006 16:33:56.767471 5, 0xFFFF, sum = 0
3007 16:33:56.767518 6, 0xFFFF, sum = 0
3008 16:33:56.767564 7, 0xFFFF, sum = 0
3009 16:33:56.767611 8, 0xFFFF, sum = 0
3010 16:33:56.767658 9, 0xFFFF, sum = 0
3011 16:33:56.767705 10, 0xFFFF, sum = 0
3012 16:33:56.767752 11, 0xFFFF, sum = 0
3013 16:33:56.767999 12, 0x0, sum = 1
3014 16:33:56.768053 13, 0x0, sum = 2
3015 16:33:56.768101 14, 0x0, sum = 3
3016 16:33:56.768149 15, 0x0, sum = 4
3017 16:33:56.768196 best_step = 13
3018 16:33:56.768243
3019 16:33:56.768289 ==
3020 16:33:56.768336 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 16:33:56.768383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 16:33:56.768430 ==
3023 16:33:56.768476 RX Vref Scan: 0
3024 16:33:56.768522
3025 16:33:56.768569 RX Vref 0 -> 0, step: 1
3026 16:33:56.768615
3027 16:33:56.768697 RX Delay -37 -> 252, step: 4
3028 16:33:56.768762 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3029 16:33:56.768810 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3030 16:33:56.768857 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3031 16:33:56.768904 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3032 16:33:56.768950 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3033 16:33:56.768997 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3034 16:33:56.769043 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3035 16:33:56.769090 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3036 16:33:56.769136 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3037 16:33:56.769183 iDelay=195, Bit 9, Center 82 (15 ~ 150) 136
3038 16:33:56.769229 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3039 16:33:56.769276 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3040 16:33:56.769323 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3041 16:33:56.769369 iDelay=195, Bit 13, Center 104 (35 ~ 174) 140
3042 16:33:56.769415 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3043 16:33:56.769461 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3044 16:33:56.769507 ==
3045 16:33:56.769553 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 16:33:56.769600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 16:33:56.769647 ==
3048 16:33:56.769693 DQS Delay:
3049 16:33:56.769739 DQS0 = 0, DQS1 = 0
3050 16:33:56.769786 DQM Delay:
3051 16:33:56.769831 DQM0 = 110, DQM1 = 99
3052 16:33:56.769877 DQ Delay:
3053 16:33:56.769924 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3054 16:33:56.769970 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3055 16:33:56.770017 DQ8 =88, DQ9 =82, DQ10 =100, DQ11 =90
3056 16:33:56.770064 DQ12 =108, DQ13 =104, DQ14 =112, DQ15 =108
3057 16:33:56.770122
3058 16:33:56.770169
3059 16:33:56.770216 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3060 16:33:56.770265 CH0 RK1: MR19=403, MR18=14FB
3061 16:33:56.770312 CH0_RK1: MR19=0x403, MR18=0x14FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3062 16:33:56.770360 [RxdqsGatingPostProcess] freq 1200
3063 16:33:56.770406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3064 16:33:56.770453 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 16:33:56.770500 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 16:33:56.770546 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 16:33:56.770593 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 16:33:56.770639 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 16:33:56.770686 best DQS1 dly(2T, 0.5T) = (0, 11)
3070 16:33:56.770732 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 16:33:56.770778 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3072 16:33:56.770824 Pre-setting of DQS Precalculation
3073 16:33:56.770871 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3074 16:33:56.770918 ==
3075 16:33:56.770965 Dram Type= 6, Freq= 0, CH_1, rank 0
3076 16:33:56.771011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 16:33:56.771059 ==
3078 16:33:56.771106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 16:33:56.771152 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 16:33:56.771200 [CA 0] Center 37 (8~67) winsize 60
3081 16:33:56.771247 [CA 1] Center 38 (8~68) winsize 61
3082 16:33:56.771294 [CA 2] Center 34 (4~64) winsize 61
3083 16:33:56.771341 [CA 3] Center 34 (4~64) winsize 61
3084 16:33:56.771387 [CA 4] Center 35 (5~65) winsize 61
3085 16:33:56.771433 [CA 5] Center 33 (3~63) winsize 61
3086 16:33:56.771480
3087 16:33:56.771526 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3088 16:33:56.771590
3089 16:33:56.771653 [CATrainingPosCal] consider 1 rank data
3090 16:33:56.771701 u2DelayCellTimex100 = 270/100 ps
3091 16:33:56.771752 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3092 16:33:56.771799 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3093 16:33:56.771846 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 16:33:56.771893 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 16:33:56.771940 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 16:33:56.771987 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3097 16:33:56.772033
3098 16:33:56.772079 CA PerBit enable=1, Macro0, CA PI delay=33
3099 16:33:56.772142
3100 16:33:56.772189 [CBTSetCACLKResult] CA Dly = 33
3101 16:33:56.772280 CS Dly: 6 (0~37)
3102 16:33:56.772355 ==
3103 16:33:56.772430 Dram Type= 6, Freq= 0, CH_1, rank 1
3104 16:33:56.772505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 16:33:56.772580 ==
3106 16:33:56.772676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 16:33:56.772744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3108 16:33:56.772795 [CA 0] Center 38 (8~68) winsize 61
3109 16:33:56.772845 [CA 1] Center 37 (7~68) winsize 62
3110 16:33:56.772892 [CA 2] Center 35 (5~65) winsize 61
3111 16:33:56.772939 [CA 3] Center 33 (3~64) winsize 62
3112 16:33:56.772986 [CA 4] Center 34 (4~65) winsize 62
3113 16:33:56.773033 [CA 5] Center 33 (3~64) winsize 62
3114 16:33:56.773080
3115 16:33:56.773126 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 16:33:56.773190
3117 16:33:56.773255 [CATrainingPosCal] consider 2 rank data
3118 16:33:56.773305 u2DelayCellTimex100 = 270/100 ps
3119 16:33:56.773353 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3120 16:33:56.773400 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3121 16:33:56.773447 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3122 16:33:56.773494 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 16:33:56.773542 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3124 16:33:56.773589 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3125 16:33:56.773636
3126 16:33:56.773683 CA PerBit enable=1, Macro0, CA PI delay=33
3127 16:33:56.773730
3128 16:33:56.773776 [CBTSetCACLKResult] CA Dly = 33
3129 16:33:56.773823 CS Dly: 7 (0~40)
3130 16:33:56.773870
3131 16:33:56.773917 ----->DramcWriteLeveling(PI) begin...
3132 16:33:56.773965 ==
3133 16:33:56.774011 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 16:33:56.774059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 16:33:56.774106 ==
3136 16:33:56.774153 Write leveling (Byte 0): 26 => 26
3137 16:33:56.774200 Write leveling (Byte 1): 28 => 28
3138 16:33:56.774247 DramcWriteLeveling(PI) end<-----
3139 16:33:56.774294
3140 16:33:56.774341 ==
3141 16:33:56.774577 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 16:33:56.774630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 16:33:56.774679 ==
3144 16:33:56.774726 [Gating] SW mode calibration
3145 16:33:56.774774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3146 16:33:56.774822 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3147 16:33:56.774870 0 15 0 | B1->B0 | 2827 2828 | 1 0 | (0 0) (0 0)
3148 16:33:56.774918 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 16:33:56.774966 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 16:33:56.775013 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 16:33:56.775061 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 16:33:56.775109 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 16:33:56.775155 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3154 16:33:56.775202 0 15 28 | B1->B0 | 2d2d 3232 | 1 1 | (1 1) (1 0)
3155 16:33:56.775249 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3156 16:33:56.775296 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 16:33:56.775343 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 16:33:56.775390 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 16:33:56.775438 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 16:33:56.775485 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 16:33:56.775532 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 16:33:56.775579 1 0 28 | B1->B0 | 4141 3635 | 0 1 | (0 0) (1 1)
3163 16:33:56.775625 1 1 0 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
3164 16:33:56.775672 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 16:33:56.775719 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 16:33:56.775767 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 16:33:56.775830 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 16:33:56.775895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 16:33:56.775945 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 16:33:56.775994 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3171 16:33:56.776041 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3172 16:33:56.776088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 16:33:56.776135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 16:33:56.776183 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 16:33:56.776229 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 16:33:56.776275 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 16:33:56.776322 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 16:33:56.776369 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 16:33:56.776416 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 16:33:56.776463 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 16:33:56.776510 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 16:33:56.776556 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 16:33:56.776604 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 16:33:56.776677 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 16:33:56.776774 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3186 16:33:56.776822 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3187 16:33:56.776871 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 16:33:56.776918 Total UI for P1: 0, mck2ui 16
3189 16:33:56.776966 best dqsien dly found for B0: ( 1, 3, 26)
3190 16:33:56.777013 Total UI for P1: 0, mck2ui 16
3191 16:33:56.777060 best dqsien dly found for B1: ( 1, 3, 28)
3192 16:33:56.777125 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3193 16:33:56.777223 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3194 16:33:56.777314
3195 16:33:56.777393 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3196 16:33:56.777499 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3197 16:33:56.777574 [Gating] SW calibration Done
3198 16:33:56.777648 ==
3199 16:33:56.777724 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 16:33:56.777832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 16:33:56.777943 ==
3202 16:33:56.778020 RX Vref Scan: 0
3203 16:33:56.778096
3204 16:33:56.778187 RX Vref 0 -> 0, step: 1
3205 16:33:56.778277
3206 16:33:56.778353 RX Delay -40 -> 252, step: 8
3207 16:33:56.778428 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3208 16:33:56.778504 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3209 16:33:56.778612 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3210 16:33:56.778705 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3211 16:33:56.778797 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3212 16:33:56.778874 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3213 16:33:56.778949 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3214 16:33:56.779024 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3215 16:33:56.779116 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3216 16:33:56.779207 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3217 16:33:56.779284 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3218 16:33:56.779359 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3219 16:33:56.779464 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3220 16:33:56.779541 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3221 16:33:56.779648 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3222 16:33:56.779699 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3223 16:33:56.779749 ==
3224 16:33:56.779796 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 16:33:56.779844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 16:33:56.779906 ==
3227 16:33:56.779971 DQS Delay:
3228 16:33:56.780076 DQS0 = 0, DQS1 = 0
3229 16:33:56.780153 DQM Delay:
3230 16:33:56.780228 DQM0 = 114, DQM1 = 105
3231 16:33:56.780302 DQ Delay:
3232 16:33:56.780377 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3233 16:33:56.780452 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3234 16:33:56.780526 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3235 16:33:56.780622 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3236 16:33:56.780692
3237 16:33:56.780782
3238 16:33:56.780855 ==
3239 16:33:56.780930 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 16:33:56.781005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 16:33:56.781080 ==
3242 16:33:56.781154
3243 16:33:56.781278
3244 16:33:56.781368 TX Vref Scan disable
3245 16:33:56.781444 == TX Byte 0 ==
3246 16:33:56.781741 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3247 16:33:56.781842 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3248 16:33:56.781935 == TX Byte 1 ==
3249 16:33:56.782011 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3250 16:33:56.782087 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3251 16:33:56.782161 ==
3252 16:33:56.782269 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 16:33:56.782346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 16:33:56.782435 ==
3255 16:33:56.782527 TX Vref=22, minBit 1, minWin=24, winSum=408
3256 16:33:56.782605 TX Vref=24, minBit 1, minWin=24, winSum=411
3257 16:33:56.782697 TX Vref=26, minBit 1, minWin=25, winSum=413
3258 16:33:56.782788 TX Vref=28, minBit 3, minWin=25, winSum=419
3259 16:33:56.782865 TX Vref=30, minBit 2, minWin=25, winSum=420
3260 16:33:56.782941 TX Vref=32, minBit 1, minWin=25, winSum=418
3261 16:33:56.783047 [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 30
3262 16:33:56.783123
3263 16:33:56.783198 Final TX Range 1 Vref 30
3264 16:33:56.783272
3265 16:33:56.783376 ==
3266 16:33:56.783482 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 16:33:56.783560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 16:33:56.783635 ==
3269 16:33:56.783738
3270 16:33:56.783829
3271 16:33:56.783937 TX Vref Scan disable
3272 16:33:56.784014 == TX Byte 0 ==
3273 16:33:56.784090 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3274 16:33:56.784165 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3275 16:33:56.784239 == TX Byte 1 ==
3276 16:33:56.784314 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3277 16:33:56.784391 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3278 16:33:56.784465
3279 16:33:56.784539 [DATLAT]
3280 16:33:56.784614 Freq=1200, CH1 RK0
3281 16:33:56.784728
3282 16:33:56.784804 DATLAT Default: 0xd
3283 16:33:56.784881 0, 0xFFFF, sum = 0
3284 16:33:56.784961 1, 0xFFFF, sum = 0
3285 16:33:56.785038 2, 0xFFFF, sum = 0
3286 16:33:56.785115 3, 0xFFFF, sum = 0
3287 16:33:56.785191 4, 0xFFFF, sum = 0
3288 16:33:56.785267 5, 0xFFFF, sum = 0
3289 16:33:56.785374 6, 0xFFFF, sum = 0
3290 16:33:56.785439 7, 0xFFFF, sum = 0
3291 16:33:56.785488 8, 0xFFFF, sum = 0
3292 16:33:56.785585 9, 0xFFFF, sum = 0
3293 16:33:56.785646 10, 0xFFFF, sum = 0
3294 16:33:56.785711 11, 0xFFFF, sum = 0
3295 16:33:56.785760 12, 0x0, sum = 1
3296 16:33:56.785822 13, 0x0, sum = 2
3297 16:33:56.785886 14, 0x0, sum = 3
3298 16:33:56.785947 15, 0x0, sum = 4
3299 16:33:56.786009 best_step = 13
3300 16:33:56.786069
3301 16:33:56.786129 ==
3302 16:33:56.786195 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 16:33:56.786245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 16:33:56.786321 ==
3305 16:33:56.786368 RX Vref Scan: 1
3306 16:33:56.786428
3307 16:33:56.786488 Set Vref Range= 32 -> 127
3308 16:33:56.786551
3309 16:33:56.786598 RX Vref 32 -> 127, step: 1
3310 16:33:56.786645
3311 16:33:56.786706 RX Delay -21 -> 252, step: 4
3312 16:33:56.786751
3313 16:33:56.786811 Set Vref, RX VrefLevel [Byte0]: 32
3314 16:33:56.786876 [Byte1]: 32
3315 16:33:56.786926
3316 16:33:56.786973 Set Vref, RX VrefLevel [Byte0]: 33
3317 16:33:56.787020 [Byte1]: 33
3318 16:33:56.787066
3319 16:33:56.787112 Set Vref, RX VrefLevel [Byte0]: 34
3320 16:33:56.787159 [Byte1]: 34
3321 16:33:56.787205
3322 16:33:56.787250 Set Vref, RX VrefLevel [Byte0]: 35
3323 16:33:56.787296 [Byte1]: 35
3324 16:33:56.787358
3325 16:33:56.787423 Set Vref, RX VrefLevel [Byte0]: 36
3326 16:33:56.787472 [Byte1]: 36
3327 16:33:56.787522
3328 16:33:56.787568 Set Vref, RX VrefLevel [Byte0]: 37
3329 16:33:56.787615 [Byte1]: 37
3330 16:33:56.787661
3331 16:33:56.787707 Set Vref, RX VrefLevel [Byte0]: 38
3332 16:33:56.787753 [Byte1]: 38
3333 16:33:56.787799
3334 16:33:56.787845 Set Vref, RX VrefLevel [Byte0]: 39
3335 16:33:56.787890 [Byte1]: 39
3336 16:33:56.787950
3337 16:33:56.788013 Set Vref, RX VrefLevel [Byte0]: 40
3338 16:33:56.788064 [Byte1]: 40
3339 16:33:56.788110
3340 16:33:56.788155 Set Vref, RX VrefLevel [Byte0]: 41
3341 16:33:56.788202 [Byte1]: 41
3342 16:33:56.788248
3343 16:33:56.788293 Set Vref, RX VrefLevel [Byte0]: 42
3344 16:33:56.788338 [Byte1]: 42
3345 16:33:56.788384
3346 16:33:56.788429 Set Vref, RX VrefLevel [Byte0]: 43
3347 16:33:56.788501 [Byte1]: 43
3348 16:33:56.788578
3349 16:33:56.788658 Set Vref, RX VrefLevel [Byte0]: 44
3350 16:33:56.788722 [Byte1]: 44
3351 16:33:56.788768
3352 16:33:56.788814 Set Vref, RX VrefLevel [Byte0]: 45
3353 16:33:56.788860 [Byte1]: 45
3354 16:33:56.788906
3355 16:33:56.788952 Set Vref, RX VrefLevel [Byte0]: 46
3356 16:33:56.788999 [Byte1]: 46
3357 16:33:56.789045
3358 16:33:56.789091 Set Vref, RX VrefLevel [Byte0]: 47
3359 16:33:56.789137 [Byte1]: 47
3360 16:33:56.789182
3361 16:33:56.789229 Set Vref, RX VrefLevel [Byte0]: 48
3362 16:33:56.789275 [Byte1]: 48
3363 16:33:56.789321
3364 16:33:56.789424 Set Vref, RX VrefLevel [Byte0]: 49
3365 16:33:56.789491 [Byte1]: 49
3366 16:33:56.789553
3367 16:33:56.789599 Set Vref, RX VrefLevel [Byte0]: 50
3368 16:33:56.789645 [Byte1]: 50
3369 16:33:56.789692
3370 16:33:56.789737 Set Vref, RX VrefLevel [Byte0]: 51
3371 16:33:56.789783 [Byte1]: 51
3372 16:33:56.789829
3373 16:33:56.789875 Set Vref, RX VrefLevel [Byte0]: 52
3374 16:33:56.789921 [Byte1]: 52
3375 16:33:56.789967
3376 16:33:56.790013 Set Vref, RX VrefLevel [Byte0]: 53
3377 16:33:56.790059 [Byte1]: 53
3378 16:33:56.790105
3379 16:33:56.790154 Set Vref, RX VrefLevel [Byte0]: 54
3380 16:33:56.790202 [Byte1]: 54
3381 16:33:56.790267
3382 16:33:56.790352 Set Vref, RX VrefLevel [Byte0]: 55
3383 16:33:56.790418 [Byte1]: 55
3384 16:33:56.790465
3385 16:33:56.790544 Set Vref, RX VrefLevel [Byte0]: 56
3386 16:33:56.790594 [Byte1]: 56
3387 16:33:56.790647
3388 16:33:56.790721 Set Vref, RX VrefLevel [Byte0]: 57
3389 16:33:56.790798 [Byte1]: 57
3390 16:33:56.790872
3391 16:33:56.790946 Set Vref, RX VrefLevel [Byte0]: 58
3392 16:33:56.791020 [Byte1]: 58
3393 16:33:56.791094
3394 16:33:56.791168 Set Vref, RX VrefLevel [Byte0]: 59
3395 16:33:56.791242 [Byte1]: 59
3396 16:33:56.791315
3397 16:33:56.791389 Set Vref, RX VrefLevel [Byte0]: 60
3398 16:33:56.791479 [Byte1]: 60
3399 16:33:56.791554
3400 16:33:56.791630 Set Vref, RX VrefLevel [Byte0]: 61
3401 16:33:56.791706 [Byte1]: 61
3402 16:33:56.791781
3403 16:33:56.791857 Set Vref, RX VrefLevel [Byte0]: 62
3404 16:33:56.791933 [Byte1]: 62
3405 16:33:56.792008
3406 16:33:56.792084 Set Vref, RX VrefLevel [Byte0]: 63
3407 16:33:56.792160 [Byte1]: 63
3408 16:33:56.792235
3409 16:33:56.792313 Set Vref, RX VrefLevel [Byte0]: 64
3410 16:33:56.792585 [Byte1]: 64
3411 16:33:56.792669
3412 16:33:56.792721 Set Vref, RX VrefLevel [Byte0]: 65
3413 16:33:56.792769 [Byte1]: 65
3414 16:33:56.792818
3415 16:33:56.792866 Set Vref, RX VrefLevel [Byte0]: 66
3416 16:33:56.792915 [Byte1]: 66
3417 16:33:56.792962
3418 16:33:56.793010 Set Vref, RX VrefLevel [Byte0]: 67
3419 16:33:56.793058 [Byte1]: 67
3420 16:33:56.793105
3421 16:33:56.793152 Final RX Vref Byte 0 = 57 to rank0
3422 16:33:56.793201 Final RX Vref Byte 1 = 48 to rank0
3423 16:33:56.793249 Final RX Vref Byte 0 = 57 to rank1
3424 16:33:56.793296 Final RX Vref Byte 1 = 48 to rank1==
3425 16:33:56.793343 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 16:33:56.793400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 16:33:56.793474 ==
3428 16:33:56.793547 DQS Delay:
3429 16:33:56.793595 DQS0 = 0, DQS1 = 0
3430 16:33:56.793643 DQM Delay:
3431 16:33:56.793691 DQM0 = 115, DQM1 = 106
3432 16:33:56.793738 DQ Delay:
3433 16:33:56.793785 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3434 16:33:56.793832 DQ4 =114, DQ5 =122, DQ6 =126, DQ7 =114
3435 16:33:56.793879 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =100
3436 16:33:56.793926 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =112
3437 16:33:56.793973
3438 16:33:56.794020
3439 16:33:56.794066 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3440 16:33:56.794115 CH1 RK0: MR19=303, MR18=EEF5
3441 16:33:56.794162 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3442 16:33:56.794210
3443 16:33:56.794257 ----->DramcWriteLeveling(PI) begin...
3444 16:33:56.794306 ==
3445 16:33:56.794354 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 16:33:56.794402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 16:33:56.794450 ==
3448 16:33:56.794505 Write leveling (Byte 0): 23 => 23
3449 16:33:56.794584 Write leveling (Byte 1): 27 => 27
3450 16:33:56.794660 DramcWriteLeveling(PI) end<-----
3451 16:33:56.794735
3452 16:33:56.794810 ==
3453 16:33:56.794887 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 16:33:56.794964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 16:33:56.795040 ==
3456 16:33:56.795116 [Gating] SW mode calibration
3457 16:33:56.795193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 16:33:56.795270 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 16:33:56.795348 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 16:33:56.795425 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 16:33:56.795502 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 16:33:56.795580 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 16:33:56.795661 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 16:33:56.795714 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 16:33:56.795762 0 15 24 | B1->B0 | 3333 2424 | 1 0 | (1 1) (1 0)
3466 16:33:56.795810 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3467 16:33:56.795858 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 16:33:56.795905 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 16:33:56.795952 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 16:33:56.796000 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 16:33:56.796048 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 16:33:56.796095 1 0 20 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
3473 16:33:56.796143 1 0 24 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
3474 16:33:56.796190 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 16:33:56.796237 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 16:33:56.796285 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 16:33:56.796332 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 16:33:56.796378 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 16:33:56.796426 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 16:33:56.796474 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3481 16:33:56.796522 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3482 16:33:56.796569 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3483 16:33:56.796618 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 16:33:56.796686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 16:33:56.796736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 16:33:56.796783 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 16:33:56.796831 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 16:33:56.796879 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 16:33:56.796927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 16:33:56.796975 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 16:33:56.797022 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 16:33:56.797069 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 16:33:56.797117 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 16:33:56.797164 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 16:33:56.797212 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 16:33:56.797259 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3497 16:33:56.797306 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3498 16:33:56.797354 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 16:33:56.797409 Total UI for P1: 0, mck2ui 16
3500 16:33:56.797458 best dqsien dly found for B0: ( 1, 3, 22)
3501 16:33:56.797506 Total UI for P1: 0, mck2ui 16
3502 16:33:56.797554 best dqsien dly found for B1: ( 1, 3, 24)
3503 16:33:56.797601 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3504 16:33:56.797648 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3505 16:33:56.797695
3506 16:33:56.797743 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3507 16:33:56.797790 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3508 16:33:56.797838 [Gating] SW calibration Done
3509 16:33:56.797886 ==
3510 16:33:56.797933 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 16:33:56.797981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 16:33:56.798028 ==
3513 16:33:56.798075 RX Vref Scan: 0
3514 16:33:56.798122
3515 16:33:56.798169 RX Vref 0 -> 0, step: 1
3516 16:33:56.798216
3517 16:33:56.798263 RX Delay -40 -> 252, step: 8
3518 16:33:56.798310 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3519 16:33:56.798358 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3520 16:33:56.798598 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3521 16:33:56.798655 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3522 16:33:56.798705 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3523 16:33:56.798752 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3524 16:33:56.798800 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3525 16:33:56.798848 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3526 16:33:56.798895 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3527 16:33:56.798943 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3528 16:33:56.798990 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3529 16:33:56.799038 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3530 16:33:56.799086 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3531 16:33:56.799134 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3532 16:33:56.799182 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3533 16:33:56.799230 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3534 16:33:56.799282 ==
3535 16:33:56.799333 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 16:33:56.799384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 16:33:56.799446 ==
3538 16:33:56.799497 DQS Delay:
3539 16:33:56.799545 DQS0 = 0, DQS1 = 0
3540 16:33:56.799597 DQM Delay:
3541 16:33:56.799648 DQM0 = 111, DQM1 = 109
3542 16:33:56.799696 DQ Delay:
3543 16:33:56.799744 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3544 16:33:56.799818 DQ4 =107, DQ5 =123, DQ6 =123, DQ7 =111
3545 16:33:56.799895 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3546 16:33:56.799972 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3547 16:33:56.800049
3548 16:33:56.800126
3549 16:33:56.800204 ==
3550 16:33:56.800281 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 16:33:56.800358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 16:33:56.800434 ==
3553 16:33:56.800510
3554 16:33:56.800585
3555 16:33:56.800668 TX Vref Scan disable
3556 16:33:56.800745 == TX Byte 0 ==
3557 16:33:56.800822 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3558 16:33:56.800899 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3559 16:33:56.800975 == TX Byte 1 ==
3560 16:33:56.801051 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3561 16:33:56.801128 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3562 16:33:56.801203 ==
3563 16:33:56.801279 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 16:33:56.801356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 16:33:56.801432 ==
3566 16:33:56.801508 TX Vref=22, minBit 0, minWin=25, winSum=413
3567 16:33:56.801586 TX Vref=24, minBit 1, minWin=25, winSum=421
3568 16:33:56.801663 TX Vref=26, minBit 3, minWin=25, winSum=423
3569 16:33:56.801740 TX Vref=28, minBit 1, minWin=25, winSum=423
3570 16:33:56.801805 TX Vref=30, minBit 1, minWin=25, winSum=423
3571 16:33:56.801857 TX Vref=32, minBit 1, minWin=25, winSum=416
3572 16:33:56.801907 [TxChooseVref] Worse bit 3, Min win 25, Win sum 423, Final Vref 26
3573 16:33:56.801958
3574 16:33:56.802007 Final TX Range 1 Vref 26
3575 16:33:56.802084
3576 16:33:56.802159 ==
3577 16:33:56.802236 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 16:33:56.802312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 16:33:56.802389 ==
3580 16:33:56.802464
3581 16:33:56.802525
3582 16:33:56.802577 TX Vref Scan disable
3583 16:33:56.802625 == TX Byte 0 ==
3584 16:33:56.802672 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3585 16:33:56.802720 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3586 16:33:56.802767 == TX Byte 1 ==
3587 16:33:56.802814 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3588 16:33:56.802861 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3589 16:33:56.802908
3590 16:33:56.802955 [DATLAT]
3591 16:33:56.803001 Freq=1200, CH1 RK1
3592 16:33:56.803048
3593 16:33:56.803100 DATLAT Default: 0xd
3594 16:33:56.803151 0, 0xFFFF, sum = 0
3595 16:33:56.803199 1, 0xFFFF, sum = 0
3596 16:33:56.803248 2, 0xFFFF, sum = 0
3597 16:33:56.803295 3, 0xFFFF, sum = 0
3598 16:33:56.803343 4, 0xFFFF, sum = 0
3599 16:33:56.803395 5, 0xFFFF, sum = 0
3600 16:33:56.803463 6, 0xFFFF, sum = 0
3601 16:33:56.803548 7, 0xFFFF, sum = 0
3602 16:33:56.803605 8, 0xFFFF, sum = 0
3603 16:33:56.803657 9, 0xFFFF, sum = 0
3604 16:33:56.803706 10, 0xFFFF, sum = 0
3605 16:33:56.803755 11, 0xFFFF, sum = 0
3606 16:33:56.803803 12, 0x0, sum = 1
3607 16:33:56.803851 13, 0x0, sum = 2
3608 16:33:56.803899 14, 0x0, sum = 3
3609 16:33:56.803947 15, 0x0, sum = 4
3610 16:33:56.803995 best_step = 13
3611 16:33:56.804042
3612 16:33:56.804093 ==
3613 16:33:56.804146 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 16:33:56.804194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 16:33:56.804242 ==
3616 16:33:56.804289 RX Vref Scan: 0
3617 16:33:56.804336
3618 16:33:56.804383 RX Vref 0 -> 0, step: 1
3619 16:33:56.804431
3620 16:33:56.804479 RX Delay -21 -> 252, step: 4
3621 16:33:56.804527 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3622 16:33:56.804575 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3623 16:33:56.804623 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3624 16:33:56.804680 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3625 16:33:56.804728 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3626 16:33:56.804775 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3627 16:33:56.804822 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3628 16:33:56.804870 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3629 16:33:56.804917 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3630 16:33:56.804965 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3631 16:33:56.805015 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3632 16:33:56.805064 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3633 16:33:56.805113 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3634 16:33:56.805161 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3635 16:33:56.805208 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3636 16:33:56.805255 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3637 16:33:56.805302 ==
3638 16:33:56.805349 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 16:33:56.805397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 16:33:56.805444 ==
3641 16:33:56.805492 DQS Delay:
3642 16:33:56.805542 DQS0 = 0, DQS1 = 0
3643 16:33:56.805591 DQM Delay:
3644 16:33:56.805641 DQM0 = 111, DQM1 = 109
3645 16:33:56.805688 DQ Delay:
3646 16:33:56.805735 DQ0 =116, DQ1 =108, DQ2 =100, DQ3 =110
3647 16:33:56.805782 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =110
3648 16:33:56.805829 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =106
3649 16:33:56.805876 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3650 16:33:56.805924
3651 16:33:56.805971
3652 16:33:56.806018 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3653 16:33:56.806072 CH1 RK1: MR19=304, MR18=FB0B
3654 16:33:56.806123 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3655 16:33:56.806172 [RxdqsGatingPostProcess] freq 1200
3656 16:33:56.806219 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 16:33:56.806460 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 16:33:56.806520 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 16:33:56.806577 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 16:33:56.806627 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 16:33:56.806679 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 16:33:56.806760 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 16:33:56.806844 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 16:33:56.806924 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 16:33:56.807006 Pre-setting of DQS Precalculation
3666 16:33:56.807089 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 16:33:56.807171 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 16:33:56.807254 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 16:33:56.807333
3670 16:33:56.807414
3671 16:33:56.807492 [Calibration Summary] 2400 Mbps
3672 16:33:56.807572 CH 0, Rank 0
3673 16:33:56.807654 SW Impedance : PASS
3674 16:33:56.807734 DUTY Scan : NO K
3675 16:33:56.807816 ZQ Calibration : PASS
3676 16:33:56.807895 Jitter Meter : NO K
3677 16:33:56.807976 CBT Training : PASS
3678 16:33:56.808052 Write leveling : PASS
3679 16:33:56.808127 RX DQS gating : PASS
3680 16:33:56.808207 RX DQ/DQS(RDDQC) : PASS
3681 16:33:56.808283 TX DQ/DQS : PASS
3682 16:33:56.808365 RX DATLAT : PASS
3683 16:33:56.808445 RX DQ/DQS(Engine): PASS
3684 16:33:56.808525 TX OE : NO K
3685 16:33:56.808607 All Pass.
3686 16:33:56.808695
3687 16:33:56.808776 CH 0, Rank 1
3688 16:33:56.808858 SW Impedance : PASS
3689 16:33:56.808942 DUTY Scan : NO K
3690 16:33:56.809022 ZQ Calibration : PASS
3691 16:33:56.809104 Jitter Meter : NO K
3692 16:33:56.809185 CBT Training : PASS
3693 16:33:56.809275 Write leveling : PASS
3694 16:33:56.809372 RX DQS gating : PASS
3695 16:33:56.809466 RX DQ/DQS(RDDQC) : PASS
3696 16:33:56.809557 TX DQ/DQS : PASS
3697 16:33:56.809657 RX DATLAT : PASS
3698 16:33:56.809744 RX DQ/DQS(Engine): PASS
3699 16:33:56.809824 TX OE : NO K
3700 16:33:56.809894 All Pass.
3701 16:33:56.809944
3702 16:33:56.809992 CH 1, Rank 0
3703 16:33:56.810046 SW Impedance : PASS
3704 16:33:56.810107 DUTY Scan : NO K
3705 16:33:56.810160 ZQ Calibration : PASS
3706 16:33:56.810213 Jitter Meter : NO K
3707 16:33:56.810287 CBT Training : PASS
3708 16:33:56.810374 Write leveling : PASS
3709 16:33:56.810460 RX DQS gating : PASS
3710 16:33:56.810545 RX DQ/DQS(RDDQC) : PASS
3711 16:33:56.810635 TX DQ/DQS : PASS
3712 16:33:56.810723 RX DATLAT : PASS
3713 16:33:56.810810 RX DQ/DQS(Engine): PASS
3714 16:33:56.810896 TX OE : NO K
3715 16:33:56.810983 All Pass.
3716 16:33:56.811074
3717 16:33:56.811161 CH 1, Rank 1
3718 16:33:56.811248 SW Impedance : PASS
3719 16:33:56.811336 DUTY Scan : NO K
3720 16:33:56.811419 ZQ Calibration : PASS
3721 16:33:56.811506 Jitter Meter : NO K
3722 16:33:56.811596 CBT Training : PASS
3723 16:33:56.811682 Write leveling : PASS
3724 16:33:56.811768 RX DQS gating : PASS
3725 16:33:56.811855 RX DQ/DQS(RDDQC) : PASS
3726 16:33:56.811941 TX DQ/DQS : PASS
3727 16:33:56.812029 RX DATLAT : PASS
3728 16:33:56.812114 RX DQ/DQS(Engine): PASS
3729 16:33:56.812202 TX OE : NO K
3730 16:33:56.812290 All Pass.
3731 16:33:56.812372
3732 16:33:56.812457 DramC Write-DBI off
3733 16:33:56.812539 PER_BANK_REFRESH: Hybrid Mode
3734 16:33:56.812622 TX_TRACKING: ON
3735 16:33:56.812711 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 16:33:56.812793 [FAST_K] Save calibration result to emmc
3737 16:33:56.812875 dramc_set_vcore_voltage set vcore to 650000
3738 16:33:56.812963 Read voltage for 600, 5
3739 16:33:56.813045 Vio18 = 0
3740 16:33:56.813132 Vcore = 650000
3741 16:33:56.813216 Vdram = 0
3742 16:33:56.813301 Vddq = 0
3743 16:33:56.813381 Vmddr = 0
3744 16:33:56.813465 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 16:33:56.813550 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 16:33:56.813636 MEM_TYPE=3, freq_sel=19
3747 16:33:56.813718 sv_algorithm_assistance_LP4_1600
3748 16:33:56.813803 ============ PULL DRAM RESETB DOWN ============
3749 16:33:56.813885 ========== PULL DRAM RESETB DOWN end =========
3750 16:33:56.813970 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 16:33:56.814054 ===================================
3752 16:33:56.814138 LPDDR4 DRAM CONFIGURATION
3753 16:33:56.814221 ===================================
3754 16:33:56.814305 EX_ROW_EN[0] = 0x0
3755 16:33:56.814386 EX_ROW_EN[1] = 0x0
3756 16:33:56.814470 LP4Y_EN = 0x0
3757 16:33:56.814551 WORK_FSP = 0x0
3758 16:33:56.814634 WL = 0x2
3759 16:33:56.814716 RL = 0x2
3760 16:33:56.814799 BL = 0x2
3761 16:33:56.814882 RPST = 0x0
3762 16:33:56.814966 RD_PRE = 0x0
3763 16:33:56.815048 WR_PRE = 0x1
3764 16:33:56.815132 WR_PST = 0x0
3765 16:33:56.815213 DBI_WR = 0x0
3766 16:33:56.815298 DBI_RD = 0x0
3767 16:33:56.815379 OTF = 0x1
3768 16:33:56.815464 ===================================
3769 16:33:56.815547 ===================================
3770 16:33:56.815635 ANA top config
3771 16:33:56.815719 ===================================
3772 16:33:56.815806 DLL_ASYNC_EN = 0
3773 16:33:56.815887 ALL_SLAVE_EN = 1
3774 16:33:56.815964 NEW_RANK_MODE = 1
3775 16:33:56.816042 DLL_IDLE_MODE = 1
3776 16:33:56.816121 LP45_APHY_COMB_EN = 1
3777 16:33:56.816204 TX_ODT_DIS = 1
3778 16:33:56.816287 NEW_8X_MODE = 1
3779 16:33:56.816370 ===================================
3780 16:33:56.816455 ===================================
3781 16:33:56.816539 data_rate = 1200
3782 16:33:56.816622 CKR = 1
3783 16:33:56.816710 DQ_P2S_RATIO = 8
3784 16:33:56.816793 ===================================
3785 16:33:56.816876 CA_P2S_RATIO = 8
3786 16:33:56.816960 DQ_CA_OPEN = 0
3787 16:33:56.817043 DQ_SEMI_OPEN = 0
3788 16:33:56.817128 CA_SEMI_OPEN = 0
3789 16:33:56.817209 CA_FULL_RATE = 0
3790 16:33:56.817291 DQ_CKDIV4_EN = 1
3791 16:33:56.817370 CA_CKDIV4_EN = 1
3792 16:33:56.817451 CA_PREDIV_EN = 0
3793 16:33:56.817532 PH8_DLY = 0
3794 16:33:56.817613 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 16:33:56.817694 DQ_AAMCK_DIV = 4
3796 16:33:56.817777 CA_AAMCK_DIV = 4
3797 16:33:56.817859 CA_ADMCK_DIV = 4
3798 16:33:56.817942 DQ_TRACK_CA_EN = 0
3799 16:33:56.818022 CA_PICK = 600
3800 16:33:56.818109 CA_MCKIO = 600
3801 16:33:56.818194 MCKIO_SEMI = 0
3802 16:33:56.818274 PLL_FREQ = 2288
3803 16:33:56.818547 DQ_UI_PI_RATIO = 32
3804 16:33:56.818631 CA_UI_PI_RATIO = 0
3805 16:33:56.818714 ===================================
3806 16:33:56.818798 ===================================
3807 16:33:56.818880 memory_type:LPDDR4
3808 16:33:56.818961 GP_NUM : 10
3809 16:33:56.819043 SRAM_EN : 1
3810 16:33:56.819126 MD32_EN : 0
3811 16:33:56.819208 ===================================
3812 16:33:56.819288 [ANA_INIT] >>>>>>>>>>>>>>
3813 16:33:56.819369 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 16:33:56.819450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 16:33:56.819531 ===================================
3816 16:33:56.819614 data_rate = 1200,PCW = 0X5800
3817 16:33:56.819697 ===================================
3818 16:33:56.819778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 16:33:56.819860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 16:33:56.819944 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 16:33:56.820031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 16:33:56.820111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 16:33:56.820202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 16:33:56.820284 [ANA_INIT] flow start
3825 16:33:56.820366 [ANA_INIT] PLL >>>>>>>>
3826 16:33:56.820446 [ANA_INIT] PLL <<<<<<<<
3827 16:33:56.820527 [ANA_INIT] MIDPI >>>>>>>>
3828 16:33:56.820609 [ANA_INIT] MIDPI <<<<<<<<
3829 16:33:56.820700 [ANA_INIT] DLL >>>>>>>>
3830 16:33:56.820782 [ANA_INIT] flow end
3831 16:33:56.820864 ============ LP4 DIFF to SE enter ============
3832 16:33:56.820949 ============ LP4 DIFF to SE exit ============
3833 16:33:56.821032 [ANA_INIT] <<<<<<<<<<<<<
3834 16:33:56.821113 [Flow] Enable top DCM control >>>>>
3835 16:33:56.821193 [Flow] Enable top DCM control <<<<<
3836 16:33:56.821274 Enable DLL master slave shuffle
3837 16:33:56.821352 ==============================================================
3838 16:33:56.821432 Gating Mode config
3839 16:33:56.821514 ==============================================================
3840 16:33:56.821599 Config description:
3841 16:33:56.821683 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 16:33:56.821768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 16:33:56.821851 SELPH_MODE 0: By rank 1: By Phase
3844 16:33:56.821935 ==============================================================
3845 16:33:56.822023 GAT_TRACK_EN = 1
3846 16:33:56.822106 RX_GATING_MODE = 2
3847 16:33:56.822193 RX_GATING_TRACK_MODE = 2
3848 16:33:56.822273 SELPH_MODE = 1
3849 16:33:56.822349 PICG_EARLY_EN = 1
3850 16:33:56.822438 VALID_LAT_VALUE = 1
3851 16:33:56.826757 ==============================================================
3852 16:33:56.830111 Enter into Gating configuration >>>>
3853 16:33:56.833533 Exit from Gating configuration <<<<
3854 16:33:56.836857 Enter into DVFS_PRE_config >>>>>
3855 16:33:56.846557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 16:33:56.850300 Exit from DVFS_PRE_config <<<<<
3857 16:33:56.853176 Enter into PICG configuration >>>>
3858 16:33:56.856521 Exit from PICG configuration <<<<
3859 16:33:56.859952 [RX_INPUT] configuration >>>>>
3860 16:33:56.863043 [RX_INPUT] configuration <<<<<
3861 16:33:56.866815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 16:33:56.873249 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 16:33:56.879500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 16:33:56.886392 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 16:33:56.893240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 16:33:56.896143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 16:33:56.903097 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 16:33:56.906052 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 16:33:56.909656 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 16:33:56.913161 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 16:33:56.919832 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 16:33:56.922857 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 16:33:56.926017 ===================================
3874 16:33:56.929636 LPDDR4 DRAM CONFIGURATION
3875 16:33:56.933093 ===================================
3876 16:33:56.933186 EX_ROW_EN[0] = 0x0
3877 16:33:56.936114 EX_ROW_EN[1] = 0x0
3878 16:33:56.936209 LP4Y_EN = 0x0
3879 16:33:56.939556 WORK_FSP = 0x0
3880 16:33:56.939651 WL = 0x2
3881 16:33:56.942571 RL = 0x2
3882 16:33:56.942664 BL = 0x2
3883 16:33:56.945885 RPST = 0x0
3884 16:33:56.949482 RD_PRE = 0x0
3885 16:33:56.949580 WR_PRE = 0x1
3886 16:33:56.952546 WR_PST = 0x0
3887 16:33:56.952656 DBI_WR = 0x0
3888 16:33:56.956278 DBI_RD = 0x0
3889 16:33:56.956385 OTF = 0x1
3890 16:33:56.959319 ===================================
3891 16:33:56.962736 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 16:33:56.969122 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 16:33:56.972689 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 16:33:56.975781 ===================================
3895 16:33:56.978928 LPDDR4 DRAM CONFIGURATION
3896 16:33:56.982669 ===================================
3897 16:33:56.982822 EX_ROW_EN[0] = 0x10
3898 16:33:56.985692 EX_ROW_EN[1] = 0x0
3899 16:33:56.985806 LP4Y_EN = 0x0
3900 16:33:56.989363 WORK_FSP = 0x0
3901 16:33:56.989472 WL = 0x2
3902 16:33:56.992416 RL = 0x2
3903 16:33:56.992520 BL = 0x2
3904 16:33:56.995606 RPST = 0x0
3905 16:33:56.995710 RD_PRE = 0x0
3906 16:33:56.999327 WR_PRE = 0x1
3907 16:33:56.999411 WR_PST = 0x0
3908 16:33:57.002497 DBI_WR = 0x0
3909 16:33:57.005726 DBI_RD = 0x0
3910 16:33:57.005797 OTF = 0x1
3911 16:33:57.009222 ===================================
3912 16:33:57.015613 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 16:33:57.019463 nWR fixed to 30
3914 16:33:57.022454 [ModeRegInit_LP4] CH0 RK0
3915 16:33:57.022564 [ModeRegInit_LP4] CH0 RK1
3916 16:33:57.025522 [ModeRegInit_LP4] CH1 RK0
3917 16:33:57.029387 [ModeRegInit_LP4] CH1 RK1
3918 16:33:57.029479 match AC timing 17
3919 16:33:57.035658 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 16:33:57.038760 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 16:33:57.042435 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 16:33:57.048617 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 16:33:57.052316 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 16:33:57.052419 ==
3925 16:33:57.055801 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 16:33:57.058993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 16:33:57.059086 ==
3928 16:33:57.065355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 16:33:57.071828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3930 16:33:57.075223 [CA 0] Center 37 (7~67) winsize 61
3931 16:33:57.078850 [CA 1] Center 36 (6~67) winsize 62
3932 16:33:57.081828 [CA 2] Center 35 (5~65) winsize 61
3933 16:33:57.085361 [CA 3] Center 35 (5~65) winsize 61
3934 16:33:57.088580 [CA 4] Center 34 (4~65) winsize 62
3935 16:33:57.091911 [CA 5] Center 34 (4~64) winsize 61
3936 16:33:57.091995
3937 16:33:57.095118 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3938 16:33:57.095199
3939 16:33:57.098424 [CATrainingPosCal] consider 1 rank data
3940 16:33:57.102169 u2DelayCellTimex100 = 270/100 ps
3941 16:33:57.105532 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3942 16:33:57.108758 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3943 16:33:57.111958 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3944 16:33:57.115063 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 16:33:57.118767 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3946 16:33:57.125710 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3947 16:33:57.125849
3948 16:33:57.128770 CA PerBit enable=1, Macro0, CA PI delay=34
3949 16:33:57.128857
3950 16:33:57.131690 [CBTSetCACLKResult] CA Dly = 34
3951 16:33:57.131772 CS Dly: 5 (0~36)
3952 16:33:57.131833 ==
3953 16:33:57.135270 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 16:33:57.138305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 16:33:57.141494 ==
3956 16:33:57.145336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 16:33:57.151493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3958 16:33:57.155233 [CA 0] Center 37 (7~67) winsize 61
3959 16:33:57.158513 [CA 1] Center 37 (7~67) winsize 61
3960 16:33:57.161363 [CA 2] Center 35 (5~65) winsize 61
3961 16:33:57.164587 [CA 3] Center 35 (5~65) winsize 61
3962 16:33:57.168466 [CA 4] Center 34 (4~65) winsize 62
3963 16:33:57.171753 [CA 5] Center 33 (3~64) winsize 62
3964 16:33:57.171823
3965 16:33:57.174880 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3966 16:33:57.174959
3967 16:33:57.178409 [CATrainingPosCal] consider 2 rank data
3968 16:33:57.181420 u2DelayCellTimex100 = 270/100 ps
3969 16:33:57.185007 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3970 16:33:57.188022 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3971 16:33:57.191567 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3972 16:33:57.198394 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 16:33:57.201629 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3974 16:33:57.204783 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3975 16:33:57.204850
3976 16:33:57.208025 CA PerBit enable=1, Macro0, CA PI delay=34
3977 16:33:57.208091
3978 16:33:57.211192 [CBTSetCACLKResult] CA Dly = 34
3979 16:33:57.211263 CS Dly: 5 (0~37)
3980 16:33:57.211356
3981 16:33:57.214972 ----->DramcWriteLeveling(PI) begin...
3982 16:33:57.215066 ==
3983 16:33:57.218189 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 16:33:57.224814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 16:33:57.224913 ==
3986 16:33:57.228057 Write leveling (Byte 0): 34 => 34
3987 16:33:57.231342 Write leveling (Byte 1): 30 => 30
3988 16:33:57.234436 DramcWriteLeveling(PI) end<-----
3989 16:33:57.234552
3990 16:33:57.234613 ==
3991 16:33:57.238088 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 16:33:57.241171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 16:33:57.241280 ==
3994 16:33:57.244208 [Gating] SW mode calibration
3995 16:33:57.250936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 16:33:57.254177 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 16:33:57.260865 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 16:33:57.264420 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 16:33:57.268025 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 16:33:57.274384 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 16:33:57.277661 0 9 16 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
4002 16:33:57.280850 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 16:33:57.287481 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 16:33:57.291223 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 16:33:57.294452 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 16:33:57.301014 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 16:33:57.304117 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 16:33:57.307274 0 10 12 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (0 0)
4009 16:33:57.314416 0 10 16 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
4010 16:33:57.317506 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 16:33:57.320625 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 16:33:57.327403 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 16:33:57.330646 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 16:33:57.333813 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 16:33:57.340780 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 16:33:57.343815 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4017 16:33:57.346968 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4018 16:33:57.353908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4019 16:33:57.356903 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 16:33:57.360398 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 16:33:57.366856 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 16:33:57.369891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 16:33:57.373525 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 16:33:57.380335 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 16:33:57.383381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 16:33:57.386580 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 16:33:57.393416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 16:33:57.397055 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 16:33:57.400210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 16:33:57.406897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 16:33:57.409916 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 16:33:57.413158 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 16:33:57.419693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4034 16:33:57.419793 Total UI for P1: 0, mck2ui 16
4035 16:33:57.426843 best dqsien dly found for B0: ( 0, 13, 14)
4036 16:33:57.429958 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 16:33:57.433082 Total UI for P1: 0, mck2ui 16
4038 16:33:57.436304 best dqsien dly found for B1: ( 0, 13, 16)
4039 16:33:57.439473 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4040 16:33:57.443354 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4041 16:33:57.443437
4042 16:33:57.446528 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4043 16:33:57.449612 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4044 16:33:57.452657 [Gating] SW calibration Done
4045 16:33:57.452747 ==
4046 16:33:57.456526 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 16:33:57.459661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 16:33:57.462681 ==
4049 16:33:57.462768 RX Vref Scan: 0
4050 16:33:57.462830
4051 16:33:57.466143 RX Vref 0 -> 0, step: 1
4052 16:33:57.466226
4053 16:33:57.469062 RX Delay -230 -> 252, step: 16
4054 16:33:57.472731 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4055 16:33:57.475792 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4056 16:33:57.479296 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4057 16:33:57.485909 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4058 16:33:57.489090 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4059 16:33:57.492349 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4060 16:33:57.495946 iDelay=218, Bit 6, Center 41 (-118 ~ 201) 320
4061 16:33:57.502501 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4062 16:33:57.505707 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4063 16:33:57.508794 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4064 16:33:57.512496 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4065 16:33:57.515581 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4066 16:33:57.522137 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4067 16:33:57.525182 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4068 16:33:57.528900 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4069 16:33:57.531987 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4070 16:33:57.535057 ==
4071 16:33:57.538855 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 16:33:57.542025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 16:33:57.542103 ==
4074 16:33:57.542162 DQS Delay:
4075 16:33:57.545189 DQS0 = 0, DQS1 = 0
4076 16:33:57.545269 DQM Delay:
4077 16:33:57.549017 DQM0 = 36, DQM1 = 27
4078 16:33:57.549098 DQ Delay:
4079 16:33:57.552180 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4080 16:33:57.555335 DQ4 =41, DQ5 =17, DQ6 =41, DQ7 =49
4081 16:33:57.558578 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =25
4082 16:33:57.561726 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4083 16:33:57.561833
4084 16:33:57.561916
4085 16:33:57.561996 ==
4086 16:33:57.564899 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 16:33:57.568027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 16:33:57.568116 ==
4089 16:33:57.568237
4090 16:33:57.568315
4091 16:33:57.571809 TX Vref Scan disable
4092 16:33:57.574888 == TX Byte 0 ==
4093 16:33:57.578136 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4094 16:33:57.581645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4095 16:33:57.584728 == TX Byte 1 ==
4096 16:33:57.588328 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4097 16:33:57.591466 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4098 16:33:57.591544 ==
4099 16:33:57.594575 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 16:33:57.601569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 16:33:57.601650 ==
4102 16:33:57.601709
4103 16:33:57.601764
4104 16:33:57.601816 TX Vref Scan disable
4105 16:33:57.605832 == TX Byte 0 ==
4106 16:33:57.609209 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4107 16:33:57.615901 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4108 16:33:57.615985 == TX Byte 1 ==
4109 16:33:57.619174 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4110 16:33:57.625784 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4111 16:33:57.625908
4112 16:33:57.625988 [DATLAT]
4113 16:33:57.626072 Freq=600, CH0 RK0
4114 16:33:57.626162
4115 16:33:57.629063 DATLAT Default: 0x9
4116 16:33:57.629186 0, 0xFFFF, sum = 0
4117 16:33:57.632748 1, 0xFFFF, sum = 0
4118 16:33:57.635746 2, 0xFFFF, sum = 0
4119 16:33:57.635916 3, 0xFFFF, sum = 0
4120 16:33:57.638840 4, 0xFFFF, sum = 0
4121 16:33:57.638949 5, 0xFFFF, sum = 0
4122 16:33:57.642654 6, 0xFFFF, sum = 0
4123 16:33:57.642810 7, 0xFFFF, sum = 0
4124 16:33:57.645845 8, 0x0, sum = 1
4125 16:33:57.645997 9, 0x0, sum = 2
4126 16:33:57.646092 10, 0x0, sum = 3
4127 16:33:57.649089 11, 0x0, sum = 4
4128 16:33:57.649226 best_step = 9
4129 16:33:57.649337
4130 16:33:57.649450 ==
4131 16:33:57.652355 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 16:33:57.658850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 16:33:57.658949 ==
4134 16:33:57.659012 RX Vref Scan: 1
4135 16:33:57.659069
4136 16:33:57.662058 RX Vref 0 -> 0, step: 1
4137 16:33:57.662146
4138 16:33:57.665375 RX Delay -195 -> 252, step: 8
4139 16:33:57.665487
4140 16:33:57.668809 Set Vref, RX VrefLevel [Byte0]: 61
4141 16:33:57.671985 [Byte1]: 45
4142 16:33:57.672086
4143 16:33:57.675271 Final RX Vref Byte 0 = 61 to rank0
4144 16:33:57.678621 Final RX Vref Byte 1 = 45 to rank0
4145 16:33:57.682433 Final RX Vref Byte 0 = 61 to rank1
4146 16:33:57.685422 Final RX Vref Byte 1 = 45 to rank1==
4147 16:33:57.688547 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 16:33:57.692170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 16:33:57.692276 ==
4150 16:33:57.695797 DQS Delay:
4151 16:33:57.695882 DQS0 = 0, DQS1 = 0
4152 16:33:57.698740 DQM Delay:
4153 16:33:57.698821 DQM0 = 34, DQM1 = 28
4154 16:33:57.698882 DQ Delay:
4155 16:33:57.701942 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4156 16:33:57.705173 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4157 16:33:57.708399 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4158 16:33:57.712165 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4159 16:33:57.712252
4160 16:33:57.712314
4161 16:33:57.721753 [DQSOSCAuto] RK0, (LSB)MR18= 0x4241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4162 16:33:57.725429 CH0 RK0: MR19=808, MR18=4241
4163 16:33:57.731886 CH0_RK0: MR19=0x808, MR18=0x4241, DQSOSC=397, MR23=63, INC=166, DEC=110
4164 16:33:57.731983
4165 16:33:57.734945 ----->DramcWriteLeveling(PI) begin...
4166 16:33:57.735053 ==
4167 16:33:57.738214 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 16:33:57.741471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 16:33:57.741551 ==
4170 16:33:57.745395 Write leveling (Byte 0): 33 => 33
4171 16:33:57.748494 Write leveling (Byte 1): 33 => 33
4172 16:33:57.751686 DramcWriteLeveling(PI) end<-----
4173 16:33:57.751758
4174 16:33:57.751815 ==
4175 16:33:57.754887 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 16:33:57.758721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 16:33:57.758807 ==
4178 16:33:57.761973 [Gating] SW mode calibration
4179 16:33:57.768346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4180 16:33:57.774976 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4181 16:33:57.778133 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 16:33:57.781382 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 16:33:57.788441 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 16:33:57.791486 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4185 16:33:57.795225 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4186 16:33:57.801459 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 16:33:57.805016 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 16:33:57.808531 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 16:33:57.815234 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 16:33:57.818310 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 16:33:57.821566 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 16:33:57.828284 0 10 12 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
4193 16:33:57.831695 0 10 16 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
4194 16:33:57.835052 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 16:33:57.841084 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 16:33:57.844774 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 16:33:57.847961 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 16:33:57.854705 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 16:33:57.858016 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 16:33:57.861169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4201 16:33:57.867996 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 16:33:57.871097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 16:33:57.874260 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 16:33:57.877464 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 16:33:57.884379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 16:33:57.887459 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 16:33:57.891146 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 16:33:57.897516 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 16:33:57.900800 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 16:33:57.904493 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 16:33:57.911018 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 16:33:57.914108 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 16:33:57.917756 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 16:33:57.924258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 16:33:57.927311 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 16:33:57.931054 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4217 16:33:57.937202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 16:33:57.940633 Total UI for P1: 0, mck2ui 16
4219 16:33:57.943882 best dqsien dly found for B0: ( 0, 13, 12)
4220 16:33:57.947217 Total UI for P1: 0, mck2ui 16
4221 16:33:57.950467 best dqsien dly found for B1: ( 0, 13, 14)
4222 16:33:57.953640 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4223 16:33:57.957401 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4224 16:33:57.957612
4225 16:33:57.960712 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4226 16:33:57.963666 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4227 16:33:57.967490 [Gating] SW calibration Done
4228 16:33:57.967636 ==
4229 16:33:57.970712 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 16:33:57.973906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 16:33:57.974059 ==
4232 16:33:57.977122 RX Vref Scan: 0
4233 16:33:57.977263
4234 16:33:57.977380 RX Vref 0 -> 0, step: 1
4235 16:33:57.980890
4236 16:33:57.981011 RX Delay -230 -> 252, step: 16
4237 16:33:57.987124 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4238 16:33:57.990485 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4239 16:33:57.994228 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4240 16:33:57.997234 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4241 16:33:58.000878 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4242 16:33:58.007127 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4243 16:33:58.010345 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4244 16:33:58.013961 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4245 16:33:58.017518 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4246 16:33:58.023634 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4247 16:33:58.027280 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4248 16:33:58.030313 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4249 16:33:58.033518 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4250 16:33:58.040616 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4251 16:33:58.043900 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4252 16:33:58.047064 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4253 16:33:58.047180 ==
4254 16:33:58.050287 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 16:33:58.053681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 16:33:58.053798 ==
4257 16:33:58.056884 DQS Delay:
4258 16:33:58.056984 DQS0 = 0, DQS1 = 0
4259 16:33:58.059843 DQM Delay:
4260 16:33:58.059938 DQM0 = 34, DQM1 = 27
4261 16:33:58.063596 DQ Delay:
4262 16:33:58.063716 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =25
4263 16:33:58.066493 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4264 16:33:58.070008 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4265 16:33:58.073423 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4266 16:33:58.073551
4267 16:33:58.073643
4268 16:33:58.076726 ==
4269 16:33:58.080224 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 16:33:58.083230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 16:33:58.083348 ==
4272 16:33:58.083433
4273 16:33:58.083512
4274 16:33:58.086421 TX Vref Scan disable
4275 16:33:58.086529 == TX Byte 0 ==
4276 16:33:58.090247 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4277 16:33:58.096268 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4278 16:33:58.096407 == TX Byte 1 ==
4279 16:33:58.103385 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4280 16:33:58.106570 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4281 16:33:58.106694 ==
4282 16:33:58.109956 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 16:33:58.113217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 16:33:58.113325 ==
4285 16:33:58.113404
4286 16:33:58.113477
4287 16:33:58.116509 TX Vref Scan disable
4288 16:33:58.120081 == TX Byte 0 ==
4289 16:33:58.123279 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4290 16:33:58.126239 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4291 16:33:58.129496 == TX Byte 1 ==
4292 16:33:58.133393 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4293 16:33:58.136536 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4294 16:33:58.136664
4295 16:33:58.139776 [DATLAT]
4296 16:33:58.139881 Freq=600, CH0 RK1
4297 16:33:58.139967
4298 16:33:58.143325 DATLAT Default: 0x9
4299 16:33:58.143429 0, 0xFFFF, sum = 0
4300 16:33:58.146496 1, 0xFFFF, sum = 0
4301 16:33:58.146579 2, 0xFFFF, sum = 0
4302 16:33:58.149655 3, 0xFFFF, sum = 0
4303 16:33:58.149734 4, 0xFFFF, sum = 0
4304 16:33:58.153472 5, 0xFFFF, sum = 0
4305 16:33:58.153557 6, 0xFFFF, sum = 0
4306 16:33:58.156684 7, 0xFFFF, sum = 0
4307 16:33:58.156788 8, 0x0, sum = 1
4308 16:33:58.159943 9, 0x0, sum = 2
4309 16:33:58.160023 10, 0x0, sum = 3
4310 16:33:58.163100 11, 0x0, sum = 4
4311 16:33:58.163200 best_step = 9
4312 16:33:58.163287
4313 16:33:58.163369 ==
4314 16:33:58.166501 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 16:33:58.169655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 16:33:58.172914 ==
4317 16:33:58.172993 RX Vref Scan: 0
4318 16:33:58.173053
4319 16:33:58.176111 RX Vref 0 -> 0, step: 1
4320 16:33:58.176212
4321 16:33:58.179407 RX Delay -195 -> 252, step: 8
4322 16:33:58.182525 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4323 16:33:58.186313 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4324 16:33:58.193756 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4325 16:33:58.195836 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4326 16:33:58.199602 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4327 16:33:58.202501 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4328 16:33:58.209530 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4329 16:33:58.212654 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4330 16:33:58.215874 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4331 16:33:58.219696 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4332 16:33:58.225917 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4333 16:33:58.229081 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4334 16:33:58.232739 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4335 16:33:58.235823 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4336 16:33:58.238967 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4337 16:33:58.245958 iDelay=205, Bit 15, Center 32 (-123 ~ 188) 312
4338 16:33:58.246059 ==
4339 16:33:58.248948 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 16:33:58.252374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 16:33:58.252516 ==
4342 16:33:58.252640 DQS Delay:
4343 16:33:58.256042 DQS0 = 0, DQS1 = 0
4344 16:33:58.256167 DQM Delay:
4345 16:33:58.259288 DQM0 = 33, DQM1 = 27
4346 16:33:58.259413 DQ Delay:
4347 16:33:58.262473 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4348 16:33:58.266170 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4349 16:33:58.269391 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4350 16:33:58.272489 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =32
4351 16:33:58.272615
4352 16:33:58.272736
4353 16:33:58.282695 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f3f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4354 16:33:58.282806 CH0 RK1: MR19=808, MR18=6F3F
4355 16:33:58.289191 CH0_RK1: MR19=0x808, MR18=0x6F3F, DQSOSC=389, MR23=63, INC=173, DEC=115
4356 16:33:58.292360 [RxdqsGatingPostProcess] freq 600
4357 16:33:58.299205 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4358 16:33:58.302531 Pre-setting of DQS Precalculation
4359 16:33:58.305625 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4360 16:33:58.305731 ==
4361 16:33:58.308747 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 16:33:58.312298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 16:33:58.315549 ==
4364 16:33:58.319065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 16:33:58.325703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4366 16:33:58.328784 [CA 0] Center 35 (5~66) winsize 62
4367 16:33:58.331778 [CA 1] Center 35 (5~66) winsize 62
4368 16:33:58.335443 [CA 2] Center 34 (4~65) winsize 62
4369 16:33:58.338560 [CA 3] Center 34 (4~65) winsize 62
4370 16:33:58.342302 [CA 4] Center 34 (4~65) winsize 62
4371 16:33:58.345454 [CA 5] Center 33 (3~64) winsize 62
4372 16:33:58.345542
4373 16:33:58.348583 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4374 16:33:58.348674
4375 16:33:58.351838 [CATrainingPosCal] consider 1 rank data
4376 16:33:58.355117 u2DelayCellTimex100 = 270/100 ps
4377 16:33:58.358839 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4378 16:33:58.361831 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 16:33:58.364848 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 16:33:58.371682 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 16:33:58.374961 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 16:33:58.378645 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 16:33:58.378722
4384 16:33:58.381723 CA PerBit enable=1, Macro0, CA PI delay=33
4385 16:33:58.381799
4386 16:33:58.384926 [CBTSetCACLKResult] CA Dly = 33
4387 16:33:58.385001 CS Dly: 4 (0~35)
4388 16:33:58.385060 ==
4389 16:33:58.388554 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 16:33:58.395152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 16:33:58.395254 ==
4392 16:33:58.398209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 16:33:58.404593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4394 16:33:58.408374 [CA 0] Center 36 (6~66) winsize 61
4395 16:33:58.411553 [CA 1] Center 36 (6~66) winsize 61
4396 16:33:58.415405 [CA 2] Center 34 (4~65) winsize 62
4397 16:33:58.418527 [CA 3] Center 34 (3~65) winsize 63
4398 16:33:58.421577 [CA 4] Center 34 (4~65) winsize 62
4399 16:33:58.425044 [CA 5] Center 33 (3~64) winsize 62
4400 16:33:58.425118
4401 16:33:58.428641 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4402 16:33:58.428750
4403 16:33:58.431617 [CATrainingPosCal] consider 2 rank data
4404 16:33:58.434726 u2DelayCellTimex100 = 270/100 ps
4405 16:33:58.438415 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4406 16:33:58.444935 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 16:33:58.447951 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 16:33:58.451643 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 16:33:58.454799 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 16:33:58.458085 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 16:33:58.458150
4412 16:33:58.461164 CA PerBit enable=1, Macro0, CA PI delay=33
4413 16:33:58.461226
4414 16:33:58.464892 [CBTSetCACLKResult] CA Dly = 33
4415 16:33:58.468030 CS Dly: 4 (0~36)
4416 16:33:58.468103
4417 16:33:58.471074 ----->DramcWriteLeveling(PI) begin...
4418 16:33:58.471150 ==
4419 16:33:58.474835 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 16:33:58.478073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 16:33:58.478147 ==
4422 16:33:58.481102 Write leveling (Byte 0): 31 => 31
4423 16:33:58.484590 Write leveling (Byte 1): 31 => 31
4424 16:33:58.487670 DramcWriteLeveling(PI) end<-----
4425 16:33:58.487744
4426 16:33:58.487809 ==
4427 16:33:58.491357 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 16:33:58.494558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 16:33:58.494632 ==
4430 16:33:58.497807 [Gating] SW mode calibration
4431 16:33:58.504090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4432 16:33:58.511048 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4433 16:33:58.514226 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 16:33:58.517456 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 16:33:58.524454 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 16:33:58.527430 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4437 16:33:58.530572 0 9 16 | B1->B0 | 2c2c 2424 | 0 0 | (1 1) (1 1)
4438 16:33:58.537237 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 16:33:58.540884 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 16:33:58.544394 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 16:33:58.550613 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 16:33:58.554060 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 16:33:58.557476 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 16:33:58.563758 0 10 12 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (0 0)
4445 16:33:58.567440 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
4446 16:33:58.570989 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 16:33:58.577089 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 16:33:58.580938 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 16:33:58.584116 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 16:33:58.587117 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 16:33:58.593840 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 16:33:58.596960 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 16:33:58.600831 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 16:33:58.607244 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 16:33:58.610310 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 16:33:58.613482 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 16:33:58.620026 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 16:33:58.623936 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 16:33:58.627164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 16:33:58.633198 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 16:33:58.636982 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 16:33:58.640126 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 16:33:58.646801 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 16:33:58.649741 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 16:33:58.653073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 16:33:58.660145 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 16:33:58.663139 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4468 16:33:58.666698 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4469 16:33:58.673223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 16:33:58.676125 Total UI for P1: 0, mck2ui 16
4471 16:33:58.679938 best dqsien dly found for B0: ( 0, 13, 14)
4472 16:33:58.682924 Total UI for P1: 0, mck2ui 16
4473 16:33:58.686122 best dqsien dly found for B1: ( 0, 13, 10)
4474 16:33:58.689898 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4475 16:33:58.692993 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4476 16:33:58.693071
4477 16:33:58.696062 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4478 16:33:58.699968 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4479 16:33:58.703092 [Gating] SW calibration Done
4480 16:33:58.703168 ==
4481 16:33:58.706214 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 16:33:58.709340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 16:33:58.709417 ==
4484 16:33:58.713143 RX Vref Scan: 0
4485 16:33:58.713220
4486 16:33:58.716193 RX Vref 0 -> 0, step: 1
4487 16:33:58.716272
4488 16:33:58.716350 RX Delay -230 -> 252, step: 16
4489 16:33:58.723077 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4490 16:33:58.726296 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4491 16:33:58.729516 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4492 16:33:58.732549 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4493 16:33:58.739503 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4494 16:33:58.742678 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4495 16:33:58.745914 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4496 16:33:58.749758 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4497 16:33:58.752818 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4498 16:33:58.759602 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4499 16:33:58.762540 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4500 16:33:58.766394 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4501 16:33:58.769408 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4502 16:33:58.776031 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4503 16:33:58.778960 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4504 16:33:58.782432 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4505 16:33:58.782511 ==
4506 16:33:58.785800 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 16:33:58.792039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 16:33:58.792117 ==
4509 16:33:58.792196 DQS Delay:
4510 16:33:58.792267 DQS0 = 0, DQS1 = 0
4511 16:33:58.795818 DQM Delay:
4512 16:33:58.795895 DQM0 = 38, DQM1 = 28
4513 16:33:58.798771 DQ Delay:
4514 16:33:58.801957 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4515 16:33:58.805789 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4516 16:33:58.809000 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4517 16:33:58.812167 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4518 16:33:58.812249
4519 16:33:58.812327
4520 16:33:58.812398 ==
4521 16:33:58.815335 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 16:33:58.818471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 16:33:58.818548 ==
4524 16:33:58.818625
4525 16:33:58.818696
4526 16:33:58.822191 TX Vref Scan disable
4527 16:33:58.822268 == TX Byte 0 ==
4528 16:33:58.828964 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4529 16:33:58.832050 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4530 16:33:58.832120 == TX Byte 1 ==
4531 16:33:58.839006 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4532 16:33:58.842046 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4533 16:33:58.842116 ==
4534 16:33:58.845219 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 16:33:58.848382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 16:33:58.848462 ==
4537 16:33:58.848560
4538 16:33:58.852076
4539 16:33:58.852143 TX Vref Scan disable
4540 16:33:58.855129 == TX Byte 0 ==
4541 16:33:58.858435 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4542 16:33:58.865351 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4543 16:33:58.865431 == TX Byte 1 ==
4544 16:33:58.868218 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4545 16:33:58.874879 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4546 16:33:58.874961
4547 16:33:58.875040 [DATLAT]
4548 16:33:58.875111 Freq=600, CH1 RK0
4549 16:33:58.875182
4550 16:33:58.878623 DATLAT Default: 0x9
4551 16:33:58.878701 0, 0xFFFF, sum = 0
4552 16:33:58.881801 1, 0xFFFF, sum = 0
4553 16:33:58.884961 2, 0xFFFF, sum = 0
4554 16:33:58.885040 3, 0xFFFF, sum = 0
4555 16:33:58.888508 4, 0xFFFF, sum = 0
4556 16:33:58.888577 5, 0xFFFF, sum = 0
4557 16:33:58.891557 6, 0xFFFF, sum = 0
4558 16:33:58.891634 7, 0xFFFF, sum = 0
4559 16:33:58.895002 8, 0x0, sum = 1
4560 16:33:58.895078 9, 0x0, sum = 2
4561 16:33:58.895138 10, 0x0, sum = 3
4562 16:33:58.898495 11, 0x0, sum = 4
4563 16:33:58.898560 best_step = 9
4564 16:33:58.898616
4565 16:33:58.898668 ==
4566 16:33:58.901359 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 16:33:58.908099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 16:33:58.908202 ==
4569 16:33:58.908262 RX Vref Scan: 1
4570 16:33:58.908316
4571 16:33:58.911667 RX Vref 0 -> 0, step: 1
4572 16:33:58.911742
4573 16:33:58.914950 RX Delay -195 -> 252, step: 8
4574 16:33:58.915026
4575 16:33:58.918149 Set Vref, RX VrefLevel [Byte0]: 57
4576 16:33:58.921408 [Byte1]: 48
4577 16:33:58.921484
4578 16:33:58.924539 Final RX Vref Byte 0 = 57 to rank0
4579 16:33:58.927772 Final RX Vref Byte 1 = 48 to rank0
4580 16:33:58.931496 Final RX Vref Byte 0 = 57 to rank1
4581 16:33:58.934500 Final RX Vref Byte 1 = 48 to rank1==
4582 16:33:58.938143 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 16:33:58.941334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 16:33:58.944518 ==
4585 16:33:58.944596 DQS Delay:
4586 16:33:58.944717 DQS0 = 0, DQS1 = 0
4587 16:33:58.947773 DQM Delay:
4588 16:33:58.947851 DQM0 = 40, DQM1 = 29
4589 16:33:58.950856 DQ Delay:
4590 16:33:58.950933 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4591 16:33:58.954710 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4592 16:33:58.957728 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4593 16:33:58.960916 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4594 16:33:58.960994
4595 16:33:58.964064
4596 16:33:58.970904 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4597 16:33:58.974582 CH1 RK0: MR19=808, MR18=2330
4598 16:33:58.981023 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4599 16:33:58.981097
4600 16:33:58.984422 ----->DramcWriteLeveling(PI) begin...
4601 16:33:58.984495 ==
4602 16:33:58.987522 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 16:33:58.990575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 16:33:58.990651 ==
4605 16:33:58.994310 Write leveling (Byte 0): 31 => 31
4606 16:33:58.997562 Write leveling (Byte 1): 32 => 32
4607 16:33:59.000513 DramcWriteLeveling(PI) end<-----
4608 16:33:59.000605
4609 16:33:59.000720 ==
4610 16:33:59.004128 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 16:33:59.007104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 16:33:59.007177 ==
4613 16:33:59.010749 [Gating] SW mode calibration
4614 16:33:59.017055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4615 16:33:59.023877 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4616 16:33:59.027054 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 16:33:59.030250 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 16:33:59.037092 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4619 16:33:59.040292 0 9 12 | B1->B0 | 3131 2c2c | 0 1 | (0 1) (1 0)
4620 16:33:59.043313 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4621 16:33:59.050224 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 16:33:59.053508 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 16:33:59.059738 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 16:33:59.063358 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 16:33:59.066639 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 16:33:59.072959 0 10 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
4627 16:33:59.076782 0 10 12 | B1->B0 | 3131 3c3c | 1 1 | (0 0) (0 0)
4628 16:33:59.079792 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 16:33:59.086112 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 16:33:59.089826 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 16:33:59.093264 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 16:33:59.096125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 16:33:59.102892 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 16:33:59.106033 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 16:33:59.109835 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 16:33:59.116109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 16:33:59.119589 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 16:33:59.123197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 16:33:59.129830 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 16:33:59.133148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 16:33:59.136051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 16:33:59.142741 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 16:33:59.146465 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 16:33:59.149477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 16:33:59.155787 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 16:33:59.159559 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 16:33:59.162756 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 16:33:59.169673 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 16:33:59.172856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 16:33:59.176086 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 16:33:59.182896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 16:33:59.182972 Total UI for P1: 0, mck2ui 16
4653 16:33:59.189224 best dqsien dly found for B0: ( 0, 13, 10)
4654 16:33:59.189302 Total UI for P1: 0, mck2ui 16
4655 16:33:59.195617 best dqsien dly found for B1: ( 0, 13, 10)
4656 16:33:59.199120 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4657 16:33:59.202098 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4658 16:33:59.202186
4659 16:33:59.205557 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4660 16:33:59.208919 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4661 16:33:59.211945 [Gating] SW calibration Done
4662 16:33:59.212020 ==
4663 16:33:59.215741 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 16:33:59.218924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 16:33:59.219000 ==
4666 16:33:59.221971 RX Vref Scan: 0
4667 16:33:59.222047
4668 16:33:59.222105 RX Vref 0 -> 0, step: 1
4669 16:33:59.225626
4670 16:33:59.225701 RX Delay -230 -> 252, step: 16
4671 16:33:59.232121 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4672 16:33:59.235274 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4673 16:33:59.238368 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4674 16:33:59.241792 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4675 16:33:59.248750 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4676 16:33:59.251730 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4677 16:33:59.255273 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4678 16:33:59.258248 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4679 16:33:59.262058 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4680 16:33:59.268454 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4681 16:33:59.271487 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4682 16:33:59.274728 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4683 16:33:59.278610 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4684 16:33:59.284917 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4685 16:33:59.288064 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4686 16:33:59.291915 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4687 16:33:59.291992 ==
4688 16:33:59.295157 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 16:33:59.298416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 16:33:59.301418 ==
4691 16:33:59.301498 DQS Delay:
4692 16:33:59.301557 DQS0 = 0, DQS1 = 0
4693 16:33:59.304585 DQM Delay:
4694 16:33:59.304720 DQM0 = 36, DQM1 = 29
4695 16:33:59.308355 DQ Delay:
4696 16:33:59.311325 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4697 16:33:59.311403 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4698 16:33:59.314986 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4699 16:33:59.317803 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4700 16:33:59.321176
4701 16:33:59.321253
4702 16:33:59.321311 ==
4703 16:33:59.324492 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 16:33:59.328339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 16:33:59.328417 ==
4706 16:33:59.328477
4707 16:33:59.328531
4708 16:33:59.331309 TX Vref Scan disable
4709 16:33:59.331409 == TX Byte 0 ==
4710 16:33:59.337661 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4711 16:33:59.341508 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4712 16:33:59.341587 == TX Byte 1 ==
4713 16:33:59.347632 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4714 16:33:59.351484 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4715 16:33:59.351566 ==
4716 16:33:59.354524 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 16:33:59.357645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 16:33:59.357723 ==
4719 16:33:59.357799
4720 16:33:59.357871
4721 16:33:59.361098 TX Vref Scan disable
4722 16:33:59.364258 == TX Byte 0 ==
4723 16:33:59.367776 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 16:33:59.371386 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 16:33:59.374417 == TX Byte 1 ==
4726 16:33:59.377633 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4727 16:33:59.381347 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4728 16:33:59.384557
4729 16:33:59.384638 [DATLAT]
4730 16:33:59.384734 Freq=600, CH1 RK1
4731 16:33:59.384808
4732 16:33:59.387692 DATLAT Default: 0x9
4733 16:33:59.387759 0, 0xFFFF, sum = 0
4734 16:33:59.390834 1, 0xFFFF, sum = 0
4735 16:33:59.390902 2, 0xFFFF, sum = 0
4736 16:33:59.393993 3, 0xFFFF, sum = 0
4737 16:33:59.394098 4, 0xFFFF, sum = 0
4738 16:33:59.397417 5, 0xFFFF, sum = 0
4739 16:33:59.401225 6, 0xFFFF, sum = 0
4740 16:33:59.401306 7, 0xFFFF, sum = 0
4741 16:33:59.401385 8, 0x0, sum = 1
4742 16:33:59.404327 9, 0x0, sum = 2
4743 16:33:59.404405 10, 0x0, sum = 3
4744 16:33:59.407491 11, 0x0, sum = 4
4745 16:33:59.407570 best_step = 9
4746 16:33:59.407646
4747 16:33:59.407717 ==
4748 16:33:59.411212 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 16:33:59.417513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 16:33:59.417591 ==
4751 16:33:59.417668 RX Vref Scan: 0
4752 16:33:59.417740
4753 16:33:59.420513 RX Vref 0 -> 0, step: 1
4754 16:33:59.420590
4755 16:33:59.424162 RX Delay -195 -> 252, step: 8
4756 16:33:59.427228 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4757 16:33:59.434120 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4758 16:33:59.437087 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4759 16:33:59.440634 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4760 16:33:59.443869 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4761 16:33:59.450772 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4762 16:33:59.453748 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4763 16:33:59.456938 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4764 16:33:59.460666 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4765 16:33:59.463748 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4766 16:33:59.470651 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4767 16:33:59.473797 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4768 16:33:59.477354 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4769 16:33:59.480273 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4770 16:33:59.487136 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4771 16:33:59.490353 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4772 16:33:59.490422 ==
4773 16:33:59.493519 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 16:33:59.497353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 16:33:59.497431 ==
4776 16:33:59.500366 DQS Delay:
4777 16:33:59.500443 DQS0 = 0, DQS1 = 0
4778 16:33:59.500539 DQM Delay:
4779 16:33:59.503500 DQM0 = 36, DQM1 = 29
4780 16:33:59.503580 DQ Delay:
4781 16:33:59.507204 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4782 16:33:59.510447 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4783 16:33:59.513519 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4784 16:33:59.516760 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4785 16:33:59.516836
4786 16:33:59.516912
4787 16:33:59.526828 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4788 16:33:59.530079 CH1 RK1: MR19=808, MR18=3E5D
4789 16:33:59.533761 CH1_RK1: MR19=0x808, MR18=0x3E5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4790 16:33:59.537042 [RxdqsGatingPostProcess] freq 600
4791 16:33:59.543489 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4792 16:33:59.546817 Pre-setting of DQS Precalculation
4793 16:33:59.549721 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4794 16:33:59.560030 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4795 16:33:59.566288 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4796 16:33:59.566369
4797 16:33:59.566446
4798 16:33:59.570013 [Calibration Summary] 1200 Mbps
4799 16:33:59.570089 CH 0, Rank 0
4800 16:33:59.573206 SW Impedance : PASS
4801 16:33:59.573283 DUTY Scan : NO K
4802 16:33:59.576454 ZQ Calibration : PASS
4803 16:33:59.579600 Jitter Meter : NO K
4804 16:33:59.579678 CBT Training : PASS
4805 16:33:59.583461 Write leveling : PASS
4806 16:33:59.586570 RX DQS gating : PASS
4807 16:33:59.586648 RX DQ/DQS(RDDQC) : PASS
4808 16:33:59.589645 TX DQ/DQS : PASS
4809 16:33:59.593018 RX DATLAT : PASS
4810 16:33:59.593096 RX DQ/DQS(Engine): PASS
4811 16:33:59.596408 TX OE : NO K
4812 16:33:59.596484 All Pass.
4813 16:33:59.596581
4814 16:33:59.599924 CH 0, Rank 1
4815 16:33:59.600000 SW Impedance : PASS
4816 16:33:59.602983 DUTY Scan : NO K
4817 16:33:59.603063 ZQ Calibration : PASS
4818 16:33:59.606735 Jitter Meter : NO K
4819 16:33:59.609871 CBT Training : PASS
4820 16:33:59.609941 Write leveling : PASS
4821 16:33:59.613075 RX DQS gating : PASS
4822 16:33:59.616219 RX DQ/DQS(RDDQC) : PASS
4823 16:33:59.616292 TX DQ/DQS : PASS
4824 16:33:59.619955 RX DATLAT : PASS
4825 16:33:59.623231 RX DQ/DQS(Engine): PASS
4826 16:33:59.623298 TX OE : NO K
4827 16:33:59.626276 All Pass.
4828 16:33:59.626352
4829 16:33:59.626426 CH 1, Rank 0
4830 16:33:59.629323 SW Impedance : PASS
4831 16:33:59.629391 DUTY Scan : NO K
4832 16:33:59.633174 ZQ Calibration : PASS
4833 16:33:59.636335 Jitter Meter : NO K
4834 16:33:59.636406 CBT Training : PASS
4835 16:33:59.639411 Write leveling : PASS
4836 16:33:59.643102 RX DQS gating : PASS
4837 16:33:59.643170 RX DQ/DQS(RDDQC) : PASS
4838 16:33:59.646338 TX DQ/DQS : PASS
4839 16:33:59.649194 RX DATLAT : PASS
4840 16:33:59.649270 RX DQ/DQS(Engine): PASS
4841 16:33:59.652570 TX OE : NO K
4842 16:33:59.652698 All Pass.
4843 16:33:59.652762
4844 16:33:59.656073 CH 1, Rank 1
4845 16:33:59.656149 SW Impedance : PASS
4846 16:33:59.659454 DUTY Scan : NO K
4847 16:33:59.659530 ZQ Calibration : PASS
4848 16:33:59.662793 Jitter Meter : NO K
4849 16:33:59.666171 CBT Training : PASS
4850 16:33:59.666247 Write leveling : PASS
4851 16:33:59.669118 RX DQS gating : PASS
4852 16:33:59.672861 RX DQ/DQS(RDDQC) : PASS
4853 16:33:59.672937 TX DQ/DQS : PASS
4854 16:33:59.675922 RX DATLAT : PASS
4855 16:33:59.679121 RX DQ/DQS(Engine): PASS
4856 16:33:59.679198 TX OE : NO K
4857 16:33:59.682419 All Pass.
4858 16:33:59.682496
4859 16:33:59.682573 DramC Write-DBI off
4860 16:33:59.685662 PER_BANK_REFRESH: Hybrid Mode
4861 16:33:59.689466 TX_TRACKING: ON
4862 16:33:59.695573 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4863 16:33:59.699184 [FAST_K] Save calibration result to emmc
4864 16:33:59.702158 dramc_set_vcore_voltage set vcore to 662500
4865 16:33:59.705663 Read voltage for 933, 3
4866 16:33:59.705740 Vio18 = 0
4867 16:33:59.708772 Vcore = 662500
4868 16:33:59.708848 Vdram = 0
4869 16:33:59.708924 Vddq = 0
4870 16:33:59.712184 Vmddr = 0
4871 16:33:59.715474 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4872 16:33:59.722433 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4873 16:33:59.722510 MEM_TYPE=3, freq_sel=17
4874 16:33:59.725684 sv_algorithm_assistance_LP4_1600
4875 16:33:59.731930 ============ PULL DRAM RESETB DOWN ============
4876 16:33:59.735181 ========== PULL DRAM RESETB DOWN end =========
4877 16:33:59.738430 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4878 16:33:59.742103 ===================================
4879 16:33:59.745348 LPDDR4 DRAM CONFIGURATION
4880 16:33:59.748516 ===================================
4881 16:33:59.751772 EX_ROW_EN[0] = 0x0
4882 16:33:59.751844 EX_ROW_EN[1] = 0x0
4883 16:33:59.755023 LP4Y_EN = 0x0
4884 16:33:59.755090 WORK_FSP = 0x0
4885 16:33:59.758706 WL = 0x3
4886 16:33:59.758783 RL = 0x3
4887 16:33:59.761701 BL = 0x2
4888 16:33:59.761778 RPST = 0x0
4889 16:33:59.765179 RD_PRE = 0x0
4890 16:33:59.765256 WR_PRE = 0x1
4891 16:33:59.768632 WR_PST = 0x0
4892 16:33:59.768725 DBI_WR = 0x0
4893 16:33:59.771854 DBI_RD = 0x0
4894 16:33:59.771923 OTF = 0x1
4895 16:33:59.775157 ===================================
4896 16:33:59.778349 ===================================
4897 16:33:59.781744 ANA top config
4898 16:33:59.785061 ===================================
4899 16:33:59.788567 DLL_ASYNC_EN = 0
4900 16:33:59.788638 ALL_SLAVE_EN = 1
4901 16:33:59.791890 NEW_RANK_MODE = 1
4902 16:33:59.795135 DLL_IDLE_MODE = 1
4903 16:33:59.798286 LP45_APHY_COMB_EN = 1
4904 16:33:59.798370 TX_ODT_DIS = 1
4905 16:33:59.801474 NEW_8X_MODE = 1
4906 16:33:59.804735 ===================================
4907 16:33:59.808458 ===================================
4908 16:33:59.811534 data_rate = 1866
4909 16:33:59.814678 CKR = 1
4910 16:33:59.818365 DQ_P2S_RATIO = 8
4911 16:33:59.821465 ===================================
4912 16:33:59.825032 CA_P2S_RATIO = 8
4913 16:33:59.825108 DQ_CA_OPEN = 0
4914 16:33:59.828451 DQ_SEMI_OPEN = 0
4915 16:33:59.831366 CA_SEMI_OPEN = 0
4916 16:33:59.834767 CA_FULL_RATE = 0
4917 16:33:59.837798 DQ_CKDIV4_EN = 1
4918 16:33:59.841667 CA_CKDIV4_EN = 1
4919 16:33:59.841746 CA_PREDIV_EN = 0
4920 16:33:59.844761 PH8_DLY = 0
4921 16:33:59.847919 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4922 16:33:59.851585 DQ_AAMCK_DIV = 4
4923 16:33:59.854824 CA_AAMCK_DIV = 4
4924 16:33:59.857990 CA_ADMCK_DIV = 4
4925 16:33:59.858067 DQ_TRACK_CA_EN = 0
4926 16:33:59.861214 CA_PICK = 933
4927 16:33:59.864981 CA_MCKIO = 933
4928 16:33:59.868104 MCKIO_SEMI = 0
4929 16:33:59.871413 PLL_FREQ = 3732
4930 16:33:59.874468 DQ_UI_PI_RATIO = 32
4931 16:33:59.878186 CA_UI_PI_RATIO = 0
4932 16:33:59.881303 ===================================
4933 16:33:59.884666 ===================================
4934 16:33:59.884741 memory_type:LPDDR4
4935 16:33:59.888117 GP_NUM : 10
4936 16:33:59.890946 SRAM_EN : 1
4937 16:33:59.891020 MD32_EN : 0
4938 16:33:59.894648 ===================================
4939 16:33:59.897743 [ANA_INIT] >>>>>>>>>>>>>>
4940 16:33:59.901107 <<<<<< [CONFIGURE PHASE]: ANA_TX
4941 16:33:59.904454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4942 16:33:59.907711 ===================================
4943 16:33:59.911337 data_rate = 1866,PCW = 0X8f00
4944 16:33:59.914364 ===================================
4945 16:33:59.917410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4946 16:33:59.921178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 16:33:59.927566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 16:33:59.930741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4949 16:33:59.934504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4950 16:33:59.937691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4951 16:33:59.940765 [ANA_INIT] flow start
4952 16:33:59.943815 [ANA_INIT] PLL >>>>>>>>
4953 16:33:59.943892 [ANA_INIT] PLL <<<<<<<<
4954 16:33:59.947293 [ANA_INIT] MIDPI >>>>>>>>
4955 16:33:59.950586 [ANA_INIT] MIDPI <<<<<<<<
4956 16:33:59.954136 [ANA_INIT] DLL >>>>>>>>
4957 16:33:59.954215 [ANA_INIT] flow end
4958 16:33:59.957543 ============ LP4 DIFF to SE enter ============
4959 16:33:59.963833 ============ LP4 DIFF to SE exit ============
4960 16:33:59.963912 [ANA_INIT] <<<<<<<<<<<<<
4961 16:33:59.967051 [Flow] Enable top DCM control >>>>>
4962 16:33:59.970811 [Flow] Enable top DCM control <<<<<
4963 16:33:59.973865 Enable DLL master slave shuffle
4964 16:33:59.980274 ==============================================================
4965 16:33:59.980351 Gating Mode config
4966 16:33:59.987291 ==============================================================
4967 16:33:59.990425 Config description:
4968 16:34:00.000390 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4969 16:34:00.006773 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4970 16:34:00.009958 SELPH_MODE 0: By rank 1: By Phase
4971 16:34:00.016687 ==============================================================
4972 16:34:00.020114 GAT_TRACK_EN = 1
4973 16:34:00.023371 RX_GATING_MODE = 2
4974 16:34:00.023449 RX_GATING_TRACK_MODE = 2
4975 16:34:00.026566 SELPH_MODE = 1
4976 16:34:00.029717 PICG_EARLY_EN = 1
4977 16:34:00.032934 VALID_LAT_VALUE = 1
4978 16:34:00.039842 ==============================================================
4979 16:34:00.042919 Enter into Gating configuration >>>>
4980 16:34:00.046697 Exit from Gating configuration <<<<
4981 16:34:00.049732 Enter into DVFS_PRE_config >>>>>
4982 16:34:00.059648 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4983 16:34:00.063192 Exit from DVFS_PRE_config <<<<<
4984 16:34:00.066205 Enter into PICG configuration >>>>
4985 16:34:00.069679 Exit from PICG configuration <<<<
4986 16:34:00.072893 [RX_INPUT] configuration >>>>>
4987 16:34:00.076347 [RX_INPUT] configuration <<<<<
4988 16:34:00.079442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4989 16:34:00.086449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4990 16:34:00.092883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 16:34:00.099179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 16:34:00.103107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 16:34:00.109371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 16:34:00.116154 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4995 16:34:00.119266 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4996 16:34:00.122426 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4997 16:34:00.125958 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4998 16:34:00.129385 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4999 16:34:00.135486 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 16:34:00.139106 ===================================
5001 16:34:00.142711 LPDDR4 DRAM CONFIGURATION
5002 16:34:00.145666 ===================================
5003 16:34:00.145746 EX_ROW_EN[0] = 0x0
5004 16:34:00.148869 EX_ROW_EN[1] = 0x0
5005 16:34:00.148945 LP4Y_EN = 0x0
5006 16:34:00.152018 WORK_FSP = 0x0
5007 16:34:00.152096 WL = 0x3
5008 16:34:00.155300 RL = 0x3
5009 16:34:00.155376 BL = 0x2
5010 16:34:00.159198 RPST = 0x0
5011 16:34:00.159274 RD_PRE = 0x0
5012 16:34:00.162384 WR_PRE = 0x1
5013 16:34:00.162460 WR_PST = 0x0
5014 16:34:00.165556 DBI_WR = 0x0
5015 16:34:00.168667 DBI_RD = 0x0
5016 16:34:00.168759 OTF = 0x1
5017 16:34:00.171909 ===================================
5018 16:34:00.175690 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5019 16:34:00.178867 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5020 16:34:00.185380 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5021 16:34:00.188943 ===================================
5022 16:34:00.191716 LPDDR4 DRAM CONFIGURATION
5023 16:34:00.195466 ===================================
5024 16:34:00.195543 EX_ROW_EN[0] = 0x10
5025 16:34:00.198661 EX_ROW_EN[1] = 0x0
5026 16:34:00.198737 LP4Y_EN = 0x0
5027 16:34:00.201794 WORK_FSP = 0x0
5028 16:34:00.201869 WL = 0x3
5029 16:34:00.204938 RL = 0x3
5030 16:34:00.205013 BL = 0x2
5031 16:34:00.208176 RPST = 0x0
5032 16:34:00.208251 RD_PRE = 0x0
5033 16:34:00.211461 WR_PRE = 0x1
5034 16:34:00.211536 WR_PST = 0x0
5035 16:34:00.215259 DBI_WR = 0x0
5036 16:34:00.218340 DBI_RD = 0x0
5037 16:34:00.218416 OTF = 0x1
5038 16:34:00.221370 ===================================
5039 16:34:00.228449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5040 16:34:00.231671 nWR fixed to 30
5041 16:34:00.234840 [ModeRegInit_LP4] CH0 RK0
5042 16:34:00.234916 [ModeRegInit_LP4] CH0 RK1
5043 16:34:00.238782 [ModeRegInit_LP4] CH1 RK0
5044 16:34:00.241996 [ModeRegInit_LP4] CH1 RK1
5045 16:34:00.242072 match AC timing 9
5046 16:34:00.248872 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5047 16:34:00.251717 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5048 16:34:00.254945 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5049 16:34:00.261378 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5050 16:34:00.264603 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5051 16:34:00.264728 ==
5052 16:34:00.268364 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 16:34:00.271340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 16:34:00.271444 ==
5055 16:34:00.278242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 16:34:00.284428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5057 16:34:00.288186 [CA 0] Center 38 (8~69) winsize 62
5058 16:34:00.291138 [CA 1] Center 38 (8~69) winsize 62
5059 16:34:00.294363 [CA 2] Center 35 (5~66) winsize 62
5060 16:34:00.298259 [CA 3] Center 35 (4~66) winsize 63
5061 16:34:00.301298 [CA 4] Center 34 (4~65) winsize 62
5062 16:34:00.304308 [CA 5] Center 34 (4~64) winsize 61
5063 16:34:00.304385
5064 16:34:00.308028 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5065 16:34:00.308105
5066 16:34:00.311200 [CATrainingPosCal] consider 1 rank data
5067 16:34:00.314315 u2DelayCellTimex100 = 270/100 ps
5068 16:34:00.317607 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5069 16:34:00.320953 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5070 16:34:00.324530 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5071 16:34:00.327627 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5072 16:34:00.330810 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5073 16:34:00.337942 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5074 16:34:00.338021
5075 16:34:00.341089 CA PerBit enable=1, Macro0, CA PI delay=34
5076 16:34:00.341166
5077 16:34:00.344228 [CBTSetCACLKResult] CA Dly = 34
5078 16:34:00.344328 CS Dly: 7 (0~38)
5079 16:34:00.344415 ==
5080 16:34:00.347478 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 16:34:00.350757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 16:34:00.353995 ==
5083 16:34:00.357618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5084 16:34:00.364080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5085 16:34:00.367685 [CA 0] Center 38 (8~69) winsize 62
5086 16:34:00.370648 [CA 1] Center 38 (8~69) winsize 62
5087 16:34:00.374022 [CA 2] Center 35 (5~66) winsize 62
5088 16:34:00.377305 [CA 3] Center 35 (5~66) winsize 62
5089 16:34:00.380434 [CA 4] Center 34 (3~65) winsize 63
5090 16:34:00.384012 [CA 5] Center 34 (4~64) winsize 61
5091 16:34:00.384105
5092 16:34:00.387019 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5093 16:34:00.387116
5094 16:34:00.390467 [CATrainingPosCal] consider 2 rank data
5095 16:34:00.393666 u2DelayCellTimex100 = 270/100 ps
5096 16:34:00.397060 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5097 16:34:00.400605 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5098 16:34:00.403795 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5099 16:34:00.410574 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5100 16:34:00.413644 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5101 16:34:00.417099 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5102 16:34:00.417175
5103 16:34:00.420207 CA PerBit enable=1, Macro0, CA PI delay=34
5104 16:34:00.420308
5105 16:34:00.423983 [CBTSetCACLKResult] CA Dly = 34
5106 16:34:00.424061 CS Dly: 7 (0~39)
5107 16:34:00.424121
5108 16:34:00.427152 ----->DramcWriteLeveling(PI) begin...
5109 16:34:00.427229 ==
5110 16:34:00.430241 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 16:34:00.437276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 16:34:00.437359 ==
5113 16:34:00.440474 Write leveling (Byte 0): 30 => 30
5114 16:34:00.443496 Write leveling (Byte 1): 30 => 30
5115 16:34:00.443602 DramcWriteLeveling(PI) end<-----
5116 16:34:00.446713
5117 16:34:00.446788 ==
5118 16:34:00.450604 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 16:34:00.453793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 16:34:00.453871 ==
5121 16:34:00.457035 [Gating] SW mode calibration
5122 16:34:00.463181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5123 16:34:00.467043 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5124 16:34:00.473512 0 14 0 | B1->B0 | 2323 2828 | 1 1 | (1 1) (1 1)
5125 16:34:00.476690 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5126 16:34:00.479919 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 16:34:00.486884 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 16:34:00.489921 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 16:34:00.493384 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 16:34:00.499966 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 16:34:00.503391 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5132 16:34:00.506612 0 15 0 | B1->B0 | 3434 2929 | 0 0 | (0 0) (0 0)
5133 16:34:00.513015 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5134 16:34:00.516424 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 16:34:00.519657 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 16:34:00.526178 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 16:34:00.529528 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 16:34:00.532899 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 16:34:00.539525 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 16:34:00.542962 1 0 0 | B1->B0 | 2c2c 3a3a | 0 0 | (0 0) (0 0)
5141 16:34:00.546823 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 16:34:00.553334 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 16:34:00.556529 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 16:34:00.559646 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 16:34:00.566605 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 16:34:00.569762 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 16:34:00.572888 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5148 16:34:00.579913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 16:34:00.583109 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 16:34:00.586326 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 16:34:00.592508 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 16:34:00.596153 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 16:34:00.599355 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 16:34:00.606362 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 16:34:00.609500 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 16:34:00.612626 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 16:34:00.615894 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 16:34:00.623103 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 16:34:00.626041 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 16:34:00.629501 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 16:34:00.636038 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 16:34:00.639420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 16:34:00.642923 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5164 16:34:00.649192 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5165 16:34:00.652538 Total UI for P1: 0, mck2ui 16
5166 16:34:00.655842 best dqsien dly found for B0: ( 1, 2, 28)
5167 16:34:00.658941 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5168 16:34:00.662598 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 16:34:00.665791 Total UI for P1: 0, mck2ui 16
5170 16:34:00.668868 best dqsien dly found for B1: ( 1, 3, 4)
5171 16:34:00.672554 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5172 16:34:00.675714 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5173 16:34:00.675789
5174 16:34:00.682047 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5175 16:34:00.685372 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5176 16:34:00.689158 [Gating] SW calibration Done
5177 16:34:00.689234 ==
5178 16:34:00.692285 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 16:34:00.695387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 16:34:00.695464 ==
5181 16:34:00.695525 RX Vref Scan: 0
5182 16:34:00.695580
5183 16:34:00.699045 RX Vref 0 -> 0, step: 1
5184 16:34:00.699122
5185 16:34:00.702077 RX Delay -80 -> 252, step: 8
5186 16:34:00.705189 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5187 16:34:00.708925 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5188 16:34:00.715360 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5189 16:34:00.718551 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5190 16:34:00.722407 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5191 16:34:00.725450 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5192 16:34:00.728539 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5193 16:34:00.732225 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5194 16:34:00.738575 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5195 16:34:00.742071 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5196 16:34:00.745503 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5197 16:34:00.748428 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5198 16:34:00.752056 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5199 16:34:00.758859 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5200 16:34:00.762115 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5201 16:34:00.765065 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5202 16:34:00.765145 ==
5203 16:34:00.768371 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 16:34:00.771908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 16:34:00.771984 ==
5206 16:34:00.775289 DQS Delay:
5207 16:34:00.775364 DQS0 = 0, DQS1 = 0
5208 16:34:00.778651 DQM Delay:
5209 16:34:00.778726 DQM0 = 94, DQM1 = 83
5210 16:34:00.778786 DQ Delay:
5211 16:34:00.781408 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5212 16:34:00.784871 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5213 16:34:00.788363 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5214 16:34:00.791609 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5215 16:34:00.791684
5216 16:34:00.791742
5217 16:34:00.794801 ==
5218 16:34:00.797977 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 16:34:00.801759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 16:34:00.801835 ==
5221 16:34:00.801893
5222 16:34:00.801947
5223 16:34:00.804806 TX Vref Scan disable
5224 16:34:00.804882 == TX Byte 0 ==
5225 16:34:00.811725 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5226 16:34:00.814927 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5227 16:34:00.815035 == TX Byte 1 ==
5228 16:34:00.821490 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5229 16:34:00.824630 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5230 16:34:00.824746 ==
5231 16:34:00.827701 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 16:34:00.831579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 16:34:00.831655 ==
5234 16:34:00.831714
5235 16:34:00.831766
5236 16:34:00.834763 TX Vref Scan disable
5237 16:34:00.837888 == TX Byte 0 ==
5238 16:34:00.841054 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5239 16:34:00.844334 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5240 16:34:00.847916 == TX Byte 1 ==
5241 16:34:00.851022 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5242 16:34:00.854744 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5243 16:34:00.854820
5244 16:34:00.857810 [DATLAT]
5245 16:34:00.857886 Freq=933, CH0 RK0
5246 16:34:00.857945
5247 16:34:00.861341 DATLAT Default: 0xd
5248 16:34:00.861417 0, 0xFFFF, sum = 0
5249 16:34:00.864420 1, 0xFFFF, sum = 0
5250 16:34:00.864500 2, 0xFFFF, sum = 0
5251 16:34:00.867720 3, 0xFFFF, sum = 0
5252 16:34:00.867797 4, 0xFFFF, sum = 0
5253 16:34:00.871403 5, 0xFFFF, sum = 0
5254 16:34:00.871479 6, 0xFFFF, sum = 0
5255 16:34:00.874373 7, 0xFFFF, sum = 0
5256 16:34:00.874450 8, 0xFFFF, sum = 0
5257 16:34:00.878161 9, 0xFFFF, sum = 0
5258 16:34:00.878237 10, 0x0, sum = 1
5259 16:34:00.881393 11, 0x0, sum = 2
5260 16:34:00.881469 12, 0x0, sum = 3
5261 16:34:00.884373 13, 0x0, sum = 4
5262 16:34:00.884449 best_step = 11
5263 16:34:00.884507
5264 16:34:00.884562 ==
5265 16:34:00.887849 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 16:34:00.891085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 16:34:00.894609 ==
5268 16:34:00.894686 RX Vref Scan: 1
5269 16:34:00.894744
5270 16:34:00.897590 RX Vref 0 -> 0, step: 1
5271 16:34:00.897665
5272 16:34:00.901114 RX Delay -69 -> 252, step: 4
5273 16:34:00.901189
5274 16:34:00.904513 Set Vref, RX VrefLevel [Byte0]: 61
5275 16:34:00.907601 [Byte1]: 45
5276 16:34:00.907676
5277 16:34:00.910764 Final RX Vref Byte 0 = 61 to rank0
5278 16:34:00.913927 Final RX Vref Byte 1 = 45 to rank0
5279 16:34:00.917782 Final RX Vref Byte 0 = 61 to rank1
5280 16:34:00.920955 Final RX Vref Byte 1 = 45 to rank1==
5281 16:34:00.924208 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 16:34:00.927354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 16:34:00.927431 ==
5284 16:34:00.930421 DQS Delay:
5285 16:34:00.930497 DQS0 = 0, DQS1 = 0
5286 16:34:00.930557 DQM Delay:
5287 16:34:00.933987 DQM0 = 95, DQM1 = 82
5288 16:34:00.934063 DQ Delay:
5289 16:34:00.937147 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =94
5290 16:34:00.940812 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5291 16:34:00.944044 DQ8 =74, DQ9 =70, DQ10 =82, DQ11 =76
5292 16:34:00.947337 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =92
5293 16:34:00.947415
5294 16:34:00.947473
5295 16:34:00.957087 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5296 16:34:00.960305 CH0 RK0: MR19=505, MR18=1616
5297 16:34:00.963616 CH0_RK0: MR19=0x505, MR18=0x1616, DQSOSC=414, MR23=63, INC=63, DEC=42
5298 16:34:00.967057
5299 16:34:00.970708 ----->DramcWriteLeveling(PI) begin...
5300 16:34:00.970786 ==
5301 16:34:00.973966 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 16:34:00.977136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 16:34:00.977213 ==
5304 16:34:00.980201 Write leveling (Byte 0): 31 => 31
5305 16:34:00.983310 Write leveling (Byte 1): 30 => 30
5306 16:34:00.987048 DramcWriteLeveling(PI) end<-----
5307 16:34:00.987124
5308 16:34:00.987183 ==
5309 16:34:00.989972 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 16:34:00.993653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 16:34:00.993730 ==
5312 16:34:00.996681 [Gating] SW mode calibration
5313 16:34:01.003479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 16:34:01.010202 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 16:34:01.013290 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5316 16:34:01.016691 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 16:34:01.023301 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 16:34:01.026490 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 16:34:01.029711 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 16:34:01.036005 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 16:34:01.039596 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 16:34:01.042767 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (1 1)
5323 16:34:01.049809 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5324 16:34:01.052888 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 16:34:01.055975 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 16:34:01.062636 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 16:34:01.066388 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 16:34:01.069555 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 16:34:01.076273 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5330 16:34:01.079304 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5331 16:34:01.083076 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5332 16:34:01.089200 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 16:34:01.092364 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 16:34:01.096075 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 16:34:01.102927 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 16:34:01.106019 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 16:34:01.109010 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 16:34:01.116144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5339 16:34:01.119288 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5340 16:34:01.122343 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 16:34:01.129151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 16:34:01.132536 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 16:34:01.135879 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 16:34:01.139349 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 16:34:01.145632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 16:34:01.148863 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 16:34:01.152824 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 16:34:01.159010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 16:34:01.162678 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 16:34:01.165677 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 16:34:01.172615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 16:34:01.175836 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 16:34:01.178997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5354 16:34:01.185685 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5355 16:34:01.189202 Total UI for P1: 0, mck2ui 16
5356 16:34:01.192305 best dqsien dly found for B0: ( 1, 2, 24)
5357 16:34:01.195431 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 16:34:01.198687 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 16:34:01.202459 Total UI for P1: 0, mck2ui 16
5360 16:34:01.205482 best dqsien dly found for B1: ( 1, 3, 0)
5361 16:34:01.208754 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5362 16:34:01.212394 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5363 16:34:01.212479
5364 16:34:01.218645 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5365 16:34:01.221804 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5366 16:34:01.221880 [Gating] SW calibration Done
5367 16:34:01.225052 ==
5368 16:34:01.228381 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 16:34:01.232234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 16:34:01.232311 ==
5371 16:34:01.232369 RX Vref Scan: 0
5372 16:34:01.232424
5373 16:34:01.235389 RX Vref 0 -> 0, step: 1
5374 16:34:01.235464
5375 16:34:01.238365 RX Delay -80 -> 252, step: 8
5376 16:34:01.241752 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5377 16:34:01.245390 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5378 16:34:01.248415 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5379 16:34:01.255441 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5380 16:34:01.258218 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5381 16:34:01.261817 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5382 16:34:01.264900 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5383 16:34:01.268623 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5384 16:34:01.271756 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5385 16:34:01.278117 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5386 16:34:01.281970 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5387 16:34:01.285097 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5388 16:34:01.288266 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5389 16:34:01.294797 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5390 16:34:01.298036 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5391 16:34:01.301593 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5392 16:34:01.301668 ==
5393 16:34:01.304776 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 16:34:01.308488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 16:34:01.308564 ==
5396 16:34:01.311599 DQS Delay:
5397 16:34:01.311675 DQS0 = 0, DQS1 = 0
5398 16:34:01.311733 DQM Delay:
5399 16:34:01.314732 DQM0 = 92, DQM1 = 81
5400 16:34:01.314823 DQ Delay:
5401 16:34:01.318490 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5402 16:34:01.321669 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =107
5403 16:34:01.324896 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =75
5404 16:34:01.327959 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5405 16:34:01.328036
5406 16:34:01.328095
5407 16:34:01.328148 ==
5408 16:34:01.331757 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 16:34:01.338263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 16:34:01.338339 ==
5411 16:34:01.338397
5412 16:34:01.338451
5413 16:34:01.338502 TX Vref Scan disable
5414 16:34:01.341505 == TX Byte 0 ==
5415 16:34:01.345375 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5416 16:34:01.351352 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5417 16:34:01.351460 == TX Byte 1 ==
5418 16:34:01.355132 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5419 16:34:01.361515 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5420 16:34:01.361590 ==
5421 16:34:01.365046 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 16:34:01.367956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 16:34:01.368032 ==
5424 16:34:01.368090
5425 16:34:01.368143
5426 16:34:01.371563 TX Vref Scan disable
5427 16:34:01.371638 == TX Byte 0 ==
5428 16:34:01.377914 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5429 16:34:01.381077 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5430 16:34:01.381153 == TX Byte 1 ==
5431 16:34:01.387858 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5432 16:34:01.391156 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5433 16:34:01.391231
5434 16:34:01.391290 [DATLAT]
5435 16:34:01.394983 Freq=933, CH0 RK1
5436 16:34:01.395058
5437 16:34:01.395115 DATLAT Default: 0xb
5438 16:34:01.398239 0, 0xFFFF, sum = 0
5439 16:34:01.398365 1, 0xFFFF, sum = 0
5440 16:34:01.401373 2, 0xFFFF, sum = 0
5441 16:34:01.404344 3, 0xFFFF, sum = 0
5442 16:34:01.404437 4, 0xFFFF, sum = 0
5443 16:34:01.407872 5, 0xFFFF, sum = 0
5444 16:34:01.407952 6, 0xFFFF, sum = 0
5445 16:34:01.411307 7, 0xFFFF, sum = 0
5446 16:34:01.411390 8, 0xFFFF, sum = 0
5447 16:34:01.414801 9, 0xFFFF, sum = 0
5448 16:34:01.414916 10, 0x0, sum = 1
5449 16:34:01.417814 11, 0x0, sum = 2
5450 16:34:01.417906 12, 0x0, sum = 3
5451 16:34:01.420938 13, 0x0, sum = 4
5452 16:34:01.421004 best_step = 11
5453 16:34:01.421057
5454 16:34:01.421108 ==
5455 16:34:01.424511 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 16:34:01.427640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 16:34:01.427727 ==
5458 16:34:01.430737 RX Vref Scan: 0
5459 16:34:01.430823
5460 16:34:01.434520 RX Vref 0 -> 0, step: 1
5461 16:34:01.434583
5462 16:34:01.434637 RX Delay -77 -> 252, step: 4
5463 16:34:01.442113 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5464 16:34:01.445236 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5465 16:34:01.448537 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5466 16:34:01.452071 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5467 16:34:01.455148 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5468 16:34:01.462190 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5469 16:34:01.465449 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5470 16:34:01.468599 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5471 16:34:01.472431 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5472 16:34:01.475648 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5473 16:34:01.478953 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5474 16:34:01.485062 iDelay=199, Bit 11, Center 76 (-9 ~ 162) 172
5475 16:34:01.488472 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5476 16:34:01.491776 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5477 16:34:01.495029 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5478 16:34:01.498685 iDelay=199, Bit 15, Center 90 (3 ~ 178) 176
5479 16:34:01.501976 ==
5480 16:34:01.505387 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 16:34:01.508610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 16:34:01.508729 ==
5483 16:34:01.508789 DQS Delay:
5484 16:34:01.511669 DQS0 = 0, DQS1 = 0
5485 16:34:01.511744 DQM Delay:
5486 16:34:01.515505 DQM0 = 92, DQM1 = 83
5487 16:34:01.515582 DQ Delay:
5488 16:34:01.518604 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =90
5489 16:34:01.521475 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5490 16:34:01.524899 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5491 16:34:01.528088 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =90
5492 16:34:01.528164
5493 16:34:01.528222
5494 16:34:01.534782 [DQSOSCAuto] RK1, (LSB)MR18= 0x3214, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5495 16:34:01.538326 CH0 RK1: MR19=505, MR18=3214
5496 16:34:01.544600 CH0_RK1: MR19=0x505, MR18=0x3214, DQSOSC=406, MR23=63, INC=65, DEC=43
5497 16:34:01.547885 [RxdqsGatingPostProcess] freq 933
5498 16:34:01.554894 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 16:34:01.557974 best DQS0 dly(2T, 0.5T) = (0, 10)
5500 16:34:01.558050 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 16:34:01.560974 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5502 16:34:01.564829 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 16:34:01.568016 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 16:34:01.571252 best DQS1 dly(2T, 0.5T) = (0, 11)
5505 16:34:01.574474 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 16:34:01.578185 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5507 16:34:01.581415 Pre-setting of DQS Precalculation
5508 16:34:01.587680 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 16:34:01.587758 ==
5510 16:34:01.590905 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 16:34:01.594518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 16:34:01.594595 ==
5513 16:34:01.600715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 16:34:01.604367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5515 16:34:01.608317 [CA 0] Center 37 (7~67) winsize 61
5516 16:34:01.612092 [CA 1] Center 37 (7~68) winsize 62
5517 16:34:01.615078 [CA 2] Center 35 (5~65) winsize 61
5518 16:34:01.618680 [CA 3] Center 35 (5~65) winsize 61
5519 16:34:01.621513 [CA 4] Center 35 (5~65) winsize 61
5520 16:34:01.625083 [CA 5] Center 33 (4~63) winsize 60
5521 16:34:01.625159
5522 16:34:01.628171 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5523 16:34:01.628246
5524 16:34:01.631892 [CATrainingPosCal] consider 1 rank data
5525 16:34:01.634929 u2DelayCellTimex100 = 270/100 ps
5526 16:34:01.638585 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5527 16:34:01.645006 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5528 16:34:01.648328 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5529 16:34:01.651384 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5530 16:34:01.654589 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5531 16:34:01.658400 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5532 16:34:01.658476
5533 16:34:01.661508 CA PerBit enable=1, Macro0, CA PI delay=33
5534 16:34:01.661583
5535 16:34:01.664473 [CBTSetCACLKResult] CA Dly = 33
5536 16:34:01.668251 CS Dly: 6 (0~37)
5537 16:34:01.668326 ==
5538 16:34:01.671567 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 16:34:01.674705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 16:34:01.674782 ==
5541 16:34:01.681313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 16:34:01.684558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5543 16:34:01.688954 [CA 0] Center 37 (8~67) winsize 60
5544 16:34:01.692248 [CA 1] Center 37 (7~68) winsize 62
5545 16:34:01.695347 [CA 2] Center 35 (5~65) winsize 61
5546 16:34:01.698519 [CA 3] Center 34 (4~64) winsize 61
5547 16:34:01.702255 [CA 4] Center 35 (5~65) winsize 61
5548 16:34:01.705736 [CA 5] Center 34 (4~64) winsize 61
5549 16:34:01.705811
5550 16:34:01.709000 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5551 16:34:01.709075
5552 16:34:01.712114 [CATrainingPosCal] consider 2 rank data
5553 16:34:01.715182 u2DelayCellTimex100 = 270/100 ps
5554 16:34:01.718392 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5555 16:34:01.725105 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5556 16:34:01.728801 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5557 16:34:01.731780 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5558 16:34:01.735375 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5559 16:34:01.738339 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5560 16:34:01.738414
5561 16:34:01.741904 CA PerBit enable=1, Macro0, CA PI delay=33
5562 16:34:01.741980
5563 16:34:01.744911 [CBTSetCACLKResult] CA Dly = 33
5564 16:34:01.748416 CS Dly: 7 (0~39)
5565 16:34:01.748491
5566 16:34:01.751460 ----->DramcWriteLeveling(PI) begin...
5567 16:34:01.751538 ==
5568 16:34:01.755070 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 16:34:01.758548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 16:34:01.758655 ==
5571 16:34:01.761398 Write leveling (Byte 0): 28 => 28
5572 16:34:01.765150 Write leveling (Byte 1): 30 => 30
5573 16:34:01.768367 DramcWriteLeveling(PI) end<-----
5574 16:34:01.768443
5575 16:34:01.768501 ==
5576 16:34:01.771959 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 16:34:01.775011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 16:34:01.775096 ==
5579 16:34:01.778305 [Gating] SW mode calibration
5580 16:34:01.784619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 16:34:01.791750 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 16:34:01.794903 0 14 0 | B1->B0 | 3131 3131 | 1 1 | (1 1) (1 1)
5583 16:34:01.798054 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 16:34:01.805217 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 16:34:01.808364 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 16:34:01.811427 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 16:34:01.818340 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 16:34:01.821471 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 16:34:01.824560 0 14 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (1 0)
5590 16:34:01.831466 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5591 16:34:01.834647 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 16:34:01.837849 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 16:34:01.844683 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 16:34:01.847790 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 16:34:01.851519 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 16:34:01.857883 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 16:34:01.861277 0 15 28 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
5598 16:34:01.864518 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 16:34:01.871013 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 16:34:01.874619 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 16:34:01.877511 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 16:34:01.884199 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 16:34:01.887494 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 16:34:01.890803 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 16:34:01.897340 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5606 16:34:01.901153 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5607 16:34:01.904323 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 16:34:01.910529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 16:34:01.914344 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 16:34:01.917526 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 16:34:01.923960 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 16:34:01.927093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 16:34:01.930293 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 16:34:01.936850 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 16:34:01.940247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 16:34:01.943760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 16:34:01.946985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 16:34:01.953329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 16:34:01.957079 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 16:34:01.963286 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5621 16:34:01.966962 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5622 16:34:01.970162 Total UI for P1: 0, mck2ui 16
5623 16:34:01.973145 best dqsien dly found for B1: ( 1, 2, 24)
5624 16:34:01.976589 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5625 16:34:01.979949 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 16:34:01.983534 Total UI for P1: 0, mck2ui 16
5627 16:34:01.986477 best dqsien dly found for B0: ( 1, 2, 28)
5628 16:34:01.990144 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5629 16:34:01.996788 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5630 16:34:01.996864
5631 16:34:01.999654 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5632 16:34:02.003437 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5633 16:34:02.006222 [Gating] SW calibration Done
5634 16:34:02.006297 ==
5635 16:34:02.009458 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 16:34:02.013211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 16:34:02.013314 ==
5638 16:34:02.016387 RX Vref Scan: 0
5639 16:34:02.016463
5640 16:34:02.016558 RX Vref 0 -> 0, step: 1
5641 16:34:02.016641
5642 16:34:02.019599 RX Delay -80 -> 252, step: 8
5643 16:34:02.022856 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5644 16:34:02.029416 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5645 16:34:02.032567 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5646 16:34:02.035782 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5647 16:34:02.039597 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5648 16:34:02.042659 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5649 16:34:02.045714 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5650 16:34:02.052527 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5651 16:34:02.055856 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5652 16:34:02.058994 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5653 16:34:02.062117 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5654 16:34:02.065786 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5655 16:34:02.072509 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5656 16:34:02.075732 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5657 16:34:02.078821 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5658 16:34:02.082018 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5659 16:34:02.082094 ==
5660 16:34:02.085147 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 16:34:02.091933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 16:34:02.092009 ==
5663 16:34:02.092068 DQS Delay:
5664 16:34:02.092122 DQS0 = 0, DQS1 = 0
5665 16:34:02.095493 DQM Delay:
5666 16:34:02.095569 DQM0 = 95, DQM1 = 86
5667 16:34:02.098422 DQ Delay:
5668 16:34:02.101940 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5669 16:34:02.105196 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5670 16:34:02.108823 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5671 16:34:02.111687 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5672 16:34:02.111824
5673 16:34:02.111883
5674 16:34:02.111937 ==
5675 16:34:02.115092 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 16:34:02.118132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 16:34:02.118208 ==
5678 16:34:02.118266
5679 16:34:02.118320
5680 16:34:02.121730 TX Vref Scan disable
5681 16:34:02.121861 == TX Byte 0 ==
5682 16:34:02.128084 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5683 16:34:02.131888 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5684 16:34:02.131987 == TX Byte 1 ==
5685 16:34:02.138267 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5686 16:34:02.141365 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5687 16:34:02.141441 ==
5688 16:34:02.145136 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 16:34:02.148184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 16:34:02.148261 ==
5691 16:34:02.151299
5692 16:34:02.151410
5693 16:34:02.151530 TX Vref Scan disable
5694 16:34:02.154922 == TX Byte 0 ==
5695 16:34:02.158312 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 16:34:02.161292 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 16:34:02.165175 == TX Byte 1 ==
5698 16:34:02.168238 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5699 16:34:02.174686 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5700 16:34:02.174786
5701 16:34:02.174870 [DATLAT]
5702 16:34:02.174951 Freq=933, CH1 RK0
5703 16:34:02.175031
5704 16:34:02.178278 DATLAT Default: 0xd
5705 16:34:02.178354 0, 0xFFFF, sum = 0
5706 16:34:02.181445 1, 0xFFFF, sum = 0
5707 16:34:02.181522 2, 0xFFFF, sum = 0
5708 16:34:02.184572 3, 0xFFFF, sum = 0
5709 16:34:02.187714 4, 0xFFFF, sum = 0
5710 16:34:02.187791 5, 0xFFFF, sum = 0
5711 16:34:02.191504 6, 0xFFFF, sum = 0
5712 16:34:02.191580 7, 0xFFFF, sum = 0
5713 16:34:02.194696 8, 0xFFFF, sum = 0
5714 16:34:02.194774 9, 0xFFFF, sum = 0
5715 16:34:02.197865 10, 0x0, sum = 1
5716 16:34:02.197954 11, 0x0, sum = 2
5717 16:34:02.200983 12, 0x0, sum = 3
5718 16:34:02.201062 13, 0x0, sum = 4
5719 16:34:02.201122 best_step = 11
5720 16:34:02.204633
5721 16:34:02.204800 ==
5722 16:34:02.207989 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 16:34:02.210872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 16:34:02.210949 ==
5725 16:34:02.211008 RX Vref Scan: 1
5726 16:34:02.211063
5727 16:34:02.214342 RX Vref 0 -> 0, step: 1
5728 16:34:02.214417
5729 16:34:02.217511 RX Delay -61 -> 252, step: 4
5730 16:34:02.217586
5731 16:34:02.220619 Set Vref, RX VrefLevel [Byte0]: 57
5732 16:34:02.223872 [Byte1]: 48
5733 16:34:02.227410
5734 16:34:02.227485 Final RX Vref Byte 0 = 57 to rank0
5735 16:34:02.230661 Final RX Vref Byte 1 = 48 to rank0
5736 16:34:02.233827 Final RX Vref Byte 0 = 57 to rank1
5737 16:34:02.237027 Final RX Vref Byte 1 = 48 to rank1==
5738 16:34:02.240598 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 16:34:02.246890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 16:34:02.246966 ==
5741 16:34:02.247025 DQS Delay:
5742 16:34:02.250649 DQS0 = 0, DQS1 = 0
5743 16:34:02.250749 DQM Delay:
5744 16:34:02.250833 DQM0 = 95, DQM1 = 88
5745 16:34:02.253791 DQ Delay:
5746 16:34:02.256986 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5747 16:34:02.260791 DQ4 =94, DQ5 =104, DQ6 =104, DQ7 =92
5748 16:34:02.263700 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5749 16:34:02.267076 DQ12 =96, DQ13 =92, DQ14 =94, DQ15 =94
5750 16:34:02.267152
5751 16:34:02.267210
5752 16:34:02.273813 [DQSOSCAuto] RK0, (LSB)MR18= 0x30b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5753 16:34:02.276950 CH1 RK0: MR19=505, MR18=30B
5754 16:34:02.283782 CH1_RK0: MR19=0x505, MR18=0x30B, DQSOSC=418, MR23=63, INC=62, DEC=41
5755 16:34:02.283882
5756 16:34:02.287040 ----->DramcWriteLeveling(PI) begin...
5757 16:34:02.287117 ==
5758 16:34:02.290275 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 16:34:02.293989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 16:34:02.294065 ==
5761 16:34:02.297234 Write leveling (Byte 0): 25 => 25
5762 16:34:02.300458 Write leveling (Byte 1): 29 => 29
5763 16:34:02.303570 DramcWriteLeveling(PI) end<-----
5764 16:34:02.303652
5765 16:34:02.303714 ==
5766 16:34:02.306708 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 16:34:02.310482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 16:34:02.310558 ==
5769 16:34:02.313749 [Gating] SW mode calibration
5770 16:34:02.320147 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5771 16:34:02.326743 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5772 16:34:02.329949 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5773 16:34:02.336536 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 16:34:02.340095 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 16:34:02.342946 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 16:34:02.349821 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 16:34:02.353340 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5778 16:34:02.356751 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5779 16:34:02.363082 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5780 16:34:02.366394 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 16:34:02.369578 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 16:34:02.373189 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 16:34:02.379549 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 16:34:02.383395 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 16:34:02.386432 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 16:34:02.393191 0 15 24 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
5787 16:34:02.396218 0 15 28 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
5788 16:34:02.399943 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 16:34:02.406307 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 16:34:02.410095 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 16:34:02.413164 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 16:34:02.419890 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 16:34:02.423020 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 16:34:02.426195 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5795 16:34:02.432919 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5796 16:34:02.435859 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 16:34:02.439548 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 16:34:02.445855 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 16:34:02.449593 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 16:34:02.452762 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 16:34:02.459348 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 16:34:02.462601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 16:34:02.466371 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 16:34:02.472929 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 16:34:02.476091 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 16:34:02.479334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 16:34:02.486196 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 16:34:02.489146 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 16:34:02.492880 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 16:34:02.499041 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5811 16:34:02.499118 Total UI for P1: 0, mck2ui 16
5812 16:34:02.506046 best dqsien dly found for B0: ( 1, 2, 22)
5813 16:34:02.509188 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 16:34:02.512277 Total UI for P1: 0, mck2ui 16
5815 16:34:02.516189 best dqsien dly found for B1: ( 1, 2, 24)
5816 16:34:02.519349 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5817 16:34:02.522635 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5818 16:34:02.522711
5819 16:34:02.525818 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5820 16:34:02.528945 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5821 16:34:02.532803 [Gating] SW calibration Done
5822 16:34:02.532878 ==
5823 16:34:02.536006 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 16:34:02.539123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 16:34:02.539199 ==
5826 16:34:02.542198 RX Vref Scan: 0
5827 16:34:02.542273
5828 16:34:02.545682 RX Vref 0 -> 0, step: 1
5829 16:34:02.545766
5830 16:34:02.545832 RX Delay -80 -> 252, step: 8
5831 16:34:02.552014 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5832 16:34:02.555795 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5833 16:34:02.558839 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5834 16:34:02.562062 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5835 16:34:02.565325 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5836 16:34:02.572014 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5837 16:34:02.575687 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5838 16:34:02.578796 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5839 16:34:02.582388 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5840 16:34:02.585347 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5841 16:34:02.588996 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5842 16:34:02.595529 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5843 16:34:02.598516 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5844 16:34:02.602022 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5845 16:34:02.605143 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5846 16:34:02.608382 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5847 16:34:02.612209 ==
5848 16:34:02.612286 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 16:34:02.618611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 16:34:02.618687 ==
5851 16:34:02.618746 DQS Delay:
5852 16:34:02.621654 DQS0 = 0, DQS1 = 0
5853 16:34:02.621729 DQM Delay:
5854 16:34:02.625458 DQM0 = 93, DQM1 = 87
5855 16:34:02.625533 DQ Delay:
5856 16:34:02.628600 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5857 16:34:02.631942 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5858 16:34:02.635120 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5859 16:34:02.638470 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5860 16:34:02.638545
5861 16:34:02.638603
5862 16:34:02.638657 ==
5863 16:34:02.641691 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 16:34:02.644887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 16:34:02.644963 ==
5866 16:34:02.645022
5867 16:34:02.645076
5868 16:34:02.648698 TX Vref Scan disable
5869 16:34:02.651750 == TX Byte 0 ==
5870 16:34:02.654889 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5871 16:34:02.658406 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5872 16:34:02.661793 == TX Byte 1 ==
5873 16:34:02.664821 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5874 16:34:02.668537 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5875 16:34:02.668612 ==
5876 16:34:02.671633 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 16:34:02.677987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 16:34:02.678096 ==
5879 16:34:02.678158
5880 16:34:02.678217
5881 16:34:02.678295 TX Vref Scan disable
5882 16:34:02.682206 == TX Byte 0 ==
5883 16:34:02.685337 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5884 16:34:02.691923 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5885 16:34:02.692041 == TX Byte 1 ==
5886 16:34:02.695596 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5887 16:34:02.701725 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5888 16:34:02.701820
5889 16:34:02.701881 [DATLAT]
5890 16:34:02.701936 Freq=933, CH1 RK1
5891 16:34:02.701989
5892 16:34:02.705392 DATLAT Default: 0xb
5893 16:34:02.705468 0, 0xFFFF, sum = 0
5894 16:34:02.708503 1, 0xFFFF, sum = 0
5895 16:34:02.712119 2, 0xFFFF, sum = 0
5896 16:34:02.712197 3, 0xFFFF, sum = 0
5897 16:34:02.715307 4, 0xFFFF, sum = 0
5898 16:34:02.715385 5, 0xFFFF, sum = 0
5899 16:34:02.718410 6, 0xFFFF, sum = 0
5900 16:34:02.718488 7, 0xFFFF, sum = 0
5901 16:34:02.721628 8, 0xFFFF, sum = 0
5902 16:34:02.721705 9, 0xFFFF, sum = 0
5903 16:34:02.724831 10, 0x0, sum = 1
5904 16:34:02.724909 11, 0x0, sum = 2
5905 16:34:02.728701 12, 0x0, sum = 3
5906 16:34:02.728778 13, 0x0, sum = 4
5907 16:34:02.728837 best_step = 11
5908 16:34:02.728891
5909 16:34:02.731833 ==
5910 16:34:02.734961 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 16:34:02.738232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 16:34:02.738309 ==
5913 16:34:02.738369 RX Vref Scan: 0
5914 16:34:02.738423
5915 16:34:02.741954 RX Vref 0 -> 0, step: 1
5916 16:34:02.742046
5917 16:34:02.744999 RX Delay -69 -> 252, step: 4
5918 16:34:02.752042 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5919 16:34:02.755220 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5920 16:34:02.758263 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5921 16:34:02.761382 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5922 16:34:02.764846 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5923 16:34:02.768341 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5924 16:34:02.774708 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5925 16:34:02.777946 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5926 16:34:02.781653 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5927 16:34:02.784713 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5928 16:34:02.787836 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5929 16:34:02.795079 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5930 16:34:02.797981 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5931 16:34:02.801492 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5932 16:34:02.804558 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5933 16:34:02.808007 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5934 16:34:02.808109 ==
5935 16:34:02.811537 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 16:34:02.814678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 16:34:02.817867 ==
5938 16:34:02.817946 DQS Delay:
5939 16:34:02.818006 DQS0 = 0, DQS1 = 0
5940 16:34:02.821772 DQM Delay:
5941 16:34:02.821848 DQM0 = 91, DQM1 = 91
5942 16:34:02.825053 DQ Delay:
5943 16:34:02.828183 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5944 16:34:02.831413 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
5945 16:34:02.834700 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =86
5946 16:34:02.837923 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =96
5947 16:34:02.838010
5948 16:34:02.838071
5949 16:34:02.844914 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5950 16:34:02.847920 CH1 RK1: MR19=505, MR18=D21
5951 16:34:02.854828 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
5952 16:34:02.858012 [RxdqsGatingPostProcess] freq 933
5953 16:34:02.861254 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5954 16:34:02.864495 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 16:34:02.867728 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 16:34:02.870889 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 16:34:02.874450 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 16:34:02.877637 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 16:34:02.880839 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 16:34:02.884358 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 16:34:02.887847 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 16:34:02.890669 Pre-setting of DQS Precalculation
5963 16:34:02.894030 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5964 16:34:02.904351 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5965 16:34:02.910807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5966 16:34:02.910906
5967 16:34:02.910965
5968 16:34:02.914004 [Calibration Summary] 1866 Mbps
5969 16:34:02.914081 CH 0, Rank 0
5970 16:34:02.917456 SW Impedance : PASS
5971 16:34:02.917548 DUTY Scan : NO K
5972 16:34:02.920510 ZQ Calibration : PASS
5973 16:34:02.923974 Jitter Meter : NO K
5974 16:34:02.924077 CBT Training : PASS
5975 16:34:02.927514 Write leveling : PASS
5976 16:34:02.930784 RX DQS gating : PASS
5977 16:34:02.930866 RX DQ/DQS(RDDQC) : PASS
5978 16:34:02.933840 TX DQ/DQS : PASS
5979 16:34:02.936960 RX DATLAT : PASS
5980 16:34:02.937040 RX DQ/DQS(Engine): PASS
5981 16:34:02.940841 TX OE : NO K
5982 16:34:02.940929 All Pass.
5983 16:34:02.940989
5984 16:34:02.943970 CH 0, Rank 1
5985 16:34:02.944065 SW Impedance : PASS
5986 16:34:02.947044 DUTY Scan : NO K
5987 16:34:02.950316 ZQ Calibration : PASS
5988 16:34:02.950397 Jitter Meter : NO K
5989 16:34:02.953529 CBT Training : PASS
5990 16:34:02.953619 Write leveling : PASS
5991 16:34:02.956658 RX DQS gating : PASS
5992 16:34:02.959989 RX DQ/DQS(RDDQC) : PASS
5993 16:34:02.960066 TX DQ/DQS : PASS
5994 16:34:02.963802 RX DATLAT : PASS
5995 16:34:02.966984 RX DQ/DQS(Engine): PASS
5996 16:34:02.967063 TX OE : NO K
5997 16:34:02.970006 All Pass.
5998 16:34:02.970083
5999 16:34:02.970142 CH 1, Rank 0
6000 16:34:02.973265 SW Impedance : PASS
6001 16:34:02.973342 DUTY Scan : NO K
6002 16:34:02.976878 ZQ Calibration : PASS
6003 16:34:02.980029 Jitter Meter : NO K
6004 16:34:02.980106 CBT Training : PASS
6005 16:34:02.983012 Write leveling : PASS
6006 16:34:02.986881 RX DQS gating : PASS
6007 16:34:02.986958 RX DQ/DQS(RDDQC) : PASS
6008 16:34:02.990010 TX DQ/DQS : PASS
6009 16:34:02.993308 RX DATLAT : PASS
6010 16:34:02.993386 RX DQ/DQS(Engine): PASS
6011 16:34:02.996393 TX OE : NO K
6012 16:34:02.996470 All Pass.
6013 16:34:02.996530
6014 16:34:03.000026 CH 1, Rank 1
6015 16:34:03.000104 SW Impedance : PASS
6016 16:34:03.003636 DUTY Scan : NO K
6017 16:34:03.006726 ZQ Calibration : PASS
6018 16:34:03.006816 Jitter Meter : NO K
6019 16:34:03.009624 CBT Training : PASS
6020 16:34:03.009725 Write leveling : PASS
6021 16:34:03.013083 RX DQS gating : PASS
6022 16:34:03.016278 RX DQ/DQS(RDDQC) : PASS
6023 16:34:03.016356 TX DQ/DQS : PASS
6024 16:34:03.019941 RX DATLAT : PASS
6025 16:34:03.023331 RX DQ/DQS(Engine): PASS
6026 16:34:03.023406 TX OE : NO K
6027 16:34:03.026686 All Pass.
6028 16:34:03.026763
6029 16:34:03.026821 DramC Write-DBI off
6030 16:34:03.029412 PER_BANK_REFRESH: Hybrid Mode
6031 16:34:03.032792 TX_TRACKING: ON
6032 16:34:03.039638 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6033 16:34:03.042985 [FAST_K] Save calibration result to emmc
6034 16:34:03.046246 dramc_set_vcore_voltage set vcore to 650000
6035 16:34:03.049369 Read voltage for 400, 6
6036 16:34:03.049457 Vio18 = 0
6037 16:34:03.053187 Vcore = 650000
6038 16:34:03.053264 Vdram = 0
6039 16:34:03.053322 Vddq = 0
6040 16:34:03.056358 Vmddr = 0
6041 16:34:03.059652 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6042 16:34:03.065941 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6043 16:34:03.066027 MEM_TYPE=3, freq_sel=20
6044 16:34:03.069783 sv_algorithm_assistance_LP4_800
6045 16:34:03.076105 ============ PULL DRAM RESETB DOWN ============
6046 16:34:03.079309 ========== PULL DRAM RESETB DOWN end =========
6047 16:34:03.083023 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6048 16:34:03.086088 ===================================
6049 16:34:03.089285 LPDDR4 DRAM CONFIGURATION
6050 16:34:03.092427 ===================================
6051 16:34:03.096201 EX_ROW_EN[0] = 0x0
6052 16:34:03.096285 EX_ROW_EN[1] = 0x0
6053 16:34:03.099300 LP4Y_EN = 0x0
6054 16:34:03.099379 WORK_FSP = 0x0
6055 16:34:03.102519 WL = 0x2
6056 16:34:03.102597 RL = 0x2
6057 16:34:03.105619 BL = 0x2
6058 16:34:03.105695 RPST = 0x0
6059 16:34:03.109342 RD_PRE = 0x0
6060 16:34:03.109420 WR_PRE = 0x1
6061 16:34:03.112485 WR_PST = 0x0
6062 16:34:03.112561 DBI_WR = 0x0
6063 16:34:03.115534 DBI_RD = 0x0
6064 16:34:03.115611 OTF = 0x1
6065 16:34:03.119067 ===================================
6066 16:34:03.122169 ===================================
6067 16:34:03.125941 ANA top config
6068 16:34:03.129027 ===================================
6069 16:34:03.132679 DLL_ASYNC_EN = 0
6070 16:34:03.132774 ALL_SLAVE_EN = 1
6071 16:34:03.135901 NEW_RANK_MODE = 1
6072 16:34:03.138955 DLL_IDLE_MODE = 1
6073 16:34:03.142447 LP45_APHY_COMB_EN = 1
6074 16:34:03.142532 TX_ODT_DIS = 1
6075 16:34:03.145895 NEW_8X_MODE = 1
6076 16:34:03.148772 ===================================
6077 16:34:03.152239 ===================================
6078 16:34:03.155688 data_rate = 800
6079 16:34:03.159144 CKR = 1
6080 16:34:03.162411 DQ_P2S_RATIO = 4
6081 16:34:03.165485 ===================================
6082 16:34:03.169029 CA_P2S_RATIO = 4
6083 16:34:03.169139 DQ_CA_OPEN = 0
6084 16:34:03.172313 DQ_SEMI_OPEN = 1
6085 16:34:03.175610 CA_SEMI_OPEN = 1
6086 16:34:03.178858 CA_FULL_RATE = 0
6087 16:34:03.182061 DQ_CKDIV4_EN = 0
6088 16:34:03.185328 CA_CKDIV4_EN = 1
6089 16:34:03.185409 CA_PREDIV_EN = 0
6090 16:34:03.188454 PH8_DLY = 0
6091 16:34:03.192109 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6092 16:34:03.195314 DQ_AAMCK_DIV = 0
6093 16:34:03.198535 CA_AAMCK_DIV = 0
6094 16:34:03.202171 CA_ADMCK_DIV = 4
6095 16:34:03.202249 DQ_TRACK_CA_EN = 0
6096 16:34:03.205162 CA_PICK = 800
6097 16:34:03.208848 CA_MCKIO = 400
6098 16:34:03.211904 MCKIO_SEMI = 400
6099 16:34:03.214904 PLL_FREQ = 3016
6100 16:34:03.218262 DQ_UI_PI_RATIO = 32
6101 16:34:03.221876 CA_UI_PI_RATIO = 32
6102 16:34:03.224985 ===================================
6103 16:34:03.228811 ===================================
6104 16:34:03.228892 memory_type:LPDDR4
6105 16:34:03.231839 GP_NUM : 10
6106 16:34:03.234953 SRAM_EN : 1
6107 16:34:03.235033 MD32_EN : 0
6108 16:34:03.238687 ===================================
6109 16:34:03.241886 [ANA_INIT] >>>>>>>>>>>>>>
6110 16:34:03.245000 <<<<<< [CONFIGURE PHASE]: ANA_TX
6111 16:34:03.248209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6112 16:34:03.251774 ===================================
6113 16:34:03.255360 data_rate = 800,PCW = 0X7400
6114 16:34:03.258548 ===================================
6115 16:34:03.261709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6116 16:34:03.265330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 16:34:03.278460 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 16:34:03.281557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6119 16:34:03.285305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6120 16:34:03.288308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6121 16:34:03.291402 [ANA_INIT] flow start
6122 16:34:03.295086 [ANA_INIT] PLL >>>>>>>>
6123 16:34:03.295168 [ANA_INIT] PLL <<<<<<<<
6124 16:34:03.298360 [ANA_INIT] MIDPI >>>>>>>>
6125 16:34:03.301338 [ANA_INIT] MIDPI <<<<<<<<
6126 16:34:03.301419 [ANA_INIT] DLL >>>>>>>>
6127 16:34:03.305113 [ANA_INIT] flow end
6128 16:34:03.308156 ============ LP4 DIFF to SE enter ============
6129 16:34:03.311909 ============ LP4 DIFF to SE exit ============
6130 16:34:03.314920 [ANA_INIT] <<<<<<<<<<<<<
6131 16:34:03.317956 [Flow] Enable top DCM control >>>>>
6132 16:34:03.321783 [Flow] Enable top DCM control <<<<<
6133 16:34:03.324739 Enable DLL master slave shuffle
6134 16:34:03.331501 ==============================================================
6135 16:34:03.331597 Gating Mode config
6136 16:34:03.338376 ==============================================================
6137 16:34:03.338468 Config description:
6138 16:34:03.348034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6139 16:34:03.354804 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6140 16:34:03.361601 SELPH_MODE 0: By rank 1: By Phase
6141 16:34:03.364601 ==============================================================
6142 16:34:03.367940 GAT_TRACK_EN = 0
6143 16:34:03.370977 RX_GATING_MODE = 2
6144 16:34:03.374100 RX_GATING_TRACK_MODE = 2
6145 16:34:03.377676 SELPH_MODE = 1
6146 16:34:03.381081 PICG_EARLY_EN = 1
6147 16:34:03.384528 VALID_LAT_VALUE = 1
6148 16:34:03.390938 ==============================================================
6149 16:34:03.394208 Enter into Gating configuration >>>>
6150 16:34:03.397391 Exit from Gating configuration <<<<
6151 16:34:03.401090 Enter into DVFS_PRE_config >>>>>
6152 16:34:03.410594 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6153 16:34:03.414383 Exit from DVFS_PRE_config <<<<<
6154 16:34:03.417363 Enter into PICG configuration >>>>
6155 16:34:03.420938 Exit from PICG configuration <<<<
6156 16:34:03.424011 [RX_INPUT] configuration >>>>>
6157 16:34:03.424092 [RX_INPUT] configuration <<<<<
6158 16:34:03.430843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6159 16:34:03.437152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6160 16:34:03.440866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 16:34:03.447384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 16:34:03.454200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 16:34:03.460511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 16:34:03.464064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6165 16:34:03.467100 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6166 16:34:03.474021 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6167 16:34:03.477144 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6168 16:34:03.480372 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6169 16:34:03.487146 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 16:34:03.490610 ===================================
6171 16:34:03.490696 LPDDR4 DRAM CONFIGURATION
6172 16:34:03.494086 ===================================
6173 16:34:03.497396 EX_ROW_EN[0] = 0x0
6174 16:34:03.497476 EX_ROW_EN[1] = 0x0
6175 16:34:03.500568 LP4Y_EN = 0x0
6176 16:34:03.500652 WORK_FSP = 0x0
6177 16:34:03.503633 WL = 0x2
6178 16:34:03.503709 RL = 0x2
6179 16:34:03.507410 BL = 0x2
6180 16:34:03.510604 RPST = 0x0
6181 16:34:03.510682 RD_PRE = 0x0
6182 16:34:03.513645 WR_PRE = 0x1
6183 16:34:03.513722 WR_PST = 0x0
6184 16:34:03.517333 DBI_WR = 0x0
6185 16:34:03.517411 DBI_RD = 0x0
6186 16:34:03.520417 OTF = 0x1
6187 16:34:03.523497 ===================================
6188 16:34:03.527127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6189 16:34:03.530389 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6190 16:34:03.533392 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 16:34:03.537089 ===================================
6192 16:34:03.540251 LPDDR4 DRAM CONFIGURATION
6193 16:34:03.543453 ===================================
6194 16:34:03.546711 EX_ROW_EN[0] = 0x10
6195 16:34:03.546790 EX_ROW_EN[1] = 0x0
6196 16:34:03.550539 LP4Y_EN = 0x0
6197 16:34:03.550617 WORK_FSP = 0x0
6198 16:34:03.553594 WL = 0x2
6199 16:34:03.553671 RL = 0x2
6200 16:34:03.556846 BL = 0x2
6201 16:34:03.556927 RPST = 0x0
6202 16:34:03.560082 RD_PRE = 0x0
6203 16:34:03.563457 WR_PRE = 0x1
6204 16:34:03.563537 WR_PST = 0x0
6205 16:34:03.567075 DBI_WR = 0x0
6206 16:34:03.567153 DBI_RD = 0x0
6207 16:34:03.570106 OTF = 0x1
6208 16:34:03.573187 ===================================
6209 16:34:03.576964 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6210 16:34:03.582028 nWR fixed to 30
6211 16:34:03.585335 [ModeRegInit_LP4] CH0 RK0
6212 16:34:03.585417 [ModeRegInit_LP4] CH0 RK1
6213 16:34:03.588573 [ModeRegInit_LP4] CH1 RK0
6214 16:34:03.591716 [ModeRegInit_LP4] CH1 RK1
6215 16:34:03.591830 match AC timing 19
6216 16:34:03.598820 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6217 16:34:03.601679 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6218 16:34:03.605323 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6219 16:34:03.611571 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6220 16:34:03.615432 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6221 16:34:03.615519 ==
6222 16:34:03.618534 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 16:34:03.621567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 16:34:03.621652 ==
6225 16:34:03.628433 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 16:34:03.634887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6227 16:34:03.638150 [CA 0] Center 36 (8~64) winsize 57
6228 16:34:03.641309 [CA 1] Center 36 (8~64) winsize 57
6229 16:34:03.645209 [CA 2] Center 36 (8~64) winsize 57
6230 16:34:03.648435 [CA 3] Center 36 (8~64) winsize 57
6231 16:34:03.648513 [CA 4] Center 36 (8~64) winsize 57
6232 16:34:03.651559 [CA 5] Center 36 (8~64) winsize 57
6233 16:34:03.651628
6234 16:34:03.657905 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6235 16:34:03.658007
6236 16:34:03.661740 [CATrainingPosCal] consider 1 rank data
6237 16:34:03.664833 u2DelayCellTimex100 = 270/100 ps
6238 16:34:03.667878 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 16:34:03.671246 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 16:34:03.674859 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 16:34:03.677781 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 16:34:03.681331 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 16:34:03.684547 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 16:34:03.684681
6245 16:34:03.688359 CA PerBit enable=1, Macro0, CA PI delay=36
6246 16:34:03.688438
6247 16:34:03.691497 [CBTSetCACLKResult] CA Dly = 36
6248 16:34:03.694684 CS Dly: 1 (0~32)
6249 16:34:03.694762 ==
6250 16:34:03.697865 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 16:34:03.700957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 16:34:03.701039 ==
6253 16:34:03.707663 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 16:34:03.714623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6255 16:34:03.717897 [CA 0] Center 36 (8~64) winsize 57
6256 16:34:03.717985 [CA 1] Center 36 (8~64) winsize 57
6257 16:34:03.721112 [CA 2] Center 36 (8~64) winsize 57
6258 16:34:03.724258 [CA 3] Center 36 (8~64) winsize 57
6259 16:34:03.727942 [CA 4] Center 36 (8~64) winsize 57
6260 16:34:03.731179 [CA 5] Center 36 (8~64) winsize 57
6261 16:34:03.731262
6262 16:34:03.734367 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6263 16:34:03.734454
6264 16:34:03.737934 [CATrainingPosCal] consider 2 rank data
6265 16:34:03.740807 u2DelayCellTimex100 = 270/100 ps
6266 16:34:03.744462 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 16:34:03.751116 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 16:34:03.754282 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 16:34:03.757522 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 16:34:03.760748 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 16:34:03.763893 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 16:34:03.763978
6273 16:34:03.767155 CA PerBit enable=1, Macro0, CA PI delay=36
6274 16:34:03.767233
6275 16:34:03.770833 [CBTSetCACLKResult] CA Dly = 36
6276 16:34:03.773823 CS Dly: 1 (0~32)
6277 16:34:03.773903
6278 16:34:03.777622 ----->DramcWriteLeveling(PI) begin...
6279 16:34:03.777703 ==
6280 16:34:03.780756 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 16:34:03.784193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 16:34:03.784276 ==
6283 16:34:03.787341 Write leveling (Byte 0): 40 => 8
6284 16:34:03.790564 Write leveling (Byte 1): 40 => 8
6285 16:34:03.793745 DramcWriteLeveling(PI) end<-----
6286 16:34:03.793824
6287 16:34:03.793884 ==
6288 16:34:03.796931 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 16:34:03.800854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 16:34:03.800951 ==
6291 16:34:03.804053 [Gating] SW mode calibration
6292 16:34:03.810274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6293 16:34:03.817565 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6294 16:34:03.820519 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 16:34:03.823501 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 16:34:03.830175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 16:34:03.833964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 16:34:03.836834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 16:34:03.843716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 16:34:03.846873 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 16:34:03.850487 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 16:34:03.857270 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 16:34:03.857383 Total UI for P1: 0, mck2ui 16
6304 16:34:03.860390 best dqsien dly found for B0: ( 0, 14, 24)
6305 16:34:03.863667 Total UI for P1: 0, mck2ui 16
6306 16:34:03.866745 best dqsien dly found for B1: ( 0, 14, 24)
6307 16:34:03.870704 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6308 16:34:03.876815 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6309 16:34:03.876914
6310 16:34:03.880503 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 16:34:03.883822 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 16:34:03.886971 [Gating] SW calibration Done
6313 16:34:03.887044 ==
6314 16:34:03.890020 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 16:34:03.893773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 16:34:03.893848 ==
6317 16:34:03.896860 RX Vref Scan: 0
6318 16:34:03.896927
6319 16:34:03.896979 RX Vref 0 -> 0, step: 1
6320 16:34:03.897030
6321 16:34:03.900153 RX Delay -410 -> 252, step: 16
6322 16:34:03.906975 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6323 16:34:03.910070 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6324 16:34:03.913104 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6325 16:34:03.916905 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6326 16:34:03.923099 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6327 16:34:03.926175 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6328 16:34:03.930019 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6329 16:34:03.933054 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6330 16:34:03.939373 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6331 16:34:03.942919 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6332 16:34:03.946727 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6333 16:34:03.949583 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6334 16:34:03.956093 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6335 16:34:03.959761 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6336 16:34:03.962991 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6337 16:34:03.966170 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6338 16:34:03.969346 ==
6339 16:34:03.969421 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 16:34:03.976366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 16:34:03.976479 ==
6342 16:34:03.976565 DQS Delay:
6343 16:34:03.979416 DQS0 = 59, DQS1 = 59
6344 16:34:03.979494 DQM Delay:
6345 16:34:03.982464 DQM0 = 18, DQM1 = 10
6346 16:34:03.982548 DQ Delay:
6347 16:34:03.986124 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6348 16:34:03.989447 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6349 16:34:03.992474 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6350 16:34:03.996130 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6351 16:34:03.996212
6352 16:34:03.996271
6353 16:34:03.996330 ==
6354 16:34:03.999034 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 16:34:04.002896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 16:34:04.002976 ==
6357 16:34:04.003036
6358 16:34:04.003089
6359 16:34:04.006037 TX Vref Scan disable
6360 16:34:04.006116 == TX Byte 0 ==
6361 16:34:04.012535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 16:34:04.015709 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 16:34:04.015820 == TX Byte 1 ==
6364 16:34:04.022386 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 16:34:04.026087 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 16:34:04.026172 ==
6367 16:34:04.029024 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 16:34:04.032637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 16:34:04.032737 ==
6370 16:34:04.032796
6371 16:34:04.032850
6372 16:34:04.035821 TX Vref Scan disable
6373 16:34:04.035899 == TX Byte 0 ==
6374 16:34:04.042844 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 16:34:04.046059 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 16:34:04.046140 == TX Byte 1 ==
6377 16:34:04.052550 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 16:34:04.055529 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 16:34:04.055636
6380 16:34:04.055720 [DATLAT]
6381 16:34:04.058979 Freq=400, CH0 RK0
6382 16:34:04.059070
6383 16:34:04.059129 DATLAT Default: 0xf
6384 16:34:04.062309 0, 0xFFFF, sum = 0
6385 16:34:04.062389 1, 0xFFFF, sum = 0
6386 16:34:04.065606 2, 0xFFFF, sum = 0
6387 16:34:04.065685 3, 0xFFFF, sum = 0
6388 16:34:04.069250 4, 0xFFFF, sum = 0
6389 16:34:04.069333 5, 0xFFFF, sum = 0
6390 16:34:04.072357 6, 0xFFFF, sum = 0
6391 16:34:04.072435 7, 0xFFFF, sum = 0
6392 16:34:04.075601 8, 0xFFFF, sum = 0
6393 16:34:04.075678 9, 0xFFFF, sum = 0
6394 16:34:04.078918 10, 0xFFFF, sum = 0
6395 16:34:04.082039 11, 0xFFFF, sum = 0
6396 16:34:04.082122 12, 0xFFFF, sum = 0
6397 16:34:04.085845 13, 0x0, sum = 1
6398 16:34:04.085926 14, 0x0, sum = 2
6399 16:34:04.088892 15, 0x0, sum = 3
6400 16:34:04.088972 16, 0x0, sum = 4
6401 16:34:04.089031 best_step = 14
6402 16:34:04.089085
6403 16:34:04.091974 ==
6404 16:34:04.095332 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 16:34:04.098550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 16:34:04.098632 ==
6407 16:34:04.098692 RX Vref Scan: 1
6408 16:34:04.098746
6409 16:34:04.102197 RX Vref 0 -> 0, step: 1
6410 16:34:04.102280
6411 16:34:04.105235 RX Delay -359 -> 252, step: 8
6412 16:34:04.105312
6413 16:34:04.108970 Set Vref, RX VrefLevel [Byte0]: 61
6414 16:34:04.112145 [Byte1]: 45
6415 16:34:04.116080
6416 16:34:04.116168 Final RX Vref Byte 0 = 61 to rank0
6417 16:34:04.119184 Final RX Vref Byte 1 = 45 to rank0
6418 16:34:04.122277 Final RX Vref Byte 0 = 61 to rank1
6419 16:34:04.125433 Final RX Vref Byte 1 = 45 to rank1==
6420 16:34:04.129026 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 16:34:04.135443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 16:34:04.135547 ==
6423 16:34:04.135610 DQS Delay:
6424 16:34:04.139118 DQS0 = 60, DQS1 = 68
6425 16:34:04.139212 DQM Delay:
6426 16:34:04.139299 DQM0 = 14, DQM1 = 13
6427 16:34:04.142258 DQ Delay:
6428 16:34:04.145496 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6429 16:34:04.148706 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6430 16:34:04.148815 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6431 16:34:04.152503 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6432 16:34:04.155528
6433 16:34:04.155608
6434 16:34:04.162519 [DQSOSCAuto] RK0, (LSB)MR18= 0x8382, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6435 16:34:04.165483 CH0 RK0: MR19=C0C, MR18=8382
6436 16:34:04.171843 CH0_RK0: MR19=0xC0C, MR18=0x8382, DQSOSC=393, MR23=63, INC=382, DEC=254
6437 16:34:04.171942 ==
6438 16:34:04.175228 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 16:34:04.178582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 16:34:04.178664 ==
6441 16:34:04.182023 [Gating] SW mode calibration
6442 16:34:04.188911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 16:34:04.195261 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6444 16:34:04.198321 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 16:34:04.202222 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 16:34:04.208572 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 16:34:04.212161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 16:34:04.215054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 16:34:04.221946 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 16:34:04.225090 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 16:34:04.228294 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 16:34:04.235157 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 16:34:04.235261 Total UI for P1: 0, mck2ui 16
6454 16:34:04.238208 best dqsien dly found for B0: ( 0, 14, 24)
6455 16:34:04.241931 Total UI for P1: 0, mck2ui 16
6456 16:34:04.244908 best dqsien dly found for B1: ( 0, 14, 24)
6457 16:34:04.251892 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6458 16:34:04.255095 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6459 16:34:04.255193
6460 16:34:04.258161 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 16:34:04.261350 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 16:34:04.264799 [Gating] SW calibration Done
6463 16:34:04.264877 ==
6464 16:34:04.267859 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 16:34:04.271779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 16:34:04.271869 ==
6467 16:34:04.274979 RX Vref Scan: 0
6468 16:34:04.275058
6469 16:34:04.275117 RX Vref 0 -> 0, step: 1
6470 16:34:04.275193
6471 16:34:04.277970 RX Delay -410 -> 252, step: 16
6472 16:34:04.284818 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6473 16:34:04.287834 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6474 16:34:04.291251 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6475 16:34:04.294423 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6476 16:34:04.301073 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6477 16:34:04.304916 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6478 16:34:04.307970 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6479 16:34:04.311122 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6480 16:34:04.318062 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6481 16:34:04.321173 iDelay=230, Bit 9, Center -67 (-314 ~ 181) 496
6482 16:34:04.324742 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6483 16:34:04.327764 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6484 16:34:04.334071 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6485 16:34:04.337969 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6486 16:34:04.341215 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6487 16:34:04.344184 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6488 16:34:04.347892 ==
6489 16:34:04.347977 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 16:34:04.354108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 16:34:04.354209 ==
6492 16:34:04.354273 DQS Delay:
6493 16:34:04.357221 DQS0 = 59, DQS1 = 67
6494 16:34:04.357321 DQM Delay:
6495 16:34:04.361127 DQM0 = 16, DQM1 = 17
6496 16:34:04.361211 DQ Delay:
6497 16:34:04.364369 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6498 16:34:04.367490 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6499 16:34:04.370543 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6500 16:34:04.373988 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6501 16:34:04.374075
6502 16:34:04.374134
6503 16:34:04.374188 ==
6504 16:34:04.377137 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 16:34:04.380853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 16:34:04.380959 ==
6507 16:34:04.381019
6508 16:34:04.381108
6509 16:34:04.383991 TX Vref Scan disable
6510 16:34:04.384068 == TX Byte 0 ==
6511 16:34:04.390495 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6512 16:34:04.393662 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6513 16:34:04.393748 == TX Byte 1 ==
6514 16:34:04.400371 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6515 16:34:04.403800 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6516 16:34:04.403914 ==
6517 16:34:04.407207 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 16:34:04.410244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 16:34:04.410444 ==
6520 16:34:04.410547
6521 16:34:04.410614
6522 16:34:04.413774 TX Vref Scan disable
6523 16:34:04.416888 == TX Byte 0 ==
6524 16:34:04.420040 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6525 16:34:04.423324 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6526 16:34:04.423441 == TX Byte 1 ==
6527 16:34:04.430235 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6528 16:34:04.433609 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6529 16:34:04.433698
6530 16:34:04.433758 [DATLAT]
6531 16:34:04.436561 Freq=400, CH0 RK1
6532 16:34:04.436639
6533 16:34:04.436743 DATLAT Default: 0xe
6534 16:34:04.439825 0, 0xFFFF, sum = 0
6535 16:34:04.439905 1, 0xFFFF, sum = 0
6536 16:34:04.443674 2, 0xFFFF, sum = 0
6537 16:34:04.443756 3, 0xFFFF, sum = 0
6538 16:34:04.446944 4, 0xFFFF, sum = 0
6539 16:34:04.450059 5, 0xFFFF, sum = 0
6540 16:34:04.450140 6, 0xFFFF, sum = 0
6541 16:34:04.453671 7, 0xFFFF, sum = 0
6542 16:34:04.453754 8, 0xFFFF, sum = 0
6543 16:34:04.456540 9, 0xFFFF, sum = 0
6544 16:34:04.456662 10, 0xFFFF, sum = 0
6545 16:34:04.459714 11, 0xFFFF, sum = 0
6546 16:34:04.459799 12, 0xFFFF, sum = 0
6547 16:34:04.463483 13, 0x0, sum = 1
6548 16:34:04.463557 14, 0x0, sum = 2
6549 16:34:04.466757 15, 0x0, sum = 3
6550 16:34:04.466838 16, 0x0, sum = 4
6551 16:34:04.469958 best_step = 14
6552 16:34:04.470036
6553 16:34:04.470095 ==
6554 16:34:04.473136 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 16:34:04.476231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 16:34:04.476378 ==
6557 16:34:04.476494 RX Vref Scan: 0
6558 16:34:04.479895
6559 16:34:04.480013 RX Vref 0 -> 0, step: 1
6560 16:34:04.480111
6561 16:34:04.483121 RX Delay -359 -> 252, step: 8
6562 16:34:04.490310 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6563 16:34:04.493559 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6564 16:34:04.496874 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6565 16:34:04.500170 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6566 16:34:04.506818 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6567 16:34:04.510202 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6568 16:34:04.514028 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6569 16:34:04.517216 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6570 16:34:04.523695 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6571 16:34:04.527025 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6572 16:34:04.530330 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6573 16:34:04.536859 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6574 16:34:04.540502 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6575 16:34:04.543473 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6576 16:34:04.546870 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6577 16:34:04.553138 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6578 16:34:04.553241 ==
6579 16:34:04.556454 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 16:34:04.560138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 16:34:04.560254 ==
6582 16:34:04.560315 DQS Delay:
6583 16:34:04.563293 DQS0 = 60, DQS1 = 68
6584 16:34:04.563374 DQM Delay:
6585 16:34:04.566380 DQM0 = 11, DQM1 = 13
6586 16:34:04.566461 DQ Delay:
6587 16:34:04.570254 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6588 16:34:04.573420 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6589 16:34:04.576555 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6590 16:34:04.579687 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6591 16:34:04.579769
6592 16:34:04.579829
6593 16:34:04.586625 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6594 16:34:04.589646 CH0 RK1: MR19=C0C, MR18=C77D
6595 16:34:04.596516 CH0_RK1: MR19=0xC0C, MR18=0xC77D, DQSOSC=385, MR23=63, INC=398, DEC=265
6596 16:34:04.599683 [RxdqsGatingPostProcess] freq 400
6597 16:34:04.606264 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6598 16:34:04.609703 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 16:34:04.609811 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 16:34:04.613034 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 16:34:04.616246 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 16:34:04.619849 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 16:34:04.622904 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 16:34:04.626494 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 16:34:04.629580 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 16:34:04.632663 Pre-setting of DQS Precalculation
6607 16:34:04.639701 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6608 16:34:04.639805 ==
6609 16:34:04.642946 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 16:34:04.645872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 16:34:04.645962 ==
6612 16:34:04.652979 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 16:34:04.656067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6614 16:34:04.659355 [CA 0] Center 36 (8~64) winsize 57
6615 16:34:04.662543 [CA 1] Center 36 (8~64) winsize 57
6616 16:34:04.666172 [CA 2] Center 36 (8~64) winsize 57
6617 16:34:04.669135 [CA 3] Center 36 (8~64) winsize 57
6618 16:34:04.672898 [CA 4] Center 36 (8~64) winsize 57
6619 16:34:04.676058 [CA 5] Center 36 (8~64) winsize 57
6620 16:34:04.676146
6621 16:34:04.679120 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6622 16:34:04.679226
6623 16:34:04.682356 [CATrainingPosCal] consider 1 rank data
6624 16:34:04.685707 u2DelayCellTimex100 = 270/100 ps
6625 16:34:04.689400 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 16:34:04.692718 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 16:34:04.699531 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 16:34:04.702546 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 16:34:04.705739 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 16:34:04.708903 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 16:34:04.708988
6632 16:34:04.712658 CA PerBit enable=1, Macro0, CA PI delay=36
6633 16:34:04.712768
6634 16:34:04.715948 [CBTSetCACLKResult] CA Dly = 36
6635 16:34:04.716031 CS Dly: 1 (0~32)
6636 16:34:04.716112 ==
6637 16:34:04.719138 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 16:34:04.725738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 16:34:04.725846 ==
6640 16:34:04.729533 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 16:34:04.735724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6642 16:34:04.738805 [CA 0] Center 36 (8~64) winsize 57
6643 16:34:04.742783 [CA 1] Center 36 (8~64) winsize 57
6644 16:34:04.745968 [CA 2] Center 36 (8~64) winsize 57
6645 16:34:04.749118 [CA 3] Center 36 (8~64) winsize 57
6646 16:34:04.752280 [CA 4] Center 36 (8~64) winsize 57
6647 16:34:04.755335 [CA 5] Center 36 (8~64) winsize 57
6648 16:34:04.755424
6649 16:34:04.759066 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6650 16:34:04.759159
6651 16:34:04.762249 [CATrainingPosCal] consider 2 rank data
6652 16:34:04.765723 u2DelayCellTimex100 = 270/100 ps
6653 16:34:04.769302 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 16:34:04.772383 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 16:34:04.775746 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 16:34:04.778951 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 16:34:04.782114 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 16:34:04.788580 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 16:34:04.788686
6660 16:34:04.792467 CA PerBit enable=1, Macro0, CA PI delay=36
6661 16:34:04.792550
6662 16:34:04.795615 [CBTSetCACLKResult] CA Dly = 36
6663 16:34:04.795717 CS Dly: 1 (0~32)
6664 16:34:04.795802
6665 16:34:04.798695 ----->DramcWriteLeveling(PI) begin...
6666 16:34:04.798775 ==
6667 16:34:04.802442 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 16:34:04.805601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 16:34:04.808589 ==
6670 16:34:04.808733 Write leveling (Byte 0): 40 => 8
6671 16:34:04.812182 Write leveling (Byte 1): 40 => 8
6672 16:34:04.815428 DramcWriteLeveling(PI) end<-----
6673 16:34:04.815512
6674 16:34:04.815590 ==
6675 16:34:04.818605 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 16:34:04.825121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 16:34:04.825282 ==
6678 16:34:04.828740 [Gating] SW mode calibration
6679 16:34:04.835313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6680 16:34:04.838532 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6681 16:34:04.844879 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6682 16:34:04.848240 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 16:34:04.851399 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 16:34:04.858562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 16:34:04.861678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 16:34:04.864807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 16:34:04.871695 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 16:34:04.874630 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 16:34:04.878301 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 16:34:04.881437 Total UI for P1: 0, mck2ui 16
6691 16:34:04.884771 best dqsien dly found for B0: ( 0, 14, 24)
6692 16:34:04.887804 Total UI for P1: 0, mck2ui 16
6693 16:34:04.891641 best dqsien dly found for B1: ( 0, 14, 24)
6694 16:34:04.894761 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6695 16:34:04.897989 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6696 16:34:04.898071
6697 16:34:04.901196 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 16:34:04.908012 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 16:34:04.908114 [Gating] SW calibration Done
6700 16:34:04.911097 ==
6701 16:34:04.911176 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 16:34:04.917844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 16:34:04.917937 ==
6704 16:34:04.917997 RX Vref Scan: 0
6705 16:34:04.918052
6706 16:34:04.921005 RX Vref 0 -> 0, step: 1
6707 16:34:04.921087
6708 16:34:04.924302 RX Delay -410 -> 252, step: 16
6709 16:34:04.927424 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6710 16:34:04.931218 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6711 16:34:04.937337 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6712 16:34:04.940867 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6713 16:34:04.943969 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6714 16:34:04.947584 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6715 16:34:04.954563 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6716 16:34:04.957605 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6717 16:34:04.960879 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6718 16:34:04.964058 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6719 16:34:04.970843 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6720 16:34:04.973978 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6721 16:34:04.977102 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6722 16:34:04.984209 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6723 16:34:04.987388 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6724 16:34:04.990333 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6725 16:34:04.990429 ==
6726 16:34:04.993845 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 16:34:04.997009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 16:34:05.000465 ==
6729 16:34:05.000577 DQS Delay:
6730 16:34:05.000691 DQS0 = 51, DQS1 = 67
6731 16:34:05.003822 DQM Delay:
6732 16:34:05.003976 DQM0 = 12, DQM1 = 19
6733 16:34:05.007319 DQ Delay:
6734 16:34:05.007430 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6735 16:34:05.010684 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6736 16:34:05.013382 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6737 16:34:05.017372 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6738 16:34:05.017485
6739 16:34:05.017598
6740 16:34:05.019983 ==
6741 16:34:05.020122 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 16:34:05.027301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 16:34:05.027403 ==
6744 16:34:05.027465
6745 16:34:05.027520
6746 16:34:05.031023 TX Vref Scan disable
6747 16:34:05.031104 == TX Byte 0 ==
6748 16:34:05.033696 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 16:34:05.040303 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 16:34:05.040423 == TX Byte 1 ==
6751 16:34:05.043429 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 16:34:05.047079 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 16:34:05.050038 ==
6754 16:34:05.053625 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 16:34:05.056602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 16:34:05.056732 ==
6757 16:34:05.056792
6758 16:34:05.056846
6759 16:34:05.059891 TX Vref Scan disable
6760 16:34:05.059983 == TX Byte 0 ==
6761 16:34:05.063756 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 16:34:05.070207 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 16:34:05.070351 == TX Byte 1 ==
6764 16:34:05.073339 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 16:34:05.079758 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 16:34:05.079845
6767 16:34:05.079906 [DATLAT]
6768 16:34:05.079961 Freq=400, CH1 RK0
6769 16:34:05.080013
6770 16:34:05.083068 DATLAT Default: 0xf
6771 16:34:05.086617 0, 0xFFFF, sum = 0
6772 16:34:05.086695 1, 0xFFFF, sum = 0
6773 16:34:05.089614 2, 0xFFFF, sum = 0
6774 16:34:05.089693 3, 0xFFFF, sum = 0
6775 16:34:05.093247 4, 0xFFFF, sum = 0
6776 16:34:05.093327 5, 0xFFFF, sum = 0
6777 16:34:05.096299 6, 0xFFFF, sum = 0
6778 16:34:05.096404 7, 0xFFFF, sum = 0
6779 16:34:05.099913 8, 0xFFFF, sum = 0
6780 16:34:05.099995 9, 0xFFFF, sum = 0
6781 16:34:05.103318 10, 0xFFFF, sum = 0
6782 16:34:05.103401 11, 0xFFFF, sum = 0
6783 16:34:05.106862 12, 0xFFFF, sum = 0
6784 16:34:05.106944 13, 0x0, sum = 1
6785 16:34:05.110053 14, 0x0, sum = 2
6786 16:34:05.110134 15, 0x0, sum = 3
6787 16:34:05.113312 16, 0x0, sum = 4
6788 16:34:05.113392 best_step = 14
6789 16:34:05.113452
6790 16:34:05.113507 ==
6791 16:34:05.116403 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 16:34:05.119690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 16:34:05.122985 ==
6794 16:34:05.123074 RX Vref Scan: 1
6795 16:34:05.123135
6796 16:34:05.126060 RX Vref 0 -> 0, step: 1
6797 16:34:05.126164
6798 16:34:05.129450 RX Delay -375 -> 252, step: 8
6799 16:34:05.129532
6800 16:34:05.133112 Set Vref, RX VrefLevel [Byte0]: 57
6801 16:34:05.136233 [Byte1]: 48
6802 16:34:05.136315
6803 16:34:05.139473 Final RX Vref Byte 0 = 57 to rank0
6804 16:34:05.143101 Final RX Vref Byte 1 = 48 to rank0
6805 16:34:05.146259 Final RX Vref Byte 0 = 57 to rank1
6806 16:34:05.149177 Final RX Vref Byte 1 = 48 to rank1==
6807 16:34:05.153026 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 16:34:05.156280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 16:34:05.159260 ==
6810 16:34:05.159349 DQS Delay:
6811 16:34:05.159411 DQS0 = 52, DQS1 = 68
6812 16:34:05.162812 DQM Delay:
6813 16:34:05.162891 DQM0 = 9, DQM1 = 14
6814 16:34:05.166071 DQ Delay:
6815 16:34:05.166154 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6816 16:34:05.169374 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6817 16:34:05.172454 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6818 16:34:05.175750 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6819 16:34:05.175834
6820 16:34:05.175913
6821 16:34:05.185613 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6822 16:34:05.188711 CH1 RK0: MR19=C0C, MR18=5D71
6823 16:34:05.195842 CH1_RK0: MR19=0xC0C, MR18=0x5D71, DQSOSC=395, MR23=63, INC=378, DEC=252
6824 16:34:05.195966 ==
6825 16:34:05.198900 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 16:34:05.202418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 16:34:05.202519 ==
6828 16:34:05.205563 [Gating] SW mode calibration
6829 16:34:05.212533 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6830 16:34:05.215650 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6831 16:34:05.222108 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 16:34:05.225314 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 16:34:05.228969 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 16:34:05.235332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 16:34:05.238537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 16:34:05.242274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 16:34:05.248500 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 16:34:05.252096 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 16:34:05.255173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 16:34:05.258966 Total UI for P1: 0, mck2ui 16
6841 16:34:05.261970 best dqsien dly found for B0: ( 0, 14, 24)
6842 16:34:05.265092 Total UI for P1: 0, mck2ui 16
6843 16:34:05.268505 best dqsien dly found for B1: ( 0, 14, 24)
6844 16:34:05.271562 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6845 16:34:05.275306 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6846 16:34:05.278406
6847 16:34:05.281531 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 16:34:05.285379 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 16:34:05.288517 [Gating] SW calibration Done
6850 16:34:05.288601 ==
6851 16:34:05.291772 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 16:34:05.294998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 16:34:05.295085 ==
6854 16:34:05.295164 RX Vref Scan: 0
6855 16:34:05.295222
6856 16:34:05.298695 RX Vref 0 -> 0, step: 1
6857 16:34:05.298813
6858 16:34:05.301828 RX Delay -410 -> 252, step: 16
6859 16:34:05.304854 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6860 16:34:05.311371 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6861 16:34:05.315009 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6862 16:34:05.318045 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6863 16:34:05.321397 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6864 16:34:05.328319 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6865 16:34:05.331325 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6866 16:34:05.335021 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6867 16:34:05.337927 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6868 16:34:05.344826 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6869 16:34:05.347922 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6870 16:34:05.351674 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6871 16:34:05.354845 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6872 16:34:05.361141 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6873 16:34:05.365030 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6874 16:34:05.368148 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6875 16:34:05.368234 ==
6876 16:34:05.371131 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 16:34:05.378127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 16:34:05.378234 ==
6879 16:34:05.378316 DQS Delay:
6880 16:34:05.381299 DQS0 = 59, DQS1 = 59
6881 16:34:05.381381 DQM Delay:
6882 16:34:05.381489 DQM0 = 19, DQM1 = 12
6883 16:34:05.384543 DQ Delay:
6884 16:34:05.387684 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6885 16:34:05.391491 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6886 16:34:05.391579 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6887 16:34:05.394651 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6888 16:34:05.397804
6889 16:34:05.397887
6890 16:34:05.397965 ==
6891 16:34:05.400989 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 16:34:05.404790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 16:34:05.404875 ==
6894 16:34:05.404954
6895 16:34:05.405027
6896 16:34:05.407933 TX Vref Scan disable
6897 16:34:05.408018 == TX Byte 0 ==
6898 16:34:05.411079 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6899 16:34:05.417753 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6900 16:34:05.417851 == TX Byte 1 ==
6901 16:34:05.420865 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6902 16:34:05.427574 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6903 16:34:05.427671 ==
6904 16:34:05.431097 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 16:34:05.434131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 16:34:05.434214 ==
6907 16:34:05.434274
6908 16:34:05.434335
6909 16:34:05.437757 TX Vref Scan disable
6910 16:34:05.437837 == TX Byte 0 ==
6911 16:34:05.440918 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6912 16:34:05.447724 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6913 16:34:05.447829 == TX Byte 1 ==
6914 16:34:05.450819 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6915 16:34:05.457659 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6916 16:34:05.457787
6917 16:34:05.457880 [DATLAT]
6918 16:34:05.457972 Freq=400, CH1 RK1
6919 16:34:05.460855
6920 16:34:05.460940 DATLAT Default: 0xe
6921 16:34:05.464438 0, 0xFFFF, sum = 0
6922 16:34:05.464524 1, 0xFFFF, sum = 0
6923 16:34:05.467614 2, 0xFFFF, sum = 0
6924 16:34:05.467700 3, 0xFFFF, sum = 0
6925 16:34:05.470630 4, 0xFFFF, sum = 0
6926 16:34:05.470714 5, 0xFFFF, sum = 0
6927 16:34:05.473816 6, 0xFFFF, sum = 0
6928 16:34:05.473897 7, 0xFFFF, sum = 0
6929 16:34:05.477530 8, 0xFFFF, sum = 0
6930 16:34:05.477612 9, 0xFFFF, sum = 0
6931 16:34:05.480652 10, 0xFFFF, sum = 0
6932 16:34:05.480750 11, 0xFFFF, sum = 0
6933 16:34:05.483968 12, 0xFFFF, sum = 0
6934 16:34:05.484049 13, 0x0, sum = 1
6935 16:34:05.487155 14, 0x0, sum = 2
6936 16:34:05.487235 15, 0x0, sum = 3
6937 16:34:05.490336 16, 0x0, sum = 4
6938 16:34:05.490416 best_step = 14
6939 16:34:05.490475
6940 16:34:05.490529 ==
6941 16:34:05.494123 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 16:34:05.500443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 16:34:05.500533 ==
6944 16:34:05.500593 RX Vref Scan: 0
6945 16:34:05.500676
6946 16:34:05.503628 RX Vref 0 -> 0, step: 1
6947 16:34:05.503712
6948 16:34:05.506865 RX Delay -359 -> 252, step: 8
6949 16:34:05.513777 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6950 16:34:05.516922 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6951 16:34:05.520217 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6952 16:34:05.523650 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6953 16:34:05.530352 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6954 16:34:05.533496 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6955 16:34:05.537149 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6956 16:34:05.540110 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6957 16:34:05.546888 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6958 16:34:05.550094 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6959 16:34:05.553799 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6960 16:34:05.556742 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6961 16:34:05.563613 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6962 16:34:05.566804 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6963 16:34:05.570251 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6964 16:34:05.576481 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6965 16:34:05.576621 ==
6966 16:34:05.580313 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 16:34:05.583550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 16:34:05.583636 ==
6969 16:34:05.583713 DQS Delay:
6970 16:34:05.586697 DQS0 = 60, DQS1 = 64
6971 16:34:05.586782 DQM Delay:
6972 16:34:05.589967 DQM0 = 13, DQM1 = 10
6973 16:34:05.590049 DQ Delay:
6974 16:34:05.593044 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6975 16:34:05.596540 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6976 16:34:05.599730 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6977 16:34:05.603040 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6978 16:34:05.603127
6979 16:34:05.603204
6980 16:34:05.610009 [DQSOSCAuto] RK1, (LSB)MR18= 0x82b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6981 16:34:05.613247 CH1 RK1: MR19=C0C, MR18=82B2
6982 16:34:05.619463 CH1_RK1: MR19=0xC0C, MR18=0x82B2, DQSOSC=387, MR23=63, INC=394, DEC=262
6983 16:34:05.622661 [RxdqsGatingPostProcess] freq 400
6984 16:34:05.629363 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6985 16:34:05.632966 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 16:34:05.633050 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 16:34:05.636475 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 16:34:05.639545 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 16:34:05.642678 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 16:34:05.645908 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 16:34:05.649873 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 16:34:05.652866 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 16:34:05.655929 Pre-setting of DQS Precalculation
6994 16:34:05.662688 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6995 16:34:05.669332 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6996 16:34:05.676049 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6997 16:34:05.676158
6998 16:34:05.676251
6999 16:34:05.679111 [Calibration Summary] 800 Mbps
7000 16:34:05.679203 CH 0, Rank 0
7001 16:34:05.682468 SW Impedance : PASS
7002 16:34:05.686168 DUTY Scan : NO K
7003 16:34:05.686264 ZQ Calibration : PASS
7004 16:34:05.689413 Jitter Meter : NO K
7005 16:34:05.692395 CBT Training : PASS
7006 16:34:05.692483 Write leveling : PASS
7007 16:34:05.695955 RX DQS gating : PASS
7008 16:34:05.696034 RX DQ/DQS(RDDQC) : PASS
7009 16:34:05.699042 TX DQ/DQS : PASS
7010 16:34:05.702918 RX DATLAT : PASS
7011 16:34:05.702995 RX DQ/DQS(Engine): PASS
7012 16:34:05.706115 TX OE : NO K
7013 16:34:05.706198 All Pass.
7014 16:34:05.706291
7015 16:34:05.709236 CH 0, Rank 1
7016 16:34:05.709304 SW Impedance : PASS
7017 16:34:05.712322 DUTY Scan : NO K
7018 16:34:05.715597 ZQ Calibration : PASS
7019 16:34:05.715668 Jitter Meter : NO K
7020 16:34:05.719408 CBT Training : PASS
7021 16:34:05.722612 Write leveling : NO K
7022 16:34:05.722684 RX DQS gating : PASS
7023 16:34:05.725720 RX DQ/DQS(RDDQC) : PASS
7024 16:34:05.728805 TX DQ/DQS : PASS
7025 16:34:05.728883 RX DATLAT : PASS
7026 16:34:05.732077 RX DQ/DQS(Engine): PASS
7027 16:34:05.736013 TX OE : NO K
7028 16:34:05.736083 All Pass.
7029 16:34:05.736137
7030 16:34:05.736194 CH 1, Rank 0
7031 16:34:05.739034 SW Impedance : PASS
7032 16:34:05.741961 DUTY Scan : NO K
7033 16:34:05.742026 ZQ Calibration : PASS
7034 16:34:05.745556 Jitter Meter : NO K
7035 16:34:05.748978 CBT Training : PASS
7036 16:34:05.749053 Write leveling : PASS
7037 16:34:05.752158 RX DQS gating : PASS
7038 16:34:05.755386 RX DQ/DQS(RDDQC) : PASS
7039 16:34:05.755464 TX DQ/DQS : PASS
7040 16:34:05.758449 RX DATLAT : PASS
7041 16:34:05.758526 RX DQ/DQS(Engine): PASS
7042 16:34:05.762026 TX OE : NO K
7043 16:34:05.762112 All Pass.
7044 16:34:05.762172
7045 16:34:05.765072 CH 1, Rank 1
7046 16:34:05.765151 SW Impedance : PASS
7047 16:34:05.768818 DUTY Scan : NO K
7048 16:34:05.771744 ZQ Calibration : PASS
7049 16:34:05.771824 Jitter Meter : NO K
7050 16:34:05.775116 CBT Training : PASS
7051 16:34:05.778824 Write leveling : NO K
7052 16:34:05.778916 RX DQS gating : PASS
7053 16:34:05.781869 RX DQ/DQS(RDDQC) : PASS
7054 16:34:05.784928 TX DQ/DQS : PASS
7055 16:34:05.785096 RX DATLAT : PASS
7056 16:34:05.788844 RX DQ/DQS(Engine): PASS
7057 16:34:05.791947 TX OE : NO K
7058 16:34:05.792037 All Pass.
7059 16:34:05.792096
7060 16:34:05.795278 DramC Write-DBI off
7061 16:34:05.795347 PER_BANK_REFRESH: Hybrid Mode
7062 16:34:05.798494 TX_TRACKING: ON
7063 16:34:05.805053 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7064 16:34:05.811927 [FAST_K] Save calibration result to emmc
7065 16:34:05.815054 dramc_set_vcore_voltage set vcore to 725000
7066 16:34:05.815140 Read voltage for 1600, 0
7067 16:34:05.818320 Vio18 = 0
7068 16:34:05.818401 Vcore = 725000
7069 16:34:05.818462 Vdram = 0
7070 16:34:05.821502 Vddq = 0
7071 16:34:05.821631 Vmddr = 0
7072 16:34:05.824889 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7073 16:34:05.831818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7074 16:34:05.835153 MEM_TYPE=3, freq_sel=13
7075 16:34:05.838450 sv_algorithm_assistance_LP4_3733
7076 16:34:05.841507 ============ PULL DRAM RESETB DOWN ============
7077 16:34:05.845100 ========== PULL DRAM RESETB DOWN end =========
7078 16:34:05.851731 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7079 16:34:05.854682 ===================================
7080 16:34:05.854765 LPDDR4 DRAM CONFIGURATION
7081 16:34:05.858252 ===================================
7082 16:34:05.861422 EX_ROW_EN[0] = 0x0
7083 16:34:05.861511 EX_ROW_EN[1] = 0x0
7084 16:34:05.864488 LP4Y_EN = 0x0
7085 16:34:05.864591 WORK_FSP = 0x1
7086 16:34:05.868064 WL = 0x5
7087 16:34:05.870938 RL = 0x5
7088 16:34:05.871025 BL = 0x2
7089 16:34:05.874559 RPST = 0x0
7090 16:34:05.874639 RD_PRE = 0x0
7091 16:34:05.877725 WR_PRE = 0x1
7092 16:34:05.877805 WR_PST = 0x1
7093 16:34:05.881390 DBI_WR = 0x0
7094 16:34:05.881469 DBI_RD = 0x0
7095 16:34:05.884747 OTF = 0x1
7096 16:34:05.888577 ===================================
7097 16:34:05.891094 ===================================
7098 16:34:05.891175 ANA top config
7099 16:34:05.894466 ===================================
7100 16:34:05.897861 DLL_ASYNC_EN = 0
7101 16:34:05.901028 ALL_SLAVE_EN = 0
7102 16:34:05.901110 NEW_RANK_MODE = 1
7103 16:34:05.904282 DLL_IDLE_MODE = 1
7104 16:34:05.908134 LP45_APHY_COMB_EN = 1
7105 16:34:05.911049 TX_ODT_DIS = 0
7106 16:34:05.914208 NEW_8X_MODE = 1
7107 16:34:05.917629 ===================================
7108 16:34:05.920633 ===================================
7109 16:34:05.920752 data_rate = 3200
7110 16:34:05.924476 CKR = 1
7111 16:34:05.927656 DQ_P2S_RATIO = 8
7112 16:34:05.930769 ===================================
7113 16:34:05.933921 CA_P2S_RATIO = 8
7114 16:34:05.937767 DQ_CA_OPEN = 0
7115 16:34:05.940910 DQ_SEMI_OPEN = 0
7116 16:34:05.940990 CA_SEMI_OPEN = 0
7117 16:34:05.944034 CA_FULL_RATE = 0
7118 16:34:05.947210 DQ_CKDIV4_EN = 0
7119 16:34:05.950326 CA_CKDIV4_EN = 0
7120 16:34:05.954085 CA_PREDIV_EN = 0
7121 16:34:05.957120 PH8_DLY = 12
7122 16:34:05.960555 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7123 16:34:05.960641 DQ_AAMCK_DIV = 4
7124 16:34:05.963481 CA_AAMCK_DIV = 4
7125 16:34:05.967081 CA_ADMCK_DIV = 4
7126 16:34:05.970245 DQ_TRACK_CA_EN = 0
7127 16:34:05.973512 CA_PICK = 1600
7128 16:34:05.977187 CA_MCKIO = 1600
7129 16:34:05.980033 MCKIO_SEMI = 0
7130 16:34:05.980119 PLL_FREQ = 3068
7131 16:34:05.983297 DQ_UI_PI_RATIO = 32
7132 16:34:05.986967 CA_UI_PI_RATIO = 0
7133 16:34:05.990005 ===================================
7134 16:34:05.993757 ===================================
7135 16:34:05.996929 memory_type:LPDDR4
7136 16:34:05.997011 GP_NUM : 10
7137 16:34:06.000009 SRAM_EN : 1
7138 16:34:06.003742 MD32_EN : 0
7139 16:34:06.006859 ===================================
7140 16:34:06.006940 [ANA_INIT] >>>>>>>>>>>>>>
7141 16:34:06.010046 <<<<<< [CONFIGURE PHASE]: ANA_TX
7142 16:34:06.013192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7143 16:34:06.016420 ===================================
7144 16:34:06.020070 data_rate = 3200,PCW = 0X7600
7145 16:34:06.023091 ===================================
7146 16:34:06.026777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7147 16:34:06.033353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 16:34:06.036332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 16:34:06.042852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7150 16:34:06.045987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7151 16:34:06.049241 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7152 16:34:06.052974 [ANA_INIT] flow start
7153 16:34:06.053057 [ANA_INIT] PLL >>>>>>>>
7154 16:34:06.056172 [ANA_INIT] PLL <<<<<<<<
7155 16:34:06.059407 [ANA_INIT] MIDPI >>>>>>>>
7156 16:34:06.059554 [ANA_INIT] MIDPI <<<<<<<<
7157 16:34:06.063015 [ANA_INIT] DLL >>>>>>>>
7158 16:34:06.066153 [ANA_INIT] DLL <<<<<<<<
7159 16:34:06.066239 [ANA_INIT] flow end
7160 16:34:06.072586 ============ LP4 DIFF to SE enter ============
7161 16:34:06.076347 ============ LP4 DIFF to SE exit ============
7162 16:34:06.079484 [ANA_INIT] <<<<<<<<<<<<<
7163 16:34:06.082616 [Flow] Enable top DCM control >>>>>
7164 16:34:06.085797 [Flow] Enable top DCM control <<<<<
7165 16:34:06.085880 Enable DLL master slave shuffle
7166 16:34:06.092338 ==============================================================
7167 16:34:06.095861 Gating Mode config
7168 16:34:06.098924 ==============================================================
7169 16:34:06.102816 Config description:
7170 16:34:06.112452 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7171 16:34:06.118939 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7172 16:34:06.122218 SELPH_MODE 0: By rank 1: By Phase
7173 16:34:06.128920 ==============================================================
7174 16:34:06.132011 GAT_TRACK_EN = 1
7175 16:34:06.135670 RX_GATING_MODE = 2
7176 16:34:06.138588 RX_GATING_TRACK_MODE = 2
7177 16:34:06.142225 SELPH_MODE = 1
7178 16:34:06.145361 PICG_EARLY_EN = 1
7179 16:34:06.145444 VALID_LAT_VALUE = 1
7180 16:34:06.151820 ==============================================================
7181 16:34:06.155603 Enter into Gating configuration >>>>
7182 16:34:06.158737 Exit from Gating configuration <<<<
7183 16:34:06.161953 Enter into DVFS_PRE_config >>>>>
7184 16:34:06.171895 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7185 16:34:06.175006 Exit from DVFS_PRE_config <<<<<
7186 16:34:06.178560 Enter into PICG configuration >>>>
7187 16:34:06.181476 Exit from PICG configuration <<<<
7188 16:34:06.185055 [RX_INPUT] configuration >>>>>
7189 16:34:06.188358 [RX_INPUT] configuration <<<<<
7190 16:34:06.195143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7191 16:34:06.198208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7192 16:34:06.204635 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 16:34:06.210987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 16:34:06.217702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 16:34:06.224412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 16:34:06.228223 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7197 16:34:06.231329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7198 16:34:06.234502 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7199 16:34:06.241326 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7200 16:34:06.244336 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7201 16:34:06.247959 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 16:34:06.251030 ===================================
7203 16:34:06.254203 LPDDR4 DRAM CONFIGURATION
7204 16:34:06.258039 ===================================
7205 16:34:06.258124 EX_ROW_EN[0] = 0x0
7206 16:34:06.260694 EX_ROW_EN[1] = 0x0
7207 16:34:06.264442 LP4Y_EN = 0x0
7208 16:34:06.264523 WORK_FSP = 0x1
7209 16:34:06.267575 WL = 0x5
7210 16:34:06.267653 RL = 0x5
7211 16:34:06.270719 BL = 0x2
7212 16:34:06.270798 RPST = 0x0
7213 16:34:06.274476 RD_PRE = 0x0
7214 16:34:06.274556 WR_PRE = 0x1
7215 16:34:06.277655 WR_PST = 0x1
7216 16:34:06.277732 DBI_WR = 0x0
7217 16:34:06.280857 DBI_RD = 0x0
7218 16:34:06.280934 OTF = 0x1
7219 16:34:06.284571 ===================================
7220 16:34:06.287496 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7221 16:34:06.294123 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7222 16:34:06.297382 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 16:34:06.300964 ===================================
7224 16:34:06.303899 LPDDR4 DRAM CONFIGURATION
7225 16:34:06.307614 ===================================
7226 16:34:06.307697 EX_ROW_EN[0] = 0x10
7227 16:34:06.311162 EX_ROW_EN[1] = 0x0
7228 16:34:06.314079 LP4Y_EN = 0x0
7229 16:34:06.314164 WORK_FSP = 0x1
7230 16:34:06.317157 WL = 0x5
7231 16:34:06.317225 RL = 0x5
7232 16:34:06.320345 BL = 0x2
7233 16:34:06.320411 RPST = 0x0
7234 16:34:06.324038 RD_PRE = 0x0
7235 16:34:06.324106 WR_PRE = 0x1
7236 16:34:06.327094 WR_PST = 0x1
7237 16:34:06.327159 DBI_WR = 0x0
7238 16:34:06.330802 DBI_RD = 0x0
7239 16:34:06.330884 OTF = 0x1
7240 16:34:06.333916 ===================================
7241 16:34:06.340152 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7242 16:34:06.340246 ==
7243 16:34:06.343841 Dram Type= 6, Freq= 0, CH_0, rank 0
7244 16:34:06.350027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7245 16:34:06.350120 ==
7246 16:34:06.350181 [Duty_Offset_Calibration]
7247 16:34:06.353627 B0:2 B1:0 CA:3
7248 16:34:06.353708
7249 16:34:06.356491 [DutyScan_Calibration_Flow] k_type=0
7250 16:34:06.365980
7251 16:34:06.366105 ==CLK 0==
7252 16:34:06.369065 Final CLK duty delay cell = 0
7253 16:34:06.372790 [0] MAX Duty = 5031%(X100), DQS PI = 12
7254 16:34:06.375958 [0] MIN Duty = 4907%(X100), DQS PI = 6
7255 16:34:06.376040 [0] AVG Duty = 4969%(X100)
7256 16:34:06.379232
7257 16:34:06.379311 CH0 CLK Duty spec in!! Max-Min= 124%
7258 16:34:06.385635 [DutyScan_Calibration_Flow] ====Done====
7259 16:34:06.385732
7260 16:34:06.388945 [DutyScan_Calibration_Flow] k_type=1
7261 16:34:06.405716
7262 16:34:06.405859 ==DQS 0 ==
7263 16:34:06.409303 Final DQS duty delay cell = 0
7264 16:34:06.412414 [0] MAX Duty = 5125%(X100), DQS PI = 30
7265 16:34:06.415540 [0] MIN Duty = 4875%(X100), DQS PI = 48
7266 16:34:06.415619 [0] AVG Duty = 5000%(X100)
7267 16:34:06.419214
7268 16:34:06.419300 ==DQS 1 ==
7269 16:34:06.422207 Final DQS duty delay cell = 0
7270 16:34:06.426014 [0] MAX Duty = 5156%(X100), DQS PI = 32
7271 16:34:06.429125 [0] MIN Duty = 5031%(X100), DQS PI = 12
7272 16:34:06.432259 [0] AVG Duty = 5093%(X100)
7273 16:34:06.432339
7274 16:34:06.435945 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7275 16:34:06.436026
7276 16:34:06.439050 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7277 16:34:06.442204 [DutyScan_Calibration_Flow] ====Done====
7278 16:34:06.442285
7279 16:34:06.445435 [DutyScan_Calibration_Flow] k_type=3
7280 16:34:06.464145
7281 16:34:06.464278 ==DQM 0 ==
7282 16:34:06.467046 Final DQM duty delay cell = 0
7283 16:34:06.470268 [0] MAX Duty = 5156%(X100), DQS PI = 30
7284 16:34:06.473449 [0] MIN Duty = 4875%(X100), DQS PI = 0
7285 16:34:06.476982 [0] AVG Duty = 5015%(X100)
7286 16:34:06.477066
7287 16:34:06.477125 ==DQM 1 ==
7288 16:34:06.480070 Final DQM duty delay cell = 4
7289 16:34:06.483292 [4] MAX Duty = 5156%(X100), DQS PI = 52
7290 16:34:06.487122 [4] MIN Duty = 5000%(X100), DQS PI = 38
7291 16:34:06.490371 [4] AVG Duty = 5078%(X100)
7292 16:34:06.490472
7293 16:34:06.493553 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7294 16:34:06.493633
7295 16:34:06.496764 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7296 16:34:06.499960 [DutyScan_Calibration_Flow] ====Done====
7297 16:34:06.500045
7298 16:34:06.503685 [DutyScan_Calibration_Flow] k_type=2
7299 16:34:06.519965
7300 16:34:06.520098 ==DQ 0 ==
7301 16:34:06.523665 Final DQ duty delay cell = -4
7302 16:34:06.526760 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7303 16:34:06.530369 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7304 16:34:06.533588 [-4] AVG Duty = 4938%(X100)
7305 16:34:06.533670
7306 16:34:06.533728 ==DQ 1 ==
7307 16:34:06.536821 Final DQ duty delay cell = 0
7308 16:34:06.539803 [0] MAX Duty = 5156%(X100), DQS PI = 60
7309 16:34:06.543463 [0] MIN Duty = 5000%(X100), DQS PI = 16
7310 16:34:06.546388 [0] AVG Duty = 5078%(X100)
7311 16:34:06.546468
7312 16:34:06.549942 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7313 16:34:06.550108
7314 16:34:06.553182 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7315 16:34:06.556871 [DutyScan_Calibration_Flow] ====Done====
7316 16:34:06.556967 ==
7317 16:34:06.559940 Dram Type= 6, Freq= 0, CH_1, rank 0
7318 16:34:06.563132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 16:34:06.563227 ==
7320 16:34:06.566689 [Duty_Offset_Calibration]
7321 16:34:06.566771 B0:1 B1:-2 CA:0
7322 16:34:06.566830
7323 16:34:06.569936 [DutyScan_Calibration_Flow] k_type=0
7324 16:34:06.580977
7325 16:34:06.581153 ==CLK 0==
7326 16:34:06.584120 Final CLK duty delay cell = 0
7327 16:34:06.587441 [0] MAX Duty = 5093%(X100), DQS PI = 22
7328 16:34:06.590694 [0] MIN Duty = 4844%(X100), DQS PI = 58
7329 16:34:06.593884 [0] AVG Duty = 4968%(X100)
7330 16:34:06.593965
7331 16:34:06.597096 CH1 CLK Duty spec in!! Max-Min= 249%
7332 16:34:06.600368 [DutyScan_Calibration_Flow] ====Done====
7333 16:34:06.600465
7334 16:34:06.603555 [DutyScan_Calibration_Flow] k_type=1
7335 16:34:06.619945
7336 16:34:06.620155 ==DQS 0 ==
7337 16:34:06.622946 Final DQS duty delay cell = -4
7338 16:34:06.626184 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7339 16:34:06.629223 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7340 16:34:06.633270 [-4] AVG Duty = 4906%(X100)
7341 16:34:06.633403
7342 16:34:06.633483 ==DQS 1 ==
7343 16:34:06.636270 Final DQS duty delay cell = 0
7344 16:34:06.639813 [0] MAX Duty = 5093%(X100), DQS PI = 62
7345 16:34:06.643202 [0] MIN Duty = 4844%(X100), DQS PI = 24
7346 16:34:06.646441 [0] AVG Duty = 4968%(X100)
7347 16:34:06.646574
7348 16:34:06.649942 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7349 16:34:06.650064
7350 16:34:06.653053 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7351 16:34:06.656015 [DutyScan_Calibration_Flow] ====Done====
7352 16:34:06.656101
7353 16:34:06.659692 [DutyScan_Calibration_Flow] k_type=3
7354 16:34:06.676624
7355 16:34:06.676782 ==DQM 0 ==
7356 16:34:06.680050 Final DQM duty delay cell = 0
7357 16:34:06.683568 [0] MAX Duty = 5031%(X100), DQS PI = 26
7358 16:34:06.687007 [0] MIN Duty = 4813%(X100), DQS PI = 54
7359 16:34:06.690215 [0] AVG Duty = 4922%(X100)
7360 16:34:06.690315
7361 16:34:06.690380 ==DQM 1 ==
7362 16:34:06.693451 Final DQM duty delay cell = 0
7363 16:34:06.696605 [0] MAX Duty = 5062%(X100), DQS PI = 34
7364 16:34:06.699827 [0] MIN Duty = 4875%(X100), DQS PI = 24
7365 16:34:06.703652 [0] AVG Duty = 4968%(X100)
7366 16:34:06.703742
7367 16:34:06.706927 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7368 16:34:06.707008
7369 16:34:06.710098 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7370 16:34:06.713423 [DutyScan_Calibration_Flow] ====Done====
7371 16:34:06.713507
7372 16:34:06.716587 [DutyScan_Calibration_Flow] k_type=2
7373 16:34:06.733821
7374 16:34:06.733958 ==DQ 0 ==
7375 16:34:06.737366 Final DQ duty delay cell = 0
7376 16:34:06.740362 [0] MAX Duty = 5093%(X100), DQS PI = 20
7377 16:34:06.743865 [0] MIN Duty = 4907%(X100), DQS PI = 46
7378 16:34:06.743959 [0] AVG Duty = 5000%(X100)
7379 16:34:06.746846
7380 16:34:06.746926 ==DQ 1 ==
7381 16:34:06.750440 Final DQ duty delay cell = 0
7382 16:34:06.753921 [0] MAX Duty = 5125%(X100), DQS PI = 34
7383 16:34:06.757171 [0] MIN Duty = 4969%(X100), DQS PI = 24
7384 16:34:06.757293 [0] AVG Duty = 5047%(X100)
7385 16:34:06.757384
7386 16:34:06.760603 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7387 16:34:06.763889
7388 16:34:06.766935 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7389 16:34:06.770626 [DutyScan_Calibration_Flow] ====Done====
7390 16:34:06.773721 nWR fixed to 30
7391 16:34:06.773827 [ModeRegInit_LP4] CH0 RK0
7392 16:34:06.776846 [ModeRegInit_LP4] CH0 RK1
7393 16:34:06.780482 [ModeRegInit_LP4] CH1 RK0
7394 16:34:06.783732 [ModeRegInit_LP4] CH1 RK1
7395 16:34:06.783827 match AC timing 5
7396 16:34:06.786855 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7397 16:34:06.793673 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7398 16:34:06.796861 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7399 16:34:06.803609 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7400 16:34:06.806770 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7401 16:34:06.806860 [MiockJmeterHQA]
7402 16:34:06.806921
7403 16:34:06.809896 [DramcMiockJmeter] u1RxGatingPI = 0
7404 16:34:06.813691 0 : 4252, 4027
7405 16:34:06.813803 4 : 4257, 4027
7406 16:34:06.816456 8 : 4363, 4138
7407 16:34:06.816569 12 : 4255, 4029
7408 16:34:06.816683 16 : 4253, 4027
7409 16:34:06.819947 20 : 4363, 4137
7410 16:34:06.820078 24 : 4253, 4027
7411 16:34:06.823323 28 : 4253, 4026
7412 16:34:06.823441 32 : 4252, 4027
7413 16:34:06.826434 36 : 4254, 4029
7414 16:34:06.826542 40 : 4363, 4137
7415 16:34:06.826639 44 : 4252, 4027
7416 16:34:06.830171 48 : 4363, 4138
7417 16:34:06.830275 52 : 4253, 4026
7418 16:34:06.833246 56 : 4253, 4026
7419 16:34:06.833351 60 : 4250, 4027
7420 16:34:06.836438 64 : 4365, 4140
7421 16:34:06.836544 68 : 4250, 4027
7422 16:34:06.840039 72 : 4360, 4138
7423 16:34:06.840145 76 : 4250, 4027
7424 16:34:06.840247 80 : 4250, 4027
7425 16:34:06.843344 84 : 4250, 4027
7426 16:34:06.843449 88 : 4252, 4029
7427 16:34:06.846549 92 : 4250, 4026
7428 16:34:06.846669 96 : 4250, 4027
7429 16:34:06.849893 100 : 4363, 4140
7430 16:34:06.850003 104 : 4360, 3744
7431 16:34:06.852988 108 : 4250, 0
7432 16:34:06.853109 112 : 4250, 0
7433 16:34:06.853209 116 : 4250, 0
7434 16:34:06.856654 120 : 4360, 0
7435 16:34:06.856776 124 : 4250, 0
7436 16:34:06.859618 128 : 4252, 0
7437 16:34:06.859735 132 : 4250, 0
7438 16:34:06.859836 136 : 4252, 0
7439 16:34:06.863085 140 : 4250, 0
7440 16:34:06.863203 144 : 4253, 0
7441 16:34:06.863303 148 : 4363, 0
7442 16:34:06.866478 152 : 4250, 0
7443 16:34:06.866588 156 : 4250, 0
7444 16:34:06.869869 160 : 4252, 0
7445 16:34:06.869979 164 : 4250, 0
7446 16:34:06.870080 168 : 4250, 0
7447 16:34:06.873012 172 : 4360, 0
7448 16:34:06.873095 176 : 4250, 0
7449 16:34:06.876197 180 : 4250, 0
7450 16:34:06.876299 184 : 4250, 0
7451 16:34:06.876396 188 : 4361, 0
7452 16:34:06.879544 192 : 4250, 0
7453 16:34:06.879654 196 : 4250, 0
7454 16:34:06.882701 200 : 4361, 0
7455 16:34:06.882803 204 : 4361, 0
7456 16:34:06.882904 208 : 4250, 0
7457 16:34:06.886304 212 : 4250, 0
7458 16:34:06.886404 216 : 4252, 0
7459 16:34:06.889399 220 : 4250, 0
7460 16:34:06.889505 224 : 4363, 0
7461 16:34:06.889601 228 : 4250, 0
7462 16:34:06.892482 232 : 4250, 0
7463 16:34:06.892584 236 : 4250, 1088
7464 16:34:06.896325 240 : 4250, 4027
7465 16:34:06.896425 244 : 4250, 4026
7466 16:34:06.899323 248 : 4363, 4140
7467 16:34:06.899429 252 : 4360, 4137
7468 16:34:06.899525 256 : 4249, 4027
7469 16:34:06.902972 260 : 4361, 4137
7470 16:34:06.903080 264 : 4360, 4138
7471 16:34:06.905754 268 : 4250, 4027
7472 16:34:06.905859 272 : 4250, 4027
7473 16:34:06.909082 276 : 4249, 4027
7474 16:34:06.909183 280 : 4250, 4027
7475 16:34:06.912725 284 : 4250, 4027
7476 16:34:06.912808 288 : 4250, 4026
7477 16:34:06.915913 292 : 4249, 4027
7478 16:34:06.916021 296 : 4250, 4026
7479 16:34:06.919004 300 : 4361, 4138
7480 16:34:06.919110 304 : 4363, 4138
7481 16:34:06.922843 308 : 4250, 4027
7482 16:34:06.922946 312 : 4360, 4137
7483 16:34:06.925954 316 : 4250, 4026
7484 16:34:06.926061 320 : 4250, 4027
7485 16:34:06.926158 324 : 4250, 4027
7486 16:34:06.929021 328 : 4249, 4027
7487 16:34:06.929105 332 : 4250, 4026
7488 16:34:06.932245 336 : 4250, 4027
7489 16:34:06.932350 340 : 4250, 4027
7490 16:34:06.936137 344 : 4250, 4027
7491 16:34:06.936253 348 : 4250, 4026
7492 16:34:06.939303 352 : 4361, 4118
7493 16:34:06.939414 356 : 4363, 2948
7494 16:34:06.942488 360 : 4251, 0
7495 16:34:06.942599
7496 16:34:06.942697 MIOCK jitter meter ch=0
7497 16:34:06.942796
7498 16:34:06.945640 1T = (360-108) = 252 dly cells
7499 16:34:06.952123 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7500 16:34:06.952254 ==
7501 16:34:06.955964 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 16:34:06.959253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 16:34:06.959359 ==
7504 16:34:06.965350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 16:34:06.968808 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 16:34:06.972293 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 16:34:06.978846 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 16:34:06.988493 [CA 0] Center 43 (13~74) winsize 62
7509 16:34:06.991779 [CA 1] Center 43 (13~74) winsize 62
7510 16:34:06.995634 [CA 2] Center 39 (10~68) winsize 59
7511 16:34:06.998826 [CA 3] Center 39 (10~68) winsize 59
7512 16:34:07.002047 [CA 4] Center 36 (7~66) winsize 60
7513 16:34:07.005137 [CA 5] Center 36 (7~66) winsize 60
7514 16:34:07.005253
7515 16:34:07.008390 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 16:34:07.008497
7517 16:34:07.015426 [CATrainingPosCal] consider 1 rank data
7518 16:34:07.015546 u2DelayCellTimex100 = 258/100 ps
7519 16:34:07.021728 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7520 16:34:07.024977 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7521 16:34:07.028289 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7522 16:34:07.032136 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7523 16:34:07.035413 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7524 16:34:07.038637 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7525 16:34:07.038735
7526 16:34:07.041816 CA PerBit enable=1, Macro0, CA PI delay=36
7527 16:34:07.041923
7528 16:34:07.044948 [CBTSetCACLKResult] CA Dly = 36
7529 16:34:07.048603 CS Dly: 11 (0~42)
7530 16:34:07.051812 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 16:34:07.054864 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 16:34:07.054946 ==
7533 16:34:07.058261 Dram Type= 6, Freq= 0, CH_0, rank 1
7534 16:34:07.064658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 16:34:07.064783 ==
7536 16:34:07.068005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 16:34:07.074909 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 16:34:07.078584 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 16:34:07.085097 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 16:34:07.092936 [CA 0] Center 44 (14~75) winsize 62
7541 16:34:07.096097 [CA 1] Center 43 (13~74) winsize 62
7542 16:34:07.099327 [CA 2] Center 39 (10~69) winsize 60
7543 16:34:07.102987 [CA 3] Center 39 (10~69) winsize 60
7544 16:34:07.106263 [CA 4] Center 37 (8~67) winsize 60
7545 16:34:07.109700 [CA 5] Center 36 (7~66) winsize 60
7546 16:34:07.109829
7547 16:34:07.112828 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 16:34:07.112915
7549 16:34:07.115883 [CATrainingPosCal] consider 2 rank data
7550 16:34:07.119176 u2DelayCellTimex100 = 258/100 ps
7551 16:34:07.126083 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7552 16:34:07.129251 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7553 16:34:07.132651 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7554 16:34:07.135617 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7555 16:34:07.139300 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7556 16:34:07.142492 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7557 16:34:07.142658
7558 16:34:07.145602 CA PerBit enable=1, Macro0, CA PI delay=36
7559 16:34:07.145742
7560 16:34:07.148770 [CBTSetCACLKResult] CA Dly = 36
7561 16:34:07.152475 CS Dly: 11 (0~43)
7562 16:34:07.155623 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 16:34:07.158750 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 16:34:07.158877
7565 16:34:07.162000 ----->DramcWriteLeveling(PI) begin...
7566 16:34:07.162127 ==
7567 16:34:07.165250 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 16:34:07.172031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 16:34:07.172196 ==
7570 16:34:07.175843 Write leveling (Byte 0): 36 => 36
7571 16:34:07.178968 Write leveling (Byte 1): 28 => 28
7572 16:34:07.179094 DramcWriteLeveling(PI) end<-----
7573 16:34:07.182106
7574 16:34:07.182213 ==
7575 16:34:07.185815 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 16:34:07.188894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 16:34:07.189042 ==
7578 16:34:07.192030 [Gating] SW mode calibration
7579 16:34:07.198719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7580 16:34:07.202233 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7581 16:34:07.209219 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 16:34:07.212376 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 16:34:07.215537 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 16:34:07.221955 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 16:34:07.225873 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7586 16:34:07.229037 1 4 20 | B1->B0 | 2827 3434 | 1 1 | (1 1) (1 1)
7587 16:34:07.235325 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7588 16:34:07.238910 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 16:34:07.242347 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 16:34:07.248844 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 16:34:07.252128 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 16:34:07.255744 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7593 16:34:07.262280 1 5 16 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
7594 16:34:07.265385 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7595 16:34:07.268766 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7596 16:34:07.275427 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 16:34:07.278666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 16:34:07.281806 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 16:34:07.288619 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 16:34:07.291566 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 16:34:07.295483 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7602 16:34:07.301987 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7603 16:34:07.305094 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7604 16:34:07.308586 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 16:34:07.311662 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 16:34:07.318422 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 16:34:07.321738 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 16:34:07.325114 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 16:34:07.331617 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 16:34:07.335062 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7611 16:34:07.338314 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 16:34:07.344853 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 16:34:07.348238 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 16:34:07.351510 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 16:34:07.358059 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 16:34:07.361662 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 16:34:07.365204 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 16:34:07.371608 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 16:34:07.374998 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 16:34:07.378234 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 16:34:07.384854 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 16:34:07.388123 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 16:34:07.391365 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 16:34:07.398311 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 16:34:07.402072 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 16:34:07.405084 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 16:34:07.408482 Total UI for P1: 0, mck2ui 16
7628 16:34:07.411705 best dqsien dly found for B0: ( 1, 9, 16)
7629 16:34:07.414756 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 16:34:07.421745 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 16:34:07.424855 Total UI for P1: 0, mck2ui 16
7632 16:34:07.428215 best dqsien dly found for B1: ( 1, 9, 22)
7633 16:34:07.431766 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7634 16:34:07.434878 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7635 16:34:07.434976
7636 16:34:07.438219 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7637 16:34:07.441540 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7638 16:34:07.444769 [Gating] SW calibration Done
7639 16:34:07.444841 ==
7640 16:34:07.447981 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 16:34:07.451137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 16:34:07.451223 ==
7643 16:34:07.454998 RX Vref Scan: 0
7644 16:34:07.455081
7645 16:34:07.458243 RX Vref 0 -> 0, step: 1
7646 16:34:07.458322
7647 16:34:07.458381 RX Delay 0 -> 252, step: 8
7648 16:34:07.464703 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7649 16:34:07.467904 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7650 16:34:07.471101 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7651 16:34:07.474265 iDelay=192, Bit 3, Center 123 (64 ~ 183) 120
7652 16:34:07.477576 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7653 16:34:07.484032 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7654 16:34:07.487929 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7655 16:34:07.490798 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7656 16:34:07.494150 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7657 16:34:07.497598 iDelay=192, Bit 9, Center 107 (48 ~ 167) 120
7658 16:34:07.504452 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7659 16:34:07.507469 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7660 16:34:07.510582 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7661 16:34:07.514079 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7662 16:34:07.520498 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7663 16:34:07.524038 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7664 16:34:07.524123 ==
7665 16:34:07.527120 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 16:34:07.530379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 16:34:07.530453 ==
7668 16:34:07.533486 DQS Delay:
7669 16:34:07.533555 DQS0 = 0, DQS1 = 0
7670 16:34:07.533612 DQM Delay:
7671 16:34:07.537226 DQM0 = 127, DQM1 = 122
7672 16:34:07.537363 DQ Delay:
7673 16:34:07.540608 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7674 16:34:07.543987 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7675 16:34:07.547392 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7676 16:34:07.553856 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7677 16:34:07.553952
7678 16:34:07.554011
7679 16:34:07.554065 ==
7680 16:34:07.557026 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 16:34:07.560559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 16:34:07.560692 ==
7683 16:34:07.560754
7684 16:34:07.560807
7685 16:34:07.563651 TX Vref Scan disable
7686 16:34:07.563759 == TX Byte 0 ==
7687 16:34:07.570087 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7688 16:34:07.573801 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7689 16:34:07.573903 == TX Byte 1 ==
7690 16:34:07.580610 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7691 16:34:07.583834 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7692 16:34:07.583937 ==
7693 16:34:07.586615 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 16:34:07.589967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 16:34:07.590062 ==
7696 16:34:07.605220
7697 16:34:07.608740 TX Vref early break, caculate TX vref
7698 16:34:07.611537 TX Vref=16, minBit 8, minWin=21, winSum=363
7699 16:34:07.615078 TX Vref=18, minBit 8, minWin=21, winSum=370
7700 16:34:07.618290 TX Vref=20, minBit 8, minWin=22, winSum=383
7701 16:34:07.621661 TX Vref=22, minBit 8, minWin=23, winSum=392
7702 16:34:07.624923 TX Vref=24, minBit 4, minWin=24, winSum=403
7703 16:34:07.631514 TX Vref=26, minBit 9, minWin=24, winSum=406
7704 16:34:07.635270 TX Vref=28, minBit 8, minWin=24, winSum=409
7705 16:34:07.638094 TX Vref=30, minBit 8, minWin=23, winSum=404
7706 16:34:07.641425 TX Vref=32, minBit 8, minWin=23, winSum=395
7707 16:34:07.645180 TX Vref=34, minBit 8, minWin=22, winSum=386
7708 16:34:07.651394 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
7709 16:34:07.651511
7710 16:34:07.654702 Final TX Range 0 Vref 28
7711 16:34:07.654823
7712 16:34:07.654926 ==
7713 16:34:07.657903 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 16:34:07.661728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 16:34:07.661868 ==
7716 16:34:07.661957
7717 16:34:07.662039
7718 16:34:07.664947 TX Vref Scan disable
7719 16:34:07.671560 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7720 16:34:07.671663 == TX Byte 0 ==
7721 16:34:07.674804 u2DelayCellOfst[0]=15 cells (4 PI)
7722 16:34:07.677927 u2DelayCellOfst[1]=22 cells (6 PI)
7723 16:34:07.681667 u2DelayCellOfst[2]=15 cells (4 PI)
7724 16:34:07.684975 u2DelayCellOfst[3]=15 cells (4 PI)
7725 16:34:07.688297 u2DelayCellOfst[4]=11 cells (3 PI)
7726 16:34:07.691636 u2DelayCellOfst[5]=0 cells (0 PI)
7727 16:34:07.694609 u2DelayCellOfst[6]=22 cells (6 PI)
7728 16:34:07.697749 u2DelayCellOfst[7]=18 cells (5 PI)
7729 16:34:07.700952 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7730 16:34:07.704825 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7731 16:34:07.708392 == TX Byte 1 ==
7732 16:34:07.711253 u2DelayCellOfst[8]=0 cells (0 PI)
7733 16:34:07.711358 u2DelayCellOfst[9]=7 cells (2 PI)
7734 16:34:07.714526 u2DelayCellOfst[10]=11 cells (3 PI)
7735 16:34:07.717797 u2DelayCellOfst[11]=7 cells (2 PI)
7736 16:34:07.721067 u2DelayCellOfst[12]=15 cells (4 PI)
7737 16:34:07.724233 u2DelayCellOfst[13]=15 cells (4 PI)
7738 16:34:07.727929 u2DelayCellOfst[14]=18 cells (5 PI)
7739 16:34:07.731197 u2DelayCellOfst[15]=15 cells (4 PI)
7740 16:34:07.737660 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7741 16:34:07.741037 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7742 16:34:07.741161 DramC Write-DBI on
7743 16:34:07.741225 ==
7744 16:34:07.744406 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 16:34:07.750817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 16:34:07.750914 ==
7747 16:34:07.750973
7748 16:34:07.751028
7749 16:34:07.751079 TX Vref Scan disable
7750 16:34:07.754712 == TX Byte 0 ==
7751 16:34:07.758286 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7752 16:34:07.761393 == TX Byte 1 ==
7753 16:34:07.764497 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7754 16:34:07.768280 DramC Write-DBI off
7755 16:34:07.768397
7756 16:34:07.768483 [DATLAT]
7757 16:34:07.768565 Freq=1600, CH0 RK0
7758 16:34:07.768652
7759 16:34:07.771560 DATLAT Default: 0xf
7760 16:34:07.771639 0, 0xFFFF, sum = 0
7761 16:34:07.774854 1, 0xFFFF, sum = 0
7762 16:34:07.778180 2, 0xFFFF, sum = 0
7763 16:34:07.778281 3, 0xFFFF, sum = 0
7764 16:34:07.781481 4, 0xFFFF, sum = 0
7765 16:34:07.781580 5, 0xFFFF, sum = 0
7766 16:34:07.784590 6, 0xFFFF, sum = 0
7767 16:34:07.784765 7, 0xFFFF, sum = 0
7768 16:34:07.787958 8, 0xFFFF, sum = 0
7769 16:34:07.788062 9, 0xFFFF, sum = 0
7770 16:34:07.791905 10, 0xFFFF, sum = 0
7771 16:34:07.791989 11, 0xFFFF, sum = 0
7772 16:34:07.794694 12, 0xFFFF, sum = 0
7773 16:34:07.794776 13, 0xCFFF, sum = 0
7774 16:34:07.797856 14, 0x0, sum = 1
7775 16:34:07.797942 15, 0x0, sum = 2
7776 16:34:07.801830 16, 0x0, sum = 3
7777 16:34:07.801918 17, 0x0, sum = 4
7778 16:34:07.805168 best_step = 15
7779 16:34:07.805249
7780 16:34:07.805310 ==
7781 16:34:07.808442 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 16:34:07.811682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 16:34:07.811763 ==
7784 16:34:07.811825 RX Vref Scan: 1
7785 16:34:07.814977
7786 16:34:07.815064 Set Vref Range= 24 -> 127
7787 16:34:07.815124
7788 16:34:07.818287 RX Vref 24 -> 127, step: 1
7789 16:34:07.818368
7790 16:34:07.821530 RX Delay 3 -> 252, step: 4
7791 16:34:07.821613
7792 16:34:07.824892 Set Vref, RX VrefLevel [Byte0]: 24
7793 16:34:07.828066 [Byte1]: 24
7794 16:34:07.828150
7795 16:34:07.831235 Set Vref, RX VrefLevel [Byte0]: 25
7796 16:34:07.834328 [Byte1]: 25
7797 16:34:07.834418
7798 16:34:07.837735 Set Vref, RX VrefLevel [Byte0]: 26
7799 16:34:07.840946 [Byte1]: 26
7800 16:34:07.845092
7801 16:34:07.845186 Set Vref, RX VrefLevel [Byte0]: 27
7802 16:34:07.848641 [Byte1]: 27
7803 16:34:07.853079
7804 16:34:07.853172 Set Vref, RX VrefLevel [Byte0]: 28
7805 16:34:07.856138 [Byte1]: 28
7806 16:34:07.860665
7807 16:34:07.860788 Set Vref, RX VrefLevel [Byte0]: 29
7808 16:34:07.863700 [Byte1]: 29
7809 16:34:07.868374
7810 16:34:07.868481 Set Vref, RX VrefLevel [Byte0]: 30
7811 16:34:07.871821 [Byte1]: 30
7812 16:34:07.876288
7813 16:34:07.876374 Set Vref, RX VrefLevel [Byte0]: 31
7814 16:34:07.879232 [Byte1]: 31
7815 16:34:07.883792
7816 16:34:07.883879 Set Vref, RX VrefLevel [Byte0]: 32
7817 16:34:07.886923 [Byte1]: 32
7818 16:34:07.891254
7819 16:34:07.891362 Set Vref, RX VrefLevel [Byte0]: 33
7820 16:34:07.894699 [Byte1]: 33
7821 16:34:07.899286
7822 16:34:07.899376 Set Vref, RX VrefLevel [Byte0]: 34
7823 16:34:07.901856 [Byte1]: 34
7824 16:34:07.906505
7825 16:34:07.906590 Set Vref, RX VrefLevel [Byte0]: 35
7826 16:34:07.909679 [Byte1]: 35
7827 16:34:07.914200
7828 16:34:07.914304 Set Vref, RX VrefLevel [Byte0]: 36
7829 16:34:07.917488 [Byte1]: 36
7830 16:34:07.921791
7831 16:34:07.921876 Set Vref, RX VrefLevel [Byte0]: 37
7832 16:34:07.925076 [Byte1]: 37
7833 16:34:07.929671
7834 16:34:07.929776 Set Vref, RX VrefLevel [Byte0]: 38
7835 16:34:07.932815 [Byte1]: 38
7836 16:34:07.937357
7837 16:34:07.937443 Set Vref, RX VrefLevel [Byte0]: 39
7838 16:34:07.940548 [Byte1]: 39
7839 16:34:07.944632
7840 16:34:07.944743 Set Vref, RX VrefLevel [Byte0]: 40
7841 16:34:07.947894 [Byte1]: 40
7842 16:34:07.952274
7843 16:34:07.952370 Set Vref, RX VrefLevel [Byte0]: 41
7844 16:34:07.955588 [Byte1]: 41
7845 16:34:07.960026
7846 16:34:07.960112 Set Vref, RX VrefLevel [Byte0]: 42
7847 16:34:07.963194 [Byte1]: 42
7848 16:34:07.967712
7849 16:34:07.967801 Set Vref, RX VrefLevel [Byte0]: 43
7850 16:34:07.970861 [Byte1]: 43
7851 16:34:07.975277
7852 16:34:07.975366 Set Vref, RX VrefLevel [Byte0]: 44
7853 16:34:07.978795 [Byte1]: 44
7854 16:34:07.982896
7855 16:34:07.982982 Set Vref, RX VrefLevel [Byte0]: 45
7856 16:34:07.986443 [Byte1]: 45
7857 16:34:07.990770
7858 16:34:07.990856 Set Vref, RX VrefLevel [Byte0]: 46
7859 16:34:07.993905 [Byte1]: 46
7860 16:34:07.998668
7861 16:34:07.998757 Set Vref, RX VrefLevel [Byte0]: 47
7862 16:34:08.001757 [Byte1]: 47
7863 16:34:08.006234
7864 16:34:08.006395 Set Vref, RX VrefLevel [Byte0]: 48
7865 16:34:08.009493 [Byte1]: 48
7866 16:34:08.013515
7867 16:34:08.013596 Set Vref, RX VrefLevel [Byte0]: 49
7868 16:34:08.017382 [Byte1]: 49
7869 16:34:08.021293
7870 16:34:08.021402 Set Vref, RX VrefLevel [Byte0]: 50
7871 16:34:08.024251 [Byte1]: 50
7872 16:34:08.028970
7873 16:34:08.029093 Set Vref, RX VrefLevel [Byte0]: 51
7874 16:34:08.032355 [Byte1]: 51
7875 16:34:08.036931
7876 16:34:08.037027 Set Vref, RX VrefLevel [Byte0]: 52
7877 16:34:08.040147 [Byte1]: 52
7878 16:34:08.044596
7879 16:34:08.044731 Set Vref, RX VrefLevel [Byte0]: 53
7880 16:34:08.047830 [Byte1]: 53
7881 16:34:08.051789
7882 16:34:08.051870 Set Vref, RX VrefLevel [Byte0]: 54
7883 16:34:08.055513 [Byte1]: 54
7884 16:34:08.059738
7885 16:34:08.059839 Set Vref, RX VrefLevel [Byte0]: 55
7886 16:34:08.063122 [Byte1]: 55
7887 16:34:08.067063
7888 16:34:08.067205 Set Vref, RX VrefLevel [Byte0]: 56
7889 16:34:08.070766 [Byte1]: 56
7890 16:34:08.075055
7891 16:34:08.075145 Set Vref, RX VrefLevel [Byte0]: 57
7892 16:34:08.078307 [Byte1]: 57
7893 16:34:08.082684
7894 16:34:08.082770 Set Vref, RX VrefLevel [Byte0]: 58
7895 16:34:08.085895 [Byte1]: 58
7896 16:34:08.090315
7897 16:34:08.090430 Set Vref, RX VrefLevel [Byte0]: 59
7898 16:34:08.093326 [Byte1]: 59
7899 16:34:08.097858
7900 16:34:08.097942 Set Vref, RX VrefLevel [Byte0]: 60
7901 16:34:08.101240 [Byte1]: 60
7902 16:34:08.105770
7903 16:34:08.105881 Set Vref, RX VrefLevel [Byte0]: 61
7904 16:34:08.108822 [Byte1]: 61
7905 16:34:08.113257
7906 16:34:08.113339 Set Vref, RX VrefLevel [Byte0]: 62
7907 16:34:08.116469 [Byte1]: 62
7908 16:34:08.120985
7909 16:34:08.121063 Set Vref, RX VrefLevel [Byte0]: 63
7910 16:34:08.124268 [Byte1]: 63
7911 16:34:08.128607
7912 16:34:08.128735 Set Vref, RX VrefLevel [Byte0]: 64
7913 16:34:08.132005 [Byte1]: 64
7914 16:34:08.135929
7915 16:34:08.136037 Set Vref, RX VrefLevel [Byte0]: 65
7916 16:34:08.139272 [Byte1]: 65
7917 16:34:08.143624
7918 16:34:08.143727 Set Vref, RX VrefLevel [Byte0]: 66
7919 16:34:08.146871 [Byte1]: 66
7920 16:34:08.151594
7921 16:34:08.151701 Set Vref, RX VrefLevel [Byte0]: 67
7922 16:34:08.154918 [Byte1]: 67
7923 16:34:08.159407
7924 16:34:08.159509 Set Vref, RX VrefLevel [Byte0]: 68
7925 16:34:08.162374 [Byte1]: 68
7926 16:34:08.166882
7927 16:34:08.166993 Set Vref, RX VrefLevel [Byte0]: 69
7928 16:34:08.169989 [Byte1]: 69
7929 16:34:08.174461
7930 16:34:08.174559 Set Vref, RX VrefLevel [Byte0]: 70
7931 16:34:08.177517 [Byte1]: 70
7932 16:34:08.182115
7933 16:34:08.182214 Set Vref, RX VrefLevel [Byte0]: 71
7934 16:34:08.185249 [Byte1]: 71
7935 16:34:08.189639
7936 16:34:08.189784 Set Vref, RX VrefLevel [Byte0]: 72
7937 16:34:08.192842 [Byte1]: 72
7938 16:34:08.197452
7939 16:34:08.197564 Set Vref, RX VrefLevel [Byte0]: 73
7940 16:34:08.200604 [Byte1]: 73
7941 16:34:08.205286
7942 16:34:08.205436 Set Vref, RX VrefLevel [Byte0]: 74
7943 16:34:08.208468 [Byte1]: 74
7944 16:34:08.212419
7945 16:34:08.212505 Set Vref, RX VrefLevel [Byte0]: 75
7946 16:34:08.216212 [Byte1]: 75
7947 16:34:08.220398
7948 16:34:08.220531 Final RX Vref Byte 0 = 63 to rank0
7949 16:34:08.223637 Final RX Vref Byte 1 = 60 to rank0
7950 16:34:08.226838 Final RX Vref Byte 0 = 63 to rank1
7951 16:34:08.230149 Final RX Vref Byte 1 = 60 to rank1==
7952 16:34:08.233376 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 16:34:08.239938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 16:34:08.240038 ==
7955 16:34:08.240098 DQS Delay:
7956 16:34:08.240152 DQS0 = 0, DQS1 = 0
7957 16:34:08.243642 DQM Delay:
7958 16:34:08.243748 DQM0 = 126, DQM1 = 119
7959 16:34:08.246817 DQ Delay:
7960 16:34:08.249871 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7961 16:34:08.253637 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7962 16:34:08.256811 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7963 16:34:08.260091 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7964 16:34:08.260189
7965 16:34:08.260275
7966 16:34:08.260348
7967 16:34:08.263175 [DramC_TX_OE_Calibration] TA2
7968 16:34:08.266856 Original DQ_B0 (3 6) =30, OEN = 27
7969 16:34:08.270090 Original DQ_B1 (3 6) =30, OEN = 27
7970 16:34:08.273432 24, 0x0, End_B0=24 End_B1=24
7971 16:34:08.273516 25, 0x0, End_B0=25 End_B1=25
7972 16:34:08.276541 26, 0x0, End_B0=26 End_B1=26
7973 16:34:08.279918 27, 0x0, End_B0=27 End_B1=27
7974 16:34:08.283027 28, 0x0, End_B0=28 End_B1=28
7975 16:34:08.286442 29, 0x0, End_B0=29 End_B1=29
7976 16:34:08.286540 30, 0x0, End_B0=30 End_B1=30
7977 16:34:08.289915 31, 0x4141, End_B0=30 End_B1=30
7978 16:34:08.293236 Byte0 end_step=30 best_step=27
7979 16:34:08.296463 Byte1 end_step=30 best_step=27
7980 16:34:08.299440 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 16:34:08.303151 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 16:34:08.303255
7983 16:34:08.303339
7984 16:34:08.309396 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7985 16:34:08.313324 CH0 RK0: MR19=303, MR18=1716
7986 16:34:08.319748 CH0_RK0: MR19=0x303, MR18=0x1716, DQSOSC=398, MR23=63, INC=23, DEC=15
7987 16:34:08.319850
7988 16:34:08.322846 ----->DramcWriteLeveling(PI) begin...
7989 16:34:08.322929 ==
7990 16:34:08.326327 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 16:34:08.330060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 16:34:08.330158 ==
7993 16:34:08.333189 Write leveling (Byte 0): 34 => 34
7994 16:34:08.336411 Write leveling (Byte 1): 28 => 28
7995 16:34:08.339638 DramcWriteLeveling(PI) end<-----
7996 16:34:08.339724
7997 16:34:08.339784 ==
7998 16:34:08.342902 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 16:34:08.346061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 16:34:08.346144 ==
8001 16:34:08.349775 [Gating] SW mode calibration
8002 16:34:08.356003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 16:34:08.362509 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 16:34:08.366265 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 16:34:08.373120 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 16:34:08.376311 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 16:34:08.379569 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8008 16:34:08.382916 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8009 16:34:08.389538 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8010 16:34:08.392811 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 16:34:08.395908 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 16:34:08.402727 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 16:34:08.405640 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 16:34:08.409276 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8015 16:34:08.416131 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8016 16:34:08.418995 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8017 16:34:08.422583 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8018 16:34:08.429453 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 16:34:08.432476 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 16:34:08.435638 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 16:34:08.442522 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 16:34:08.445794 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8023 16:34:08.449103 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8024 16:34:08.455519 1 6 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8025 16:34:08.458724 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8026 16:34:08.461922 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 16:34:08.469193 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 16:34:08.472231 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 16:34:08.475264 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 16:34:08.482395 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 16:34:08.485559 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 16:34:08.488763 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8033 16:34:08.495445 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 16:34:08.498747 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 16:34:08.501869 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 16:34:08.508521 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 16:34:08.511718 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 16:34:08.515662 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 16:34:08.521767 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 16:34:08.525460 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 16:34:08.528430 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 16:34:08.535332 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 16:34:08.538535 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 16:34:08.541836 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 16:34:08.548552 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 16:34:08.551945 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 16:34:08.555034 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 16:34:08.561441 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 16:34:08.561560 Total UI for P1: 0, mck2ui 16
8050 16:34:08.564994 best dqsien dly found for B0: ( 1, 9, 10)
8051 16:34:08.571450 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 16:34:08.574667 Total UI for P1: 0, mck2ui 16
8053 16:34:08.578457 best dqsien dly found for B1: ( 1, 9, 16)
8054 16:34:08.581594 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8055 16:34:08.584715 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8056 16:34:08.584794
8057 16:34:08.588052 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8058 16:34:08.591287 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8059 16:34:08.595100 [Gating] SW calibration Done
8060 16:34:08.595189 ==
8061 16:34:08.598369 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 16:34:08.601675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 16:34:08.601784 ==
8064 16:34:08.604804 RX Vref Scan: 0
8065 16:34:08.604903
8066 16:34:08.608017 RX Vref 0 -> 0, step: 1
8067 16:34:08.608116
8068 16:34:08.608206 RX Delay 0 -> 252, step: 8
8069 16:34:08.614926 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8070 16:34:08.618065 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8071 16:34:08.621239 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8072 16:34:08.624512 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8073 16:34:08.628192 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8074 16:34:08.634492 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8075 16:34:08.637596 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8076 16:34:08.641447 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8077 16:34:08.644334 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8078 16:34:08.647722 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8079 16:34:08.654363 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8080 16:34:08.657928 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8081 16:34:08.660877 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8082 16:34:08.664340 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8083 16:34:08.667746 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8084 16:34:08.674671 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8085 16:34:08.674776 ==
8086 16:34:08.677845 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 16:34:08.681090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 16:34:08.681180 ==
8089 16:34:08.681241 DQS Delay:
8090 16:34:08.684174 DQS0 = 0, DQS1 = 0
8091 16:34:08.684264 DQM Delay:
8092 16:34:08.687683 DQM0 = 128, DQM1 = 121
8093 16:34:08.687790 DQ Delay:
8094 16:34:08.691031 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8095 16:34:08.694081 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8096 16:34:08.697207 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8097 16:34:08.704355 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8098 16:34:08.704519
8099 16:34:08.704610
8100 16:34:08.704734 ==
8101 16:34:08.707480 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 16:34:08.710668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 16:34:08.710813 ==
8104 16:34:08.710913
8105 16:34:08.710993
8106 16:34:08.713869 TX Vref Scan disable
8107 16:34:08.713967 == TX Byte 0 ==
8108 16:34:08.720878 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8109 16:34:08.724105 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8110 16:34:08.724215 == TX Byte 1 ==
8111 16:34:08.730342 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8112 16:34:08.734093 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8113 16:34:08.734201 ==
8114 16:34:08.737307 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 16:34:08.740397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 16:34:08.740512 ==
8117 16:34:08.755988
8118 16:34:08.759175 TX Vref early break, caculate TX vref
8119 16:34:08.762696 TX Vref=16, minBit 0, minWin=22, winSum=365
8120 16:34:08.765760 TX Vref=18, minBit 8, minWin=22, winSum=375
8121 16:34:08.769358 TX Vref=20, minBit 8, minWin=22, winSum=380
8122 16:34:08.772392 TX Vref=22, minBit 0, minWin=24, winSum=391
8123 16:34:08.775893 TX Vref=24, minBit 2, minWin=24, winSum=400
8124 16:34:08.782817 TX Vref=26, minBit 0, minWin=24, winSum=405
8125 16:34:08.785862 TX Vref=28, minBit 8, minWin=24, winSum=405
8126 16:34:08.789311 TX Vref=30, minBit 8, minWin=24, winSum=403
8127 16:34:08.792563 TX Vref=32, minBit 8, minWin=23, winSum=393
8128 16:34:08.795580 TX Vref=34, minBit 8, minWin=22, winSum=390
8129 16:34:08.799293 TX Vref=36, minBit 8, minWin=22, winSum=381
8130 16:34:08.805930 [TxChooseVref] Worse bit 0, Min win 24, Win sum 405, Final Vref 26
8131 16:34:08.806032
8132 16:34:08.808858 Final TX Range 0 Vref 26
8133 16:34:08.808939
8134 16:34:08.808999 ==
8135 16:34:08.812075 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 16:34:08.815873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 16:34:08.815956 ==
8138 16:34:08.816017
8139 16:34:08.818896
8140 16:34:08.818976 TX Vref Scan disable
8141 16:34:08.825344 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8142 16:34:08.825460 == TX Byte 0 ==
8143 16:34:08.829110 u2DelayCellOfst[0]=15 cells (4 PI)
8144 16:34:08.832328 u2DelayCellOfst[1]=22 cells (6 PI)
8145 16:34:08.835587 u2DelayCellOfst[2]=15 cells (4 PI)
8146 16:34:08.838669 u2DelayCellOfst[3]=15 cells (4 PI)
8147 16:34:08.841979 u2DelayCellOfst[4]=11 cells (3 PI)
8148 16:34:08.845768 u2DelayCellOfst[5]=0 cells (0 PI)
8149 16:34:08.848944 u2DelayCellOfst[6]=22 cells (6 PI)
8150 16:34:08.852039 u2DelayCellOfst[7]=22 cells (6 PI)
8151 16:34:08.855764 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8152 16:34:08.859097 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8153 16:34:08.862350 == TX Byte 1 ==
8154 16:34:08.865381 u2DelayCellOfst[8]=0 cells (0 PI)
8155 16:34:08.868653 u2DelayCellOfst[9]=3 cells (1 PI)
8156 16:34:08.872031 u2DelayCellOfst[10]=11 cells (3 PI)
8157 16:34:08.874933 u2DelayCellOfst[11]=7 cells (2 PI)
8158 16:34:08.875022 u2DelayCellOfst[12]=15 cells (4 PI)
8159 16:34:08.878314 u2DelayCellOfst[13]=11 cells (3 PI)
8160 16:34:08.881583 u2DelayCellOfst[14]=15 cells (4 PI)
8161 16:34:08.884954 u2DelayCellOfst[15]=11 cells (3 PI)
8162 16:34:08.891736 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8163 16:34:08.894805 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8164 16:34:08.894889 DramC Write-DBI on
8165 16:34:08.898453 ==
8166 16:34:08.901467 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 16:34:08.904888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 16:34:08.904996 ==
8169 16:34:08.905083
8170 16:34:08.905165
8171 16:34:08.908142 TX Vref Scan disable
8172 16:34:08.908222 == TX Byte 0 ==
8173 16:34:08.914587 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8174 16:34:08.914699 == TX Byte 1 ==
8175 16:34:08.918029 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8176 16:34:08.921375 DramC Write-DBI off
8177 16:34:08.921461
8178 16:34:08.921522 [DATLAT]
8179 16:34:08.924939 Freq=1600, CH0 RK1
8180 16:34:08.925045
8181 16:34:08.925130 DATLAT Default: 0xf
8182 16:34:08.928050 0, 0xFFFF, sum = 0
8183 16:34:08.928151 1, 0xFFFF, sum = 0
8184 16:34:08.931455 2, 0xFFFF, sum = 0
8185 16:34:08.931555 3, 0xFFFF, sum = 0
8186 16:34:08.934627 4, 0xFFFF, sum = 0
8187 16:34:08.937862 5, 0xFFFF, sum = 0
8188 16:34:08.937966 6, 0xFFFF, sum = 0
8189 16:34:08.941610 7, 0xFFFF, sum = 0
8190 16:34:08.941718 8, 0xFFFF, sum = 0
8191 16:34:08.944550 9, 0xFFFF, sum = 0
8192 16:34:08.944681 10, 0xFFFF, sum = 0
8193 16:34:08.947698 11, 0xFFFF, sum = 0
8194 16:34:08.947799 12, 0xFFFF, sum = 0
8195 16:34:08.950983 13, 0xCFFF, sum = 0
8196 16:34:08.951086 14, 0x0, sum = 1
8197 16:34:08.954828 15, 0x0, sum = 2
8198 16:34:08.954939 16, 0x0, sum = 3
8199 16:34:08.958053 17, 0x0, sum = 4
8200 16:34:08.958156 best_step = 15
8201 16:34:08.958241
8202 16:34:08.958322 ==
8203 16:34:08.961209 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 16:34:08.964928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 16:34:08.965039 ==
8206 16:34:08.968142 RX Vref Scan: 0
8207 16:34:08.968239
8208 16:34:08.971298 RX Vref 0 -> 0, step: 1
8209 16:34:08.971397
8210 16:34:08.971483 RX Delay 3 -> 252, step: 4
8211 16:34:08.978175 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8212 16:34:08.982007 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8213 16:34:08.985119 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8214 16:34:08.988135 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8215 16:34:08.991659 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8216 16:34:08.998496 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8217 16:34:09.001201 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8218 16:34:09.004871 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8219 16:34:09.008480 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8220 16:34:09.011321 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8221 16:34:09.018135 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8222 16:34:09.021330 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8223 16:34:09.024875 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8224 16:34:09.028279 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8225 16:34:09.034515 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8226 16:34:09.038083 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8227 16:34:09.038192 ==
8228 16:34:09.041216 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 16:34:09.044309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 16:34:09.044410 ==
8231 16:34:09.048163 DQS Delay:
8232 16:34:09.048263 DQS0 = 0, DQS1 = 0
8233 16:34:09.048349 DQM Delay:
8234 16:34:09.051395 DQM0 = 124, DQM1 = 118
8235 16:34:09.051493 DQ Delay:
8236 16:34:09.054504 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8237 16:34:09.057763 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8238 16:34:09.061439 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8239 16:34:09.067696 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8240 16:34:09.067820
8241 16:34:09.067906
8242 16:34:09.067988
8243 16:34:09.070945 [DramC_TX_OE_Calibration] TA2
8244 16:34:09.071044 Original DQ_B0 (3 6) =30, OEN = 27
8245 16:34:09.074818 Original DQ_B1 (3 6) =30, OEN = 27
8246 16:34:09.077859 24, 0x0, End_B0=24 End_B1=24
8247 16:34:09.080855 25, 0x0, End_B0=25 End_B1=25
8248 16:34:09.084578 26, 0x0, End_B0=26 End_B1=26
8249 16:34:09.087757 27, 0x0, End_B0=27 End_B1=27
8250 16:34:09.087859 28, 0x0, End_B0=28 End_B1=28
8251 16:34:09.090880 29, 0x0, End_B0=29 End_B1=29
8252 16:34:09.093974 30, 0x0, End_B0=30 End_B1=30
8253 16:34:09.097779 31, 0x4545, End_B0=30 End_B1=30
8254 16:34:09.100837 Byte0 end_step=30 best_step=27
8255 16:34:09.103864 Byte1 end_step=30 best_step=27
8256 16:34:09.103965 Byte0 TX OE(2T, 0.5T) = (3, 3)
8257 16:34:09.107357 Byte1 TX OE(2T, 0.5T) = (3, 3)
8258 16:34:09.107457
8259 16:34:09.107540
8260 16:34:09.116990 [DQSOSCAuto] RK1, (LSB)MR18= 0x2513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8261 16:34:09.120573 CH0 RK1: MR19=303, MR18=2513
8262 16:34:09.123664 CH0_RK1: MR19=0x303, MR18=0x2513, DQSOSC=391, MR23=63, INC=24, DEC=16
8263 16:34:09.126921 [RxdqsGatingPostProcess] freq 1600
8264 16:34:09.133383 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8265 16:34:09.137054 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 16:34:09.139967 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 16:34:09.143490 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 16:34:09.147122 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 16:34:09.150069 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 16:34:09.153625 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 16:34:09.153734 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 16:34:09.156893 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 16:34:09.160080 Pre-setting of DQS Precalculation
8274 16:34:09.166980 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8275 16:34:09.167081 ==
8276 16:34:09.170131 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 16:34:09.173318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 16:34:09.173403 ==
8279 16:34:09.179617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 16:34:09.183357 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 16:34:09.186426 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 16:34:09.192895 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 16:34:09.202957 [CA 0] Center 41 (12~71) winsize 60
8284 16:34:09.205988 [CA 1] Center 42 (12~72) winsize 61
8285 16:34:09.209116 [CA 2] Center 37 (8~67) winsize 60
8286 16:34:09.212632 [CA 3] Center 37 (8~66) winsize 59
8287 16:34:09.216071 [CA 4] Center 37 (8~67) winsize 60
8288 16:34:09.219050 [CA 5] Center 36 (7~66) winsize 60
8289 16:34:09.219153
8290 16:34:09.222660 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 16:34:09.222759
8292 16:34:09.229274 [CATrainingPosCal] consider 1 rank data
8293 16:34:09.229392 u2DelayCellTimex100 = 258/100 ps
8294 16:34:09.235449 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8295 16:34:09.239201 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8296 16:34:09.242279 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8297 16:34:09.245381 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8298 16:34:09.249036 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8299 16:34:09.252411 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8300 16:34:09.252513
8301 16:34:09.255872 CA PerBit enable=1, Macro0, CA PI delay=36
8302 16:34:09.255974
8303 16:34:09.258741 [CBTSetCACLKResult] CA Dly = 36
8304 16:34:09.262456 CS Dly: 9 (0~40)
8305 16:34:09.265704 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 16:34:09.268777 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 16:34:09.268878 ==
8308 16:34:09.271957 Dram Type= 6, Freq= 0, CH_1, rank 1
8309 16:34:09.275708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 16:34:09.278876 ==
8311 16:34:09.282242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 16:34:09.285222 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 16:34:09.291984 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 16:34:09.298137 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 16:34:09.305671 [CA 0] Center 41 (12~71) winsize 60
8316 16:34:09.309401 [CA 1] Center 42 (12~72) winsize 61
8317 16:34:09.312533 [CA 2] Center 38 (9~67) winsize 59
8318 16:34:09.315668 [CA 3] Center 36 (7~66) winsize 60
8319 16:34:09.318836 [CA 4] Center 38 (8~68) winsize 61
8320 16:34:09.322556 [CA 5] Center 36 (6~66) winsize 61
8321 16:34:09.322660
8322 16:34:09.325609 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8323 16:34:09.325707
8324 16:34:09.331831 [CATrainingPosCal] consider 2 rank data
8325 16:34:09.331938 u2DelayCellTimex100 = 258/100 ps
8326 16:34:09.338451 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8327 16:34:09.342291 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8328 16:34:09.345316 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8329 16:34:09.348283 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8330 16:34:09.352035 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8331 16:34:09.355163 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8332 16:34:09.355269
8333 16:34:09.358118 CA PerBit enable=1, Macro0, CA PI delay=36
8334 16:34:09.358220
8335 16:34:09.361492 [CBTSetCACLKResult] CA Dly = 36
8336 16:34:09.364893 CS Dly: 11 (0~44)
8337 16:34:09.368620 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 16:34:09.371695 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 16:34:09.371799
8340 16:34:09.375025 ----->DramcWriteLeveling(PI) begin...
8341 16:34:09.375126 ==
8342 16:34:09.378216 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 16:34:09.385217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 16:34:09.385331 ==
8345 16:34:09.388292 Write leveling (Byte 0): 24 => 24
8346 16:34:09.391433 Write leveling (Byte 1): 28 => 28
8347 16:34:09.391532 DramcWriteLeveling(PI) end<-----
8348 16:34:09.391617
8349 16:34:09.395047 ==
8350 16:34:09.398089 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 16:34:09.401312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 16:34:09.401414 ==
8353 16:34:09.404949 [Gating] SW mode calibration
8354 16:34:09.411685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8355 16:34:09.414727 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8356 16:34:09.421125 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 16:34:09.424853 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 16:34:09.428355 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 16:34:09.435081 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 16:34:09.438139 1 4 16 | B1->B0 | 3333 3130 | 1 1 | (1 1) (0 0)
8361 16:34:09.441188 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 16:34:09.448058 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 16:34:09.451109 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 16:34:09.454892 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 16:34:09.461289 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 16:34:09.464471 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 16:34:09.468090 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8368 16:34:09.474568 1 5 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (1 0)
8369 16:34:09.477512 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 16:34:09.480655 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 16:34:09.487683 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 16:34:09.490945 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 16:34:09.494135 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 16:34:09.500688 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 16:34:09.504337 1 6 12 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
8376 16:34:09.507594 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 16:34:09.514301 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 16:34:09.517384 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 16:34:09.520592 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 16:34:09.527271 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 16:34:09.530295 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 16:34:09.533861 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 16:34:09.540602 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8384 16:34:09.543758 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 16:34:09.546889 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 16:34:09.553758 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 16:34:09.556945 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 16:34:09.559991 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 16:34:09.566883 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 16:34:09.570091 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 16:34:09.573809 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 16:34:09.580433 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 16:34:09.583564 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 16:34:09.586721 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 16:34:09.590534 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 16:34:09.596809 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 16:34:09.599923 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 16:34:09.603738 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 16:34:09.609995 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8400 16:34:09.613674 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 16:34:09.616738 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8402 16:34:09.620245 Total UI for P1: 0, mck2ui 16
8403 16:34:09.623399 best dqsien dly found for B1: ( 1, 9, 16)
8404 16:34:09.630273 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 16:34:09.633391 Total UI for P1: 0, mck2ui 16
8406 16:34:09.636386 best dqsien dly found for B0: ( 1, 9, 16)
8407 16:34:09.639994 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8408 16:34:09.643623 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8409 16:34:09.643729
8410 16:34:09.646658 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 16:34:09.650251 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 16:34:09.653383 [Gating] SW calibration Done
8413 16:34:09.653487 ==
8414 16:34:09.656576 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 16:34:09.659812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 16:34:09.659914 ==
8417 16:34:09.662955 RX Vref Scan: 0
8418 16:34:09.663053
8419 16:34:09.666806 RX Vref 0 -> 0, step: 1
8420 16:34:09.666920
8421 16:34:09.667006 RX Delay 0 -> 252, step: 8
8422 16:34:09.673460 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8423 16:34:09.676579 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8424 16:34:09.679551 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8425 16:34:09.682971 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8426 16:34:09.686307 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8427 16:34:09.689919 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8428 16:34:09.696421 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8429 16:34:09.699655 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8430 16:34:09.703452 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8431 16:34:09.706402 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8432 16:34:09.709477 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8433 16:34:09.716513 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8434 16:34:09.719748 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8435 16:34:09.722696 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8436 16:34:09.726430 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8437 16:34:09.732695 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8438 16:34:09.732831 ==
8439 16:34:09.736508 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 16:34:09.739526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 16:34:09.739627 ==
8442 16:34:09.739714 DQS Delay:
8443 16:34:09.742713 DQS0 = 0, DQS1 = 0
8444 16:34:09.742812 DQM Delay:
8445 16:34:09.746518 DQM0 = 132, DQM1 = 126
8446 16:34:09.746619 DQ Delay:
8447 16:34:09.749555 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8448 16:34:09.752497 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8449 16:34:09.756214 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8450 16:34:09.759322 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8451 16:34:09.759425
8452 16:34:09.759510
8453 16:34:09.762629 ==
8454 16:34:09.765751 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 16:34:09.769638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 16:34:09.769755 ==
8457 16:34:09.769842
8458 16:34:09.769923
8459 16:34:09.772686 TX Vref Scan disable
8460 16:34:09.772783 == TX Byte 0 ==
8461 16:34:09.779336 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8462 16:34:09.782283 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8463 16:34:09.782386 == TX Byte 1 ==
8464 16:34:09.788911 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8465 16:34:09.792778 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8466 16:34:09.792887 ==
8467 16:34:09.795698 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 16:34:09.798972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 16:34:09.799075 ==
8470 16:34:09.812712
8471 16:34:09.815737 TX Vref early break, caculate TX vref
8472 16:34:09.818984 TX Vref=16, minBit 1, minWin=21, winSum=362
8473 16:34:09.822686 TX Vref=18, minBit 1, minWin=22, winSum=370
8474 16:34:09.825678 TX Vref=20, minBit 11, minWin=21, winSum=379
8475 16:34:09.829371 TX Vref=22, minBit 6, minWin=23, winSum=387
8476 16:34:09.832413 TX Vref=24, minBit 1, minWin=24, winSum=403
8477 16:34:09.838752 TX Vref=26, minBit 0, minWin=25, winSum=414
8478 16:34:09.842425 TX Vref=28, minBit 5, minWin=24, winSum=413
8479 16:34:09.845468 TX Vref=30, minBit 0, minWin=23, winSum=409
8480 16:34:09.848685 TX Vref=32, minBit 0, minWin=24, winSum=407
8481 16:34:09.852268 TX Vref=34, minBit 0, minWin=23, winSum=391
8482 16:34:09.858985 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8483 16:34:09.859095
8484 16:34:09.861921 Final TX Range 0 Vref 26
8485 16:34:09.862022
8486 16:34:09.862107 ==
8487 16:34:09.865633 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 16:34:09.868768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 16:34:09.868869 ==
8490 16:34:09.868953
8491 16:34:09.869033
8492 16:34:09.871933 TX Vref Scan disable
8493 16:34:09.878786 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8494 16:34:09.878882 == TX Byte 0 ==
8495 16:34:09.881914 u2DelayCellOfst[0]=22 cells (6 PI)
8496 16:34:09.884956 u2DelayCellOfst[1]=15 cells (4 PI)
8497 16:34:09.888623 u2DelayCellOfst[2]=0 cells (0 PI)
8498 16:34:09.891557 u2DelayCellOfst[3]=7 cells (2 PI)
8499 16:34:09.895108 u2DelayCellOfst[4]=11 cells (3 PI)
8500 16:34:09.898705 u2DelayCellOfst[5]=22 cells (6 PI)
8501 16:34:09.901846 u2DelayCellOfst[6]=22 cells (6 PI)
8502 16:34:09.905052 u2DelayCellOfst[7]=7 cells (2 PI)
8503 16:34:09.908256 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8504 16:34:09.911415 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8505 16:34:09.915184 == TX Byte 1 ==
8506 16:34:09.918249 u2DelayCellOfst[8]=0 cells (0 PI)
8507 16:34:09.918348 u2DelayCellOfst[9]=7 cells (2 PI)
8508 16:34:09.921348 u2DelayCellOfst[10]=15 cells (4 PI)
8509 16:34:09.925057 u2DelayCellOfst[11]=11 cells (3 PI)
8510 16:34:09.928180 u2DelayCellOfst[12]=18 cells (5 PI)
8511 16:34:09.931160 u2DelayCellOfst[13]=22 cells (6 PI)
8512 16:34:09.934936 u2DelayCellOfst[14]=22 cells (6 PI)
8513 16:34:09.938098 u2DelayCellOfst[15]=22 cells (6 PI)
8514 16:34:09.941738 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8515 16:34:09.947916 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 16:34:09.948016 DramC Write-DBI on
8517 16:34:09.948103 ==
8518 16:34:09.951784 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 16:34:09.957972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 16:34:09.958072 ==
8521 16:34:09.958153
8522 16:34:09.958230
8523 16:34:09.958306 TX Vref Scan disable
8524 16:34:09.961720 == TX Byte 0 ==
8525 16:34:09.965290 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8526 16:34:09.968378 == TX Byte 1 ==
8527 16:34:09.971966 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8528 16:34:09.975245 DramC Write-DBI off
8529 16:34:09.975342
8530 16:34:09.975427 [DATLAT]
8531 16:34:09.975508 Freq=1600, CH1 RK0
8532 16:34:09.975589
8533 16:34:09.978377 DATLAT Default: 0xf
8534 16:34:09.978474 0, 0xFFFF, sum = 0
8535 16:34:09.981498 1, 0xFFFF, sum = 0
8536 16:34:09.985114 2, 0xFFFF, sum = 0
8537 16:34:09.985211 3, 0xFFFF, sum = 0
8538 16:34:09.988286 4, 0xFFFF, sum = 0
8539 16:34:09.988368 5, 0xFFFF, sum = 0
8540 16:34:09.991527 6, 0xFFFF, sum = 0
8541 16:34:09.991605 7, 0xFFFF, sum = 0
8542 16:34:09.995166 8, 0xFFFF, sum = 0
8543 16:34:09.995268 9, 0xFFFF, sum = 0
8544 16:34:09.998264 10, 0xFFFF, sum = 0
8545 16:34:09.998368 11, 0xFFFF, sum = 0
8546 16:34:10.001816 12, 0xFFFF, sum = 0
8547 16:34:10.001916 13, 0x8FFF, sum = 0
8548 16:34:10.005285 14, 0x0, sum = 1
8549 16:34:10.005385 15, 0x0, sum = 2
8550 16:34:10.008298 16, 0x0, sum = 3
8551 16:34:10.008397 17, 0x0, sum = 4
8552 16:34:10.011934 best_step = 15
8553 16:34:10.012031
8554 16:34:10.012181 ==
8555 16:34:10.015139 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 16:34:10.018163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 16:34:10.018259 ==
8558 16:34:10.021889 RX Vref Scan: 1
8559 16:34:10.021985
8560 16:34:10.022067 Set Vref Range= 24 -> 127
8561 16:34:10.022146
8562 16:34:10.025027 RX Vref 24 -> 127, step: 1
8563 16:34:10.025122
8564 16:34:10.028096 RX Delay 11 -> 252, step: 4
8565 16:34:10.028191
8566 16:34:10.031758 Set Vref, RX VrefLevel [Byte0]: 24
8567 16:34:10.034788 [Byte1]: 24
8568 16:34:10.034884
8569 16:34:10.038530 Set Vref, RX VrefLevel [Byte0]: 25
8570 16:34:10.041724 [Byte1]: 25
8571 16:34:10.041826
8572 16:34:10.044851 Set Vref, RX VrefLevel [Byte0]: 26
8573 16:34:10.047919 [Byte1]: 26
8574 16:34:10.052289
8575 16:34:10.052389 Set Vref, RX VrefLevel [Byte0]: 27
8576 16:34:10.055390 [Byte1]: 27
8577 16:34:10.059569
8578 16:34:10.059671 Set Vref, RX VrefLevel [Byte0]: 28
8579 16:34:10.063347 [Byte1]: 28
8580 16:34:10.067759
8581 16:34:10.067858 Set Vref, RX VrefLevel [Byte0]: 29
8582 16:34:10.070890 [Byte1]: 29
8583 16:34:10.075210
8584 16:34:10.075309 Set Vref, RX VrefLevel [Byte0]: 30
8585 16:34:10.078125 [Byte1]: 30
8586 16:34:10.082457
8587 16:34:10.082552 Set Vref, RX VrefLevel [Byte0]: 31
8588 16:34:10.086245 [Byte1]: 31
8589 16:34:10.090584
8590 16:34:10.090683 Set Vref, RX VrefLevel [Byte0]: 32
8591 16:34:10.093771 [Byte1]: 32
8592 16:34:10.098210
8593 16:34:10.098306 Set Vref, RX VrefLevel [Byte0]: 33
8594 16:34:10.101175 [Byte1]: 33
8595 16:34:10.105483
8596 16:34:10.105584 Set Vref, RX VrefLevel [Byte0]: 34
8597 16:34:10.109154 [Byte1]: 34
8598 16:34:10.113338
8599 16:34:10.113436 Set Vref, RX VrefLevel [Byte0]: 35
8600 16:34:10.116363 [Byte1]: 35
8601 16:34:10.120447
8602 16:34:10.120548 Set Vref, RX VrefLevel [Byte0]: 36
8603 16:34:10.124288 [Byte1]: 36
8604 16:34:10.128610
8605 16:34:10.128751 Set Vref, RX VrefLevel [Byte0]: 37
8606 16:34:10.131671 [Byte1]: 37
8607 16:34:10.136099
8608 16:34:10.136198 Set Vref, RX VrefLevel [Byte0]: 38
8609 16:34:10.139331 [Byte1]: 38
8610 16:34:10.143815
8611 16:34:10.143913 Set Vref, RX VrefLevel [Byte0]: 39
8612 16:34:10.146930 [Byte1]: 39
8613 16:34:10.151487
8614 16:34:10.151583 Set Vref, RX VrefLevel [Byte0]: 40
8615 16:34:10.154624 [Byte1]: 40
8616 16:34:10.158799
8617 16:34:10.158897 Set Vref, RX VrefLevel [Byte0]: 41
8618 16:34:10.162004 [Byte1]: 41
8619 16:34:10.166375
8620 16:34:10.166473 Set Vref, RX VrefLevel [Byte0]: 42
8621 16:34:10.169582 [Byte1]: 42
8622 16:34:10.174064
8623 16:34:10.174162 Set Vref, RX VrefLevel [Byte0]: 43
8624 16:34:10.177357 [Byte1]: 43
8625 16:34:10.181572
8626 16:34:10.181669 Set Vref, RX VrefLevel [Byte0]: 44
8627 16:34:10.185297 [Byte1]: 44
8628 16:34:10.189147
8629 16:34:10.189245 Set Vref, RX VrefLevel [Byte0]: 45
8630 16:34:10.192882 [Byte1]: 45
8631 16:34:10.196619
8632 16:34:10.196749 Set Vref, RX VrefLevel [Byte0]: 46
8633 16:34:10.200454 [Byte1]: 46
8634 16:34:10.204274
8635 16:34:10.204370 Set Vref, RX VrefLevel [Byte0]: 47
8636 16:34:10.207931 [Byte1]: 47
8637 16:34:10.212384
8638 16:34:10.212480 Set Vref, RX VrefLevel [Byte0]: 48
8639 16:34:10.215384 [Byte1]: 48
8640 16:34:10.219663
8641 16:34:10.219759 Set Vref, RX VrefLevel [Byte0]: 49
8642 16:34:10.222765 [Byte1]: 49
8643 16:34:10.227599
8644 16:34:10.227694 Set Vref, RX VrefLevel [Byte0]: 50
8645 16:34:10.230593 [Byte1]: 50
8646 16:34:10.235424
8647 16:34:10.235521 Set Vref, RX VrefLevel [Byte0]: 51
8648 16:34:10.238595 [Byte1]: 51
8649 16:34:10.242420
8650 16:34:10.242516 Set Vref, RX VrefLevel [Byte0]: 52
8651 16:34:10.246067 [Byte1]: 52
8652 16:34:10.250550
8653 16:34:10.250646 Set Vref, RX VrefLevel [Byte0]: 53
8654 16:34:10.253653 [Byte1]: 53
8655 16:34:10.258036
8656 16:34:10.258132 Set Vref, RX VrefLevel [Byte0]: 54
8657 16:34:10.261099 [Byte1]: 54
8658 16:34:10.265430
8659 16:34:10.265526 Set Vref, RX VrefLevel [Byte0]: 55
8660 16:34:10.268924 [Byte1]: 55
8661 16:34:10.273214
8662 16:34:10.273312 Set Vref, RX VrefLevel [Byte0]: 56
8663 16:34:10.276342 [Byte1]: 56
8664 16:34:10.280664
8665 16:34:10.280775 Set Vref, RX VrefLevel [Byte0]: 57
8666 16:34:10.283629 [Byte1]: 57
8667 16:34:10.287950
8668 16:34:10.288047 Set Vref, RX VrefLevel [Byte0]: 58
8669 16:34:10.291712 [Byte1]: 58
8670 16:34:10.295970
8671 16:34:10.296067 Set Vref, RX VrefLevel [Byte0]: 59
8672 16:34:10.298951 [Byte1]: 59
8673 16:34:10.303295
8674 16:34:10.303392 Set Vref, RX VrefLevel [Byte0]: 60
8675 16:34:10.306398 [Byte1]: 60
8676 16:34:10.310819
8677 16:34:10.310912 Set Vref, RX VrefLevel [Byte0]: 61
8678 16:34:10.314381 [Byte1]: 61
8679 16:34:10.318639
8680 16:34:10.318737 Set Vref, RX VrefLevel [Byte0]: 62
8681 16:34:10.321811 [Byte1]: 62
8682 16:34:10.326373
8683 16:34:10.326470 Set Vref, RX VrefLevel [Byte0]: 63
8684 16:34:10.329331 [Byte1]: 63
8685 16:34:10.333859
8686 16:34:10.333956 Set Vref, RX VrefLevel [Byte0]: 64
8687 16:34:10.337464 [Byte1]: 64
8688 16:34:10.341582
8689 16:34:10.341678 Set Vref, RX VrefLevel [Byte0]: 65
8690 16:34:10.345037 [Byte1]: 65
8691 16:34:10.349241
8692 16:34:10.349338 Set Vref, RX VrefLevel [Byte0]: 66
8693 16:34:10.352120 [Byte1]: 66
8694 16:34:10.356490
8695 16:34:10.356590 Set Vref, RX VrefLevel [Byte0]: 67
8696 16:34:10.360198 [Byte1]: 67
8697 16:34:10.364426
8698 16:34:10.364540 Set Vref, RX VrefLevel [Byte0]: 68
8699 16:34:10.367600 [Byte1]: 68
8700 16:34:10.371952
8701 16:34:10.372057 Set Vref, RX VrefLevel [Byte0]: 69
8702 16:34:10.375573 [Byte1]: 69
8703 16:34:10.379480
8704 16:34:10.379644 Set Vref, RX VrefLevel [Byte0]: 70
8705 16:34:10.382806 [Byte1]: 70
8706 16:34:10.387272
8707 16:34:10.387435 Set Vref, RX VrefLevel [Byte0]: 71
8708 16:34:10.390392 [Byte1]: 71
8709 16:34:10.395312
8710 16:34:10.395474 Final RX Vref Byte 0 = 55 to rank0
8711 16:34:10.398346 Final RX Vref Byte 1 = 54 to rank0
8712 16:34:10.401340 Final RX Vref Byte 0 = 55 to rank1
8713 16:34:10.405100 Final RX Vref Byte 1 = 54 to rank1==
8714 16:34:10.408103 Dram Type= 6, Freq= 0, CH_1, rank 0
8715 16:34:10.414478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 16:34:10.414579 ==
8717 16:34:10.414663 DQS Delay:
8718 16:34:10.414743 DQS0 = 0, DQS1 = 0
8719 16:34:10.418287 DQM Delay:
8720 16:34:10.418388 DQM0 = 130, DQM1 = 123
8721 16:34:10.421304 DQ Delay:
8722 16:34:10.424891 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =126
8723 16:34:10.427796 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8724 16:34:10.431303 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8725 16:34:10.434504 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8726 16:34:10.434581
8727 16:34:10.434640
8728 16:34:10.434695
8729 16:34:10.438192 [DramC_TX_OE_Calibration] TA2
8730 16:34:10.441366 Original DQ_B0 (3 6) =30, OEN = 27
8731 16:34:10.444500 Original DQ_B1 (3 6) =30, OEN = 27
8732 16:34:10.447997 24, 0x0, End_B0=24 End_B1=24
8733 16:34:10.448076 25, 0x0, End_B0=25 End_B1=25
8734 16:34:10.451130 26, 0x0, End_B0=26 End_B1=26
8735 16:34:10.454790 27, 0x0, End_B0=27 End_B1=27
8736 16:34:10.457739 28, 0x0, End_B0=28 End_B1=28
8737 16:34:10.461395 29, 0x0, End_B0=29 End_B1=29
8738 16:34:10.461473 30, 0x0, End_B0=30 End_B1=30
8739 16:34:10.464393 31, 0x4141, End_B0=30 End_B1=30
8740 16:34:10.467921 Byte0 end_step=30 best_step=27
8741 16:34:10.471041 Byte1 end_step=30 best_step=27
8742 16:34:10.474151 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 16:34:10.477900 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 16:34:10.477979
8745 16:34:10.478039
8746 16:34:10.484128 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8747 16:34:10.488011 CH1 RK0: MR19=303, MR18=80C
8748 16:34:10.494408 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8749 16:34:10.494507
8750 16:34:10.497456 ----->DramcWriteLeveling(PI) begin...
8751 16:34:10.497560 ==
8752 16:34:10.500997 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 16:34:10.503931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 16:34:10.504023 ==
8755 16:34:10.507692 Write leveling (Byte 0): 25 => 25
8756 16:34:10.510908 Write leveling (Byte 1): 27 => 27
8757 16:34:10.514171 DramcWriteLeveling(PI) end<-----
8758 16:34:10.514271
8759 16:34:10.514356 ==
8760 16:34:10.517319 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 16:34:10.520522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 16:34:10.520624 ==
8763 16:34:10.524146 [Gating] SW mode calibration
8764 16:34:10.530962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8765 16:34:10.537406 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8766 16:34:10.540443 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 16:34:10.543957 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 16:34:10.550821 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 0)
8769 16:34:10.553790 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8770 16:34:10.556993 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 16:34:10.563892 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 16:34:10.566907 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 16:34:10.570454 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 16:34:10.576774 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 16:34:10.580283 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8776 16:34:10.583883 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8777 16:34:10.590250 1 5 12 | B1->B0 | 2525 2423 | 0 1 | (1 0) (0 0)
8778 16:34:10.593411 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 16:34:10.597130 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 16:34:10.603533 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 16:34:10.606547 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 16:34:10.610030 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 16:34:10.616467 1 6 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8784 16:34:10.620197 1 6 8 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8785 16:34:10.623474 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8786 16:34:10.629925 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 16:34:10.633267 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 16:34:10.636456 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 16:34:10.643329 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 16:34:10.646496 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 16:34:10.649908 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 16:34:10.656649 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8793 16:34:10.659797 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 16:34:10.662938 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 16:34:10.670027 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 16:34:10.673384 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 16:34:10.676364 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 16:34:10.682793 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 16:34:10.686346 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 16:34:10.689678 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 16:34:10.696253 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 16:34:10.699263 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 16:34:10.702967 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 16:34:10.709241 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 16:34:10.713042 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 16:34:10.716162 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 16:34:10.722944 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8808 16:34:10.726042 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8809 16:34:10.729205 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8810 16:34:10.732426 Total UI for P1: 0, mck2ui 16
8811 16:34:10.735614 best dqsien dly found for B0: ( 1, 9, 6)
8812 16:34:10.742597 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 16:34:10.742680 Total UI for P1: 0, mck2ui 16
8814 16:34:10.745610 best dqsien dly found for B1: ( 1, 9, 12)
8815 16:34:10.752618 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8816 16:34:10.755735 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8817 16:34:10.755812
8818 16:34:10.758707 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8819 16:34:10.762289 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8820 16:34:10.765655 [Gating] SW calibration Done
8821 16:34:10.765733 ==
8822 16:34:10.768685 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 16:34:10.772421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 16:34:10.772509 ==
8825 16:34:10.775550 RX Vref Scan: 0
8826 16:34:10.775631
8827 16:34:10.775690 RX Vref 0 -> 0, step: 1
8828 16:34:10.775746
8829 16:34:10.778677 RX Delay 0 -> 252, step: 8
8830 16:34:10.781801 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8831 16:34:10.788737 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8832 16:34:10.791804 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8833 16:34:10.795525 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8834 16:34:10.798637 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8835 16:34:10.802194 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8836 16:34:10.808542 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8837 16:34:10.811850 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8838 16:34:10.815302 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8839 16:34:10.818503 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8840 16:34:10.821687 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8841 16:34:10.828336 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8842 16:34:10.831449 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8843 16:34:10.835158 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8844 16:34:10.838440 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8845 16:34:10.841798 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8846 16:34:10.844904 ==
8847 16:34:10.847897 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 16:34:10.851493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 16:34:10.851595 ==
8850 16:34:10.851655 DQS Delay:
8851 16:34:10.854695 DQS0 = 0, DQS1 = 0
8852 16:34:10.854777 DQM Delay:
8853 16:34:10.858475 DQM0 = 131, DQM1 = 128
8854 16:34:10.858556 DQ Delay:
8855 16:34:10.861592 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8856 16:34:10.864797 DQ4 =123, DQ5 =143, DQ6 =139, DQ7 =131
8857 16:34:10.867866 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8858 16:34:10.871520 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8859 16:34:10.871599
8860 16:34:10.871659
8861 16:34:10.871714 ==
8862 16:34:10.875008 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 16:34:10.881487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 16:34:10.881567 ==
8865 16:34:10.881626
8866 16:34:10.881710
8867 16:34:10.884771 TX Vref Scan disable
8868 16:34:10.884848 == TX Byte 0 ==
8869 16:34:10.887924 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8870 16:34:10.894801 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8871 16:34:10.894881 == TX Byte 1 ==
8872 16:34:10.897859 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8873 16:34:10.904340 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8874 16:34:10.904419 ==
8875 16:34:10.907517 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 16:34:10.910680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 16:34:10.910756 ==
8878 16:34:10.924920
8879 16:34:10.927972 TX Vref early break, caculate TX vref
8880 16:34:10.931191 TX Vref=16, minBit 0, minWin=23, winSum=385
8881 16:34:10.934729 TX Vref=18, minBit 0, minWin=23, winSum=391
8882 16:34:10.938365 TX Vref=20, minBit 0, minWin=23, winSum=404
8883 16:34:10.941594 TX Vref=22, minBit 0, minWin=23, winSum=410
8884 16:34:10.944766 TX Vref=24, minBit 0, minWin=25, winSum=421
8885 16:34:10.950977 TX Vref=26, minBit 0, minWin=25, winSum=424
8886 16:34:10.954682 TX Vref=28, minBit 6, minWin=25, winSum=425
8887 16:34:10.957899 TX Vref=30, minBit 1, minWin=25, winSum=424
8888 16:34:10.961011 TX Vref=32, minBit 1, minWin=24, winSum=415
8889 16:34:10.964160 TX Vref=34, minBit 0, minWin=24, winSum=406
8890 16:34:10.971080 TX Vref=36, minBit 1, minWin=23, winSum=401
8891 16:34:10.974242 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 28
8892 16:34:10.974321
8893 16:34:10.977336 Final TX Range 0 Vref 28
8894 16:34:10.977412
8895 16:34:10.977470 ==
8896 16:34:10.981020 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 16:34:10.984051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 16:34:10.987648 ==
8899 16:34:10.987727
8900 16:34:10.987788
8901 16:34:10.987841 TX Vref Scan disable
8902 16:34:10.994226 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8903 16:34:10.994325 == TX Byte 0 ==
8904 16:34:10.997516 u2DelayCellOfst[0]=18 cells (5 PI)
8905 16:34:11.000627 u2DelayCellOfst[1]=18 cells (5 PI)
8906 16:34:11.003825 u2DelayCellOfst[2]=0 cells (0 PI)
8907 16:34:11.007555 u2DelayCellOfst[3]=7 cells (2 PI)
8908 16:34:11.010634 u2DelayCellOfst[4]=11 cells (3 PI)
8909 16:34:11.014303 u2DelayCellOfst[5]=22 cells (6 PI)
8910 16:34:11.017539 u2DelayCellOfst[6]=22 cells (6 PI)
8911 16:34:11.020783 u2DelayCellOfst[7]=7 cells (2 PI)
8912 16:34:11.023845 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 16:34:11.027520 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8914 16:34:11.030566 == TX Byte 1 ==
8915 16:34:11.033605 u2DelayCellOfst[8]=0 cells (0 PI)
8916 16:34:11.037271 u2DelayCellOfst[9]=7 cells (2 PI)
8917 16:34:11.040611 u2DelayCellOfst[10]=15 cells (4 PI)
8918 16:34:11.044008 u2DelayCellOfst[11]=7 cells (2 PI)
8919 16:34:11.044084 u2DelayCellOfst[12]=18 cells (5 PI)
8920 16:34:11.047156 u2DelayCellOfst[13]=18 cells (5 PI)
8921 16:34:11.050586 u2DelayCellOfst[14]=22 cells (6 PI)
8922 16:34:11.053728 u2DelayCellOfst[15]=18 cells (5 PI)
8923 16:34:11.060420 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8924 16:34:11.063736 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8925 16:34:11.063812 DramC Write-DBI on
8926 16:34:11.066931 ==
8927 16:34:11.070536 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 16:34:11.073623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 16:34:11.073700 ==
8930 16:34:11.073758
8931 16:34:11.073812
8932 16:34:11.077318 TX Vref Scan disable
8933 16:34:11.077393 == TX Byte 0 ==
8934 16:34:11.083631 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8935 16:34:11.083707 == TX Byte 1 ==
8936 16:34:11.086906 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8937 16:34:11.090622 DramC Write-DBI off
8938 16:34:11.090698
8939 16:34:11.090756 [DATLAT]
8940 16:34:11.093663 Freq=1600, CH1 RK1
8941 16:34:11.093739
8942 16:34:11.093798 DATLAT Default: 0xf
8943 16:34:11.097118 0, 0xFFFF, sum = 0
8944 16:34:11.097198 1, 0xFFFF, sum = 0
8945 16:34:11.100104 2, 0xFFFF, sum = 0
8946 16:34:11.100182 3, 0xFFFF, sum = 0
8947 16:34:11.103599 4, 0xFFFF, sum = 0
8948 16:34:11.103677 5, 0xFFFF, sum = 0
8949 16:34:11.106839 6, 0xFFFF, sum = 0
8950 16:34:11.106916 7, 0xFFFF, sum = 0
8951 16:34:11.110540 8, 0xFFFF, sum = 0
8952 16:34:11.110617 9, 0xFFFF, sum = 0
8953 16:34:11.113731 10, 0xFFFF, sum = 0
8954 16:34:11.116916 11, 0xFFFF, sum = 0
8955 16:34:11.116993 12, 0xFFFF, sum = 0
8956 16:34:11.120174 13, 0x8FFF, sum = 0
8957 16:34:11.120251 14, 0x0, sum = 1
8958 16:34:11.123402 15, 0x0, sum = 2
8959 16:34:11.123478 16, 0x0, sum = 3
8960 16:34:11.127084 17, 0x0, sum = 4
8961 16:34:11.127161 best_step = 15
8962 16:34:11.127220
8963 16:34:11.127274 ==
8964 16:34:11.130394 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 16:34:11.133532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 16:34:11.133608 ==
8967 16:34:11.136732 RX Vref Scan: 0
8968 16:34:11.136807
8969 16:34:11.139866 RX Vref 0 -> 0, step: 1
8970 16:34:11.139942
8971 16:34:11.140000 RX Delay 11 -> 252, step: 4
8972 16:34:11.146876 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8973 16:34:11.150568 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8974 16:34:11.153556 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8975 16:34:11.157178 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8976 16:34:11.160788 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8977 16:34:11.166946 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8978 16:34:11.170642 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8979 16:34:11.173922 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8980 16:34:11.176959 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8981 16:34:11.180514 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8982 16:34:11.186803 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8983 16:34:11.190571 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8984 16:34:11.193823 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8985 16:34:11.196955 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8986 16:34:11.203556 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8987 16:34:11.206596 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8988 16:34:11.206683 ==
8989 16:34:11.210403 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 16:34:11.213405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 16:34:11.213481 ==
8992 16:34:11.213540 DQS Delay:
8993 16:34:11.216472 DQS0 = 0, DQS1 = 0
8994 16:34:11.216571 DQM Delay:
8995 16:34:11.219955 DQM0 = 129, DQM1 = 125
8996 16:34:11.220031 DQ Delay:
8997 16:34:11.223244 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
8998 16:34:11.226431 DQ4 =124, DQ5 =140, DQ6 =140, DQ7 =124
8999 16:34:11.230092 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9000 16:34:11.236970 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =134
9001 16:34:11.237051
9002 16:34:11.237109
9003 16:34:11.237163
9004 16:34:11.237215 [DramC_TX_OE_Calibration] TA2
9005 16:34:11.240076 Original DQ_B0 (3 6) =30, OEN = 27
9006 16:34:11.243354 Original DQ_B1 (3 6) =30, OEN = 27
9007 16:34:11.246646 24, 0x0, End_B0=24 End_B1=24
9008 16:34:11.250307 25, 0x0, End_B0=25 End_B1=25
9009 16:34:11.253481 26, 0x0, End_B0=26 End_B1=26
9010 16:34:11.253574 27, 0x0, End_B0=27 End_B1=27
9011 16:34:11.256604 28, 0x0, End_B0=28 End_B1=28
9012 16:34:11.259687 29, 0x0, End_B0=29 End_B1=29
9013 16:34:11.263488 30, 0x0, End_B0=30 End_B1=30
9014 16:34:11.266646 31, 0x4141, End_B0=30 End_B1=30
9015 16:34:11.266750 Byte0 end_step=30 best_step=27
9016 16:34:11.269752 Byte1 end_step=30 best_step=27
9017 16:34:11.273324 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 16:34:11.276352 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 16:34:11.276468
9020 16:34:11.276566
9021 16:34:11.286613 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9022 16:34:11.286703 CH1 RK1: MR19=303, MR18=101C
9023 16:34:11.293253 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9024 16:34:11.296388 [RxdqsGatingPostProcess] freq 1600
9025 16:34:11.302815 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 16:34:11.306671 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 16:34:11.309626 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 16:34:11.313279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 16:34:11.313358 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 16:34:11.316480 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 16:34:11.319483 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 16:34:11.323075 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 16:34:11.326248 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 16:34:11.329874 Pre-setting of DQS Precalculation
9035 16:34:11.336249 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 16:34:11.343113 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 16:34:11.349334 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 16:34:11.349418
9039 16:34:11.349478
9040 16:34:11.352986 [Calibration Summary] 3200 Mbps
9041 16:34:11.353054 CH 0, Rank 0
9042 16:34:11.356194 SW Impedance : PASS
9043 16:34:11.359213 DUTY Scan : NO K
9044 16:34:11.359281 ZQ Calibration : PASS
9045 16:34:11.362439 Jitter Meter : NO K
9046 16:34:11.366220 CBT Training : PASS
9047 16:34:11.366297 Write leveling : PASS
9048 16:34:11.369362 RX DQS gating : PASS
9049 16:34:11.372639 RX DQ/DQS(RDDQC) : PASS
9050 16:34:11.372760 TX DQ/DQS : PASS
9051 16:34:11.375757 RX DATLAT : PASS
9052 16:34:11.375856 RX DQ/DQS(Engine): PASS
9053 16:34:11.379447 TX OE : PASS
9054 16:34:11.379516 All Pass.
9055 16:34:11.379574
9056 16:34:11.382640 CH 0, Rank 1
9057 16:34:11.382705 SW Impedance : PASS
9058 16:34:11.385887 DUTY Scan : NO K
9059 16:34:11.389120 ZQ Calibration : PASS
9060 16:34:11.389197 Jitter Meter : NO K
9061 16:34:11.392278 CBT Training : PASS
9062 16:34:11.396038 Write leveling : PASS
9063 16:34:11.396115 RX DQS gating : PASS
9064 16:34:11.398876 RX DQ/DQS(RDDQC) : PASS
9065 16:34:11.402415 TX DQ/DQS : PASS
9066 16:34:11.402496 RX DATLAT : PASS
9067 16:34:11.405811 RX DQ/DQS(Engine): PASS
9068 16:34:11.409267 TX OE : PASS
9069 16:34:11.409350 All Pass.
9070 16:34:11.409416
9071 16:34:11.409472 CH 1, Rank 0
9072 16:34:11.412508 SW Impedance : PASS
9073 16:34:11.415770 DUTY Scan : NO K
9074 16:34:11.415847 ZQ Calibration : PASS
9075 16:34:11.418789 Jitter Meter : NO K
9076 16:34:11.422242 CBT Training : PASS
9077 16:34:11.422353 Write leveling : PASS
9078 16:34:11.425882 RX DQS gating : PASS
9079 16:34:11.428851 RX DQ/DQS(RDDQC) : PASS
9080 16:34:11.428930 TX DQ/DQS : PASS
9081 16:34:11.432324 RX DATLAT : PASS
9082 16:34:11.432424 RX DQ/DQS(Engine): PASS
9083 16:34:11.435538 TX OE : PASS
9084 16:34:11.435638 All Pass.
9085 16:34:11.435722
9086 16:34:11.439062 CH 1, Rank 1
9087 16:34:11.439146 SW Impedance : PASS
9088 16:34:11.442245 DUTY Scan : NO K
9089 16:34:11.445323 ZQ Calibration : PASS
9090 16:34:11.445400 Jitter Meter : NO K
9091 16:34:11.449026 CBT Training : PASS
9092 16:34:11.452087 Write leveling : PASS
9093 16:34:11.452163 RX DQS gating : PASS
9094 16:34:11.455227 RX DQ/DQS(RDDQC) : PASS
9095 16:34:11.459053 TX DQ/DQS : PASS
9096 16:34:11.459129 RX DATLAT : PASS
9097 16:34:11.462323 RX DQ/DQS(Engine): PASS
9098 16:34:11.465489 TX OE : PASS
9099 16:34:11.465565 All Pass.
9100 16:34:11.465653
9101 16:34:11.465736 DramC Write-DBI on
9102 16:34:11.468562 PER_BANK_REFRESH: Hybrid Mode
9103 16:34:11.471807 TX_TRACKING: ON
9104 16:34:11.478834 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 16:34:11.488343 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 16:34:11.495205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 16:34:11.498382 [FAST_K] Save calibration result to emmc
9108 16:34:11.501451 sync common calibartion params.
9109 16:34:11.505094 sync cbt_mode0:1, 1:1
9110 16:34:11.505171 dram_init: ddr_geometry: 2
9111 16:34:11.508236 dram_init: ddr_geometry: 2
9112 16:34:11.511832 dram_init: ddr_geometry: 2
9113 16:34:11.514813 0:dram_rank_size:100000000
9114 16:34:11.514911 1:dram_rank_size:100000000
9115 16:34:11.521731 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 16:34:11.524922 DFS_SHUFFLE_HW_MODE: ON
9117 16:34:11.528030 dramc_set_vcore_voltage set vcore to 725000
9118 16:34:11.528107 Read voltage for 1600, 0
9119 16:34:11.531577 Vio18 = 0
9120 16:34:11.531654 Vcore = 725000
9121 16:34:11.531712 Vdram = 0
9122 16:34:11.535073 Vddq = 0
9123 16:34:11.535149 Vmddr = 0
9124 16:34:11.538029 switch to 3200 Mbps bootup
9125 16:34:11.538105 [DramcRunTimeConfig]
9126 16:34:11.538164 PHYPLL
9127 16:34:11.541556 DPM_CONTROL_AFTERK: ON
9128 16:34:11.544947 PER_BANK_REFRESH: ON
9129 16:34:11.548077 REFRESH_OVERHEAD_REDUCTION: ON
9130 16:34:11.548161 CMD_PICG_NEW_MODE: OFF
9131 16:34:11.551240 XRTWTW_NEW_MODE: ON
9132 16:34:11.551319 XRTRTR_NEW_MODE: ON
9133 16:34:11.554995 TX_TRACKING: ON
9134 16:34:11.555075 RDSEL_TRACKING: OFF
9135 16:34:11.558284 DQS Precalculation for DVFS: ON
9136 16:34:11.561550 RX_TRACKING: OFF
9137 16:34:11.561660 HW_GATING DBG: ON
9138 16:34:11.564957 ZQCS_ENABLE_LP4: ON
9139 16:34:11.565036 RX_PICG_NEW_MODE: ON
9140 16:34:11.568322 TX_PICG_NEW_MODE: ON
9141 16:34:11.568402 ENABLE_RX_DCM_DPHY: ON
9142 16:34:11.571446 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 16:34:11.574599 DUMMY_READ_FOR_TRACKING: OFF
9144 16:34:11.578539 !!! SPM_CONTROL_AFTERK: OFF
9145 16:34:11.581707 !!! SPM could not control APHY
9146 16:34:11.581789 IMPEDANCE_TRACKING: ON
9147 16:34:11.584778 TEMP_SENSOR: ON
9148 16:34:11.584858 HW_SAVE_FOR_SR: OFF
9149 16:34:11.587891 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 16:34:11.591717 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 16:34:11.594953 Read ODT Tracking: ON
9152 16:34:11.598144 Refresh Rate DeBounce: ON
9153 16:34:11.598245 DFS_NO_QUEUE_FLUSH: ON
9154 16:34:11.601347 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 16:34:11.604505 ENABLE_DFS_RUNTIME_MRW: OFF
9156 16:34:11.608303 DDR_RESERVE_NEW_MODE: ON
9157 16:34:11.608382 MR_CBT_SWITCH_FREQ: ON
9158 16:34:11.611500 =========================
9159 16:34:11.629929 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 16:34:11.632978 dram_init: ddr_geometry: 2
9161 16:34:11.651181 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 16:34:11.654314 dram_init: dram init end (result: 0)
9163 16:34:11.661003 DRAM-K: Full calibration passed in 24575 msecs
9164 16:34:11.664589 MRC: failed to locate region type 0.
9165 16:34:11.664709 DRAM rank0 size:0x100000000,
9166 16:34:11.667891 DRAM rank1 size=0x100000000
9167 16:34:11.677578 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 16:34:11.684439 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 16:34:11.690869 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 16:34:11.697717 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 16:34:11.700975 DRAM rank0 size:0x100000000,
9172 16:34:11.704033 DRAM rank1 size=0x100000000
9173 16:34:11.704113 CBMEM:
9174 16:34:11.707199 IMD: root @ 0xfffff000 254 entries.
9175 16:34:11.711025 IMD: root @ 0xffffec00 62 entries.
9176 16:34:11.714304 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 16:34:11.717487 WARNING: RO_VPD is uninitialized or empty.
9178 16:34:11.723785 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 16:34:11.731278 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 16:34:11.744024 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9181 16:34:11.755347 BS: romstage times (exec / console): total (unknown) / 24037 ms
9182 16:34:11.755457
9183 16:34:11.755539
9184 16:34:11.765610 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 16:34:11.768830 ARM64: Exception handlers installed.
9186 16:34:11.772371 ARM64: Testing exception
9187 16:34:11.775358 ARM64: Done test exception
9188 16:34:11.775437 Enumerating buses...
9189 16:34:11.778817 Show all devs... Before device enumeration.
9190 16:34:11.781937 Root Device: enabled 1
9191 16:34:11.785493 CPU_CLUSTER: 0: enabled 1
9192 16:34:11.785570 CPU: 00: enabled 1
9193 16:34:11.788505 Compare with tree...
9194 16:34:11.788620 Root Device: enabled 1
9195 16:34:11.792152 CPU_CLUSTER: 0: enabled 1
9196 16:34:11.795102 CPU: 00: enabled 1
9197 16:34:11.795181 Root Device scanning...
9198 16:34:11.798595 scan_static_bus for Root Device
9199 16:34:11.802028 CPU_CLUSTER: 0 enabled
9200 16:34:11.804785 scan_static_bus for Root Device done
9201 16:34:11.808359 scan_bus: bus Root Device finished in 8 msecs
9202 16:34:11.808473 done
9203 16:34:11.815423 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 16:34:11.818589 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 16:34:11.824888 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 16:34:11.828626 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 16:34:11.831902 Allocating resources...
9208 16:34:11.834970 Reading resources...
9209 16:34:11.838030 Root Device read_resources bus 0 link: 0
9210 16:34:11.838145 DRAM rank0 size:0x100000000,
9211 16:34:11.841714 DRAM rank1 size=0x100000000
9212 16:34:11.845109 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 16:34:11.848216 CPU: 00 missing read_resources
9214 16:34:11.851406 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 16:34:11.858433 Root Device read_resources bus 0 link: 0 done
9216 16:34:11.858510 Done reading resources.
9217 16:34:11.864748 Show resources in subtree (Root Device)...After reading.
9218 16:34:11.867794 Root Device child on link 0 CPU_CLUSTER: 0
9219 16:34:11.871350 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 16:34:11.881563 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 16:34:11.881650 CPU: 00
9222 16:34:11.884564 Root Device assign_resources, bus 0 link: 0
9223 16:34:11.887560 CPU_CLUSTER: 0 missing set_resources
9224 16:34:11.894491 Root Device assign_resources, bus 0 link: 0 done
9225 16:34:11.894675 Done setting resources.
9226 16:34:11.901075 Show resources in subtree (Root Device)...After assigning values.
9227 16:34:11.904565 Root Device child on link 0 CPU_CLUSTER: 0
9228 16:34:11.907715 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 16:34:11.917451 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 16:34:11.917556 CPU: 00
9231 16:34:11.921129 Done allocating resources.
9232 16:34:11.927362 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 16:34:11.927442 Enabling resources...
9234 16:34:11.927503 done.
9235 16:34:11.934295 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 16:34:11.934408 Initializing devices...
9237 16:34:11.937413 Root Device init
9238 16:34:11.940537 init hardware done!
9239 16:34:11.940632 0x00000018: ctrlr->caps
9240 16:34:11.943751 52.000 MHz: ctrlr->f_max
9241 16:34:11.947470 0.400 MHz: ctrlr->f_min
9242 16:34:11.947589 0x40ff8080: ctrlr->voltages
9243 16:34:11.950631 sclk: 390625
9244 16:34:11.950766 Bus Width = 1
9245 16:34:11.950882 sclk: 390625
9246 16:34:11.953686 Bus Width = 1
9247 16:34:11.953763 Early init status = 3
9248 16:34:11.960549 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 16:34:11.963741 in-header: 03 fc 00 00 01 00 00 00
9250 16:34:11.966869 in-data: 00
9251 16:34:11.970071 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 16:34:11.975545 in-header: 03 fd 00 00 00 00 00 00
9253 16:34:11.979289 in-data:
9254 16:34:11.982370 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 16:34:11.986738 in-header: 03 fc 00 00 01 00 00 00
9256 16:34:11.990231 in-data: 00
9257 16:34:11.992983 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 16:34:11.998673 in-header: 03 fd 00 00 00 00 00 00
9259 16:34:12.002481 in-data:
9260 16:34:12.005537 [SSUSB] Setting up USB HOST controller...
9261 16:34:12.008530 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 16:34:12.012212 [SSUSB] phy power-on done.
9263 16:34:12.015379 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 16:34:12.021742 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 16:34:12.025252 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 16:34:12.031735 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 16:34:12.038595 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 16:34:12.044910 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 16:34:12.051866 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 16:34:12.058204 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9271 16:34:12.061962 SPM: binary array size = 0x9dc
9272 16:34:12.065204 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 16:34:12.071349 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 16:34:12.078225 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 16:34:12.084977 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 16:34:12.088135 configure_display: Starting display init
9277 16:34:12.122231 anx7625_power_on_init: Init interface.
9278 16:34:12.125348 anx7625_disable_pd_protocol: Disabled PD feature.
9279 16:34:12.128490 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 16:34:12.156590 anx7625_start_dp_work: Secure OCM version=00
9281 16:34:12.159833 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 16:34:12.174964 sp_tx_get_edid_block: EDID Block = 1
9283 16:34:12.277188 Extracted contents:
9284 16:34:12.280877 header: 00 ff ff ff ff ff ff 00
9285 16:34:12.283784 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 16:34:12.287258 version: 01 04
9287 16:34:12.290629 basic params: 95 1f 11 78 0a
9288 16:34:12.293745 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 16:34:12.296954 established: 00 00 00
9290 16:34:12.303892 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 16:34:12.307123 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 16:34:12.313316 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 16:34:12.320223 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 16:34:12.326575 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 16:34:12.329808 extensions: 00
9296 16:34:12.329887 checksum: fb
9297 16:34:12.329945
9298 16:34:12.333459 Manufacturer: IVO Model 57d Serial Number 0
9299 16:34:12.336472 Made week 0 of 2020
9300 16:34:12.339841 EDID version: 1.4
9301 16:34:12.339938 Digital display
9302 16:34:12.343453 6 bits per primary color channel
9303 16:34:12.343533 DisplayPort interface
9304 16:34:12.346717 Maximum image size: 31 cm x 17 cm
9305 16:34:12.349829 Gamma: 220%
9306 16:34:12.349907 Check DPMS levels
9307 16:34:12.353050 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 16:34:12.359559 First detailed timing is preferred timing
9309 16:34:12.359647 Established timings supported:
9310 16:34:12.363282 Standard timings supported:
9311 16:34:12.366330 Detailed timings
9312 16:34:12.369900 Hex of detail: 383680a07038204018303c0035ae10000019
9313 16:34:12.375964 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 16:34:12.379880 0780 0798 07c8 0820 hborder 0
9315 16:34:12.382998 0438 043b 0447 0458 vborder 0
9316 16:34:12.386141 -hsync -vsync
9317 16:34:12.386220 Did detailed timing
9318 16:34:12.392902 Hex of detail: 000000000000000000000000000000000000
9319 16:34:12.395878 Manufacturer-specified data, tag 0
9320 16:34:12.399230 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 16:34:12.402803 ASCII string: InfoVision
9322 16:34:12.406147 Hex of detail: 000000fe00523134304e574635205248200a
9323 16:34:12.409175 ASCII string: R140NWF5 RH
9324 16:34:12.409253 Checksum
9325 16:34:12.412306 Checksum: 0xfb (valid)
9326 16:34:12.415884 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 16:34:12.418869 DSI data_rate: 832800000 bps
9328 16:34:12.425394 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 16:34:12.429285 anx7625_parse_edid: pixelclock(138800).
9330 16:34:12.432369 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 16:34:12.435398 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 16:34:12.439160 anx7625_dsi_config: config dsi.
9333 16:34:12.445241 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 16:34:12.459445 anx7625_dsi_config: success to config DSI
9335 16:34:12.462613 anx7625_dp_start: MIPI phy setup OK.
9336 16:34:12.465661 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 16:34:12.468807 mtk_ddp_mode_set invalid vrefresh 60
9338 16:34:12.472477 main_disp_path_setup
9339 16:34:12.472581 ovl_layer_smi_id_en
9340 16:34:12.475695 ovl_layer_smi_id_en
9341 16:34:12.475795 ccorr_config
9342 16:34:12.475883 aal_config
9343 16:34:12.478706 gamma_config
9344 16:34:12.478806 postmask_config
9345 16:34:12.482420 dither_config
9346 16:34:12.485926 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 16:34:12.492506 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 16:34:12.495654 Root Device init finished in 555 msecs
9349 16:34:12.498827 CPU_CLUSTER: 0 init
9350 16:34:12.505769 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 16:34:12.512245 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 16:34:12.512337 APU_MBOX 0x190000b0 = 0x10001
9353 16:34:12.515241 APU_MBOX 0x190001b0 = 0x10001
9354 16:34:12.518401 APU_MBOX 0x190005b0 = 0x10001
9355 16:34:12.521715 APU_MBOX 0x190006b0 = 0x10001
9356 16:34:12.528545 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 16:34:12.538544 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9358 16:34:12.550627 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 16:34:12.557060 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 16:34:12.568810 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9361 16:34:12.578312 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 16:34:12.581498 CPU_CLUSTER: 0 init finished in 81 msecs
9363 16:34:12.584547 Devices initialized
9364 16:34:12.587694 Show all devs... After init.
9365 16:34:12.587798 Root Device: enabled 1
9366 16:34:12.591470 CPU_CLUSTER: 0: enabled 1
9367 16:34:12.594646 CPU: 00: enabled 1
9368 16:34:12.597670 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9369 16:34:12.601269 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 16:34:12.604341 ELOG: NV offset 0x57f000 size 0x1000
9371 16:34:12.611357 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9372 16:34:12.617541 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 16:34:12.620965 ELOG: Event(17) added with size 13 at 2024-06-17 16:34:12 UTC
9374 16:34:12.627503 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 16:34:12.630581 in-header: 03 9a 00 00 2c 00 00 00
9376 16:34:12.640863 in-data: a3 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 16:34:12.647137 ELOG: Event(A1) added with size 10 at 2024-06-17 16:34:12 UTC
9378 16:34:12.654078 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9379 16:34:12.660653 ELOG: Event(A0) added with size 9 at 2024-06-17 16:34:12 UTC
9380 16:34:12.664226 elog_add_boot_reason: Logged dev mode boot
9381 16:34:12.670796 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 16:34:12.670887 Finalize devices...
9383 16:34:12.673977 Devices finalized
9384 16:34:12.677246 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 16:34:12.680387 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9386 16:34:12.683489 in-header: 03 07 00 00 08 00 00 00
9387 16:34:12.687253 in-data: aa e4 47 04 13 02 00 00
9388 16:34:12.690538 Chrome EC: UHEPI supported
9389 16:34:12.696615 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9390 16:34:12.700375 in-header: 03 a9 00 00 08 00 00 00
9391 16:34:12.703377 in-data: 84 60 60 08 00 00 00 00
9392 16:34:12.710110 ELOG: Event(91) added with size 10 at 2024-06-17 16:34:12 UTC
9393 16:34:12.713720 Chrome EC: clear events_b mask to 0x0000000020004000
9394 16:34:12.720182 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9395 16:34:12.723816 in-header: 03 fd 00 00 00 00 00 00
9396 16:34:12.723912 in-data:
9397 16:34:12.730648 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9398 16:34:12.733626 Writing coreboot table at 0xffe64000
9399 16:34:12.736880 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 16:34:12.743528 1. 0000000040000000-00000000400fffff: RAM
9401 16:34:12.746948 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 16:34:12.749905 3. 000000004032b000-00000000545fffff: RAM
9403 16:34:12.753737 4. 0000000054600000-000000005465ffff: BL31
9404 16:34:12.756783 5. 0000000054660000-00000000ffe63fff: RAM
9405 16:34:12.763822 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 16:34:12.766993 7. 0000000100000000-000000023fffffff: RAM
9407 16:34:12.770029 Passing 5 GPIOs to payload:
9408 16:34:12.773647 NAME | PORT | POLARITY | VALUE
9409 16:34:12.777049 EC in RW | 0x000000aa | low | undefined
9410 16:34:12.783267 EC interrupt | 0x00000005 | low | undefined
9411 16:34:12.786955 TPM interrupt | 0x000000ab | high | undefined
9412 16:34:12.793253 SD card detect | 0x00000011 | high | undefined
9413 16:34:12.796954 speaker enable | 0x00000093 | high | undefined
9414 16:34:12.800194 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 16:34:12.803427 in-header: 03 f9 00 00 02 00 00 00
9416 16:34:12.806569 in-data: 02 00
9417 16:34:12.806645 ADC[4]: Raw value=895930 ID=7
9418 16:34:12.809733 ADC[3]: Raw value=212700 ID=1
9419 16:34:12.813531 RAM Code: 0x71
9420 16:34:12.816636 ADC[6]: Raw value=74722 ID=0
9421 16:34:12.816739 ADC[5]: Raw value=211590 ID=1
9422 16:34:12.819890 SKU Code: 0x1
9423 16:34:12.823055 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9279
9424 16:34:12.826714 coreboot table: 964 bytes.
9425 16:34:12.829632 IMD ROOT 0. 0xfffff000 0x00001000
9426 16:34:12.833055 IMD SMALL 1. 0xffffe000 0x00001000
9427 16:34:12.836505 RO MCACHE 2. 0xffffc000 0x00001104
9428 16:34:12.839264 CONSOLE 3. 0xfff7c000 0x00080000
9429 16:34:12.842913 FMAP 4. 0xfff7b000 0x00000452
9430 16:34:12.846022 TIME STAMP 5. 0xfff7a000 0x00000910
9431 16:34:12.849339 VBOOT WORK 6. 0xfff66000 0x00014000
9432 16:34:12.852955 RAMOOPS 7. 0xffe66000 0x00100000
9433 16:34:12.855882 COREBOOT 8. 0xffe64000 0x00002000
9434 16:34:12.859474 IMD small region:
9435 16:34:12.862677 IMD ROOT 0. 0xffffec00 0x00000400
9436 16:34:12.865829 VPD 1. 0xffffeb80 0x0000006c
9437 16:34:12.869061 MMC STATUS 2. 0xffffeb60 0x00000004
9438 16:34:12.872219 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 16:34:12.878850 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9440 16:34:12.919985 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9441 16:34:12.923180 Checking segment from ROM address 0x40100000
9442 16:34:12.930129 Checking segment from ROM address 0x4010001c
9443 16:34:12.933329 Loading segment from ROM address 0x40100000
9444 16:34:12.933410 code (compression=0)
9445 16:34:12.943365 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9446 16:34:12.949770 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9447 16:34:12.949888 it's not compressed!
9448 16:34:12.956188 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9449 16:34:12.962785 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9450 16:34:12.980513 Loading segment from ROM address 0x4010001c
9451 16:34:12.980675 Entry Point 0x80000000
9452 16:34:12.984002 Loaded segments
9453 16:34:12.987197 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9454 16:34:12.993706 Jumping to boot code at 0x80000000(0xffe64000)
9455 16:34:13.000520 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9456 16:34:13.006910 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9457 16:34:13.014898 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9458 16:34:13.018017 Checking segment from ROM address 0x40100000
9459 16:34:13.021202 Checking segment from ROM address 0x4010001c
9460 16:34:13.028168 Loading segment from ROM address 0x40100000
9461 16:34:13.028286 code (compression=1)
9462 16:34:13.034647 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9463 16:34:13.044751 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9464 16:34:13.044883 using LZMA
9465 16:34:13.053654 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9466 16:34:13.060037 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9467 16:34:13.063226 Loading segment from ROM address 0x4010001c
9468 16:34:13.063306 Entry Point 0x54601000
9469 16:34:13.066414 Loaded segments
9470 16:34:13.069519 NOTICE: MT8192 bl31_setup
9471 16:34:13.077001 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9472 16:34:13.080058 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9473 16:34:13.083383 WARNING: region 0:
9474 16:34:13.087105 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 16:34:13.087183 WARNING: region 1:
9476 16:34:13.093279 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9477 16:34:13.096804 WARNING: region 2:
9478 16:34:13.100193 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9479 16:34:13.103383 WARNING: region 3:
9480 16:34:13.106553 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 16:34:13.110060 WARNING: region 4:
9482 16:34:13.116785 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 16:34:13.116896 WARNING: region 5:
9484 16:34:13.119805 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 16:34:13.123414 WARNING: region 6:
9486 16:34:13.126281 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 16:34:13.129580 WARNING: region 7:
9488 16:34:13.133273 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 16:34:13.139706 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9490 16:34:13.142879 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9491 16:34:13.149731 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9492 16:34:13.152931 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9493 16:34:13.156059 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9494 16:34:13.162920 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9495 16:34:13.166121 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9496 16:34:13.169375 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9497 16:34:13.176283 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9498 16:34:13.179444 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9499 16:34:13.185878 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9500 16:34:13.189095 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9501 16:34:13.192277 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9502 16:34:13.199314 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9503 16:34:13.202365 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9504 16:34:13.205984 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9505 16:34:13.212107 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9506 16:34:13.215736 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9507 16:34:13.222188 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9508 16:34:13.225260 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9509 16:34:13.228793 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9510 16:34:13.235490 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9511 16:34:13.238642 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9512 16:34:13.245440 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9513 16:34:13.248544 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9514 16:34:13.251600 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9515 16:34:13.258656 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9516 16:34:13.262144 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9517 16:34:13.268413 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9518 16:34:13.271570 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9519 16:34:13.278654 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9520 16:34:13.281752 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9521 16:34:13.284861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9522 16:34:13.288173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9523 16:34:13.294839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9524 16:34:13.297976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9525 16:34:13.301362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9526 16:34:13.305008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9527 16:34:13.311319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9528 16:34:13.315011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9529 16:34:13.318283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9530 16:34:13.321343 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9531 16:34:13.328138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9532 16:34:13.331373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9533 16:34:13.334512 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9534 16:34:13.337756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9535 16:34:13.344635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9536 16:34:13.347663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9537 16:34:13.351515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9538 16:34:13.357779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9539 16:34:13.360679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9540 16:34:13.367785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9541 16:34:13.370677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9542 16:34:13.377665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9543 16:34:13.380780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9544 16:34:13.387239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9545 16:34:13.390511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9546 16:34:13.393886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9547 16:34:13.400603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9548 16:34:13.403941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9549 16:34:13.410751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9550 16:34:13.413905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9551 16:34:13.420589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9552 16:34:13.423742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9553 16:34:13.430561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9554 16:34:13.433705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9555 16:34:13.436928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9556 16:34:13.443312 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9557 16:34:13.446947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9558 16:34:13.453615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9559 16:34:13.456855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9560 16:34:13.463071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9561 16:34:13.466289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9562 16:34:13.472833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9563 16:34:13.476670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9564 16:34:13.482727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9565 16:34:13.486327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9566 16:34:13.489676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9567 16:34:13.495942 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9568 16:34:13.499613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9569 16:34:13.506088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9570 16:34:13.509582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9571 16:34:13.515954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9572 16:34:13.519380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9573 16:34:13.526181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9574 16:34:13.529237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9575 16:34:13.532339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9576 16:34:13.538957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9577 16:34:13.542267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9578 16:34:13.549072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9579 16:34:13.552229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9580 16:34:13.559058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9581 16:34:13.562289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9582 16:34:13.568502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9583 16:34:13.571701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9584 16:34:13.575544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9585 16:34:13.581968 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9586 16:34:13.585097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9587 16:34:13.588260 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9588 16:34:13.594974 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9589 16:34:13.598094 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9590 16:34:13.601756 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9591 16:34:13.607832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9592 16:34:13.611695 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9593 16:34:13.618140 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9594 16:34:13.621292 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9595 16:34:13.624863 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9596 16:34:13.631193 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9597 16:34:13.634711 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9598 16:34:13.641428 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9599 16:34:13.644861 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9600 16:34:13.648008 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9601 16:34:13.654236 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9602 16:34:13.657844 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9603 16:34:13.664155 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9604 16:34:13.667979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9605 16:34:13.671160 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9606 16:34:13.674253 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9607 16:34:13.680684 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9608 16:34:13.684478 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9609 16:34:13.687783 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9610 16:34:13.694248 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9611 16:34:13.697240 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9612 16:34:13.701020 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9613 16:34:13.707109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9614 16:34:13.710543 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9615 16:34:13.714352 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9616 16:34:13.720641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9617 16:34:13.723875 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9618 16:34:13.730251 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9619 16:34:13.734122 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9620 16:34:13.737330 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9621 16:34:13.743841 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9622 16:34:13.746988 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9623 16:34:13.750749 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9624 16:34:13.757331 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9625 16:34:13.760212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9626 16:34:13.767002 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9627 16:34:13.769968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9628 16:34:13.773399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9629 16:34:13.780092 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9630 16:34:13.783651 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9631 16:34:13.789803 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9632 16:34:13.793392 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9633 16:34:13.796562 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9634 16:34:13.803308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9635 16:34:13.806470 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9636 16:34:13.813548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9637 16:34:13.816570 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9638 16:34:13.820028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9639 16:34:13.826740 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9640 16:34:13.829923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9641 16:34:13.836246 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9642 16:34:13.839315 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9643 16:34:13.843281 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9644 16:34:13.849614 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9645 16:34:13.852794 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9646 16:34:13.859359 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9647 16:34:13.862492 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9648 16:34:13.865743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9649 16:34:13.872292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9650 16:34:13.876025 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9651 16:34:13.882407 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9652 16:34:13.885835 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9653 16:34:13.889313 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9654 16:34:13.895574 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9655 16:34:13.898945 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9656 16:34:13.905687 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9657 16:34:13.908964 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9658 16:34:13.912204 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9659 16:34:13.918627 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9660 16:34:13.922242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9661 16:34:13.928823 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9662 16:34:13.932242 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9663 16:34:13.935602 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9664 16:34:13.941771 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9665 16:34:13.945583 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9666 16:34:13.951995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9667 16:34:13.955241 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9668 16:34:13.958413 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9669 16:34:13.964838 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9670 16:34:13.968553 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9671 16:34:13.975071 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9672 16:34:13.978354 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9673 16:34:13.981556 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9674 16:34:13.987815 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9675 16:34:13.991567 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9676 16:34:13.998303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9677 16:34:14.001468 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9678 16:34:14.004462 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9679 16:34:14.010977 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9680 16:34:14.014854 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9681 16:34:14.021047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9682 16:34:14.024283 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9683 16:34:14.030983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9684 16:34:14.034247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9685 16:34:14.037544 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9686 16:34:14.044216 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9687 16:34:14.047750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9688 16:34:14.054052 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9689 16:34:14.057348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9690 16:34:14.060921 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9691 16:34:14.067809 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9692 16:34:14.071013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9693 16:34:14.077455 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9694 16:34:14.080658 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9695 16:34:14.087651 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9696 16:34:14.090914 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9697 16:34:14.094086 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9698 16:34:14.100280 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9699 16:34:14.104019 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9700 16:34:14.110699 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9701 16:34:14.113711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9702 16:34:14.120556 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9703 16:34:14.123672 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9704 16:34:14.126821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9705 16:34:14.133313 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9706 16:34:14.137127 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9707 16:34:14.143506 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9708 16:34:14.146756 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9709 16:34:14.153533 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9710 16:34:14.156461 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9711 16:34:14.160121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9712 16:34:14.166489 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9713 16:34:14.170213 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9714 16:34:14.176482 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9715 16:34:14.179771 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9716 16:34:14.183219 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9717 16:34:14.189856 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9718 16:34:14.192895 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9719 16:34:14.196337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9720 16:34:14.202988 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9721 16:34:14.206032 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9722 16:34:14.209699 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9723 16:34:14.212836 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9724 16:34:14.219599 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9725 16:34:14.222710 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9726 16:34:14.229020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9727 16:34:14.232849 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9728 16:34:14.235944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9729 16:34:14.242861 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9730 16:34:14.245970 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9731 16:34:14.252428 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9732 16:34:14.255689 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9733 16:34:14.258778 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9734 16:34:14.265686 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9735 16:34:14.268916 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9736 16:34:14.272106 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9737 16:34:14.278907 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9738 16:34:14.282119 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9739 16:34:14.285840 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9740 16:34:14.292045 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9741 16:34:14.295013 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9742 16:34:14.301840 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9743 16:34:14.305142 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9744 16:34:14.308255 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9745 16:34:14.315087 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9746 16:34:14.318237 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9747 16:34:14.321388 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9748 16:34:14.327984 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9749 16:34:14.331583 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9750 16:34:14.338453 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9751 16:34:14.341693 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9752 16:34:14.344845 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9753 16:34:14.351321 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9754 16:34:14.354451 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9755 16:34:14.361300 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9756 16:34:14.364290 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9757 16:34:14.367433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9758 16:34:14.371254 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9759 16:34:14.377566 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9760 16:34:14.380577 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9761 16:34:14.384359 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9762 16:34:14.387430 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9763 16:34:14.393784 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9764 16:34:14.397648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9765 16:34:14.400848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9766 16:34:14.404026 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9767 16:34:14.410424 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9768 16:34:14.414023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9769 16:34:14.417021 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9770 16:34:14.423394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9771 16:34:14.427249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9772 16:34:14.430314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9773 16:34:14.437373 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9774 16:34:14.440082 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9775 16:34:14.447018 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9776 16:34:14.450217 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9777 16:34:14.456638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9778 16:34:14.460050 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9779 16:34:14.463407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9780 16:34:14.469916 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9781 16:34:14.473075 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9782 16:34:14.479533 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9783 16:34:14.483255 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9784 16:34:14.486323 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9785 16:34:14.492793 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9786 16:34:14.496566 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9787 16:34:14.502891 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9788 16:34:14.506062 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9789 16:34:14.509684 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9790 16:34:14.515836 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9791 16:34:14.519480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9792 16:34:14.526184 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9793 16:34:14.529344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9794 16:34:14.535633 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9795 16:34:14.538887 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9796 16:34:14.542091 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9797 16:34:14.549144 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9798 16:34:14.552197 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9799 16:34:14.558967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9800 16:34:14.561872 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9801 16:34:14.568727 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9802 16:34:14.571616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9803 16:34:14.575067 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9804 16:34:14.581732 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9805 16:34:14.585072 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9806 16:34:14.591450 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9807 16:34:14.594875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9808 16:34:14.601752 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9809 16:34:14.604933 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9810 16:34:14.608061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9811 16:34:14.615019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9812 16:34:14.618043 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9813 16:34:14.624423 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9814 16:34:14.628163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9815 16:34:14.631180 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9816 16:34:14.638139 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9817 16:34:14.641318 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9818 16:34:14.647592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9819 16:34:14.650881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9820 16:34:14.654702 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9821 16:34:14.661036 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9822 16:34:14.664156 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9823 16:34:14.670648 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9824 16:34:14.674382 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9825 16:34:14.680629 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9826 16:34:14.683838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9827 16:34:14.687582 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9828 16:34:14.693873 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9829 16:34:14.697370 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9830 16:34:14.703818 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9831 16:34:14.707229 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9832 16:34:14.713357 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9833 16:34:14.716665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9834 16:34:14.720223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9835 16:34:14.726587 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9836 16:34:14.730317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9837 16:34:14.736605 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9838 16:34:14.740192 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9839 16:34:14.743338 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9840 16:34:14.749693 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9841 16:34:14.753468 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9842 16:34:14.759787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9843 16:34:14.762867 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9844 16:34:14.769800 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9845 16:34:14.773224 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9846 16:34:14.776118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9847 16:34:14.782650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9848 16:34:14.786424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9849 16:34:14.792757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9850 16:34:14.795845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9851 16:34:14.802783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9852 16:34:14.806063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9853 16:34:14.812861 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9854 16:34:14.815914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9855 16:34:14.822245 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9856 16:34:14.825570 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9857 16:34:14.829032 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9858 16:34:14.835727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9859 16:34:14.839446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9860 16:34:14.845697 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9861 16:34:14.848751 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9862 16:34:14.855520 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9863 16:34:14.858631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9864 16:34:14.864923 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9865 16:34:14.868762 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9866 16:34:14.871960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9867 16:34:14.878224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9868 16:34:14.881928 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9869 16:34:14.888104 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9870 16:34:14.891563 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9871 16:34:14.898020 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9872 16:34:14.901914 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9873 16:34:14.908344 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9874 16:34:14.911554 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9875 16:34:14.914500 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9876 16:34:14.921520 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9877 16:34:14.924800 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9878 16:34:14.931461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9879 16:34:14.934591 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9880 16:34:14.941219 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9881 16:34:14.944729 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9882 16:34:14.947684 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9883 16:34:14.954279 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9884 16:34:14.957505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9885 16:34:14.964234 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9886 16:34:14.967478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9887 16:34:14.974005 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9888 16:34:14.977505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9889 16:34:14.984375 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9890 16:34:14.987617 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9891 16:34:14.990691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9892 16:34:14.997516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9893 16:34:15.000388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9894 16:34:15.007278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9895 16:34:15.010524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9896 16:34:15.017005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9897 16:34:15.020606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9898 16:34:15.027015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9899 16:34:15.030305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9900 16:34:15.037065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9901 16:34:15.040146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9902 16:34:15.046974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9903 16:34:15.049960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9904 16:34:15.056533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9905 16:34:15.060109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9906 16:34:15.066960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9907 16:34:15.069993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9908 16:34:15.076333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9909 16:34:15.080071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9910 16:34:15.083176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9911 16:34:15.089633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9912 16:34:15.096279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9913 16:34:15.099570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9914 16:34:15.106134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9915 16:34:15.109538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9916 16:34:15.115966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9917 16:34:15.119235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9918 16:34:15.126006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9919 16:34:15.129235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9920 16:34:15.136130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9921 16:34:15.139253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9922 16:34:15.146073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9923 16:34:15.149295 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9924 16:34:15.149373 INFO: [APUAPC] vio 0
9925 16:34:15.156621 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9926 16:34:15.160363 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9927 16:34:15.163353 INFO: [APUAPC] D0_APC_0: 0x400510
9928 16:34:15.166976 INFO: [APUAPC] D0_APC_1: 0x0
9929 16:34:15.169731 INFO: [APUAPC] D0_APC_2: 0x1540
9930 16:34:15.173374 INFO: [APUAPC] D0_APC_3: 0x0
9931 16:34:15.176574 INFO: [APUAPC] D1_APC_0: 0xffffffff
9932 16:34:15.179724 INFO: [APUAPC] D1_APC_1: 0xffffffff
9933 16:34:15.183578 INFO: [APUAPC] D1_APC_2: 0x3fffff
9934 16:34:15.186688 INFO: [APUAPC] D1_APC_3: 0x0
9935 16:34:15.189917 INFO: [APUAPC] D2_APC_0: 0xffffffff
9936 16:34:15.193179 INFO: [APUAPC] D2_APC_1: 0xffffffff
9937 16:34:15.196249 INFO: [APUAPC] D2_APC_2: 0x3fffff
9938 16:34:15.199737 INFO: [APUAPC] D2_APC_3: 0x0
9939 16:34:15.202732 INFO: [APUAPC] D3_APC_0: 0xffffffff
9940 16:34:15.206484 INFO: [APUAPC] D3_APC_1: 0xffffffff
9941 16:34:15.209688 INFO: [APUAPC] D3_APC_2: 0x3fffff
9942 16:34:15.213223 INFO: [APUAPC] D3_APC_3: 0x0
9943 16:34:15.216506 INFO: [APUAPC] D4_APC_0: 0xffffffff
9944 16:34:15.219999 INFO: [APUAPC] D4_APC_1: 0xffffffff
9945 16:34:15.222816 INFO: [APUAPC] D4_APC_2: 0x3fffff
9946 16:34:15.226451 INFO: [APUAPC] D4_APC_3: 0x0
9947 16:34:15.229483 INFO: [APUAPC] D5_APC_0: 0xffffffff
9948 16:34:15.232653 INFO: [APUAPC] D5_APC_1: 0xffffffff
9949 16:34:15.236368 INFO: [APUAPC] D5_APC_2: 0x3fffff
9950 16:34:15.236444 INFO: [APUAPC] D5_APC_3: 0x0
9951 16:34:15.242630 INFO: [APUAPC] D6_APC_0: 0xffffffff
9952 16:34:15.246297 INFO: [APUAPC] D6_APC_1: 0xffffffff
9953 16:34:15.249374 INFO: [APUAPC] D6_APC_2: 0x3fffff
9954 16:34:15.249452 INFO: [APUAPC] D6_APC_3: 0x0
9955 16:34:15.252558 INFO: [APUAPC] D7_APC_0: 0xffffffff
9956 16:34:15.255653 INFO: [APUAPC] D7_APC_1: 0xffffffff
9957 16:34:15.259395 INFO: [APUAPC] D7_APC_2: 0x3fffff
9958 16:34:15.262409 INFO: [APUAPC] D7_APC_3: 0x0
9959 16:34:15.266098 INFO: [APUAPC] D8_APC_0: 0xffffffff
9960 16:34:15.269351 INFO: [APUAPC] D8_APC_1: 0xffffffff
9961 16:34:15.272483 INFO: [APUAPC] D8_APC_2: 0x3fffff
9962 16:34:15.275932 INFO: [APUAPC] D8_APC_3: 0x0
9963 16:34:15.278755 INFO: [APUAPC] D9_APC_0: 0xffffffff
9964 16:34:15.282335 INFO: [APUAPC] D9_APC_1: 0xffffffff
9965 16:34:15.285499 INFO: [APUAPC] D9_APC_2: 0x3fffff
9966 16:34:15.288653 INFO: [APUAPC] D9_APC_3: 0x0
9967 16:34:15.291853 INFO: [APUAPC] D10_APC_0: 0xffffffff
9968 16:34:15.295686 INFO: [APUAPC] D10_APC_1: 0xffffffff
9969 16:34:15.298861 INFO: [APUAPC] D10_APC_2: 0x3fffff
9970 16:34:15.302038 INFO: [APUAPC] D10_APC_3: 0x0
9971 16:34:15.305092 INFO: [APUAPC] D11_APC_0: 0xffffffff
9972 16:34:15.308701 INFO: [APUAPC] D11_APC_1: 0xffffffff
9973 16:34:15.311821 INFO: [APUAPC] D11_APC_2: 0x3fffff
9974 16:34:15.315039 INFO: [APUAPC] D11_APC_3: 0x0
9975 16:34:15.318450 INFO: [APUAPC] D12_APC_0: 0xffffffff
9976 16:34:15.322076 INFO: [APUAPC] D12_APC_1: 0xffffffff
9977 16:34:15.325154 INFO: [APUAPC] D12_APC_2: 0x3fffff
9978 16:34:15.328759 INFO: [APUAPC] D12_APC_3: 0x0
9979 16:34:15.331636 INFO: [APUAPC] D13_APC_0: 0xffffffff
9980 16:34:15.335014 INFO: [APUAPC] D13_APC_1: 0xffffffff
9981 16:34:15.338661 INFO: [APUAPC] D13_APC_2: 0x3fffff
9982 16:34:15.341846 INFO: [APUAPC] D13_APC_3: 0x0
9983 16:34:15.345104 INFO: [APUAPC] D14_APC_0: 0xffffffff
9984 16:34:15.351982 INFO: [APUAPC] D14_APC_1: 0xffffffff
9985 16:34:15.355072 INFO: [APUAPC] D14_APC_2: 0x3fffff
9986 16:34:15.355144 INFO: [APUAPC] D14_APC_3: 0x0
9987 16:34:15.358681 INFO: [APUAPC] D15_APC_0: 0xffffffff
9988 16:34:15.364837 INFO: [APUAPC] D15_APC_1: 0xffffffff
9989 16:34:15.368468 INFO: [APUAPC] D15_APC_2: 0x3fffff
9990 16:34:15.368545 INFO: [APUAPC] D15_APC_3: 0x0
9991 16:34:15.371497 INFO: [APUAPC] APC_CON: 0x4
9992 16:34:15.375324 INFO: [NOCDAPC] D0_APC_0: 0x0
9993 16:34:15.378529 INFO: [NOCDAPC] D0_APC_1: 0x0
9994 16:34:15.381588 INFO: [NOCDAPC] D1_APC_0: 0x0
9995 16:34:15.385046 INFO: [NOCDAPC] D1_APC_1: 0xfff
9996 16:34:15.387881 INFO: [NOCDAPC] D2_APC_0: 0x0
9997 16:34:15.391644 INFO: [NOCDAPC] D2_APC_1: 0xfff
9998 16:34:15.394858 INFO: [NOCDAPC] D3_APC_0: 0x0
9999 16:34:15.398160 INFO: [NOCDAPC] D3_APC_1: 0xfff
10000 16:34:15.398238 INFO: [NOCDAPC] D4_APC_0: 0x0
10001 16:34:15.401279 INFO: [NOCDAPC] D4_APC_1: 0xfff
10002 16:34:15.404474 INFO: [NOCDAPC] D5_APC_0: 0x0
10003 16:34:15.408100 INFO: [NOCDAPC] D5_APC_1: 0xfff
10004 16:34:15.411240 INFO: [NOCDAPC] D6_APC_0: 0x0
10005 16:34:15.414875 INFO: [NOCDAPC] D6_APC_1: 0xfff
10006 16:34:15.417961 INFO: [NOCDAPC] D7_APC_0: 0x0
10007 16:34:15.421059 INFO: [NOCDAPC] D7_APC_1: 0xfff
10008 16:34:15.424355 INFO: [NOCDAPC] D8_APC_0: 0x0
10009 16:34:15.427644 INFO: [NOCDAPC] D8_APC_1: 0xfff
10010 16:34:15.431408 INFO: [NOCDAPC] D9_APC_0: 0x0
10011 16:34:15.431486 INFO: [NOCDAPC] D9_APC_1: 0xfff
10012 16:34:15.434664 INFO: [NOCDAPC] D10_APC_0: 0x0
10013 16:34:15.437949 INFO: [NOCDAPC] D10_APC_1: 0xfff
10014 16:34:15.441150 INFO: [NOCDAPC] D11_APC_0: 0x0
10015 16:34:15.444283 INFO: [NOCDAPC] D11_APC_1: 0xfff
10016 16:34:15.447838 INFO: [NOCDAPC] D12_APC_0: 0x0
10017 16:34:15.450797 INFO: [NOCDAPC] D12_APC_1: 0xfff
10018 16:34:15.454333 INFO: [NOCDAPC] D13_APC_0: 0x0
10019 16:34:15.457836 INFO: [NOCDAPC] D13_APC_1: 0xfff
10020 16:34:15.461023 INFO: [NOCDAPC] D14_APC_0: 0x0
10021 16:34:15.464275 INFO: [NOCDAPC] D14_APC_1: 0xfff
10022 16:34:15.467438 INFO: [NOCDAPC] D15_APC_0: 0x0
10023 16:34:15.471206 INFO: [NOCDAPC] D15_APC_1: 0xfff
10024 16:34:15.474288 INFO: [NOCDAPC] APC_CON: 0x4
10025 16:34:15.477445 INFO: [APUAPC] set_apusys_apc done
10026 16:34:15.480672 INFO: [DEVAPC] devapc_init done
10027 16:34:15.483837 INFO: GICv3 without legacy support detected.
10028 16:34:15.487672 INFO: ARM GICv3 driver initialized in EL3
10029 16:34:15.490687 INFO: Maximum SPI INTID supported: 639
10030 16:34:15.494162 INFO: BL31: Initializing runtime services
10031 16:34:15.500614 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10032 16:34:15.503875 INFO: SPM: enable CPC mode
10033 16:34:15.507024 INFO: mcdi ready for mcusys-off-idle and system suspend
10034 16:34:15.513939 INFO: BL31: Preparing for EL3 exit to normal world
10035 16:34:15.517173 INFO: Entry point address = 0x80000000
10036 16:34:15.520242 INFO: SPSR = 0x8
10037 16:34:15.524941
10038 16:34:15.525020
10039 16:34:15.525081
10040 16:34:15.528024 Starting depthcharge on Spherion...
10041 16:34:15.528100
10042 16:34:15.528163 Wipe memory regions:
10043 16:34:15.528220
10044 16:34:15.528868 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10045 16:34:15.528963 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10046 16:34:15.529039 Setting prompt string to ['asurada:']
10047 16:34:15.529110 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10048 16:34:15.531156 [0x00000040000000, 0x00000054600000)
10049 16:34:15.653831
10050 16:34:15.653963 [0x00000054660000, 0x00000080000000)
10051 16:34:15.914291
10052 16:34:15.914440 [0x000000821a7280, 0x000000ffe64000)
10053 16:34:16.659604
10054 16:34:16.659749 [0x00000100000000, 0x00000240000000)
10055 16:34:18.549319
10056 16:34:18.552514 Initializing XHCI USB controller at 0x11200000.
10057 16:34:19.590785
10058 16:34:19.594095 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10059 16:34:19.594500
10060 16:34:19.594809
10061 16:34:19.595492 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 16:34:19.696582 asurada: tftpboot 192.168.201.1 14396141/tftp-deploy-9j6kryo5/kernel/image.itb 14396141/tftp-deploy-9j6kryo5/kernel/cmdline
10064 16:34:19.697220 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 16:34:19.697646 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10066 16:34:19.701895 tftpboot 192.168.201.1 14396141/tftp-deploy-9j6kryo5/kernel/image.itp-deploy-9j6kryo5/kernel/cmdline
10067 16:34:19.702301
10068 16:34:19.702603 Waiting for link
10069 16:34:19.860115
10070 16:34:19.860605 R8152: Initializing
10071 16:34:19.861116
10072 16:34:19.863328 Version 6 (ocp_data = 5c30)
10073 16:34:19.863681
10074 16:34:19.866532 R8152: Done initializing
10075 16:34:19.866885
10076 16:34:19.867258 Adding net device
10077 16:34:21.770351
10078 16:34:21.770499 done.
10079 16:34:21.770591
10080 16:34:21.770675 MAC: 00:24:32:30:78:ff
10081 16:34:21.770770
10082 16:34:21.773626 Sending DHCP discover... done.
10083 16:34:21.773714
10084 16:34:21.776864 Waiting for reply... done.
10085 16:34:21.776942
10086 16:34:21.780030 Sending DHCP request... done.
10087 16:34:21.780122
10088 16:34:22.078353 Waiting for reply... done.
10089 16:34:22.078482
10090 16:34:22.078545 My ip is 192.168.201.21
10091 16:34:22.078600
10092 16:34:22.081670 The DHCP server ip is 192.168.201.1
10093 16:34:22.081746
10094 16:34:22.088525 TFTP server IP predefined by user: 192.168.201.1
10095 16:34:22.088676
10096 16:34:22.095224 Bootfile predefined by user: 14396141/tftp-deploy-9j6kryo5/kernel/image.itb
10097 16:34:22.095353
10098 16:34:22.097884 Sending tftp read request... done.
10099 16:34:22.097967
10100 16:34:22.101853 Waiting for the transfer...
10101 16:34:22.101924
10102 16:34:22.819502 00000000 ################################################################
10103 16:34:22.819658
10104 16:34:23.142781 00080000 ################################################################
10105 16:34:23.142910
10106 16:34:23.664515 00100000 ################################################################
10107 16:34:23.664656
10108 16:34:24.196349 00180000 ################################################################
10109 16:34:24.196481
10110 16:34:24.721865 00200000 ################################################################
10111 16:34:24.722009
10112 16:34:25.254081 00280000 ################################################################
10113 16:34:25.254230
10114 16:34:25.794424 00300000 ################################################################
10115 16:34:25.794547
10116 16:34:26.327302 00380000 ################################################################
10117 16:34:26.327422
10118 16:34:26.849033 00400000 ################################################################
10119 16:34:26.849149
10120 16:34:27.378935 00480000 ################################################################
10121 16:34:27.379051
10122 16:34:27.932823 00500000 ################################################################
10123 16:34:27.932937
10124 16:34:28.451612 00580000 ################################################################
10125 16:34:28.451727
10126 16:34:28.968548 00600000 ################################################################
10127 16:34:28.968718
10128 16:34:29.495144 00680000 ################################################################
10129 16:34:29.495264
10130 16:34:30.027200 00700000 ################################################################
10131 16:34:30.027334
10132 16:34:30.576800 00780000 ################################################################
10133 16:34:30.576935
10134 16:34:31.131501 00800000 ################################################################
10135 16:34:31.131641
10136 16:34:31.695521 00880000 ################################################################
10137 16:34:31.695632
10138 16:34:32.279253 00900000 ################################################################
10139 16:34:32.279367
10140 16:34:32.872395 00980000 ################################################################
10141 16:34:32.872524
10142 16:34:33.434975 00a00000 ################################################################
10143 16:34:33.435116
10144 16:34:34.002446 00a80000 ################################################################
10145 16:34:34.002561
10146 16:34:34.539398 00b00000 ################################################################
10147 16:34:34.539539
10148 16:34:35.074663 00b80000 ################################################################
10149 16:34:35.074781
10150 16:34:35.612548 00c00000 ################################################################
10151 16:34:35.612725
10152 16:34:36.143132 00c80000 ################################################################
10153 16:34:36.143244
10154 16:34:36.681812 00d00000 ################################################################
10155 16:34:36.681929
10156 16:34:37.207168 00d80000 ################################################################
10157 16:34:37.207293
10158 16:34:37.751605 00e00000 ################################################################
10159 16:34:37.751733
10160 16:34:38.287282 00e80000 ################################################################
10161 16:34:38.287408
10162 16:34:38.831405 00f00000 ################################################################
10163 16:34:38.831525
10164 16:34:39.374906 00f80000 ################################################################
10165 16:34:39.375021
10166 16:34:39.900453 01000000 ################################################################
10167 16:34:39.900598
10168 16:34:40.430712 01080000 ################################################################
10169 16:34:40.430826
10170 16:34:40.952573 01100000 ################################################################
10171 16:34:40.952740
10172 16:34:41.501133 01180000 ################################################################
10173 16:34:41.501260
10174 16:34:42.030818 01200000 ################################################################
10175 16:34:42.030942
10176 16:34:42.567509 01280000 ################################################################
10177 16:34:42.567629
10178 16:34:43.089056 01300000 ################################################################
10179 16:34:43.089174
10180 16:34:43.609569 01380000 ################################################################
10181 16:34:43.609713
10182 16:34:44.123181 01400000 ################################################################
10183 16:34:44.123350
10184 16:34:44.651219 01480000 ################################################################
10185 16:34:44.651375
10186 16:34:45.182267 01500000 ################################################################
10187 16:34:45.182395
10188 16:34:45.708560 01580000 ################################################################
10189 16:34:45.708708
10190 16:34:46.238559 01600000 ################################################################
10191 16:34:46.238680
10192 16:34:46.761153 01680000 ################################################################
10193 16:34:46.761283
10194 16:34:47.295129 01700000 ################################################################
10195 16:34:47.295287
10196 16:34:47.827084 01780000 ################################################################
10197 16:34:47.827242
10198 16:34:48.363118 01800000 ################################################################
10199 16:34:48.363242
10200 16:34:48.886336 01880000 ################################################################
10201 16:34:48.886461
10202 16:34:49.403392 01900000 ################################################################
10203 16:34:49.403507
10204 16:34:49.921609 01980000 ################################################################
10205 16:34:49.921750
10206 16:34:50.442760 01a00000 ################################################################
10207 16:34:50.442919
10208 16:34:50.956970 01a80000 ################################################################
10209 16:34:50.957101
10210 16:34:51.472242 01b00000 ################################################################
10211 16:34:51.472394
10212 16:34:52.005064 01b80000 ################################################################
10213 16:34:52.005293
10214 16:34:52.531472 01c00000 ################################################################
10215 16:34:52.531597
10216 16:34:53.055839 01c80000 ################################################################
10217 16:34:53.055959
10218 16:34:53.571965 01d00000 ################################################################
10219 16:34:53.572101
10220 16:34:54.089840 01d80000 ################################################################
10221 16:34:54.089964
10222 16:34:54.667811 01e00000 ################################################################
10223 16:34:54.667970
10224 16:34:55.251053 01e80000 ################################################################
10225 16:34:55.251193
10226 16:34:55.774978 01f00000 ################################################################
10227 16:34:55.775102
10228 16:34:56.290245 01f80000 ################################################################
10229 16:34:56.290360
10230 16:34:56.823338 02000000 ################################################################
10231 16:34:56.823476
10232 16:34:57.336307 02080000 ################################################################
10233 16:34:57.336434
10234 16:34:57.860010 02100000 ################################################################
10235 16:34:57.860174
10236 16:34:58.399843 02180000 ################################################################
10237 16:34:58.399995
10238 16:34:58.938542 02200000 ################################################################
10239 16:34:58.938670
10240 16:34:59.527366 02280000 ################################################################
10241 16:34:59.527509
10242 16:35:00.077375 02300000 ################################################################
10243 16:35:00.077505
10244 16:35:00.597368 02380000 ################################################################
10245 16:35:00.597508
10246 16:35:01.130923 02400000 ################################################################
10247 16:35:01.131070
10248 16:35:01.662073 02480000 ################################################################
10249 16:35:01.662225
10250 16:35:02.207584 02500000 ################################################################
10251 16:35:02.207701
10252 16:35:02.734070 02580000 ################################################################
10253 16:35:02.734187
10254 16:35:03.263569 02600000 ################################################################
10255 16:35:03.263686
10256 16:35:03.803442 02680000 ################################################################
10257 16:35:03.803564
10258 16:35:04.343102 02700000 ################################################################
10259 16:35:04.343224
10260 16:35:04.879432 02780000 ################################################################
10261 16:35:04.879572
10262 16:35:05.420442 02800000 ################################################################
10263 16:35:05.420581
10264 16:35:05.986497 02880000 ################################################################
10265 16:35:05.986648
10266 16:35:06.567108 02900000 ################################################################
10267 16:35:06.567236
10268 16:35:07.142659 02980000 ################################################################
10269 16:35:07.142800
10270 16:35:07.736664 02a00000 ################################################################
10271 16:35:07.736810
10272 16:35:08.332465 02a80000 ################################################################
10273 16:35:08.332613
10274 16:35:08.928017 02b00000 ################################################################
10275 16:35:08.928136
10276 16:35:09.485094 02b80000 ################################################################
10277 16:35:09.485224
10278 16:35:10.048935 02c00000 ################################################################
10279 16:35:10.049057
10280 16:35:10.624446 02c80000 ################################################################
10281 16:35:10.624583
10282 16:35:11.173957 02d00000 ################################################################
10283 16:35:11.174107
10284 16:35:11.721265 02d80000 ################################################################
10285 16:35:11.721392
10286 16:35:12.271288 02e00000 ################################################################
10287 16:35:12.271457
10288 16:35:12.801519 02e80000 ################################################################
10289 16:35:12.801655
10290 16:35:13.342867 02f00000 ################################################################
10291 16:35:13.342997
10292 16:35:13.912064 02f80000 ################################################################
10293 16:35:13.912196
10294 16:35:14.483325 03000000 ################################################################
10295 16:35:14.483458
10296 16:35:15.052828 03080000 ################################################################
10297 16:35:15.052987
10298 16:35:15.600515 03100000 ################################################################
10299 16:35:15.600692
10300 16:35:16.151949 03180000 ################################################################
10301 16:35:16.152061
10302 16:35:16.693315 03200000 ################################################################
10303 16:35:16.693473
10304 16:35:17.237290 03280000 ################################################################
10305 16:35:17.237419
10306 16:35:17.801930 03300000 ################################################################
10307 16:35:17.802050
10308 16:35:18.345150 03380000 ################################################################
10309 16:35:18.345276
10310 16:35:18.876962 03400000 ################################################################
10311 16:35:18.877093
10312 16:35:19.412536 03480000 ################################################################
10313 16:35:19.412696
10314 16:35:19.954720 03500000 ################################################################
10315 16:35:19.954836
10316 16:35:20.525223 03580000 ################################################################
10317 16:35:20.525346
10318 16:35:21.070037 03600000 ################################################################
10319 16:35:21.070157
10320 16:35:21.627422 03680000 ################################################################
10321 16:35:21.627556
10322 16:35:22.175264 03700000 ################################################################
10323 16:35:22.175417
10324 16:35:22.703885 03780000 ################################################################
10325 16:35:22.704010
10326 16:35:23.244568 03800000 ################################################################
10327 16:35:23.244713
10328 16:35:23.785658 03880000 ################################################################
10329 16:35:23.785778
10330 16:35:24.328931 03900000 ################################################################
10331 16:35:24.329086
10332 16:35:24.864986 03980000 ################################################################
10333 16:35:24.865104
10334 16:35:25.415025 03a00000 ################################################################
10335 16:35:25.415141
10336 16:35:25.963873 03a80000 ################################################################
10337 16:35:25.964008
10338 16:35:26.516830 03b00000 ################################################################
10339 16:35:26.516960
10340 16:35:27.046977 03b80000 ################################################################
10341 16:35:27.047146
10342 16:35:27.573522 03c00000 ################################################################
10343 16:35:27.573663
10344 16:35:28.099250 03c80000 ################################################################
10345 16:35:28.099421
10346 16:35:28.623057 03d00000 ################################################################
10347 16:35:28.623182
10348 16:35:29.149127 03d80000 ################################################################
10349 16:35:29.149265
10350 16:35:29.673364 03e00000 ################################################################
10351 16:35:29.673532
10352 16:35:30.211574 03e80000 ################################################################
10353 16:35:30.211759
10354 16:35:30.759318 03f00000 ################################################################
10355 16:35:30.759467
10356 16:35:31.306668 03f80000 ################################################################
10357 16:35:31.306800
10358 16:35:31.843275 04000000 ################################################################
10359 16:35:31.843421
10360 16:35:32.432518 04080000 ################################################################
10361 16:35:32.432671
10362 16:35:33.038816 04100000 ################################################################
10363 16:35:33.038990
10364 16:35:33.578169 04180000 ################################################################
10365 16:35:33.578321
10366 16:35:34.141851 04200000 ################################################################
10367 16:35:34.141972
10368 16:35:34.801222 04280000 ################################################################
10369 16:35:34.801682
10370 16:35:35.360690 04300000 ################################################################
10371 16:35:35.360806
10372 16:35:35.929760 04380000 ################################################################
10373 16:35:35.929884
10374 16:35:36.503751 04400000 ################################################################
10375 16:35:36.504041
10376 16:35:37.176542 04480000 ################################################################
10377 16:35:37.177050
10378 16:35:37.836305 04500000 ################################################################
10379 16:35:37.836928
10380 16:35:38.524559 04580000 ################################################################
10381 16:35:38.525101
10382 16:35:39.086391 04600000 ################################################################
10383 16:35:39.086506
10384 16:35:39.386411 04680000 ################################## done.
10385 16:35:39.386525
10386 16:35:39.389472 The bootfile was 74201710 bytes long.
10387 16:35:39.389555
10388 16:35:39.392618 Sending tftp read request... done.
10389 16:35:39.392718
10390 16:35:39.392786 Waiting for the transfer...
10391 16:35:39.392849
10392 16:35:39.395742 00000000 # done.
10393 16:35:39.395831
10394 16:35:39.403095 Command line loaded dynamically from TFTP file: 14396141/tftp-deploy-9j6kryo5/kernel/cmdline
10395 16:35:39.403525
10396 16:35:39.416172 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10397 16:35:39.416614
10398 16:35:39.419476 Loading FIT.
10399 16:35:39.420031
10400 16:35:39.423010 Image ramdisk-1 has 61023671 bytes.
10401 16:35:39.423432
10402 16:35:39.423754 Image fdt-1 has 47258 bytes.
10403 16:35:39.426011
10404 16:35:39.426433 Image kernel-1 has 13128753 bytes.
10405 16:35:39.426763
10406 16:35:39.435998 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10407 16:35:39.436554
10408 16:35:39.452974 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10409 16:35:39.456084
10410 16:35:39.459335 Choosing best match conf-1 for compat google,spherion-rev2.
10411 16:35:39.463585
10412 16:35:39.468681 Connected to device vid:did:rid of 1ae0:0028:00
10413 16:35:39.476216
10414 16:35:39.479485 tpm_get_response: command 0x17b, return code 0x0
10415 16:35:39.479911
10416 16:35:39.482698 ec_init: CrosEC protocol v3 supported (256, 248)
10417 16:35:39.486874
10418 16:35:39.489973 tpm_cleanup: add release locality here.
10419 16:35:39.490421
10420 16:35:39.490755 Shutting down all USB controllers.
10421 16:35:39.493538
10422 16:35:39.494090 Removing current net device
10423 16:35:39.494442
10424 16:35:39.500391 Exiting depthcharge with code 4 at timestamp: 113323667
10425 16:35:39.500959
10426 16:35:39.503525 LZMA decompressing kernel-1 to 0x821a6718
10427 16:35:39.503999
10428 16:35:39.506590 LZMA decompressing kernel-1 to 0x40000000
10429 16:35:41.124016
10430 16:35:41.124448 jumping to kernel
10431 16:35:41.126448 end: 2.2.4 bootloader-commands (duration 00:01:26) [common]
10432 16:35:41.126914 start: 2.2.5 auto-login-action (timeout 00:03:01) [common]
10433 16:35:41.127247 Setting prompt string to ['Linux version [0-9]']
10434 16:35:41.127569 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10435 16:35:41.127878 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10436 16:35:41.205633
10437 16:35:41.209172 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10438 16:35:41.213256 start: 2.2.5.1 login-action (timeout 00:03:01) [common]
10439 16:35:41.213692 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10440 16:35:41.214067 Setting prompt string to []
10441 16:35:41.214450 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10442 16:35:41.214781 Using line separator: #'\n'#
10443 16:35:41.215066 No login prompt set.
10444 16:35:41.215351 Parsing kernel messages
10445 16:35:41.215609 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10446 16:35:41.216173 [login-action] Waiting for messages, (timeout 00:03:01)
10447 16:35:41.216500 Waiting using forced prompt support (timeout 00:01:31)
10448 16:35:41.231994 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10449 16:35:41.235773 [ 0.000000] random: crng init done
10450 16:35:41.242592 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10451 16:35:41.245809 [ 0.000000] efi: UEFI not found.
10452 16:35:41.252305 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10453 16:35:41.259171 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10454 16:35:41.269007 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10455 16:35:41.278575 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10456 16:35:41.284993 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10457 16:35:41.292038 [ 0.000000] printk: bootconsole [mtk8250] enabled
10458 16:35:41.298428 [ 0.000000] NUMA: No NUMA configuration found
10459 16:35:41.305345 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10460 16:35:41.308617 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10461 16:35:41.311871 [ 0.000000] Zone ranges:
10462 16:35:41.318481 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10463 16:35:41.321239 [ 0.000000] DMA32 empty
10464 16:35:41.328237 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10465 16:35:41.331309 [ 0.000000] Movable zone start for each node
10466 16:35:41.334825 [ 0.000000] Early memory node ranges
10467 16:35:41.341659 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10468 16:35:41.347836 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10469 16:35:41.354756 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10470 16:35:41.361301 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10471 16:35:41.367600 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10472 16:35:41.374292 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10473 16:35:41.430528 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10474 16:35:41.436786 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10475 16:35:41.444032 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10476 16:35:41.447430 [ 0.000000] psci: probing for conduit method from DT.
10477 16:35:41.453527 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10478 16:35:41.457106 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10479 16:35:41.463564 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10480 16:35:41.466799 [ 0.000000] psci: SMC Calling Convention v1.2
10481 16:35:41.473688 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10482 16:35:41.476720 [ 0.000000] Detected VIPT I-cache on CPU0
10483 16:35:41.483729 [ 0.000000] CPU features: detected: GIC system register CPU interface
10484 16:35:41.489895 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10485 16:35:41.496712 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10486 16:35:41.503063 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10487 16:35:41.513264 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10488 16:35:41.519606 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10489 16:35:41.523294 [ 0.000000] alternatives: applying boot alternatives
10490 16:35:41.529696 [ 0.000000] Fallback order for Node 0: 0
10491 16:35:41.536681 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10492 16:35:41.539798 [ 0.000000] Policy zone: Normal
10493 16:35:41.553037 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10494 16:35:41.563170 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10495 16:35:41.574942 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10496 16:35:41.584786 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10497 16:35:41.591248 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10498 16:35:41.594479 <6>[ 0.000000] software IO TLB: area num 8.
10499 16:35:41.650881 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10500 16:35:41.800678 <6>[ 0.000000] Memory: 7904464K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448304K reserved, 32768K cma-reserved)
10501 16:35:41.807092 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10502 16:35:41.813294 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10503 16:35:41.816993 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10504 16:35:41.823714 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10505 16:35:41.829888 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10506 16:35:41.833691 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10507 16:35:41.843685 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10508 16:35:41.850035 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10509 16:35:41.853512 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10510 16:35:41.861521 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10511 16:35:41.864615 <6>[ 0.000000] GICv3: 608 SPIs implemented
10512 16:35:41.871231 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10513 16:35:41.874252 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10514 16:35:41.878052 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10515 16:35:41.887799 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10516 16:35:41.897870 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10517 16:35:41.910443 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10518 16:35:41.916866 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10519 16:35:41.926195 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10520 16:35:41.939545 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10521 16:35:41.946590 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10522 16:35:41.953188 <6>[ 0.009231] Console: colour dummy device 80x25
10523 16:35:41.962599 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10524 16:35:41.969652 <6>[ 0.024400] pid_max: default: 32768 minimum: 301
10525 16:35:41.972842 <6>[ 0.029270] LSM: Security Framework initializing
10526 16:35:41.979506 <6>[ 0.034240] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10527 16:35:41.989939 <6>[ 0.042054] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10528 16:35:41.999488 <6>[ 0.051525] cblist_init_generic: Setting adjustable number of callback queues.
10529 16:35:42.003119 <6>[ 0.058968] cblist_init_generic: Setting shift to 3 and lim to 1.
10530 16:35:42.012923 <6>[ 0.065307] cblist_init_generic: Setting adjustable number of callback queues.
10531 16:35:42.019505 <6>[ 0.072734] cblist_init_generic: Setting shift to 3 and lim to 1.
10532 16:35:42.023046 <6>[ 0.079134] rcu: Hierarchical SRCU implementation.
10533 16:35:42.029550 <6>[ 0.084149] rcu: Max phase no-delay instances is 1000.
10534 16:35:42.035889 <6>[ 0.091177] EFI services will not be available.
10535 16:35:42.039059 <6>[ 0.096135] smp: Bringing up secondary CPUs ...
10536 16:35:42.047822 <6>[ 0.101186] Detected VIPT I-cache on CPU1
10537 16:35:42.054889 <6>[ 0.101259] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10538 16:35:42.060862 <6>[ 0.101289] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10539 16:35:42.063870 <6>[ 0.101622] Detected VIPT I-cache on CPU2
10540 16:35:42.070641 <6>[ 0.101672] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10541 16:35:42.080561 <6>[ 0.101689] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10542 16:35:42.083699 <6>[ 0.101948] Detected VIPT I-cache on CPU3
10543 16:35:42.090536 <6>[ 0.101995] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10544 16:35:42.097458 <6>[ 0.102009] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10545 16:35:42.100634 <6>[ 0.102311] CPU features: detected: Spectre-v4
10546 16:35:42.107077 <6>[ 0.102317] CPU features: detected: Spectre-BHB
10547 16:35:42.110325 <6>[ 0.102322] Detected PIPT I-cache on CPU4
10548 16:35:42.117019 <6>[ 0.102381] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10549 16:35:42.123975 <6>[ 0.102397] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10550 16:35:42.130301 <6>[ 0.102691] Detected PIPT I-cache on CPU5
10551 16:35:42.137087 <6>[ 0.102753] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10552 16:35:42.143319 <6>[ 0.102769] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10553 16:35:42.147172 <6>[ 0.103053] Detected PIPT I-cache on CPU6
10554 16:35:42.153257 <6>[ 0.103117] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10555 16:35:42.160174 <6>[ 0.103134] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10556 16:35:42.166857 <6>[ 0.103430] Detected PIPT I-cache on CPU7
10557 16:35:42.173562 <6>[ 0.103496] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10558 16:35:42.180029 <6>[ 0.103512] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10559 16:35:42.183268 <6>[ 0.103559] smp: Brought up 1 node, 8 CPUs
10560 16:35:42.189724 <6>[ 0.244857] SMP: Total of 8 processors activated.
10561 16:35:42.193325 <6>[ 0.249778] CPU features: detected: 32-bit EL0 Support
10562 16:35:42.202889 <6>[ 0.255142] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10563 16:35:42.209843 <6>[ 0.263942] CPU features: detected: Common not Private translations
10564 16:35:42.216324 <6>[ 0.270418] CPU features: detected: CRC32 instructions
10565 16:35:42.219967 <6>[ 0.275769] CPU features: detected: RCpc load-acquire (LDAPR)
10566 16:35:42.226230 <6>[ 0.281729] CPU features: detected: LSE atomic instructions
10567 16:35:42.232689 <6>[ 0.287511] CPU features: detected: Privileged Access Never
10568 16:35:42.239078 <6>[ 0.293291] CPU features: detected: RAS Extension Support
10569 16:35:42.245920 <6>[ 0.298900] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10570 16:35:42.249675 <6>[ 0.306117] CPU: All CPU(s) started at EL2
10571 16:35:42.256070 <6>[ 0.310433] alternatives: applying system-wide alternatives
10572 16:35:42.265156 <6>[ 0.321310] devtmpfs: initialized
10573 16:35:42.277647 <6>[ 0.330168] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10574 16:35:42.287402 <6>[ 0.340129] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10575 16:35:42.294401 <6>[ 0.348071] pinctrl core: initialized pinctrl subsystem
10576 16:35:42.297583 <6>[ 0.354756] DMI not present or invalid.
10577 16:35:42.304329 <6>[ 0.359170] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10578 16:35:42.313907 <6>[ 0.366029] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10579 16:35:42.320682 <6>[ 0.373617] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10580 16:35:42.330293 <6>[ 0.381835] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10581 16:35:42.333877 <6>[ 0.390077] audit: initializing netlink subsys (disabled)
10582 16:35:42.343772 <5>[ 0.395771] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10583 16:35:42.349885 <6>[ 0.396488] thermal_sys: Registered thermal governor 'step_wise'
10584 16:35:42.356750 <6>[ 0.403737] thermal_sys: Registered thermal governor 'power_allocator'
10585 16:35:42.359866 <6>[ 0.409993] cpuidle: using governor menu
10586 16:35:42.366918 <6>[ 0.420954] NET: Registered PF_QIPCRTR protocol family
10587 16:35:42.373185 <6>[ 0.426434] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10588 16:35:42.380031 <6>[ 0.433535] ASID allocator initialised with 32768 entries
10589 16:35:42.383347 <6>[ 0.440116] Serial: AMBA PL011 UART driver
10590 16:35:42.392906 <4>[ 0.448948] Trying to register duplicate clock ID: 134
10591 16:35:42.451416 <6>[ 0.510526] KASLR enabled
10592 16:35:42.465914 <6>[ 0.518226] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10593 16:35:42.471894 <6>[ 0.525240] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10594 16:35:42.478881 <6>[ 0.531729] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10595 16:35:42.485110 <6>[ 0.538734] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10596 16:35:42.491944 <6>[ 0.545223] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10597 16:35:42.498395 <6>[ 0.552227] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10598 16:35:42.505121 <6>[ 0.558712] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10599 16:35:42.511485 <6>[ 0.565717] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10600 16:35:42.515496 <6>[ 0.573240] ACPI: Interpreter disabled.
10601 16:35:42.523483 <6>[ 0.579657] iommu: Default domain type: Translated
10602 16:35:42.530176 <6>[ 0.584770] iommu: DMA domain TLB invalidation policy: strict mode
10603 16:35:42.533597 <5>[ 0.591434] SCSI subsystem initialized
10604 16:35:42.539943 <6>[ 0.595601] usbcore: registered new interface driver usbfs
10605 16:35:42.546790 <6>[ 0.601331] usbcore: registered new interface driver hub
10606 16:35:42.550054 <6>[ 0.606882] usbcore: registered new device driver usb
10607 16:35:42.557212 <6>[ 0.612983] pps_core: LinuxPPS API ver. 1 registered
10608 16:35:42.567186 <6>[ 0.618177] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10609 16:35:42.570198 <6>[ 0.627522] PTP clock support registered
10610 16:35:42.573447 <6>[ 0.631765] EDAC MC: Ver: 3.0.0
10611 16:35:42.580853 <6>[ 0.636909] FPGA manager framework
10612 16:35:42.587637 <6>[ 0.640593] Advanced Linux Sound Architecture Driver Initialized.
10613 16:35:42.590822 <6>[ 0.647370] vgaarb: loaded
10614 16:35:42.597187 <6>[ 0.650525] clocksource: Switched to clocksource arch_sys_counter
10615 16:35:42.600733 <5>[ 0.656964] VFS: Disk quotas dquot_6.6.0
10616 16:35:42.606876 <6>[ 0.661151] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10617 16:35:42.610042 <6>[ 0.668342] pnp: PnP ACPI: disabled
10618 16:35:42.619228 <6>[ 0.675081] NET: Registered PF_INET protocol family
10619 16:35:42.628942 <6>[ 0.680675] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10620 16:35:42.639950 <6>[ 0.693000] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10621 16:35:42.649983 <6>[ 0.701813] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10622 16:35:42.656633 <6>[ 0.709785] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10623 16:35:42.666510 <6>[ 0.718483] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10624 16:35:42.672927 <6>[ 0.728235] TCP: Hash tables configured (established 65536 bind 65536)
10625 16:35:42.679811 <6>[ 0.735100] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10626 16:35:42.689589 <6>[ 0.742298] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10627 16:35:42.695876 <6>[ 0.750003] NET: Registered PF_UNIX/PF_LOCAL protocol family
10628 16:35:42.702759 <6>[ 0.756158] RPC: Registered named UNIX socket transport module.
10629 16:35:42.705916 <6>[ 0.762310] RPC: Registered udp transport module.
10630 16:35:42.713088 <6>[ 0.767243] RPC: Registered tcp transport module.
10631 16:35:42.719440 <6>[ 0.772175] RPC: Registered tcp NFSv4.1 backchannel transport module.
10632 16:35:42.722422 <6>[ 0.778843] PCI: CLS 0 bytes, default 64
10633 16:35:42.725776 <6>[ 0.783166] Unpacking initramfs...
10634 16:35:42.741621 <6>[ 0.795053] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10635 16:35:42.751691 <6>[ 0.803698] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10636 16:35:42.755378 <6>[ 0.812534] kvm [1]: IPA Size Limit: 40 bits
10637 16:35:42.761425 <6>[ 0.817061] kvm [1]: GICv3: no GICV resource entry
10638 16:35:42.765098 <6>[ 0.822082] kvm [1]: disabling GICv2 emulation
10639 16:35:42.771793 <6>[ 0.826771] kvm [1]: GIC system register CPU interface enabled
10640 16:35:42.778095 <6>[ 0.834539] kvm [1]: vgic interrupt IRQ18
10641 16:35:42.781544 <6>[ 0.838929] kvm [1]: VHE mode initialized successfully
10642 16:35:42.789400 <5>[ 0.845430] Initialise system trusted keyrings
10643 16:35:42.795945 <6>[ 0.850223] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10644 16:35:42.804421 <6>[ 0.860474] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10645 16:35:42.810677 <5>[ 0.866866] NFS: Registering the id_resolver key type
10646 16:35:42.813815 <5>[ 0.872166] Key type id_resolver registered
10647 16:35:42.820683 <5>[ 0.876581] Key type id_legacy registered
10648 16:35:42.827476 <6>[ 0.880861] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10649 16:35:42.834106 <6>[ 0.887784] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10650 16:35:42.840298 <6>[ 0.895488] 9p: Installing v9fs 9p2000 file system support
10651 16:35:42.877759 <5>[ 0.933983] Key type asymmetric registered
10652 16:35:42.880867 <5>[ 0.938314] Asymmetric key parser 'x509' registered
10653 16:35:42.890791 <6>[ 0.943457] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10654 16:35:42.894294 <6>[ 0.951071] io scheduler mq-deadline registered
10655 16:35:42.897201 <6>[ 0.955832] io scheduler kyber registered
10656 16:35:42.916083 <6>[ 0.972793] EINJ: ACPI disabled.
10657 16:35:42.949511 <4>[ 0.999080] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 16:35:42.959594 <4>[ 1.009715] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 16:35:42.974420 <6>[ 1.030574] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10660 16:35:42.981952 <6>[ 1.038563] printk: console [ttyS0] disabled
10661 16:35:43.010216 <6>[ 1.063221] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10662 16:35:43.016842 <6>[ 1.072698] printk: console [ttyS0] enabled
10663 16:35:43.020012 <6>[ 1.072698] printk: console [ttyS0] enabled
10664 16:35:43.026896 <6>[ 1.081594] printk: bootconsole [mtk8250] disabled
10665 16:35:43.029972 <6>[ 1.081594] printk: bootconsole [mtk8250] disabled
10666 16:35:43.036876 <6>[ 1.092872] SuperH (H)SCI(F) driver initialized
10667 16:35:43.040055 <6>[ 1.098160] msm_serial: driver initialized
10668 16:35:43.054704 <6>[ 1.107173] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10669 16:35:43.064315 <6>[ 1.115724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10670 16:35:43.071074 <6>[ 1.124274] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10671 16:35:43.081174 <6>[ 1.132904] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10672 16:35:43.090930 <6>[ 1.141613] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10673 16:35:43.097584 <6>[ 1.150328] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10674 16:35:43.107500 <6>[ 1.158868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10675 16:35:43.114007 <6>[ 1.167673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10676 16:35:43.123850 <6>[ 1.176216] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10677 16:35:43.136168 <6>[ 1.191905] loop: module loaded
10678 16:35:43.142530 <6>[ 1.197883] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10679 16:35:43.165338 <4>[ 1.221474] mtk-pmic-keys: Failed to locate of_node [id: -1]
10680 16:35:43.172210 <6>[ 1.228476] megasas: 07.719.03.00-rc1
10681 16:35:43.182101 <6>[ 1.238118] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10682 16:35:43.193877 <6>[ 1.249896] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10683 16:35:43.210651 <6>[ 1.266563] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10684 16:35:43.266976 <6>[ 1.316399] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10685 16:35:45.427543 <6>[ 3.484617] Freeing initrd memory: 59592K
10686 16:35:45.439971 <6>[ 3.496574] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10687 16:35:45.450793 <6>[ 3.507504] tun: Universal TUN/TAP device driver, 1.6
10688 16:35:45.454001 <6>[ 3.513550] thunder_xcv, ver 1.0
10689 16:35:45.457588 <6>[ 3.517054] thunder_bgx, ver 1.0
10690 16:35:45.460588 <6>[ 3.520554] nicpf, ver 1.0
10691 16:35:45.471065 <6>[ 3.524563] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10692 16:35:45.474647 <6>[ 3.532040] hns3: Copyright (c) 2017 Huawei Corporation.
10693 16:35:45.480865 <6>[ 3.537629] hclge is initializing
10694 16:35:45.484371 <6>[ 3.541207] e1000: Intel(R) PRO/1000 Network Driver
10695 16:35:45.491284 <6>[ 3.546336] e1000: Copyright (c) 1999-2006 Intel Corporation.
10696 16:35:45.494634 <6>[ 3.552348] e1000e: Intel(R) PRO/1000 Network Driver
10697 16:35:45.501262 <6>[ 3.557564] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10698 16:35:45.507825 <6>[ 3.563748] igb: Intel(R) Gigabit Ethernet Network Driver
10699 16:35:45.514001 <6>[ 3.569398] igb: Copyright (c) 2007-2014 Intel Corporation.
10700 16:35:45.520897 <6>[ 3.575232] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10701 16:35:45.527317 <6>[ 3.581750] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10702 16:35:45.530560 <6>[ 3.588211] sky2: driver version 1.30
10703 16:35:45.537669 <6>[ 3.593126] usbcore: registered new device driver r8152-cfgselector
10704 16:35:45.543804 <6>[ 3.599666] usbcore: registered new interface driver r8152
10705 16:35:45.550267 <6>[ 3.605485] VFIO - User Level meta-driver version: 0.3
10706 16:35:45.557436 <6>[ 3.613712] usbcore: registered new interface driver usb-storage
10707 16:35:45.563684 <6>[ 3.620155] usbcore: registered new device driver onboard-usb-hub
10708 16:35:45.572762 <6>[ 3.629281] mt6397-rtc mt6359-rtc: registered as rtc0
10709 16:35:45.582576 <6>[ 3.634749] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:35:45 UTC (1718642145)
10710 16:35:45.585837 <6>[ 3.644306] i2c_dev: i2c /dev entries driver
10711 16:35:45.599460 <4>[ 3.656157] cpu cpu0: supply cpu not found, using dummy regulator
10712 16:35:45.606008 <4>[ 3.662590] cpu cpu1: supply cpu not found, using dummy regulator
10713 16:35:45.612367 <4>[ 3.668999] cpu cpu2: supply cpu not found, using dummy regulator
10714 16:35:45.619245 <4>[ 3.675399] cpu cpu3: supply cpu not found, using dummy regulator
10715 16:35:45.625487 <4>[ 3.681820] cpu cpu4: supply cpu not found, using dummy regulator
10716 16:35:45.632371 <4>[ 3.688214] cpu cpu5: supply cpu not found, using dummy regulator
10717 16:35:45.638637 <4>[ 3.694616] cpu cpu6: supply cpu not found, using dummy regulator
10718 16:35:45.645418 <4>[ 3.701010] cpu cpu7: supply cpu not found, using dummy regulator
10719 16:35:45.666140 <6>[ 3.722679] cpu cpu0: EM: created perf domain
10720 16:35:45.668972 <6>[ 3.727629] cpu cpu4: EM: created perf domain
10721 16:35:45.676397 <6>[ 3.733184] sdhci: Secure Digital Host Controller Interface driver
10722 16:35:45.682954 <6>[ 3.739617] sdhci: Copyright(c) Pierre Ossman
10723 16:35:45.689807 <6>[ 3.744561] Synopsys Designware Multimedia Card Interface Driver
10724 16:35:45.695969 <6>[ 3.751198] sdhci-pltfm: SDHCI platform and OF driver helper
10725 16:35:45.699639 <6>[ 3.751249] mmc0: CQHCI version 5.10
10726 16:35:45.706282 <6>[ 3.761557] ledtrig-cpu: registered to indicate activity on CPUs
10727 16:35:45.712856 <6>[ 3.768637] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10728 16:35:45.719445 <6>[ 3.775696] usbcore: registered new interface driver usbhid
10729 16:35:45.722915 <6>[ 3.781518] usbhid: USB HID core driver
10730 16:35:45.729245 <6>[ 3.785705] spi_master spi0: will run message pump with realtime priority
10731 16:35:45.778186 <6>[ 3.828220] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10732 16:35:45.797711 <6>[ 3.843905] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10733 16:35:45.800934 <6>[ 3.856638] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10734 16:35:45.807699 <6>[ 3.858971] cros-ec-spi spi0.0: Chrome EC device registered
10735 16:35:45.810874 <6>[ 3.869364] mmc0: Command Queue Engine enabled
10736 16:35:45.817826 <6>[ 3.874090] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10737 16:35:45.825098 <6>[ 3.881900] mmcblk0: mmc0:0001 DA4128 116 GiB
10738 16:35:45.834884 <6>[ 3.882642] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10739 16:35:45.841606 <6>[ 3.890261] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10740 16:35:45.844686 <6>[ 3.896993] NET: Registered PF_PACKET protocol family
10741 16:35:45.851433 <6>[ 3.903031] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10742 16:35:45.855095 <6>[ 3.907248] 9pnet: Installing 9P2000 support
10743 16:35:45.861257 <6>[ 3.913050] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10744 16:35:45.865040 <5>[ 3.916939] Key type dns_resolver registered
10745 16:35:45.871223 <6>[ 3.922864] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10746 16:35:45.874817 <6>[ 3.927207] registered taskstats version 1
10747 16:35:45.881614 <5>[ 3.937544] Loading compiled-in X.509 certificates
10748 16:35:45.908842 <4>[ 3.959241] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10749 16:35:45.918782 <4>[ 3.969942] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10750 16:35:45.934389 <6>[ 3.991211] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10751 16:35:45.941147 <6>[ 3.998014] xhci-mtk 11200000.usb: xHCI Host Controller
10752 16:35:45.947549 <6>[ 4.003523] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10753 16:35:45.958114 <6>[ 4.011375] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10754 16:35:45.964269 <6>[ 4.020808] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10755 16:35:45.971244 <6>[ 4.026893] xhci-mtk 11200000.usb: xHCI Host Controller
10756 16:35:45.977515 <6>[ 4.032389] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10757 16:35:45.984503 <6>[ 4.040176] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10758 16:35:45.991443 <6>[ 4.048069] hub 1-0:1.0: USB hub found
10759 16:35:45.994491 <6>[ 4.052123] hub 1-0:1.0: 1 port detected
10760 16:35:46.004713 <6>[ 4.056443] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10761 16:35:46.007613 <6>[ 4.065243] hub 2-0:1.0: USB hub found
10762 16:35:46.011216 <6>[ 4.069270] hub 2-0:1.0: 1 port detected
10763 16:35:46.020344 <6>[ 4.077259] mtk-msdc 11f70000.mmc: Got CD GPIO
10764 16:35:46.035243 <6>[ 4.088515] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10765 16:35:46.045058 <6>[ 4.096928] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10766 16:35:46.051862 <6>[ 4.105267] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10767 16:35:46.061712 <6>[ 4.113606] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10768 16:35:46.067992 <6>[ 4.121947] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10769 16:35:46.078101 <6>[ 4.130287] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10770 16:35:46.084360 <6>[ 4.138629] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10771 16:35:46.094316 <6>[ 4.146969] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10772 16:35:46.101105 <6>[ 4.155307] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10773 16:35:46.110843 <6>[ 4.163646] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10774 16:35:46.117543 <6>[ 4.171982] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10775 16:35:46.127603 <6>[ 4.180330] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10776 16:35:46.133792 <6>[ 4.188669] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10777 16:35:46.143700 <6>[ 4.197007] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10778 16:35:46.150540 <6>[ 4.205344] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10779 16:35:46.157388 <6>[ 4.214035] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10780 16:35:46.164380 <6>[ 4.221197] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10781 16:35:46.171067 <6>[ 4.227995] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10782 16:35:46.181371 <6>[ 4.234761] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10783 16:35:46.188213 <6>[ 4.241728] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10784 16:35:46.194568 <6>[ 4.248600] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10785 16:35:46.204845 <6>[ 4.257733] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10786 16:35:46.214658 <6>[ 4.266852] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10787 16:35:46.224757 <6>[ 4.276148] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10788 16:35:46.234457 <6>[ 4.285616] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10789 16:35:46.241404 <6>[ 4.295087] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10790 16:35:46.250898 <6>[ 4.304207] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10791 16:35:46.260903 <6>[ 4.313673] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10792 16:35:46.270954 <6>[ 4.322793] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10793 16:35:46.280784 <6>[ 4.332087] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10794 16:35:46.290623 <6>[ 4.342247] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10795 16:35:46.300578 <6>[ 4.353785] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10796 16:35:46.421451 <6>[ 4.474816] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10797 16:35:46.575619 <6>[ 4.632368] hub 1-1:1.0: USB hub found
10798 16:35:46.578899 <6>[ 4.636918] hub 1-1:1.0: 4 ports detected
10799 16:35:46.590730 <6>[ 4.647256] hub 1-1:1.0: USB hub found
10800 16:35:46.593659 <6>[ 4.651556] hub 1-1:1.0: 4 ports detected
10801 16:35:46.701499 <6>[ 4.755143] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10802 16:35:46.727548 <6>[ 4.784608] hub 2-1:1.0: USB hub found
10803 16:35:46.731374 <6>[ 4.789100] hub 2-1:1.0: 3 ports detected
10804 16:35:46.743085 <6>[ 4.800103] hub 2-1:1.0: USB hub found
10805 16:35:46.746785 <6>[ 4.804593] hub 2-1:1.0: 3 ports detected
10806 16:35:46.913041 <6>[ 4.966781] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10807 16:35:47.045474 <6>[ 5.102481] hub 1-1.4:1.0: USB hub found
10808 16:35:47.049148 <6>[ 5.107301] hub 1-1.4:1.0: 2 ports detected
10809 16:35:47.060340 <6>[ 5.116935] hub 1-1.4:1.0: USB hub found
10810 16:35:47.063326 <6>[ 5.121446] hub 1-1.4:1.0: 2 ports detected
10811 16:35:47.133033 <6>[ 5.186884] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10812 16:35:47.241401 <6>[ 5.295217] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10813 16:35:47.274059 <4>[ 5.327523] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10814 16:35:47.283813 <4>[ 5.336708] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10815 16:35:47.318675 <6>[ 5.375485] r8152 2-1.3:1.0 eth0: v1.12.13
10816 16:35:47.369471 <6>[ 5.422835] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10817 16:35:47.564793 <6>[ 5.618750] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10818 16:35:48.904671 <6>[ 6.962093] r8152 2-1.3:1.0 eth0: carrier on
10819 16:35:51.653088 <5>[ 6.990635] Sending DHCP requests .., OK
10820 16:35:51.660269 <6>[ 9.714925] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10821 16:35:51.663179 <6>[ 9.723214] IP-Config: Complete:
10822 16:35:51.676287 <6>[ 9.726713] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10823 16:35:51.683080 <6>[ 9.737422] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10824 16:35:51.689355 <6>[ 9.746038] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10825 16:35:51.696362 <6>[ 9.746047] nameserver0=192.168.201.1
10826 16:35:51.699627 <6>[ 9.758227] clk: Disabling unused clocks
10827 16:35:51.702849 <6>[ 9.763771] ALSA device list:
10828 16:35:51.709382 <6>[ 9.767049] No soundcards found.
10829 16:35:51.717477 <6>[ 9.774795] Freeing unused kernel memory: 8512K
10830 16:35:51.720579 <6>[ 9.779703] Run /init as init process
10831 16:35:51.750784 <6>[ 9.808361] NET: Registered PF_INET6 protocol family
10832 16:35:51.757994 <6>[ 9.815187] Segment Routing with IPv6
10833 16:35:51.760810 <6>[ 9.819133] In-situ OAM (IOAM) with IPv6
10834 16:35:51.801751 <30>[ 9.832894] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10835 16:35:51.808267 <30>[ 9.865958] systemd[1]: Detected architecture arm64.
10836 16:35:51.808348
10837 16:35:51.815229 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10838 16:35:51.815326
10839 16:35:51.829357 <30>[ 9.886966] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10840 16:35:51.946061 <30>[ 10.000117] systemd[1]: Queued start job for default target graphical.target.
10841 16:35:52.006107 <30>[ 10.060644] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10842 16:35:52.013256 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10843 16:35:52.033824 <30>[ 10.088067] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10844 16:35:52.043935 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10845 16:35:52.062145 <30>[ 10.116332] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10846 16:35:52.072006 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10847 16:35:52.090264 <30>[ 10.144648] systemd[1]: Created slice user.slice - User and Session Slice.
10848 16:35:52.097055 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10849 16:35:52.121024 <30>[ 10.171750] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10850 16:35:52.130901 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10851 16:35:52.147991 <30>[ 10.199037] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10852 16:35:52.154667 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10853 16:35:52.182912 <30>[ 10.227306] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10854 16:35:52.192937 <30>[ 10.247191] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10855 16:35:52.199824 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10856 16:35:52.217152 <30>[ 10.271217] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10857 16:35:52.227027 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10858 16:35:52.245098 <30>[ 10.299309] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10859 16:35:52.254741 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10860 16:35:52.269588 <30>[ 10.327335] systemd[1]: Reached target paths.target - Path Units.
10861 16:35:52.279897 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10862 16:35:52.297258 <30>[ 10.351314] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10863 16:35:52.303458 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10864 16:35:52.317199 <30>[ 10.374811] systemd[1]: Reached target slices.target - Slice Units.
10865 16:35:52.327547 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10866 16:35:52.341014 <30>[ 10.398858] systemd[1]: Reached target swap.target - Swaps.
10867 16:35:52.348141 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10868 16:35:52.369062 <30>[ 10.423363] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10869 16:35:52.378906 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10870 16:35:52.397513 <30>[ 10.451687] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10871 16:35:52.407358 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10872 16:35:52.425833 <30>[ 10.480285] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10873 16:35:52.436008 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10874 16:35:52.453513 <30>[ 10.507421] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10875 16:35:52.463355 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10876 16:35:52.482076 <30>[ 10.536150] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10877 16:35:52.488634 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10878 16:35:52.509181 <30>[ 10.563491] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10879 16:35:52.519065 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10880 16:35:52.537020 <30>[ 10.591310] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10881 16:35:52.547118 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10882 16:35:52.600854 <30>[ 10.655056] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10883 16:35:52.607407 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10884 16:35:52.632307 <30>[ 10.686616] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10885 16:35:52.638742 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10886 16:35:52.663102 <30>[ 10.717140] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10887 16:35:52.669365 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10888 16:35:52.695264 <30>[ 10.742989] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10889 16:35:52.737215 <30>[ 10.791545] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10890 16:35:52.747276 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10891 16:35:52.769732 <30>[ 10.824206] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10892 16:35:52.776585 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10893 16:35:52.845430 <30>[ 10.899525] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10894 16:35:52.855141 Startin<6>[ 10.908943] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10895 16:35:52.861542 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10896 16:35:52.885478 <30>[ 10.940053] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10897 16:35:52.892435 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10898 16:35:52.918019 <30>[ 10.972081] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10899 16:35:52.927501 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10900 16:35:52.988944 <30>[ 11.043354] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10901 16:35:52.995550 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10902 16:35:53.021395 <30>[ 11.075483] systemd[1]: Starting systemd-journald.service - Journal Service...
10903 16:35:53.027426 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10904 16:35:53.047100 <30>[ 11.101503] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10905 16:35:53.053733 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10906 16:35:53.081004 <30>[ 11.132264] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10907 16:35:53.087493 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10908 16:35:53.141032 <30>[ 11.195412] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10909 16:35:53.151125 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10910 16:35:53.171718 <30>[ 11.225871] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10911 16:35:53.181302 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10912 16:35:53.201725 <30>[ 11.255733] systemd[1]: Started systemd-journald.service - Journal Service.
10913 16:35:53.208004 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10914 16:35:53.226920 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10915 16:35:53.249229 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10916 16:35:53.274026 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10917 16:35:53.297367 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10918 16:35:53.318253 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10919 16:35:53.338533 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10920 16:35:53.358332 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10921 16:35:53.377793 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10922 16:35:53.397995 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10923 16:35:53.419347 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10924 16:35:53.441770 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10925 16:35:53.467040 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10926 16:35:53.473350 See 'systemctl status systemd-remount-fs.service' for details.
10927 16:35:53.483427 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10928 16:35:53.502955 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10929 16:35:53.561385 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10930 16:35:53.585612 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10931 16:35:53.603467 <46>[ 11.658038] systemd-journald[186]: Received client request to flush runtime journal.
10932 16:35:53.616519 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10933 16:35:53.637301 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10934 16:35:53.661773 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10935 16:35:53.691161 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10936 16:35:53.710150 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10937 16:35:53.729764 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10938 16:35:53.750044 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10939 16:35:53.769842 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10940 16:35:53.829041 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10941 16:35:53.851776 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10942 16:35:53.868613 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10943 16:35:53.888558 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10944 16:35:53.945482 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10945 16:35:53.974348 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10946 16:35:53.996816 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10947 16:35:54.041552 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10948 16:35:54.070923 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10949 16:35:54.091846 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10950 16:35:54.125610 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10951 16:35:54.158944 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10952 16:35:54.194738 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10953 16:35:54.285831 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10954 16:35:54.305711 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10955 16:35:54.325092 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10956 16:35:54.345779 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10957 16:35:54.365553 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10958 16:35:54.381651 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10959 16:35:54.395012 <3>[ 12.449497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 16:35:54.401439 <3>[ 12.457671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10961 16:35:54.412038 <3>[ 12.465768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 16:35:54.424775 [[0;32m OK [0m] Reached target [0;1;39msock<6>[ 12.477411] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10963 16:35:54.431141 ets.target[0m -<3>[ 12.480066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 16:35:54.434893 Socket Units.
10965 16:35:54.441657 <6>[ 12.494425] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10966 16:35:54.451031 <3>[ 12.495859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10967 16:35:54.451177
10968 16:35:54.457927 <3>[ 12.495865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10969 16:35:54.467854 <3>[ 12.495872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 16:35:54.474388 <3>[ 12.495878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10971 16:35:54.481210 <6>[ 12.497461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10972 16:35:54.490589 <6>[ 12.502075] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10973 16:35:54.497458 <6>[ 12.505072] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10974 16:35:54.507376 <3>[ 12.507372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10975 16:35:54.514109 <3>[ 12.509401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 16:35:54.523956 <3>[ 12.509414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10977 16:35:54.530594 <3>[ 12.509419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 16:35:54.537101 <6>[ 12.512973] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10979 16:35:54.546958 <4>[ 12.513215] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10980 16:35:54.557069 <6>[ 12.521181] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10981 16:35:54.563538 <6>[ 12.529932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10982 16:35:54.570513 <6>[ 12.540136] remoteproc remoteproc0: scp is available
10983 16:35:54.576997 <6>[ 12.545399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10984 16:35:54.586633 <3>[ 12.548141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 16:35:54.590304 <6>[ 12.552789] remoteproc remoteproc0: powering up scp
10986 16:35:54.600311 <3>[ 12.561783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10987 16:35:54.606545 <6>[ 12.569542] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10988 16:35:54.613501 <6>[ 12.569568] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10989 16:35:54.619823 <3>[ 12.577702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10990 16:35:54.626298 <6>[ 12.604288] mc: Linux media interface: v0.10
10991 16:35:54.632822 <6>[ 12.605683] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10992 16:35:54.642868 <6>[ 12.605699] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10993 16:35:54.649649 <6>[ 12.605704] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10994 16:35:54.659414 <6>[ 12.605710] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10995 16:35:54.666347 <3>[ 12.611053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10996 16:35:54.672543 <4>[ 12.643220] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10997 16:35:54.682499 <3>[ 12.648698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10998 16:35:54.690291 <4>[ 12.662976] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10999 16:35:54.696574 <3>[ 12.672553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11000 16:35:54.703191 <6>[ 12.673236] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11001 16:35:54.710062 <6>[ 12.673261] pci_bus 0000:00: root bus resource [bus 00-ff]
11002 16:35:54.716911 <6>[ 12.673272] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11003 16:35:54.726443 <6>[ 12.673279] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11004 16:35:54.733225 <6>[ 12.673384] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11005 16:35:54.739841 <6>[ 12.673417] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11006 16:35:54.746330 <6>[ 12.673547] pci 0000:00:00.0: supports D1 D2
11007 16:35:54.753268 <6>[ 12.673552] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11008 16:35:54.759816 <6>[ 12.674733] videodev: Linux video capture interface: v2.00
11009 16:35:54.766108 <6>[ 12.707063] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11010 16:35:54.772935 <6>[ 12.710779] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11011 16:35:54.782586 <6>[ 12.711017] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11012 16:35:54.789156 <6>[ 12.711017] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11013 16:35:54.796399 <6>[ 12.711032] remoteproc remoteproc0: remote processor scp is now up
11014 16:35:54.802801 <6>[ 12.731102] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11015 16:35:54.809045 <6>[ 12.737001] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11016 16:35:54.818849 <4>[ 12.738804] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11017 16:35:54.825778 <4>[ 12.738804] Fallback method does not support PEC.
11018 16:35:54.832084 <6>[ 12.747961] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11019 16:35:54.838959 <6>[ 12.752300] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11020 16:35:54.848814 <6>[ 12.759329] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11021 16:35:54.858550 <6>[ 12.759680] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11022 16:35:54.868618 <6>[ 12.787241] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11023 16:35:54.875508 <6>[ 12.790548] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11024 16:35:54.878569 <6>[ 12.852764] Bluetooth: Core ver 2.22
11025 16:35:54.888243 <6>[ 12.858823] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11026 16:35:54.891674 <6>[ 12.867108] NET: Registered PF_BLUETOOTH protocol family
11027 16:35:54.898102 <6>[ 12.873362] pci 0000:01:00.0: supports D1 D2
11028 16:35:54.905141 <6>[ 12.886901] Bluetooth: HCI device and connection manager initialized
11029 16:35:54.911393 <6>[ 12.895123] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11030 16:35:54.917838 <6>[ 12.896516] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11031 16:35:54.921372 <6>[ 12.902641] Bluetooth: HCI socket layer initialized
11032 16:35:54.931372 <3>[ 12.902740] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 16:35:54.937678 <6>[ 12.906698] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11034 16:35:54.947731 <6>[ 12.906731] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11035 16:35:54.954083 <6>[ 12.906734] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11036 16:35:54.960945 <6>[ 12.906742] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11037 16:35:54.970498 <6>[ 12.906755] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11038 16:35:54.977509 <6>[ 12.906768] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11039 16:35:54.984149 <6>[ 12.906780] pci 0000:00:00.0: PCI bridge to [bus 01]
11040 16:35:54.990506 <6>[ 12.906785] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11041 16:35:54.997002 <6>[ 12.906953] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11042 16:35:55.004092 <6>[ 12.907713] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11043 16:35:55.010240 <6>[ 12.908186] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11044 16:35:55.023499 <6>[ 12.914197] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11045 16:35:55.026660 <6>[ 12.921769] Bluetooth: L2CAP socket layer initialized
11046 16:35:55.033444 <6>[ 12.921795] Bluetooth: SCO socket layer initialized
11047 16:35:55.039910 <6>[ 12.931464] usbcore: registered new interface driver uvcvideo
11048 16:35:55.046761 <5>[ 12.934392] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11049 16:35:55.053110 <5>[ 12.948129] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11050 16:35:55.059950 <6>[ 12.950800] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11051 16:35:55.070023 <5>[ 12.955986] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11052 16:35:55.073156 <6>[ 12.981075] usbcore: registered new interface driver btusb
11053 16:35:55.083417 <4>[ 12.981802] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11054 16:35:55.091026 <3>[ 12.981809] Bluetooth: hci0: Failed to load firmware file (-2)
11055 16:35:55.098204 <3>[ 12.981812] Bluetooth: hci0: Failed to set up firmware (-2)
11056 16:35:55.108586 <4>[ 12.981814] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11057 16:35:55.115814 <4>[ 12.985722] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11058 16:35:55.122837 <6>[ 13.087631] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11059 16:35:55.129007 <6>[ 13.090758] cfg80211: failed to load regulatory.db
11060 16:35:55.136028 <6>[ 13.095962] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11061 16:35:55.142517 <3>[ 13.161870] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11062 16:35:55.152314 <3>[ 13.169185] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11063 16:35:55.159224 <3>[ 13.181637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11064 16:35:55.166623 <6>[ 13.190172] mt7921e 0000:01:00.0: ASIC revision: 79610010
11065 16:35:55.176729 <3>[ 13.229286] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11066 16:35:55.186777 [[0;32m OK [<3>[ 13.238962] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
11067 16:35:55.189846 0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11068 16:35:55.208387 <3>[ 13.263079] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11069 16:35:55.239015 Starting [0;1;39mdbus.service[0m - D-Bus System Messa<3>[ 13.291152] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11070 16:35:55.239104 ge Bus...
11071 16:35:55.268365 <6>[ 13.322118] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11072 16:35:55.268455 <6>[ 13.322118]
11073 16:35:55.277838 <3>[ 13.332246] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11074 16:35:55.293950 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11075 16:35:55.309115 <3>[ 13.363717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11076 16:35:55.324173 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11077 16:35:55.348984 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11078 16:35:55.380437 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11079 16:35:55.435124 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11080 16:35:55.473918 [[0;32m OK [0m] Created slice [0;1;39msyste<46>[ 13.514983] systemd-journald[186]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.6 (1547 of 2047 items, 524288 file size, 338 bytes per hash table item), suggesting rotation.
11081 16:35:55.489886 m-syste…- Slic<46>[ 13.536935] systemd-journald[186]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11082 16:35:55.493498 e /system/systemd-backlight.
11083 16:35:55.509374 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11084 16:35:55.536753 [[0;32m OK [0m] Listening on<6>[ 13.590127] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11085 16:35:55.543014 [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11086 16:35:55.581381 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11087 16:35:55.636944 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11088 16:35:55.656221 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11089 16:35:55.671768 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11090 16:35:55.691589 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11091 16:35:55.752394 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11092 16:35:55.777030 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11093 16:35:55.802344 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11094 16:35:55.867982 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11095 16:35:55.888218 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11096 16:35:55.914590 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11097 16:35:55.953409
11098 16:35:55.956974 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11099 16:35:55.957110
11100 16:35:55.960252 debian-bookworm-arm64 login: root (automatic login)
11101 16:35:55.960355
11102 16:35:55.974969 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11103 16:35:55.975089
11104 16:35:55.981656 The programs included with the Debian GNU/Linux system are free software;
11105 16:35:55.988461 the exact distribution terms for each program are described in the
11106 16:35:55.991558 individual files in /usr/share/doc/*/copyright.
11107 16:35:55.991630
11108 16:35:55.998488 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11109 16:35:56.001773 permitted by applicable law.
11110 16:35:56.002276 Matched prompt #10: / #
11112 16:35:56.002605 Setting prompt string to ['/ #']
11113 16:35:56.002708 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11115 16:35:56.002906 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11116 16:35:56.003019 start: 2.2.6 expect-shell-connection (timeout 00:02:46) [common]
11117 16:35:56.003104 Setting prompt string to ['/ #']
11118 16:35:56.003212 Forcing a shell prompt, looking for ['/ #']
11120 16:35:56.053404 / #
11121 16:35:56.053587 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11122 16:35:56.053680 Waiting using forced prompt support (timeout 00:02:30)
11123 16:35:56.058824
11124 16:35:56.059086 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11125 16:35:56.059180 start: 2.2.7 export-device-env (timeout 00:02:46) [common]
11126 16:35:56.059264 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11127 16:35:56.059360 end: 2.2 depthcharge-retry (duration 00:02:14) [common]
11128 16:35:56.059452 end: 2 depthcharge-action (duration 00:02:14) [common]
11129 16:35:56.059531 start: 3 lava-test-retry (timeout 00:07:20) [common]
11130 16:35:56.059614 start: 3.1 lava-test-shell (timeout 00:07:20) [common]
11131 16:35:56.059682 Using namespace: common
11133 16:35:56.159956 / # #
11134 16:35:56.160156 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11135 16:35:56.165238 #
11136 16:35:56.165493 Using /lava-14396141
11138 16:35:56.265767 / # export SHELL=/bin/sh
11139 16:35:56.271077 export SHELL=/bin/sh
11141 16:35:56.371559 / # . /lava-14396141/environment
11142 16:35:56.376420 . /lava-14396141/environment
11144 16:35:56.480071 / # /lava-14396141/bin/lava-test-runner /lava-14396141/0
11145 16:35:56.480255 Test shell timeout: 10s (minimum of the action and connection timeout)
11146 16:35:56.480540 <6>[ 14.475619] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11147 16:35:56.484916 /lava-14396141/bin/lava-test-runner /lava-14396141/0
11148 16:35:56.528720 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 14.569119] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14396141_1.5.2.3.1>
11149 16:35:56.528840 nfrost
11150 16:35:56.529089 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14396141_1.5.2.3.1
11151 16:35:56.529161 Starting test lava.0_igt-gpu-panfrost (14396141_1.5.2.3.1)
11152 16:35:56.529242 Skipping test definition patterns.
11153 16:35:56.529336 + cd /lava-14396141/0/tests/0_igt-gpu-panfrost
11154 16:35:56.529398 + cat uuid
11155 16:35:56.529453 + UUID=14396141_1.5.2.3.1
11156 16:35:56.529507 + set +x
11157 16:35:56.538677 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime p<8>[ 14.594168] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11158 16:35:56.538773 anfrost_submit
11159 16:35:56.539006 Received signal: <TESTSET> START panfrost_gem_new
11160 16:35:56.539075 Starting test_set panfrost_gem_new
11161 16:35:56.556774 <14>[ 14.614695] [IGT] panfrost_gem_new: executing
11162 16:35:56.563538 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.621782] [IGT] panfrost_gem_new: exiting, ret=77
11163 16:35:56.566749 h64) (Linux: 6.1.92-cip22 aarch64)
11164 16:35:56.576902 Using IGT_SRANDOM=1718642156<8>[ 14.632267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11165 16:35:56.577186 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11167 16:35:56.580086 for randomisation
11168 16:35:56.586321 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11169 16:35:56.589943 Test requirement: !(fd<0)
11170 16:35:56.592914 No known gpu found for chipset flags 0x32 (panfrost)
11171 16:35:56.596185 Last errno: 2, No such file or directory
11172 16:35:56.599896 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11173 16:35:56.609573 <14>[ 14.667789] [IGT] panfrost_gem_new: executing
11174 16:35:56.619813 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.675524] [IGT] panfrost_gem_new: exiting, ret=77
11175 16:35:56.619944 .92-cip22 aarch64)
11176 16:35:56.629594 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11178 16:35:56.632910 Using IGT_SRANDOM=1718642156 for randomisati<8>[ 14.687309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11179 16:35:56.632987 on
11180 16:35:56.639581 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11181 16:35:56.639656 Test requirement: !(fd<0)
11182 16:35:56.646417 No known gpu found for chipset flags 0x32 (panfrost)
11183 16:35:56.653064 Last errn<14>[ 14.708337] [IGT] panfrost_gem_new: executing
11184 16:35:56.653176 o: 2, No such file or directory
11185 16:35:56.659795 <14>[ 14.716581] [IGT] panfrost_gem_new: exiting, ret=77
11186 16:35:56.659896
11187 16:35:56.663233 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11188 16:35:56.672601 IGT-Version: 1.28-ga4<8>[ 14.726705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11189 16:35:56.672914 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11191 16:35:56.675847 4ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11192 16:35:56.679072 U<8>[ 14.738043] <LAVA_SIGNAL_TESTSET STOP>
11193 16:35:56.679364 Received signal: <TESTSET> STOP
11194 16:35:56.679454 Closing test_set panfrost_gem_new
11195 16:35:56.685928 sing IGT_SRANDOM=1718642156 for randomisation
11196 16:35:56.692351 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11197 16:35:56.692460 Test requirement: !(fd<0)
11198 16:35:56.702447 Received signal: <TESTSET> START panfrost_get_param
11199 16:35:56.702576 Starting test_set panfrost_get_param
11200 16:35:56.706111 No known gpu found for chipset flags 0x32 (panfrost)<8>[ 14.760159] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11201 16:35:56.706194
11202 16:35:56.709142 Last errno: 2, No such file or directory
11203 16:35:56.712169 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11204 16:35:56.738395 <14>[ 14.796170] [IGT] panfrost_get_param: executing
11205 16:35:56.747878 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.805316] [IGT] panfrost_get_param: exiting, ret=77
11206 16:35:56.748018 .92-cip22 aarch64)
11207 16:35:56.754483 Using IGT_SRANDOM=1718642156 for randomisation
11208 16:35:56.761228 Test require<8>[ 14.816459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11209 16:35:56.761492 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11211 16:35:56.768199 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11212 16:35:56.771421 Test requirement: !(fd<0)
11213 16:35:56.774559 No known gpu found for chipset flags 0x32 (panfrost)
11214 16:35:56.781073 Last errn<14>[ 14.838328] [IGT] panfrost_get_param: executing
11215 16:35:56.784354 o: 2, No such file or directory
11216 16:35:56.788136 <14>[ 14.846026] [IGT] panfrost_get_param: exiting, ret=77
11217 16:35:56.788229
11218 16:35:56.791242 [1mSubtest base-params: SKIP (0.000s)[0m
11219 16:35:56.801485 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11221 16:35:56.804527 IGT-Version: 1.28-ga44ebfe (aarch64<8>[ 14.858510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11222 16:35:56.804621 ) (Linux: 6.1.92-cip22 aarch64)
11223 16:35:56.810909 Using IGT_SRANDOM=1718642156 for randomisation
11224 16:35:56.817824 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11225 16:35:56.824036 Test requirem<14>[ 14.879944] [IGT] panfrost_get_param: executing
11226 16:35:56.824146 ent: !(fd<0)
11227 16:35:56.830514 No known gpu found<14>[ 14.888410] [IGT] panfrost_get_param: exiting, ret=77
11228 16:35:56.834179 for chipset flags 0x32 (panfrost)
11229 16:35:56.844068 Last errno: 2, No such file <8>[ 14.899351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11230 16:35:56.844193 or directory
11231 16:35:56.844466 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11233 16:35:56.850608 [1mSubtest get-ba<8>[ 14.908919] <LAVA_SIGNAL_TESTSET STOP>
11234 16:35:56.850881 Received signal: <TESTSET> STOP
11235 16:35:56.850978 Closing test_set panfrost_get_param
11236 16:35:56.853962 d-param: SKIP (0.000s)[0m
11237 16:35:56.860355 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11238 16:35:56.863791 Using IGT_SRANDOM=1718642156 for randomisation
11239 16:35:56.877164 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:<8>[ 14.932586] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11240 16:35:56.877272
11241 16:35:56.877334 Test requirement: !(fd<0)
11242 16:35:56.877563 Received signal: <TESTSET> START panfrost_prime
11243 16:35:56.877630 Starting test_set panfrost_prime
11244 16:35:56.883582 No known gpu found for chipset flags 0x32 (panfrost)
11245 16:35:56.886921 Last errno: 2, No such file or directory
11246 16:35:56.890589 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11247 16:35:56.903766 <14>[ 14.961983] [IGT] panfrost_prime: executing
11248 16:35:56.914088 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.970069] [IGT] panfrost_prime: exiting, ret=77
11249 16:35:56.914191 .92-cip22 aarch64)
11250 16:35:56.920567 Using IGT_SRANDOM=1718642156 for randomisation
11251 16:35:56.930642 Test requirement not met in function drm_ope<8>[ 14.985431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11252 16:35:56.930907 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11254 16:35:56.937438 n_driver, file ../lib/drmtest.c:<8>[ 14.994685] <LAVA_SIGNAL_TESTSET STOP>
11255 16:35:56.937523 694:
11256 16:35:56.937755 Received signal: <TESTSET> STOP
11257 16:35:56.937820 Closing test_set panfrost_prime
11258 16:35:56.940534 Test requirement: !(fd<0)
11259 16:35:56.943619 No known gpu found for chipset flags 0x32 (panfrost)
11260 16:35:56.947202 Last errno: 2, No such file or directory
11261 16:35:56.953461 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11262 16:35:56.968297 <8>[ 15.026600] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11263 16:35:56.968573 Received signal: <TESTSET> START panfrost_submit
11264 16:35:56.968642 Starting test_set panfrost_submit
11265 16:35:56.992991 <14>[ 15.051353] [IGT] panfrost_submit: executing
11266 16:35:57.003372 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 15.059329] [IGT] panfrost_submit: exiting, ret=77
11267 16:35:57.003499 .92-cip22 aarch64)
11268 16:35:57.009826 Using IGT_SRANDOM=1718642156 for randomisation
11269 16:35:57.019624 Test requirement not met in function drm_ope<8>[ 15.074517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11270 16:35:57.019896 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11272 16:35:57.022784 n_driver, file ../lib/drmtest.c:694:
11273 16:35:57.026225 Test requirement: !(fd<0)
11274 16:35:57.029714 No known gpu found for chipset flags 0x32 (panfrost)
11275 16:35:57.032942 Last errno: 2, No such file or directory
11276 16:35:57.039611 [1mSubtest pan-submit: SKIP (0<14>[ 15.098860] [IGT] panfrost_submit: executing
11277 16:35:57.042841 .000s)[0m
11278 16:35:57.049313 IGT-Version: 1.2<14>[ 15.105712] [IGT] panfrost_submit: exiting, ret=77
11279 16:35:57.052964 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11280 16:35:57.062333 Using IGT_SR<8>[ 15.115633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11281 16:35:57.062605 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11283 16:35:57.066044 ANDOM=1718642156 for randomisation
11284 16:35:57.072567 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11285 16:35:57.072669 Test requirement: !(fd<0)
11286 16:35:57.078791 No known gpu found for chipset flags 0x32 (panfrost)
11287 16:35:57.082347 Last errno: 2, No such file or directory
11288 16:35:57.092093 [1mSubtest pan-submit-error-no-jc: SKIP (0.000<14>[ 15.148796] [IGT] panfrost_submit: executing
11289 16:35:57.092197 s)[0m
11290 16:35:57.102500 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 15.158149] [IGT] panfrost_submit: exiting, ret=77
11291 16:35:57.102615 .92-cip22 aarch64)
11292 16:35:57.105437 Using IGT_SRANDOM=1718642157 for randomisation
11293 16:35:57.118549 Test requirement not met in <8>[ 15.171612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11294 16:35:57.118857 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11296 16:35:57.121712 function drm_open_driver, file ../lib/drmtest.c:694:
11297 16:35:57.125461 Test requirement: !(fd<0)
11298 16:35:57.128764 No known gpu found for chipset flags 0x32 (panfrost)
11299 16:35:57.131887 Last errno: 2, No such file or directory
11300 16:35:57.141741 [1mSubtest pan-submit-error-ba<14>[ 15.197695] [IGT] panfrost_submit: executing
11301 16:35:57.141856 d-in-syncs: SKIP (0.000s)[0m
11302 16:35:57.148553 I<14>[ 15.205895] [IGT] panfrost_submit: exiting, ret=77
11303 16:35:57.161647 GT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64<8>[ 15.216964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11304 16:35:57.161749 )
11305 16:35:57.161983 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11307 16:35:57.168450 Using IGT_SRANDOM=1718642157 for randomisation
11308 16:35:57.175194 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11309 16:35:57.175315 Test requirement: !(fd<0)
11310 16:35:57.181855 <14>[ 15.239236] [IGT] panfrost_submit: executing
11311 16:35:57.188295 No known gpu found for chipset f<14>[ 15.246592] [IGT] panfrost_submit: exiting, ret=77
11312 16:35:57.191426 lags 0x32 (panfrost)
11313 16:35:57.195151 Last errno: 2, No such file or directory
11314 16:35:57.204955 [1mSubtest pan-<8>[ 15.258704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11315 16:35:57.205222 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11317 16:35:57.207938 submit-error-bad-bo-handles: SKIP (0.000s)[0m
11318 16:35:57.214730 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11319 16:35:57.218145 Using IGT_SRANDOM=1718642157 for randomisation
11320 16:35:57.224381 Test require<14>[ 15.282502] [IGT] panfrost_submit: executing
11321 16:35:57.234725 ment not met in function drm_ope<14>[ 15.290304] [IGT] panfrost_submit: exiting, ret=77
11322 16:35:57.237872 n_driver, file ../lib/drmtest.c:694:
11323 16:35:57.237954 Test requirement: !(fd<0)
11324 16:35:57.250994 No known gpu found for chipset flags 0x32 (panf<8>[ 15.304493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11325 16:35:57.251123 rost)
11326 16:35:57.251386 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11328 16:35:57.253902 Last errno: 2, No such file or directory
11329 16:35:57.260753 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11330 16:35:57.270771 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <14>[ 15.327536] [IGT] panfrost_submit: executing
11331 16:35:57.270923 6.1.92-cip22 aarch64)
11332 16:35:57.277133 Using IGT<14>[ 15.335031] [IGT] panfrost_submit: exiting, ret=77
11333 16:35:57.280460 _SRANDOM=1718642157 for randomisation
11334 16:35:57.290328 Test requirement not met <8>[ 15.346014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11335 16:35:57.290607 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11337 16:35:57.294191 in function drm_open_driver, file ../lib/drmtest.c:694:
11338 16:35:57.297280 Test requirement: !(fd<0)
11339 16:35:57.300413 No known gpu found for chipset flags 0x32 (panfrost)
11340 16:35:57.307236 Last errno: 2, No such file or directory
11341 16:35:57.310212 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11342 16:35:57.317011 IGT-Version: 1.28-ga44ebfe (aa<14>[ 15.376334] [IGT] panfrost_submit: executing
11343 16:35:57.320054 rch64) (Linux: 6.1.92-cip22 aarch64)
11344 16:35:57.327186 Using IGT_<14>[ 15.384607] [IGT] panfrost_submit: exiting, ret=77
11345 16:35:57.330264 SRANDOM=1718642157 for randomisation
11346 16:35:57.343200 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 15.399707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11347 16:35:57.343528 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11349 16:35:57.346346 c:694:
11350 16:35:57.346449 Test requirement: !(fd<0)
11351 16:35:57.353104 No known gpu found for chipset flags 0x32 (panfrost)
11352 16:35:57.356760 Last errno: 2, No such file or directory
11353 16:35:57.359668 [1mSubtest pan-reset: SKIP (0.000s)[0m
11354 16:35:57.366284 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11355 16:35:57.370107 Using IGT_SRANDOM=1718642157 for randomisation
11356 16:35:57.373489 <14>[ 15.432178] [IGT] panfrost_submit: executing
11357 16:35:57.373617
11358 16:35:57.383075 Test requirement not met in function drm_open_d<14>[ 15.441129] [IGT] panfrost_submit: exiting, ret=77
11359 16:35:57.386348 river, file ../lib/drmtest.c:694:
11360 16:35:57.389494 Test requirement: !(fd<0)
11361 16:35:57.399718 No known gpu found for chipset fla<8>[ 15.454024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11362 16:35:57.400039 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11364 16:35:57.402755 gs 0x32 (panfrost)
11365 16:35:57.406352 Last errno: <8>[ 15.464855] <LAVA_SIGNAL_TESTSET STOP>
11366 16:35:57.406646 Received signal: <TESTSET> STOP
11367 16:35:57.406749 Closing test_set panfrost_submit
11368 16:35:57.415888 2, No such file <8>[ 15.470925] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14396141_1.5.2.3.1>
11369 16:35:57.416022 or directory
11370 16:35:57.416292 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14396141_1.5.2.3.1
11371 16:35:57.416410 Ending use of test pattern.
11372 16:35:57.416503 Ending test lava.0_igt-gpu-panfrost (14396141_1.5.2.3.1), duration 0.89
11374 16:35:57.422833 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11375 16:35:57.425993 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11376 16:35:57.432627 Using IGT_SRANDOM=1718642157 for randomisation
11377 16:35:57.439380 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11378 16:35:57.439508 Test requirement: !(fd<0)
11379 16:35:57.445920 No known gpu found for chipset flags 0x32 (panfrost)
11380 16:35:57.448853 Last errno: 2, No such file or directory
11381 16:35:57.452520 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11382 16:35:57.455767 + set +x
11383 16:35:57.455876 <LAVA_TEST_RUNNER EXIT>
11384 16:35:57.456144 ok: lava_test_shell seems to have completed
11385 16:35:57.456693 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11386 16:35:57.456848 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11387 16:35:57.456973 end: 3 lava-test-retry (duration 00:00:01) [common]
11388 16:35:57.457095 start: 4 finalize (timeout 00:07:19) [common]
11389 16:35:57.457222 start: 4.1 power-off (timeout 00:00:30) [common]
11390 16:35:57.457441 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11391 16:35:57.658576 >> Command sent successfully.
11392 16:35:57.662070 Returned 0 in 0 seconds
11393 16:35:57.762466 end: 4.1 power-off (duration 00:00:00) [common]
11395 16:35:57.762880 start: 4.2 read-feedback (timeout 00:07:18) [common]
11396 16:35:57.763192 Listened to connection for namespace 'common' for up to 1s
11397 16:35:58.764126 Finalising connection for namespace 'common'
11398 16:35:58.764288 Disconnecting from shell: Finalise
11399 16:35:58.764369 / #
11400 16:35:58.864630 end: 4.2 read-feedback (duration 00:00:01) [common]
11401 16:35:58.864856 end: 4 finalize (duration 00:00:01) [common]
11402 16:35:58.865006 Cleaning after the job
11403 16:35:58.865133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/ramdisk
11404 16:35:58.872207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/kernel
11405 16:35:58.887584 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/dtb
11406 16:35:58.887885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396141/tftp-deploy-9j6kryo5/modules
11407 16:35:58.894179 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396141
11408 16:35:59.009170 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396141
11409 16:35:59.009316 Job finished correctly