Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 16:33:18.705716 lava-dispatcher, installed at version: 2024.03
2 16:33:18.705924 start: 0 validate
3 16:33:18.706041 Start time: 2024-06-17 16:33:18.706034+00:00 (UTC)
4 16:33:18.706172 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:33:18.706355 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 16:33:18.967527 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:33:18.968221 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:33:19.235305 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:33:19.236049 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:33:19.495731 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:33:19.496358 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:33:19.769320 validate duration: 1.06
14 16:33:19.770424 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:33:19.770923 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:33:19.771486 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:33:19.772413 Not decompressing ramdisk as can be used compressed.
18 16:33:19.772890 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 16:33:19.773268 saving as /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/ramdisk/rootfs.cpio.gz
20 16:33:19.773679 total size: 47897469 (45 MB)
21 16:33:19.778686 progress 0 % (0 MB)
22 16:33:19.810705 progress 5 % (2 MB)
23 16:33:19.823154 progress 10 % (4 MB)
24 16:33:19.835350 progress 15 % (6 MB)
25 16:33:19.847528 progress 20 % (9 MB)
26 16:33:19.859477 progress 25 % (11 MB)
27 16:33:19.871579 progress 30 % (13 MB)
28 16:33:19.883694 progress 35 % (16 MB)
29 16:33:19.895643 progress 40 % (18 MB)
30 16:33:19.907636 progress 45 % (20 MB)
31 16:33:19.919565 progress 50 % (22 MB)
32 16:33:19.931645 progress 55 % (25 MB)
33 16:33:19.943711 progress 60 % (27 MB)
34 16:33:19.955643 progress 65 % (29 MB)
35 16:33:19.967464 progress 70 % (32 MB)
36 16:33:19.979434 progress 75 % (34 MB)
37 16:33:19.991290 progress 80 % (36 MB)
38 16:33:20.003130 progress 85 % (38 MB)
39 16:33:20.015102 progress 90 % (41 MB)
40 16:33:20.026841 progress 95 % (43 MB)
41 16:33:20.038806 progress 100 % (45 MB)
42 16:33:20.039025 45 MB downloaded in 0.27 s (172.15 MB/s)
43 16:33:20.039180 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:33:20.039397 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:33:20.039478 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:33:20.039553 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:33:20.039683 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:33:20.039744 saving as /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/kernel/Image
50 16:33:20.039797 total size: 54813184 (52 MB)
51 16:33:20.039850 No compression specified
52 16:33:20.040821 progress 0 % (0 MB)
53 16:33:20.054707 progress 5 % (2 MB)
54 16:33:20.068255 progress 10 % (5 MB)
55 16:33:20.081934 progress 15 % (7 MB)
56 16:33:20.095618 progress 20 % (10 MB)
57 16:33:20.109141 progress 25 % (13 MB)
58 16:33:20.122703 progress 30 % (15 MB)
59 16:33:20.136337 progress 35 % (18 MB)
60 16:33:20.150185 progress 40 % (20 MB)
61 16:33:20.163983 progress 45 % (23 MB)
62 16:33:20.177598 progress 50 % (26 MB)
63 16:33:20.191281 progress 55 % (28 MB)
64 16:33:20.204683 progress 60 % (31 MB)
65 16:33:20.218641 progress 65 % (34 MB)
66 16:33:20.232430 progress 70 % (36 MB)
67 16:33:20.246939 progress 75 % (39 MB)
68 16:33:20.261430 progress 80 % (41 MB)
69 16:33:20.276632 progress 85 % (44 MB)
70 16:33:20.290297 progress 90 % (47 MB)
71 16:33:20.304587 progress 95 % (49 MB)
72 16:33:20.318029 progress 100 % (52 MB)
73 16:33:20.318401 52 MB downloaded in 0.28 s (187.63 MB/s)
74 16:33:20.318555 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:33:20.318771 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:33:20.318852 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:33:20.318928 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:33:20.319053 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:33:20.319114 saving as /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/dtb/mt8192-asurada-spherion-r0.dtb
81 16:33:20.319167 total size: 47258 (0 MB)
82 16:33:20.319220 No compression specified
83 16:33:20.320222 progress 69 % (0 MB)
84 16:33:20.320477 progress 100 % (0 MB)
85 16:33:20.320621 0 MB downloaded in 0.00 s (31.04 MB/s)
86 16:33:20.320731 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:33:20.320927 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:33:20.321002 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:33:20.321077 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:33:20.321179 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:33:20.321238 saving as /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/modules/modules.tar
93 16:33:20.321290 total size: 8628772 (8 MB)
94 16:33:20.321343 Using unxz to decompress xz
95 16:33:20.322632 progress 0 % (0 MB)
96 16:33:20.344114 progress 5 % (0 MB)
97 16:33:20.370554 progress 10 % (0 MB)
98 16:33:20.394092 progress 15 % (1 MB)
99 16:33:20.417753 progress 20 % (1 MB)
100 16:33:20.441913 progress 25 % (2 MB)
101 16:33:20.465534 progress 30 % (2 MB)
102 16:33:20.491340 progress 35 % (2 MB)
103 16:33:20.515490 progress 40 % (3 MB)
104 16:33:20.540073 progress 45 % (3 MB)
105 16:33:20.565036 progress 50 % (4 MB)
106 16:33:20.588682 progress 55 % (4 MB)
107 16:33:20.612633 progress 60 % (4 MB)
108 16:33:20.639005 progress 65 % (5 MB)
109 16:33:20.663045 progress 70 % (5 MB)
110 16:33:20.686028 progress 75 % (6 MB)
111 16:33:20.709053 progress 80 % (6 MB)
112 16:33:20.735614 progress 85 % (7 MB)
113 16:33:20.762060 progress 90 % (7 MB)
114 16:33:20.787064 progress 95 % (7 MB)
115 16:33:20.811726 progress 100 % (8 MB)
116 16:33:20.816619 8 MB downloaded in 0.50 s (16.61 MB/s)
117 16:33:20.816784 end: 1.4.1 http-download (duration 00:00:00) [common]
119 16:33:20.816992 end: 1.4 download-retry (duration 00:00:00) [common]
120 16:33:20.817073 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:33:20.817152 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:33:20.817225 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:33:20.817297 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:33:20.817456 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s
125 16:33:20.817569 makedir: /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin
126 16:33:20.817658 makedir: /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/tests
127 16:33:20.817769 makedir: /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/results
128 16:33:20.817886 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-add-keys
129 16:33:20.818025 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-add-sources
130 16:33:20.818141 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-background-process-start
131 16:33:20.818305 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-background-process-stop
132 16:33:20.818430 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-common-functions
133 16:33:20.818543 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-echo-ipv4
134 16:33:20.818655 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-install-packages
135 16:33:20.818769 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-installed-packages
136 16:33:20.818880 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-os-build
137 16:33:20.818991 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-probe-channel
138 16:33:20.819103 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-probe-ip
139 16:33:20.819212 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-target-ip
140 16:33:20.819354 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-target-mac
141 16:33:20.819463 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-target-storage
142 16:33:20.819575 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-case
143 16:33:20.819687 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-event
144 16:33:20.819796 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-feedback
145 16:33:20.819905 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-raise
146 16:33:20.820013 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-reference
147 16:33:20.820123 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-runner
148 16:33:20.820231 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-set
149 16:33:20.820362 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-test-shell
150 16:33:20.820476 Updating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-install-packages (oe)
151 16:33:20.820612 Updating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/bin/lava-installed-packages (oe)
152 16:33:20.820727 Creating /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/environment
153 16:33:20.820810 LAVA metadata
154 16:33:20.820873 - LAVA_JOB_ID=14396148
155 16:33:20.820928 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:33:20.821026 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:33:20.821083 skipped lava-vland-overlay
158 16:33:20.821148 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:33:20.821219 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:33:20.821272 skipped lava-multinode-overlay
161 16:33:20.821336 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:33:20.821405 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:33:20.821465 Loading test definitions
164 16:33:20.821539 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:33:20.821597 Using /lava-14396148 at stage 0
166 16:33:20.821881 uuid=14396148_1.5.2.3.1 testdef=None
167 16:33:20.821960 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:33:20.822036 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:33:20.822520 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:33:20.822719 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:33:20.823282 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:33:20.823505 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:33:20.824046 runner path: /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/0/tests/0_igt-kms-mediatek test_uuid 14396148_1.5.2.3.1
176 16:33:20.824192 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:33:20.824381 Creating lava-test-runner.conf files
179 16:33:20.824435 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396148/lava-overlay-6l1but0s/lava-14396148/0 for stage 0
180 16:33:20.824514 - 0_igt-kms-mediatek
181 16:33:20.824639 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:33:20.824714 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:33:20.830648 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:33:20.830743 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:33:20.830822 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:33:20.830904 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:33:20.830980 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:33:22.597355 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 16:33:22.597490 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 16:33:22.597569 extracting modules file /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396148/extract-overlay-ramdisk-18uwattx/ramdisk
191 16:33:22.864242 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:33:22.864371 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 16:33:22.864452 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396148/compress-overlay-liv7v0vd/overlay-1.5.2.4.tar.gz to ramdisk
194 16:33:22.864512 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396148/compress-overlay-liv7v0vd/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396148/extract-overlay-ramdisk-18uwattx/ramdisk
195 16:33:22.870938 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:33:22.871035 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 16:33:22.871115 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:33:22.871193 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 16:33:22.871257 Building ramdisk /var/lib/lava/dispatcher/tmp/14396148/extract-overlay-ramdisk-18uwattx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396148/extract-overlay-ramdisk-18uwattx/ramdisk
200 16:33:24.076489 >> 466049 blocks
201 16:33:30.716581 rename /var/lib/lava/dispatcher/tmp/14396148/extract-overlay-ramdisk-18uwattx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/ramdisk/ramdisk.cpio.gz
202 16:33:30.716744 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 16:33:30.716835 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 16:33:30.716914 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 16:33:30.716997 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/kernel/Image']
206 16:33:44.308110 Returned 0 in 13 seconds
207 16:33:44.408966 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/kernel/image.itb
208 16:33:45.417908 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:33:45.418029 output: Created: Mon Jun 17 17:33:45 2024
210 16:33:45.418092 output: Image 0 (kernel-1)
211 16:33:45.418153 output: Description:
212 16:33:45.418214 output: Created: Mon Jun 17 17:33:45 2024
213 16:33:45.418312 output: Type: Kernel Image
214 16:33:45.418371 output: Compression: lzma compressed
215 16:33:45.418429 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
216 16:33:45.418487 output: Architecture: AArch64
217 16:33:45.418543 output: OS: Linux
218 16:33:45.418599 output: Load Address: 0x00000000
219 16:33:45.418653 output: Entry Point: 0x00000000
220 16:33:45.418708 output: Hash algo: crc32
221 16:33:45.418764 output: Hash value: 106ffd6f
222 16:33:45.418816 output: Image 1 (fdt-1)
223 16:33:45.418867 output: Description: mt8192-asurada-spherion-r0
224 16:33:45.418920 output: Created: Mon Jun 17 17:33:45 2024
225 16:33:45.418972 output: Type: Flat Device Tree
226 16:33:45.419022 output: Compression: uncompressed
227 16:33:45.419077 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 16:33:45.419127 output: Architecture: AArch64
229 16:33:45.419179 output: Hash algo: crc32
230 16:33:45.419227 output: Hash value: 0f8e4d2e
231 16:33:45.419275 output: Image 2 (ramdisk-1)
232 16:33:45.419322 output: Description: unavailable
233 16:33:45.419370 output: Created: Mon Jun 17 17:33:45 2024
234 16:33:45.419418 output: Type: RAMDisk Image
235 16:33:45.419465 output: Compression: uncompressed
236 16:33:45.419512 output: Data Size: 61010956 Bytes = 59581.01 KiB = 58.18 MiB
237 16:33:45.419560 output: Architecture: AArch64
238 16:33:45.419606 output: OS: Linux
239 16:33:45.419653 output: Load Address: unavailable
240 16:33:45.419700 output: Entry Point: unavailable
241 16:33:45.419747 output: Hash algo: crc32
242 16:33:45.419794 output: Hash value: 0b5341db
243 16:33:45.419841 output: Default Configuration: 'conf-1'
244 16:33:45.419888 output: Configuration 0 (conf-1)
245 16:33:45.419936 output: Description: mt8192-asurada-spherion-r0
246 16:33:45.419983 output: Kernel: kernel-1
247 16:33:45.420031 output: Init Ramdisk: ramdisk-1
248 16:33:45.420079 output: FDT: fdt-1
249 16:33:45.420127 output: Loadables: kernel-1
250 16:33:45.420174 output:
251 16:33:45.420309 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 16:33:45.420394 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 16:33:45.420482 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
254 16:33:45.420563 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 16:33:45.420633 No LXC device requested
256 16:33:45.420705 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:33:45.420783 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 16:33:45.420851 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:33:45.420909 Checking files for TFTP limit of 4294967296 bytes.
260 16:33:45.421352 end: 1 tftp-deploy (duration 00:00:26) [common]
261 16:33:45.421450 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:33:45.421532 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:33:45.421639 substitutions:
264 16:33:45.421697 - {DTB}: 14396148/tftp-deploy-4nudwhtf/dtb/mt8192-asurada-spherion-r0.dtb
265 16:33:45.421755 - {INITRD}: 14396148/tftp-deploy-4nudwhtf/ramdisk/ramdisk.cpio.gz
266 16:33:45.421808 - {KERNEL}: 14396148/tftp-deploy-4nudwhtf/kernel/Image
267 16:33:45.421859 - {LAVA_MAC}: None
268 16:33:45.421909 - {PRESEED_CONFIG}: None
269 16:33:45.421959 - {PRESEED_LOCAL}: None
270 16:33:45.422010 - {RAMDISK}: 14396148/tftp-deploy-4nudwhtf/ramdisk/ramdisk.cpio.gz
271 16:33:45.422067 - {ROOT_PART}: None
272 16:33:45.422118 - {ROOT}: None
273 16:33:45.422168 - {SERVER_IP}: 192.168.201.1
274 16:33:45.422244 - {TEE}: None
275 16:33:45.422308 Parsed boot commands:
276 16:33:45.422363 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:33:45.422513 Parsed boot commands: tftpboot 192.168.201.1 14396148/tftp-deploy-4nudwhtf/kernel/image.itb 14396148/tftp-deploy-4nudwhtf/kernel/cmdline
278 16:33:45.422599 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:33:45.422678 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:33:45.422757 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:33:45.422833 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:33:45.422893 Not connected, no need to disconnect.
283 16:33:45.422960 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:33:45.423032 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:33:45.423090 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 16:33:45.426390 Setting prompt string to ['lava-test: # ']
287 16:33:45.426700 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:33:45.426796 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:33:45.426890 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:33:45.426972 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:33:45.427162 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
292 16:33:59.129055 Returned 0 in 13 seconds
293 16:33:59.230048 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 16:33:59.231331 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 16:33:59.231799 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 16:33:59.232227 Setting prompt string to 'Starting depthcharge on Spherion...'
298 16:33:59.232533 Changing prompt to 'Starting depthcharge on Spherion...'
299 16:33:59.232869 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 16:33:59.234539 [Enter `^Ec?' for help]
301 16:33:59.234913
302 16:33:59.235219
303 16:33:59.235522 F0: 102B 0000
304 16:33:59.235831
305 16:33:59.236110 F3: 1001 0000 [0200]
306 16:33:59.236409
307 16:33:59.236708 F3: 1001 0000
308 16:33:59.237073
309 16:33:59.237374 F7: 102D 0000
310 16:33:59.237664
311 16:33:59.237938 F1: 0000 0000
312 16:33:59.238208
313 16:33:59.238491 V0: 0000 0000 [0001]
314 16:33:59.238755
315 16:33:59.239014 00: 0007 8000
316 16:33:59.239285
317 16:33:59.239531 01: 0000 0000
318 16:33:59.239783
319 16:33:59.240027 BP: 0C00 0209 [0000]
320 16:33:59.240273
321 16:33:59.240515 G0: 1182 0000
322 16:33:59.240758
323 16:33:59.241003 EC: 0000 0021 [4000]
324 16:33:59.241248
325 16:33:59.241491 S7: 0000 0000 [0000]
326 16:33:59.241732
327 16:33:59.241974 CC: 0000 0000 [0001]
328 16:33:59.242235
329 16:33:59.242491 T0: 0000 0040 [010F]
330 16:33:59.242735
331 16:33:59.242978 Jump to BL
332 16:33:59.243223
333 16:33:59.243469
334 16:33:59.243712
335 16:33:59.243958 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 16:33:59.244222 ARM64: Exception handlers installed.
337 16:33:59.244477 ARM64: Testing exception
338 16:33:59.244729 ARM64: Done test exception
339 16:33:59.245208 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 16:33:59.245561 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 16:33:59.245925 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 16:33:59.246207 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 16:33:59.246500 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 16:33:59.246751 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 16:33:59.247005 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 16:33:59.247256 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 16:33:59.247506 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 16:33:59.247759 WDT: Last reset was cold boot
349 16:33:59.248007 SPI1(PAD0) initialized at 2873684 Hz
350 16:33:59.248252 SPI5(PAD0) initialized at 992727 Hz
351 16:33:59.248500 VBOOT: Loading verstage.
352 16:33:59.248748 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 16:33:59.248998 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 16:33:59.249250 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 16:33:59.249504 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 16:33:59.249753 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 16:33:59.250124 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 16:33:59.250421 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
359 16:33:59.250677
360 16:33:59.250925
361 16:33:59.251327 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 16:33:59.251618 ARM64: Exception handlers installed.
363 16:33:59.251910 ARM64: Testing exception
364 16:33:59.252165 ARM64: Done test exception
365 16:33:59.252420 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 16:33:59.252675 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 16:33:59.252927 Probing TPM: . done!
368 16:33:59.253174 TPM ready after 0 ms
369 16:33:59.253593 Connected to device vid:did:rid of 1ae0:0028:00
370 16:33:59.253870 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
371 16:33:59.254162 Initialized TPM device CR50 revision 0
372 16:33:59.254398 tlcl_send_startup: Startup return code is 0
373 16:33:59.254584 TPM: setup succeeded
374 16:33:59.254763 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 16:33:59.254942 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 16:33:59.255118 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 16:33:59.255297 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:33:59.255474 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 16:33:59.255653 in-header: 03 07 00 00 08 00 00 00
380 16:33:59.255828 in-data: aa e4 47 04 13 02 00 00
381 16:33:59.256005 Chrome EC: UHEPI supported
382 16:33:59.256183 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 16:33:59.256363 in-header: 03 a9 00 00 08 00 00 00
384 16:33:59.256537 in-data: 84 60 60 08 00 00 00 00
385 16:33:59.256713 Phase 1
386 16:33:59.256891 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 16:33:59.257072 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 16:33:59.257251 VB2:vb2_check_recovery() Recovery was requested manually
389 16:33:59.257430 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 16:33:59.257607 Recovery requested (1009000e)
391 16:33:59.257782 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 16:33:59.257958 tlcl_extend: response is 0
393 16:33:59.258135 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 16:33:59.258338 tlcl_extend: response is 0
395 16:33:59.258518 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 16:33:59.258677 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
397 16:33:59.258811 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 16:33:59.258944
399 16:33:59.259076
400 16:33:59.259207 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 16:33:59.259343 ARM64: Exception handlers installed.
402 16:33:59.259477 ARM64: Testing exception
403 16:33:59.259610 ARM64: Done test exception
404 16:33:59.259741 pmic_efuse_setting: Set efuses in 11 msecs
405 16:33:59.259874 pmwrap_interface_init: Select PMIF_VLD_RDY
406 16:33:59.260006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 16:33:59.260140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 16:33:59.260580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 16:33:59.260754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 16:33:59.260893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 16:33:59.261028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 16:33:59.261164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 16:33:59.261299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 16:33:59.261435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 16:33:59.261568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 16:33:59.261702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 16:33:59.261835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 16:33:59.261968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 16:33:59.262102 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 16:33:59.262274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 16:33:59.262419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 16:33:59.262556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 16:33:59.262688 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 16:33:59.262821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 16:33:59.262954 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 16:33:59.263088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 16:33:59.263224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 16:33:59.263358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 16:33:59.263492 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 16:33:59.263622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 16:33:59.263729 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 16:33:59.263835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 16:33:59.263942 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 16:33:59.264050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 16:33:59.264158 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 16:33:59.264264 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 16:33:59.264372 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 16:33:59.264480 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 16:33:59.264586 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 16:33:59.264692 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 16:33:59.264799 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 16:33:59.264907 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 16:33:59.265022 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 16:33:59.265135 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 16:33:59.265247 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 16:33:59.265361 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 16:33:59.265466 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 16:33:59.265572 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 16:33:59.265679 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 16:33:59.265785 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 16:33:59.265891 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 16:33:59.265998 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 16:33:59.266104 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 16:33:59.266219 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 16:33:59.266349 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 16:33:59.266461 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 16:33:59.266575 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 16:33:59.266691 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 16:33:59.266806 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 16:33:59.266914 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 16:33:59.267023 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 16:33:59.267138 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 16:33:59.267246 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 16:33:59.267359 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:33:59.267469 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x12
466 16:33:59.267577 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 16:33:59.267690 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 16:33:59.267798 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 16:33:59.267925 [RTC]rtc_get_frequency_meter,154: input=15, output=764
470 16:33:59.268058 [RTC]rtc_get_frequency_meter,154: input=23, output=948
471 16:33:59.268175 [RTC]rtc_get_frequency_meter,154: input=19, output=856
472 16:33:59.268287 [RTC]rtc_get_frequency_meter,154: input=17, output=810
473 16:33:59.268394 [RTC]rtc_get_frequency_meter,154: input=16, output=787
474 16:33:59.268502 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 16:33:59.268609 [RTC]rtc_get_frequency_meter,154: input=17, output=810
476 16:33:59.268698 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 16:33:59.268788 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 16:33:59.269098 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 16:33:59.269202 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 16:33:59.269294 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 16:33:59.269384 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 16:33:59.269474 ADC[4]: Raw value=670432 ID=5
483 16:33:59.269563 ADC[3]: Raw value=212549 ID=1
484 16:33:59.269652 RAM Code: 0x51
485 16:33:59.269741 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 16:33:59.269833 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 16:33:59.269922 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 16:33:59.270012 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 16:33:59.270102 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 16:33:59.270193 in-header: 03 07 00 00 08 00 00 00
491 16:33:59.270295 in-data: aa e4 47 04 13 02 00 00
492 16:33:59.270385 Chrome EC: UHEPI supported
493 16:33:59.270474 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 16:33:59.270565 in-header: 03 a9 00 00 08 00 00 00
495 16:33:59.270654 in-data: 84 60 60 08 00 00 00 00
496 16:33:59.270743 MRC: failed to locate region type 0.
497 16:33:59.270832 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 16:33:59.270922 DRAM-K: Running full calibration
499 16:33:59.271011 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 16:33:59.271102 header.status = 0x0
501 16:33:59.271190 header.version = 0x6 (expected: 0x6)
502 16:33:59.271280 header.size = 0xd00 (expected: 0xd00)
503 16:33:59.271369 header.flags = 0x0
504 16:33:59.271458 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 16:33:59.271549 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
506 16:33:59.271640 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 16:33:59.271730 dram_init: ddr_geometry: 0
508 16:33:59.271825 [EMI] MDL number = 0
509 16:33:59.271914 [EMI] Get MDL freq = 0
510 16:33:59.272003 dram_init: ddr_type: 0
511 16:33:59.272098 is_discrete_lpddr4: 1
512 16:33:59.272195 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 16:33:59.272337
514 16:33:59.272469
515 16:33:59.272615 [Bian_co] ETT version 0.0.0.1
516 16:33:59.272757 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 16:33:59.272906
518 16:33:59.273059 dramc_set_vcore_voltage set vcore to 650000
519 16:33:59.273216 Read voltage for 800, 4
520 16:33:59.273333 Vio18 = 0
521 16:33:59.273485 Vcore = 650000
522 16:33:59.273597 Vdram = 0
523 16:33:59.273683 Vddq = 0
524 16:33:59.273765 Vmddr = 0
525 16:33:59.273842 dram_init: config_dvfs: 1
526 16:33:59.273921 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 16:33:59.273999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 16:33:59.274077 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 16:33:59.274155 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 16:33:59.274252 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 16:33:59.274334 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 16:33:59.274411 MEM_TYPE=3, freq_sel=18
533 16:33:59.274488 sv_algorithm_assistance_LP4_1600
534 16:33:59.274566 ============ PULL DRAM RESETB DOWN ============
535 16:33:59.274650 ========== PULL DRAM RESETB DOWN end =========
536 16:33:59.274728 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 16:33:59.274805 ===================================
538 16:33:59.274882 LPDDR4 DRAM CONFIGURATION
539 16:33:59.274959 ===================================
540 16:33:59.275036 EX_ROW_EN[0] = 0x0
541 16:33:59.275113 EX_ROW_EN[1] = 0x0
542 16:33:59.275189 LP4Y_EN = 0x0
543 16:33:59.275266 WORK_FSP = 0x0
544 16:33:59.275341 WL = 0x2
545 16:33:59.275416 RL = 0x2
546 16:33:59.275491 BL = 0x2
547 16:33:59.275566 RPST = 0x0
548 16:33:59.275641 RD_PRE = 0x0
549 16:33:59.275717 WR_PRE = 0x1
550 16:33:59.275792 WR_PST = 0x0
551 16:33:59.275867 DBI_WR = 0x0
552 16:33:59.275942 DBI_RD = 0x0
553 16:33:59.276018 OTF = 0x1
554 16:33:59.276094 ===================================
555 16:33:59.276171 ===================================
556 16:33:59.276247 ANA top config
557 16:33:59.276323 ===================================
558 16:33:59.276400 DLL_ASYNC_EN = 0
559 16:33:59.276476 ALL_SLAVE_EN = 1
560 16:33:59.276551 NEW_RANK_MODE = 1
561 16:33:59.276628 DLL_IDLE_MODE = 1
562 16:33:59.276703 LP45_APHY_COMB_EN = 1
563 16:33:59.276779 TX_ODT_DIS = 1
564 16:33:59.276854 NEW_8X_MODE = 1
565 16:33:59.276930 ===================================
566 16:33:59.277006 ===================================
567 16:33:59.277082 data_rate = 1600
568 16:33:59.277158 CKR = 1
569 16:33:59.277234 DQ_P2S_RATIO = 8
570 16:33:59.277309 ===================================
571 16:33:59.277386 CA_P2S_RATIO = 8
572 16:33:59.277461 DQ_CA_OPEN = 0
573 16:33:59.277537 DQ_SEMI_OPEN = 0
574 16:33:59.277612 CA_SEMI_OPEN = 0
575 16:33:59.277688 CA_FULL_RATE = 0
576 16:33:59.277763 DQ_CKDIV4_EN = 1
577 16:33:59.277839 CA_CKDIV4_EN = 1
578 16:33:59.277915 CA_PREDIV_EN = 0
579 16:33:59.277991 PH8_DLY = 0
580 16:33:59.278066 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 16:33:59.278142 DQ_AAMCK_DIV = 4
582 16:33:59.278230 CA_AAMCK_DIV = 4
583 16:33:59.278314 CA_ADMCK_DIV = 4
584 16:33:59.278389 DQ_TRACK_CA_EN = 0
585 16:33:59.278465 CA_PICK = 800
586 16:33:59.278541 CA_MCKIO = 800
587 16:33:59.278622 MCKIO_SEMI = 0
588 16:33:59.278690 PLL_FREQ = 3068
589 16:33:59.278759 DQ_UI_PI_RATIO = 32
590 16:33:59.278827 CA_UI_PI_RATIO = 0
591 16:33:59.278894 ===================================
592 16:33:59.278962 ===================================
593 16:33:59.279030 memory_type:LPDDR4
594 16:33:59.279096 GP_NUM : 10
595 16:33:59.279163 SRAM_EN : 1
596 16:33:59.279230 MD32_EN : 0
597 16:33:59.279297 ===================================
598 16:33:59.279587 [ANA_INIT] >>>>>>>>>>>>>>
599 16:33:59.279665 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 16:33:59.279742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 16:33:59.279810 ===================================
602 16:33:59.279878 data_rate = 1600,PCW = 0X7600
603 16:33:59.279945 ===================================
604 16:33:59.280013 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 16:33:59.280082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 16:33:59.280150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 16:33:59.280218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 16:33:59.280286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 16:33:59.280354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 16:33:59.280421 [ANA_INIT] flow start
611 16:33:59.280489 [ANA_INIT] PLL >>>>>>>>
612 16:33:59.280555 [ANA_INIT] PLL <<<<<<<<
613 16:33:59.280623 [ANA_INIT] MIDPI >>>>>>>>
614 16:33:59.280690 [ANA_INIT] MIDPI <<<<<<<<
615 16:33:59.280757 [ANA_INIT] DLL >>>>>>>>
616 16:33:59.280824 [ANA_INIT] flow end
617 16:33:59.280891 ============ LP4 DIFF to SE enter ============
618 16:33:59.280959 ============ LP4 DIFF to SE exit ============
619 16:33:59.281026 [ANA_INIT] <<<<<<<<<<<<<
620 16:33:59.281092 [Flow] Enable top DCM control >>>>>
621 16:33:59.281159 [Flow] Enable top DCM control <<<<<
622 16:33:59.281226 Enable DLL master slave shuffle
623 16:33:59.281293 ==============================================================
624 16:33:59.281361 Gating Mode config
625 16:33:59.281428 ==============================================================
626 16:33:59.281496 Config description:
627 16:33:59.281564 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 16:33:59.281632 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 16:33:59.281700 SELPH_MODE 0: By rank 1: By Phase
630 16:33:59.281767 ==============================================================
631 16:33:59.281836 GAT_TRACK_EN = 1
632 16:33:59.281903 RX_GATING_MODE = 2
633 16:33:59.281970 RX_GATING_TRACK_MODE = 2
634 16:33:59.282037 SELPH_MODE = 1
635 16:33:59.282103 PICG_EARLY_EN = 1
636 16:33:59.282170 VALID_LAT_VALUE = 1
637 16:33:59.282248 ==============================================================
638 16:33:59.282318 Enter into Gating configuration >>>>
639 16:33:59.282385 Exit from Gating configuration <<<<
640 16:33:59.282451 Enter into DVFS_PRE_config >>>>>
641 16:33:59.282518 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 16:33:59.282590 Exit from DVFS_PRE_config <<<<<
643 16:33:59.282657 Enter into PICG configuration >>>>
644 16:33:59.282724 Exit from PICG configuration <<<<
645 16:33:59.282791 [RX_INPUT] configuration >>>>>
646 16:33:59.282877 [RX_INPUT] configuration <<<<<
647 16:33:59.282975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 16:33:59.283045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 16:33:59.283113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 16:33:59.283196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 16:33:59.283264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 16:33:59.283337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 16:33:59.283408 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 16:33:59.283476 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 16:33:59.283555 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 16:33:59.283615 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 16:33:59.283675 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 16:33:59.283735 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 16:33:59.283795 ===================================
660 16:33:59.283868 LPDDR4 DRAM CONFIGURATION
661 16:33:59.283930 ===================================
662 16:33:59.283990 EX_ROW_EN[0] = 0x0
663 16:33:59.284050 EX_ROW_EN[1] = 0x0
664 16:33:59.284122 LP4Y_EN = 0x0
665 16:33:59.284186 WORK_FSP = 0x0
666 16:33:59.284246 WL = 0x2
667 16:33:59.284305 RL = 0x2
668 16:33:59.284364 BL = 0x2
669 16:33:59.284423 RPST = 0x0
670 16:33:59.284483 RD_PRE = 0x0
671 16:33:59.284541 WR_PRE = 0x1
672 16:33:59.284600 WR_PST = 0x0
673 16:33:59.284660 DBI_WR = 0x0
674 16:33:59.284720 DBI_RD = 0x0
675 16:33:59.284780 OTF = 0x1
676 16:33:59.284840 ===================================
677 16:33:59.284900 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 16:33:59.284961 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 16:33:59.285021 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 16:33:59.285081 ===================================
681 16:33:59.285140 LPDDR4 DRAM CONFIGURATION
682 16:33:59.285199 ===================================
683 16:33:59.285259 EX_ROW_EN[0] = 0x10
684 16:33:59.285318 EX_ROW_EN[1] = 0x0
685 16:33:59.285378 LP4Y_EN = 0x0
686 16:33:59.285438 WORK_FSP = 0x0
687 16:33:59.285497 WL = 0x2
688 16:33:59.285557 RL = 0x2
689 16:33:59.285615 BL = 0x2
690 16:33:59.285675 RPST = 0x0
691 16:33:59.285733 RD_PRE = 0x0
692 16:33:59.285791 WR_PRE = 0x1
693 16:33:59.285849 WR_PST = 0x0
694 16:33:59.285908 DBI_WR = 0x0
695 16:33:59.285967 DBI_RD = 0x0
696 16:33:59.286026 OTF = 0x1
697 16:33:59.286085 ===================================
698 16:33:59.286144 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 16:33:59.286204 nWR fixed to 40
700 16:33:59.286274 [ModeRegInit_LP4] CH0 RK0
701 16:33:59.286334 [ModeRegInit_LP4] CH0 RK1
702 16:33:59.286394 [ModeRegInit_LP4] CH1 RK0
703 16:33:59.286453 [ModeRegInit_LP4] CH1 RK1
704 16:33:59.286512 match AC timing 12
705 16:33:59.286572 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 16:33:59.286633 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 16:33:59.286894 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 16:33:59.286964 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 16:33:59.287026 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 16:33:59.287086 [EMI DOE] emi_dcm 0
711 16:33:59.287146 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 16:33:59.287207 ==
713 16:33:59.287267 Dram Type= 6, Freq= 0, CH_0, rank 0
714 16:33:59.287327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 16:33:59.287390 ==
716 16:33:59.287450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 16:33:59.287510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 16:33:59.287570 [CA 0] Center 37 (7~68) winsize 62
719 16:33:59.287629 [CA 1] Center 37 (7~68) winsize 62
720 16:33:59.287688 [CA 2] Center 35 (5~66) winsize 62
721 16:33:59.287747 [CA 3] Center 35 (5~66) winsize 62
722 16:33:59.287807 [CA 4] Center 34 (4~65) winsize 62
723 16:33:59.287866 [CA 5] Center 34 (4~65) winsize 62
724 16:33:59.287925
725 16:33:59.287984 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 16:33:59.288044
727 16:33:59.288103 [CATrainingPosCal] consider 1 rank data
728 16:33:59.288162 u2DelayCellTimex100 = 270/100 ps
729 16:33:59.288221 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
730 16:33:59.288281 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 16:33:59.288340 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 16:33:59.288400 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
733 16:33:59.288459 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 16:33:59.288531 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
735 16:33:59.288584
736 16:33:59.288637 CA PerBit enable=1, Macro0, CA PI delay=34
737 16:33:59.288690
738 16:33:59.288742 [CBTSetCACLKResult] CA Dly = 34
739 16:33:59.288795 CS Dly: 6 (0~37)
740 16:33:59.288848 ==
741 16:33:59.288901 Dram Type= 6, Freq= 0, CH_0, rank 1
742 16:33:59.288955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 16:33:59.289009 ==
744 16:33:59.289063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 16:33:59.289117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 16:33:59.289171 [CA 0] Center 37 (7~68) winsize 62
747 16:33:59.289224 [CA 1] Center 37 (6~68) winsize 63
748 16:33:59.289277 [CA 2] Center 35 (4~66) winsize 63
749 16:33:59.289329 [CA 3] Center 35 (4~66) winsize 63
750 16:33:59.289383 [CA 4] Center 34 (4~64) winsize 61
751 16:33:59.289436 [CA 5] Center 34 (3~65) winsize 63
752 16:33:59.289489
753 16:33:59.289542 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 16:33:59.289595
755 16:33:59.289648 [CATrainingPosCal] consider 2 rank data
756 16:33:59.289702 u2DelayCellTimex100 = 270/100 ps
757 16:33:59.289757 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
758 16:33:59.289811 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 16:33:59.289865 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 16:33:59.289919 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 16:33:59.289973 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
762 16:33:59.290027 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
763 16:33:59.290081
764 16:33:59.290134 CA PerBit enable=1, Macro0, CA PI delay=34
765 16:33:59.290188
766 16:33:59.290251 [CBTSetCACLKResult] CA Dly = 34
767 16:33:59.290305 CS Dly: 6 (0~37)
768 16:33:59.290359
769 16:33:59.290412 ----->DramcWriteLeveling(PI) begin...
770 16:33:59.290470 ==
771 16:33:59.290525 Dram Type= 6, Freq= 0, CH_0, rank 0
772 16:33:59.290579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 16:33:59.290633 ==
774 16:33:59.290687 Write leveling (Byte 0): 30 => 30
775 16:33:59.290740 Write leveling (Byte 1): 30 => 30
776 16:33:59.290794 DramcWriteLeveling(PI) end<-----
777 16:33:59.290847
778 16:33:59.290899 ==
779 16:33:59.290953 Dram Type= 6, Freq= 0, CH_0, rank 0
780 16:33:59.291007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 16:33:59.291061 ==
782 16:33:59.291114 [Gating] SW mode calibration
783 16:33:59.291168 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 16:33:59.291222 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 16:33:59.291276 0 6 0 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 0)
786 16:33:59.291330 0 6 4 | B1->B0 | 2828 2626 | 0 1 | (1 0) (1 0)
787 16:33:59.291384 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 16:33:59.291438 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 16:33:59.291491 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:33:59.291545 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:33:59.291598 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:33:59.291652 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:33:59.291705 0 7 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
794 16:33:59.291758 0 7 4 | B1->B0 | 3a3a 3d3d | 0 0 | (0 0) (0 0)
795 16:33:59.291812 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 16:33:59.291866 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 16:33:59.291920 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 16:33:59.291973 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 16:33:59.292027 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 16:33:59.292081 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 16:33:59.292134 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
802 16:33:59.292187 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
803 16:33:59.292240 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 16:33:59.292294 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 16:33:59.292348 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 16:33:59.292402 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 16:33:59.292455 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 16:33:59.292509 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 16:33:59.292562 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 16:33:59.292616 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 16:33:59.292669 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 16:33:59.292722 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 16:33:59.292776 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 16:33:59.293037 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 16:33:59.293099 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 16:33:59.293155 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 16:33:59.293209 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
818 16:33:59.293263 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
819 16:33:59.293317 Total UI for P1: 0, mck2ui 16
820 16:33:59.293371 best dqsien dly found for B0: ( 0, 10, 0)
821 16:33:59.293426 Total UI for P1: 0, mck2ui 16
822 16:33:59.293481 best dqsien dly found for B1: ( 0, 10, 0)
823 16:33:59.293534 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
824 16:33:59.293598 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
825 16:33:59.293647
826 16:33:59.293695 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
827 16:33:59.293745 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 16:33:59.293794 [Gating] SW calibration Done
829 16:33:59.293842 ==
830 16:33:59.293891 Dram Type= 6, Freq= 0, CH_0, rank 0
831 16:33:59.293940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
832 16:33:59.293989 ==
833 16:33:59.294038 RX Vref Scan: 0
834 16:33:59.294087
835 16:33:59.294136 RX Vref 0 -> 0, step: 1
836 16:33:59.294184
837 16:33:59.294240 RX Delay -130 -> 252, step: 16
838 16:33:59.294289 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
839 16:33:59.294338 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
840 16:33:59.294387 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
841 16:33:59.294436 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
842 16:33:59.294485 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
843 16:33:59.294534 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
844 16:33:59.294582 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
845 16:33:59.294631 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
846 16:33:59.294679 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
847 16:33:59.294728 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
848 16:33:59.294776 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
849 16:33:59.294825 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
850 16:33:59.294874 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
851 16:33:59.294922 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
852 16:33:59.294971 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
853 16:33:59.295020 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
854 16:33:59.295068 ==
855 16:33:59.295117 Dram Type= 6, Freq= 0, CH_0, rank 0
856 16:33:59.295166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
857 16:33:59.295215 ==
858 16:33:59.295264 DQS Delay:
859 16:33:59.295313 DQS0 = 0, DQS1 = 0
860 16:33:59.295361 DQM Delay:
861 16:33:59.295409 DQM0 = 83, DQM1 = 74
862 16:33:59.295457 DQ Delay:
863 16:33:59.295506 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
864 16:33:59.295555 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
865 16:33:59.295603 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
866 16:33:59.295652 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
867 16:33:59.295700
868 16:33:59.295748
869 16:33:59.295796 ==
870 16:33:59.295845 Dram Type= 6, Freq= 0, CH_0, rank 0
871 16:33:59.295894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
872 16:33:59.295943 ==
873 16:33:59.295992
874 16:33:59.296040
875 16:33:59.296087 TX Vref Scan disable
876 16:33:59.296135 == TX Byte 0 ==
877 16:33:59.296184 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
878 16:33:59.296233 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
879 16:33:59.296282 == TX Byte 1 ==
880 16:33:59.296331 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
881 16:33:59.296380 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
882 16:33:59.296428 ==
883 16:33:59.296477 Dram Type= 6, Freq= 0, CH_0, rank 0
884 16:33:59.296526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
885 16:33:59.296574 ==
886 16:33:59.296622 TX Vref=22, minBit 3, minWin=27, winSum=444
887 16:33:59.296671 TX Vref=24, minBit 4, minWin=27, winSum=450
888 16:33:59.296721 TX Vref=26, minBit 5, minWin=27, winSum=454
889 16:33:59.296770 TX Vref=28, minBit 1, minWin=28, winSum=456
890 16:33:59.296820 TX Vref=30, minBit 0, minWin=28, winSum=457
891 16:33:59.296869 TX Vref=32, minBit 0, minWin=28, winSum=454
892 16:33:59.296919 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
893 16:33:59.296968
894 16:33:59.297017 Final TX Range 1 Vref 30
895 16:33:59.297066
896 16:33:59.297114 ==
897 16:33:59.297163 Dram Type= 6, Freq= 0, CH_0, rank 0
898 16:33:59.297213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 16:33:59.297261 ==
900 16:33:59.297309
901 16:33:59.297357
902 16:33:59.297405 TX Vref Scan disable
903 16:33:59.297453 == TX Byte 0 ==
904 16:33:59.297501 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
905 16:33:59.297550 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
906 16:33:59.297598 == TX Byte 1 ==
907 16:33:59.297647 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
908 16:33:59.297695 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
909 16:33:59.297744
910 16:33:59.297791 [DATLAT]
911 16:33:59.297840 Freq=800, CH0 RK0
912 16:33:59.297888
913 16:33:59.297937 DATLAT Default: 0xa
914 16:33:59.297985 0, 0xFFFF, sum = 0
915 16:33:59.298034 1, 0xFFFF, sum = 0
916 16:33:59.298084 2, 0xFFFF, sum = 0
917 16:33:59.298133 3, 0xFFFF, sum = 0
918 16:33:59.298184 4, 0xFFFF, sum = 0
919 16:33:59.298238 5, 0xFFFF, sum = 0
920 16:33:59.298287 6, 0xFFFF, sum = 0
921 16:33:59.298337 7, 0xFFFF, sum = 0
922 16:33:59.298386 8, 0x0, sum = 1
923 16:33:59.298435 9, 0x0, sum = 2
924 16:33:59.298484 10, 0x0, sum = 3
925 16:33:59.298547 11, 0x0, sum = 4
926 16:33:59.298596 best_step = 9
927 16:33:59.298644
928 16:33:59.298691 ==
929 16:33:59.298739 Dram Type= 6, Freq= 0, CH_0, rank 0
930 16:33:59.298788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
931 16:33:59.298836 ==
932 16:33:59.298883 RX Vref Scan: 1
933 16:33:59.298930
934 16:33:59.298977 Set Vref Range= 32 -> 127
935 16:33:59.299025
936 16:33:59.299072 RX Vref 32 -> 127, step: 1
937 16:33:59.299119
938 16:33:59.299166 RX Delay -95 -> 252, step: 8
939 16:33:59.299213
940 16:33:59.299261 Set Vref, RX VrefLevel [Byte0]: 32
941 16:33:59.299309 [Byte1]: 32
942 16:33:59.299357
943 16:33:59.299404 Set Vref, RX VrefLevel [Byte0]: 33
944 16:33:59.299451 [Byte1]: 33
945 16:33:59.299499
946 16:33:59.299547 Set Vref, RX VrefLevel [Byte0]: 34
947 16:33:59.299595 [Byte1]: 34
948 16:33:59.299642
949 16:33:59.299689 Set Vref, RX VrefLevel [Byte0]: 35
950 16:33:59.299737 [Byte1]: 35
951 16:33:59.299784
952 16:33:59.299831 Set Vref, RX VrefLevel [Byte0]: 36
953 16:33:59.299878 [Byte1]: 36
954 16:33:59.299925
955 16:33:59.299973 Set Vref, RX VrefLevel [Byte0]: 37
956 16:33:59.300020 [Byte1]: 37
957 16:33:59.300067
958 16:33:59.300114 Set Vref, RX VrefLevel [Byte0]: 38
959 16:33:59.300161 [Byte1]: 38
960 16:33:59.300209
961 16:33:59.300256 Set Vref, RX VrefLevel [Byte0]: 39
962 16:33:59.300304 [Byte1]: 39
963 16:33:59.300351
964 16:33:59.300590 Set Vref, RX VrefLevel [Byte0]: 40
965 16:33:59.300648 [Byte1]: 40
966 16:33:59.300697
967 16:33:59.300745 Set Vref, RX VrefLevel [Byte0]: 41
968 16:33:59.300796 [Byte1]: 41
969 16:33:59.300843
970 16:33:59.300891 Set Vref, RX VrefLevel [Byte0]: 42
971 16:33:59.300938 [Byte1]: 42
972 16:33:59.300986
973 16:33:59.301033 Set Vref, RX VrefLevel [Byte0]: 43
974 16:33:59.301081 [Byte1]: 43
975 16:33:59.301128
976 16:33:59.301175 Set Vref, RX VrefLevel [Byte0]: 44
977 16:33:59.301223 [Byte1]: 44
978 16:33:59.301270
979 16:33:59.301316 Set Vref, RX VrefLevel [Byte0]: 45
980 16:33:59.301364 [Byte1]: 45
981 16:33:59.301411
982 16:33:59.301458 Set Vref, RX VrefLevel [Byte0]: 46
983 16:33:59.301505 [Byte1]: 46
984 16:33:59.301553
985 16:33:59.301600 Set Vref, RX VrefLevel [Byte0]: 47
986 16:33:59.301648 [Byte1]: 47
987 16:33:59.301695
988 16:33:59.301742 Set Vref, RX VrefLevel [Byte0]: 48
989 16:33:59.301789 [Byte1]: 48
990 16:33:59.301836
991 16:33:59.301883 Set Vref, RX VrefLevel [Byte0]: 49
992 16:33:59.301930 [Byte1]: 49
993 16:33:59.301976
994 16:33:59.302024 Set Vref, RX VrefLevel [Byte0]: 50
995 16:33:59.302071 [Byte1]: 50
996 16:33:59.302118
997 16:33:59.302165 Set Vref, RX VrefLevel [Byte0]: 51
998 16:33:59.302220 [Byte1]: 51
999 16:33:59.302301
1000 16:33:59.302349 Set Vref, RX VrefLevel [Byte0]: 52
1001 16:33:59.302396 [Byte1]: 52
1002 16:33:59.302443
1003 16:33:59.302490 Set Vref, RX VrefLevel [Byte0]: 53
1004 16:33:59.302537 [Byte1]: 53
1005 16:33:59.302585
1006 16:33:59.302632 Set Vref, RX VrefLevel [Byte0]: 54
1007 16:33:59.302679 [Byte1]: 54
1008 16:33:59.302726
1009 16:33:59.302774 Set Vref, RX VrefLevel [Byte0]: 55
1010 16:33:59.302822 [Byte1]: 55
1011 16:33:59.302869
1012 16:33:59.302916 Set Vref, RX VrefLevel [Byte0]: 56
1013 16:33:59.302964 [Byte1]: 56
1014 16:33:59.303011
1015 16:33:59.303059 Set Vref, RX VrefLevel [Byte0]: 57
1016 16:33:59.303107 [Byte1]: 57
1017 16:33:59.303155
1018 16:33:59.303202 Set Vref, RX VrefLevel [Byte0]: 58
1019 16:33:59.303249 [Byte1]: 58
1020 16:33:59.303296
1021 16:33:59.303343 Set Vref, RX VrefLevel [Byte0]: 59
1022 16:33:59.303392 [Byte1]: 59
1023 16:33:59.303440
1024 16:33:59.303487 Set Vref, RX VrefLevel [Byte0]: 60
1025 16:33:59.303535 [Byte1]: 60
1026 16:33:59.303582
1027 16:33:59.303629 Set Vref, RX VrefLevel [Byte0]: 61
1028 16:33:59.303676 [Byte1]: 61
1029 16:33:59.303723
1030 16:33:59.303771 Set Vref, RX VrefLevel [Byte0]: 62
1031 16:33:59.303818 [Byte1]: 62
1032 16:33:59.303866
1033 16:33:59.303912 Set Vref, RX VrefLevel [Byte0]: 63
1034 16:33:59.303960 [Byte1]: 63
1035 16:33:59.304007
1036 16:33:59.304054 Set Vref, RX VrefLevel [Byte0]: 64
1037 16:33:59.304102 [Byte1]: 64
1038 16:33:59.304149
1039 16:33:59.304196 Set Vref, RX VrefLevel [Byte0]: 65
1040 16:33:59.304244 [Byte1]: 65
1041 16:33:59.304291
1042 16:33:59.304337 Set Vref, RX VrefLevel [Byte0]: 66
1043 16:33:59.304384 [Byte1]: 66
1044 16:33:59.304432
1045 16:33:59.304479 Set Vref, RX VrefLevel [Byte0]: 67
1046 16:33:59.304526 [Byte1]: 67
1047 16:33:59.304573
1048 16:33:59.304620 Set Vref, RX VrefLevel [Byte0]: 68
1049 16:33:59.304667 [Byte1]: 68
1050 16:33:59.304714
1051 16:33:59.304761 Set Vref, RX VrefLevel [Byte0]: 69
1052 16:33:59.304808 [Byte1]: 69
1053 16:33:59.304855
1054 16:33:59.304902 Set Vref, RX VrefLevel [Byte0]: 70
1055 16:33:59.304950 [Byte1]: 70
1056 16:33:59.304997
1057 16:33:59.305043 Set Vref, RX VrefLevel [Byte0]: 71
1058 16:33:59.305091 [Byte1]: 71
1059 16:33:59.305138
1060 16:33:59.305185 Set Vref, RX VrefLevel [Byte0]: 72
1061 16:33:59.305232 [Byte1]: 72
1062 16:33:59.305279
1063 16:33:59.305325 Set Vref, RX VrefLevel [Byte0]: 73
1064 16:33:59.305372 [Byte1]: 73
1065 16:33:59.305420
1066 16:33:59.305467 Set Vref, RX VrefLevel [Byte0]: 74
1067 16:33:59.305514 [Byte1]: 74
1068 16:33:59.305575
1069 16:33:59.305623 Final RX Vref Byte 0 = 53 to rank0
1070 16:33:59.305672 Final RX Vref Byte 1 = 54 to rank0
1071 16:33:59.305720 Final RX Vref Byte 0 = 53 to rank1
1072 16:33:59.305779 Final RX Vref Byte 1 = 54 to rank1==
1073 16:33:59.305827 Dram Type= 6, Freq= 0, CH_0, rank 0
1074 16:33:59.305880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1075 16:33:59.305928 ==
1076 16:33:59.305976 DQS Delay:
1077 16:33:59.306022 DQS0 = 0, DQS1 = 0
1078 16:33:59.306072 DQM Delay:
1079 16:33:59.306119 DQM0 = 83, DQM1 = 73
1080 16:33:59.306167 DQ Delay:
1081 16:33:59.306217 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1082 16:33:59.306300 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1083 16:33:59.306348 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1084 16:33:59.306395 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1085 16:33:59.306443
1086 16:33:59.306491
1087 16:33:59.306538 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1088 16:33:59.306587 CH0 RK0: MR19=606, MR18=3C3C
1089 16:33:59.306635 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1090 16:33:59.306683
1091 16:33:59.306729 ----->DramcWriteLeveling(PI) begin...
1092 16:33:59.306777 ==
1093 16:33:59.306825 Dram Type= 6, Freq= 0, CH_0, rank 1
1094 16:33:59.306874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1095 16:33:59.306922 ==
1096 16:33:59.306969 Write leveling (Byte 0): 30 => 30
1097 16:33:59.307017 Write leveling (Byte 1): 30 => 30
1098 16:33:59.307064 DramcWriteLeveling(PI) end<-----
1099 16:33:59.307111
1100 16:33:59.307158 ==
1101 16:33:59.307205 Dram Type= 6, Freq= 0, CH_0, rank 1
1102 16:33:59.307256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1103 16:33:59.307304 ==
1104 16:33:59.307351 [Gating] SW mode calibration
1105 16:33:59.307399 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1106 16:33:59.307448 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1107 16:33:59.307496 0 6 0 | B1->B0 | 3333 2f2f | 1 1 | (0 1) (1 1)
1108 16:33:59.307544 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1109 16:33:59.307592 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 16:33:59.307639 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 16:33:59.307687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 16:33:59.307928 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 16:33:59.307984 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 16:33:59.308033 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 16:33:59.308081 0 7 0 | B1->B0 | 2d2d 2b2b | 0 1 | (1 1) (0 0)
1116 16:33:59.308132 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1117 16:33:59.308180 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 16:33:59.308228 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 16:33:59.308276 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 16:33:59.308324 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 16:33:59.308371 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 16:33:59.308420 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 16:33:59.308467 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1124 16:33:59.308515 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 16:33:59.308562 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 16:33:59.308609 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 16:33:59.308657 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 16:33:59.308705 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 16:33:59.308753 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 16:33:59.308800 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 16:33:59.308848 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 16:33:59.308896 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 16:33:59.308943 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 16:33:59.308990 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 16:33:59.309038 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 16:33:59.309093 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 16:33:59.309161 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 16:33:59.309234 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 16:33:59.309305 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1140 16:33:59.309383 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1141 16:33:59.309458 Total UI for P1: 0, mck2ui 16
1142 16:33:59.309529 best dqsien dly found for B0: ( 0, 10, 2)
1143 16:33:59.309604 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1144 16:33:59.309657 Total UI for P1: 0, mck2ui 16
1145 16:33:59.309707 best dqsien dly found for B1: ( 0, 10, 2)
1146 16:33:59.309756 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1147 16:33:59.309805 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1148 16:33:59.309852
1149 16:33:59.309900 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1150 16:33:59.309948 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1151 16:33:59.309996 [Gating] SW calibration Done
1152 16:33:59.310044 ==
1153 16:33:59.310091 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 16:33:59.310139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1155 16:33:59.310187 ==
1156 16:33:59.310270 RX Vref Scan: 0
1157 16:33:59.310335
1158 16:33:59.310382 RX Vref 0 -> 0, step: 1
1159 16:33:59.310429
1160 16:33:59.310476 RX Delay -130 -> 252, step: 16
1161 16:33:59.310524 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1162 16:33:59.310571 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1163 16:33:59.310620 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1164 16:33:59.310667 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1165 16:33:59.310714 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1166 16:33:59.310762 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1167 16:33:59.310809 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1168 16:33:59.310856 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1169 16:33:59.310904 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1170 16:33:59.310951 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1171 16:33:59.310999 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1172 16:33:59.311046 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1173 16:33:59.311093 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1174 16:33:59.311141 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1175 16:33:59.311188 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1176 16:33:59.311235 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1177 16:33:59.311284 ==
1178 16:33:59.311331 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 16:33:59.311379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1180 16:33:59.311426 ==
1181 16:33:59.311481 DQS Delay:
1182 16:33:59.311534 DQS0 = 0, DQS1 = 0
1183 16:33:59.311582 DQM Delay:
1184 16:33:59.311629 DQM0 = 83, DQM1 = 71
1185 16:33:59.311676 DQ Delay:
1186 16:33:59.311724 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =69
1187 16:33:59.311772 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
1188 16:33:59.311820 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1189 16:33:59.311867 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =77
1190 16:33:59.311915
1191 16:33:59.311962
1192 16:33:59.312009 ==
1193 16:33:59.312056 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 16:33:59.312104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1195 16:33:59.312151 ==
1196 16:33:59.312199
1197 16:33:59.312245
1198 16:33:59.312292 TX Vref Scan disable
1199 16:33:59.312339 == TX Byte 0 ==
1200 16:33:59.312386 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1201 16:33:59.312434 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1202 16:33:59.312482 == TX Byte 1 ==
1203 16:33:59.312529 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1204 16:33:59.312576 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1205 16:33:59.312624 ==
1206 16:33:59.312671 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 16:33:59.312719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1208 16:33:59.312766 ==
1209 16:33:59.312813 TX Vref=22, minBit 0, minWin=27, winSum=446
1210 16:33:59.312861 TX Vref=24, minBit 2, minWin=28, winSum=456
1211 16:33:59.312909 TX Vref=26, minBit 2, minWin=28, winSum=456
1212 16:33:59.312956 TX Vref=28, minBit 4, minWin=28, winSum=459
1213 16:33:59.313004 TX Vref=30, minBit 2, minWin=28, winSum=458
1214 16:33:59.313052 TX Vref=32, minBit 0, minWin=28, winSum=458
1215 16:33:59.313100 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1216 16:33:59.313147
1217 16:33:59.313195 Final TX Range 1 Vref 28
1218 16:33:59.313242
1219 16:33:59.313290 ==
1220 16:33:59.313337 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 16:33:59.313385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 16:33:59.313433 ==
1223 16:33:59.313479
1224 16:33:59.313526
1225 16:33:59.313572 TX Vref Scan disable
1226 16:33:59.313620 == TX Byte 0 ==
1227 16:33:59.313668 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1228 16:33:59.313910 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1229 16:33:59.313964 == TX Byte 1 ==
1230 16:33:59.314013 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1231 16:33:59.314061 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1232 16:33:59.314109
1233 16:33:59.314157 [DATLAT]
1234 16:33:59.314204 Freq=800, CH0 RK1
1235 16:33:59.314290
1236 16:33:59.314338 DATLAT Default: 0x9
1237 16:33:59.314386 0, 0xFFFF, sum = 0
1238 16:33:59.314435 1, 0xFFFF, sum = 0
1239 16:33:59.314483 2, 0xFFFF, sum = 0
1240 16:33:59.314531 3, 0xFFFF, sum = 0
1241 16:33:59.314580 4, 0xFFFF, sum = 0
1242 16:33:59.314628 5, 0xFFFF, sum = 0
1243 16:33:59.314676 6, 0xFFFF, sum = 0
1244 16:33:59.314724 7, 0xFFFF, sum = 0
1245 16:33:59.314771 8, 0x0, sum = 1
1246 16:33:59.314819 9, 0x0, sum = 2
1247 16:33:59.314868 10, 0x0, sum = 3
1248 16:33:59.314915 11, 0x0, sum = 4
1249 16:33:59.314962 best_step = 9
1250 16:33:59.315010
1251 16:33:59.315057 ==
1252 16:33:59.315104 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 16:33:59.315152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1254 16:33:59.315200 ==
1255 16:33:59.315247 RX Vref Scan: 0
1256 16:33:59.315294
1257 16:33:59.315341 RX Vref 0 -> 0, step: 1
1258 16:33:59.315388
1259 16:33:59.315434 RX Delay -111 -> 252, step: 8
1260 16:33:59.315482 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1261 16:33:59.315531 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1262 16:33:59.315579 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1263 16:33:59.315626 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1264 16:33:59.315674 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1265 16:33:59.315721 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1266 16:33:59.315769 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1267 16:33:59.315816 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1268 16:33:59.315863 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1269 16:33:59.315910 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1270 16:33:59.315958 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1271 16:33:59.316005 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1272 16:33:59.316052 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1273 16:33:59.316099 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1274 16:33:59.316147 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1275 16:33:59.316195 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1276 16:33:59.316241 ==
1277 16:33:59.316288 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 16:33:59.316336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 16:33:59.316384 ==
1280 16:33:59.316432 DQS Delay:
1281 16:33:59.316479 DQS0 = 0, DQS1 = 0
1282 16:33:59.316526 DQM Delay:
1283 16:33:59.316573 DQM0 = 85, DQM1 = 73
1284 16:33:59.316620 DQ Delay:
1285 16:33:59.316668 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1286 16:33:59.316715 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1287 16:33:59.316762 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1288 16:33:59.316809 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1289 16:33:59.316856
1290 16:33:59.316903
1291 16:33:59.316951 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1292 16:33:59.317000 CH0 RK1: MR19=606, MR18=4343
1293 16:33:59.317048 CH0_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1294 16:33:59.317095 [RxdqsGatingPostProcess] freq 800
1295 16:33:59.317143 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1296 16:33:59.317190 Pre-setting of DQS Precalculation
1297 16:33:59.317237 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1298 16:33:59.317284 ==
1299 16:33:59.317332 Dram Type= 6, Freq= 0, CH_1, rank 0
1300 16:33:59.317379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1301 16:33:59.317427 ==
1302 16:33:59.317474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1303 16:33:59.317522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1304 16:33:59.317570 [CA 0] Center 36 (6~67) winsize 62
1305 16:33:59.317617 [CA 1] Center 36 (6~67) winsize 62
1306 16:33:59.317664 [CA 2] Center 34 (4~65) winsize 62
1307 16:33:59.317710 [CA 3] Center 34 (4~65) winsize 62
1308 16:33:59.317758 [CA 4] Center 33 (2~64) winsize 63
1309 16:33:59.317805 [CA 5] Center 33 (3~64) winsize 62
1310 16:33:59.317852
1311 16:33:59.317898 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1312 16:33:59.317945
1313 16:33:59.317992 [CATrainingPosCal] consider 1 rank data
1314 16:33:59.318040 u2DelayCellTimex100 = 270/100 ps
1315 16:33:59.318086 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1316 16:33:59.318133 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1317 16:33:59.318180 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1318 16:33:59.318254 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 16:33:59.318316 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1320 16:33:59.318363 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 16:33:59.318410
1322 16:33:59.318456 CA PerBit enable=1, Macro0, CA PI delay=33
1323 16:33:59.318504
1324 16:33:59.318550 [CBTSetCACLKResult] CA Dly = 33
1325 16:33:59.318596 CS Dly: 5 (0~36)
1326 16:33:59.318643 ==
1327 16:33:59.318690 Dram Type= 6, Freq= 0, CH_1, rank 1
1328 16:33:59.318737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1329 16:33:59.318784 ==
1330 16:33:59.318831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1331 16:33:59.318879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1332 16:33:59.318928 [CA 0] Center 36 (6~67) winsize 62
1333 16:33:59.318975 [CA 1] Center 36 (5~67) winsize 63
1334 16:33:59.319022 [CA 2] Center 34 (4~65) winsize 62
1335 16:33:59.319068 [CA 3] Center 34 (3~65) winsize 63
1336 16:33:59.319115 [CA 4] Center 33 (3~64) winsize 62
1337 16:33:59.319161 [CA 5] Center 33 (3~63) winsize 61
1338 16:33:59.319209
1339 16:33:59.319255 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1340 16:33:59.319302
1341 16:33:59.319349 [CATrainingPosCal] consider 2 rank data
1342 16:33:59.319396 u2DelayCellTimex100 = 270/100 ps
1343 16:33:59.319443 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1344 16:33:59.319490 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1345 16:33:59.319537 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1346 16:33:59.319584 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 16:33:59.319632 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1348 16:33:59.319679 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1349 16:33:59.319725
1350 16:33:59.319771 CA PerBit enable=1, Macro0, CA PI delay=33
1351 16:33:59.319818
1352 16:33:59.319864 [CBTSetCACLKResult] CA Dly = 33
1353 16:33:59.319911 CS Dly: 5 (0~36)
1354 16:33:59.319957
1355 16:33:59.320003 ----->DramcWriteLeveling(PI) begin...
1356 16:33:59.320050 ==
1357 16:33:59.320096 Dram Type= 6, Freq= 0, CH_1, rank 0
1358 16:33:59.320143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 16:33:59.320191 ==
1360 16:33:59.320238 Write leveling (Byte 0): 23 => 23
1361 16:33:59.320476 Write leveling (Byte 1): 22 => 22
1362 16:33:59.320532 DramcWriteLeveling(PI) end<-----
1363 16:33:59.320580
1364 16:33:59.320627 ==
1365 16:33:59.320674 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 16:33:59.320722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 16:33:59.320770 ==
1368 16:33:59.320817 [Gating] SW mode calibration
1369 16:33:59.320864 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1370 16:33:59.320913 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1371 16:33:59.320960 0 6 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1372 16:33:59.321008 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 16:33:59.321056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 16:33:59.321104 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 16:33:59.321151 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 16:33:59.321198 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 16:33:59.321245 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 16:33:59.321292 0 6 28 | B1->B0 | 2525 2d2d | 0 1 | (0 0) (0 0)
1379 16:33:59.321340 0 7 0 | B1->B0 | 2f2f 4444 | 0 0 | (1 1) (0 0)
1380 16:33:59.321386 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 16:33:59.321433 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 16:33:59.321480 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 16:33:59.321527 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 16:33:59.321574 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 16:33:59.321622 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 16:33:59.321669 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 16:33:59.321716 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1388 16:33:59.321763 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 16:33:59.321810 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 16:33:59.321856 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 16:33:59.321903 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 16:33:59.321950 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 16:33:59.321997 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 16:33:59.322044 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 16:33:59.322091 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 16:33:59.322138 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 16:33:59.322185 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 16:33:59.322242 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 16:33:59.322289 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 16:33:59.322336 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 16:33:59.322383 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 16:33:59.322430 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 16:33:59.322477 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1404 16:33:59.322524 Total UI for P1: 0, mck2ui 16
1405 16:33:59.322572 best dqsien dly found for B0: ( 0, 9, 30)
1406 16:33:59.322620 Total UI for P1: 0, mck2ui 16
1407 16:33:59.322667 best dqsien dly found for B1: ( 0, 9, 30)
1408 16:33:59.322714 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1409 16:33:59.322761 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1410 16:33:59.322808
1411 16:33:59.322854 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1412 16:33:59.322902 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1413 16:33:59.322949 [Gating] SW calibration Done
1414 16:33:59.322995 ==
1415 16:33:59.323043 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 16:33:59.323090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1417 16:33:59.323136 ==
1418 16:33:59.323182 RX Vref Scan: 0
1419 16:33:59.323229
1420 16:33:59.323276 RX Vref 0 -> 0, step: 1
1421 16:33:59.323323
1422 16:33:59.323370 RX Delay -130 -> 252, step: 16
1423 16:33:59.323417 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1424 16:33:59.323464 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1425 16:33:59.323511 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1426 16:33:59.323558 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1427 16:33:59.323604 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1428 16:33:59.323651 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1429 16:33:59.323698 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1430 16:33:59.323746 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1431 16:33:59.323793 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1432 16:33:59.323840 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1433 16:33:59.323887 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1434 16:33:59.323934 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1435 16:33:59.323981 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1436 16:33:59.324027 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1437 16:33:59.324074 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1438 16:33:59.324121 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1439 16:33:59.324168 ==
1440 16:33:59.324215 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 16:33:59.324261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1442 16:33:59.324309 ==
1443 16:33:59.324356 DQS Delay:
1444 16:33:59.324404 DQS0 = 0, DQS1 = 0
1445 16:33:59.324451 DQM Delay:
1446 16:33:59.324498 DQM0 = 81, DQM1 = 71
1447 16:33:59.324544 DQ Delay:
1448 16:33:59.324591 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1449 16:33:59.324638 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1450 16:33:59.324685 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1451 16:33:59.324732 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1452 16:33:59.324780
1453 16:33:59.324840
1454 16:33:59.324889 ==
1455 16:33:59.324936 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 16:33:59.324983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1457 16:33:59.325043 ==
1458 16:33:59.325093
1459 16:33:59.325141
1460 16:33:59.325188 TX Vref Scan disable
1461 16:33:59.325235 == TX Byte 0 ==
1462 16:33:59.325282 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1463 16:33:59.325330 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1464 16:33:59.325377 == TX Byte 1 ==
1465 16:33:59.325425 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1466 16:33:59.325472 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1467 16:33:59.325519 ==
1468 16:33:59.325566 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 16:33:59.325614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1470 16:33:59.325661 ==
1471 16:33:59.325709 TX Vref=22, minBit 0, minWin=28, winSum=455
1472 16:33:59.325946 TX Vref=24, minBit 3, minWin=28, winSum=459
1473 16:33:59.326000 TX Vref=26, minBit 2, minWin=28, winSum=462
1474 16:33:59.326048 TX Vref=28, minBit 0, minWin=28, winSum=460
1475 16:33:59.326096 TX Vref=30, minBit 9, minWin=28, winSum=463
1476 16:33:59.326144 TX Vref=32, minBit 9, minWin=28, winSum=463
1477 16:33:59.326192 [TxChooseVref] Worse bit 9, Min win 28, Win sum 463, Final Vref 30
1478 16:33:59.326265
1479 16:33:59.326344 Final TX Range 1 Vref 30
1480 16:33:59.326405
1481 16:33:59.326452 ==
1482 16:33:59.326531 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 16:33:59.326577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1484 16:33:59.326625 ==
1485 16:33:59.326672
1486 16:33:59.326719
1487 16:33:59.326767 TX Vref Scan disable
1488 16:33:59.326814 == TX Byte 0 ==
1489 16:33:59.326861 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1490 16:33:59.326912 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1491 16:33:59.326959 == TX Byte 1 ==
1492 16:33:59.327006 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1493 16:33:59.327054 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1494 16:33:59.327104
1495 16:33:59.327152 [DATLAT]
1496 16:33:59.327198 Freq=800, CH1 RK0
1497 16:33:59.327246
1498 16:33:59.327294 DATLAT Default: 0xa
1499 16:33:59.327341 0, 0xFFFF, sum = 0
1500 16:33:59.327390 1, 0xFFFF, sum = 0
1501 16:33:59.327438 2, 0xFFFF, sum = 0
1502 16:33:59.327487 3, 0xFFFF, sum = 0
1503 16:33:59.327534 4, 0xFFFF, sum = 0
1504 16:33:59.327581 5, 0xFFFF, sum = 0
1505 16:33:59.327629 6, 0xFFFF, sum = 0
1506 16:33:59.327681 7, 0xFFFF, sum = 0
1507 16:33:59.327728 8, 0x0, sum = 1
1508 16:33:59.327776 9, 0x0, sum = 2
1509 16:33:59.327824 10, 0x0, sum = 3
1510 16:33:59.327875 11, 0x0, sum = 4
1511 16:33:59.327924 best_step = 9
1512 16:33:59.327971
1513 16:33:59.328025 ==
1514 16:33:59.328074 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 16:33:59.328121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1516 16:33:59.328169 ==
1517 16:33:59.328219 RX Vref Scan: 1
1518 16:33:59.328268
1519 16:33:59.328315 Set Vref Range= 32 -> 127
1520 16:33:59.328361
1521 16:33:59.328410 RX Vref 32 -> 127, step: 1
1522 16:33:59.328458
1523 16:33:59.328504 RX Delay -111 -> 252, step: 8
1524 16:33:59.328551
1525 16:33:59.328597 Set Vref, RX VrefLevel [Byte0]: 32
1526 16:33:59.328645 [Byte1]: 32
1527 16:33:59.328693
1528 16:33:59.328739 Set Vref, RX VrefLevel [Byte0]: 33
1529 16:33:59.328786 [Byte1]: 33
1530 16:33:59.328834
1531 16:33:59.328880 Set Vref, RX VrefLevel [Byte0]: 34
1532 16:33:59.328927 [Byte1]: 34
1533 16:33:59.328974
1534 16:33:59.329021 Set Vref, RX VrefLevel [Byte0]: 35
1535 16:33:59.329069 [Byte1]: 35
1536 16:33:59.329115
1537 16:33:59.329161 Set Vref, RX VrefLevel [Byte0]: 36
1538 16:33:59.329208 [Byte1]: 36
1539 16:33:59.329255
1540 16:33:59.329302 Set Vref, RX VrefLevel [Byte0]: 37
1541 16:33:59.329349 [Byte1]: 37
1542 16:33:59.329396
1543 16:33:59.329443 Set Vref, RX VrefLevel [Byte0]: 38
1544 16:33:59.329490 [Byte1]: 38
1545 16:33:59.329538
1546 16:33:59.329584 Set Vref, RX VrefLevel [Byte0]: 39
1547 16:33:59.329631 [Byte1]: 39
1548 16:33:59.329678
1549 16:33:59.329724 Set Vref, RX VrefLevel [Byte0]: 40
1550 16:33:59.329772 [Byte1]: 40
1551 16:33:59.329819
1552 16:33:59.329864 Set Vref, RX VrefLevel [Byte0]: 41
1553 16:33:59.329911 [Byte1]: 41
1554 16:33:59.329958
1555 16:33:59.330005 Set Vref, RX VrefLevel [Byte0]: 42
1556 16:33:59.330052 [Byte1]: 42
1557 16:33:59.330099
1558 16:33:59.330145 Set Vref, RX VrefLevel [Byte0]: 43
1559 16:33:59.330192 [Byte1]: 43
1560 16:33:59.330247
1561 16:33:59.330302 Set Vref, RX VrefLevel [Byte0]: 44
1562 16:33:59.330349 [Byte1]: 44
1563 16:33:59.330396
1564 16:33:59.330443 Set Vref, RX VrefLevel [Byte0]: 45
1565 16:33:59.330491 [Byte1]: 45
1566 16:33:59.330538
1567 16:33:59.330586 Set Vref, RX VrefLevel [Byte0]: 46
1568 16:33:59.330633 [Byte1]: 46
1569 16:33:59.330680
1570 16:33:59.330727 Set Vref, RX VrefLevel [Byte0]: 47
1571 16:33:59.330774 [Byte1]: 47
1572 16:33:59.330821
1573 16:33:59.330867 Set Vref, RX VrefLevel [Byte0]: 48
1574 16:33:59.330916 [Byte1]: 48
1575 16:33:59.330963
1576 16:33:59.331010 Set Vref, RX VrefLevel [Byte0]: 49
1577 16:33:59.331057 [Byte1]: 49
1578 16:33:59.331105
1579 16:33:59.331152 Set Vref, RX VrefLevel [Byte0]: 50
1580 16:33:59.331200 [Byte1]: 50
1581 16:33:59.331246
1582 16:33:59.331293 Set Vref, RX VrefLevel [Byte0]: 51
1583 16:33:59.331340 [Byte1]: 51
1584 16:33:59.331387
1585 16:33:59.331434 Set Vref, RX VrefLevel [Byte0]: 52
1586 16:33:59.331481 [Byte1]: 52
1587 16:33:59.331528
1588 16:33:59.331574 Set Vref, RX VrefLevel [Byte0]: 53
1589 16:33:59.331622 [Byte1]: 53
1590 16:33:59.331669
1591 16:33:59.331715 Set Vref, RX VrefLevel [Byte0]: 54
1592 16:33:59.331762 [Byte1]: 54
1593 16:33:59.331808
1594 16:33:59.331854 Set Vref, RX VrefLevel [Byte0]: 55
1595 16:33:59.331901 [Byte1]: 55
1596 16:33:59.331948
1597 16:33:59.331995 Set Vref, RX VrefLevel [Byte0]: 56
1598 16:33:59.332042 [Byte1]: 56
1599 16:33:59.332088
1600 16:33:59.332134 Set Vref, RX VrefLevel [Byte0]: 57
1601 16:33:59.332182 [Byte1]: 57
1602 16:33:59.332229
1603 16:33:59.332275 Set Vref, RX VrefLevel [Byte0]: 58
1604 16:33:59.332322 [Byte1]: 58
1605 16:33:59.332369
1606 16:33:59.332416 Set Vref, RX VrefLevel [Byte0]: 59
1607 16:33:59.332464 [Byte1]: 59
1608 16:33:59.332510
1609 16:33:59.332557 Set Vref, RX VrefLevel [Byte0]: 60
1610 16:33:59.332604 [Byte1]: 60
1611 16:33:59.332651
1612 16:33:59.332698 Set Vref, RX VrefLevel [Byte0]: 61
1613 16:33:59.332745 [Byte1]: 61
1614 16:33:59.332791
1615 16:33:59.332838 Set Vref, RX VrefLevel [Byte0]: 62
1616 16:33:59.332886 [Byte1]: 62
1617 16:33:59.332933
1618 16:33:59.332980 Set Vref, RX VrefLevel [Byte0]: 63
1619 16:33:59.333026 [Byte1]: 63
1620 16:33:59.333073
1621 16:33:59.333120 Set Vref, RX VrefLevel [Byte0]: 64
1622 16:33:59.333166 [Byte1]: 64
1623 16:33:59.333213
1624 16:33:59.333259 Set Vref, RX VrefLevel [Byte0]: 65
1625 16:33:59.333306 [Byte1]: 65
1626 16:33:59.333354
1627 16:33:59.333400 Set Vref, RX VrefLevel [Byte0]: 66
1628 16:33:59.333447 [Byte1]: 66
1629 16:33:59.333494
1630 16:33:59.333541 Set Vref, RX VrefLevel [Byte0]: 67
1631 16:33:59.333589 [Byte1]: 67
1632 16:33:59.333635
1633 16:33:59.333682 Set Vref, RX VrefLevel [Byte0]: 68
1634 16:33:59.333729 [Byte1]: 68
1635 16:33:59.333777
1636 16:33:59.333824 Set Vref, RX VrefLevel [Byte0]: 69
1637 16:33:59.333871 [Byte1]: 69
1638 16:33:59.333918
1639 16:33:59.334152 Set Vref, RX VrefLevel [Byte0]: 70
1640 16:33:59.334205 [Byte1]: 70
1641 16:33:59.334297
1642 16:33:59.334347 Set Vref, RX VrefLevel [Byte0]: 71
1643 16:33:59.334394 [Byte1]: 71
1644 16:33:59.334442
1645 16:33:59.334489 Set Vref, RX VrefLevel [Byte0]: 72
1646 16:33:59.334537 [Byte1]: 72
1647 16:33:59.334584
1648 16:33:59.334630 Set Vref, RX VrefLevel [Byte0]: 73
1649 16:33:59.334678 [Byte1]: 73
1650 16:33:59.334724
1651 16:33:59.334771 Set Vref, RX VrefLevel [Byte0]: 74
1652 16:33:59.334818 [Byte1]: 74
1653 16:33:59.334865
1654 16:33:59.334911 Final RX Vref Byte 0 = 59 to rank0
1655 16:33:59.334959 Final RX Vref Byte 1 = 53 to rank0
1656 16:33:59.335006 Final RX Vref Byte 0 = 59 to rank1
1657 16:33:59.335053 Final RX Vref Byte 1 = 53 to rank1==
1658 16:33:59.335101 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 16:33:59.335149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1660 16:33:59.335196 ==
1661 16:33:59.335242 DQS Delay:
1662 16:33:59.335289 DQS0 = 0, DQS1 = 0
1663 16:33:59.335336 DQM Delay:
1664 16:33:59.335383 DQM0 = 79, DQM1 = 72
1665 16:33:59.335429 DQ Delay:
1666 16:33:59.335476 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1667 16:33:59.335523 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1668 16:33:59.335570 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1669 16:33:59.335617 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1670 16:33:59.335664
1671 16:33:59.335710
1672 16:33:59.335757 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1673 16:33:59.335805 CH1 RK0: MR19=606, MR18=5050
1674 16:33:59.335853 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1675 16:33:59.335900
1676 16:33:59.335947 ----->DramcWriteLeveling(PI) begin...
1677 16:33:59.335998 ==
1678 16:33:59.336058 Dram Type= 6, Freq= 0, CH_1, rank 1
1679 16:33:59.336108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1680 16:33:59.336155 ==
1681 16:33:59.336213 Write leveling (Byte 0): 27 => 27
1682 16:33:59.336262 Write leveling (Byte 1): 26 => 26
1683 16:33:59.336313 DramcWriteLeveling(PI) end<-----
1684 16:33:59.336361
1685 16:33:59.336407 ==
1686 16:33:59.336454 Dram Type= 6, Freq= 0, CH_1, rank 1
1687 16:33:59.336518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1688 16:33:59.336568 ==
1689 16:33:59.336616 [Gating] SW mode calibration
1690 16:33:59.336664 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1691 16:33:59.336728 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1692 16:33:59.336777 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1693 16:33:59.336825 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1694 16:33:59.336873 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1695 16:33:59.336927 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 16:33:59.336990 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 16:33:59.337041 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 16:33:59.337089 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 16:33:59.337136 0 6 28 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
1700 16:33:59.337184 0 7 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1701 16:33:59.337231 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1702 16:33:59.337279 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 16:33:59.337326 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 16:33:59.337373 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 16:33:59.337420 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 16:33:59.337467 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 16:33:59.337514 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1708 16:33:59.337561 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1709 16:33:59.337609 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 16:33:59.337657 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 16:33:59.337704 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 16:33:59.337752 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 16:33:59.337799 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 16:33:59.337846 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 16:33:59.337892 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 16:33:59.337939 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 16:33:59.337986 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 16:33:59.338034 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 16:33:59.338082 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 16:33:59.338129 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 16:33:59.338176 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 16:33:59.338251 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 16:33:59.338314 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1724 16:33:59.338361 Total UI for P1: 0, mck2ui 16
1725 16:33:59.338409 best dqsien dly found for B0: ( 0, 9, 26)
1726 16:33:59.338457 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1727 16:33:59.338505 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1728 16:33:59.338552 Total UI for P1: 0, mck2ui 16
1729 16:33:59.338600 best dqsien dly found for B1: ( 0, 9, 30)
1730 16:33:59.338647 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1731 16:33:59.338695 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1732 16:33:59.338742
1733 16:33:59.338789 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1734 16:33:59.338836 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1735 16:33:59.338883 [Gating] SW calibration Done
1736 16:33:59.338931 ==
1737 16:33:59.338978 Dram Type= 6, Freq= 0, CH_1, rank 1
1738 16:33:59.339039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1739 16:33:59.339087 ==
1740 16:33:59.339134 RX Vref Scan: 0
1741 16:33:59.339182
1742 16:33:59.339240 RX Vref 0 -> 0, step: 1
1743 16:33:59.339291
1744 16:33:59.339339 RX Delay -130 -> 252, step: 16
1745 16:33:59.339387 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1746 16:33:59.339435 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1747 16:33:59.339483 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1748 16:33:59.339531 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1749 16:33:59.339578 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1750 16:33:59.339625 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1751 16:33:59.339878 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1752 16:33:59.339934 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1753 16:33:59.339983 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1754 16:33:59.340031 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1755 16:33:59.340079 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1756 16:33:59.340126 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1757 16:33:59.340174 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1758 16:33:59.340221 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1759 16:33:59.340268 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1760 16:33:59.340315 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1761 16:33:59.340362 ==
1762 16:33:59.340410 Dram Type= 6, Freq= 0, CH_1, rank 1
1763 16:33:59.340457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1764 16:33:59.340505 ==
1765 16:33:59.340552 DQS Delay:
1766 16:33:59.340600 DQS0 = 0, DQS1 = 0
1767 16:33:59.340647 DQM Delay:
1768 16:33:59.340694 DQM0 = 80, DQM1 = 70
1769 16:33:59.340740 DQ Delay:
1770 16:33:59.340788 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1771 16:33:59.340836 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1772 16:33:59.340885 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1773 16:33:59.340944 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1774 16:33:59.340994
1775 16:33:59.341040
1776 16:33:59.341087 ==
1777 16:33:59.341134 Dram Type= 6, Freq= 0, CH_1, rank 1
1778 16:33:59.341181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1779 16:33:59.341229 ==
1780 16:33:59.341276
1781 16:33:59.341323
1782 16:33:59.341369 TX Vref Scan disable
1783 16:33:59.341417 == TX Byte 0 ==
1784 16:33:59.341464 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1785 16:33:59.341512 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1786 16:33:59.341559 == TX Byte 1 ==
1787 16:33:59.341606 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1788 16:33:59.341654 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1789 16:33:59.341700 ==
1790 16:33:59.341746 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 16:33:59.341794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1792 16:33:59.341841 ==
1793 16:33:59.341888 TX Vref=22, minBit 10, minWin=27, winSum=452
1794 16:33:59.341936 TX Vref=24, minBit 5, minWin=28, winSum=455
1795 16:33:59.341984 TX Vref=26, minBit 0, minWin=28, winSum=455
1796 16:33:59.342031 TX Vref=28, minBit 8, minWin=28, winSum=459
1797 16:33:59.342079 TX Vref=30, minBit 8, minWin=28, winSum=457
1798 16:33:59.342126 TX Vref=32, minBit 0, minWin=28, winSum=457
1799 16:33:59.342173 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1800 16:33:59.342295
1801 16:33:59.342345 Final TX Range 1 Vref 28
1802 16:33:59.342393
1803 16:33:59.342442 ==
1804 16:33:59.342489 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 16:33:59.342537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1806 16:33:59.342585 ==
1807 16:33:59.342632
1808 16:33:59.342677
1809 16:33:59.342724 TX Vref Scan disable
1810 16:33:59.342771 == TX Byte 0 ==
1811 16:33:59.342819 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1812 16:33:59.342868 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1813 16:33:59.342916 == TX Byte 1 ==
1814 16:33:59.342982 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1815 16:33:59.343030 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1816 16:33:59.343077
1817 16:33:59.343123 [DATLAT]
1818 16:33:59.343183 Freq=800, CH1 RK1
1819 16:33:59.343230
1820 16:33:59.343277 DATLAT Default: 0x9
1821 16:33:59.343325 0, 0xFFFF, sum = 0
1822 16:33:59.343374 1, 0xFFFF, sum = 0
1823 16:33:59.343422 2, 0xFFFF, sum = 0
1824 16:33:59.343470 3, 0xFFFF, sum = 0
1825 16:33:59.343536 4, 0xFFFF, sum = 0
1826 16:33:59.343584 5, 0xFFFF, sum = 0
1827 16:33:59.343632 6, 0xFFFF, sum = 0
1828 16:33:59.343693 7, 0xFFFF, sum = 0
1829 16:33:59.343744 8, 0x0, sum = 1
1830 16:33:59.343793 9, 0x0, sum = 2
1831 16:33:59.343840 10, 0x0, sum = 3
1832 16:33:59.343892 11, 0x0, sum = 4
1833 16:33:59.343940 best_step = 9
1834 16:33:59.343987
1835 16:33:59.344034 ==
1836 16:33:59.344092 Dram Type= 6, Freq= 0, CH_1, rank 1
1837 16:33:59.344142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1838 16:33:59.344190 ==
1839 16:33:59.344236 RX Vref Scan: 0
1840 16:33:59.344295
1841 16:33:59.344360 RX Vref 0 -> 0, step: 1
1842 16:33:59.344408
1843 16:33:59.344454 RX Delay -111 -> 252, step: 8
1844 16:33:59.344504 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1845 16:33:59.344552 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1846 16:33:59.344599 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1847 16:33:59.344646 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1848 16:33:59.344693 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1849 16:33:59.344741 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1850 16:33:59.344789 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1851 16:33:59.344836 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1852 16:33:59.344883 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1853 16:33:59.344929 iDelay=217, Bit 9, Center 60 (-63 ~ 184) 248
1854 16:33:59.344977 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1855 16:33:59.345035 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1856 16:33:59.345085 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1857 16:33:59.345133 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1858 16:33:59.345179 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1859 16:33:59.345226 iDelay=217, Bit 15, Center 76 (-39 ~ 192) 232
1860 16:33:59.345295 ==
1861 16:33:59.345342 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 16:33:59.345390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1863 16:33:59.345438 ==
1864 16:33:59.345486 DQS Delay:
1865 16:33:59.345534 DQS0 = 0, DQS1 = 0
1866 16:33:59.345581 DQM Delay:
1867 16:33:59.345628 DQM0 = 82, DQM1 = 71
1868 16:33:59.345675 DQ Delay:
1869 16:33:59.345722 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1870 16:33:59.345770 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1871 16:33:59.345816 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1872 16:33:59.345863 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =76
1873 16:33:59.345909
1874 16:33:59.345967
1875 16:33:59.346034 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1876 16:33:59.346084 CH1 RK1: MR19=606, MR18=3636
1877 16:33:59.346132 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1878 16:33:59.346180 [RxdqsGatingPostProcess] freq 800
1879 16:33:59.346238 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1880 16:33:59.346288 Pre-setting of DQS Precalculation
1881 16:33:59.346335 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1882 16:33:59.346383 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1883 16:33:59.346431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1884 16:33:59.346479
1885 16:33:59.346525
1886 16:33:59.346572 [Calibration Summary] 1600 Mbps
1887 16:33:59.346619 CH 0, Rank 0
1888 16:33:59.346665 SW Impedance : PASS
1889 16:33:59.346901 DUTY Scan : NO K
1890 16:33:59.346954 ZQ Calibration : PASS
1891 16:33:59.347002 Jitter Meter : NO K
1892 16:33:59.347050 CBT Training : PASS
1893 16:33:59.347098 Write leveling : PASS
1894 16:33:59.347145 RX DQS gating : PASS
1895 16:33:59.347192 RX DQ/DQS(RDDQC) : PASS
1896 16:33:59.347239 TX DQ/DQS : PASS
1897 16:33:59.347285 RX DATLAT : PASS
1898 16:33:59.347332 RX DQ/DQS(Engine): PASS
1899 16:33:59.347378 TX OE : NO K
1900 16:33:59.347425 All Pass.
1901 16:33:59.347471
1902 16:33:59.347518 CH 0, Rank 1
1903 16:33:59.347565 SW Impedance : PASS
1904 16:33:59.347612 DUTY Scan : NO K
1905 16:33:59.347659 ZQ Calibration : PASS
1906 16:33:59.347706 Jitter Meter : NO K
1907 16:33:59.347753 CBT Training : PASS
1908 16:33:59.347799 Write leveling : PASS
1909 16:33:59.347845 RX DQS gating : PASS
1910 16:33:59.347892 RX DQ/DQS(RDDQC) : PASS
1911 16:33:59.347938 TX DQ/DQS : PASS
1912 16:33:59.347985 RX DATLAT : PASS
1913 16:33:59.348032 RX DQ/DQS(Engine): PASS
1914 16:33:59.348078 TX OE : NO K
1915 16:33:59.348124 All Pass.
1916 16:33:59.348170
1917 16:33:59.348216 CH 1, Rank 0
1918 16:33:59.348262 SW Impedance : PASS
1919 16:33:59.348309 DUTY Scan : NO K
1920 16:33:59.348355 ZQ Calibration : PASS
1921 16:33:59.348401 Jitter Meter : NO K
1922 16:33:59.348448 CBT Training : PASS
1923 16:33:59.348494 Write leveling : PASS
1924 16:33:59.348541 RX DQS gating : PASS
1925 16:33:59.348588 RX DQ/DQS(RDDQC) : PASS
1926 16:33:59.348635 TX DQ/DQS : PASS
1927 16:33:59.348682 RX DATLAT : PASS
1928 16:33:59.348728 RX DQ/DQS(Engine): PASS
1929 16:33:59.348775 TX OE : NO K
1930 16:33:59.348821 All Pass.
1931 16:33:59.348867
1932 16:33:59.348912 CH 1, Rank 1
1933 16:33:59.348958 SW Impedance : PASS
1934 16:33:59.349006 DUTY Scan : NO K
1935 16:33:59.349052 ZQ Calibration : PASS
1936 16:33:59.349099 Jitter Meter : NO K
1937 16:33:59.575657 CBT Training : PASS
1938 16:33:59.576086 Write leveling : PASS
1939 16:33:59.576380 RX DQS gating : PASS
1940 16:33:59.576650 RX DQ/DQS(RDDQC) : PASS
1941 16:33:59.576910 TX DQ/DQS : PASS
1942 16:33:59.577165 RX DATLAT : PASS
1943 16:33:59.577414 RX DQ/DQS(Engine): PASS
1944 16:33:59.577655 TX OE : NO K
1945 16:33:59.577901 All Pass.
1946 16:33:59.578151
1947 16:33:59.578477 DramC Write-DBI off
1948 16:33:59.578736 PER_BANK_REFRESH: Hybrid Mode
1949 16:33:59.578988 TX_TRACKING: ON
1950 16:33:59.579238 [GetDramInforAfterCalByMRR] Vendor 6.
1951 16:33:59.579488 [GetDramInforAfterCalByMRR] Revision 606.
1952 16:33:59.579736 [GetDramInforAfterCalByMRR] Revision 2 0.
1953 16:33:59.579983 MR0 0x3939
1954 16:33:59.580228 MR8 0x1111
1955 16:33:59.580472 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1956 16:33:59.580718
1957 16:33:59.580962 MR0 0x3939
1958 16:33:59.581205 MR8 0x1111
1959 16:33:59.581446 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1960 16:33:59.581688
1961 16:33:59.581933 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1962 16:33:59.582185 [FAST_K] Save calibration result to emmc
1963 16:33:59.582455 [FAST_K] Save calibration result to emmc
1964 16:33:59.582699 dram_init: config_dvfs: 1
1965 16:33:59.582942 dramc_set_vcore_voltage set vcore to 662500
1966 16:33:59.583186 Read voltage for 1200, 2
1967 16:33:59.583431 Vio18 = 0
1968 16:33:59.583673 Vcore = 662500
1969 16:33:59.583915 Vdram = 0
1970 16:33:59.584158 Vddq = 0
1971 16:33:59.584400 Vmddr = 0
1972 16:33:59.584643 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1973 16:33:59.584889 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1974 16:33:59.585134 MEM_TYPE=3, freq_sel=15
1975 16:33:59.585380 sv_algorithm_assistance_LP4_1600
1976 16:33:59.585628 ============ PULL DRAM RESETB DOWN ============
1977 16:33:59.585876 ========== PULL DRAM RESETB DOWN end =========
1978 16:33:59.586124 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1979 16:33:59.586533 ===================================
1980 16:33:59.586799 LPDDR4 DRAM CONFIGURATION
1981 16:33:59.587177 ===================================
1982 16:33:59.587429 EX_ROW_EN[0] = 0x0
1983 16:33:59.587674 EX_ROW_EN[1] = 0x0
1984 16:33:59.587919 LP4Y_EN = 0x0
1985 16:33:59.588164 WORK_FSP = 0x0
1986 16:33:59.588407 WL = 0x4
1987 16:33:59.588648 RL = 0x4
1988 16:33:59.588891 BL = 0x2
1989 16:33:59.589137 RPST = 0x0
1990 16:33:59.589380 RD_PRE = 0x0
1991 16:33:59.589638 WR_PRE = 0x1
1992 16:33:59.589896 WR_PST = 0x0
1993 16:33:59.590140 DBI_WR = 0x0
1994 16:33:59.590640 DBI_RD = 0x0
1995 16:33:59.591054 OTF = 0x1
1996 16:33:59.591446 ===================================
1997 16:33:59.591839 ===================================
1998 16:33:59.592236 ANA top config
1999 16:33:59.592639 ===================================
2000 16:33:59.593039 DLL_ASYNC_EN = 0
2001 16:33:59.593426 ALL_SLAVE_EN = 0
2002 16:33:59.593810 NEW_RANK_MODE = 1
2003 16:33:59.594203 DLL_IDLE_MODE = 1
2004 16:33:59.594643 LP45_APHY_COMB_EN = 1
2005 16:33:59.595030 TX_ODT_DIS = 1
2006 16:33:59.595419 NEW_8X_MODE = 1
2007 16:33:59.595810 ===================================
2008 16:33:59.596198 ===================================
2009 16:33:59.596586 data_rate = 2400
2010 16:33:59.596930 CKR = 1
2011 16:33:59.597186 DQ_P2S_RATIO = 8
2012 16:33:59.597432 ===================================
2013 16:33:59.597788 CA_P2S_RATIO = 8
2014 16:33:59.598061 DQ_CA_OPEN = 0
2015 16:33:59.598340 DQ_SEMI_OPEN = 0
2016 16:33:59.598658 CA_SEMI_OPEN = 0
2017 16:33:59.598915 CA_FULL_RATE = 0
2018 16:33:59.599239 DQ_CKDIV4_EN = 0
2019 16:33:59.599537 CA_CKDIV4_EN = 0
2020 16:33:59.599766 CA_PREDIV_EN = 0
2021 16:33:59.599944 PH8_DLY = 17
2022 16:33:59.600121 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2023 16:33:59.600299 DQ_AAMCK_DIV = 4
2024 16:33:59.600475 CA_AAMCK_DIV = 4
2025 16:33:59.600651 CA_ADMCK_DIV = 4
2026 16:33:59.600827 DQ_TRACK_CA_EN = 0
2027 16:33:59.601003 CA_PICK = 1200
2028 16:33:59.601233 CA_MCKIO = 1200
2029 16:33:59.601422 MCKIO_SEMI = 0
2030 16:33:59.601608 PLL_FREQ = 2366
2031 16:33:59.601862 DQ_UI_PI_RATIO = 32
2032 16:33:59.602062 CA_UI_PI_RATIO = 0
2033 16:33:59.602294 ===================================
2034 16:33:59.602494 ===================================
2035 16:33:59.602674 memory_type:LPDDR4
2036 16:33:59.602851 GP_NUM : 10
2037 16:33:59.603029 SRAM_EN : 1
2038 16:33:59.603207 MD32_EN : 0
2039 16:33:59.603382 ===================================
2040 16:33:59.603867 [ANA_INIT] >>>>>>>>>>>>>>
2041 16:33:59.604067 <<<<<< [CONFIGURE PHASE]: ANA_TX
2042 16:33:59.604296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2043 16:33:59.604499 ===================================
2044 16:33:59.604663 data_rate = 2400,PCW = 0X5b00
2045 16:33:59.604805 ===================================
2046 16:33:59.604944 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2047 16:33:59.605080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2048 16:33:59.605250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2049 16:33:59.605398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2050 16:33:59.605564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2051 16:33:59.605724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2052 16:33:59.605866 [ANA_INIT] flow start
2053 16:33:59.606014 [ANA_INIT] PLL >>>>>>>>
2054 16:33:59.606171 [ANA_INIT] PLL <<<<<<<<
2055 16:33:59.606402 [ANA_INIT] MIDPI >>>>>>>>
2056 16:33:59.606550 [ANA_INIT] MIDPI <<<<<<<<
2057 16:33:59.606702 [ANA_INIT] DLL >>>>>>>>
2058 16:33:59.606850 [ANA_INIT] DLL <<<<<<<<
2059 16:33:59.607004 [ANA_INIT] flow end
2060 16:33:59.607152 ============ LP4 DIFF to SE enter ============
2061 16:33:59.607306 ============ LP4 DIFF to SE exit ============
2062 16:33:59.607448 [ANA_INIT] <<<<<<<<<<<<<
2063 16:33:59.607610 [Flow] Enable top DCM control >>>>>
2064 16:33:59.607752 [Flow] Enable top DCM control <<<<<
2065 16:33:59.607889 Enable DLL master slave shuffle
2066 16:33:59.608045 ==============================================================
2067 16:33:59.608207 Gating Mode config
2068 16:33:59.608354 ==============================================================
2069 16:33:59.608496 Config description:
2070 16:33:59.608634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2071 16:33:59.608847 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2072 16:33:59.609058 SELPH_MODE 0: By rank 1: By Phase
2073 16:33:59.609266 ==============================================================
2074 16:33:59.609407 GAT_TRACK_EN = 1
2075 16:33:59.609547 RX_GATING_MODE = 2
2076 16:33:59.609654 RX_GATING_TRACK_MODE = 2
2077 16:33:59.609760 SELPH_MODE = 1
2078 16:33:59.609866 PICG_EARLY_EN = 1
2079 16:33:59.609971 VALID_LAT_VALUE = 1
2080 16:33:59.610091 ==============================================================
2081 16:33:59.610266 Enter into Gating configuration >>>>
2082 16:33:59.610379 Exit from Gating configuration <<<<
2083 16:33:59.610485 Enter into DVFS_PRE_config >>>>>
2084 16:33:59.610592 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2085 16:33:59.610703 Exit from DVFS_PRE_config <<<<<
2086 16:33:59.610809 Enter into PICG configuration >>>>
2087 16:33:59.610916 Exit from PICG configuration <<<<
2088 16:33:59.611031 [RX_INPUT] configuration >>>>>
2089 16:33:59.611138 [RX_INPUT] configuration <<<<<
2090 16:33:59.611244 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2091 16:33:59.611350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2092 16:33:59.611457 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2093 16:33:59.611564 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2094 16:33:59.611672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2095 16:33:59.611779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2096 16:33:59.611885 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2097 16:33:59.611992 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2098 16:33:59.612096 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2099 16:33:59.612201 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2100 16:33:59.612306 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2101 16:33:59.612415 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2102 16:33:59.612523 ===================================
2103 16:33:59.612641 LPDDR4 DRAM CONFIGURATION
2104 16:33:59.612751 ===================================
2105 16:33:59.612859 EX_ROW_EN[0] = 0x0
2106 16:33:59.612964 EX_ROW_EN[1] = 0x0
2107 16:33:59.613069 LP4Y_EN = 0x0
2108 16:33:59.613174 WORK_FSP = 0x0
2109 16:33:59.613279 WL = 0x4
2110 16:33:59.613385 RL = 0x4
2111 16:33:59.613493 BL = 0x2
2112 16:33:59.613641 RPST = 0x0
2113 16:33:59.613809 RD_PRE = 0x0
2114 16:33:59.613975 WR_PRE = 0x1
2115 16:33:59.614147 WR_PST = 0x0
2116 16:33:59.614333 DBI_WR = 0x0
2117 16:33:59.614506 DBI_RD = 0x0
2118 16:33:59.614674 OTF = 0x1
2119 16:33:59.614772 ===================================
2120 16:33:59.614863 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2121 16:33:59.614953 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2122 16:33:59.615043 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 16:33:59.615132 ===================================
2124 16:33:59.615220 LPDDR4 DRAM CONFIGURATION
2125 16:33:59.615309 ===================================
2126 16:33:59.615399 EX_ROW_EN[0] = 0x10
2127 16:33:59.615487 EX_ROW_EN[1] = 0x0
2128 16:33:59.615575 LP4Y_EN = 0x0
2129 16:33:59.615663 WORK_FSP = 0x0
2130 16:33:59.615752 WL = 0x4
2131 16:33:59.615840 RL = 0x4
2132 16:33:59.615927 BL = 0x2
2133 16:33:59.616014 RPST = 0x0
2134 16:33:59.616103 RD_PRE = 0x0
2135 16:33:59.616191 WR_PRE = 0x1
2136 16:33:59.616279 WR_PST = 0x0
2137 16:33:59.616369 DBI_WR = 0x0
2138 16:33:59.616457 DBI_RD = 0x0
2139 16:33:59.616545 OTF = 0x1
2140 16:33:59.616635 ===================================
2141 16:33:59.616725 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2142 16:33:59.616813 ==
2143 16:33:59.616902 Dram Type= 6, Freq= 0, CH_0, rank 0
2144 16:33:59.616992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2145 16:33:59.617082 ==
2146 16:33:59.617170 [Duty_Offset_Calibration]
2147 16:33:59.617259 B0:0 B1:2 CA:1
2148 16:33:59.617347
2149 16:33:59.617435 [DutyScan_Calibration_Flow] k_type=0
2150 16:33:59.617524
2151 16:33:59.617611 ==CLK 0==
2152 16:33:59.617934 Final CLK duty delay cell = 0
2153 16:33:59.618034 [0] MAX Duty = 5093%(X100), DQS PI = 12
2154 16:33:59.618126 [0] MIN Duty = 4938%(X100), DQS PI = 54
2155 16:33:59.618236 [0] AVG Duty = 5015%(X100)
2156 16:33:59.618333
2157 16:33:59.618422 CH0 CLK Duty spec in!! Max-Min= 155%
2158 16:33:59.618514 [DutyScan_Calibration_Flow] ====Done====
2159 16:33:59.618604
2160 16:33:59.618692 [DutyScan_Calibration_Flow] k_type=1
2161 16:33:59.618780
2162 16:33:59.618868 ==DQS 0 ==
2163 16:33:59.618957 Final DQS duty delay cell = 0
2164 16:33:59.619047 [0] MAX Duty = 5125%(X100), DQS PI = 32
2165 16:33:59.619137 [0] MIN Duty = 5031%(X100), DQS PI = 4
2166 16:33:59.619226 [0] AVG Duty = 5078%(X100)
2167 16:33:59.619314
2168 16:33:59.619401 ==DQS 1 ==
2169 16:33:59.619490 Final DQS duty delay cell = 0
2170 16:33:59.619589 [0] MAX Duty = 5031%(X100), DQS PI = 50
2171 16:33:59.619665 [0] MIN Duty = 4906%(X100), DQS PI = 14
2172 16:33:59.619741 [0] AVG Duty = 4968%(X100)
2173 16:33:59.619818
2174 16:33:59.619893 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2175 16:33:59.619968
2176 16:33:59.620043 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2177 16:33:59.620120 [DutyScan_Calibration_Flow] ====Done====
2178 16:33:59.620196
2179 16:33:59.620272 [DutyScan_Calibration_Flow] k_type=3
2180 16:33:59.620347
2181 16:33:59.620422 ==DQM 0 ==
2182 16:33:59.620498 Final DQM duty delay cell = 0
2183 16:33:59.620576 [0] MAX Duty = 5124%(X100), DQS PI = 20
2184 16:33:59.620651 [0] MIN Duty = 4969%(X100), DQS PI = 40
2185 16:33:59.620728 [0] AVG Duty = 5046%(X100)
2186 16:33:59.620805
2187 16:33:59.620880 ==DQM 1 ==
2188 16:33:59.620955 Final DQM duty delay cell = 4
2189 16:33:59.621032 [4] MAX Duty = 5187%(X100), DQS PI = 54
2190 16:33:59.621108 [4] MIN Duty = 5000%(X100), DQS PI = 16
2191 16:33:59.621183 [4] AVG Duty = 5093%(X100)
2192 16:33:59.621260
2193 16:33:59.621336 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2194 16:33:59.621413
2195 16:33:59.621487 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2196 16:33:59.621563 [DutyScan_Calibration_Flow] ====Done====
2197 16:33:59.621639
2198 16:33:59.621714 [DutyScan_Calibration_Flow] k_type=2
2199 16:33:59.621790
2200 16:33:59.621864 ==DQ 0 ==
2201 16:33:59.621940 Final DQ duty delay cell = -4
2202 16:33:59.622017 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2203 16:33:59.622093 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2204 16:33:59.622170 [-4] AVG Duty = 4937%(X100)
2205 16:33:59.622255
2206 16:33:59.622332 ==DQ 1 ==
2207 16:33:59.622408 Final DQ duty delay cell = -4
2208 16:33:59.622486 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2209 16:33:59.622562 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2210 16:33:59.622637 [-4] AVG Duty = 4969%(X100)
2211 16:33:59.622712
2212 16:33:59.622787 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2213 16:33:59.622864
2214 16:33:59.622939 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2215 16:33:59.623015 [DutyScan_Calibration_Flow] ====Done====
2216 16:33:59.623092 ==
2217 16:33:59.623168 Dram Type= 6, Freq= 0, CH_1, rank 0
2218 16:33:59.623245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2219 16:33:59.623321 ==
2220 16:33:59.623397 [Duty_Offset_Calibration]
2221 16:33:59.623472 B0:0 B1:4 CA:-5
2222 16:33:59.623548
2223 16:33:59.623623 [DutyScan_Calibration_Flow] k_type=0
2224 16:33:59.623698
2225 16:33:59.623773 ==CLK 0==
2226 16:33:59.623848 Final CLK duty delay cell = 0
2227 16:33:59.623926 [0] MAX Duty = 5094%(X100), DQS PI = 24
2228 16:33:59.624002 [0] MIN Duty = 4876%(X100), DQS PI = 52
2229 16:33:59.624076 [0] AVG Duty = 4985%(X100)
2230 16:33:59.624151
2231 16:33:59.624229 CH1 CLK Duty spec in!! Max-Min= 218%
2232 16:33:59.624306 [DutyScan_Calibration_Flow] ====Done====
2233 16:33:59.624382
2234 16:33:59.624456 [DutyScan_Calibration_Flow] k_type=1
2235 16:33:59.624542
2236 16:33:59.624607 ==DQS 0 ==
2237 16:33:59.624673 Final DQS duty delay cell = 0
2238 16:33:59.624740 [0] MAX Duty = 5125%(X100), DQS PI = 16
2239 16:33:59.624806 [0] MIN Duty = 4875%(X100), DQS PI = 40
2240 16:33:59.624872 [0] AVG Duty = 5000%(X100)
2241 16:33:59.624939
2242 16:33:59.625005 ==DQS 1 ==
2243 16:33:59.625070 Final DQS duty delay cell = -4
2244 16:33:59.625137 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2245 16:33:59.625203 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2246 16:33:59.625269 [-4] AVG Duty = 4953%(X100)
2247 16:33:59.625335
2248 16:33:59.625400 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2249 16:33:59.625466
2250 16:33:59.625532 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2251 16:33:59.625599 [DutyScan_Calibration_Flow] ====Done====
2252 16:33:59.625666
2253 16:33:59.625731 [DutyScan_Calibration_Flow] k_type=3
2254 16:33:59.625797
2255 16:33:59.625863 ==DQM 0 ==
2256 16:33:59.625929 Final DQM duty delay cell = -4
2257 16:33:59.625996 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2258 16:33:59.626062 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2259 16:33:59.626129 [-4] AVG Duty = 4953%(X100)
2260 16:33:59.626195
2261 16:33:59.626274 ==DQM 1 ==
2262 16:33:59.626342 Final DQM duty delay cell = -4
2263 16:33:59.626410 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2264 16:33:59.626476 [-4] MIN Duty = 4907%(X100), DQS PI = 60
2265 16:33:59.626543 [-4] AVG Duty = 4984%(X100)
2266 16:33:59.626610
2267 16:33:59.626676 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2268 16:33:59.626741
2269 16:33:59.626808 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2270 16:33:59.626875 [DutyScan_Calibration_Flow] ====Done====
2271 16:33:59.626941
2272 16:33:59.627006 [DutyScan_Calibration_Flow] k_type=2
2273 16:33:59.627073
2274 16:33:59.627139 ==DQ 0 ==
2275 16:33:59.627206 Final DQ duty delay cell = 0
2276 16:33:59.627274 [0] MAX Duty = 5062%(X100), DQS PI = 0
2277 16:33:59.627342 [0] MIN Duty = 4969%(X100), DQS PI = 42
2278 16:33:59.627409 [0] AVG Duty = 5015%(X100)
2279 16:33:59.627475
2280 16:33:59.627540 ==DQ 1 ==
2281 16:33:59.627607 Final DQ duty delay cell = 0
2282 16:33:59.627675 [0] MAX Duty = 5000%(X100), DQS PI = 8
2283 16:33:59.627743 [0] MIN Duty = 4875%(X100), DQS PI = 0
2284 16:33:59.627809 [0] AVG Duty = 4937%(X100)
2285 16:33:59.627875
2286 16:33:59.627942 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2287 16:33:59.628008
2288 16:33:59.628073 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2289 16:33:59.628139 [DutyScan_Calibration_Flow] ====Done====
2290 16:33:59.628206 nWR fixed to 30
2291 16:33:59.628274 [ModeRegInit_LP4] CH0 RK0
2292 16:33:59.628341 [ModeRegInit_LP4] CH0 RK1
2293 16:33:59.628406 [ModeRegInit_LP4] CH1 RK0
2294 16:33:59.628472 [ModeRegInit_LP4] CH1 RK1
2295 16:33:59.628536 match AC timing 6
2296 16:33:59.628602 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2297 16:33:59.628669 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2298 16:33:59.628735 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2299 16:33:59.628801 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2300 16:33:59.628868 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2301 16:33:59.628934 ==
2302 16:33:59.629000 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 16:33:59.629066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2304 16:33:59.629132 ==
2305 16:33:59.629199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2306 16:33:59.629266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2307 16:33:59.629550 [CA 0] Center 39 (9~70) winsize 62
2308 16:33:59.629617 [CA 1] Center 39 (8~70) winsize 63
2309 16:33:59.629678 [CA 2] Center 36 (5~67) winsize 63
2310 16:33:59.629737 [CA 3] Center 35 (4~66) winsize 63
2311 16:33:59.629796 [CA 4] Center 34 (3~65) winsize 63
2312 16:33:59.629855 [CA 5] Center 33 (3~64) winsize 62
2313 16:33:59.629913
2314 16:33:59.629971 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2315 16:33:59.630030
2316 16:33:59.630087 [CATrainingPosCal] consider 1 rank data
2317 16:33:59.630146 u2DelayCellTimex100 = 270/100 ps
2318 16:33:59.630206 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2319 16:33:59.630277 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2320 16:33:59.630336 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2321 16:33:59.630395 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2322 16:33:59.630453 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2323 16:33:59.630511 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2324 16:33:59.630569
2325 16:33:59.630627 CA PerBit enable=1, Macro0, CA PI delay=33
2326 16:33:59.630686
2327 16:33:59.630744 [CBTSetCACLKResult] CA Dly = 33
2328 16:33:59.630821 CS Dly: 7 (0~38)
2329 16:33:59.630882 ==
2330 16:33:59.630942 Dram Type= 6, Freq= 0, CH_0, rank 1
2331 16:33:59.631001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2332 16:33:59.631061 ==
2333 16:33:59.631122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2334 16:33:59.631183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2335 16:33:59.631242 [CA 0] Center 39 (8~70) winsize 63
2336 16:33:59.631301 [CA 1] Center 39 (8~70) winsize 63
2337 16:33:59.631360 [CA 2] Center 36 (5~67) winsize 63
2338 16:33:59.631418 [CA 3] Center 35 (4~66) winsize 63
2339 16:33:59.631476 [CA 4] Center 33 (3~64) winsize 62
2340 16:33:59.631535 [CA 5] Center 34 (3~65) winsize 63
2341 16:33:59.631593
2342 16:33:59.631652 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2343 16:33:59.631710
2344 16:33:59.631769 [CATrainingPosCal] consider 2 rank data
2345 16:33:59.631828 u2DelayCellTimex100 = 270/100 ps
2346 16:33:59.631886 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2347 16:33:59.631946 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2348 16:33:59.632011 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2349 16:33:59.632070 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2350 16:33:59.632129 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2351 16:33:59.632188 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2352 16:33:59.632246
2353 16:33:59.632305 CA PerBit enable=1, Macro0, CA PI delay=33
2354 16:33:59.632364
2355 16:33:59.632422 [CBTSetCACLKResult] CA Dly = 33
2356 16:33:59.632481 CS Dly: 7 (0~39)
2357 16:33:59.632540
2358 16:33:59.632598 ----->DramcWriteLeveling(PI) begin...
2359 16:33:59.632658 ==
2360 16:33:59.632717 Dram Type= 6, Freq= 0, CH_0, rank 0
2361 16:33:59.632777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2362 16:33:59.632844 ==
2363 16:33:59.632935 Write leveling (Byte 0): 27 => 27
2364 16:33:59.632996 Write leveling (Byte 1): 26 => 26
2365 16:33:59.633093 DramcWriteLeveling(PI) end<-----
2366 16:33:59.633158
2367 16:33:59.633218 ==
2368 16:33:59.633307 Dram Type= 6, Freq= 0, CH_0, rank 0
2369 16:33:59.633372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2370 16:33:59.633432 ==
2371 16:33:59.633492 [Gating] SW mode calibration
2372 16:33:59.633552 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2373 16:33:59.633614 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2374 16:33:59.633675 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2375 16:33:59.633735 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 16:33:59.633794 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2377 16:33:59.633853 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 16:33:59.633912 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 16:33:59.633970 0 11 20 | B1->B0 | 2f2f 2c2c | 0 1 | (0 1) (1 0)
2380 16:33:59.634028 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2381 16:33:59.634088 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 16:33:59.634147 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 16:33:59.634206 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 16:33:59.634273 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 16:33:59.634333 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 16:33:59.634392 0 12 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2387 16:33:59.634451 0 12 20 | B1->B0 | 3c3c 4141 | 1 1 | (0 0) (0 0)
2388 16:33:59.634509 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2389 16:33:59.634581 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 16:33:59.634644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 16:33:59.634698 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 16:33:59.634751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 16:33:59.634804 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 16:33:59.634857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 16:33:59.634910 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2396 16:33:59.634963 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2397 16:33:59.635015 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 16:33:59.635069 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 16:33:59.635122 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 16:33:59.635176 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 16:33:59.635229 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 16:33:59.635282 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 16:33:59.635337 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 16:33:59.635390 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 16:33:59.635443 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 16:33:59.635497 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 16:33:59.635550 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 16:33:59.635603 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 16:33:59.635656 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 16:33:59.635709 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2411 16:33:59.635761 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2412 16:33:59.636011 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2413 16:33:59.636080 Total UI for P1: 0, mck2ui 16
2414 16:33:59.636138 best dqsien dly found for B0: ( 0, 15, 18)
2415 16:33:59.636193 Total UI for P1: 0, mck2ui 16
2416 16:33:59.636246 best dqsien dly found for B1: ( 0, 15, 20)
2417 16:33:59.636299 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2418 16:33:59.636353 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2419 16:33:59.636405
2420 16:33:59.636457 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2421 16:33:59.636510 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2422 16:33:59.636562 [Gating] SW calibration Done
2423 16:33:59.636619 ==
2424 16:33:59.636673 Dram Type= 6, Freq= 0, CH_0, rank 0
2425 16:33:59.636726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2426 16:33:59.636780 ==
2427 16:33:59.636833 RX Vref Scan: 0
2428 16:33:59.636886
2429 16:33:59.636939 RX Vref 0 -> 0, step: 1
2430 16:33:59.636992
2431 16:33:59.637043 RX Delay -40 -> 252, step: 8
2432 16:33:59.637096 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2433 16:33:59.637149 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2434 16:33:59.637203 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2435 16:33:59.637256 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2436 16:33:59.637309 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2437 16:33:59.637362 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2438 16:33:59.637416 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2439 16:33:59.637468 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2440 16:33:59.637524 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2441 16:33:59.637578 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2442 16:33:59.637631 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2443 16:33:59.637685 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2444 16:33:59.637740 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2445 16:33:59.637793 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2446 16:33:59.637846 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2447 16:33:59.637899 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2448 16:33:59.637951 ==
2449 16:33:59.638003 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 16:33:59.638056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2451 16:33:59.638111 ==
2452 16:33:59.638164 DQS Delay:
2453 16:33:59.638287 DQS0 = 0, DQS1 = 0
2454 16:33:59.638421 DQM Delay:
2455 16:33:59.638478 DQM0 = 115, DQM1 = 106
2456 16:33:59.638533 DQ Delay:
2457 16:33:59.638586 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2458 16:33:59.638640 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2459 16:33:59.638694 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2460 16:33:59.638748 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2461 16:33:59.638801
2462 16:33:59.638853
2463 16:33:59.638905 ==
2464 16:33:59.638958 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 16:33:59.639012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2466 16:33:59.639066 ==
2467 16:33:59.639118
2468 16:33:59.639169
2469 16:33:59.639221 TX Vref Scan disable
2470 16:33:59.639274 == TX Byte 0 ==
2471 16:33:59.639327 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2472 16:33:59.639382 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2473 16:33:59.639436 == TX Byte 1 ==
2474 16:33:59.639503 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2475 16:33:59.639581 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2476 16:33:59.639631 ==
2477 16:33:59.639683 Dram Type= 6, Freq= 0, CH_0, rank 0
2478 16:33:59.639732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2479 16:33:59.639781 ==
2480 16:33:59.639829 TX Vref=22, minBit 9, minWin=25, winSum=412
2481 16:33:59.639894 TX Vref=24, minBit 9, minWin=25, winSum=425
2482 16:33:59.639944 TX Vref=26, minBit 13, minWin=25, winSum=429
2483 16:33:59.639993 TX Vref=28, minBit 13, minWin=25, winSum=430
2484 16:33:59.640042 TX Vref=30, minBit 8, minWin=25, winSum=428
2485 16:33:59.640110 TX Vref=32, minBit 5, minWin=26, winSum=431
2486 16:33:59.640160 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 32
2487 16:33:59.640209
2488 16:33:59.640258 Final TX Range 1 Vref 32
2489 16:33:59.640310
2490 16:33:59.640359 ==
2491 16:33:59.640408 Dram Type= 6, Freq= 0, CH_0, rank 0
2492 16:33:59.640456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2493 16:33:59.640507 ==
2494 16:33:59.640555
2495 16:33:59.640603
2496 16:33:59.640650 TX Vref Scan disable
2497 16:33:59.640698 == TX Byte 0 ==
2498 16:33:59.640747 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2499 16:33:59.640796 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2500 16:33:59.640846 == TX Byte 1 ==
2501 16:33:59.640894 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2502 16:33:59.640943 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2503 16:33:59.640991
2504 16:33:59.641039 [DATLAT]
2505 16:33:59.641086 Freq=1200, CH0 RK0
2506 16:33:59.641133
2507 16:33:59.641181 DATLAT Default: 0xd
2508 16:33:59.641229 0, 0xFFFF, sum = 0
2509 16:33:59.641278 1, 0xFFFF, sum = 0
2510 16:33:59.641327 2, 0xFFFF, sum = 0
2511 16:33:59.641377 3, 0xFFFF, sum = 0
2512 16:33:59.641426 4, 0xFFFF, sum = 0
2513 16:33:59.641475 5, 0xFFFF, sum = 0
2514 16:33:59.641524 6, 0xFFFF, sum = 0
2515 16:33:59.641572 7, 0xFFFF, sum = 0
2516 16:33:59.641621 8, 0xFFFF, sum = 0
2517 16:33:59.641671 9, 0xFFFF, sum = 0
2518 16:33:59.641720 10, 0xFFFF, sum = 0
2519 16:33:59.641769 11, 0x0, sum = 1
2520 16:33:59.641818 12, 0x0, sum = 2
2521 16:33:59.641867 13, 0x0, sum = 3
2522 16:33:59.641916 14, 0x0, sum = 4
2523 16:33:59.641965 best_step = 12
2524 16:33:59.642012
2525 16:33:59.642060 ==
2526 16:33:59.642109 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 16:33:59.642158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2528 16:33:59.642206 ==
2529 16:33:59.642274 RX Vref Scan: 1
2530 16:33:59.642323
2531 16:33:59.642371 Set Vref Range= 32 -> 127
2532 16:33:59.642419
2533 16:33:59.642466 RX Vref 32 -> 127, step: 1
2534 16:33:59.642514
2535 16:33:59.642562 RX Delay -21 -> 252, step: 4
2536 16:33:59.642611
2537 16:33:59.642659 Set Vref, RX VrefLevel [Byte0]: 32
2538 16:33:59.642708 [Byte1]: 32
2539 16:33:59.642756
2540 16:33:59.642804 Set Vref, RX VrefLevel [Byte0]: 33
2541 16:33:59.642853 [Byte1]: 33
2542 16:33:59.642901
2543 16:33:59.642949 Set Vref, RX VrefLevel [Byte0]: 34
2544 16:33:59.642997 [Byte1]: 34
2545 16:33:59.643045
2546 16:33:59.643093 Set Vref, RX VrefLevel [Byte0]: 35
2547 16:33:59.643142 [Byte1]: 35
2548 16:33:59.643190
2549 16:33:59.643238 Set Vref, RX VrefLevel [Byte0]: 36
2550 16:33:59.643287 [Byte1]: 36
2551 16:33:59.643335
2552 16:33:59.643383 Set Vref, RX VrefLevel [Byte0]: 37
2553 16:33:59.643445 [Byte1]: 37
2554 16:33:59.643495
2555 16:33:59.643543 Set Vref, RX VrefLevel [Byte0]: 38
2556 16:33:59.643603 [Byte1]: 38
2557 16:33:59.643666
2558 16:33:59.643715 Set Vref, RX VrefLevel [Byte0]: 39
2559 16:33:59.643764 [Byte1]: 39
2560 16:33:59.643812
2561 16:33:59.643864 Set Vref, RX VrefLevel [Byte0]: 40
2562 16:33:59.643913 [Byte1]: 40
2563 16:33:59.643961
2564 16:33:59.644008 Set Vref, RX VrefLevel [Byte0]: 41
2565 16:33:59.644249 [Byte1]: 41
2566 16:33:59.644305
2567 16:33:59.644354 Set Vref, RX VrefLevel [Byte0]: 42
2568 16:33:59.644413 [Byte1]: 42
2569 16:33:59.644474
2570 16:33:59.644524 Set Vref, RX VrefLevel [Byte0]: 43
2571 16:33:59.644589 [Byte1]: 43
2572 16:33:59.644638
2573 16:33:59.644685 Set Vref, RX VrefLevel [Byte0]: 44
2574 16:33:59.644733 [Byte1]: 44
2575 16:33:59.644792
2576 16:33:59.644840 Set Vref, RX VrefLevel [Byte0]: 45
2577 16:33:59.644888 [Byte1]: 45
2578 16:33:59.644935
2579 16:33:59.644993 Set Vref, RX VrefLevel [Byte0]: 46
2580 16:33:59.645043 [Byte1]: 46
2581 16:33:59.645090
2582 16:33:59.645137 Set Vref, RX VrefLevel [Byte0]: 47
2583 16:33:59.645185 [Byte1]: 47
2584 16:33:59.645235
2585 16:33:59.645282 Set Vref, RX VrefLevel [Byte0]: 48
2586 16:33:59.645329 [Byte1]: 48
2587 16:33:59.645376
2588 16:33:59.645423 Set Vref, RX VrefLevel [Byte0]: 49
2589 16:33:59.645470 [Byte1]: 49
2590 16:33:59.645517
2591 16:33:59.645564 Set Vref, RX VrefLevel [Byte0]: 50
2592 16:33:59.645611 [Byte1]: 50
2593 16:33:59.645658
2594 16:33:59.645705 Set Vref, RX VrefLevel [Byte0]: 51
2595 16:33:59.645752 [Byte1]: 51
2596 16:33:59.645798
2597 16:33:59.645845 Set Vref, RX VrefLevel [Byte0]: 52
2598 16:33:59.645893 [Byte1]: 52
2599 16:33:59.645940
2600 16:33:59.645986 Set Vref, RX VrefLevel [Byte0]: 53
2601 16:33:59.646033 [Byte1]: 53
2602 16:33:59.646080
2603 16:33:59.646127 Set Vref, RX VrefLevel [Byte0]: 54
2604 16:33:59.646175 [Byte1]: 54
2605 16:33:59.646243
2606 16:33:59.646304 Set Vref, RX VrefLevel [Byte0]: 55
2607 16:33:59.646351 [Byte1]: 55
2608 16:33:59.646398
2609 16:33:59.646445 Set Vref, RX VrefLevel [Byte0]: 56
2610 16:33:59.646492 [Byte1]: 56
2611 16:33:59.646539
2612 16:33:59.646586 Set Vref, RX VrefLevel [Byte0]: 57
2613 16:33:59.646633 [Byte1]: 57
2614 16:33:59.646682
2615 16:33:59.646729 Set Vref, RX VrefLevel [Byte0]: 58
2616 16:33:59.646776 [Byte1]: 58
2617 16:33:59.646822
2618 16:33:59.646869 Set Vref, RX VrefLevel [Byte0]: 59
2619 16:33:59.646917 [Byte1]: 59
2620 16:33:59.646963
2621 16:33:59.647010 Set Vref, RX VrefLevel [Byte0]: 60
2622 16:33:59.647057 [Byte1]: 60
2623 16:33:59.647104
2624 16:33:59.647150 Set Vref, RX VrefLevel [Byte0]: 61
2625 16:33:59.647197 [Byte1]: 61
2626 16:33:59.647243
2627 16:33:59.647290 Set Vref, RX VrefLevel [Byte0]: 62
2628 16:33:59.647336 [Byte1]: 62
2629 16:33:59.647383
2630 16:33:59.647429 Set Vref, RX VrefLevel [Byte0]: 63
2631 16:33:59.647475 [Byte1]: 63
2632 16:33:59.647521
2633 16:33:59.647568 Set Vref, RX VrefLevel [Byte0]: 64
2634 16:33:59.647615 [Byte1]: 64
2635 16:33:59.647663
2636 16:33:59.647709 Set Vref, RX VrefLevel [Byte0]: 65
2637 16:33:59.647756 [Byte1]: 65
2638 16:33:59.647802
2639 16:33:59.647849 Set Vref, RX VrefLevel [Byte0]: 66
2640 16:33:59.647895 [Byte1]: 66
2641 16:33:59.647941
2642 16:33:59.647988 Final RX Vref Byte 0 = 52 to rank0
2643 16:33:59.648036 Final RX Vref Byte 1 = 46 to rank0
2644 16:33:59.648084 Final RX Vref Byte 0 = 52 to rank1
2645 16:33:59.648130 Final RX Vref Byte 1 = 46 to rank1==
2646 16:33:59.648178 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 16:33:59.648225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2648 16:33:59.648272 ==
2649 16:33:59.648319 DQS Delay:
2650 16:33:59.648365 DQS0 = 0, DQS1 = 0
2651 16:33:59.648413 DQM Delay:
2652 16:33:59.648460 DQM0 = 114, DQM1 = 104
2653 16:33:59.648508 DQ Delay:
2654 16:33:59.648555 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2655 16:33:59.648602 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2656 16:33:59.648651 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2657 16:33:59.648698 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2658 16:33:59.648746
2659 16:33:59.648792
2660 16:33:59.648839 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2661 16:33:59.648888 CH0 RK0: MR19=404, MR18=909
2662 16:33:59.648935 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2663 16:33:59.648983
2664 16:33:59.649030 ----->DramcWriteLeveling(PI) begin...
2665 16:33:59.649079 ==
2666 16:33:59.649126 Dram Type= 6, Freq= 0, CH_0, rank 1
2667 16:33:59.649172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2668 16:33:59.649219 ==
2669 16:33:59.649266 Write leveling (Byte 0): 27 => 27
2670 16:33:59.649313 Write leveling (Byte 1): 25 => 25
2671 16:33:59.649359 DramcWriteLeveling(PI) end<-----
2672 16:33:59.649406
2673 16:33:59.649452 ==
2674 16:33:59.649499 Dram Type= 6, Freq= 0, CH_0, rank 1
2675 16:33:59.649547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2676 16:33:59.649594 ==
2677 16:33:59.649641 [Gating] SW mode calibration
2678 16:33:59.649688 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2679 16:33:59.649735 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2680 16:33:59.649783 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2681 16:33:59.649830 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2682 16:33:59.649878 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2683 16:33:59.649926 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2684 16:33:59.649973 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2685 16:33:59.650020 0 11 20 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (1 0)
2686 16:33:59.650067 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2687 16:33:59.650114 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 16:33:59.650161 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 16:33:59.650208 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 16:33:59.650303 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 16:33:59.650351 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 16:33:59.650398 0 12 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
2693 16:33:59.650446 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2694 16:33:59.650493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2695 16:33:59.650540 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 16:33:59.650587 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 16:33:59.650634 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 16:33:59.650681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 16:33:59.650916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 16:33:59.650970 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2701 16:33:59.651018 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2702 16:33:59.651066 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 16:33:59.651114 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 16:33:59.651161 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 16:33:59.651209 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 16:33:59.651256 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 16:33:59.651304 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 16:33:59.651351 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 16:33:59.651398 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 16:33:59.651445 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 16:33:59.651492 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 16:33:59.651539 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 16:33:59.651586 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 16:33:59.651634 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 16:33:59.651681 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 16:33:59.651729 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2717 16:33:59.651776 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2718 16:33:59.651824 Total UI for P1: 0, mck2ui 16
2719 16:33:59.651872 best dqsien dly found for B0: ( 0, 15, 16)
2720 16:33:59.651919 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2721 16:33:59.651966 Total UI for P1: 0, mck2ui 16
2722 16:33:59.652014 best dqsien dly found for B1: ( 0, 15, 18)
2723 16:33:59.652062 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2724 16:33:59.652110 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2725 16:33:59.652157
2726 16:33:59.652204 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2727 16:33:59.652253 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2728 16:33:59.652301 [Gating] SW calibration Done
2729 16:33:59.652348 ==
2730 16:33:59.652396 Dram Type= 6, Freq= 0, CH_0, rank 1
2731 16:33:59.652444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2732 16:33:59.652492 ==
2733 16:33:59.652539 RX Vref Scan: 0
2734 16:33:59.652585
2735 16:33:59.652632 RX Vref 0 -> 0, step: 1
2736 16:33:59.652679
2737 16:33:59.652725 RX Delay -40 -> 252, step: 8
2738 16:33:59.652773 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2739 16:33:59.652821 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2740 16:33:59.652868 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2741 16:33:59.652915 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2742 16:33:59.652962 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2743 16:33:59.653009 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2744 16:33:59.653056 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2745 16:33:59.653104 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2746 16:33:59.653150 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2747 16:33:59.653198 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2748 16:33:59.653244 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2749 16:33:59.653314 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2750 16:33:59.653367 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2751 16:33:59.653414 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2752 16:33:59.653462 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2753 16:33:59.653509 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2754 16:33:59.653556 ==
2755 16:33:59.653603 Dram Type= 6, Freq= 0, CH_0, rank 1
2756 16:33:59.653651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2757 16:33:59.653698 ==
2758 16:33:59.653745 DQS Delay:
2759 16:33:59.653792 DQS0 = 0, DQS1 = 0
2760 16:33:59.653838 DQM Delay:
2761 16:33:59.653886 DQM0 = 115, DQM1 = 106
2762 16:33:59.653933 DQ Delay:
2763 16:33:59.653979 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =107
2764 16:33:59.654027 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2765 16:33:59.654074 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2766 16:33:59.654122 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2767 16:33:59.654169
2768 16:33:59.654220
2769 16:33:59.654299 ==
2770 16:33:59.654345 Dram Type= 6, Freq= 0, CH_0, rank 1
2771 16:33:59.654393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2772 16:33:59.654441 ==
2773 16:33:59.654488
2774 16:33:59.654535
2775 16:33:59.654582 TX Vref Scan disable
2776 16:33:59.654629 == TX Byte 0 ==
2777 16:33:59.654677 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2778 16:33:59.654724 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2779 16:33:59.654771 == TX Byte 1 ==
2780 16:33:59.654818 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2781 16:33:59.654865 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2782 16:33:59.654912 ==
2783 16:33:59.654959 Dram Type= 6, Freq= 0, CH_0, rank 1
2784 16:33:59.655006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2785 16:33:59.655054 ==
2786 16:33:59.655118 TX Vref=22, minBit 5, minWin=24, winSum=411
2787 16:33:59.655203 TX Vref=24, minBit 12, minWin=25, winSum=419
2788 16:33:59.655259 TX Vref=26, minBit 1, minWin=26, winSum=428
2789 16:33:59.655311 TX Vref=28, minBit 8, minWin=26, winSum=429
2790 16:33:59.655359 TX Vref=30, minBit 1, minWin=26, winSum=425
2791 16:33:59.655462 TX Vref=32, minBit 4, minWin=26, winSum=433
2792 16:33:59.655523 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 32
2793 16:33:59.655571
2794 16:33:59.655618 Final TX Range 1 Vref 32
2795 16:33:59.655666
2796 16:33:59.655713 ==
2797 16:33:59.655760 Dram Type= 6, Freq= 0, CH_0, rank 1
2798 16:33:59.655808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2799 16:33:59.655855 ==
2800 16:33:59.655902
2801 16:33:59.655949
2802 16:33:59.656000 TX Vref Scan disable
2803 16:33:59.656047 == TX Byte 0 ==
2804 16:33:59.656095 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2805 16:33:59.656142 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2806 16:33:59.656192 == TX Byte 1 ==
2807 16:33:59.656239 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2808 16:33:59.656287 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2809 16:33:59.656334
2810 16:33:59.656381 [DATLAT]
2811 16:33:59.656429 Freq=1200, CH0 RK1
2812 16:33:59.656476
2813 16:33:59.656525 DATLAT Default: 0xc
2814 16:33:59.656573 0, 0xFFFF, sum = 0
2815 16:33:59.656622 1, 0xFFFF, sum = 0
2816 16:33:59.656671 2, 0xFFFF, sum = 0
2817 16:33:59.656719 3, 0xFFFF, sum = 0
2818 16:33:59.656767 4, 0xFFFF, sum = 0
2819 16:33:59.656815 5, 0xFFFF, sum = 0
2820 16:33:59.656865 6, 0xFFFF, sum = 0
2821 16:33:59.656914 7, 0xFFFF, sum = 0
2822 16:33:59.656961 8, 0xFFFF, sum = 0
2823 16:33:59.657010 9, 0xFFFF, sum = 0
2824 16:33:59.657060 10, 0xFFFF, sum = 0
2825 16:33:59.657111 11, 0x0, sum = 1
2826 16:33:59.657161 12, 0x0, sum = 2
2827 16:33:59.657209 13, 0x0, sum = 3
2828 16:33:59.657445 14, 0x0, sum = 4
2829 16:33:59.657500 best_step = 12
2830 16:33:59.657551
2831 16:33:59.657599 ==
2832 16:33:59.657647 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 16:33:59.657695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2834 16:33:59.657742 ==
2835 16:33:59.657792 RX Vref Scan: 0
2836 16:33:59.657841
2837 16:33:59.657890 RX Vref 0 -> 0, step: 1
2838 16:33:59.657938
2839 16:33:59.657988 RX Delay -21 -> 252, step: 4
2840 16:33:59.658037 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2841 16:33:59.658085 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2842 16:33:59.658132 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2843 16:33:59.658179 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2844 16:33:59.658267 iDelay=199, Bit 4, Center 118 (43 ~ 194) 152
2845 16:33:59.658315 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2846 16:33:59.658368 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2847 16:33:59.658418 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2848 16:33:59.658467 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2849 16:33:59.658514 iDelay=199, Bit 9, Center 88 (27 ~ 150) 124
2850 16:33:59.658565 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2851 16:33:59.658613 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2852 16:33:59.658660 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128
2853 16:33:59.658708 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2854 16:33:59.658754 iDelay=199, Bit 14, Center 114 (51 ~ 178) 128
2855 16:33:59.658801 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2856 16:33:59.658847 ==
2857 16:33:59.658895 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 16:33:59.658943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2859 16:33:59.658990 ==
2860 16:33:59.659037 DQS Delay:
2861 16:33:59.659084 DQS0 = 0, DQS1 = 0
2862 16:33:59.659131 DQM Delay:
2863 16:33:59.659177 DQM0 = 115, DQM1 = 104
2864 16:33:59.659224 DQ Delay:
2865 16:33:59.659270 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2866 16:33:59.659317 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2867 16:33:59.659365 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2868 16:33:59.659412 DQ12 =110, DQ13 =112, DQ14 =114, DQ15 =114
2869 16:33:59.659458
2870 16:33:59.659505
2871 16:33:59.659552 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2872 16:33:59.659600 CH0 RK1: MR19=404, MR18=1010
2873 16:33:59.659647 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2874 16:33:59.659695 [RxdqsGatingPostProcess] freq 1200
2875 16:33:59.659742 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2876 16:33:59.659790 Pre-setting of DQS Precalculation
2877 16:33:59.659837 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2878 16:33:59.659884 ==
2879 16:33:59.659932 Dram Type= 6, Freq= 0, CH_1, rank 0
2880 16:33:59.659979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2881 16:33:59.660026 ==
2882 16:33:59.660073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2883 16:33:59.660121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2884 16:33:59.660168 [CA 0] Center 37 (7~68) winsize 62
2885 16:33:59.660216 [CA 1] Center 37 (7~68) winsize 62
2886 16:33:59.660263 [CA 2] Center 34 (4~65) winsize 62
2887 16:33:59.660310 [CA 3] Center 33 (3~64) winsize 62
2888 16:33:59.660361 [CA 4] Center 32 (2~63) winsize 62
2889 16:33:59.660411 [CA 5] Center 32 (2~63) winsize 62
2890 16:33:59.660458
2891 16:33:59.660504 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2892 16:33:59.660550
2893 16:33:59.660600 [CATrainingPosCal] consider 1 rank data
2894 16:33:59.660647 u2DelayCellTimex100 = 270/100 ps
2895 16:33:59.660699 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2896 16:33:59.660747 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2897 16:33:59.660794 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2898 16:33:59.660841 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2899 16:33:59.660889 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2900 16:33:59.660936 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2901 16:33:59.660983
2902 16:33:59.661043 CA PerBit enable=1, Macro0, CA PI delay=32
2903 16:33:59.661102
2904 16:33:59.661169 [CBTSetCACLKResult] CA Dly = 32
2905 16:33:59.661231 CS Dly: 6 (0~37)
2906 16:33:59.661279 ==
2907 16:33:59.661327 Dram Type= 6, Freq= 0, CH_1, rank 1
2908 16:33:59.661378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2909 16:33:59.661425 ==
2910 16:33:59.661473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2911 16:33:59.661521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2912 16:33:59.661570 [CA 0] Center 37 (7~68) winsize 62
2913 16:33:59.661621 [CA 1] Center 37 (7~68) winsize 62
2914 16:33:59.661670 [CA 2] Center 34 (3~65) winsize 63
2915 16:33:59.661717 [CA 3] Center 33 (3~64) winsize 62
2916 16:33:59.661764 [CA 4] Center 32 (2~63) winsize 62
2917 16:33:59.661811 [CA 5] Center 32 (1~63) winsize 63
2918 16:33:59.661858
2919 16:33:59.661905 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2920 16:33:59.661952
2921 16:33:59.661998 [CATrainingPosCal] consider 2 rank data
2922 16:33:59.662045 u2DelayCellTimex100 = 270/100 ps
2923 16:33:59.662092 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2924 16:33:59.662139 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2925 16:33:59.662186 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2926 16:33:59.662256 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2927 16:33:59.916853 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2928 16:33:59.917279 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2929 16:33:59.917571
2930 16:33:59.917840 CA PerBit enable=1, Macro0, CA PI delay=32
2931 16:33:59.918103
2932 16:33:59.918414 [CBTSetCACLKResult] CA Dly = 32
2933 16:33:59.918675 CS Dly: 6 (0~38)
2934 16:33:59.918927
2935 16:33:59.919175 ----->DramcWriteLeveling(PI) begin...
2936 16:33:59.919429 ==
2937 16:33:59.919680 Dram Type= 6, Freq= 0, CH_1, rank 0
2938 16:33:59.919928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2939 16:33:59.920194 ==
2940 16:33:59.920446 Write leveling (Byte 0): 20 => 20
2941 16:33:59.920733 Write leveling (Byte 1): 20 => 20
2942 16:33:59.920999 DramcWriteLeveling(PI) end<-----
2943 16:33:59.921257
2944 16:33:59.921496 ==
2945 16:33:59.921739 Dram Type= 6, Freq= 0, CH_1, rank 0
2946 16:33:59.921986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2947 16:33:59.922285 ==
2948 16:33:59.922549 [Gating] SW mode calibration
2949 16:33:59.922894 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2950 16:33:59.923191 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2951 16:33:59.923457 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 16:33:59.924087 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 16:33:59.924376 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 16:33:59.924633 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2955 16:33:59.924885 0 11 16 | B1->B0 | 3434 2a2a | 0 1 | (0 0) (1 0)
2956 16:33:59.925131 0 11 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2957 16:33:59.925376 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 16:33:59.925633 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 16:33:59.925878 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 16:33:59.926121 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 16:33:59.926448 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 16:33:59.926698 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2963 16:33:59.926943 0 12 16 | B1->B0 | 3838 4343 | 1 0 | (0 0) (0 0)
2964 16:33:59.927198 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2965 16:33:59.927449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 16:33:59.927690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 16:33:59.927927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 16:33:59.928170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 16:33:59.928415 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 16:33:59.928660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 16:33:59.928905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2972 16:33:59.929146 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2973 16:33:59.929406 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 16:33:59.929650 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 16:33:59.929891 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 16:33:59.930133 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 16:33:59.930407 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 16:33:59.930653 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 16:33:59.930899 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 16:33:59.931141 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 16:33:59.931394 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 16:33:59.931639 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 16:33:59.931884 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 16:33:59.932125 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 16:33:59.932367 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 16:33:59.932609 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 16:33:59.932851 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2988 16:33:59.933095 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2989 16:33:59.933339 Total UI for P1: 0, mck2ui 16
2990 16:33:59.933585 best dqsien dly found for B0: ( 0, 15, 16)
2991 16:33:59.933832 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 16:33:59.934075 Total UI for P1: 0, mck2ui 16
2993 16:33:59.934411 best dqsien dly found for B1: ( 0, 15, 20)
2994 16:33:59.934667 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2995 16:33:59.934912 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2996 16:33:59.935164
2997 16:33:59.935409 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2998 16:33:59.935654 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2999 16:33:59.935897 [Gating] SW calibration Done
3000 16:33:59.936140 ==
3001 16:33:59.936381 Dram Type= 6, Freq= 0, CH_1, rank 0
3002 16:33:59.936775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3003 16:33:59.937093 ==
3004 16:33:59.937439 RX Vref Scan: 0
3005 16:33:59.937715
3006 16:33:59.937961 RX Vref 0 -> 0, step: 1
3007 16:33:59.938206
3008 16:33:59.938492 RX Delay -40 -> 252, step: 8
3009 16:33:59.938888 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3010 16:33:59.939150 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3011 16:33:59.939397 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3012 16:33:59.939640 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3013 16:33:59.939881 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3014 16:33:59.940122 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3015 16:33:59.940362 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3016 16:33:59.940605 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3017 16:33:59.940845 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3018 16:33:59.941087 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3019 16:33:59.941331 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3020 16:33:59.941573 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3021 16:33:59.941743 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3022 16:33:59.941915 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3023 16:33:59.942085 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3024 16:33:59.942279 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3025 16:33:59.942458 ==
3026 16:33:59.942633 Dram Type= 6, Freq= 0, CH_1, rank 0
3027 16:33:59.942807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3028 16:33:59.942982 ==
3029 16:33:59.943153 DQS Delay:
3030 16:33:59.943321 DQS0 = 0, DQS1 = 0
3031 16:33:59.943496 DQM Delay:
3032 16:33:59.943671 DQM0 = 115, DQM1 = 108
3033 16:33:59.943848 DQ Delay:
3034 16:33:59.944024 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3035 16:33:59.944199 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3036 16:33:59.944375 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3037 16:33:59.944549 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3038 16:33:59.944724
3039 16:33:59.944898
3040 16:33:59.945068 ==
3041 16:33:59.945240 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 16:33:59.945416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3043 16:33:59.945591 ==
3044 16:33:59.945765
3045 16:33:59.945936
3046 16:33:59.946109 TX Vref Scan disable
3047 16:33:59.946307 == TX Byte 0 ==
3048 16:33:59.946485 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3049 16:33:59.946650 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3050 16:33:59.946780 == TX Byte 1 ==
3051 16:33:59.946910 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3052 16:33:59.947041 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3053 16:33:59.947173 ==
3054 16:33:59.947305 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 16:33:59.947436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3056 16:33:59.947569 ==
3057 16:33:59.947701 TX Vref=22, minBit 11, minWin=24, winSum=409
3058 16:33:59.947834 TX Vref=24, minBit 9, minWin=25, winSum=416
3059 16:33:59.947967 TX Vref=26, minBit 1, minWin=26, winSum=425
3060 16:33:59.948355 TX Vref=28, minBit 0, minWin=26, winSum=426
3061 16:33:59.948506 TX Vref=30, minBit 0, minWin=26, winSum=429
3062 16:33:59.948642 TX Vref=32, minBit 0, minWin=26, winSum=428
3063 16:33:59.948789 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
3064 16:33:59.948930
3065 16:33:59.949063 Final TX Range 1 Vref 30
3066 16:33:59.949196
3067 16:33:59.949335 ==
3068 16:33:59.949468 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 16:33:59.949603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3070 16:33:59.949745 ==
3071 16:33:59.949877
3072 16:33:59.950008
3073 16:33:59.950138 TX Vref Scan disable
3074 16:33:59.950289 == TX Byte 0 ==
3075 16:33:59.950424 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3076 16:33:59.950558 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3077 16:33:59.950691 == TX Byte 1 ==
3078 16:33:59.950824 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3079 16:33:59.950957 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3080 16:33:59.951089
3081 16:33:59.951220 [DATLAT]
3082 16:33:59.951351 Freq=1200, CH1 RK0
3083 16:33:59.951483
3084 16:33:59.951616 DATLAT Default: 0xd
3085 16:33:59.951723 0, 0xFFFF, sum = 0
3086 16:33:59.951832 1, 0xFFFF, sum = 0
3087 16:33:59.951938 2, 0xFFFF, sum = 0
3088 16:33:59.952046 3, 0xFFFF, sum = 0
3089 16:33:59.952153 4, 0xFFFF, sum = 0
3090 16:33:59.952261 5, 0xFFFF, sum = 0
3091 16:33:59.952367 6, 0xFFFF, sum = 0
3092 16:33:59.952473 7, 0xFFFF, sum = 0
3093 16:33:59.952579 8, 0xFFFF, sum = 0
3094 16:33:59.952684 9, 0xFFFF, sum = 0
3095 16:33:59.952791 10, 0xFFFF, sum = 0
3096 16:33:59.952898 11, 0x0, sum = 1
3097 16:33:59.953007 12, 0x0, sum = 2
3098 16:33:59.953114 13, 0x0, sum = 3
3099 16:33:59.953220 14, 0x0, sum = 4
3100 16:33:59.953327 best_step = 12
3101 16:33:59.953432
3102 16:33:59.953536 ==
3103 16:33:59.953641 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 16:33:59.953746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3105 16:33:59.953853 ==
3106 16:33:59.953959 RX Vref Scan: 1
3107 16:33:59.954064
3108 16:33:59.954168 Set Vref Range= 32 -> 127
3109 16:33:59.954289
3110 16:33:59.954395 RX Vref 32 -> 127, step: 1
3111 16:33:59.954501
3112 16:33:59.954605 RX Delay -21 -> 252, step: 4
3113 16:33:59.954710
3114 16:33:59.954816 Set Vref, RX VrefLevel [Byte0]: 32
3115 16:33:59.954921 [Byte1]: 32
3116 16:33:59.955026
3117 16:33:59.955132 Set Vref, RX VrefLevel [Byte0]: 33
3118 16:33:59.955237 [Byte1]: 33
3119 16:33:59.955342
3120 16:33:59.955447 Set Vref, RX VrefLevel [Byte0]: 34
3121 16:33:59.955553 [Byte1]: 34
3122 16:33:59.955657
3123 16:33:59.955761 Set Vref, RX VrefLevel [Byte0]: 35
3124 16:33:59.955865 [Byte1]: 35
3125 16:33:59.955970
3126 16:33:59.956075 Set Vref, RX VrefLevel [Byte0]: 36
3127 16:33:59.956188 [Byte1]: 36
3128 16:33:59.956386
3129 16:33:59.956512 Set Vref, RX VrefLevel [Byte0]: 37
3130 16:33:59.956619 [Byte1]: 37
3131 16:33:59.956737
3132 16:33:59.956890 Set Vref, RX VrefLevel [Byte0]: 38
3133 16:33:59.956986 [Byte1]: 38
3134 16:33:59.957077
3135 16:33:59.957165 Set Vref, RX VrefLevel [Byte0]: 39
3136 16:33:59.957252 [Byte1]: 39
3137 16:33:59.957340
3138 16:33:59.957428 Set Vref, RX VrefLevel [Byte0]: 40
3139 16:33:59.957516 [Byte1]: 40
3140 16:33:59.957604
3141 16:33:59.957692 Set Vref, RX VrefLevel [Byte0]: 41
3142 16:33:59.957780 [Byte1]: 41
3143 16:33:59.957867
3144 16:33:59.957954 Set Vref, RX VrefLevel [Byte0]: 42
3145 16:33:59.958043 [Byte1]: 42
3146 16:33:59.958131
3147 16:33:59.958240 Set Vref, RX VrefLevel [Byte0]: 43
3148 16:33:59.958338 [Byte1]: 43
3149 16:33:59.958427
3150 16:33:59.958515 Set Vref, RX VrefLevel [Byte0]: 44
3151 16:33:59.958604 [Byte1]: 44
3152 16:33:59.958693
3153 16:33:59.958781 Set Vref, RX VrefLevel [Byte0]: 45
3154 16:33:59.958869 [Byte1]: 45
3155 16:33:59.958957
3156 16:33:59.959044 Set Vref, RX VrefLevel [Byte0]: 46
3157 16:33:59.959132 [Byte1]: 46
3158 16:33:59.959219
3159 16:33:59.959306 Set Vref, RX VrefLevel [Byte0]: 47
3160 16:33:59.959395 [Byte1]: 47
3161 16:33:59.959483
3162 16:33:59.959569 Set Vref, RX VrefLevel [Byte0]: 48
3163 16:33:59.959657 [Byte1]: 48
3164 16:33:59.959744
3165 16:33:59.959833 Set Vref, RX VrefLevel [Byte0]: 49
3166 16:33:59.959921 [Byte1]: 49
3167 16:33:59.960008
3168 16:33:59.960094 Set Vref, RX VrefLevel [Byte0]: 50
3169 16:33:59.960182 [Byte1]: 50
3170 16:33:59.960270
3171 16:33:59.960357 Set Vref, RX VrefLevel [Byte0]: 51
3172 16:33:59.960444 [Byte1]: 51
3173 16:33:59.960531
3174 16:33:59.960619 Set Vref, RX VrefLevel [Byte0]: 52
3175 16:33:59.960707 [Byte1]: 52
3176 16:33:59.960793
3177 16:33:59.960879 Set Vref, RX VrefLevel [Byte0]: 53
3178 16:33:59.960966 [Byte1]: 53
3179 16:33:59.961053
3180 16:33:59.961140 Set Vref, RX VrefLevel [Byte0]: 54
3181 16:33:59.961230 [Byte1]: 54
3182 16:33:59.961318
3183 16:33:59.961405 Set Vref, RX VrefLevel [Byte0]: 55
3184 16:33:59.961492 [Byte1]: 55
3185 16:33:59.961589
3186 16:33:59.961664 Set Vref, RX VrefLevel [Byte0]: 56
3187 16:33:59.961739 [Byte1]: 56
3188 16:33:59.961814
3189 16:33:59.961889 Set Vref, RX VrefLevel [Byte0]: 57
3190 16:33:59.961964 [Byte1]: 57
3191 16:33:59.962039
3192 16:33:59.962114 Set Vref, RX VrefLevel [Byte0]: 58
3193 16:33:59.962191 [Byte1]: 58
3194 16:33:59.962281
3195 16:33:59.962359 Set Vref, RX VrefLevel [Byte0]: 59
3196 16:33:59.962435 [Byte1]: 59
3197 16:33:59.962510
3198 16:33:59.962584 Set Vref, RX VrefLevel [Byte0]: 60
3199 16:33:59.962660 [Byte1]: 60
3200 16:33:59.962736
3201 16:33:59.962811 Set Vref, RX VrefLevel [Byte0]: 61
3202 16:33:59.962888 [Byte1]: 61
3203 16:33:59.962963
3204 16:33:59.963037 Set Vref, RX VrefLevel [Byte0]: 62
3205 16:33:59.963113 [Byte1]: 62
3206 16:33:59.963188
3207 16:33:59.963264 Set Vref, RX VrefLevel [Byte0]: 63
3208 16:33:59.963339 [Byte1]: 63
3209 16:33:59.963413
3210 16:33:59.963488 Set Vref, RX VrefLevel [Byte0]: 64
3211 16:33:59.963564 [Byte1]: 64
3212 16:33:59.963639
3213 16:33:59.963714 Set Vref, RX VrefLevel [Byte0]: 65
3214 16:33:59.963789 [Byte1]: 65
3215 16:33:59.963865
3216 16:33:59.963940 Final RX Vref Byte 0 = 52 to rank0
3217 16:33:59.964016 Final RX Vref Byte 1 = 49 to rank0
3218 16:33:59.964091 Final RX Vref Byte 0 = 52 to rank1
3219 16:33:59.964166 Final RX Vref Byte 1 = 49 to rank1==
3220 16:33:59.964243 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 16:33:59.964320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3222 16:33:59.964397 ==
3223 16:33:59.964472 DQS Delay:
3224 16:33:59.964548 DQS0 = 0, DQS1 = 0
3225 16:33:59.964624 DQM Delay:
3226 16:33:59.964700 DQM0 = 115, DQM1 = 105
3227 16:33:59.964776 DQ Delay:
3228 16:33:59.964851 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3229 16:33:59.965140 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3230 16:33:59.965226 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3231 16:33:59.965305 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =114
3232 16:33:59.965382
3233 16:33:59.965458
3234 16:33:59.965535 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3235 16:33:59.965615 CH1 RK0: MR19=404, MR18=1B1B
3236 16:33:59.965692 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3237 16:33:59.965768
3238 16:33:59.965845 ----->DramcWriteLeveling(PI) begin...
3239 16:33:59.965923 ==
3240 16:33:59.966000 Dram Type= 6, Freq= 0, CH_1, rank 1
3241 16:33:59.966077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3242 16:33:59.966153 ==
3243 16:33:59.966248 Write leveling (Byte 0): 21 => 21
3244 16:33:59.966329 Write leveling (Byte 1): 22 => 22
3245 16:33:59.966406 DramcWriteLeveling(PI) end<-----
3246 16:33:59.966482
3247 16:33:59.966565 ==
3248 16:33:59.966632 Dram Type= 6, Freq= 0, CH_1, rank 1
3249 16:33:59.966700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3250 16:33:59.966767 ==
3251 16:33:59.966834 [Gating] SW mode calibration
3252 16:33:59.966902 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3253 16:33:59.966972 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3254 16:33:59.967039 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3255 16:33:59.967107 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3256 16:33:59.967174 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3257 16:33:59.967241 0 11 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
3258 16:33:59.967308 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3259 16:33:59.967375 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3260 16:33:59.967441 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 16:33:59.967508 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 16:33:59.967574 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3263 16:33:59.967640 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 16:33:59.967705 0 12 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3265 16:33:59.967772 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3266 16:33:59.967838 0 12 16 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
3267 16:33:59.967904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3268 16:33:59.967971 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 16:33:59.968039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 16:33:59.968106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 16:33:59.968172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 16:33:59.968238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 16:33:59.968305 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3274 16:33:59.968372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3275 16:33:59.968438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3276 16:33:59.968505 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 16:33:59.968574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 16:33:59.968642 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 16:33:59.968709 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 16:33:59.968776 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 16:33:59.968842 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 16:33:59.968909 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 16:33:59.968976 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 16:33:59.969043 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 16:33:59.969111 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 16:33:59.969178 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 16:33:59.969245 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 16:33:59.969311 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 16:33:59.969376 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3290 16:33:59.969443 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3291 16:33:59.969510 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3292 16:33:59.969577 Total UI for P1: 0, mck2ui 16
3293 16:33:59.969645 best dqsien dly found for B0: ( 0, 15, 14)
3294 16:33:59.969712 Total UI for P1: 0, mck2ui 16
3295 16:33:59.969779 best dqsien dly found for B1: ( 0, 15, 16)
3296 16:33:59.969845 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3297 16:33:59.969911 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3298 16:33:59.969977
3299 16:33:59.970043 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3300 16:33:59.970109 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3301 16:33:59.970174 [Gating] SW calibration Done
3302 16:33:59.970256 ==
3303 16:33:59.970325 Dram Type= 6, Freq= 0, CH_1, rank 1
3304 16:33:59.970392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3305 16:33:59.970459 ==
3306 16:33:59.970524 RX Vref Scan: 0
3307 16:33:59.970590
3308 16:33:59.970655 RX Vref 0 -> 0, step: 1
3309 16:33:59.970720
3310 16:33:59.970786 RX Delay -40 -> 252, step: 8
3311 16:33:59.970852 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3312 16:33:59.970917 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3313 16:33:59.970983 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3314 16:33:59.971049 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3315 16:33:59.971115 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3316 16:33:59.971180 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3317 16:33:59.971245 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3318 16:33:59.971311 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3319 16:33:59.971377 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3320 16:33:59.971443 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3321 16:33:59.971508 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3322 16:33:59.971582 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3323 16:33:59.971641 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3324 16:33:59.971698 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3325 16:33:59.971756 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3326 16:33:59.971815 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3327 16:33:59.971873 ==
3328 16:33:59.971932 Dram Type= 6, Freq= 0, CH_1, rank 1
3329 16:33:59.972188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3330 16:33:59.972255 ==
3331 16:33:59.972314 DQS Delay:
3332 16:33:59.972373 DQS0 = 0, DQS1 = 0
3333 16:33:59.972434 DQM Delay:
3334 16:33:59.972492 DQM0 = 116, DQM1 = 105
3335 16:33:59.972550 DQ Delay:
3336 16:33:59.972609 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3337 16:33:59.972668 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3338 16:33:59.972727 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =103
3339 16:33:59.972785 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3340 16:33:59.972844
3341 16:33:59.972903
3342 16:33:59.972960 ==
3343 16:33:59.973017 Dram Type= 6, Freq= 0, CH_1, rank 1
3344 16:33:59.973076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3345 16:33:59.973134 ==
3346 16:33:59.973192
3347 16:33:59.973270
3348 16:33:59.973332 TX Vref Scan disable
3349 16:33:59.973392 == TX Byte 0 ==
3350 16:33:59.973451 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3351 16:33:59.973510 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3352 16:33:59.973569 == TX Byte 1 ==
3353 16:33:59.973628 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3354 16:33:59.973688 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3355 16:33:59.973747 ==
3356 16:33:59.973806 Dram Type= 6, Freq= 0, CH_1, rank 1
3357 16:33:59.973865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3358 16:33:59.973924 ==
3359 16:33:59.973983 TX Vref=22, minBit 11, minWin=25, winSum=427
3360 16:33:59.974042 TX Vref=24, minBit 8, minWin=25, winSum=424
3361 16:33:59.974103 TX Vref=26, minBit 3, minWin=26, winSum=428
3362 16:33:59.974163 TX Vref=28, minBit 3, minWin=26, winSum=429
3363 16:33:59.974235 TX Vref=30, minBit 9, minWin=26, winSum=436
3364 16:33:59.974298 TX Vref=32, minBit 9, minWin=26, winSum=431
3365 16:33:59.974357 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3366 16:33:59.974416
3367 16:33:59.974474 Final TX Range 1 Vref 30
3368 16:33:59.974533
3369 16:33:59.974592 ==
3370 16:33:59.974650 Dram Type= 6, Freq= 0, CH_1, rank 1
3371 16:33:59.974709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3372 16:33:59.974768 ==
3373 16:33:59.974826
3374 16:33:59.974889
3375 16:33:59.974950 TX Vref Scan disable
3376 16:33:59.975009 == TX Byte 0 ==
3377 16:33:59.975068 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3378 16:33:59.975128 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3379 16:33:59.975187 == TX Byte 1 ==
3380 16:33:59.975245 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3381 16:33:59.975303 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3382 16:33:59.975362
3383 16:33:59.975420 [DATLAT]
3384 16:33:59.975486 Freq=1200, CH1 RK1
3385 16:33:59.975569
3386 16:33:59.975661 DATLAT Default: 0xc
3387 16:33:59.975747 0, 0xFFFF, sum = 0
3388 16:33:59.975810 1, 0xFFFF, sum = 0
3389 16:33:59.975872 2, 0xFFFF, sum = 0
3390 16:33:59.975932 3, 0xFFFF, sum = 0
3391 16:33:59.975992 4, 0xFFFF, sum = 0
3392 16:33:59.976052 5, 0xFFFF, sum = 0
3393 16:33:59.976113 6, 0xFFFF, sum = 0
3394 16:33:59.976176 7, 0xFFFF, sum = 0
3395 16:33:59.976236 8, 0xFFFF, sum = 0
3396 16:33:59.976296 9, 0xFFFF, sum = 0
3397 16:33:59.976356 10, 0xFFFF, sum = 0
3398 16:33:59.976416 11, 0x0, sum = 1
3399 16:33:59.976476 12, 0x0, sum = 2
3400 16:33:59.976536 13, 0x0, sum = 3
3401 16:33:59.976605 14, 0x0, sum = 4
3402 16:33:59.976662 best_step = 12
3403 16:33:59.976716
3404 16:33:59.976768 ==
3405 16:33:59.976822 Dram Type= 6, Freq= 0, CH_1, rank 1
3406 16:33:59.976875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3407 16:33:59.976927 ==
3408 16:33:59.976979 RX Vref Scan: 0
3409 16:33:59.977032
3410 16:33:59.977085 RX Vref 0 -> 0, step: 1
3411 16:33:59.977138
3412 16:33:59.977191 RX Delay -29 -> 252, step: 4
3413 16:33:59.977244 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3414 16:33:59.977298 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3415 16:33:59.977351 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3416 16:33:59.977403 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3417 16:33:59.977456 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3418 16:33:59.977510 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3419 16:33:59.977563 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3420 16:33:59.977616 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3421 16:33:59.977669 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3422 16:33:59.977722 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3423 16:33:59.977774 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3424 16:33:59.977827 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3425 16:33:59.977879 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3426 16:33:59.977932 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3427 16:33:59.977984 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3428 16:33:59.978037 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3429 16:33:59.978089 ==
3430 16:33:59.978142 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 16:33:59.978195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3432 16:33:59.978261 ==
3433 16:33:59.978314 DQS Delay:
3434 16:33:59.978367 DQS0 = 0, DQS1 = 0
3435 16:33:59.978419 DQM Delay:
3436 16:33:59.978471 DQM0 = 114, DQM1 = 103
3437 16:33:59.978524 DQ Delay:
3438 16:33:59.978576 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3439 16:33:59.978630 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3440 16:33:59.978682 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3441 16:33:59.978734 DQ12 =114, DQ13 =112, DQ14 =112, DQ15 =110
3442 16:33:59.978786
3443 16:33:59.978838
3444 16:33:59.978890 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3445 16:33:59.978945 CH1 RK1: MR19=404, MR18=707
3446 16:33:59.978997 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3447 16:33:59.979050 [RxdqsGatingPostProcess] freq 1200
3448 16:33:59.979103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3449 16:33:59.979156 Pre-setting of DQS Precalculation
3450 16:33:59.979210 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3451 16:33:59.979263 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3452 16:33:59.979317 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3453 16:33:59.979369
3454 16:33:59.979420
3455 16:33:59.979473 [Calibration Summary] 2400 Mbps
3456 16:33:59.979527 CH 0, Rank 0
3457 16:33:59.979579 SW Impedance : PASS
3458 16:33:59.979632 DUTY Scan : NO K
3459 16:33:59.979699 ZQ Calibration : PASS
3460 16:33:59.979775 Jitter Meter : NO K
3461 16:33:59.979835 CBT Training : PASS
3462 16:33:59.979888 Write leveling : PASS
3463 16:33:59.979941 RX DQS gating : PASS
3464 16:33:59.979993 RX DQ/DQS(RDDQC) : PASS
3465 16:33:59.980045 TX DQ/DQS : PASS
3466 16:33:59.980099 RX DATLAT : PASS
3467 16:33:59.980151 RX DQ/DQS(Engine): PASS
3468 16:33:59.980205 TX OE : NO K
3469 16:33:59.980258 All Pass.
3470 16:33:59.980311
3471 16:33:59.980363 CH 0, Rank 1
3472 16:33:59.980415 SW Impedance : PASS
3473 16:33:59.980468 DUTY Scan : NO K
3474 16:33:59.980520 ZQ Calibration : PASS
3475 16:33:59.980573 Jitter Meter : NO K
3476 16:33:59.980820 CBT Training : PASS
3477 16:33:59.980879 Write leveling : PASS
3478 16:33:59.980933 RX DQS gating : PASS
3479 16:33:59.980987 RX DQ/DQS(RDDQC) : PASS
3480 16:33:59.981040 TX DQ/DQS : PASS
3481 16:33:59.981093 RX DATLAT : PASS
3482 16:33:59.981145 RX DQ/DQS(Engine): PASS
3483 16:33:59.981199 TX OE : NO K
3484 16:33:59.981252 All Pass.
3485 16:33:59.981305
3486 16:33:59.981358 CH 1, Rank 0
3487 16:33:59.981412 SW Impedance : PASS
3488 16:33:59.981465 DUTY Scan : NO K
3489 16:33:59.981518 ZQ Calibration : PASS
3490 16:33:59.981580 Jitter Meter : NO K
3491 16:33:59.981627 CBT Training : PASS
3492 16:33:59.981674 Write leveling : PASS
3493 16:33:59.981721 RX DQS gating : PASS
3494 16:33:59.981769 RX DQ/DQS(RDDQC) : PASS
3495 16:33:59.981816 TX DQ/DQS : PASS
3496 16:33:59.981865 RX DATLAT : PASS
3497 16:33:59.981912 RX DQ/DQS(Engine): PASS
3498 16:33:59.981960 TX OE : NO K
3499 16:33:59.982009 All Pass.
3500 16:33:59.982057
3501 16:33:59.982104 CH 1, Rank 1
3502 16:33:59.982152 SW Impedance : PASS
3503 16:33:59.982199 DUTY Scan : NO K
3504 16:33:59.982268 ZQ Calibration : PASS
3505 16:33:59.982318 Jitter Meter : NO K
3506 16:33:59.982366 CBT Training : PASS
3507 16:33:59.982414 Write leveling : PASS
3508 16:33:59.982462 RX DQS gating : PASS
3509 16:33:59.982513 RX DQ/DQS(RDDQC) : PASS
3510 16:33:59.982561 TX DQ/DQS : PASS
3511 16:33:59.982610 RX DATLAT : PASS
3512 16:33:59.982658 RX DQ/DQS(Engine): PASS
3513 16:33:59.982705 TX OE : NO K
3514 16:33:59.982753 All Pass.
3515 16:33:59.982803
3516 16:33:59.982852 DramC Write-DBI off
3517 16:33:59.982900 PER_BANK_REFRESH: Hybrid Mode
3518 16:33:59.982948 TX_TRACKING: ON
3519 16:33:59.982997 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3520 16:33:59.983047 [FAST_K] Save calibration result to emmc
3521 16:33:59.983096 dramc_set_vcore_voltage set vcore to 650000
3522 16:33:59.983145 Read voltage for 600, 5
3523 16:33:59.983192 Vio18 = 0
3524 16:33:59.983239 Vcore = 650000
3525 16:33:59.983287 Vdram = 0
3526 16:33:59.983335 Vddq = 0
3527 16:33:59.983383 Vmddr = 0
3528 16:33:59.983430 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3529 16:33:59.983480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3530 16:33:59.983532 MEM_TYPE=3, freq_sel=19
3531 16:33:59.983580 sv_algorithm_assistance_LP4_1600
3532 16:33:59.983628 ============ PULL DRAM RESETB DOWN ============
3533 16:33:59.983677 ========== PULL DRAM RESETB DOWN end =========
3534 16:33:59.983728 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3535 16:33:59.983776 ===================================
3536 16:33:59.983824 LPDDR4 DRAM CONFIGURATION
3537 16:33:59.983872 ===================================
3538 16:33:59.983920 EX_ROW_EN[0] = 0x0
3539 16:33:59.983967 EX_ROW_EN[1] = 0x0
3540 16:33:59.984016 LP4Y_EN = 0x0
3541 16:33:59.984064 WORK_FSP = 0x0
3542 16:33:59.984114 WL = 0x2
3543 16:33:59.984162 RL = 0x2
3544 16:33:59.984209 BL = 0x2
3545 16:33:59.984257 RPST = 0x0
3546 16:33:59.984305 RD_PRE = 0x0
3547 16:33:59.984353 WR_PRE = 0x1
3548 16:33:59.984400 WR_PST = 0x0
3549 16:33:59.984447 DBI_WR = 0x0
3550 16:33:59.984497 DBI_RD = 0x0
3551 16:33:59.984560 OTF = 0x1
3552 16:33:59.984609 ===================================
3553 16:33:59.984658 ===================================
3554 16:33:59.984706 ANA top config
3555 16:33:59.984757 ===================================
3556 16:33:59.984806 DLL_ASYNC_EN = 0
3557 16:33:59.984854 ALL_SLAVE_EN = 1
3558 16:33:59.984902 NEW_RANK_MODE = 1
3559 16:33:59.984951 DLL_IDLE_MODE = 1
3560 16:33:59.984999 LP45_APHY_COMB_EN = 1
3561 16:33:59.985047 TX_ODT_DIS = 1
3562 16:33:59.985094 NEW_8X_MODE = 1
3563 16:33:59.985142 ===================================
3564 16:33:59.985190 ===================================
3565 16:33:59.985239 data_rate = 1200
3566 16:33:59.985287 CKR = 1
3567 16:33:59.985336 DQ_P2S_RATIO = 8
3568 16:33:59.985384 ===================================
3569 16:33:59.985432 CA_P2S_RATIO = 8
3570 16:33:59.985481 DQ_CA_OPEN = 0
3571 16:33:59.985529 DQ_SEMI_OPEN = 0
3572 16:33:59.985576 CA_SEMI_OPEN = 0
3573 16:33:59.985624 CA_FULL_RATE = 0
3574 16:33:59.985672 DQ_CKDIV4_EN = 1
3575 16:33:59.985720 CA_CKDIV4_EN = 1
3576 16:33:59.985767 CA_PREDIV_EN = 0
3577 16:33:59.985815 PH8_DLY = 0
3578 16:33:59.985863 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3579 16:33:59.985911 DQ_AAMCK_DIV = 4
3580 16:33:59.985959 CA_AAMCK_DIV = 4
3581 16:33:59.986007 CA_ADMCK_DIV = 4
3582 16:33:59.986055 DQ_TRACK_CA_EN = 0
3583 16:33:59.986103 CA_PICK = 600
3584 16:33:59.986150 CA_MCKIO = 600
3585 16:33:59.986198 MCKIO_SEMI = 0
3586 16:33:59.986263 PLL_FREQ = 2288
3587 16:33:59.986314 DQ_UI_PI_RATIO = 32
3588 16:33:59.986363 CA_UI_PI_RATIO = 0
3589 16:33:59.986411 ===================================
3590 16:33:59.986460 ===================================
3591 16:33:59.986508 memory_type:LPDDR4
3592 16:33:59.986567 GP_NUM : 10
3593 16:33:59.986614 SRAM_EN : 1
3594 16:33:59.986661 MD32_EN : 0
3595 16:33:59.986708 ===================================
3596 16:33:59.986755 [ANA_INIT] >>>>>>>>>>>>>>
3597 16:33:59.986802 <<<<<< [CONFIGURE PHASE]: ANA_TX
3598 16:33:59.986849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3599 16:33:59.986896 ===================================
3600 16:33:59.986942 data_rate = 1200,PCW = 0X5800
3601 16:33:59.986989 ===================================
3602 16:33:59.987036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3603 16:33:59.987083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3604 16:33:59.987130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3605 16:33:59.987178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3606 16:33:59.987225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3607 16:33:59.987272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3608 16:33:59.987319 [ANA_INIT] flow start
3609 16:33:59.987365 [ANA_INIT] PLL >>>>>>>>
3610 16:33:59.987411 [ANA_INIT] PLL <<<<<<<<
3611 16:33:59.987458 [ANA_INIT] MIDPI >>>>>>>>
3612 16:33:59.987504 [ANA_INIT] MIDPI <<<<<<<<
3613 16:33:59.987552 [ANA_INIT] DLL >>>>>>>>
3614 16:33:59.987598 [ANA_INIT] flow end
3615 16:33:59.987644 ============ LP4 DIFF to SE enter ============
3616 16:33:59.987881 ============ LP4 DIFF to SE exit ============
3617 16:33:59.987935 [ANA_INIT] <<<<<<<<<<<<<
3618 16:33:59.987984 [Flow] Enable top DCM control >>>>>
3619 16:33:59.988032 [Flow] Enable top DCM control <<<<<
3620 16:33:59.988081 Enable DLL master slave shuffle
3621 16:33:59.988130 ==============================================================
3622 16:33:59.988178 Gating Mode config
3623 16:33:59.988226 ==============================================================
3624 16:33:59.988273 Config description:
3625 16:33:59.988321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3626 16:33:59.988369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3627 16:33:59.988418 SELPH_MODE 0: By rank 1: By Phase
3628 16:33:59.988466 ==============================================================
3629 16:33:59.988514 GAT_TRACK_EN = 1
3630 16:33:59.988561 RX_GATING_MODE = 2
3631 16:33:59.988608 RX_GATING_TRACK_MODE = 2
3632 16:33:59.988655 SELPH_MODE = 1
3633 16:33:59.988701 PICG_EARLY_EN = 1
3634 16:33:59.988748 VALID_LAT_VALUE = 1
3635 16:33:59.988794 ==============================================================
3636 16:33:59.988841 Enter into Gating configuration >>>>
3637 16:33:59.988889 Exit from Gating configuration <<<<
3638 16:33:59.988935 Enter into DVFS_PRE_config >>>>>
3639 16:33:59.988983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3640 16:33:59.989031 Exit from DVFS_PRE_config <<<<<
3641 16:33:59.989079 Enter into PICG configuration >>>>
3642 16:33:59.989126 Exit from PICG configuration <<<<
3643 16:33:59.989173 [RX_INPUT] configuration >>>>>
3644 16:33:59.989220 [RX_INPUT] configuration <<<<<
3645 16:33:59.989267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3646 16:33:59.989314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3647 16:33:59.989361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3648 16:33:59.989409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3649 16:33:59.989456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3650 16:33:59.989504 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3651 16:33:59.989551 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3652 16:33:59.989598 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3653 16:33:59.989646 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3654 16:33:59.989693 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3655 16:33:59.989741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3656 16:33:59.989788 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3657 16:33:59.989835 ===================================
3658 16:33:59.989882 LPDDR4 DRAM CONFIGURATION
3659 16:33:59.989930 ===================================
3660 16:33:59.989977 EX_ROW_EN[0] = 0x0
3661 16:33:59.990035 EX_ROW_EN[1] = 0x0
3662 16:33:59.990101 LP4Y_EN = 0x0
3663 16:33:59.990156 WORK_FSP = 0x0
3664 16:33:59.990204 WL = 0x2
3665 16:33:59.990289 RL = 0x2
3666 16:33:59.990337 BL = 0x2
3667 16:33:59.990383 RPST = 0x0
3668 16:33:59.990430 RD_PRE = 0x0
3669 16:33:59.990477 WR_PRE = 0x1
3670 16:33:59.990523 WR_PST = 0x0
3671 16:33:59.990569 DBI_WR = 0x0
3672 16:33:59.990616 DBI_RD = 0x0
3673 16:33:59.990662 OTF = 0x1
3674 16:33:59.990709 ===================================
3675 16:33:59.990757 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3676 16:33:59.990804 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3677 16:33:59.990852 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3678 16:33:59.990899 ===================================
3679 16:33:59.990946 LPDDR4 DRAM CONFIGURATION
3680 16:33:59.991003 ===================================
3681 16:33:59.991052 EX_ROW_EN[0] = 0x10
3682 16:33:59.991099 EX_ROW_EN[1] = 0x0
3683 16:33:59.991147 LP4Y_EN = 0x0
3684 16:33:59.991210 WORK_FSP = 0x0
3685 16:33:59.991270 WL = 0x2
3686 16:33:59.991317 RL = 0x2
3687 16:33:59.991364 BL = 0x2
3688 16:33:59.991412 RPST = 0x0
3689 16:33:59.991459 RD_PRE = 0x0
3690 16:33:59.991522 WR_PRE = 0x1
3691 16:33:59.991571 WR_PST = 0x0
3692 16:33:59.991618 DBI_WR = 0x0
3693 16:33:59.991664 DBI_RD = 0x0
3694 16:33:59.991725 OTF = 0x1
3695 16:33:59.991773 ===================================
3696 16:33:59.991821 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3697 16:33:59.991869 nWR fixed to 30
3698 16:33:59.991921 [ModeRegInit_LP4] CH0 RK0
3699 16:33:59.991968 [ModeRegInit_LP4] CH0 RK1
3700 16:33:59.992014 [ModeRegInit_LP4] CH1 RK0
3701 16:33:59.992061 [ModeRegInit_LP4] CH1 RK1
3702 16:33:59.992111 match AC timing 16
3703 16:33:59.992159 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3704 16:33:59.992206 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3705 16:33:59.992254 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3706 16:33:59.992301 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3707 16:33:59.992349 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3708 16:33:59.992396 ==
3709 16:33:59.992443 Dram Type= 6, Freq= 0, CH_0, rank 0
3710 16:33:59.992490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3711 16:33:59.992537 ==
3712 16:33:59.992586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3713 16:33:59.992634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3714 16:33:59.992682 [CA 0] Center 36 (6~66) winsize 61
3715 16:33:59.992729 [CA 1] Center 35 (5~66) winsize 62
3716 16:33:59.992776 [CA 2] Center 34 (4~65) winsize 62
3717 16:33:59.992823 [CA 3] Center 34 (3~65) winsize 63
3718 16:33:59.992870 [CA 4] Center 33 (3~64) winsize 62
3719 16:33:59.992916 [CA 5] Center 33 (3~64) winsize 62
3720 16:33:59.992963
3721 16:33:59.993017 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3722 16:33:59.993065
3723 16:33:59.993111 [CATrainingPosCal] consider 1 rank data
3724 16:33:59.993158 u2DelayCellTimex100 = 270/100 ps
3725 16:33:59.993395 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3726 16:33:59.993449 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3727 16:33:59.993497 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3728 16:33:59.993545 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3729 16:33:59.993592 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3730 16:33:59.993639 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3731 16:33:59.993686
3732 16:33:59.993735 CA PerBit enable=1, Macro0, CA PI delay=33
3733 16:33:59.993783
3734 16:33:59.993831 [CBTSetCACLKResult] CA Dly = 33
3735 16:33:59.993878 CS Dly: 4 (0~35)
3736 16:33:59.993928 ==
3737 16:33:59.993976 Dram Type= 6, Freq= 0, CH_0, rank 1
3738 16:33:59.994023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3739 16:33:59.994070 ==
3740 16:33:59.994131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3741 16:33:59.994193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3742 16:33:59.994290 [CA 0] Center 35 (5~66) winsize 62
3743 16:33:59.994339 [CA 1] Center 35 (5~66) winsize 62
3744 16:33:59.994398 [CA 2] Center 34 (4~65) winsize 62
3745 16:33:59.994448 [CA 3] Center 34 (4~65) winsize 62
3746 16:33:59.994495 [CA 4] Center 33 (2~64) winsize 63
3747 16:33:59.994543 [CA 5] Center 33 (3~64) winsize 62
3748 16:33:59.994593
3749 16:33:59.994640 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3750 16:33:59.994688
3751 16:33:59.994735 [CATrainingPosCal] consider 2 rank data
3752 16:33:59.994782 u2DelayCellTimex100 = 270/100 ps
3753 16:33:59.994830 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3754 16:33:59.994877 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3755 16:33:59.994924 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3756 16:33:59.994974 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3757 16:33:59.995043 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3758 16:33:59.995093 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3759 16:33:59.995141
3760 16:33:59.995187 CA PerBit enable=1, Macro0, CA PI delay=33
3761 16:33:59.995235
3762 16:33:59.995282 [CBTSetCACLKResult] CA Dly = 33
3763 16:33:59.995329 CS Dly: 5 (0~37)
3764 16:33:59.995376
3765 16:33:59.995422 ----->DramcWriteLeveling(PI) begin...
3766 16:33:59.995469 ==
3767 16:33:59.995517 Dram Type= 6, Freq= 0, CH_0, rank 0
3768 16:33:59.995565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3769 16:33:59.995612 ==
3770 16:33:59.995659 Write leveling (Byte 0): 30 => 30
3771 16:33:59.995707 Write leveling (Byte 1): 30 => 30
3772 16:33:59.995753 DramcWriteLeveling(PI) end<-----
3773 16:33:59.995802
3774 16:33:59.995848 ==
3775 16:33:59.995895 Dram Type= 6, Freq= 0, CH_0, rank 0
3776 16:33:59.995942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3777 16:33:59.995989 ==
3778 16:33:59.996036 [Gating] SW mode calibration
3779 16:33:59.996084 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3780 16:33:59.996131 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3781 16:33:59.996180 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3782 16:33:59.996228 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3783 16:33:59.996276 0 5 8 | B1->B0 | 3232 3030 | 1 0 | (1 0) (1 0)
3784 16:33:59.996322 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3785 16:33:59.996369 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3786 16:33:59.996416 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3787 16:33:59.996463 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3788 16:33:59.996510 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3789 16:33:59.996558 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3790 16:33:59.996605 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 16:33:59.996652 0 6 8 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
3792 16:33:59.996699 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3793 16:33:59.996746 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3794 16:33:59.996793 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3795 16:33:59.996841 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3796 16:33:59.996888 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 16:33:59.996936 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 16:33:59.996982 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 16:33:59.997029 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 16:33:59.997076 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3801 16:33:59.997126 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3802 16:33:59.997174 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3803 16:33:59.997232 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3804 16:33:59.997292 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3805 16:33:59.997341 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 16:33:59.997392 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 16:33:59.997440 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 16:33:59.997488 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 16:33:59.997537 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 16:33:59.997584 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 16:33:59.997631 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 16:33:59.997678 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 16:33:59.997726 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 16:33:59.997773 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 16:33:59.997820 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 16:33:59.997870 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3817 16:33:59.997917 Total UI for P1: 0, mck2ui 16
3818 16:33:59.997964 best dqsien dly found for B0: ( 0, 9, 10)
3819 16:33:59.998012 Total UI for P1: 0, mck2ui 16
3820 16:33:59.998071 best dqsien dly found for B1: ( 0, 9, 10)
3821 16:33:59.998120 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3822 16:33:59.998168 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3823 16:33:59.998279
3824 16:33:59.998331 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3825 16:33:59.998379 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3826 16:33:59.998427 [Gating] SW calibration Done
3827 16:33:59.998477 ==
3828 16:33:59.998525 Dram Type= 6, Freq= 0, CH_0, rank 0
3829 16:33:59.998573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3830 16:33:59.998621 ==
3831 16:33:59.998681 RX Vref Scan: 0
3832 16:33:59.998731
3833 16:33:59.998791 RX Vref 0 -> 0, step: 1
3834 16:33:59.998840
3835 16:33:59.999077 RX Delay -230 -> 252, step: 16
3836 16:33:59.999134 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3837 16:33:59.999186 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3838 16:33:59.999234 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3839 16:33:59.999282 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3840 16:33:59.999330 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3841 16:33:59.999377 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3842 16:33:59.999425 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3843 16:33:59.999472 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3844 16:33:59.999518 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3845 16:33:59.999566 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3846 16:33:59.999614 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3847 16:33:59.999661 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3848 16:33:59.999708 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3849 16:33:59.999755 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3850 16:33:59.999815 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3851 16:33:59.999863 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3852 16:33:59.999911 ==
3853 16:33:59.999958 Dram Type= 6, Freq= 0, CH_0, rank 0
3854 16:34:00.000020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3855 16:34:00.000069 ==
3856 16:34:00.000116 DQS Delay:
3857 16:34:00.000174 DQS0 = 0, DQS1 = 0
3858 16:34:00.000223 DQM Delay:
3859 16:34:00.000271 DQM0 = 38, DQM1 = 33
3860 16:34:00.000318 DQ Delay:
3861 16:34:00.000367 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3862 16:34:00.000415 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3863 16:34:00.000462 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3864 16:34:00.000508 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3865 16:34:00.000573
3866 16:34:00.000623
3867 16:34:00.000670 ==
3868 16:34:00.000717 Dram Type= 6, Freq= 0, CH_0, rank 0
3869 16:34:00.000777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3870 16:34:00.000825 ==
3871 16:34:00.000873
3872 16:34:00.000919
3873 16:34:00.000978 TX Vref Scan disable
3874 16:34:00.001026 == TX Byte 0 ==
3875 16:34:00.001073 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3876 16:34:00.001120 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3877 16:34:00.001180 == TX Byte 1 ==
3878 16:34:00.001229 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3879 16:34:00.001277 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3880 16:34:00.001326 ==
3881 16:34:00.001374 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 16:34:00.001422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3883 16:34:00.001470 ==
3884 16:34:00.001517
3885 16:34:00.001563
3886 16:34:00.001609 TX Vref Scan disable
3887 16:34:00.001657 == TX Byte 0 ==
3888 16:34:00.001705 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3889 16:34:00.001753 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3890 16:34:00.001801 == TX Byte 1 ==
3891 16:34:00.001848 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3892 16:34:00.001895 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3893 16:34:00.001944
3894 16:34:00.002025 [DATLAT]
3895 16:34:00.002100 Freq=600, CH0 RK0
3896 16:34:00.002178
3897 16:34:00.002280 DATLAT Default: 0x9
3898 16:34:00.002330 0, 0xFFFF, sum = 0
3899 16:34:00.002378 1, 0xFFFF, sum = 0
3900 16:34:00.002427 2, 0xFFFF, sum = 0
3901 16:34:00.002475 3, 0xFFFF, sum = 0
3902 16:34:00.002523 4, 0xFFFF, sum = 0
3903 16:34:00.002571 5, 0xFFFF, sum = 0
3904 16:34:00.002620 6, 0xFFFF, sum = 0
3905 16:34:00.002667 7, 0x0, sum = 1
3906 16:34:00.002715 8, 0x0, sum = 2
3907 16:34:00.002762 9, 0x0, sum = 3
3908 16:34:00.002810 10, 0x0, sum = 4
3909 16:34:00.002857 best_step = 8
3910 16:34:00.002905
3911 16:34:00.002952 ==
3912 16:34:00.002999 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 16:34:00.003048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3914 16:34:00.003095 ==
3915 16:34:00.003143 RX Vref Scan: 1
3916 16:34:00.003189
3917 16:34:00.003236 RX Vref 0 -> 0, step: 1
3918 16:34:00.003284
3919 16:34:00.003330 RX Delay -195 -> 252, step: 8
3920 16:34:00.003376
3921 16:34:00.003423 Set Vref, RX VrefLevel [Byte0]: 52
3922 16:34:00.003471 [Byte1]: 46
3923 16:34:00.003518
3924 16:34:00.003565 Final RX Vref Byte 0 = 52 to rank0
3925 16:34:00.003613 Final RX Vref Byte 1 = 46 to rank0
3926 16:34:00.003660 Final RX Vref Byte 0 = 52 to rank1
3927 16:34:00.003707 Final RX Vref Byte 1 = 46 to rank1==
3928 16:34:00.003754 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 16:34:00.003800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3930 16:34:00.003848 ==
3931 16:34:00.293788 DQS Delay:
3932 16:34:00.294247 DQS0 = 0, DQS1 = 0
3933 16:34:00.294554 DQM Delay:
3934 16:34:00.294830 DQM0 = 40, DQM1 = 31
3935 16:34:00.295248 DQ Delay:
3936 16:34:00.295722 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3937 16:34:00.296009 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =52
3938 16:34:00.296266 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
3939 16:34:00.296518 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
3940 16:34:00.296768
3941 16:34:00.297036
3942 16:34:00.297310 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3943 16:34:00.297568 CH0 RK0: MR19=808, MR18=5959
3944 16:34:00.297831 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
3945 16:34:00.298092
3946 16:34:00.298408 ----->DramcWriteLeveling(PI) begin...
3947 16:34:00.298845 ==
3948 16:34:00.299121 Dram Type= 6, Freq= 0, CH_0, rank 1
3949 16:34:00.299413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 16:34:00.299737 ==
3951 16:34:00.300037 Write leveling (Byte 0): 31 => 31
3952 16:34:00.300409 Write leveling (Byte 1): 30 => 30
3953 16:34:00.300741 DramcWriteLeveling(PI) end<-----
3954 16:34:00.301085
3955 16:34:00.301334 ==
3956 16:34:00.301581 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 16:34:00.301832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3958 16:34:00.302082 ==
3959 16:34:00.302487 [Gating] SW mode calibration
3960 16:34:00.302900 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3961 16:34:00.303298 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3962 16:34:00.303692 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 16:34:00.304088 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 16:34:00.304482 0 5 8 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 1)
3965 16:34:00.304874 0 5 12 | B1->B0 | 2929 2727 | 1 0 | (1 0) (0 0)
3966 16:34:00.305263 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 16:34:00.305654 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 16:34:00.306045 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 16:34:00.306563 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 16:34:00.306974 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 16:34:00.307419 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 16:34:00.307689 0 6 8 | B1->B0 | 2d2d 3535 | 0 1 | (0 0) (0 0)
3973 16:34:00.308289 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3974 16:34:00.308569 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 16:34:00.308819 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 16:34:00.309063 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 16:34:00.309313 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 16:34:00.309561 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 16:34:00.309821 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 16:34:00.310069 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3981 16:34:00.310368 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 16:34:00.310618 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 16:34:00.310864 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 16:34:00.311106 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 16:34:00.311351 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 16:34:00.311593 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 16:34:00.311838 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 16:34:00.312081 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 16:34:00.312323 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 16:34:00.312594 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 16:34:00.312876 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 16:34:00.313125 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 16:34:00.313370 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 16:34:00.313614 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 16:34:00.313864 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3996 16:34:00.314108 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 16:34:00.314416 Total UI for P1: 0, mck2ui 16
3998 16:34:00.314674 best dqsien dly found for B0: ( 0, 9, 4)
3999 16:34:00.314971 Total UI for P1: 0, mck2ui 16
4000 16:34:00.315242 best dqsien dly found for B1: ( 0, 9, 6)
4001 16:34:00.315666 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4002 16:34:00.316137 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4003 16:34:00.316423
4004 16:34:00.316675 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4005 16:34:00.316951 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4006 16:34:00.317199 [Gating] SW calibration Done
4007 16:34:00.317463 ==
4008 16:34:00.317732 Dram Type= 6, Freq= 0, CH_0, rank 1
4009 16:34:00.318002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4010 16:34:00.318289 ==
4011 16:34:00.318544 RX Vref Scan: 0
4012 16:34:00.318790
4013 16:34:00.319177 RX Vref 0 -> 0, step: 1
4014 16:34:00.319439
4015 16:34:00.319691 RX Delay -230 -> 252, step: 16
4016 16:34:00.319980 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4017 16:34:00.320230 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4018 16:34:00.320476 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4019 16:34:00.320724 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4020 16:34:00.320989 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
4021 16:34:00.321236 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4022 16:34:00.321481 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4023 16:34:00.321686 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4024 16:34:00.321926 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4025 16:34:00.322110 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4026 16:34:00.322353 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4027 16:34:00.322581 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4028 16:34:00.322761 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4029 16:34:00.322939 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4030 16:34:00.323117 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4031 16:34:00.323293 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4032 16:34:00.323467 ==
4033 16:34:00.323645 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 16:34:00.323823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4035 16:34:00.324112 ==
4036 16:34:00.324342 DQS Delay:
4037 16:34:00.324528 DQS0 = 0, DQS1 = 0
4038 16:34:00.324707 DQM Delay:
4039 16:34:00.324883 DQM0 = 39, DQM1 = 31
4040 16:34:00.325060 DQ Delay:
4041 16:34:00.325236 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4042 16:34:00.325412 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4043 16:34:00.325596 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4044 16:34:00.325867 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4045 16:34:00.326052
4046 16:34:00.326242
4047 16:34:00.326425 ==
4048 16:34:00.326593 Dram Type= 6, Freq= 0, CH_0, rank 1
4049 16:34:00.326727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4050 16:34:00.326863 ==
4051 16:34:00.326993
4052 16:34:00.327123
4053 16:34:00.327253 TX Vref Scan disable
4054 16:34:00.327388 == TX Byte 0 ==
4055 16:34:00.327520 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4056 16:34:00.327655 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4057 16:34:00.327786 == TX Byte 1 ==
4058 16:34:00.327919 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4059 16:34:00.328051 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4060 16:34:00.328183 ==
4061 16:34:00.328316 Dram Type= 6, Freq= 0, CH_0, rank 1
4062 16:34:00.328448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4063 16:34:00.328589 ==
4064 16:34:00.328786
4065 16:34:00.328922
4066 16:34:00.329054 TX Vref Scan disable
4067 16:34:00.329274 == TX Byte 0 ==
4068 16:34:00.329437 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4069 16:34:00.329638 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4070 16:34:00.329801 == TX Byte 1 ==
4071 16:34:00.329951 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4072 16:34:00.330096 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4073 16:34:00.330251
4074 16:34:00.330390 [DATLAT]
4075 16:34:00.330524 Freq=600, CH0 RK1
4076 16:34:00.330657
4077 16:34:00.330788 DATLAT Default: 0x8
4078 16:34:00.330919 0, 0xFFFF, sum = 0
4079 16:34:00.331055 1, 0xFFFF, sum = 0
4080 16:34:00.332341 2, 0xFFFF, sum = 0
4081 16:34:00.332512 3, 0xFFFF, sum = 0
4082 16:34:00.335845 4, 0xFFFF, sum = 0
4083 16:34:00.336014 5, 0xFFFF, sum = 0
4084 16:34:00.338897 6, 0xFFFF, sum = 0
4085 16:34:00.339036 7, 0x0, sum = 1
4086 16:34:00.342617 8, 0x0, sum = 2
4087 16:34:00.342829 9, 0x0, sum = 3
4088 16:34:00.342947 10, 0x0, sum = 4
4089 16:34:00.345995 best_step = 8
4090 16:34:00.346160
4091 16:34:00.346295 ==
4092 16:34:00.349416 Dram Type= 6, Freq= 0, CH_0, rank 1
4093 16:34:00.352678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4094 16:34:00.352855 ==
4095 16:34:00.355645 RX Vref Scan: 0
4096 16:34:00.355813
4097 16:34:00.355933 RX Vref 0 -> 0, step: 1
4098 16:34:00.356042
4099 16:34:00.358578 RX Delay -195 -> 252, step: 8
4100 16:34:00.366522 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4101 16:34:00.369937 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4102 16:34:00.373370 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4103 16:34:00.376685 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4104 16:34:00.383032 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4105 16:34:00.386338 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4106 16:34:00.389538 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4107 16:34:00.393213 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4108 16:34:00.396239 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4109 16:34:00.402957 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4110 16:34:00.406430 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4111 16:34:00.409515 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4112 16:34:00.413199 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4113 16:34:00.419863 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4114 16:34:00.423215 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4115 16:34:00.426416 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4116 16:34:00.426883 ==
4117 16:34:00.429642 Dram Type= 6, Freq= 0, CH_0, rank 1
4118 16:34:00.436014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4119 16:34:00.436400 ==
4120 16:34:00.436701 DQS Delay:
4121 16:34:00.436978 DQS0 = 0, DQS1 = 0
4122 16:34:00.439739 DQM Delay:
4123 16:34:00.440121 DQM0 = 42, DQM1 = 32
4124 16:34:00.442799 DQ Delay:
4125 16:34:00.445951 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4126 16:34:00.446390 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4127 16:34:00.449539 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4128 16:34:00.456144 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4129 16:34:00.456529
4130 16:34:00.456822
4131 16:34:00.462810 [DQSOSCAuto] RK1, (LSB)MR18= 0x6868, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4132 16:34:00.466349 CH0 RK1: MR19=808, MR18=6868
4133 16:34:00.472801 CH0_RK1: MR19=0x808, MR18=0x6868, DQSOSC=390, MR23=63, INC=172, DEC=114
4134 16:34:00.476521 [RxdqsGatingPostProcess] freq 600
4135 16:34:00.479727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4136 16:34:00.482815 Pre-setting of DQS Precalculation
4137 16:34:00.489948 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4138 16:34:00.490456 ==
4139 16:34:00.492523 Dram Type= 6, Freq= 0, CH_1, rank 0
4140 16:34:00.496204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4141 16:34:00.496624 ==
4142 16:34:00.502842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4143 16:34:00.505682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4144 16:34:00.509977 [CA 0] Center 35 (5~66) winsize 62
4145 16:34:00.513485 [CA 1] Center 35 (5~66) winsize 62
4146 16:34:00.516494 [CA 2] Center 33 (3~64) winsize 62
4147 16:34:00.519972 [CA 3] Center 33 (3~64) winsize 62
4148 16:34:00.523699 [CA 4] Center 33 (2~64) winsize 63
4149 16:34:00.526781 [CA 5] Center 33 (2~64) winsize 63
4150 16:34:00.527169
4151 16:34:00.529966 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4152 16:34:00.530386
4153 16:34:00.533301 [CATrainingPosCal] consider 1 rank data
4154 16:34:00.536442 u2DelayCellTimex100 = 270/100 ps
4155 16:34:00.539775 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4156 16:34:00.546598 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4157 16:34:00.549519 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4158 16:34:00.553043 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4159 16:34:00.556538 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4160 16:34:00.559488 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4161 16:34:00.559990
4162 16:34:00.563301 CA PerBit enable=1, Macro0, CA PI delay=33
4163 16:34:00.563773
4164 16:34:00.566772 [CBTSetCACLKResult] CA Dly = 33
4165 16:34:00.567162 CS Dly: 4 (0~35)
4166 16:34:00.569826 ==
4167 16:34:00.573365 Dram Type= 6, Freq= 0, CH_1, rank 1
4168 16:34:00.576326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4169 16:34:00.576721 ==
4170 16:34:00.579744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4171 16:34:00.586398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4172 16:34:00.590268 [CA 0] Center 35 (4~66) winsize 63
4173 16:34:00.593504 [CA 1] Center 34 (4~65) winsize 62
4174 16:34:00.596461 [CA 2] Center 33 (3~64) winsize 62
4175 16:34:00.599879 [CA 3] Center 33 (3~64) winsize 62
4176 16:34:00.603352 [CA 4] Center 32 (2~63) winsize 62
4177 16:34:00.606946 [CA 5] Center 32 (2~63) winsize 62
4178 16:34:00.607414
4179 16:34:00.609894 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4180 16:34:00.610422
4181 16:34:00.613317 [CATrainingPosCal] consider 2 rank data
4182 16:34:00.616702 u2DelayCellTimex100 = 270/100 ps
4183 16:34:00.619781 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4184 16:34:00.626707 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4185 16:34:00.629889 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4186 16:34:00.633442 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4187 16:34:00.637026 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4188 16:34:00.639764 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4189 16:34:00.640165
4190 16:34:00.643647 CA PerBit enable=1, Macro0, CA PI delay=32
4191 16:34:00.644035
4192 16:34:00.646532 [CBTSetCACLKResult] CA Dly = 32
4193 16:34:00.646921 CS Dly: 3 (0~34)
4194 16:34:00.647220
4195 16:34:00.650199 ----->DramcWriteLeveling(PI) begin...
4196 16:34:00.653468 ==
4197 16:34:00.656240 Dram Type= 6, Freq= 0, CH_1, rank 0
4198 16:34:00.659880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4199 16:34:00.660266 ==
4200 16:34:00.663524 Write leveling (Byte 0): 29 => 29
4201 16:34:00.666474 Write leveling (Byte 1): 29 => 29
4202 16:34:00.669460 DramcWriteLeveling(PI) end<-----
4203 16:34:00.669976
4204 16:34:00.670406 ==
4205 16:34:00.673115 Dram Type= 6, Freq= 0, CH_1, rank 0
4206 16:34:00.676229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4207 16:34:00.676665 ==
4208 16:34:00.679762 [Gating] SW mode calibration
4209 16:34:00.686271 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4210 16:34:00.692620 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4211 16:34:00.696301 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 16:34:00.699374 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4213 16:34:00.705922 0 5 8 | B1->B0 | 3030 2a2a | 0 0 | (1 0) (0 0)
4214 16:34:00.709287 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 16:34:00.712520 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 16:34:00.719408 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 16:34:00.722387 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 16:34:00.725858 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 16:34:00.732489 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 16:34:00.735771 0 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
4221 16:34:00.739073 0 6 8 | B1->B0 | 3636 4141 | 0 0 | (0 0) (0 0)
4222 16:34:00.746256 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 16:34:00.748635 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 16:34:00.752492 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 16:34:00.758940 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 16:34:00.762282 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 16:34:00.765888 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 16:34:00.772168 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 16:34:00.775205 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4230 16:34:00.778885 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 16:34:00.785405 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 16:34:00.788300 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 16:34:00.792041 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 16:34:00.795357 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 16:34:00.801775 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 16:34:00.805406 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 16:34:00.808744 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 16:34:00.814861 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 16:34:00.818506 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 16:34:00.821541 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 16:34:00.827995 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 16:34:00.831641 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 16:34:00.835035 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 16:34:00.841505 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4245 16:34:00.844708 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4246 16:34:00.847960 Total UI for P1: 0, mck2ui 16
4247 16:34:00.851230 best dqsien dly found for B0: ( 0, 9, 4)
4248 16:34:00.854917 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 16:34:00.857963 Total UI for P1: 0, mck2ui 16
4250 16:34:00.861211 best dqsien dly found for B1: ( 0, 9, 10)
4251 16:34:00.864357 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4252 16:34:00.867749 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4253 16:34:00.871136
4254 16:34:00.873973 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4255 16:34:00.877612 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4256 16:34:00.880822 [Gating] SW calibration Done
4257 16:34:00.880905 ==
4258 16:34:00.884312 Dram Type= 6, Freq= 0, CH_1, rank 0
4259 16:34:00.887417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4260 16:34:00.887493 ==
4261 16:34:00.887552 RX Vref Scan: 0
4262 16:34:00.891041
4263 16:34:00.891176 RX Vref 0 -> 0, step: 1
4264 16:34:00.891243
4265 16:34:00.894154 RX Delay -230 -> 252, step: 16
4266 16:34:00.897523 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4267 16:34:00.904077 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4268 16:34:00.907134 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4269 16:34:00.910824 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4270 16:34:00.913827 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4271 16:34:00.916923 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4272 16:34:00.924106 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4273 16:34:00.927184 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4274 16:34:00.930180 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4275 16:34:00.933490 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4276 16:34:00.940273 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4277 16:34:00.943905 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4278 16:34:00.946906 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4279 16:34:00.950308 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4280 16:34:00.957103 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4281 16:34:00.960289 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4282 16:34:00.960711 ==
4283 16:34:00.964095 Dram Type= 6, Freq= 0, CH_1, rank 0
4284 16:34:00.967072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4285 16:34:00.967431 ==
4286 16:34:00.970374 DQS Delay:
4287 16:34:00.970759 DQS0 = 0, DQS1 = 0
4288 16:34:00.971060 DQM Delay:
4289 16:34:00.973955 DQM0 = 43, DQM1 = 36
4290 16:34:00.974387 DQ Delay:
4291 16:34:00.977292 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4292 16:34:00.980641 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4293 16:34:00.983841 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4294 16:34:00.987183 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4295 16:34:00.987688
4296 16:34:00.988156
4297 16:34:00.988553 ==
4298 16:34:00.990366 Dram Type= 6, Freq= 0, CH_1, rank 0
4299 16:34:00.996986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4300 16:34:00.997494 ==
4301 16:34:00.997923
4302 16:34:00.998373
4303 16:34:00.998678 TX Vref Scan disable
4304 16:34:01.000597 == TX Byte 0 ==
4305 16:34:01.004332 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4306 16:34:01.010693 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4307 16:34:01.010963 == TX Byte 1 ==
4308 16:34:01.013505 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4309 16:34:01.020258 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4310 16:34:01.020554 ==
4311 16:34:01.024061 Dram Type= 6, Freq= 0, CH_1, rank 0
4312 16:34:01.026866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4313 16:34:01.027103 ==
4314 16:34:01.027332
4315 16:34:01.027548
4316 16:34:01.030373 TX Vref Scan disable
4317 16:34:01.033474 == TX Byte 0 ==
4318 16:34:01.037042 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4319 16:34:01.040131 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4320 16:34:01.043732 == TX Byte 1 ==
4321 16:34:01.046586 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4322 16:34:01.050144 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4323 16:34:01.050383
4324 16:34:01.050545 [DATLAT]
4325 16:34:01.053472 Freq=600, CH1 RK0
4326 16:34:01.053741
4327 16:34:01.056711 DATLAT Default: 0x9
4328 16:34:01.056971 0, 0xFFFF, sum = 0
4329 16:34:01.059831 1, 0xFFFF, sum = 0
4330 16:34:01.060040 2, 0xFFFF, sum = 0
4331 16:34:01.063263 3, 0xFFFF, sum = 0
4332 16:34:01.063551 4, 0xFFFF, sum = 0
4333 16:34:01.066590 5, 0xFFFF, sum = 0
4334 16:34:01.066822 6, 0xFFFF, sum = 0
4335 16:34:01.069665 7, 0x0, sum = 1
4336 16:34:01.069946 8, 0x0, sum = 2
4337 16:34:01.073012 9, 0x0, sum = 3
4338 16:34:01.073290 10, 0x0, sum = 4
4339 16:34:01.073528 best_step = 8
4340 16:34:01.073744
4341 16:34:01.076244 ==
4342 16:34:01.079660 Dram Type= 6, Freq= 0, CH_1, rank 0
4343 16:34:01.083003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4344 16:34:01.083208 ==
4345 16:34:01.083365 RX Vref Scan: 1
4346 16:34:01.083510
4347 16:34:01.086273 RX Vref 0 -> 0, step: 1
4348 16:34:01.086478
4349 16:34:01.089424 RX Delay -195 -> 252, step: 8
4350 16:34:01.089589
4351 16:34:01.093110 Set Vref, RX VrefLevel [Byte0]: 52
4352 16:34:01.096220 [Byte1]: 49
4353 16:34:01.096358
4354 16:34:01.099515 Final RX Vref Byte 0 = 52 to rank0
4355 16:34:01.102629 Final RX Vref Byte 1 = 49 to rank0
4356 16:34:01.105897 Final RX Vref Byte 0 = 52 to rank1
4357 16:34:01.109516 Final RX Vref Byte 1 = 49 to rank1==
4358 16:34:01.112463 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 16:34:01.115974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4360 16:34:01.118958 ==
4361 16:34:01.119096 DQS Delay:
4362 16:34:01.119198 DQS0 = 0, DQS1 = 0
4363 16:34:01.122516 DQM Delay:
4364 16:34:01.122714 DQM0 = 36, DQM1 = 29
4365 16:34:01.125958 DQ Delay:
4366 16:34:01.126060 DQ0 =36, DQ1 =32, DQ2 =28, DQ3 =36
4367 16:34:01.129455 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4368 16:34:01.132965 DQ8 =8, DQ9 =20, DQ10 =32, DQ11 =24
4369 16:34:01.136066 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =40
4370 16:34:01.136443
4371 16:34:01.139632
4372 16:34:01.146110 [DQSOSCAuto] RK0, (LSB)MR18= 0x7575, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4373 16:34:01.149167 CH1 RK0: MR19=808, MR18=7575
4374 16:34:01.156208 CH1_RK0: MR19=0x808, MR18=0x7575, DQSOSC=387, MR23=63, INC=175, DEC=116
4375 16:34:01.156708
4376 16:34:01.159256 ----->DramcWriteLeveling(PI) begin...
4377 16:34:01.159644 ==
4378 16:34:01.162736 Dram Type= 6, Freq= 0, CH_1, rank 1
4379 16:34:01.165830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4380 16:34:01.166261 ==
4381 16:34:01.169213 Write leveling (Byte 0): 26 => 26
4382 16:34:01.172227 Write leveling (Byte 1): 28 => 28
4383 16:34:01.175633 DramcWriteLeveling(PI) end<-----
4384 16:34:01.176040
4385 16:34:01.176334 ==
4386 16:34:01.179321 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 16:34:01.182520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4388 16:34:01.183076 ==
4389 16:34:01.185667 [Gating] SW mode calibration
4390 16:34:01.192333 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4391 16:34:01.198727 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4392 16:34:01.201994 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4393 16:34:01.208699 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4394 16:34:01.212173 0 5 8 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4395 16:34:01.215567 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 16:34:01.219059 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 16:34:01.225386 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 16:34:01.228775 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 16:34:01.231822 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 16:34:01.238295 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 16:34:01.241831 0 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4402 16:34:01.245242 0 6 8 | B1->B0 | 3333 4343 | 0 0 | (0 0) (0 0)
4403 16:34:01.251863 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 16:34:01.255433 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 16:34:01.258271 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 16:34:01.264841 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 16:34:01.268551 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 16:34:01.271948 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 16:34:01.278291 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4410 16:34:01.281486 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 16:34:01.285049 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 16:34:01.291981 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 16:34:01.294913 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 16:34:01.298380 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 16:34:01.304785 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 16:34:01.308142 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 16:34:01.311767 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 16:34:01.317935 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 16:34:01.321292 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 16:34:01.324572 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 16:34:01.331208 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 16:34:01.334207 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 16:34:01.338092 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 16:34:01.344255 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 16:34:01.347889 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4426 16:34:01.350931 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 16:34:01.354644 Total UI for P1: 0, mck2ui 16
4428 16:34:01.357421 best dqsien dly found for B0: ( 0, 9, 4)
4429 16:34:01.361036 Total UI for P1: 0, mck2ui 16
4430 16:34:01.364236 best dqsien dly found for B1: ( 0, 9, 6)
4431 16:34:01.367646 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4432 16:34:01.371204 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4433 16:34:01.371588
4434 16:34:01.377620 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4435 16:34:01.381406 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4436 16:34:01.381884 [Gating] SW calibration Done
4437 16:34:01.384200 ==
4438 16:34:01.387106 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 16:34:01.390718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4440 16:34:01.391121 ==
4441 16:34:01.391513 RX Vref Scan: 0
4442 16:34:01.391934
4443 16:34:01.394254 RX Vref 0 -> 0, step: 1
4444 16:34:01.394677
4445 16:34:01.397087 RX Delay -230 -> 252, step: 16
4446 16:34:01.400770 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4447 16:34:01.404411 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4448 16:34:01.410453 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4449 16:34:01.413811 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4450 16:34:01.417549 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4451 16:34:01.420472 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4452 16:34:01.427184 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4453 16:34:01.430331 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4454 16:34:01.433775 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4455 16:34:01.437321 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4456 16:34:01.440155 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4457 16:34:01.446708 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4458 16:34:01.450304 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4459 16:34:01.453529 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4460 16:34:01.456916 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4461 16:34:01.463732 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4462 16:34:01.464126 ==
4463 16:34:01.466774 Dram Type= 6, Freq= 0, CH_1, rank 1
4464 16:34:01.470627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4465 16:34:01.471115 ==
4466 16:34:01.471425 DQS Delay:
4467 16:34:01.473825 DQS0 = 0, DQS1 = 0
4468 16:34:01.474435 DQM Delay:
4469 16:34:01.476571 DQM0 = 39, DQM1 = 33
4470 16:34:01.477028 DQ Delay:
4471 16:34:01.480239 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4472 16:34:01.483592 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4473 16:34:01.486934 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4474 16:34:01.490327 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4475 16:34:01.490716
4476 16:34:01.491015
4477 16:34:01.491313 ==
4478 16:34:01.493193 Dram Type= 6, Freq= 0, CH_1, rank 1
4479 16:34:01.496622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4480 16:34:01.499660 ==
4481 16:34:01.500170
4482 16:34:01.500604
4483 16:34:01.501020 TX Vref Scan disable
4484 16:34:01.503092 == TX Byte 0 ==
4485 16:34:01.506836 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4486 16:34:01.513718 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4487 16:34:01.514200 == TX Byte 1 ==
4488 16:34:01.516250 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4489 16:34:01.523863 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4490 16:34:01.524254 ==
4491 16:34:01.526684 Dram Type= 6, Freq= 0, CH_1, rank 1
4492 16:34:01.530191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4493 16:34:01.530706 ==
4494 16:34:01.531093
4495 16:34:01.531671
4496 16:34:01.532860 TX Vref Scan disable
4497 16:34:01.536188 == TX Byte 0 ==
4498 16:34:01.539786 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4499 16:34:01.542836 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4500 16:34:01.546198 == TX Byte 1 ==
4501 16:34:01.549734 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4502 16:34:01.552970 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4503 16:34:01.553436
4504 16:34:01.553736 [DATLAT]
4505 16:34:01.556556 Freq=600, CH1 RK1
4506 16:34:01.556942
4507 16:34:01.557252 DATLAT Default: 0x8
4508 16:34:01.560395 0, 0xFFFF, sum = 0
4509 16:34:01.561020 1, 0xFFFF, sum = 0
4510 16:34:01.562867 2, 0xFFFF, sum = 0
4511 16:34:01.566441 3, 0xFFFF, sum = 0
4512 16:34:01.566852 4, 0xFFFF, sum = 0
4513 16:34:01.569456 5, 0xFFFF, sum = 0
4514 16:34:01.569843 6, 0xFFFF, sum = 0
4515 16:34:01.573083 7, 0x0, sum = 1
4516 16:34:01.573875 8, 0x0, sum = 2
4517 16:34:01.574373 9, 0x0, sum = 3
4518 16:34:01.576116 10, 0x0, sum = 4
4519 16:34:01.576503 best_step = 8
4520 16:34:01.576833
4521 16:34:01.577254 ==
4522 16:34:01.579285 Dram Type= 6, Freq= 0, CH_1, rank 1
4523 16:34:01.586005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4524 16:34:01.586474 ==
4525 16:34:01.586783 RX Vref Scan: 0
4526 16:34:01.587177
4527 16:34:01.589009 RX Vref 0 -> 0, step: 1
4528 16:34:01.589395
4529 16:34:01.592828 RX Delay -195 -> 252, step: 8
4530 16:34:01.596314 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4531 16:34:01.602975 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4532 16:34:01.605895 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4533 16:34:01.609324 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4534 16:34:01.612615 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4535 16:34:01.619064 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4536 16:34:01.622695 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4537 16:34:01.625701 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4538 16:34:01.629306 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4539 16:34:01.635615 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4540 16:34:01.638959 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4541 16:34:01.642633 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4542 16:34:01.645360 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4543 16:34:01.648836 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4544 16:34:01.655686 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4545 16:34:01.659004 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4546 16:34:01.659482 ==
4547 16:34:01.662189 Dram Type= 6, Freq= 0, CH_1, rank 1
4548 16:34:01.665598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4549 16:34:01.665986 ==
4550 16:34:01.669507 DQS Delay:
4551 16:34:01.669973 DQS0 = 0, DQS1 = 0
4552 16:34:01.672404 DQM Delay:
4553 16:34:01.672875 DQM0 = 36, DQM1 = 29
4554 16:34:01.673183 DQ Delay:
4555 16:34:01.675846 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4556 16:34:01.679180 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4557 16:34:01.682447 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4558 16:34:01.685897 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4559 16:34:01.686396
4560 16:34:01.686698
4561 16:34:01.695591 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4562 16:34:01.698962 CH1 RK1: MR19=808, MR18=6363
4563 16:34:01.702664 CH1_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4564 16:34:01.705469 [RxdqsGatingPostProcess] freq 600
4565 16:34:01.711942 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4566 16:34:01.715419 Pre-setting of DQS Precalculation
4567 16:34:01.718675 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4568 16:34:01.728772 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4569 16:34:01.735445 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4570 16:34:01.735834
4571 16:34:01.736137
4572 16:34:01.738390 [Calibration Summary] 1200 Mbps
4573 16:34:01.738778 CH 0, Rank 0
4574 16:34:01.741478 SW Impedance : PASS
4575 16:34:01.741863 DUTY Scan : NO K
4576 16:34:01.744931 ZQ Calibration : PASS
4577 16:34:01.748618 Jitter Meter : NO K
4578 16:34:01.749131 CBT Training : PASS
4579 16:34:01.751907 Write leveling : PASS
4580 16:34:01.755091 RX DQS gating : PASS
4581 16:34:01.755598 RX DQ/DQS(RDDQC) : PASS
4582 16:34:01.758741 TX DQ/DQS : PASS
4583 16:34:01.761609 RX DATLAT : PASS
4584 16:34:01.762145 RX DQ/DQS(Engine): PASS
4585 16:34:01.764985 TX OE : NO K
4586 16:34:01.765372 All Pass.
4587 16:34:01.765671
4588 16:34:01.768378 CH 0, Rank 1
4589 16:34:01.768843 SW Impedance : PASS
4590 16:34:01.771873 DUTY Scan : NO K
4591 16:34:01.774799 ZQ Calibration : PASS
4592 16:34:01.775229 Jitter Meter : NO K
4593 16:34:01.778525 CBT Training : PASS
4594 16:34:01.778914 Write leveling : PASS
4595 16:34:01.781617 RX DQS gating : PASS
4596 16:34:01.785510 RX DQ/DQS(RDDQC) : PASS
4597 16:34:01.785982 TX DQ/DQS : PASS
4598 16:34:01.788067 RX DATLAT : PASS
4599 16:34:01.791693 RX DQ/DQS(Engine): PASS
4600 16:34:01.792172 TX OE : NO K
4601 16:34:01.794853 All Pass.
4602 16:34:01.795252
4603 16:34:01.795553 CH 1, Rank 0
4604 16:34:01.798507 SW Impedance : PASS
4605 16:34:01.798993 DUTY Scan : NO K
4606 16:34:01.801258 ZQ Calibration : PASS
4607 16:34:01.804677 Jitter Meter : NO K
4608 16:34:01.805143 CBT Training : PASS
4609 16:34:01.808353 Write leveling : PASS
4610 16:34:01.811377 RX DQS gating : PASS
4611 16:34:01.811893 RX DQ/DQS(RDDQC) : PASS
4612 16:34:01.814428 TX DQ/DQS : PASS
4613 16:34:01.818015 RX DATLAT : PASS
4614 16:34:01.818436 RX DQ/DQS(Engine): PASS
4615 16:34:01.821101 TX OE : NO K
4616 16:34:01.821563 All Pass.
4617 16:34:01.821871
4618 16:34:01.824266 CH 1, Rank 1
4619 16:34:01.824653 SW Impedance : PASS
4620 16:34:01.827814 DUTY Scan : NO K
4621 16:34:01.831365 ZQ Calibration : PASS
4622 16:34:01.831760 Jitter Meter : NO K
4623 16:34:01.834170 CBT Training : PASS
4624 16:34:01.837751 Write leveling : PASS
4625 16:34:01.838362 RX DQS gating : PASS
4626 16:34:01.840846 RX DQ/DQS(RDDQC) : PASS
4627 16:34:01.844540 TX DQ/DQS : PASS
4628 16:34:01.844932 RX DATLAT : PASS
4629 16:34:01.847370 RX DQ/DQS(Engine): PASS
4630 16:34:01.847815 TX OE : NO K
4631 16:34:01.850410 All Pass.
4632 16:34:01.850963
4633 16:34:01.851478 DramC Write-DBI off
4634 16:34:01.854042 PER_BANK_REFRESH: Hybrid Mode
4635 16:34:01.857251 TX_TRACKING: ON
4636 16:34:01.864110 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4637 16:34:01.867427 [FAST_K] Save calibration result to emmc
4638 16:34:01.874011 dramc_set_vcore_voltage set vcore to 662500
4639 16:34:01.874506 Read voltage for 933, 3
4640 16:34:01.874828 Vio18 = 0
4641 16:34:01.877593 Vcore = 662500
4642 16:34:01.877980 Vdram = 0
4643 16:34:01.878338 Vddq = 0
4644 16:34:01.880295 Vmddr = 0
4645 16:34:01.883714 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4646 16:34:01.890565 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4647 16:34:01.893958 MEM_TYPE=3, freq_sel=17
4648 16:34:01.894383 sv_algorithm_assistance_LP4_1600
4649 16:34:01.900672 ============ PULL DRAM RESETB DOWN ============
4650 16:34:01.904075 ========== PULL DRAM RESETB DOWN end =========
4651 16:34:01.906826 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4652 16:34:01.910309 ===================================
4653 16:34:01.913622 LPDDR4 DRAM CONFIGURATION
4654 16:34:01.916971 ===================================
4655 16:34:01.920176 EX_ROW_EN[0] = 0x0
4656 16:34:01.920563 EX_ROW_EN[1] = 0x0
4657 16:34:01.923469 LP4Y_EN = 0x0
4658 16:34:01.923851 WORK_FSP = 0x0
4659 16:34:01.927113 WL = 0x3
4660 16:34:01.927510 RL = 0x3
4661 16:34:01.930065 BL = 0x2
4662 16:34:01.930479 RPST = 0x0
4663 16:34:01.933360 RD_PRE = 0x0
4664 16:34:01.933744 WR_PRE = 0x1
4665 16:34:01.936477 WR_PST = 0x0
4666 16:34:01.936984 DBI_WR = 0x0
4667 16:34:01.940122 DBI_RD = 0x0
4668 16:34:01.943637 OTF = 0x1
4669 16:34:01.946669 ===================================
4670 16:34:01.949776 ===================================
4671 16:34:01.950268 ANA top config
4672 16:34:01.953460 ===================================
4673 16:34:01.956433 DLL_ASYNC_EN = 0
4674 16:34:01.959827 ALL_SLAVE_EN = 1
4675 16:34:01.960210 NEW_RANK_MODE = 1
4676 16:34:01.963604 DLL_IDLE_MODE = 1
4677 16:34:01.966468 LP45_APHY_COMB_EN = 1
4678 16:34:01.969978 TX_ODT_DIS = 1
4679 16:34:01.970405 NEW_8X_MODE = 1
4680 16:34:01.973055 ===================================
4681 16:34:01.976921 ===================================
4682 16:34:01.979874 data_rate = 1866
4683 16:34:01.982771 CKR = 1
4684 16:34:01.986786 DQ_P2S_RATIO = 8
4685 16:34:01.989479 ===================================
4686 16:34:01.992991 CA_P2S_RATIO = 8
4687 16:34:01.996620 DQ_CA_OPEN = 0
4688 16:34:01.997022 DQ_SEMI_OPEN = 0
4689 16:34:01.999302 CA_SEMI_OPEN = 0
4690 16:34:02.002929 CA_FULL_RATE = 0
4691 16:34:02.005886 DQ_CKDIV4_EN = 1
4692 16:34:02.009585 CA_CKDIV4_EN = 1
4693 16:34:02.012722 CA_PREDIV_EN = 0
4694 16:34:02.015975 PH8_DLY = 0
4695 16:34:02.016513 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4696 16:34:02.019488 DQ_AAMCK_DIV = 4
4697 16:34:02.022587 CA_AAMCK_DIV = 4
4698 16:34:02.025756 CA_ADMCK_DIV = 4
4699 16:34:02.029141 DQ_TRACK_CA_EN = 0
4700 16:34:02.032723 CA_PICK = 933
4701 16:34:02.033115 CA_MCKIO = 933
4702 16:34:02.036190 MCKIO_SEMI = 0
4703 16:34:02.038987 PLL_FREQ = 3732
4704 16:34:02.042856 DQ_UI_PI_RATIO = 32
4705 16:34:02.045837 CA_UI_PI_RATIO = 0
4706 16:34:02.049027 ===================================
4707 16:34:02.052656 ===================================
4708 16:34:02.055572 memory_type:LPDDR4
4709 16:34:02.055964 GP_NUM : 10
4710 16:34:02.059163 SRAM_EN : 1
4711 16:34:02.059550 MD32_EN : 0
4712 16:34:02.062201 ===================================
4713 16:34:02.065370 [ANA_INIT] >>>>>>>>>>>>>>
4714 16:34:02.068879 <<<<<< [CONFIGURE PHASE]: ANA_TX
4715 16:34:02.071927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4716 16:34:02.075491 ===================================
4717 16:34:02.078558 data_rate = 1866,PCW = 0X8f00
4718 16:34:02.082356 ===================================
4719 16:34:02.085433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4720 16:34:02.092131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4721 16:34:02.095265 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4722 16:34:02.101946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4723 16:34:02.104949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4724 16:34:02.108538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4725 16:34:02.108923 [ANA_INIT] flow start
4726 16:34:02.111598 [ANA_INIT] PLL >>>>>>>>
4727 16:34:02.114907 [ANA_INIT] PLL <<<<<<<<
4728 16:34:02.115293 [ANA_INIT] MIDPI >>>>>>>>
4729 16:34:02.118442 [ANA_INIT] MIDPI <<<<<<<<
4730 16:34:02.121457 [ANA_INIT] DLL >>>>>>>>
4731 16:34:02.121867 [ANA_INIT] flow end
4732 16:34:02.128252 ============ LP4 DIFF to SE enter ============
4733 16:34:02.131719 ============ LP4 DIFF to SE exit ============
4734 16:34:02.134709 [ANA_INIT] <<<<<<<<<<<<<
4735 16:34:02.138692 [Flow] Enable top DCM control >>>>>
4736 16:34:02.141684 [Flow] Enable top DCM control <<<<<
4737 16:34:02.144809 Enable DLL master slave shuffle
4738 16:34:02.148426 ==============================================================
4739 16:34:02.151466 Gating Mode config
4740 16:34:02.154685 ==============================================================
4741 16:34:02.157994 Config description:
4742 16:34:02.167815 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4743 16:34:02.174491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4744 16:34:02.177665 SELPH_MODE 0: By rank 1: By Phase
4745 16:34:02.184247 ==============================================================
4746 16:34:02.187730 GAT_TRACK_EN = 1
4747 16:34:02.190802 RX_GATING_MODE = 2
4748 16:34:02.194277 RX_GATING_TRACK_MODE = 2
4749 16:34:02.197288 SELPH_MODE = 1
4750 16:34:02.200879 PICG_EARLY_EN = 1
4751 16:34:02.204048 VALID_LAT_VALUE = 1
4752 16:34:02.207408 ==============================================================
4753 16:34:02.210567 Enter into Gating configuration >>>>
4754 16:34:02.213763 Exit from Gating configuration <<<<
4755 16:34:02.217531 Enter into DVFS_PRE_config >>>>>
4756 16:34:02.230510 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4757 16:34:02.231045 Exit from DVFS_PRE_config <<<<<
4758 16:34:02.233926 Enter into PICG configuration >>>>
4759 16:34:02.237099 Exit from PICG configuration <<<<
4760 16:34:02.240491 [RX_INPUT] configuration >>>>>
4761 16:34:02.243436 [RX_INPUT] configuration <<<<<
4762 16:34:02.250037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4763 16:34:02.253835 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4764 16:34:02.260065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4765 16:34:02.266977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4766 16:34:02.273422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4767 16:34:02.280157 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4768 16:34:02.283689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4769 16:34:02.286727 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4770 16:34:02.289568 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4771 16:34:02.296970 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4772 16:34:02.299940 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4773 16:34:02.302923 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4774 16:34:02.306253 ===================================
4775 16:34:02.309443 LPDDR4 DRAM CONFIGURATION
4776 16:34:02.313091 ===================================
4777 16:34:02.316269 EX_ROW_EN[0] = 0x0
4778 16:34:02.316655 EX_ROW_EN[1] = 0x0
4779 16:34:02.319713 LP4Y_EN = 0x0
4780 16:34:02.320100 WORK_FSP = 0x0
4781 16:34:02.323193 WL = 0x3
4782 16:34:02.323635 RL = 0x3
4783 16:34:02.326449 BL = 0x2
4784 16:34:02.326913 RPST = 0x0
4785 16:34:02.330145 RD_PRE = 0x0
4786 16:34:02.330665 WR_PRE = 0x1
4787 16:34:02.332849 WR_PST = 0x0
4788 16:34:02.333238 DBI_WR = 0x0
4789 16:34:02.335932 DBI_RD = 0x0
4790 16:34:02.336322 OTF = 0x1
4791 16:34:02.339599 ===================================
4792 16:34:02.346641 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4793 16:34:02.349339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4794 16:34:02.352907 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4795 16:34:02.356032 ===================================
4796 16:34:02.359428 LPDDR4 DRAM CONFIGURATION
4797 16:34:02.362419 ===================================
4798 16:34:02.366036 EX_ROW_EN[0] = 0x10
4799 16:34:02.366458 EX_ROW_EN[1] = 0x0
4800 16:34:02.369007 LP4Y_EN = 0x0
4801 16:34:02.369386 WORK_FSP = 0x0
4802 16:34:02.372415 WL = 0x3
4803 16:34:02.372797 RL = 0x3
4804 16:34:02.375652 BL = 0x2
4805 16:34:02.376031 RPST = 0x0
4806 16:34:02.379218 RD_PRE = 0x0
4807 16:34:02.379608 WR_PRE = 0x1
4808 16:34:02.382359 WR_PST = 0x0
4809 16:34:02.382911 DBI_WR = 0x0
4810 16:34:02.385400 DBI_RD = 0x0
4811 16:34:02.385786 OTF = 0x1
4812 16:34:02.388859 ===================================
4813 16:34:02.395440 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4814 16:34:02.400751 nWR fixed to 30
4815 16:34:02.404333 [ModeRegInit_LP4] CH0 RK0
4816 16:34:02.404732 [ModeRegInit_LP4] CH0 RK1
4817 16:34:02.407225 [ModeRegInit_LP4] CH1 RK0
4818 16:34:02.410278 [ModeRegInit_LP4] CH1 RK1
4819 16:34:02.410670 match AC timing 8
4820 16:34:02.417478 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4821 16:34:02.420354 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4822 16:34:02.423578 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4823 16:34:02.430318 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4824 16:34:02.433504 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4825 16:34:02.433891 ==
4826 16:34:02.436862 Dram Type= 6, Freq= 0, CH_0, rank 0
4827 16:34:02.440161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4828 16:34:02.440552 ==
4829 16:34:02.446733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4830 16:34:02.453642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4831 16:34:02.456792 [CA 0] Center 38 (8~69) winsize 62
4832 16:34:02.459668 [CA 1] Center 38 (8~69) winsize 62
4833 16:34:02.463096 [CA 2] Center 36 (6~67) winsize 62
4834 16:34:02.466752 [CA 3] Center 35 (5~66) winsize 62
4835 16:34:02.469756 [CA 4] Center 35 (5~65) winsize 61
4836 16:34:02.473213 [CA 5] Center 34 (4~65) winsize 62
4837 16:34:02.473602
4838 16:34:02.476271 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4839 16:34:02.476659
4840 16:34:02.479902 [CATrainingPosCal] consider 1 rank data
4841 16:34:02.482806 u2DelayCellTimex100 = 270/100 ps
4842 16:34:02.486573 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4843 16:34:02.489809 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4844 16:34:02.493081 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4845 16:34:02.496452 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4846 16:34:02.502529 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4847 16:34:02.505734 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4848 16:34:02.505898
4849 16:34:02.509377 CA PerBit enable=1, Macro0, CA PI delay=34
4850 16:34:02.509542
4851 16:34:02.512883 [CBTSetCACLKResult] CA Dly = 34
4852 16:34:02.513047 CS Dly: 7 (0~38)
4853 16:34:02.513175 ==
4854 16:34:02.516012 Dram Type= 6, Freq= 0, CH_0, rank 1
4855 16:34:02.519593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4856 16:34:02.522687 ==
4857 16:34:02.525728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4858 16:34:02.533058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4859 16:34:02.536034 [CA 0] Center 38 (8~69) winsize 62
4860 16:34:02.539368 [CA 1] Center 38 (8~69) winsize 62
4861 16:34:02.542334 [CA 2] Center 36 (5~67) winsize 63
4862 16:34:02.546316 [CA 3] Center 35 (5~66) winsize 62
4863 16:34:02.549229 [CA 4] Center 34 (4~65) winsize 62
4864 16:34:02.553115 [CA 5] Center 34 (4~65) winsize 62
4865 16:34:02.553587
4866 16:34:02.556141 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4867 16:34:02.556614
4868 16:34:02.559090 [CATrainingPosCal] consider 2 rank data
4869 16:34:02.562406 u2DelayCellTimex100 = 270/100 ps
4870 16:34:02.566342 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4871 16:34:02.569158 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4872 16:34:02.572372 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4873 16:34:02.579200 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4874 16:34:02.582614 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4875 16:34:02.585983 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4876 16:34:02.586520
4877 16:34:02.589052 CA PerBit enable=1, Macro0, CA PI delay=34
4878 16:34:02.589433
4879 16:34:02.592703 [CBTSetCACLKResult] CA Dly = 34
4880 16:34:02.593178 CS Dly: 7 (0~39)
4881 16:34:02.593485
4882 16:34:02.596104 ----->DramcWriteLeveling(PI) begin...
4883 16:34:02.596579 ==
4884 16:34:02.599224 Dram Type= 6, Freq= 0, CH_0, rank 0
4885 16:34:02.605745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4886 16:34:02.606141 ==
4887 16:34:02.608715 Write leveling (Byte 0): 30 => 30
4888 16:34:02.612109 Write leveling (Byte 1): 26 => 26
4889 16:34:02.615319 DramcWriteLeveling(PI) end<-----
4890 16:34:02.615703
4891 16:34:02.615996 ==
4892 16:34:02.618585 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 16:34:02.622323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 16:34:02.622977 ==
4895 16:34:02.625579 [Gating] SW mode calibration
4896 16:34:02.632295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4897 16:34:02.638533 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4898 16:34:02.641989 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4899 16:34:02.645526 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4900 16:34:02.652325 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4901 16:34:02.654989 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4902 16:34:02.658731 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4903 16:34:02.661732 0 10 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4904 16:34:02.668553 0 10 24 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4905 16:34:02.671881 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4906 16:34:02.675098 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4907 16:34:02.681977 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4908 16:34:02.684739 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4909 16:34:02.688001 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4910 16:34:02.694947 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 16:34:02.698378 0 11 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4912 16:34:02.701400 0 11 24 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
4913 16:34:02.708499 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4914 16:34:02.711128 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4915 16:34:02.714372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4916 16:34:02.721923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4917 16:34:02.724881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4918 16:34:02.728051 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 16:34:02.734606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4920 16:34:02.737525 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4921 16:34:02.740991 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4922 16:34:02.747529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4923 16:34:02.751330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4924 16:34:02.754494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4925 16:34:02.761164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4926 16:34:02.764280 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 16:34:02.767381 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 16:34:02.774238 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 16:34:02.777474 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 16:34:02.781497 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 16:34:02.787746 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 16:34:02.790885 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 16:34:02.794375 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 16:34:02.801156 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 16:34:02.804195 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4936 16:34:02.807506 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4937 16:34:02.813934 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 16:34:02.814433 Total UI for P1: 0, mck2ui 16
4939 16:34:02.820519 best dqsien dly found for B0: ( 0, 14, 22)
4940 16:34:02.820903 Total UI for P1: 0, mck2ui 16
4941 16:34:02.827663 best dqsien dly found for B1: ( 0, 14, 22)
4942 16:34:02.830261 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4943 16:34:02.834125 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4944 16:34:02.834651
4945 16:34:02.837300 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4946 16:34:02.840847 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4947 16:34:02.843667 [Gating] SW calibration Done
4948 16:34:02.844049 ==
4949 16:34:02.847224 Dram Type= 6, Freq= 0, CH_0, rank 0
4950 16:34:02.850429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4951 16:34:02.850897 ==
4952 16:34:02.853592 RX Vref Scan: 0
4953 16:34:02.854100
4954 16:34:02.854497 RX Vref 0 -> 0, step: 1
4955 16:34:02.857304
4956 16:34:02.857763 RX Delay -80 -> 252, step: 8
4957 16:34:02.863500 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4958 16:34:02.867399 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
4959 16:34:02.869957 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4960 16:34:02.873912 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4961 16:34:02.876819 iDelay=208, Bit 4, Center 95 (-8 ~ 199) 208
4962 16:34:02.880263 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4963 16:34:02.886540 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
4964 16:34:02.890585 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
4965 16:34:02.893157 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4966 16:34:02.896592 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4967 16:34:02.899941 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4968 16:34:02.907024 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
4969 16:34:02.910569 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4970 16:34:02.913288 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4971 16:34:02.916813 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4972 16:34:02.919978 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4973 16:34:02.920375 ==
4974 16:34:02.923102 Dram Type= 6, Freq= 0, CH_0, rank 0
4975 16:34:02.929542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4976 16:34:02.929945 ==
4977 16:34:02.930428 DQS Delay:
4978 16:34:02.933394 DQS0 = 0, DQS1 = 0
4979 16:34:02.933872 DQM Delay:
4980 16:34:02.934370 DQM0 = 95, DQM1 = 86
4981 16:34:02.936464 DQ Delay:
4982 16:34:02.939632 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
4983 16:34:02.942871 DQ4 =95, DQ5 =87, DQ6 =111, DQ7 =103
4984 16:34:02.946495 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83
4985 16:34:02.949538 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
4986 16:34:02.950139
4987 16:34:02.950574
4988 16:34:02.950947 ==
4989 16:34:02.952900 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 16:34:02.956342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 16:34:02.956743 ==
4992 16:34:02.957136
4993 16:34:02.957505
4994 16:34:02.959964 TX Vref Scan disable
4995 16:34:02.963066 == TX Byte 0 ==
4996 16:34:02.966296 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
4997 16:34:02.969870 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
4998 16:34:02.972820 == TX Byte 1 ==
4999 16:34:02.976918 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5000 16:34:02.979746 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5001 16:34:02.980238 ==
5002 16:34:02.982968 Dram Type= 6, Freq= 0, CH_0, rank 0
5003 16:34:02.986908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5004 16:34:02.987393 ==
5005 16:34:02.989456
5006 16:34:02.989865
5007 16:34:02.990375 TX Vref Scan disable
5008 16:34:02.992523 == TX Byte 0 ==
5009 16:34:02.996152 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5010 16:34:03.002911 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5011 16:34:03.003357 == TX Byte 1 ==
5012 16:34:03.005804 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5013 16:34:03.013232 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5014 16:34:03.013731
5015 16:34:03.014126 [DATLAT]
5016 16:34:03.014518 Freq=933, CH0 RK0
5017 16:34:03.015002
5018 16:34:03.015817 DATLAT Default: 0xd
5019 16:34:03.016379 0, 0xFFFF, sum = 0
5020 16:34:03.019676 1, 0xFFFF, sum = 0
5021 16:34:03.022409 2, 0xFFFF, sum = 0
5022 16:34:03.022804 3, 0xFFFF, sum = 0
5023 16:34:03.026204 4, 0xFFFF, sum = 0
5024 16:34:03.026730 5, 0xFFFF, sum = 0
5025 16:34:03.029031 6, 0xFFFF, sum = 0
5026 16:34:03.029560 7, 0xFFFF, sum = 0
5027 16:34:03.032305 8, 0xFFFF, sum = 0
5028 16:34:03.032795 9, 0xFFFF, sum = 0
5029 16:34:03.035756 10, 0x0, sum = 1
5030 16:34:03.036303 11, 0x0, sum = 2
5031 16:34:03.039061 12, 0x0, sum = 3
5032 16:34:03.039450 13, 0x0, sum = 4
5033 16:34:03.039758 best_step = 11
5034 16:34:03.042203
5035 16:34:03.042705 ==
5036 16:34:03.045714 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 16:34:03.048963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5038 16:34:03.049350 ==
5039 16:34:03.049649 RX Vref Scan: 1
5040 16:34:03.049925
5041 16:34:03.051984 RX Vref 0 -> 0, step: 1
5042 16:34:03.052366
5043 16:34:03.055572 RX Delay -69 -> 252, step: 4
5044 16:34:03.055969
5045 16:34:03.058789 Set Vref, RX VrefLevel [Byte0]: 52
5046 16:34:03.062601 [Byte1]: 46
5047 16:34:03.065849
5048 16:34:03.066395 Final RX Vref Byte 0 = 52 to rank0
5049 16:34:03.069110 Final RX Vref Byte 1 = 46 to rank0
5050 16:34:03.072721 Final RX Vref Byte 0 = 52 to rank1
5051 16:34:03.075559 Final RX Vref Byte 1 = 46 to rank1==
5052 16:34:03.078765 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 16:34:03.085596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5054 16:34:03.085985 ==
5055 16:34:03.086330 DQS Delay:
5056 16:34:03.086621 DQS0 = 0, DQS1 = 0
5057 16:34:03.089255 DQM Delay:
5058 16:34:03.089638 DQM0 = 96, DQM1 = 87
5059 16:34:03.092199 DQ Delay:
5060 16:34:03.095489 DQ0 =92, DQ1 =96, DQ2 =94, DQ3 =92
5061 16:34:03.099112 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =102
5062 16:34:03.102264 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5063 16:34:03.105269 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =98
5064 16:34:03.105654
5065 16:34:03.105951
5066 16:34:03.111938 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5067 16:34:03.115313 CH0 RK0: MR19=505, MR18=1D1D
5068 16:34:03.121913 CH0_RK0: MR19=0x505, MR18=0x1D1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5069 16:34:03.122413
5070 16:34:03.125020 ----->DramcWriteLeveling(PI) begin...
5071 16:34:03.125422 ==
5072 16:34:03.128649 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 16:34:03.131962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5074 16:34:03.132457 ==
5075 16:34:03.135173 Write leveling (Byte 0): 32 => 32
5076 16:34:03.138332 Write leveling (Byte 1): 30 => 30
5077 16:34:03.141954 DramcWriteLeveling(PI) end<-----
5078 16:34:03.142365
5079 16:34:03.142668 ==
5080 16:34:03.145034 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 16:34:03.148372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5082 16:34:03.148784 ==
5083 16:34:03.151820 [Gating] SW mode calibration
5084 16:34:03.158282 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5085 16:34:03.164673 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5086 16:34:03.168251 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 16:34:03.175162 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 16:34:03.177981 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 16:34:03.181543 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 16:34:03.188247 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5091 16:34:03.191438 0 10 20 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
5092 16:34:03.194318 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5093 16:34:03.200926 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 16:34:03.204570 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 16:34:03.207895 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 16:34:03.214304 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 16:34:03.217586 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 16:34:03.221219 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 16:34:03.227676 0 11 20 | B1->B0 | 2e2e 3535 | 0 0 | (1 1) (0 0)
5100 16:34:03.231749 0 11 24 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
5101 16:34:03.234869 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 16:34:03.241768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 16:34:03.244434 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 16:34:03.247368 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 16:34:03.254403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 16:34:03.257321 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 16:34:03.260544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5108 16:34:03.267118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5109 16:34:03.270498 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 16:34:03.273975 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 16:34:03.280801 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 16:34:03.283557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 16:34:03.287115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 16:34:03.293719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 16:34:03.296593 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 16:34:03.300033 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 16:34:03.306566 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 16:34:03.310019 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 16:34:03.313558 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 16:34:03.320227 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 16:34:03.323325 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 16:34:03.326828 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 16:34:03.333243 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5124 16:34:03.336908 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 16:34:03.339647 Total UI for P1: 0, mck2ui 16
5126 16:34:03.343337 best dqsien dly found for B0: ( 0, 14, 20)
5127 16:34:03.346857 Total UI for P1: 0, mck2ui 16
5128 16:34:03.349953 best dqsien dly found for B1: ( 0, 14, 22)
5129 16:34:03.353047 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5130 16:34:03.356715 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5131 16:34:03.357106
5132 16:34:03.360409 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5133 16:34:03.363010 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5134 16:34:03.366665 [Gating] SW calibration Done
5135 16:34:03.367053 ==
5136 16:34:03.369556 Dram Type= 6, Freq= 0, CH_0, rank 1
5137 16:34:03.372762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5138 16:34:03.376402 ==
5139 16:34:03.376883 RX Vref Scan: 0
5140 16:34:03.377190
5141 16:34:03.379708 RX Vref 0 -> 0, step: 1
5142 16:34:03.380095
5143 16:34:03.380400 RX Delay -80 -> 252, step: 8
5144 16:34:03.386313 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5145 16:34:03.389619 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5146 16:34:03.393368 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5147 16:34:03.396423 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5148 16:34:03.399952 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5149 16:34:03.402755 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5150 16:34:03.409314 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5151 16:34:03.413070 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5152 16:34:03.416321 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5153 16:34:03.419691 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5154 16:34:03.422790 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5155 16:34:03.429437 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5156 16:34:03.432390 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5157 16:34:03.436031 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5158 16:34:03.439854 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5159 16:34:03.442641 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5160 16:34:03.443033 ==
5161 16:34:03.445856 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 16:34:03.452856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5163 16:34:03.453335 ==
5164 16:34:03.453644 DQS Delay:
5165 16:34:03.455732 DQS0 = 0, DQS1 = 0
5166 16:34:03.456134 DQM Delay:
5167 16:34:03.459389 DQM0 = 97, DQM1 = 83
5168 16:34:03.459780 DQ Delay:
5169 16:34:03.462528 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5170 16:34:03.465886 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5171 16:34:03.468981 DQ8 =71, DQ9 =71, DQ10 =83, DQ11 =75
5172 16:34:03.472480 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5173 16:34:03.472874
5174 16:34:03.473180
5175 16:34:03.473650 ==
5176 16:34:03.476173 Dram Type= 6, Freq= 0, CH_0, rank 1
5177 16:34:03.479164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5178 16:34:03.479557 ==
5179 16:34:03.479859
5180 16:34:03.480136
5181 16:34:03.482163 TX Vref Scan disable
5182 16:34:03.485936 == TX Byte 0 ==
5183 16:34:03.489160 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5184 16:34:03.492005 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5185 16:34:03.495421 == TX Byte 1 ==
5186 16:34:03.498992 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5187 16:34:03.502552 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5188 16:34:03.502944 ==
5189 16:34:03.505573 Dram Type= 6, Freq= 0, CH_0, rank 1
5190 16:34:03.509476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5191 16:34:03.512406 ==
5192 16:34:03.512879
5193 16:34:03.513181
5194 16:34:03.513462 TX Vref Scan disable
5195 16:34:03.515881 == TX Byte 0 ==
5196 16:34:03.519451 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5197 16:34:03.525813 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5198 16:34:03.526249 == TX Byte 1 ==
5199 16:34:03.529175 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5200 16:34:03.536078 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5201 16:34:03.536469
5202 16:34:03.536772 [DATLAT]
5203 16:34:03.537054 Freq=933, CH0 RK1
5204 16:34:03.537326
5205 16:34:03.539266 DATLAT Default: 0xb
5206 16:34:03.539654 0, 0xFFFF, sum = 0
5207 16:34:03.542255 1, 0xFFFF, sum = 0
5208 16:34:03.542651 2, 0xFFFF, sum = 0
5209 16:34:03.545786 3, 0xFFFF, sum = 0
5210 16:34:03.548892 4, 0xFFFF, sum = 0
5211 16:34:03.549290 5, 0xFFFF, sum = 0
5212 16:34:03.552225 6, 0xFFFF, sum = 0
5213 16:34:03.552622 7, 0xFFFF, sum = 0
5214 16:34:03.555579 8, 0xFFFF, sum = 0
5215 16:34:03.555974 9, 0xFFFF, sum = 0
5216 16:34:03.559133 10, 0x0, sum = 1
5217 16:34:03.559530 11, 0x0, sum = 2
5218 16:34:03.562407 12, 0x0, sum = 3
5219 16:34:03.562803 13, 0x0, sum = 4
5220 16:34:03.563111 best_step = 11
5221 16:34:03.563388
5222 16:34:03.565857 ==
5223 16:34:03.568956 Dram Type= 6, Freq= 0, CH_0, rank 1
5224 16:34:03.572045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5225 16:34:03.572666 ==
5226 16:34:03.573026 RX Vref Scan: 0
5227 16:34:03.573455
5228 16:34:03.575519 RX Vref 0 -> 0, step: 1
5229 16:34:03.575907
5230 16:34:03.578940 RX Delay -69 -> 252, step: 4
5231 16:34:03.582605 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5232 16:34:03.589112 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5233 16:34:03.592129 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5234 16:34:03.595306 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5235 16:34:03.598876 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5236 16:34:03.602244 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5237 16:34:03.605329 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5238 16:34:03.611692 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5239 16:34:03.615298 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5240 16:34:03.618297 iDelay=203, Bit 9, Center 74 (-13 ~ 162) 176
5241 16:34:03.621926 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5242 16:34:03.625211 iDelay=203, Bit 11, Center 80 (-5 ~ 166) 172
5243 16:34:03.631678 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5244 16:34:03.635305 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5245 16:34:03.638707 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5246 16:34:03.641530 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5247 16:34:03.641804 ==
5248 16:34:03.644916 Dram Type= 6, Freq= 0, CH_0, rank 1
5249 16:34:03.651725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5250 16:34:03.652114 ==
5251 16:34:03.652340 DQS Delay:
5252 16:34:03.652542 DQS0 = 0, DQS1 = 0
5253 16:34:03.654614 DQM Delay:
5254 16:34:03.654888 DQM0 = 97, DQM1 = 86
5255 16:34:03.658468 DQ Delay:
5256 16:34:03.661722 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90
5257 16:34:03.664749 DQ4 =102, DQ5 =90, DQ6 =106, DQ7 =108
5258 16:34:03.668142 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5259 16:34:03.671804 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5260 16:34:03.672337
5261 16:34:03.672799
5262 16:34:03.678380 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5263 16:34:03.681401 CH0 RK1: MR19=505, MR18=2A2A
5264 16:34:03.688042 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5265 16:34:03.691570 [RxdqsGatingPostProcess] freq 933
5266 16:34:03.694995 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5267 16:34:03.698292 Pre-setting of DQS Precalculation
5268 16:34:03.704825 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5269 16:34:03.705214 ==
5270 16:34:03.708000 Dram Type= 6, Freq= 0, CH_1, rank 0
5271 16:34:03.711631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5272 16:34:03.712021 ==
5273 16:34:03.718003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5274 16:34:03.724710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5275 16:34:03.728118 [CA 0] Center 37 (7~68) winsize 62
5276 16:34:03.731183 [CA 1] Center 37 (6~68) winsize 63
5277 16:34:03.734836 [CA 2] Center 35 (5~65) winsize 61
5278 16:34:03.737708 [CA 3] Center 34 (4~65) winsize 62
5279 16:34:03.741227 [CA 4] Center 33 (3~64) winsize 62
5280 16:34:03.741620 [CA 5] Center 33 (3~63) winsize 61
5281 16:34:03.744606
5282 16:34:03.747959 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5283 16:34:03.748347
5284 16:34:03.751351 [CATrainingPosCal] consider 1 rank data
5285 16:34:03.754725 u2DelayCellTimex100 = 270/100 ps
5286 16:34:03.757989 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5287 16:34:03.761539 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5288 16:34:03.764565 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5289 16:34:03.767717 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5290 16:34:03.770947 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5291 16:34:03.774304 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5292 16:34:03.774699
5293 16:34:03.777528 CA PerBit enable=1, Macro0, CA PI delay=33
5294 16:34:03.781035
5295 16:34:03.781436 [CBTSetCACLKResult] CA Dly = 33
5296 16:34:03.784165 CS Dly: 5 (0~36)
5297 16:34:03.784545 ==
5298 16:34:03.787507 Dram Type= 6, Freq= 0, CH_1, rank 1
5299 16:34:03.790713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5300 16:34:03.791105 ==
5301 16:34:03.797206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5302 16:34:03.803788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5303 16:34:03.807349 [CA 0] Center 37 (6~68) winsize 63
5304 16:34:03.810702 [CA 1] Center 37 (6~68) winsize 63
5305 16:34:03.814272 [CA 2] Center 34 (4~65) winsize 62
5306 16:34:03.817226 [CA 3] Center 33 (3~64) winsize 62
5307 16:34:03.820273 [CA 4] Center 33 (2~64) winsize 63
5308 16:34:03.824226 [CA 5] Center 33 (2~64) winsize 63
5309 16:34:03.824499
5310 16:34:03.827230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5311 16:34:03.827506
5312 16:34:03.830485 [CATrainingPosCal] consider 2 rank data
5313 16:34:03.833669 u2DelayCellTimex100 = 270/100 ps
5314 16:34:03.837376 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5315 16:34:03.840857 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5316 16:34:03.844207 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5317 16:34:03.846845 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5318 16:34:03.850407 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5319 16:34:03.854354 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5320 16:34:03.854820
5321 16:34:03.860111 CA PerBit enable=1, Macro0, CA PI delay=33
5322 16:34:03.860501
5323 16:34:03.863797 [CBTSetCACLKResult] CA Dly = 33
5324 16:34:03.864315 CS Dly: 5 (0~37)
5325 16:34:03.864726
5326 16:34:03.866865 ----->DramcWriteLeveling(PI) begin...
5327 16:34:03.867258 ==
5328 16:34:03.870314 Dram Type= 6, Freq= 0, CH_1, rank 0
5329 16:34:03.873873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5330 16:34:03.876838 ==
5331 16:34:03.877225 Write leveling (Byte 0): 23 => 23
5332 16:34:03.880743 Write leveling (Byte 1): 26 => 26
5333 16:34:03.883624 DramcWriteLeveling(PI) end<-----
5334 16:34:03.884232
5335 16:34:03.884578 ==
5336 16:34:03.886849 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 16:34:03.893395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 16:34:03.893785 ==
5339 16:34:03.896603 [Gating] SW mode calibration
5340 16:34:03.903284 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 16:34:03.906653 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5342 16:34:03.913088 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 16:34:03.916637 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 16:34:03.920220 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 16:34:03.923730 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 16:34:03.929859 0 10 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5347 16:34:03.933590 0 10 20 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5348 16:34:03.936414 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5349 16:34:03.943089 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 16:34:03.946766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 16:34:03.949956 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 16:34:03.956532 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 16:34:03.959765 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 16:34:03.963313 0 11 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5355 16:34:03.969463 0 11 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
5356 16:34:03.973050 0 11 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5357 16:34:03.976369 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 16:34:03.982958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 16:34:03.986053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 16:34:03.989551 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 16:34:03.995825 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 16:34:03.999201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5363 16:34:04.002932 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5364 16:34:04.009582 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 16:34:04.012981 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 16:34:04.015684 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 16:34:04.022704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 16:34:04.026148 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 16:34:04.029331 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 16:34:04.035915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 16:34:04.039182 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 16:34:04.042462 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 16:34:04.049263 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 16:34:04.052242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 16:34:04.055720 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 16:34:04.062303 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 16:34:04.065433 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 16:34:04.069492 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 16:34:04.075648 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5380 16:34:04.078417 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 16:34:04.081782 Total UI for P1: 0, mck2ui 16
5382 16:34:04.085148 best dqsien dly found for B0: ( 0, 14, 20)
5383 16:34:04.088739 Total UI for P1: 0, mck2ui 16
5384 16:34:04.091669 best dqsien dly found for B1: ( 0, 14, 20)
5385 16:34:04.095121 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5386 16:34:04.098685 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5387 16:34:04.099075
5388 16:34:04.101452 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5389 16:34:04.105095 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5390 16:34:04.108673 [Gating] SW calibration Done
5391 16:34:04.109067 ==
5392 16:34:04.111437 Dram Type= 6, Freq= 0, CH_1, rank 0
5393 16:34:04.117986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5394 16:34:04.118417 ==
5395 16:34:04.118724 RX Vref Scan: 0
5396 16:34:04.119005
5397 16:34:04.121245 RX Vref 0 -> 0, step: 1
5398 16:34:04.121629
5399 16:34:04.124422 RX Delay -80 -> 252, step: 8
5400 16:34:04.127977 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5401 16:34:04.131501 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5402 16:34:04.134724 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5403 16:34:04.137958 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5404 16:34:04.144469 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5405 16:34:04.147781 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5406 16:34:04.150878 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5407 16:34:04.154599 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5408 16:34:04.157586 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5409 16:34:04.164739 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5410 16:34:04.168275 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5411 16:34:04.170984 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5412 16:34:04.174498 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5413 16:34:04.177526 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5414 16:34:04.184201 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5415 16:34:04.187632 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5416 16:34:04.188027 ==
5417 16:34:04.190762 Dram Type= 6, Freq= 0, CH_1, rank 0
5418 16:34:04.194266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5419 16:34:04.194775 ==
5420 16:34:04.195099 DQS Delay:
5421 16:34:04.197483 DQS0 = 0, DQS1 = 0
5422 16:34:04.197988 DQM Delay:
5423 16:34:04.201084 DQM0 = 95, DQM1 = 87
5424 16:34:04.201471 DQ Delay:
5425 16:34:04.204053 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5426 16:34:04.207531 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5427 16:34:04.210990 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5428 16:34:04.214587 DQ12 =95, DQ13 =103, DQ14 =91, DQ15 =95
5429 16:34:04.214974
5430 16:34:04.215270
5431 16:34:04.215542 ==
5432 16:34:04.217383 Dram Type= 6, Freq= 0, CH_1, rank 0
5433 16:34:04.224266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5434 16:34:04.224652 ==
5435 16:34:04.224949
5436 16:34:04.225224
5437 16:34:04.225561 TX Vref Scan disable
5438 16:34:04.227127 == TX Byte 0 ==
5439 16:34:04.230529 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5440 16:34:04.237571 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5441 16:34:04.237961 == TX Byte 1 ==
5442 16:34:04.240443 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5443 16:34:04.246982 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5444 16:34:04.247371 ==
5445 16:34:04.250914 Dram Type= 6, Freq= 0, CH_1, rank 0
5446 16:34:04.253982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5447 16:34:04.254502 ==
5448 16:34:04.254808
5449 16:34:04.255085
5450 16:34:04.257396 TX Vref Scan disable
5451 16:34:04.257849 == TX Byte 0 ==
5452 16:34:04.264171 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5453 16:34:04.267755 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5454 16:34:04.268254 == TX Byte 1 ==
5455 16:34:04.273713 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5456 16:34:04.277272 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5457 16:34:04.277656
5458 16:34:04.277952 [DATLAT]
5459 16:34:04.280341 Freq=933, CH1 RK0
5460 16:34:04.280720
5461 16:34:04.281017 DATLAT Default: 0xd
5462 16:34:04.283931 0, 0xFFFF, sum = 0
5463 16:34:04.284320 1, 0xFFFF, sum = 0
5464 16:34:04.287865 2, 0xFFFF, sum = 0
5465 16:34:04.288334 3, 0xFFFF, sum = 0
5466 16:34:04.290561 4, 0xFFFF, sum = 0
5467 16:34:04.294008 5, 0xFFFF, sum = 0
5468 16:34:04.294424 6, 0xFFFF, sum = 0
5469 16:34:04.297164 7, 0xFFFF, sum = 0
5470 16:34:04.297636 8, 0xFFFF, sum = 0
5471 16:34:04.300808 9, 0xFFFF, sum = 0
5472 16:34:04.301292 10, 0x0, sum = 1
5473 16:34:04.303979 11, 0x0, sum = 2
5474 16:34:04.304464 12, 0x0, sum = 3
5475 16:34:04.304827 13, 0x0, sum = 4
5476 16:34:04.306815 best_step = 11
5477 16:34:04.307194
5478 16:34:04.307490 ==
5479 16:34:04.310113 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 16:34:04.314269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5481 16:34:04.314745 ==
5482 16:34:04.317387 RX Vref Scan: 1
5483 16:34:04.317873
5484 16:34:04.320077 RX Vref 0 -> 0, step: 1
5485 16:34:04.320461
5486 16:34:04.320761 RX Delay -69 -> 252, step: 4
5487 16:34:04.321036
5488 16:34:04.323587 Set Vref, RX VrefLevel [Byte0]: 52
5489 16:34:04.326553 [Byte1]: 49
5490 16:34:04.331745
5491 16:34:04.332158 Final RX Vref Byte 0 = 52 to rank0
5492 16:34:04.334683 Final RX Vref Byte 1 = 49 to rank0
5493 16:34:04.337844 Final RX Vref Byte 0 = 52 to rank1
5494 16:34:04.341215 Final RX Vref Byte 1 = 49 to rank1==
5495 16:34:04.344767 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 16:34:04.351266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5497 16:34:04.351651 ==
5498 16:34:04.351951 DQS Delay:
5499 16:34:04.354842 DQS0 = 0, DQS1 = 0
5500 16:34:04.355225 DQM Delay:
5501 16:34:04.355527 DQM0 = 93, DQM1 = 87
5502 16:34:04.357713 DQ Delay:
5503 16:34:04.361217 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =90
5504 16:34:04.364856 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =90
5505 16:34:04.367602 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5506 16:34:04.371300 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5507 16:34:04.371682
5508 16:34:04.371979
5509 16:34:04.377970 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5510 16:34:04.380987 CH1 RK0: MR19=505, MR18=3838
5511 16:34:04.387526 CH1_RK0: MR19=0x505, MR18=0x3838, DQSOSC=404, MR23=63, INC=66, DEC=44
5512 16:34:04.387916
5513 16:34:04.391226 ----->DramcWriteLeveling(PI) begin...
5514 16:34:04.391622 ==
5515 16:34:04.394009 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 16:34:04.397379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5517 16:34:04.397785 ==
5518 16:34:04.400609 Write leveling (Byte 0): 22 => 22
5519 16:34:04.404297 Write leveling (Byte 1): 23 => 23
5520 16:34:04.407008 DramcWriteLeveling(PI) end<-----
5521 16:34:04.407430
5522 16:34:04.407730 ==
5523 16:34:04.410207 Dram Type= 6, Freq= 0, CH_1, rank 1
5524 16:34:04.414069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5525 16:34:04.417135 ==
5526 16:34:04.417538 [Gating] SW mode calibration
5527 16:34:04.426858 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5528 16:34:04.430461 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5529 16:34:04.433924 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5530 16:34:04.440459 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5531 16:34:04.443776 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5532 16:34:04.446823 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5533 16:34:04.453565 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
5534 16:34:04.456607 0 10 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5535 16:34:04.459949 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5536 16:34:04.467006 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5537 16:34:04.469880 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5538 16:34:04.473314 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5539 16:34:04.479936 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 16:34:04.483201 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5541 16:34:04.486373 0 11 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5542 16:34:04.492941 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5543 16:34:04.496393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5544 16:34:04.500262 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5545 16:34:04.506328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5546 16:34:04.509812 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5547 16:34:04.513490 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 16:34:04.519520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 16:34:04.522840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 16:34:04.526541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5551 16:34:04.532751 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5552 16:34:04.535831 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5553 16:34:04.539106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5554 16:34:04.546337 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 16:34:04.549878 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 16:34:04.552765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 16:34:04.559413 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 16:34:04.562891 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 16:34:04.566374 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 16:34:04.572580 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 16:34:04.576284 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 16:34:04.579493 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 16:34:04.585963 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 16:34:04.588939 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 16:34:04.592377 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5566 16:34:04.598871 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5567 16:34:04.599260 Total UI for P1: 0, mck2ui 16
5568 16:34:04.605647 best dqsien dly found for B0: ( 0, 14, 16)
5569 16:34:04.608925 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 16:34:04.612242 Total UI for P1: 0, mck2ui 16
5571 16:34:04.615665 best dqsien dly found for B1: ( 0, 14, 20)
5572 16:34:04.619191 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5573 16:34:04.622023 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5574 16:34:04.622466
5575 16:34:04.625929 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5576 16:34:04.629155 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5577 16:34:04.631934 [Gating] SW calibration Done
5578 16:34:04.632324 ==
5579 16:34:04.635551 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 16:34:04.638758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5581 16:34:04.642321 ==
5582 16:34:04.642713 RX Vref Scan: 0
5583 16:34:04.643017
5584 16:34:04.645168 RX Vref 0 -> 0, step: 1
5585 16:34:04.645635
5586 16:34:04.648584 RX Delay -80 -> 252, step: 8
5587 16:34:04.652326 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5588 16:34:04.655428 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5589 16:34:04.658885 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5590 16:34:04.661606 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5591 16:34:04.664917 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5592 16:34:04.671859 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5593 16:34:04.675181 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5594 16:34:04.678553 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5595 16:34:04.682147 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5596 16:34:04.685080 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5597 16:34:04.691963 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5598 16:34:04.694901 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5599 16:34:04.698460 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5600 16:34:04.701295 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5601 16:34:04.705135 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5602 16:34:04.708210 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5603 16:34:04.711329 ==
5604 16:34:04.714787 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 16:34:04.717825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5606 16:34:04.718245 ==
5607 16:34:04.718558 DQS Delay:
5608 16:34:04.721310 DQS0 = 0, DQS1 = 0
5609 16:34:04.721695 DQM Delay:
5610 16:34:04.724783 DQM0 = 95, DQM1 = 87
5611 16:34:04.725169 DQ Delay:
5612 16:34:04.727818 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5613 16:34:04.731384 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5614 16:34:04.734751 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5615 16:34:04.738013 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =91
5616 16:34:04.738723
5617 16:34:04.739159
5618 16:34:04.739647 ==
5619 16:34:04.741226 Dram Type= 6, Freq= 0, CH_1, rank 1
5620 16:34:04.744695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5621 16:34:04.745095 ==
5622 16:34:04.745395
5623 16:34:04.745671
5624 16:34:04.747950 TX Vref Scan disable
5625 16:34:04.751083 == TX Byte 0 ==
5626 16:34:04.754583 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5627 16:34:04.757955 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5628 16:34:04.761735 == TX Byte 1 ==
5629 16:34:04.764364 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5630 16:34:04.767912 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5631 16:34:04.768296 ==
5632 16:34:04.770905 Dram Type= 6, Freq= 0, CH_1, rank 1
5633 16:34:04.777752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5634 16:34:04.778140 ==
5635 16:34:04.778608
5636 16:34:04.779106
5637 16:34:04.779587 TX Vref Scan disable
5638 16:34:04.781717 == TX Byte 0 ==
5639 16:34:04.785172 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5640 16:34:04.791681 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5641 16:34:04.792071 == TX Byte 1 ==
5642 16:34:04.794644 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5643 16:34:04.801322 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5644 16:34:04.801705
5645 16:34:04.802003 [DATLAT]
5646 16:34:04.802329 Freq=933, CH1 RK1
5647 16:34:04.802608
5648 16:34:04.805118 DATLAT Default: 0xb
5649 16:34:04.805584 0, 0xFFFF, sum = 0
5650 16:34:04.808944 1, 0xFFFF, sum = 0
5651 16:34:04.811469 2, 0xFFFF, sum = 0
5652 16:34:04.811866 3, 0xFFFF, sum = 0
5653 16:34:04.814645 4, 0xFFFF, sum = 0
5654 16:34:04.815191 5, 0xFFFF, sum = 0
5655 16:34:04.818078 6, 0xFFFF, sum = 0
5656 16:34:04.818590 7, 0xFFFF, sum = 0
5657 16:34:04.821206 8, 0xFFFF, sum = 0
5658 16:34:04.821718 9, 0xFFFF, sum = 0
5659 16:34:04.824481 10, 0x0, sum = 1
5660 16:34:04.825006 11, 0x0, sum = 2
5661 16:34:04.827907 12, 0x0, sum = 3
5662 16:34:04.828332 13, 0x0, sum = 4
5663 16:34:04.828677 best_step = 11
5664 16:34:04.830811
5665 16:34:04.831199 ==
5666 16:34:04.834568 Dram Type= 6, Freq= 0, CH_1, rank 1
5667 16:34:04.838126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5668 16:34:04.838663 ==
5669 16:34:04.839040 RX Vref Scan: 0
5670 16:34:04.839328
5671 16:34:04.841013 RX Vref 0 -> 0, step: 1
5672 16:34:04.841399
5673 16:34:04.844466 RX Delay -69 -> 252, step: 4
5674 16:34:04.851038 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5675 16:34:04.854265 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5676 16:34:04.857590 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5677 16:34:04.861390 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5678 16:34:04.864151 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5679 16:34:04.867883 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5680 16:34:04.874174 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5681 16:34:04.877456 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5682 16:34:04.881113 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5683 16:34:04.883975 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5684 16:34:04.887513 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5685 16:34:04.890927 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5686 16:34:04.897681 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5687 16:34:04.900404 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5688 16:34:04.904113 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5689 16:34:04.907946 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5690 16:34:04.908431 ==
5691 16:34:04.910916 Dram Type= 6, Freq= 0, CH_1, rank 1
5692 16:34:04.913969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5693 16:34:04.916878 ==
5694 16:34:04.917294 DQS Delay:
5695 16:34:04.917687 DQS0 = 0, DQS1 = 0
5696 16:34:04.920544 DQM Delay:
5697 16:34:04.921056 DQM0 = 96, DQM1 = 87
5698 16:34:04.923809 DQ Delay:
5699 16:34:04.927054 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =94
5700 16:34:04.930668 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5701 16:34:04.933944 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5702 16:34:04.937254 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5703 16:34:04.937735
5704 16:34:04.938050
5705 16:34:04.943828 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5706 16:34:04.947457 CH1 RK1: MR19=505, MR18=2929
5707 16:34:04.953963 CH1_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5708 16:34:04.956915 [RxdqsGatingPostProcess] freq 933
5709 16:34:04.960121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5710 16:34:04.964066 Pre-setting of DQS Precalculation
5711 16:34:04.970486 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5712 16:34:04.977465 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5713 16:34:04.983854 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5714 16:34:04.984256
5715 16:34:04.984557
5716 16:34:04.986990 [Calibration Summary] 1866 Mbps
5717 16:34:04.987379 CH 0, Rank 0
5718 16:34:04.990567 SW Impedance : PASS
5719 16:34:04.993313 DUTY Scan : NO K
5720 16:34:04.993743 ZQ Calibration : PASS
5721 16:34:04.996841 Jitter Meter : NO K
5722 16:34:05.000282 CBT Training : PASS
5723 16:34:05.000670 Write leveling : PASS
5724 16:34:05.003564 RX DQS gating : PASS
5725 16:34:05.006774 RX DQ/DQS(RDDQC) : PASS
5726 16:34:05.007166 TX DQ/DQS : PASS
5727 16:34:05.010445 RX DATLAT : PASS
5728 16:34:05.013379 RX DQ/DQS(Engine): PASS
5729 16:34:05.013767 TX OE : NO K
5730 16:34:05.014191 All Pass.
5731 16:34:05.016946
5732 16:34:05.017390 CH 0, Rank 1
5733 16:34:05.020003 SW Impedance : PASS
5734 16:34:05.020391 DUTY Scan : NO K
5735 16:34:05.023333 ZQ Calibration : PASS
5736 16:34:05.023723 Jitter Meter : NO K
5737 16:34:05.026615 CBT Training : PASS
5738 16:34:05.030447 Write leveling : PASS
5739 16:34:05.030913 RX DQS gating : PASS
5740 16:34:05.033839 RX DQ/DQS(RDDQC) : PASS
5741 16:34:05.036718 TX DQ/DQS : PASS
5742 16:34:05.037188 RX DATLAT : PASS
5743 16:34:05.040100 RX DQ/DQS(Engine): PASS
5744 16:34:05.043141 TX OE : NO K
5745 16:34:05.043651 All Pass.
5746 16:34:05.044089
5747 16:34:05.044508 CH 1, Rank 0
5748 16:34:05.046618 SW Impedance : PASS
5749 16:34:05.050108 DUTY Scan : NO K
5750 16:34:05.050553 ZQ Calibration : PASS
5751 16:34:05.052983 Jitter Meter : NO K
5752 16:34:05.056412 CBT Training : PASS
5753 16:34:05.056801 Write leveling : PASS
5754 16:34:05.059668 RX DQS gating : PASS
5755 16:34:05.062884 RX DQ/DQS(RDDQC) : PASS
5756 16:34:05.063298 TX DQ/DQS : PASS
5757 16:34:05.066527 RX DATLAT : PASS
5758 16:34:05.069822 RX DQ/DQS(Engine): PASS
5759 16:34:05.070333 TX OE : NO K
5760 16:34:05.070650 All Pass.
5761 16:34:05.073389
5762 16:34:05.073774 CH 1, Rank 1
5763 16:34:05.076307 SW Impedance : PASS
5764 16:34:05.076693 DUTY Scan : NO K
5765 16:34:05.079596 ZQ Calibration : PASS
5766 16:34:05.083001 Jitter Meter : NO K
5767 16:34:05.083444 CBT Training : PASS
5768 16:34:05.086320 Write leveling : PASS
5769 16:34:05.086704 RX DQS gating : PASS
5770 16:34:05.089825 RX DQ/DQS(RDDQC) : PASS
5771 16:34:05.092731 TX DQ/DQS : PASS
5772 16:34:05.093191 RX DATLAT : PASS
5773 16:34:05.096175 RX DQ/DQS(Engine): PASS
5774 16:34:05.099345 TX OE : NO K
5775 16:34:05.099732 All Pass.
5776 16:34:05.100032
5777 16:34:05.102645 DramC Write-DBI off
5778 16:34:05.103065 PER_BANK_REFRESH: Hybrid Mode
5779 16:34:05.105941 TX_TRACKING: ON
5780 16:34:05.115567 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5781 16:34:05.119236 [FAST_K] Save calibration result to emmc
5782 16:34:05.122209 dramc_set_vcore_voltage set vcore to 650000
5783 16:34:05.122724 Read voltage for 400, 6
5784 16:34:05.125745 Vio18 = 0
5785 16:34:05.126200 Vcore = 650000
5786 16:34:05.126639 Vdram = 0
5787 16:34:05.129431 Vddq = 0
5788 16:34:05.129815 Vmddr = 0
5789 16:34:05.135381 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5790 16:34:05.138876 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5791 16:34:05.142531 MEM_TYPE=3, freq_sel=20
5792 16:34:05.146130 sv_algorithm_assistance_LP4_800
5793 16:34:05.148627 ============ PULL DRAM RESETB DOWN ============
5794 16:34:05.152288 ========== PULL DRAM RESETB DOWN end =========
5795 16:34:05.159051 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5796 16:34:05.162361 ===================================
5797 16:34:05.162836 LPDDR4 DRAM CONFIGURATION
5798 16:34:05.165232 ===================================
5799 16:34:05.169154 EX_ROW_EN[0] = 0x0
5800 16:34:05.172160 EX_ROW_EN[1] = 0x0
5801 16:34:05.172703 LP4Y_EN = 0x0
5802 16:34:05.175812 WORK_FSP = 0x0
5803 16:34:05.176285 WL = 0x2
5804 16:34:05.178662 RL = 0x2
5805 16:34:05.179052 BL = 0x2
5806 16:34:05.182128 RPST = 0x0
5807 16:34:05.182557 RD_PRE = 0x0
5808 16:34:05.185614 WR_PRE = 0x1
5809 16:34:05.186001 WR_PST = 0x0
5810 16:34:05.188552 DBI_WR = 0x0
5811 16:34:05.188942 DBI_RD = 0x0
5812 16:34:05.191855 OTF = 0x1
5813 16:34:05.195011 ===================================
5814 16:34:05.198678 ===================================
5815 16:34:05.199067 ANA top config
5816 16:34:05.201959 ===================================
5817 16:34:05.204958 DLL_ASYNC_EN = 0
5818 16:34:05.208379 ALL_SLAVE_EN = 1
5819 16:34:05.211591 NEW_RANK_MODE = 1
5820 16:34:05.211983 DLL_IDLE_MODE = 1
5821 16:34:05.214969 LP45_APHY_COMB_EN = 1
5822 16:34:05.218369 TX_ODT_DIS = 1
5823 16:34:05.221653 NEW_8X_MODE = 1
5824 16:34:05.225209 ===================================
5825 16:34:05.228699 ===================================
5826 16:34:05.231894 data_rate = 800
5827 16:34:05.232362 CKR = 1
5828 16:34:05.235224 DQ_P2S_RATIO = 4
5829 16:34:05.238099 ===================================
5830 16:34:05.241744 CA_P2S_RATIO = 4
5831 16:34:05.244761 DQ_CA_OPEN = 0
5832 16:34:05.247775 DQ_SEMI_OPEN = 1
5833 16:34:05.251319 CA_SEMI_OPEN = 1
5834 16:34:05.251777 CA_FULL_RATE = 0
5835 16:34:05.254680 DQ_CKDIV4_EN = 0
5836 16:34:05.257697 CA_CKDIV4_EN = 1
5837 16:34:05.261132 CA_PREDIV_EN = 0
5838 16:34:05.264322 PH8_DLY = 0
5839 16:34:05.268230 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5840 16:34:05.268702 DQ_AAMCK_DIV = 0
5841 16:34:05.271411 CA_AAMCK_DIV = 0
5842 16:34:05.274416 CA_ADMCK_DIV = 4
5843 16:34:05.277905 DQ_TRACK_CA_EN = 0
5844 16:34:05.281188 CA_PICK = 800
5845 16:34:05.284542 CA_MCKIO = 400
5846 16:34:05.287577 MCKIO_SEMI = 400
5847 16:34:05.287964 PLL_FREQ = 3016
5848 16:34:05.291074 DQ_UI_PI_RATIO = 32
5849 16:34:05.294690 CA_UI_PI_RATIO = 32
5850 16:34:05.297426 ===================================
5851 16:34:05.301279 ===================================
5852 16:34:05.304582 memory_type:LPDDR4
5853 16:34:05.305244 GP_NUM : 10
5854 16:34:05.307709 SRAM_EN : 1
5855 16:34:05.311145 MD32_EN : 0
5856 16:34:05.314259 ===================================
5857 16:34:05.314815 [ANA_INIT] >>>>>>>>>>>>>>
5858 16:34:05.317689 <<<<<< [CONFIGURE PHASE]: ANA_TX
5859 16:34:05.321025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5860 16:34:05.324154 ===================================
5861 16:34:05.327509 data_rate = 800,PCW = 0X7400
5862 16:34:05.331072 ===================================
5863 16:34:05.333893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5864 16:34:05.340943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5865 16:34:05.350659 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5866 16:34:05.357530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5867 16:34:05.360887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5868 16:34:05.363626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5869 16:34:05.364015 [ANA_INIT] flow start
5870 16:34:05.367390 [ANA_INIT] PLL >>>>>>>>
5871 16:34:05.370133 [ANA_INIT] PLL <<<<<<<<
5872 16:34:05.373589 [ANA_INIT] MIDPI >>>>>>>>
5873 16:34:05.373975 [ANA_INIT] MIDPI <<<<<<<<
5874 16:34:05.376866 [ANA_INIT] DLL >>>>>>>>
5875 16:34:05.379988 [ANA_INIT] flow end
5876 16:34:05.383750 ============ LP4 DIFF to SE enter ============
5877 16:34:05.386622 ============ LP4 DIFF to SE exit ============
5878 16:34:05.390013 [ANA_INIT] <<<<<<<<<<<<<
5879 16:34:05.393654 [Flow] Enable top DCM control >>>>>
5880 16:34:05.396627 [Flow] Enable top DCM control <<<<<
5881 16:34:05.400566 Enable DLL master slave shuffle
5882 16:34:05.403227 ==============================================================
5883 16:34:05.406414 Gating Mode config
5884 16:34:05.413148 ==============================================================
5885 16:34:05.413679 Config description:
5886 16:34:05.423391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5887 16:34:05.430276 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5888 16:34:05.432971 SELPH_MODE 0: By rank 1: By Phase
5889 16:34:05.439747 ==============================================================
5890 16:34:05.442848 GAT_TRACK_EN = 0
5891 16:34:05.446275 RX_GATING_MODE = 2
5892 16:34:05.449747 RX_GATING_TRACK_MODE = 2
5893 16:34:05.453148 SELPH_MODE = 1
5894 16:34:05.456425 PICG_EARLY_EN = 1
5895 16:34:05.459765 VALID_LAT_VALUE = 1
5896 16:34:05.462768 ==============================================================
5897 16:34:05.466255 Enter into Gating configuration >>>>
5898 16:34:05.469657 Exit from Gating configuration <<<<
5899 16:34:05.472973 Enter into DVFS_PRE_config >>>>>
5900 16:34:05.486079 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5901 16:34:05.486678 Exit from DVFS_PRE_config <<<<<
5902 16:34:05.489532 Enter into PICG configuration >>>>
5903 16:34:05.492709 Exit from PICG configuration <<<<
5904 16:34:05.495726 [RX_INPUT] configuration >>>>>
5905 16:34:05.499139 [RX_INPUT] configuration <<<<<
5906 16:34:05.505870 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5907 16:34:05.509080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5908 16:34:05.516247 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5909 16:34:05.522644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5910 16:34:05.529146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5911 16:34:05.535717 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5912 16:34:05.539016 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5913 16:34:05.542107 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5914 16:34:05.545485 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5915 16:34:05.552401 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5916 16:34:05.555581 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5917 16:34:05.559144 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5918 16:34:05.561934 ===================================
5919 16:34:05.565550 LPDDR4 DRAM CONFIGURATION
5920 16:34:05.568467 ===================================
5921 16:34:05.571968 EX_ROW_EN[0] = 0x0
5922 16:34:05.572465 EX_ROW_EN[1] = 0x0
5923 16:34:05.575649 LP4Y_EN = 0x0
5924 16:34:05.576233 WORK_FSP = 0x0
5925 16:34:05.578769 WL = 0x2
5926 16:34:05.579154 RL = 0x2
5927 16:34:05.582367 BL = 0x2
5928 16:34:05.582787 RPST = 0x0
5929 16:34:05.585435 RD_PRE = 0x0
5930 16:34:05.585843 WR_PRE = 0x1
5931 16:34:05.588291 WR_PST = 0x0
5932 16:34:05.588674 DBI_WR = 0x0
5933 16:34:05.592080 DBI_RD = 0x0
5934 16:34:05.592716 OTF = 0x1
5935 16:34:05.595599 ===================================
5936 16:34:05.601895 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5937 16:34:05.604991 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5938 16:34:05.608321 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5939 16:34:05.611501 ===================================
5940 16:34:05.614973 LPDDR4 DRAM CONFIGURATION
5941 16:34:05.618194 ===================================
5942 16:34:05.621647 EX_ROW_EN[0] = 0x10
5943 16:34:05.622034 EX_ROW_EN[1] = 0x0
5944 16:34:05.625196 LP4Y_EN = 0x0
5945 16:34:05.625584 WORK_FSP = 0x0
5946 16:34:05.628224 WL = 0x2
5947 16:34:05.628612 RL = 0x2
5948 16:34:05.631739 BL = 0x2
5949 16:34:05.632253 RPST = 0x0
5950 16:34:05.634641 RD_PRE = 0x0
5951 16:34:05.635108 WR_PRE = 0x1
5952 16:34:05.638511 WR_PST = 0x0
5953 16:34:05.638898 DBI_WR = 0x0
5954 16:34:05.641260 DBI_RD = 0x0
5955 16:34:05.641641 OTF = 0x1
5956 16:34:05.644672 ===================================
5957 16:34:05.651329 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5958 16:34:05.655987 nWR fixed to 30
5959 16:34:05.659579 [ModeRegInit_LP4] CH0 RK0
5960 16:34:05.659991 [ModeRegInit_LP4] CH0 RK1
5961 16:34:05.662640 [ModeRegInit_LP4] CH1 RK0
5962 16:34:05.666077 [ModeRegInit_LP4] CH1 RK1
5963 16:34:05.666529 match AC timing 18
5964 16:34:05.672645 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5965 16:34:05.676086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5966 16:34:05.679085 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5967 16:34:05.685584 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5968 16:34:05.689377 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5969 16:34:05.689942 ==
5970 16:34:05.692429 Dram Type= 6, Freq= 0, CH_0, rank 0
5971 16:34:05.696085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5972 16:34:05.696509 ==
5973 16:34:05.702682 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5974 16:34:05.709248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5975 16:34:05.712472 [CA 0] Center 36 (8~64) winsize 57
5976 16:34:05.716016 [CA 1] Center 36 (8~64) winsize 57
5977 16:34:05.719194 [CA 2] Center 36 (8~64) winsize 57
5978 16:34:05.722287 [CA 3] Center 36 (8~64) winsize 57
5979 16:34:05.722688 [CA 4] Center 36 (8~64) winsize 57
5980 16:34:05.726018 [CA 5] Center 36 (8~64) winsize 57
5981 16:34:05.726776
5982 16:34:05.732556 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5983 16:34:05.733043
5984 16:34:05.736238 [CATrainingPosCal] consider 1 rank data
5985 16:34:05.738889 u2DelayCellTimex100 = 270/100 ps
5986 16:34:05.742574 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5987 16:34:05.745648 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5988 16:34:05.749029 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5989 16:34:05.752723 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5990 16:34:05.755832 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5991 16:34:05.758676 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 16:34:05.759065
5993 16:34:05.762113 CA PerBit enable=1, Macro0, CA PI delay=36
5994 16:34:05.762547
5995 16:34:05.765341 [CBTSetCACLKResult] CA Dly = 36
5996 16:34:05.768705 CS Dly: 1 (0~32)
5997 16:34:05.769111 ==
5998 16:34:05.771840 Dram Type= 6, Freq= 0, CH_0, rank 1
5999 16:34:05.775176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6000 16:34:05.775561 ==
6001 16:34:05.781769 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6002 16:34:05.789169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6003 16:34:05.791903 [CA 0] Center 36 (8~64) winsize 57
6004 16:34:05.792393 [CA 1] Center 36 (8~64) winsize 57
6005 16:34:05.794884 [CA 2] Center 36 (8~64) winsize 57
6006 16:34:05.798435 [CA 3] Center 36 (8~64) winsize 57
6007 16:34:05.801736 [CA 4] Center 36 (8~64) winsize 57
6008 16:34:05.804718 [CA 5] Center 36 (8~64) winsize 57
6009 16:34:05.805207
6010 16:34:05.808324 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6011 16:34:05.808746
6012 16:34:05.812053 [CATrainingPosCal] consider 2 rank data
6013 16:34:05.814898 u2DelayCellTimex100 = 270/100 ps
6014 16:34:05.818422 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6015 16:34:05.825074 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 16:34:05.828381 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 16:34:05.831287 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 16:34:05.835027 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 16:34:05.838263 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 16:34:05.838748
6021 16:34:05.841555 CA PerBit enable=1, Macro0, CA PI delay=36
6022 16:34:05.841959
6023 16:34:05.844987 [CBTSetCACLKResult] CA Dly = 36
6024 16:34:05.848225 CS Dly: 1 (0~32)
6025 16:34:05.848606
6026 16:34:05.851524 ----->DramcWriteLeveling(PI) begin...
6027 16:34:05.851913 ==
6028 16:34:05.854774 Dram Type= 6, Freq= 0, CH_0, rank 0
6029 16:34:05.858271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6030 16:34:05.858658 ==
6031 16:34:05.861054 Write leveling (Byte 0): 32 => 0
6032 16:34:05.864967 Write leveling (Byte 1): 32 => 0
6033 16:34:05.868419 DramcWriteLeveling(PI) end<-----
6034 16:34:05.868892
6035 16:34:05.869198 ==
6036 16:34:05.871188 Dram Type= 6, Freq= 0, CH_0, rank 0
6037 16:34:05.874296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6038 16:34:05.874691 ==
6039 16:34:05.877903 [Gating] SW mode calibration
6040 16:34:05.884337 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6041 16:34:05.891314 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6042 16:34:05.893882 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6043 16:34:05.897595 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6044 16:34:05.904198 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6045 16:34:05.907076 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6046 16:34:05.910753 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6047 16:34:05.917677 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6048 16:34:05.921166 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6049 16:34:05.923858 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6050 16:34:05.930616 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6051 16:34:05.931229 Total UI for P1: 0, mck2ui 16
6052 16:34:05.937437 best dqsien dly found for B0: ( 0, 10, 16)
6053 16:34:05.937901 Total UI for P1: 0, mck2ui 16
6054 16:34:05.943899 best dqsien dly found for B1: ( 0, 10, 16)
6055 16:34:05.946914 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6056 16:34:05.950116 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6057 16:34:05.950541
6058 16:34:05.953771 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6059 16:34:05.956847 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6060 16:34:05.959963 [Gating] SW calibration Done
6061 16:34:05.960450 ==
6062 16:34:05.963225 Dram Type= 6, Freq= 0, CH_0, rank 0
6063 16:34:05.966659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6064 16:34:05.967047 ==
6065 16:34:05.970166 RX Vref Scan: 0
6066 16:34:05.970577
6067 16:34:05.973187 RX Vref 0 -> 0, step: 1
6068 16:34:05.973568
6069 16:34:05.973865 RX Delay -410 -> 252, step: 16
6070 16:34:05.980338 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6071 16:34:05.983169 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6072 16:34:05.986664 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6073 16:34:05.993205 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6074 16:34:05.996237 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6075 16:34:05.999918 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6076 16:34:06.002972 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6077 16:34:06.009651 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6078 16:34:06.013141 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6079 16:34:06.016050 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6080 16:34:06.019349 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6081 16:34:06.025810 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6082 16:34:06.029223 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6083 16:34:06.032726 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6084 16:34:06.036701 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6085 16:34:06.042669 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6086 16:34:06.043058 ==
6087 16:34:06.046298 Dram Type= 6, Freq= 0, CH_0, rank 0
6088 16:34:06.049360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6089 16:34:06.049756 ==
6090 16:34:06.050289 DQS Delay:
6091 16:34:06.052950 DQS0 = 51, DQS1 = 59
6092 16:34:06.053361 DQM Delay:
6093 16:34:06.056081 DQM0 = 12, DQM1 = 14
6094 16:34:06.056478 DQ Delay:
6095 16:34:06.059377 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6096 16:34:06.062946 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6097 16:34:06.065803 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6098 16:34:06.069044 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6099 16:34:06.069464
6100 16:34:06.069863
6101 16:34:06.070265 ==
6102 16:34:06.072300 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 16:34:06.075536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 16:34:06.075934 ==
6105 16:34:06.076325
6106 16:34:06.076688
6107 16:34:06.079123 TX Vref Scan disable
6108 16:34:06.082471 == TX Byte 0 ==
6109 16:34:06.085424 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6110 16:34:06.089360 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6111 16:34:06.092252 == TX Byte 1 ==
6112 16:34:06.095880 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6113 16:34:06.098967 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6114 16:34:06.099364 ==
6115 16:34:06.102295 Dram Type= 6, Freq= 0, CH_0, rank 0
6116 16:34:06.105676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6117 16:34:06.108838 ==
6118 16:34:06.109245
6119 16:34:06.109630
6120 16:34:06.109921 TX Vref Scan disable
6121 16:34:06.112395 == TX Byte 0 ==
6122 16:34:06.115874 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6123 16:34:06.119224 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6124 16:34:06.122306 == TX Byte 1 ==
6125 16:34:06.125461 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6126 16:34:06.128902 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6127 16:34:06.129294
6128 16:34:06.131939 [DATLAT]
6129 16:34:06.132342 Freq=400, CH0 RK0
6130 16:34:06.132647
6131 16:34:06.135498 DATLAT Default: 0xf
6132 16:34:06.135888 0, 0xFFFF, sum = 0
6133 16:34:06.138714 1, 0xFFFF, sum = 0
6134 16:34:06.139207 2, 0xFFFF, sum = 0
6135 16:34:06.142039 3, 0xFFFF, sum = 0
6136 16:34:06.142558 4, 0xFFFF, sum = 0
6137 16:34:06.145591 5, 0xFFFF, sum = 0
6138 16:34:06.145987 6, 0xFFFF, sum = 0
6139 16:34:06.148668 7, 0xFFFF, sum = 0
6140 16:34:06.149065 8, 0xFFFF, sum = 0
6141 16:34:06.152890 9, 0xFFFF, sum = 0
6142 16:34:06.153814 10, 0xFFFF, sum = 0
6143 16:34:06.155213 11, 0xFFFF, sum = 0
6144 16:34:06.155659 12, 0x0, sum = 1
6145 16:34:06.158788 13, 0x0, sum = 2
6146 16:34:06.159203 14, 0x0, sum = 3
6147 16:34:06.161906 15, 0x0, sum = 4
6148 16:34:06.162448 best_step = 13
6149 16:34:06.162762
6150 16:34:06.163047 ==
6151 16:34:06.165031 Dram Type= 6, Freq= 0, CH_0, rank 0
6152 16:34:06.171600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6153 16:34:06.171992 ==
6154 16:34:06.172296 RX Vref Scan: 1
6155 16:34:06.172580
6156 16:34:06.175170 RX Vref 0 -> 0, step: 1
6157 16:34:06.175665
6158 16:34:06.178615 RX Delay -359 -> 252, step: 8
6159 16:34:06.179002
6160 16:34:06.181715 Set Vref, RX VrefLevel [Byte0]: 52
6161 16:34:06.185367 [Byte1]: 46
6162 16:34:06.188516
6163 16:34:06.188919 Final RX Vref Byte 0 = 52 to rank0
6164 16:34:06.191532 Final RX Vref Byte 1 = 46 to rank0
6165 16:34:06.194948 Final RX Vref Byte 0 = 52 to rank1
6166 16:34:06.198246 Final RX Vref Byte 1 = 46 to rank1==
6167 16:34:06.201741 Dram Type= 6, Freq= 0, CH_0, rank 0
6168 16:34:06.208055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6169 16:34:06.208448 ==
6170 16:34:06.208801 DQS Delay:
6171 16:34:06.211620 DQS0 = 52, DQS1 = 68
6172 16:34:06.212005 DQM Delay:
6173 16:34:06.212307 DQM0 = 8, DQM1 = 17
6174 16:34:06.214746 DQ Delay:
6175 16:34:06.218236 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6176 16:34:06.218632 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6177 16:34:06.221599 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6178 16:34:06.224716 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6179 16:34:06.225191
6180 16:34:06.225497
6181 16:34:06.234617 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b9b, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6182 16:34:06.238434 CH0 RK0: MR19=C0C, MR18=9B9B
6183 16:34:06.244925 CH0_RK0: MR19=0xC0C, MR18=0x9B9B, DQSOSC=390, MR23=63, INC=388, DEC=258
6184 16:34:06.245397 ==
6185 16:34:06.248128 Dram Type= 6, Freq= 0, CH_0, rank 1
6186 16:34:06.251228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6187 16:34:06.251619 ==
6188 16:34:06.254595 [Gating] SW mode calibration
6189 16:34:06.261722 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6190 16:34:06.265360 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6191 16:34:06.271927 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6192 16:34:06.274533 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6193 16:34:06.277807 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6194 16:34:06.284580 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6195 16:34:06.287553 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6196 16:34:06.291153 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6197 16:34:06.298110 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6198 16:34:06.301142 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6199 16:34:06.304471 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6200 16:34:06.307655 Total UI for P1: 0, mck2ui 16
6201 16:34:06.310574 best dqsien dly found for B0: ( 0, 10, 16)
6202 16:34:06.314396 Total UI for P1: 0, mck2ui 16
6203 16:34:06.317612 best dqsien dly found for B1: ( 0, 10, 24)
6204 16:34:06.320727 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6205 16:34:06.327472 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6206 16:34:06.327857
6207 16:34:06.330541 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6208 16:34:06.334006 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6209 16:34:06.337065 [Gating] SW calibration Done
6210 16:34:06.337477 ==
6211 16:34:06.340808 Dram Type= 6, Freq= 0, CH_0, rank 1
6212 16:34:06.344301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6213 16:34:06.344705 ==
6214 16:34:06.347388 RX Vref Scan: 0
6215 16:34:06.347776
6216 16:34:06.348125 RX Vref 0 -> 0, step: 1
6217 16:34:06.348416
6218 16:34:06.350295 RX Delay -410 -> 252, step: 16
6219 16:34:06.356778 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6220 16:34:06.360241 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6221 16:34:06.363918 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6222 16:34:06.366808 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6223 16:34:06.370429 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6224 16:34:06.377101 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6225 16:34:06.380229 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6226 16:34:06.383896 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6227 16:34:06.390372 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6228 16:34:06.394352 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6229 16:34:06.397019 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6230 16:34:06.400662 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6231 16:34:06.407047 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6232 16:34:06.410075 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6233 16:34:06.413699 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6234 16:34:06.416787 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6235 16:34:06.419880 ==
6236 16:34:06.420274 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 16:34:06.426507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6238 16:34:06.426902 ==
6239 16:34:06.427207 DQS Delay:
6240 16:34:06.430204 DQS0 = 43, DQS1 = 59
6241 16:34:06.430632 DQM Delay:
6242 16:34:06.433669 DQM0 = 6, DQM1 = 15
6243 16:34:06.434054 DQ Delay:
6244 16:34:06.436428 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6245 16:34:06.440319 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6246 16:34:06.440709 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6247 16:34:06.443655 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6248 16:34:06.446725
6249 16:34:06.447111
6250 16:34:06.447411 ==
6251 16:34:06.450286 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 16:34:06.453600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6253 16:34:06.454068 ==
6254 16:34:06.454554
6255 16:34:06.454877
6256 16:34:06.456623 TX Vref Scan disable
6257 16:34:06.457188 == TX Byte 0 ==
6258 16:34:06.459857 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6259 16:34:06.466608 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6260 16:34:06.467031 == TX Byte 1 ==
6261 16:34:06.469615 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6262 16:34:06.476656 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6263 16:34:06.477162 ==
6264 16:34:06.479658 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 16:34:06.482727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6266 16:34:06.483190 ==
6267 16:34:06.483713
6268 16:34:06.484355
6269 16:34:06.486091 TX Vref Scan disable
6270 16:34:06.486496 == TX Byte 0 ==
6271 16:34:06.492716 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6272 16:34:06.496409 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6273 16:34:06.496866 == TX Byte 1 ==
6274 16:34:06.499980 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6275 16:34:06.506753 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6276 16:34:06.507280
6277 16:34:06.507679 [DATLAT]
6278 16:34:06.509513 Freq=400, CH0 RK1
6279 16:34:06.509901
6280 16:34:06.510200 DATLAT Default: 0xd
6281 16:34:06.512462 0, 0xFFFF, sum = 0
6282 16:34:06.512855 1, 0xFFFF, sum = 0
6283 16:34:06.515979 2, 0xFFFF, sum = 0
6284 16:34:06.516375 3, 0xFFFF, sum = 0
6285 16:34:06.518879 4, 0xFFFF, sum = 0
6286 16:34:06.519271 5, 0xFFFF, sum = 0
6287 16:34:06.522570 6, 0xFFFF, sum = 0
6288 16:34:06.522966 7, 0xFFFF, sum = 0
6289 16:34:06.525836 8, 0xFFFF, sum = 0
6290 16:34:06.526271 9, 0xFFFF, sum = 0
6291 16:34:06.528955 10, 0xFFFF, sum = 0
6292 16:34:06.532596 11, 0xFFFF, sum = 0
6293 16:34:06.533034 12, 0x0, sum = 1
6294 16:34:06.533342 13, 0x0, sum = 2
6295 16:34:06.535766 14, 0x0, sum = 3
6296 16:34:06.536185 15, 0x0, sum = 4
6297 16:34:06.539068 best_step = 13
6298 16:34:06.539451
6299 16:34:06.539748 ==
6300 16:34:06.542285 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 16:34:06.545824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6302 16:34:06.546241 ==
6303 16:34:06.549276 RX Vref Scan: 0
6304 16:34:06.549657
6305 16:34:06.549952 RX Vref 0 -> 0, step: 1
6306 16:34:06.550272
6307 16:34:06.551961 RX Delay -359 -> 252, step: 8
6308 16:34:06.560476 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6309 16:34:06.563936 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6310 16:34:06.567051 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6311 16:34:06.570293 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6312 16:34:06.576916 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6313 16:34:06.580708 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6314 16:34:06.584261 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6315 16:34:06.587183 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6316 16:34:06.594077 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6317 16:34:06.597092 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6318 16:34:06.600720 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6319 16:34:06.607130 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6320 16:34:06.610204 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6321 16:34:06.613770 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6322 16:34:06.616552 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6323 16:34:06.623596 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6324 16:34:06.623982 ==
6325 16:34:06.626827 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 16:34:06.630162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 16:34:06.630595 ==
6328 16:34:06.630900 DQS Delay:
6329 16:34:06.633581 DQS0 = 52, DQS1 = 64
6330 16:34:06.634063 DQM Delay:
6331 16:34:06.636890 DQM0 = 9, DQM1 = 13
6332 16:34:06.637276 DQ Delay:
6333 16:34:06.639815 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6334 16:34:06.643192 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6335 16:34:06.646450 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6336 16:34:06.650063 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6337 16:34:06.650476
6338 16:34:06.650777
6339 16:34:06.656661 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6340 16:34:06.660184 CH0 RK1: MR19=C0C, MR18=C1C1
6341 16:34:06.666868 CH0_RK1: MR19=0xC0C, MR18=0xC1C1, DQSOSC=385, MR23=63, INC=398, DEC=265
6342 16:34:06.669650 [RxdqsGatingPostProcess] freq 400
6343 16:34:06.676412 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6344 16:34:06.679723 Pre-setting of DQS Precalculation
6345 16:34:06.682889 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6346 16:34:06.683294 ==
6347 16:34:06.686627 Dram Type= 6, Freq= 0, CH_1, rank 0
6348 16:34:06.689847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6349 16:34:06.690296 ==
6350 16:34:06.696145 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6351 16:34:06.702911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6352 16:34:06.706382 [CA 0] Center 36 (8~64) winsize 57
6353 16:34:06.709858 [CA 1] Center 36 (8~64) winsize 57
6354 16:34:06.712756 [CA 2] Center 36 (8~64) winsize 57
6355 16:34:06.716461 [CA 3] Center 36 (8~64) winsize 57
6356 16:34:06.719426 [CA 4] Center 36 (8~64) winsize 57
6357 16:34:06.719989 [CA 5] Center 36 (8~64) winsize 57
6358 16:34:06.722922
6359 16:34:06.726034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6360 16:34:06.726658
6361 16:34:06.729667 [CATrainingPosCal] consider 1 rank data
6362 16:34:06.732707 u2DelayCellTimex100 = 270/100 ps
6363 16:34:06.736237 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 16:34:06.739362 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 16:34:06.742814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 16:34:06.745678 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 16:34:06.749374 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 16:34:06.752673 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 16:34:06.753170
6370 16:34:06.755617 CA PerBit enable=1, Macro0, CA PI delay=36
6371 16:34:06.756004
6372 16:34:06.759325 [CBTSetCACLKResult] CA Dly = 36
6373 16:34:06.762450 CS Dly: 1 (0~32)
6374 16:34:06.762835 ==
6375 16:34:06.765692 Dram Type= 6, Freq= 0, CH_1, rank 1
6376 16:34:06.769197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6377 16:34:06.769776 ==
6378 16:34:06.775477 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6379 16:34:06.781995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6380 16:34:06.785994 [CA 0] Center 36 (8~64) winsize 57
6381 16:34:06.788859 [CA 1] Center 36 (8~64) winsize 57
6382 16:34:06.789445 [CA 2] Center 36 (8~64) winsize 57
6383 16:34:06.792327 [CA 3] Center 36 (8~64) winsize 57
6384 16:34:06.795680 [CA 4] Center 36 (8~64) winsize 57
6385 16:34:06.798813 [CA 5] Center 36 (8~64) winsize 57
6386 16:34:06.799330
6387 16:34:06.802174 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6388 16:34:06.802597
6389 16:34:06.809091 [CATrainingPosCal] consider 2 rank data
6390 16:34:06.809541 u2DelayCellTimex100 = 270/100 ps
6391 16:34:06.815413 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6392 16:34:06.818931 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 16:34:06.822013 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 16:34:06.825834 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 16:34:06.828596 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 16:34:06.832141 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 16:34:06.832527
6398 16:34:06.835353 CA PerBit enable=1, Macro0, CA PI delay=36
6399 16:34:06.835835
6400 16:34:06.838686 [CBTSetCACLKResult] CA Dly = 36
6401 16:34:06.841739 CS Dly: 1 (0~32)
6402 16:34:06.842123
6403 16:34:06.845341 ----->DramcWriteLeveling(PI) begin...
6404 16:34:06.845732 ==
6405 16:34:06.848192 Dram Type= 6, Freq= 0, CH_1, rank 0
6406 16:34:06.851660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6407 16:34:06.852049 ==
6408 16:34:06.855104 Write leveling (Byte 0): 32 => 0
6409 16:34:06.858400 Write leveling (Byte 1): 32 => 0
6410 16:34:06.861781 DramcWriteLeveling(PI) end<-----
6411 16:34:06.862269
6412 16:34:06.862591 ==
6413 16:34:06.865114 Dram Type= 6, Freq= 0, CH_1, rank 0
6414 16:34:06.868526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6415 16:34:06.868917 ==
6416 16:34:06.871660 [Gating] SW mode calibration
6417 16:34:06.878350 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6418 16:34:06.885273 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6419 16:34:06.888270 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 16:34:06.891922 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 16:34:06.898373 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 16:34:06.901739 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6423 16:34:06.904961 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 16:34:06.911287 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 16:34:06.914998 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 16:34:06.918458 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6427 16:34:06.925244 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 16:34:06.925631 Total UI for P1: 0, mck2ui 16
6429 16:34:06.931696 best dqsien dly found for B0: ( 0, 10, 16)
6430 16:34:06.932212 Total UI for P1: 0, mck2ui 16
6431 16:34:06.934663 best dqsien dly found for B1: ( 0, 10, 16)
6432 16:34:06.942114 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6433 16:34:06.944864 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6434 16:34:06.945251
6435 16:34:06.947820 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6436 16:34:06.951624 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6437 16:34:06.954573 [Gating] SW calibration Done
6438 16:34:06.954958 ==
6439 16:34:06.958114 Dram Type= 6, Freq= 0, CH_1, rank 0
6440 16:34:06.961715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6441 16:34:06.962185 ==
6442 16:34:06.964956 RX Vref Scan: 0
6443 16:34:06.965428
6444 16:34:06.965731 RX Vref 0 -> 0, step: 1
6445 16:34:06.966032
6446 16:34:06.968190 RX Delay -410 -> 252, step: 16
6447 16:34:06.974692 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6448 16:34:06.978123 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6449 16:34:06.981478 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6450 16:34:06.985465 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6451 16:34:06.991056 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6452 16:34:06.994431 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6453 16:34:06.997738 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6454 16:34:07.000890 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6455 16:34:07.007719 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6456 16:34:07.011357 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6457 16:34:07.014490 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6458 16:34:07.017358 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6459 16:34:07.024037 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6460 16:34:07.028145 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6461 16:34:07.030737 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6462 16:34:07.037261 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6463 16:34:07.037726 ==
6464 16:34:07.040972 Dram Type= 6, Freq= 0, CH_1, rank 0
6465 16:34:07.043962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6466 16:34:07.044378 ==
6467 16:34:07.044680 DQS Delay:
6468 16:34:07.047504 DQS0 = 43, DQS1 = 59
6469 16:34:07.047905 DQM Delay:
6470 16:34:07.050455 DQM0 = 8, DQM1 = 15
6471 16:34:07.050856 DQ Delay:
6472 16:34:07.053988 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6473 16:34:07.057079 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =8
6474 16:34:07.060788 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6475 16:34:07.063725 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6476 16:34:07.064112
6477 16:34:07.064409
6478 16:34:07.064681 ==
6479 16:34:07.067239 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 16:34:07.070656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 16:34:07.071169 ==
6482 16:34:07.071554
6483 16:34:07.071862
6484 16:34:07.073835 TX Vref Scan disable
6485 16:34:07.074597 == TX Byte 0 ==
6486 16:34:07.080267 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6487 16:34:07.084221 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6488 16:34:07.084690 == TX Byte 1 ==
6489 16:34:07.090281 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6490 16:34:07.093760 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6491 16:34:07.094142 ==
6492 16:34:07.096571 Dram Type= 6, Freq= 0, CH_1, rank 0
6493 16:34:07.100029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6494 16:34:07.100436 ==
6495 16:34:07.100738
6496 16:34:07.103559
6497 16:34:07.103939 TX Vref Scan disable
6498 16:34:07.106674 == TX Byte 0 ==
6499 16:34:07.110106 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6500 16:34:07.113825 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6501 16:34:07.116756 == TX Byte 1 ==
6502 16:34:07.119842 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6503 16:34:07.123113 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6504 16:34:07.123865
6505 16:34:07.124273 [DATLAT]
6506 16:34:07.126440 Freq=400, CH1 RK0
6507 16:34:07.126822
6508 16:34:07.130070 DATLAT Default: 0xf
6509 16:34:07.130476 0, 0xFFFF, sum = 0
6510 16:34:07.133564 1, 0xFFFF, sum = 0
6511 16:34:07.133971 2, 0xFFFF, sum = 0
6512 16:34:07.136327 3, 0xFFFF, sum = 0
6513 16:34:07.136716 4, 0xFFFF, sum = 0
6514 16:34:07.139760 5, 0xFFFF, sum = 0
6515 16:34:07.140146 6, 0xFFFF, sum = 0
6516 16:34:07.143223 7, 0xFFFF, sum = 0
6517 16:34:07.143610 8, 0xFFFF, sum = 0
6518 16:34:07.146365 9, 0xFFFF, sum = 0
6519 16:34:07.146779 10, 0xFFFF, sum = 0
6520 16:34:07.149438 11, 0xFFFF, sum = 0
6521 16:34:07.149826 12, 0x0, sum = 1
6522 16:34:07.153060 13, 0x0, sum = 2
6523 16:34:07.153445 14, 0x0, sum = 3
6524 16:34:07.156323 15, 0x0, sum = 4
6525 16:34:07.156713 best_step = 13
6526 16:34:07.157006
6527 16:34:07.157278 ==
6528 16:34:07.160138 Dram Type= 6, Freq= 0, CH_1, rank 0
6529 16:34:07.166175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6530 16:34:07.166612 ==
6531 16:34:07.166913 RX Vref Scan: 1
6532 16:34:07.167188
6533 16:34:07.170080 RX Vref 0 -> 0, step: 1
6534 16:34:07.170638
6535 16:34:07.172675 RX Delay -359 -> 252, step: 8
6536 16:34:07.173163
6537 16:34:07.176150 Set Vref, RX VrefLevel [Byte0]: 52
6538 16:34:07.179084 [Byte1]: 49
6539 16:34:07.179471
6540 16:34:07.182981 Final RX Vref Byte 0 = 52 to rank0
6541 16:34:07.185966 Final RX Vref Byte 1 = 49 to rank0
6542 16:34:07.189488 Final RX Vref Byte 0 = 52 to rank1
6543 16:34:07.192423 Final RX Vref Byte 1 = 49 to rank1==
6544 16:34:07.196013 Dram Type= 6, Freq= 0, CH_1, rank 0
6545 16:34:07.199132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6546 16:34:07.202333 ==
6547 16:34:07.202722 DQS Delay:
6548 16:34:07.203023 DQS0 = 48, DQS1 = 68
6549 16:34:07.205950 DQM Delay:
6550 16:34:07.206373 DQM0 = 9, DQM1 = 20
6551 16:34:07.209633 DQ Delay:
6552 16:34:07.210021 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6553 16:34:07.212288 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6554 16:34:07.215703 DQ8 =0, DQ9 =12, DQ10 =24, DQ11 =12
6555 16:34:07.219364 DQ12 =28, DQ13 =32, DQ14 =28, DQ15 =28
6556 16:34:07.219750
6557 16:34:07.220047
6558 16:34:07.228798 [DQSOSCAuto] RK0, (LSB)MR18= 0xe1e1, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6559 16:34:07.232356 CH1 RK0: MR19=C0C, MR18=E1E1
6560 16:34:07.238980 CH1_RK0: MR19=0xC0C, MR18=0xE1E1, DQSOSC=382, MR23=63, INC=404, DEC=269
6561 16:34:07.239459 ==
6562 16:34:07.241856 Dram Type= 6, Freq= 0, CH_1, rank 1
6563 16:34:07.245251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6564 16:34:07.245672 ==
6565 16:34:07.248533 [Gating] SW mode calibration
6566 16:34:07.254946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6567 16:34:07.261905 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6568 16:34:07.265469 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6569 16:34:07.268397 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6570 16:34:07.274920 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6571 16:34:07.278403 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6572 16:34:07.281522 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6573 16:34:07.288770 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6574 16:34:07.291301 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6575 16:34:07.295158 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6576 16:34:07.298587 Total UI for P1: 0, mck2ui 16
6577 16:34:07.301346 best dqsien dly found for B0: ( 0, 10, 8)
6578 16:34:07.304757 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6579 16:34:07.308384 Total UI for P1: 0, mck2ui 16
6580 16:34:07.311254 best dqsien dly found for B1: ( 0, 10, 16)
6581 16:34:07.317870 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6582 16:34:07.321653 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6583 16:34:07.322120
6584 16:34:07.324870 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6585 16:34:07.328298 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6586 16:34:07.331727 [Gating] SW calibration Done
6587 16:34:07.332197 ==
6588 16:34:07.334836 Dram Type= 6, Freq= 0, CH_1, rank 1
6589 16:34:07.338444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6590 16:34:07.339047 ==
6591 16:34:07.341576 RX Vref Scan: 0
6592 16:34:07.341957
6593 16:34:07.342457 RX Vref 0 -> 0, step: 1
6594 16:34:07.342822
6595 16:34:07.344678 RX Delay -410 -> 252, step: 16
6596 16:34:07.351200 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6597 16:34:07.354343 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6598 16:34:07.357913 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6599 16:34:07.360918 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6600 16:34:07.367723 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6601 16:34:07.371413 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6602 16:34:07.374251 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6603 16:34:07.377791 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6604 16:34:07.384282 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6605 16:34:07.387777 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6606 16:34:07.390670 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6607 16:34:07.394013 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6608 16:34:07.400283 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6609 16:34:07.403908 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6610 16:34:07.407110 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6611 16:34:07.414058 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6612 16:34:07.414477 ==
6613 16:34:07.416963 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 16:34:07.420591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6615 16:34:07.420993 ==
6616 16:34:07.421316 DQS Delay:
6617 16:34:07.423611 DQS0 = 43, DQS1 = 59
6618 16:34:07.423992 DQM Delay:
6619 16:34:07.427257 DQM0 = 10, DQM1 = 17
6620 16:34:07.427639 DQ Delay:
6621 16:34:07.430238 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6622 16:34:07.433446 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6623 16:34:07.436608 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6624 16:34:07.440155 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6625 16:34:07.440534
6626 16:34:07.440827
6627 16:34:07.441100 ==
6628 16:34:07.443686 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 16:34:07.446564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6630 16:34:07.446949 ==
6631 16:34:07.447245
6632 16:34:07.447516
6633 16:34:07.450045 TX Vref Scan disable
6634 16:34:07.450512 == TX Byte 0 ==
6635 16:34:07.456802 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6636 16:34:07.460266 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6637 16:34:07.460742 == TX Byte 1 ==
6638 16:34:07.466638 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6639 16:34:07.469701 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6640 16:34:07.470086 ==
6641 16:34:07.473238 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 16:34:07.476624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6643 16:34:07.477010 ==
6644 16:34:07.477308
6645 16:34:07.477714
6646 16:34:07.479706 TX Vref Scan disable
6647 16:34:07.480013 == TX Byte 0 ==
6648 16:34:07.486870 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6649 16:34:07.489805 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6650 16:34:07.490190 == TX Byte 1 ==
6651 16:34:07.496744 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6652 16:34:07.499661 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6653 16:34:07.500046
6654 16:34:07.500345 [DATLAT]
6655 16:34:07.503364 Freq=400, CH1 RK1
6656 16:34:07.503746
6657 16:34:07.504040 DATLAT Default: 0xd
6658 16:34:07.506769 0, 0xFFFF, sum = 0
6659 16:34:07.507162 1, 0xFFFF, sum = 0
6660 16:34:07.509482 2, 0xFFFF, sum = 0
6661 16:34:07.509871 3, 0xFFFF, sum = 0
6662 16:34:07.512960 4, 0xFFFF, sum = 0
6663 16:34:07.513488 5, 0xFFFF, sum = 0
6664 16:34:07.516434 6, 0xFFFF, sum = 0
6665 16:34:07.519329 7, 0xFFFF, sum = 0
6666 16:34:07.519782 8, 0xFFFF, sum = 0
6667 16:34:07.522959 9, 0xFFFF, sum = 0
6668 16:34:07.523350 10, 0xFFFF, sum = 0
6669 16:34:07.526028 11, 0xFFFF, sum = 0
6670 16:34:07.526447 12, 0x0, sum = 1
6671 16:34:07.529627 13, 0x0, sum = 2
6672 16:34:07.530092 14, 0x0, sum = 3
6673 16:34:07.533590 15, 0x0, sum = 4
6674 16:34:07.534058 best_step = 13
6675 16:34:07.534427
6676 16:34:07.534714 ==
6677 16:34:07.536094 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 16:34:07.539638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6679 16:34:07.540406 ==
6680 16:34:07.542779 RX Vref Scan: 0
6681 16:34:07.543191
6682 16:34:07.545739 RX Vref 0 -> 0, step: 1
6683 16:34:07.546170
6684 16:34:07.546526 RX Delay -359 -> 252, step: 8
6685 16:34:07.554703 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6686 16:34:07.558135 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6687 16:34:07.561331 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6688 16:34:07.564760 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6689 16:34:07.571302 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6690 16:34:07.574601 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6691 16:34:07.577886 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6692 16:34:07.581217 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6693 16:34:07.587619 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6694 16:34:07.591422 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6695 16:34:07.594947 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6696 16:34:07.601200 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6697 16:34:07.604826 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6698 16:34:07.607691 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6699 16:34:07.611394 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6700 16:34:07.617726 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6701 16:34:07.618112 ==
6702 16:34:07.621285 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 16:34:07.624352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 16:34:07.624835 ==
6705 16:34:07.625136 DQS Delay:
6706 16:34:07.627995 DQS0 = 48, DQS1 = 64
6707 16:34:07.628378 DQM Delay:
6708 16:34:07.630870 DQM0 = 9, DQM1 = 15
6709 16:34:07.631254 DQ Delay:
6710 16:34:07.634304 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6711 16:34:07.637246 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6712 16:34:07.640867 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6713 16:34:07.643872 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6714 16:34:07.644254
6715 16:34:07.644550
6716 16:34:07.650992 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6717 16:34:07.654174 CH1 RK1: MR19=C0C, MR18=A8A8
6718 16:34:07.660956 CH1_RK1: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6719 16:34:07.664188 [RxdqsGatingPostProcess] freq 400
6720 16:34:07.670734 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6721 16:34:07.674465 Pre-setting of DQS Precalculation
6722 16:34:07.677008 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6723 16:34:07.683552 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6724 16:34:07.690550 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6725 16:34:07.691019
6726 16:34:07.693823
6727 16:34:07.694407 [Calibration Summary] 800 Mbps
6728 16:34:07.696874 CH 0, Rank 0
6729 16:34:07.697258 SW Impedance : PASS
6730 16:34:07.700227 DUTY Scan : NO K
6731 16:34:07.703672 ZQ Calibration : PASS
6732 16:34:07.704056 Jitter Meter : NO K
6733 16:34:07.706724 CBT Training : PASS
6734 16:34:07.710128 Write leveling : PASS
6735 16:34:07.710544 RX DQS gating : PASS
6736 16:34:07.713648 RX DQ/DQS(RDDQC) : PASS
6737 16:34:07.716502 TX DQ/DQS : PASS
6738 16:34:07.716889 RX DATLAT : PASS
6739 16:34:07.720184 RX DQ/DQS(Engine): PASS
6740 16:34:07.723091 TX OE : NO K
6741 16:34:07.723472 All Pass.
6742 16:34:07.723791
6743 16:34:07.724138 CH 0, Rank 1
6744 16:34:07.726523 SW Impedance : PASS
6745 16:34:07.729885 DUTY Scan : NO K
6746 16:34:07.730354 ZQ Calibration : PASS
6747 16:34:07.733180 Jitter Meter : NO K
6748 16:34:07.736767 CBT Training : PASS
6749 16:34:07.737379 Write leveling : NO K
6750 16:34:07.739868 RX DQS gating : PASS
6751 16:34:07.740253 RX DQ/DQS(RDDQC) : PASS
6752 16:34:07.743005 TX DQ/DQS : PASS
6753 16:34:07.746534 RX DATLAT : PASS
6754 16:34:07.746928 RX DQ/DQS(Engine): PASS
6755 16:34:07.750076 TX OE : NO K
6756 16:34:07.750524 All Pass.
6757 16:34:07.750830
6758 16:34:07.753088 CH 1, Rank 0
6759 16:34:07.753504 SW Impedance : PASS
6760 16:34:07.756742 DUTY Scan : NO K
6761 16:34:07.760432 ZQ Calibration : PASS
6762 16:34:07.760823 Jitter Meter : NO K
6763 16:34:07.763109 CBT Training : PASS
6764 16:34:07.766517 Write leveling : PASS
6765 16:34:07.766916 RX DQS gating : PASS
6766 16:34:07.769660 RX DQ/DQS(RDDQC) : PASS
6767 16:34:07.773032 TX DQ/DQS : PASS
6768 16:34:07.773424 RX DATLAT : PASS
6769 16:34:07.776217 RX DQ/DQS(Engine): PASS
6770 16:34:07.779668 TX OE : NO K
6771 16:34:07.780058 All Pass.
6772 16:34:07.780358
6773 16:34:07.780637 CH 1, Rank 1
6774 16:34:07.782942 SW Impedance : PASS
6775 16:34:07.786281 DUTY Scan : NO K
6776 16:34:07.786668 ZQ Calibration : PASS
6777 16:34:07.789695 Jitter Meter : NO K
6778 16:34:07.792544 CBT Training : PASS
6779 16:34:07.792931 Write leveling : NO K
6780 16:34:07.796228 RX DQS gating : PASS
6781 16:34:07.799561 RX DQ/DQS(RDDQC) : PASS
6782 16:34:07.799948 TX DQ/DQS : PASS
6783 16:34:07.802620 RX DATLAT : PASS
6784 16:34:07.803009 RX DQ/DQS(Engine): PASS
6785 16:34:07.806171 TX OE : NO K
6786 16:34:07.806607 All Pass.
6787 16:34:07.806908
6788 16:34:07.809613 DramC Write-DBI off
6789 16:34:07.812577 PER_BANK_REFRESH: Hybrid Mode
6790 16:34:07.812966 TX_TRACKING: ON
6791 16:34:07.822510 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6792 16:34:07.825680 [FAST_K] Save calibration result to emmc
6793 16:34:07.829391 dramc_set_vcore_voltage set vcore to 725000
6794 16:34:07.833044 Read voltage for 1600, 0
6795 16:34:07.833433 Vio18 = 0
6796 16:34:07.835690 Vcore = 725000
6797 16:34:07.836076 Vdram = 0
6798 16:34:07.836374 Vddq = 0
6799 16:34:07.836649 Vmddr = 0
6800 16:34:07.842340 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6801 16:34:07.848788 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6802 16:34:07.849063 MEM_TYPE=3, freq_sel=13
6803 16:34:07.852492 sv_algorithm_assistance_LP4_3733
6804 16:34:07.855331 ============ PULL DRAM RESETB DOWN ============
6805 16:34:07.862098 ========== PULL DRAM RESETB DOWN end =========
6806 16:34:07.865887 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6807 16:34:07.868737 ===================================
6808 16:34:07.872006 LPDDR4 DRAM CONFIGURATION
6809 16:34:07.875549 ===================================
6810 16:34:07.875849 EX_ROW_EN[0] = 0x0
6811 16:34:07.878909 EX_ROW_EN[1] = 0x0
6812 16:34:07.879206 LP4Y_EN = 0x0
6813 16:34:07.882539 WORK_FSP = 0x1
6814 16:34:07.882841 WL = 0x5
6815 16:34:07.885671 RL = 0x5
6816 16:34:07.886060 BL = 0x2
6817 16:34:07.888805 RPST = 0x0
6818 16:34:07.892096 RD_PRE = 0x0
6819 16:34:07.892396 WR_PRE = 0x1
6820 16:34:07.895274 WR_PST = 0x1
6821 16:34:07.895669 DBI_WR = 0x0
6822 16:34:07.898377 DBI_RD = 0x0
6823 16:34:07.898680 OTF = 0x1
6824 16:34:07.901825 ===================================
6825 16:34:07.905492 ===================================
6826 16:34:07.908620 ANA top config
6827 16:34:07.911824 ===================================
6828 16:34:07.912130 DLL_ASYNC_EN = 0
6829 16:34:07.915174 ALL_SLAVE_EN = 0
6830 16:34:07.918183 NEW_RANK_MODE = 1
6831 16:34:07.921686 DLL_IDLE_MODE = 1
6832 16:34:07.921992 LP45_APHY_COMB_EN = 1
6833 16:34:07.925346 TX_ODT_DIS = 0
6834 16:34:07.928376 NEW_8X_MODE = 1
6835 16:34:07.932088 ===================================
6836 16:34:07.934779 ===================================
6837 16:34:07.938381 data_rate = 3200
6838 16:34:07.941725 CKR = 1
6839 16:34:07.944660 DQ_P2S_RATIO = 8
6840 16:34:07.948211 ===================================
6841 16:34:07.948719 CA_P2S_RATIO = 8
6842 16:34:07.951818 DQ_CA_OPEN = 0
6843 16:34:07.954724 DQ_SEMI_OPEN = 0
6844 16:34:07.958740 CA_SEMI_OPEN = 0
6845 16:34:07.961834 CA_FULL_RATE = 0
6846 16:34:07.964651 DQ_CKDIV4_EN = 0
6847 16:34:07.965039 CA_CKDIV4_EN = 0
6848 16:34:07.968641 CA_PREDIV_EN = 0
6849 16:34:07.971239 PH8_DLY = 12
6850 16:34:07.974963 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6851 16:34:07.977976 DQ_AAMCK_DIV = 4
6852 16:34:07.981203 CA_AAMCK_DIV = 4
6853 16:34:07.981590 CA_ADMCK_DIV = 4
6854 16:34:07.984555 DQ_TRACK_CA_EN = 0
6855 16:34:07.988244 CA_PICK = 1600
6856 16:34:07.990901 CA_MCKIO = 1600
6857 16:34:07.994907 MCKIO_SEMI = 0
6858 16:34:07.997643 PLL_FREQ = 3068
6859 16:34:08.001070 DQ_UI_PI_RATIO = 32
6860 16:34:08.004642 CA_UI_PI_RATIO = 0
6861 16:34:08.008555 ===================================
6862 16:34:08.011310 ===================================
6863 16:34:08.011698 memory_type:LPDDR4
6864 16:34:08.014282 GP_NUM : 10
6865 16:34:08.017747 SRAM_EN : 1
6866 16:34:08.018134 MD32_EN : 0
6867 16:34:08.021320 ===================================
6868 16:34:08.024101 [ANA_INIT] >>>>>>>>>>>>>>
6869 16:34:08.027490 <<<<<< [CONFIGURE PHASE]: ANA_TX
6870 16:34:08.031057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6871 16:34:08.034491 ===================================
6872 16:34:08.037479 data_rate = 3200,PCW = 0X7600
6873 16:34:08.040777 ===================================
6874 16:34:08.043943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6875 16:34:08.047390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6876 16:34:08.053905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6877 16:34:08.057430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6878 16:34:08.060421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6879 16:34:08.063825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6880 16:34:08.066876 [ANA_INIT] flow start
6881 16:34:08.070506 [ANA_INIT] PLL >>>>>>>>
6882 16:34:08.070891 [ANA_INIT] PLL <<<<<<<<
6883 16:34:08.073595 [ANA_INIT] MIDPI >>>>>>>>
6884 16:34:08.077273 [ANA_INIT] MIDPI <<<<<<<<
6885 16:34:08.080207 [ANA_INIT] DLL >>>>>>>>
6886 16:34:08.080594 [ANA_INIT] DLL <<<<<<<<
6887 16:34:08.083711 [ANA_INIT] flow end
6888 16:34:08.087056 ============ LP4 DIFF to SE enter ============
6889 16:34:08.090483 ============ LP4 DIFF to SE exit ============
6890 16:34:08.093514 [ANA_INIT] <<<<<<<<<<<<<
6891 16:34:08.096718 [Flow] Enable top DCM control >>>>>
6892 16:34:08.100247 [Flow] Enable top DCM control <<<<<
6893 16:34:08.103670 Enable DLL master slave shuffle
6894 16:34:08.110320 ==============================================================
6895 16:34:08.110805 Gating Mode config
6896 16:34:08.116404 ==============================================================
6897 16:34:08.116794 Config description:
6898 16:34:08.126522 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6899 16:34:08.132722 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6900 16:34:08.139720 SELPH_MODE 0: By rank 1: By Phase
6901 16:34:08.143529 ==============================================================
6902 16:34:08.146167 GAT_TRACK_EN = 1
6903 16:34:08.149922 RX_GATING_MODE = 2
6904 16:34:08.152639 RX_GATING_TRACK_MODE = 2
6905 16:34:08.155983 SELPH_MODE = 1
6906 16:34:08.159259 PICG_EARLY_EN = 1
6907 16:34:08.162959 VALID_LAT_VALUE = 1
6908 16:34:08.169008 ==============================================================
6909 16:34:08.172539 Enter into Gating configuration >>>>
6910 16:34:08.175714 Exit from Gating configuration <<<<
6911 16:34:08.178993 Enter into DVFS_PRE_config >>>>>
6912 16:34:08.189289 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6913 16:34:08.192241 Exit from DVFS_PRE_config <<<<<
6914 16:34:08.195876 Enter into PICG configuration >>>>
6915 16:34:08.199271 Exit from PICG configuration <<<<
6916 16:34:08.202598 [RX_INPUT] configuration >>>>>
6917 16:34:08.202987 [RX_INPUT] configuration <<<<<
6918 16:34:08.209177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6919 16:34:08.215524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6920 16:34:08.222079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6921 16:34:08.225681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6922 16:34:08.232247 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6923 16:34:08.238788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6924 16:34:08.242161 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6925 16:34:08.245257 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6926 16:34:08.251925 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6927 16:34:08.255158 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6928 16:34:08.258658 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6929 16:34:08.265332 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6930 16:34:08.268540 ===================================
6931 16:34:08.268932 LPDDR4 DRAM CONFIGURATION
6932 16:34:08.272229 ===================================
6933 16:34:08.275466 EX_ROW_EN[0] = 0x0
6934 16:34:08.278928 EX_ROW_EN[1] = 0x0
6935 16:34:08.279315 LP4Y_EN = 0x0
6936 16:34:08.281785 WORK_FSP = 0x1
6937 16:34:08.282169 WL = 0x5
6938 16:34:08.285687 RL = 0x5
6939 16:34:08.286156 BL = 0x2
6940 16:34:08.288474 RPST = 0x0
6941 16:34:08.288945 RD_PRE = 0x0
6942 16:34:08.291926 WR_PRE = 0x1
6943 16:34:08.292417 WR_PST = 0x1
6944 16:34:08.294900 DBI_WR = 0x0
6945 16:34:08.295285 DBI_RD = 0x0
6946 16:34:08.298568 OTF = 0x1
6947 16:34:08.301600 ===================================
6948 16:34:08.305028 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6949 16:34:08.308497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6950 16:34:08.314802 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6951 16:34:08.318419 ===================================
6952 16:34:08.318805 LPDDR4 DRAM CONFIGURATION
6953 16:34:08.321770 ===================================
6954 16:34:08.325156 EX_ROW_EN[0] = 0x10
6955 16:34:08.328423 EX_ROW_EN[1] = 0x0
6956 16:34:08.328893 LP4Y_EN = 0x0
6957 16:34:08.331582 WORK_FSP = 0x1
6958 16:34:08.331967 WL = 0x5
6959 16:34:08.335012 RL = 0x5
6960 16:34:08.335533 BL = 0x2
6961 16:34:08.337764 RPST = 0x0
6962 16:34:08.338148 RD_PRE = 0x0
6963 16:34:08.341986 WR_PRE = 0x1
6964 16:34:08.342524 WR_PST = 0x1
6965 16:34:08.345046 DBI_WR = 0x0
6966 16:34:08.345517 DBI_RD = 0x0
6967 16:34:08.347973 OTF = 0x1
6968 16:34:08.351561 ===================================
6969 16:34:08.357706 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6970 16:34:08.358241 ==
6971 16:34:08.361133 Dram Type= 6, Freq= 0, CH_0, rank 0
6972 16:34:08.364963 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6973 16:34:08.365355 ==
6974 16:34:08.368290 [Duty_Offset_Calibration]
6975 16:34:08.368761 B0:0 B1:2 CA:1
6976 16:34:08.369063
6977 16:34:08.371457 [DutyScan_Calibration_Flow] k_type=0
6978 16:34:08.381797
6979 16:34:08.382298 ==CLK 0==
6980 16:34:08.385582 Final CLK duty delay cell = 0
6981 16:34:08.388279 [0] MAX Duty = 5156%(X100), DQS PI = 20
6982 16:34:08.392020 [0] MIN Duty = 4938%(X100), DQS PI = 52
6983 16:34:08.392663 [0] AVG Duty = 5047%(X100)
6984 16:34:08.395075
6985 16:34:08.398058 CH0 CLK Duty spec in!! Max-Min= 218%
6986 16:34:08.401576 [DutyScan_Calibration_Flow] ====Done====
6987 16:34:08.401964
6988 16:34:08.404753 [DutyScan_Calibration_Flow] k_type=1
6989 16:34:08.421944
6990 16:34:08.422484 ==DQS 0 ==
6991 16:34:08.425006 Final DQS duty delay cell = 0
6992 16:34:08.428006 [0] MAX Duty = 5125%(X100), DQS PI = 30
6993 16:34:08.431530 [0] MIN Duty = 5000%(X100), DQS PI = 8
6994 16:34:08.434994 [0] AVG Duty = 5062%(X100)
6995 16:34:08.435386
6996 16:34:08.435706 ==DQS 1 ==
6997 16:34:08.438155 Final DQS duty delay cell = 0
6998 16:34:08.441568 [0] MAX Duty = 5031%(X100), DQS PI = 6
6999 16:34:08.445313 [0] MIN Duty = 4876%(X100), DQS PI = 16
7000 16:34:08.445805 [0] AVG Duty = 4953%(X100)
7001 16:34:08.448336
7002 16:34:08.451603 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7003 16:34:08.452002
7004 16:34:08.454943 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7005 16:34:08.457895 [DutyScan_Calibration_Flow] ====Done====
7006 16:34:08.458327
7007 16:34:08.461382 [DutyScan_Calibration_Flow] k_type=3
7008 16:34:08.479051
7009 16:34:08.479565 ==DQM 0 ==
7010 16:34:08.482119 Final DQM duty delay cell = 0
7011 16:34:08.485545 [0] MAX Duty = 5187%(X100), DQS PI = 24
7012 16:34:08.488603 [0] MIN Duty = 4907%(X100), DQS PI = 42
7013 16:34:08.492358 [0] AVG Duty = 5047%(X100)
7014 16:34:08.492742
7015 16:34:08.493041 ==DQM 1 ==
7016 16:34:08.495172 Final DQM duty delay cell = 0
7017 16:34:08.498303 [0] MAX Duty = 5031%(X100), DQS PI = 50
7018 16:34:08.501641 [0] MIN Duty = 4782%(X100), DQS PI = 12
7019 16:34:08.505480 [0] AVG Duty = 4906%(X100)
7020 16:34:08.505866
7021 16:34:08.508447 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7022 16:34:08.508834
7023 16:34:08.512348 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7024 16:34:08.515075 [DutyScan_Calibration_Flow] ====Done====
7025 16:34:08.515580
7026 16:34:08.518104 [DutyScan_Calibration_Flow] k_type=2
7027 16:34:08.534979
7028 16:34:08.535365 ==DQ 0 ==
7029 16:34:08.538771 Final DQ duty delay cell = 0
7030 16:34:08.541706 [0] MAX Duty = 5218%(X100), DQS PI = 18
7031 16:34:08.545134 [0] MIN Duty = 4938%(X100), DQS PI = 56
7032 16:34:08.545603 [0] AVG Duty = 5078%(X100)
7033 16:34:08.548221
7034 16:34:08.548607 ==DQ 1 ==
7035 16:34:08.551725 Final DQ duty delay cell = -4
7036 16:34:08.555091 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7037 16:34:08.558071 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7038 16:34:08.561557 [-4] AVG Duty = 4953%(X100)
7039 16:34:08.561938
7040 16:34:08.564678 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7041 16:34:08.565060
7042 16:34:08.568069 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7043 16:34:08.571820 [DutyScan_Calibration_Flow] ====Done====
7044 16:34:08.572206 ==
7045 16:34:08.574767 Dram Type= 6, Freq= 0, CH_1, rank 0
7046 16:34:08.577985 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7047 16:34:08.578517 ==
7048 16:34:08.581641 [Duty_Offset_Calibration]
7049 16:34:08.582132 B0:0 B1:4 CA:-5
7050 16:34:08.582480
7051 16:34:08.584838 [DutyScan_Calibration_Flow] k_type=0
7052 16:34:08.595851
7053 16:34:08.596374 ==CLK 0==
7054 16:34:08.598906 Final CLK duty delay cell = 0
7055 16:34:08.602198 [0] MAX Duty = 5156%(X100), DQS PI = 20
7056 16:34:08.605631 [0] MIN Duty = 4906%(X100), DQS PI = 50
7057 16:34:08.606023 [0] AVG Duty = 5031%(X100)
7058 16:34:08.608752
7059 16:34:08.612380 CH1 CLK Duty spec in!! Max-Min= 250%
7060 16:34:08.615219 [DutyScan_Calibration_Flow] ====Done====
7061 16:34:08.615608
7062 16:34:08.618743 [DutyScan_Calibration_Flow] k_type=1
7063 16:34:08.634471
7064 16:34:08.634969 ==DQS 0 ==
7065 16:34:08.638024 Final DQS duty delay cell = 0
7066 16:34:08.641437 [0] MAX Duty = 5187%(X100), DQS PI = 20
7067 16:34:08.644838 [0] MIN Duty = 4876%(X100), DQS PI = 42
7068 16:34:08.647739 [0] AVG Duty = 5031%(X100)
7069 16:34:08.648121
7070 16:34:08.648420 ==DQS 1 ==
7071 16:34:08.651395 Final DQS duty delay cell = -4
7072 16:34:08.654526 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7073 16:34:08.657681 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7074 16:34:08.660758 [-4] AVG Duty = 4922%(X100)
7075 16:34:08.661142
7076 16:34:08.664165 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7077 16:34:08.664549
7078 16:34:08.668142 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7079 16:34:08.671052 [DutyScan_Calibration_Flow] ====Done====
7080 16:34:08.671563
7081 16:34:08.674006 [DutyScan_Calibration_Flow] k_type=3
7082 16:34:08.690253
7083 16:34:08.690640 ==DQM 0 ==
7084 16:34:08.693214 Final DQM duty delay cell = -4
7085 16:34:08.696824 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7086 16:34:08.699839 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7087 16:34:08.703325 [-4] AVG Duty = 4922%(X100)
7088 16:34:08.703707
7089 16:34:08.704003 ==DQM 1 ==
7090 16:34:08.706651 Final DQM duty delay cell = -4
7091 16:34:08.710181 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7092 16:34:08.713330 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7093 16:34:08.716686 [-4] AVG Duty = 4984%(X100)
7094 16:34:08.717087
7095 16:34:08.719995 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7096 16:34:08.720396
7097 16:34:08.722949 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7098 16:34:08.726765 [DutyScan_Calibration_Flow] ====Done====
7099 16:34:08.727167
7100 16:34:08.729974 [DutyScan_Calibration_Flow] k_type=2
7101 16:34:08.747921
7102 16:34:08.748466 ==DQ 0 ==
7103 16:34:08.750808 Final DQ duty delay cell = 0
7104 16:34:08.754172 [0] MAX Duty = 5093%(X100), DQS PI = 20
7105 16:34:08.758085 [0] MIN Duty = 4969%(X100), DQS PI = 44
7106 16:34:08.758617 [0] AVG Duty = 5031%(X100)
7107 16:34:08.761246
7108 16:34:08.761743 ==DQ 1 ==
7109 16:34:08.764306 Final DQ duty delay cell = 0
7110 16:34:08.767417 [0] MAX Duty = 5031%(X100), DQS PI = 4
7111 16:34:08.770911 [0] MIN Duty = 4876%(X100), DQS PI = 26
7112 16:34:08.771314 [0] AVG Duty = 4953%(X100)
7113 16:34:08.771727
7114 16:34:08.773986 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7115 16:34:08.777456
7116 16:34:08.780824 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7117 16:34:08.784468 [DutyScan_Calibration_Flow] ====Done====
7118 16:34:08.787309 nWR fixed to 30
7119 16:34:08.787714 [ModeRegInit_LP4] CH0 RK0
7120 16:34:08.790522 [ModeRegInit_LP4] CH0 RK1
7121 16:34:08.794011 [ModeRegInit_LP4] CH1 RK0
7122 16:34:08.794536 [ModeRegInit_LP4] CH1 RK1
7123 16:34:08.797669 match AC timing 4
7124 16:34:08.800682 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7125 16:34:08.804147 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7126 16:34:08.810545 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7127 16:34:08.814184 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7128 16:34:08.820476 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7129 16:34:08.820753 [MiockJmeterHQA]
7130 16:34:08.820981
7131 16:34:08.824047 [DramcMiockJmeter] u1RxGatingPI = 0
7132 16:34:08.827253 0 : 4366, 4139
7133 16:34:08.827419 4 : 4363, 4137
7134 16:34:08.827552 8 : 4255, 4026
7135 16:34:08.830644 12 : 4257, 4029
7136 16:34:08.830785 16 : 4258, 4029
7137 16:34:08.833827 20 : 4255, 4027
7138 16:34:08.833968 24 : 4252, 4027
7139 16:34:08.837340 28 : 4255, 4027
7140 16:34:08.837481 32 : 4254, 4026
7141 16:34:08.840475 36 : 4368, 4139
7142 16:34:08.840615 40 : 4255, 4027
7143 16:34:08.840726 44 : 4255, 4027
7144 16:34:08.844292 48 : 4255, 4027
7145 16:34:08.844500 52 : 4366, 4137
7146 16:34:08.847228 56 : 4365, 4137
7147 16:34:08.847448 60 : 4365, 4138
7148 16:34:08.850572 64 : 4255, 4027
7149 16:34:08.850743 68 : 4252, 4027
7150 16:34:08.853502 72 : 4255, 4027
7151 16:34:08.853643 76 : 4255, 4029
7152 16:34:08.853751 80 : 4252, 4027
7153 16:34:08.856946 84 : 4257, 4029
7154 16:34:08.857087 88 : 4365, 4139
7155 16:34:08.860585 92 : 4258, 4030
7156 16:34:08.860762 96 : 4260, 4032
7157 16:34:08.863597 100 : 4253, 1897
7158 16:34:08.863760 104 : 4255, 0
7159 16:34:08.863886 108 : 4255, 0
7160 16:34:08.867225 112 : 4252, 0
7161 16:34:08.867411 116 : 4250, 0
7162 16:34:08.870244 120 : 4250, 0
7163 16:34:08.870431 124 : 4253, 0
7164 16:34:08.870579 128 : 4363, 0
7165 16:34:08.873595 132 : 4360, 0
7166 16:34:08.873817 136 : 4250, 0
7167 16:34:08.876964 140 : 4250, 0
7168 16:34:08.877241 144 : 4360, 0
7169 16:34:08.877462 148 : 4249, 0
7170 16:34:08.880032 152 : 4250, 0
7171 16:34:08.880309 156 : 4360, 0
7172 16:34:08.880528 160 : 4361, 0
7173 16:34:08.883915 164 : 4250, 0
7174 16:34:08.884279 168 : 4250, 0
7175 16:34:08.886768 172 : 4250, 0
7176 16:34:08.887155 176 : 4250, 0
7177 16:34:08.887478 180 : 4360, 0
7178 16:34:08.890272 184 : 4250, 0
7179 16:34:08.890664 188 : 4251, 0
7180 16:34:08.893787 192 : 4255, 0
7181 16:34:08.894205 196 : 4250, 0
7182 16:34:08.894574 200 : 4364, 0
7183 16:34:08.897173 204 : 4250, 0
7184 16:34:08.897567 208 : 4250, 0
7185 16:34:08.900029 212 : 4255, 0
7186 16:34:08.900617 216 : 4255, 0
7187 16:34:08.900953 220 : 4250, 612
7188 16:34:08.903833 224 : 4250, 4016
7189 16:34:08.904223 228 : 4250, 4027
7190 16:34:08.906858 232 : 4251, 4027
7191 16:34:08.907248 236 : 4361, 4137
7192 16:34:08.910330 240 : 4251, 4027
7193 16:34:08.910853 244 : 4250, 4027
7194 16:34:08.913588 248 : 4361, 4137
7195 16:34:08.913976 252 : 4250, 4027
7196 16:34:08.917096 256 : 4250, 4027
7197 16:34:08.917486 260 : 4249, 4027
7198 16:34:08.919983 264 : 4250, 4026
7199 16:34:08.920517 268 : 4250, 4027
7200 16:34:08.920945 272 : 4361, 4137
7201 16:34:08.923575 276 : 4250, 4027
7202 16:34:08.923966 280 : 4252, 4030
7203 16:34:08.927179 284 : 4361, 4137
7204 16:34:08.927635 288 : 4361, 4138
7205 16:34:08.930168 292 : 4247, 4025
7206 16:34:08.930604 296 : 4252, 4030
7207 16:34:08.933695 300 : 4360, 4137
7208 16:34:08.934081 304 : 4250, 4027
7209 16:34:08.937090 308 : 4250, 4027
7210 16:34:08.937478 312 : 4254, 4032
7211 16:34:08.940225 316 : 4251, 4027
7212 16:34:08.940613 320 : 4250, 4027
7213 16:34:08.943744 324 : 4250, 4027
7214 16:34:08.944219 328 : 4250, 4027
7215 16:34:08.944530 332 : 4361, 4137
7216 16:34:08.946696 336 : 4250, 3744
7217 16:34:08.947114 340 : 4250, 1523
7218 16:34:08.947421
7219 16:34:08.950116 MIOCK jitter meter ch=0
7220 16:34:08.950552
7221 16:34:08.953311 1T = (340-100) = 240 dly cells
7222 16:34:08.959951 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7223 16:34:08.960628 ==
7224 16:34:08.963494 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 16:34:08.966806 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7226 16:34:08.967197 ==
7227 16:34:08.972973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7228 16:34:08.976674 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7229 16:34:08.979961 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7230 16:34:08.986411 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7231 16:34:08.994765 [CA 0] Center 41 (11~72) winsize 62
7232 16:34:08.998366 [CA 1] Center 41 (11~72) winsize 62
7233 16:34:09.001234 [CA 2] Center 37 (7~68) winsize 62
7234 16:34:09.004589 [CA 3] Center 37 (7~67) winsize 61
7235 16:34:09.008573 [CA 4] Center 35 (5~66) winsize 62
7236 16:34:09.011281 [CA 5] Center 35 (5~65) winsize 61
7237 16:34:09.011666
7238 16:34:09.014158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7239 16:34:09.014585
7240 16:34:09.021423 [CATrainingPosCal] consider 1 rank data
7241 16:34:09.021894 u2DelayCellTimex100 = 271/100 ps
7242 16:34:09.027334 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7243 16:34:09.030832 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7244 16:34:09.034599 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7245 16:34:09.037658 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7246 16:34:09.041448 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7247 16:34:09.044140 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7248 16:34:09.044527
7249 16:34:09.047512 CA PerBit enable=1, Macro0, CA PI delay=35
7250 16:34:09.048021
7251 16:34:09.050442 [CBTSetCACLKResult] CA Dly = 35
7252 16:34:09.054074 CS Dly: 11 (0~42)
7253 16:34:09.057315 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7254 16:34:09.060922 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7255 16:34:09.061307 ==
7256 16:34:09.063964 Dram Type= 6, Freq= 0, CH_0, rank 1
7257 16:34:09.070758 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7258 16:34:09.071150 ==
7259 16:34:09.073819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7260 16:34:09.080758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7261 16:34:09.084007 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7262 16:34:09.090662 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7263 16:34:09.097787 [CA 0] Center 42 (12~73) winsize 62
7264 16:34:09.100796 [CA 1] Center 42 (12~73) winsize 62
7265 16:34:09.104257 [CA 2] Center 38 (9~68) winsize 60
7266 16:34:09.107556 [CA 3] Center 37 (8~67) winsize 60
7267 16:34:09.110820 [CA 4] Center 36 (6~66) winsize 61
7268 16:34:09.113919 [CA 5] Center 36 (6~66) winsize 61
7269 16:34:09.114435
7270 16:34:09.117720 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7271 16:34:09.118184
7272 16:34:09.124091 [CATrainingPosCal] consider 2 rank data
7273 16:34:09.124562 u2DelayCellTimex100 = 271/100 ps
7274 16:34:09.130489 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7275 16:34:09.133441 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7276 16:34:09.136842 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7277 16:34:09.140833 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7278 16:34:09.143547 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7279 16:34:09.147316 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7280 16:34:09.147788
7281 16:34:09.150086 CA PerBit enable=1, Macro0, CA PI delay=35
7282 16:34:09.150518
7283 16:34:09.153717 [CBTSetCACLKResult] CA Dly = 35
7284 16:34:09.156931 CS Dly: 11 (0~42)
7285 16:34:09.159956 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7286 16:34:09.163496 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7287 16:34:09.163962
7288 16:34:09.166571 ----->DramcWriteLeveling(PI) begin...
7289 16:34:09.166966 ==
7290 16:34:09.170255 Dram Type= 6, Freq= 0, CH_0, rank 0
7291 16:34:09.176949 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7292 16:34:09.177426 ==
7293 16:34:09.179637 Write leveling (Byte 0): 29 => 29
7294 16:34:09.182989 Write leveling (Byte 1): 26 => 26
7295 16:34:09.186497 DramcWriteLeveling(PI) end<-----
7296 16:34:09.186933
7297 16:34:09.187400 ==
7298 16:34:09.189731 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 16:34:09.192989 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7300 16:34:09.193375 ==
7301 16:34:09.196184 [Gating] SW mode calibration
7302 16:34:09.202499 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7303 16:34:09.209218 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7304 16:34:09.212680 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7305 16:34:09.215717 0 12 4 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7306 16:34:09.222712 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7307 16:34:09.225480 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7308 16:34:09.229182 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7309 16:34:09.235425 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7310 16:34:09.238959 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7311 16:34:09.242604 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7312 16:34:09.248886 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7313 16:34:09.252263 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7314 16:34:09.255410 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7315 16:34:09.261964 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7316 16:34:09.265471 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7317 16:34:09.269034 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7318 16:34:09.275455 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7319 16:34:09.278626 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7320 16:34:09.282085 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7321 16:34:09.288510 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7322 16:34:09.292305 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7323 16:34:09.295030 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7324 16:34:09.298493 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7325 16:34:09.305080 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7326 16:34:09.308620 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7327 16:34:09.315027 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7328 16:34:09.318301 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7329 16:34:09.321635 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7330 16:34:09.327983 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7331 16:34:09.332119 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7332 16:34:09.334740 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7333 16:34:09.341375 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7334 16:34:09.344895 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7335 16:34:09.348120 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 16:34:09.351159 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 16:34:09.357750 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 16:34:09.361443 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 16:34:09.365382 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 16:34:09.371208 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 16:34:09.374610 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 16:34:09.378311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 16:34:09.384582 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7344 16:34:09.388130 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7345 16:34:09.391004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7346 16:34:09.394326 Total UI for P1: 0, mck2ui 16
7347 16:34:09.398160 best dqsien dly found for B0: ( 1, 0, 30)
7348 16:34:09.404541 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7349 16:34:09.407431 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7350 16:34:09.410734 Total UI for P1: 0, mck2ui 16
7351 16:34:09.414178 best dqsien dly found for B1: ( 1, 1, 6)
7352 16:34:09.417563 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7353 16:34:09.421225 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7354 16:34:09.421698
7355 16:34:09.423952 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7356 16:34:09.427625 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7357 16:34:09.430621 [Gating] SW calibration Done
7358 16:34:09.431010 ==
7359 16:34:09.434071 Dram Type= 6, Freq= 0, CH_0, rank 0
7360 16:34:09.440907 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7361 16:34:09.441402 ==
7362 16:34:09.441716 RX Vref Scan: 0
7363 16:34:09.441996
7364 16:34:09.443650 RX Vref 0 -> 0, step: 1
7365 16:34:09.444041
7366 16:34:09.446956 RX Delay 0 -> 252, step: 8
7367 16:34:09.450330 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7368 16:34:09.453632 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7369 16:34:09.457362 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7370 16:34:09.460635 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7371 16:34:09.466965 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7372 16:34:09.470052 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7373 16:34:09.473258 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7374 16:34:09.476810 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7375 16:34:09.479870 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7376 16:34:09.486459 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7377 16:34:09.489921 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7378 16:34:09.493227 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7379 16:34:09.496125 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7380 16:34:09.503173 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7381 16:34:09.506046 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7382 16:34:09.509444 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7383 16:34:09.509583 ==
7384 16:34:09.513158 Dram Type= 6, Freq= 0, CH_0, rank 0
7385 16:34:09.516083 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7386 16:34:09.516224 ==
7387 16:34:09.519496 DQS Delay:
7388 16:34:09.519636 DQS0 = 0, DQS1 = 0
7389 16:34:09.522606 DQM Delay:
7390 16:34:09.522744 DQM0 = 129, DQM1 = 124
7391 16:34:09.526065 DQ Delay:
7392 16:34:09.529370 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7393 16:34:09.532648 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7394 16:34:09.535820 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7395 16:34:09.539068 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7396 16:34:09.539227
7397 16:34:09.539359
7398 16:34:09.539474 ==
7399 16:34:09.542421 Dram Type= 6, Freq= 0, CH_0, rank 0
7400 16:34:09.545754 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7401 16:34:09.545941 ==
7402 16:34:09.546084
7403 16:34:09.546228
7404 16:34:09.549033 TX Vref Scan disable
7405 16:34:09.552693 == TX Byte 0 ==
7406 16:34:09.555698 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7407 16:34:09.559087 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7408 16:34:09.562578 == TX Byte 1 ==
7409 16:34:09.566069 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7410 16:34:09.568857 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7411 16:34:09.569213 ==
7412 16:34:09.572587 Dram Type= 6, Freq= 0, CH_0, rank 0
7413 16:34:09.579090 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7414 16:34:09.579507 ==
7415 16:34:09.591233
7416 16:34:09.594052 TX Vref early break, caculate TX vref
7417 16:34:09.597048 TX Vref=16, minBit 9, minWin=22, winSum=371
7418 16:34:09.600595 TX Vref=18, minBit 8, minWin=22, winSum=379
7419 16:34:09.603594 TX Vref=20, minBit 8, minWin=22, winSum=386
7420 16:34:09.607308 TX Vref=22, minBit 8, minWin=23, winSum=392
7421 16:34:09.610589 TX Vref=24, minBit 8, minWin=24, winSum=405
7422 16:34:09.617466 TX Vref=26, minBit 8, minWin=25, winSum=413
7423 16:34:09.620794 TX Vref=28, minBit 4, minWin=25, winSum=415
7424 16:34:09.623796 TX Vref=30, minBit 6, minWin=24, winSum=409
7425 16:34:09.627115 TX Vref=32, minBit 6, minWin=24, winSum=401
7426 16:34:09.630160 TX Vref=34, minBit 3, minWin=23, winSum=390
7427 16:34:09.636869 [TxChooseVref] Worse bit 4, Min win 25, Win sum 415, Final Vref 28
7428 16:34:09.637251
7429 16:34:09.640134 Final TX Range 0 Vref 28
7430 16:34:09.640519
7431 16:34:09.640815 ==
7432 16:34:09.643965 Dram Type= 6, Freq= 0, CH_0, rank 0
7433 16:34:09.647198 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7434 16:34:09.647582 ==
7435 16:34:09.647884
7436 16:34:09.648154
7437 16:34:09.650008 TX Vref Scan disable
7438 16:34:09.657078 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7439 16:34:09.657541 == TX Byte 0 ==
7440 16:34:09.660264 u2DelayCellOfst[0]=14 cells (4 PI)
7441 16:34:09.663643 u2DelayCellOfst[1]=18 cells (5 PI)
7442 16:34:09.666941 u2DelayCellOfst[2]=14 cells (4 PI)
7443 16:34:09.670418 u2DelayCellOfst[3]=10 cells (3 PI)
7444 16:34:09.673411 u2DelayCellOfst[4]=7 cells (2 PI)
7445 16:34:09.676568 u2DelayCellOfst[5]=0 cells (0 PI)
7446 16:34:09.680597 u2DelayCellOfst[6]=21 cells (6 PI)
7447 16:34:09.683238 u2DelayCellOfst[7]=21 cells (6 PI)
7448 16:34:09.686723 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7449 16:34:09.689902 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7450 16:34:09.693744 == TX Byte 1 ==
7451 16:34:09.694262 u2DelayCellOfst[8]=3 cells (1 PI)
7452 16:34:09.696495 u2DelayCellOfst[9]=0 cells (0 PI)
7453 16:34:09.700458 u2DelayCellOfst[10]=10 cells (3 PI)
7454 16:34:09.702837 u2DelayCellOfst[11]=3 cells (1 PI)
7455 16:34:09.706644 u2DelayCellOfst[12]=14 cells (4 PI)
7456 16:34:09.709969 u2DelayCellOfst[13]=14 cells (4 PI)
7457 16:34:09.712754 u2DelayCellOfst[14]=18 cells (5 PI)
7458 16:34:09.716431 u2DelayCellOfst[15]=18 cells (5 PI)
7459 16:34:09.720001 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7460 16:34:09.726195 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7461 16:34:09.726807 DramC Write-DBI on
7462 16:34:09.727235 ==
7463 16:34:09.730085 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 16:34:09.736184 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7465 16:34:09.736706 ==
7466 16:34:09.737031
7467 16:34:09.737309
7468 16:34:09.737575 TX Vref Scan disable
7469 16:34:09.740284 == TX Byte 0 ==
7470 16:34:09.743285 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7471 16:34:09.746946 == TX Byte 1 ==
7472 16:34:09.750300 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7473 16:34:09.750782 DramC Write-DBI off
7474 16:34:09.753963
7475 16:34:09.754531 [DATLAT]
7476 16:34:09.754847 Freq=1600, CH0 RK0
7477 16:34:09.755147
7478 16:34:09.756566 DATLAT Default: 0xf
7479 16:34:09.757012 0, 0xFFFF, sum = 0
7480 16:34:09.760262 1, 0xFFFF, sum = 0
7481 16:34:09.760787 2, 0xFFFF, sum = 0
7482 16:34:09.763506 3, 0xFFFF, sum = 0
7483 16:34:09.766496 4, 0xFFFF, sum = 0
7484 16:34:09.766906 5, 0xFFFF, sum = 0
7485 16:34:09.770117 6, 0xFFFF, sum = 0
7486 16:34:09.770563 7, 0xFFFF, sum = 0
7487 16:34:09.773321 8, 0xFFFF, sum = 0
7488 16:34:09.773731 9, 0xFFFF, sum = 0
7489 16:34:09.776509 10, 0xFFFF, sum = 0
7490 16:34:09.777012 11, 0xFFFF, sum = 0
7491 16:34:09.780219 12, 0xBFF, sum = 0
7492 16:34:09.780629 13, 0x0, sum = 1
7493 16:34:09.783525 14, 0x0, sum = 2
7494 16:34:09.783920 15, 0x0, sum = 3
7495 16:34:09.786576 16, 0x0, sum = 4
7496 16:34:09.786967 best_step = 14
7497 16:34:09.787266
7498 16:34:09.787543 ==
7499 16:34:09.790365 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 16:34:09.793354 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7501 16:34:09.793829 ==
7502 16:34:09.797064 RX Vref Scan: 1
7503 16:34:09.797547
7504 16:34:09.799710 Set Vref Range= 24 -> 127
7505 16:34:09.800095
7506 16:34:09.800473 RX Vref 24 -> 127, step: 1
7507 16:34:09.803330
7508 16:34:09.803717 RX Delay 11 -> 252, step: 4
7509 16:34:09.804018
7510 16:34:09.806697 Set Vref, RX VrefLevel [Byte0]: 24
7511 16:34:09.810087 [Byte1]: 24
7512 16:34:09.813833
7513 16:34:09.814352 Set Vref, RX VrefLevel [Byte0]: 25
7514 16:34:09.816972 [Byte1]: 25
7515 16:34:09.821107
7516 16:34:09.821498 Set Vref, RX VrefLevel [Byte0]: 26
7517 16:34:09.824329 [Byte1]: 26
7518 16:34:09.828685
7519 16:34:09.829477 Set Vref, RX VrefLevel [Byte0]: 27
7520 16:34:09.831664 [Byte1]: 27
7521 16:34:09.836247
7522 16:34:09.836635 Set Vref, RX VrefLevel [Byte0]: 28
7523 16:34:09.839175 [Byte1]: 28
7524 16:34:09.843947
7525 16:34:09.844332 Set Vref, RX VrefLevel [Byte0]: 29
7526 16:34:09.847016 [Byte1]: 29
7527 16:34:09.851258
7528 16:34:09.851643 Set Vref, RX VrefLevel [Byte0]: 30
7529 16:34:09.854898 [Byte1]: 30
7530 16:34:09.859295
7531 16:34:09.859888 Set Vref, RX VrefLevel [Byte0]: 31
7532 16:34:09.862137 [Byte1]: 31
7533 16:34:09.866986
7534 16:34:09.867380 Set Vref, RX VrefLevel [Byte0]: 32
7535 16:34:09.873042 [Byte1]: 32
7536 16:34:09.873497
7537 16:34:09.876546 Set Vref, RX VrefLevel [Byte0]: 33
7538 16:34:09.880077 [Byte1]: 33
7539 16:34:09.880716
7540 16:34:09.883040 Set Vref, RX VrefLevel [Byte0]: 34
7541 16:34:09.886290 [Byte1]: 34
7542 16:34:09.889855
7543 16:34:09.890387 Set Vref, RX VrefLevel [Byte0]: 35
7544 16:34:09.893216 [Byte1]: 35
7545 16:34:09.897530
7546 16:34:09.898000 Set Vref, RX VrefLevel [Byte0]: 36
7547 16:34:09.900242 [Byte1]: 36
7548 16:34:09.904569
7549 16:34:09.904956 Set Vref, RX VrefLevel [Byte0]: 37
7550 16:34:09.908244 [Byte1]: 37
7551 16:34:09.912752
7552 16:34:09.913249 Set Vref, RX VrefLevel [Byte0]: 38
7553 16:34:09.916103 [Byte1]: 38
7554 16:34:09.919839
7555 16:34:09.920222 Set Vref, RX VrefLevel [Byte0]: 39
7556 16:34:09.923476 [Byte1]: 39
7557 16:34:09.927333
7558 16:34:09.927721 Set Vref, RX VrefLevel [Byte0]: 40
7559 16:34:09.930619 [Byte1]: 40
7560 16:34:09.935435
7561 16:34:09.935822 Set Vref, RX VrefLevel [Byte0]: 41
7562 16:34:09.938259 [Byte1]: 41
7563 16:34:09.942896
7564 16:34:09.943282 Set Vref, RX VrefLevel [Byte0]: 42
7565 16:34:09.946563 [Byte1]: 42
7566 16:34:09.950645
7567 16:34:09.951042 Set Vref, RX VrefLevel [Byte0]: 43
7568 16:34:09.953696 [Byte1]: 43
7569 16:34:09.957894
7570 16:34:09.958317 Set Vref, RX VrefLevel [Byte0]: 44
7571 16:34:09.961642 [Byte1]: 44
7572 16:34:09.966127
7573 16:34:09.966653 Set Vref, RX VrefLevel [Byte0]: 45
7574 16:34:09.971774 [Byte1]: 45
7575 16:34:09.972166
7576 16:34:09.975784 Set Vref, RX VrefLevel [Byte0]: 46
7577 16:34:09.978907 [Byte1]: 46
7578 16:34:09.979298
7579 16:34:09.981932 Set Vref, RX VrefLevel [Byte0]: 47
7580 16:34:09.985491 [Byte1]: 47
7581 16:34:09.985877
7582 16:34:09.988460 Set Vref, RX VrefLevel [Byte0]: 48
7583 16:34:09.991846 [Byte1]: 48
7584 16:34:09.996004
7585 16:34:09.996394 Set Vref, RX VrefLevel [Byte0]: 49
7586 16:34:09.999293 [Byte1]: 49
7587 16:34:10.003789
7588 16:34:10.004306 Set Vref, RX VrefLevel [Byte0]: 50
7589 16:34:10.007003 [Byte1]: 50
7590 16:34:10.011607
7591 16:34:10.011994 Set Vref, RX VrefLevel [Byte0]: 51
7592 16:34:10.014516 [Byte1]: 51
7593 16:34:10.018724
7594 16:34:10.019113 Set Vref, RX VrefLevel [Byte0]: 52
7595 16:34:10.022164 [Byte1]: 52
7596 16:34:10.026708
7597 16:34:10.027095 Set Vref, RX VrefLevel [Byte0]: 53
7598 16:34:10.030005 [Byte1]: 53
7599 16:34:10.033940
7600 16:34:10.034369 Set Vref, RX VrefLevel [Byte0]: 54
7601 16:34:10.037549 [Byte1]: 54
7602 16:34:10.041542
7603 16:34:10.041935 Set Vref, RX VrefLevel [Byte0]: 55
7604 16:34:10.045077 [Byte1]: 55
7605 16:34:10.049300
7606 16:34:10.049687 Set Vref, RX VrefLevel [Byte0]: 56
7607 16:34:10.052675 [Byte1]: 56
7608 16:34:10.056866
7609 16:34:10.057399 Set Vref, RX VrefLevel [Byte0]: 57
7610 16:34:10.060371 [Byte1]: 57
7611 16:34:10.064442
7612 16:34:10.064828 Set Vref, RX VrefLevel [Byte0]: 58
7613 16:34:10.071287 [Byte1]: 58
7614 16:34:10.071676
7615 16:34:10.074312 Set Vref, RX VrefLevel [Byte0]: 59
7616 16:34:10.077356 [Byte1]: 59
7617 16:34:10.077744
7618 16:34:10.081129 Set Vref, RX VrefLevel [Byte0]: 60
7619 16:34:10.084277 [Byte1]: 60
7620 16:34:10.087536
7621 16:34:10.088191 Set Vref, RX VrefLevel [Byte0]: 61
7622 16:34:10.090430 [Byte1]: 61
7623 16:34:10.095113
7624 16:34:10.095741 Set Vref, RX VrefLevel [Byte0]: 62
7625 16:34:10.098033 [Byte1]: 62
7626 16:34:10.102790
7627 16:34:10.103433 Set Vref, RX VrefLevel [Byte0]: 63
7628 16:34:10.105768 [Byte1]: 63
7629 16:34:10.109987
7630 16:34:10.110289 Set Vref, RX VrefLevel [Byte0]: 64
7631 16:34:10.113076 [Byte1]: 64
7632 16:34:10.117715
7633 16:34:10.117882 Set Vref, RX VrefLevel [Byte0]: 65
7634 16:34:10.120905 [Byte1]: 65
7635 16:34:10.125202
7636 16:34:10.125365 Set Vref, RX VrefLevel [Byte0]: 66
7637 16:34:10.128691 [Byte1]: 66
7638 16:34:10.132778
7639 16:34:10.132894 Set Vref, RX VrefLevel [Byte0]: 67
7640 16:34:10.136203 [Byte1]: 67
7641 16:34:10.140183
7642 16:34:10.140285 Set Vref, RX VrefLevel [Byte0]: 68
7643 16:34:10.143570 [Byte1]: 68
7644 16:34:10.147590
7645 16:34:10.147674 Set Vref, RX VrefLevel [Byte0]: 69
7646 16:34:10.151282 [Byte1]: 69
7647 16:34:10.155497
7648 16:34:10.155581 Set Vref, RX VrefLevel [Byte0]: 70
7649 16:34:10.158810 [Byte1]: 70
7650 16:34:10.163202
7651 16:34:10.163307 Set Vref, RX VrefLevel [Byte0]: 71
7652 16:34:10.169844 [Byte1]: 71
7653 16:34:10.169930
7654 16:34:10.172828 Set Vref, RX VrefLevel [Byte0]: 72
7655 16:34:10.176329 [Byte1]: 72
7656 16:34:10.176406
7657 16:34:10.179266 Final RX Vref Byte 0 = 53 to rank0
7658 16:34:10.182748 Final RX Vref Byte 1 = 56 to rank0
7659 16:34:10.185851 Final RX Vref Byte 0 = 53 to rank1
7660 16:34:10.189284 Final RX Vref Byte 1 = 56 to rank1==
7661 16:34:10.192616 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 16:34:10.196031 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7663 16:34:10.196116 ==
7664 16:34:10.199542 DQS Delay:
7665 16:34:10.199645 DQS0 = 0, DQS1 = 0
7666 16:34:10.199709 DQM Delay:
7667 16:34:10.202514 DQM0 = 127, DQM1 = 121
7668 16:34:10.202590 DQ Delay:
7669 16:34:10.206406 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7670 16:34:10.209422 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7671 16:34:10.215993 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7672 16:34:10.219695 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7673 16:34:10.219990
7674 16:34:10.220220
7675 16:34:10.220439
7676 16:34:10.223012 [DramC_TX_OE_Calibration] TA2
7677 16:34:10.226236 Original DQ_B0 (3 6) =30, OEN = 27
7678 16:34:10.229806 Original DQ_B1 (3 6) =30, OEN = 27
7679 16:34:10.230101 24, 0x0, End_B0=24 End_B1=24
7680 16:34:10.232389 25, 0x0, End_B0=25 End_B1=25
7681 16:34:10.236068 26, 0x0, End_B0=26 End_B1=26
7682 16:34:10.239651 27, 0x0, End_B0=27 End_B1=27
7683 16:34:10.239952 28, 0x0, End_B0=28 End_B1=28
7684 16:34:10.242806 29, 0x0, End_B0=29 End_B1=29
7685 16:34:10.246002 30, 0x0, End_B0=30 End_B1=30
7686 16:34:10.249489 31, 0x4141, End_B0=30 End_B1=30
7687 16:34:10.252423 Byte0 end_step=30 best_step=27
7688 16:34:10.255866 Byte1 end_step=30 best_step=27
7689 16:34:10.256395 Byte0 TX OE(2T, 0.5T) = (3, 3)
7690 16:34:10.259361 Byte1 TX OE(2T, 0.5T) = (3, 3)
7691 16:34:10.259783
7692 16:34:10.260236
7693 16:34:10.269166 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7694 16:34:10.272681 CH0 RK0: MR19=303, MR18=1A1A
7695 16:34:10.275604 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7696 16:34:10.279249
7697 16:34:10.282125 ----->DramcWriteLeveling(PI) begin...
7698 16:34:10.282620 ==
7699 16:34:10.285781 Dram Type= 6, Freq= 0, CH_0, rank 1
7700 16:34:10.289701 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7701 16:34:10.290164 ==
7702 16:34:10.292599 Write leveling (Byte 0): 31 => 31
7703 16:34:10.295910 Write leveling (Byte 1): 27 => 27
7704 16:34:10.298792 DramcWriteLeveling(PI) end<-----
7705 16:34:10.299174
7706 16:34:10.299466 ==
7707 16:34:10.302125 Dram Type= 6, Freq= 0, CH_0, rank 1
7708 16:34:10.305237 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7709 16:34:10.305698 ==
7710 16:34:10.309090 [Gating] SW mode calibration
7711 16:34:10.315902 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7712 16:34:10.322563 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7713 16:34:10.325462 0 12 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7714 16:34:10.328746 0 12 4 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7715 16:34:10.335089 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7716 16:34:10.338266 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7717 16:34:10.341495 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7718 16:34:10.347959 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7719 16:34:10.351590 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7720 16:34:10.355046 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
7721 16:34:10.361686 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7722 16:34:10.364817 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
7723 16:34:10.368069 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7724 16:34:10.374501 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7725 16:34:10.378270 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7726 16:34:10.381275 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 16:34:10.387893 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7728 16:34:10.391183 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7729 16:34:10.394378 0 14 0 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7730 16:34:10.401293 0 14 4 | B1->B0 | 3534 4646 | 1 0 | (1 1) (0 0)
7731 16:34:10.404130 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7732 16:34:10.407592 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7733 16:34:10.414118 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 16:34:10.417642 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 16:34:10.421019 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7736 16:34:10.427609 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7737 16:34:10.431337 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7738 16:34:10.434453 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7739 16:34:10.441000 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7740 16:34:10.444001 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7741 16:34:10.447873 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7742 16:34:10.454315 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 16:34:10.457156 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 16:34:10.460374 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 16:34:10.467066 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 16:34:10.470309 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 16:34:10.473826 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 16:34:10.480291 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 16:34:10.483482 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 16:34:10.486934 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 16:34:10.493849 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 16:34:10.496748 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7753 16:34:10.500359 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7754 16:34:10.506780 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7755 16:34:10.507173 Total UI for P1: 0, mck2ui 16
7756 16:34:10.510692 best dqsien dly found for B0: ( 1, 0, 30)
7757 16:34:10.516773 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 16:34:10.520224 Total UI for P1: 0, mck2ui 16
7759 16:34:10.523606 best dqsien dly found for B1: ( 1, 1, 4)
7760 16:34:10.526722 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7761 16:34:10.530513 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7762 16:34:10.530903
7763 16:34:10.533506 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7764 16:34:10.536633 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7765 16:34:10.540140 [Gating] SW calibration Done
7766 16:34:10.540529 ==
7767 16:34:10.543050 Dram Type= 6, Freq= 0, CH_0, rank 1
7768 16:34:10.546970 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7769 16:34:10.547490 ==
7770 16:34:10.550098 RX Vref Scan: 0
7771 16:34:10.550544
7772 16:34:10.553260 RX Vref 0 -> 0, step: 1
7773 16:34:10.553723
7774 16:34:10.554026 RX Delay 0 -> 252, step: 8
7775 16:34:10.560233 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7776 16:34:10.563299 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7777 16:34:10.566374 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7778 16:34:10.569873 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7779 16:34:10.573149 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7780 16:34:10.579902 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7781 16:34:10.583053 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7782 16:34:10.586310 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7783 16:34:10.589646 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7784 16:34:10.592604 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7785 16:34:10.599298 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7786 16:34:10.603003 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7787 16:34:10.606348 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7788 16:34:10.609740 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7789 16:34:10.612763 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7790 16:34:10.619267 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7791 16:34:10.619765 ==
7792 16:34:10.622850 Dram Type= 6, Freq= 0, CH_0, rank 1
7793 16:34:10.625674 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7794 16:34:10.626281 ==
7795 16:34:10.626605 DQS Delay:
7796 16:34:10.629130 DQS0 = 0, DQS1 = 0
7797 16:34:10.629517 DQM Delay:
7798 16:34:10.632137 DQM0 = 131, DQM1 = 124
7799 16:34:10.632728 DQ Delay:
7800 16:34:10.635797 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7801 16:34:10.639284 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7802 16:34:10.642343 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7803 16:34:10.649242 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7804 16:34:10.649729
7805 16:34:10.650039
7806 16:34:10.650366 ==
7807 16:34:10.652398 Dram Type= 6, Freq= 0, CH_0, rank 1
7808 16:34:10.655646 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7809 16:34:10.656037 ==
7810 16:34:10.656340
7811 16:34:10.656619
7812 16:34:10.659132 TX Vref Scan disable
7813 16:34:10.659525 == TX Byte 0 ==
7814 16:34:10.665333 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7815 16:34:10.668970 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7816 16:34:10.669530 == TX Byte 1 ==
7817 16:34:10.675150 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7818 16:34:10.678692 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7819 16:34:10.679081 ==
7820 16:34:10.682028 Dram Type= 6, Freq= 0, CH_0, rank 1
7821 16:34:10.685673 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7822 16:34:10.686305 ==
7823 16:34:10.700485
7824 16:34:10.703739 TX Vref early break, caculate TX vref
7825 16:34:10.707109 TX Vref=16, minBit 8, minWin=21, winSum=374
7826 16:34:10.710733 TX Vref=18, minBit 8, minWin=22, winSum=384
7827 16:34:10.713728 TX Vref=20, minBit 8, minWin=23, winSum=388
7828 16:34:10.716996 TX Vref=22, minBit 1, minWin=23, winSum=396
7829 16:34:10.720221 TX Vref=24, minBit 8, minWin=24, winSum=408
7830 16:34:10.726837 TX Vref=26, minBit 3, minWin=25, winSum=414
7831 16:34:10.730430 TX Vref=28, minBit 0, minWin=25, winSum=414
7832 16:34:10.733999 TX Vref=30, minBit 8, minWin=24, winSum=412
7833 16:34:10.737549 TX Vref=32, minBit 8, minWin=24, winSum=404
7834 16:34:10.740666 TX Vref=34, minBit 8, minWin=23, winSum=397
7835 16:34:10.743984 TX Vref=36, minBit 8, minWin=22, winSum=389
7836 16:34:10.750322 [TxChooseVref] Worse bit 3, Min win 25, Win sum 414, Final Vref 26
7837 16:34:10.750716
7838 16:34:10.753960 Final TX Range 0 Vref 26
7839 16:34:10.754488
7840 16:34:10.754795 ==
7841 16:34:10.756631 Dram Type= 6, Freq= 0, CH_0, rank 1
7842 16:34:10.760180 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7843 16:34:10.760660 ==
7844 16:34:10.761205
7845 16:34:10.761530
7846 16:34:10.763786 TX Vref Scan disable
7847 16:34:10.770755 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7848 16:34:10.771255 == TX Byte 0 ==
7849 16:34:10.773725 u2DelayCellOfst[0]=10 cells (3 PI)
7850 16:34:10.776991 u2DelayCellOfst[1]=14 cells (4 PI)
7851 16:34:10.779930 u2DelayCellOfst[2]=10 cells (3 PI)
7852 16:34:10.783553 u2DelayCellOfst[3]=7 cells (2 PI)
7853 16:34:10.786730 u2DelayCellOfst[4]=7 cells (2 PI)
7854 16:34:10.790252 u2DelayCellOfst[5]=0 cells (0 PI)
7855 16:34:10.793600 u2DelayCellOfst[6]=14 cells (4 PI)
7856 16:34:10.796776 u2DelayCellOfst[7]=14 cells (4 PI)
7857 16:34:10.800185 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7858 16:34:10.803686 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7859 16:34:10.806632 == TX Byte 1 ==
7860 16:34:10.810121 u2DelayCellOfst[8]=3 cells (1 PI)
7861 16:34:10.813287 u2DelayCellOfst[9]=0 cells (0 PI)
7862 16:34:10.813678 u2DelayCellOfst[10]=7 cells (2 PI)
7863 16:34:10.816683 u2DelayCellOfst[11]=3 cells (1 PI)
7864 16:34:10.820214 u2DelayCellOfst[12]=14 cells (4 PI)
7865 16:34:10.823350 u2DelayCellOfst[13]=14 cells (4 PI)
7866 16:34:10.826384 u2DelayCellOfst[14]=18 cells (5 PI)
7867 16:34:10.829623 u2DelayCellOfst[15]=14 cells (4 PI)
7868 16:34:10.836226 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7869 16:34:10.839711 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7870 16:34:10.840153 DramC Write-DBI on
7871 16:34:10.840452 ==
7872 16:34:10.842761 Dram Type= 6, Freq= 0, CH_0, rank 1
7873 16:34:10.849789 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7874 16:34:10.850568 ==
7875 16:34:10.850949
7876 16:34:10.851404
7877 16:34:10.852901 TX Vref Scan disable
7878 16:34:10.853481 == TX Byte 0 ==
7879 16:34:10.859499 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7880 16:34:10.859891 == TX Byte 1 ==
7881 16:34:10.862981 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7882 16:34:10.865888 DramC Write-DBI off
7883 16:34:10.866311
7884 16:34:10.866618 [DATLAT]
7885 16:34:10.869718 Freq=1600, CH0 RK1
7886 16:34:10.870104
7887 16:34:10.870449 DATLAT Default: 0xe
7888 16:34:10.872552 0, 0xFFFF, sum = 0
7889 16:34:10.873123 1, 0xFFFF, sum = 0
7890 16:34:10.876172 2, 0xFFFF, sum = 0
7891 16:34:10.876566 3, 0xFFFF, sum = 0
7892 16:34:10.879417 4, 0xFFFF, sum = 0
7893 16:34:10.879888 5, 0xFFFF, sum = 0
7894 16:34:10.882700 6, 0xFFFF, sum = 0
7895 16:34:10.883092 7, 0xFFFF, sum = 0
7896 16:34:10.886103 8, 0xFFFF, sum = 0
7897 16:34:10.886678 9, 0xFFFF, sum = 0
7898 16:34:10.889261 10, 0xFFFF, sum = 0
7899 16:34:10.892825 11, 0xFFFF, sum = 0
7900 16:34:10.893220 12, 0x8FFF, sum = 0
7901 16:34:10.895701 13, 0x0, sum = 1
7902 16:34:10.896109 14, 0x0, sum = 2
7903 16:34:10.899039 15, 0x0, sum = 3
7904 16:34:10.899748 16, 0x0, sum = 4
7905 16:34:10.900162 best_step = 14
7906 16:34:10.900458
7907 16:34:10.902535 ==
7908 16:34:10.905855 Dram Type= 6, Freq= 0, CH_0, rank 1
7909 16:34:10.909197 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7910 16:34:10.909748 ==
7911 16:34:10.910352 RX Vref Scan: 0
7912 16:34:10.910682
7913 16:34:10.912704 RX Vref 0 -> 0, step: 1
7914 16:34:10.913220
7915 16:34:10.915355 RX Delay 11 -> 252, step: 4
7916 16:34:10.919146 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7917 16:34:10.922115 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7918 16:34:10.929230 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7919 16:34:10.932360 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7920 16:34:10.935539 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7921 16:34:10.938877 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7922 16:34:10.942143 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7923 16:34:10.948976 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7924 16:34:10.951692 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7925 16:34:10.955365 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7926 16:34:10.958752 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7927 16:34:10.961917 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7928 16:34:10.969191 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7929 16:34:10.972149 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7930 16:34:10.975629 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7931 16:34:10.978391 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7932 16:34:10.982156 ==
7933 16:34:10.982667 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 16:34:10.988592 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7935 16:34:10.988978 ==
7936 16:34:10.989402 DQS Delay:
7937 16:34:10.991868 DQS0 = 0, DQS1 = 0
7938 16:34:10.992346 DQM Delay:
7939 16:34:10.995463 DQM0 = 129, DQM1 = 120
7940 16:34:10.995923 DQ Delay:
7941 16:34:10.998167 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7942 16:34:11.001978 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7943 16:34:11.004812 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7944 16:34:11.008133 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7945 16:34:11.008652
7946 16:34:11.009081
7947 16:34:11.009495
7948 16:34:11.011280 [DramC_TX_OE_Calibration] TA2
7949 16:34:11.014684 Original DQ_B0 (3 6) =30, OEN = 27
7950 16:34:11.017986 Original DQ_B1 (3 6) =30, OEN = 27
7951 16:34:11.021481 24, 0x0, End_B0=24 End_B1=24
7952 16:34:11.024795 25, 0x0, End_B0=25 End_B1=25
7953 16:34:11.025337 26, 0x0, End_B0=26 End_B1=26
7954 16:34:11.027824 27, 0x0, End_B0=27 End_B1=27
7955 16:34:11.031543 28, 0x0, End_B0=28 End_B1=28
7956 16:34:11.034674 29, 0x0, End_B0=29 End_B1=29
7957 16:34:11.038292 30, 0x0, End_B0=30 End_B1=30
7958 16:34:11.038907 31, 0x4141, End_B0=30 End_B1=30
7959 16:34:11.041344 Byte0 end_step=30 best_step=27
7960 16:34:11.044498 Byte1 end_step=30 best_step=27
7961 16:34:11.047544 Byte0 TX OE(2T, 0.5T) = (3, 3)
7962 16:34:11.050794 Byte1 TX OE(2T, 0.5T) = (3, 3)
7963 16:34:11.051174
7964 16:34:11.051466
7965 16:34:11.057522 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
7966 16:34:11.061172 CH0 RK1: MR19=303, MR18=2525
7967 16:34:11.067673 CH0_RK1: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
7968 16:34:11.070394 [RxdqsGatingPostProcess] freq 1600
7969 16:34:11.077069 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7970 16:34:11.080793 Pre-setting of DQS Precalculation
7971 16:34:11.083589 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7972 16:34:11.083981 ==
7973 16:34:11.087209 Dram Type= 6, Freq= 0, CH_1, rank 0
7974 16:34:11.090787 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7975 16:34:11.091065 ==
7976 16:34:11.097313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7977 16:34:11.100831 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7978 16:34:11.106967 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7979 16:34:11.110588 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7980 16:34:11.119468 [CA 0] Center 41 (11~71) winsize 61
7981 16:34:11.123568 [CA 1] Center 40 (10~71) winsize 62
7982 16:34:11.126671 [CA 2] Center 36 (6~66) winsize 61
7983 16:34:11.130303 [CA 3] Center 35 (6~65) winsize 60
7984 16:34:11.132924 [CA 4] Center 33 (4~63) winsize 60
7985 16:34:11.136355 [CA 5] Center 33 (4~63) winsize 60
7986 16:34:11.136724
7987 16:34:11.139586 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7988 16:34:11.139958
7989 16:34:11.143295 [CATrainingPosCal] consider 1 rank data
7990 16:34:11.145929 u2DelayCellTimex100 = 271/100 ps
7991 16:34:11.149943 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
7992 16:34:11.156796 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
7993 16:34:11.159927 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
7994 16:34:11.163311 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
7995 16:34:11.166241 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
7996 16:34:11.170188 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
7997 16:34:11.170702
7998 16:34:11.172892 CA PerBit enable=1, Macro0, CA PI delay=33
7999 16:34:11.173272
8000 16:34:11.176428 [CBTSetCACLKResult] CA Dly = 33
8001 16:34:11.179759 CS Dly: 9 (0~40)
8002 16:34:11.182953 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8003 16:34:11.186521 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8004 16:34:11.186905 ==
8005 16:34:11.189362 Dram Type= 6, Freq= 0, CH_1, rank 1
8006 16:34:11.193009 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8007 16:34:11.195935 ==
8008 16:34:11.199893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8009 16:34:11.202717 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8010 16:34:11.209255 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8011 16:34:11.212641 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8012 16:34:11.222327 [CA 0] Center 41 (11~71) winsize 61
8013 16:34:11.225501 [CA 1] Center 41 (10~72) winsize 63
8014 16:34:11.229075 [CA 2] Center 36 (7~66) winsize 60
8015 16:34:11.232514 [CA 3] Center 36 (7~65) winsize 59
8016 16:34:11.235823 [CA 4] Center 34 (5~64) winsize 60
8017 16:34:11.238813 [CA 5] Center 34 (4~64) winsize 61
8018 16:34:11.239341
8019 16:34:11.242160 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8020 16:34:11.242593
8021 16:34:11.246032 [CATrainingPosCal] consider 2 rank data
8022 16:34:11.248860 u2DelayCellTimex100 = 271/100 ps
8023 16:34:11.251966 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8024 16:34:11.258632 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8025 16:34:11.261982 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8026 16:34:11.265800 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8027 16:34:11.268994 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8028 16:34:11.272241 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8029 16:34:11.272713
8030 16:34:11.275609 CA PerBit enable=1, Macro0, CA PI delay=33
8031 16:34:11.276175
8032 16:34:11.278426 [CBTSetCACLKResult] CA Dly = 33
8033 16:34:11.282091 CS Dly: 9 (0~41)
8034 16:34:11.285585 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8035 16:34:11.288893 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8036 16:34:11.289309
8037 16:34:11.292272 ----->DramcWriteLeveling(PI) begin...
8038 16:34:11.292665 ==
8039 16:34:11.295193 Dram Type= 6, Freq= 0, CH_1, rank 0
8040 16:34:11.298790 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8041 16:34:11.301786 ==
8042 16:34:11.305421 Write leveling (Byte 0): 23 => 23
8043 16:34:11.305883 Write leveling (Byte 1): 21 => 21
8044 16:34:11.308395 DramcWriteLeveling(PI) end<-----
8045 16:34:11.308897
8046 16:34:11.309344 ==
8047 16:34:11.311829 Dram Type= 6, Freq= 0, CH_1, rank 0
8048 16:34:11.318505 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8049 16:34:11.319088 ==
8050 16:34:11.321662 [Gating] SW mode calibration
8051 16:34:11.328308 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8052 16:34:11.331574 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8053 16:34:11.338299 0 12 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
8054 16:34:11.341777 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 16:34:11.344991 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 16:34:11.351657 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 16:34:11.354727 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 16:34:11.358167 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 16:34:11.364698 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8060 16:34:11.368276 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8061 16:34:11.371791 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
8062 16:34:11.378054 0 13 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8063 16:34:11.381201 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 16:34:11.385269 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 16:34:11.391635 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 16:34:11.394791 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 16:34:11.397808 0 13 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8068 16:34:11.404499 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8069 16:34:11.407805 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8070 16:34:11.411043 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 16:34:11.418156 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 16:34:11.420912 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 16:34:11.424440 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 16:34:11.430753 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 16:34:11.434045 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8076 16:34:11.437332 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8077 16:34:11.444087 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8078 16:34:11.447281 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8079 16:34:11.450449 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8080 16:34:11.457800 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 16:34:11.460812 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 16:34:11.463944 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 16:34:11.467047 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 16:34:11.473759 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 16:34:11.477267 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 16:34:11.480925 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 16:34:11.486900 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 16:34:11.490844 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 16:34:11.493897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 16:34:11.500450 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 16:34:11.503986 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8092 16:34:11.507021 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8093 16:34:11.513930 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8094 16:34:11.516952 Total UI for P1: 0, mck2ui 16
8095 16:34:11.520057 best dqsien dly found for B0: ( 1, 0, 26)
8096 16:34:11.523809 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 16:34:11.527357 Total UI for P1: 0, mck2ui 16
8098 16:34:11.530175 best dqsien dly found for B1: ( 1, 1, 0)
8099 16:34:11.533170 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8100 16:34:11.536702 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8101 16:34:11.537096
8102 16:34:11.540321 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8103 16:34:11.543447 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8104 16:34:11.546820 [Gating] SW calibration Done
8105 16:34:11.547209 ==
8106 16:34:11.549723 Dram Type= 6, Freq= 0, CH_1, rank 0
8107 16:34:11.556726 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8108 16:34:11.557135 ==
8109 16:34:11.557447 RX Vref Scan: 0
8110 16:34:11.557731
8111 16:34:11.560106 RX Vref 0 -> 0, step: 1
8112 16:34:11.560492
8113 16:34:11.563192 RX Delay 0 -> 252, step: 8
8114 16:34:11.566586 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8115 16:34:11.570076 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8116 16:34:11.572978 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8117 16:34:11.576415 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8118 16:34:11.582971 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8119 16:34:11.586090 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8120 16:34:11.589378 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8121 16:34:11.592661 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8122 16:34:11.596440 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8123 16:34:11.602780 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8124 16:34:11.606312 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8125 16:34:11.609658 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8126 16:34:11.612907 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8127 16:34:11.619078 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8128 16:34:11.622650 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8129 16:34:11.625911 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8130 16:34:11.626454 ==
8131 16:34:11.629242 Dram Type= 6, Freq= 0, CH_1, rank 0
8132 16:34:11.632386 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8133 16:34:11.632855 ==
8134 16:34:11.635890 DQS Delay:
8135 16:34:11.636429 DQS0 = 0, DQS1 = 0
8136 16:34:11.639388 DQM Delay:
8137 16:34:11.640041 DQM0 = 130, DQM1 = 125
8138 16:34:11.640480 DQ Delay:
8139 16:34:11.645805 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8140 16:34:11.649175 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8141 16:34:11.652466 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8142 16:34:11.655439 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8143 16:34:11.655828
8144 16:34:11.656124
8145 16:34:11.656396 ==
8146 16:34:11.658946 Dram Type= 6, Freq= 0, CH_1, rank 0
8147 16:34:11.662489 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8148 16:34:11.662875 ==
8149 16:34:11.663175
8150 16:34:11.663475
8151 16:34:11.665650 TX Vref Scan disable
8152 16:34:11.668768 == TX Byte 0 ==
8153 16:34:11.672102 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8154 16:34:11.675536 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8155 16:34:11.679333 == TX Byte 1 ==
8156 16:34:11.681995 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8157 16:34:11.685200 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8158 16:34:11.685584 ==
8159 16:34:11.688990 Dram Type= 6, Freq= 0, CH_1, rank 0
8160 16:34:11.692392 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8161 16:34:11.695794 ==
8162 16:34:11.706351
8163 16:34:11.709324 TX Vref early break, caculate TX vref
8164 16:34:11.712682 TX Vref=16, minBit 0, minWin=22, winSum=370
8165 16:34:11.716450 TX Vref=18, minBit 0, minWin=23, winSum=380
8166 16:34:11.719731 TX Vref=20, minBit 3, minWin=23, winSum=387
8167 16:34:11.722805 TX Vref=22, minBit 3, minWin=23, winSum=395
8168 16:34:11.726372 TX Vref=24, minBit 0, minWin=24, winSum=403
8169 16:34:11.733503 TX Vref=26, minBit 0, minWin=25, winSum=413
8170 16:34:11.736196 TX Vref=28, minBit 0, minWin=25, winSum=414
8171 16:34:11.739960 TX Vref=30, minBit 0, minWin=24, winSum=409
8172 16:34:11.742863 TX Vref=32, minBit 3, minWin=23, winSum=398
8173 16:34:11.746326 TX Vref=34, minBit 1, minWin=23, winSum=389
8174 16:34:11.752998 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8175 16:34:11.753481
8176 16:34:11.755823 Final TX Range 0 Vref 28
8177 16:34:11.756222
8178 16:34:11.756612 ==
8179 16:34:11.759900 Dram Type= 6, Freq= 0, CH_1, rank 0
8180 16:34:11.762828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8181 16:34:11.763350 ==
8182 16:34:11.763748
8183 16:34:11.764112
8184 16:34:11.766121 TX Vref Scan disable
8185 16:34:11.772670 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8186 16:34:11.773163 == TX Byte 0 ==
8187 16:34:11.775761 u2DelayCellOfst[0]=14 cells (4 PI)
8188 16:34:11.779372 u2DelayCellOfst[1]=10 cells (3 PI)
8189 16:34:11.782608 u2DelayCellOfst[2]=0 cells (0 PI)
8190 16:34:11.785798 u2DelayCellOfst[3]=7 cells (2 PI)
8191 16:34:11.788679 u2DelayCellOfst[4]=7 cells (2 PI)
8192 16:34:11.792492 u2DelayCellOfst[5]=14 cells (4 PI)
8193 16:34:11.795759 u2DelayCellOfst[6]=14 cells (4 PI)
8194 16:34:11.798705 u2DelayCellOfst[7]=3 cells (1 PI)
8195 16:34:11.802792 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8196 16:34:11.805645 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8197 16:34:11.808957 == TX Byte 1 ==
8198 16:34:11.809346 u2DelayCellOfst[8]=0 cells (0 PI)
8199 16:34:11.811913 u2DelayCellOfst[9]=3 cells (1 PI)
8200 16:34:11.815645 u2DelayCellOfst[10]=10 cells (3 PI)
8201 16:34:11.818592 u2DelayCellOfst[11]=0 cells (0 PI)
8202 16:34:11.821746 u2DelayCellOfst[12]=14 cells (4 PI)
8203 16:34:11.825725 u2DelayCellOfst[13]=18 cells (5 PI)
8204 16:34:11.828857 u2DelayCellOfst[14]=14 cells (4 PI)
8205 16:34:11.832140 u2DelayCellOfst[15]=18 cells (5 PI)
8206 16:34:11.835278 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8207 16:34:11.841760 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8208 16:34:11.842303 DramC Write-DBI on
8209 16:34:11.842751 ==
8210 16:34:11.845539 Dram Type= 6, Freq= 0, CH_1, rank 0
8211 16:34:11.851952 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8212 16:34:11.852441 ==
8213 16:34:11.852744
8214 16:34:11.853022
8215 16:34:11.853340 TX Vref Scan disable
8216 16:34:11.855536 == TX Byte 0 ==
8217 16:34:11.858591 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8218 16:34:11.862345 == TX Byte 1 ==
8219 16:34:11.865252 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8220 16:34:11.868776 DramC Write-DBI off
8221 16:34:11.869190
8222 16:34:11.869529 [DATLAT]
8223 16:34:11.869812 Freq=1600, CH1 RK0
8224 16:34:11.870081
8225 16:34:11.872202 DATLAT Default: 0xf
8226 16:34:11.875507 0, 0xFFFF, sum = 0
8227 16:34:11.875900 1, 0xFFFF, sum = 0
8228 16:34:11.878401 2, 0xFFFF, sum = 0
8229 16:34:11.878862 3, 0xFFFF, sum = 0
8230 16:34:11.881886 4, 0xFFFF, sum = 0
8231 16:34:11.882593 5, 0xFFFF, sum = 0
8232 16:34:11.885446 6, 0xFFFF, sum = 0
8233 16:34:11.885842 7, 0xFFFF, sum = 0
8234 16:34:11.888334 8, 0xFFFF, sum = 0
8235 16:34:11.888739 9, 0xFFFF, sum = 0
8236 16:34:11.891593 10, 0xFFFF, sum = 0
8237 16:34:11.891987 11, 0xFFFF, sum = 0
8238 16:34:11.895147 12, 0x8F7F, sum = 0
8239 16:34:11.895619 13, 0x0, sum = 1
8240 16:34:11.899009 14, 0x0, sum = 2
8241 16:34:11.899656 15, 0x0, sum = 3
8242 16:34:11.901687 16, 0x0, sum = 4
8243 16:34:11.902080 best_step = 14
8244 16:34:11.902435
8245 16:34:11.902720 ==
8246 16:34:11.904980 Dram Type= 6, Freq= 0, CH_1, rank 0
8247 16:34:11.908251 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8248 16:34:11.911805 ==
8249 16:34:11.912192 RX Vref Scan: 1
8250 16:34:11.912665
8251 16:34:11.915024 Set Vref Range= 24 -> 127
8252 16:34:11.915411
8253 16:34:11.918294 RX Vref 24 -> 127, step: 1
8254 16:34:11.918683
8255 16:34:11.918985 RX Delay 3 -> 252, step: 4
8256 16:34:11.919266
8257 16:34:11.921878 Set Vref, RX VrefLevel [Byte0]: 24
8258 16:34:11.924587 [Byte1]: 24
8259 16:34:11.928408
8260 16:34:11.928916 Set Vref, RX VrefLevel [Byte0]: 25
8261 16:34:11.931992 [Byte1]: 25
8262 16:34:11.936347
8263 16:34:11.936856 Set Vref, RX VrefLevel [Byte0]: 26
8264 16:34:11.939716 [Byte1]: 26
8265 16:34:11.944108
8266 16:34:11.944496 Set Vref, RX VrefLevel [Byte0]: 27
8267 16:34:11.947199 [Byte1]: 27
8268 16:34:11.952152
8269 16:34:11.952600 Set Vref, RX VrefLevel [Byte0]: 28
8270 16:34:11.954877 [Byte1]: 28
8271 16:34:11.959738
8272 16:34:11.960124 Set Vref, RX VrefLevel [Byte0]: 29
8273 16:34:11.963046 [Byte1]: 29
8274 16:34:11.966830
8275 16:34:11.967219 Set Vref, RX VrefLevel [Byte0]: 30
8276 16:34:11.970333 [Byte1]: 30
8277 16:34:11.974921
8278 16:34:11.975480 Set Vref, RX VrefLevel [Byte0]: 31
8279 16:34:11.977658 [Byte1]: 31
8280 16:34:11.982780
8281 16:34:11.983245 Set Vref, RX VrefLevel [Byte0]: 32
8282 16:34:11.985607 [Byte1]: 32
8283 16:34:11.990350
8284 16:34:11.990908 Set Vref, RX VrefLevel [Byte0]: 33
8285 16:34:11.993003 [Byte1]: 33
8286 16:34:11.997850
8287 16:34:11.998364 Set Vref, RX VrefLevel [Byte0]: 34
8288 16:34:12.000845 [Byte1]: 34
8289 16:34:12.005303
8290 16:34:12.005765 Set Vref, RX VrefLevel [Byte0]: 35
8291 16:34:12.008472 [Byte1]: 35
8292 16:34:12.013160
8293 16:34:12.013709 Set Vref, RX VrefLevel [Byte0]: 36
8294 16:34:12.016012 [Byte1]: 36
8295 16:34:12.020528
8296 16:34:12.020909 Set Vref, RX VrefLevel [Byte0]: 37
8297 16:34:12.023839 [Byte1]: 37
8298 16:34:12.028194
8299 16:34:12.028681 Set Vref, RX VrefLevel [Byte0]: 38
8300 16:34:12.031619 [Byte1]: 38
8301 16:34:12.035826
8302 16:34:12.036206 Set Vref, RX VrefLevel [Byte0]: 39
8303 16:34:12.039071 [Byte1]: 39
8304 16:34:12.043389
8305 16:34:12.043770 Set Vref, RX VrefLevel [Byte0]: 40
8306 16:34:12.046663 [Byte1]: 40
8307 16:34:12.051163
8308 16:34:12.051619 Set Vref, RX VrefLevel [Byte0]: 41
8309 16:34:12.054524 [Byte1]: 41
8310 16:34:12.058668
8311 16:34:12.059045 Set Vref, RX VrefLevel [Byte0]: 42
8312 16:34:12.062141 [Byte1]: 42
8313 16:34:12.066750
8314 16:34:12.067208 Set Vref, RX VrefLevel [Byte0]: 43
8315 16:34:12.069903 [Byte1]: 43
8316 16:34:12.074054
8317 16:34:12.074532 Set Vref, RX VrefLevel [Byte0]: 44
8318 16:34:12.077431 [Byte1]: 44
8319 16:34:12.081594
8320 16:34:12.081970 Set Vref, RX VrefLevel [Byte0]: 45
8321 16:34:12.085046 [Byte1]: 45
8322 16:34:12.089494
8323 16:34:12.089944 Set Vref, RX VrefLevel [Byte0]: 46
8324 16:34:12.092924 [Byte1]: 46
8325 16:34:12.097231
8326 16:34:12.097692 Set Vref, RX VrefLevel [Byte0]: 47
8327 16:34:12.100464 [Byte1]: 47
8328 16:34:12.104719
8329 16:34:12.105096 Set Vref, RX VrefLevel [Byte0]: 48
8330 16:34:12.108089 [Byte1]: 48
8331 16:34:12.112590
8332 16:34:12.113003 Set Vref, RX VrefLevel [Byte0]: 49
8333 16:34:12.115402 [Byte1]: 49
8334 16:34:12.120300
8335 16:34:12.120758 Set Vref, RX VrefLevel [Byte0]: 50
8336 16:34:12.123194 [Byte1]: 50
8337 16:34:12.127468
8338 16:34:12.127849 Set Vref, RX VrefLevel [Byte0]: 51
8339 16:34:12.131101 [Byte1]: 51
8340 16:34:12.135619
8341 16:34:12.136000 Set Vref, RX VrefLevel [Byte0]: 52
8342 16:34:12.138974 [Byte1]: 52
8343 16:34:12.142808
8344 16:34:12.143377 Set Vref, RX VrefLevel [Byte0]: 53
8345 16:34:12.146073 [Byte1]: 53
8346 16:34:12.151158
8347 16:34:12.151618 Set Vref, RX VrefLevel [Byte0]: 54
8348 16:34:12.153796 [Byte1]: 54
8349 16:34:12.158695
8350 16:34:12.159326 Set Vref, RX VrefLevel [Byte0]: 55
8351 16:34:12.161611 [Byte1]: 55
8352 16:34:12.166116
8353 16:34:12.166823 Set Vref, RX VrefLevel [Byte0]: 56
8354 16:34:12.169297 [Byte1]: 56
8355 16:34:12.173605
8356 16:34:12.174109 Set Vref, RX VrefLevel [Byte0]: 57
8357 16:34:12.177166 [Byte1]: 57
8358 16:34:12.181345
8359 16:34:12.181847 Set Vref, RX VrefLevel [Byte0]: 58
8360 16:34:12.184501 [Byte1]: 58
8361 16:34:12.189280
8362 16:34:12.189767 Set Vref, RX VrefLevel [Byte0]: 59
8363 16:34:12.192011 [Byte1]: 59
8364 16:34:12.197240
8365 16:34:12.197694 Set Vref, RX VrefLevel [Byte0]: 60
8366 16:34:12.199773 [Byte1]: 60
8367 16:34:12.204485
8368 16:34:12.204952 Set Vref, RX VrefLevel [Byte0]: 61
8369 16:34:12.207467 [Byte1]: 61
8370 16:34:12.211458
8371 16:34:12.211883 Set Vref, RX VrefLevel [Byte0]: 62
8372 16:34:12.215306 [Byte1]: 62
8373 16:34:12.219674
8374 16:34:12.220089 Set Vref, RX VrefLevel [Byte0]: 63
8375 16:34:12.222834 [Byte1]: 63
8376 16:34:12.227224
8377 16:34:12.227614 Set Vref, RX VrefLevel [Byte0]: 64
8378 16:34:12.230240 [Byte1]: 64
8379 16:34:12.234799
8380 16:34:12.235306 Set Vref, RX VrefLevel [Byte0]: 65
8381 16:34:12.238356 [Byte1]: 65
8382 16:34:12.242194
8383 16:34:12.242632 Set Vref, RX VrefLevel [Byte0]: 66
8384 16:34:12.248973 [Byte1]: 66
8385 16:34:12.249466
8386 16:34:12.252811 Set Vref, RX VrefLevel [Byte0]: 67
8387 16:34:12.255499 [Byte1]: 67
8388 16:34:12.255890
8389 16:34:12.258815 Set Vref, RX VrefLevel [Byte0]: 68
8390 16:34:12.261955 [Byte1]: 68
8391 16:34:12.265623
8392 16:34:12.266059 Set Vref, RX VrefLevel [Byte0]: 69
8393 16:34:12.268654 [Byte1]: 69
8394 16:34:12.273382
8395 16:34:12.273846 Set Vref, RX VrefLevel [Byte0]: 70
8396 16:34:12.276233 [Byte1]: 70
8397 16:34:12.280925
8398 16:34:12.281393 Set Vref, RX VrefLevel [Byte0]: 71
8399 16:34:12.284029 [Byte1]: 71
8400 16:34:12.288125
8401 16:34:12.288512 Set Vref, RX VrefLevel [Byte0]: 72
8402 16:34:12.291957 [Byte1]: 72
8403 16:34:12.295944
8404 16:34:12.296336 Set Vref, RX VrefLevel [Byte0]: 73
8405 16:34:12.299025 [Byte1]: 73
8406 16:34:12.303468
8407 16:34:12.303852 Set Vref, RX VrefLevel [Byte0]: 74
8408 16:34:12.306968 [Byte1]: 74
8409 16:34:12.311315
8410 16:34:12.311772 Set Vref, RX VrefLevel [Byte0]: 75
8411 16:34:12.314671 [Byte1]: 75
8412 16:34:12.318918
8413 16:34:12.319371 Final RX Vref Byte 0 = 59 to rank0
8414 16:34:12.322387 Final RX Vref Byte 1 = 53 to rank0
8415 16:34:12.325819 Final RX Vref Byte 0 = 59 to rank1
8416 16:34:12.329410 Final RX Vref Byte 1 = 53 to rank1==
8417 16:34:12.332775 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 16:34:12.339295 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8419 16:34:12.339698 ==
8420 16:34:12.340003 DQS Delay:
8421 16:34:12.340287 DQS0 = 0, DQS1 = 0
8422 16:34:12.342117 DQM Delay:
8423 16:34:12.342658 DQM0 = 128, DQM1 = 122
8424 16:34:12.345644 DQ Delay:
8425 16:34:12.349015 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8426 16:34:12.352402 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =126
8427 16:34:12.355718 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8428 16:34:12.358643 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8429 16:34:12.359034
8430 16:34:12.359338
8431 16:34:12.359611
8432 16:34:12.362313 [DramC_TX_OE_Calibration] TA2
8433 16:34:12.365486 Original DQ_B0 (3 6) =30, OEN = 27
8434 16:34:12.369041 Original DQ_B1 (3 6) =30, OEN = 27
8435 16:34:12.372101 24, 0x0, End_B0=24 End_B1=24
8436 16:34:12.372592 25, 0x0, End_B0=25 End_B1=25
8437 16:34:12.375667 26, 0x0, End_B0=26 End_B1=26
8438 16:34:12.378508 27, 0x0, End_B0=27 End_B1=27
8439 16:34:12.382103 28, 0x0, End_B0=28 End_B1=28
8440 16:34:12.384979 29, 0x0, End_B0=29 End_B1=29
8441 16:34:12.385371 30, 0x0, End_B0=30 End_B1=30
8442 16:34:12.388306 31, 0x4141, End_B0=30 End_B1=30
8443 16:34:12.391733 Byte0 end_step=30 best_step=27
8444 16:34:12.394899 Byte1 end_step=30 best_step=27
8445 16:34:12.398666 Byte0 TX OE(2T, 0.5T) = (3, 3)
8446 16:34:12.401767 Byte1 TX OE(2T, 0.5T) = (3, 3)
8447 16:34:12.402159
8448 16:34:12.402511
8449 16:34:12.408761 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8450 16:34:12.411788 CH1 RK0: MR19=303, MR18=2929
8451 16:34:12.418163 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8452 16:34:12.418614
8453 16:34:12.421910 ----->DramcWriteLeveling(PI) begin...
8454 16:34:12.422696 ==
8455 16:34:12.424540 Dram Type= 6, Freq= 0, CH_1, rank 1
8456 16:34:12.428162 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8457 16:34:12.428736 ==
8458 16:34:12.431613 Write leveling (Byte 0): 21 => 21
8459 16:34:12.434671 Write leveling (Byte 1): 18 => 18
8460 16:34:12.438202 DramcWriteLeveling(PI) end<-----
8461 16:34:12.438733
8462 16:34:12.439041 ==
8463 16:34:12.441309 Dram Type= 6, Freq= 0, CH_1, rank 1
8464 16:34:12.444672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8465 16:34:12.445064 ==
8466 16:34:12.448195 [Gating] SW mode calibration
8467 16:34:12.455046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8468 16:34:12.461715 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8469 16:34:12.464479 0 12 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8470 16:34:12.471459 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 16:34:12.474508 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 16:34:12.478154 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 16:34:12.482067 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 16:34:12.488382 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 16:34:12.491431 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8476 16:34:12.494950 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8477 16:34:12.501499 0 13 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8478 16:34:12.505061 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 16:34:12.507909 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 16:34:12.514576 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 16:34:12.518071 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 16:34:12.521308 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 16:34:12.527932 0 13 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8484 16:34:12.530920 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8485 16:34:12.534404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 16:34:12.541560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 16:34:12.544129 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 16:34:12.547743 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 16:34:12.553915 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 16:34:12.557592 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8491 16:34:12.560812 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8492 16:34:12.567022 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8493 16:34:12.570966 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8494 16:34:12.573812 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 16:34:12.580924 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 16:34:12.584092 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 16:34:12.587367 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 16:34:12.594082 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 16:34:12.597679 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 16:34:12.600635 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 16:34:12.607414 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 16:34:12.610887 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 16:34:12.613900 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 16:34:12.620511 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 16:34:12.623606 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 16:34:12.627330 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8507 16:34:12.634301 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8508 16:34:12.634925 Total UI for P1: 0, mck2ui 16
8509 16:34:12.640642 best dqsien dly found for B0: ( 1, 0, 20)
8510 16:34:12.643861 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8511 16:34:12.646865 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 16:34:12.650475 Total UI for P1: 0, mck2ui 16
8513 16:34:12.653892 best dqsien dly found for B1: ( 1, 0, 28)
8514 16:34:12.656793 best DQS0 dly(MCK, UI, PI) = (1, 0, 20)
8515 16:34:12.660396 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8516 16:34:12.660785
8517 16:34:12.666592 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 20)
8518 16:34:12.669972 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8519 16:34:12.670617 [Gating] SW calibration Done
8520 16:34:12.673769 ==
8521 16:34:12.677185 Dram Type= 6, Freq= 0, CH_1, rank 1
8522 16:34:12.680524 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8523 16:34:12.680915 ==
8524 16:34:12.681212 RX Vref Scan: 0
8525 16:34:12.681488
8526 16:34:12.683306 RX Vref 0 -> 0, step: 1
8527 16:34:12.683716
8528 16:34:12.686980 RX Delay 0 -> 252, step: 8
8529 16:34:12.690310 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8530 16:34:12.693442 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8531 16:34:12.696400 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8532 16:34:12.703180 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8533 16:34:12.706670 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8534 16:34:12.709652 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8535 16:34:12.713159 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8536 16:34:12.716531 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8537 16:34:12.723098 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8538 16:34:12.726535 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8539 16:34:12.729827 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8540 16:34:12.732962 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8541 16:34:12.736254 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8542 16:34:12.742800 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8543 16:34:12.746788 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8544 16:34:12.749351 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8545 16:34:12.749734 ==
8546 16:34:12.752568 Dram Type= 6, Freq= 0, CH_1, rank 1
8547 16:34:12.759163 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8548 16:34:12.759550 ==
8549 16:34:12.759851 DQS Delay:
8550 16:34:12.760128 DQS0 = 0, DQS1 = 0
8551 16:34:12.762745 DQM Delay:
8552 16:34:12.763156 DQM0 = 130, DQM1 = 124
8553 16:34:12.766079 DQ Delay:
8554 16:34:12.769739 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =131
8555 16:34:12.772805 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8556 16:34:12.776527 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8557 16:34:12.779092 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8558 16:34:12.779580
8559 16:34:12.779967
8560 16:34:12.780254 ==
8561 16:34:12.782847 Dram Type= 6, Freq= 0, CH_1, rank 1
8562 16:34:12.785831 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8563 16:34:12.786254 ==
8564 16:34:12.789015
8565 16:34:12.789412
8566 16:34:12.789711 TX Vref Scan disable
8567 16:34:12.792752 == TX Byte 0 ==
8568 16:34:12.795876 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8569 16:34:12.799146 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8570 16:34:12.802762 == TX Byte 1 ==
8571 16:34:12.805636 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8572 16:34:12.809019 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8573 16:34:12.809428 ==
8574 16:34:12.812076 Dram Type= 6, Freq= 0, CH_1, rank 1
8575 16:34:12.818793 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8576 16:34:12.819263 ==
8577 16:34:12.833069
8578 16:34:12.836410 TX Vref early break, caculate TX vref
8579 16:34:12.839538 TX Vref=16, minBit 0, minWin=23, winSum=383
8580 16:34:12.842691 TX Vref=18, minBit 3, minWin=23, winSum=392
8581 16:34:12.846342 TX Vref=20, minBit 1, minWin=23, winSum=398
8582 16:34:12.849813 TX Vref=22, minBit 0, minWin=24, winSum=409
8583 16:34:12.853199 TX Vref=24, minBit 3, minWin=24, winSum=415
8584 16:34:12.859155 TX Vref=26, minBit 0, minWin=25, winSum=419
8585 16:34:12.862729 TX Vref=28, minBit 0, minWin=25, winSum=421
8586 16:34:12.865825 TX Vref=30, minBit 0, minWin=24, winSum=417
8587 16:34:12.868877 TX Vref=32, minBit 0, minWin=24, winSum=413
8588 16:34:12.872899 TX Vref=34, minBit 0, minWin=23, winSum=405
8589 16:34:12.876473 TX Vref=36, minBit 0, minWin=23, winSum=399
8590 16:34:12.882866 TX Vref=38, minBit 3, minWin=22, winSum=388
8591 16:34:12.885633 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8592 16:34:12.886020
8593 16:34:12.889108 Final TX Range 0 Vref 28
8594 16:34:12.889492
8595 16:34:12.889787 ==
8596 16:34:12.892299 Dram Type= 6, Freq= 0, CH_1, rank 1
8597 16:34:12.899078 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8598 16:34:12.899552 ==
8599 16:34:12.899855
8600 16:34:12.900127
8601 16:34:12.900388 TX Vref Scan disable
8602 16:34:12.905823 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8603 16:34:12.906317 == TX Byte 0 ==
8604 16:34:12.909193 u2DelayCellOfst[0]=18 cells (5 PI)
8605 16:34:12.912491 u2DelayCellOfst[1]=10 cells (3 PI)
8606 16:34:12.915675 u2DelayCellOfst[2]=0 cells (0 PI)
8607 16:34:12.919260 u2DelayCellOfst[3]=7 cells (2 PI)
8608 16:34:12.922456 u2DelayCellOfst[4]=7 cells (2 PI)
8609 16:34:12.926043 u2DelayCellOfst[5]=14 cells (4 PI)
8610 16:34:12.929096 u2DelayCellOfst[6]=18 cells (5 PI)
8611 16:34:12.932401 u2DelayCellOfst[7]=7 cells (2 PI)
8612 16:34:12.935800 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8613 16:34:12.939227 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8614 16:34:12.942004 == TX Byte 1 ==
8615 16:34:12.945217 u2DelayCellOfst[8]=0 cells (0 PI)
8616 16:34:12.948690 u2DelayCellOfst[9]=7 cells (2 PI)
8617 16:34:12.951976 u2DelayCellOfst[10]=10 cells (3 PI)
8618 16:34:12.955156 u2DelayCellOfst[11]=3 cells (1 PI)
8619 16:34:12.958816 u2DelayCellOfst[12]=14 cells (4 PI)
8620 16:34:12.961887 u2DelayCellOfst[13]=18 cells (5 PI)
8621 16:34:12.962313 u2DelayCellOfst[14]=18 cells (5 PI)
8622 16:34:12.965984 u2DelayCellOfst[15]=18 cells (5 PI)
8623 16:34:12.972361 Update DQ dly =970 (3 ,6, 10) DQ OEN =(3 ,3)
8624 16:34:12.975070 Update DQM dly =972 (3 ,6, 12) DQM OEN =(3 ,3)
8625 16:34:12.978495 DramC Write-DBI on
8626 16:34:12.978882 ==
8627 16:34:12.981617 Dram Type= 6, Freq= 0, CH_1, rank 1
8628 16:34:12.985660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8629 16:34:12.986131 ==
8630 16:34:12.986477
8631 16:34:12.986756
8632 16:34:12.988644 TX Vref Scan disable
8633 16:34:12.989110 == TX Byte 0 ==
8634 16:34:12.995171 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8635 16:34:12.995555 == TX Byte 1 ==
8636 16:34:12.998010 Update DQM dly =714 (2 ,6, 10) DQM OEN =(3 ,3)
8637 16:34:13.001856 DramC Write-DBI off
8638 16:34:13.002306
8639 16:34:13.002618 [DATLAT]
8640 16:34:13.005193 Freq=1600, CH1 RK1
8641 16:34:13.005529
8642 16:34:13.005806 DATLAT Default: 0xe
8643 16:34:13.008021 0, 0xFFFF, sum = 0
8644 16:34:13.008417 1, 0xFFFF, sum = 0
8645 16:34:13.011624 2, 0xFFFF, sum = 0
8646 16:34:13.012021 3, 0xFFFF, sum = 0
8647 16:34:13.014832 4, 0xFFFF, sum = 0
8648 16:34:13.018121 5, 0xFFFF, sum = 0
8649 16:34:13.018643 6, 0xFFFF, sum = 0
8650 16:34:13.021724 7, 0xFFFF, sum = 0
8651 16:34:13.022111 8, 0xFFFF, sum = 0
8652 16:34:13.024721 9, 0xFFFF, sum = 0
8653 16:34:13.025118 10, 0xFFFF, sum = 0
8654 16:34:13.028241 11, 0xFFFF, sum = 0
8655 16:34:13.028633 12, 0x8F7F, sum = 0
8656 16:34:13.031046 13, 0x0, sum = 1
8657 16:34:13.031321 14, 0x0, sum = 2
8658 16:34:13.034439 15, 0x0, sum = 3
8659 16:34:13.034715 16, 0x0, sum = 4
8660 16:34:13.037908 best_step = 14
8661 16:34:13.038114
8662 16:34:13.038297 ==
8663 16:34:13.040709 Dram Type= 6, Freq= 0, CH_1, rank 1
8664 16:34:13.044450 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8665 16:34:13.044622 ==
8666 16:34:13.044752 RX Vref Scan: 0
8667 16:34:13.047851
8668 16:34:13.047991 RX Vref 0 -> 0, step: 1
8669 16:34:13.048099
8670 16:34:13.050801 RX Delay 3 -> 252, step: 4
8671 16:34:13.054486 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8672 16:34:13.060924 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8673 16:34:13.064260 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8674 16:34:13.067444 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8675 16:34:13.071391 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8676 16:34:13.074632 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8677 16:34:13.081156 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8678 16:34:13.084398 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8679 16:34:13.087881 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8680 16:34:13.090950 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8681 16:34:13.094670 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8682 16:34:13.100903 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8683 16:34:13.104177 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8684 16:34:13.107367 iDelay=195, Bit 13, Center 130 (79 ~ 182) 104
8685 16:34:13.110630 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8686 16:34:13.117201 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8687 16:34:13.117590 ==
8688 16:34:13.120658 Dram Type= 6, Freq= 0, CH_1, rank 1
8689 16:34:13.123562 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8690 16:34:13.123946 ==
8691 16:34:13.124243 DQS Delay:
8692 16:34:13.127219 DQS0 = 0, DQS1 = 0
8693 16:34:13.127598 DQM Delay:
8694 16:34:13.130707 DQM0 = 127, DQM1 = 122
8695 16:34:13.131091 DQ Delay:
8696 16:34:13.133739 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8697 16:34:13.136800 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8698 16:34:13.140305 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8699 16:34:13.144080 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8700 16:34:13.144459
8701 16:34:13.144754
8702 16:34:13.147029
8703 16:34:13.147410 [DramC_TX_OE_Calibration] TA2
8704 16:34:13.150119 Original DQ_B0 (3 6) =30, OEN = 27
8705 16:34:13.153641 Original DQ_B1 (3 6) =30, OEN = 27
8706 16:34:13.156847 24, 0x0, End_B0=24 End_B1=24
8707 16:34:13.160281 25, 0x0, End_B0=25 End_B1=25
8708 16:34:13.163305 26, 0x0, End_B0=26 End_B1=26
8709 16:34:13.163692 27, 0x0, End_B0=27 End_B1=27
8710 16:34:13.166713 28, 0x0, End_B0=28 End_B1=28
8711 16:34:13.169933 29, 0x0, End_B0=29 End_B1=29
8712 16:34:13.173750 30, 0x0, End_B0=30 End_B1=30
8713 16:34:13.176679 31, 0x4141, End_B0=30 End_B1=30
8714 16:34:13.177152 Byte0 end_step=30 best_step=27
8715 16:34:13.179997 Byte1 end_step=30 best_step=27
8716 16:34:13.183153 Byte0 TX OE(2T, 0.5T) = (3, 3)
8717 16:34:13.186962 Byte1 TX OE(2T, 0.5T) = (3, 3)
8718 16:34:13.187560
8719 16:34:13.187871
8720 16:34:13.196606 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8721 16:34:13.197010 CH1 RK1: MR19=303, MR18=1D1D
8722 16:34:13.203209 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8723 16:34:13.207029 [RxdqsGatingPostProcess] freq 1600
8724 16:34:13.213437 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8725 16:34:13.216470 Pre-setting of DQS Precalculation
8726 16:34:13.219590 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8727 16:34:13.226088 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8728 16:34:13.235982 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8729 16:34:13.236371
8730 16:34:13.236682
8731 16:34:13.239543 [Calibration Summary] 3200 Mbps
8732 16:34:13.239991 CH 0, Rank 0
8733 16:34:13.242722 SW Impedance : PASS
8734 16:34:13.243111 DUTY Scan : NO K
8735 16:34:13.245993 ZQ Calibration : PASS
8736 16:34:13.246428 Jitter Meter : NO K
8737 16:34:13.249454 CBT Training : PASS
8738 16:34:13.252933 Write leveling : PASS
8739 16:34:13.253323 RX DQS gating : PASS
8740 16:34:13.256128 RX DQ/DQS(RDDQC) : PASS
8741 16:34:13.259143 TX DQ/DQS : PASS
8742 16:34:13.259529 RX DATLAT : PASS
8743 16:34:13.262710 RX DQ/DQS(Engine): PASS
8744 16:34:13.266147 TX OE : PASS
8745 16:34:13.266578 All Pass.
8746 16:34:13.266929
8747 16:34:13.267210 CH 0, Rank 1
8748 16:34:13.269116 SW Impedance : PASS
8749 16:34:13.272772 DUTY Scan : NO K
8750 16:34:13.273237 ZQ Calibration : PASS
8751 16:34:13.275790 Jitter Meter : NO K
8752 16:34:13.279001 CBT Training : PASS
8753 16:34:13.279515 Write leveling : PASS
8754 16:34:13.282333 RX DQS gating : PASS
8755 16:34:13.286129 RX DQ/DQS(RDDQC) : PASS
8756 16:34:13.286558 TX DQ/DQS : PASS
8757 16:34:13.289251 RX DATLAT : PASS
8758 16:34:13.292489 RX DQ/DQS(Engine): PASS
8759 16:34:13.293056 TX OE : PASS
8760 16:34:13.295547 All Pass.
8761 16:34:13.295933
8762 16:34:13.296232 CH 1, Rank 0
8763 16:34:13.299079 SW Impedance : PASS
8764 16:34:13.299513 DUTY Scan : NO K
8765 16:34:13.302046 ZQ Calibration : PASS
8766 16:34:13.305641 Jitter Meter : NO K
8767 16:34:13.306028 CBT Training : PASS
8768 16:34:13.308562 Write leveling : PASS
8769 16:34:13.308948 RX DQS gating : PASS
8770 16:34:13.312223 RX DQ/DQS(RDDQC) : PASS
8771 16:34:13.315594 TX DQ/DQS : PASS
8772 16:34:13.315982 RX DATLAT : PASS
8773 16:34:13.318581 RX DQ/DQS(Engine): PASS
8774 16:34:13.321859 TX OE : PASS
8775 16:34:13.322280 All Pass.
8776 16:34:13.322587
8777 16:34:13.322961 CH 1, Rank 1
8778 16:34:13.325431 SW Impedance : PASS
8779 16:34:13.328609 DUTY Scan : NO K
8780 16:34:13.328995 ZQ Calibration : PASS
8781 16:34:13.332142 Jitter Meter : NO K
8782 16:34:13.335219 CBT Training : PASS
8783 16:34:13.335625 Write leveling : PASS
8784 16:34:13.338788 RX DQS gating : PASS
8785 16:34:13.342107 RX DQ/DQS(RDDQC) : PASS
8786 16:34:13.342632 TX DQ/DQS : PASS
8787 16:34:13.345742 RX DATLAT : PASS
8788 16:34:13.348414 RX DQ/DQS(Engine): PASS
8789 16:34:13.348799 TX OE : PASS
8790 16:34:13.352048 All Pass.
8791 16:34:13.352515
8792 16:34:13.352810 DramC Write-DBI on
8793 16:34:13.355040 PER_BANK_REFRESH: Hybrid Mode
8794 16:34:13.355436 TX_TRACKING: ON
8795 16:34:13.365520 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8796 16:34:13.375193 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8797 16:34:13.381659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8798 16:34:13.384760 [FAST_K] Save calibration result to emmc
8799 16:34:13.388094 sync common calibartion params.
8800 16:34:13.388481 sync cbt_mode0:0, 1:0
8801 16:34:13.391788 dram_init: ddr_geometry: 0
8802 16:34:13.395164 dram_init: ddr_geometry: 0
8803 16:34:13.395551 dram_init: ddr_geometry: 0
8804 16:34:13.398135 0:dram_rank_size:80000000
8805 16:34:13.401671 1:dram_rank_size:80000000
8806 16:34:13.408268 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8807 16:34:13.408726 DFS_SHUFFLE_HW_MODE: ON
8808 16:34:13.411581 dramc_set_vcore_voltage set vcore to 725000
8809 16:34:13.414533 Read voltage for 1600, 0
8810 16:34:13.414934 Vio18 = 0
8811 16:34:13.418033 Vcore = 725000
8812 16:34:13.418466 Vdram = 0
8813 16:34:13.418769 Vddq = 0
8814 16:34:13.421700 Vmddr = 0
8815 16:34:13.422320 switch to 3200 Mbps bootup
8816 16:34:13.424414 [DramcRunTimeConfig]
8817 16:34:13.424799 PHYPLL
8818 16:34:13.428150 DPM_CONTROL_AFTERK: ON
8819 16:34:13.428627 PER_BANK_REFRESH: ON
8820 16:34:13.430989 REFRESH_OVERHEAD_REDUCTION: ON
8821 16:34:13.434903 CMD_PICG_NEW_MODE: OFF
8822 16:34:13.435291 XRTWTW_NEW_MODE: ON
8823 16:34:13.437569 XRTRTR_NEW_MODE: ON
8824 16:34:13.437955 TX_TRACKING: ON
8825 16:34:13.441028 RDSEL_TRACKING: OFF
8826 16:34:13.444025 DQS Precalculation for DVFS: ON
8827 16:34:13.444413 RX_TRACKING: OFF
8828 16:34:13.447688 HW_GATING DBG: ON
8829 16:34:13.448155 ZQCS_ENABLE_LP4: ON
8830 16:34:13.450791 RX_PICG_NEW_MODE: ON
8831 16:34:13.451230 TX_PICG_NEW_MODE: ON
8832 16:34:13.453894 ENABLE_RX_DCM_DPHY: ON
8833 16:34:13.457060 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8834 16:34:13.460476 DUMMY_READ_FOR_TRACKING: OFF
8835 16:34:13.464012 !!! SPM_CONTROL_AFTERK: OFF
8836 16:34:13.464580 !!! SPM could not control APHY
8837 16:34:13.467510 IMPEDANCE_TRACKING: ON
8838 16:34:13.467900 TEMP_SENSOR: ON
8839 16:34:13.470900 HW_SAVE_FOR_SR: OFF
8840 16:34:13.473971 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8841 16:34:13.477467 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8842 16:34:13.480791 Read ODT Tracking: ON
8843 16:34:13.481204 Refresh Rate DeBounce: ON
8844 16:34:13.484129 DFS_NO_QUEUE_FLUSH: ON
8845 16:34:13.487404 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8846 16:34:13.490550 ENABLE_DFS_RUNTIME_MRW: OFF
8847 16:34:13.490938 DDR_RESERVE_NEW_MODE: ON
8848 16:34:13.493791 MR_CBT_SWITCH_FREQ: ON
8849 16:34:13.496946 =========================
8850 16:34:13.514585 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8851 16:34:13.517516 dram_init: ddr_geometry: 0
8852 16:34:13.535685 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8853 16:34:13.539185 dram_init: dram init end (result: 0)
8854 16:34:13.545619 DRAM-K: Full calibration passed in 23398 msecs
8855 16:34:13.549026 MRC: failed to locate region type 0.
8856 16:34:13.549486 DRAM rank0 size:0x80000000,
8857 16:34:13.552847 DRAM rank1 size=0x80000000
8858 16:34:13.562243 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8859 16:34:13.568675 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8860 16:34:13.575366 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8861 16:34:13.582155 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8862 16:34:13.585093 DRAM rank0 size:0x80000000,
8863 16:34:13.588521 DRAM rank1 size=0x80000000
8864 16:34:13.588905 CBMEM:
8865 16:34:13.591771 IMD: root @ 0xfffff000 254 entries.
8866 16:34:13.594937 IMD: root @ 0xffffec00 62 entries.
8867 16:34:13.598305 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8868 16:34:13.602126 WARNING: RO_VPD is uninitialized or empty.
8869 16:34:13.608537 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8870 16:34:13.615717 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8871 16:34:13.627932 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8872 16:34:13.639943 BS: romstage times (exec / console): total (unknown) / 22941 ms
8873 16:34:13.640405
8874 16:34:13.640709
8875 16:34:13.649427 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8876 16:34:13.652843 ARM64: Exception handlers installed.
8877 16:34:13.656222 ARM64: Testing exception
8878 16:34:13.659274 ARM64: Done test exception
8879 16:34:13.659661 Enumerating buses...
8880 16:34:13.662832 Show all devs... Before device enumeration.
8881 16:34:13.665935 Root Device: enabled 1
8882 16:34:13.669336 CPU_CLUSTER: 0: enabled 1
8883 16:34:13.669734 CPU: 00: enabled 1
8884 16:34:13.672828 Compare with tree...
8885 16:34:13.673214 Root Device: enabled 1
8886 16:34:13.675844 CPU_CLUSTER: 0: enabled 1
8887 16:34:13.679491 CPU: 00: enabled 1
8888 16:34:13.679896 Root Device scanning...
8889 16:34:13.683009 scan_static_bus for Root Device
8890 16:34:13.686402 CPU_CLUSTER: 0 enabled
8891 16:34:13.689344 scan_static_bus for Root Device done
8892 16:34:13.692570 scan_bus: bus Root Device finished in 8 msecs
8893 16:34:13.692969 done
8894 16:34:13.699231 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8895 16:34:13.702589 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8896 16:34:13.709445 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8897 16:34:13.712659 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8898 16:34:13.716030 Allocating resources...
8899 16:34:13.716415 Reading resources...
8900 16:34:13.723038 Root Device read_resources bus 0 link: 0
8901 16:34:13.723527 DRAM rank0 size:0x80000000,
8902 16:34:13.726375 DRAM rank1 size=0x80000000
8903 16:34:13.729345 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8904 16:34:13.732551 CPU: 00 missing read_resources
8905 16:34:13.736466 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8906 16:34:13.742592 Root Device read_resources bus 0 link: 0 done
8907 16:34:13.742991 Done reading resources.
8908 16:34:13.749053 Show resources in subtree (Root Device)...After reading.
8909 16:34:13.753014 Root Device child on link 0 CPU_CLUSTER: 0
8910 16:34:13.756020 CPU_CLUSTER: 0 child on link 0 CPU: 00
8911 16:34:13.765922 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8912 16:34:13.766376 CPU: 00
8913 16:34:13.768994 Root Device assign_resources, bus 0 link: 0
8914 16:34:13.772716 CPU_CLUSTER: 0 missing set_resources
8915 16:34:13.775540 Root Device assign_resources, bus 0 link: 0 done
8916 16:34:13.778829 Done setting resources.
8917 16:34:13.785265 Show resources in subtree (Root Device)...After assigning values.
8918 16:34:13.788767 Root Device child on link 0 CPU_CLUSTER: 0
8919 16:34:13.792427 CPU_CLUSTER: 0 child on link 0 CPU: 00
8920 16:34:13.802350 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8921 16:34:13.802875 CPU: 00
8922 16:34:13.805189 Done allocating resources.
8923 16:34:13.808748 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8924 16:34:13.811713 Enabling resources...
8925 16:34:13.812104 done.
8926 16:34:13.818642 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8927 16:34:13.819037 Initializing devices...
8928 16:34:13.822110 Root Device init
8929 16:34:13.822669 init hardware done!
8930 16:34:13.825195 0x00000018: ctrlr->caps
8931 16:34:13.828447 52.000 MHz: ctrlr->f_max
8932 16:34:13.828847 0.400 MHz: ctrlr->f_min
8933 16:34:13.831634 0x40ff8080: ctrlr->voltages
8934 16:34:13.832274 sclk: 390625
8935 16:34:13.835237 Bus Width = 1
8936 16:34:13.835620 sclk: 390625
8937 16:34:13.838293 Bus Width = 1
8938 16:34:13.838680 Early init status = 3
8939 16:34:13.844847 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8940 16:34:13.848213 in-header: 03 fc 00 00 01 00 00 00
8941 16:34:13.848630 in-data: 00
8942 16:34:13.854822 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8943 16:34:13.858297 in-header: 03 fd 00 00 00 00 00 00
8944 16:34:13.861887 in-data:
8945 16:34:13.864792 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8946 16:34:13.868512 in-header: 03 fc 00 00 01 00 00 00
8947 16:34:13.871405 in-data: 00
8948 16:34:13.874665 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8949 16:34:13.879748 in-header: 03 fd 00 00 00 00 00 00
8950 16:34:13.882606 in-data:
8951 16:34:13.886141 [SSUSB] Setting up USB HOST controller...
8952 16:34:13.889050 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8953 16:34:13.892586 [SSUSB] phy power-on done.
8954 16:34:13.895571 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8955 16:34:13.902141 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8956 16:34:13.905576 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8957 16:34:13.912717 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8958 16:34:13.919060 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8959 16:34:13.925625 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8960 16:34:13.932699 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8961 16:34:13.939041 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
8962 16:34:13.942396 SPM: binary array size = 0x9dc
8963 16:34:13.945497 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8964 16:34:13.952161 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8965 16:34:13.959035 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8966 16:34:13.965517 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8967 16:34:13.968644 configure_display: Starting display init
8968 16:34:14.002331 anx7625_power_on_init: Init interface.
8969 16:34:14.005982 anx7625_disable_pd_protocol: Disabled PD feature.
8970 16:34:14.009408 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8971 16:34:14.036900 anx7625_start_dp_work: Secure OCM version=00
8972 16:34:14.040141 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8973 16:34:14.055023 sp_tx_get_edid_block: EDID Block = 1
8974 16:34:14.158075 Extracted contents:
8975 16:34:14.161129 header: 00 ff ff ff ff ff ff 00
8976 16:34:14.164208 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8977 16:34:14.167841 version: 01 04
8978 16:34:14.170874 basic params: 95 1f 11 78 0a
8979 16:34:14.174204 chroma info: 76 90 94 55 54 90 27 21 50 54
8980 16:34:14.177650 established: 00 00 00
8981 16:34:14.184172 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8982 16:34:14.187130 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8983 16:34:14.194320 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8984 16:34:14.200972 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8985 16:34:14.207883 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8986 16:34:14.210664 extensions: 00
8987 16:34:14.211062 checksum: fb
8988 16:34:14.211460
8989 16:34:14.214061 Manufacturer: IVO Model 57d Serial Number 0
8990 16:34:14.217157 Made week 0 of 2020
8991 16:34:14.217665 EDID version: 1.4
8992 16:34:14.221051 Digital display
8993 16:34:14.223630 6 bits per primary color channel
8994 16:34:14.224039 DisplayPort interface
8995 16:34:14.227203 Maximum image size: 31 cm x 17 cm
8996 16:34:14.230288 Gamma: 220%
8997 16:34:14.230688 Check DPMS levels
8998 16:34:14.233674 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8999 16:34:14.240189 First detailed timing is preferred timing
9000 16:34:14.240582 Established timings supported:
9001 16:34:14.244338 Standard timings supported:
9002 16:34:14.246953 Detailed timings
9003 16:34:14.250047 Hex of detail: 383680a07038204018303c0035ae10000019
9004 16:34:14.253581 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9005 16:34:14.260486 0780 0798 07c8 0820 hborder 0
9006 16:34:14.263867 0438 043b 0447 0458 vborder 0
9007 16:34:14.266709 -hsync -vsync
9008 16:34:14.267118 Did detailed timing
9009 16:34:14.273842 Hex of detail: 000000000000000000000000000000000000
9010 16:34:14.274263 Manufacturer-specified data, tag 0
9011 16:34:14.280152 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9012 16:34:14.283647 ASCII string: InfoVision
9013 16:34:14.287393 Hex of detail: 000000fe00523134304e574635205248200a
9014 16:34:14.289963 ASCII string: R140NWF5 RH
9015 16:34:14.290389 Checksum
9016 16:34:14.293591 Checksum: 0xfb (valid)
9017 16:34:14.297035 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9018 16:34:14.299859 DSI data_rate: 832800000 bps
9019 16:34:14.306502 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9020 16:34:14.310040 anx7625_parse_edid: pixelclock(138800).
9021 16:34:14.313067 hactive(1920), hsync(48), hfp(24), hbp(88)
9022 16:34:14.316712 vactive(1080), vsync(12), vfp(3), vbp(17)
9023 16:34:14.320575 anx7625_dsi_config: config dsi.
9024 16:34:14.326280 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9025 16:34:14.339892 anx7625_dsi_config: success to config DSI
9026 16:34:14.342837 anx7625_dp_start: MIPI phy setup OK.
9027 16:34:14.346506 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9028 16:34:14.349514 mtk_ddp_mode_set invalid vrefresh 60
9029 16:34:14.352588 main_disp_path_setup
9030 16:34:14.353010 ovl_layer_smi_id_en
9031 16:34:14.356126 ovl_layer_smi_id_en
9032 16:34:14.356609 ccorr_config
9033 16:34:14.357011 aal_config
9034 16:34:14.359205 gamma_config
9035 16:34:14.359602 postmask_config
9036 16:34:14.362767 dither_config
9037 16:34:14.365851 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9038 16:34:14.372857 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9039 16:34:14.376433 Root Device init finished in 551 msecs
9040 16:34:14.379491 CPU_CLUSTER: 0 init
9041 16:34:14.385986 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9042 16:34:14.392768 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9043 16:34:14.393260 APU_MBOX 0x190000b0 = 0x10001
9044 16:34:14.395769 APU_MBOX 0x190001b0 = 0x10001
9045 16:34:14.399014 APU_MBOX 0x190005b0 = 0x10001
9046 16:34:14.402726 APU_MBOX 0x190006b0 = 0x10001
9047 16:34:14.409335 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9048 16:34:14.418610 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9049 16:34:14.431315 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9050 16:34:14.437787 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9051 16:34:14.449783 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9052 16:34:14.458557 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9053 16:34:14.461897 CPU_CLUSTER: 0 init finished in 81 msecs
9054 16:34:14.464956 Devices initialized
9055 16:34:14.468730 Show all devs... After init.
9056 16:34:14.469132 Root Device: enabled 1
9057 16:34:14.471726 CPU_CLUSTER: 0: enabled 1
9058 16:34:14.475247 CPU: 00: enabled 1
9059 16:34:14.478601 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9060 16:34:14.481830 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9061 16:34:14.485102 ELOG: NV offset 0x57f000 size 0x1000
9062 16:34:14.491839 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9063 16:34:14.498656 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9064 16:34:14.501856 ELOG: Event(17) added with size 13 at 2024-06-17 16:34:14 UTC
9065 16:34:14.505547 out: cmd=0x121: 03 db 21 01 00 00 00 00
9066 16:34:14.508777 in-header: 03 36 00 00 2c 00 00 00
9067 16:34:14.522002 in-data: 0c 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9068 16:34:14.528188 ELOG: Event(A1) added with size 10 at 2024-06-17 16:34:14 UTC
9069 16:34:14.534861 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9070 16:34:14.541477 ELOG: Event(A0) added with size 9 at 2024-06-17 16:34:14 UTC
9071 16:34:14.544993 elog_add_boot_reason: Logged dev mode boot
9072 16:34:14.548143 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9073 16:34:14.551788 Finalize devices...
9074 16:34:14.552190 Devices finalized
9075 16:34:14.558250 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9076 16:34:14.561858 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9077 16:34:14.564956 in-header: 03 07 00 00 08 00 00 00
9078 16:34:14.568313 in-data: aa e4 47 04 13 02 00 00
9079 16:34:14.571223 Chrome EC: UHEPI supported
9080 16:34:14.577799 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9081 16:34:14.581146 in-header: 03 a9 00 00 08 00 00 00
9082 16:34:14.584698 in-data: 84 60 60 08 00 00 00 00
9083 16:34:14.588254 ELOG: Event(91) added with size 10 at 2024-06-17 16:34:14 UTC
9084 16:34:14.594670 Chrome EC: clear events_b mask to 0x0000000020004000
9085 16:34:14.601347 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9086 16:34:14.604970 in-header: 03 fd 00 00 00 00 00 00
9087 16:34:14.605393 in-data:
9088 16:34:14.611333 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9089 16:34:14.614680 Writing coreboot table at 0xffe64000
9090 16:34:14.618064 0. 000000000010a000-0000000000113fff: RAMSTAGE
9091 16:34:14.621619 1. 0000000040000000-00000000400fffff: RAM
9092 16:34:14.624638 2. 0000000040100000-000000004032afff: RAMSTAGE
9093 16:34:14.631809 3. 000000004032b000-00000000545fffff: RAM
9094 16:34:14.634653 4. 0000000054600000-000000005465ffff: BL31
9095 16:34:14.638201 5. 0000000054660000-00000000ffe63fff: RAM
9096 16:34:14.641381 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9097 16:34:14.647987 7. 0000000100000000-000000013fffffff: RAM
9098 16:34:14.648692 Passing 5 GPIOs to payload:
9099 16:34:14.654611 NAME | PORT | POLARITY | VALUE
9100 16:34:14.657602 EC in RW | 0x000000aa | low | undefined
9101 16:34:14.664440 EC interrupt | 0x00000005 | low | undefined
9102 16:34:14.667865 TPM interrupt | 0x000000ab | high | undefined
9103 16:34:14.671378 SD card detect | 0x00000011 | high | undefined
9104 16:34:14.677465 speaker enable | 0x00000093 | high | undefined
9105 16:34:14.681071 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9106 16:34:14.684592 in-header: 03 f8 00 00 02 00 00 00
9107 16:34:14.684801 in-data: 03 00
9108 16:34:14.687833 ADC[4]: Raw value=668958 ID=5
9109 16:34:14.690848 ADC[3]: Raw value=212549 ID=1
9110 16:34:14.691056 RAM Code: 0x51
9111 16:34:14.694149 ADC[6]: Raw value=74410 ID=0
9112 16:34:14.697917 ADC[5]: Raw value=211444 ID=1
9113 16:34:14.698289 SKU Code: 0x1
9114 16:34:14.704607 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fa8c
9115 16:34:14.707629 coreboot table: 964 bytes.
9116 16:34:14.710964 IMD ROOT 0. 0xfffff000 0x00001000
9117 16:34:14.714119 IMD SMALL 1. 0xffffe000 0x00001000
9118 16:34:14.718108 RO MCACHE 2. 0xffffc000 0x00001104
9119 16:34:14.721081 CONSOLE 3. 0xfff7c000 0x00080000
9120 16:34:14.724223 FMAP 4. 0xfff7b000 0x00000452
9121 16:34:14.727686 TIME STAMP 5. 0xfff7a000 0x00000910
9122 16:34:14.731290 VBOOT WORK 6. 0xfff66000 0x00014000
9123 16:34:14.734289 RAMOOPS 7. 0xffe66000 0x00100000
9124 16:34:14.737361 COREBOOT 8. 0xffe64000 0x00002000
9125 16:34:14.737847 IMD small region:
9126 16:34:14.740952 IMD ROOT 0. 0xffffec00 0x00000400
9127 16:34:14.744134 VPD 1. 0xffffeb80 0x0000006c
9128 16:34:14.747522 MMC STATUS 2. 0xffffeb60 0x00000004
9129 16:34:14.754140 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9130 16:34:14.760744 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9131 16:34:14.800952 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9132 16:34:14.804001 Checking segment from ROM address 0x40100000
9133 16:34:14.807426 Checking segment from ROM address 0x4010001c
9134 16:34:14.813825 Loading segment from ROM address 0x40100000
9135 16:34:14.814374 code (compression=0)
9136 16:34:14.824038 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9137 16:34:14.830637 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9138 16:34:14.831061 it's not compressed!
9139 16:34:14.837011 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9140 16:34:14.843428 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9141 16:34:14.860836 Loading segment from ROM address 0x4010001c
9142 16:34:14.861306 Entry Point 0x80000000
9143 16:34:14.864105 Loaded segments
9144 16:34:14.867460 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9145 16:34:14.874278 Jumping to boot code at 0x80000000(0xffe64000)
9146 16:34:14.880869 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9147 16:34:14.887740 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9148 16:34:14.895529 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9149 16:34:14.899063 Checking segment from ROM address 0x40100000
9150 16:34:14.902380 Checking segment from ROM address 0x4010001c
9151 16:34:14.909108 Loading segment from ROM address 0x40100000
9152 16:34:14.909667 code (compression=1)
9153 16:34:14.915911 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9154 16:34:14.924917 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9155 16:34:14.925396 using LZMA
9156 16:34:14.934057 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9157 16:34:14.940093 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9158 16:34:14.943531 Loading segment from ROM address 0x4010001c
9159 16:34:14.943936 Entry Point 0x54601000
9160 16:34:14.946770 Loaded segments
9161 16:34:14.950034 NOTICE: MT8192 bl31_setup
9162 16:34:14.957601 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9163 16:34:14.960914 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9164 16:34:14.964293 WARNING: region 0:
9165 16:34:14.967145 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9166 16:34:14.967552 WARNING: region 1:
9167 16:34:14.973848 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9168 16:34:14.977781 WARNING: region 2:
9169 16:34:14.980542 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9170 16:34:14.984074 WARNING: region 3:
9171 16:34:14.987586 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9172 16:34:14.990731 WARNING: region 4:
9173 16:34:14.997128 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9174 16:34:14.997587 WARNING: region 5:
9175 16:34:15.001021 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9176 16:34:15.004038 WARNING: region 6:
9177 16:34:15.007244 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9178 16:34:15.010768 WARNING: region 7:
9179 16:34:15.014078 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 16:34:15.020424 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9181 16:34:15.024011 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9182 16:34:15.026984 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9183 16:34:15.033677 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9184 16:34:15.037348 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9185 16:34:15.040243 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9186 16:34:15.046934 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9187 16:34:15.050294 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9188 16:34:15.057259 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9189 16:34:15.060381 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9190 16:34:15.063734 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9191 16:34:15.070870 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9192 16:34:15.073929 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9193 16:34:15.076834 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9194 16:34:15.083914 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9195 16:34:15.087103 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9196 16:34:15.093434 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9197 16:34:15.096907 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9198 16:34:15.099934 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9199 16:34:15.106603 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9200 16:34:15.110632 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9201 16:34:15.116852 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9202 16:34:15.120597 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9203 16:34:15.123942 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9204 16:34:15.130008 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9205 16:34:15.133657 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9206 16:34:15.139979 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9207 16:34:15.143474 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9208 16:34:15.146986 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9209 16:34:15.153197 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9210 16:34:15.156715 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9211 16:34:15.163439 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9212 16:34:15.166531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9213 16:34:15.169515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9214 16:34:15.172870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9215 16:34:15.180345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9216 16:34:15.182922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9217 16:34:15.186371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9218 16:34:15.190115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9219 16:34:15.196890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9220 16:34:15.199852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9221 16:34:15.202953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9222 16:34:15.206523 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9223 16:34:15.213157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9224 16:34:15.216048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9225 16:34:15.219661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9226 16:34:15.223267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9227 16:34:15.229376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9228 16:34:15.232871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9229 16:34:15.239392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9230 16:34:15.242894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9231 16:34:15.245955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9232 16:34:15.252436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9233 16:34:15.255932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9234 16:34:15.262651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9235 16:34:15.266252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9236 16:34:15.272822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9237 16:34:15.276377 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9238 16:34:15.279479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9239 16:34:15.285997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9240 16:34:15.289575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9241 16:34:15.296248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9242 16:34:15.299169 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9243 16:34:15.306099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9244 16:34:15.309564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9245 16:34:15.316178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9246 16:34:15.318821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9247 16:34:15.322485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9248 16:34:15.329463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9249 16:34:15.332411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9250 16:34:15.338905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9251 16:34:15.342345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9252 16:34:15.348910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9253 16:34:15.352466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9254 16:34:15.355322 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9255 16:34:15.362533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9256 16:34:15.365329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9257 16:34:15.372171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9258 16:34:15.375670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9259 16:34:15.382102 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9260 16:34:15.385411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9261 16:34:15.391845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9262 16:34:15.395267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9263 16:34:15.398857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9264 16:34:15.405273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9265 16:34:15.408758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9266 16:34:15.415538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9267 16:34:15.418547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9268 16:34:15.425056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9269 16:34:15.428399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9270 16:34:15.431984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9271 16:34:15.438540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9272 16:34:15.441934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9273 16:34:15.448613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9274 16:34:15.451715 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9275 16:34:15.458626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9276 16:34:15.461651 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9277 16:34:15.465216 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9278 16:34:15.468761 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9279 16:34:15.474386 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9280 16:34:15.478222 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9281 16:34:15.481392 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9282 16:34:15.487861 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9283 16:34:15.491491 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9284 16:34:15.498363 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9285 16:34:15.501171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9286 16:34:15.504763 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9287 16:34:15.511219 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9288 16:34:15.514305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9289 16:34:15.521348 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9290 16:34:15.524039 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9291 16:34:15.528145 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9292 16:34:15.534722 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9293 16:34:15.537747 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9294 16:34:15.544175 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9295 16:34:15.547704 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9296 16:34:15.551069 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9297 16:34:15.557618 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9298 16:34:15.560672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9299 16:34:15.564247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9300 16:34:15.567329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9301 16:34:15.573893 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9302 16:34:15.577399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9303 16:34:15.580740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9304 16:34:15.587110 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9305 16:34:15.590673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9306 16:34:15.593592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9307 16:34:15.600644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9308 16:34:15.604008 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9309 16:34:15.610641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9310 16:34:15.613855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9311 16:34:15.617374 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9312 16:34:15.623859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9313 16:34:15.626862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9314 16:34:15.633684 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9315 16:34:15.636984 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9316 16:34:15.640157 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9317 16:34:15.646378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9318 16:34:15.649965 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9319 16:34:15.656700 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9320 16:34:15.659737 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9321 16:34:15.663106 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9322 16:34:15.669817 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9323 16:34:15.673338 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9324 16:34:15.676302 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9325 16:34:15.683306 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9326 16:34:15.686135 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9327 16:34:15.693087 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9328 16:34:15.695998 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9329 16:34:15.702716 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9330 16:34:15.706353 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9331 16:34:15.709250 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9332 16:34:15.716062 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9333 16:34:15.719326 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9334 16:34:15.725787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9335 16:34:15.729471 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9336 16:34:15.732295 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9337 16:34:15.739316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9338 16:34:15.742766 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9339 16:34:15.745666 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9340 16:34:15.752414 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9341 16:34:15.755817 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9342 16:34:15.762650 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9343 16:34:15.765621 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9344 16:34:15.769304 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9345 16:34:15.775680 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9346 16:34:15.779253 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9347 16:34:15.785570 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9348 16:34:15.788618 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9349 16:34:15.792089 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9350 16:34:15.798863 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9351 16:34:15.801996 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9352 16:34:15.808663 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9353 16:34:15.812187 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9354 16:34:15.815253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9355 16:34:15.821943 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9356 16:34:15.824976 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9357 16:34:15.831666 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9358 16:34:15.835214 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9359 16:34:15.838714 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9360 16:34:15.844626 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9361 16:34:15.848513 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9362 16:34:15.854537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9363 16:34:15.858132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9364 16:34:15.861816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9365 16:34:15.868139 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9366 16:34:15.871093 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9367 16:34:15.878398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9368 16:34:15.881490 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9369 16:34:15.885060 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9370 16:34:15.891308 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9371 16:34:15.894652 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9372 16:34:15.901316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9373 16:34:15.904755 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9374 16:34:15.911244 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9375 16:34:15.914906 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9376 16:34:15.917819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9377 16:34:15.924278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9378 16:34:15.927759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9379 16:34:15.934153 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9380 16:34:15.937552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9381 16:34:15.941583 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9382 16:34:15.947671 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9383 16:34:15.951139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9384 16:34:15.957391 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9385 16:34:15.960687 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9386 16:34:15.967606 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9387 16:34:15.970923 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9388 16:34:15.974382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9389 16:34:15.980689 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9390 16:34:15.984287 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9391 16:34:15.990916 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9392 16:34:15.993823 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9393 16:34:16.001022 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9394 16:34:16.003886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9395 16:34:16.007222 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9396 16:34:16.014474 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9397 16:34:16.017438 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9398 16:34:16.024007 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9399 16:34:16.027118 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9400 16:34:16.030468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9401 16:34:16.037627 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9402 16:34:16.040758 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9403 16:34:16.047492 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9404 16:34:16.050545 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9405 16:34:16.054142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9406 16:34:16.060932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9407 16:34:16.064114 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9408 16:34:16.070800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9409 16:34:16.074004 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9410 16:34:16.077611 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9411 16:34:16.080968 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9412 16:34:16.087213 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9413 16:34:16.090758 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9414 16:34:16.094667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9415 16:34:16.100737 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9416 16:34:16.103992 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9417 16:34:16.107449 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9418 16:34:16.114140 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9419 16:34:16.117553 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9420 16:34:16.120491 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9421 16:34:16.127200 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9422 16:34:16.130502 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9423 16:34:16.133883 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9424 16:34:16.140453 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9425 16:34:16.143943 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9426 16:34:16.150519 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9427 16:34:16.153728 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9428 16:34:16.157596 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9429 16:34:16.163882 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9430 16:34:16.167459 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9431 16:34:16.173468 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9432 16:34:16.177090 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9433 16:34:16.180309 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9434 16:34:16.186748 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9435 16:34:16.189799 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9436 16:34:16.193449 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9437 16:34:16.200069 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9438 16:34:16.203205 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9439 16:34:16.206392 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9440 16:34:16.213083 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9441 16:34:16.216537 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9442 16:34:16.222934 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9443 16:34:16.226521 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9444 16:34:16.230089 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9445 16:34:16.236771 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9446 16:34:16.239560 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9447 16:34:16.243123 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9448 16:34:16.249824 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9449 16:34:16.253476 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9450 16:34:16.256599 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9451 16:34:16.259717 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9452 16:34:16.266504 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9453 16:34:16.269793 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9454 16:34:16.273264 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9455 16:34:16.276326 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9456 16:34:16.282611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9457 16:34:16.286040 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9458 16:34:16.289998 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9459 16:34:16.292675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9460 16:34:16.299105 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9461 16:34:16.302715 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9462 16:34:16.306328 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9463 16:34:16.312975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9464 16:34:16.316669 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9465 16:34:16.322458 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9466 16:34:16.326125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9467 16:34:16.332958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9468 16:34:16.335718 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9469 16:34:16.339355 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9470 16:34:16.345801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9471 16:34:16.349293 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9472 16:34:16.352898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9473 16:34:16.359075 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9474 16:34:16.362743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9475 16:34:16.369469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9476 16:34:16.372926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9477 16:34:16.375716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9478 16:34:16.382616 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9479 16:34:16.386047 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9480 16:34:16.392467 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9481 16:34:16.395537 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9482 16:34:16.402636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9483 16:34:16.406276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9484 16:34:16.408961 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9485 16:34:16.415463 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9486 16:34:16.418777 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9487 16:34:16.425863 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9488 16:34:16.428799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9489 16:34:16.432542 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9490 16:34:16.438692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9491 16:34:16.442069 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9492 16:34:16.449102 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9493 16:34:16.452041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9494 16:34:16.455632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9495 16:34:16.462274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9496 16:34:16.465657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9497 16:34:16.472047 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9498 16:34:16.475343 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9499 16:34:16.481755 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9500 16:34:16.485317 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9501 16:34:16.488606 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9502 16:34:16.495219 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9503 16:34:16.499005 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9504 16:34:16.505122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9505 16:34:16.508567 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9506 16:34:16.511610 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9507 16:34:16.518506 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9508 16:34:16.521933 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9509 16:34:16.528635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9510 16:34:16.531644 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9511 16:34:16.535200 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9512 16:34:16.541561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9513 16:34:16.544810 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9514 16:34:16.551787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9515 16:34:16.555077 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9516 16:34:16.558269 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9517 16:34:16.565397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9518 16:34:16.568268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9519 16:34:16.574986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9520 16:34:16.578451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9521 16:34:16.581506 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9522 16:34:16.588078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9523 16:34:16.591783 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9524 16:34:16.598022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9525 16:34:16.601562 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9526 16:34:16.604741 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9527 16:34:16.611321 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9528 16:34:16.614593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9529 16:34:16.621422 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9530 16:34:16.625194 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9531 16:34:16.631192 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9532 16:34:16.634693 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9533 16:34:16.637781 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9534 16:34:16.644333 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9535 16:34:16.647828 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9536 16:34:16.654556 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9537 16:34:16.657886 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9538 16:34:16.664626 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9539 16:34:16.667796 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9540 16:34:16.674160 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9541 16:34:16.677812 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9542 16:34:16.681245 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9543 16:34:16.687886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9544 16:34:16.690889 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9545 16:34:16.697552 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9546 16:34:16.700951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9547 16:34:16.707321 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9548 16:34:16.710788 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9549 16:34:16.714407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9550 16:34:16.720552 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9551 16:34:16.723917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9552 16:34:16.731207 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9553 16:34:16.734171 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9554 16:34:16.740882 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9555 16:34:16.743976 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9556 16:34:16.747356 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9557 16:34:16.754060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9558 16:34:16.757461 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9559 16:34:16.764255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9560 16:34:16.767395 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9561 16:34:16.774394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9562 16:34:16.777261 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9563 16:34:16.780411 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9564 16:34:16.787449 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9565 16:34:16.790368 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9566 16:34:16.797627 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9567 16:34:16.800644 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9568 16:34:16.807162 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9569 16:34:16.810606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9570 16:34:16.816801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9571 16:34:16.819975 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9572 16:34:16.823455 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9573 16:34:16.829858 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9574 16:34:16.833377 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9575 16:34:16.839906 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9576 16:34:16.843166 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9577 16:34:16.850132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9578 16:34:16.853424 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9579 16:34:16.860301 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9580 16:34:16.863229 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9581 16:34:16.866590 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9582 16:34:16.873194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9583 16:34:16.876425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9584 16:34:16.883422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9585 16:34:16.886410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9586 16:34:16.893267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9587 16:34:16.896444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9588 16:34:16.899893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9589 16:34:16.906642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9590 16:34:16.909693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9591 16:34:16.915961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9592 16:34:16.919539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9593 16:34:16.926182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9594 16:34:16.929724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9595 16:34:16.935811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9596 16:34:16.939099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9597 16:34:16.945746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9598 16:34:16.949685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9599 16:34:16.955963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9600 16:34:16.959481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9601 16:34:16.965555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9602 16:34:16.969092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9603 16:34:16.975303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9604 16:34:16.979199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9605 16:34:16.985947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9606 16:34:16.989127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9607 16:34:16.995325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9608 16:34:16.998940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9609 16:34:17.005970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9610 16:34:17.008756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9611 16:34:17.015232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9612 16:34:17.018674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9613 16:34:17.025559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9614 16:34:17.028612 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9615 16:34:17.032756 INFO: [APUAPC] vio 0
9616 16:34:17.035673 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9617 16:34:17.042231 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9618 16:34:17.045395 INFO: [APUAPC] D0_APC_0: 0x400510
9619 16:34:17.045593 INFO: [APUAPC] D0_APC_1: 0x0
9620 16:34:17.048945 INFO: [APUAPC] D0_APC_2: 0x1540
9621 16:34:17.051814 INFO: [APUAPC] D0_APC_3: 0x0
9622 16:34:17.055007 INFO: [APUAPC] D1_APC_0: 0xffffffff
9623 16:34:17.058777 INFO: [APUAPC] D1_APC_1: 0xffffffff
9624 16:34:17.061708 INFO: [APUAPC] D1_APC_2: 0x3fffff
9625 16:34:17.065501 INFO: [APUAPC] D1_APC_3: 0x0
9626 16:34:17.068805 INFO: [APUAPC] D2_APC_0: 0xffffffff
9627 16:34:17.072088 INFO: [APUAPC] D2_APC_1: 0xffffffff
9628 16:34:17.075259 INFO: [APUAPC] D2_APC_2: 0x3fffff
9629 16:34:17.078662 INFO: [APUAPC] D2_APC_3: 0x0
9630 16:34:17.081856 INFO: [APUAPC] D3_APC_0: 0xffffffff
9631 16:34:17.085236 INFO: [APUAPC] D3_APC_1: 0xffffffff
9632 16:34:17.088283 INFO: [APUAPC] D3_APC_2: 0x3fffff
9633 16:34:17.091733 INFO: [APUAPC] D3_APC_3: 0x0
9634 16:34:17.095475 INFO: [APUAPC] D4_APC_0: 0xffffffff
9635 16:34:17.098261 INFO: [APUAPC] D4_APC_1: 0xffffffff
9636 16:34:17.101681 INFO: [APUAPC] D4_APC_2: 0x3fffff
9637 16:34:17.105182 INFO: [APUAPC] D4_APC_3: 0x0
9638 16:34:17.108814 INFO: [APUAPC] D5_APC_0: 0xffffffff
9639 16:34:17.111550 INFO: [APUAPC] D5_APC_1: 0xffffffff
9640 16:34:17.114827 INFO: [APUAPC] D5_APC_2: 0x3fffff
9641 16:34:17.118400 INFO: [APUAPC] D5_APC_3: 0x0
9642 16:34:17.122021 INFO: [APUAPC] D6_APC_0: 0xffffffff
9643 16:34:17.125394 INFO: [APUAPC] D6_APC_1: 0xffffffff
9644 16:34:17.128425 INFO: [APUAPC] D6_APC_2: 0x3fffff
9645 16:34:17.131887 INFO: [APUAPC] D6_APC_3: 0x0
9646 16:34:17.134873 INFO: [APUAPC] D7_APC_0: 0xffffffff
9647 16:34:17.138517 INFO: [APUAPC] D7_APC_1: 0xffffffff
9648 16:34:17.141600 INFO: [APUAPC] D7_APC_2: 0x3fffff
9649 16:34:17.145096 INFO: [APUAPC] D7_APC_3: 0x0
9650 16:34:17.148694 INFO: [APUAPC] D8_APC_0: 0xffffffff
9651 16:34:17.151868 INFO: [APUAPC] D8_APC_1: 0xffffffff
9652 16:34:17.155163 INFO: [APUAPC] D8_APC_2: 0x3fffff
9653 16:34:17.158251 INFO: [APUAPC] D8_APC_3: 0x0
9654 16:34:17.161880 INFO: [APUAPC] D9_APC_0: 0xffffffff
9655 16:34:17.165112 INFO: [APUAPC] D9_APC_1: 0xffffffff
9656 16:34:17.168526 INFO: [APUAPC] D9_APC_2: 0x3fffff
9657 16:34:17.171657 INFO: [APUAPC] D9_APC_3: 0x0
9658 16:34:17.175123 INFO: [APUAPC] D10_APC_0: 0xffffffff
9659 16:34:17.178195 INFO: [APUAPC] D10_APC_1: 0xffffffff
9660 16:34:17.181777 INFO: [APUAPC] D10_APC_2: 0x3fffff
9661 16:34:17.185135 INFO: [APUAPC] D10_APC_3: 0x0
9662 16:34:17.188103 INFO: [APUAPC] D11_APC_0: 0xffffffff
9663 16:34:17.191578 INFO: [APUAPC] D11_APC_1: 0xffffffff
9664 16:34:17.194835 INFO: [APUAPC] D11_APC_2: 0x3fffff
9665 16:34:17.198289 INFO: [APUAPC] D11_APC_3: 0x0
9666 16:34:17.201543 INFO: [APUAPC] D12_APC_0: 0xffffffff
9667 16:34:17.204626 INFO: [APUAPC] D12_APC_1: 0xffffffff
9668 16:34:17.208523 INFO: [APUAPC] D12_APC_2: 0x3fffff
9669 16:34:17.211677 INFO: [APUAPC] D12_APC_3: 0x0
9670 16:34:17.214559 INFO: [APUAPC] D13_APC_0: 0xffffffff
9671 16:34:17.218011 INFO: [APUAPC] D13_APC_1: 0xffffffff
9672 16:34:17.220958 INFO: [APUAPC] D13_APC_2: 0x3fffff
9673 16:34:17.224571 INFO: [APUAPC] D13_APC_3: 0x0
9674 16:34:17.228411 INFO: [APUAPC] D14_APC_0: 0xffffffff
9675 16:34:17.231336 INFO: [APUAPC] D14_APC_1: 0xffffffff
9676 16:34:17.234722 INFO: [APUAPC] D14_APC_2: 0x3fffff
9677 16:34:17.237746 INFO: [APUAPC] D14_APC_3: 0x0
9678 16:34:17.241693 INFO: [APUAPC] D15_APC_0: 0xffffffff
9679 16:34:17.245284 INFO: [APUAPC] D15_APC_1: 0xffffffff
9680 16:34:17.248265 INFO: [APUAPC] D15_APC_2: 0x3fffff
9681 16:34:17.251466 INFO: [APUAPC] D15_APC_3: 0x0
9682 16:34:17.254707 INFO: [APUAPC] APC_CON: 0x4
9683 16:34:17.255228 INFO: [NOCDAPC] D0_APC_0: 0x0
9684 16:34:17.258243 INFO: [NOCDAPC] D0_APC_1: 0x0
9685 16:34:17.260932 INFO: [NOCDAPC] D1_APC_0: 0x0
9686 16:34:17.264694 INFO: [NOCDAPC] D1_APC_1: 0xfff
9687 16:34:17.268023 INFO: [NOCDAPC] D2_APC_0: 0x0
9688 16:34:17.271619 INFO: [NOCDAPC] D2_APC_1: 0xfff
9689 16:34:17.274526 INFO: [NOCDAPC] D3_APC_0: 0x0
9690 16:34:17.277636 INFO: [NOCDAPC] D3_APC_1: 0xfff
9691 16:34:17.281215 INFO: [NOCDAPC] D4_APC_0: 0x0
9692 16:34:17.284562 INFO: [NOCDAPC] D4_APC_1: 0xfff
9693 16:34:17.285026 INFO: [NOCDAPC] D5_APC_0: 0x0
9694 16:34:17.287994 INFO: [NOCDAPC] D5_APC_1: 0xfff
9695 16:34:17.290921 INFO: [NOCDAPC] D6_APC_0: 0x0
9696 16:34:17.294632 INFO: [NOCDAPC] D6_APC_1: 0xfff
9697 16:34:17.297717 INFO: [NOCDAPC] D7_APC_0: 0x0
9698 16:34:17.301254 INFO: [NOCDAPC] D7_APC_1: 0xfff
9699 16:34:17.304399 INFO: [NOCDAPC] D8_APC_0: 0x0
9700 16:34:17.307290 INFO: [NOCDAPC] D8_APC_1: 0xfff
9701 16:34:17.311161 INFO: [NOCDAPC] D9_APC_0: 0x0
9702 16:34:17.314430 INFO: [NOCDAPC] D9_APC_1: 0xfff
9703 16:34:17.317549 INFO: [NOCDAPC] D10_APC_0: 0x0
9704 16:34:17.320804 INFO: [NOCDAPC] D10_APC_1: 0xfff
9705 16:34:17.321202 INFO: [NOCDAPC] D11_APC_0: 0x0
9706 16:34:17.324345 INFO: [NOCDAPC] D11_APC_1: 0xfff
9707 16:34:17.327624 INFO: [NOCDAPC] D12_APC_0: 0x0
9708 16:34:17.330923 INFO: [NOCDAPC] D12_APC_1: 0xfff
9709 16:34:17.334470 INFO: [NOCDAPC] D13_APC_0: 0x0
9710 16:34:17.337365 INFO: [NOCDAPC] D13_APC_1: 0xfff
9711 16:34:17.341000 INFO: [NOCDAPC] D14_APC_0: 0x0
9712 16:34:17.344141 INFO: [NOCDAPC] D14_APC_1: 0xfff
9713 16:34:17.347458 INFO: [NOCDAPC] D15_APC_0: 0x0
9714 16:34:17.351247 INFO: [NOCDAPC] D15_APC_1: 0xfff
9715 16:34:17.354104 INFO: [NOCDAPC] APC_CON: 0x4
9716 16:34:17.358022 INFO: [APUAPC] set_apusys_apc done
9717 16:34:17.360767 INFO: [DEVAPC] devapc_init done
9718 16:34:17.364623 INFO: GICv3 without legacy support detected.
9719 16:34:17.367446 INFO: ARM GICv3 driver initialized in EL3
9720 16:34:17.370844 INFO: Maximum SPI INTID supported: 639
9721 16:34:17.374136 INFO: BL31: Initializing runtime services
9722 16:34:17.380673 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9723 16:34:17.384096 INFO: SPM: enable CPC mode
9724 16:34:17.390697 INFO: mcdi ready for mcusys-off-idle and system suspend
9725 16:34:17.394149 INFO: BL31: Preparing for EL3 exit to normal world
9726 16:34:17.397230 INFO: Entry point address = 0x80000000
9727 16:34:17.400869 INFO: SPSR = 0x8
9728 16:34:17.405366
9729 16:34:17.405749
9730 16:34:17.406051
9731 16:34:17.408900 Starting depthcharge on Spherion...
9732 16:34:17.409289
9733 16:34:17.409588 Wipe memory regions:
9734 16:34:17.409866
9735 16:34:17.411974 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9736 16:34:17.412427 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9737 16:34:17.412806 Setting prompt string to ['asurada:']
9738 16:34:17.413163 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9739 16:34:17.413757 [0x00000040000000, 0x00000054600000)
9740 16:34:17.534324
9741 16:34:17.534786 [0x00000054660000, 0x00000080000000)
9742 16:34:17.795049
9743 16:34:17.795513 [0x000000821a7280, 0x000000ffe64000)
9744 16:34:18.540091
9745 16:34:18.540659 [0x00000100000000, 0x00000140000000)
9746 16:34:18.921046
9747 16:34:18.924452 Initializing XHCI USB controller at 0x11200000.
9748 16:34:19.962512
9749 16:34:19.965511 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9750 16:34:19.965929
9751 16:34:19.966273
9752 16:34:19.966973 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9754 16:34:20.068156 asurada: tftpboot 192.168.201.1 14396148/tftp-deploy-4nudwhtf/kernel/image.itb 14396148/tftp-deploy-4nudwhtf/kernel/cmdline
9755 16:34:20.068788 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9756 16:34:20.069208 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
9757 16:34:20.073639 tftpboot 192.168.201.1 14396148/tftp-deploy-4nudwhtf/kernel/image.itp-deploy-4nudwhtf/kernel/cmdline
9758 16:34:20.074036
9759 16:34:20.074393 Waiting for link
9760 16:34:20.231735
9761 16:34:20.232204 R8152: Initializing
9762 16:34:20.232506
9763 16:34:20.234915 Version 9 (ocp_data = 6010)
9764 16:34:20.235302
9765 16:34:20.238492 R8152: Done initializing
9766 16:34:20.238929
9767 16:34:20.239231 Adding net device
9768 16:34:22.179910
9769 16:34:22.180041 done.
9770 16:34:22.180116
9771 16:34:22.180171 MAC: 00:e0:4c:68:03:bd
9772 16:34:22.180223
9773 16:34:22.183224 Sending DHCP discover... done.
9774 16:34:22.183305
9775 16:34:22.186795 Waiting for reply... done.
9776 16:34:22.186872
9777 16:34:22.189955 Sending DHCP request... done.
9778 16:34:22.190031
9779 16:34:22.190089 Waiting for reply... done.
9780 16:34:22.193301
9781 16:34:22.193375 My ip is 192.168.201.16
9782 16:34:22.193434
9783 16:34:22.196808 The DHCP server ip is 192.168.201.1
9784 16:34:22.196883
9785 16:34:22.199862 TFTP server IP predefined by user: 192.168.201.1
9786 16:34:22.199938
9787 16:34:22.206250 Bootfile predefined by user: 14396148/tftp-deploy-4nudwhtf/kernel/image.itb
9788 16:34:22.206341
9789 16:34:22.209980 Sending tftp read request... done.
9790 16:34:22.210054
9791 16:34:22.212959 Waiting for the transfer...
9792 16:34:22.216401
9793 16:34:22.488393 00000000 ################################################################
9794 16:34:22.488521
9795 16:34:22.756232 00080000 ################################################################
9796 16:34:22.756360
9797 16:34:23.021267 00100000 ################################################################
9798 16:34:23.021396
9799 16:34:23.287130 00180000 ################################################################
9800 16:34:23.287247
9801 16:34:23.553605 00200000 ################################################################
9802 16:34:23.553729
9803 16:34:23.830028 00280000 ################################################################
9804 16:34:23.830152
9805 16:34:24.116300 00300000 ################################################################
9806 16:34:24.116425
9807 16:34:24.391844 00380000 ################################################################
9808 16:34:24.391970
9809 16:34:24.668012 00400000 ################################################################
9810 16:34:24.668136
9811 16:34:24.940498 00480000 ################################################################
9812 16:34:24.940631
9813 16:34:25.225836 00500000 ################################################################
9814 16:34:25.225962
9815 16:34:25.518342 00580000 ################################################################
9816 16:34:25.518464
9817 16:34:25.797739 00600000 ################################################################
9818 16:34:25.797885
9819 16:34:26.079515 00680000 ################################################################
9820 16:34:26.079643
9821 16:34:26.345023 00700000 ################################################################
9822 16:34:26.345149
9823 16:34:26.634331 00780000 ################################################################
9824 16:34:26.634487
9825 16:34:26.897051 00800000 ################################################################
9826 16:34:26.897176
9827 16:34:27.155379 00880000 ################################################################
9828 16:34:27.155502
9829 16:34:27.417663 00900000 ################################################################
9830 16:34:27.417784
9831 16:34:27.686406 00980000 ################################################################
9832 16:34:27.686531
9833 16:34:27.984325 00a00000 ################################################################
9834 16:34:27.984451
9835 16:34:28.279483 00a80000 ################################################################
9836 16:34:28.279609
9837 16:34:28.550722 00b00000 ################################################################
9838 16:34:28.550840
9839 16:34:28.844902 00b80000 ################################################################
9840 16:34:28.845034
9841 16:34:29.128084 00c00000 ################################################################
9842 16:34:29.128212
9843 16:34:29.397329 00c80000 ################################################################
9844 16:34:29.397457
9845 16:34:29.671220 00d00000 ################################################################
9846 16:34:29.671348
9847 16:34:29.951732 00d80000 ################################################################
9848 16:34:29.951859
9849 16:34:30.230573 00e00000 ################################################################
9850 16:34:30.230696
9851 16:34:30.509563 00e80000 ################################################################
9852 16:34:30.509691
9853 16:34:30.779056 00f00000 ################################################################
9854 16:34:30.779177
9855 16:34:31.075560 00f80000 ################################################################
9856 16:34:31.075694
9857 16:34:31.371687 01000000 ################################################################
9858 16:34:31.371815
9859 16:34:31.656236 01080000 ################################################################
9860 16:34:31.656365
9861 16:34:31.921400 01100000 ################################################################
9862 16:34:31.921527
9863 16:34:32.193133 01180000 ################################################################
9864 16:34:32.193265
9865 16:34:32.449402 01200000 ################################################################
9866 16:34:32.449531
9867 16:34:32.711536 01280000 ################################################################
9868 16:34:32.711713
9869 16:34:32.975715 01300000 ################################################################
9870 16:34:32.975845
9871 16:34:33.237116 01380000 ################################################################
9872 16:34:33.237244
9873 16:34:33.522162 01400000 ################################################################
9874 16:34:33.522305
9875 16:34:33.769392 01480000 ################################################################
9876 16:34:33.769521
9877 16:34:34.035220 01500000 ################################################################
9878 16:34:34.035344
9879 16:34:34.304685 01580000 ################################################################
9880 16:34:34.304812
9881 16:34:34.578067 01600000 ################################################################
9882 16:34:34.578195
9883 16:34:34.854418 01680000 ################################################################
9884 16:34:34.854558
9885 16:34:35.125606 01700000 ################################################################
9886 16:34:35.125754
9887 16:34:35.410711 01780000 ################################################################
9888 16:34:35.410840
9889 16:34:35.695597 01800000 ################################################################
9890 16:34:35.695719
9891 16:34:35.968628 01880000 ################################################################
9892 16:34:35.968778
9893 16:34:36.234514 01900000 ################################################################
9894 16:34:36.234666
9895 16:34:36.502729 01980000 ################################################################
9896 16:34:36.502878
9897 16:34:36.784275 01a00000 ################################################################
9898 16:34:36.784430
9899 16:34:37.062876 01a80000 ################################################################
9900 16:34:37.063021
9901 16:34:37.336415 01b00000 ################################################################
9902 16:34:37.336566
9903 16:34:37.606461 01b80000 ################################################################
9904 16:34:37.606600
9905 16:34:37.880708 01c00000 ################################################################
9906 16:34:37.880857
9907 16:34:38.140138 01c80000 ################################################################
9908 16:34:38.140278
9909 16:34:38.394620 01d00000 ################################################################
9910 16:34:38.394769
9911 16:34:38.658928 01d80000 ################################################################
9912 16:34:38.659063
9913 16:34:38.918040 01e00000 ################################################################
9914 16:34:38.918234
9915 16:34:39.186156 01e80000 ################################################################
9916 16:34:39.186331
9917 16:34:39.457318 01f00000 ################################################################
9918 16:34:39.457453
9919 16:34:39.712680 01f80000 ################################################################
9920 16:34:39.712832
9921 16:34:40.001476 02000000 ################################################################
9922 16:34:40.001594
9923 16:34:40.279027 02080000 ################################################################
9924 16:34:40.279149
9925 16:34:40.542335 02100000 ################################################################
9926 16:34:40.542452
9927 16:34:40.810141 02180000 ################################################################
9928 16:34:40.810304
9929 16:34:41.083103 02200000 ################################################################
9930 16:34:41.083234
9931 16:34:41.351630 02280000 ################################################################
9932 16:34:41.351755
9933 16:34:41.609692 02300000 ################################################################
9934 16:34:41.609813
9935 16:34:41.872244 02380000 ################################################################
9936 16:34:41.872374
9937 16:34:42.139696 02400000 ################################################################
9938 16:34:42.139825
9939 16:34:42.405606 02480000 ################################################################
9940 16:34:42.405743
9941 16:34:42.671853 02500000 ################################################################
9942 16:34:42.671967
9943 16:34:42.935648 02580000 ################################################################
9944 16:34:42.935762
9945 16:34:43.215980 02600000 ################################################################
9946 16:34:43.216116
9947 16:34:43.497561 02680000 ################################################################
9948 16:34:43.497697
9949 16:34:43.771535 02700000 ################################################################
9950 16:34:43.771650
9951 16:34:44.036976 02780000 ################################################################
9952 16:34:44.037089
9953 16:34:44.310589 02800000 ################################################################
9954 16:34:44.310703
9955 16:34:44.568929 02880000 ################################################################
9956 16:34:44.569044
9957 16:34:44.823609 02900000 ################################################################
9958 16:34:44.823721
9959 16:34:45.096962 02980000 ################################################################
9960 16:34:45.097078
9961 16:34:45.359142 02a00000 ################################################################
9962 16:34:45.359252
9963 16:34:45.620609 02a80000 ################################################################
9964 16:34:45.620721
9965 16:34:45.880210 02b00000 ################################################################
9966 16:34:45.880328
9967 16:34:46.137197 02b80000 ################################################################
9968 16:34:46.137320
9969 16:34:46.428929 02c00000 ################################################################
9970 16:34:46.429035
9971 16:34:46.690517 02c80000 ################################################################
9972 16:34:46.690640
9973 16:34:46.950198 02d00000 ################################################################
9974 16:34:46.950331
9975 16:34:47.220588 02d80000 ################################################################
9976 16:34:47.220722
9977 16:34:47.517012 02e00000 ################################################################
9978 16:34:47.517144
9979 16:34:47.789089 02e80000 ################################################################
9980 16:34:47.789207
9981 16:34:48.063008 02f00000 ################################################################
9982 16:34:48.063137
9983 16:34:48.327002 02f80000 ################################################################
9984 16:34:48.327135
9985 16:34:48.602558 03000000 ################################################################
9986 16:34:48.602686
9987 16:34:48.863805 03080000 ################################################################
9988 16:34:48.863930
9989 16:34:49.143339 03100000 ################################################################
9990 16:34:49.143488
9991 16:34:49.420849 03180000 ################################################################
9992 16:34:49.420979
9993 16:34:49.691962 03200000 ################################################################
9994 16:34:49.692086
9995 16:34:49.950811 03280000 ################################################################
9996 16:34:49.950935
9997 16:34:50.209979 03300000 ################################################################
9998 16:34:50.210120
9999 16:34:50.477654 03380000 ################################################################
10000 16:34:50.477792
10001 16:34:50.762779 03400000 ################################################################
10002 16:34:50.762930
10003 16:34:51.022692 03480000 ################################################################
10004 16:34:51.022820
10005 16:34:51.292331 03500000 ################################################################
10006 16:34:51.292472
10007 16:34:51.570621 03580000 ################################################################
10008 16:34:51.570754
10009 16:34:51.846448 03600000 ################################################################
10010 16:34:51.846575
10011 16:34:52.125549 03680000 ################################################################
10012 16:34:52.125679
10013 16:34:52.388341 03700000 ################################################################
10014 16:34:52.388490
10015 16:34:52.652313 03780000 ################################################################
10016 16:34:52.652437
10017 16:34:52.918895 03800000 ################################################################
10018 16:34:52.919029
10019 16:34:53.187878 03880000 ################################################################
10020 16:34:53.188041
10021 16:34:53.449275 03900000 ################################################################
10022 16:34:53.449419
10023 16:34:53.711017 03980000 ################################################################
10024 16:34:53.711175
10025 16:34:53.984583 03a00000 ################################################################
10026 16:34:53.984714
10027 16:34:54.254519 03a80000 ################################################################
10028 16:34:54.254661
10029 16:34:54.517227 03b00000 ################################################################
10030 16:34:54.517364
10031 16:34:54.771907 03b80000 ################################################################
10032 16:34:54.772044
10033 16:34:55.034087 03c00000 ################################################################
10034 16:34:55.034286
10035 16:34:55.302324 03c80000 ################################################################
10036 16:34:55.302465
10037 16:34:55.575936 03d00000 ################################################################
10038 16:34:55.576070
10039 16:34:55.849039 03d80000 ################################################################
10040 16:34:55.849187
10041 16:34:56.125353 03e00000 ################################################################
10042 16:34:56.125493
10043 16:34:56.379200 03e80000 ################################################################
10044 16:34:56.379335
10045 16:34:56.639541 03f00000 ################################################################
10046 16:34:56.639689
10047 16:34:56.909087 03f80000 ################################################################
10048 16:34:56.909219
10049 16:34:57.196811 04000000 ################################################################
10050 16:34:57.196939
10051 16:34:57.479912 04080000 ################################################################
10052 16:34:57.480023
10053 16:34:57.769729 04100000 ################################################################
10054 16:34:57.769848
10055 16:34:58.029473 04180000 ################################################################
10056 16:34:58.029603
10057 16:34:58.312384 04200000 ################################################################
10058 16:34:58.312518
10059 16:34:58.568428 04280000 ################################################################
10060 16:34:58.568558
10061 16:34:58.839965 04300000 ################################################################
10062 16:34:58.840116
10063 16:34:59.096111 04380000 ################################################################
10064 16:34:59.096262
10065 16:34:59.361433 04400000 ################################################################
10066 16:34:59.361560
10067 16:34:59.622463 04480000 ################################################################
10068 16:34:59.622592
10069 16:34:59.879714 04500000 ################################################################
10070 16:34:59.879881
10071 16:35:00.128553 04580000 ################################################################
10072 16:35:00.128666
10073 16:35:00.389243 04600000 ################################################################
10074 16:35:00.389391
10075 16:35:00.514403 04680000 ################################# done.
10076 16:35:00.514536
10077 16:35:00.517542 The bootfile was 74188994 bytes long.
10078 16:35:00.517629
10079 16:35:00.521127 Sending tftp read request... done.
10080 16:35:00.521219
10081 16:35:00.524234 Waiting for the transfer...
10082 16:35:00.524322
10083 16:35:00.524381 00000000 # done.
10084 16:35:00.524443
10085 16:35:00.534592 Command line loaded dynamically from TFTP file: 14396148/tftp-deploy-4nudwhtf/kernel/cmdline
10086 16:35:00.534686
10087 16:35:00.547847 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10088 16:35:00.547960
10089 16:35:00.548022 Loading FIT.
10090 16:35:00.548076
10091 16:35:00.550775 Image ramdisk-1 has 61010956 bytes.
10092 16:35:00.550877
10093 16:35:00.554311 Image fdt-1 has 47258 bytes.
10094 16:35:00.554387
10095 16:35:00.557366 Image kernel-1 has 13128753 bytes.
10096 16:35:00.557474
10097 16:35:00.563651 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10098 16:35:00.567245
10099 16:35:00.584157 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10100 16:35:00.584287
10101 16:35:00.587204 Choosing best match conf-1 for compat google,spherion-rev3.
10102 16:35:00.592670
10103 16:35:00.597500 Connected to device vid:did:rid of 1ae0:0028:00
10104 16:35:00.603693
10105 16:35:00.607168 tpm_get_response: command 0x17b, return code 0x0
10106 16:35:00.607251
10107 16:35:00.610370 ec_init: CrosEC protocol v3 supported (256, 248)
10108 16:35:00.614841
10109 16:35:00.618170 tpm_cleanup: add release locality here.
10110 16:35:00.618274
10111 16:35:00.618335 Shutting down all USB controllers.
10112 16:35:00.621659
10113 16:35:00.621740 Removing current net device
10114 16:35:00.621799
10115 16:35:00.628280 Exiting depthcharge with code 4 at timestamp: 71430553
10116 16:35:00.628368
10117 16:35:00.631402 LZMA decompressing kernel-1 to 0x821a6718
10118 16:35:00.631481
10119 16:35:00.634595 LZMA decompressing kernel-1 to 0x40000000
10120 16:35:02.250588
10121 16:35:02.250755 jumping to kernel
10122 16:35:02.251481 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10123 16:35:02.251581 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10124 16:35:02.251664 Setting prompt string to ['Linux version [0-9]']
10125 16:35:02.251736 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 16:35:02.251830 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10127 16:35:02.301002
10128 16:35:02.304555 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10129 16:35:02.307913 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10130 16:35:02.308030 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10131 16:35:02.308098 Setting prompt string to []
10132 16:35:02.308186 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10133 16:35:02.308260 Using line separator: #'\n'#
10134 16:35:02.308316 No login prompt set.
10135 16:35:02.308381 Parsing kernel messages
10136 16:35:02.308446 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10137 16:35:02.308546 [login-action] Waiting for messages, (timeout 00:03:43)
10138 16:35:02.308618 Waiting using forced prompt support (timeout 00:01:52)
10139 16:35:02.327626 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10140 16:35:02.331120 [ 0.000000] random: crng init done
10141 16:35:02.337400 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10142 16:35:02.340417 [ 0.000000] efi: UEFI not found.
10143 16:35:02.347155 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10144 16:35:02.357298 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10145 16:35:02.367098 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10146 16:35:02.373701 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10147 16:35:02.380026 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10148 16:35:02.386376 [ 0.000000] printk: bootconsole [mtk8250] enabled
10149 16:35:02.393244 [ 0.000000] NUMA: No NUMA configuration found
10150 16:35:02.399701 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10151 16:35:02.406631 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10152 16:35:02.406758 [ 0.000000] Zone ranges:
10153 16:35:02.413233 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10154 16:35:02.416109 [ 0.000000] DMA32 empty
10155 16:35:02.422643 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10156 16:35:02.426335 [ 0.000000] Movable zone start for each node
10157 16:35:02.429294 [ 0.000000] Early memory node ranges
10158 16:35:02.436347 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10159 16:35:02.442513 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10160 16:35:02.449395 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10161 16:35:02.456051 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10162 16:35:02.462364 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10163 16:35:02.469025 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10164 16:35:02.499191 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10165 16:35:02.506078 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10166 16:35:02.512294 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10167 16:35:02.515887 [ 0.000000] psci: probing for conduit method from DT.
10168 16:35:02.522498 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10169 16:35:02.525555 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10170 16:35:02.532297 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10171 16:35:02.535749 [ 0.000000] psci: SMC Calling Convention v1.2
10172 16:35:02.542153 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10173 16:35:02.545630 [ 0.000000] Detected VIPT I-cache on CPU0
10174 16:35:02.552377 [ 0.000000] CPU features: detected: GIC system register CPU interface
10175 16:35:02.558475 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10176 16:35:02.565614 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10177 16:35:02.572191 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10178 16:35:02.578843 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10179 16:35:02.588548 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10180 16:35:02.592233 [ 0.000000] alternatives: applying boot alternatives
10181 16:35:02.598385 [ 0.000000] Fallback order for Node 0: 0
10182 16:35:02.605331 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10183 16:35:02.608395 [ 0.000000] Policy zone: Normal
10184 16:35:02.621538 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10185 16:35:02.631493 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10186 16:35:02.642161 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10187 16:35:02.651681 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10188 16:35:02.658420 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10189 16:35:02.661360 <6>[ 0.000000] software IO TLB: area num 8.
10190 16:35:02.718046 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10191 16:35:02.798488 <6>[ 0.000000] Memory: 3790060K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 368404K reserved, 32768K cma-reserved)
10192 16:35:02.805170 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10193 16:35:02.811473 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10194 16:35:02.814972 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10195 16:35:02.821355 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10196 16:35:02.827946 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10197 16:35:02.831644 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10198 16:35:02.841399 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10199 16:35:02.847759 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10200 16:35:02.854189 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10201 16:35:02.860748 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10202 16:35:02.864225 <6>[ 0.000000] GICv3: 608 SPIs implemented
10203 16:35:02.867517 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10204 16:35:02.873916 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10205 16:35:02.877550 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10206 16:35:02.884531 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10207 16:35:02.897610 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10208 16:35:02.910895 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10209 16:35:02.917145 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10210 16:35:02.925114 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10211 16:35:02.938207 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10212 16:35:02.944760 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10213 16:35:02.951650 <6>[ 0.009224] Console: colour dummy device 80x25
10214 16:35:02.961813 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10215 16:35:02.968482 <6>[ 0.024393] pid_max: default: 32768 minimum: 301
10216 16:35:02.971083 <6>[ 0.029294] LSM: Security Framework initializing
10217 16:35:02.978312 <6>[ 0.034236] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10218 16:35:02.988043 <6>[ 0.041845] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10219 16:35:02.994467 <6>[ 0.051084] cblist_init_generic: Setting adjustable number of callback queues.
10220 16:35:03.000763 <6>[ 0.058574] cblist_init_generic: Setting shift to 3 and lim to 1.
10221 16:35:03.010820 <6>[ 0.064912] cblist_init_generic: Setting adjustable number of callback queues.
10222 16:35:03.017579 <6>[ 0.072339] cblist_init_generic: Setting shift to 3 and lim to 1.
10223 16:35:03.021102 <6>[ 0.078739] rcu: Hierarchical SRCU implementation.
10224 16:35:03.027449 <6>[ 0.083754] rcu: Max phase no-delay instances is 1000.
10225 16:35:03.034183 <6>[ 0.090768] EFI services will not be available.
10226 16:35:03.037307 <6>[ 0.095725] smp: Bringing up secondary CPUs ...
10227 16:35:03.045320 <6>[ 0.100776] Detected VIPT I-cache on CPU1
10228 16:35:03.052308 <6>[ 0.100844] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10229 16:35:03.058862 <6>[ 0.100876] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10230 16:35:03.062103 <6>[ 0.101206] Detected VIPT I-cache on CPU2
10231 16:35:03.071944 <6>[ 0.101256] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10232 16:35:03.078573 <6>[ 0.101272] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10233 16:35:03.081518 <6>[ 0.101528] Detected VIPT I-cache on CPU3
10234 16:35:03.088220 <6>[ 0.101575] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10235 16:35:03.095103 <6>[ 0.101590] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10236 16:35:03.098197 <6>[ 0.101891] CPU features: detected: Spectre-v4
10237 16:35:03.104729 <6>[ 0.101897] CPU features: detected: Spectre-BHB
10238 16:35:03.108214 <6>[ 0.101902] Detected PIPT I-cache on CPU4
10239 16:35:03.114769 <6>[ 0.101961] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10240 16:35:03.121400 <6>[ 0.101978] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10241 16:35:03.128057 <6>[ 0.102270] Detected PIPT I-cache on CPU5
10242 16:35:03.134754 <6>[ 0.102333] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10243 16:35:03.141052 <6>[ 0.102349] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10244 16:35:03.144506 <6>[ 0.102628] Detected PIPT I-cache on CPU6
10245 16:35:03.151185 <6>[ 0.102691] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10246 16:35:03.157856 <6>[ 0.102707] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10247 16:35:03.164771 <6>[ 0.103003] Detected PIPT I-cache on CPU7
10248 16:35:03.170833 <6>[ 0.103068] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10249 16:35:03.177307 <6>[ 0.103083] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10250 16:35:03.180940 <6>[ 0.103131] smp: Brought up 1 node, 8 CPUs
10251 16:35:03.187585 <6>[ 0.244477] SMP: Total of 8 processors activated.
10252 16:35:03.190846 <6>[ 0.249429] CPU features: detected: 32-bit EL0 Support
10253 16:35:03.200407 <6>[ 0.254792] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10254 16:35:03.207310 <6>[ 0.263647] CPU features: detected: Common not Private translations
10255 16:35:03.213646 <6>[ 0.270122] CPU features: detected: CRC32 instructions
10256 16:35:03.220122 <6>[ 0.275507] CPU features: detected: RCpc load-acquire (LDAPR)
10257 16:35:03.223646 <6>[ 0.281467] CPU features: detected: LSE atomic instructions
10258 16:35:03.229951 <6>[ 0.287249] CPU features: detected: Privileged Access Never
10259 16:35:03.236950 <6>[ 0.293028] CPU features: detected: RAS Extension Support
10260 16:35:03.243528 <6>[ 0.298637] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10261 16:35:03.246528 <6>[ 0.305856] CPU: All CPU(s) started at EL2
10262 16:35:03.253453 <6>[ 0.310199] alternatives: applying system-wide alternatives
10263 16:35:03.262369 <6>[ 0.320234] devtmpfs: initialized
10264 16:35:03.274139 <6>[ 0.328477] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10265 16:35:03.283957 <6>[ 0.338439] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10266 16:35:03.290771 <6>[ 0.346482] pinctrl core: initialized pinctrl subsystem
10267 16:35:03.293797 <6>[ 0.353179] DMI not present or invalid.
10268 16:35:03.300356 <6>[ 0.357589] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10269 16:35:03.310504 <6>[ 0.364428] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10270 16:35:03.317278 <6>[ 0.371873] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10271 16:35:03.326896 <6>[ 0.379969] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10272 16:35:03.330379 <6>[ 0.388124] audit: initializing netlink subsys (disabled)
10273 16:35:03.340218 <5>[ 0.393821] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10274 16:35:03.346898 <6>[ 0.394542] thermal_sys: Registered thermal governor 'step_wise'
10275 16:35:03.353560 <6>[ 0.401787] thermal_sys: Registered thermal governor 'power_allocator'
10276 16:35:03.356616 <6>[ 0.408045] cpuidle: using governor menu
10277 16:35:03.359846 <6>[ 0.419004] NET: Registered PF_QIPCRTR protocol family
10278 16:35:03.370300 <6>[ 0.424480] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10279 16:35:03.373164 <6>[ 0.431579] ASID allocator initialised with 32768 entries
10280 16:35:03.380482 <6>[ 0.438148] Serial: AMBA PL011 UART driver
10281 16:35:03.388909 <4>[ 0.446908] Trying to register duplicate clock ID: 134
10282 16:35:03.449062 <6>[ 0.510053] KASLR enabled
10283 16:35:03.463478 <6>[ 0.517824] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10284 16:35:03.469908 <6>[ 0.524836] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10285 16:35:03.476326 <6>[ 0.531327] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10286 16:35:03.483306 <6>[ 0.538334] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10287 16:35:03.489629 <6>[ 0.544823] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10288 16:35:03.496153 <6>[ 0.551829] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10289 16:35:03.503000 <6>[ 0.558316] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10290 16:35:03.509441 <6>[ 0.565319] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10291 16:35:03.512628 <6>[ 0.572833] ACPI: Interpreter disabled.
10292 16:35:03.521580 <6>[ 0.579255] iommu: Default domain type: Translated
10293 16:35:03.528143 <6>[ 0.584369] iommu: DMA domain TLB invalidation policy: strict mode
10294 16:35:03.531541 <5>[ 0.591028] SCSI subsystem initialized
10295 16:35:03.538190 <6>[ 0.595195] usbcore: registered new interface driver usbfs
10296 16:35:03.544569 <6>[ 0.600929] usbcore: registered new interface driver hub
10297 16:35:03.547548 <6>[ 0.606482] usbcore: registered new device driver usb
10298 16:35:03.554919 <6>[ 0.612579] pps_core: LinuxPPS API ver. 1 registered
10299 16:35:03.564811 <6>[ 0.617773] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10300 16:35:03.567930 <6>[ 0.627120] PTP clock support registered
10301 16:35:03.571449 <6>[ 0.631363] EDAC MC: Ver: 3.0.0
10302 16:35:03.578881 <6>[ 0.636516] FPGA manager framework
10303 16:35:03.585370 <6>[ 0.640202] Advanced Linux Sound Architecture Driver Initialized.
10304 16:35:03.588700 <6>[ 0.646983] vgaarb: loaded
10305 16:35:03.595364 <6>[ 0.650133] clocksource: Switched to clocksource arch_sys_counter
10306 16:35:03.598383 <5>[ 0.656573] VFS: Disk quotas dquot_6.6.0
10307 16:35:03.605077 <6>[ 0.660760] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10308 16:35:03.608889 <6>[ 0.667951] pnp: PnP ACPI: disabled
10309 16:35:03.616968 <6>[ 0.674710] NET: Registered PF_INET protocol family
10310 16:35:03.623301 <6>[ 0.680100] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10311 16:35:03.635934 <6>[ 0.690167] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10312 16:35:03.645714 <6>[ 0.698954] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10313 16:35:03.652249 <6>[ 0.706924] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10314 16:35:03.658618 <6>[ 0.715328] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10315 16:35:03.669737 <6>[ 0.723985] TCP: Hash tables configured (established 32768 bind 32768)
10316 16:35:03.676380 <6>[ 0.730845] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10317 16:35:03.683262 <6>[ 0.737864] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10318 16:35:03.689523 <6>[ 0.745387] NET: Registered PF_UNIX/PF_LOCAL protocol family
10319 16:35:03.696111 <6>[ 0.751538] RPC: Registered named UNIX socket transport module.
10320 16:35:03.699655 <6>[ 0.757691] RPC: Registered udp transport module.
10321 16:35:03.705898 <6>[ 0.762626] RPC: Registered tcp transport module.
10322 16:35:03.712647 <6>[ 0.767557] RPC: Registered tcp NFSv4.1 backchannel transport module.
10323 16:35:03.716054 <6>[ 0.774224] PCI: CLS 0 bytes, default 64
10324 16:35:03.719412 <6>[ 0.778479] Unpacking initramfs...
10325 16:35:03.743588 <6>[ 0.798247] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10326 16:35:03.754014 <6>[ 0.806916] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10327 16:35:03.757318 <6>[ 0.815734] kvm [1]: IPA Size Limit: 40 bits
10328 16:35:03.763437 <6>[ 0.820264] kvm [1]: GICv3: no GICV resource entry
10329 16:35:03.767056 <6>[ 0.825285] kvm [1]: disabling GICv2 emulation
10330 16:35:03.773671 <6>[ 0.829971] kvm [1]: GIC system register CPU interface enabled
10331 16:35:03.776858 <6>[ 0.836119] kvm [1]: vgic interrupt IRQ18
10332 16:35:03.783622 <6>[ 0.840468] kvm [1]: VHE mode initialized successfully
10333 16:35:03.790151 <5>[ 0.846864] Initialise system trusted keyrings
10334 16:35:03.796461 <6>[ 0.851650] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10335 16:35:03.803865 <6>[ 0.861653] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10336 16:35:03.810610 <5>[ 0.868036] NFS: Registering the id_resolver key type
10337 16:35:03.813688 <5>[ 0.873337] Key type id_resolver registered
10338 16:35:03.820100 <5>[ 0.877752] Key type id_legacy registered
10339 16:35:03.826617 <6>[ 0.882030] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10340 16:35:03.833446 <6>[ 0.888951] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10341 16:35:03.840221 <6>[ 0.896641] 9p: Installing v9fs 9p2000 file system support
10342 16:35:03.877644 <5>[ 0.935288] Key type asymmetric registered
10343 16:35:03.880946 <5>[ 0.939619] Asymmetric key parser 'x509' registered
10344 16:35:03.890581 <6>[ 0.944767] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10345 16:35:03.894063 <6>[ 0.952382] io scheduler mq-deadline registered
10346 16:35:03.897206 <6>[ 0.957141] io scheduler kyber registered
10347 16:35:03.916238 <6>[ 0.974120] EINJ: ACPI disabled.
10348 16:35:03.949584 <4>[ 1.000577] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10349 16:35:03.959146 <4>[ 1.011201] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10350 16:35:03.974450 <6>[ 1.032274] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10351 16:35:03.982791 <6>[ 1.040228] printk: console [ttyS0] disabled
10352 16:35:04.010680 <6>[ 1.064859] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10353 16:35:04.016849 <6>[ 1.074333] printk: console [ttyS0] enabled
10354 16:35:04.020549 <6>[ 1.074333] printk: console [ttyS0] enabled
10355 16:35:04.026812 <6>[ 1.083228] printk: bootconsole [mtk8250] disabled
10356 16:35:04.030506 <6>[ 1.083228] printk: bootconsole [mtk8250] disabled
10357 16:35:04.036631 <6>[ 1.094253] SuperH (H)SCI(F) driver initialized
10358 16:35:04.040391 <6>[ 1.099518] msm_serial: driver initialized
10359 16:35:04.054076 <6>[ 1.108385] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10360 16:35:04.064229 <6>[ 1.116932] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10361 16:35:04.070314 <6>[ 1.125474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10362 16:35:04.080580 <6>[ 1.134101] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10363 16:35:04.086944 <6>[ 1.142808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10364 16:35:04.097183 <6>[ 1.151521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10365 16:35:04.106997 <6>[ 1.160060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10366 16:35:04.113574 <6>[ 1.168867] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10367 16:35:04.123295 <6>[ 1.177408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10368 16:35:04.135801 <6>[ 1.193400] loop: module loaded
10369 16:35:04.142458 <6>[ 1.199135] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10370 16:35:04.165057 <4>[ 1.222343] mtk-pmic-keys: Failed to locate of_node [id: -1]
10371 16:35:04.171623 <6>[ 1.229086] megasas: 07.719.03.00-rc1
10372 16:35:04.181524 <6>[ 1.238976] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10373 16:35:04.188292 <6>[ 1.245514] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10374 16:35:04.204387 <6>[ 1.262049] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10375 16:35:04.260782 <6>[ 1.311834] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10376 16:35:06.422477 <6>[ 3.479773] Freeing initrd memory: 59580K
10377 16:35:06.433664 <6>[ 3.491523] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10378 16:35:06.444740 <6>[ 3.502514] tun: Universal TUN/TAP device driver, 1.6
10379 16:35:06.448398 <6>[ 3.508566] thunder_xcv, ver 1.0
10380 16:35:06.451514 <6>[ 3.512069] thunder_bgx, ver 1.0
10381 16:35:06.454687 <6>[ 3.515565] nicpf, ver 1.0
10382 16:35:06.465438 <6>[ 3.519589] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10383 16:35:06.468282 <6>[ 3.527064] hns3: Copyright (c) 2017 Huawei Corporation.
10384 16:35:06.475265 <6>[ 3.532652] hclge is initializing
10385 16:35:06.478432 <6>[ 3.536229] e1000: Intel(R) PRO/1000 Network Driver
10386 16:35:06.485393 <6>[ 3.541359] e1000: Copyright (c) 1999-2006 Intel Corporation.
10387 16:35:06.488701 <6>[ 3.547377] e1000e: Intel(R) PRO/1000 Network Driver
10388 16:35:06.495065 <6>[ 3.552593] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10389 16:35:06.501328 <6>[ 3.558777] igb: Intel(R) Gigabit Ethernet Network Driver
10390 16:35:06.508122 <6>[ 3.564427] igb: Copyright (c) 2007-2014 Intel Corporation.
10391 16:35:06.514969 <6>[ 3.570264] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10392 16:35:06.521328 <6>[ 3.576781] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10393 16:35:06.524920 <6>[ 3.583244] sky2: driver version 1.30
10394 16:35:06.531382 <6>[ 3.588171] usbcore: registered new device driver r8152-cfgselector
10395 16:35:06.538163 <6>[ 3.594707] usbcore: registered new interface driver r8152
10396 16:35:06.544474 <6>[ 3.600526] VFIO - User Level meta-driver version: 0.3
10397 16:35:06.551038 <6>[ 3.608772] usbcore: registered new interface driver usb-storage
10398 16:35:06.557957 <6>[ 3.615226] usbcore: registered new device driver onboard-usb-hub
10399 16:35:06.567054 <6>[ 3.624433] mt6397-rtc mt6359-rtc: registered as rtc0
10400 16:35:06.577090 <6>[ 3.629923] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:35:06 UTC (1718642106)
10401 16:35:06.580236 <6>[ 3.639527] i2c_dev: i2c /dev entries driver
10402 16:35:06.593854 <4>[ 3.651519] cpu cpu0: supply cpu not found, using dummy regulator
10403 16:35:06.600656 <4>[ 3.657950] cpu cpu1: supply cpu not found, using dummy regulator
10404 16:35:06.606880 <4>[ 3.664354] cpu cpu2: supply cpu not found, using dummy regulator
10405 16:35:06.613602 <4>[ 3.670758] cpu cpu3: supply cpu not found, using dummy regulator
10406 16:35:06.620148 <4>[ 3.677181] cpu cpu4: supply cpu not found, using dummy regulator
10407 16:35:06.626575 <4>[ 3.683575] cpu cpu5: supply cpu not found, using dummy regulator
10408 16:35:06.633426 <4>[ 3.689975] cpu cpu6: supply cpu not found, using dummy regulator
10409 16:35:06.639936 <4>[ 3.696370] cpu cpu7: supply cpu not found, using dummy regulator
10410 16:35:06.659459 <6>[ 3.716989] cpu cpu0: EM: created perf domain
10411 16:35:06.662768 <6>[ 3.721899] cpu cpu4: EM: created perf domain
10412 16:35:06.669664 <6>[ 3.727393] sdhci: Secure Digital Host Controller Interface driver
10413 16:35:06.676425 <6>[ 3.733825] sdhci: Copyright(c) Pierre Ossman
10414 16:35:06.683097 <6>[ 3.738743] Synopsys Designware Multimedia Card Interface Driver
10415 16:35:06.689656 <6>[ 3.745340] sdhci-pltfm: SDHCI platform and OF driver helper
10416 16:35:06.693395 <6>[ 3.745499] mmc0: CQHCI version 5.10
10417 16:35:06.699689 <6>[ 3.755458] ledtrig-cpu: registered to indicate activity on CPUs
10418 16:35:06.706245 <6>[ 3.762379] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10419 16:35:06.713443 <6>[ 3.769403] usbcore: registered new interface driver usbhid
10420 16:35:06.716161 <6>[ 3.775224] usbhid: USB HID core driver
10421 16:35:06.723069 <6>[ 3.779426] spi_master spi0: will run message pump with realtime priority
10422 16:35:06.765859 <6>[ 3.817201] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10423 16:35:06.785502 <6>[ 3.832512] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10424 16:35:06.788587 <6>[ 3.845788] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10425 16:35:06.795586 <6>[ 3.853109] cros-ec-spi spi0.0: Chrome EC device registered
10426 16:35:06.802194 <6>[ 3.859111] mmc0: Command Queue Engine enabled
10427 16:35:06.808933 <6>[ 3.863842] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10428 16:35:06.812365 <6>[ 3.871311] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10429 16:35:06.822303 <6>[ 3.880178] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10430 16:35:06.829812 <6>[ 3.887630] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10431 16:35:06.839745 <6>[ 3.891652] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10432 16:35:06.842818 <6>[ 3.893565] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10433 16:35:06.849785 <6>[ 3.903218] NET: Registered PF_PACKET protocol family
10434 16:35:06.856384 <6>[ 3.907997] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10435 16:35:06.859524 <6>[ 3.912764] 9pnet: Installing 9P2000 support
10436 16:35:06.866466 <5>[ 3.923756] Key type dns_resolver registered
10437 16:35:06.869686 <6>[ 3.928689] registered taskstats version 1
10438 16:35:06.876365 <5>[ 3.933066] Loading compiled-in X.509 certificates
10439 16:35:06.902447 <4>[ 3.953549] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10440 16:35:06.912397 <4>[ 3.964294] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10441 16:35:06.926268 <6>[ 3.984293] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10442 16:35:06.933000 <6>[ 3.991048] xhci-mtk 11200000.usb: xHCI Host Controller
10443 16:35:06.940157 <6>[ 3.996560] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10444 16:35:06.949739 <6>[ 4.004417] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10445 16:35:06.956593 <6>[ 4.013849] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10446 16:35:06.963583 <6>[ 4.020033] xhci-mtk 11200000.usb: xHCI Host Controller
10447 16:35:06.969957 <6>[ 4.025531] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10448 16:35:06.976626 <6>[ 4.033184] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10449 16:35:06.983267 <6>[ 4.041035] hub 1-0:1.0: USB hub found
10450 16:35:06.986363 <6>[ 4.045059] hub 1-0:1.0: 1 port detected
10451 16:35:06.996272 <6>[ 4.049347] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10452 16:35:07.000074 <6>[ 4.058110] hub 2-0:1.0: USB hub found
10453 16:35:07.003147 <6>[ 4.062131] hub 2-0:1.0: 1 port detected
10454 16:35:07.011843 <6>[ 4.069970] mtk-msdc 11f70000.mmc: Got CD GPIO
10455 16:35:07.023989 <6>[ 4.078063] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10456 16:35:07.033459 <6>[ 4.086450] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10457 16:35:07.040431 <6>[ 4.094790] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10458 16:35:07.050298 <6>[ 4.103129] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10459 16:35:07.056971 <6>[ 4.111467] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10460 16:35:07.066664 <6>[ 4.119805] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10461 16:35:07.073768 <6>[ 4.128143] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10462 16:35:07.083245 <6>[ 4.136481] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10463 16:35:07.089873 <6>[ 4.144819] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10464 16:35:07.100177 <6>[ 4.153160] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10465 16:35:07.106261 <6>[ 4.161499] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10466 16:35:07.115979 <6>[ 4.169836] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10467 16:35:07.122789 <6>[ 4.178177] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10468 16:35:07.132662 <6>[ 4.186516] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10469 16:35:07.139644 <6>[ 4.194853] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10470 16:35:07.145677 <6>[ 4.203543] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10471 16:35:07.153143 <6>[ 4.210686] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10472 16:35:07.159697 <6>[ 4.217433] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10473 16:35:07.170048 <6>[ 4.224223] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10474 16:35:07.176455 <6>[ 4.231128] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10475 16:35:07.182919 <6>[ 4.237987] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10476 16:35:07.192755 <6>[ 4.247122] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10477 16:35:07.202735 <6>[ 4.256245] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10478 16:35:07.212695 <6>[ 4.265538] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10479 16:35:07.222428 <6>[ 4.275005] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10480 16:35:07.232298 <6>[ 4.284474] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10481 16:35:07.238995 <6>[ 4.293593] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10482 16:35:07.249364 <6>[ 4.303059] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10483 16:35:07.258532 <6>[ 4.312177] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10484 16:35:07.269288 <6>[ 4.321470] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10485 16:35:07.278600 <6>[ 4.331630] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10486 16:35:07.289324 <6>[ 4.343152] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10487 16:35:07.356954 <6>[ 4.410665] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10488 16:35:07.384307 <6>[ 4.441954] hub 2-1:1.0: USB hub found
10489 16:35:07.387545 <6>[ 4.446444] hub 2-1:1.0: 3 ports detected
10490 16:35:07.397788 <6>[ 4.455610] hub 2-1:1.0: USB hub found
10491 16:35:07.401532 <6>[ 4.459988] hub 2-1:1.0: 3 ports detected
10492 16:35:07.507980 <6>[ 4.562400] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10493 16:35:07.662554 <6>[ 4.720006] hub 1-1:1.0: USB hub found
10494 16:35:07.665680 <6>[ 4.724513] hub 1-1:1.0: 4 ports detected
10495 16:35:07.676451 <6>[ 4.734329] hub 1-1:1.0: USB hub found
10496 16:35:07.680134 <6>[ 4.738791] hub 1-1:1.0: 4 ports detected
10497 16:35:07.748627 <6>[ 4.802517] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10498 16:35:07.856312 <6>[ 4.910818] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10499 16:35:07.888773 <4>[ 4.942877] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10500 16:35:07.898959 <4>[ 4.952069] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10501 16:35:07.937549 <6>[ 4.995069] r8152 2-1.3:1.0 eth0: v1.12.13
10502 16:35:08.012207 <6>[ 5.066442] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10503 16:35:08.143979 <6>[ 5.201539] hub 1-1.4:1.0: USB hub found
10504 16:35:08.146965 <6>[ 5.206172] hub 1-1.4:1.0: 2 ports detected
10505 16:35:08.160156 <6>[ 5.218122] hub 1-1.4:1.0: USB hub found
10506 16:35:08.163514 <6>[ 5.222749] hub 1-1.4:1.0: 2 ports detected
10507 16:35:08.459662 <6>[ 5.514320] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10508 16:35:08.651833 <6>[ 5.706351] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10509 16:35:09.578619 <6>[ 6.636700] r8152 2-1.3:1.0 eth0: carrier on
10510 16:35:09.817938 <5>[ 6.666354] Sending DHCP requests .
10511 16:35:09.824737 <3>[ 6.875778] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[360d164f]
10512 16:35:09.830781 <3>[ 6.886400] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[360d164f]
10513 16:35:11.852532 <4>[ 8.898441] ., OK
10514 16:35:11.862179 <6>[ 8.916519] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10515 16:35:11.865974 <6>[ 8.924814] IP-Config: Complete:
10516 16:35:11.875556 <6>[ 8.928313] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10517 16:35:11.885976 <6>[ 8.939081] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10518 16:35:11.892057 <6>[ 8.947736] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10519 16:35:11.895180 <6>[ 8.947747] nameserver0=192.168.201.1
10520 16:35:11.901830 <6>[ 8.959927] clk: Disabling unused clocks
10521 16:35:11.905545 <6>[ 8.965475] ALSA device list:
10522 16:35:11.908567 <6>[ 8.968757] No soundcards found.
10523 16:35:11.917678 <6>[ 8.976122] Freeing unused kernel memory: 8512K
10524 16:35:11.921421 <6>[ 8.981009] Run /init as init process
10525 16:35:11.951267 <6>[ 9.009719] NET: Registered PF_INET6 protocol family
10526 16:35:11.958018 <6>[ 9.016462] Segment Routing with IPv6
10527 16:35:11.961809 <6>[ 9.020456] In-situ OAM (IOAM) with IPv6
10528 16:35:12.004854 <30>[ 9.036509] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10529 16:35:12.011734 <30>[ 9.069568] systemd[1]: Detected architecture arm64.
10530 16:35:12.012216
10531 16:35:12.018032 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10532 16:35:12.018468
10533 16:35:12.032383 <30>[ 9.090559] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10534 16:35:12.169353 <30>[ 9.224574] systemd[1]: Queued start job for default target graphical.target.
10535 16:35:12.232992 <30>[ 9.287919] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10536 16:35:12.239468 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10537 16:35:12.259674 <30>[ 9.314860] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10538 16:35:12.266580 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10539 16:35:12.288259 <30>[ 9.343120] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10540 16:35:12.298072 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10541 16:35:12.316318 <30>[ 9.371281] systemd[1]: Created slice user.slice - User and Session Slice.
10542 16:35:12.323171 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10543 16:35:12.342988 <30>[ 9.394413] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10544 16:35:12.349492 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10545 16:35:12.371587 <30>[ 9.422930] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10546 16:35:12.377659 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10547 16:35:12.406054 <30>[ 9.450744] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10548 16:35:12.415766 <30>[ 9.470581] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10549 16:35:12.422121 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10550 16:35:12.439860 <30>[ 9.494663] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10551 16:35:12.446113 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10552 16:35:12.463839 <30>[ 9.518539] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10553 16:35:12.473204 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10554 16:35:12.488493 <30>[ 9.546806] systemd[1]: Reached target paths.target - Path Units.
10555 16:35:12.498583 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10556 16:35:12.515918 <30>[ 9.570903] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10557 16:35:12.522455 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10558 16:35:12.535865 <30>[ 9.594411] systemd[1]: Reached target slices.target - Slice Units.
10559 16:35:12.545776 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10560 16:35:12.559669 <30>[ 9.618574] systemd[1]: Reached target swap.target - Swaps.
10561 16:35:12.566652 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10562 16:35:12.587138 <30>[ 9.642586] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10563 16:35:12.596872 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10564 16:35:12.616775 <30>[ 9.671384] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10565 16:35:12.626022 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10566 16:35:12.645747 <30>[ 9.700695] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10567 16:35:12.655560 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10568 16:35:12.671967 <30>[ 9.727157] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10569 16:35:12.682149 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10570 16:35:12.700009 <30>[ 9.755084] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10571 16:35:12.706469 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10572 16:35:12.723922 <30>[ 9.779066] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10573 16:35:12.734006 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10574 16:35:12.752268 <30>[ 9.806911] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10575 16:35:12.762033 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10576 16:35:12.795248 <30>[ 9.850408] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10577 16:35:12.801801 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10578 16:35:12.821105 <30>[ 9.876222] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10579 16:35:12.827530 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10580 16:35:12.854300 <30>[ 9.909739] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10581 16:35:12.861179 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10582 16:35:12.890310 <30>[ 9.938879] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10583 16:35:12.904567 <30>[ 9.959317] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10584 16:35:12.913801 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10585 16:35:12.940309 <30>[ 9.995436] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10586 16:35:12.946925 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10587 16:35:12.976098 <30>[ 10.030985] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10588 16:35:12.989406 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.043884] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10589 16:35:12.992412 Module dm_mod...
10590 16:35:13.020711 <30>[ 10.076000] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10591 16:35:13.027238 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10592 16:35:13.056324 <30>[ 10.111499] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10593 16:35:13.063025 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10594 16:35:13.092191 <30>[ 10.147667] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10595 16:35:13.098866 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10596 16:35:13.131860 <30>[ 10.187430] systemd[1]: Starting systemd-journald.service - Journal Service...
10597 16:35:13.138487 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10598 16:35:13.157403 <30>[ 10.213115] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10599 16:35:13.164380 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10600 16:35:13.190010 <30>[ 10.242351] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10601 16:35:13.196534 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10602 16:35:13.222762 <30>[ 10.278523] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10603 16:35:13.232815 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10604 16:35:13.258199 <30>[ 10.313599] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10605 16:35:13.264731 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10606 16:35:13.291930 <30>[ 10.347587] systemd[1]: Started systemd-journald.service - Journal Service.
10607 16:35:13.298866 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10608 16:35:13.326083 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10609 16:35:13.344197 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10610 16:35:13.368021 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10611 16:35:13.388542 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10612 16:35:13.408563 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10613 16:35:13.428369 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10614 16:35:13.449236 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10615 16:35:13.473277 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10616 16:35:13.497316 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10617 16:35:13.519525 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10618 16:35:13.536496 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10619 16:35:13.556608 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10620 16:35:13.563239 See 'systemctl status systemd-remount-fs.service' for details.
10621 16:35:13.584395 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10622 16:35:13.605032 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10623 16:35:13.647835 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10624 16:35:13.668445 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10625 16:35:13.679685 <46>[ 10.735468] systemd-journald[181]: Received client request to flush runtime journal.
10626 16:35:13.693865 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10627 16:35:13.716818 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10628 16:35:13.740222 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10629 16:35:13.767251 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10630 16:35:13.784473 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10631 16:35:13.804468 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10632 16:35:13.824188 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10633 16:35:13.844327 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10634 16:35:13.899403 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10635 16:35:13.917867 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10636 16:35:13.934992 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10637 16:35:13.950765 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10638 16:35:13.969369 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10639 16:35:13.995049 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10640 16:35:14.020175 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10641 16:35:14.045821 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10642 16:35:14.112604 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10643 16:35:14.141915 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10644 16:35:14.170306 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10645 16:35:14.209220 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10646 16:35:14.235380 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10647 16:35:14.323510 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10648 16:35:14.339435 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10649 16:35:14.355649 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10650 16:35:14.375394 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10651 16:35:14.397923 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - <3>[ 11.452153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 16:35:14.398024 Timer Units.
10653 16:35:14.404482 <6>[ 11.454780] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10654 16:35:14.414229 <3>[ 11.460496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 16:35:14.421026 <6>[ 11.471557] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10656 16:35:14.427594 <3>[ 11.477193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 16:35:14.437492 <6>[ 11.484721] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10658 16:35:14.444105 <6>[ 11.491049] remoteproc remoteproc0: scp is available
10659 16:35:14.447347 <6>[ 11.491155] remoteproc remoteproc0: powering up scp
10660 16:35:14.457567 <6>[ 11.491160] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10661 16:35:14.460666 <6>[ 11.491181] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10662 16:35:14.470131 <3>[ 11.511012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 16:35:14.480041 <6>[ 11.511904] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10664 16:35:14.486858 <3>[ 11.520370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 16:35:14.493739 <6>[ 11.527892] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10666 16:35:14.503136 <3>[ 11.534067] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 16:35:14.510071 <3>[ 11.534074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 16:35:14.520008 <3>[ 11.534077] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 16:35:14.533703 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bu<6>[ 11.588294] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10670 16:35:14.539736 <6>[ 11.588765] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10671 16:35:14.549869 s System Message<6>[ 11.604944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10672 16:35:14.552915 Bus Socket.
10673 16:35:14.559933 <4>[ 11.614567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10674 16:35:14.566344 <6>[ 11.616902] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10675 16:35:14.576165 <6>[ 11.616966] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10676 16:35:14.582838 <6>[ 11.616975] remoteproc remoteproc0: remote processor scp is now up
10677 16:35:14.589642 <6>[ 11.625799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10678 16:35:14.599555 <3>[ 11.642382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 16:35:14.606472 <6>[ 11.646444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10680 16:35:14.616353 <4>[ 11.647973] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10681 16:35:14.619329 <4>[ 11.647973] Fallback method does not support PEC.
10682 16:35:14.629036 <3>[ 11.656773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 16:35:14.635867 <3>[ 11.663749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10684 16:35:14.645580 <3>[ 11.670536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 16:35:14.652551 <3>[ 11.670541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 16:35:14.662145 <3>[ 11.711893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 16:35:14.669272 <3>[ 11.725356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 16:35:14.678552 <3>[ 11.725366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 16:35:14.685506 <3>[ 11.725378] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 16:35:14.695234 <3>[ 11.725386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 16:35:14.702781 <6>[ 11.729481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10692 16:35:14.709063 [[0;32m OK [<4>[ 11.729590] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10693 16:35:14.719151 0m] Reached targ<4>[ 11.769697] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10694 16:35:14.729071 et [0;1;39msock<6>[ 11.774409] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10695 16:35:14.738992 ets.target[0m -<6>[ 11.774415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10696 16:35:14.739386 Socket Units.
10697 16:35:14.749400 <6>[ 11.774424] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10698 16:35:14.749792
10699 16:35:14.755741 <3>[ 11.812624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 16:35:14.765635 <6>[ 11.812670] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10701 16:35:14.772307 <3>[ 11.812756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 16:35:14.782282 <3>[ 11.837069] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10703 16:35:14.788960 <6>[ 11.837448] pci_bus 0000:00: root bus resource [bus 00-ff]
10704 16:35:14.798893 [[0;32m OK [0m] Reached target [0;1;39mbasi<6>[ 11.854880] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10705 16:35:14.811792 c.target[0m - B<6>[ 11.862825] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10706 16:35:14.812334 asic System.
10707 16:35:14.818359 <6>[ 11.874244] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10708 16:35:14.824988 <6>[ 11.881780] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10709 16:35:14.831942 <6>[ 11.889687] pci 0000:00:00.0: supports D1 D2
10710 16:35:14.838412 <6>[ 11.894283] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 16:35:14.841863 <6>[ 11.899331] mc: Linux media interface: v0.10
10712 16:35:14.849301 <6>[ 11.902407] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10713 16:35:14.859340 <3>[ 11.913934] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 16:35:14.871305 <6>[ 11.929975] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10715 16:35:14.881709 <6>[ 11.936319] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10716 16:35:14.887933 <6>[ 11.936339] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10717 16:35:14.894674 <6>[ 11.936354] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10718 16:35:14.900929 Startin<6>[ 11.936472] pci 0000:01:00.0: supports D1 D2
10719 16:35:14.911278 g [0;1;39mdbus.<6>[ 11.956133] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10720 16:35:14.917343 <6>[ 11.958786] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10721 16:35:14.920978 service[0m - D-Bus System Message Bus...
10722 16:35:14.938038 <6>[ 11.993697] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10723 16:35:14.944803 <6>[ 12.000637] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10724 16:35:14.951765 <6>[ 12.008724] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10725 16:35:14.961973 <6>[ 12.016732] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10726 16:35:14.968714 <3>[ 12.021739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 16:35:14.978555 <6>[ 12.024743] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10728 16:35:14.985296 <6>[ 12.024758] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10729 16:35:14.992418 <6>[ 12.049508] pci 0000:00:00.0: PCI bridge to [bus 01]
10730 16:35:14.998634 <6>[ 12.054726] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10731 16:35:15.005538 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10732 16:35:15.025842 <6>[ 12.084453] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10733 16:35:15.036325 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10734 16:35:15.046132 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10735 16:35:15.082753 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10736 16:35:15.109333 <3>[ 12.141627] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10737 16:35:15.123593 <6>[ 12.179034] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10738 16:35:15.135904 <6>[ 12.191350] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10739 16:35:15.142683 [[0;32m OK [<6>[ 12.200922] videodev: Linux video capture interface: v2.00
10740 16:35:15.152259 0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10741 16:35:15.184156 <6>[ 12.241975] Bluetooth: Core ver 2.22
10742 16:35:15.187307 <6>[ 12.245930] NET: Registered PF_BLUETOOTH protocol family
10743 16:35:15.193803 <6>[ 12.251500] Bluetooth: HCI device and connection manager initialized
10744 16:35:15.204443 <3>[ 12.252416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10745 16:35:15.207092 <6>[ 12.258341] Bluetooth: HCI socket layer initialized
10746 16:35:15.217870 <3>[ 12.267031] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10747 16:35:15.221522 <6>[ 12.272133] Bluetooth: L2CAP socket layer initialized
10748 16:35:15.231031 <3>[ 12.282668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 16:35:15.237726 <6>[ 12.286179] Bluetooth: SCO socket layer initialized
10750 16:35:15.244643 <6>[ 12.302572] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10751 16:35:15.252889 <6>[ 12.311285] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10752 16:35:15.280906 <4>[ 12.332199] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10753 16:35:15.284056 <6>[ 12.334074] usbcore: registered new interface driver btusb
10754 16:35:15.290672 <3>[ 12.342760] Bluetooth: hci0: Failed to load firmware file (-2)
10755 16:35:15.300568 <3>[ 12.348503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10756 16:35:15.306984 <6>[ 12.349311] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10757 16:35:15.313876 <3>[ 12.354571] Bluetooth: hci0: Failed to set up firmware (-2)
10758 16:35:15.323695 <4>[ 12.354574] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10759 16:35:15.330365 <6>[ 12.356120] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10760 16:35:15.336812 <6>[ 12.365169] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10761 16:35:15.347522 <5>[ 12.390616] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10762 16:35:15.360812 [[0;32m OK [<6>[ 12.411149] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10763 16:35:15.370449 0m] Started [0;<6>[ 12.412200] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10764 16:35:15.377735 <6>[ 12.424859] usbcore: registered new interface driver uvcvideo
10765 16:35:15.381405 1;39mgetty@tty1.service[0m - Getty on tty1.
10766 16:35:15.396849 <5>[ 12.452035] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10767 16:35:15.403213 <5>[ 12.459837] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10768 16:35:15.412965 <4>[ 12.468294] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10769 16:35:15.420009 [[0;32m OK [<6>[ 12.477647] cfg80211: failed to load regulatory.db
10770 16:35:15.426814 0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10771 16:35:15.444703 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10772 16:35:15.478154 <46>[ 12.520364] systemd-journald[181]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1538 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
10773 16:35:15.485026 <6>[ 12.530709] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10774 16:35:15.501603 <46>[ 12.541604] systemd-journald[181]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
10775 16:35:15.507648 <6>[ 12.549064] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10776 16:35:15.531756 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight..<6>[ 12.590487] mt7921e 0000:01:00.0: ASIC revision: 79610010
10777 16:35:15.532198 .
10778 16:35:15.555764 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10779 16:35:15.602265 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10780 16:35:15.622074 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10781 16:35:15.634679 <6>[ 12.689903] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10782 16:35:15.638081 <6>[ 12.689903]
10783 16:35:15.644453 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10784 16:35:15.663015 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10785 16:35:15.679607 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10786 16:35:15.723412 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10787 16:35:15.786972 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10788 16:35:15.807588 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10789 16:35:15.832467 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10790 16:35:15.878573
10791 16:35:15.882140 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10792 16:35:15.882224
10793 16:35:15.885273 debian-bookworm-arm64 login: root (automatic login)
10794 16:35:15.885348
10795 16:35:15.905165 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC <6>[ 12.960465] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10796 16:35:15.908256 2024 aarch64
10797 16:35:15.908333
10798 16:35:15.914802 The programs included with the Debian GNU/Linux system are free software;
10799 16:35:15.918075 the exact distribution terms for each program are described in the
10800 16:35:15.924440 individual files in /usr/share/doc/*/copyright.
10801 16:35:15.924517
10802 16:35:15.931483 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10803 16:35:15.931560 permitted by applicable law.
10804 16:35:15.931915 Matched prompt #10: / #
10806 16:35:15.932097 Setting prompt string to ['/ #']
10807 16:35:15.932184 end: 2.2.5.1 login-action (duration 00:00:14) [common]
10809 16:35:15.932360 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
10810 16:35:15.932443 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
10811 16:35:15.932511 Setting prompt string to ['/ #']
10812 16:35:15.932566 Forcing a shell prompt, looking for ['/ #']
10814 16:35:15.982786 / #
10815 16:35:15.982951 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10816 16:35:15.983028 Waiting using forced prompt support (timeout 00:02:30)
10817 16:35:15.988016
10818 16:35:15.988279 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10819 16:35:15.988368 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
10820 16:35:15.988454 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10821 16:35:15.988532 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
10822 16:35:15.988610 end: 2 depthcharge-action (duration 00:01:31) [common]
10823 16:35:15.988696 start: 3 lava-test-retry (timeout 00:08:04) [common]
10824 16:35:15.988781 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
10825 16:35:15.988850 Using namespace: common
10827 16:35:16.089170 / # #
10828 16:35:16.089356 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10829 16:35:16.094158 #
10830 16:35:16.094472 Using /lava-14396148
10832 16:35:16.194803 / # export SHELL=/bin/sh
10833 16:35:16.199645 export SHELL=/bin/sh
10835 16:35:16.300260 / # . /lava-14396148/environment
10836 16:35:16.305157 . /lava-14396148/environment
10838 16:35:16.405696 / # /lava-14396148/bin/lava-test-runner /lava-14396148/0
10839 16:35:16.405888 Test shell timeout: 10s (minimum of the action and connection timeout)
10840 16:35:16.410829 /lava-14396148/bin/lava-test-runner /lava-14396148/0
10841 16:35:16.436303 + export TESTRUN_ID=0_igt-kms-me<8>[ 13.494169] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14396148_1.5.2.3.1>
10842 16:35:16.436592 Received signal: <STARTRUN> 0_igt-kms-mediatek 14396148_1.5.2.3.1
10843 16:35:16.436669 Starting test lava.0_igt-kms-mediatek (14396148_1.5.2.3.1)
10844 16:35:16.436766 Skipping test definition patterns.
10845 16:35:16.439285 diatek
10846 16:35:16.442564 + cd /lava-14396148/0/tests/0_igt-kms-mediatek
10847 16:35:16.442643 + cat uuid
10848 16:35:16.446182 + UUID=14396148_1.5.2.3.1
10849 16:35:16.446324 + set +x
10850 16:35:16.466066 Received signal: <TESTSET> START core_auth
10851 16:35:16.466173 Starting test_set core_auth
10852 16:35:16.469000 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_lea<8>[ 13.526304] <LAVA_SIGNAL_TESTSET START core_auth>
10853 16:35:16.472603 k kms_prop_blob kms_setmode kms_vblank
10854 16:35:16.486021 <14>[ 13.544989] [IGT] core_auth: executing
10855 16:35:16.492744 IGT-Version: 1.2<14>[ 13.549329] [IGT] core_auth: starting subtest getclient-simple
10856 16:35:16.502581 8-ga44ebfe (aarc<14>[ 13.556943] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
10857 16:35:16.506355 h64) (Linux: 6.1<14>[ 13.565216] [IGT] core_auth: exiting, ret=0
10858 16:35:16.509358 .92-cip22 aarch64)
10859 16:35:16.512485 Using IGT_SRANDOM=1718642116 for randomisation
10860 16:35:16.522573 Starting sub<8>[ 13.577271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
10861 16:35:16.522962 test: getclient-simple
10862 16:35:16.523510 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
10864 16:35:16.526069 Opened device: /dev/dri/card0
10865 16:35:16.532428 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
10866 16:35:16.540846 <14>[ 13.599732] [IGT] core_auth: executing
10867 16:35:16.547379 IGT-Version: 1.2<14>[ 13.604070] [IGT] core_auth: starting subtest getclient-master-drop
10868 16:35:16.557513 8-ga44ebfe (aarc<14>[ 13.612117] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
10869 16:35:16.564108 h64) (Linux: 6.1<14>[ 13.620818] [IGT] core_auth: exiting, ret=0
10870 16:35:16.564567 .92-cip22 aarch64)
10871 16:35:16.567422 Using IGT_SRANDOM=1718642116 for randomisation
10872 16:35:16.577830 Starting sub<8>[ 13.632388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
10873 16:35:16.578505 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
10875 16:35:16.580716 test: getclient-master-drop
10876 16:35:16.584220 Opened device: /dev/dri/card0
10877 16:35:16.587203 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
10878 16:35:16.595935 <14>[ 13.654848] [IGT] core_auth: executing
10879 16:35:16.602676 IGT-Version: 1.2<14>[ 13.659223] [IGT] core_auth: starting subtest basic-auth
10880 16:35:16.609537 8-ga44ebfe (aarc<14>[ 13.666217] [IGT] core_auth: finished subtest basic-auth, SUCCESS
10881 16:35:16.615703 h64) (Linux: 6.1<14>[ 13.674010] [IGT] core_auth: exiting, ret=0
10882 16:35:16.619341 .92-cip22 aarch64)
10883 16:35:16.622543 Using IGT_SRANDOM=1718642116 for randomisation
10884 16:35:16.629232 Opened devic<8>[ 13.685464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
10885 16:35:16.629960 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
10887 16:35:16.632359 e: /dev/dri/card0
10888 16:35:16.635904 Starting subtest: basic-auth
10889 16:35:16.638946 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
10890 16:35:16.648400 <14>[ 13.707386] [IGT] core_auth: executing
10891 16:35:16.655169 IGT-Version: 1.2<14>[ 13.711784] [IGT] core_auth: starting subtest many-magics
10892 16:35:16.658277 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10893 16:35:16.668495 Using IGT_SR<14>[ 13.723811] [IGT] core_auth: finished subtest many-magics, SUCCESS
10894 16:35:16.671708 <14>[ 13.730891] [IGT] core_auth: exiting, ret=0
10895 16:35:16.674643 ANDOM=1718642116 for randomisation
10896 16:35:16.684848 Opened device: /dev/dri/card<8>[ 13.740761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
10897 16:35:16.685239 0
10898 16:35:16.685792 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
10900 16:35:16.688441 Starting subt<8>[ 13.748935] <LAVA_SIGNAL_TESTSET STOP>
10901 16:35:16.689185 Received signal: <TESTSET> STOP
10902 16:35:16.689526 Closing test_set core_auth
10903 16:35:16.691918 est: many-magics
10904 16:35:16.695088 Reopening device failed after 1020 opens
10905 16:35:16.698540 [1mSubtest many-magics: SUCCESS (0.005s)[0m
10906 16:35:16.747378 <14>[ 13.806698] [IGT] core_getclient: executing
10907 16:35:16.753976 IGT-Version: 1.2<14>[ 13.811804] [IGT] core_getclient: exiting, ret=0
10908 16:35:16.757642 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10909 16:35:16.767177 Using IGT_SRANDOM=1718642116<8>[ 13.823651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
10910 16:35:16.767465 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
10912 16:35:16.774418 <6>[ 13.825734] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10913 16:35:16.774520 for randomisation
10914 16:35:16.777261 Opened device: /dev/dri/card0
10915 16:35:16.780612 SUCCESS (0.006s)
10916 16:35:16.797544 <14>[ 13.856709] [IGT] core_getstats: executing
10917 16:35:16.804454 IGT-Version: 1.2<14>[ 13.861463] [IGT] core_getstats: exiting, ret=0
10918 16:35:16.807434 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10919 16:35:16.817513 Using IGT_SRANDOM=1718642116<8>[ 13.873758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
10920 16:35:16.818148 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
10922 16:35:16.820848 for randomisation
10923 16:35:16.821229 Opened device: /dev/dri/card0
10924 16:35:16.824055 SUCCESS (0.006s)
10925 16:35:16.854624 <14>[ 13.913327] [IGT] core_getversion: executing
10926 16:35:16.861213 IGT-Version: 1.2<14>[ 13.918239] [IGT] core_getversion: exiting, ret=0
10927 16:35:16.864405 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10928 16:35:16.874259 Using IGT_SR<8>[ 13.928990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
10929 16:35:16.874910 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
10931 16:35:16.877945 ANDOM=1718642116 for randomisation
10932 16:35:16.880909 Opened device: /dev/dri/card0
10933 16:35:16.881294 SUCCESS (0.006s)
10934 16:35:16.903029 <14>[ 13.961677] [IGT] core_setmaster_vs_auth: executing
10935 16:35:16.909270 IGT-Version: 1.2<14>[ 13.967308] [IGT] core_setmaster_vs_auth: exiting, ret=0
10936 16:35:16.915839 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10937 16:35:16.922524 Using IGT_SR<8>[ 13.978472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
10938 16:35:16.923271 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
10940 16:35:16.925500 ANDOM=1718642116 for randomisation
10941 16:35:16.929050 Opened device: /dev/dri/card0
10942 16:35:16.932406 SUCCESS (0.007s)
10943 16:35:16.942618 <8>[ 14.001709] <LAVA_SIGNAL_TESTSET START drm_read>
10944 16:35:16.943238 Received signal: <TESTSET> START drm_read
10945 16:35:16.943558 Starting test_set drm_read
10946 16:35:16.972058 <14>[ 14.030872] [IGT] drm_read: executing
10947 16:35:16.978784 IGT-Version: 1.2<14>[ 14.035734] [IGT] drm_read: exiting, ret=77
10948 16:35:16.982537 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10949 16:35:16.992077 Using IGT_SRANDOM=1718642116<8>[ 14.046730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
10950 16:35:16.992490 for randomisation
10951 16:35:16.993044 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
10953 16:35:16.995212 Opened device: /dev/dri/card0
10954 16:35:17.002029 No KMS driver or no outputs, pipes: 16, outputs: 0
10955 16:35:17.004917 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
10956 16:35:17.008393 <14>[ 14.068724] [IGT] drm_read: executing
10957 16:35:17.015078 IGT-Version: 1.2<14>[ 14.073147] [IGT] drm_read: exiting, ret=77
10958 16:35:17.018515 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10959 16:35:17.028397 Using IGT_SR<8>[ 14.083629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
10960 16:35:17.028830 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
10962 16:35:17.031476 ANDOM=1718642116 for randomisation
10963 16:35:17.031641 Opened device: /dev/dri/card0
10964 16:35:17.038121 No KMS driver or no outputs, pipes: 16, outputs: 0
10965 16:35:17.044830 [1mSubtest fault-buffer:<14>[ 14.103590] [IGT] drm_read: executing
10966 16:35:17.051596 SKIP (0.000s)[<14>[ 14.108355] [IGT] drm_read: exiting, ret=77
10967 16:35:17.052113 0m
10968 16:35:17.061466 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aa<8>[ 14.119389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
10969 16:35:17.062250 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
10971 16:35:17.065153 rch64)
10972 16:35:17.068283 Using IGT_SRANDOM=1718642116 for randomisation
10973 16:35:17.071326 Opened device: /dev/dri/card0
10974 16:35:17.075014 No KMS driver or no outputs, pipes: 16, outputs: 0
10975 16:35:17.078227 [1mSubtest empty-block: SKIP (0.000s)[0m
10976 16:35:17.090592 <14>[ 14.149345] [IGT] drm_read: executing
10977 16:35:17.096846 IGT-Version: 1.2<14>[ 14.154193] [IGT] drm_read: exiting, ret=77
10978 16:35:17.100606 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10979 16:35:17.110576 Using IGT_SRANDOM=1718642117 for randomisati<8>[ 14.166766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
10980 16:35:17.110963 on
10981 16:35:17.111497 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
10983 16:35:17.113678 Opened device: /dev/dri/card0
10984 16:35:17.120490 No KMS driver or no outputs, pipes: 16, outputs: 0
10985 16:35:17.123845 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
10986 16:35:17.132796 <14>[ 14.191456] [IGT] drm_read: executing
10987 16:35:17.139405 IGT-Version: 1.2<14>[ 14.195901] [IGT] drm_read: exiting, ret=77
10988 16:35:17.142595 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10989 16:35:17.152546 Using IGT_SRANDOM=1718642117<8>[ 14.207702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
10990 16:35:17.153085 for randomisation
10991 16:35:17.153804 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
10993 16:35:17.156133 Opened device: /dev/dri/card0
10994 16:35:17.162718 No KMS driver or no outputs, pipes: 16, outputs: 0
10995 16:35:17.165719 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
10996 16:35:17.179580 <14>[ 14.238769] [IGT] drm_read: executing
10997 16:35:17.186645 IGT-Version: 1.2<14>[ 14.243684] [IGT] drm_read: exiting, ret=77
10998 16:35:17.189513 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
10999 16:35:17.193108 Using IGT_SRANDOM=1718642117 for randomisation
11000 16:35:17.202690 Opened devic<8>[ 14.258318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11001 16:35:17.203043 e: /dev/dri/card0
11002 16:35:17.203521 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11004 16:35:17.209436 No KMS driver or no outputs, pipes: 16, outputs: 0
11005 16:35:17.212525 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11006 16:35:17.231939 <14>[ 14.290575] [IGT] drm_read: executing
11007 16:35:17.238053 IGT-Version: 1.2<14>[ 14.295423] [IGT] drm_read: exiting, ret=77
11008 16:35:17.241271 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11009 16:35:17.244607 Using IGT_SRANDOM=1718642117 for randomisation
11010 16:35:17.254646 Opened devic<8>[ 14.310146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11011 16:35:17.254931 e: /dev/dri/card0
11012 16:35:17.255332 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11014 16:35:17.261117 No KMS driver<8>[ 14.320062] <LAVA_SIGNAL_TESTSET STOP>
11015 16:35:17.261494 Received signal: <TESTSET> STOP
11016 16:35:17.261619 Closing test_set drm_read
11017 16:35:17.264483 or no outputs, pipes: 16, outputs: 0
11018 16:35:17.267725 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11019 16:35:17.292887 <8>[ 14.351425] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11020 16:35:17.293695 Received signal: <TESTSET> START kms_addfb_basic
11021 16:35:17.294060 Starting test_set kms_addfb_basic
11022 16:35:17.310475 <14>[ 14.369483] [IGT] kms_addfb_basic: executing
11023 16:35:17.323713 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<14>[ 14.378529] [IGT] kms_addfb_basic: starting subtest unused-handle
11024 16:35:17.324115 4)
11025 16:35:17.330550 Using IGT_SR<14>[ 14.386382] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11026 16:35:17.333765 ANDOM=1718642117 for randomisation
11027 16:35:17.336984 Opened device: /dev/dri/card0
11028 16:35:17.343671 Starting subtest: unused-hand<14>[ 14.402703] [IGT] kms_addfb_basic: exiting, ret=0
11029 16:35:17.344058 le
11030 16:35:17.350068 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11031 16:35:17.357120 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11033 16:35:17.360388 Test requirement not met in<8>[ 14.414807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11034 16:35:17.363278 function igt_require_intel, file ../lib/drmtest.c:880:
11035 16:35:17.366670 Test requirement: is_intel_device(fd)
11036 16:35:17.376627 Test requirement not met in function igt_require<14>[ 14.434874] [IGT] kms_addfb_basic: executing
11037 16:35:17.380034 _intel, file ../lib/drmtest.c:880:
11038 16:35:17.386569 Test requirement: is_intel_d<14>[ 14.444054] [IGT] kms_addfb_basic: starting subtest unused-pitches
11039 16:35:17.389982 evice(fd)
11040 16:35:17.396170 No KM<14>[ 14.451894] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11041 16:35:17.399715 S driver or no outputs, pipes: 16, outputs: 0
11042 16:35:17.409755 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 14.468309] [IGT] kms_addfb_basic: exiting, ret=0
11043 16:35:17.412726 92-cip22 aarch64)
11044 16:35:17.422771 Using IGT_SRANDOM=1718642117 for randomisatio<8>[ 14.478205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11045 16:35:17.423166 n
11046 16:35:17.423712 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11048 16:35:17.425994 Opened device: /dev/dri/card0
11049 16:35:17.430097 Starting subtest: unused-pitches
11050 16:35:17.433217 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11051 16:35:17.439422 Test requirement not met i<14>[ 14.498023] [IGT] kms_addfb_basic: executing
11052 16:35:17.445815 n function igt_require_intel, file ../lib/drmtest.c:880:
11053 16:35:17.452654 Test r<14>[ 14.508260] [IGT] kms_addfb_basic: starting subtest unused-offsets
11054 16:35:17.459134 equirement: is_i<14>[ 14.516213] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11055 16:35:17.462573 ntel_device(fd)
11056 16:35:17.475992 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 14.532897] [IGT] kms_addfb_basic: exiting, ret=0
11057 16:35:17.476467 80:
11058 16:35:17.478934 Test requirement: is_intel_device(fd)
11059 16:35:17.488846 No KMS driver or no outputs, pipes: <8>[ 14.544043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11060 16:35:17.489246 16, outputs: 0
11061 16:35:17.489851 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11063 16:35:17.495750 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11064 16:35:17.499189 Using IGT_SRANDOM=1718642117 for randomisation
11065 16:35:17.505517 Opened device: /dev/dri/card<14>[ 14.565118] [IGT] kms_addfb_basic: executing
11066 16:35:17.509041 0
11067 16:35:17.509432 Starting subtest: unused-offsets
11068 16:35:17.518865 [1mSubtest unused-offsets:<14>[ 14.575239] [IGT] kms_addfb_basic: starting subtest unused-modifier
11069 16:35:17.528408 SUCCESS (0.000s<14>[ 14.583408] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11070 16:35:17.528807 )[0m
11071 16:35:17.535347 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11072 16:35:17.542156 Test <14>[ 14.599823] [IGT] kms_addfb_basic: exiting, ret=0
11073 16:35:17.545276 requirement: is_intel_device(fd)
11074 16:35:17.555168 Test requirement not met in fu<8>[ 14.610895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11075 16:35:17.555807 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11077 16:35:17.558309 nction igt_require_intel, file ../lib/drmtest.c:880:
11078 16:35:17.562094 Test requirement: is_intel_device(fd)
11079 16:35:17.568911 No KMS driver or no outputs, pipes: 16, outputs: 0
11080 16:35:17.571716 IGT-Version: 1.<14>[ 14.630869] [IGT] kms_addfb_basic: executing
11081 16:35:17.578369 28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11082 16:35:17.585481 Using IGT_S<14>[ 14.641241] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11083 16:35:17.595062 RANDOM=171864211<14>[ 14.649612] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11084 16:35:17.595520 7 for randomisation
11085 16:35:17.598190 Opened device: /dev/dri/card0
11086 16:35:17.601918 Starting subtest: unused-modifier
11087 16:35:17.608165 [1mSubte<14>[ 14.666150] [IGT] kms_addfb_basic: exiting, ret=77
11088 16:35:17.611659 st unused-modifier: SUCCESS (0.000s)[0m
11089 16:35:17.621543 Test requirement not met in function i<8>[ 14.677526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11090 16:35:17.622298 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11092 16:35:17.628366 gt_require_intel, file ../lib/drmtest.c:880:
11093 16:35:17.631330 Test requirement: is_intel_device(fd)
11094 16:35:17.641433 Test requirement not met in function igt_require_intel, fil<14>[ 14.698904] [IGT] kms_addfb_basic: executing
11095 16:35:17.641824 e ../lib/drmtest.c:880:
11096 16:35:17.644704 Test requirement: is_intel_device(fd)
11097 16:35:17.654624 <14>[ 14.708171] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11098 16:35:17.664054 No KMS driver or<14>[ 14.717121] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11099 16:35:17.664521 no outputs, pipes: 16, outputs: 0
11100 16:35:17.677238 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aa<14>[ 14.734459] [IGT] kms_addfb_basic: exiting, ret=77
11101 16:35:17.677634 rch64)
11102 16:35:17.680844 Using IGT_SRANDOM=1718642117 for randomisation
11103 16:35:17.690683 Opened d<8>[ 14.744331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11104 16:35:17.691081 evice: /dev/dri/card0
11105 16:35:17.691629 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11107 16:35:17.694017 Starting subtest: clobberred-modifier
11108 16:35:17.707286 Test requirement not met in function igt_require_i915, file ../lib<14>[ 14.765044] [IGT] kms_addfb_basic: executing
11109 16:35:17.707682 /drmtest.c:885:
11110 16:35:17.710541 Test requirement: is_i915_device(fd)
11111 16:35:17.716927 [1mSubte<14>[ 14.774179] [IGT] kms_addfb_basic: starting subtest legacy-format
11112 16:35:17.720670 st clobberred-modifier: SKIP (0.000s)[0m
11113 16:35:17.730411 Test requirement not <14>[ 14.787355] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11114 16:35:17.737242 met in function igt_require_intel, file ../lib/drmtest.c:880:
11115 16:35:17.743134 Test requirement: is_intel_device<14>[ 14.802575] [IGT] kms_addfb_basic: exiting, ret=0
11116 16:35:17.743528 (fd)
11117 16:35:17.756669 Test requirement not met in function igt_require_intel, file ../lib/drmtes<8>[ 14.814000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11118 16:35:17.757302 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11120 16:35:17.760322 t.c:880:
11121 16:35:17.763490 Test requirement: is_intel_device(fd)
11122 16:35:17.766452 No KMS driver or no outputs, pipes: 16, outputs: 0
11123 16:35:17.776785 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 14.834598] [IGT] kms_addfb_basic: executing
11124 16:35:17.777172 : 6.1.92-cip22 aarch64)
11125 16:35:17.782945 Using IGT_SRANDOM=1718642117 for randomisation
11126 16:35:17.789554 Opened <14>[ 14.845904] [IGT] kms_addfb_basic: starting subtest no-handle
11127 16:35:17.796243 device: /dev/dri<14>[ 14.852844] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11128 16:35:17.796629 /card0
11129 16:35:17.802669 Starting subtest: invalid-smem-bo-on-discrete
11130 16:35:17.809182 Test requirement not met <14>[ 14.866797] [IGT] kms_addfb_basic: exiting, ret=0
11131 16:35:17.812695 in function igt_require_intel, file ../lib/drmtest.c:880:
11132 16:35:17.822451 Test <8>[ 14.877241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11133 16:35:17.823040 requirement: is_intel_device(fd)
11134 16:35:17.823841 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11136 16:35:17.828983 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11137 16:35:17.839085 Test requirement not met in function igt_require_intel, file ../li<14>[ 14.897778] [IGT] kms_addfb_basic: executing
11138 16:35:17.842486 b/drmtest.c:880:
11139 16:35:17.845266 Test requirement: is_intel_device(fd)
11140 16:35:17.852147 Test requirement not me<14>[ 14.910140] [IGT] kms_addfb_basic: starting subtest basic
11141 16:35:17.858918 t in function ig<14>[ 14.916747] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11142 16:35:17.865746 t_require_intel, file ../lib/drmtest.c:880:
11143 16:35:17.872313 Test requirement: is_intel_device(f<14>[ 14.930492] [IGT] kms_addfb_basic: exiting, ret=0
11144 16:35:17.872743 d)
11145 16:35:17.879033 No KMS driver or no outputs, pipes: 16, outputs: 0
11146 16:35:17.885065 IGT-Vers<8>[ 14.941872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11147 16:35:17.885708 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11149 16:35:17.888726 ion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11150 16:35:17.895299 Using IGT_SRANDOM=1718642117 for randomisation
11151 16:35:17.895692 Opened device: /dev/dri/card0
11152 16:35:17.902196 Starting subtest: leg<14>[ 14.961328] [IGT] kms_addfb_basic: executing
11153 16:35:17.905191 acy-format
11154 16:35:17.908682 Successfully fuzzed 10000 {bpp, depth} variations
11155 16:35:17.914960 [1mSubtest legac<14>[ 14.973441] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11156 16:35:17.925123 y-format: SUCCES<14>[ 14.980444] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11157 16:35:17.925689 S (0.005s)[0m
11158 16:35:17.937885 Test requirement not met in function igt_require_intel, file ../<14>[ 14.994874] [IGT] kms_addfb_basic: exiting, ret=0
11159 16:35:17.938307 lib/drmtest.c:880:
11160 16:35:17.941223 Test requirement: is_intel_device(fd)
11161 16:35:17.947708 Test <8>[ 15.006488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11162 16:35:17.948376 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11164 16:35:17.958392 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11165 16:35:17.961271 Test requirement: is_intel_device(fd)
11166 16:35:17.968020 No KMS driver or no output<14>[ 15.025913] [IGT] kms_addfb_basic: executing
11167 16:35:17.968547 s, pipes: 16, outputs: 0
11168 16:35:17.981390 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<14>[ 15.036909] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11169 16:35:17.981800 p22 aarch64)
11170 16:35:17.988020 Us<14>[ 15.044086] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11171 16:35:17.991118 ing IGT_SRANDOM=1718642117 for randomisation
11172 16:35:17.994943 Opened device: /dev/dri/card0
11173 16:35:18.001628 Sta<14>[ 15.058349] [IGT] kms_addfb_basic: exiting, ret=0
11174 16:35:18.002019 rting subtest: no-handle
11175 16:35:18.014314 [1mSubtest no-handle: SUCCESS (0.000s<8>[ 15.069876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11176 16:35:18.014713 )[0m
11177 16:35:18.015267 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11179 16:35:18.021035 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11180 16:35:18.024003 Test requirement: is_intel_device(fd)
11181 16:35:18.030826 Test requirement not met in fu<14>[ 15.090160] [IGT] kms_addfb_basic: executing
11182 16:35:18.037789 nction igt_require_intel, file ../lib/drmtest.c:880:
11183 16:35:18.044288 Test requirement: is_intel<14>[ 15.102192] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11184 16:35:18.047215 _device(fd)
11185 16:35:18.054038 No <14>[ 15.109159] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11186 16:35:18.056923 KMS driver or no outputs, pipes: 16, outputs: 0
11187 16:35:18.067218 IGT-Version: 1.28-ga44ebfe (aar<14>[ 15.123437] [IGT] kms_addfb_basic: exiting, ret=0
11188 16:35:18.070299 ch64) (Linux: 6.1.92-cip22 aarch64)
11189 16:35:18.076728 Using IGT_SRANDOM=171864211<8>[ 15.135036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11190 16:35:18.077355 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11192 16:35:18.080134 7 for randomisation
11193 16:35:18.083614 Opened device: /dev/dri/card0
11194 16:35:18.084046 Starting subtest: basic
11195 16:35:18.090106 [1mSubtest basic: SUCCESS (0.000s)[0m
11196 16:35:18.097084 Test requirement not met i<14>[ 15.154870] [IGT] kms_addfb_basic: executing
11197 16:35:18.100100 n function igt_require_intel, file ../lib/drmtest.c:880:
11198 16:35:18.109658 Test requirement: is_i<14>[ 15.166009] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11199 16:35:18.110119 ntel_device(fd)
11200 16:35:18.116695 <14>[ 15.173150] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11201 16:35:18.117248
11202 16:35:18.130177 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 15.187463] [IGT] kms_addfb_basic: exiting, ret=0
11203 16:35:18.130663 80:
11204 16:35:18.132975 Test requirement: is_intel_device(fd)
11205 16:35:18.142837 No KMS driver or no outputs, pipes: <8>[ 15.199358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11206 16:35:18.143482 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11208 16:35:18.146053 16, outputs: 0
11209 16:35:18.149918 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11210 16:35:18.156151 Using IGT_SRANDOM=1718642117 for randomisation
11211 16:35:18.163032 Opened device: /dev/dri/card<14>[ 15.220308] [IGT] kms_addfb_basic: executing
11212 16:35:18.163546 0
11213 16:35:18.165866 Starting subtest: bad-pitch-0
11214 16:35:18.169654 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11215 16:35:18.175959 <14>[ 15.232853] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11216 16:35:18.176334
11217 16:35:18.185667 Test requiremen<14>[ 15.239848] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11218 16:35:18.189061 t not met in function igt_require_intel, file ../lib/drmtest.c:880:
11219 16:35:18.195258 Test requir<14>[ 15.254316] [IGT] kms_addfb_basic: exiting, ret=0
11220 16:35:18.199054 ement: is_intel_device(fd)
11221 16:35:18.208581 Test requirement not met in function<8>[ 15.264904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11222 16:35:18.208861 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11224 16:35:18.211966 igt_require_intel, file ../lib/drmtest.c:880:
11225 16:35:18.215673 Test requirement: is_intel_device(fd)
11226 16:35:18.221987 No KMS driver or no outputs, pipes: 16, outputs: 0
11227 16:35:18.225185 IGT-V<14>[ 15.284683] [IGT] kms_addfb_basic: executing
11228 16:35:18.231811 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11229 16:35:18.238534 Using IGT_SRANDOM<14>[ 15.296742] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11230 16:35:18.248071 =1718642117 for <14>[ 15.304104] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11231 16:35:18.248173 randomisation
11232 16:35:18.251381 Opened device: /dev/dri/card0
11233 16:35:18.254848 Starting subtest: bad-pitch-32
11234 16:35:18.261521 [<14>[ 15.318424] [IGT] kms_addfb_basic: exiting, ret=0
11235 16:35:18.264336 1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11236 16:35:18.271215 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11238 16:35:18.274426 Test requirement n<8>[ 15.330192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11239 16:35:18.278163 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11240 16:35:18.281112 Test requirement: is_intel_device(fd)
11241 16:35:18.291319 Test requirement not met in function ig<14>[ 15.349836] [IGT] kms_addfb_basic: executing
11242 16:35:18.294071 t_require_intel, file ../lib/drmtest.c:880:
11243 16:35:18.304443 Test requirement: is_intel_device(f<14>[ 15.361077] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11244 16:35:18.304523 d)
11245 16:35:18.311087 No KMS drive<14>[ 15.368190] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11246 16:35:18.314108 r or no outputs, pipes: 16, outputs: 0
11247 16:35:18.323877 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<14>[ 15.382588] [IGT] kms_addfb_basic: exiting, ret=0
11248 16:35:18.327199 nux: 6.1.92-cip22 aarch64)
11249 16:35:18.331008 Using IGT_SRANDOM=1718642117 for randomisation
11250 16:35:18.337624 Open<8>[ 15.394586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11251 16:35:18.337885 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11253 16:35:18.340684 ed device: /dev/dri/card0
11254 16:35:18.343822 Starting subtest: bad-pitch-63
11255 16:35:18.347410 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11256 16:35:18.357128 Test requirement not met in function igt_require_inte<14>[ 15.415960] [IGT] kms_addfb_basic: executing
11257 16:35:18.360501 l, file ../lib/drmtest.c:880:
11258 16:35:18.363925 Test requirement: is_intel_device(fd)
11259 16:35:18.370504 Test requi<14>[ 15.427995] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11260 16:35:18.380015 rement not met i<14>[ 15.435171] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11261 16:35:18.383544 n function igt_require_intel, file ../lib/drmtest.c:880:
11262 16:35:18.390443 Test requirement: is_i<14>[ 15.449707] [IGT] kms_addfb_basic: exiting, ret=0
11263 16:35:18.393461 ntel_device(fd)
11264 16:35:18.403722 No KMS driver or no outputs, pipes: 16, outputs<8>[ 15.461222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11265 16:35:18.403843 : 0
11266 16:35:18.404087 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11268 16:35:18.410142 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11269 16:35:18.413162 Using IGT_SRANDOM=1718642118 for randomisation
11270 16:35:18.416716 Opened device: /dev/dri/card0
11271 16:35:18.423489 Starting<14>[ 15.481581] [IGT] kms_addfb_basic: executing
11272 16:35:18.426587 subtest: bad-pitch-128
11273 16:35:18.430201 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11274 16:35:18.440073 Test requirement not m<14>[ 15.495477] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11275 16:35:18.446622 et in function i<14>[ 15.502940] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11276 16:35:18.453225 gt_require_intel, file ../lib/drmtest.c:880:
11277 16:35:18.456382 Te<14>[ 15.515974] [IGT] kms_addfb_basic: exiting, ret=0
11278 16:35:18.459537 st requirement: is_intel_device(fd)
11279 16:35:18.469465 Test requirement not met in<8>[ 15.526782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11280 16:35:18.469779 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11282 16:35:18.476112 function igt_require_intel, file ../lib/drmtest.c:880:
11283 16:35:18.479458 Test requirement: is_intel_device(fd)
11284 16:35:18.482849 No KMS driver or no outputs, pipes: 16, outputs: 0
11285 16:35:18.489234 IGT-Version:<14>[ 15.547290] [IGT] kms_addfb_basic: executing
11286 16:35:18.492865 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11287 16:35:18.502305 Using IGT_SRANDOM=1718642118 for randomi<14>[ 15.561386] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11288 16:35:18.505963 sation
11289 16:35:18.512289 Opened d<14>[ 15.568380] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11290 16:35:18.515690 evice: /dev/dri/card0
11291 16:35:18.522153 Starting subtest: bad-pit<14>[ 15.581354] [IGT] kms_addfb_basic: exiting, ret=0
11292 16:35:18.522316 ch-256
11293 16:35:18.525946 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11294 16:35:18.535677 Test re<8>[ 15.592060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11295 16:35:18.535940 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11297 16:35:18.542480 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11298 16:35:18.545516 Test requirement: is_intel_device(fd)
11299 16:35:18.552286 Test requirement not met in function igt_req<14>[ 15.611993] [IGT] kms_addfb_basic: executing
11300 16:35:18.558391 uire_intel, file ../lib/drmtest.c:880:
11301 16:35:18.561981 Test requirement: is_intel_device(fd)
11302 16:35:18.569108 No KMS driver or <14>[ 15.626330] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11303 16:35:18.578477 no outputs, pipe<14>[ 15.633603] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11304 16:35:18.578603 s: 16, outputs: 0
11305 16:35:18.588516 IGT-Version: 1.28-ga44ebfe (a<14>[ 15.646671] [IGT] kms_addfb_basic: exiting, ret=0
11306 16:35:18.591877 arch64) (Linux: 6.1.92-cip22 aarch64)
11307 16:35:18.602148 Using IGT_SRANDOM=1718642<8>[ 15.657562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11308 16:35:18.602495 118 for randomisation
11309 16:35:18.602945 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11311 16:35:18.605464 Opened device: /dev/dri/card0
11312 16:35:18.608378 Starting subtest: bad-pitch-1024
11313 16:35:18.612281 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11314 16:35:18.618489 Test r<14>[ 15.677770] [IGT] kms_addfb_basic: executing
11315 16:35:18.625181 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11316 16:35:18.631988 Test requirement: <14>[ 15.690609] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11317 16:35:18.642053 is_intel_device(<14>[ 15.697593] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11318 16:35:18.642552 fd)
11319 16:35:18.651735 Test requirement not met in function igt_re<14>[ 15.710382] [IGT] kms_addfb_basic: exiting, ret=0
11320 16:35:18.655355 quire_intel, file ../lib/drmtest.c:880:
11321 16:35:18.658563 Test requirement: is_intel_device(fd)
11322 16:35:18.665239 <8>[ 15.721391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11323 16:35:18.665868 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11325 16:35:18.671258 No KMS driver or no outputs, pipes: 16, outputs: 0
11326 16:35:18.678064 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11327 16:35:18.684847 Using IGT_SRANDOM=1718642118 for randomi<14>[ 15.742747] [IGT] kms_addfb_basic: executing
11328 16:35:18.685238 sation
11329 16:35:18.688183 Opened device: /dev/dri/card0
11330 16:35:18.691386 Starting subtest: bad-pitch-999
11331 16:35:18.694377 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11332 16:35:18.701035 Test re<14>[ 15.758760] [IGT] kms_addfb_basic: starting subtest master-rmfb
11333 16:35:18.710844 quirement not me<14>[ 15.766256] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11334 16:35:18.717546 t in function igt_require_intel,<14>[ 15.776588] [IGT] kms_addfb_basic: exiting, ret=0
11335 16:35:18.721135 file ../lib/drmtest.c:880:
11336 16:35:18.728076 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11338 16:35:18.730731 Test requirement: i<8>[ 15.786523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11339 16:35:18.731118 s_intel_device(fd)
11340 16:35:18.737935 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11341 16:35:18.740912 Test requirement: is_intel_device(fd)
11342 16:35:18.747431 No KMS driver or <14>[ 15.806128] [IGT] kms_addfb_basic: executing
11343 16:35:18.751015 no outputs, pipes: 16, outputs: 0
11344 16:35:18.757445 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11345 16:35:18.767585 Using IGT_SRANDOM=1718642118 for randomis<14>[ 15.823923] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11346 16:35:18.767973 ation
11347 16:35:18.777273 Opened de<14>[ 15.832292] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11348 16:35:18.783941 vice: /dev/dri/c<14>[ 15.841982] [IGT] kms_addfb_basic: exiting, ret=0
11349 16:35:18.784308 ard0
11350 16:35:18.787033 Starting subtest: bad-pitch-65536
11351 16:35:18.797275 [1mSubtest bad-pitch-6<8>[ 15.852431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11352 16:35:18.797906 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11354 16:35:18.800647 5536: SUCCESS (0.000s)[0m
11355 16:35:18.807341 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11356 16:35:18.810263 Test requirement: is_intel_device(fd)
11357 16:35:18.816819 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11358 16:35:18.820078 Test requirement: is_intel_device(fd)
11359 16:35:18.827188 No KMS driver <14>[ 15.885595] [IGT] kms_addfb_basic: executing
11360 16:35:18.830108 or no outputs, pipes: 16, outputs: 0
11361 16:35:18.836675 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11362 16:35:18.840219 Using IGT_SRANDOM=1718642118 for randomisation
11363 16:35:18.849766 Opened device: /dev/dr<14>[ 15.905395] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11364 16:35:18.850322 i/card0
11365 16:35:18.853490 Starting subtest: invalid-get-prop-any
11366 16:35:18.860088 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11367 16:35:18.866381 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11368 16:35:18.869840 Test requirement: is_intel_device(fd)
11369 16:35:18.876646 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11370 16:35:18.879869 Test requirement: is_intel_device(fd)
11371 16:35:18.886489 No KMS driver or no outputs, pipes: 16, outputs: 0
11372 16:35:18.889435 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11373 16:35:18.896407 Using IGT_SRANDOM=1718642118 for randomisation
11374 16:35:18.896795 Opened device: /dev/dri/card0
11375 16:35:18.899617 Starting subtest: invalid-get-prop
11376 16:35:18.906516 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11377 16:35:18.912712 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11378 16:35:18.916649 Test requirement: is_intel_device(fd)
11379 16:35:18.923071 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11380 16:35:18.926200 Test requirement: is_intel_device(fd)
11381 16:35:18.932846 No KMS driver or no outputs, pipes: 16, outputs: 0
11382 16:35:18.935925 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11383 16:35:18.942809 Using IGT_SRANDOM=1718642118 for randomisation
11384 16:35:18.943295 Opened device: /dev/dri/card0
11385 16:35:18.945952 Starting subtest: invalid-set-prop-any
11386 16:35:18.952698 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11387 16:35:18.959041 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11388 16:35:18.962060 Test requirement: is_intel_device(fd)
11389 16:35:18.968879 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11390 16:35:18.972539 Test requirement: is_intel_device(fd)
11391 16:35:18.978996 No KMS driver or no outputs, pipes: 16, outputs: 0
11392 16:35:18.985137 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11393 16:35:18.988764 Using IGT_SRANDOM=1718642118 for randomisation
11394 16:35:18.991961 Opened device: /dev/dri/card0
11395 16:35:18.995513 Starting subtest: invalid-set-prop
11396 16:35:18.998634 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11397 16:35:19.005155 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11398 16:35:19.008642 Test requirement: is_intel_device(fd)
11399 16:35:19.014867 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11400 16:35:19.018465 Test requirement: is_intel_device(fd)
11401 16:35:19.025071 No KMS driver or no outputs, pipes: 16, outputs: 0
11402 16:35:19.031788 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11403 16:35:19.034761 Using IGT_SRANDOM=1718642118 for randomisation
11404 16:35:19.037815 Opened device: /dev/dri/card0
11405 16:35:19.038179 Starting subtest: master-rmfb
11406 16:35:19.045047 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11407 16:35:19.051897 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11408 16:35:19.054825 Test requirement: is_intel_device(fd)
11409 16:35:19.061052 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11410 16:35:19.064799 Test requirement: is_intel_device(fd)
11411 16:35:19.071165 No KMS driver or no outputs, pipes: 16, outputs: 0
11412 16:35:19.074415 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11413 16:35:19.081269 Using IGT_SRANDOM=1718642118 for randomisation
11414 16:35:19.081962 Opened device: /dev/dri/card0
11415 16:35:19.087358 Starting subtest: addfb25-modifier-no-flag
11416 16:35:19.091422 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11417 16:35:19.097327 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11418 16:35:19.100957 Test requirement: is_intel_device(fd)
11419 16:35:19.110754 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11420 16:35:19.113809 Test requirement: is_intel_device(fd)
11421 16:35:19.117289 No KMS driver or no outputs, pipes: 16, outputs: 0
11422 16:35:19.124325 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11423 16:35:19.127156 Using IGT_SRANDOM=1718642118 for randomisation
11424 16:35:19.130301 Opened device: /dev/dri/card0
11425 16:35:19.133768 Starting subtest: addfb25-bad-modifier
11426 16:35:19.143730 (kms_addfb_basic:430) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11427 16:35:19.159823 (kms_addfb_basic:430) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11428 16:35:19.166292 (kms_addfb_basic:430) CRITICAL: error: 0 != -1
11429 16:35:19.166359 Stack trace:
11430 16:35:19.169587 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11431 16:35:19.172879 #1 [<unknown>+0xc76b4358]
11432 16:35:19.176200 #2 [<unknown>+0xc76b5fbc]
11433 16:35:19.179549 #3 [<unknown>+0xc76b156c]
11434 16:35:19.179627 #4 [__libc_init_first+0x80]
11435 16:35:19.183051 #5 [__libc_start_main+0x98]
11436 16:35:19.186441 #6 [<unknown>+0xc76b15b0]
11437 16:35:19.189609 Subtest addfb25-bad-modifier failed.
11438 16:35:19.189685 **** DEBUG ****
11439 16:35:19.199605 (kms_addfb_basic<14>[ 16.255893] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11440 16:35:19.205909 :430) ioctl_wrap<14>[ 16.264995] [IGT] kms_addfb_basic: exiting, ret=98
11441 16:35:19.212601 pers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11442 16:35:19.222347 (kms_addfb_basic:<8>[ 16.277590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11443 16:35:19.222600 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11445 16:35:19.229283 430) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11446 16:35:19.242248 (kms_addfb_basic:430) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U)<14>[ 16.299935] [IGT] kms_addfb_basic: executing
11447 16:35:19.252143 << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11448 16:35:19.259059 (kms_addfb_bas<14>[ 16.317897] [IGT] kms_addfb_basic: exiting, ret=77
11449 16:35:19.262119 ic:430) CRITICAL: error: 0 != -1
11450 16:35:19.275098 (kms_addfb_basic:430) igt_core-INFO: Stack tra<8>[ 16.329447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11451 16:35:19.275195 ce:
11452 16:35:19.275435 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11454 16:35:19.281780 (kms_addfb_basic:430) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11455 16:35:19.288439 (kms_addfb_basic:430) igt_core-INFO: #1 [<unknown>+0xc76b4358]
11456 16:35:19.291691 (km<14>[ 16.352360] [IGT] kms_addfb_basic: executing
11457 16:35:19.298542 s_addfb_basic:430) igt_core-INFO: #2 [<unknown>+0xc76b5fbc]
11458 16:35:19.305183 (kms_addfb_basic:430) igt_core-INFO: #3 [<unknown>+0xc76b156c]
11459 16:35:19.311376 (kms_addfb_basi<14>[ 16.369648] [IGT] kms_addfb_basic: exiting, ret=77
11460 16:35:19.315027 c:430) igt_core-INFO: #4 [__libc_init_first+0x80]
11461 16:35:19.324969 (kms_addfb_basic:430) igt_c<8>[ 16.381613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11462 16:35:19.325209 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11464 16:35:19.328638 ore-INFO: #5 [__libc_start_main+0x98]
11465 16:35:19.334693 (kms_addfb_basic:430) igt_core-INFO: #6 [<unknown>+0xc76b15b0]
11466 16:35:19.334788 **** END ****
11467 16:35:19.344664 [1mSubtest addfb25-bad-modifier: FA<14>[ 16.403818] [IGT] kms_addfb_basic: executing
11468 16:35:19.344787 IL (0.342s)[0m
11469 16:35:19.351353 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11470 16:35:19.355092 Test requirement: is_intel_device(fd)
11471 16:35:19.361353 Test<14>[ 16.420893] [IGT] kms_addfb_basic: exiting, ret=77
11472 16:35:19.368228 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11473 16:35:19.378094 <8>[ 16.432678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11474 16:35:19.378359 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11476 16:35:19.381199 Test requirement: is_intel_device(fd)
11477 16:35:19.384420 No KMS driver or no outputs, pipes: 16, outputs: 0
11478 16:35:19.391294 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11479 16:35:19.397463 U<14>[ 16.455942] [IGT] kms_addfb_basic: executing
11480 16:35:19.401062 sing IGT_SRANDOM=1718642119 for randomisation
11481 16:35:19.404361 Opened device: /dev/dri/card0
11482 16:35:19.414097 Test requirement not met in function igt_require_intel, file ../li<14>[ 16.472872] [IGT] kms_addfb_basic: exiting, ret=77
11483 16:35:19.414201 b/drmtest.c:880:
11484 16:35:19.417827 Test requirement: is_intel_device(fd)
11485 16:35:19.427179 [1mSubtest addfb25-x-t<8>[ 16.484598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11486 16:35:19.427432 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11488 16:35:19.430797 iled-mismatch-legacy: SKIP (0.000s)[0m
11489 16:35:19.440607 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11490 16:35:19.444286 Test requirement: is_intel_device(fd)
11491 16:35:19.447329 No KMS drive<14>[ 16.507222] [IGT] kms_addfb_basic: executing
11492 16:35:19.450699 r or no outputs, pipes: 16, outputs: 0
11493 16:35:19.457120 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11494 16:35:19.467050 Using IGT_SRANDOM=1718642119 for ran<14>[ 16.525193] [IGT] kms_addfb_basic: exiting, ret=77
11495 16:35:19.467127 domisation
11496 16:35:19.470157 Opened device: /dev/dri/card0
11497 16:35:19.480133 Test requirement not met in function <8>[ 16.536686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11498 16:35:19.480404 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11500 16:35:19.486913 igt_require_intel, file ../lib/drmtest.c:880:
11501 16:35:19.489904 Test requirement: is_intel_device(fd)
11502 16:35:19.493697 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11503 16:35:19.499805 Test requirement no<14>[ 16.559179] [IGT] kms_addfb_basic: executing
11504 16:35:19.506568 t met in function igt_require_intel, file ../lib/drmtest.c:880:
11505 16:35:19.509829 Test requirement: is_intel_device(fd)
11506 16:35:19.516745 No KMS driver or no outputs, pipes: 16, <14>[ 16.576630] [IGT] kms_addfb_basic: exiting, ret=77
11507 16:35:19.519566 outputs: 0
11508 16:35:19.523178 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11509 16:35:19.532882 <8>[ 16.588025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11510 16:35:19.533139 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11512 16:35:19.536317 Using IGT_SRANDOM=1718642119 for randomisation
11513 16:35:19.539327 Opened device: /dev/dri/card0
11514 16:35:19.546766 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11515 16:35:19.552930 Test requirem<14>[ 16.610596] [IGT] kms_addfb_basic: executing
11516 16:35:19.553041 ent: is_intel_device(fd)
11517 16:35:19.559785 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11518 16:35:19.569763 Test requirement not met in function igt_require_int<14>[ 16.628884] [IGT] kms_addfb_basic: exiting, ret=77
11519 16:35:19.572734 el, file ../lib/drmtest.c:880:
11520 16:35:19.576088 Test requirement: is_intel_device(fd)
11521 16:35:19.582944 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11523 16:35:19.585957 No KMS dr<8>[ 16.640572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11524 16:35:19.589565 iver or no outputs, pipes: 16, outputs: 0
11525 16:35:19.592964 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11526 16:35:19.599840 Using IGT_SRANDOM=1718642119 for randomisation
11527 16:35:19.602769 O<14>[ 16.662771] [IGT] kms_addfb_basic: executing
11528 16:35:19.606066 pened device: /dev/dri/card0
11529 16:35:19.612713 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11530 16:35:19.622735 Test requirement: is_intel_dev<14>[ 16.679737] [IGT] kms_addfb_basic: exiting, ret=77
11531 16:35:19.623147 ice(fd)
11532 16:35:19.635863 Test requirement not met in function igt_require_intel, file ../lib/drm<8>[ 16.691471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11533 16:35:19.636283 test.c:880:
11534 16:35:19.636926 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11536 16:35:19.639234 Test requirement: is_intel_device(fd)
11537 16:35:19.642738 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11538 16:35:19.649265 No KMS driver or no outputs, pipes: 16, outputs: 0
11539 16:35:19.652365 IGT<14>[ 16.712558] [IGT] kms_addfb_basic: executing
11540 16:35:19.659094 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11541 16:35:19.662195 Using IGT_SRANDOM=1718642119 for randomisation
11542 16:35:19.666166 Opened device: /dev/dri/card0
11543 16:35:19.672539 <14>[ 16.729824] [IGT] kms_addfb_basic: exiting, ret=77
11544 16:35:19.685113 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<8>[ 16.740738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11545 16:35:19.685526 0:
11546 16:35:19.686189 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11548 16:35:19.688870 Test requirement: is_intel_device(fd)
11549 16:35:19.695183 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11550 16:35:19.701993 Test requirement: is_intel_device<14>[ 16.761768] [IGT] kms_addfb_basic: executing
11551 16:35:19.704871 (fd)
11552 16:35:19.708635 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11553 16:35:19.711657 No KMS driver or no outputs, pipes: 16, outputs: 0
11554 16:35:19.722133 IGT-Version: 1.28-ga44ebfe (<14>[ 16.779334] [IGT] kms_addfb_basic: exiting, ret=77
11555 16:35:19.725425 aarch64) (Linux: 6.1.92-cip22 aarch64)
11556 16:35:19.734931 Using IGT_SRANDOM=1718642119 for randomi<8>[ 16.791059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11557 16:35:19.735384 sation
11558 16:35:19.736036 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11560 16:35:19.738304 Opened device: /dev/dri/card0
11561 16:35:19.745152 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11562 16:35:19.751599 Test requirement: is_intel_device(fd)<14>[ 16.811063] [IGT] kms_addfb_basic: executing
11563 16:35:19.755157
11564 16:35:19.761280 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11565 16:35:19.764936 Test requirement: is_intel_device(fd)
11566 16:35:19.771013 [1mSubtest tile-pi<14>[ 16.829261] [IGT] kms_addfb_basic: exiting, ret=77
11567 16:35:19.774787 tch-mismatch: SKIP (0.000s)[0m
11568 16:35:19.784221 No KMS driver or no outputs, pipes: 16, outputs<8>[ 16.840594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11569 16:35:19.784303 : 0
11570 16:35:19.784550 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11572 16:35:19.790830 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11573 16:35:19.793775 Using IGT_SRANDOM=1718642119 for randomisation
11574 16:35:19.797625 Opened device: /dev/dri/card0
11575 16:35:19.803868 Test req<14>[ 16.862232] [IGT] kms_addfb_basic: executing
11576 16:35:19.810687 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11577 16:35:19.813788 Test requirement: is_intel_device(fd)
11578 16:35:19.820834 Test requirement not met in f<14>[ 16.879481] [IGT] kms_addfb_basic: exiting, ret=77
11579 16:35:19.824058 unction igt_require_intel, file ../lib/drmtest.c:880:
11580 16:35:19.834205 Test requirement: is_inte<8>[ 16.891108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11581 16:35:19.834444 l_device(fd)
11582 16:35:19.834807 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11584 16:35:19.840178 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11585 16:35:19.843678 No KMS driver or no outputs, pipes: 16, outputs: 0
11586 16:35:19.853912 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<14>[ 16.911856] [IGT] kms_addfb_basic: executing
11587 16:35:19.854320 ux: 6.1.92-cip22 aarch64)
11588 16:35:19.860905 Using IGT_SRANDOM=1718642119 for randomisation
11589 16:35:19.863765 Opened device: /dev/dri/card0
11590 16:35:19.870881 Test requirement not met in function i<14>[ 16.929417] [IGT] kms_addfb_basic: exiting, ret=77
11591 16:35:19.873797 gt_require_intel, file ../lib/drmtest.c:880:
11592 16:35:19.886863 Test requirement: is_intel_device(<8>[ 16.940899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11593 16:35:19.887303 fd)
11594 16:35:19.887848 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11596 16:35:19.893581 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11597 16:35:19.896949 Test requirement: is_intel_device(fd)
11598 16:35:19.903351 No KMS driver or no outputs, pip<14>[ 16.963690] [IGT] kms_addfb_basic: executing
11599 16:35:19.906683 es: 16, outputs: 0
11600 16:35:19.910159 [1mSubtest size-max: SKIP (0.000s)[0m
11601 16:35:19.916779 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11602 16:35:19.923356 Using IGT_SRAND<14>[ 16.981139] [IGT] kms_addfb_basic: exiting, ret=77
11603 16:35:19.926557 OM=1718642119 for randomisation
11604 16:35:19.926953 Opened device: /dev/dri/card0
11605 16:35:19.936406 <8>[ 16.991703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11606 16:35:19.937044 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11608 16:35:19.943781 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11609 16:35:19.946734 Test requirement: is_intel_device(fd)
11610 16:35:19.953338 Test requirement not <14>[ 17.012007] [IGT] kms_addfb_basic: executing
11611 16:35:19.959764 met in function igt_require_intel, file ../lib/drmtest.c:880:
11612 16:35:19.963309 Test requirement: is_intel_device(fd)
11613 16:35:19.969692 No KMS driver or no outputs, pipes: 16, ou<14>[ 17.029092] [IGT] kms_addfb_basic: exiting, ret=77
11614 16:35:19.970086 tputs: 0
11615 16:35:19.976459 [1mSubtest too-wide: SKIP (0.000s)[0m
11616 16:35:19.986195 IGT-Version: 1.28-ga44ebfe (a<8>[ 17.040807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11617 16:35:19.986898 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11619 16:35:19.990197 arch64) (Linux: 6.1.92-cip22 aarch64)
11620 16:35:19.993338 Using IGT_SRANDOM=1718642119 for randomisation
11621 16:35:19.996455 Opened device: /dev/dri/card0
11622 16:35:20.002801 Test requirement not met in function igt_r<14>[ 17.063072] [IGT] kms_addfb_basic: executing
11623 16:35:20.005885 equire_intel, file ../lib/drmtest.c:880:
11624 16:35:20.009741 Test requirement: is_intel_device(fd)
11625 16:35:20.022948 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 17.080720] [IGT] kms_addfb_basic: exiting, ret=77
11626 16:35:20.023398 80:
11627 16:35:20.025830 Test requirement: is_intel_device(fd)
11628 16:35:20.039418 No KMS driver or no outputs, pipes: <8>[ 17.092930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11629 16:35:20.039816 16, outputs: 0
11630 16:35:20.040362 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11632 16:35:20.042267 [1mSubtest too-high: SKIP (0.000s)[0m
11633 16:35:20.049256 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11634 16:35:20.055464 Using IGT_SRANDOM=1718642119 for ra<14>[ 17.115169] [IGT] kms_addfb_basic: executing
11635 16:35:20.059147 ndomisation
11636 16:35:20.062124 Opened device: /dev/dri/card0
11637 16:35:20.068646 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11638 16:35:20.075632 Test requirement<14>[ 17.133190] [IGT] kms_addfb_basic: exiting, ret=77
11639 16:35:20.076020 : is_intel_device(fd)
11640 16:35:20.088450 Test requirement not met in function igt_require_intel, f<8>[ 17.144989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11641 16:35:20.089125 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11643 16:35:20.091843 ile ../lib/drmtest.c:880:
11644 16:35:20.095264 Test <8>[ 17.154683] <LAVA_SIGNAL_TESTSET STOP>
11645 16:35:20.095879 Received signal: <TESTSET> STOP
11646 16:35:20.096190 Closing test_set kms_addfb_basic
11647 16:35:20.098537 requirement: is_intel_device(fd)
11648 16:35:20.101755 No KMS driver or no outputs, pipes: 16, outputs: 0
11649 16:35:20.108439 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11650 16:35:20.111482 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11651 16:35:20.118724 Using IGT_SRANDOM=1718642119 for randomisation
11652 16:35:20.119158 Opened device: /dev/dri/card0
11653 16:35:20.127924 Test requirement not met in function igt_r<8>[ 17.187538] <LAVA_SIGNAL_TESTSET START kms_atomic>
11654 16:35:20.128559 Received signal: <TESTSET> START kms_atomic
11655 16:35:20.128879 Starting test_set kms_atomic
11656 16:35:20.131263 equire_intel, file ../lib/drmtest.c:880:
11657 16:35:20.134594 Test requirement: is_intel_device(fd)
11658 16:35:20.141410 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11659 16:35:20.144412 Test requirement: is_intel_device(fd)
11660 16:35:20.150826 No KMS driver or no outputs, pipes: 16, outputs: 0
11661 16:35:20.157427 [1mSubtest smal<14>[ 17.215034] [IGT] kms_atomic: executing
11662 16:35:20.160817 l-bo: SKIP (0.00<14>[ 17.221057] [IGT] kms_atomic: exiting, ret=77
11663 16:35:20.164398 0s)[0m
11664 16:35:20.167565 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11665 16:35:20.177528 Using IGT_SRANDOM=1<8>[ 17.234193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11666 16:35:20.177942 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11668 16:35:20.181095 718642119 for randomisation
11669 16:35:20.183940 Opened device: /dev/dri/card0
11670 16:35:20.190875 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11671 16:35:20.197976 Test requirement<14>[ 17.256389] [IGT] kms_atomic: executing
11672 16:35:20.203958 : is_intel_devic<14>[ 17.261143] [IGT] kms_atomic: exiting, ret=77
11673 16:35:20.204286 e(fd)
11674 16:35:20.217439 Test requirement not met in function igt_require_intel, f<8>[ 17.271182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11675 16:35:20.217839 ile ../lib/drmtest.c:880:
11676 16:35:20.218383 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11678 16:35:20.220638 Test requirement: is_intel_device(fd)
11679 16:35:20.227391 No KMS driver or no outputs, pipes: 16, outputs: 0
11680 16:35:20.230448 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11681 16:35:20.237136 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11682 16:35:20.243768 Using IGT_SRANDOM=1718642119 for randomisat<14>[ 17.304535] [IGT] kms_atomic: executing
11683 16:35:20.246899 ion
11684 16:35:20.250693 Opened devi<14>[ 17.310127] [IGT] kms_atomic: exiting, ret=77
11685 16:35:20.253502 ce: /dev/dri/card0
11686 16:35:20.266391 Test requirement not met in function igt_require_intel, file<8>[ 17.321040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11687 16:35:20.266643 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11689 16:35:20.270150 ../lib/drmtest.c:880:
11690 16:35:20.272953 Test requirement: is_intel_device(fd)
11691 16:35:20.279951 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11692 16:35:20.286585 Test requirem<14>[ 17.343903] [IGT] kms_atomic: executing
11693 16:35:20.289658 ent: is_intel_de<14>[ 17.349782] [IGT] kms_atomic: exiting, ret=77
11694 16:35:20.292871 vice(fd)
11695 16:35:20.296695 No KMS driver or no outputs, pipes: 16, outputs: 0
11696 16:35:20.306513 [1mSubtest addfb2<8>[ 17.361627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11697 16:35:20.306861 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11699 16:35:20.309594 5-y-tiled-legacy: SKIP (0.000s)[0m
11700 16:35:20.316381 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11701 16:35:20.319509 Using IGT_SRANDOM=1718642119 for randomisation
11702 16:35:20.322549 Opened <14>[ 17.383934] [IGT] kms_atomic: executing
11703 16:35:20.329250 device: /dev/dri<14>[ 17.388742] [IGT] kms_atomic: exiting, ret=77
11704 16:35:20.329481 /card0
11705 16:35:20.342837 Test requirement not met in function igt_require_intel, <8>[ 17.399683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11706 16:35:20.343484 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11708 16:35:20.345986 file ../lib/drmtest.c:880:
11709 16:35:20.349603 Test requirement: is_intel_device(fd)
11710 16:35:20.359019 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<14>[ 17.419145] [IGT] kms_atomic: executing
11711 16:35:20.359416 :880:
11712 16:35:20.365740 Test requ<14>[ 17.423906] [IGT] kms_atomic: exiting, ret=77
11713 16:35:20.369429 irement: is_intel_device(fd)
11714 16:35:20.379103 No KMS driver or no outputs, pipes: 16, outputs: 0<8>[ 17.435642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11715 16:35:20.379502
11716 16:35:20.380043 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11718 16:35:20.385611 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11719 16:35:20.392572 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11720 16:35:20.395690 Using IGT_SRANDOM=1718642119 for randomisation
11721 16:35:20.398590 Op<14>[ 17.458174] [IGT] kms_atomic: executing
11722 16:35:20.405355 ened device: /de<14>[ 17.464047] [IGT] kms_atomic: exiting, ret=77
11723 16:35:20.405743 v/dri/card0
11724 16:35:20.419056 Test requirement not met in function igt_require_in<8>[ 17.475148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11725 16:35:20.419689 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11727 16:35:20.422317 tel, file ../lib/drmtest.c:880:
11728 16:35:20.427544 Test requirement: is_intel_device(fd)
11729 16:35:20.432127 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11730 16:35:20.437843 Test<14>[ 17.495884] [IGT] kms_atomic: executing
11731 16:35:20.441486 requirement: is<14>[ 17.501703] [IGT] kms_atomic: exiting, ret=77
11732 16:35:20.444680 _intel_device(fd)
11733 16:35:20.447997 No KMS driver or no outputs, pipes: 16, outputs: 0
11734 16:35:20.457621 [1mSubte<8>[ 17.513033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11735 16:35:20.457974 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11737 16:35:20.461464 st addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11738 16:35:20.468024 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11739 16:35:20.474374 Using IGT_SRANDOM=1718642120 for randomi<14>[ 17.535750] [IGT] kms_atomic: executing
11740 16:35:20.477703 sation
11741 16:35:20.481247 Opened d<14>[ 17.540981] [IGT] kms_atomic: exiting, ret=77
11742 16:35:20.484490 evice: /dev/dri/card0
11743 16:35:20.497384 Test requirement not met in function igt_require_intel, f<8>[ 17.552762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11744 16:35:20.497717 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11746 16:35:20.501045 ile ../lib/drmtest.c:880:
11747 16:35:20.504501 Test requirement: is_intel_device(fd)
11748 16:35:20.510740 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11749 16:35:20.513837 Test requi<14>[ 17.574940] [IGT] kms_atomic: executing
11750 16:35:20.520705 rement: is_intel<14>[ 17.579997] [IGT] kms_atomic: exiting, ret=77
11751 16:35:20.520981 _device(fd)
11752 16:35:20.527768 No KMS driver or no outputs, pipes: 16, outputs: 0
11753 16:35:20.533790 <8>[ 17.590837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11754 16:35:20.534194
11755 16:35:20.534790 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11757 16:35:20.540689 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11758 16:35:20.544493 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11759 16:35:20.550633 Using IGT_SRANDOM=171864212<14>[ 17.611514] [IGT] kms_atomic: executing
11760 16:35:20.557658 0 for randomisat<14>[ 17.616368] [IGT] kms_atomic: exiting, ret=77
11761 16:35:20.558056 ion
11762 16:35:20.560450 Opened device: /dev/dri/card0
11763 16:35:20.573483 No KMS driver or no outputs, pipes: 16, outp<8>[ 17.628018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11764 16:35:20.573882 uts: 0
11765 16:35:20.574424 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11767 16:35:20.577090 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11768 16:35:20.583466 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11769 16:35:20.590047 Using IGT_SRANDOM=1718642120 fo<14>[ 17.650684] [IGT] kms_atomic: executing
11770 16:35:20.593415 r randomisation
11771 16:35:20.596693 <14>[ 17.655451] [IGT] kms_atomic: exiting, ret=77
11772 16:35:20.597078
11773 16:35:20.599731 Opened device: /dev/dri/card0
11774 16:35:20.609993 No KMS driver or no outputs, pip<8>[ 17.666310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
11775 16:35:20.610660 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
11777 16:35:20.613394 es: 16, outputs: 0
11778 16:35:20.616427 [1mSubtest <8>[ 17.675695] <LAVA_SIGNAL_TESTSET STOP>
11779 16:35:20.617042 Received signal: <TESTSET> STOP
11780 16:35:20.617362 Closing test_set kms_atomic
11781 16:35:20.620126 plane-primary-legacy: SKIP (0.000s)[0m
11782 16:35:20.626561 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11783 16:35:20.629878 Using IGT_SRANDOM=1718642120 for randomisation
11784 16:35:20.633353 Opened device: /dev/dri/card0
11785 16:35:20.636513 No KMS driver or no outputs, pipes: 16, outputs: 0
11786 16:35:20.642750 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11787 16:35:20.652981 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <8>[ 17.710226] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11788 16:35:20.653715 Received signal: <TESTSET> START kms_flip_event_leak
11789 16:35:20.654043 Starting test_set kms_flip_event_leak
11790 16:35:20.656492 6.1.92-cip22 aarch64)
11791 16:35:20.659578 Using IGT_SRANDOM=1718642120 for randomisation
11792 16:35:20.662769 Opened device: /dev/dri/card0
11793 16:35:20.665850 No KMS driver or no outputs, pipes: 16, outputs: 0
11794 16:35:20.672467 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11795 16:35:20.675617 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11796 16:35:20.682421 Using IGT_SRA<14>[ 17.741428] [IGT] kms_flip_event_leak: executing
11797 16:35:20.688891 NDOM=1718642120 <14>[ 17.748188] [IGT] kms_flip_event_leak: exiting, ret=77
11798 16:35:20.692302 for randomisation
11799 16:35:20.695507 Opened device: /dev/dri/card0
11800 16:35:20.705348 No KMS driver or no outputs, pipes: 16, output<8>[ 17.761549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11801 16:35:20.705756 s: 0
11802 16:35:20.706317 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11804 16:35:20.711978 [1mSubtest test-only: SKI<8>[ 17.771251] <LAVA_SIGNAL_TESTSET STOP>
11805 16:35:20.712367 P (0.000s)[0m
11806 16:35:20.712908 Received signal: <TESTSET> STOP
11807 16:35:20.713204 Closing test_set kms_flip_event_leak
11808 16:35:20.718760 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11809 16:35:20.721894 Using IGT_SRANDOM=1718642120 for randomisation
11810 16:35:20.725046 Opened device: /dev/dri/card0
11811 16:35:20.731721 No KMS driver or no outputs, pipes: 16, outputs: 0
11812 16:35:20.735424 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11813 16:35:20.744540 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-c<8>[ 17.802882] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11814 16:35:20.744993 ip22 aarch64)
11815 16:35:20.745611 Received signal: <TESTSET> START kms_prop_blob
11816 16:35:20.745924 Starting test_set kms_prop_blob
11817 16:35:20.751612 Using IGT_SRANDOM=1718642120 for randomisation
11818 16:35:20.751997 Opened device: /dev/dri/card0
11819 16:35:20.758347 No KMS driver or no outputs, pipes: 16, outputs: 0
11820 16:35:20.761486 [1mSubtest pl<14>[ 17.821789] [IGT] kms_prop_blob: executing
11821 16:35:20.771370 ane-invalid-para<14>[ 17.827714] [IGT] kms_prop_blob: starting subtest basic
11822 16:35:20.778316 ms: SKIP (0.000s<14>[ 17.834487] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
11823 16:35:20.778776 )[0m
11824 16:35:20.784918 IGT-Versi<14>[ 17.842321] [IGT] kms_prop_blob: exiting, ret=0
11825 16:35:20.788323 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11826 16:35:20.795058 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11828 16:35:20.798310 Using<8>[ 17.852706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11829 16:35:20.800975 IGT_SRANDOM=1718642120 for randomisation
11830 16:35:20.801364 Opened device: /dev/dri/card0
11831 16:35:20.807670 No KMS driver or no outputs, pipes: 16, outputs: 0
11832 16:35:20.811155 [<14>[ 17.871498] [IGT] kms_prop_blob: executing
11833 16:35:20.821066 1mSubtest plane-<14>[ 17.876509] [IGT] kms_prop_blob: starting subtest blob-prop-core
11834 16:35:20.826939 invalid-params-f<14>[ 17.884005] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
11835 16:35:20.833911 ence: SKIP (0.00<14>[ 17.892591] [IGT] kms_prop_blob: exiting, ret=0
11836 16:35:20.833989 0s)[0m
11837 16:35:20.847080 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip<8>[ 17.903082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11838 16:35:20.847171 22 aarch64)
11839 16:35:20.847413 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11841 16:35:20.853928 Using IGT_SRANDOM=1718642120 for randomisation
11842 16:35:20.854035 Opened device: /dev/dri/card0
11843 16:35:20.863489 No KMS driver or no outputs, pipes: <14>[ 17.922513] [IGT] kms_prop_blob: executing
11844 16:35:20.863658 16, outputs: 0
11845 16:35:20.870430 <14>[ 17.927493] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11846 16:35:20.880505 [1mSubtest crtc<14>[ 17.935511] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
11847 16:35:20.886840 -invalid-params:<14>[ 17.944341] [IGT] kms_prop_blob: exiting, ret=0
11848 16:35:20.887126 SKIP (0.000s)[0m
11849 16:35:20.896827 IGT-Version: 1.28-ga44ebfe (<8>[ 17.954576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11850 16:35:20.897428 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11852 16:35:20.899783 aarch64) (Linux: 6.1.92-cip22 aarch64)
11853 16:35:20.906684 Using IGT_SRANDOM=1718642120 for randomisation
11854 16:35:20.909710 Opened device: /dev/dri/card0
11855 16:35:20.913221 No KMS dr<14>[ 17.973422] [IGT] kms_prop_blob: executing
11856 16:35:20.923260 iver or no outpu<14>[ 17.978435] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
11857 16:35:20.929662 ts, pipes: 16, o<14>[ 17.986277] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
11858 16:35:20.932870 utputs: 0
11859 16:35:20.936389 [1mS<14>[ 17.995128] [IGT] kms_prop_blob: exiting, ret=0
11860 16:35:20.949239 ubtest crtc-invalid-params-fence: SKIP (0.000s)<8>[ 18.005563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
11861 16:35:20.949360 [0m
11862 16:35:20.949597 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
11864 16:35:20.955783 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11865 16:35:20.959077 Using IGT_SRANDOM=1718642120 for randomisation
11866 16:35:20.965470 Opened <14>[ 18.024279] [IGT] kms_prop_blob: executing
11867 16:35:20.972197 device: /dev/dri<14>[ 18.029221] [IGT] kms_prop_blob: starting subtest blob-multiple
11868 16:35:20.972366 /card0
11869 16:35:20.978988 No KMS d<14>[ 18.036726] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
11870 16:35:20.985253 river or no outp<14>[ 18.045022] [IGT] kms_prop_blob: exiting, ret=0
11871 16:35:20.988845 uts, pipes: 16, outputs: 0
11872 16:35:20.999072 [1mSubtest atomic-invalid-params: S<8>[ 18.055455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
11873 16:35:20.999706 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
11875 16:35:21.002286 KIP (0.000s)[0m
11876 16:35:21.008997 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11877 16:35:21.012047 Using IGT_SRANDOM=1718642120 for randomisation
11878 16:35:21.015767 Opened dev<14>[ 18.075255] [IGT] kms_prop_blob: executing
11879 16:35:21.025811 ice: /dev/dri/ca<14>[ 18.081259] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
11880 16:35:21.026307 rd0
11881 16:35:21.035132 No KMS driv<14>[ 18.089333] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
11882 16:35:21.041762 er or no outputs<14>[ 18.098445] [IGT] kms_prop_blob: exiting, ret=0
11883 16:35:21.042158 , pipes: 16, outputs: 0
11884 16:35:21.051750 [1mSubtest atomic-plan<8>[ 18.108642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11885 16:35:21.052457 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11887 16:35:21.055130 e-damage: SKIP (0.000s)[0m
11888 16:35:21.061274 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11889 16:35:21.065045 Using IGT_SRANDOM=1718642120 for randomisation
11890 16:35:21.071401 Opened device: <14>[ 18.129308] [IGT] kms_prop_blob: executing
11891 16:35:21.071791 /dev/dri/card0
11892 16:35:21.077967 <14>[ 18.135351] [IGT] kms_prop_blob: starting subtest invalid-get-prop
11893 16:35:21.088108 No KMS driver or<14>[ 18.143002] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
11894 16:35:21.094899 no outputs, pip<14>[ 18.151725] [IGT] kms_prop_blob: exiting, ret=0
11895 16:35:21.095294 es: 16, outputs: 0
11896 16:35:21.104676 [1mSubtest basic: SKIP (0.0<8>[ 18.161883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11897 16:35:21.105310 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11899 16:35:21.107581 00s)[0m
11900 16:35:21.110771 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11901 16:35:21.117740 Using IGT_SRANDOM=1718642120 for randomisation
11902 16:35:21.121335 Op<14>[ 18.180535] [IGT] kms_prop_blob: executing
11903 16:35:21.130636 ened device: /de<14>[ 18.185499] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
11904 16:35:21.131077 v/dri/card0
11905 16:35:21.137493 Sta<14>[ 18.193521] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
11906 16:35:21.144225 rting subtest: b<14>[ 18.202620] [IGT] kms_prop_blob: exiting, ret=0
11907 16:35:21.144665 asic
11908 16:35:21.146958 [1mSubtest basic: SUCCESS (0.000s)[0m
11909 16:35:21.157195 I<8>[ 18.212867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11910 16:35:21.157895 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11912 16:35:21.163762 GT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11913 16:35:21.167028 Using IGT_SRANDOM=1718642120 for randomisation
11914 16:35:21.173389 Opened device: /dev/dri/card0<14>[ 18.231982] [IGT] kms_prop_blob: executing
11915 16:35:21.173909
11916 16:35:21.180267 Starting subte<14>[ 18.238065] [IGT] kms_prop_blob: starting subtest invalid-set-prop
11917 16:35:21.190430 st: blob-prop-co<14>[ 18.245905] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
11918 16:35:21.190855 re
11919 16:35:21.196854 [1mSubtest <14>[ 18.254550] [IGT] kms_prop_blob: exiting, ret=0
11920 16:35:21.200183 blob-prop-core: SUCCESS (0.000s)[0m
11921 16:35:21.206452 IGT-Versio<8>[ 18.264801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11922 16:35:21.207091 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11924 16:35:21.213529 n: 1.28-ga44ebfe<8>[ 18.273669] <LAVA_SIGNAL_TESTSET STOP>
11925 16:35:21.214155 Received signal: <TESTSET> STOP
11926 16:35:21.214514 Closing test_set kms_prop_blob
11927 16:35:21.216617 (aarch64) (Linux: 6.1.92-cip22 aarch64)
11928 16:35:21.219880 Using IGT_SRANDOM=1718642120 for randomisation
11929 16:35:21.223098 Opened device: /dev/dri/card0
11930 16:35:21.226904 Starting subtest: blob-prop-validate
11931 16:35:21.233117 [1mSubtest blob-<8>[ 18.292011] <LAVA_SIGNAL_TESTSET START kms_setmode>
11932 16:35:21.233793 Received signal: <TESTSET> START kms_setmode
11933 16:35:21.234113 Starting test_set kms_setmode
11934 16:35:21.236417 prop-validate: SUCCESS (0.000s)[0m
11935 16:35:21.243259 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11936 16:35:21.246539 Using IGT_SRANDOM=1718642120 for randomisation
11937 16:35:21.252502 Opened device: /dev/dri<14>[ 18.312437] [IGT] kms_setmode: executing
11938 16:35:21.252579 /card0
11939 16:35:21.259107 Starting<14>[ 18.318452] [IGT] kms_setmode: starting subtest basic
11940 16:35:21.269540 subtest: blob-p<14>[ 18.325004] [IGT] kms_setmode: finished subtest basic, SKIP
11941 16:35:21.269692 rop-lifetime
11942 16:35:21.272194 [<14>[ 18.332230] [IGT] kms_setmode: exiting, ret=77
11943 16:35:21.278861 1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
11944 16:35:21.285509 IGT-Version:<8>[ 18.343810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11945 16:35:21.285837 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11947 16:35:21.292432 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11948 16:35:21.295516 Using IGT_SRANDOM=1718642120 for randomisation
11949 16:35:21.298974 Opened device: /dev/dri/card0
11950 16:35:21.305639 Starting subtest: blob-mu<14>[ 18.363103] [IGT] kms_setmode: executing
11951 16:35:21.305824 ltiple
11952 16:35:21.312049 [1mSubt<14>[ 18.368898] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
11953 16:35:21.321846 est blob-multipl<14>[ 18.377012] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
11954 16:35:21.328603 e: SUCCESS (0.00<14>[ 18.385920] [IGT] kms_setmode: exiting, ret=77
11955 16:35:21.328991 0s)[0m
11956 16:35:21.338702 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 18.396221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
11957 16:35:21.339362 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
11959 16:35:21.342326 inux: 6.1.92-cip22 aarch64)
11960 16:35:21.345915 Using IGT_SRANDOM=1718642120 for randomisation
11961 16:35:21.348650 Opened device: /dev/dri/card0
11962 16:35:21.358445 Starting subtest: invalid-get-prop-a<14>[ 18.415405] [IGT] kms_setmode: executing
11963 16:35:21.358889 ny
11964 16:35:21.364793 [1mSubtest <14>[ 18.421557] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
11965 16:35:21.374991 invalid-get-prop<14>[ 18.429708] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
11966 16:35:21.381703 -any: SUCCESS (0<14>[ 18.438817] [IGT] kms_setmode: exiting, ret=77
11967 16:35:21.382189 .000s)[0m
11968 16:35:21.394512 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-<8>[ 18.449176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
11969 16:35:21.394912 cip22 aarch64)
11970 16:35:21.395460 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
11972 16:35:21.401079 Using IGT_SRANDOM=1718642121 for randomisation
11973 16:35:21.401468 Opened device: /dev/dri/card0
11974 16:35:21.404754 Starting subtest: invalid-get-prop
11975 16:35:21.411491 [1mSubtest i<14>[ 18.470221] [IGT] kms_setmode: executing
11976 16:35:21.421109 nvalid-get-prop:<14>[ 18.475858] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
11977 16:35:21.430923 SUCCESS (0.000s<14>[ 18.484392] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
11978 16:35:21.431357 )[0m
11979 16:35:21.434466 IGT-Versi<14>[ 18.493825] [IGT] kms_setmode: exiting, ret=77
11980 16:35:21.447231 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22<8>[ 18.503921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
11981 16:35:21.447863 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
11983 16:35:21.450979 aarch64)
11984 16:35:21.453980 Using IGT_SRANDOM=1718642121 for randomisation
11985 16:35:21.457132 Opened device: /dev/dri/card0
11986 16:35:21.460420 Starting subtest: invalid-set-prop-any
11987 16:35:21.463888 [1mSubtest in<14>[ 18.524043] [IGT] kms_setmode: executing
11988 16:35:21.473876 valid-set-prop-a<14>[ 18.529849] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
11989 16:35:21.480403 ny: SUCCESS (0.0<14>[ 18.537577] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
11990 16:35:21.483525 00s)[0m
11991 16:35:21.487129 IGT-Ve<14>[ 18.546237] [IGT] kms_setmode: exiting, ret=77
11992 16:35:21.500010 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<8>[ 18.556546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
11993 16:35:21.500422 p22 aarch64)
11994 16:35:21.500972 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
11996 16:35:21.506426 Using IGT_SRANDOM=1718642121 for randomisation
11997 16:35:21.506933 Opened device: /dev/dri/card0
11998 16:35:21.510000 Starting subtest: invalid-set-prop
11999 16:35:21.516835 [1mSubtest inv<14>[ 18.575708] [IGT] kms_setmode: executing
12000 16:35:21.526693 alid-set-prop: S<14>[ 18.581712] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12001 16:35:21.536497 UCCESS (0.000s)<14>[ 18.590661] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12002 16:35:21.536952 [0m
12003 16:35:21.543160 IGT-Version<14>[ 18.600492] [IGT] kms_setmode: exiting, ret=77
12004 16:35:21.556544 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 18.610645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12005 16:35:21.557137 arch64)
12006 16:35:21.557790 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12008 16:35:21.559538 Using I<8>[ 18.620813] <LAVA_SIGNAL_TESTSET STOP>
12009 16:35:21.560334 Received signal: <TESTSET> STOP
12010 16:35:21.560822 Closing test_set kms_setmode
12011 16:35:21.563351 GT_SRANDOM=1718642121 for randomisation
12012 16:35:21.566326 Opened device: /dev/dri/card0
12013 16:35:21.569603 Starting subtest: basic
12014 16:35:21.573167 No dynamic tests executed.
12015 16:35:21.579593 [1mSubtest basic: SKIP (0.000s)[0<8>[ 18.638974] <LAVA_SIGNAL_TESTSET START kms_vblank>
12016 16:35:21.580008 m
12017 16:35:21.580544 Received signal: <TESTSET> START kms_vblank
12018 16:35:21.580846 Starting test_set kms_vblank
12019 16:35:21.586470 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12020 16:35:21.589626 Using IGT_SRANDOM=1718642121 for randomisation
12021 16:35:21.592660 Opened device: /dev/dri/card0
12022 16:35:21.599390 Starting subtest: basic-cl<14>[ 18.658784] [IGT] kms_vblank: executing
12023 16:35:21.599810 one-single-crtc
12024 16:35:21.606076 <14>[ 18.664238] [IGT] kms_vblank: exiting, ret=77
12025 16:35:21.606542
12026 16:35:21.609068 No dynamic tests executed.
12027 16:35:21.615938 [1mSubtest basic-c<8>[ 18.673923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12028 16:35:21.616612 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12030 16:35:21.618846 lone-single-crtc: SKIP (0.000s)[0m
12031 16:35:21.625930 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12032 16:35:21.632002 Using IGT_SRANDOM=1718642121 for random<14>[ 18.692592] [IGT] kms_vblank: executing
12033 16:35:21.635245 isation
12034 16:35:21.638455 Opened <14>[ 18.697791] [IGT] kms_vblank: exiting, ret=77
12035 16:35:21.641942 device: /dev/dri/card0
12036 16:35:21.651822 Starting subtest: invalid-clone-single-c<8>[ 18.708938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12037 16:35:21.652502 rtc
12038 16:35:21.653354 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12040 16:35:21.655611 No dynamic tests executed.
12041 16:35:21.658507 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12042 16:35:21.665273 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12043 16:35:21.668330 U<14>[ 18.728494] [IGT] kms_vblank: executing
12044 16:35:21.675266 sing IGT_SRANDOM<14>[ 18.734223] [IGT] kms_vblank: exiting, ret=77
12045 16:35:21.678904 =1718642121 for randomisation
12046 16:35:21.688139 Opened device: /d<8>[ 18.744057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12047 16:35:21.688536 ev/dri/card0
12048 16:35:21.689078 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12050 16:35:21.691658 Starting subtest: invalid-clone-exclusive-crtc
12051 16:35:21.694671 No dynamic tests executed.
12052 16:35:21.705088 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s<14>[ 18.763708] [IGT] kms_vblank: executing
12053 16:35:21.705553 )[0m
12054 16:35:21.708131 IGT-Versi<14>[ 18.768340] [IGT] kms_vblank: exiting, ret=77
12055 16:35:21.715056 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12056 16:35:21.721239 Using<8>[ 18.779446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12057 16:35:21.722017 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12059 16:35:21.724733 IGT_SRANDOM=1718642121 for randomisation
12060 16:35:21.728121 Opened device: /dev/dri/card0
12061 16:35:21.730987 Starting subtest: clone-exclusive-crtc
12062 16:35:21.734675 No dynamic tests executed.
12063 16:35:21.741426 [1mSubtest clone-<14>[ 18.799525] [IGT] kms_vblank: executing
12064 16:35:21.747633 exclusive-crtc: <14>[ 18.805078] [IGT] kms_vblank: exiting, ret=77
12065 16:35:21.748091 SKIP (0.000s)[0m
12066 16:35:21.757412 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <8>[ 18.816157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12067 16:35:21.758066 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12069 16:35:21.760872 6.1.92-cip22 aarch64)
12070 16:35:21.764086 Using IGT_SRANDOM=1718642121 for randomisation
12071 16:35:21.767752 Opened device: /dev/dri/card0
12072 16:35:21.774481 Starting subtest: invalid-clone-single-crtc-stealing
12073 16:35:21.777788 No d<14>[ 18.836335] [IGT] kms_vblank: executing
12074 16:35:21.784125 ynamic tests exe<14>[ 18.842298] [IGT] kms_vblank: exiting, ret=77
12075 16:35:21.784618 cuted.
12076 16:35:21.793496 [1mSubtest invalid-clone-single-crtc-st<8>[ 18.851984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12077 16:35:21.793744 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12079 16:35:21.797583 ealing: SKIP (0.000s)[0m
12080 16:35:21.804132 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12081 16:35:21.807255 Using IGT_SRANDOM=1718642121 for randomisation
12082 16:35:21.810627 O<14>[ 18.871171] [IGT] kms_vblank: executing
12083 16:35:21.816872 pened device: /d<14>[ 18.876635] [IGT] kms_vblank: exiting, ret=77
12084 16:35:21.820482 ev/dri/card0
12085 16:35:21.830486 No KMS driver or no outputs, pipes: 16, outputs: 0<8>[ 18.887479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12086 16:35:21.830945
12087 16:35:21.831491 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12089 16:35:21.833369 [1mSubtest invalid: SKIP (0.000s)[0m
12090 16:35:21.840311 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12091 16:35:21.843277 Using IGT_SRANDOM=1718642121 for randomisation
12092 16:35:21.850379 Op<14>[ 18.908010] [IGT] kms_vblank: executing
12093 16:35:21.856596 ened device: /de<14>[ 18.913658] [IGT] kms_vblank: exiting, ret=77
12094 16:35:21.857050 v/dri/card0
12095 16:35:21.866349 No KMS driver or no outputs, pipes:<8>[ 18.923504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12096 16:35:21.866824 16, outputs: 0
12097 16:35:21.867500 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12099 16:35:21.869766 [1mSubtest crtc-id: SKIP (0.000s)[0m
12100 16:35:21.876308 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12101 16:35:21.883302 Using IGT_SRANDOM=1<14>[ 18.942587] [IGT] kms_vblank: executing
12102 16:35:21.889332 718642121 for ra<14>[ 18.947632] [IGT] kms_vblank: exiting, ret=77
12103 16:35:21.889929 ndomisation
12104 16:35:21.892608 Opened device: /dev/dri/card0
12105 16:35:21.903059 No KMS driver or no <8>[ 18.958803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12106 16:35:21.903776 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12108 16:35:21.906349 outputs, pipes: 16, outputs: 0
12109 16:35:21.909544 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12110 16:35:21.916280 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12111 16:35:21.919659 Using IGT_SRAN<14>[ 18.979068] [IGT] kms_vblank: executing
12112 16:35:21.925997 DOM=1718642121 f<14>[ 18.984790] [IGT] kms_vblank: exiting, ret=77
12113 16:35:21.929084 or randomisation
12114 16:35:21.929468 Opened device: /dev/dri/card0
12115 16:35:21.942554 No KMS driver or no outputs, pipes: 16, outputs<8>[ 18.997442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12116 16:35:21.943074 : 0
12117 16:35:21.943815 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12119 16:35:21.945786 [1mSubtest query-idle: SKIP (0.000s)[0m
12120 16:35:21.952529 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12121 16:35:21.959191 Using IGT_SRANDOM=1718642121 for randomisati<14>[ 19.019362] [IGT] kms_vblank: executing
12122 16:35:21.959578 on
12123 16:35:21.965680 Opened devic<14>[ 19.024898] [IGT] kms_vblank: exiting, ret=77
12124 16:35:21.968794 e: /dev/dri/card0
12125 16:35:21.978968 No KMS driver or no outputs, pipes: 16, outpu<8>[ 19.035857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12126 16:35:21.979563 ts: 0
12127 16:35:21.980142 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12129 16:35:21.985452 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12130 16:35:21.992066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12131 16:35:21.998532 Using IGT_SRANDOM=1718642121 for rand<14>[ 19.056927] [IGT] kms_vblank: executing
12132 16:35:21.998924 omisation
12133 16:35:22.005262 Opene<14>[ 19.062311] [IGT] kms_vblank: exiting, ret=77
12134 16:35:22.005653 d device: /dev/dri/card0
12135 16:35:22.014767 No KMS driver or no outputs, pipes: 16<8>[ 19.073589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12136 16:35:22.015594 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12138 16:35:22.018090 , outputs: 0
12139 16:35:22.021257 [1mSubtest query-forked: SKIP (0.000s)[0m
12140 16:35:22.028296 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12141 16:35:22.031447 Using IGT_SRANDOM<14>[ 19.092874] [IGT] kms_vblank: executing
12142 16:35:22.038155 =1718642121 for <14>[ 19.097667] [IGT] kms_vblank: exiting, ret=77
12143 16:35:22.041479 randomisation
12144 16:35:22.044335 Opened device: /dev/dri/card0
12145 16:35:22.054364 No KMS driver or no outputs, pipes<8>[ 19.108920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12146 16:35:22.054820 : 16, outputs: 0
12147 16:35:22.055362 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12149 16:35:22.057741 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12150 16:35:22.064583 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12151 16:35:22.070651 Using IGT_SRANDOM=171864<14>[ 19.130026] [IGT] kms_vblank: executing
12152 16:35:22.077659 2121 for randomi<14>[ 19.135960] [IGT] kms_vblank: exiting, ret=77
12153 16:35:22.078100 sation
12154 16:35:22.080621 Opened device: /dev/dri/card0
12155 16:35:22.090501 No KMS driver or no outpu<8>[ 19.147075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12156 16:35:22.091015 ts, pipes: 16, outputs: 0
12157 16:35:22.091682 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12159 16:35:22.097168 [1mSubtest query-busy: SKIP (0.000s)[0m
12160 16:35:22.100285 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12161 16:35:22.107099 Using IGT_SRANDOM=1718<14>[ 19.166849] [IGT] kms_vblank: executing
12162 16:35:22.113843 642121 for rando<14>[ 19.172623] [IGT] kms_vblank: exiting, ret=77
12163 16:35:22.114366 misation
12164 16:35:22.116946 Opened device: /dev/dri/card0
12165 16:35:22.127011 No KMS driver or no out<8>[ 19.182699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12166 16:35:22.127654 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12168 16:35:22.130194 puts, pipes: 16, outputs: 0
12169 16:35:22.133872 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12170 16:35:22.140740 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12171 16:35:22.143805 Using IGT_SRANDOM=1718642121 for randomisation
12172 16:35:22.149993 Opened device: <14>[ 19.208079] [IGT] kms_vblank: executing
12173 16:35:22.150525 /dev/dri/card0
12174 16:35:22.156602 <14>[ 19.214080] [IGT] kms_vblank: exiting, ret=77
12175 16:35:22.159876 No KMS driver or no outputs, pipes: 16, outputs: 0
12176 16:35:22.167018 [1mSubtest <8>[ 19.223965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12177 16:35:22.167773 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12179 16:35:22.170070 query-forked-busy: SKIP (0.000s)[0m
12180 16:35:22.176606 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12181 16:35:22.183438 Using IGT_SRANDOM=1718642121 for rando<14>[ 19.243722] [IGT] kms_vblank: executing
12182 16:35:22.186684 misation
12183 16:35:22.190375 Opened<14>[ 19.249387] [IGT] kms_vblank: exiting, ret=77
12184 16:35:22.193343 device: /dev/dri/card0
12185 16:35:22.203340 No KMS driver or no outputs, pipes: 16,<8>[ 19.260624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12186 16:35:22.203734 outputs: 0
12187 16:35:22.204283 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12189 16:35:22.209560 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12190 16:35:22.216940 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12191 16:35:22.219596 Using IG<14>[ 19.280247] [IGT] kms_vblank: executing
12192 16:35:22.226650 T_SRANDOM=171864<14>[ 19.285091] [IGT] kms_vblank: exiting, ret=77
12193 16:35:22.229677 2121 for randomisation
12194 16:35:22.232990 Opened device: /dev/dri/card0
12195 16:35:22.239606 No KMS driver or no outpu<8>[ 19.296482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12196 16:35:22.240244 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12198 16:35:22.243276 ts, pipes: 16, outputs: 0
12199 16:35:22.245872 [1mSubtest wait-idle: SKIP (0.000s)[0m
12200 16:35:22.252151 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12201 16:35:22.259002 Using IGT_SRANDOM=17186<14>[ 19.318029] [IGT] kms_vblank: executing
12202 16:35:22.266090 42122 for random<14>[ 19.323728] [IGT] kms_vblank: exiting, ret=77
12203 16:35:22.266516 isation
12204 16:35:22.269148 Opened device: /dev/dri/card0
12205 16:35:22.279464 No KMS driver or no outp<8>[ 19.333808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12206 16:35:22.280207 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12208 16:35:22.282136 uts, pipes: 16, outputs: 0
12209 16:35:22.285814 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12210 16:35:22.292586 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12211 16:35:22.295593 U<14>[ 19.354245] [IGT] kms_vblank: executing
12212 16:35:22.302174 sing IGT_SRANDOM<14>[ 19.360009] [IGT] kms_vblank: exiting, ret=77
12213 16:35:22.305988 =1718642122 for randomisation
12214 16:35:22.306419 Opened device: /dev/dri/card0
12215 16:35:22.315709 No KMS driver or n<8>[ 19.371676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12216 16:35:22.316341 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12218 16:35:22.318835 o outputs, pipes: 16, outputs: 0
12219 16:35:22.322087 [1mSubtest wait-forked: SKIP (0.000s)[0m
12220 16:35:22.328155 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12221 16:35:22.334558 Using IGT_SRAN<14>[ 19.393051] [IGT] kms_vblank: executing
12222 16:35:22.341775 DOM=1718642122 f<14>[ 19.399045] [IGT] kms_vblank: exiting, ret=77
12223 16:35:22.341852 or randomisation
12224 16:35:22.345171 Opened device: /dev/dri/card0
12225 16:35:22.355039 No KMS driver o<8>[ 19.410228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12226 16:35:22.355285 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12228 16:35:22.358338 r no outputs, pipes: 16, outputs: 0
12229 16:35:22.361668 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12230 16:35:22.371831 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 <14>[ 19.430874] [IGT] kms_vblank: executing
12231 16:35:22.372299 aarch64)
12232 16:35:22.378375 Using <14>[ 19.435610] [IGT] kms_vblank: exiting, ret=77
12233 16:35:22.381499 IGT_SRANDOM=1718642122 for randomisation
12234 16:35:22.381879 Opened device: /dev/dri/card0
12235 16:35:22.391359 No KMS <8>[ 19.446962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12236 16:35:22.391987 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12238 16:35:22.395064 driver or no outputs, pipes: 16, outputs: 0
12239 16:35:22.398166 [1mSubtest wait-busy: SKIP (0.000s)[0m
12240 16:35:22.404740 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12241 16:35:22.410989 Using<14>[ 19.469130] [IGT] kms_vblank: executing
12242 16:35:22.414639 IGT_SRANDOM=171<14>[ 19.474891] [IGT] kms_vblank: exiting, ret=77
12243 16:35:22.417805 8642122 for randomisation
12244 16:35:22.421220 Opened device: /dev/dri/card0
12245 16:35:22.430811 No KMS<8>[ 19.486149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12246 16:35:22.431473 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12248 16:35:22.434561 driver or no outputs, pipes: 16, outputs: 0
12249 16:35:22.437901 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12250 16:35:22.444212 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12251 16:35:22.447716 <14>[ 19.507248] [IGT] kms_vblank: executing
12252 16:35:22.448098
12253 16:35:22.454326 Using IGT_SRAND<14>[ 19.513196] [IGT] kms_vblank: exiting, ret=77
12254 16:35:22.457509 OM=1718642122 for randomisation
12255 16:35:22.461238 Opened device: /dev/dri/card0
12256 16:35:22.470683 No KMS driver or<8>[ 19.525614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12257 16:35:22.471312 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12259 16:35:22.474124 no outputs, pipes: 16, outputs: 0
12260 16:35:22.477496 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12261 16:35:22.483803 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12262 16:35:22.486936 Using I<14>[ 19.546790] [IGT] kms_vblank: executing
12263 16:35:22.493437 GT_SRANDOM=17186<14>[ 19.552458] [IGT] kms_vblank: exiting, ret=77
12264 16:35:22.496633 42122 for randomisation
12265 16:35:22.496715 Opened device: /dev/dri/card0
12266 16:35:22.506563 No KMS d<8>[ 19.562689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12267 16:35:22.506928 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12269 16:35:22.510030 river or no outputs, pipes: 16, outputs: 0
12270 16:35:22.516424 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12271 16:35:22.520003 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12272 16:35:22.526833 Using IGT_SRANDOM=17186421<14>[ 19.587206] [IGT] kms_vblank: executing
12273 16:35:22.533496 22 for randomisa<14>[ 19.593061] [IGT] kms_vblank: exiting, ret=77
12274 16:35:22.533717 tion
12275 16:35:22.536744 Opened device: /dev/dri/card0
12276 16:35:22.546653 No KMS driver or no outputs<8>[ 19.602955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12277 16:35:22.547283 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12279 16:35:22.550077 , pipes: 16, outputs: 0
12280 16:35:22.556495 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12281 16:35:22.566321 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)<14>[ 19.623835] [IGT] kms_vblank: executing
12282 16:35:22.566861
12283 16:35:22.569883 Using IGT_SRAN<14>[ 19.629799] [IGT] kms_vblank: exiting, ret=77
12284 16:35:22.573327 DOM=1718642122 for randomisation
12285 16:35:22.576364 Opened device: /dev/dri/card0
12286 16:35:22.583592 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12288 16:35:22.586676 <8>[ 19.640988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12289 16:35:22.587138
12290 16:35:22.593460 No KMS driver or no outputs, pi<8>[ 19.650913] <LAVA_SIGNAL_TESTSET STOP>
12291 16:35:22.594170 Received signal: <TESTSET> STOP
12292 16:35:22.594535 Closing test_set kms_vblank
12293 16:35:22.599929 pes: 16, outputs<8>[ 19.657133] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14396148_1.5.2.3.1>
12294 16:35:22.600408 : 0
12295 16:35:22.600972 Received signal: <ENDRUN> 0_igt-kms-mediatek 14396148_1.5.2.3.1
12296 16:35:22.601350 Ending use of test pattern.
12297 16:35:22.601635 Ending test lava.0_igt-kms-mediatek (14396148_1.5.2.3.1), duration 6.16
12299 16:35:22.606205 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12300 16:35:22.613196 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12301 16:35:22.616547 Using IGT_SRANDOM=1718642122 for randomisation
12302 16:35:22.620022 Opened device: /dev/dri/card0
12303 16:35:22.622710 No KMS driver or no outputs, pipes: 16, outputs: 0
12304 16:35:22.629582 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12305 16:35:22.632565 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12306 16:35:22.639417 Using IGT_SRANDOM=1718642122 for randomisation
12307 16:35:22.639800 Opened device: /dev/dri/card0
12308 16:35:22.645462 No KMS driver or no outputs, pipes: 16, outputs: 0
12309 16:35:22.648875 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12310 16:35:22.655521 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12311 16:35:22.659181 Using IGT_SRANDOM=1718642122 for randomisation
12312 16:35:22.662077 Opened device: /dev/dri/card0
12313 16:35:22.668605 No KMS driver or no outputs, pipes: 16, outputs: 0
12314 16:35:22.671748 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12315 16:35:22.678435 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12316 16:35:22.681937 Using IGT_SRANDOM=1718642122 for randomisation
12317 16:35:22.685321 Opened device: /dev/dri/card0
12318 16:35:22.688573 No KMS driver or no outputs, pipes: 16, outputs: 0
12319 16:35:22.694650 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12320 16:35:22.701530 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12321 16:35:22.705158 Using IGT_SRANDOM=1718642122 for randomisation
12322 16:35:22.708187 Opened device: /dev/dri/card0
12323 16:35:22.711333 No KMS driver or no outputs, pipes: 16, outputs: 0
12324 16:35:22.717912 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12325 16:35:22.724678 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12326 16:35:22.727772 Using IGT_SRANDOM=1718642122 for randomisation
12327 16:35:22.730862 Opened device: /dev/dri/card0
12328 16:35:22.733965 No KMS driver or no outputs, pipes: 16, outputs: 0
12329 16:35:22.741023 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12330 16:35:22.741117 + set +x
12331 16:35:22.741204 <LAVA_TEST_RUNNER EXIT>
12332 16:35:22.741445 ok: lava_test_shell seems to have completed
12333 16:35:22.743305 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12334 16:35:22.743465 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12335 16:35:22.743579 end: 3 lava-test-retry (duration 00:00:07) [common]
12336 16:35:22.743666 start: 4 finalize (timeout 00:07:57) [common]
12337 16:35:22.743766 start: 4.1 power-off (timeout 00:00:30) [common]
12338 16:35:22.744027 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
12339 16:35:22.942626 >> Command sent successfully.
12340 16:35:22.945711 Returned 0 in 0 seconds
12341 16:35:23.046054 end: 4.1 power-off (duration 00:00:00) [common]
12343 16:35:23.046388 start: 4.2 read-feedback (timeout 00:07:57) [common]
12344 16:35:23.046625 Listened to connection for namespace 'common' for up to 1s
12345 16:35:23.046902 Listened to connection for namespace 'common' for up to 1s
12346 16:35:24.047728 Finalising connection for namespace 'common'
12347 16:35:24.048247 Disconnecting from shell: Finalise
12348 16:35:24.048616 / #
12349 16:35:24.149310 end: 4.2 read-feedback (duration 00:00:01) [common]
12350 16:35:24.149453 end: 4 finalize (duration 00:00:01) [common]
12351 16:35:24.149562 Cleaning after the job
12352 16:35:24.149662 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/ramdisk
12353 16:35:24.156407 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/kernel
12354 16:35:24.172010 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/dtb
12355 16:35:24.172206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396148/tftp-deploy-4nudwhtf/modules
12356 16:35:24.177812 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396148
12357 16:35:24.287031 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396148
12358 16:35:24.287177 Job finished correctly