Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 50
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 90
1 16:33:35.918590 lava-dispatcher, installed at version: 2024.03
2 16:33:35.918845 start: 0 validate
3 16:33:35.918998 Start time: 2024-06-17 16:33:35.918992+00:00 (UTC)
4 16:33:35.919174 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:33:35.919370 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:33:36.184315 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:33:36.184486 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:33:37.026125 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:33:37.026337 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 16:33:37.290040 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:33:37.290215 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:33:37.553407 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:33:37.553600 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:33:37.818589 validate duration: 1.90
16 16:33:37.818841 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:33:37.818945 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:33:37.819071 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:33:37.819298 Not decompressing ramdisk as can be used compressed.
20 16:33:37.819449 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:33:37.819561 saving as /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/ramdisk/initrd.cpio.gz
22 16:33:37.819663 total size: 5628169 (5 MB)
23 16:33:37.821060 progress 0 % (0 MB)
24 16:33:37.822912 progress 5 % (0 MB)
25 16:33:37.824584 progress 10 % (0 MB)
26 16:33:37.826169 progress 15 % (0 MB)
27 16:33:37.827830 progress 20 % (1 MB)
28 16:33:37.829323 progress 25 % (1 MB)
29 16:33:37.831035 progress 30 % (1 MB)
30 16:33:37.832691 progress 35 % (1 MB)
31 16:33:37.834170 progress 40 % (2 MB)
32 16:33:37.835892 progress 45 % (2 MB)
33 16:33:37.837390 progress 50 % (2 MB)
34 16:33:37.839055 progress 55 % (2 MB)
35 16:33:37.840664 progress 60 % (3 MB)
36 16:33:37.842176 progress 65 % (3 MB)
37 16:33:37.843781 progress 70 % (3 MB)
38 16:33:37.845248 progress 75 % (4 MB)
39 16:33:37.846971 progress 80 % (4 MB)
40 16:33:37.848451 progress 85 % (4 MB)
41 16:33:37.850160 progress 90 % (4 MB)
42 16:33:37.851796 progress 95 % (5 MB)
43 16:33:37.853297 progress 100 % (5 MB)
44 16:33:37.853514 5 MB downloaded in 0.03 s (158.61 MB/s)
45 16:33:37.853711 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:33:37.854086 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:33:37.854177 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:33:37.854259 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:33:37.854400 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:33:37.854468 saving as /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/kernel/Image
52 16:33:37.854530 total size: 54813184 (52 MB)
53 16:33:37.854587 No compression specified
54 16:33:37.855775 progress 0 % (0 MB)
55 16:33:37.870908 progress 5 % (2 MB)
56 16:33:37.886290 progress 10 % (5 MB)
57 16:33:37.901208 progress 15 % (7 MB)
58 16:33:37.916396 progress 20 % (10 MB)
59 16:33:37.931098 progress 25 % (13 MB)
60 16:33:37.945687 progress 30 % (15 MB)
61 16:33:37.960475 progress 35 % (18 MB)
62 16:33:37.975545 progress 40 % (20 MB)
63 16:33:37.990633 progress 45 % (23 MB)
64 16:33:38.005996 progress 50 % (26 MB)
65 16:33:38.021336 progress 55 % (28 MB)
66 16:33:38.036455 progress 60 % (31 MB)
67 16:33:38.051773 progress 65 % (34 MB)
68 16:33:38.066919 progress 70 % (36 MB)
69 16:33:38.082300 progress 75 % (39 MB)
70 16:33:38.097456 progress 80 % (41 MB)
71 16:33:38.112146 progress 85 % (44 MB)
72 16:33:38.126866 progress 90 % (47 MB)
73 16:33:38.141541 progress 95 % (49 MB)
74 16:33:38.156065 progress 100 % (52 MB)
75 16:33:38.156346 52 MB downloaded in 0.30 s (173.20 MB/s)
76 16:33:38.156552 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:33:38.156912 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:33:38.157028 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:33:38.157134 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:33:38.157308 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 16:33:38.157409 saving as /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 16:33:38.157494 total size: 57695 (0 MB)
84 16:33:38.157578 No compression specified
85 16:33:38.158999 progress 56 % (0 MB)
86 16:33:38.159296 progress 100 % (0 MB)
87 16:33:38.159522 0 MB downloaded in 0.00 s (27.17 MB/s)
88 16:33:38.159685 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:33:38.160030 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:33:38.160138 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:33:38.160246 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:33:38.160387 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:33:38.160475 saving as /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/nfsrootfs/full.rootfs.tar
95 16:33:38.160558 total size: 120894716 (115 MB)
96 16:33:38.160642 Using unxz to decompress xz
97 16:33:38.162204 progress 0 % (0 MB)
98 16:33:38.511418 progress 5 % (5 MB)
99 16:33:40.118697 progress 10 % (11 MB)
100 16:33:40.466728 progress 15 % (17 MB)
101 16:33:40.809089 progress 20 % (23 MB)
102 16:33:41.124883 progress 25 % (28 MB)
103 16:33:41.489652 progress 30 % (34 MB)
104 16:33:41.835402 progress 35 % (40 MB)
105 16:33:42.015934 progress 40 % (46 MB)
106 16:33:42.210127 progress 45 % (51 MB)
107 16:33:42.528731 progress 50 % (57 MB)
108 16:33:42.903594 progress 55 % (63 MB)
109 16:33:43.265526 progress 60 % (69 MB)
110 16:33:43.621592 progress 65 % (74 MB)
111 16:33:43.983082 progress 70 % (80 MB)
112 16:33:44.346092 progress 75 % (86 MB)
113 16:33:44.688144 progress 80 % (92 MB)
114 16:33:46.313105 progress 85 % (98 MB)
115 16:33:46.681366 progress 90 % (103 MB)
116 16:33:47.015456 progress 95 % (109 MB)
117 16:33:47.388441 progress 100 % (115 MB)
118 16:33:47.394155 115 MB downloaded in 9.23 s (12.49 MB/s)
119 16:33:47.394322 end: 1.4.1 http-download (duration 00:00:09) [common]
121 16:33:47.394550 end: 1.4 download-retry (duration 00:00:09) [common]
122 16:33:47.394635 start: 1.5 download-retry (timeout 00:09:50) [common]
123 16:33:47.394719 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 16:33:47.394860 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:33:47.394925 saving as /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/modules/modules.tar
126 16:33:47.394981 total size: 8628772 (8 MB)
127 16:33:47.395043 Using unxz to decompress xz
128 16:33:47.396607 progress 0 % (0 MB)
129 16:33:47.418591 progress 5 % (0 MB)
130 16:33:47.443572 progress 10 % (0 MB)
131 16:33:47.468462 progress 15 % (1 MB)
132 16:33:47.494049 progress 20 % (1 MB)
133 16:33:47.520160 progress 25 % (2 MB)
134 16:33:47.545785 progress 30 % (2 MB)
135 16:33:47.573188 progress 35 % (2 MB)
136 16:33:47.598875 progress 40 % (3 MB)
137 16:33:47.624155 progress 45 % (3 MB)
138 16:33:47.650525 progress 50 % (4 MB)
139 16:33:47.675651 progress 55 % (4 MB)
140 16:33:47.701149 progress 60 % (4 MB)
141 16:33:47.728890 progress 65 % (5 MB)
142 16:33:47.754165 progress 70 % (5 MB)
143 16:33:47.778229 progress 75 % (6 MB)
144 16:33:47.802849 progress 80 % (6 MB)
145 16:33:47.830566 progress 85 % (7 MB)
146 16:33:47.859043 progress 90 % (7 MB)
147 16:33:47.884918 progress 95 % (7 MB)
148 16:33:47.909756 progress 100 % (8 MB)
149 16:33:47.915011 8 MB downloaded in 0.52 s (15.82 MB/s)
150 16:33:47.915195 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:33:47.915418 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:33:47.915501 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 16:33:47.915581 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 16:33:53.281169 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto
156 16:33:53.281349 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
157 16:33:53.281448 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 16:33:53.281618 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6
159 16:33:53.281741 makedir: /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin
160 16:33:53.281837 makedir: /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/tests
161 16:33:53.281950 makedir: /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/results
162 16:33:53.282188 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-add-keys
163 16:33:53.282322 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-add-sources
164 16:33:53.282446 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-background-process-start
165 16:33:53.282572 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-background-process-stop
166 16:33:53.282700 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-common-functions
167 16:33:53.282819 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-echo-ipv4
168 16:33:53.282935 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-install-packages
169 16:33:53.283055 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-installed-packages
170 16:33:53.283170 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-os-build
171 16:33:53.283290 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-probe-channel
172 16:33:53.283404 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-probe-ip
173 16:33:53.283523 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-target-ip
174 16:33:53.283637 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-target-mac
175 16:33:53.283750 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-target-storage
176 16:33:53.283872 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-case
177 16:33:53.283991 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-event
178 16:33:53.284105 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-feedback
179 16:33:53.284218 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-raise
180 16:33:53.284331 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-reference
181 16:33:53.284443 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-runner
182 16:33:53.284560 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-set
183 16:33:53.284673 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-test-shell
184 16:33:53.284789 Updating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-add-keys (debian)
185 16:33:53.375687 Updating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-add-sources (debian)
186 16:33:53.375917 Updating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-install-packages (debian)
187 16:33:53.376090 Updating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-installed-packages (debian)
188 16:33:53.376252 Updating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/bin/lava-os-build (debian)
189 16:33:53.376397 Creating /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/environment
190 16:33:53.376522 LAVA metadata
191 16:33:53.376624 - LAVA_JOB_ID=14396137
192 16:33:53.376713 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:33:53.376856 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:44) [common]
194 16:33:53.376941 skipped lava-vland-overlay
195 16:33:53.377040 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:33:53.377128 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
197 16:33:53.377188 skipped lava-multinode-overlay
198 16:33:53.377256 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:33:53.377328 start: 1.6.2.3 test-definition (timeout 00:09:44) [common]
200 16:33:53.377395 Loading test definitions
201 16:33:53.377473 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:44) [common]
202 16:33:53.377533 Using /lava-14396137 at stage 0
203 16:33:53.377826 uuid=14396137_1.6.2.3.1 testdef=None
204 16:33:53.377910 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:33:53.377997 start: 1.6.2.3.2 test-overlay (timeout 00:09:44) [common]
206 16:33:53.378415 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:33:53.378625 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:44) [common]
209 16:33:53.482414 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:33:53.482668 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
212 16:33:53.586430 runner path: /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/0/tests/0_timesync-off test_uuid 14396137_1.6.2.3.1
213 16:33:53.586630 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:33:53.586918 start: 1.6.2.3.5 git-repo-action (timeout 00:09:44) [common]
216 16:33:53.586991 Using /lava-14396137 at stage 0
217 16:33:53.587134 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:33:53.587242 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/0/tests/1_kselftest-alsa'
219 16:34:01.433036 Running '/usr/bin/git checkout kernelci.org
220 16:34:07.192659 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 16:34:07.193219 uuid=14396137_1.6.2.3.5 testdef=None
222 16:34:07.193346 end: 1.6.2.3.5 git-repo-action (duration 00:00:14) [common]
224 16:34:07.193554 start: 1.6.2.3.6 test-overlay (timeout 00:09:31) [common]
225 16:34:07.194649 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:34:07.194991 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:31) [common]
228 16:34:07.215764 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:34:07.216051 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:31) [common]
231 16:34:07.234759 runner path: /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/0/tests/1_kselftest-alsa test_uuid 14396137_1.6.2.3.5
232 16:34:07.234859 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 16:34:07.234921 BRANCH='cip-gitlab'
234 16:34:07.234976 SKIPFILE='/dev/null'
235 16:34:07.235029 SKIP_INSTALL='True'
236 16:34:07.235080 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:34:07.235133 TST_CASENAME=''
238 16:34:07.235184 TST_CMDFILES='alsa'
239 16:34:07.235333 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:34:07.235542 Creating lava-test-runner.conf files
242 16:34:07.235600 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396137/lava-overlay-j76xf9_6/lava-14396137/0 for stage 0
243 16:34:07.235705 - 0_timesync-off
244 16:34:07.235771 - 1_kselftest-alsa
245 16:34:07.235865 end: 1.6.2.3 test-definition (duration 00:00:14) [common]
246 16:34:07.235946 start: 1.6.2.4 compress-overlay (timeout 00:09:31) [common]
247 16:34:17.833570 end: 1.6.2.4 compress-overlay (duration 00:00:11) [common]
248 16:34:17.833708 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:20) [common]
249 16:34:17.833794 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:34:17.833875 end: 1.6.2 lava-overlay (duration 00:00:25) [common]
251 16:34:17.833953 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:20) [common]
252 16:34:17.994410 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:34:17.994545 start: 1.6.4 extract-modules (timeout 00:09:20) [common]
254 16:34:17.994622 extracting modules file /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto
255 16:34:18.210818 extracting modules file /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396137/extract-overlay-ramdisk-mzjlu3n1/ramdisk
256 16:34:18.433940 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:34:18.434100 start: 1.6.5 apply-overlay-tftp (timeout 00:09:19) [common]
258 16:34:18.434180 [common] Applying overlay to NFS
259 16:34:18.434238 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396137/compress-overlay-av6qrnql/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto
260 16:34:19.291367 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:34:19.291518 start: 1.6.6 configure-preseed-file (timeout 00:09:19) [common]
262 16:34:19.291601 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:34:19.291719 start: 1.6.7 compress-ramdisk (timeout 00:09:19) [common]
264 16:34:19.291787 Building ramdisk /var/lib/lava/dispatcher/tmp/14396137/extract-overlay-ramdisk-mzjlu3n1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396137/extract-overlay-ramdisk-mzjlu3n1/ramdisk
265 16:34:20.250706 >> 130466 blocks
266 16:34:22.373935 rename /var/lib/lava/dispatcher/tmp/14396137/extract-overlay-ramdisk-mzjlu3n1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/ramdisk/ramdisk.cpio.gz
267 16:34:22.374137 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 16:34:22.374225 start: 1.6.8 prepare-kernel (timeout 00:09:15) [common]
269 16:34:22.374304 start: 1.6.8.1 prepare-fit (timeout 00:09:15) [common]
270 16:34:22.374382 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/kernel/Image']
271 16:34:36.259421 Returned 0 in 13 seconds
272 16:34:36.359887 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/kernel/image.itb
273 16:34:36.744309 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:34:36.744438 output: Created: Mon Jun 17 17:34:36 2024
275 16:34:36.744513 output: Image 0 (kernel-1)
276 16:34:36.744607 output: Description:
277 16:34:36.744693 output: Created: Mon Jun 17 17:34:36 2024
278 16:34:36.744754 output: Type: Kernel Image
279 16:34:36.744811 output: Compression: lzma compressed
280 16:34:36.744868 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
281 16:34:36.744919 output: Architecture: AArch64
282 16:34:36.744969 output: OS: Linux
283 16:34:36.745022 output: Load Address: 0x00000000
284 16:34:36.745071 output: Entry Point: 0x00000000
285 16:34:36.745119 output: Hash algo: crc32
286 16:34:36.745168 output: Hash value: 106ffd6f
287 16:34:36.745216 output: Image 1 (fdt-1)
288 16:34:36.745267 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 16:34:36.745317 output: Created: Mon Jun 17 17:34:36 2024
290 16:34:36.745365 output: Type: Flat Device Tree
291 16:34:36.745415 output: Compression: uncompressed
292 16:34:36.745464 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 16:34:36.745516 output: Architecture: AArch64
294 16:34:36.745572 output: Hash algo: crc32
295 16:34:36.745621 output: Hash value: a9713552
296 16:34:36.745675 output: Image 2 (ramdisk-1)
297 16:34:36.745727 output: Description: unavailable
298 16:34:36.745776 output: Created: Mon Jun 17 17:34:36 2024
299 16:34:36.745828 output: Type: RAMDisk Image
300 16:34:36.745877 output: Compression: uncompressed
301 16:34:36.745924 output: Data Size: 18744442 Bytes = 18305.12 KiB = 17.88 MiB
302 16:34:36.745971 output: Architecture: AArch64
303 16:34:36.746061 output: OS: Linux
304 16:34:36.746112 output: Load Address: unavailable
305 16:34:36.746160 output: Entry Point: unavailable
306 16:34:36.746207 output: Hash algo: crc32
307 16:34:36.746254 output: Hash value: 84d1448f
308 16:34:36.746301 output: Default Configuration: 'conf-1'
309 16:34:36.746351 output: Configuration 0 (conf-1)
310 16:34:36.746400 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 16:34:36.746448 output: Kernel: kernel-1
312 16:34:36.746494 output: Init Ramdisk: ramdisk-1
313 16:34:36.746540 output: FDT: fdt-1
314 16:34:36.746586 output: Loadables: kernel-1
315 16:34:36.746635 output:
316 16:34:36.746769 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 16:34:36.746854 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 16:34:36.746967 end: 1.6 prepare-tftp-overlay (duration 00:00:49) [common]
319 16:34:36.747054 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:01) [common]
320 16:34:36.747124 No LXC device requested
321 16:34:36.747192 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:34:36.747267 start: 1.8 deploy-device-env (timeout 00:09:01) [common]
323 16:34:36.747336 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:34:36.747398 Checking files for TFTP limit of 4294967296 bytes.
325 16:34:36.747867 end: 1 tftp-deploy (duration 00:00:59) [common]
326 16:34:36.747971 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:34:36.748052 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:34:36.748162 substitutions:
329 16:34:36.748223 - {DTB}: 14396137/tftp-deploy-tx65ao95/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 16:34:36.748279 - {INITRD}: 14396137/tftp-deploy-tx65ao95/ramdisk/ramdisk.cpio.gz
331 16:34:36.748331 - {KERNEL}: 14396137/tftp-deploy-tx65ao95/kernel/Image
332 16:34:36.748387 - {LAVA_MAC}: None
333 16:34:36.748440 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto
334 16:34:36.748490 - {NFS_SERVER_IP}: 192.168.201.1
335 16:34:36.748539 - {PRESEED_CONFIG}: None
336 16:34:36.748595 - {PRESEED_LOCAL}: None
337 16:34:36.748650 - {RAMDISK}: 14396137/tftp-deploy-tx65ao95/ramdisk/ramdisk.cpio.gz
338 16:34:36.748699 - {ROOT_PART}: None
339 16:34:36.748746 - {ROOT}: None
340 16:34:36.748793 - {SERVER_IP}: 192.168.201.1
341 16:34:36.748843 - {TEE}: None
342 16:34:36.748893 Parsed boot commands:
343 16:34:36.748939 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:34:36.749087 Parsed boot commands: tftpboot 192.168.201.1 14396137/tftp-deploy-tx65ao95/kernel/image.itb 14396137/tftp-deploy-tx65ao95/kernel/cmdline
345 16:34:36.749170 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:34:36.749247 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:34:36.749328 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:34:36.749404 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:34:36.749464 Not connected, no need to disconnect.
350 16:34:36.749530 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:34:36.749605 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:34:36.749689 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-1'
353 16:34:36.753089 Setting prompt string to ['lava-test: # ']
354 16:34:36.753410 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:34:36.753512 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:34:36.753633 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:34:36.753774 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:34:36.753989 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-1']
359 16:34:58.726717 Returned 0 in 21 seconds
360 16:34:58.827253 end: 2.2.2.1 pdu-reboot (duration 00:00:22) [common]
362 16:34:58.827551 end: 2.2.2 reset-device (duration 00:00:22) [common]
363 16:34:58.827647 start: 2.2.3 depthcharge-start (timeout 00:04:38) [common]
364 16:34:58.827742 Setting prompt string to 'Starting depthcharge on Juniper...'
365 16:34:58.827805 Changing prompt to 'Starting depthcharge on Juniper...'
366 16:34:58.827870 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 16:34:58.828313 [Enter `^Ec?' for help]
368 16:34:58.828428 [DL] 00000000 00000000 010701
369 16:34:58.828530
370 16:34:58.828630
371 16:34:58.828728 F0: 102B 0000
372 16:34:58.828814
373 16:34:58.828893 F3: 1006 0033 [0200]
374 16:34:58.828978
375 16:34:58.829061 F3: 4001 00E0 [0200]
376 16:34:58.829142
377 16:34:58.829226 F3: 0000 0000
378 16:34:58.829309
379 16:34:58.829391 V0: 0000 0000 [0001]
380 16:34:58.829477
381 16:34:58.829560 00: 1027 0002
382 16:34:58.829644
383 16:34:58.829731 01: 0000 0000
384 16:34:58.829817
385 16:34:58.829897 BP: 0C00 0251 [0000]
386 16:34:58.829977
387 16:34:58.830066 G0: 1182 0000
388 16:34:58.830144
389 16:34:58.830223 EC: 0004 0000 [0001]
390 16:34:58.830305
391 16:34:58.830364 S7: 0000 0000 [0000]
392 16:34:58.830414
393 16:34:58.830463 CC: 0000 0000 [0001]
394 16:34:58.830527
395 16:34:58.830606 T0: 0000 00DB [000F]
396 16:34:58.830657
397 16:34:58.830706 Jump to BL
398 16:34:58.830755
399 16:34:58.830807
400 16:34:58.830856
401 16:34:58.830906 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 16:34:58.830958 ARM64: Exception handlers installed.
403 16:34:58.831008 ARM64: Testing exception
404 16:34:58.831057 ARM64: Done test exception
405 16:34:58.831105 WDT: Last reset was cold boot
406 16:34:58.831154 SPI0(PAD0) initialized at 992727 Hz
407 16:34:58.831203 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 16:34:58.831256 Manufacturer: ef
409 16:34:58.831305 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 16:34:58.831355 Probing TPM: . done!
411 16:34:58.831404 TPM ready after 0 ms
412 16:34:58.831454 Connected to device vid:did:rid of 1ae0:0028:00
413 16:34:58.831504 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
414 16:34:58.831554 Initialized TPM device CR50 revision 0
415 16:34:58.831604 tlcl_send_startup: Startup return code is 0
416 16:34:58.831654 TPM: setup succeeded
417 16:34:58.831703 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 16:34:58.831753 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 16:34:58.831806 in-header: 03 19 00 00 08 00 00 00
420 16:34:58.831869 in-data: a2 e0 47 00 13 00 00 00
421 16:34:58.831919 Chrome EC: UHEPI supported
422 16:34:58.831968 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 16:34:58.832018 in-header: 03 a1 00 00 08 00 00 00
424 16:34:58.832067 in-data: 84 60 60 10 00 00 00 00
425 16:34:58.832116 Phase 1
426 16:34:58.832165 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 16:34:58.832214 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 16:34:58.832264 VB2:vb2_check_recovery() Recovery was requested manually
429 16:34:58.832317 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 16:34:58.832366 Recovery requested (1009000e)
431 16:34:58.832415 tlcl_extend: response is 0
432 16:34:58.832465 tlcl_extend: response is 0
433 16:34:58.832516
434 16:34:58.832564
435 16:34:58.832627 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 16:34:58.832682 ARM64: Exception handlers installed.
437 16:34:58.832731 ARM64: Testing exception
438 16:34:58.832784 ARM64: Done test exception
439 16:34:58.832834 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x826a, sec=0x2028
440 16:34:58.832887 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 16:34:58.832937 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 16:34:58.832986 [RTC]rtc_get_frequency_meter,134: input=0xf, output=876
443 16:34:58.833036 [RTC]rtc_get_frequency_meter,134: input=0x7, output=743
444 16:34:58.833085 [RTC]rtc_get_frequency_meter,134: input=0xb, output=809
445 16:34:58.833134 [RTC]rtc_get_frequency_meter,134: input=0x9, output=776
446 16:34:58.833182 [RTC]rtc_get_frequency_meter,134: input=0xa, output=793
447 16:34:58.833231 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x826a
448 16:34:58.833280 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
449 16:34:58.833332 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
450 16:34:58.833383 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
451 16:34:58.833433 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
452 16:34:58.833483 in-header: 03 19 00 00 08 00 00 00
453 16:34:58.833532 in-data: a2 e0 47 00 13 00 00 00
454 16:34:58.833584 Chrome EC: UHEPI supported
455 16:34:58.833635 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
456 16:34:58.833685 in-header: 03 a1 00 00 08 00 00 00
457 16:34:58.833735 in-data: 84 60 60 10 00 00 00 00
458 16:34:58.833785 Skip loading cached calibration data
459 16:34:58.833838 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
460 16:34:58.833888 in-header: 03 a1 00 00 08 00 00 00
461 16:34:58.833937 in-data: 84 60 60 10 00 00 00 00
462 16:34:58.833994 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
463 16:34:58.834046 in-header: 03 a1 00 00 08 00 00 00
464 16:34:58.834095 in-data: 84 60 60 10 00 00 00 00
465 16:34:58.834144 ADC[3]: Raw value=216781 ID=1
466 16:34:58.834194 Manufacturer: ef
467 16:34:58.834242 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
468 16:34:58.834310 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
469 16:34:58.834392 CBFS @ 21000 size 3d4000
470 16:34:58.834443 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
471 16:34:58.834493 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
472 16:34:58.834543 CBFS: Found @ offset 3c700 size 44
473 16:34:58.834604 DRAM-K: Full Calibration
474 16:34:58.834655 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
475 16:34:58.834704 CBFS @ 21000 size 3d4000
476 16:34:58.834754 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
477 16:34:58.834807 CBFS: Locating 'fallback/dram'
478 16:34:58.834857 CBFS: Found @ offset 24b00 size 12268
479 16:34:58.834906 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
480 16:34:58.834955 ddr_geometry: 1, config: 0x0
481 16:34:58.835006 header.status = 0x0
482 16:34:58.835056 header.magic = 0x44524d4b (expected: 0x44524d4b)
483 16:34:58.835105 header.version = 0x5 (expected: 0x5)
484 16:34:58.835155 header.size = 0x8f0 (expected: 0x8f0)
485 16:34:58.835220 header.config = 0x0
486 16:34:58.835280 header.flags = 0x0
487 16:34:58.835329 header.checksum = 0x0
488 16:34:58.835584 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
489 16:34:58.835706 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
490 16:34:58.835803 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
491 16:34:58.835925 ddr_geometry:1
492 16:34:58.836030 [EMI] new MDL number = 1
493 16:34:58.836120 dram_cbt_mode_extern: 0
494 16:34:58.836210 dram_cbt_mode [RK0]: 0, [RK1]: 0
495 16:34:58.836294 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
496 16:34:58.836375
497 16:34:58.836468
498 16:34:58.836546 [Bianco] ETT version 0.0.0.1
499 16:34:58.836625 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
500 16:34:58.836719
501 16:34:58.836809 vSetVcoreByFreq with vcore:762500, freq=1600
502 16:34:58.836890
503 16:34:58.836984 [DramcInit]
504 16:34:58.837062 AutoRefreshCKEOff AutoREF OFF
505 16:34:58.837149 DDRPhyPLLSetting-CKEOFF
506 16:34:58.837230 DDRPhyPLLSetting-CKEON
507 16:34:58.837306
508 16:34:58.837396 Enable WDQS
509 16:34:58.837473 [ModeRegInit_LP4] CH0 RK0
510 16:34:58.837551 Write Rank0 MR13 =0x18
511 16:34:58.837642 Write Rank0 MR12 =0x5d
512 16:34:58.837719 Write Rank0 MR1 =0x56
513 16:34:58.837806 Write Rank0 MR2 =0x1a
514 16:34:58.837884 Write Rank0 MR11 =0x0
515 16:34:58.837967 Write Rank0 MR22 =0x38
516 16:34:58.838036 Write Rank0 MR14 =0x5d
517 16:34:58.838087 Write Rank0 MR3 =0x30
518 16:34:58.838136 Write Rank0 MR13 =0x58
519 16:34:58.838189 Write Rank0 MR12 =0x5d
520 16:34:58.838238 Write Rank0 MR1 =0x56
521 16:34:58.838287 Write Rank0 MR2 =0x2d
522 16:34:58.838337 Write Rank0 MR11 =0x23
523 16:34:58.838385 Write Rank0 MR22 =0x34
524 16:34:58.838433 Write Rank0 MR14 =0x10
525 16:34:58.838481 Write Rank0 MR3 =0x30
526 16:34:58.838532 Write Rank0 MR13 =0xd8
527 16:34:58.838583 [ModeRegInit_LP4] CH0 RK1
528 16:34:58.838633 Write Rank1 MR13 =0x18
529 16:34:58.838681 Write Rank1 MR12 =0x5d
530 16:34:58.838730 Write Rank1 MR1 =0x56
531 16:34:58.838778 Write Rank1 MR2 =0x1a
532 16:34:58.838827 Write Rank1 MR11 =0x0
533 16:34:58.838887 Write Rank1 MR22 =0x38
534 16:34:58.838955 Write Rank1 MR14 =0x5d
535 16:34:58.839006 Write Rank1 MR3 =0x30
536 16:34:58.839056 Write Rank1 MR13 =0x58
537 16:34:58.839105 Write Rank1 MR12 =0x5d
538 16:34:58.839154 Write Rank1 MR1 =0x56
539 16:34:58.839202 Write Rank1 MR2 =0x2d
540 16:34:58.839251 Write Rank1 MR11 =0x23
541 16:34:58.839310 Write Rank1 MR22 =0x34
542 16:34:58.839361 Write Rank1 MR14 =0x10
543 16:34:58.839409 Write Rank1 MR3 =0x30
544 16:34:58.839457 Write Rank1 MR13 =0xd8
545 16:34:58.839533 [ModeRegInit_LP4] CH1 RK0
546 16:34:58.839585 Write Rank0 MR13 =0x18
547 16:34:58.839634 Write Rank0 MR12 =0x5d
548 16:34:58.839684 Write Rank0 MR1 =0x56
549 16:34:58.839734 Write Rank0 MR2 =0x1a
550 16:34:58.839783 Write Rank0 MR11 =0x0
551 16:34:58.839831 Write Rank0 MR22 =0x38
552 16:34:58.839879 Write Rank0 MR14 =0x5d
553 16:34:58.839931 Write Rank0 MR3 =0x30
554 16:34:58.839979 Write Rank0 MR13 =0x58
555 16:34:58.840028 Write Rank0 MR12 =0x5d
556 16:34:58.840076 Write Rank0 MR1 =0x56
557 16:34:58.840144 Write Rank0 MR2 =0x2d
558 16:34:58.840193 Write Rank0 MR11 =0x23
559 16:34:58.840241 Write Rank0 MR22 =0x34
560 16:34:58.840290 Write Rank0 MR14 =0x10
561 16:34:58.840358 Write Rank0 MR3 =0x30
562 16:34:58.840407 Write Rank0 MR13 =0xd8
563 16:34:58.840456 [ModeRegInit_LP4] CH1 RK1
564 16:34:58.840503 Write Rank1 MR13 =0x18
565 16:34:58.840555 Write Rank1 MR12 =0x5d
566 16:34:58.840603 Write Rank1 MR1 =0x56
567 16:34:58.840652 Write Rank1 MR2 =0x1a
568 16:34:58.840700 Write Rank1 MR11 =0x0
569 16:34:58.840750 Write Rank1 MR22 =0x38
570 16:34:58.840799 Write Rank1 MR14 =0x5d
571 16:34:58.840847 Write Rank1 MR3 =0x30
572 16:34:58.840896 Write Rank1 MR13 =0x58
573 16:34:58.840947 Write Rank1 MR12 =0x5d
574 16:34:58.840995 Write Rank1 MR1 =0x56
575 16:34:58.841043 Write Rank1 MR2 =0x2d
576 16:34:58.841091 Write Rank1 MR11 =0x23
577 16:34:58.841140 Write Rank1 MR22 =0x34
578 16:34:58.841188 Write Rank1 MR14 =0x10
579 16:34:58.841236 Write Rank1 MR3 =0x30
580 16:34:58.841284 Write Rank1 MR13 =0xd8
581 16:34:58.841332 match AC timing 3
582 16:34:58.841381 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
583 16:34:58.841435 [MiockJmeterHQA]
584 16:34:58.841484 vSetVcoreByFreq with vcore:762500, freq=1600
585 16:34:58.841535
586 16:34:58.841583 MIOCK jitter meter ch=0
587 16:34:58.841632
588 16:34:58.841686 1T = (89-15) = 74 dly cells
589 16:34:58.841775 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 844/100 ps
590 16:34:58.841854 vSetVcoreByFreq with vcore:725000, freq=1200
591 16:34:58.841934
592 16:34:58.842016 MIOCK jitter meter ch=0
593 16:34:58.842067
594 16:34:58.842116 1T = (84-13) = 71 dly cells
595 16:34:58.842167 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 880/100 ps
596 16:34:58.842217 vSetVcoreByFreq with vcore:725000, freq=800
597 16:34:58.842266
598 16:34:58.842315 MIOCK jitter meter ch=0
599 16:34:58.842364
600 16:34:58.842411 1T = (84-13) = 71 dly cells
601 16:34:58.842464 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 880/100 ps
602 16:34:58.842517 vSetVcoreByFreq with vcore:762500, freq=1600
603 16:34:58.842572 vSetVcoreByFreq with vcore:762500, freq=1600
604 16:34:58.842623
605 16:34:58.842671 K DRVP
606 16:34:58.842720 1. OCD DRVP=0 CALOUT=0
607 16:34:58.842770 1. OCD DRVP=1 CALOUT=0
608 16:34:58.842820 1. OCD DRVP=2 CALOUT=0
609 16:34:58.842870 1. OCD DRVP=3 CALOUT=0
610 16:34:58.842919 1. OCD DRVP=4 CALOUT=0
611 16:34:58.842972 1. OCD DRVP=5 CALOUT=0
612 16:34:58.843022 1. OCD DRVP=6 CALOUT=0
613 16:34:58.843075 1. OCD DRVP=7 CALOUT=0
614 16:34:58.843125 1. OCD DRVP=8 CALOUT=0
615 16:34:58.843174 1. OCD DRVP=9 CALOUT=1
616 16:34:58.843224
617 16:34:58.843275 1. OCD DRVP calibration OK! DRVP=9
618 16:34:58.843342
619 16:34:58.843419
620 16:34:58.843470
621 16:34:58.843519 K ODTN
622 16:34:58.843568 3. OCD ODTN=0 ,CALOUT=1
623 16:34:58.843643 3. OCD ODTN=1 ,CALOUT=1
624 16:34:58.843695 3. OCD ODTN=2 ,CALOUT=1
625 16:34:58.843746 3. OCD ODTN=3 ,CALOUT=1
626 16:34:58.843842 3. OCD ODTN=4 ,CALOUT=1
627 16:34:58.843896 3. OCD ODTN=5 ,CALOUT=1
628 16:34:58.843946 3. OCD ODTN=6 ,CALOUT=1
629 16:34:58.844030 3. OCD ODTN=7 ,CALOUT=1
630 16:34:58.844082 3. OCD ODTN=8 ,CALOUT=0
631 16:34:58.844132
632 16:34:58.844193 3. OCD ODTN calibration OK! ODTN=8
633 16:34:58.844247
634 16:34:58.844296 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=8
635 16:34:58.844347 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15
636 16:34:58.844414 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15 (After Adjust)
637 16:34:58.844466
638 16:34:58.844514 K DRVP
639 16:34:58.844564 1. OCD DRVP=0 CALOUT=0
640 16:34:58.844627 1. OCD DRVP=1 CALOUT=0
641 16:34:58.844678 1. OCD DRVP=2 CALOUT=0
642 16:34:58.844729 1. OCD DRVP=3 CALOUT=0
643 16:34:58.844781 1. OCD DRVP=4 CALOUT=0
644 16:34:58.844832 1. OCD DRVP=5 CALOUT=0
645 16:34:58.844882 1. OCD DRVP=6 CALOUT=0
646 16:34:58.844931 1. OCD DRVP=7 CALOUT=0
647 16:34:58.844981 1. OCD DRVP=8 CALOUT=0
648 16:34:58.845035 1. OCD DRVP=9 CALOUT=0
649 16:34:58.845085 1. OCD DRVP=10 CALOUT=1
650 16:34:58.845134
651 16:34:58.845183 1. OCD DRVP calibration OK! DRVP=10
652 16:34:58.845233
653 16:34:58.845281
654 16:34:58.845329
655 16:34:58.845377 K ODTN
656 16:34:58.845425 3. OCD ODTN=0 ,CALOUT=1
657 16:34:58.845675 3. OCD ODTN=1 ,CALOUT=1
658 16:34:58.845785 3. OCD ODTN=2 ,CALOUT=1
659 16:34:58.845885 3. OCD ODTN=3 ,CALOUT=1
660 16:34:58.846002 3. OCD ODTN=4 ,CALOUT=1
661 16:34:58.846109 3. OCD ODTN=5 ,CALOUT=1
662 16:34:58.846204 3. OCD ODTN=6 ,CALOUT=1
663 16:34:58.846291 3. OCD ODTN=7 ,CALOUT=1
664 16:34:58.846372 3. OCD ODTN=8 ,CALOUT=1
665 16:34:58.846451 3. OCD ODTN=9 ,CALOUT=1
666 16:34:58.846530 3. OCD ODTN=10 ,CALOUT=1
667 16:34:58.846615 3. OCD ODTN=11 ,CALOUT=1
668 16:34:58.846695 3. OCD ODTN=12 ,CALOUT=1
669 16:34:58.846774 3. OCD ODTN=13 ,CALOUT=1
670 16:34:58.846854 3. OCD ODTN=14 ,CALOUT=1
671 16:34:58.846907 3. OCD ODTN=15 ,CALOUT=0
672 16:34:58.846957
673 16:34:58.847006 3. OCD ODTN calibration OK! ODTN=15
674 16:34:58.847059
675 16:34:58.847109 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
676 16:34:58.847159 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
677 16:34:58.847209 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
678 16:34:58.847258
679 16:34:58.847306 [DramcInit]
680 16:34:58.847354 AutoRefreshCKEOff AutoREF OFF
681 16:34:58.847404 DDRPhyPLLSetting-CKEOFF
682 16:34:58.847452 DDRPhyPLLSetting-CKEON
683 16:34:58.847500
684 16:34:58.847551 Enable WDQS
685 16:34:58.847601 ==
686 16:34:58.847654 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 16:34:58.847704 fsp= 1, odt_onoff= 1, Byte mode= 0
688 16:34:58.847780 ==
689 16:34:58.847861 [Duty_Offset_Calibration]
690 16:34:58.847914
691 16:34:58.847964 ===========================
692 16:34:58.848014 B0:0 B1:0 CA:2
693 16:34:58.848063 ==
694 16:34:58.848115 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 16:34:58.848165 fsp= 1, odt_onoff= 1, Byte mode= 0
696 16:34:58.848215 ==
697 16:34:58.848263 [Duty_Offset_Calibration]
698 16:34:58.848311
699 16:34:58.848359 ===========================
700 16:34:58.848408 B0:0 B1:1 CA:1
701 16:34:58.848457 [ModeRegInit_LP4] CH0 RK0
702 16:34:58.848506 Write Rank0 MR13 =0x18
703 16:34:58.848555 Write Rank0 MR12 =0x5d
704 16:34:58.848603 Write Rank0 MR1 =0x56
705 16:34:58.848654 Write Rank0 MR2 =0x1a
706 16:34:58.848703 Write Rank0 MR11 =0x0
707 16:34:58.848753 Write Rank0 MR22 =0x38
708 16:34:58.848800 Write Rank0 MR14 =0x5d
709 16:34:58.848848 Write Rank0 MR3 =0x30
710 16:34:58.848896 Write Rank0 MR13 =0x58
711 16:34:58.848945 Write Rank0 MR12 =0x5d
712 16:34:58.848994 Write Rank0 MR1 =0x56
713 16:34:58.849041 Write Rank0 MR2 =0x2d
714 16:34:58.849089 Write Rank0 MR11 =0x23
715 16:34:58.849137 Write Rank0 MR22 =0x34
716 16:34:58.849185 Write Rank0 MR14 =0x10
717 16:34:58.849237 Write Rank0 MR3 =0x30
718 16:34:58.849285 Write Rank0 MR13 =0xd8
719 16:34:58.849333 [ModeRegInit_LP4] CH0 RK1
720 16:34:58.849382 Write Rank1 MR13 =0x18
721 16:34:58.849430 Write Rank1 MR12 =0x5d
722 16:34:58.849478 Write Rank1 MR1 =0x56
723 16:34:58.849527 Write Rank1 MR2 =0x1a
724 16:34:58.849575 Write Rank1 MR11 =0x0
725 16:34:58.849623 Write Rank1 MR22 =0x38
726 16:34:58.849672 Write Rank1 MR14 =0x5d
727 16:34:58.849720 Write Rank1 MR3 =0x30
728 16:34:58.849770 Write Rank1 MR13 =0x58
729 16:34:58.849819 Write Rank1 MR12 =0x5d
730 16:34:58.849868 Write Rank1 MR1 =0x56
731 16:34:58.849917 Write Rank1 MR2 =0x2d
732 16:34:58.849965 Write Rank1 MR11 =0x23
733 16:34:58.850023 Write Rank1 MR22 =0x34
734 16:34:58.850071 Write Rank1 MR14 =0x10
735 16:34:58.850119 Write Rank1 MR3 =0x30
736 16:34:58.850167 Write Rank1 MR13 =0xd8
737 16:34:58.850216 [ModeRegInit_LP4] CH1 RK0
738 16:34:58.850263 Write Rank0 MR13 =0x18
739 16:34:58.850311 Write Rank0 MR12 =0x5d
740 16:34:58.850362 Write Rank0 MR1 =0x56
741 16:34:58.850410 Write Rank0 MR2 =0x1a
742 16:34:58.850467 Write Rank0 MR11 =0x0
743 16:34:58.850517 Write Rank0 MR22 =0x38
744 16:34:58.850565 Write Rank0 MR14 =0x5d
745 16:34:58.850614 Write Rank0 MR3 =0x30
746 16:34:58.850668 Write Rank0 MR13 =0x58
747 16:34:58.850722 Write Rank0 MR12 =0x5d
748 16:34:58.850772 Write Rank0 MR1 =0x56
749 16:34:58.850821 Write Rank0 MR2 =0x2d
750 16:34:58.850868 Write Rank0 MR11 =0x23
751 16:34:58.850922 Write Rank0 MR22 =0x34
752 16:34:58.850972 Write Rank0 MR14 =0x10
753 16:34:58.851022 Write Rank0 MR3 =0x30
754 16:34:58.851070 Write Rank0 MR13 =0xd8
755 16:34:58.851118 [ModeRegInit_LP4] CH1 RK1
756 16:34:58.851167 Write Rank1 MR13 =0x18
757 16:34:58.851215 Write Rank1 MR12 =0x5d
758 16:34:58.851264 Write Rank1 MR1 =0x56
759 16:34:58.851313 Write Rank1 MR2 =0x1a
760 16:34:58.851361 Write Rank1 MR11 =0x0
761 16:34:58.851412 Write Rank1 MR22 =0x38
762 16:34:58.851461 Write Rank1 MR14 =0x5d
763 16:34:58.851509 Write Rank1 MR3 =0x30
764 16:34:58.851557 Write Rank1 MR13 =0x58
765 16:34:58.851606 Write Rank1 MR12 =0x5d
766 16:34:58.851655 Write Rank1 MR1 =0x56
767 16:34:58.851703 Write Rank1 MR2 =0x2d
768 16:34:58.851751 Write Rank1 MR11 =0x23
769 16:34:58.851800 Write Rank1 MR22 =0x34
770 16:34:58.851847 Write Rank1 MR14 =0x10
771 16:34:58.851896 Write Rank1 MR3 =0x30
772 16:34:58.851948 Write Rank1 MR13 =0xd8
773 16:34:58.851999 match AC timing 3
774 16:34:58.852047 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 16:34:58.852098 DramC Write-DBI off
776 16:34:58.852147 DramC Read-DBI off
777 16:34:58.852195 Write Rank0 MR13 =0x59
778 16:34:58.852242 ==
779 16:34:58.852292 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 16:34:58.852341 fsp= 1, odt_onoff= 1, Byte mode= 0
781 16:34:58.852391 ==
782 16:34:58.852443 === u2Vref_new: 0x56 --> 0x2d
783 16:34:58.852493 === u2Vref_new: 0x58 --> 0x38
784 16:34:58.852541 === u2Vref_new: 0x5a --> 0x39
785 16:34:58.852590 === u2Vref_new: 0x5c --> 0x3c
786 16:34:58.852639 === u2Vref_new: 0x5e --> 0x3d
787 16:34:58.852687 === u2Vref_new: 0x60 --> 0xa0
788 16:34:58.852736 [CA 0] Center 34 (6~63) winsize 58
789 16:34:58.852784 [CA 1] Center 36 (9~63) winsize 55
790 16:34:58.852833 [CA 2] Center 30 (2~59) winsize 58
791 16:34:58.852881 [CA 3] Center 26 (-2~54) winsize 57
792 16:34:58.852932 [CA 4] Center 26 (-2~54) winsize 57
793 16:34:58.852981 [CA 5] Center 31 (2~61) winsize 60
794 16:34:58.853031
795 16:34:58.853080 [CATrainingPosCal] consider 1 rank data
796 16:34:58.853128 u2DelayCellTimex100 = 844/100 ps
797 16:34:58.853176 CA0 delay=34 (6~63),Diff = 8 PI (9 cell)
798 16:34:58.853224 CA1 delay=36 (9~63),Diff = 10 PI (11 cell)
799 16:34:58.853279 CA2 delay=30 (2~59),Diff = 4 PI (4 cell)
800 16:34:58.853329 CA3 delay=26 (-2~54),Diff = 0 PI (0 cell)
801 16:34:58.853378 CA4 delay=26 (-2~54),Diff = 0 PI (0 cell)
802 16:34:58.853427 CA5 delay=31 (2~61),Diff = 5 PI (5 cell)
803 16:34:58.853479
804 16:34:58.853528 CA PerBit enable=1, Macro0, CA PI delay=26
805 16:34:58.853576 === u2Vref_new: 0x60 --> 0xa0
806 16:34:58.853624
807 16:34:58.853673 Vref(ca) range 1: 32
808 16:34:58.853721
809 16:34:58.853772 CS Dly= 10 (41-0-32)
810 16:34:58.853821 Write Rank0 MR13 =0xd8
811 16:34:58.853869 Write Rank0 MR13 =0xd8
812 16:34:58.853918 Write Rank0 MR12 =0x60
813 16:34:58.853969 Write Rank1 MR13 =0x59
814 16:34:58.854035 ==
815 16:34:58.854086 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
816 16:34:58.854373 fsp= 1, odt_onoff= 1, Byte mode= 0
817 16:34:58.854472 ==
818 16:34:58.854597 === u2Vref_new: 0x56 --> 0x2d
819 16:34:58.854693 === u2Vref_new: 0x58 --> 0x38
820 16:34:58.854824 === u2Vref_new: 0x5a --> 0x39
821 16:34:58.854945 === u2Vref_new: 0x5c --> 0x3c
822 16:34:58.855040 === u2Vref_new: 0x5e --> 0x3d
823 16:34:58.855162 === u2Vref_new: 0x60 --> 0xa0
824 16:34:58.855253 [CA 0] Center 36 (9~63) winsize 55
825 16:34:58.855339 [CA 1] Center 36 (9~63) winsize 55
826 16:34:58.855412 [CA 2] Center 31 (3~60) winsize 58
827 16:34:58.855505 [CA 3] Center 26 (-2~54) winsize 57
828 16:34:58.855583 [CA 4] Center 26 (-2~54) winsize 57
829 16:34:58.855681 [CA 5] Center 31 (2~61) winsize 60
830 16:34:58.855766
831 16:34:58.855879 [CATrainingPosCal] consider 2 rank data
832 16:34:58.855977 u2DelayCellTimex100 = 844/100 ps
833 16:34:58.856086 CA0 delay=36 (9~63),Diff = 10 PI (11 cell)
834 16:34:58.856177 CA1 delay=36 (9~63),Diff = 10 PI (11 cell)
835 16:34:58.856292 CA2 delay=31 (3~59),Diff = 5 PI (5 cell)
836 16:34:58.856388 CA3 delay=26 (-2~54),Diff = 0 PI (0 cell)
837 16:34:58.856489 CA4 delay=26 (-2~54),Diff = 0 PI (0 cell)
838 16:34:58.856577 CA5 delay=31 (2~61),Diff = 5 PI (5 cell)
839 16:34:58.856686
840 16:34:58.856777 CA PerBit enable=1, Macro0, CA PI delay=26
841 16:34:58.856881 === u2Vref_new: 0x5e --> 0x3d
842 16:34:58.856970
843 16:34:58.857081 Vref(ca) range 1: 30
844 16:34:58.857173
845 16:34:58.857260 CS Dly= 6 (37-0-32)
846 16:34:58.857351 Write Rank1 MR13 =0xd8
847 16:34:58.857441 Write Rank1 MR13 =0xd8
848 16:34:58.857537 Write Rank1 MR12 =0x5e
849 16:34:58.857628 [RankSwap] Rank num 2, (Multi 1), Rank 0
850 16:34:58.857724 Write Rank0 MR2 =0xad
851 16:34:58.857817 [Write Leveling]
852 16:34:58.857910 delay byte0 byte1 byte2 byte3
853 16:34:58.858023
854 16:34:58.858118 10 0 0
855 16:34:58.858217 11 0 0
856 16:34:58.858312 12 0 0
857 16:34:58.858405 13 0 0
858 16:34:58.858521 14 0 0
859 16:34:58.858602 15 0 0
860 16:34:58.858698 16 0 0
861 16:34:58.858778 17 0 0
862 16:34:58.858857 18 0 0
863 16:34:58.858952 19 0 0
864 16:34:58.859031 20 0 0
865 16:34:58.859127 21 0 0
866 16:34:58.859206 22 0 0
867 16:34:58.859303 23 0 0
868 16:34:58.859403 24 0 ff
869 16:34:58.859491 25 0 ff
870 16:34:58.859581 26 0 ff
871 16:34:58.859666 27 0 ff
872 16:34:58.859744 28 0 ff
873 16:34:58.859806 29 0 ff
874 16:34:58.859900 30 0 ff
875 16:34:58.859994 31 0 ff
876 16:34:58.860090 32 ff ff
877 16:34:58.860188 33 ff ff
878 16:34:58.860284 34 ff ff
879 16:34:58.860371 35 ff ff
880 16:34:58.860468 36 ff ff
881 16:34:58.860549 37 ff ff
882 16:34:58.860632 38 ff ff
883 16:34:58.860712 pass bytecount = 0xff (0xff: all bytes pass)
884 16:34:58.860789
885 16:34:58.860866 DQS0 dly: 32
886 16:34:58.860942 DQS1 dly: 24
887 16:34:58.861019 Write Rank0 MR2 =0x2d
888 16:34:58.861100 [RankSwap] Rank num 2, (Multi 1), Rank 0
889 16:34:58.861179 Write Rank0 MR1 =0xd6
890 16:34:58.861255 [Gating]
891 16:34:58.861332 ==
892 16:34:58.861409 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
893 16:34:58.861504 fsp= 1, odt_onoff= 1, Byte mode= 0
894 16:34:58.861585 ==
895 16:34:58.861664 3 1 0 |3534 3635 |(11 11)(11 11) |(0 0)(1 1)| 0
896 16:34:58.861745 3 1 4 |3534 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
897 16:34:58.861829 3 1 8 |3534 606 |(11 11)(11 11) |(1 1)(1 1)| 0
898 16:34:58.861909 3 1 12 |3534 1111 |(11 11)(11 11) |(1 1)(1 1)| 0
899 16:34:58.861998 3 1 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
900 16:34:58.862080 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
901 16:34:58.862163 [Byte 1] Lead/lag Transition tap number (1)
902 16:34:58.862241 3 1 24 |3534 504 |(11 11)(11 11) |(0 0)(0 0)| 0
903 16:34:58.862320 3 1 28 |3534 b0a |(11 11)(11 11) |(0 0)(0 0)| 0
904 16:34:58.862400 3 2 0 |3534 3434 |(11 11)(11 11) |(0 0)(0 0)| 0
905 16:34:58.862480 3 2 4 |3534 3433 |(11 11)(11 11) |(0 0)(0 0)| 0
906 16:34:58.862559 3 2 8 |3534 3535 |(11 11)(11 11) |(0 1)(0 1)| 0
907 16:34:58.862641 3 2 12 |201 1413 |(11 11)(11 11) |(0 1)(0 1)| 0
908 16:34:58.862724 3 2 16 |908 706 |(11 11)(11 11) |(1 1)(1 1)| 0
909 16:34:58.862804 3 2 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
910 16:34:58.862884 3 2 24 |3d3d 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
911 16:34:58.862964 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 16:34:58.863044 3 3 0 |3d3d 3c3c |(11 11)(10 10) |(1 1)(0 0)| 0
913 16:34:58.863124 3 3 4 |3d3d 3b3b |(11 11)(11 11) |(1 1)(1 1)| 0
914 16:34:58.863207 3 3 8 |3d3d 1313 |(11 11)(11 11) |(1 1)(1 1)| 0
915 16:34:58.863286 3 3 12 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
916 16:34:58.863366 3 3 16 |201 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
917 16:34:58.863449 3 3 20 |3534 403 |(11 11)(11 11) |(1 1)(1 1)| 0
918 16:34:58.863531 [Byte 0] Lead/lag Transition tap number (1)
919 16:34:58.863610 [Byte 1] Lead/lag Transition tap number (1)
920 16:34:58.863694 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
921 16:34:58.863777 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
922 16:34:58.863857 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
923 16:34:58.863937 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
924 16:34:58.864017 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
925 16:34:58.864097 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
926 16:34:58.864178 3 4 16 |403 201 |(11 11)(11 11) |(0 1)(0 1)| 0
927 16:34:58.864259 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 16:34:58.864339 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 16:34:58.864419 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 16:34:58.864498 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 16:34:58.864578 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 16:34:58.864657 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 16:34:58.864744 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 16:34:58.864798 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 16:34:58.864849 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 16:34:58.864899 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
937 16:34:58.864949 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
938 16:34:58.864999 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
939 16:34:58.865049 [Byte 0] Lead/lag falling Transition (3, 6, 0)
940 16:34:58.865310 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
941 16:34:58.865368 [Byte 1] Lead/lag falling Transition (3, 6, 4)
942 16:34:58.865419 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
943 16:34:58.865470 [Byte 0] Lead/lag Transition tap number (3)
944 16:34:58.865520 3 6 12 |202 3e3d |(11 11)(11 11) |(0 0)(1 0)| 0
945 16:34:58.865571 [Byte 1] Lead/lag Transition tap number (3)
946 16:34:58.865620 3 6 16 |4040 e0e |(1 1)(11 11) |(0 0)(0 0)| 0
947 16:34:58.865671 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 16:34:58.865726 [Byte 0]First pass (3, 6, 20)
949 16:34:58.865777 [Byte 1]First pass (3, 6, 20)
950 16:34:58.865826 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 16:34:58.865877 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 16:34:58.865928 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 16:34:58.865978 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 16:34:58.866041 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 16:34:58.866092 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 16:34:58.866142 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
957 16:34:58.866195 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
958 16:34:58.866246 All bytes gating window > 1UI, Early break!
959 16:34:58.866295
960 16:34:58.866344 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
961 16:34:58.866393
962 16:34:58.866442 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
963 16:34:58.866490
964 16:34:58.866539
965 16:34:58.866586
966 16:34:58.866634 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
967 16:34:58.866683
968 16:34:58.866735 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
969 16:34:58.866786
970 16:34:58.866834
971 16:34:58.866888 Write Rank0 MR1 =0x56
972 16:34:58.866937
973 16:34:58.866986 best RODT dly(2T, 0.5T) = (2, 3)
974 16:34:58.867034
975 16:34:58.867090 best RODT dly(2T, 0.5T) = (2, 3)
976 16:34:58.867144 ==
977 16:34:58.867194 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
978 16:34:58.867248 fsp= 1, odt_onoff= 1, Byte mode= 0
979 16:34:58.867297 ==
980 16:34:58.867347 Start DQ dly to find pass range UseTestEngine =0
981 16:34:58.867406 x-axis: bit #, y-axis: DQ dly (-127~63)
982 16:34:58.867463 RX Vref Scan = 0
983 16:34:58.867516 -26, [0] xxxxxxxx xxxxxxxx [MSB]
984 16:34:58.867569 -25, [0] xxxxxxxx xxxxxxxx [MSB]
985 16:34:58.867619 -24, [0] xxxxxxxx xxxxxxxx [MSB]
986 16:34:58.867669 -23, [0] xxxxxxxx xxxxxxxx [MSB]
987 16:34:58.867721 -22, [0] xxxxxxxx xxxxxxxx [MSB]
988 16:34:58.867771 -21, [0] xxxxxxxx xxxxxxxx [MSB]
989 16:34:58.867821 -20, [0] xxxxxxxx xxxxxxxx [MSB]
990 16:34:58.867871 -19, [0] xxxxxxxx xxxxxxxx [MSB]
991 16:34:58.867934 -18, [0] xxxxxxxx xxxxxxxx [MSB]
992 16:34:58.867986 -17, [0] xxxxxxxx xxxxxxxx [MSB]
993 16:34:58.868035 -16, [0] xxxxxxxx xxxxxxxx [MSB]
994 16:34:58.868085 -15, [0] xxxxxxxx xxxxxxxx [MSB]
995 16:34:58.868134 -14, [0] xxxxxxxx xxxxxxxx [MSB]
996 16:34:58.868183 -13, [0] xxxxxxxx xxxxxxxx [MSB]
997 16:34:58.868236 -12, [0] xxxxxxxx xxxxxxxx [MSB]
998 16:34:58.868285 -11, [0] xxxxxxxx xxxxxxxx [MSB]
999 16:34:58.868334 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1000 16:34:58.868383 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1001 16:34:58.868433 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1002 16:34:58.868489 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1003 16:34:58.868540 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1004 16:34:58.868600 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1005 16:34:58.868650 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1006 16:34:58.868699 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1007 16:34:58.868749 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1008 16:34:58.868799 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1009 16:34:58.868852 0, [0] xxxxxxxx xxxxxxxx [MSB]
1010 16:34:58.868902 1, [0] xxxxxxxx oxxxxxxx [MSB]
1011 16:34:58.868953 2, [0] xxxxxxxx oxxxxxxx [MSB]
1012 16:34:58.869002 3, [0] xxxxxxxx oxxoxxxx [MSB]
1013 16:34:58.869051 4, [0] xxxoxoxx ooxoxoxx [MSB]
1014 16:34:58.869100 5, [0] xxxoxoxx ooxoooox [MSB]
1015 16:34:58.869150 6, [0] xxxoxoxx ooxoooox [MSB]
1016 16:34:58.869200 7, [0] xxxoxoxo ooxoooox [MSB]
1017 16:34:58.869253 8, [0] xoxoxooo ooxooooo [MSB]
1018 16:34:58.869304 9, [0] ooxooooo ooxooooo [MSB]
1019 16:34:58.869353 31, [0] oooooooo oooooooo [MSB]
1020 16:34:58.869402 32, [0] oooxoooo oooooooo [MSB]
1021 16:34:58.869452 33, [0] oooxoooo xooooooo [MSB]
1022 16:34:58.869504 34, [0] oooxoooo xooooooo [MSB]
1023 16:34:58.869555 35, [0] oooxoooo xooxoooo [MSB]
1024 16:34:58.869605 36, [0] oooxoxxo xxoxxooo [MSB]
1025 16:34:58.869654 37, [0] oooxoxxo xxoxxoxo [MSB]
1026 16:34:58.869704 38, [0] oooxoxxo xxoxxxxo [MSB]
1027 16:34:58.869756 39, [0] oxoxoxxx xxoxxxxo [MSB]
1028 16:34:58.869805 40, [0] xxoxxxxx xxoxxxxo [MSB]
1029 16:34:58.869855 41, [0] xxoxxxxx xxoxxxxx [MSB]
1030 16:34:58.869905 42, [0] xxxxxxxx xxxxxxxx [MSB]
1031 16:34:58.869955 iDelay=42, Bit 0, Center 24 (9 ~ 39) 31
1032 16:34:58.870021 iDelay=42, Bit 1, Center 23 (8 ~ 38) 31
1033 16:34:58.870072 iDelay=42, Bit 2, Center 25 (10 ~ 41) 32
1034 16:34:58.870121 iDelay=42, Bit 3, Center 17 (4 ~ 31) 28
1035 16:34:58.870170 iDelay=42, Bit 4, Center 24 (9 ~ 39) 31
1036 16:34:58.870219 iDelay=42, Bit 5, Center 19 (4 ~ 35) 32
1037 16:34:58.870272 iDelay=42, Bit 6, Center 21 (8 ~ 35) 28
1038 16:34:58.870332 iDelay=42, Bit 7, Center 22 (7 ~ 38) 32
1039 16:34:58.870382 iDelay=42, Bit 8, Center 16 (1 ~ 32) 32
1040 16:34:58.870431 iDelay=42, Bit 9, Center 19 (4 ~ 35) 32
1041 16:34:58.870481 iDelay=42, Bit 10, Center 25 (10 ~ 41) 32
1042 16:34:58.870529 iDelay=42, Bit 11, Center 18 (3 ~ 34) 32
1043 16:34:58.870578 iDelay=42, Bit 12, Center 20 (5 ~ 35) 31
1044 16:34:58.870626 iDelay=42, Bit 13, Center 20 (4 ~ 37) 34
1045 16:34:58.870676 iDelay=42, Bit 14, Center 20 (5 ~ 36) 32
1046 16:34:58.870725 iDelay=42, Bit 15, Center 24 (8 ~ 40) 33
1047 16:34:58.870777 ==
1048 16:34:58.870827 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1049 16:34:58.870876 fsp= 1, odt_onoff= 1, Byte mode= 0
1050 16:34:58.870926 ==
1051 16:34:58.870974 DQS Delay:
1052 16:34:58.871022 DQS0 = 0, DQS1 = 0
1053 16:34:58.871071 DQM Delay:
1054 16:34:58.871119 DQM0 = 21, DQM1 = 20
1055 16:34:58.871168 DQ Delay:
1056 16:34:58.871217 DQ0 =24, DQ1 =23, DQ2 =25, DQ3 =17
1057 16:34:58.871268 DQ4 =24, DQ5 =19, DQ6 =21, DQ7 =22
1058 16:34:58.871317 DQ8 =16, DQ9 =19, DQ10 =25, DQ11 =18
1059 16:34:58.871368 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
1060 16:34:58.871417
1061 16:34:58.871465
1062 16:34:58.871512 DramC Write-DBI off
1063 16:34:58.871560 ==
1064 16:34:58.871608 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1065 16:34:58.871657 fsp= 1, odt_onoff= 1, Byte mode= 0
1066 16:34:58.871705 ==
1067 16:34:58.871973 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1068 16:34:58.872046
1069 16:34:58.872144 Begin, DQ Scan Range 920~1176
1070 16:34:58.872239
1071 16:34:58.872349
1072 16:34:58.872448 TX Vref Scan disable
1073 16:34:58.872545 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1074 16:34:58.872663 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1075 16:34:58.872764 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1076 16:34:58.872869 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1077 16:34:58.872962 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1078 16:34:58.873056 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1079 16:34:58.873147 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1080 16:34:58.873227 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1081 16:34:58.873307 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1082 16:34:58.873398 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1083 16:34:58.873478 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1084 16:34:58.873537 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1085 16:34:58.873588 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1086 16:34:58.873638 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1087 16:34:58.873689 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1088 16:34:58.873743 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1089 16:34:58.873793 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1090 16:34:58.873843 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1091 16:34:58.873893 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1092 16:34:58.873947 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1093 16:34:58.874013 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1094 16:34:58.874065 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1095 16:34:58.874117 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1096 16:34:58.874167 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1097 16:34:58.874216 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1098 16:34:58.874266 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1099 16:34:58.874316 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1100 16:34:58.874366 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1101 16:34:58.874420 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1102 16:34:58.874472 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1103 16:34:58.874522 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1104 16:34:58.874572 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1105 16:34:58.874625 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1106 16:34:58.874675 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1107 16:34:58.874724 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1108 16:34:58.874774 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1109 16:34:58.874824 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1110 16:34:58.874874 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1111 16:34:58.874927 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1112 16:34:58.874977 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1113 16:34:58.875027 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1114 16:34:58.875077 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1115 16:34:58.875126 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1116 16:34:58.875176 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1117 16:34:58.875227 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1118 16:34:58.875276 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1119 16:34:58.875325 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1120 16:34:58.875375 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1121 16:34:58.875425 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1122 16:34:58.875486 969 |3 6 9|[0] xxxxxxxx ooxoooxx [MSB]
1123 16:34:58.875539 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1124 16:34:58.875595 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1125 16:34:58.875644 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1126 16:34:58.875694 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1127 16:34:58.875743 974 |3 6 14|[0] xxxxxxxx ooooooox [MSB]
1128 16:34:58.875792 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1129 16:34:58.875842 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1130 16:34:58.875892 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1131 16:34:58.875942 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1132 16:34:58.875995 979 |3 6 19|[0] xxxoxoox oooooooo [MSB]
1133 16:34:58.876045 980 |3 6 20|[0] xoxooooo oooooooo [MSB]
1134 16:34:58.876095 988 |3 6 28|[0] oooooooo xooooooo [MSB]
1135 16:34:58.876144 989 |3 6 29|[0] oooooooo xooxoooo [MSB]
1136 16:34:58.876194 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1137 16:34:58.876244 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1138 16:34:58.876294 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1139 16:34:58.876344 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1140 16:34:58.876393 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1141 16:34:58.876445 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1142 16:34:58.876498 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1143 16:34:58.876550 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1144 16:34:58.876599 998 |3 6 38|[0] oooxoxxo xxxxxxxx [MSB]
1145 16:34:58.876656 999 |3 6 39|[0] oooxxxxx xxxxxxxx [MSB]
1146 16:34:58.876707 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1147 16:34:58.876757 Byte0, DQ PI dly=988, DQM PI dly= 988
1148 16:34:58.876806 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
1149 16:34:58.876856
1150 16:34:58.876905 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
1151 16:34:58.876954
1152 16:34:58.877006 Byte1, DQ PI dly=980, DQM PI dly= 980
1153 16:34:58.877055 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1154 16:34:58.877104
1155 16:34:58.877152 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1156 16:34:58.877201
1157 16:34:58.877249 ==
1158 16:34:58.877297 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1159 16:34:58.877346 fsp= 1, odt_onoff= 1, Byte mode= 0
1160 16:34:58.877395 ==
1161 16:34:58.877445 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1162 16:34:58.877496
1163 16:34:58.877546 Begin, DQ Scan Range 956~1020
1164 16:34:58.877595 Write Rank0 MR14 =0x0
1165 16:34:58.877643
1166 16:34:58.877691 CH=0, VrefRange= 0, VrefLevel = 0
1167 16:34:58.877747 TX Bit0 (984~994) 11 989, Bit8 (970~982) 13 976,
1168 16:34:58.877798 TX Bit1 (982~995) 14 988, Bit9 (972~985) 14 978,
1169 16:34:58.877848 TX Bit2 (984~994) 11 989, Bit10 (977~987) 11 982,
1170 16:34:58.877897 TX Bit3 (978~989) 12 983, Bit11 (971~983) 13 977,
1171 16:34:58.877947 TX Bit4 (981~993) 13 987, Bit12 (972~985) 14 978,
1172 16:34:58.878010 TX Bit5 (982~991) 10 986, Bit13 (973~984) 12 978,
1173 16:34:58.878066 TX Bit6 (981~993) 13 987, Bit14 (974~986) 13 980,
1174 16:34:58.878115 TX Bit7 (981~993) 13 987, Bit15 (978~989) 12 983,
1175 16:34:58.878164
1176 16:34:58.878212 Write Rank0 MR14 =0x2
1177 16:34:58.878261
1178 16:34:58.878514 CH=0, VrefRange= 0, VrefLevel = 2
1179 16:34:58.878592 TX Bit0 (984~995) 12 989, Bit8 (969~983) 15 976,
1180 16:34:58.878692 TX Bit1 (982~995) 14 988, Bit9 (972~986) 15 979,
1181 16:34:58.878791 TX Bit2 (983~995) 13 989, Bit10 (977~989) 13 983,
1182 16:34:58.878890 TX Bit3 (979~990) 12 984, Bit11 (971~984) 14 977,
1183 16:34:58.878985 TX Bit4 (981~993) 13 987, Bit12 (971~986) 16 978,
1184 16:34:58.879072 TX Bit5 (981~992) 12 986, Bit13 (972~985) 14 978,
1185 16:34:58.879152 TX Bit6 (980~993) 14 986, Bit14 (974~987) 14 980,
1186 16:34:58.879231 TX Bit7 (981~994) 14 987, Bit15 (978~989) 12 983,
1187 16:34:58.879307
1188 16:34:58.879384 Write Rank0 MR14 =0x4
1189 16:34:58.879460
1190 16:34:58.879537 CH=0, VrefRange= 0, VrefLevel = 4
1191 16:34:58.879618 TX Bit0 (984~995) 12 989, Bit8 (969~984) 16 976,
1192 16:34:58.879698 TX Bit1 (981~996) 16 988, Bit9 (971~986) 16 978,
1193 16:34:58.879776 TX Bit2 (983~995) 13 989, Bit10 (976~989) 14 982,
1194 16:34:58.879854 TX Bit3 (978~991) 14 984, Bit11 (970~984) 15 977,
1195 16:34:58.879932 TX Bit4 (981~994) 14 987, Bit12 (971~986) 16 978,
1196 16:34:58.880009 TX Bit5 (980~992) 13 986, Bit13 (972~986) 15 979,
1197 16:34:58.880093 TX Bit6 (980~993) 14 986, Bit14 (973~988) 16 980,
1198 16:34:58.880172 TX Bit7 (981~994) 14 987, Bit15 (977~990) 14 983,
1199 16:34:58.880249
1200 16:34:58.880326 Write Rank0 MR14 =0x6
1201 16:34:58.880402
1202 16:34:58.880479 CH=0, VrefRange= 0, VrefLevel = 6
1203 16:34:58.880557 TX Bit0 (984~996) 13 990, Bit8 (969~984) 16 976,
1204 16:34:58.880640 TX Bit1 (981~996) 16 988, Bit9 (971~987) 17 979,
1205 16:34:58.880718 TX Bit2 (983~996) 14 989, Bit10 (976~990) 15 983,
1206 16:34:58.880796 TX Bit3 (978~992) 15 985, Bit11 (970~985) 16 977,
1207 16:34:58.880878 TX Bit4 (981~994) 14 987, Bit12 (971~987) 17 979,
1208 16:34:58.880957 TX Bit5 (980~993) 14 986, Bit13 (971~986) 16 978,
1209 16:34:58.881035 TX Bit6 (980~994) 15 987, Bit14 (973~989) 17 981,
1210 16:34:58.881113 TX Bit7 (980~995) 16 987, Bit15 (976~991) 16 983,
1211 16:34:58.881192
1212 16:34:58.881269 Write Rank0 MR14 =0x8
1213 16:34:58.881346
1214 16:34:58.881423 CH=0, VrefRange= 0, VrefLevel = 8
1215 16:34:58.881501 TX Bit0 (983~997) 15 990, Bit8 (969~985) 17 977,
1216 16:34:58.881579 TX Bit1 (981~997) 17 989, Bit9 (970~988) 19 979,
1217 16:34:58.881658 TX Bit2 (982~997) 16 989, Bit10 (976~991) 16 983,
1218 16:34:58.881739 TX Bit3 (978~992) 15 985, Bit11 (969~985) 17 977,
1219 16:34:58.881826 TX Bit4 (980~995) 16 987, Bit12 (970~988) 19 979,
1220 16:34:58.881911 TX Bit5 (980~993) 14 986, Bit13 (971~986) 16 978,
1221 16:34:58.882014 TX Bit6 (979~994) 16 986, Bit14 (972~989) 18 980,
1222 16:34:58.882070 TX Bit7 (980~995) 16 987, Bit15 (976~991) 16 983,
1223 16:34:58.882120
1224 16:34:58.882169 Write Rank0 MR14 =0xa
1225 16:34:58.882219
1226 16:34:58.882271 CH=0, VrefRange= 0, VrefLevel = 10
1227 16:34:58.882322 TX Bit0 (982~998) 17 990, Bit8 (968~985) 18 976,
1228 16:34:58.882372 TX Bit1 (980~998) 19 989, Bit9 (970~989) 20 979,
1229 16:34:58.882421 TX Bit2 (981~997) 17 989, Bit10 (976~992) 17 984,
1230 16:34:58.882471 TX Bit3 (978~992) 15 985, Bit11 (969~986) 18 977,
1231 16:34:58.882519 TX Bit4 (980~996) 17 988, Bit12 (970~989) 20 979,
1232 16:34:58.882569 TX Bit5 (980~994) 15 987, Bit13 (970~987) 18 978,
1233 16:34:58.882619 TX Bit6 (979~995) 17 987, Bit14 (972~990) 19 981,
1234 16:34:58.882668 TX Bit7 (980~996) 17 988, Bit15 (976~992) 17 984,
1235 16:34:58.882718
1236 16:34:58.882766 Write Rank0 MR14 =0xc
1237 16:34:58.882818
1238 16:34:58.882868 CH=0, VrefRange= 0, VrefLevel = 12
1239 16:34:58.882918 TX Bit0 (983~999) 17 991, Bit8 (968~985) 18 976,
1240 16:34:58.882967 TX Bit1 (980~998) 19 989, Bit9 (969~989) 21 979,
1241 16:34:58.883016 TX Bit2 (982~998) 17 990, Bit10 (975~992) 18 983,
1242 16:34:58.883066 TX Bit3 (978~993) 16 985, Bit11 (969~986) 18 977,
1243 16:34:58.883115 TX Bit4 (980~996) 17 988, Bit12 (970~989) 20 979,
1244 16:34:58.883165 TX Bit5 (979~994) 16 986, Bit13 (970~988) 19 979,
1245 16:34:58.883214 TX Bit6 (979~995) 17 987, Bit14 (971~990) 20 980,
1246 16:34:58.883263 TX Bit7 (980~996) 17 988, Bit15 (975~992) 18 983,
1247 16:34:58.883312
1248 16:34:58.883363 Write Rank0 MR14 =0xe
1249 16:34:58.883411
1250 16:34:58.883459 CH=0, VrefRange= 0, VrefLevel = 14
1251 16:34:58.883508 TX Bit0 (981~1000) 20 990, Bit8 (968~986) 19 977,
1252 16:34:58.883558 TX Bit1 (980~999) 20 989, Bit9 (969~989) 21 979,
1253 16:34:58.883607 TX Bit2 (981~998) 18 989, Bit10 (975~991) 17 983,
1254 16:34:58.883658 TX Bit3 (977~993) 17 985, Bit11 (968~987) 20 977,
1255 16:34:58.883712 TX Bit4 (980~997) 18 988, Bit12 (969~989) 21 979,
1256 16:34:58.883762 TX Bit5 (979~994) 16 986, Bit13 (969~989) 21 979,
1257 16:34:58.883814 TX Bit6 (979~996) 18 987, Bit14 (971~991) 21 981,
1258 16:34:58.883864 TX Bit7 (980~997) 18 988, Bit15 (976~993) 18 984,
1259 16:34:58.883920
1260 16:34:58.883970 Write Rank0 MR14 =0x10
1261 16:34:58.884021
1262 16:34:58.884069 CH=0, VrefRange= 0, VrefLevel = 16
1263 16:34:58.884118 TX Bit0 (982~1000) 19 991, Bit8 (968~987) 20 977,
1264 16:34:58.884167 TX Bit1 (980~999) 20 989, Bit9 (969~989) 21 979,
1265 16:34:58.884217 TX Bit2 (981~999) 19 990, Bit10 (974~993) 20 983,
1266 16:34:58.884266 TX Bit3 (977~993) 17 985, Bit11 (968~988) 21 978,
1267 16:34:58.884315 TX Bit4 (979~998) 20 988, Bit12 (969~990) 22 979,
1268 16:34:58.884364 TX Bit5 (979~995) 17 987, Bit13 (969~989) 21 979,
1269 16:34:58.884415 TX Bit6 (979~996) 18 987, Bit14 (970~991) 22 980,
1270 16:34:58.884464 TX Bit7 (979~998) 20 988, Bit15 (974~993) 20 983,
1271 16:34:58.884516
1272 16:34:58.884565 Write Rank0 MR14 =0x12
1273 16:34:58.884614
1274 16:34:58.884662 CH=0, VrefRange= 0, VrefLevel = 18
1275 16:34:58.884711 TX Bit0 (981~1001) 21 991, Bit8 (968~988) 21 978,
1276 16:34:58.884761 TX Bit1 (979~1000) 22 989, Bit9 (969~990) 22 979,
1277 16:34:58.884810 TX Bit2 (982~1000) 19 991, Bit10 (974~993) 20 983,
1278 16:34:58.885062 TX Bit3 (976~994) 19 985, Bit11 (968~989) 22 978,
1279 16:34:58.885152 TX Bit4 (979~999) 21 989, Bit12 (969~990) 22 979,
1280 16:34:58.885251 TX Bit5 (979~996) 18 987, Bit13 (969~990) 22 979,
1281 16:34:58.885348 TX Bit6 (979~997) 19 988, Bit14 (970~991) 22 980,
1282 16:34:58.885448 TX Bit7 (979~999) 21 989, Bit15 (974~994) 21 984,
1283 16:34:58.885545
1284 16:34:58.885638 Write Rank0 MR14 =0x14
1285 16:34:58.885722
1286 16:34:58.885800 CH=0, VrefRange= 0, VrefLevel = 20
1287 16:34:58.885882 TX Bit0 (981~1001) 21 991, Bit8 (968~989) 22 978,
1288 16:34:58.885960 TX Bit1 (979~1000) 22 989, Bit9 (968~991) 24 979,
1289 16:34:58.886052 TX Bit2 (980~1000) 21 990, Bit10 (974~994) 21 984,
1290 16:34:58.886134 TX Bit3 (977~994) 18 985, Bit11 (968~989) 22 978,
1291 16:34:58.886216 TX Bit4 (979~999) 21 989, Bit12 (969~990) 22 979,
1292 16:34:58.886295 TX Bit5 (979~996) 18 987, Bit13 (969~990) 22 979,
1293 16:34:58.886374 TX Bit6 (979~997) 19 988, Bit14 (970~992) 23 981,
1294 16:34:58.886452 TX Bit7 (979~999) 21 989, Bit15 (974~994) 21 984,
1295 16:34:58.886529
1296 16:34:58.886606 Write Rank0 MR14 =0x16
1297 16:34:58.886669
1298 16:34:58.886718 CH=0, VrefRange= 0, VrefLevel = 22
1299 16:34:58.886769 TX Bit0 (980~1001) 22 990, Bit8 (967~989) 23 978,
1300 16:34:58.886819 TX Bit1 (980~1000) 21 990, Bit9 (969~991) 23 980,
1301 16:34:58.886869 TX Bit2 (980~1001) 22 990, Bit10 (974~995) 22 984,
1302 16:34:58.886919 TX Bit3 (976~994) 19 985, Bit11 (968~989) 22 978,
1303 16:34:58.886968 TX Bit4 (979~1000) 22 989, Bit12 (968~991) 24 979,
1304 16:34:58.887018 TX Bit5 (979~997) 19 988, Bit13 (968~990) 23 979,
1305 16:34:58.887068 TX Bit6 (979~998) 20 988, Bit14 (969~992) 24 980,
1306 16:34:58.887117 TX Bit7 (979~1000) 22 989, Bit15 (974~994) 21 984,
1307 16:34:58.887167
1308 16:34:58.887219 Write Rank0 MR14 =0x18
1309 16:34:58.887269
1310 16:34:58.887318 CH=0, VrefRange= 0, VrefLevel = 24
1311 16:34:58.887367 TX Bit0 (980~1002) 23 991, Bit8 (967~989) 23 978,
1312 16:34:58.887417 TX Bit1 (979~1002) 24 990, Bit9 (968~991) 24 979,
1313 16:34:58.887467 TX Bit2 (980~1001) 22 990, Bit10 (973~995) 23 984,
1314 16:34:58.887517 TX Bit3 (976~995) 20 985, Bit11 (968~990) 23 979,
1315 16:34:58.887566 TX Bit4 (979~1000) 22 989, Bit12 (968~991) 24 979,
1316 16:34:58.887616 TX Bit5 (978~997) 20 987, Bit13 (968~991) 24 979,
1317 16:34:58.887666 TX Bit6 (978~999) 22 988, Bit14 (969~992) 24 980,
1318 16:34:58.887715 TX Bit7 (979~1000) 22 989, Bit15 (974~995) 22 984,
1319 16:34:58.887766
1320 16:34:58.887814 Write Rank0 MR14 =0x1a
1321 16:34:58.887862
1322 16:34:58.887911 CH=0, VrefRange= 0, VrefLevel = 26
1323 16:34:58.887960 TX Bit0 (980~1003) 24 991, Bit8 (967~990) 24 978,
1324 16:34:58.888008 TX Bit1 (979~1002) 24 990, Bit9 (968~991) 24 979,
1325 16:34:58.888057 TX Bit2 (980~1002) 23 991, Bit10 (972~996) 25 984,
1326 16:34:58.888106 TX Bit3 (976~995) 20 985, Bit11 (967~990) 24 978,
1327 16:34:58.888156 TX Bit4 (979~1001) 23 990, Bit12 (968~992) 25 980,
1328 16:34:58.888204 TX Bit5 (978~998) 21 988, Bit13 (968~991) 24 979,
1329 16:34:58.888253 TX Bit6 (978~999) 22 988, Bit14 (969~992) 24 980,
1330 16:34:58.888305 TX Bit7 (979~1001) 23 990, Bit15 (973~997) 25 985,
1331 16:34:58.888356
1332 16:34:58.888404 Write Rank0 MR14 =0x1c
1333 16:34:58.888452
1334 16:34:58.888499 CH=0, VrefRange= 0, VrefLevel = 28
1335 16:34:58.888548 TX Bit0 (980~1003) 24 991, Bit8 (967~990) 24 978,
1336 16:34:58.888598 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
1337 16:34:58.888646 TX Bit2 (980~1003) 24 991, Bit10 (973~996) 24 984,
1338 16:34:58.888695 TX Bit3 (975~995) 21 985, Bit11 (967~990) 24 978,
1339 16:34:58.888745 TX Bit4 (979~1001) 23 990, Bit12 (968~992) 25 980,
1340 16:34:58.888795 TX Bit5 (978~998) 21 988, Bit13 (968~991) 24 979,
1341 16:34:58.888847 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
1342 16:34:58.888897 TX Bit7 (979~1001) 23 990, Bit15 (974~996) 23 985,
1343 16:34:58.888945
1344 16:34:58.888993 Write Rank0 MR14 =0x1e
1345 16:34:58.889041
1346 16:34:58.889089 CH=0, VrefRange= 0, VrefLevel = 30
1347 16:34:58.889137 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
1348 16:34:58.889187 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
1349 16:34:58.889236 TX Bit2 (979~1003) 25 991, Bit10 (972~997) 26 984,
1350 16:34:58.889285 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1351 16:34:58.889333 TX Bit4 (979~1002) 24 990, Bit12 (968~991) 24 979,
1352 16:34:58.889387 TX Bit5 (978~999) 22 988, Bit13 (968~991) 24 979,
1353 16:34:58.889438 TX Bit6 (978~1000) 23 989, Bit14 (969~993) 25 981,
1354 16:34:58.889487 TX Bit7 (979~1002) 24 990, Bit15 (973~997) 25 985,
1355 16:34:58.889536
1356 16:34:58.889584 Write Rank0 MR14 =0x20
1357 16:34:58.889633
1358 16:34:58.889681 CH=0, VrefRange= 0, VrefLevel = 32
1359 16:34:58.889730 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
1360 16:34:58.889780 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
1361 16:34:58.889829 TX Bit2 (979~1003) 25 991, Bit10 (972~997) 26 984,
1362 16:34:58.889914 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1363 16:34:58.890005 TX Bit4 (979~1002) 24 990, Bit12 (968~991) 24 979,
1364 16:34:58.890085 TX Bit5 (978~999) 22 988, Bit13 (968~991) 24 979,
1365 16:34:58.890166 TX Bit6 (978~1000) 23 989, Bit14 (969~993) 25 981,
1366 16:34:58.890244 TX Bit7 (979~1002) 24 990, Bit15 (973~997) 25 985,
1367 16:34:58.890320
1368 16:34:58.890371 Write Rank0 MR14 =0x22
1369 16:34:58.890423
1370 16:34:58.890472 CH=0, VrefRange= 0, VrefLevel = 34
1371 16:34:58.890523 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
1372 16:34:58.890573 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
1373 16:34:58.890622 TX Bit2 (979~1003) 25 991, Bit10 (972~997) 26 984,
1374 16:34:58.890670 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1375 16:34:58.890719 TX Bit4 (979~1002) 24 990, Bit12 (968~991) 24 979,
1376 16:34:58.890769 TX Bit5 (978~999) 22 988, Bit13 (968~991) 24 979,
1377 16:34:58.891022 TX Bit6 (978~1000) 23 989, Bit14 (969~993) 25 981,
1378 16:34:58.891078 TX Bit7 (979~1002) 24 990, Bit15 (973~997) 25 985,
1379 16:34:58.891128
1380 16:34:58.891176 Write Rank0 MR14 =0x24
1381 16:34:58.891225
1382 16:34:58.891273 CH=0, VrefRange= 0, VrefLevel = 36
1383 16:34:58.891322 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
1384 16:34:58.891371 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
1385 16:34:58.891420 TX Bit2 (979~1003) 25 991, Bit10 (972~997) 26 984,
1386 16:34:58.891468 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1387 16:34:58.891521 TX Bit4 (979~1002) 24 990, Bit12 (968~991) 24 979,
1388 16:34:58.891572 TX Bit5 (978~999) 22 988, Bit13 (968~991) 24 979,
1389 16:34:58.891621 TX Bit6 (978~1000) 23 989, Bit14 (969~993) 25 981,
1390 16:34:58.891670 TX Bit7 (979~1002) 24 990, Bit15 (973~997) 25 985,
1391 16:34:58.891718
1392 16:34:58.891765 Write Rank0 MR14 =0x26
1393 16:34:58.891812
1394 16:34:58.891867 CH=0, VrefRange= 0, VrefLevel = 38
1395 16:34:58.891916 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
1396 16:34:58.891965 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
1397 16:34:58.892019 TX Bit2 (979~1003) 25 991, Bit10 (972~997) 26 984,
1398 16:34:58.892068 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1399 16:34:58.892116 TX Bit4 (979~1002) 24 990, Bit12 (968~991) 24 979,
1400 16:34:58.892166 TX Bit5 (978~999) 22 988, Bit13 (968~991) 24 979,
1401 16:34:58.892214 TX Bit6 (978~1000) 23 989, Bit14 (969~993) 25 981,
1402 16:34:58.892263 TX Bit7 (979~1002) 24 990, Bit15 (973~997) 25 985,
1403 16:34:58.892311
1404 16:34:58.892359
1405 16:34:58.892407 TX Vref found, early break! 351< 363
1406 16:34:58.892461 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
1407 16:34:58.892517 u1DelayCellOfst[0]=8 cells (7 PI)
1408 16:34:58.892568 u1DelayCellOfst[1]=5 cells (5 PI)
1409 16:34:58.892617 u1DelayCellOfst[2]=6 cells (6 PI)
1410 16:34:58.892665 u1DelayCellOfst[3]=0 cells (0 PI)
1411 16:34:58.892712 u1DelayCellOfst[4]=5 cells (5 PI)
1412 16:34:58.892761 u1DelayCellOfst[5]=3 cells (3 PI)
1413 16:34:58.892809 u1DelayCellOfst[6]=4 cells (4 PI)
1414 16:34:58.892858 u1DelayCellOfst[7]=5 cells (5 PI)
1415 16:34:58.892906 Byte0, DQ PI dly=985, DQM PI dly= 988
1416 16:34:58.892954 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1417 16:34:58.893006
1418 16:34:58.893054 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1419 16:34:58.893103
1420 16:34:58.893151 u1DelayCellOfst[8]=0 cells (0 PI)
1421 16:34:58.893198 u1DelayCellOfst[9]=1 cells (1 PI)
1422 16:34:58.893246 u1DelayCellOfst[10]=6 cells (6 PI)
1423 16:34:58.893295 u1DelayCellOfst[11]=0 cells (0 PI)
1424 16:34:58.893343 u1DelayCellOfst[12]=1 cells (1 PI)
1425 16:34:58.893391 u1DelayCellOfst[13]=1 cells (1 PI)
1426 16:34:58.893455 u1DelayCellOfst[14]=3 cells (3 PI)
1427 16:34:58.893535 u1DelayCellOfst[15]=8 cells (7 PI)
1428 16:34:58.893624 Byte1, DQ PI dly=978, DQM PI dly= 981
1429 16:34:58.893703 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1430 16:34:58.893787
1431 16:34:58.893867 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1432 16:34:58.893945
1433 16:34:58.894024 Write Rank0 MR14 =0x1e
1434 16:34:58.894078
1435 16:34:58.894127 Final TX Range 0 Vref 30
1436 16:34:58.894177
1437 16:34:58.894227 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1438 16:34:58.894285
1439 16:34:58.894343 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1440 16:34:58.894393 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1441 16:34:58.894443 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1442 16:34:58.894493 Write Rank0 MR3 =0xb0
1443 16:34:58.894549 DramC Write-DBI on
1444 16:34:58.894599 ==
1445 16:34:58.894648 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1446 16:34:58.894697 fsp= 1, odt_onoff= 1, Byte mode= 0
1447 16:34:58.894754 ==
1448 16:34:58.894804 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1449 16:34:58.894852
1450 16:34:58.894901 Begin, DQ Scan Range 701~765
1451 16:34:58.894952
1452 16:34:58.895000
1453 16:34:58.895048 TX Vref Scan disable
1454 16:34:58.895096 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1455 16:34:58.895148 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1456 16:34:58.895198 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1457 16:34:58.895248 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1458 16:34:58.895304 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1459 16:34:58.895356 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1460 16:34:58.895406 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1461 16:34:58.895454 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1462 16:34:58.895503 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1463 16:34:58.895552 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1464 16:34:58.895604 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1465 16:34:58.895654 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1466 16:34:58.895703 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1467 16:34:58.895752 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1468 16:34:58.895801 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1469 16:34:58.895856 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1470 16:34:58.895907 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1471 16:34:58.895957 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1472 16:34:58.896007 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1473 16:34:58.896056 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1474 16:34:58.896106 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
1475 16:34:58.896159 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
1476 16:34:58.896208 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1477 16:34:58.896257 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1478 16:34:58.896305 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1479 16:34:58.896357 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1480 16:34:58.896406 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1481 16:34:58.896455 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1482 16:34:58.896511 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1483 16:34:58.896561 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1484 16:34:58.896610 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1485 16:34:58.896660 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1486 16:34:58.896712 747 |2 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
1487 16:34:58.896761 Byte0, DQ PI dly=734, DQM PI dly= 734
1488 16:34:58.896810 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
1489 16:34:58.896859
1490 16:34:58.897106 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
1491 16:34:58.897173
1492 16:34:58.897276 Byte1, DQ PI dly=724, DQM PI dly= 724
1493 16:34:58.897374 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
1494 16:34:58.897469
1495 16:34:58.897566 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
1496 16:34:58.897663
1497 16:34:58.897763 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1498 16:34:58.897851 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1499 16:34:58.897959 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1500 16:34:58.898089 Write Rank0 MR3 =0x30
1501 16:34:58.898168 DramC Write-DBI off
1502 16:34:58.898245
1503 16:34:58.898340 [DATLAT]
1504 16:34:58.898418 Freq=1600, CH0 RK0, use_rxtx_scan=0
1505 16:34:58.898510
1506 16:34:58.898588 DATLAT Default: 0xf
1507 16:34:58.898675 7, 0xFFFF, sum=0
1508 16:34:58.898755 8, 0xFFFF, sum=0
1509 16:34:58.898834 9, 0xFFFF, sum=0
1510 16:34:58.898934 10, 0xFFFF, sum=0
1511 16:34:58.899014 11, 0xFFFF, sum=0
1512 16:34:58.899103 12, 0xFFFF, sum=0
1513 16:34:58.899183 13, 0xFFFF, sum=0
1514 16:34:58.899287 14, 0x0, sum=1
1515 16:34:58.899367 15, 0x0, sum=2
1516 16:34:58.899447 16, 0x0, sum=3
1517 16:34:58.899526 17, 0x0, sum=4
1518 16:34:58.899605 pattern=2 first_step=14 total pass=5 best_step=16
1519 16:34:58.899682 ==
1520 16:34:58.899763 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1521 16:34:58.899841 fsp= 1, odt_onoff= 1, Byte mode= 0
1522 16:34:58.899919 ==
1523 16:34:58.899997 Start DQ dly to find pass range UseTestEngine =1
1524 16:34:58.900079 x-axis: bit #, y-axis: DQ dly (-127~63)
1525 16:34:58.900156 RX Vref Scan = 1
1526 16:34:58.900234
1527 16:34:58.900326 RX Vref found, early break!
1528 16:34:58.900416
1529 16:34:58.900494 Final RX Vref 12, apply to both rank0 and 1
1530 16:34:58.900574 ==
1531 16:34:58.900651 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1532 16:34:58.900729 fsp= 1, odt_onoff= 1, Byte mode= 0
1533 16:34:58.900808 ==
1534 16:34:58.900885 DQS Delay:
1535 16:34:58.900963 DQS0 = 0, DQS1 = 0
1536 16:34:58.901040 DQM Delay:
1537 16:34:58.901119 DQM0 = 21, DQM1 = 20
1538 16:34:58.901196 DQ Delay:
1539 16:34:58.901274 DQ0 =23, DQ1 =23, DQ2 =24, DQ3 =17
1540 16:34:58.901353 DQ4 =23, DQ5 =19, DQ6 =20, DQ7 =23
1541 16:34:58.901430 DQ8 =17, DQ9 =18, DQ10 =25, DQ11 =18
1542 16:34:58.901511 DQ12 =20, DQ13 =19, DQ14 =21, DQ15 =23
1543 16:34:58.901588
1544 16:34:58.901664
1545 16:34:58.901739
1546 16:34:58.901815 [DramC_TX_OE_Calibration] TA2
1547 16:34:58.901919 Original DQ_B0 (3 6) =30, OEN = 27
1548 16:34:58.902013 Original DQ_B1 (3 6) =30, OEN = 27
1549 16:34:58.902091 23, 0x0, End_B0=23 End_B1=23
1550 16:34:58.902146 24, 0x0, End_B0=24 End_B1=24
1551 16:34:58.902197 25, 0x0, End_B0=25 End_B1=25
1552 16:34:58.902247 26, 0x0, End_B0=26 End_B1=26
1553 16:34:58.902296 27, 0x0, End_B0=27 End_B1=27
1554 16:34:58.902347 28, 0x0, End_B0=28 End_B1=28
1555 16:34:58.902396 29, 0x0, End_B0=29 End_B1=29
1556 16:34:58.902447 30, 0x0, End_B0=30 End_B1=30
1557 16:34:58.902497 31, 0xFFFF, End_B0=30 End_B1=30
1558 16:34:58.902550 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1559 16:34:58.902601 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1560 16:34:58.902650
1561 16:34:58.902698
1562 16:34:58.902746 Write Rank0 MR23 =0x3f
1563 16:34:58.902794 [DQSOSC]
1564 16:34:58.902842 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbcb, (MSB)MR19= 0x202, tDQSOscB0 = 440 ps tDQSOscB1 = 440 ps
1565 16:34:58.902894 CH0_RK0: MR19=0x202, MR18=0xCBCB, DQSOSC=440, MR23=63, INC=12, DEC=19
1566 16:34:58.902944 Write Rank0 MR23 =0x3f
1567 16:34:58.902992 [DQSOSC]
1568 16:34:58.903044 [DQSOSCAuto] RK0, (LSB)MR18= 0xcece, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
1569 16:34:58.903095 CH0 RK0: MR19=202, MR18=CECE
1570 16:34:58.903144 [RankSwap] Rank num 2, (Multi 1), Rank 1
1571 16:34:58.903192 Write Rank0 MR2 =0xad
1572 16:34:58.903240 [Write Leveling]
1573 16:34:58.903287 delay byte0 byte1 byte2 byte3
1574 16:34:58.903334
1575 16:34:58.903390 10 0 0
1576 16:34:58.903446 11 0 0
1577 16:34:58.903500 12 0 0
1578 16:34:58.903549 13 0 0
1579 16:34:58.903597 14 0 0
1580 16:34:58.903645 15 0 0
1581 16:34:58.903696 16 0 0
1582 16:34:58.903745 17 0 0
1583 16:34:58.903794 18 0 0
1584 16:34:58.903842 19 0 0
1585 16:34:58.903892 20 0 0
1586 16:34:58.903941 21 0 0
1587 16:34:58.903989 22 0 0
1588 16:34:58.904037 23 0 ff
1589 16:34:58.904088 24 0 ff
1590 16:34:58.904137 25 0 ff
1591 16:34:58.904186 26 0 ff
1592 16:34:58.904235 27 0 ff
1593 16:34:58.904284 28 0 ff
1594 16:34:58.904332 29 0 ff
1595 16:34:58.904381 30 0 ff
1596 16:34:58.904429 31 0 ff
1597 16:34:58.904496 32 ff ff
1598 16:34:58.904546 33 ff ff
1599 16:34:58.904596 34 ff ff
1600 16:34:58.904649 35 ff ff
1601 16:34:58.904699 36 ff ff
1602 16:34:58.904749 37 ff ff
1603 16:34:58.904798 38 ff ff
1604 16:34:58.904847 pass bytecount = 0xff (0xff: all bytes pass)
1605 16:34:58.904896
1606 16:34:58.904944 DQS0 dly: 32
1607 16:34:58.904993 DQS1 dly: 23
1608 16:34:58.905040 Write Rank0 MR2 =0x2d
1609 16:34:58.905088 [RankSwap] Rank num 2, (Multi 1), Rank 0
1610 16:34:58.905136 Write Rank1 MR1 =0xd6
1611 16:34:58.905184 [Gating]
1612 16:34:58.905238 ==
1613 16:34:58.905286 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1614 16:34:58.905334 fsp= 1, odt_onoff= 1, Byte mode= 0
1615 16:34:58.905382 ==
1616 16:34:58.905430 3 1 0 |3534 3636 |(11 11)(0 0) |(0 0)(0 0)| 0
1617 16:34:58.905481 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1618 16:34:58.905531 3 1 8 |3534 3635 |(11 11)(11 11) |(0 0)(1 1)| 0
1619 16:34:58.905580 3 1 12 |3534 1c1c |(11 11)(11 11) |(1 1)(0 0)| 0
1620 16:34:58.905629 3 1 16 |3534 3736 |(11 11)(11 11) |(1 1)(1 1)| 0
1621 16:34:58.905678 3 1 20 |3534 3535 |(11 11)(11 11) |(0 0)(1 1)| 0
1622 16:34:58.905727 3 1 24 |3534 3535 |(11 11)(11 11) |(0 0)(0 0)| 0
1623 16:34:58.905779 3 1 28 |3534 3333 |(11 11)(1 1) |(0 0)(0 0)| 0
1624 16:34:58.905830 3 2 0 |3534 3434 |(11 11)(11 11) |(0 0)(0 0)| 0
1625 16:34:58.905880 3 2 4 |3534 3434 |(11 11)(11 11) |(0 0)(0 0)| 0
1626 16:34:58.905929 3 2 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1627 16:34:58.905979 3 2 12 |3534 3535 |(11 11)(10 10) |(0 1)(0 1)| 0
1628 16:34:58.906042 3 2 16 |3534 3231 |(11 11)(11 11) |(1 1)(0 1)| 0
1629 16:34:58.906091 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1630 16:34:58.906141 3 2 24 |3d3d 3c3c |(11 11)(11 11) |(1 1)(0 0)| 0
1631 16:34:58.906191 3 2 28 |3d3d 2b2a |(11 11)(11 11) |(1 1)(1 1)| 0
1632 16:34:58.906240 [Byte 1] Lead/lag Transition tap number (1)
1633 16:34:58.906290 3 3 0 |3d3d 2726 |(11 11)(11 11) |(1 1)(0 0)| 0
1634 16:34:58.906343 3 3 4 |3d3d 1716 |(11 11)(11 11) |(1 1)(1 1)| 0
1635 16:34:58.906608 3 3 8 |3d3d 1b1a |(11 11)(1 1) |(1 1)(1 1)| 0
1636 16:34:58.906721 3 3 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1637 16:34:58.906788 3 3 16 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
1638 16:34:58.906855 3 3 20 |201 1d1c |(11 11)(11 11) |(1 1)(1 1)| 0
1639 16:34:58.906958 3 3 24 |3534 e0d |(11 11)(11 11) |(1 1)(1 1)| 0
1640 16:34:58.907039 [Byte 0] Lead/lag Transition tap number (1)
1641 16:34:58.907110 [Byte 1] Lead/lag Transition tap number (1)
1642 16:34:58.907202 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1643 16:34:58.907296 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1644 16:34:58.907393 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1645 16:34:58.907488 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1646 16:34:58.907582 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
1647 16:34:58.907679 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1648 16:34:58.907773 3 4 20 |8887 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1649 16:34:58.907870 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1650 16:34:58.907975 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1651 16:34:58.908070 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1652 16:34:58.908167 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1653 16:34:58.908260 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1654 16:34:58.908340 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1655 16:34:58.908420 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1656 16:34:58.908502 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1657 16:34:58.908600 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1658 16:34:58.908682 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1659 16:34:58.908761 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1660 16:34:58.908858 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1661 16:34:58.908941 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1662 16:34:58.909035 [Byte 0] Lead/lag falling Transition (3, 6, 8)
1663 16:34:58.909115 [Byte 1] Lead/lag falling Transition (3, 6, 8)
1664 16:34:58.909192 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1665 16:34:58.909301 [Byte 0] Lead/lag Transition tap number (2)
1666 16:34:58.909380 [Byte 1] Lead/lag Transition tap number (2)
1667 16:34:58.909458 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
1668 16:34:58.909549 3 6 20 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1669 16:34:58.909629 [Byte 0]First pass (3, 6, 20)
1670 16:34:58.909710 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1671 16:34:58.909790 [Byte 1]First pass (3, 6, 24)
1672 16:34:58.909868 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1673 16:34:58.909948 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1674 16:34:58.910042 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1675 16:34:58.910126 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1676 16:34:58.910215 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1677 16:34:58.910298 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1678 16:34:58.910388 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1679 16:34:58.910468 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1680 16:34:58.910559 All bytes gating window > 1UI, Early break!
1681 16:34:58.910639
1682 16:34:58.910715 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
1683 16:34:58.910794
1684 16:34:58.910872 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12)
1685 16:34:58.910947
1686 16:34:58.911022
1687 16:34:58.911097
1688 16:34:58.911176 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
1689 16:34:58.911253
1690 16:34:58.911329 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
1691 16:34:58.911405
1692 16:34:58.911480
1693 16:34:58.911556 Write Rank1 MR1 =0x56
1694 16:34:58.911632
1695 16:34:58.911711 best RODT dly(2T, 0.5T) = (2, 3)
1696 16:34:58.911788
1697 16:34:58.911864 best RODT dly(2T, 0.5T) = (2, 3)
1698 16:34:58.911939 ==
1699 16:34:58.912016 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1700 16:34:58.912093 fsp= 1, odt_onoff= 1, Byte mode= 0
1701 16:34:58.912169 ==
1702 16:34:58.912249 Start DQ dly to find pass range UseTestEngine =0
1703 16:34:58.912327 x-axis: bit #, y-axis: DQ dly (-127~63)
1704 16:34:58.912403 RX Vref Scan = 0
1705 16:34:58.912480 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1706 16:34:58.912559 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1707 16:34:58.912637 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1708 16:34:58.912716 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1709 16:34:58.912797 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1710 16:34:58.912876 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1711 16:34:58.912955 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1712 16:34:58.913035 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1713 16:34:58.913114 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1714 16:34:58.913193 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1715 16:34:58.913271 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1716 16:34:58.913352 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1717 16:34:58.913431 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1718 16:34:58.913511 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1719 16:34:58.913590 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1720 16:34:58.913669 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1721 16:34:58.913747 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1722 16:34:58.913826 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1723 16:34:58.913907 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1724 16:34:58.913993 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1725 16:34:58.914074 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1726 16:34:58.914152 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1727 16:34:58.914230 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1728 16:34:58.914309 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1729 16:34:58.914387 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1730 16:34:58.914469 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1731 16:34:58.914548 0, [0] xxxxxxxx xxxxxxxx [MSB]
1732 16:34:58.914627 1, [0] xxxoxxxx oxxxxxxx [MSB]
1733 16:34:58.914705 2, [0] xxxoxxxx oxxxxxxx [MSB]
1734 16:34:58.914784 3, [0] xxxoxoxx oxxoxxxx [MSB]
1735 16:34:58.914862 4, [0] xxxoxoox ooxoxxxx [MSB]
1736 16:34:58.914941 5, [0] xxxoxoox ooxoxxxx [MSB]
1737 16:34:58.915023 6, [0] xxxoxooo ooxooxxx [MSB]
1738 16:34:58.915101 7, [0] xoxooooo ooxoooox [MSB]
1739 16:34:58.915180 8, [0] ooxooooo ooxoooox [MSB]
1740 16:34:58.915258 9, [0] oooooooo ooxooooo [MSB]
1741 16:34:58.915337 10, [0] oooooooo ooxooooo [MSB]
1742 16:34:58.915415 32, [0] oooooooo oooooooo [MSB]
1743 16:34:58.915494 33, [0] oooxoooo xooooooo [MSB]
1744 16:34:58.915575 34, [0] oooxoooo xooooooo [MSB]
1745 16:34:58.915654 35, [0] oooxoooo xooxoooo [MSB]
1746 16:34:58.915940 36, [0] oooxooxo xxoxxooo [MSB]
1747 16:34:58.916002 37, [0] oooxoxxo xxoxxxoo [MSB]
1748 16:34:58.916057 38, [0] oooxoxxo xxoxxxxo [MSB]
1749 16:34:58.916107 39, [0] oooxoxxx xxoxxxxo [MSB]
1750 16:34:58.916158 40, [0] oxoxxxxx xxoxxxxo [MSB]
1751 16:34:58.916208 41, [0] xxxxxxxx xxoxxxxx [MSB]
1752 16:34:58.916257 42, [0] xxxxxxxx xxoxxxxx [MSB]
1753 16:34:58.916307 43, [0] xxxxxxxx xxxxxxxx [MSB]
1754 16:34:58.916356 iDelay=43, Bit 0, Center 24 (8 ~ 40) 33
1755 16:34:58.916405 iDelay=43, Bit 1, Center 23 (7 ~ 39) 33
1756 16:34:58.916454 iDelay=43, Bit 2, Center 24 (9 ~ 40) 32
1757 16:34:58.916502 iDelay=43, Bit 3, Center 16 (1 ~ 32) 32
1758 16:34:58.916550 iDelay=43, Bit 4, Center 23 (7 ~ 39) 33
1759 16:34:58.916601 iDelay=43, Bit 5, Center 19 (3 ~ 36) 34
1760 16:34:58.916650 iDelay=43, Bit 6, Center 19 (4 ~ 35) 32
1761 16:34:58.916699 iDelay=43, Bit 7, Center 22 (6 ~ 38) 33
1762 16:34:58.916747 iDelay=43, Bit 8, Center 16 (1 ~ 32) 32
1763 16:34:58.916796 iDelay=43, Bit 9, Center 19 (4 ~ 35) 32
1764 16:34:58.916845 iDelay=43, Bit 10, Center 26 (11 ~ 42) 32
1765 16:34:58.916893 iDelay=43, Bit 11, Center 18 (3 ~ 34) 32
1766 16:34:58.916941 iDelay=43, Bit 12, Center 20 (6 ~ 35) 30
1767 16:34:58.916989 iDelay=43, Bit 13, Center 21 (7 ~ 36) 30
1768 16:34:58.917037 iDelay=43, Bit 14, Center 22 (7 ~ 37) 31
1769 16:34:58.917085 iDelay=43, Bit 15, Center 24 (9 ~ 40) 32
1770 16:34:58.917132 ==
1771 16:34:58.917184 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1772 16:34:58.917234 fsp= 1, odt_onoff= 1, Byte mode= 0
1773 16:34:58.917288 ==
1774 16:34:58.917347 DQS Delay:
1775 16:34:58.917397 DQS0 = 0, DQS1 = 0
1776 16:34:58.917445 DQM Delay:
1777 16:34:58.917493 DQM0 = 21, DQM1 = 20
1778 16:34:58.917541 DQ Delay:
1779 16:34:58.917589 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =16
1780 16:34:58.917638 DQ4 =23, DQ5 =19, DQ6 =19, DQ7 =22
1781 16:34:58.917713 DQ8 =16, DQ9 =19, DQ10 =26, DQ11 =18
1782 16:34:58.917764 DQ12 =20, DQ13 =21, DQ14 =22, DQ15 =24
1783 16:34:58.917812
1784 16:34:58.917861
1785 16:34:58.917909 DramC Write-DBI off
1786 16:34:58.917957 ==
1787 16:34:58.918019 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1788 16:34:58.918088 fsp= 1, odt_onoff= 1, Byte mode= 0
1789 16:34:58.918140 ==
1790 16:34:58.918205 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1791 16:34:58.918269
1792 16:34:58.918333 Begin, DQ Scan Range 919~1175
1793 16:34:58.918384
1794 16:34:58.918432
1795 16:34:58.918481 TX Vref Scan disable
1796 16:34:58.918557 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1797 16:34:58.918608 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1798 16:34:58.918658 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1799 16:34:58.918708 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1800 16:34:58.918778 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1801 16:34:58.918829 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1802 16:34:58.918879 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1803 16:34:58.918933 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1804 16:34:58.918983 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1805 16:34:58.919033 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1806 16:34:58.919083 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1807 16:34:58.919134 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1808 16:34:58.919184 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1809 16:34:58.919233 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1810 16:34:58.919286 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1811 16:34:58.919336 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1812 16:34:58.919386 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1813 16:34:58.919435 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1814 16:34:58.919484 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1815 16:34:58.919534 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1816 16:34:58.919583 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1817 16:34:58.919632 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1818 16:34:58.919680 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1819 16:34:58.919729 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1820 16:34:58.919781 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1821 16:34:58.919830 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1822 16:34:58.919879 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1823 16:34:58.919929 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1824 16:34:58.919978 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1825 16:34:58.920044 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1826 16:34:58.920115 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1827 16:34:58.920167 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1828 16:34:58.920215 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1829 16:34:58.920277 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1830 16:34:58.920326 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1831 16:34:58.920375 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1832 16:34:58.920424 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1833 16:34:58.920492 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1834 16:34:58.920541 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1835 16:34:58.920590 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1836 16:34:58.920639 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1837 16:34:58.920699 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1838 16:34:58.920749 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1839 16:34:58.920798 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1840 16:34:58.920848 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1841 16:34:58.920926 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1842 16:34:58.921000 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1843 16:34:58.921053 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1844 16:34:58.921103 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1845 16:34:58.921153 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1846 16:34:58.921203 969 |3 6 9|[0] xxxxxxxx ooxoxxxx [MSB]
1847 16:34:58.921279 970 |3 6 10|[0] xxxxxxxx ooxoooxx [MSB]
1848 16:34:58.921332 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1849 16:34:58.921382 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1850 16:34:58.921431 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1851 16:34:58.921509 974 |3 6 14|[0] xxxxxxxx ooooooox [MSB]
1852 16:34:58.921596 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1853 16:34:58.921712 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1854 16:34:58.921809 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1855 16:34:58.921923 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1856 16:34:58.922032 979 |3 6 19|[0] xxxoxoox oooooooo [MSB]
1857 16:34:58.922088 980 |3 6 20|[0] xoxooooo oooooooo [MSB]
1858 16:34:58.922148 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1859 16:34:58.922240 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1860 16:34:58.922537 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1861 16:34:58.922638 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1862 16:34:58.922720 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1863 16:34:58.922800 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1864 16:34:58.922880 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1865 16:34:58.922961 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1866 16:34:58.923041 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1867 16:34:58.923124 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1868 16:34:58.923204 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1869 16:34:58.923286 998 |3 6 38|[0] oooxoxxo xxxxxxxx [MSB]
1870 16:34:58.923365 999 |3 6 39|[0] xxxxoxxx xxxxxxxx [MSB]
1871 16:34:58.923445 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1872 16:34:58.923524 Byte0, DQ PI dly=987, DQM PI dly= 987
1873 16:34:58.923602 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1874 16:34:58.923682
1875 16:34:58.923759 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1876 16:34:58.923836
1877 16:34:58.923913 Byte1, DQ PI dly=979, DQM PI dly= 979
1878 16:34:58.923990 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1879 16:34:58.924067
1880 16:34:58.924144 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1881 16:34:58.924224
1882 16:34:58.924300 ==
1883 16:34:58.924377 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1884 16:34:58.924454 fsp= 1, odt_onoff= 1, Byte mode= 0
1885 16:34:58.924531 ==
1886 16:34:58.924608 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1887 16:34:58.924685
1888 16:34:58.924764 Begin, DQ Scan Range 955~1019
1889 16:34:58.924840 Write Rank1 MR14 =0x0
1890 16:34:58.924916
1891 16:34:58.924993 CH=0, VrefRange= 0, VrefLevel = 0
1892 16:34:58.925070 TX Bit0 (984~996) 13 990, Bit8 (970~982) 13 976,
1893 16:34:58.925148 TX Bit1 (983~994) 12 988, Bit9 (971~985) 15 978,
1894 16:34:58.925226 TX Bit2 (984~995) 12 989, Bit10 (977~990) 14 983,
1895 16:34:58.925307 TX Bit3 (979~987) 9 983, Bit11 (971~982) 12 976,
1896 16:34:58.925385 TX Bit4 (982~995) 14 988, Bit12 (973~984) 12 978,
1897 16:34:58.925462 TX Bit5 (980~992) 13 986, Bit13 (973~984) 12 978,
1898 16:34:58.925540 TX Bit6 (980~993) 14 986, Bit14 (974~985) 12 979,
1899 16:34:58.925617 TX Bit7 (983~993) 11 988, Bit15 (977~989) 13 983,
1900 16:34:58.925693
1901 16:34:58.925769 Write Rank1 MR14 =0x2
1902 16:34:58.925848
1903 16:34:58.925924 CH=0, VrefRange= 0, VrefLevel = 2
1904 16:34:58.926013 TX Bit0 (984~997) 14 990, Bit8 (969~983) 15 976,
1905 16:34:58.926093 TX Bit1 (982~995) 14 988, Bit9 (971~985) 15 978,
1906 16:34:58.926170 TX Bit2 (984~995) 12 989, Bit10 (976~990) 15 983,
1907 16:34:58.926248 TX Bit3 (978~987) 10 982, Bit11 (970~982) 13 976,
1908 16:34:58.926329 TX Bit4 (981~995) 15 988, Bit12 (974~985) 12 979,
1909 16:34:58.926426 TX Bit5 (980~992) 13 986, Bit13 (973~985) 13 979,
1910 16:34:58.926507 TX Bit6 (980~993) 14 986, Bit14 (973~986) 14 979,
1911 16:34:58.926587 TX Bit7 (982~993) 12 987, Bit15 (976~990) 15 983,
1912 16:34:58.926662
1913 16:34:58.926739 Write Rank1 MR14 =0x4
1914 16:34:58.926828
1915 16:34:58.926906 CH=0, VrefRange= 0, VrefLevel = 4
1916 16:34:58.926984 TX Bit0 (983~998) 16 990, Bit8 (969~983) 15 976,
1917 16:34:58.927082 TX Bit1 (982~995) 14 988, Bit9 (970~986) 17 978,
1918 16:34:58.927161 TX Bit2 (982~997) 16 989, Bit10 (976~991) 16 983,
1919 16:34:58.927239 TX Bit3 (978~989) 12 983, Bit11 (970~983) 14 976,
1920 16:34:58.927316 TX Bit4 (981~996) 16 988, Bit12 (972~985) 14 978,
1921 16:34:58.927394 TX Bit5 (979~993) 15 986, Bit13 (973~985) 13 979,
1922 16:34:58.927475 TX Bit6 (979~994) 16 986, Bit14 (974~988) 15 981,
1923 16:34:58.927552 TX Bit7 (983~994) 12 988, Bit15 (976~990) 15 983,
1924 16:34:58.927641
1925 16:34:58.927720 Write Rank1 MR14 =0x6
1926 16:34:58.927795
1927 16:34:58.927902 CH=0, VrefRange= 0, VrefLevel = 6
1928 16:34:58.927982 TX Bit0 (983~998) 16 990, Bit8 (969~983) 15 976,
1929 16:34:58.928060 TX Bit1 (981~996) 16 988, Bit9 (970~987) 18 978,
1930 16:34:58.928172 TX Bit2 (982~997) 16 989, Bit10 (976~991) 16 983,
1931 16:34:58.928251 TX Bit3 (978~991) 14 984, Bit11 (969~983) 15 976,
1932 16:34:58.928345 TX Bit4 (981~996) 16 988, Bit12 (971~986) 16 978,
1933 16:34:58.928424 TX Bit5 (979~993) 15 986, Bit13 (972~986) 15 979,
1934 16:34:58.928516 TX Bit6 (979~994) 16 986, Bit14 (973~989) 17 981,
1935 16:34:58.928595 TX Bit7 (982~994) 13 988, Bit15 (976~990) 15 983,
1936 16:34:58.928679
1937 16:34:58.928756 Write Rank1 MR14 =0x8
1938 16:34:58.928831
1939 16:34:58.928909 CH=0, VrefRange= 0, VrefLevel = 8
1940 16:34:58.928986 TX Bit0 (983~999) 17 991, Bit8 (968~984) 17 976,
1941 16:34:58.929066 TX Bit1 (981~997) 17 989, Bit9 (969~987) 19 978,
1942 16:34:58.929147 TX Bit2 (982~998) 17 990, Bit10 (975~991) 17 983,
1943 16:34:58.929234 TX Bit3 (978~991) 14 984, Bit11 (969~983) 15 976,
1944 16:34:58.929312 TX Bit4 (980~997) 18 988, Bit12 (972~986) 15 979,
1945 16:34:58.929390 TX Bit5 (979~994) 16 986, Bit13 (972~987) 16 979,
1946 16:34:58.929469 TX Bit6 (979~995) 17 987, Bit14 (972~989) 18 980,
1947 16:34:58.929547 TX Bit7 (981~995) 15 988, Bit15 (976~991) 16 983,
1948 16:34:58.929623
1949 16:34:58.929702 Write Rank1 MR14 =0xa
1950 16:34:58.929778
1951 16:34:58.929854 CH=0, VrefRange= 0, VrefLevel = 10
1952 16:34:58.929931 TX Bit0 (983~1000) 18 991, Bit8 (968~984) 17 976,
1953 16:34:58.930018 TX Bit1 (980~997) 18 988, Bit9 (969~988) 20 978,
1954 16:34:58.930096 TX Bit2 (982~999) 18 990, Bit10 (975~992) 18 983,
1955 16:34:58.930174 TX Bit3 (978~992) 15 985, Bit11 (969~984) 16 976,
1956 16:34:58.930256 TX Bit4 (980~998) 19 989, Bit12 (971~986) 16 978,
1957 16:34:58.930336 TX Bit5 (979~994) 16 986, Bit13 (971~986) 16 978,
1958 16:34:58.930412 TX Bit6 (979~996) 18 987, Bit14 (972~990) 19 981,
1959 16:34:58.930464 TX Bit7 (981~996) 16 988, Bit15 (975~991) 17 983,
1960 16:34:58.930513
1961 16:34:58.930561 Write Rank1 MR14 =0xc
1962 16:34:58.930609
1963 16:34:58.930657 CH=0, VrefRange= 0, VrefLevel = 12
1964 16:34:58.930706 TX Bit0 (982~1001) 20 991, Bit8 (968~985) 18 976,
1965 16:34:58.930757 TX Bit1 (981~998) 18 989, Bit9 (970~988) 19 979,
1966 16:34:58.930806 TX Bit2 (982~999) 18 990, Bit10 (975~992) 18 983,
1967 16:34:58.931055 TX Bit3 (978~992) 15 985, Bit11 (968~984) 17 976,
1968 16:34:58.931113 TX Bit4 (980~998) 19 989, Bit12 (970~987) 18 978,
1969 16:34:58.931163 TX Bit5 (979~994) 16 986, Bit13 (971~988) 18 979,
1970 16:34:58.931212 TX Bit6 (979~996) 18 987, Bit14 (971~990) 20 980,
1971 16:34:58.931261 TX Bit7 (980~996) 17 988, Bit15 (974~992) 19 983,
1972 16:34:58.931313
1973 16:34:58.931363 Write Rank1 MR14 =0xe
1974 16:34:58.931412
1975 16:34:58.931460 CH=0, VrefRange= 0, VrefLevel = 14
1976 16:34:58.931510 TX Bit0 (982~1001) 20 991, Bit8 (968~985) 18 976,
1977 16:34:59.186207 TX Bit1 (980~999) 20 989, Bit9 (969~989) 21 979,
1978 16:34:59.186327 TX Bit2 (981~1000) 20 990, Bit10 (975~993) 19 984,
1979 16:34:59.186390 TX Bit3 (977~992) 16 984, Bit11 (968~985) 18 976,
1980 16:34:59.186447 TX Bit4 (980~999) 20 989, Bit12 (970~989) 20 979,
1981 16:34:59.186503 TX Bit5 (979~995) 17 987, Bit13 (971~989) 19 980,
1982 16:34:59.186556 TX Bit6 (979~997) 19 988, Bit14 (971~991) 21 981,
1983 16:34:59.186608 TX Bit7 (980~997) 18 988, Bit15 (975~992) 18 983,
1984 16:34:59.186658
1985 16:34:59.186708 Write Rank1 MR14 =0x10
1986 16:34:59.186757
1987 16:34:59.186811 CH=0, VrefRange= 0, VrefLevel = 16
1988 16:34:59.186875 TX Bit0 (982~1002) 21 992, Bit8 (967~986) 20 976,
1989 16:34:59.186926 TX Bit1 (980~1000) 21 990, Bit9 (968~989) 22 978,
1990 16:34:59.186975 TX Bit2 (980~1000) 21 990, Bit10 (974~993) 20 983,
1991 16:34:59.187026 TX Bit3 (977~993) 17 985, Bit11 (968~986) 19 977,
1992 16:34:59.187075 TX Bit4 (980~1000) 21 990, Bit12 (970~989) 20 979,
1993 16:34:59.187125 TX Bit5 (978~995) 18 986, Bit13 (970~989) 20 979,
1994 16:34:59.187174 TX Bit6 (979~997) 19 988, Bit14 (970~991) 22 980,
1995 16:34:59.187223 TX Bit7 (980~998) 19 989, Bit15 (974~993) 20 983,
1996 16:34:59.187272
1997 16:34:59.187326 Write Rank1 MR14 =0x12
1998 16:34:59.187386
1999 16:34:59.187446 CH=0, VrefRange= 0, VrefLevel = 18
2000 16:34:59.187497 TX Bit0 (981~1002) 22 991, Bit8 (967~986) 20 976,
2001 16:34:59.187547 TX Bit1 (980~1000) 21 990, Bit9 (969~989) 21 979,
2002 16:34:59.187616 TX Bit2 (980~1001) 22 990, Bit10 (974~994) 21 984,
2003 16:34:59.187709 TX Bit3 (977~993) 17 985, Bit11 (968~986) 19 977,
2004 16:34:59.187825 TX Bit4 (979~1000) 22 989, Bit12 (969~989) 21 979,
2005 16:34:59.187877 TX Bit5 (979~996) 18 987, Bit13 (970~989) 20 979,
2006 16:34:59.187927 TX Bit6 (979~998) 20 988, Bit14 (970~991) 22 980,
2007 16:34:59.187977 TX Bit7 (980~998) 19 989, Bit15 (974~993) 20 983,
2008 16:34:59.188025
2009 16:34:59.188100 Write Rank1 MR14 =0x14
2010 16:34:59.188152
2011 16:34:59.188245 CH=0, VrefRange= 0, VrefLevel = 20
2012 16:34:59.188302 TX Bit0 (981~1003) 23 992, Bit8 (967~987) 21 977,
2013 16:34:59.188353 TX Bit1 (980~1001) 22 990, Bit9 (968~990) 23 979,
2014 16:34:59.188403 TX Bit2 (981~1001) 21 991, Bit10 (974~995) 22 984,
2015 16:34:59.188452 TX Bit3 (977~994) 18 985, Bit11 (967~987) 21 977,
2016 16:34:59.188501 TX Bit4 (979~1001) 23 990, Bit12 (969~990) 22 979,
2017 16:34:59.188552 TX Bit5 (978~996) 19 987, Bit13 (969~990) 22 979,
2018 16:34:59.188635 TX Bit6 (979~999) 21 989, Bit14 (970~992) 23 981,
2019 16:34:59.188687 TX Bit7 (980~999) 20 989, Bit15 (974~994) 21 984,
2020 16:34:59.188736
2021 16:34:59.188784 Write Rank1 MR14 =0x16
2022 16:34:59.188837
2023 16:34:59.188885 CH=0, VrefRange= 0, VrefLevel = 22
2024 16:34:59.188934 TX Bit0 (980~1003) 24 991, Bit8 (967~988) 22 977,
2025 16:34:59.188984 TX Bit1 (979~1001) 23 990, Bit9 (968~990) 23 979,
2026 16:34:59.189033 TX Bit2 (980~1002) 23 991, Bit10 (973~996) 24 984,
2027 16:34:59.189082 TX Bit3 (977~994) 18 985, Bit11 (967~988) 22 977,
2028 16:34:59.189134 TX Bit4 (979~1001) 23 990, Bit12 (969~990) 22 979,
2029 16:34:59.189185 TX Bit5 (978~997) 20 987, Bit13 (969~990) 22 979,
2030 16:34:59.189235 TX Bit6 (978~999) 22 988, Bit14 (969~992) 24 980,
2031 16:34:59.189288 TX Bit7 (980~1000) 21 990, Bit15 (974~995) 22 984,
2032 16:34:59.189340
2033 16:34:59.189390 Write Rank1 MR14 =0x18
2034 16:34:59.189439
2035 16:34:59.189487 CH=0, VrefRange= 0, VrefLevel = 24
2036 16:34:59.189535 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
2037 16:34:59.189585 TX Bit1 (979~1001) 23 990, Bit9 (968~990) 23 979,
2038 16:34:59.189659 TX Bit2 (980~1003) 24 991, Bit10 (973~996) 24 984,
2039 16:34:59.189749 TX Bit3 (976~994) 19 985, Bit11 (967~989) 23 978,
2040 16:34:59.189858 TX Bit4 (979~1002) 24 990, Bit12 (968~990) 23 979,
2041 16:34:59.189936 TX Bit5 (978~997) 20 987, Bit13 (969~990) 22 979,
2042 16:34:59.190021 TX Bit6 (978~1000) 23 989, Bit14 (969~992) 24 980,
2043 16:34:59.190078 TX Bit7 (980~1001) 22 990, Bit15 (973~995) 23 984,
2044 16:34:59.190132
2045 16:34:59.190185 Write Rank1 MR14 =0x1a
2046 16:34:59.190234
2047 16:34:59.190283 CH=0, VrefRange= 0, VrefLevel = 26
2048 16:34:59.190361 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
2049 16:34:59.190450 TX Bit1 (979~1002) 24 990, Bit9 (968~991) 24 979,
2050 16:34:59.190539 TX Bit2 (980~1003) 24 991, Bit10 (973~996) 24 984,
2051 16:34:59.190623 TX Bit3 (976~995) 20 985, Bit11 (967~989) 23 978,
2052 16:34:59.190687 TX Bit4 (979~1002) 24 990, Bit12 (969~990) 22 979,
2053 16:34:59.190738 TX Bit5 (978~998) 21 988, Bit13 (968~991) 24 979,
2054 16:34:59.190787 TX Bit6 (978~1000) 23 989, Bit14 (969~993) 25 981,
2055 16:34:59.190841 TX Bit7 (979~1001) 23 990, Bit15 (973~995) 23 984,
2056 16:34:59.190893
2057 16:34:59.190942 Write Rank1 MR14 =0x1c
2058 16:34:59.190995
2059 16:34:59.191045 CH=0, VrefRange= 0, VrefLevel = 28
2060 16:34:59.191094 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
2061 16:34:59.191144 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
2062 16:34:59.191192 TX Bit2 (980~1004) 25 992, Bit10 (973~996) 24 984,
2063 16:34:59.191241 TX Bit3 (976~995) 20 985, Bit11 (967~989) 23 978,
2064 16:34:59.191290 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
2065 16:34:59.191343 TX Bit5 (977~999) 23 988, Bit13 (968~990) 23 979,
2066 16:34:59.191595 TX Bit6 (978~1000) 23 989, Bit14 (969~992) 24 980,
2067 16:34:59.191651 TX Bit7 (979~1002) 24 990, Bit15 (973~995) 23 984,
2068 16:34:59.191701
2069 16:34:59.191749 Write Rank1 MR14 =0x1e
2070 16:34:59.191798
2071 16:34:59.191850 CH=0, VrefRange= 0, VrefLevel = 30
2072 16:34:59.191901 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
2073 16:34:59.191951 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
2074 16:34:59.192000 TX Bit2 (980~1004) 25 992, Bit10 (973~996) 24 984,
2075 16:34:59.192072 TX Bit3 (976~996) 21 986, Bit11 (967~990) 24 978,
2076 16:34:59.192158 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
2077 16:34:59.192211 TX Bit5 (978~999) 22 988, Bit13 (968~990) 23 979,
2078 16:34:59.192294 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
2079 16:34:59.192372 TX Bit7 (979~1002) 24 990, Bit15 (971~996) 26 983,
2080 16:34:59.192447
2081 16:34:59.192509 Write Rank1 MR14 =0x20
2082 16:34:59.192561
2083 16:34:59.192609 CH=0, VrefRange= 0, VrefLevel = 32
2084 16:34:59.192681 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
2085 16:34:59.192732 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
2086 16:34:59.192781 TX Bit2 (980~1004) 25 992, Bit10 (973~996) 24 984,
2087 16:34:59.192840 TX Bit3 (976~996) 21 986, Bit11 (967~990) 24 978,
2088 16:34:59.192890 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
2089 16:34:59.192939 TX Bit5 (978~999) 22 988, Bit13 (968~990) 23 979,
2090 16:34:59.192988 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
2091 16:34:59.193037 TX Bit7 (979~1002) 24 990, Bit15 (971~996) 26 983,
2092 16:34:59.193084
2093 16:34:59.193132 Write Rank1 MR14 =0x22
2094 16:34:59.193180
2095 16:34:59.193229 CH=0, VrefRange= 0, VrefLevel = 34
2096 16:34:59.193278 TX Bit0 (980~1005) 26 992, Bit8 (966~989) 24 977,
2097 16:34:59.193327 TX Bit1 (979~1002) 24 990, Bit9 (968~990) 23 979,
2098 16:34:59.193380 TX Bit2 (980~1004) 25 992, Bit10 (973~996) 24 984,
2099 16:34:59.193433 TX Bit3 (976~996) 21 986, Bit11 (967~990) 24 978,
2100 16:34:59.193484 TX Bit4 (979~1003) 25 991, Bit12 (968~991) 24 979,
2101 16:34:59.193533 TX Bit5 (978~999) 22 988, Bit13 (968~990) 23 979,
2102 16:34:59.193581 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
2103 16:34:59.193630 TX Bit7 (979~1002) 24 990, Bit15 (971~996) 26 983,
2104 16:34:59.193702
2105 16:34:59.193752
2106 16:34:59.193801 TX Vref found, early break! 362< 363
2107 16:34:59.193856 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
2108 16:34:59.193906 u1DelayCellOfst[0]=6 cells (6 PI)
2109 16:34:59.193955 u1DelayCellOfst[1]=4 cells (4 PI)
2110 16:34:59.194023 u1DelayCellOfst[2]=6 cells (6 PI)
2111 16:34:59.194075 u1DelayCellOfst[3]=0 cells (0 PI)
2112 16:34:59.194135 u1DelayCellOfst[4]=5 cells (5 PI)
2113 16:34:59.194196 u1DelayCellOfst[5]=2 cells (2 PI)
2114 16:34:59.194282 u1DelayCellOfst[6]=3 cells (3 PI)
2115 16:34:59.194338 u1DelayCellOfst[7]=4 cells (4 PI)
2116 16:34:59.194394 Byte0, DQ PI dly=986, DQM PI dly= 989
2117 16:34:59.194444 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2118 16:34:59.194494
2119 16:34:59.194542 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2120 16:34:59.194592
2121 16:34:59.194642 u1DelayCellOfst[8]=0 cells (0 PI)
2122 16:34:59.194725 u1DelayCellOfst[9]=2 cells (2 PI)
2123 16:34:59.194799 u1DelayCellOfst[10]=8 cells (7 PI)
2124 16:34:59.194874 u1DelayCellOfst[11]=1 cells (1 PI)
2125 16:34:59.194933 u1DelayCellOfst[12]=2 cells (2 PI)
2126 16:34:59.194983 u1DelayCellOfst[13]=2 cells (2 PI)
2127 16:34:59.195032 u1DelayCellOfst[14]=3 cells (3 PI)
2128 16:34:59.195081 u1DelayCellOfst[15]=6 cells (6 PI)
2129 16:34:59.195131 Byte1, DQ PI dly=977, DQM PI dly= 980
2130 16:34:59.195181 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2131 16:34:59.195230
2132 16:34:59.195279 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2133 16:34:59.195336
2134 16:34:59.195389 Write Rank1 MR14 =0x1e
2135 16:34:59.195438
2136 16:34:59.195486 Final TX Range 0 Vref 30
2137 16:34:59.195536
2138 16:34:59.195585 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2139 16:34:59.195634
2140 16:34:59.195682 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2141 16:34:59.195732 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2142 16:34:59.195782 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2143 16:34:59.195832 Write Rank1 MR3 =0xb0
2144 16:34:59.195891 DramC Write-DBI on
2145 16:34:59.195942 ==
2146 16:34:59.195992 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2147 16:34:59.196042 fsp= 1, odt_onoff= 1, Byte mode= 0
2148 16:34:59.196095 ==
2149 16:34:59.196145 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2150 16:34:59.196194
2151 16:34:59.196244 Begin, DQ Scan Range 700~764
2152 16:34:59.196293
2153 16:34:59.196341
2154 16:34:59.196388 TX Vref Scan disable
2155 16:34:59.196442 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2156 16:34:59.196493 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2157 16:34:59.196551 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2158 16:34:59.196601 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2159 16:34:59.196652 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2160 16:34:59.196702 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2161 16:34:59.196752 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2162 16:34:59.196801 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2163 16:34:59.196851 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2164 16:34:59.196900 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2165 16:34:59.196955 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2166 16:34:59.197005 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2167 16:34:59.197055 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2168 16:34:59.197105 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2169 16:34:59.197154 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2170 16:34:59.197207 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2171 16:34:59.197292 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2172 16:34:59.197367 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2173 16:34:59.197445 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2174 16:34:59.197508 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2175 16:34:59.197568 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2176 16:34:59.197618 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2177 16:34:59.197669 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2178 16:34:59.197944 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2179 16:34:59.198030 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2180 16:34:59.198087 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2181 16:34:59.198147 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2182 16:34:59.198245 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2183 16:34:59.198301 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2184 16:34:59.198352 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2185 16:34:59.198413 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2186 16:34:59.198479 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2187 16:34:59.198535 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2188 16:34:59.198588 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2189 16:34:59.198639 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2190 16:34:59.198701 748 |2 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
2191 16:34:59.198751 Byte0, DQ PI dly=735, DQM PI dly= 735
2192 16:34:59.198801 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
2193 16:34:59.198872
2194 16:34:59.198923 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
2195 16:34:59.198972
2196 16:34:59.199022 Byte1, DQ PI dly=723, DQM PI dly= 723
2197 16:34:59.199082 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2198 16:34:59.199132
2199 16:34:59.199181 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2200 16:34:59.199239
2201 16:34:59.199290 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2202 16:34:59.199340 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2203 16:34:59.199390 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2204 16:34:59.199439 Write Rank1 MR3 =0x30
2205 16:34:59.199488 DramC Write-DBI off
2206 16:34:59.199552
2207 16:34:59.199605 [DATLAT]
2208 16:34:59.199654 Freq=1600, CH0 RK1, use_rxtx_scan=0
2209 16:34:59.199702
2210 16:34:59.199751 DATLAT Default: 0x10
2211 16:34:59.199800 7, 0xFFFF, sum=0
2212 16:34:59.199850 8, 0xFFFF, sum=0
2213 16:34:59.199899 9, 0xFFFF, sum=0
2214 16:34:59.199957 10, 0xFFFF, sum=0
2215 16:34:59.200077 11, 0xFFFF, sum=0
2216 16:34:59.200158 12, 0xFFFF, sum=0
2217 16:34:59.200227 13, 0xFFFF, sum=0
2218 16:34:59.200278 14, 0x0, sum=1
2219 16:34:59.200341 15, 0x0, sum=2
2220 16:34:59.200391 16, 0x0, sum=3
2221 16:34:59.200441 17, 0x0, sum=4
2222 16:34:59.200528 pattern=2 first_step=14 total pass=5 best_step=16
2223 16:34:59.200582 ==
2224 16:34:59.200632 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2225 16:34:59.200687 fsp= 1, odt_onoff= 1, Byte mode= 0
2226 16:34:59.200742 ==
2227 16:34:59.200792 Start DQ dly to find pass range UseTestEngine =1
2228 16:34:59.200842 x-axis: bit #, y-axis: DQ dly (-127~63)
2229 16:34:59.200892 RX Vref Scan = 0
2230 16:34:59.200941 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2231 16:34:59.200992 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2232 16:34:59.201042 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2233 16:34:59.201091 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2234 16:34:59.201159 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2235 16:34:59.201211 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2236 16:34:59.201260 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2237 16:34:59.201310 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2238 16:34:59.201360 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2239 16:34:59.201409 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2240 16:34:59.201459 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2241 16:34:59.201509 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2242 16:34:59.201558 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2243 16:34:59.201607 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2244 16:34:59.201657 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2245 16:34:59.201710 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2246 16:34:59.201761 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2247 16:34:59.201810 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2248 16:34:59.201860 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2249 16:34:59.201910 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2250 16:34:59.201960 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2251 16:34:59.202021 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2252 16:34:59.202073 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2253 16:34:59.202146 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2254 16:34:59.202209 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2255 16:34:59.202294 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2256 16:34:59.202348 0, [0] xxxxxxxx xxxxxxxx [MSB]
2257 16:34:59.202400 1, [0] xxxoxxxx oxxxxxxx [MSB]
2258 16:34:59.202450 2, [0] xxxoxxxx oxxxxxxx [MSB]
2259 16:34:59.202500 3, [0] xxxoxxxx oxxoxxxx [MSB]
2260 16:34:59.202550 4, [0] xxxoxoxx oxxoxxxx [MSB]
2261 16:34:59.202599 5, [0] xxxoxoox ooxooxxx [MSB]
2262 16:34:59.202649 6, [0] xxxoxooo ooxooxxx [MSB]
2263 16:34:59.202700 7, [0] xoxoxooo ooxoooox [MSB]
2264 16:34:59.202750 8, [0] xoxoxooo ooxoooox [MSB]
2265 16:34:59.202800 9, [0] oooooooo ooxooooo [MSB]
2266 16:34:59.202855 10, [0] oooooooo ooxooooo [MSB]
2267 16:34:59.202904 33, [0] oooxoooo xooxoooo [MSB]
2268 16:34:59.202954 34, [0] oooxoooo xooxoooo [MSB]
2269 16:34:59.203004 35, [0] oooxoxoo xxoxoxoo [MSB]
2270 16:34:59.203053 36, [0] oooxoxxo xxoxoxoo [MSB]
2271 16:34:59.203104 37, [0] oooxoxxo xxoxxxoo [MSB]
2272 16:34:59.203153 38, [0] oooxxxxx xxoxxxxo [MSB]
2273 16:34:59.203203 39, [0] oooxxxxx xxoxxxxx [MSB]
2274 16:34:59.203252 40, [0] xxxxxxxx xxoxxxxx [MSB]
2275 16:34:59.203308 41, [0] xxxxxxxx xxoxxxxx [MSB]
2276 16:34:59.203363 42, [0] xxxxxxxx xxxxxxxx [MSB]
2277 16:34:59.203413 iDelay=42, Bit 0, Center 24 (9 ~ 39) 31
2278 16:34:59.203463 iDelay=42, Bit 1, Center 23 (7 ~ 39) 33
2279 16:34:59.203511 iDelay=42, Bit 2, Center 24 (9 ~ 39) 31
2280 16:34:59.203560 iDelay=42, Bit 3, Center 16 (1 ~ 32) 32
2281 16:34:59.203609 iDelay=42, Bit 4, Center 23 (9 ~ 37) 29
2282 16:34:59.203657 iDelay=42, Bit 5, Center 19 (4 ~ 34) 31
2283 16:34:59.203706 iDelay=42, Bit 6, Center 20 (5 ~ 35) 31
2284 16:34:59.203755 iDelay=42, Bit 7, Center 21 (6 ~ 37) 32
2285 16:34:59.203807 iDelay=42, Bit 8, Center 16 (1 ~ 32) 32
2286 16:34:59.203895 iDelay=42, Bit 9, Center 19 (5 ~ 34) 30
2287 16:34:59.203968 iDelay=42, Bit 10, Center 26 (11 ~ 41) 31
2288 16:34:59.204041 iDelay=42, Bit 11, Center 17 (3 ~ 32) 30
2289 16:34:59.204098 iDelay=42, Bit 12, Center 20 (5 ~ 36) 32
2290 16:34:59.204148 iDelay=42, Bit 13, Center 20 (7 ~ 34) 28
2291 16:34:59.204198 iDelay=42, Bit 14, Center 22 (7 ~ 37) 31
2292 16:34:59.204247 iDelay=42, Bit 15, Center 23 (9 ~ 38) 30
2293 16:34:59.204295 ==
2294 16:34:59.204344 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2295 16:34:59.204398 fsp= 1, odt_onoff= 1, Byte mode= 0
2296 16:34:59.204456 ==
2297 16:34:59.204535 DQS Delay:
2298 16:34:59.204612 DQS0 = 0, DQS1 = 0
2299 16:34:59.204689 DQM Delay:
2300 16:34:59.204766 DQM0 = 21, DQM1 = 20
2301 16:34:59.204843 DQ Delay:
2302 16:34:59.204915 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =16
2303 16:34:59.204965 DQ4 =23, DQ5 =19, DQ6 =20, DQ7 =21
2304 16:34:59.205227 DQ8 =16, DQ9 =19, DQ10 =26, DQ11 =17
2305 16:34:59.205286 DQ12 =20, DQ13 =20, DQ14 =22, DQ15 =23
2306 16:34:59.205337
2307 16:34:59.205390
2308 16:34:59.205440
2309 16:34:59.205489 [DramC_TX_OE_Calibration] TA2
2310 16:34:59.205538 Original DQ_B0 (3 6) =30, OEN = 27
2311 16:34:59.205587 Original DQ_B1 (3 6) =30, OEN = 27
2312 16:34:59.205637 23, 0x0, End_B0=23 End_B1=23
2313 16:34:59.205693 24, 0x0, End_B0=24 End_B1=24
2314 16:34:59.205745 25, 0x0, End_B0=25 End_B1=25
2315 16:34:59.205795 26, 0x0, End_B0=26 End_B1=26
2316 16:34:59.205843 27, 0x0, End_B0=27 End_B1=27
2317 16:34:59.205892 28, 0x0, End_B0=28 End_B1=28
2318 16:34:59.205946 29, 0x0, End_B0=29 End_B1=29
2319 16:34:59.206012 30, 0x0, End_B0=30 End_B1=30
2320 16:34:59.206094 31, 0xFFFF, End_B0=30 End_B1=30
2321 16:34:59.206189 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2322 16:34:59.206270 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2323 16:34:59.206321
2324 16:34:59.206399
2325 16:34:59.206480 Write Rank1 MR23 =0x3f
2326 16:34:59.206552 [DQSOSC]
2327 16:34:59.206630 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
2328 16:34:59.206709 CH0_RK1: MR19=0x202, MR18=0xB7B7, DQSOSC=453, MR23=63, INC=11, DEC=17
2329 16:34:59.206787 Write Rank1 MR23 =0x3f
2330 16:34:59.206863 [DQSOSC]
2331 16:34:59.206945 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
2332 16:34:59.207026 CH0 RK1: MR19=202, MR18=B7B7
2333 16:34:59.207104 [RxdqsGatingPostProcess] freq 1600
2334 16:34:59.207183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2335 16:34:59.207259 Rank: 0
2336 16:34:59.207336 best DQS0 dly(2T, 0.5T) = (2, 6)
2337 16:34:59.207414 best DQS1 dly(2T, 0.5T) = (2, 6)
2338 16:34:59.207495 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2339 16:34:59.207573 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2340 16:34:59.207653 Rank: 1
2341 16:34:59.207729 best DQS0 dly(2T, 0.5T) = (2, 6)
2342 16:34:59.207806 best DQS1 dly(2T, 0.5T) = (2, 6)
2343 16:34:59.207883 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2344 16:34:59.207963 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2345 16:34:59.208040 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2346 16:34:59.208118 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2347 16:34:59.208197 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2348 16:34:59.208255 Write Rank0 MR13 =0x59
2349 16:34:59.208304 ==
2350 16:34:59.208353 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2351 16:34:59.208403 fsp= 1, odt_onoff= 1, Byte mode= 0
2352 16:34:59.208456 ==
2353 16:34:59.208505 === u2Vref_new: 0x56 --> 0x3a
2354 16:34:59.208554 === u2Vref_new: 0x58 --> 0x58
2355 16:34:59.208603 === u2Vref_new: 0x5a --> 0x5a
2356 16:34:59.208653 === u2Vref_new: 0x5c --> 0x78
2357 16:34:59.208701 === u2Vref_new: 0x5e --> 0x7a
2358 16:34:59.208749 === u2Vref_new: 0x60 --> 0x90
2359 16:34:59.208798 [CA 0] Center 38 (14~63) winsize 50
2360 16:34:59.208853 [CA 1] Center 37 (11~63) winsize 53
2361 16:34:59.208934 [CA 2] Center 35 (7~63) winsize 57
2362 16:34:59.209015 [CA 3] Center 34 (6~63) winsize 58
2363 16:34:59.209089 [CA 4] Center 34 (5~63) winsize 59
2364 16:34:59.209139 [CA 5] Center 29 (0~58) winsize 59
2365 16:34:59.209187
2366 16:34:59.209236 [CATrainingPosCal] consider 1 rank data
2367 16:34:59.209284 u2DelayCellTimex100 = 844/100 ps
2368 16:34:59.209333 CA0 delay=38 (14~63),Diff = 9 PI (10 cell)
2369 16:34:59.209381 CA1 delay=37 (11~63),Diff = 8 PI (9 cell)
2370 16:34:59.209433 CA2 delay=35 (7~63),Diff = 6 PI (6 cell)
2371 16:34:59.209486 CA3 delay=34 (6~63),Diff = 5 PI (5 cell)
2372 16:34:59.209535 CA4 delay=34 (5~63),Diff = 5 PI (5 cell)
2373 16:34:59.209583 CA5 delay=29 (0~58),Diff = 0 PI (0 cell)
2374 16:34:59.209630
2375 16:34:59.209677 CA PerBit enable=1, Macro0, CA PI delay=29
2376 16:34:59.209726 === u2Vref_new: 0x60 --> 0x90
2377 16:34:59.209774
2378 16:34:59.209823 Vref(ca) range 1: 32
2379 16:34:59.209870
2380 16:34:59.209918 CS Dly= 11 (42-0-32)
2381 16:34:59.209966 Write Rank0 MR13 =0xd8
2382 16:34:59.210038 Write Rank0 MR13 =0xd8
2383 16:34:59.210093 Write Rank0 MR12 =0x60
2384 16:34:59.210173 Write Rank1 MR13 =0x59
2385 16:34:59.210255 ==
2386 16:34:59.210335 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2387 16:34:59.210413 fsp= 1, odt_onoff= 1, Byte mode= 0
2388 16:34:59.210489 ==
2389 16:34:59.210571 === u2Vref_new: 0x56 --> 0x3a
2390 16:34:59.210652 === u2Vref_new: 0x58 --> 0x58
2391 16:34:59.210730 === u2Vref_new: 0x5a --> 0x5a
2392 16:34:59.210807 === u2Vref_new: 0x5c --> 0x78
2393 16:34:59.210884 === u2Vref_new: 0x5e --> 0x7a
2394 16:34:59.210963 === u2Vref_new: 0x60 --> 0x90
2395 16:34:59.211046 [CA 0] Center 36 (10~63) winsize 54
2396 16:34:59.211123 [CA 1] Center 37 (11~63) winsize 53
2397 16:34:59.211208 [CA 2] Center 34 (5~63) winsize 59
2398 16:34:59.211291 [CA 3] Center 35 (7~63) winsize 57
2399 16:34:59.211363 [CA 4] Center 34 (5~63) winsize 59
2400 16:34:59.211433 [CA 5] Center 28 (-1~57) winsize 59
2401 16:34:59.211488
2402 16:34:59.211541 [CATrainingPosCal] consider 2 rank data
2403 16:34:59.211591 u2DelayCellTimex100 = 844/100 ps
2404 16:34:59.211640 CA0 delay=38 (14~63),Diff = 10 PI (11 cell)
2405 16:34:59.211689 CA1 delay=37 (11~63),Diff = 9 PI (10 cell)
2406 16:34:59.211745 CA2 delay=35 (7~63),Diff = 7 PI (8 cell)
2407 16:34:59.211795 CA3 delay=35 (7~63),Diff = 7 PI (8 cell)
2408 16:34:59.211843 CA4 delay=34 (5~63),Diff = 6 PI (6 cell)
2409 16:34:59.211891 CA5 delay=28 (0~57),Diff = 0 PI (0 cell)
2410 16:34:59.211939
2411 16:34:59.211987 CA PerBit enable=1, Macro0, CA PI delay=28
2412 16:34:59.212040 === u2Vref_new: 0x60 --> 0x90
2413 16:34:59.212090
2414 16:34:59.212142 Vref(ca) range 1: 32
2415 16:34:59.212225
2416 16:34:59.212313 CS Dly= 11 (42-0-32)
2417 16:34:59.212398 Write Rank1 MR13 =0xd8
2418 16:34:59.212475 Write Rank1 MR13 =0xd8
2419 16:34:59.212555 Write Rank1 MR12 =0x60
2420 16:34:59.212632 [RankSwap] Rank num 2, (Multi 1), Rank 0
2421 16:34:59.212708 Write Rank0 MR2 =0xad
2422 16:34:59.212784 [Write Leveling]
2423 16:34:59.212861 delay byte0 byte1 byte2 byte3
2424 16:34:59.212926
2425 16:34:59.212976 10 0 0
2426 16:34:59.213026 11 0 0
2427 16:34:59.213079 12 0 0
2428 16:34:59.213129 13 0 0
2429 16:34:59.213194 14 0 0
2430 16:34:59.213250 15 0 0
2431 16:34:59.213313 16 0 0
2432 16:34:59.213394 17 0 0
2433 16:34:59.213474 18 0 0
2434 16:34:59.213559 19 0 0
2435 16:34:59.213639 20 0 0
2436 16:34:59.213712 21 0 0
2437 16:34:59.213793 22 0 0
2438 16:34:59.213876 23 0 0
2439 16:34:59.213957 24 0 0
2440 16:34:59.214043 25 0 0
2441 16:34:59.214162 26 0 0
2442 16:34:59.214256 27 0 0
2443 16:34:59.214344 28 0 0
2444 16:34:59.214440 29 0 0
2445 16:34:59.214522 30 0 0
2446 16:34:59.214597 31 0 0
2447 16:34:59.214851 32 0 ff
2448 16:34:59.214934 33 0 ff
2449 16:34:59.215013 34 ff ff
2450 16:34:59.215095 35 ff ff
2451 16:34:59.215175 36 ff ff
2452 16:34:59.215272 37 ff ff
2453 16:34:59.215376 38 ff ff
2454 16:34:59.215446 39 ff ff
2455 16:34:59.215498 40 ff ff
2456 16:34:59.215548 pass bytecount = 0xff (0xff: all bytes pass)
2457 16:34:59.215598
2458 16:34:59.215651 DQS0 dly: 34
2459 16:34:59.215700 DQS1 dly: 32
2460 16:34:59.215748 Write Rank0 MR2 =0x2d
2461 16:34:59.215803 [RankSwap] Rank num 2, (Multi 1), Rank 0
2462 16:34:59.215854 Write Rank0 MR1 =0xd6
2463 16:34:59.215902 [Gating]
2464 16:34:59.215960 ==
2465 16:34:59.216048 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2466 16:34:59.216122 fsp= 1, odt_onoff= 1, Byte mode= 0
2467 16:34:59.216195 ==
2468 16:34:59.216281 3 1 0 |3534 605 |(11 11)(11 11) |(0 0)(1 1)| 0
2469 16:34:59.216373 3 1 4 |3534 2c2c |(11 11)(11 11) |(0 0)(1 1)| 0
2470 16:34:59.216489 3 1 8 |3534 2d2c |(11 11)(11 11) |(0 0)(1 1)| 0
2471 16:34:59.216581 3 1 12 |3534 2d2d |(11 11)(11 11) |(0 0)(1 1)| 0
2472 16:34:59.216676 3 1 16 |3534 2f2e |(11 11)(11 11) |(0 0)(1 1)| 0
2473 16:34:59.216767 3 1 20 |3534 3332 |(11 11)(11 11) |(1 1)(1 1)| 0
2474 16:34:59.216848 [Byte 1] Lead/lag falling Transition (3, 1, 20)
2475 16:34:59.216926 3 1 24 |3534 2e2e |(11 11)(10 10) |(1 1)(1 0)| 0
2476 16:34:59.217009 3 1 28 |3534 2e2e |(11 11)(11 11) |(0 1)(1 1)| 0
2477 16:34:59.217089 [Byte 1] Lead/lag falling Transition (3, 1, 28)
2478 16:34:59.217160 3 2 0 |3534 2524 |(11 11)(11 11) |(0 1)(0 1)| 0
2479 16:34:59.217218 3 2 4 |3534 2d2c |(11 11)(11 11) |(0 1)(0 1)| 0
2480 16:34:59.217300 3 2 8 |3534 2f2f |(11 11)(11 11) |(0 1)(1 0)| 0
2481 16:34:59.217383 3 2 12 |3534 2524 |(11 11)(11 11) |(0 1)(0 1)| 0
2482 16:34:59.217462 3 2 16 |3534 2d2c |(11 11)(11 11) |(0 1)(0 1)| 0
2483 16:34:59.217541 3 2 20 |201 2d2c |(11 11)(11 11) |(1 1)(0 1)| 0
2484 16:34:59.217621 [Byte 1] Lead/lag Transition tap number (7)
2485 16:34:59.217715 3 2 24 |1515 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2486 16:34:59.217804 3 2 28 |3d3d 909 |(11 11)(11 11) |(1 1)(1 1)| 0
2487 16:34:59.217906 3 3 0 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2488 16:34:59.220342 3 3 4 |3d3d 3938 |(11 11)(11 11) |(1 1)(1 1)| 0
2489 16:34:59.223865 3 3 8 |3d3d 3736 |(11 11)(11 11) |(1 1)(0 0)| 0
2490 16:34:59.230713 3 3 12 |3d3d 3737 |(11 11)(11 11) |(1 1)(0 0)| 0
2491 16:34:59.233624 3 3 16 |3d3d 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
2492 16:34:59.236949 3 3 20 |3d3d 3636 |(11 11)(11 11) |(1 1)(0 0)| 0
2493 16:34:59.243266 3 3 24 |1010 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
2494 16:34:59.246878 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2495 16:34:59.249826 [Byte 0] Lead/lag falling Transition (3, 3, 28)
2496 16:34:59.256637 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2497 16:34:59.260159 [Byte 1] Lead/lag falling Transition (3, 4, 0)
2498 16:34:59.263282 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2499 16:34:59.270132 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2500 16:34:59.273854 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2501 16:34:59.276875 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2502 16:34:59.280169 3 4 20 |504 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2503 16:34:59.286561 3 4 24 |1313 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2504 16:34:59.289799 3 4 28 |3d3d 3231 |(11 11)(11 11) |(1 1)(1 1)| 0
2505 16:34:59.293329 3 5 0 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
2506 16:34:59.299749 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2507 16:34:59.303344 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2508 16:34:59.306789 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2509 16:34:59.312974 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2510 16:34:59.316664 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2511 16:34:59.319823 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2512 16:34:59.326240 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2513 16:34:59.329487 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2514 16:34:59.332820 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2515 16:34:59.339454 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2516 16:34:59.342860 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2517 16:34:59.346107 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2518 16:34:59.349662 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2519 16:34:59.356519 [Byte 0] Lead/lag Transition tap number (3)
2520 16:34:59.359565 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2521 16:34:59.362923 [Byte 1] Lead/lag falling Transition (3, 6, 20)
2522 16:34:59.365966 3 6 24 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
2523 16:34:59.369761 [Byte 0]First pass (3, 6, 24)
2524 16:34:59.372538 [Byte 1] Lead/lag Transition tap number (2)
2525 16:34:59.379350 3 6 28 |4646 403 |(0 0)(11 11) |(0 0)(0 0)| 0
2526 16:34:59.383095 3 7 0 |4646 404 |(0 0)(1 1) |(0 0)(0 0)| 0
2527 16:34:59.386194 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2528 16:34:59.389124 [Byte 1]First pass (3, 7, 4)
2529 16:34:59.392603 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2530 16:34:59.396114 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2531 16:34:59.399507 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2532 16:34:59.405821 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2533 16:34:59.409381 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2534 16:34:59.412735 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2535 16:34:59.415853 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2536 16:34:59.419439 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2537 16:34:59.425992 All bytes gating window > 1UI, Early break!
2538 16:34:59.426136
2539 16:34:59.429082 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 14)
2540 16:34:59.429170
2541 16:34:59.432652 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 24)
2542 16:34:59.432742
2543 16:34:59.432805
2544 16:34:59.432869
2545 16:34:59.436180 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
2546 16:34:59.436266
2547 16:34:59.439103 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 24)
2548 16:34:59.442893
2549 16:34:59.442988
2550 16:34:59.443051 Write Rank0 MR1 =0x56
2551 16:34:59.443115
2552 16:34:59.445997 best RODT dly(2T, 0.5T) = (2, 3)
2553 16:34:59.446081
2554 16:34:59.449093 best RODT dly(2T, 0.5T) = (2, 3)
2555 16:34:59.449177 ==
2556 16:34:59.455720 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2557 16:34:59.459224 fsp= 1, odt_onoff= 1, Byte mode= 0
2558 16:34:59.459349 ==
2559 16:34:59.462316 Start DQ dly to find pass range UseTestEngine =0
2560 16:34:59.465630 x-axis: bit #, y-axis: DQ dly (-127~63)
2561 16:34:59.465728 RX Vref Scan = 0
2562 16:34:59.469364 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2563 16:34:59.472552 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2564 16:34:59.476005 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2565 16:34:59.478975 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2566 16:34:59.482572 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2567 16:34:59.485623 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2568 16:34:59.489191 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2569 16:34:59.492325 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2570 16:34:59.492441 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2571 16:34:59.495312 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2572 16:34:59.498882 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2573 16:34:59.502312 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2574 16:34:59.505759 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2575 16:34:59.508585 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2576 16:34:59.512065 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2577 16:34:59.515604 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2578 16:34:59.515715 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2579 16:34:59.518713 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2580 16:34:59.522189 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2581 16:34:59.525798 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2582 16:34:59.528969 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2583 16:34:59.532043 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2584 16:34:59.535605 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2585 16:34:59.535717 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2586 16:34:59.538621 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2587 16:34:59.541663 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2588 16:34:59.545239 0, [0] xxxxxxxx xxxxxxxo [MSB]
2589 16:34:59.548504 1, [0] xxxxxxxx xxxxxxxo [MSB]
2590 16:34:59.551983 2, [0] xxxxxxxx xoxxxxxo [MSB]
2591 16:34:59.555136 3, [0] xxxoxxxx xoxxxxxo [MSB]
2592 16:34:59.555224 4, [0] xxxoxxxx ooxxxxxo [MSB]
2593 16:34:59.558648 5, [0] xoxoxxxx ooxxxxxo [MSB]
2594 16:34:59.562016 6, [0] xoooxxxo ooxxxxxo [MSB]
2595 16:34:59.565525 7, [0] xooooxxo oooxoxoo [MSB]
2596 16:34:59.568330 31, [0] oooooooo ooooooox [MSB]
2597 16:34:59.572295 32, [0] oooooooo ooooooox [MSB]
2598 16:34:59.572418 33, [0] oooooooo ooooooox [MSB]
2599 16:34:59.575229 34, [0] oooooooo oxooooox [MSB]
2600 16:34:59.578658 35, [0] ooxxoooo xxooooox [MSB]
2601 16:34:59.581971 36, [0] ooxxoooo xxooooox [MSB]
2602 16:34:59.585139 37, [0] ooxxxooo xxxoooox [MSB]
2603 16:34:59.588687 38, [0] oxxxxooo xxxxoxxx [MSB]
2604 16:34:59.591643 39, [0] oxxxxoox xxxxxxxx [MSB]
2605 16:34:59.591760 40, [0] oxxxxxox xxxxxxxx [MSB]
2606 16:34:59.595335 41, [0] xxxxxxxx xxxxxxxx [MSB]
2607 16:34:59.598443 iDelay=41, Bit 0, Center 24 (8 ~ 40) 33
2608 16:34:59.602178 iDelay=41, Bit 1, Center 21 (5 ~ 37) 33
2609 16:34:59.605683 iDelay=41, Bit 2, Center 20 (6 ~ 34) 29
2610 16:34:59.612015 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
2611 16:34:59.615225 iDelay=41, Bit 4, Center 21 (7 ~ 36) 30
2612 16:34:59.618655 iDelay=41, Bit 5, Center 23 (8 ~ 39) 32
2613 16:34:59.621634 iDelay=41, Bit 6, Center 24 (8 ~ 40) 33
2614 16:34:59.625402 iDelay=41, Bit 7, Center 22 (6 ~ 38) 33
2615 16:34:59.628405 iDelay=41, Bit 8, Center 19 (4 ~ 34) 31
2616 16:34:59.632118 iDelay=41, Bit 9, Center 17 (2 ~ 33) 32
2617 16:34:59.635231 iDelay=41, Bit 10, Center 21 (7 ~ 36) 30
2618 16:34:59.638272 iDelay=41, Bit 11, Center 22 (8 ~ 37) 30
2619 16:34:59.641850 iDelay=41, Bit 12, Center 22 (7 ~ 38) 32
2620 16:34:59.644958 iDelay=41, Bit 13, Center 22 (8 ~ 37) 30
2621 16:34:59.648576 iDelay=41, Bit 14, Center 22 (7 ~ 37) 31
2622 16:34:59.651674 iDelay=41, Bit 15, Center 14 (-1 ~ 30) 32
2623 16:34:59.655187 ==
2624 16:34:59.658188 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2625 16:34:59.661352 fsp= 1, odt_onoff= 1, Byte mode= 0
2626 16:34:59.661463 ==
2627 16:34:59.661551 DQS Delay:
2628 16:34:59.664708 DQS0 = 0, DQS1 = 0
2629 16:34:59.664823 DQM Delay:
2630 16:34:59.668115 DQM0 = 21, DQM1 = 19
2631 16:34:59.668202 DQ Delay:
2632 16:34:59.671614 DQ0 =24, DQ1 =21, DQ2 =20, DQ3 =18
2633 16:34:59.675274 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
2634 16:34:59.678263 DQ8 =19, DQ9 =17, DQ10 =21, DQ11 =22
2635 16:34:59.681851 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =14
2636 16:34:59.681972
2637 16:34:59.682079
2638 16:34:59.685433 DramC Write-DBI off
2639 16:34:59.685543 ==
2640 16:34:59.688482 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2641 16:34:59.691726 fsp= 1, odt_onoff= 1, Byte mode= 0
2642 16:34:59.691846 ==
2643 16:34:59.695083 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2644 16:34:59.698518
2645 16:34:59.698636 Begin, DQ Scan Range 928~1184
2646 16:34:59.698729
2647 16:34:59.698815
2648 16:34:59.702081 TX Vref Scan disable
2649 16:34:59.705066 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2650 16:34:59.708660 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2651 16:34:59.712153 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2652 16:34:59.714995 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2653 16:34:59.718551 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2654 16:34:59.722030 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2655 16:34:59.725317 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2656 16:34:59.728331 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2657 16:34:59.734834 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2658 16:34:59.738591 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2659 16:34:59.741543 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2660 16:34:59.744732 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2661 16:34:59.748217 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2662 16:34:59.751785 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2663 16:34:59.754706 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2664 16:34:59.758296 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2665 16:34:59.761214 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2666 16:34:59.764831 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2667 16:34:59.767855 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2668 16:34:59.771356 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2669 16:34:59.774389 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2670 16:34:59.778358 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2671 16:34:59.784418 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2672 16:34:59.788180 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2673 16:34:59.791137 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2674 16:34:59.794827 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2675 16:34:59.797885 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2676 16:34:59.801284 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2677 16:34:59.804671 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2678 16:34:59.807690 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2679 16:34:59.811141 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2680 16:34:59.814524 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2681 16:34:59.817936 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2682 16:34:59.821330 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2683 16:34:59.824504 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2684 16:34:59.828016 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2685 16:34:59.831235 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2686 16:34:59.834514 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2687 16:34:59.837380 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2688 16:34:59.841063 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2689 16:34:59.844280 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2690 16:34:59.847937 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2691 16:34:59.854153 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2692 16:34:59.857702 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2693 16:34:59.860687 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2694 16:34:59.864409 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2695 16:34:59.867357 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2696 16:34:59.871010 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2697 16:34:59.873913 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2698 16:34:59.877615 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2699 16:34:59.880551 978 |3 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2700 16:34:59.883739 979 |3 6 19|[0] xxxxxxxx ooxxxxxo [MSB]
2701 16:34:59.887085 980 |3 6 20|[0] xxxxxxxx ooxxxxxo [MSB]
2702 16:34:59.890797 981 |3 6 21|[0] xxxxxxxx ooxxxxxo [MSB]
2703 16:34:59.893694 982 |3 6 22|[0] xxxxxxxx ooooxxoo [MSB]
2704 16:34:59.897699 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
2705 16:34:59.900736 984 |3 6 24|[0] xooooxoo oooooooo [MSB]
2706 16:34:59.908594 995 |3 6 35|[0] oooooooo ooooooox [MSB]
2707 16:34:59.912286 996 |3 6 36|[0] oooooooo ooooooox [MSB]
2708 16:34:59.915624 997 |3 6 37|[0] oooooooo ooooooox [MSB]
2709 16:34:59.918912 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2710 16:34:59.921935 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2711 16:34:59.925388 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
2712 16:34:59.929050 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2713 16:34:59.932181 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2714 16:34:59.935648 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2715 16:34:59.939026 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
2716 16:34:59.941935 1005 |3 6 45|[0] oxxxooox xxxxxxxx [MSB]
2717 16:34:59.945636 1006 |3 6 46|[0] oxxxooox xxxxxxxx [MSB]
2718 16:34:59.948796 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2719 16:34:59.955429 Byte0, DQ PI dly=993, DQM PI dly= 993
2720 16:34:59.958629 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
2721 16:34:59.958752
2722 16:34:59.962155 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
2723 16:34:59.962271
2724 16:34:59.965781 Byte1, DQ PI dly=988, DQM PI dly= 988
2725 16:34:59.972405 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2726 16:34:59.972541
2727 16:34:59.975474 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2728 16:34:59.975561
2729 16:34:59.975642 ==
2730 16:34:59.978915 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2731 16:34:59.982201 fsp= 1, odt_onoff= 1, Byte mode= 0
2732 16:34:59.982285 ==
2733 16:34:59.988823 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2734 16:34:59.988949
2735 16:34:59.992291 Begin, DQ Scan Range 964~1028
2736 16:34:59.992407 Write Rank0 MR14 =0x0
2737 16:35:00.000239
2738 16:35:00.000368 CH=1, VrefRange= 0, VrefLevel = 0
2739 16:35:00.007397 TX Bit0 (986~1001) 16 993, Bit8 (982~993) 12 987,
2740 16:35:00.010316 TX Bit1 (985~999) 15 992, Bit9 (981~992) 12 986,
2741 16:35:00.017157 TX Bit2 (983~999) 17 991, Bit10 (984~995) 12 989,
2742 16:35:00.020099 TX Bit3 (982~994) 13 988, Bit11 (984~996) 13 990,
2743 16:35:00.023684 TX Bit4 (985~1000) 16 992, Bit12 (985~996) 12 990,
2744 16:35:00.030721 TX Bit5 (987~1000) 14 993, Bit13 (985~993) 9 989,
2745 16:35:00.033932 TX Bit6 (985~1000) 16 992, Bit14 (984~995) 12 989,
2746 16:35:00.040352 TX Bit7 (985~1000) 16 992, Bit15 (978~989) 12 983,
2747 16:35:00.040458
2748 16:35:00.040522 Write Rank0 MR14 =0x2
2749 16:35:00.048651
2750 16:35:00.048752 CH=1, VrefRange= 0, VrefLevel = 2
2751 16:35:00.055695 TX Bit0 (986~1002) 17 994, Bit8 (982~993) 12 987,
2752 16:35:00.058920 TX Bit1 (985~1000) 16 992, Bit9 (982~993) 12 987,
2753 16:35:00.065500 TX Bit2 (983~1000) 18 991, Bit10 (984~995) 12 989,
2754 16:35:00.068581 TX Bit3 (981~995) 15 988, Bit11 (984~998) 15 991,
2755 16:35:00.072255 TX Bit4 (985~1001) 17 993, Bit12 (984~997) 14 990,
2756 16:35:00.078302 TX Bit5 (986~1001) 16 993, Bit13 (985~995) 11 990,
2757 16:35:00.081894 TX Bit6 (985~1001) 17 993, Bit14 (984~996) 13 990,
2758 16:35:00.088729 TX Bit7 (985~1000) 16 992, Bit15 (977~990) 14 983,
2759 16:35:00.088874
2760 16:35:00.088976 Write Rank0 MR14 =0x4
2761 16:35:00.097316
2762 16:35:00.097451 CH=1, VrefRange= 0, VrefLevel = 4
2763 16:35:00.103805 TX Bit0 (986~1002) 17 994, Bit8 (981~994) 14 987,
2764 16:35:00.107436 TX Bit1 (985~1000) 16 992, Bit9 (980~993) 14 986,
2765 16:35:00.114429 TX Bit2 (983~1000) 18 991, Bit10 (984~996) 13 990,
2766 16:35:00.117019 TX Bit3 (981~996) 16 988, Bit11 (984~998) 15 991,
2767 16:35:00.120421 TX Bit4 (984~1001) 18 992, Bit12 (984~998) 15 991,
2768 16:35:00.127101 TX Bit5 (986~1001) 16 993, Bit13 (985~995) 11 990,
2769 16:35:00.130594 TX Bit6 (984~1002) 19 993, Bit14 (984~997) 14 990,
2770 16:35:00.137567 TX Bit7 (985~1001) 17 993, Bit15 (977~991) 15 984,
2771 16:35:00.137712
2772 16:35:00.137816 Write Rank0 MR14 =0x6
2773 16:35:00.146055
2774 16:35:00.146207 CH=1, VrefRange= 0, VrefLevel = 6
2775 16:35:00.152457 TX Bit0 (986~1003) 18 994, Bit8 (981~995) 15 988,
2776 16:35:00.155795 TX Bit1 (985~1001) 17 993, Bit9 (980~994) 15 987,
2777 16:35:00.162704 TX Bit2 (982~1001) 20 991, Bit10 (983~998) 16 990,
2778 16:35:00.166180 TX Bit3 (980~996) 17 988, Bit11 (984~999) 16 991,
2779 16:35:00.169598 TX Bit4 (984~1002) 19 993, Bit12 (984~998) 15 991,
2780 16:35:00.175894 TX Bit5 (986~1002) 17 994, Bit13 (985~997) 13 991,
2781 16:35:00.179253 TX Bit6 (984~1002) 19 993, Bit14 (983~998) 16 990,
2782 16:35:00.185976 TX Bit7 (985~1001) 17 993, Bit15 (977~991) 15 984,
2783 16:35:00.186104
2784 16:35:00.186169 Write Rank0 MR14 =0x8
2785 16:35:00.194727
2786 16:35:00.194845 CH=1, VrefRange= 0, VrefLevel = 8
2787 16:35:00.201464 TX Bit0 (986~1004) 19 995, Bit8 (980~995) 16 987,
2788 16:35:00.205011 TX Bit1 (985~1001) 17 993, Bit9 (979~994) 16 986,
2789 16:35:00.211865 TX Bit2 (983~1001) 19 992, Bit10 (983~998) 16 990,
2790 16:35:00.214998 TX Bit3 (980~997) 18 988, Bit11 (983~999) 17 991,
2791 16:35:00.217857 TX Bit4 (984~1003) 20 993, Bit12 (984~999) 16 991,
2792 16:35:00.224578 TX Bit5 (986~1003) 18 994, Bit13 (984~998) 15 991,
2793 16:35:00.227740 TX Bit6 (984~1003) 20 993, Bit14 (983~999) 17 991,
2794 16:35:00.234514 TX Bit7 (984~1002) 19 993, Bit15 (976~992) 17 984,
2795 16:35:00.234619
2796 16:35:00.234682 Write Rank0 MR14 =0xa
2797 16:35:00.243999
2798 16:35:00.247059 CH=1, VrefRange= 0, VrefLevel = 10
2799 16:35:00.250650 TX Bit0 (985~1005) 21 995, Bit8 (979~996) 18 987,
2800 16:35:00.253525 TX Bit1 (984~1002) 19 993, Bit9 (979~995) 17 987,
2801 16:35:00.260456 TX Bit2 (982~1002) 21 992, Bit10 (983~999) 17 991,
2802 16:35:00.263878 TX Bit3 (980~998) 19 989, Bit11 (983~999) 17 991,
2803 16:35:00.267447 TX Bit4 (984~1003) 20 993, Bit12 (983~999) 17 991,
2804 16:35:00.273487 TX Bit5 (986~1004) 19 995, Bit13 (984~998) 15 991,
2805 16:35:00.276979 TX Bit6 (984~1003) 20 993, Bit14 (983~999) 17 991,
2806 16:35:00.283389 TX Bit7 (984~1003) 20 993, Bit15 (977~992) 16 984,
2807 16:35:00.283517
2808 16:35:00.283614 Write Rank0 MR14 =0xc
2809 16:35:00.293001
2810 16:35:00.296089 CH=1, VrefRange= 0, VrefLevel = 12
2811 16:35:00.299703 TX Bit0 (985~1004) 20 994, Bit8 (979~996) 18 987,
2812 16:35:00.302801 TX Bit1 (984~1003) 20 993, Bit9 (978~996) 19 987,
2813 16:35:00.309278 TX Bit2 (981~1002) 22 991, Bit10 (983~999) 17 991,
2814 16:35:00.313122 TX Bit3 (979~999) 21 989, Bit11 (983~1000) 18 991,
2815 16:35:00.315676 TX Bit4 (983~1004) 22 993, Bit12 (983~999) 17 991,
2816 16:35:00.322747 TX Bit5 (986~1004) 19 995, Bit13 (984~999) 16 991,
2817 16:35:00.325908 TX Bit6 (984~1004) 21 994, Bit14 (982~999) 18 990,
2818 16:35:00.332300 TX Bit7 (984~1003) 20 993, Bit15 (975~993) 19 984,
2819 16:35:00.332403
2820 16:35:00.332466 Write Rank0 MR14 =0xe
2821 16:35:00.341781
2822 16:35:00.345173 CH=1, VrefRange= 0, VrefLevel = 14
2823 16:35:00.348637 TX Bit0 (985~1005) 21 995, Bit8 (978~998) 21 988,
2824 16:35:00.352201 TX Bit1 (984~1004) 21 994, Bit9 (978~997) 20 987,
2825 16:35:00.358760 TX Bit2 (981~1003) 23 992, Bit10 (982~1000) 19 991,
2826 16:35:00.362007 TX Bit3 (979~1000) 22 989, Bit11 (983~1000) 18 991,
2827 16:35:00.365075 TX Bit4 (983~1005) 23 994, Bit12 (983~1000) 18 991,
2828 16:35:00.371727 TX Bit5 (985~1005) 21 995, Bit13 (984~999) 16 991,
2829 16:35:00.375323 TX Bit6 (983~1005) 23 994, Bit14 (982~1000) 19 991,
2830 16:35:00.381951 TX Bit7 (984~1004) 21 994, Bit15 (975~993) 19 984,
2831 16:35:00.382060
2832 16:35:00.382122 Write Rank0 MR14 =0x10
2833 16:35:00.391727
2834 16:35:00.395248 CH=1, VrefRange= 0, VrefLevel = 16
2835 16:35:00.398617 TX Bit0 (984~1006) 23 995, Bit8 (977~997) 21 987,
2836 16:35:00.401849 TX Bit1 (983~1004) 22 993, Bit9 (978~997) 20 987,
2837 16:35:00.408569 TX Bit2 (981~1004) 24 992, Bit10 (982~1000) 19 991,
2838 16:35:00.411566 TX Bit3 (979~1000) 22 989, Bit11 (983~1000) 18 991,
2839 16:35:00.418228 TX Bit4 (983~1005) 23 994, Bit12 (983~1000) 18 991,
2840 16:35:00.421861 TX Bit5 (985~1006) 22 995, Bit13 (983~999) 17 991,
2841 16:35:00.424876 TX Bit6 (983~1006) 24 994, Bit14 (982~1000) 19 991,
2842 16:35:00.431530 TX Bit7 (983~1004) 22 993, Bit15 (976~993) 18 984,
2843 16:35:00.431655
2844 16:35:00.431719 Write Rank0 MR14 =0x12
2845 16:35:00.441790
2846 16:35:00.445142 CH=1, VrefRange= 0, VrefLevel = 18
2847 16:35:00.448412 TX Bit0 (984~1007) 24 995, Bit8 (978~998) 21 988,
2848 16:35:00.451675 TX Bit1 (983~1005) 23 994, Bit9 (978~998) 21 988,
2849 16:35:00.458241 TX Bit2 (980~1004) 25 992, Bit10 (982~1000) 19 991,
2850 16:35:00.461607 TX Bit3 (979~1001) 23 990, Bit11 (982~1001) 20 991,
2851 16:35:00.468260 TX Bit4 (982~1006) 25 994, Bit12 (982~1000) 19 991,
2852 16:35:00.471741 TX Bit5 (985~1006) 22 995, Bit13 (983~1000) 18 991,
2853 16:35:00.474677 TX Bit6 (983~1006) 24 994, Bit14 (982~1000) 19 991,
2854 16:35:00.481657 TX Bit7 (983~1005) 23 994, Bit15 (975~994) 20 984,
2855 16:35:00.481790
2856 16:35:00.481878 Write Rank0 MR14 =0x14
2857 16:35:00.491828
2858 16:35:00.495164 CH=1, VrefRange= 0, VrefLevel = 20
2859 16:35:00.498514 TX Bit0 (985~1007) 23 996, Bit8 (977~999) 23 988,
2860 16:35:00.501692 TX Bit1 (982~1006) 25 994, Bit9 (977~998) 22 987,
2861 16:35:00.508473 TX Bit2 (980~1004) 25 992, Bit10 (981~1000) 20 990,
2862 16:35:00.511466 TX Bit3 (978~1001) 24 989, Bit11 (982~1001) 20 991,
2863 16:35:00.518318 TX Bit4 (982~1006) 25 994, Bit12 (982~1000) 19 991,
2864 16:35:00.521848 TX Bit5 (984~1006) 23 995, Bit13 (983~1000) 18 991,
2865 16:35:00.524982 TX Bit6 (982~1006) 25 994, Bit14 (981~1000) 20 990,
2866 16:35:00.531514 TX Bit7 (982~1006) 25 994, Bit15 (974~995) 22 984,
2867 16:35:00.531652
2868 16:35:00.531721 Write Rank0 MR14 =0x16
2869 16:35:00.541946
2870 16:35:00.544960 CH=1, VrefRange= 0, VrefLevel = 22
2871 16:35:00.548640 TX Bit0 (984~1007) 24 995, Bit8 (977~999) 23 988,
2872 16:35:00.551653 TX Bit1 (982~1006) 25 994, Bit9 (976~999) 24 987,
2873 16:35:00.558562 TX Bit2 (980~1006) 27 993, Bit10 (981~1001) 21 991,
2874 16:35:00.561850 TX Bit3 (978~1001) 24 989, Bit11 (981~1002) 22 991,
2875 16:35:00.564910 TX Bit4 (982~1007) 26 994, Bit12 (982~1001) 20 991,
2876 16:35:00.571841 TX Bit5 (984~1007) 24 995, Bit13 (983~1001) 19 992,
2877 16:35:00.574993 TX Bit6 (983~1007) 25 995, Bit14 (981~1001) 21 991,
2878 16:35:00.581473 TX Bit7 (982~1006) 25 994, Bit15 (974~995) 22 984,
2879 16:35:00.581599
2880 16:35:00.581690 Write Rank0 MR14 =0x18
2881 16:35:00.591610
2882 16:35:00.595132 CH=1, VrefRange= 0, VrefLevel = 24
2883 16:35:00.598164 TX Bit0 (984~1007) 24 995, Bit8 (977~999) 23 988,
2884 16:35:00.601489 TX Bit1 (982~1006) 25 994, Bit9 (977~999) 23 988,
2885 16:35:00.608395 TX Bit2 (979~1006) 28 992, Bit10 (980~1001) 22 990,
2886 16:35:00.611460 TX Bit3 (978~1002) 25 990, Bit11 (982~1002) 21 992,
2887 16:35:00.618059 TX Bit4 (981~1007) 27 994, Bit12 (981~1001) 21 991,
2888 16:35:00.621719 TX Bit5 (984~1007) 24 995, Bit13 (982~1001) 20 991,
2889 16:35:00.624791 TX Bit6 (982~1007) 26 994, Bit14 (981~1001) 21 991,
2890 16:35:00.631350 TX Bit7 (982~1007) 26 994, Bit15 (974~996) 23 985,
2891 16:35:00.631448
2892 16:35:00.631511 Write Rank0 MR14 =0x1a
2893 16:35:00.642012
2894 16:35:00.644825 CH=1, VrefRange= 0, VrefLevel = 26
2895 16:35:00.648061 TX Bit0 (984~1007) 24 995, Bit8 (976~999) 24 987,
2896 16:35:00.651558 TX Bit1 (981~1007) 27 994, Bit9 (976~999) 24 987,
2897 16:35:00.658371 TX Bit2 (979~1006) 28 992, Bit10 (980~1001) 22 990,
2898 16:35:00.661901 TX Bit3 (978~1002) 25 990, Bit11 (981~1002) 22 991,
2899 16:35:00.668394 TX Bit4 (981~1007) 27 994, Bit12 (981~1002) 22 991,
2900 16:35:00.672030 TX Bit5 (984~1007) 24 995, Bit13 (982~1001) 20 991,
2901 16:35:00.674869 TX Bit6 (981~1007) 27 994, Bit14 (980~1002) 23 991,
2902 16:35:00.681715 TX Bit7 (982~1007) 26 994, Bit15 (973~997) 25 985,
2903 16:35:00.681842
2904 16:35:00.681931 Write Rank0 MR14 =0x1c
2905 16:35:00.692138
2906 16:35:00.692260 CH=1, VrefRange= 0, VrefLevel = 28
2907 16:35:00.698490 TX Bit0 (984~1008) 25 996, Bit8 (976~1000) 25 988,
2908 16:35:00.702095 TX Bit1 (982~1007) 26 994, Bit9 (976~999) 24 987,
2909 16:35:00.708776 TX Bit2 (979~1004) 26 991, Bit10 (979~1002) 24 990,
2910 16:35:00.711707 TX Bit3 (978~1003) 26 990, Bit11 (981~1002) 22 991,
2911 16:35:00.718408 TX Bit4 (982~1007) 26 994, Bit12 (980~1002) 23 991,
2912 16:35:00.722180 TX Bit5 (983~1007) 25 995, Bit13 (982~1002) 21 992,
2913 16:35:00.725486 TX Bit6 (980~1007) 28 993, Bit14 (980~1002) 23 991,
2914 16:35:00.732099 TX Bit7 (981~1007) 27 994, Bit15 (972~998) 27 985,
2915 16:35:00.732220
2916 16:35:00.732308 Write Rank0 MR14 =0x1e
2917 16:35:00.741962
2918 16:35:00.745524 CH=1, VrefRange= 0, VrefLevel = 30
2919 16:35:00.748605 TX Bit0 (983~1008) 26 995, Bit8 (976~1000) 25 988,
2920 16:35:00.752363 TX Bit1 (981~1007) 27 994, Bit9 (975~999) 25 987,
2921 16:35:00.759128 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2922 16:35:00.762141 TX Bit3 (978~1003) 26 990, Bit11 (981~1002) 22 991,
2923 16:35:00.768779 TX Bit4 (982~1007) 26 994, Bit12 (981~1002) 22 991,
2924 16:35:00.771694 TX Bit5 (983~1008) 26 995, Bit13 (981~1002) 22 991,
2925 16:35:00.775354 TX Bit6 (982~1007) 26 994, Bit14 (979~1001) 23 990,
2926 16:35:00.782146 TX Bit7 (981~1007) 27 994, Bit15 (971~997) 27 984,
2927 16:35:00.782277
2928 16:35:00.785079 Write Rank0 MR14 =0x20
2929 16:35:00.792608
2930 16:35:00.796175 CH=1, VrefRange= 0, VrefLevel = 32
2931 16:35:00.799099 TX Bit0 (983~1008) 26 995, Bit8 (976~1000) 25 988,
2932 16:35:00.802536 TX Bit1 (981~1007) 27 994, Bit9 (975~999) 25 987,
2933 16:35:00.808880 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2934 16:35:00.812466 TX Bit3 (978~1003) 26 990, Bit11 (981~1002) 22 991,
2935 16:35:00.819212 TX Bit4 (982~1007) 26 994, Bit12 (981~1002) 22 991,
2936 16:35:00.822045 TX Bit5 (983~1008) 26 995, Bit13 (981~1002) 22 991,
2937 16:35:00.825831 TX Bit6 (982~1007) 26 994, Bit14 (979~1001) 23 990,
2938 16:35:00.832500 TX Bit7 (981~1007) 27 994, Bit15 (971~997) 27 984,
2939 16:35:00.832614
2940 16:35:00.832702 Write Rank0 MR14 =0x22
2941 16:35:00.842676
2942 16:35:00.846169 CH=1, VrefRange= 0, VrefLevel = 34
2943 16:35:00.849187 TX Bit0 (983~1008) 26 995, Bit8 (976~1000) 25 988,
2944 16:35:00.852841 TX Bit1 (981~1007) 27 994, Bit9 (975~999) 25 987,
2945 16:35:00.859514 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2946 16:35:00.862570 TX Bit3 (978~1003) 26 990, Bit11 (981~1002) 22 991,
2947 16:35:00.869306 TX Bit4 (982~1007) 26 994, Bit12 (981~1002) 22 991,
2948 16:35:00.872684 TX Bit5 (983~1008) 26 995, Bit13 (981~1002) 22 991,
2949 16:35:00.876338 TX Bit6 (982~1007) 26 994, Bit14 (979~1001) 23 990,
2950 16:35:00.882318 TX Bit7 (981~1007) 27 994, Bit15 (971~997) 27 984,
2951 16:35:00.882417
2952 16:35:00.882480 Write Rank0 MR14 =0x24
2953 16:35:00.892716
2954 16:35:00.896290 CH=1, VrefRange= 0, VrefLevel = 36
2955 16:35:00.899379 TX Bit0 (983~1008) 26 995, Bit8 (976~1000) 25 988,
2956 16:35:00.902961 TX Bit1 (981~1007) 27 994, Bit9 (975~999) 25 987,
2957 16:35:00.909410 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2958 16:35:00.912507 TX Bit3 (978~1003) 26 990, Bit11 (981~1002) 22 991,
2959 16:35:00.919520 TX Bit4 (982~1007) 26 994, Bit12 (981~1002) 22 991,
2960 16:35:00.922647 TX Bit5 (983~1008) 26 995, Bit13 (981~1002) 22 991,
2961 16:35:00.925820 TX Bit6 (982~1007) 26 994, Bit14 (979~1001) 23 990,
2962 16:35:00.932277 TX Bit7 (981~1007) 27 994, Bit15 (971~997) 27 984,
2963 16:35:00.932412
2964 16:35:00.932506
2965 16:35:00.935579 TX Vref found, early break! 372< 381
2966 16:35:00.939215 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
2967 16:35:00.942528 u1DelayCellOfst[0]=5 cells (5 PI)
2968 16:35:00.945625 u1DelayCellOfst[1]=4 cells (4 PI)
2969 16:35:00.949311 u1DelayCellOfst[2]=2 cells (2 PI)
2970 16:35:00.952172 u1DelayCellOfst[3]=0 cells (0 PI)
2971 16:35:00.956018 u1DelayCellOfst[4]=4 cells (4 PI)
2972 16:35:00.959160 u1DelayCellOfst[5]=5 cells (5 PI)
2973 16:35:00.962188 u1DelayCellOfst[6]=4 cells (4 PI)
2974 16:35:00.965784 u1DelayCellOfst[7]=4 cells (4 PI)
2975 16:35:00.968936 Byte0, DQ PI dly=990, DQM PI dly= 992
2976 16:35:00.972585 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2977 16:35:00.972694
2978 16:35:00.975366 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2979 16:35:00.975476
2980 16:35:00.978846 u1DelayCellOfst[8]=4 cells (4 PI)
2981 16:35:00.982432 u1DelayCellOfst[9]=3 cells (3 PI)
2982 16:35:00.985443 u1DelayCellOfst[10]=6 cells (6 PI)
2983 16:35:00.989081 u1DelayCellOfst[11]=8 cells (7 PI)
2984 16:35:00.992185 u1DelayCellOfst[12]=8 cells (7 PI)
2985 16:35:00.995667 u1DelayCellOfst[13]=8 cells (7 PI)
2986 16:35:00.999275 u1DelayCellOfst[14]=6 cells (6 PI)
2987 16:35:01.002291 u1DelayCellOfst[15]=0 cells (0 PI)
2988 16:35:01.005396 Byte1, DQ PI dly=984, DQM PI dly= 987
2989 16:35:01.008965 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2990 16:35:01.009067
2991 16:35:01.012103 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2992 16:35:01.012178
2993 16:35:01.015852 Write Rank0 MR14 =0x1e
2994 16:35:01.015931
2995 16:35:01.018777 Final TX Range 0 Vref 30
2996 16:35:01.018876
2997 16:35:01.025608 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2998 16:35:01.025732
2999 16:35:01.032151 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3000 16:35:01.038663 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3001 16:35:01.045234 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3002 16:35:01.049034 Write Rank0 MR3 =0xb0
3003 16:35:01.049140 DramC Write-DBI on
3004 16:35:01.049236 ==
3005 16:35:01.055409 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3006 16:35:01.058791 fsp= 1, odt_onoff= 1, Byte mode= 0
3007 16:35:01.058887 ==
3008 16:35:01.062126 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3009 16:35:01.062216
3010 16:35:01.065230 Begin, DQ Scan Range 707~771
3011 16:35:01.065320
3012 16:35:01.065400
3013 16:35:01.068449 TX Vref Scan disable
3014 16:35:01.072176 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3015 16:35:01.075265 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3016 16:35:01.078948 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3017 16:35:01.081679 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3018 16:35:01.085344 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3019 16:35:01.088383 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3020 16:35:01.091948 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3021 16:35:01.095018 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3022 16:35:01.098092 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3023 16:35:01.101735 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3024 16:35:01.104810 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3025 16:35:01.108519 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3026 16:35:01.111666 719 |2 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3027 16:35:01.115391 720 |2 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
3028 16:35:01.118363 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3029 16:35:01.124953 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3030 16:35:01.128096 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3031 16:35:01.131557 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3032 16:35:01.135009 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3033 16:35:01.138005 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3034 16:35:01.145096 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3035 16:35:01.148745 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3036 16:35:01.151690 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3037 16:35:01.155491 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3038 16:35:01.158648 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3039 16:35:01.161937 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3040 16:35:01.165416 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3041 16:35:01.168669 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3042 16:35:01.171633 753 |2 6 49|[0] xxxxxxxx xxxxxxxx [MSB]
3043 16:35:01.174890 Byte0, DQ PI dly=739, DQM PI dly= 739
3044 16:35:01.178299 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 35)
3045 16:35:01.178382
3046 16:35:01.185081 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 35)
3047 16:35:01.185193
3048 16:35:01.188412 Byte1, DQ PI dly=732, DQM PI dly= 732
3049 16:35:01.192097 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
3050 16:35:01.192205
3051 16:35:01.195133 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
3052 16:35:01.195248
3053 16:35:01.201696 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3054 16:35:01.211408 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3055 16:35:01.218121 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3056 16:35:01.218228 Write Rank0 MR3 =0x30
3057 16:35:01.221749 DramC Write-DBI off
3058 16:35:01.221866
3059 16:35:01.221965 [DATLAT]
3060 16:35:01.224759 Freq=1600, CH1 RK0, use_rxtx_scan=0
3061 16:35:01.224864
3062 16:35:01.227851 DATLAT Default: 0xf
3063 16:35:01.227927 7, 0xFFFF, sum=0
3064 16:35:01.231470 8, 0xFFFF, sum=0
3065 16:35:01.231546 9, 0xFFFF, sum=0
3066 16:35:01.235085 10, 0xFFFF, sum=0
3067 16:35:01.235178 11, 0xFFFF, sum=0
3068 16:35:01.238633 12, 0xFFFF, sum=0
3069 16:35:01.238740 13, 0xFFFF, sum=0
3070 16:35:01.238826 14, 0x0, sum=1
3071 16:35:01.241450 15, 0x0, sum=2
3072 16:35:01.241545 16, 0x0, sum=3
3073 16:35:01.244688 17, 0x0, sum=4
3074 16:35:01.247823 pattern=2 first_step=14 total pass=5 best_step=16
3075 16:35:01.247908 ==
3076 16:35:01.254815 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3077 16:35:01.257760 fsp= 1, odt_onoff= 1, Byte mode= 0
3078 16:35:01.257877 ==
3079 16:35:01.261196 Start DQ dly to find pass range UseTestEngine =1
3080 16:35:01.264444 x-axis: bit #, y-axis: DQ dly (-127~63)
3081 16:35:01.267916 RX Vref Scan = 1
3082 16:35:01.381298
3083 16:35:01.381452 RX Vref found, early break!
3084 16:35:01.381550
3085 16:35:01.387957 Final RX Vref 12, apply to both rank0 and 1
3086 16:35:01.388080 ==
3087 16:35:01.391478 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3088 16:35:01.394447 fsp= 1, odt_onoff= 1, Byte mode= 0
3089 16:35:01.394573 ==
3090 16:35:01.394671 DQS Delay:
3091 16:35:01.398056 DQS0 = 0, DQS1 = 0
3092 16:35:01.398179 DQM Delay:
3093 16:35:01.401397 DQM0 = 21, DQM1 = 19
3094 16:35:01.401508 DQ Delay:
3095 16:35:01.404533 DQ0 =23, DQ1 =21, DQ2 =20, DQ3 =19
3096 16:35:01.407892 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =23
3097 16:35:01.411171 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3098 16:35:01.414722 DQ12 =22, DQ13 =22, DQ14 =21, DQ15 =16
3099 16:35:01.414855
3100 16:35:01.414956
3101 16:35:01.415047
3102 16:35:01.417834 [DramC_TX_OE_Calibration] TA2
3103 16:35:01.420904 Original DQ_B0 (3 6) =30, OEN = 27
3104 16:35:01.424468 Original DQ_B1 (3 6) =30, OEN = 27
3105 16:35:01.427496 23, 0x0, End_B0=23 End_B1=23
3106 16:35:01.427593 24, 0x0, End_B0=24 End_B1=24
3107 16:35:01.431204 25, 0x0, End_B0=25 End_B1=25
3108 16:35:01.434222 26, 0x0, End_B0=26 End_B1=26
3109 16:35:01.437923 27, 0x0, End_B0=27 End_B1=27
3110 16:35:01.440854 28, 0x0, End_B0=28 End_B1=28
3111 16:35:01.440980 29, 0x0, End_B0=29 End_B1=29
3112 16:35:01.444463 30, 0x0, End_B0=30 End_B1=30
3113 16:35:01.447437 31, 0xFFFF, End_B0=30 End_B1=30
3114 16:35:01.454206 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3115 16:35:01.457276 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3116 16:35:01.457389
3117 16:35:01.457477
3118 16:35:01.461033 Write Rank0 MR23 =0x3f
3119 16:35:01.461112 [DQSOSC]
3120 16:35:01.470691 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3121 16:35:01.477361 CH1_RK0: MR19=0x202, MR18=0xBFBF, DQSOSC=448, MR23=63, INC=12, DEC=18
3122 16:35:01.477468 Write Rank0 MR23 =0x3f
3123 16:35:01.477533 [DQSOSC]
3124 16:35:01.487446 [DQSOSCAuto] RK0, (LSB)MR18= 0xbebe, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3125 16:35:01.491092 CH1 RK0: MR19=202, MR18=BEBE
3126 16:35:01.494073 [RankSwap] Rank num 2, (Multi 1), Rank 1
3127 16:35:01.494189 Write Rank0 MR2 =0xad
3128 16:35:01.497339 [Write Leveling]
3129 16:35:01.500612 delay byte0 byte1 byte2 byte3
3130 16:35:01.500698
3131 16:35:01.500763 10 0 0
3132 16:35:01.504382 11 0 0
3133 16:35:01.504462 12 0 0
3134 16:35:01.504524 13 0 0
3135 16:35:01.507902 14 0 0
3136 16:35:01.507987 15 0 0
3137 16:35:01.510689 16 0 0
3138 16:35:01.510786 17 0 0
3139 16:35:01.510848 18 0 0
3140 16:35:01.514123 19 0 0
3141 16:35:01.514242 20 0 0
3142 16:35:01.517341 21 0 0
3143 16:35:01.517444 22 0 0
3144 16:35:01.520684 23 0 0
3145 16:35:01.520820 24 0 0
3146 16:35:01.520932 25 0 0
3147 16:35:01.523923 26 0 0
3148 16:35:01.524030 27 0 0
3149 16:35:01.527572 28 0 0
3150 16:35:01.527696 29 0 0
3151 16:35:01.527796 30 0 0
3152 16:35:01.530487 31 0 0
3153 16:35:01.530598 32 0 0
3154 16:35:01.534006 33 0 ff
3155 16:35:01.534116 34 0 ff
3156 16:35:01.537662 35 0 ff
3157 16:35:01.537769 36 0 ff
3158 16:35:01.540668 37 ff ff
3159 16:35:01.540747 38 0 ff
3160 16:35:01.540808 39 ff ff
3161 16:35:01.544287 40 ff ff
3162 16:35:01.544403 41 ff ff
3163 16:35:01.547392 42 ff ff
3164 16:35:01.547502 43 ff ff
3165 16:35:01.550373 44 ff ff
3166 16:35:01.550484 45 ff ff
3167 16:35:01.554044 pass bytecount = 0xff (0xff: all bytes pass)
3168 16:35:01.557288
3169 16:35:01.557413 DQS0 dly: 39
3170 16:35:01.557509 DQS1 dly: 33
3171 16:35:01.560820 Write Rank0 MR2 =0x2d
3172 16:35:01.563851 [RankSwap] Rank num 2, (Multi 1), Rank 0
3173 16:35:01.566967 Write Rank1 MR1 =0xd6
3174 16:35:01.567082 [Gating]
3175 16:35:01.567173 ==
3176 16:35:01.570480 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3177 16:35:01.573926 fsp= 1, odt_onoff= 1, Byte mode= 0
3178 16:35:01.574058 ==
3179 16:35:01.580482 3 1 0 |3534 2828 |(11 11)(11 11) |(0 0)(0 0)| 0
3180 16:35:01.583950 3 1 4 |3534 2f2e |(11 11)(11 11) |(1 1)(0 0)| 0
3181 16:35:01.586923 3 1 8 |3534 2f2f |(11 11)(11 11) |(1 1)(1 1)| 0
3182 16:35:01.593897 3 1 12 |3534 302f |(11 11)(11 11) |(1 1)(1 0)| 0
3183 16:35:01.596993 3 1 16 |3534 1312 |(11 11)(11 11) |(0 1)(1 1)| 0
3184 16:35:01.600474 3 1 20 |3534 2d2d |(11 11)(0 0) |(0 1)(1 1)| 0
3185 16:35:01.603551 3 1 24 |3534 303 |(11 11)(11 11) |(0 1)(1 0)| 0
3186 16:35:01.610333 3 1 28 |3534 2a2a |(11 11)(11 11) |(0 1)(1 0)| 0
3187 16:35:01.613661 3 2 0 |3534 2d2c |(11 11)(11 11) |(0 1)(0 1)| 0
3188 16:35:01.617322 3 2 4 |3534 1111 |(11 11)(11 11) |(0 1)(0 1)| 0
3189 16:35:01.623822 3 2 8 |3534 2e2d |(11 11)(11 11) |(0 1)(0 1)| 0
3190 16:35:01.627091 3 2 12 |1110 2c2c |(11 11)(11 11) |(1 1)(0 1)| 0
3191 16:35:01.630098 3 2 16 |3d3d 2f2f |(11 11)(11 11) |(1 1)(1 0)| 0
3192 16:35:01.636803 3 2 20 |3d3d 1616 |(11 11)(11 11) |(1 1)(1 1)| 0
3193 16:35:01.640535 3 2 24 |3d3d 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
3194 16:35:01.643439 3 2 28 |3d3d 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
3195 16:35:01.650729 3 3 0 |3d3d 1414 |(11 11)(1 1) |(1 1)(1 1)| 0
3196 16:35:01.653789 [Byte 1] Lead/lag Transition tap number (1)
3197 16:35:01.656902 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3198 16:35:01.660235 3 3 8 |3d3d 3636 |(11 11)(0 0) |(1 1)(0 0)| 0
3199 16:35:01.666746 3 3 12 |1717 3535 |(11 11)(0 0) |(1 1)(1 1)| 0
3200 16:35:01.669944 3 3 16 |0 e0e |(11 11)(11 11) |(1 1)(1 1)| 0
3201 16:35:01.673637 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3202 16:35:01.677089 [Byte 0] Lead/lag falling Transition (3, 3, 20)
3203 16:35:01.683550 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3204 16:35:01.687068 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3205 16:35:01.690112 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3206 16:35:01.696899 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3207 16:35:01.700141 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3208 16:35:01.703454 3 4 12 |707 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3209 16:35:01.710056 3 4 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3210 16:35:01.713396 3 4 20 |3d3d 1413 |(11 11)(11 11) |(1 1)(1 1)| 0
3211 16:35:01.716906 3 4 24 |3d3d 707 |(11 11)(11 11) |(1 1)(1 1)| 0
3212 16:35:01.720031 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3213 16:35:01.727026 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3214 16:35:01.730276 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3215 16:35:01.733435 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3216 16:35:01.740044 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3217 16:35:01.742962 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3218 16:35:01.746630 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3219 16:35:01.753464 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3220 16:35:01.756351 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3221 16:35:01.760057 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3222 16:35:01.766275 [Byte 0] Lead/lag falling Transition (3, 6, 0)
3223 16:35:01.769603 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3224 16:35:01.773175 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3225 16:35:01.776237 [Byte 0] Lead/lag Transition tap number (3)
3226 16:35:01.783285 [Byte 1] Lead/lag falling Transition (3, 6, 8)
3227 16:35:01.786275 3 6 12 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3228 16:35:01.789773 [Byte 1] Lead/lag Transition tap number (2)
3229 16:35:01.793281 3 6 16 |4646 3d3d |(0 0)(11 11) |(0 0)(0 0)| 0
3230 16:35:01.796178 [Byte 0]First pass (3, 6, 16)
3231 16:35:01.799858 3 6 20 |4646 909 |(0 0)(11 11) |(0 0)(0 0)| 0
3232 16:35:01.806350 3 6 24 |4646 1c1c |(0 0)(1 1) |(0 0)(0 0)| 0
3233 16:35:01.809534 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3234 16:35:01.813314 [Byte 1]First pass (3, 6, 28)
3235 16:35:01.816209 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3236 16:35:01.819506 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3237 16:35:01.823125 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3238 16:35:01.826192 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3239 16:35:01.832729 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3240 16:35:01.836403 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3241 16:35:01.839381 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3242 16:35:01.842610 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3243 16:35:01.845847 All bytes gating window > 1UI, Early break!
3244 16:35:01.845964
3245 16:35:01.852661 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
3246 16:35:01.852761
3247 16:35:01.856261 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12)
3248 16:35:01.856355
3249 16:35:01.856445
3250 16:35:01.856535
3251 16:35:01.859503 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
3252 16:35:01.859583
3253 16:35:01.862598 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3254 16:35:01.862692
3255 16:35:01.862776
3256 16:35:01.866075 Write Rank1 MR1 =0x56
3257 16:35:01.866180
3258 16:35:01.869198 best RODT dly(2T, 0.5T) = (2, 3)
3259 16:35:01.869282
3260 16:35:01.873005 best RODT dly(2T, 0.5T) = (2, 3)
3261 16:35:01.873120 ==
3262 16:35:01.875920 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3263 16:35:01.879515 fsp= 1, odt_onoff= 1, Byte mode= 0
3264 16:35:01.879636 ==
3265 16:35:01.886183 Start DQ dly to find pass range UseTestEngine =0
3266 16:35:01.889316 x-axis: bit #, y-axis: DQ dly (-127~63)
3267 16:35:01.889403 RX Vref Scan = 0
3268 16:35:01.892856 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3269 16:35:01.895791 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3270 16:35:01.899314 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3271 16:35:01.902943 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3272 16:35:01.906132 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3273 16:35:01.906224 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3274 16:35:01.908999 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3275 16:35:01.912709 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3276 16:35:01.916234 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3277 16:35:01.919582 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3278 16:35:01.922785 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3279 16:35:01.925870 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3280 16:35:01.928989 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3281 16:35:01.932528 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3282 16:35:01.932651 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3283 16:35:01.936115 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3284 16:35:01.939099 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3285 16:35:01.942766 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3286 16:35:01.945769 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3287 16:35:01.949306 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3288 16:35:01.952611 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3289 16:35:01.952722 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3290 16:35:01.955691 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3291 16:35:01.958785 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3292 16:35:01.962303 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3293 16:35:01.966038 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3294 16:35:01.969089 0, [0] xxxxxxxx xxxxxxxo [MSB]
3295 16:35:01.972198 1, [0] xxxxxxxx xoxxxxxo [MSB]
3296 16:35:01.972322 2, [0] xxxoxxxx ooxxxxxo [MSB]
3297 16:35:01.975820 3, [0] xxxoxxxx ooxxxxxo [MSB]
3298 16:35:01.978993 4, [0] xxooxxxx oooxxxxo [MSB]
3299 16:35:01.982385 5, [0] xxooxxxx oooxoxxo [MSB]
3300 16:35:01.985570 6, [0] xxoooxxx oooooooo [MSB]
3301 16:35:01.989126 7, [0] oooooxxo oooooooo [MSB]
3302 16:35:01.989219 8, [0] ooooooxo oooooooo [MSB]
3303 16:35:01.992429 31, [0] oooooooo ooooooox [MSB]
3304 16:35:01.995353 32, [0] oooooooo ooooooox [MSB]
3305 16:35:01.998964 33, [0] oooooooo ooooooox [MSB]
3306 16:35:02.002022 34, [0] oooooooo oxooooox [MSB]
3307 16:35:02.005514 35, [0] oooooooo xxooooox [MSB]
3308 16:35:02.008898 36, [0] ooxxoooo xxooooox [MSB]
3309 16:35:02.009021 37, [0] ooxxoooo xxooooox [MSB]
3310 16:35:02.012567 38, [0] ooxxxooo xxxoooox [MSB]
3311 16:35:02.015498 39, [0] ooxxxoox xxxxxxxx [MSB]
3312 16:35:02.018802 40, [0] oxxxxoox xxxxxxxx [MSB]
3313 16:35:02.022278 41, [0] xxxxxxox xxxxxxxx [MSB]
3314 16:35:02.025287 42, [0] xxxxxxxx xxxxxxxx [MSB]
3315 16:35:02.028621 iDelay=42, Bit 0, Center 23 (7 ~ 40) 34
3316 16:35:02.032042 iDelay=42, Bit 1, Center 23 (7 ~ 39) 33
3317 16:35:02.035282 iDelay=42, Bit 2, Center 19 (4 ~ 35) 32
3318 16:35:02.038542 iDelay=42, Bit 3, Center 18 (2 ~ 35) 34
3319 16:35:02.041955 iDelay=42, Bit 4, Center 21 (6 ~ 37) 32
3320 16:35:02.045387 iDelay=42, Bit 5, Center 24 (8 ~ 40) 33
3321 16:35:02.048528 iDelay=42, Bit 6, Center 25 (9 ~ 41) 33
3322 16:35:02.051905 iDelay=42, Bit 7, Center 22 (7 ~ 38) 32
3323 16:35:02.055091 iDelay=42, Bit 8, Center 18 (2 ~ 34) 33
3324 16:35:02.058742 iDelay=42, Bit 9, Center 17 (1 ~ 33) 33
3325 16:35:02.062135 iDelay=42, Bit 10, Center 20 (4 ~ 37) 34
3326 16:35:02.065355 iDelay=42, Bit 11, Center 22 (6 ~ 38) 33
3327 16:35:02.071713 iDelay=42, Bit 12, Center 21 (5 ~ 38) 34
3328 16:35:02.075414 iDelay=42, Bit 13, Center 22 (6 ~ 38) 33
3329 16:35:02.078496 iDelay=42, Bit 14, Center 22 (6 ~ 38) 33
3330 16:35:02.082043 iDelay=42, Bit 15, Center 15 (0 ~ 30) 31
3331 16:35:02.082144 ==
3332 16:35:02.085067 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3333 16:35:02.088710 fsp= 1, odt_onoff= 1, Byte mode= 0
3334 16:35:02.088838 ==
3335 16:35:02.091839 DQS Delay:
3336 16:35:02.091968 DQS0 = 0, DQS1 = 0
3337 16:35:02.095144 DQM Delay:
3338 16:35:02.095269 DQM0 = 21, DQM1 = 19
3339 16:35:02.095378 DQ Delay:
3340 16:35:02.098745 DQ0 =23, DQ1 =23, DQ2 =19, DQ3 =18
3341 16:35:02.102085 DQ4 =21, DQ5 =24, DQ6 =25, DQ7 =22
3342 16:35:02.105313 DQ8 =18, DQ9 =17, DQ10 =20, DQ11 =22
3343 16:35:02.108981 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =15
3344 16:35:02.109064
3345 16:35:02.109129
3346 16:35:02.111882 DramC Write-DBI off
3347 16:35:02.111954 ==
3348 16:35:02.118873 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3349 16:35:02.118981 fsp= 1, odt_onoff= 1, Byte mode= 0
3350 16:35:02.121851 ==
3351 16:35:02.125670 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3352 16:35:02.125778
3353 16:35:02.128702 Begin, DQ Scan Range 929~1185
3354 16:35:02.128782
3355 16:35:02.128843
3356 16:35:02.128903 TX Vref Scan disable
3357 16:35:02.132309 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3358 16:35:02.138725 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3359 16:35:02.142034 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3360 16:35:02.145445 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3361 16:35:02.148424 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3362 16:35:02.152330 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3363 16:35:02.154962 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3364 16:35:02.158713 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3365 16:35:02.162189 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3366 16:35:02.165241 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3367 16:35:02.168696 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3368 16:35:02.171707 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3369 16:35:02.175227 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3370 16:35:02.178301 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3371 16:35:02.181432 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3372 16:35:02.184671 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3373 16:35:02.188332 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3374 16:35:02.195154 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3375 16:35:02.198201 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3376 16:35:02.201772 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3377 16:35:02.205173 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3378 16:35:02.208235 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3379 16:35:02.211771 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3380 16:35:02.214781 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3381 16:35:02.218477 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3382 16:35:02.221297 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3383 16:35:02.224689 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3384 16:35:02.228382 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3385 16:35:02.231330 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3386 16:35:02.234910 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3387 16:35:02.238447 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3388 16:35:02.241374 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3389 16:35:02.247876 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3390 16:35:02.251646 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3391 16:35:02.254515 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3392 16:35:02.257823 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3393 16:35:02.261253 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3394 16:35:02.264469 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3395 16:35:02.268096 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3396 16:35:02.271175 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3397 16:35:02.274705 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3398 16:35:02.277605 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3399 16:35:02.281396 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3400 16:35:02.284958 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3401 16:35:02.287682 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3402 16:35:02.291180 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3403 16:35:02.294421 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3404 16:35:02.298157 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
3405 16:35:02.301209 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
3406 16:35:02.304275 978 |3 6 18|[0] xxxxxxxx ooxxxxxo [MSB]
3407 16:35:02.308062 979 |3 6 19|[0] xxxxxxxx ooxxxxxo [MSB]
3408 16:35:02.311768 980 |3 6 20|[0] xxxxxxxx ooxxxxxo [MSB]
3409 16:35:02.317950 981 |3 6 21|[0] xxxxxxxx oooxxxoo [MSB]
3410 16:35:02.321545 982 |3 6 22|[0] xxxxxxxx ooooxxoo [MSB]
3411 16:35:02.324629 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3412 16:35:02.328051 984 |3 6 24|[0] xxoooxox oooooooo [MSB]
3413 16:35:02.330963 985 |3 6 25|[0] xooooooo oooooooo [MSB]
3414 16:35:02.334685 995 |3 6 35|[0] oooooooo ooooooox [MSB]
3415 16:35:02.337619 996 |3 6 36|[0] oooooooo ooooooox [MSB]
3416 16:35:02.341222 997 |3 6 37|[0] oooooooo oxooooox [MSB]
3417 16:35:02.344318 998 |3 6 38|[0] oooooooo xxooooox [MSB]
3418 16:35:02.351315 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3419 16:35:02.354376 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
3420 16:35:02.357940 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
3421 16:35:02.361022 1002 |3 6 42|[0] oooooooo xxxxxxxx [MSB]
3422 16:35:02.364608 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
3423 16:35:02.368092 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
3424 16:35:02.370827 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
3425 16:35:02.374373 1006 |3 6 46|[0] ooxxoooo xxxxxxxx [MSB]
3426 16:35:02.377840 1007 |3 6 47|[0] oxxxxxxx xxxxxxxx [MSB]
3427 16:35:02.381225 1008 |3 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3428 16:35:02.384485 Byte0, DQ PI dly=994, DQM PI dly= 994
3429 16:35:02.391055 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 34)
3430 16:35:02.391154
3431 16:35:02.394594 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 34)
3432 16:35:02.394714
3433 16:35:02.397553 Byte1, DQ PI dly=988, DQM PI dly= 988
3434 16:35:02.401130 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3435 16:35:02.401247
3436 16:35:02.407676 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3437 16:35:02.407797
3438 16:35:02.407891 ==
3439 16:35:02.411033 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3440 16:35:02.414160 fsp= 1, odt_onoff= 1, Byte mode= 0
3441 16:35:02.414269 ==
3442 16:35:02.420967 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3443 16:35:02.421087
3444 16:35:02.424117 Begin, DQ Scan Range 964~1028
3445 16:35:02.424233 Write Rank1 MR14 =0x0
3446 16:35:02.432676
3447 16:35:02.432797 CH=1, VrefRange= 0, VrefLevel = 0
3448 16:35:02.439245 TX Bit0 (988~1001) 14 994, Bit8 (981~992) 12 986,
3449 16:35:02.442656 TX Bit1 (987~1000) 14 993, Bit9 (982~992) 11 987,
3450 16:35:02.449385 TX Bit2 (985~999) 15 992, Bit10 (984~995) 12 989,
3451 16:35:02.452362 TX Bit3 (983~996) 14 989, Bit11 (984~997) 14 990,
3452 16:35:02.455854 TX Bit4 (986~1002) 17 994, Bit12 (984~995) 12 989,
3453 16:35:02.462329 TX Bit5 (988~1000) 13 994, Bit13 (985~994) 10 989,
3454 16:35:02.465644 TX Bit6 (986~1000) 15 993, Bit14 (984~995) 12 989,
3455 16:35:02.472551 TX Bit7 (987~1001) 15 994, Bit15 (977~990) 14 983,
3456 16:35:02.472691
3457 16:35:02.472784 Write Rank1 MR14 =0x2
3458 16:35:02.480907
3459 16:35:02.481046 CH=1, VrefRange= 0, VrefLevel = 2
3460 16:35:02.487602 TX Bit0 (988~1003) 16 995, Bit8 (980~993) 14 986,
3461 16:35:02.491398 TX Bit1 (987~1001) 15 994, Bit9 (981~992) 12 986,
3462 16:35:02.497831 TX Bit2 (985~1000) 16 992, Bit10 (983~995) 13 989,
3463 16:35:02.500758 TX Bit3 (983~997) 15 990, Bit11 (984~998) 15 991,
3464 16:35:02.504493 TX Bit4 (985~1002) 18 993, Bit12 (984~996) 13 990,
3465 16:35:02.511030 TX Bit5 (988~1001) 14 994, Bit13 (985~995) 11 990,
3466 16:35:02.514517 TX Bit6 (986~1001) 16 993, Bit14 (984~996) 13 990,
3467 16:35:02.520699 TX Bit7 (986~1002) 17 994, Bit15 (977~990) 14 983,
3468 16:35:02.520849
3469 16:35:02.520950 Write Rank1 MR14 =0x4
3470 16:35:02.530190
3471 16:35:02.530356 CH=1, VrefRange= 0, VrefLevel = 4
3472 16:35:02.536517 TX Bit0 (988~1003) 16 995, Bit8 (979~993) 15 986,
3473 16:35:02.540034 TX Bit1 (986~1002) 17 994, Bit9 (981~993) 13 987,
3474 16:35:02.546510 TX Bit2 (984~1000) 17 992, Bit10 (983~997) 15 990,
3475 16:35:02.549431 TX Bit3 (983~998) 16 990, Bit11 (984~999) 16 991,
3476 16:35:02.553154 TX Bit4 (985~1003) 19 994, Bit12 (984~998) 15 991,
3477 16:35:02.559533 TX Bit5 (987~1002) 16 994, Bit13 (984~997) 14 990,
3478 16:35:02.562902 TX Bit6 (986~1002) 17 994, Bit14 (984~997) 14 990,
3479 16:35:02.569141 TX Bit7 (986~1002) 17 994, Bit15 (976~991) 16 983,
3480 16:35:02.569240
3481 16:35:02.569303 Write Rank1 MR14 =0x6
3482 16:35:02.578730
3483 16:35:02.578844 CH=1, VrefRange= 0, VrefLevel = 6
3484 16:35:02.585209 TX Bit0 (987~1004) 18 995, Bit8 (980~994) 15 987,
3485 16:35:02.588739 TX Bit1 (986~1003) 18 994, Bit9 (980~993) 14 986,
3486 16:35:02.595528 TX Bit2 (984~1001) 18 992, Bit10 (982~998) 17 990,
3487 16:35:02.598475 TX Bit3 (982~999) 18 990, Bit11 (984~999) 16 991,
3488 16:35:02.602052 TX Bit4 (985~1004) 20 994, Bit12 (984~998) 15 991,
3489 16:35:02.608452 TX Bit5 (986~1003) 18 994, Bit13 (984~998) 15 991,
3490 16:35:02.612082 TX Bit6 (986~1003) 18 994, Bit14 (984~998) 15 991,
3491 16:35:02.618584 TX Bit7 (986~1003) 18 994, Bit15 (976~992) 17 984,
3492 16:35:02.618681
3493 16:35:02.618743 Write Rank1 MR14 =0x8
3494 16:35:02.627871
3495 16:35:02.628009 CH=1, VrefRange= 0, VrefLevel = 8
3496 16:35:02.634334 TX Bit0 (987~1005) 19 996, Bit8 (979~994) 16 986,
3497 16:35:02.637876 TX Bit1 (986~1003) 18 994, Bit9 (979~994) 16 986,
3498 16:35:02.644758 TX Bit2 (984~1002) 19 993, Bit10 (982~998) 17 990,
3499 16:35:02.647769 TX Bit3 (982~999) 18 990, Bit11 (983~999) 17 991,
3500 16:35:02.651187 TX Bit4 (985~1004) 20 994, Bit12 (984~999) 16 991,
3501 16:35:02.657726 TX Bit5 (986~1005) 20 995, Bit13 (984~998) 15 991,
3502 16:35:02.661215 TX Bit6 (985~1003) 19 994, Bit14 (983~999) 17 991,
3503 16:35:02.667849 TX Bit7 (986~1004) 19 995, Bit15 (976~992) 17 984,
3504 16:35:02.667973
3505 16:35:02.668060 Write Rank1 MR14 =0xa
3506 16:35:02.676842
3507 16:35:02.680436 CH=1, VrefRange= 0, VrefLevel = 10
3508 16:35:02.684075 TX Bit0 (986~1006) 21 996, Bit8 (978~995) 18 986,
3509 16:35:02.686901 TX Bit1 (986~1004) 19 995, Bit9 (979~994) 16 986,
3510 16:35:02.694006 TX Bit2 (984~1002) 19 993, Bit10 (982~999) 18 990,
3511 16:35:02.696850 TX Bit3 (981~1000) 20 990, Bit11 (983~1000) 18 991,
3512 16:35:02.700368 TX Bit4 (985~1005) 21 995, Bit12 (983~999) 17 991,
3513 16:35:02.707484 TX Bit5 (986~1005) 20 995, Bit13 (984~999) 16 991,
3514 16:35:02.710462 TX Bit6 (985~1004) 20 994, Bit14 (983~999) 17 991,
3515 16:35:02.717135 TX Bit7 (986~1004) 19 995, Bit15 (975~993) 19 984,
3516 16:35:02.717251
3517 16:35:02.717346 Write Rank1 MR14 =0xc
3518 16:35:02.726466
3519 16:35:02.729816 CH=1, VrefRange= 0, VrefLevel = 12
3520 16:35:02.732988 TX Bit0 (986~1006) 21 996, Bit8 (978~995) 18 986,
3521 16:35:02.736529 TX Bit1 (985~1005) 21 995, Bit9 (978~994) 17 986,
3522 16:35:02.743204 TX Bit2 (984~1003) 20 993, Bit10 (982~999) 18 990,
3523 16:35:02.746246 TX Bit3 (981~1001) 21 991, Bit11 (983~1000) 18 991,
3524 16:35:02.753268 TX Bit4 (984~1006) 23 995, Bit12 (983~999) 17 991,
3525 16:35:02.756519 TX Bit5 (986~1006) 21 996, Bit13 (984~999) 16 991,
3526 16:35:02.759710 TX Bit6 (985~1005) 21 995, Bit14 (982~999) 18 990,
3527 16:35:02.766227 TX Bit7 (985~1005) 21 995, Bit15 (975~993) 19 984,
3528 16:35:02.766346
3529 16:35:02.766437 Write Rank1 MR14 =0xe
3530 16:35:02.775920
3531 16:35:02.779594 CH=1, VrefRange= 0, VrefLevel = 14
3532 16:35:02.782439 TX Bit0 (986~1006) 21 996, Bit8 (977~996) 20 986,
3533 16:35:02.786062 TX Bit1 (985~1005) 21 995, Bit9 (978~995) 18 986,
3534 16:35:02.792722 TX Bit2 (983~1004) 22 993, Bit10 (981~999) 19 990,
3535 16:35:02.795782 TX Bit3 (981~1001) 21 991, Bit11 (982~1000) 19 991,
3536 16:35:02.802318 TX Bit4 (984~1006) 23 995, Bit12 (983~999) 17 991,
3537 16:35:02.805880 TX Bit5 (986~1006) 21 996, Bit13 (983~1000) 18 991,
3538 16:35:02.809306 TX Bit6 (985~1006) 22 995, Bit14 (982~999) 18 990,
3539 16:35:02.815849 TX Bit7 (985~1006) 22 995, Bit15 (975~994) 20 984,
3540 16:35:02.815945
3541 16:35:02.816008 Write Rank1 MR14 =0x10
3542 16:35:02.825697
3543 16:35:02.829056 CH=1, VrefRange= 0, VrefLevel = 16
3544 16:35:02.832723 TX Bit0 (986~1007) 22 996, Bit8 (977~997) 21 987,
3545 16:35:02.835704 TX Bit1 (985~1006) 22 995, Bit9 (978~996) 19 987,
3546 16:35:02.842314 TX Bit2 (982~1005) 24 993, Bit10 (981~999) 19 990,
3547 16:35:02.845512 TX Bit3 (980~1002) 23 991, Bit11 (982~1001) 20 991,
3548 16:35:02.852516 TX Bit4 (984~1006) 23 995, Bit12 (982~1000) 19 991,
3549 16:35:02.855768 TX Bit5 (985~1006) 22 995, Bit13 (983~1000) 18 991,
3550 16:35:02.859280 TX Bit6 (985~1006) 22 995, Bit14 (981~1000) 20 990,
3551 16:35:02.865560 TX Bit7 (985~1006) 22 995, Bit15 (974~994) 21 984,
3552 16:35:02.865689
3553 16:35:02.865764 Write Rank1 MR14 =0x12
3554 16:35:02.876265
3555 16:35:02.879131 CH=1, VrefRange= 0, VrefLevel = 18
3556 16:35:02.882564 TX Bit0 (986~1007) 22 996, Bit8 (977~997) 21 987,
3557 16:35:02.886156 TX Bit1 (985~1006) 22 995, Bit9 (978~997) 20 987,
3558 16:35:02.892224 TX Bit2 (982~1005) 24 993, Bit10 (980~1000) 21 990,
3559 16:35:02.895636 TX Bit3 (980~1002) 23 991, Bit11 (982~1001) 20 991,
3560 16:35:02.902251 TX Bit4 (984~1006) 23 995, Bit12 (982~1000) 19 991,
3561 16:35:02.905875 TX Bit5 (985~1006) 22 995, Bit13 (983~1000) 18 991,
3562 16:35:02.908827 TX Bit6 (984~1006) 23 995, Bit14 (982~1000) 19 991,
3563 16:35:02.915779 TX Bit7 (985~1006) 22 995, Bit15 (974~995) 22 984,
3564 16:35:02.915898
3565 16:35:02.915965 Write Rank1 MR14 =0x14
3566 16:35:02.925734
3567 16:35:02.929509 CH=1, VrefRange= 0, VrefLevel = 20
3568 16:35:02.932495 TX Bit0 (986~1007) 22 996, Bit8 (977~998) 22 987,
3569 16:35:02.936222 TX Bit1 (985~1006) 22 995, Bit9 (977~998) 22 987,
3570 16:35:02.942476 TX Bit2 (982~1006) 25 994, Bit10 (980~1000) 21 990,
3571 16:35:02.946050 TX Bit3 (979~1003) 25 991, Bit11 (981~1001) 21 991,
3572 16:35:02.952735 TX Bit4 (983~1007) 25 995, Bit12 (982~1000) 19 991,
3573 16:35:02.955939 TX Bit5 (985~1007) 23 996, Bit13 (982~1001) 20 991,
3574 16:35:02.959281 TX Bit6 (984~1007) 24 995, Bit14 (981~1000) 20 990,
3575 16:35:02.966133 TX Bit7 (985~1006) 22 995, Bit15 (973~995) 23 984,
3576 16:35:02.966232
3577 16:35:02.966305 Write Rank1 MR14 =0x16
3578 16:35:02.975909
3579 16:35:02.979425 CH=1, VrefRange= 0, VrefLevel = 22
3580 16:35:02.982681 TX Bit0 (985~1007) 23 996, Bit8 (976~998) 23 987,
3581 16:35:02.986525 TX Bit1 (985~1007) 23 996, Bit9 (977~998) 22 987,
3582 16:35:02.992619 TX Bit2 (982~1006) 25 994, Bit10 (979~1001) 23 990,
3583 16:35:02.995901 TX Bit3 (979~1004) 26 991, Bit11 (981~1002) 22 991,
3584 16:35:03.002745 TX Bit4 (983~1007) 25 995, Bit12 (982~1001) 20 991,
3585 16:35:03.006127 TX Bit5 (985~1007) 23 996, Bit13 (982~1001) 20 991,
3586 16:35:03.009307 TX Bit6 (984~1007) 24 995, Bit14 (981~1001) 21 991,
3587 16:35:03.015911 TX Bit7 (984~1007) 24 995, Bit15 (973~996) 24 984,
3588 16:35:03.016009
3589 16:35:03.016077 Write Rank1 MR14 =0x18
3590 16:35:03.026418
3591 16:35:03.029347 CH=1, VrefRange= 0, VrefLevel = 24
3592 16:35:03.032927 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3593 16:35:03.035974 TX Bit1 (984~1007) 24 995, Bit9 (976~998) 23 987,
3594 16:35:03.042597 TX Bit2 (982~1006) 25 994, Bit10 (979~1001) 23 990,
3595 16:35:03.046343 TX Bit3 (979~1004) 26 991, Bit11 (981~1002) 22 991,
3596 16:35:03.052556 TX Bit4 (983~1007) 25 995, Bit12 (981~1001) 21 991,
3597 16:35:03.056009 TX Bit5 (984~1007) 24 995, Bit13 (982~1002) 21 992,
3598 16:35:03.059732 TX Bit6 (984~1007) 24 995, Bit14 (980~1001) 22 990,
3599 16:35:03.066207 TX Bit7 (984~1007) 24 995, Bit15 (973~997) 25 985,
3600 16:35:03.066303
3601 16:35:03.069093 Write Rank1 MR14 =0x1a
3602 16:35:03.076451
3603 16:35:03.079613 CH=1, VrefRange= 0, VrefLevel = 26
3604 16:35:03.083321 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3605 16:35:03.086375 TX Bit1 (984~1007) 24 995, Bit9 (976~999) 24 987,
3606 16:35:03.093059 TX Bit2 (981~1006) 26 993, Bit10 (979~1001) 23 990,
3607 16:35:03.096406 TX Bit3 (979~1005) 27 992, Bit11 (980~1002) 23 991,
3608 16:35:03.102808 TX Bit4 (984~1007) 24 995, Bit12 (981~1002) 22 991,
3609 16:35:03.106453 TX Bit5 (984~1007) 24 995, Bit13 (982~1002) 21 992,
3610 16:35:03.109877 TX Bit6 (983~1007) 25 995, Bit14 (979~1001) 23 990,
3611 16:35:03.116287 TX Bit7 (984~1007) 24 995, Bit15 (972~998) 27 985,
3612 16:35:03.116391
3613 16:35:03.116456 Write Rank1 MR14 =0x1c
3614 16:35:03.126920
3615 16:35:03.129913 CH=1, VrefRange= 0, VrefLevel = 28
3616 16:35:03.133605 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3617 16:35:03.136544 TX Bit1 (984~1007) 24 995, Bit9 (976~999) 24 987,
3618 16:35:03.143261 TX Bit2 (981~1006) 26 993, Bit10 (979~1002) 24 990,
3619 16:35:03.146861 TX Bit3 (979~1005) 27 992, Bit11 (979~1002) 24 990,
3620 16:35:03.153481 TX Bit4 (984~1007) 24 995, Bit12 (981~1002) 22 991,
3621 16:35:03.156769 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
3622 16:35:03.159826 TX Bit6 (983~1007) 25 995, Bit14 (979~1001) 23 990,
3623 16:35:03.167094 TX Bit7 (984~1007) 24 995, Bit15 (971~998) 28 984,
3624 16:35:03.167192
3625 16:35:03.167256 Write Rank1 MR14 =0x1e
3626 16:35:03.177385
3627 16:35:03.180277 CH=1, VrefRange= 0, VrefLevel = 30
3628 16:35:03.183644 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3629 16:35:03.186744 TX Bit1 (983~1007) 25 995, Bit9 (976~999) 24 987,
3630 16:35:03.193555 TX Bit2 (980~1007) 28 993, Bit10 (978~1001) 24 989,
3631 16:35:03.196748 TX Bit3 (979~1005) 27 992, Bit11 (979~1001) 23 990,
3632 16:35:03.203676 TX Bit4 (984~1008) 25 996, Bit12 (980~1002) 23 991,
3633 16:35:03.206783 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
3634 16:35:03.210072 TX Bit6 (983~1007) 25 995, Bit14 (978~1001) 24 989,
3635 16:35:03.217079 TX Bit7 (983~1007) 25 995, Bit15 (971~997) 27 984,
3636 16:35:03.217218
3637 16:35:03.217318 Write Rank1 MR14 =0x20
3638 16:35:03.227110
3639 16:35:03.230378 CH=1, VrefRange= 0, VrefLevel = 32
3640 16:35:03.234219 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3641 16:35:03.237135 TX Bit1 (983~1007) 25 995, Bit9 (976~999) 24 987,
3642 16:35:03.244175 TX Bit2 (980~1007) 28 993, Bit10 (978~1001) 24 989,
3643 16:35:03.247698 TX Bit3 (979~1005) 27 992, Bit11 (979~1001) 23 990,
3644 16:35:03.253896 TX Bit4 (984~1008) 25 996, Bit12 (980~1002) 23 991,
3645 16:35:03.257319 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
3646 16:35:03.260504 TX Bit6 (983~1007) 25 995, Bit14 (978~1001) 24 989,
3647 16:35:03.267132 TX Bit7 (983~1007) 25 995, Bit15 (971~997) 27 984,
3648 16:35:03.267259
3649 16:35:03.267354 Write Rank1 MR14 =0x22
3650 16:35:03.277520
3651 16:35:03.281190 CH=1, VrefRange= 0, VrefLevel = 34
3652 16:35:03.284214 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3653 16:35:03.287448 TX Bit1 (983~1007) 25 995, Bit9 (976~999) 24 987,
3654 16:35:03.294232 TX Bit2 (980~1007) 28 993, Bit10 (978~1001) 24 989,
3655 16:35:03.297508 TX Bit3 (979~1005) 27 992, Bit11 (979~1001) 23 990,
3656 16:35:03.304025 TX Bit4 (984~1008) 25 996, Bit12 (980~1002) 23 991,
3657 16:35:03.307509 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
3658 16:35:03.310462 TX Bit6 (983~1007) 25 995, Bit14 (978~1001) 24 989,
3659 16:35:03.316932 TX Bit7 (983~1007) 25 995, Bit15 (971~997) 27 984,
3660 16:35:03.317064
3661 16:35:03.320281 Write Rank1 MR14 =0x24
3662 16:35:03.327653
3663 16:35:03.331201 CH=1, VrefRange= 0, VrefLevel = 36
3664 16:35:03.334351 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3665 16:35:03.337829 TX Bit1 (983~1007) 25 995, Bit9 (976~999) 24 987,
3666 16:35:03.344717 TX Bit2 (980~1007) 28 993, Bit10 (978~1001) 24 989,
3667 16:35:03.347920 TX Bit3 (979~1005) 27 992, Bit11 (979~1001) 23 990,
3668 16:35:03.351016 TX Bit4 (984~1008) 25 996, Bit12 (980~1002) 23 991,
3669 16:35:03.357654 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
3670 16:35:03.361349 TX Bit6 (983~1007) 25 995, Bit14 (978~1001) 24 989,
3671 16:35:03.368068 TX Bit7 (983~1007) 25 995, Bit15 (971~997) 27 984,
3672 16:35:03.368196
3673 16:35:03.368293 Write Rank1 MR14 =0x26
3674 16:35:03.377756
3675 16:35:03.381277 CH=1, VrefRange= 0, VrefLevel = 38
3676 16:35:03.384442 TX Bit0 (985~1008) 24 996, Bit8 (976~999) 24 987,
3677 16:35:03.388048 TX Bit1 (983~1007) 25 995, Bit9 (976~999) 24 987,
3678 16:35:03.394767 TX Bit2 (980~1007) 28 993, Bit10 (978~1001) 24 989,
3679 16:35:03.397812 TX Bit3 (979~1005) 27 992, Bit11 (979~1001) 23 990,
3680 16:35:03.404327 TX Bit4 (984~1008) 25 996, Bit12 (980~1002) 23 991,
3681 16:35:03.407890 TX Bit5 (984~1008) 25 996, Bit13 (981~1002) 22 991,
3682 16:35:03.410968 TX Bit6 (983~1007) 25 995, Bit14 (978~1001) 24 989,
3683 16:35:03.418013 TX Bit7 (983~1007) 25 995, Bit15 (971~997) 27 984,
3684 16:35:03.418155
3685 16:35:03.418252
3686 16:35:03.421014 TX Vref found, early break! 369< 375
3687 16:35:03.424427 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
3688 16:35:03.427932 u1DelayCellOfst[0]=4 cells (4 PI)
3689 16:35:03.431013 u1DelayCellOfst[1]=3 cells (3 PI)
3690 16:35:03.434444 u1DelayCellOfst[2]=1 cells (1 PI)
3691 16:35:03.437746 u1DelayCellOfst[3]=0 cells (0 PI)
3692 16:35:03.441322 u1DelayCellOfst[4]=4 cells (4 PI)
3693 16:35:03.444296 u1DelayCellOfst[5]=4 cells (4 PI)
3694 16:35:03.447909 u1DelayCellOfst[6]=3 cells (3 PI)
3695 16:35:03.450920 u1DelayCellOfst[7]=3 cells (3 PI)
3696 16:35:03.454409 Byte0, DQ PI dly=992, DQM PI dly= 994
3697 16:35:03.457735 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
3698 16:35:03.457853
3699 16:35:03.461000 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
3700 16:35:03.461109
3701 16:35:03.464401 u1DelayCellOfst[8]=3 cells (3 PI)
3702 16:35:03.467741 u1DelayCellOfst[9]=3 cells (3 PI)
3703 16:35:03.471004 u1DelayCellOfst[10]=5 cells (5 PI)
3704 16:35:03.474689 u1DelayCellOfst[11]=6 cells (6 PI)
3705 16:35:03.477819 u1DelayCellOfst[12]=8 cells (7 PI)
3706 16:35:03.480742 u1DelayCellOfst[13]=8 cells (7 PI)
3707 16:35:03.484406 u1DelayCellOfst[14]=5 cells (5 PI)
3708 16:35:03.488092 u1DelayCellOfst[15]=0 cells (0 PI)
3709 16:35:03.491095 Byte1, DQ PI dly=984, DQM PI dly= 987
3710 16:35:03.494131 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
3711 16:35:03.494243
3712 16:35:03.497731 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
3713 16:35:03.497841
3714 16:35:03.500827 Write Rank1 MR14 =0x1e
3715 16:35:03.500934
3716 16:35:03.504353 Final TX Range 0 Vref 30
3717 16:35:03.504464
3718 16:35:03.511118 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3719 16:35:03.511256
3720 16:35:03.517711 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3721 16:35:03.524568 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3722 16:35:03.531208 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3723 16:35:03.531361 Write Rank1 MR3 =0xb0
3724 16:35:03.534892 DramC Write-DBI on
3725 16:35:03.535012 ==
3726 16:35:03.540810 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3727 16:35:03.544443 fsp= 1, odt_onoff= 1, Byte mode= 0
3728 16:35:03.544571 ==
3729 16:35:03.547817 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3730 16:35:03.547932
3731 16:35:03.550694 Begin, DQ Scan Range 707~771
3732 16:35:03.550805
3733 16:35:03.550899
3734 16:35:03.550992 TX Vref Scan disable
3735 16:35:03.554522 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3736 16:35:03.560730 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3737 16:35:03.564196 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3738 16:35:03.567588 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3739 16:35:03.570513 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3740 16:35:03.573946 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3741 16:35:03.577387 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3742 16:35:03.580696 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3743 16:35:03.584197 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3744 16:35:03.587457 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3745 16:35:03.590927 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3746 16:35:03.593891 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3747 16:35:03.596973 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3748 16:35:03.600478 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3749 16:35:03.604161 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3750 16:35:03.607173 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3751 16:35:03.610417 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3752 16:35:03.613903 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3753 16:35:03.620627 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3754 16:35:03.623781 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3755 16:35:03.627357 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3756 16:35:03.633803 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3757 16:35:03.636904 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3758 16:35:03.639923 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3759 16:35:03.643427 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3760 16:35:03.646877 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3761 16:35:03.650471 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3762 16:35:03.653313 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3763 16:35:03.656857 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3764 16:35:03.660070 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
3765 16:35:03.663448 754 |2 6 50|[0] xxxxxxxx xxxxxxxx [MSB]
3766 16:35:03.666372 Byte0, DQ PI dly=740, DQM PI dly= 740
3767 16:35:03.673096 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 36)
3768 16:35:03.673230
3769 16:35:03.676660 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 36)
3770 16:35:03.676781
3771 16:35:03.679734 Byte1, DQ PI dly=731, DQM PI dly= 731
3772 16:35:03.683174 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
3773 16:35:03.683287
3774 16:35:03.689991 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
3775 16:35:03.690116
3776 16:35:03.696391 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3777 16:35:03.702895 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3778 16:35:03.709638 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3779 16:35:03.709766 Write Rank1 MR3 =0x30
3780 16:35:03.713313 DramC Write-DBI off
3781 16:35:03.713421
3782 16:35:03.713512 [DATLAT]
3783 16:35:03.716313 Freq=1600, CH1 RK1, use_rxtx_scan=0
3784 16:35:03.716420
3785 16:35:03.719973 DATLAT Default: 0x10
3786 16:35:03.720079 7, 0xFFFF, sum=0
3787 16:35:03.723077 8, 0xFFFF, sum=0
3788 16:35:03.723185 9, 0xFFFF, sum=0
3789 16:35:03.726107 10, 0xFFFF, sum=0
3790 16:35:03.726218 11, 0xFFFF, sum=0
3791 16:35:03.729769 12, 0xFFFF, sum=0
3792 16:35:03.729879 13, 0xFFFF, sum=0
3793 16:35:03.732857 14, 0x0, sum=1
3794 16:35:03.732974 15, 0x0, sum=2
3795 16:35:03.733068 16, 0x0, sum=3
3796 16:35:03.736538 17, 0x0, sum=4
3797 16:35:03.739702 pattern=2 first_step=14 total pass=5 best_step=16
3798 16:35:03.739811 ==
3799 16:35:03.746517 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3800 16:35:03.749702 fsp= 1, odt_onoff= 1, Byte mode= 0
3801 16:35:03.749817 ==
3802 16:35:03.752971 Start DQ dly to find pass range UseTestEngine =1
3803 16:35:03.756129 x-axis: bit #, y-axis: DQ dly (-127~63)
3804 16:35:03.759677 RX Vref Scan = 0
3805 16:35:03.762844 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3806 16:35:03.762963 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3807 16:35:03.766402 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3808 16:35:03.769578 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3809 16:35:03.772704 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3810 16:35:03.776002 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3811 16:35:03.779218 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3812 16:35:03.782810 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3813 16:35:03.786027 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3814 16:35:03.789031 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3815 16:35:03.789144 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3816 16:35:03.792647 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3817 16:35:03.795564 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3818 16:35:03.798707 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3819 16:35:03.802162 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3820 16:35:03.805281 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3821 16:35:03.808900 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3822 16:35:03.812093 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3823 16:35:03.815663 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3824 16:35:03.815772 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3825 16:35:03.818666 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3826 16:35:03.822358 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3827 16:35:03.825491 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3828 16:35:03.828940 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3829 16:35:03.831954 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3830 16:35:03.835403 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3831 16:35:03.835520 0, [0] xxxxxxxx xxxxxxxx [MSB]
3832 16:35:03.838438 1, [0] xxxxxxxx xxxxxxxo [MSB]
3833 16:35:03.841997 2, [0] xxxxxxxx xoxxxxxo [MSB]
3834 16:35:03.845156 3, [0] xxxoxxxx ooxxxxxo [MSB]
3835 16:35:03.848646 4, [0] xxooxxxx ooxxxxxo [MSB]
3836 16:35:03.851705 5, [0] xxoooxxx ooxxxxxo [MSB]
3837 16:35:03.851819 6, [0] xxoooxxx oooxxxxo [MSB]
3838 16:35:03.855412 7, [0] oooooxxx oooooooo [MSB]
3839 16:35:03.858778 8, [0] ooooooxo oooooooo [MSB]
3840 16:35:03.862243 30, [0] oooooooo ooooooox [MSB]
3841 16:35:03.865471 31, [0] oooooooo ooooooox [MSB]
3842 16:35:03.868663 32, [0] oooooooo ooooooox [MSB]
3843 16:35:03.872150 33, [0] oooooooo oxooooox [MSB]
3844 16:35:03.875530 34, [0] oooooooo xxooooox [MSB]
3845 16:35:03.878323 35, [0] oooxoooo xxooooox [MSB]
3846 16:35:03.881875 36, [0] ooxxoooo xxooooox [MSB]
3847 16:35:03.881992 37, [0] ooxxooox xxooxoxx [MSB]
3848 16:35:03.885144 38, [0] oxxxxoox xxxxxxxx [MSB]
3849 16:35:03.888497 39, [0] xxxxxoox xxxxxxxx [MSB]
3850 16:35:03.891671 40, [0] xxxxxxox xxxxxxxx [MSB]
3851 16:35:03.895413 41, [0] xxxxxxxx xxxxxxxx [MSB]
3852 16:35:03.898462 iDelay=41, Bit 0, Center 22 (7 ~ 38) 32
3853 16:35:03.901868 iDelay=41, Bit 1, Center 22 (7 ~ 37) 31
3854 16:35:03.905063 iDelay=41, Bit 2, Center 19 (4 ~ 35) 32
3855 16:35:03.908298 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
3856 16:35:03.911776 iDelay=41, Bit 4, Center 21 (5 ~ 37) 33
3857 16:35:03.914799 iDelay=41, Bit 5, Center 23 (8 ~ 39) 32
3858 16:35:03.918411 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
3859 16:35:03.921996 iDelay=41, Bit 7, Center 22 (8 ~ 36) 29
3860 16:35:03.925106 iDelay=41, Bit 8, Center 18 (3 ~ 33) 31
3861 16:35:03.928646 iDelay=41, Bit 9, Center 17 (2 ~ 32) 31
3862 16:35:03.934821 iDelay=41, Bit 10, Center 21 (6 ~ 37) 32
3863 16:35:03.938355 iDelay=41, Bit 11, Center 22 (7 ~ 37) 31
3864 16:35:03.941411 iDelay=41, Bit 12, Center 21 (7 ~ 36) 30
3865 16:35:03.945013 iDelay=41, Bit 13, Center 22 (7 ~ 37) 31
3866 16:35:03.948050 iDelay=41, Bit 14, Center 21 (7 ~ 36) 30
3867 16:35:03.951851 iDelay=41, Bit 15, Center 15 (1 ~ 29) 29
3868 16:35:03.951961 ==
3869 16:35:03.958544 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3870 16:35:03.958657 fsp= 1, odt_onoff= 1, Byte mode= 0
3871 16:35:03.961262 ==
3872 16:35:03.961361 DQS Delay:
3873 16:35:03.961445 DQS0 = 0, DQS1 = 0
3874 16:35:03.964879 DQM Delay:
3875 16:35:03.964956 DQM0 = 21, DQM1 = 19
3876 16:35:03.968562 DQ Delay:
3877 16:35:03.971438 DQ0 =22, DQ1 =22, DQ2 =19, DQ3 =18
3878 16:35:03.971537 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3879 16:35:03.975109 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3880 16:35:03.978363 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =15
3881 16:35:03.981767
3882 16:35:03.981873
3883 16:35:03.981961
3884 16:35:03.982065 [DramC_TX_OE_Calibration] TA2
3885 16:35:03.984725 Original DQ_B0 (3 6) =30, OEN = 27
3886 16:35:03.988555 Original DQ_B1 (3 6) =30, OEN = 27
3887 16:35:03.991831 23, 0x0, End_B0=23 End_B1=23
3888 16:35:03.994780 24, 0x0, End_B0=24 End_B1=24
3889 16:35:03.998158 25, 0x0, End_B0=25 End_B1=25
3890 16:35:03.998239 26, 0x0, End_B0=26 End_B1=26
3891 16:35:04.001681 27, 0x0, End_B0=27 End_B1=27
3892 16:35:04.004763 28, 0x0, End_B0=28 End_B1=28
3893 16:35:04.008066 29, 0x0, End_B0=29 End_B1=29
3894 16:35:04.008144 30, 0x0, End_B0=30 End_B1=30
3895 16:35:04.011639 31, 0xFFFF, End_B0=30 End_B1=30
3896 16:35:04.017963 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3897 16:35:04.024960 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3898 16:35:04.025090
3899 16:35:04.025177
3900 16:35:04.025243 Write Rank1 MR23 =0x3f
3901 16:35:04.028350 [DQSOSC]
3902 16:35:04.034417 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
3903 16:35:04.041064 CH1_RK1: MR19=0x202, MR18=0xD8D8, DQSOSC=432, MR23=63, INC=13, DEC=19
3904 16:35:04.044832 Write Rank1 MR23 =0x3f
3905 16:35:04.044913 [DQSOSC]
3906 16:35:04.051416 [DQSOSCAuto] RK1, (LSB)MR18= 0xd7d7, (MSB)MR19= 0x202, tDQSOscB0 = 433 ps tDQSOscB1 = 433 ps
3907 16:35:04.054472 CH1 RK1: MR19=202, MR18=D7D7
3908 16:35:04.058098 [RxdqsGatingPostProcess] freq 1600
3909 16:35:04.064848 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3910 16:35:04.064967 Rank: 0
3911 16:35:04.067769 best DQS0 dly(2T, 0.5T) = (2, 6)
3912 16:35:04.070869 best DQS1 dly(2T, 0.5T) = (2, 6)
3913 16:35:04.074628 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3914 16:35:04.077682 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3915 16:35:04.077784 Rank: 1
3916 16:35:04.081214 best DQS0 dly(2T, 0.5T) = (2, 6)
3917 16:35:04.084794 best DQS1 dly(2T, 0.5T) = (2, 6)
3918 16:35:04.087467 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3919 16:35:04.091259 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3920 16:35:04.094271 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3921 16:35:04.097963 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3922 16:35:04.100902 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3923 16:35:04.100989
3924 16:35:04.104317
3925 16:35:04.104398 [Calibration Summary] Freqency 1600
3926 16:35:04.107767 CH 0, Rank 0
3927 16:35:04.107848 All Pass.
3928 16:35:04.107945
3929 16:35:04.111159 CH 0, Rank 1
3930 16:35:04.111267 All Pass.
3931 16:35:04.111355
3932 16:35:04.111439 CH 1, Rank 0
3933 16:35:04.111520 All Pass.
3934 16:35:04.114143
3935 16:35:04.114215 CH 1, Rank 1
3936 16:35:04.114273 All Pass.
3937 16:35:04.114328
3938 16:35:04.121015 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3939 16:35:04.127758 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3940 16:35:04.134479 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3941 16:35:04.137570 Write Rank0 MR3 =0xb0
3942 16:35:04.144184 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3943 16:35:04.151405 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3944 16:35:04.157441 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3945 16:35:04.161050 Write Rank1 MR3 =0xb0
3946 16:35:04.167733 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3947 16:35:04.174224 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3948 16:35:04.180940 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3949 16:35:04.184136 Write Rank0 MR3 =0xb0
3950 16:35:04.187696 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3951 16:35:04.197385 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3952 16:35:04.204073 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3953 16:35:04.204179 Write Rank1 MR3 =0xb0
3954 16:35:04.207387 DramC Write-DBI on
3955 16:35:04.211184 [GetDramInforAfterCalByMRR] Vendor 6.
3956 16:35:04.213906 [GetDramInforAfterCalByMRR] Revision 505.
3957 16:35:04.214016 MR8 1111
3958 16:35:04.220927 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3959 16:35:04.221061 MR8 1111
3960 16:35:04.223924 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3961 16:35:04.227258 MR8 1111
3962 16:35:04.230581 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3963 16:35:04.230705 MR8 1111
3964 16:35:04.237839 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3965 16:35:04.247412 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3966 16:35:04.247549 Write Rank0 MR13 =0xd0
3967 16:35:04.250439 Write Rank1 MR13 =0xd0
3968 16:35:04.250551 Write Rank0 MR13 =0xd0
3969 16:35:04.253961 Write Rank1 MR13 =0xd0
3970 16:35:04.257583 Save calibration result to emmc
3971 16:35:04.257692
3972 16:35:04.257783
3973 16:35:04.260612 [DramcModeReg_Check] Freq_1600, FSP_1
3974 16:35:04.260716 FSP_1, CH_0, RK0
3975 16:35:04.264187 Write Rank0 MR13 =0xd8
3976 16:35:04.267417 MR12 = 0x60 (global = 0x60) match
3977 16:35:04.271089 MR14 = 0x1e (global = 0x1e) match
3978 16:35:04.271199 FSP_1, CH_0, RK1
3979 16:35:04.273762 Write Rank1 MR13 =0xd8
3980 16:35:04.277387 MR12 = 0x5e (global = 0x5e) match
3981 16:35:04.280448 MR14 = 0x1e (global = 0x1e) match
3982 16:35:04.280556 FSP_1, CH_1, RK0
3983 16:35:04.284097 Write Rank0 MR13 =0xd8
3984 16:35:04.287045 MR12 = 0x60 (global = 0x60) match
3985 16:35:04.290655 MR14 = 0x1e (global = 0x1e) match
3986 16:35:04.290765 FSP_1, CH_1, RK1
3987 16:35:04.293777 Write Rank1 MR13 =0xd8
3988 16:35:04.297374 MR12 = 0x60 (global = 0x60) match
3989 16:35:04.300423 MR14 = 0x1e (global = 0x1e) match
3990 16:35:04.300530
3991 16:35:04.304039 [MEM_TEST] 02: After DFS, before run time config
3992 16:35:04.315631 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3993 16:35:04.315771
3994 16:35:04.315864 [TA2_TEST]
3995 16:35:04.315954 === TA2 HW
3996 16:35:04.318885 TA2 PAT: XTALK
3997 16:35:04.322497 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3998 16:35:04.329182 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3999 16:35:04.332481 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
4000 16:35:04.338681 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
4001 16:35:04.338778
4002 16:35:04.338842
4003 16:35:04.338899 Settings after calibration
4004 16:35:04.338955
4005 16:35:04.342529 [DramcRunTimeConfig]
4006 16:35:04.345695 TransferPLLToSPMControl - MODE SW PHYPLL
4007 16:35:04.348717 TX_TRACKING: ON
4008 16:35:04.348832 RX_TRACKING: ON
4009 16:35:04.348923 HW_GATING: ON
4010 16:35:04.351915 HW_GATING DBG: OFF
4011 16:35:04.351999 ddr_geometry:1
4012 16:35:04.355313 ddr_geometry:1
4013 16:35:04.355390 ddr_geometry:1
4014 16:35:04.358620 ddr_geometry:1
4015 16:35:04.358693 ddr_geometry:1
4016 16:35:04.358752 ddr_geometry:1
4017 16:35:04.362344 ddr_geometry:1
4018 16:35:04.362450 ddr_geometry:1
4019 16:35:04.365326 High Freq DUMMY_READ_FOR_TRACKING: ON
4020 16:35:04.369161 ZQCS_ENABLE_LP4: OFF
4021 16:35:04.372179 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4022 16:35:04.375304 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4023 16:35:04.375385 SPM_CONTROL_AFTERK: ON
4024 16:35:04.379006 IMPEDANCE_TRACKING: ON
4025 16:35:04.379117 TEMP_SENSOR: ON
4026 16:35:04.381894 PER_BANK_REFRESH: ON
4027 16:35:04.382013 HW_SAVE_FOR_SR: ON
4028 16:35:04.385716 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4029 16:35:04.388671 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4030 16:35:04.391920 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4031 16:35:04.395558 Read ODT Tracking: ON
4032 16:35:04.398547 =========================
4033 16:35:04.398658
4034 16:35:04.398748 [TA2_TEST]
4035 16:35:04.398839 === TA2 HW
4036 16:35:04.405156 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4037 16:35:04.408839 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4038 16:35:04.415477 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4039 16:35:04.418555 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4040 16:35:04.418669
4041 16:35:04.421762 [MEM_TEST] 03: After run time config
4042 16:35:04.433863 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4043 16:35:04.436884 [complex_mem_test] start addr:0x40024000, len:131072
4044 16:35:04.641655 1st complex R/W mem test pass
4045 16:35:04.648206 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4046 16:35:04.651279 sync preloader write leveling
4047 16:35:04.654744 sync preloader cbt_mr12
4048 16:35:04.658370 sync preloader cbt_clk_dly
4049 16:35:04.658481 sync preloader cbt_cmd_dly
4050 16:35:04.661147 sync preloader cbt_cs
4051 16:35:04.665091 sync preloader cbt_ca_perbit_delay
4052 16:35:04.665202 sync preloader clk_delay
4053 16:35:04.668146 sync preloader dqs_delay
4054 16:35:04.671445 sync preloader u1Gating2T_Save
4055 16:35:04.674805 sync preloader u1Gating05T_Save
4056 16:35:04.678175 sync preloader u1Gatingfine_tune_Save
4057 16:35:04.681367 sync preloader u1Gatingucpass_count_Save
4058 16:35:04.684497 sync preloader u1TxWindowPerbitVref_Save
4059 16:35:04.687937 sync preloader u1TxCenter_min_Save
4060 16:35:04.691570 sync preloader u1TxCenter_max_Save
4061 16:35:04.694494 sync preloader u1Txwin_center_Save
4062 16:35:04.698058 sync preloader u1Txfirst_pass_Save
4063 16:35:04.701150 sync preloader u1Txlast_pass_Save
4064 16:35:04.701235 sync preloader u1RxDatlat_Save
4065 16:35:04.704611 sync preloader u1RxWinPerbitVref_Save
4066 16:35:04.711397 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4067 16:35:04.714419 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4068 16:35:04.718181 sync preloader delay_cell_unit
4069 16:35:04.724807 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4070 16:35:04.728001 sync preloader write leveling
4071 16:35:04.728133 sync preloader cbt_mr12
4072 16:35:04.731458 sync preloader cbt_clk_dly
4073 16:35:04.734440 sync preloader cbt_cmd_dly
4074 16:35:04.734558 sync preloader cbt_cs
4075 16:35:04.738186 sync preloader cbt_ca_perbit_delay
4076 16:35:04.741087 sync preloader clk_delay
4077 16:35:04.744929 sync preloader dqs_delay
4078 16:35:04.745033 sync preloader u1Gating2T_Save
4079 16:35:04.747767 sync preloader u1Gating05T_Save
4080 16:35:04.751517 sync preloader u1Gatingfine_tune_Save
4081 16:35:04.754667 sync preloader u1Gatingucpass_count_Save
4082 16:35:04.757971 sync preloader u1TxWindowPerbitVref_Save
4083 16:35:04.761127 sync preloader u1TxCenter_min_Save
4084 16:35:04.764356 sync preloader u1TxCenter_max_Save
4085 16:35:04.767884 sync preloader u1Txwin_center_Save
4086 16:35:04.770823 sync preloader u1Txfirst_pass_Save
4087 16:35:04.774380 sync preloader u1Txlast_pass_Save
4088 16:35:04.777723 sync preloader u1RxDatlat_Save
4089 16:35:04.781058 sync preloader u1RxWinPerbitVref_Save
4090 16:35:04.784396 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4091 16:35:04.787669 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4092 16:35:04.791205 sync preloader delay_cell_unit
4093 16:35:04.797664 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4094 16:35:04.801436 sync preloader write leveling
4095 16:35:04.804583 sync preloader cbt_mr12
4096 16:35:04.804703 sync preloader cbt_clk_dly
4097 16:35:04.807454 sync preloader cbt_cmd_dly
4098 16:35:04.810971 sync preloader cbt_cs
4099 16:35:04.814412 sync preloader cbt_ca_perbit_delay
4100 16:35:04.814516 sync preloader clk_delay
4101 16:35:04.817600 sync preloader dqs_delay
4102 16:35:04.820718 sync preloader u1Gating2T_Save
4103 16:35:04.824267 sync preloader u1Gating05T_Save
4104 16:35:04.827906 sync preloader u1Gatingfine_tune_Save
4105 16:35:04.830923 sync preloader u1Gatingucpass_count_Save
4106 16:35:04.834508 sync preloader u1TxWindowPerbitVref_Save
4107 16:35:04.837433 sync preloader u1TxCenter_min_Save
4108 16:35:04.840687 sync preloader u1TxCenter_max_Save
4109 16:35:04.844167 sync preloader u1Txwin_center_Save
4110 16:35:04.847955 sync preloader u1Txfirst_pass_Save
4111 16:35:04.850922 sync preloader u1Txlast_pass_Save
4112 16:35:04.851027 sync preloader u1RxDatlat_Save
4113 16:35:04.854586 sync preloader u1RxWinPerbitVref_Save
4114 16:35:04.861170 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4115 16:35:04.864856 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4116 16:35:04.867473 sync preloader delay_cell_unit
4117 16:35:04.871024 just_for_test_dump_coreboot_params dump all params
4118 16:35:04.874342 dump source = 0x0
4119 16:35:04.874450 dump params frequency:1600
4120 16:35:04.877533 dump params rank number:2
4121 16:35:04.877638
4122 16:35:04.880870 dump params write leveling
4123 16:35:04.884289 write leveling[0][0][0] = 0x20
4124 16:35:04.884378 write leveling[0][0][1] = 0x18
4125 16:35:04.887548 write leveling[0][1][0] = 0x20
4126 16:35:04.890676 write leveling[0][1][1] = 0x17
4127 16:35:04.894640 write leveling[1][0][0] = 0x22
4128 16:35:04.897745 write leveling[1][0][1] = 0x20
4129 16:35:04.901070 write leveling[1][1][0] = 0x27
4130 16:35:04.901181 write leveling[1][1][1] = 0x21
4131 16:35:04.904222 dump params cbt_cs
4132 16:35:04.904329 cbt_cs[0][0] = 0x8
4133 16:35:04.907232 cbt_cs[0][1] = 0x8
4134 16:35:04.910936 cbt_cs[1][0] = 0xb
4135 16:35:04.911044 cbt_cs[1][1] = 0xb
4136 16:35:04.914413 dump params cbt_mr12
4137 16:35:04.914518 cbt_mr12[0][0] = 0x20
4138 16:35:04.917289 cbt_mr12[0][1] = 0x1e
4139 16:35:04.917397 cbt_mr12[1][0] = 0x20
4140 16:35:04.920891 cbt_mr12[1][1] = 0x20
4141 16:35:04.923768 dump params tx window
4142 16:35:04.923874 tx_center_min[0][0][0] = 985
4143 16:35:04.927583 tx_center_max[0][0][0] = 992
4144 16:35:04.930854 tx_center_min[0][0][1] = 978
4145 16:35:04.933857 tx_center_max[0][0][1] = 985
4146 16:35:04.936920 tx_center_min[0][1][0] = 986
4147 16:35:04.937003 tx_center_max[0][1][0] = 992
4148 16:35:04.940612 tx_center_min[0][1][1] = 977
4149 16:35:04.943818 tx_center_max[0][1][1] = 984
4150 16:35:04.947356 tx_center_min[1][0][0] = 990
4151 16:35:04.950507 tx_center_max[1][0][0] = 995
4152 16:35:04.950589 tx_center_min[1][0][1] = 984
4153 16:35:04.953456 tx_center_max[1][0][1] = 991
4154 16:35:04.957023 tx_center_min[1][1][0] = 992
4155 16:35:04.960088 tx_center_max[1][1][0] = 996
4156 16:35:04.963688 tx_center_min[1][1][1] = 984
4157 16:35:04.963797 tx_center_max[1][1][1] = 991
4158 16:35:04.966878 dump params tx window
4159 16:35:04.970405 tx_win_center[0][0][0] = 992
4160 16:35:04.973574 tx_first_pass[0][0][0] = 980
4161 16:35:04.973655 tx_last_pass[0][0][0] = 1004
4162 16:35:04.976922 tx_win_center[0][0][1] = 990
4163 16:35:04.980400 tx_first_pass[0][0][1] = 979
4164 16:35:04.983289 tx_last_pass[0][0][1] = 1002
4165 16:35:04.983418 tx_win_center[0][0][2] = 991
4166 16:35:04.987036 tx_first_pass[0][0][2] = 979
4167 16:35:04.990227 tx_last_pass[0][0][2] = 1003
4168 16:35:04.993446 tx_win_center[0][0][3] = 985
4169 16:35:04.996826 tx_first_pass[0][0][3] = 975
4170 16:35:04.996907 tx_last_pass[0][0][3] = 996
4171 16:35:05.000193 tx_win_center[0][0][4] = 990
4172 16:35:05.003198 tx_first_pass[0][0][4] = 979
4173 16:35:05.006834 tx_last_pass[0][0][4] = 1002
4174 16:35:05.010109 tx_win_center[0][0][5] = 988
4175 16:35:05.010196 tx_first_pass[0][0][5] = 978
4176 16:35:05.013241 tx_last_pass[0][0][5] = 999
4177 16:35:05.016540 tx_win_center[0][0][6] = 989
4178 16:35:05.019498 tx_first_pass[0][0][6] = 978
4179 16:35:05.023019 tx_last_pass[0][0][6] = 1000
4180 16:35:05.023103 tx_win_center[0][0][7] = 990
4181 16:35:05.026737 tx_first_pass[0][0][7] = 979
4182 16:35:05.029634 tx_last_pass[0][0][7] = 1002
4183 16:35:05.033197 tx_win_center[0][0][8] = 978
4184 16:35:05.033288 tx_first_pass[0][0][8] = 967
4185 16:35:05.036606 tx_last_pass[0][0][8] = 989
4186 16:35:05.039887 tx_win_center[0][0][9] = 979
4187 16:35:05.042837 tx_first_pass[0][0][9] = 968
4188 16:35:05.046310 tx_last_pass[0][0][9] = 990
4189 16:35:05.046393 tx_win_center[0][0][10] = 984
4190 16:35:05.049361 tx_first_pass[0][0][10] = 972
4191 16:35:05.052982 tx_last_pass[0][0][10] = 997
4192 16:35:05.055990 tx_win_center[0][0][11] = 978
4193 16:35:05.059232 tx_first_pass[0][0][11] = 967
4194 16:35:05.059312 tx_last_pass[0][0][11] = 990
4195 16:35:05.062875 tx_win_center[0][0][12] = 979
4196 16:35:05.065746 tx_first_pass[0][0][12] = 968
4197 16:35:05.069395 tx_last_pass[0][0][12] = 991
4198 16:35:05.072633 tx_win_center[0][0][13] = 979
4199 16:35:05.072742 tx_first_pass[0][0][13] = 968
4200 16:35:05.076210 tx_last_pass[0][0][13] = 991
4201 16:35:05.079071 tx_win_center[0][0][14] = 981
4202 16:35:05.082603 tx_first_pass[0][0][14] = 969
4203 16:35:05.085773 tx_last_pass[0][0][14] = 993
4204 16:35:05.089285 tx_win_center[0][0][15] = 985
4205 16:35:05.089367 tx_first_pass[0][0][15] = 973
4206 16:35:05.092279 tx_last_pass[0][0][15] = 997
4207 16:35:05.095571 tx_win_center[0][1][0] = 992
4208 16:35:05.098933 tx_first_pass[0][1][0] = 980
4209 16:35:05.099015 tx_last_pass[0][1][0] = 1005
4210 16:35:05.102271 tx_win_center[0][1][1] = 990
4211 16:35:05.105524 tx_first_pass[0][1][1] = 979
4212 16:35:05.108962 tx_last_pass[0][1][1] = 1002
4213 16:35:05.112287 tx_win_center[0][1][2] = 992
4214 16:35:05.112368 tx_first_pass[0][1][2] = 980
4215 16:35:05.115537 tx_last_pass[0][1][2] = 1004
4216 16:35:05.119029 tx_win_center[0][1][3] = 986
4217 16:35:05.122353 tx_first_pass[0][1][3] = 976
4218 16:35:05.125508 tx_last_pass[0][1][3] = 996
4219 16:35:05.125622 tx_win_center[0][1][4] = 991
4220 16:35:05.129001 tx_first_pass[0][1][4] = 979
4221 16:35:05.132464 tx_last_pass[0][1][4] = 1003
4222 16:35:05.135478 tx_win_center[0][1][5] = 988
4223 16:35:05.138994 tx_first_pass[0][1][5] = 978
4224 16:35:05.139102 tx_last_pass[0][1][5] = 999
4225 16:35:05.142229 tx_win_center[0][1][6] = 989
4226 16:35:05.145613 tx_first_pass[0][1][6] = 978
4227 16:35:05.149199 tx_last_pass[0][1][6] = 1000
4228 16:35:05.149312 tx_win_center[0][1][7] = 990
4229 16:35:05.152209 tx_first_pass[0][1][7] = 979
4230 16:35:05.155685 tx_last_pass[0][1][7] = 1002
4231 16:35:05.158753 tx_win_center[0][1][8] = 977
4232 16:35:05.162433 tx_first_pass[0][1][8] = 966
4233 16:35:05.162542 tx_last_pass[0][1][8] = 989
4234 16:35:05.165307 tx_win_center[0][1][9] = 979
4235 16:35:05.169001 tx_first_pass[0][1][9] = 968
4236 16:35:05.172039 tx_last_pass[0][1][9] = 990
4237 16:35:05.172146 tx_win_center[0][1][10] = 984
4238 16:35:05.175697 tx_first_pass[0][1][10] = 973
4239 16:35:05.178656 tx_last_pass[0][1][10] = 996
4240 16:35:05.182383 tx_win_center[0][1][11] = 978
4241 16:35:05.185364 tx_first_pass[0][1][11] = 967
4242 16:35:05.185510 tx_last_pass[0][1][11] = 990
4243 16:35:05.188516 tx_win_center[0][1][12] = 979
4244 16:35:05.192084 tx_first_pass[0][1][12] = 968
4245 16:35:05.195204 tx_last_pass[0][1][12] = 991
4246 16:35:05.198687 tx_win_center[0][1][13] = 979
4247 16:35:05.202105 tx_first_pass[0][1][13] = 968
4248 16:35:05.202217 tx_last_pass[0][1][13] = 990
4249 16:35:05.205593 tx_win_center[0][1][14] = 980
4250 16:35:05.208552 tx_first_pass[0][1][14] = 968
4251 16:35:05.211879 tx_last_pass[0][1][14] = 992
4252 16:35:05.215174 tx_win_center[0][1][15] = 983
4253 16:35:05.215261 tx_first_pass[0][1][15] = 971
4254 16:35:05.218347 tx_last_pass[0][1][15] = 996
4255 16:35:05.222294 tx_win_center[1][0][0] = 995
4256 16:35:05.225439 tx_first_pass[1][0][0] = 983
4257 16:35:05.225555 tx_last_pass[1][0][0] = 1008
4258 16:35:05.228465 tx_win_center[1][0][1] = 994
4259 16:35:05.231864 tx_first_pass[1][0][1] = 981
4260 16:35:05.235280 tx_last_pass[1][0][1] = 1007
4261 16:35:05.238452 tx_win_center[1][0][2] = 992
4262 16:35:05.238567 tx_first_pass[1][0][2] = 979
4263 16:35:05.241530 tx_last_pass[1][0][2] = 1006
4264 16:35:05.244934 tx_win_center[1][0][3] = 990
4265 16:35:05.248358 tx_first_pass[1][0][3] = 978
4266 16:35:05.251412 tx_last_pass[1][0][3] = 1003
4267 16:35:05.251494 tx_win_center[1][0][4] = 994
4268 16:35:05.255046 tx_first_pass[1][0][4] = 982
4269 16:35:05.258498 tx_last_pass[1][0][4] = 1007
4270 16:35:05.261814 tx_win_center[1][0][5] = 995
4271 16:35:05.265064 tx_first_pass[1][0][5] = 983
4272 16:35:05.265145 tx_last_pass[1][0][5] = 1008
4273 16:35:05.268776 tx_win_center[1][0][6] = 994
4274 16:35:05.271799 tx_first_pass[1][0][6] = 982
4275 16:35:05.274799 tx_last_pass[1][0][6] = 1007
4276 16:35:05.274875 tx_win_center[1][0][7] = 994
4277 16:35:05.278382 tx_first_pass[1][0][7] = 981
4278 16:35:05.281426 tx_last_pass[1][0][7] = 1007
4279 16:35:05.285183 tx_win_center[1][0][8] = 988
4280 16:35:05.288086 tx_first_pass[1][0][8] = 976
4281 16:35:05.288190 tx_last_pass[1][0][8] = 1000
4282 16:35:05.291589 tx_win_center[1][0][9] = 987
4283 16:35:05.294707 tx_first_pass[1][0][9] = 975
4284 16:35:05.298352 tx_last_pass[1][0][9] = 999
4285 16:35:05.301341 tx_win_center[1][0][10] = 990
4286 16:35:05.301425 tx_first_pass[1][0][10] = 979
4287 16:35:05.305010 tx_last_pass[1][0][10] = 1002
4288 16:35:05.308336 tx_win_center[1][0][11] = 991
4289 16:35:05.311891 tx_first_pass[1][0][11] = 981
4290 16:35:05.314804 tx_last_pass[1][0][11] = 1002
4291 16:35:05.314906 tx_win_center[1][0][12] = 991
4292 16:35:05.318339 tx_first_pass[1][0][12] = 981
4293 16:35:05.321626 tx_last_pass[1][0][12] = 1002
4294 16:35:05.325063 tx_win_center[1][0][13] = 991
4295 16:35:05.328193 tx_first_pass[1][0][13] = 981
4296 16:35:05.328424 tx_last_pass[1][0][13] = 1002
4297 16:35:05.331825 tx_win_center[1][0][14] = 990
4298 16:35:05.334764 tx_first_pass[1][0][14] = 979
4299 16:35:05.338369 tx_last_pass[1][0][14] = 1001
4300 16:35:05.341458 tx_win_center[1][0][15] = 984
4301 16:35:05.344886 tx_first_pass[1][0][15] = 971
4302 16:35:05.344985 tx_last_pass[1][0][15] = 997
4303 16:35:05.348459 tx_win_center[1][1][0] = 996
4304 16:35:05.351150 tx_first_pass[1][1][0] = 985
4305 16:35:05.354707 tx_last_pass[1][1][0] = 1008
4306 16:35:05.354804 tx_win_center[1][1][1] = 995
4307 16:35:05.357848 tx_first_pass[1][1][1] = 983
4308 16:35:05.361254 tx_last_pass[1][1][1] = 1007
4309 16:35:05.364933 tx_win_center[1][1][2] = 993
4310 16:35:05.367733 tx_first_pass[1][1][2] = 980
4311 16:35:05.367833 tx_last_pass[1][1][2] = 1007
4312 16:35:05.371243 tx_win_center[1][1][3] = 992
4313 16:35:05.374612 tx_first_pass[1][1][3] = 979
4314 16:35:05.377740 tx_last_pass[1][1][3] = 1005
4315 16:35:05.381469 tx_win_center[1][1][4] = 996
4316 16:35:05.381582 tx_first_pass[1][1][4] = 984
4317 16:35:05.384459 tx_last_pass[1][1][4] = 1008
4318 16:35:05.387991 tx_win_center[1][1][5] = 996
4319 16:35:05.391613 tx_first_pass[1][1][5] = 984
4320 16:35:05.391698 tx_last_pass[1][1][5] = 1008
4321 16:35:05.394615 tx_win_center[1][1][6] = 995
4322 16:35:05.398147 tx_first_pass[1][1][6] = 983
4323 16:35:05.401366 tx_last_pass[1][1][6] = 1007
4324 16:35:05.404933 tx_win_center[1][1][7] = 995
4325 16:35:05.405023 tx_first_pass[1][1][7] = 983
4326 16:35:05.407993 tx_last_pass[1][1][7] = 1007
4327 16:35:05.411540 tx_win_center[1][1][8] = 987
4328 16:35:05.414913 tx_first_pass[1][1][8] = 976
4329 16:35:05.417718 tx_last_pass[1][1][8] = 999
4330 16:35:05.417828 tx_win_center[1][1][9] = 987
4331 16:35:05.421422 tx_first_pass[1][1][9] = 976
4332 16:35:05.424354 tx_last_pass[1][1][9] = 999
4333 16:35:05.427820 tx_win_center[1][1][10] = 989
4334 16:35:05.427920 tx_first_pass[1][1][10] = 978
4335 16:35:05.431095 tx_last_pass[1][1][10] = 1001
4336 16:35:05.434456 tx_win_center[1][1][11] = 990
4337 16:35:05.437701 tx_first_pass[1][1][11] = 979
4338 16:35:05.441268 tx_last_pass[1][1][11] = 1001
4339 16:35:05.444371 tx_win_center[1][1][12] = 991
4340 16:35:05.444477 tx_first_pass[1][1][12] = 980
4341 16:35:05.448102 tx_last_pass[1][1][12] = 1002
4342 16:35:05.451266 tx_win_center[1][1][13] = 991
4343 16:35:05.454373 tx_first_pass[1][1][13] = 981
4344 16:35:05.457884 tx_last_pass[1][1][13] = 1002
4345 16:35:05.458002 tx_win_center[1][1][14] = 989
4346 16:35:05.461456 tx_first_pass[1][1][14] = 978
4347 16:35:05.464559 tx_last_pass[1][1][14] = 1001
4348 16:35:05.467735 tx_win_center[1][1][15] = 984
4349 16:35:05.471403 tx_first_pass[1][1][15] = 971
4350 16:35:05.471508 tx_last_pass[1][1][15] = 997
4351 16:35:05.474180 dump params rx window
4352 16:35:05.477931 rx_firspass[0][0][0] = 9
4353 16:35:05.478040 rx_lastpass[0][0][0] = 37
4354 16:35:05.480873 rx_firspass[0][0][1] = 9
4355 16:35:05.484429 rx_lastpass[0][0][1] = 37
4356 16:35:05.487524 rx_firspass[0][0][2] = 11
4357 16:35:05.487604 rx_lastpass[0][0][2] = 37
4358 16:35:05.490892 rx_firspass[0][0][3] = 3
4359 16:35:05.494442 rx_lastpass[0][0][3] = 32
4360 16:35:05.494547 rx_firspass[0][0][4] = 10
4361 16:35:05.497605 rx_lastpass[0][0][4] = 36
4362 16:35:05.501230 rx_firspass[0][0][5] = 6
4363 16:35:05.501321 rx_lastpass[0][0][5] = 32
4364 16:35:05.504251 rx_firspass[0][0][6] = 7
4365 16:35:05.507327 rx_lastpass[0][0][6] = 36
4366 16:35:05.511047 rx_firspass[0][0][7] = 11
4367 16:35:05.511135 rx_lastpass[0][0][7] = 35
4368 16:35:05.514535 rx_firspass[0][0][8] = 3
4369 16:35:05.517429 rx_lastpass[0][0][8] = 31
4370 16:35:05.517501 rx_firspass[0][0][9] = 5
4371 16:35:05.520852 rx_lastpass[0][0][9] = 32
4372 16:35:05.524420 rx_firspass[0][0][10] = 11
4373 16:35:05.527455 rx_lastpass[0][0][10] = 39
4374 16:35:05.527570 rx_firspass[0][0][11] = 4
4375 16:35:05.531177 rx_lastpass[0][0][11] = 31
4376 16:35:05.533925 rx_firspass[0][0][12] = 5
4377 16:35:05.537297 rx_lastpass[0][0][12] = 35
4378 16:35:05.537411 rx_firspass[0][0][13] = 7
4379 16:35:05.540900 rx_lastpass[0][0][13] = 32
4380 16:35:05.544194 rx_firspass[0][0][14] = 7
4381 16:35:05.544308 rx_lastpass[0][0][14] = 35
4382 16:35:05.547397 rx_firspass[0][0][15] = 9
4383 16:35:05.550410 rx_lastpass[0][0][15] = 36
4384 16:35:05.554105 rx_firspass[0][1][0] = 9
4385 16:35:05.554227 rx_lastpass[0][1][0] = 39
4386 16:35:05.557730 rx_firspass[0][1][1] = 7
4387 16:35:05.560553 rx_lastpass[0][1][1] = 39
4388 16:35:05.560664 rx_firspass[0][1][2] = 9
4389 16:35:05.564068 rx_lastpass[0][1][2] = 39
4390 16:35:05.567060 rx_firspass[0][1][3] = 1
4391 16:35:05.567170 rx_lastpass[0][1][3] = 32
4392 16:35:05.570814 rx_firspass[0][1][4] = 9
4393 16:35:05.574211 rx_lastpass[0][1][4] = 37
4394 16:35:05.577520 rx_firspass[0][1][5] = 4
4395 16:35:05.577631 rx_lastpass[0][1][5] = 34
4396 16:35:05.580713 rx_firspass[0][1][6] = 5
4397 16:35:05.583807 rx_lastpass[0][1][6] = 35
4398 16:35:05.583917 rx_firspass[0][1][7] = 6
4399 16:35:05.587393 rx_lastpass[0][1][7] = 37
4400 16:35:05.590959 rx_firspass[0][1][8] = 1
4401 16:35:05.591067 rx_lastpass[0][1][8] = 32
4402 16:35:05.594074 rx_firspass[0][1][9] = 5
4403 16:35:05.597232 rx_lastpass[0][1][9] = 34
4404 16:35:05.601084 rx_firspass[0][1][10] = 11
4405 16:35:05.601192 rx_lastpass[0][1][10] = 41
4406 16:35:05.604073 rx_firspass[0][1][11] = 3
4407 16:35:05.607643 rx_lastpass[0][1][11] = 32
4408 16:35:05.607752 rx_firspass[0][1][12] = 5
4409 16:35:05.610570 rx_lastpass[0][1][12] = 36
4410 16:35:05.614330 rx_firspass[0][1][13] = 7
4411 16:35:05.617296 rx_lastpass[0][1][13] = 34
4412 16:35:05.617395 rx_firspass[0][1][14] = 7
4413 16:35:05.620870 rx_lastpass[0][1][14] = 37
4414 16:35:05.623944 rx_firspass[0][1][15] = 9
4415 16:35:05.627211 rx_lastpass[0][1][15] = 38
4416 16:35:05.627312 rx_firspass[1][0][0] = 8
4417 16:35:05.630749 rx_lastpass[1][0][0] = 37
4418 16:35:05.633943 rx_firspass[1][0][1] = 7
4419 16:35:05.634046 rx_lastpass[1][0][1] = 35
4420 16:35:05.637546 rx_firspass[1][0][2] = 5
4421 16:35:05.640577 rx_lastpass[1][0][2] = 35
4422 16:35:05.640682 rx_firspass[1][0][3] = 5
4423 16:35:05.643788 rx_lastpass[1][0][3] = 32
4424 16:35:05.647520 rx_firspass[1][0][4] = 7
4425 16:35:05.650417 rx_lastpass[1][0][4] = 36
4426 16:35:05.650528 rx_firspass[1][0][5] = 9
4427 16:35:05.653635 rx_lastpass[1][0][5] = 38
4428 16:35:05.656968 rx_firspass[1][0][6] = 11
4429 16:35:05.657088 rx_lastpass[1][0][6] = 37
4430 16:35:05.660728 rx_firspass[1][0][7] = 9
4431 16:35:05.663532 rx_lastpass[1][0][7] = 36
4432 16:35:05.663641 rx_firspass[1][0][8] = 5
4433 16:35:05.667064 rx_lastpass[1][0][8] = 32
4434 16:35:05.670186 rx_firspass[1][0][9] = 3
4435 16:35:05.673747 rx_lastpass[1][0][9] = 31
4436 16:35:05.673853 rx_firspass[1][0][10] = 6
4437 16:35:05.676804 rx_lastpass[1][0][10] = 36
4438 16:35:05.680413 rx_firspass[1][0][11] = 7
4439 16:35:05.684064 rx_lastpass[1][0][11] = 36
4440 16:35:05.684173 rx_firspass[1][0][12] = 8
4441 16:35:05.686945 rx_lastpass[1][0][12] = 35
4442 16:35:05.690362 rx_firspass[1][0][13] = 8
4443 16:35:05.690477 rx_lastpass[1][0][13] = 36
4444 16:35:05.693684 rx_firspass[1][0][14] = 9
4445 16:35:05.697301 rx_lastpass[1][0][14] = 34
4446 16:35:05.700398 rx_firspass[1][0][15] = 4
4447 16:35:05.700506 rx_lastpass[1][0][15] = 28
4448 16:35:05.703845 rx_firspass[1][1][0] = 7
4449 16:35:05.706736 rx_lastpass[1][1][0] = 38
4450 16:35:05.706841 rx_firspass[1][1][1] = 7
4451 16:35:05.710092 rx_lastpass[1][1][1] = 37
4452 16:35:05.713404 rx_firspass[1][1][2] = 4
4453 16:35:05.717090 rx_lastpass[1][1][2] = 35
4454 16:35:05.717200 rx_firspass[1][1][3] = 3
4455 16:35:05.720534 rx_lastpass[1][1][3] = 34
4456 16:35:05.723449 rx_firspass[1][1][4] = 5
4457 16:35:05.723565 rx_lastpass[1][1][4] = 37
4458 16:35:05.727165 rx_firspass[1][1][5] = 8
4459 16:35:05.730022 rx_lastpass[1][1][5] = 39
4460 16:35:05.730118 rx_firspass[1][1][6] = 9
4461 16:35:05.733541 rx_lastpass[1][1][6] = 40
4462 16:35:05.737066 rx_firspass[1][1][7] = 8
4463 16:35:05.740233 rx_lastpass[1][1][7] = 36
4464 16:35:05.740317 rx_firspass[1][1][8] = 3
4465 16:35:05.743066 rx_lastpass[1][1][8] = 33
4466 16:35:05.746714 rx_firspass[1][1][9] = 2
4467 16:35:05.746825 rx_lastpass[1][1][9] = 32
4468 16:35:05.749775 rx_firspass[1][1][10] = 6
4469 16:35:05.753157 rx_lastpass[1][1][10] = 37
4470 16:35:05.756534 rx_firspass[1][1][11] = 7
4471 16:35:05.756652 rx_lastpass[1][1][11] = 37
4472 16:35:05.760170 rx_firspass[1][1][12] = 7
4473 16:35:05.763400 rx_lastpass[1][1][12] = 36
4474 16:35:05.763507 rx_firspass[1][1][13] = 7
4475 16:35:05.766555 rx_lastpass[1][1][13] = 37
4476 16:35:05.769934 rx_firspass[1][1][14] = 7
4477 16:35:05.772933 rx_lastpass[1][1][14] = 36
4478 16:35:05.773039 rx_firspass[1][1][15] = 1
4479 16:35:05.776061 rx_lastpass[1][1][15] = 29
4480 16:35:05.779682 dump params clk_delay
4481 16:35:05.779794 clk_delay[0] = 0
4482 16:35:05.783115 clk_delay[1] = 0
4483 16:35:05.783225 dump params dqs_delay
4484 16:35:05.786344 dqs_delay[0][0] = 0
4485 16:35:05.786454 dqs_delay[0][1] = 0
4486 16:35:05.789918 dqs_delay[1][0] = 0
4487 16:35:05.790034 dqs_delay[1][1] = 0
4488 16:35:05.792829 dump params delay_cell_unit = 844
4489 16:35:05.796019 dump source = 0x0
4490 16:35:05.799410 dump params frequency:1200
4491 16:35:05.799520 dump params rank number:2
4492 16:35:05.799610
4493 16:35:05.802725 dump params write leveling
4494 16:35:05.805870 write leveling[0][0][0] = 0x0
4495 16:35:05.809627 write leveling[0][0][1] = 0x0
4496 16:35:05.812475 write leveling[0][1][0] = 0x0
4497 16:35:05.812612 write leveling[0][1][1] = 0x0
4498 16:35:05.816311 write leveling[1][0][0] = 0x0
4499 16:35:05.819231 write leveling[1][0][1] = 0x0
4500 16:35:05.822483 write leveling[1][1][0] = 0x0
4501 16:35:05.825752 write leveling[1][1][1] = 0x0
4502 16:35:05.825861 dump params cbt_cs
4503 16:35:05.829422 cbt_cs[0][0] = 0x0
4504 16:35:05.829530 cbt_cs[0][1] = 0x0
4505 16:35:05.832476 cbt_cs[1][0] = 0x0
4506 16:35:05.832611 cbt_cs[1][1] = 0x0
4507 16:35:05.835947 dump params cbt_mr12
4508 16:35:05.836061 cbt_mr12[0][0] = 0x0
4509 16:35:05.839354 cbt_mr12[0][1] = 0x0
4510 16:35:05.839463 cbt_mr12[1][0] = 0x0
4511 16:35:05.842380 cbt_mr12[1][1] = 0x0
4512 16:35:05.846009 dump params tx window
4513 16:35:05.846120 tx_center_min[0][0][0] = 0
4514 16:35:05.849054 tx_center_max[0][0][0] = 0
4515 16:35:05.852757 tx_center_min[0][0][1] = 0
4516 16:35:05.855606 tx_center_max[0][0][1] = 0
4517 16:35:05.855722 tx_center_min[0][1][0] = 0
4518 16:35:05.859109 tx_center_max[0][1][0] = 0
4519 16:35:05.862488 tx_center_min[0][1][1] = 0
4520 16:35:05.865862 tx_center_max[0][1][1] = 0
4521 16:35:05.865973 tx_center_min[1][0][0] = 0
4522 16:35:05.869089 tx_center_max[1][0][0] = 0
4523 16:35:05.872389 tx_center_min[1][0][1] = 0
4524 16:35:05.875613 tx_center_max[1][0][1] = 0
4525 16:35:05.875727 tx_center_min[1][1][0] = 0
4526 16:35:05.878854 tx_center_max[1][1][0] = 0
4527 16:35:05.882508 tx_center_min[1][1][1] = 0
4528 16:35:05.885583 tx_center_max[1][1][1] = 0
4529 16:35:05.885694 dump params tx window
4530 16:35:05.888605 tx_win_center[0][0][0] = 0
4531 16:35:05.892143 tx_first_pass[0][0][0] = 0
4532 16:35:05.892253 tx_last_pass[0][0][0] = 0
4533 16:35:05.895220 tx_win_center[0][0][1] = 0
4534 16:35:05.898870 tx_first_pass[0][0][1] = 0
4535 16:35:05.901930 tx_last_pass[0][0][1] = 0
4536 16:35:05.902089 tx_win_center[0][0][2] = 0
4537 16:35:05.905569 tx_first_pass[0][0][2] = 0
4538 16:35:05.908613 tx_last_pass[0][0][2] = 0
4539 16:35:05.908755 tx_win_center[0][0][3] = 0
4540 16:35:05.912088 tx_first_pass[0][0][3] = 0
4541 16:35:05.915479 tx_last_pass[0][0][3] = 0
4542 16:35:05.918684 tx_win_center[0][0][4] = 0
4543 16:35:05.918797 tx_first_pass[0][0][4] = 0
4544 16:35:05.921936 tx_last_pass[0][0][4] = 0
4545 16:35:05.925607 tx_win_center[0][0][5] = 0
4546 16:35:05.928435 tx_first_pass[0][0][5] = 0
4547 16:35:05.928582 tx_last_pass[0][0][5] = 0
4548 16:35:05.932137 tx_win_center[0][0][6] = 0
4549 16:35:05.935293 tx_first_pass[0][0][6] = 0
4550 16:35:05.935425 tx_last_pass[0][0][6] = 0
4551 16:35:05.938906 tx_win_center[0][0][7] = 0
4552 16:35:05.941723 tx_first_pass[0][0][7] = 0
4553 16:35:05.945470 tx_last_pass[0][0][7] = 0
4554 16:35:05.945556 tx_win_center[0][0][8] = 0
4555 16:35:05.948561 tx_first_pass[0][0][8] = 0
4556 16:35:05.951800 tx_last_pass[0][0][8] = 0
4557 16:35:05.955395 tx_win_center[0][0][9] = 0
4558 16:35:05.955483 tx_first_pass[0][0][9] = 0
4559 16:35:05.958571 tx_last_pass[0][0][9] = 0
4560 16:35:05.962127 tx_win_center[0][0][10] = 0
4561 16:35:05.962208 tx_first_pass[0][0][10] = 0
4562 16:35:05.965017 tx_last_pass[0][0][10] = 0
4563 16:35:05.968570 tx_win_center[0][0][11] = 0
4564 16:35:05.971716 tx_first_pass[0][0][11] = 0
4565 16:35:05.971820 tx_last_pass[0][0][11] = 0
4566 16:35:05.974997 tx_win_center[0][0][12] = 0
4567 16:35:05.978663 tx_first_pass[0][0][12] = 0
4568 16:35:05.982006 tx_last_pass[0][0][12] = 0
4569 16:35:05.982096 tx_win_center[0][0][13] = 0
4570 16:35:05.985297 tx_first_pass[0][0][13] = 0
4571 16:35:05.988270 tx_last_pass[0][0][13] = 0
4572 16:35:05.991851 tx_win_center[0][0][14] = 0
4573 16:35:05.994869 tx_first_pass[0][0][14] = 0
4574 16:35:05.994950 tx_last_pass[0][0][14] = 0
4575 16:35:05.998563 tx_win_center[0][0][15] = 0
4576 16:35:06.001550 tx_first_pass[0][0][15] = 0
4577 16:35:06.001656 tx_last_pass[0][0][15] = 0
4578 16:35:06.005199 tx_win_center[0][1][0] = 0
4579 16:35:06.008300 tx_first_pass[0][1][0] = 0
4580 16:35:06.011929 tx_last_pass[0][1][0] = 0
4581 16:35:06.012016 tx_win_center[0][1][1] = 0
4582 16:35:06.015092 tx_first_pass[0][1][1] = 0
4583 16:35:06.018687 tx_last_pass[0][1][1] = 0
4584 16:35:06.021713 tx_win_center[0][1][2] = 0
4585 16:35:06.021833 tx_first_pass[0][1][2] = 0
4586 16:35:06.024599 tx_last_pass[0][1][2] = 0
4587 16:35:06.028004 tx_win_center[0][1][3] = 0
4588 16:35:06.031536 tx_first_pass[0][1][3] = 0
4589 16:35:06.031662 tx_last_pass[0][1][3] = 0
4590 16:35:06.034918 tx_win_center[0][1][4] = 0
4591 16:35:06.037953 tx_first_pass[0][1][4] = 0
4592 16:35:06.038073 tx_last_pass[0][1][4] = 0
4593 16:35:06.041798 tx_win_center[0][1][5] = 0
4594 16:35:06.044567 tx_first_pass[0][1][5] = 0
4595 16:35:06.047869 tx_last_pass[0][1][5] = 0
4596 16:35:06.047978 tx_win_center[0][1][6] = 0
4597 16:35:06.051290 tx_first_pass[0][1][6] = 0
4598 16:35:06.054837 tx_last_pass[0][1][6] = 0
4599 16:35:06.058308 tx_win_center[0][1][7] = 0
4600 16:35:06.058424 tx_first_pass[0][1][7] = 0
4601 16:35:06.061151 tx_last_pass[0][1][7] = 0
4602 16:35:06.064699 tx_win_center[0][1][8] = 0
4603 16:35:06.064806 tx_first_pass[0][1][8] = 0
4604 16:35:06.067982 tx_last_pass[0][1][8] = 0
4605 16:35:06.071545 tx_win_center[0][1][9] = 0
4606 16:35:06.075097 tx_first_pass[0][1][9] = 0
4607 16:35:06.075223 tx_last_pass[0][1][9] = 0
4608 16:35:06.078048 tx_win_center[0][1][10] = 0
4609 16:35:06.081287 tx_first_pass[0][1][10] = 0
4610 16:35:06.084869 tx_last_pass[0][1][10] = 0
4611 16:35:06.084993 tx_win_center[0][1][11] = 0
4612 16:35:06.088294 tx_first_pass[0][1][11] = 0
4613 16:35:06.091086 tx_last_pass[0][1][11] = 0
4614 16:35:06.094517 tx_win_center[0][1][12] = 0
4615 16:35:06.094652 tx_first_pass[0][1][12] = 0
4616 16:35:06.098037 tx_last_pass[0][1][12] = 0
4617 16:35:06.101104 tx_win_center[0][1][13] = 0
4618 16:35:06.104799 tx_first_pass[0][1][13] = 0
4619 16:35:06.104934 tx_last_pass[0][1][13] = 0
4620 16:35:06.107689 tx_win_center[0][1][14] = 0
4621 16:35:06.111562 tx_first_pass[0][1][14] = 0
4622 16:35:06.114579 tx_last_pass[0][1][14] = 0
4623 16:35:06.114675 tx_win_center[0][1][15] = 0
4624 16:35:06.118176 tx_first_pass[0][1][15] = 0
4625 16:35:06.121116 tx_last_pass[0][1][15] = 0
4626 16:35:06.124623 tx_win_center[1][0][0] = 0
4627 16:35:06.124752 tx_first_pass[1][0][0] = 0
4628 16:35:06.127791 tx_last_pass[1][0][0] = 0
4629 16:35:06.130837 tx_win_center[1][0][1] = 0
4630 16:35:06.134465 tx_first_pass[1][0][1] = 0
4631 16:35:06.134581 tx_last_pass[1][0][1] = 0
4632 16:35:06.137886 tx_win_center[1][0][2] = 0
4633 16:35:06.141170 tx_first_pass[1][0][2] = 0
4634 16:35:06.141305 tx_last_pass[1][0][2] = 0
4635 16:35:06.144326 tx_win_center[1][0][3] = 0
4636 16:35:06.147786 tx_first_pass[1][0][3] = 0
4637 16:35:06.150821 tx_last_pass[1][0][3] = 0
4638 16:35:06.150965 tx_win_center[1][0][4] = 0
4639 16:35:06.154431 tx_first_pass[1][0][4] = 0
4640 16:35:06.157592 tx_last_pass[1][0][4] = 0
4641 16:35:06.157723 tx_win_center[1][0][5] = 0
4642 16:35:06.161028 tx_first_pass[1][0][5] = 0
4643 16:35:06.164305 tx_last_pass[1][0][5] = 0
4644 16:35:06.167645 tx_win_center[1][0][6] = 0
4645 16:35:06.167780 tx_first_pass[1][0][6] = 0
4646 16:35:06.170891 tx_last_pass[1][0][6] = 0
4647 16:35:06.174103 tx_win_center[1][0][7] = 0
4648 16:35:06.177453 tx_first_pass[1][0][7] = 0
4649 16:35:06.177549 tx_last_pass[1][0][7] = 0
4650 16:35:06.180868 tx_win_center[1][0][8] = 0
4651 16:35:06.184705 tx_first_pass[1][0][8] = 0
4652 16:35:06.184809 tx_last_pass[1][0][8] = 0
4653 16:35:06.187853 tx_win_center[1][0][9] = 0
4654 16:35:06.191169 tx_first_pass[1][0][9] = 0
4655 16:35:06.194225 tx_last_pass[1][0][9] = 0
4656 16:35:06.194344 tx_win_center[1][0][10] = 0
4657 16:35:06.197544 tx_first_pass[1][0][10] = 0
4658 16:35:06.200791 tx_last_pass[1][0][10] = 0
4659 16:35:06.204058 tx_win_center[1][0][11] = 0
4660 16:35:06.204150 tx_first_pass[1][0][11] = 0
4661 16:35:06.207567 tx_last_pass[1][0][11] = 0
4662 16:35:06.210580 tx_win_center[1][0][12] = 0
4663 16:35:06.214374 tx_first_pass[1][0][12] = 0
4664 16:35:06.214492 tx_last_pass[1][0][12] = 0
4665 16:35:06.217304 tx_win_center[1][0][13] = 0
4666 16:35:06.220785 tx_first_pass[1][0][13] = 0
4667 16:35:06.223861 tx_last_pass[1][0][13] = 0
4668 16:35:06.223980 tx_win_center[1][0][14] = 0
4669 16:35:06.227599 tx_first_pass[1][0][14] = 0
4670 16:35:06.230610 tx_last_pass[1][0][14] = 0
4671 16:35:06.234301 tx_win_center[1][0][15] = 0
4672 16:35:06.234407 tx_first_pass[1][0][15] = 0
4673 16:35:06.237337 tx_last_pass[1][0][15] = 0
4674 16:35:06.240895 tx_win_center[1][1][0] = 0
4675 16:35:06.244000 tx_first_pass[1][1][0] = 0
4676 16:35:06.244115 tx_last_pass[1][1][0] = 0
4677 16:35:06.247639 tx_win_center[1][1][1] = 0
4678 16:35:06.250925 tx_first_pass[1][1][1] = 0
4679 16:35:06.251025 tx_last_pass[1][1][1] = 0
4680 16:35:06.254394 tx_win_center[1][1][2] = 0
4681 16:35:06.257613 tx_first_pass[1][1][2] = 0
4682 16:35:06.260841 tx_last_pass[1][1][2] = 0
4683 16:35:06.260967 tx_win_center[1][1][3] = 0
4684 16:35:06.264413 tx_first_pass[1][1][3] = 0
4685 16:35:06.267636 tx_last_pass[1][1][3] = 0
4686 16:35:06.271192 tx_win_center[1][1][4] = 0
4687 16:35:06.271294 tx_first_pass[1][1][4] = 0
4688 16:35:06.274299 tx_last_pass[1][1][4] = 0
4689 16:35:06.277441 tx_win_center[1][1][5] = 0
4690 16:35:06.277536 tx_first_pass[1][1][5] = 0
4691 16:35:06.280943 tx_last_pass[1][1][5] = 0
4692 16:35:06.284593 tx_win_center[1][1][6] = 0
4693 16:35:06.287289 tx_first_pass[1][1][6] = 0
4694 16:35:06.287387 tx_last_pass[1][1][6] = 0
4695 16:35:06.290860 tx_win_center[1][1][7] = 0
4696 16:35:06.294002 tx_first_pass[1][1][7] = 0
4697 16:35:06.297824 tx_last_pass[1][1][7] = 0
4698 16:35:06.297976 tx_win_center[1][1][8] = 0
4699 16:35:06.300840 tx_first_pass[1][1][8] = 0
4700 16:35:06.303988 tx_last_pass[1][1][8] = 0
4701 16:35:06.304130 tx_win_center[1][1][9] = 0
4702 16:35:06.307548 tx_first_pass[1][1][9] = 0
4703 16:35:06.311042 tx_last_pass[1][1][9] = 0
4704 16:35:06.314086 tx_win_center[1][1][10] = 0
4705 16:35:06.314232 tx_first_pass[1][1][10] = 0
4706 16:35:06.317784 tx_last_pass[1][1][10] = 0
4707 16:35:06.320768 tx_win_center[1][1][11] = 0
4708 16:35:06.324466 tx_first_pass[1][1][11] = 0
4709 16:35:06.324604 tx_last_pass[1][1][11] = 0
4710 16:35:06.327487 tx_win_center[1][1][12] = 0
4711 16:35:06.330558 tx_first_pass[1][1][12] = 0
4712 16:35:06.334365 tx_last_pass[1][1][12] = 0
4713 16:35:06.334499 tx_win_center[1][1][13] = 0
4714 16:35:06.337528 tx_first_pass[1][1][13] = 0
4715 16:35:06.340591 tx_last_pass[1][1][13] = 0
4716 16:35:06.344127 tx_win_center[1][1][14] = 0
4717 16:35:06.344259 tx_first_pass[1][1][14] = 0
4718 16:35:06.347208 tx_last_pass[1][1][14] = 0
4719 16:35:06.350957 tx_win_center[1][1][15] = 0
4720 16:35:06.353908 tx_first_pass[1][1][15] = 0
4721 16:35:06.354040 tx_last_pass[1][1][15] = 0
4722 16:35:06.357539 dump params rx window
4723 16:35:06.360473 rx_firspass[0][0][0] = 0
4724 16:35:06.360580 rx_lastpass[0][0][0] = 0
4725 16:35:06.363964 rx_firspass[0][0][1] = 0
4726 16:35:06.367284 rx_lastpass[0][0][1] = 0
4727 16:35:06.367391 rx_firspass[0][0][2] = 0
4728 16:35:06.370296 rx_lastpass[0][0][2] = 0
4729 16:35:06.373862 rx_firspass[0][0][3] = 0
4730 16:35:06.377410 rx_lastpass[0][0][3] = 0
4731 16:35:06.377539 rx_firspass[0][0][4] = 0
4732 16:35:06.380491 rx_lastpass[0][0][4] = 0
4733 16:35:06.383416 rx_firspass[0][0][5] = 0
4734 16:35:06.383521 rx_lastpass[0][0][5] = 0
4735 16:35:06.387179 rx_firspass[0][0][6] = 0
4736 16:35:06.390090 rx_lastpass[0][0][6] = 0
4737 16:35:06.390198 rx_firspass[0][0][7] = 0
4738 16:35:06.393765 rx_lastpass[0][0][7] = 0
4739 16:35:06.396888 rx_firspass[0][0][8] = 0
4740 16:35:06.397022 rx_lastpass[0][0][8] = 0
4741 16:35:06.400292 rx_firspass[0][0][9] = 0
4742 16:35:06.403723 rx_lastpass[0][0][9] = 0
4743 16:35:06.407132 rx_firspass[0][0][10] = 0
4744 16:35:06.407271 rx_lastpass[0][0][10] = 0
4745 16:35:06.410219 rx_firspass[0][0][11] = 0
4746 16:35:06.413704 rx_lastpass[0][0][11] = 0
4747 16:35:06.413830 rx_firspass[0][0][12] = 0
4748 16:35:06.416957 rx_lastpass[0][0][12] = 0
4749 16:35:06.420494 rx_firspass[0][0][13] = 0
4750 16:35:06.423576 rx_lastpass[0][0][13] = 0
4751 16:35:06.423706 rx_firspass[0][0][14] = 0
4752 16:35:06.426651 rx_lastpass[0][0][14] = 0
4753 16:35:06.429889 rx_firspass[0][0][15] = 0
4754 16:35:06.430038 rx_lastpass[0][0][15] = 0
4755 16:35:06.433536 rx_firspass[0][1][0] = 0
4756 16:35:06.436509 rx_lastpass[0][1][0] = 0
4757 16:35:06.436649 rx_firspass[0][1][1] = 0
4758 16:35:06.440044 rx_lastpass[0][1][1] = 0
4759 16:35:06.443260 rx_firspass[0][1][2] = 0
4760 16:35:06.447035 rx_lastpass[0][1][2] = 0
4761 16:35:06.447183 rx_firspass[0][1][3] = 0
4762 16:35:06.450043 rx_lastpass[0][1][3] = 0
4763 16:35:06.453040 rx_firspass[0][1][4] = 0
4764 16:35:06.453145 rx_lastpass[0][1][4] = 0
4765 16:35:06.456758 rx_firspass[0][1][5] = 0
4766 16:35:06.459678 rx_lastpass[0][1][5] = 0
4767 16:35:06.459797 rx_firspass[0][1][6] = 0
4768 16:35:06.463338 rx_lastpass[0][1][6] = 0
4769 16:35:06.466383 rx_firspass[0][1][7] = 0
4770 16:35:06.466495 rx_lastpass[0][1][7] = 0
4771 16:35:06.469963 rx_firspass[0][1][8] = 0
4772 16:35:06.473071 rx_lastpass[0][1][8] = 0
4773 16:35:06.473164 rx_firspass[0][1][9] = 0
4774 16:35:06.476418 rx_lastpass[0][1][9] = 0
4775 16:35:06.479712 rx_firspass[0][1][10] = 0
4776 16:35:06.483421 rx_lastpass[0][1][10] = 0
4777 16:35:06.483508 rx_firspass[0][1][11] = 0
4778 16:35:06.486770 rx_lastpass[0][1][11] = 0
4779 16:35:06.490337 rx_firspass[0][1][12] = 0
4780 16:35:06.490521 rx_lastpass[0][1][12] = 0
4781 16:35:06.493092 rx_firspass[0][1][13] = 0
4782 16:35:06.496790 rx_lastpass[0][1][13] = 0
4783 16:35:06.499777 rx_firspass[0][1][14] = 0
4784 16:35:06.499940 rx_lastpass[0][1][14] = 0
4785 16:35:06.503270 rx_firspass[0][1][15] = 0
4786 16:35:06.506326 rx_lastpass[0][1][15] = 0
4787 16:35:06.506450 rx_firspass[1][0][0] = 0
4788 16:35:06.509771 rx_lastpass[1][0][0] = 0
4789 16:35:06.513170 rx_firspass[1][0][1] = 0
4790 16:35:06.513307 rx_lastpass[1][0][1] = 0
4791 16:35:06.516755 rx_firspass[1][0][2] = 0
4792 16:35:06.519813 rx_lastpass[1][0][2] = 0
4793 16:35:06.519940 rx_firspass[1][0][3] = 0
4794 16:35:06.523013 rx_lastpass[1][0][3] = 0
4795 16:35:06.526278 rx_firspass[1][0][4] = 0
4796 16:35:06.529796 rx_lastpass[1][0][4] = 0
4797 16:35:06.529939 rx_firspass[1][0][5] = 0
4798 16:35:06.533084 rx_lastpass[1][0][5] = 0
4799 16:35:06.536285 rx_firspass[1][0][6] = 0
4800 16:35:06.536393 rx_lastpass[1][0][6] = 0
4801 16:35:06.539771 rx_firspass[1][0][7] = 0
4802 16:35:06.542987 rx_lastpass[1][0][7] = 0
4803 16:35:06.543090 rx_firspass[1][0][8] = 0
4804 16:35:06.546904 rx_lastpass[1][0][8] = 0
4805 16:35:06.549752 rx_firspass[1][0][9] = 0
4806 16:35:06.549870 rx_lastpass[1][0][9] = 0
4807 16:35:06.552835 rx_firspass[1][0][10] = 0
4808 16:35:06.556557 rx_lastpass[1][0][10] = 0
4809 16:35:06.559628 rx_firspass[1][0][11] = 0
4810 16:35:06.559763 rx_lastpass[1][0][11] = 0
4811 16:35:06.563153 rx_firspass[1][0][12] = 0
4812 16:35:06.566193 rx_lastpass[1][0][12] = 0
4813 16:35:06.566325 rx_firspass[1][0][13] = 0
4814 16:35:06.569862 rx_lastpass[1][0][13] = 0
4815 16:35:06.572940 rx_firspass[1][0][14] = 0
4816 16:35:06.576595 rx_lastpass[1][0][14] = 0
4817 16:35:06.576700 rx_firspass[1][0][15] = 0
4818 16:35:06.579860 rx_lastpass[1][0][15] = 0
4819 16:35:06.583422 rx_firspass[1][1][0] = 0
4820 16:35:06.583558 rx_lastpass[1][1][0] = 0
4821 16:35:06.586263 rx_firspass[1][1][1] = 0
4822 16:35:06.589674 rx_lastpass[1][1][1] = 0
4823 16:35:06.589794 rx_firspass[1][1][2] = 0
4824 16:35:06.593095 rx_lastpass[1][1][2] = 0
4825 16:35:06.596006 rx_firspass[1][1][3] = 0
4826 16:35:06.596139 rx_lastpass[1][1][3] = 0
4827 16:35:06.599594 rx_firspass[1][1][4] = 0
4828 16:35:06.602777 rx_lastpass[1][1][4] = 0
4829 16:35:06.606173 rx_firspass[1][1][5] = 0
4830 16:35:06.606279 rx_lastpass[1][1][5] = 0
4831 16:35:06.609841 rx_firspass[1][1][6] = 0
4832 16:35:06.612914 rx_lastpass[1][1][6] = 0
4833 16:35:06.613031 rx_firspass[1][1][7] = 0
4834 16:35:06.616287 rx_lastpass[1][1][7] = 0
4835 16:35:06.619427 rx_firspass[1][1][8] = 0
4836 16:35:06.619552 rx_lastpass[1][1][8] = 0
4837 16:35:06.623003 rx_firspass[1][1][9] = 0
4838 16:35:06.626026 rx_lastpass[1][1][9] = 0
4839 16:35:06.626123 rx_firspass[1][1][10] = 0
4840 16:35:06.629503 rx_lastpass[1][1][10] = 0
4841 16:35:06.632621 rx_firspass[1][1][11] = 0
4842 16:35:06.636409 rx_lastpass[1][1][11] = 0
4843 16:35:06.636549 rx_firspass[1][1][12] = 0
4844 16:35:06.639300 rx_lastpass[1][1][12] = 0
4845 16:35:06.642813 rx_firspass[1][1][13] = 0
4846 16:35:06.642930 rx_lastpass[1][1][13] = 0
4847 16:35:06.645829 rx_firspass[1][1][14] = 0
4848 16:35:06.649461 rx_lastpass[1][1][14] = 0
4849 16:35:06.652657 rx_firspass[1][1][15] = 0
4850 16:35:06.652755 rx_lastpass[1][1][15] = 0
4851 16:35:06.655875 dump params clk_delay
4852 16:35:06.655953 clk_delay[0] = 0
4853 16:35:06.659584 clk_delay[1] = 0
4854 16:35:06.659711 dump params dqs_delay
4855 16:35:06.663016 dqs_delay[0][0] = 0
4856 16:35:06.666074 dqs_delay[0][1] = 0
4857 16:35:06.666211 dqs_delay[1][0] = 0
4858 16:35:06.669152 dqs_delay[1][1] = 0
4859 16:35:06.672697 dump params delay_cell_unit = 844
4860 16:35:06.672829 dump source = 0x0
4861 16:35:06.675764 dump params frequency:800
4862 16:35:06.675904 dump params rank number:2
4863 16:35:06.676004
4864 16:35:06.679411 dump params write leveling
4865 16:35:06.682542 write leveling[0][0][0] = 0x0
4866 16:35:06.686050 write leveling[0][0][1] = 0x0
4867 16:35:06.689145 write leveling[0][1][0] = 0x0
4868 16:35:06.689312 write leveling[0][1][1] = 0x0
4869 16:35:06.692618 write leveling[1][0][0] = 0x0
4870 16:35:06.695709 write leveling[1][0][1] = 0x0
4871 16:35:06.699112 write leveling[1][1][0] = 0x0
4872 16:35:06.702241 write leveling[1][1][1] = 0x0
4873 16:35:06.702345 dump params cbt_cs
4874 16:35:06.705738 cbt_cs[0][0] = 0x0
4875 16:35:06.705851 cbt_cs[0][1] = 0x0
4876 16:35:06.709062 cbt_cs[1][0] = 0x0
4877 16:35:06.709196 cbt_cs[1][1] = 0x0
4878 16:35:06.712426 dump params cbt_mr12
4879 16:35:06.712552 cbt_mr12[0][0] = 0x0
4880 16:35:06.715681 cbt_mr12[0][1] = 0x0
4881 16:35:06.718816 cbt_mr12[1][0] = 0x0
4882 16:35:06.718952 cbt_mr12[1][1] = 0x0
4883 16:35:06.722352 dump params tx window
4884 16:35:06.722487 tx_center_min[0][0][0] = 0
4885 16:35:06.725790 tx_center_max[0][0][0] = 0
4886 16:35:06.728931 tx_center_min[0][0][1] = 0
4887 16:35:06.732507 tx_center_max[0][0][1] = 0
4888 16:35:06.732652 tx_center_min[0][1][0] = 0
4889 16:35:06.735966 tx_center_max[0][1][0] = 0
4890 16:35:06.738874 tx_center_min[0][1][1] = 0
4891 16:35:06.742485 tx_center_max[0][1][1] = 0
4892 16:35:06.742617 tx_center_min[1][0][0] = 0
4893 16:35:06.745524 tx_center_max[1][0][0] = 0
4894 16:35:06.749097 tx_center_min[1][0][1] = 0
4895 16:35:06.752601 tx_center_max[1][0][1] = 0
4896 16:35:06.752742 tx_center_min[1][1][0] = 0
4897 16:35:06.755540 tx_center_max[1][1][0] = 0
4898 16:35:06.758676 tx_center_min[1][1][1] = 0
4899 16:35:06.762152 tx_center_max[1][1][1] = 0
4900 16:35:06.762253 dump params tx window
4901 16:35:06.765753 tx_win_center[0][0][0] = 0
4902 16:35:06.769048 tx_first_pass[0][0][0] = 0
4903 16:35:06.769165 tx_last_pass[0][0][0] = 0
4904 16:35:06.772174 tx_win_center[0][0][1] = 0
4905 16:35:06.775611 tx_first_pass[0][0][1] = 0
4906 16:35:06.778690 tx_last_pass[0][0][1] = 0
4907 16:35:06.778816 tx_win_center[0][0][2] = 0
4908 16:35:06.782193 tx_first_pass[0][0][2] = 0
4909 16:35:06.785285 tx_last_pass[0][0][2] = 0
4910 16:35:06.785415 tx_win_center[0][0][3] = 0
4911 16:35:06.788970 tx_first_pass[0][0][3] = 0
4912 16:35:06.792037 tx_last_pass[0][0][3] = 0
4913 16:35:06.795672 tx_win_center[0][0][4] = 0
4914 16:35:06.795840 tx_first_pass[0][0][4] = 0
4915 16:35:06.798407 tx_last_pass[0][0][4] = 0
4916 16:35:06.801946 tx_win_center[0][0][5] = 0
4917 16:35:06.805263 tx_first_pass[0][0][5] = 0
4918 16:35:06.805398 tx_last_pass[0][0][5] = 0
4919 16:35:06.808785 tx_win_center[0][0][6] = 0
4920 16:35:06.811764 tx_first_pass[0][0][6] = 0
4921 16:35:06.811854 tx_last_pass[0][0][6] = 0
4922 16:35:06.815213 tx_win_center[0][0][7] = 0
4923 16:35:06.818760 tx_first_pass[0][0][7] = 0
4924 16:35:06.821925 tx_last_pass[0][0][7] = 0
4925 16:35:06.822058 tx_win_center[0][0][8] = 0
4926 16:35:06.825447 tx_first_pass[0][0][8] = 0
4927 16:35:06.828746 tx_last_pass[0][0][8] = 0
4928 16:35:06.828866 tx_win_center[0][0][9] = 0
4929 16:35:06.832220 tx_first_pass[0][0][9] = 0
4930 16:35:06.835551 tx_last_pass[0][0][9] = 0
4931 16:35:06.838909 tx_win_center[0][0][10] = 0
4932 16:35:06.839018 tx_first_pass[0][0][10] = 0
4933 16:35:06.841876 tx_last_pass[0][0][10] = 0
4934 16:35:06.845460 tx_win_center[0][0][11] = 0
4935 16:35:06.848527 tx_first_pass[0][0][11] = 0
4936 16:35:06.848643 tx_last_pass[0][0][11] = 0
4937 16:35:06.852224 tx_win_center[0][0][12] = 0
4938 16:35:06.855203 tx_first_pass[0][0][12] = 0
4939 16:35:06.858528 tx_last_pass[0][0][12] = 0
4940 16:35:06.858630 tx_win_center[0][0][13] = 0
4941 16:35:06.862180 tx_first_pass[0][0][13] = 0
4942 16:35:06.865316 tx_last_pass[0][0][13] = 0
4943 16:35:06.868916 tx_win_center[0][0][14] = 0
4944 16:35:06.869011 tx_first_pass[0][0][14] = 0
4945 16:35:06.871987 tx_last_pass[0][0][14] = 0
4946 16:35:06.875577 tx_win_center[0][0][15] = 0
4947 16:35:06.878828 tx_first_pass[0][0][15] = 0
4948 16:35:06.878928 tx_last_pass[0][0][15] = 0
4949 16:35:06.882093 tx_win_center[0][1][0] = 0
4950 16:35:06.885554 tx_first_pass[0][1][0] = 0
4951 16:35:06.888712 tx_last_pass[0][1][0] = 0
4952 16:35:06.888848 tx_win_center[0][1][1] = 0
4953 16:35:06.892428 tx_first_pass[0][1][1] = 0
4954 16:35:06.895401 tx_last_pass[0][1][1] = 0
4955 16:35:06.895483 tx_win_center[0][1][2] = 0
4956 16:35:06.899008 tx_first_pass[0][1][2] = 0
4957 16:35:06.901856 tx_last_pass[0][1][2] = 0
4958 16:35:06.905499 tx_win_center[0][1][3] = 0
4959 16:35:06.905597 tx_first_pass[0][1][3] = 0
4960 16:35:06.908957 tx_last_pass[0][1][3] = 0
4961 16:35:06.912258 tx_win_center[0][1][4] = 0
4962 16:35:06.915023 tx_first_pass[0][1][4] = 0
4963 16:35:06.915173 tx_last_pass[0][1][4] = 0
4964 16:35:06.918535 tx_win_center[0][1][5] = 0
4965 16:35:06.922147 tx_first_pass[0][1][5] = 0
4966 16:35:06.922281 tx_last_pass[0][1][5] = 0
4967 16:35:06.925651 tx_win_center[0][1][6] = 0
4968 16:35:06.928921 tx_first_pass[0][1][6] = 0
4969 16:35:06.931895 tx_last_pass[0][1][6] = 0
4970 16:35:06.932038 tx_win_center[0][1][7] = 0
4971 16:35:06.935362 tx_first_pass[0][1][7] = 0
4972 16:35:06.938411 tx_last_pass[0][1][7] = 0
4973 16:35:06.941873 tx_win_center[0][1][8] = 0
4974 16:35:06.942013 tx_first_pass[0][1][8] = 0
4975 16:35:06.945237 tx_last_pass[0][1][8] = 0
4976 16:35:06.948444 tx_win_center[0][1][9] = 0
4977 16:35:06.951989 tx_first_pass[0][1][9] = 0
4978 16:35:06.952136 tx_last_pass[0][1][9] = 0
4979 16:35:06.955108 tx_win_center[0][1][10] = 0
4980 16:35:06.958196 tx_first_pass[0][1][10] = 0
4981 16:35:06.958330 tx_last_pass[0][1][10] = 0
4982 16:35:06.962075 tx_win_center[0][1][11] = 0
4983 16:35:06.965457 tx_first_pass[0][1][11] = 0
4984 16:35:06.968549 tx_last_pass[0][1][11] = 0
4985 16:35:06.968683 tx_win_center[0][1][12] = 0
4986 16:35:06.971438 tx_first_pass[0][1][12] = 0
4987 16:35:06.975241 tx_last_pass[0][1][12] = 0
4988 16:35:06.978272 tx_win_center[0][1][13] = 0
4989 16:35:06.981903 tx_first_pass[0][1][13] = 0
4990 16:35:06.982037 tx_last_pass[0][1][13] = 0
4991 16:35:06.984902 tx_win_center[0][1][14] = 0
4992 16:35:06.988507 tx_first_pass[0][1][14] = 0
4993 16:35:06.988638 tx_last_pass[0][1][14] = 0
4994 16:35:06.991498 tx_win_center[0][1][15] = 0
4995 16:35:06.994855 tx_first_pass[0][1][15] = 0
4996 16:35:06.998161 tx_last_pass[0][1][15] = 0
4997 16:35:06.998292 tx_win_center[1][0][0] = 0
4998 16:35:07.001737 tx_first_pass[1][0][0] = 0
4999 16:35:07.004671 tx_last_pass[1][0][0] = 0
5000 16:35:07.008177 tx_win_center[1][0][1] = 0
5001 16:35:07.008313 tx_first_pass[1][0][1] = 0
5002 16:35:07.011831 tx_last_pass[1][0][1] = 0
5003 16:35:07.014758 tx_win_center[1][0][2] = 0
5004 16:35:07.018535 tx_first_pass[1][0][2] = 0
5005 16:35:07.018666 tx_last_pass[1][0][2] = 0
5006 16:35:07.021541 tx_win_center[1][0][3] = 0
5007 16:35:07.025335 tx_first_pass[1][0][3] = 0
5008 16:35:07.025418 tx_last_pass[1][0][3] = 0
5009 16:35:07.028182 tx_win_center[1][0][4] = 0
5010 16:35:07.031911 tx_first_pass[1][0][4] = 0
5011 16:35:07.035393 tx_last_pass[1][0][4] = 0
5012 16:35:07.035553 tx_win_center[1][0][5] = 0
5013 16:35:07.038764 tx_first_pass[1][0][5] = 0
5014 16:35:07.041632 tx_last_pass[1][0][5] = 0
5015 16:35:07.041774 tx_win_center[1][0][6] = 0
5016 16:35:07.045206 tx_first_pass[1][0][6] = 0
5017 16:35:07.048343 tx_last_pass[1][0][6] = 0
5018 16:35:07.051770 tx_win_center[1][0][7] = 0
5019 16:35:07.051867 tx_first_pass[1][0][7] = 0
5020 16:35:07.055230 tx_last_pass[1][0][7] = 0
5021 16:35:07.058635 tx_win_center[1][0][8] = 0
5022 16:35:07.061463 tx_first_pass[1][0][8] = 0
5023 16:35:07.061561 tx_last_pass[1][0][8] = 0
5024 16:35:07.064924 tx_win_center[1][0][9] = 0
5025 16:35:07.068530 tx_first_pass[1][0][9] = 0
5026 16:35:07.068633 tx_last_pass[1][0][9] = 0
5027 16:35:07.071748 tx_win_center[1][0][10] = 0
5028 16:35:07.074756 tx_first_pass[1][0][10] = 0
5029 16:35:07.078590 tx_last_pass[1][0][10] = 0
5030 16:35:07.078681 tx_win_center[1][0][11] = 0
5031 16:35:07.081806 tx_first_pass[1][0][11] = 0
5032 16:35:07.084954 tx_last_pass[1][0][11] = 0
5033 16:35:07.088032 tx_win_center[1][0][12] = 0
5034 16:35:07.091726 tx_first_pass[1][0][12] = 0
5035 16:35:07.091857 tx_last_pass[1][0][12] = 0
5036 16:35:07.094643 tx_win_center[1][0][13] = 0
5037 16:35:07.098404 tx_first_pass[1][0][13] = 0
5038 16:35:07.098499 tx_last_pass[1][0][13] = 0
5039 16:35:07.101379 tx_win_center[1][0][14] = 0
5040 16:35:07.105035 tx_first_pass[1][0][14] = 0
5041 16:35:07.107965 tx_last_pass[1][0][14] = 0
5042 16:35:07.108099 tx_win_center[1][0][15] = 0
5043 16:35:07.111421 tx_first_pass[1][0][15] = 0
5044 16:35:07.115110 tx_last_pass[1][0][15] = 0
5045 16:35:07.118101 tx_win_center[1][1][0] = 0
5046 16:35:07.118219 tx_first_pass[1][1][0] = 0
5047 16:35:07.121528 tx_last_pass[1][1][0] = 0
5048 16:35:07.124680 tx_win_center[1][1][1] = 0
5049 16:35:07.128145 tx_first_pass[1][1][1] = 0
5050 16:35:07.128234 tx_last_pass[1][1][1] = 0
5051 16:35:07.131839 tx_win_center[1][1][2] = 0
5052 16:35:07.134678 tx_first_pass[1][1][2] = 0
5053 16:35:07.138281 tx_last_pass[1][1][2] = 0
5054 16:35:07.138364 tx_win_center[1][1][3] = 0
5055 16:35:07.141116 tx_first_pass[1][1][3] = 0
5056 16:35:07.145188 tx_last_pass[1][1][3] = 0
5057 16:35:07.145280 tx_win_center[1][1][4] = 0
5058 16:35:07.147843 tx_first_pass[1][1][4] = 0
5059 16:35:07.151413 tx_last_pass[1][1][4] = 0
5060 16:35:07.154907 tx_win_center[1][1][5] = 0
5061 16:35:07.154987 tx_first_pass[1][1][5] = 0
5062 16:35:07.158078 tx_last_pass[1][1][5] = 0
5063 16:35:07.161301 tx_win_center[1][1][6] = 0
5064 16:35:07.164637 tx_first_pass[1][1][6] = 0
5065 16:35:07.164718 tx_last_pass[1][1][6] = 0
5066 16:35:07.168014 tx_win_center[1][1][7] = 0
5067 16:35:07.171295 tx_first_pass[1][1][7] = 0
5068 16:35:07.171413 tx_last_pass[1][1][7] = 0
5069 16:35:07.174738 tx_win_center[1][1][8] = 0
5070 16:35:07.177966 tx_first_pass[1][1][8] = 0
5071 16:35:07.181634 tx_last_pass[1][1][8] = 0
5072 16:35:07.181754 tx_win_center[1][1][9] = 0
5073 16:35:07.184685 tx_first_pass[1][1][9] = 0
5074 16:35:07.187812 tx_last_pass[1][1][9] = 0
5075 16:35:07.187912 tx_win_center[1][1][10] = 0
5076 16:35:07.191494 tx_first_pass[1][1][10] = 0
5077 16:35:07.194429 tx_last_pass[1][1][10] = 0
5078 16:35:07.197993 tx_win_center[1][1][11] = 0
5079 16:35:07.201159 tx_first_pass[1][1][11] = 0
5080 16:35:07.201246 tx_last_pass[1][1][11] = 0
5081 16:35:07.204661 tx_win_center[1][1][12] = 0
5082 16:35:07.207712 tx_first_pass[1][1][12] = 0
5083 16:35:07.211419 tx_last_pass[1][1][12] = 0
5084 16:35:07.211550 tx_win_center[1][1][13] = 0
5085 16:35:07.214486 tx_first_pass[1][1][13] = 0
5086 16:35:07.218123 tx_last_pass[1][1][13] = 0
5087 16:35:07.221379 tx_win_center[1][1][14] = 0
5088 16:35:07.221494 tx_first_pass[1][1][14] = 0
5089 16:35:07.224640 tx_last_pass[1][1][14] = 0
5090 16:35:07.228189 tx_win_center[1][1][15] = 0
5091 16:35:07.231151 tx_first_pass[1][1][15] = 0
5092 16:35:07.231281 tx_last_pass[1][1][15] = 0
5093 16:35:07.234240 dump params rx window
5094 16:35:07.237655 rx_firspass[0][0][0] = 0
5095 16:35:07.237773 rx_lastpass[0][0][0] = 0
5096 16:35:07.241109 rx_firspass[0][0][1] = 0
5097 16:35:07.244639 rx_lastpass[0][0][1] = 0
5098 16:35:07.244753 rx_firspass[0][0][2] = 0
5099 16:35:07.247646 rx_lastpass[0][0][2] = 0
5100 16:35:07.251242 rx_firspass[0][0][3] = 0
5101 16:35:07.251359 rx_lastpass[0][0][3] = 0
5102 16:35:07.254564 rx_firspass[0][0][4] = 0
5103 16:35:07.257638 rx_lastpass[0][0][4] = 0
5104 16:35:07.257755 rx_firspass[0][0][5] = 0
5105 16:35:07.261317 rx_lastpass[0][0][5] = 0
5106 16:35:07.264248 rx_firspass[0][0][6] = 0
5107 16:35:07.264365 rx_lastpass[0][0][6] = 0
5108 16:35:07.267948 rx_firspass[0][0][7] = 0
5109 16:35:07.271324 rx_lastpass[0][0][7] = 0
5110 16:35:07.274786 rx_firspass[0][0][8] = 0
5111 16:35:07.274904 rx_lastpass[0][0][8] = 0
5112 16:35:07.277764 rx_firspass[0][0][9] = 0
5113 16:35:07.281335 rx_lastpass[0][0][9] = 0
5114 16:35:07.281464 rx_firspass[0][0][10] = 0
5115 16:35:07.284500 rx_lastpass[0][0][10] = 0
5116 16:35:07.287831 rx_firspass[0][0][11] = 0
5117 16:35:07.287929 rx_lastpass[0][0][11] = 0
5118 16:35:07.291605 rx_firspass[0][0][12] = 0
5119 16:35:07.294639 rx_lastpass[0][0][12] = 0
5120 16:35:07.297684 rx_firspass[0][0][13] = 0
5121 16:35:07.297808 rx_lastpass[0][0][13] = 0
5122 16:35:07.301148 rx_firspass[0][0][14] = 0
5123 16:35:07.304178 rx_lastpass[0][0][14] = 0
5124 16:35:07.304307 rx_firspass[0][0][15] = 0
5125 16:35:07.307898 rx_lastpass[0][0][15] = 0
5126 16:35:07.310824 rx_firspass[0][1][0] = 0
5127 16:35:07.314450 rx_lastpass[0][1][0] = 0
5128 16:35:07.314534 rx_firspass[0][1][1] = 0
5129 16:35:07.317617 rx_lastpass[0][1][1] = 0
5130 16:35:07.321076 rx_firspass[0][1][2] = 0
5131 16:35:07.321151 rx_lastpass[0][1][2] = 0
5132 16:35:07.324142 rx_firspass[0][1][3] = 0
5133 16:35:07.327836 rx_lastpass[0][1][3] = 0
5134 16:35:07.327942 rx_firspass[0][1][4] = 0
5135 16:35:07.330829 rx_lastpass[0][1][4] = 0
5136 16:35:07.334576 rx_firspass[0][1][5] = 0
5137 16:35:07.334666 rx_lastpass[0][1][5] = 0
5138 16:35:07.337490 rx_firspass[0][1][6] = 0
5139 16:35:07.340934 rx_lastpass[0][1][6] = 0
5140 16:35:07.341008 rx_firspass[0][1][7] = 0
5141 16:35:07.344398 rx_lastpass[0][1][7] = 0
5142 16:35:07.347564 rx_firspass[0][1][8] = 0
5143 16:35:07.347637 rx_lastpass[0][1][8] = 0
5144 16:35:07.350870 rx_firspass[0][1][9] = 0
5145 16:35:07.354260 rx_lastpass[0][1][9] = 0
5146 16:35:07.357733 rx_firspass[0][1][10] = 0
5147 16:35:07.357857 rx_lastpass[0][1][10] = 0
5148 16:35:07.360551 rx_firspass[0][1][11] = 0
5149 16:35:07.364071 rx_lastpass[0][1][11] = 0
5150 16:35:07.364147 rx_firspass[0][1][12] = 0
5151 16:35:07.367285 rx_lastpass[0][1][12] = 0
5152 16:35:07.371017 rx_firspass[0][1][13] = 0
5153 16:35:07.374095 rx_lastpass[0][1][13] = 0
5154 16:35:07.374217 rx_firspass[0][1][14] = 0
5155 16:35:07.377386 rx_lastpass[0][1][14] = 0
5156 16:35:07.381157 rx_firspass[0][1][15] = 0
5157 16:35:07.381272 rx_lastpass[0][1][15] = 0
5158 16:35:07.384249 rx_firspass[1][0][0] = 0
5159 16:35:07.387927 rx_lastpass[1][0][0] = 0
5160 16:35:07.388061 rx_firspass[1][0][1] = 0
5161 16:35:07.391050 rx_lastpass[1][0][1] = 0
5162 16:35:07.393758 rx_firspass[1][0][2] = 0
5163 16:35:07.397110 rx_lastpass[1][0][2] = 0
5164 16:35:07.397229 rx_firspass[1][0][3] = 0
5165 16:35:07.400949 rx_lastpass[1][0][3] = 0
5166 16:35:07.404027 rx_firspass[1][0][4] = 0
5167 16:35:07.404207 rx_lastpass[1][0][4] = 0
5168 16:35:07.407440 rx_firspass[1][0][5] = 0
5169 16:35:07.410572 rx_lastpass[1][0][5] = 0
5170 16:35:07.410716 rx_firspass[1][0][6] = 0
5171 16:35:07.413583 rx_lastpass[1][0][6] = 0
5172 16:35:07.417251 rx_firspass[1][0][7] = 0
5173 16:35:07.417373 rx_lastpass[1][0][7] = 0
5174 16:35:07.420412 rx_firspass[1][0][8] = 0
5175 16:35:07.423912 rx_lastpass[1][0][8] = 0
5176 16:35:07.426904 rx_firspass[1][0][9] = 0
5177 16:35:07.427024 rx_lastpass[1][0][9] = 0
5178 16:35:07.430638 rx_firspass[1][0][10] = 0
5179 16:35:07.433674 rx_lastpass[1][0][10] = 0
5180 16:35:07.433797 rx_firspass[1][0][11] = 0
5181 16:35:07.437091 rx_lastpass[1][0][11] = 0
5182 16:35:07.439988 rx_firspass[1][0][12] = 0
5183 16:35:07.443743 rx_lastpass[1][0][12] = 0
5184 16:35:07.443881 rx_firspass[1][0][13] = 0
5185 16:35:07.446678 rx_lastpass[1][0][13] = 0
5186 16:35:07.450189 rx_firspass[1][0][14] = 0
5187 16:35:07.450323 rx_lastpass[1][0][14] = 0
5188 16:35:07.453976 rx_firspass[1][0][15] = 0
5189 16:35:07.457032 rx_lastpass[1][0][15] = 0
5190 16:35:07.460342 rx_firspass[1][1][0] = 0
5191 16:35:07.460475 rx_lastpass[1][1][0] = 0
5192 16:35:07.463544 rx_firspass[1][1][1] = 0
5193 16:35:07.466635 rx_lastpass[1][1][1] = 0
5194 16:35:07.466776 rx_firspass[1][1][2] = 0
5195 16:35:07.470139 rx_lastpass[1][1][2] = 0
5196 16:35:07.473111 rx_firspass[1][1][3] = 0
5197 16:35:07.473210 rx_lastpass[1][1][3] = 0
5198 16:35:07.476827 rx_firspass[1][1][4] = 0
5199 16:35:07.479805 rx_lastpass[1][1][4] = 0
5200 16:35:07.479946 rx_firspass[1][1][5] = 0
5201 16:35:07.483425 rx_lastpass[1][1][5] = 0
5202 16:35:07.486590 rx_firspass[1][1][6] = 0
5203 16:35:07.489882 rx_lastpass[1][1][6] = 0
5204 16:35:07.489995 rx_firspass[1][1][7] = 0
5205 16:35:07.493415 rx_lastpass[1][1][7] = 0
5206 16:35:07.496486 rx_firspass[1][1][8] = 0
5207 16:35:07.496567 rx_lastpass[1][1][8] = 0
5208 16:35:07.500030 rx_firspass[1][1][9] = 0
5209 16:35:07.503552 rx_lastpass[1][1][9] = 0
5210 16:35:07.503670 rx_firspass[1][1][10] = 0
5211 16:35:07.506251 rx_lastpass[1][1][10] = 0
5212 16:35:07.509979 rx_firspass[1][1][11] = 0
5213 16:35:07.510121 rx_lastpass[1][1][11] = 0
5214 16:35:07.513265 rx_firspass[1][1][12] = 0
5215 16:35:07.516247 rx_lastpass[1][1][12] = 0
5216 16:35:07.519853 rx_firspass[1][1][13] = 0
5217 16:35:07.519985 rx_lastpass[1][1][13] = 0
5218 16:35:07.523423 rx_firspass[1][1][14] = 0
5219 16:35:07.526492 rx_lastpass[1][1][14] = 0
5220 16:35:07.529517 rx_firspass[1][1][15] = 0
5221 16:35:07.529647 rx_lastpass[1][1][15] = 0
5222 16:35:07.533319 dump params clk_delay
5223 16:35:07.533463 clk_delay[0] = 0
5224 16:35:07.536319 clk_delay[1] = 0
5225 16:35:07.536450 dump params dqs_delay
5226 16:35:07.539850 dqs_delay[0][0] = 0
5227 16:35:07.539987 dqs_delay[0][1] = 0
5228 16:35:07.542923 dqs_delay[1][0] = 0
5229 16:35:07.546400 dqs_delay[1][1] = 0
5230 16:35:07.546545 dump params delay_cell_unit = 844
5231 16:35:07.549385 mt_set_emi_preloader end
5232 16:35:07.556085 [mt_mem_init] dram size: 0x100000000, rank number: 2
5233 16:35:07.559677 [complex_mem_test] start addr:0x40000000, len:20480
5234 16:35:07.596139 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5235 16:35:07.602244 [complex_mem_test] start addr:0x80000000, len:20480
5236 16:35:07.638867 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5237 16:35:07.644772 [complex_mem_test] start addr:0xc0000000, len:20480
5238 16:35:07.680442 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5239 16:35:07.687191 [complex_mem_test] start addr:0x56000000, len:8192
5240 16:35:07.704284 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5241 16:35:07.704483 ddr_geometry:1
5242 16:35:07.710548 [complex_mem_test] start addr:0x80000000, len:8192
5243 16:35:07.727655 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5244 16:35:07.731262 dram_init: dram init end (result: 0)
5245 16:35:07.737837 Successfully loaded DRAM blobs and ran DRAM calibration
5246 16:35:07.747799 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5247 16:35:07.747984 CBMEM:
5248 16:35:07.751349 IMD: root @ 00000000fffff000 254 entries.
5249 16:35:07.754370 IMD: root @ 00000000ffffec00 62 entries.
5250 16:35:07.761288 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5251 16:35:07.767860 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5252 16:35:07.770878 in-header: 03 a1 00 00 08 00 00 00
5253 16:35:07.774494 in-data: 84 60 60 10 00 00 00 00
5254 16:35:07.777468 Chrome EC: clear events_b mask to 0x0000000020004000
5255 16:35:07.785256 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5256 16:35:07.788139 in-header: 03 fd 00 00 00 00 00 00
5257 16:35:07.788315 in-data:
5258 16:35:07.794921 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5259 16:35:07.795108 CBFS @ 21000 size 3d4000
5260 16:35:07.801429 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5261 16:35:07.805115 CBFS: Locating 'fallback/ramstage'
5262 16:35:07.807925 CBFS: Found @ offset 10d40 size d563
5263 16:35:07.829776 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5264 16:35:07.841718 Accumulated console time in romstage 13660 ms
5265 16:35:07.841913
5266 16:35:07.842042
5267 16:35:07.852139 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5268 16:35:07.855084 ARM64: Exception handlers installed.
5269 16:35:07.855247 ARM64: Testing exception
5270 16:35:07.858167 ARM64: Done test exception
5271 16:35:07.861685 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5272 16:35:07.865102 Manufacturer: ef
5273 16:35:07.868247 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5274 16:35:07.874864 WARNING: RO_VPD is uninitialized or empty.
5275 16:35:07.878533 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5276 16:35:07.881297 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5277 16:35:07.891309 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5278 16:35:07.894857 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5279 16:35:07.901572 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5280 16:35:07.901778 Enumerating buses...
5281 16:35:07.908223 Show all devs... Before device enumeration.
5282 16:35:07.908427 Root Device: enabled 1
5283 16:35:07.911137 CPU_CLUSTER: 0: enabled 1
5284 16:35:07.911317 CPU: 00: enabled 1
5285 16:35:07.914783 Compare with tree...
5286 16:35:07.917833 Root Device: enabled 1
5287 16:35:07.917990 CPU_CLUSTER: 0: enabled 1
5288 16:35:07.921534 CPU: 00: enabled 1
5289 16:35:07.924726 Root Device scanning...
5290 16:35:07.924879 root_dev_scan_bus for Root Device
5291 16:35:07.928060 CPU_CLUSTER: 0 enabled
5292 16:35:07.931560 root_dev_scan_bus for Root Device done
5293 16:35:07.938200 scan_bus: scanning of bus Root Device took 10689 usecs
5294 16:35:07.938379 done
5295 16:35:07.941340 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5296 16:35:07.944807 Allocating resources...
5297 16:35:07.944947 Reading resources...
5298 16:35:07.948047 Root Device read_resources bus 0 link: 0
5299 16:35:07.954738 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5300 16:35:07.954897 CPU: 00 missing read_resources
5301 16:35:07.961428 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5302 16:35:07.964561 Root Device read_resources bus 0 link: 0 done
5303 16:35:07.967938 Done reading resources.
5304 16:35:07.971487 Show resources in subtree (Root Device)...After reading.
5305 16:35:07.974533 Root Device child on link 0 CPU_CLUSTER: 0
5306 16:35:07.978090 CPU_CLUSTER: 0 child on link 0 CPU: 00
5307 16:35:07.987780 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5308 16:35:07.987891 CPU: 00
5309 16:35:07.990922 Setting resources...
5310 16:35:07.994446 Root Device assign_resources, bus 0 link: 0
5311 16:35:07.997810 CPU_CLUSTER: 0 missing set_resources
5312 16:35:08.001494 Root Device assign_resources, bus 0 link: 0
5313 16:35:08.004514 Done setting resources.
5314 16:35:08.011485 Show resources in subtree (Root Device)...After assigning values.
5315 16:35:08.014383 Root Device child on link 0 CPU_CLUSTER: 0
5316 16:35:08.017824 CPU_CLUSTER: 0 child on link 0 CPU: 00
5317 16:35:08.027542 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5318 16:35:08.027757 CPU: 00
5319 16:35:08.031157 Done allocating resources.
5320 16:35:08.034285 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5321 16:35:08.037770 Enabling resources...
5322 16:35:08.037883 done.
5323 16:35:08.040738 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5324 16:35:08.044204 Initializing devices...
5325 16:35:08.044335 Root Device init ...
5326 16:35:08.047784 mainboard_init: Starting display init.
5327 16:35:08.050739 ADC[4]: Raw value=76301 ID=0
5328 16:35:08.074096 anx7625_power_on_init: Init interface.
5329 16:35:08.077805 anx7625_disable_pd_protocol: Disabled PD feature.
5330 16:35:08.084313 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5331 16:35:08.141345 anx7625_start_dp_work: Secure OCM version=00
5332 16:35:08.144621 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5333 16:35:08.161479 sp_tx_get_edid_block: EDID Block = 1
5334 16:35:08.278950 Extracted contents:
5335 16:35:08.281949 header: 00 ff ff ff ff ff ff 00
5336 16:35:08.285602 serial number: 06 af 5c 14 00 00 00 00 00 1a
5337 16:35:08.289139 version: 01 04
5338 16:35:08.292391 basic params: 95 1a 0e 78 02
5339 16:35:08.295357 chroma info: 99 85 95 55 56 92 28 22 50 54
5340 16:35:08.298461 established: 00 00 00
5341 16:35:08.304999 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5342 16:35:08.308621 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5343 16:35:08.315221 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5344 16:35:08.321843 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5345 16:35:08.328504 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5346 16:35:08.331679 extensions: 00
5347 16:35:08.331820 checksum: ae
5348 16:35:08.331939
5349 16:35:08.334909 Manufacturer: AUO Model 145c Serial Number 0
5350 16:35:08.338506 Made week 0 of 2016
5351 16:35:08.338654 EDID version: 1.4
5352 16:35:08.341575 Digital display
5353 16:35:08.345214 6 bits per primary color channel
5354 16:35:08.345368 DisplayPort interface
5355 16:35:08.348389 Maximum image size: 26 cm x 14 cm
5356 16:35:08.351759 Gamma: 220%
5357 16:35:08.351899 Check DPMS levels
5358 16:35:08.355297 Supported color formats: RGB 4:4:4
5359 16:35:08.358342 First detailed timing is preferred timing
5360 16:35:08.361370 Established timings supported:
5361 16:35:08.364958 Standard timings supported:
5362 16:35:08.365116 Detailed timings
5363 16:35:08.371541 Hex of detail: ce1d56ea50001a3030204600009010000018
5364 16:35:08.375217 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5365 16:35:08.378182 0556 0586 05a6 0640 hborder 0
5366 16:35:08.381726 0300 0304 030a 031a vborder 0
5367 16:35:08.385266 -hsync -vsync
5368 16:35:08.388163 Did detailed timing
5369 16:35:08.391895 Hex of detail: 0000000f0000000000000000000000000020
5370 16:35:08.394993 Manufacturer-specified data, tag 15
5371 16:35:08.401604 Hex of detail: 000000fe0041554f0a202020202020202020
5372 16:35:08.401756 ASCII string: AUO
5373 16:35:08.405114 Hex of detail: 000000fe004231313658414230312e34200a
5374 16:35:08.408128 ASCII string: B116XAB01.4
5375 16:35:08.408245 Checksum
5376 16:35:08.411464 Checksum: 0xae (valid)
5377 16:35:08.418521 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5378 16:35:08.418660 DSI data_rate: 457800000 bps
5379 16:35:08.425824 anx7625_parse_edid: set default k value to 0x3d for panel
5380 16:35:08.429044 anx7625_parse_edid: pixelclock(76300).
5381 16:35:08.432773 hactive(1366), hsync(32), hfp(48), hbp(154)
5382 16:35:08.435653 vactive(768), vsync(6), vfp(4), vbp(16)
5383 16:35:08.439068 anx7625_dsi_config: config dsi.
5384 16:35:08.447126 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5385 16:35:08.468260 anx7625_dsi_config: success to config DSI
5386 16:35:08.471107 anx7625_dp_start: MIPI phy setup OK.
5387 16:35:08.474936 [SSUSB] Setting up USB HOST controller...
5388 16:35:08.477813 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5389 16:35:08.481246 [SSUSB] phy power-on done.
5390 16:35:08.485266 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5391 16:35:08.488997 in-header: 03 fc 01 00 00 00 00 00
5392 16:35:08.489152 in-data:
5393 16:35:08.491922 handle_proto3_response: EC response with error code: 1
5394 16:35:08.495607 SPM: pcm index = 1
5395 16:35:08.498576 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5396 16:35:08.501774 CBFS @ 21000 size 3d4000
5397 16:35:08.508346 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5398 16:35:08.511823 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5399 16:35:08.514945 CBFS: Found @ offset 1e7c0 size 1026
5400 16:35:08.521531 read SPI 0x3f808 0x1026: 1272 us, 3250 KB/s, 26.000 Mbps
5401 16:35:08.525187 SPM: binary array size = 2988
5402 16:35:08.528275 SPM: version = pcm_allinone_v1.17.2_20180829
5403 16:35:08.531568 SPM binary loaded in 32 msecs
5404 16:35:08.539301 spm_kick_im_to_fetch: ptr = 000000004021eec2
5405 16:35:08.542383 spm_kick_im_to_fetch: len = 2988
5406 16:35:08.542580 SPM: spm_kick_pcm_to_run
5407 16:35:08.546283 SPM: spm_kick_pcm_to_run done
5408 16:35:08.549094 SPM: spm_init done in 52 msecs
5409 16:35:08.552818 Root Device init finished in 505262 usecs
5410 16:35:08.556092 CPU_CLUSTER: 0 init ...
5411 16:35:08.562704 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5412 16:35:08.569380 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5413 16:35:08.572436 CBFS @ 21000 size 3d4000
5414 16:35:08.576056 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5415 16:35:08.579194 CBFS: Locating 'sspm.bin'
5416 16:35:08.582612 CBFS: Found @ offset 208c0 size 41cb
5417 16:35:08.592663 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5418 16:35:08.600482 CPU_CLUSTER: 0 init finished in 42800 usecs
5419 16:35:08.600685 Devices initialized
5420 16:35:08.603644 Show all devs... After init.
5421 16:35:08.607053 Root Device: enabled 1
5422 16:35:08.607231 CPU_CLUSTER: 0: enabled 1
5423 16:35:08.610187 CPU: 00: enabled 1
5424 16:35:08.613718 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5425 16:35:08.616928 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5426 16:35:08.619913 ELOG: NV offset 0x558000 size 0x1000
5427 16:35:08.627800 read SPI 0x558000 0x1000: 1258 us, 3255 KB/s, 26.040 Mbps
5428 16:35:08.634653 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5429 16:35:08.637823 ELOG: Event(17) added with size 13 at 2024-06-17 16:35:08 UTC
5430 16:35:08.644341 out: cmd=0x121: 03 db 21 01 00 00 00 00
5431 16:35:08.647606 in-header: 03 86 00 00 2c 00 00 00
5432 16:35:08.657712 in-data: 40 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 06 e1 02 00 06 80 00 00 f9 2c 0b 00 06 80 00 00 c1 17 01 00 06 80 00 00 dd c5 02 00
5433 16:35:08.661233 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5434 16:35:08.664331 in-header: 03 19 00 00 08 00 00 00
5435 16:35:08.667513 in-data: a2 e0 47 00 13 00 00 00
5436 16:35:08.671001 Chrome EC: UHEPI supported
5437 16:35:08.677998 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5438 16:35:08.681080 in-header: 03 e1 00 00 08 00 00 00
5439 16:35:08.684197 in-data: 84 20 60 10 00 00 00 00
5440 16:35:08.687807 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5441 16:35:08.694237 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5442 16:35:08.697711 in-header: 03 e1 00 00 08 00 00 00
5443 16:35:08.700609 in-data: 84 20 60 10 00 00 00 00
5444 16:35:08.707416 ELOG: Event(A1) added with size 10 at 2024-06-17 16:35:08 UTC
5445 16:35:08.713818 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5446 16:35:08.717389 ELOG: Event(A0) added with size 9 at 2024-06-17 16:35:08 UTC
5447 16:35:08.724065 elog_add_boot_reason: Logged dev mode boot
5448 16:35:08.724146 Finalize devices...
5449 16:35:08.727169 Devices finalized
5450 16:35:08.730733 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5451 16:35:08.737298 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5452 16:35:08.740366 ELOG: Event(91) added with size 10 at 2024-06-17 16:35:08 UTC
5453 16:35:08.743920 Writing coreboot table at 0xffeda000
5454 16:35:08.747194 0. 0000000000114000-000000000011efff: RAMSTAGE
5455 16:35:08.753670 1. 0000000040000000-000000004023cfff: RAMSTAGE
5456 16:35:08.757525 2. 000000004023d000-00000000545fffff: RAM
5457 16:35:08.760412 3. 0000000054600000-000000005465ffff: BL31
5458 16:35:08.763544 4. 0000000054660000-00000000ffed9fff: RAM
5459 16:35:08.770807 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5460 16:35:08.773509 6. 0000000100000000-000000013fffffff: RAM
5461 16:35:08.777280 Passing 5 GPIOs to payload:
5462 16:35:08.780799 NAME | PORT | POLARITY | VALUE
5463 16:35:08.787057 write protect | 0x00000096 | low | low
5464 16:35:08.790718 EC in RW | 0x000000b1 | high | undefined
5465 16:35:08.793664 EC interrupt | 0x00000097 | low | undefined
5466 16:35:08.800252 TPM interrupt | 0x00000099 | high | undefined
5467 16:35:08.803564 speaker enable | 0x000000af | high | undefined
5468 16:35:08.807033 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5469 16:35:08.810745 in-header: 03 f7 00 00 02 00 00 00
5470 16:35:08.813647 in-data: 04 00
5471 16:35:08.813743 Board ID: 4
5472 16:35:08.817214 ADC[3]: Raw value=216068 ID=1
5473 16:35:08.817338 RAM code: 1
5474 16:35:08.817451 SKU ID: 16
5475 16:35:08.823856 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5476 16:35:08.824056 CBFS @ 21000 size 3d4000
5477 16:35:08.830921 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5478 16:35:08.837250 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum bfb0
5479 16:35:08.840330 coreboot table: 940 bytes.
5480 16:35:08.843875 IMD ROOT 0. 00000000fffff000 00001000
5481 16:35:08.847034 IMD SMALL 1. 00000000ffffe000 00001000
5482 16:35:08.850552 CONSOLE 2. 00000000fffde000 00020000
5483 16:35:08.853926 FMAP 3. 00000000fffdd000 0000047c
5484 16:35:08.856670 TIME STAMP 4. 00000000fffdc000 00000910
5485 16:35:08.860363 RAMOOPS 5. 00000000ffedc000 00100000
5486 16:35:08.863852 COREBOOT 6. 00000000ffeda000 00002000
5487 16:35:08.867021 IMD small region:
5488 16:35:08.869901 IMD ROOT 0. 00000000ffffec00 00000400
5489 16:35:08.873296 VBOOT WORK 1. 00000000ffffeb00 00000100
5490 16:35:08.876727 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5491 16:35:08.880263 VPD 3. 00000000ffffea60 0000006c
5492 16:35:08.886552 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5493 16:35:08.893493 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5494 16:35:08.896515 in-header: 03 e1 00 00 08 00 00 00
5495 16:35:08.899901 in-data: 84 20 60 10 00 00 00 00
5496 16:35:08.903343 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5497 16:35:08.906479 CBFS @ 21000 size 3d4000
5498 16:35:08.909820 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5499 16:35:08.913405 CBFS: Locating 'fallback/payload'
5500 16:35:08.921911 CBFS: Found @ offset dc040 size 439a0
5501 16:35:09.009775 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5502 16:35:09.013478 Checking segment from ROM address 0x0000000040003a00
5503 16:35:09.019848 Checking segment from ROM address 0x0000000040003a1c
5504 16:35:09.023656 Loading segment from ROM address 0x0000000040003a00
5505 16:35:09.026399 code (compression=0)
5506 16:35:09.036614 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5507 16:35:09.043276 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5508 16:35:09.046790 it's not compressed!
5509 16:35:09.049989 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5510 16:35:09.056533 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5511 16:35:09.064128 Loading segment from ROM address 0x0000000040003a1c
5512 16:35:09.067532 Entry Point 0x0000000080000000
5513 16:35:09.067669 Loaded segments
5514 16:35:09.073940 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5515 16:35:09.077809 Jumping to boot code at 0000000080000000(00000000ffeda000)
5516 16:35:09.087804 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5517 16:35:09.090526 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5518 16:35:09.093944 CBFS @ 21000 size 3d4000
5519 16:35:09.100520 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5520 16:35:09.104183 CBFS: Locating 'fallback/bl31'
5521 16:35:09.107439 CBFS: Found @ offset 36dc0 size 5820
5522 16:35:09.118061 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5523 16:35:09.121393 Checking segment from ROM address 0x0000000040003a00
5524 16:35:09.128050 Checking segment from ROM address 0x0000000040003a1c
5525 16:35:09.131678 Loading segment from ROM address 0x0000000040003a00
5526 16:35:09.134607 code (compression=1)
5527 16:35:09.141334 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5528 16:35:09.151437 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5529 16:35:09.151636 using LZMA
5530 16:35:09.159725 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5531 16:35:09.166958 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5532 16:35:09.169766 Loading segment from ROM address 0x0000000040003a1c
5533 16:35:09.173196 Entry Point 0x0000000054601000
5534 16:35:09.173379 Loaded segments
5535 16:35:09.176678 NOTICE: MT8183 bl31_setup
5536 16:35:09.183847 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5537 16:35:09.186802 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5538 16:35:09.190455 INFO: [DEVAPC] dump DEVAPC registers:
5539 16:35:09.200182 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5540 16:35:09.206904 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5541 16:35:09.216636 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5542 16:35:09.223184 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5543 16:35:09.233785 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5544 16:35:09.240180 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5545 16:35:09.249730 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5546 16:35:09.256755 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5547 16:35:09.266719 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5548 16:35:09.273271 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5549 16:35:09.280158 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5550 16:35:09.289790 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5551 16:35:09.296351 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5552 16:35:09.306649 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5553 16:35:09.312869 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5554 16:35:09.319589 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5555 16:35:09.326263 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5556 16:35:09.332683 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5557 16:35:09.342817 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5558 16:35:09.349568 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5559 16:35:09.355982 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5560 16:35:09.362581 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5561 16:35:09.366226 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5562 16:35:09.369337 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5563 16:35:09.372908 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5564 16:35:09.376453 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5565 16:35:09.379657 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5566 16:35:09.385963 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5567 16:35:09.392751 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5568 16:35:09.392910 WARNING: region 0:
5569 16:35:09.395806 WARNING: apc:0x168, sa:0x0, ea:0xfff
5570 16:35:09.399548 WARNING: region 1:
5571 16:35:09.402530 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5572 16:35:09.402642 WARNING: region 2:
5573 16:35:09.406094 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5574 16:35:09.409597 WARNING: region 3:
5575 16:35:09.412384 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5576 16:35:09.416052 WARNING: region 4:
5577 16:35:09.419063 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5578 16:35:09.419157 WARNING: region 5:
5579 16:35:09.422432 WARNING: apc:0x0, sa:0x0, ea:0x0
5580 16:35:09.425700 WARNING: region 6:
5581 16:35:09.429201 WARNING: apc:0x0, sa:0x0, ea:0x0
5582 16:35:09.429299 WARNING: region 7:
5583 16:35:09.432805 WARNING: apc:0x0, sa:0x0, ea:0x0
5584 16:35:09.439152 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5585 16:35:09.442505 INFO: SPM: enable SPMC mode
5586 16:35:09.445724 NOTICE: spm_boot_init() start
5587 16:35:09.449237 NOTICE: spm_boot_init() end
5588 16:35:09.452475 INFO: BL31: Initializing runtime services
5589 16:35:09.458886 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5590 16:35:09.462429 INFO: BL31: Preparing for EL3 exit to normal world
5591 16:35:09.465437 INFO: Entry point address = 0x80000000
5592 16:35:09.468928 INFO: SPSR = 0x8
5593 16:35:09.490000
5594 16:35:09.490136
5595 16:35:09.490201
5596 16:35:09.490726 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5597 16:35:09.490873 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5598 16:35:09.490987 Setting prompt string to ['jacuzzi:']
5599 16:35:09.491101 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5600 16:35:09.493504 Starting depthcharge on Juniper...
5601 16:35:09.493608
5602 16:35:09.496659 vboot_handoff: creating legacy vboot_handoff structure
5603 16:35:09.496813
5604 16:35:09.500145 ec_init(0): CrosEC protocol v3 supported (544, 544)
5605 16:35:09.500315
5606 16:35:09.504006 Wipe memory regions:
5607 16:35:09.504175
5608 16:35:09.506971 [0x00000040000000, 0x00000054600000)
5609 16:35:09.549485
5610 16:35:09.549657 [0x00000054660000, 0x00000080000000)
5611 16:35:09.641078
5612 16:35:09.641199 [0x000000811994a0, 0x000000ffeda000)
5613 16:35:09.901904
5614 16:35:09.902067 [0x00000100000000, 0x00000140000000)
5615 16:35:10.034705
5616 16:35:10.037772 Initializing XHCI USB controller at 0x11200000.
5617 16:35:10.061174
5618 16:35:10.064126 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5619 16:35:10.064212
5620 16:35:10.064279
5621 16:35:10.064547 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5623 16:35:10.164891 jacuzzi: tftpboot 192.168.201.1 14396137/tftp-deploy-tx65ao95/kernel/image.itb 14396137/tftp-deploy-tx65ao95/kernel/cmdline
5624 16:35:10.165139 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5625 16:35:10.165272 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5626 16:35:10.169486 tftpboot 192.168.201.1 14396137/tftp-deploy-tx65ao95/kernel/image.ittp-deploy-tx65ao95/kernel/cmdline
5627 16:35:10.169606
5628 16:35:10.169711 Waiting for link
5629 16:35:10.574844
5630 16:35:10.574988 R8152: Initializing
5631 16:35:10.575082
5632 16:35:10.578318 Version 9 (ocp_data = 6010)
5633 16:35:10.578424
5634 16:35:10.581092 R8152: Done initializing
5635 16:35:10.581190
5636 16:35:10.581278 Adding net device
5637 16:35:10.966772
5638 16:35:10.966891 done.
5639 16:35:10.966955
5640 16:35:10.967012 MAC: 00:e0:4c:72:3d:67
5641 16:35:10.967094
5642 16:35:10.970740 Sending DHCP discover... done.
5643 16:35:10.970816
5644 16:35:10.973662 Waiting for reply... done.
5645 16:35:10.973790
5646 16:35:10.977028 Sending DHCP request... done.
5647 16:35:10.977146
5648 16:35:10.981033 Waiting for reply... done.
5649 16:35:10.981143
5650 16:35:10.981234 My ip is 192.168.201.13
5651 16:35:10.981321
5652 16:35:10.984432 The DHCP server ip is 192.168.201.1
5653 16:35:10.984537
5654 16:35:10.991447 TFTP server IP predefined by user: 192.168.201.1
5655 16:35:10.991578
5656 16:35:10.998118 Bootfile predefined by user: 14396137/tftp-deploy-tx65ao95/kernel/image.itb
5657 16:35:10.998238
5658 16:35:10.998329 Sending tftp read request... done.
5659 16:35:11.001010
5660 16:35:11.004553 Waiting for the transfer...
5661 16:35:11.004665
5662 16:35:11.268180 00000000 ################################################################
5663 16:35:11.268301
5664 16:35:11.532272 00080000 ################################################################
5665 16:35:11.532395
5666 16:35:11.790276 00100000 ################################################################
5667 16:35:11.790406
5668 16:35:12.043929 00180000 ################################################################
5669 16:35:12.044073
5670 16:35:12.303147 00200000 ################################################################
5671 16:35:12.303269
5672 16:35:12.562036 00280000 ################################################################
5673 16:35:12.562193
5674 16:35:12.836450 00300000 ################################################################
5675 16:35:12.836596
5676 16:35:13.112260 00380000 ################################################################
5677 16:35:13.112400
5678 16:35:13.389314 00400000 ################################################################
5679 16:35:13.389476
5680 16:35:13.658604 00480000 ################################################################
5681 16:35:13.658775
5682 16:35:13.936870 00500000 ################################################################
5683 16:35:13.937031
5684 16:35:14.223986 00580000 ################################################################
5685 16:35:14.224152
5686 16:35:14.511649 00600000 ################################################################
5687 16:35:14.511788
5688 16:35:14.798546 00680000 ################################################################
5689 16:35:14.798714
5690 16:35:15.052685 00700000 ################################################################
5691 16:35:15.052806
5692 16:35:15.313128 00780000 ################################################################
5693 16:35:15.313272
5694 16:35:15.569501 00800000 ################################################################
5695 16:35:15.569628
5696 16:35:15.828204 00880000 ################################################################
5697 16:35:15.828335
5698 16:35:16.083806 00900000 ################################################################
5699 16:35:16.083953
5700 16:35:16.346337 00980000 ################################################################
5701 16:35:16.346459
5702 16:35:16.614313 00a00000 ################################################################
5703 16:35:16.614444
5704 16:35:16.873315 00a80000 ################################################################
5705 16:35:16.873479
5706 16:35:17.129688 00b00000 ################################################################
5707 16:35:17.129833
5708 16:35:17.393551 00b80000 ################################################################
5709 16:35:17.393685
5710 16:35:17.649113 00c00000 ################################################################
5711 16:35:17.649282
5712 16:35:17.901365 00c80000 ################################################################
5713 16:35:17.901534
5714 16:35:18.155985 00d00000 ################################################################
5715 16:35:18.156131
5716 16:35:18.482589 00d80000 ################################################################
5717 16:35:18.482712
5718 16:35:18.817186 00e00000 ################################################################
5719 16:35:18.817335
5720 16:35:19.066487 00e80000 ################################################################
5721 16:35:19.066609
5722 16:35:19.314641 00f00000 ################################################################
5723 16:35:19.314800
5724 16:35:19.576722 00f80000 ################################################################
5725 16:35:19.576862
5726 16:35:19.830410 01000000 ################################################################
5727 16:35:19.830538
5728 16:35:20.089870 01080000 ################################################################
5729 16:35:20.089994
5730 16:35:20.334368 01100000 ################################################################
5731 16:35:20.334485
5732 16:35:20.581950 01180000 ################################################################
5733 16:35:20.582085
5734 16:35:20.851645 01200000 ################################################################
5735 16:35:20.851804
5736 16:35:21.146634 01280000 ################################################################
5737 16:35:21.146782
5738 16:35:21.437317 01300000 ################################################################
5739 16:35:21.437487
5740 16:35:21.701877 01380000 ################################################################
5741 16:35:21.702057
5742 16:35:21.994868 01400000 ################################################################
5743 16:35:21.994981
5744 16:35:22.255852 01480000 ################################################################
5745 16:35:22.255966
5746 16:35:22.529887 01500000 ################################################################
5747 16:35:22.530035
5748 16:35:22.802401 01580000 ################################################################
5749 16:35:22.802521
5750 16:35:23.079305 01600000 ################################################################
5751 16:35:23.079422
5752 16:35:23.336332 01680000 ################################################################
5753 16:35:23.336450
5754 16:35:23.597647 01700000 ################################################################
5755 16:35:23.597766
5756 16:35:23.850394 01780000 ################################################################
5757 16:35:23.850516
5758 16:35:24.131260 01800000 ################################################################
5759 16:35:24.131386
5760 16:35:24.389823 01880000 ################################################################
5761 16:35:24.389965
5762 16:35:24.650725 01900000 ################################################################
5763 16:35:24.650873
5764 16:35:24.933974 01980000 ################################################################
5765 16:35:24.934127
5766 16:35:25.200859 01a00000 ################################################################
5767 16:35:25.201043
5768 16:35:25.469562 01a80000 ################################################################
5769 16:35:25.469709
5770 16:35:25.730959 01b00000 ################################################################
5771 16:35:25.731079
5772 16:35:25.992086 01b80000 ################################################################
5773 16:35:25.992235
5774 16:35:26.247929 01c00000 ################################################################
5775 16:35:26.248076
5776 16:35:26.505604 01c80000 ################################################################
5777 16:35:26.505749
5778 16:35:26.765225 01d00000 ################################################################
5779 16:35:26.765376
5780 16:35:27.029473 01d80000 ################################################################
5781 16:35:27.029622
5782 16:35:27.260532 01e00000 ########################################################### done.
5783 16:35:27.260674
5784 16:35:27.263855 The bootfile was 31932934 bytes long.
5785 16:35:27.263945
5786 16:35:27.267365 Sending tftp read request... done.
5787 16:35:27.267469
5788 16:35:27.267533 Waiting for the transfer...
5789 16:35:27.270576
5790 16:35:27.270680 00000000 # done.
5791 16:35:27.270773
5792 16:35:27.277385 Command line loaded dynamically from TFTP file: 14396137/tftp-deploy-tx65ao95/kernel/cmdline
5793 16:35:27.277503
5794 16:35:27.304254 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5795 16:35:27.304373
5796 16:35:27.304442 Loading FIT.
5797 16:35:27.306943
5798 16:35:27.307020 Image ramdisk-1 has 18744442 bytes.
5799 16:35:27.310695
5800 16:35:27.310783 Image fdt-1 has 57695 bytes.
5801 16:35:27.310861
5802 16:35:27.313766 Image kernel-1 has 13128753 bytes.
5803 16:35:27.313882
5804 16:35:27.323339 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5805 16:35:27.323457
5806 16:35:27.333321 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5807 16:35:27.337081
5808 16:35:27.340083 Choosing best match conf-1 for compat google,juniper-sku16.
5809 16:35:27.344987
5810 16:35:27.349332 Connected to device vid:did:rid of 1ae0:0028:00
5811 16:35:27.357502
5812 16:35:27.360588 tpm_get_response: command 0x17b, return code 0x0
5813 16:35:27.360675
5814 16:35:27.364444 tpm_cleanup: add release locality here.
5815 16:35:27.364526
5816 16:35:27.367430 Shutting down all USB controllers.
5817 16:35:27.367507
5818 16:35:27.371123 Removing current net device
5819 16:35:27.371207
5820 16:35:27.374145 Exiting depthcharge with code 4 at timestamp: 35135561
5821 16:35:27.374231
5822 16:35:27.377255 LZMA decompressing kernel-1 to 0x80193568
5823 16:35:27.377347
5824 16:35:27.384129 LZMA decompressing kernel-1 to 0x40000000
5825 16:35:29.248980
5826 16:35:29.249138 jumping to kernel
5827 16:35:29.249792 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5828 16:35:29.249929 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
5829 16:35:29.250048 Setting prompt string to ['Linux version [0-9]']
5830 16:35:29.250149 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5831 16:35:29.250263 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5832 16:35:29.324575
5833 16:35:29.327787 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5834 16:35:29.331099 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
5835 16:35:29.331221 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5836 16:35:29.331293 Setting prompt string to []
5837 16:35:29.331371 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5838 16:35:29.331463 Using line separator: #'\n'#
5839 16:35:29.331521 No login prompt set.
5840 16:35:29.331581 Parsing kernel messages
5841 16:35:29.331633 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5842 16:35:29.331737 [login-action] Waiting for messages, (timeout 00:04:07)
5843 16:35:29.331798 Waiting using forced prompt support (timeout 00:02:04)
5844 16:35:29.350731 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
5845 16:35:29.354474 [ 0.000000] random: crng init done
5846 16:35:29.360763 [ 0.000000] Machine model: Google juniper sku16 board
5847 16:35:29.364441 [ 0.000000] efi: UEFI not found.
5848 16:35:29.370853 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5849 16:35:29.380758 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5850 16:35:29.387687 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5851 16:35:29.390677 [ 0.000000] printk: bootconsole [mtk8250] enabled
5852 16:35:29.399678 [ 0.000000] NUMA: No NUMA configuration found
5853 16:35:29.406190 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5854 16:35:29.412851 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bda00-0x13f7bffff]
5855 16:35:29.412993 [ 0.000000] Zone ranges:
5856 16:35:29.419145 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5857 16:35:29.422800 [ 0.000000] DMA32 empty
5858 16:35:29.428951 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5859 16:35:29.432755 [ 0.000000] Movable zone start for each node
5860 16:35:29.435771 [ 0.000000] Early memory node ranges
5861 16:35:29.442398 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5862 16:35:29.449274 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5863 16:35:29.455970 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5864 16:35:29.462575 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5865 16:35:29.468757 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5866 16:35:29.475627 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5867 16:35:29.491718 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5868 16:35:29.498539 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5869 16:35:29.505033 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5870 16:35:29.508259 [ 0.000000] psci: probing for conduit method from DT.
5871 16:35:29.515267 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5872 16:35:29.518374 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5873 16:35:29.525203 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5874 16:35:29.528194 [ 0.000000] psci: SMC Calling Convention v1.1
5875 16:35:29.535082 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5876 16:35:29.538139 [ 0.000000] Detected VIPT I-cache on CPU0
5877 16:35:29.544703 [ 0.000000] CPU features: detected: GIC system register CPU interface
5878 16:35:29.551766 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5879 16:35:29.558348 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5880 16:35:29.561499 [ 0.000000] CPU features: detected: ARM erratum 845719
5881 16:35:29.568118 [ 0.000000] alternatives: applying boot alternatives
5882 16:35:29.571871 [ 0.000000] Fallback order for Node 0: 0
5883 16:35:29.578278 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5884 16:35:29.581420 [ 0.000000] Policy zone: Normal
5885 16:35:29.607711 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5886 16:35:29.621105 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5887 16:35:29.631377 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5888 16:35:29.638125 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5889 16:35:29.644298 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5890 16:35:29.650888 <6>[ 0.000000] software IO TLB: area num 8.
5891 16:35:29.675457 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5892 16:35:29.733316 <6>[ 0.000000] Memory: 3896764K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261700K reserved, 32768K cma-reserved)
5893 16:35:29.740182 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5894 16:35:29.746363 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5895 16:35:29.749504 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5896 16:35:29.756021 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5897 16:35:29.762698 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5898 16:35:29.766270 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5899 16:35:29.776001 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5900 16:35:29.782785 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5901 16:35:29.789206 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5902 16:35:29.799172 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5903 16:35:29.802906 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5904 16:35:29.806026 <6>[ 0.000000] GICv3: 640 SPIs implemented
5905 16:35:29.812961 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5906 16:35:29.815977 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5907 16:35:29.822493 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5908 16:35:29.828983 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5909 16:35:29.839135 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5910 16:35:29.852380 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5911 16:35:29.859286 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5912 16:35:29.870224 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5913 16:35:29.883588 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5914 16:35:29.889802 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5915 16:35:29.896700 <6>[ 0.009467] Console: colour dummy device 80x25
5916 16:35:29.900442 <6>[ 0.014511] printk: console [tty1] enabled
5917 16:35:29.913576 <6>[ 0.018899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5918 16:35:29.916679 <6>[ 0.029362] pid_max: default: 32768 minimum: 301
5919 16:35:29.920449 <6>[ 0.034244] LSM: Security Framework initializing
5920 16:35:29.929957 <6>[ 0.039161] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5921 16:35:29.936927 <6>[ 0.046784] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5922 16:35:29.942874 <4>[ 0.055666] cacheinfo: Unable to detect cache hierarchy for CPU 0
5923 16:35:29.953159 <6>[ 0.062294] cblist_init_generic: Setting adjustable number of callback queues.
5924 16:35:29.959629 <6>[ 0.069740] cblist_init_generic: Setting shift to 3 and lim to 1.
5925 16:35:29.966254 <6>[ 0.076092] cblist_init_generic: Setting adjustable number of callback queues.
5926 16:35:29.972606 <6>[ 0.083538] cblist_init_generic: Setting shift to 3 and lim to 1.
5927 16:35:29.975826 <6>[ 0.089935] rcu: Hierarchical SRCU implementation.
5928 16:35:29.982538 <6>[ 0.094961] rcu: Max phase no-delay instances is 1000.
5929 16:35:29.990351 <6>[ 0.102886] EFI services will not be available.
5930 16:35:29.993623 <6>[ 0.107831] smp: Bringing up secondary CPUs ...
5931 16:35:30.004272 <6>[ 0.113136] Detected VIPT I-cache on CPU1
5932 16:35:30.011002 <4>[ 0.113182] cacheinfo: Unable to detect cache hierarchy for CPU 1
5933 16:35:30.017355 <6>[ 0.113192] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5934 16:35:30.024057 <6>[ 0.113224] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5935 16:35:30.027243 <6>[ 0.113706] Detected VIPT I-cache on CPU2
5936 16:35:30.034048 <4>[ 0.113739] cacheinfo: Unable to detect cache hierarchy for CPU 2
5937 16:35:30.040547 <6>[ 0.113744] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5938 16:35:30.047022 <6>[ 0.113756] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5939 16:35:30.054004 <6>[ 0.114201] Detected VIPT I-cache on CPU3
5940 16:35:30.056993 <4>[ 0.114232] cacheinfo: Unable to detect cache hierarchy for CPU 3
5941 16:35:30.066873 <6>[ 0.114237] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5942 16:35:30.073803 <6>[ 0.114248] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5943 16:35:30.076941 <6>[ 0.114822] CPU features: detected: Spectre-v2
5944 16:35:30.080570 <6>[ 0.114832] CPU features: detected: Spectre-BHB
5945 16:35:30.087009 <6>[ 0.114836] CPU features: detected: ARM erratum 858921
5946 16:35:30.090091 <6>[ 0.114841] Detected VIPT I-cache on CPU4
5947 16:35:30.096743 <4>[ 0.114891] cacheinfo: Unable to detect cache hierarchy for CPU 4
5948 16:35:30.103700 <6>[ 0.114899] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5949 16:35:30.110454 <6>[ 0.114906] arch_timer: Enabling local workaround for ARM erratum 858921
5950 16:35:30.116829 <6>[ 0.114917] arch_timer: CPU4: Trapping CNTVCT access
5951 16:35:30.123627 <6>[ 0.114924] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5952 16:35:30.126716 <6>[ 0.115409] Detected VIPT I-cache on CPU5
5953 16:35:30.133514 <4>[ 0.115449] cacheinfo: Unable to detect cache hierarchy for CPU 5
5954 16:35:30.139787 <6>[ 0.115455] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5955 16:35:30.150198 <6>[ 0.115462] arch_timer: Enabling local workaround for ARM erratum 858921
5956 16:35:30.152982 <6>[ 0.115468] arch_timer: CPU5: Trapping CNTVCT access
5957 16:35:30.159880 <6>[ 0.115473] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5958 16:35:30.163306 <6>[ 0.115908] Detected VIPT I-cache on CPU6
5959 16:35:30.170259 <4>[ 0.115954] cacheinfo: Unable to detect cache hierarchy for CPU 6
5960 16:35:30.176660 <6>[ 0.115960] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5961 16:35:30.186513 <6>[ 0.115967] arch_timer: Enabling local workaround for ARM erratum 858921
5962 16:35:30.190217 <6>[ 0.115973] arch_timer: CPU6: Trapping CNTVCT access
5963 16:35:30.196705 <6>[ 0.115977] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5964 16:35:30.199901 <6>[ 0.116509] Detected VIPT I-cache on CPU7
5965 16:35:30.206449 <4>[ 0.116551] cacheinfo: Unable to detect cache hierarchy for CPU 7
5966 16:35:30.216498 <6>[ 0.116557] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5967 16:35:30.222895 <6>[ 0.116564] arch_timer: Enabling local workaround for ARM erratum 858921
5968 16:35:30.225934 <6>[ 0.116570] arch_timer: CPU7: Trapping CNTVCT access
5969 16:35:30.232713 <6>[ 0.116575] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5970 16:35:30.239649 <6>[ 0.116641] smp: Brought up 1 node, 8 CPUs
5971 16:35:30.242794 <6>[ 0.355510] SMP: Total of 8 processors activated.
5972 16:35:30.249678 <6>[ 0.360446] CPU features: detected: 32-bit EL0 Support
5973 16:35:30.252683 <6>[ 0.365817] CPU features: detected: 32-bit EL1 Support
5974 16:35:30.259518 <6>[ 0.371183] CPU features: detected: CRC32 instructions
5975 16:35:30.262434 <6>[ 0.376610] CPU: All CPU(s) started at EL2
5976 16:35:30.268973 <6>[ 0.380948] alternatives: applying system-wide alternatives
5977 16:35:30.276475 <6>[ 0.388932] devtmpfs: initialized
5978 16:35:30.288563 <6>[ 0.397871] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5979 16:35:30.298900 <6>[ 0.407819] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5980 16:35:30.302066 <6>[ 0.415546] pinctrl core: initialized pinctrl subsystem
5981 16:35:30.310455 <6>[ 0.422651] DMI not present or invalid.
5982 16:35:30.316642 <6>[ 0.427022] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5983 16:35:30.323619 <6>[ 0.433933] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5984 16:35:30.333045 <6>[ 0.441459] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5985 16:35:30.340010 <6>[ 0.449710] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5986 16:35:30.347004 <6>[ 0.457888] audit: initializing netlink subsys (disabled)
5987 16:35:30.353364 <5>[ 0.463592] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5988 16:35:30.360170 <6>[ 0.464573] thermal_sys: Registered thermal governor 'step_wise'
5989 16:35:30.366201 <6>[ 0.471558] thermal_sys: Registered thermal governor 'power_allocator'
5990 16:35:30.370049 <6>[ 0.477857] cpuidle: using governor menu
5991 16:35:30.376376 <6>[ 0.488818] NET: Registered PF_QIPCRTR protocol family
5992 16:35:30.382910 <6>[ 0.494314] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5993 16:35:30.389636 <6>[ 0.501410] ASID allocator initialised with 32768 entries
5994 16:35:30.396064 <6>[ 0.508175] Serial: AMBA PL011 UART driver
5995 16:35:30.405919 <4>[ 0.518582] Trying to register duplicate clock ID: 113
5996 16:35:30.465611 <6>[ 0.574813] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5997 16:35:30.480403 <6>[ 0.589156] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5998 16:35:30.483926 <6>[ 0.598906] KASLR enabled
5999 16:35:30.497645 <6>[ 0.606913] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
6000 16:35:30.504340 <6>[ 0.613915] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
6001 16:35:30.511314 <6>[ 0.620391] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
6002 16:35:30.517771 <6>[ 0.627382] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6003 16:35:30.524420 <6>[ 0.633856] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6004 16:35:30.531297 <6>[ 0.640846] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6005 16:35:30.538049 <6>[ 0.647320] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6006 16:35:30.544316 <6>[ 0.654309] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6007 16:35:30.547483 <6>[ 0.661874] ACPI: Interpreter disabled.
6008 16:35:30.557478 <6>[ 0.669872] iommu: Default domain type: Translated
6009 16:35:30.563686 <6>[ 0.674978] iommu: DMA domain TLB invalidation policy: strict mode
6010 16:35:30.567287 <5>[ 0.681609] SCSI subsystem initialized
6011 16:35:30.574078 <6>[ 0.686023] usbcore: registered new interface driver usbfs
6012 16:35:30.580732 <6>[ 0.691750] usbcore: registered new interface driver hub
6013 16:35:30.583848 <6>[ 0.697291] usbcore: registered new device driver usb
6014 16:35:30.591412 <6>[ 0.703592] pps_core: LinuxPPS API ver. 1 registered
6015 16:35:30.600905 <6>[ 0.708776] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6016 16:35:30.604365 <6>[ 0.718101] PTP clock support registered
6017 16:35:30.607887 <6>[ 0.722354] EDAC MC: Ver: 3.0.0
6018 16:35:30.615343 <6>[ 0.727984] FPGA manager framework
6019 16:35:30.622003 <6>[ 0.731665] Advanced Linux Sound Architecture Driver Initialized.
6020 16:35:30.625469 <6>[ 0.738416] vgaarb: loaded
6021 16:35:30.628851 <6>[ 0.741545] clocksource: Switched to clocksource arch_sys_counter
6022 16:35:30.635708 <5>[ 0.747975] VFS: Disk quotas dquot_6.6.0
6023 16:35:30.641951 <6>[ 0.752152] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6024 16:35:30.645099 <6>[ 0.759326] pnp: PnP ACPI: disabled
6025 16:35:30.653871 <6>[ 0.766234] NET: Registered PF_INET protocol family
6026 16:35:30.660168 <6>[ 0.771465] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6027 16:35:30.672057 <6>[ 0.781358] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6028 16:35:30.682295 <6>[ 0.790111] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6029 16:35:30.688844 <6>[ 0.798061] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6030 16:35:30.695783 <6>[ 0.806294] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6031 16:35:30.702250 <6>[ 0.814391] TCP: Hash tables configured (established 32768 bind 32768)
6032 16:35:30.712669 <6>[ 0.821217] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6033 16:35:30.718988 <6>[ 0.828189] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6034 16:35:30.725564 <6>[ 0.835671] NET: Registered PF_UNIX/PF_LOCAL protocol family
6035 16:35:30.728977 <6>[ 0.841749] RPC: Registered named UNIX socket transport module.
6036 16:35:30.735731 <6>[ 0.847891] RPC: Registered udp transport module.
6037 16:35:30.738601 <6>[ 0.852815] RPC: Registered tcp transport module.
6038 16:35:30.745577 <6>[ 0.857738] RPC: Registered tcp NFSv4.1 backchannel transport module.
6039 16:35:30.751639 <6>[ 0.864390] PCI: CLS 0 bytes, default 64
6040 16:35:30.755399 <6>[ 0.868676] Unpacking initramfs...
6041 16:35:30.780669 <6>[ 0.889701] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6042 16:35:30.790646 <6>[ 0.898453] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6043 16:35:30.793538 <6>[ 0.907360] kvm [1]: IPA Size Limit: 40 bits
6044 16:35:30.800957 <6>[ 0.913715] kvm [1]: vgic-v2@c420000
6045 16:35:30.804718 <6>[ 0.917547] kvm [1]: GIC system register CPU interface enabled
6046 16:35:30.810911 <6>[ 0.923731] kvm [1]: vgic interrupt IRQ18
6047 16:35:30.814032 <6>[ 0.928097] kvm [1]: Hyp mode initialized successfully
6048 16:35:30.822070 <5>[ 0.934477] Initialise system trusted keyrings
6049 16:35:30.828585 <6>[ 0.939328] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6050 16:35:30.837098 <6>[ 0.949300] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6051 16:35:30.843553 <5>[ 0.955730] NFS: Registering the id_resolver key type
6052 16:35:30.847011 <5>[ 0.961042] Key type id_resolver registered
6053 16:35:30.853355 <5>[ 0.965454] Key type id_legacy registered
6054 16:35:30.859974 <6>[ 0.969758] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6055 16:35:30.866777 <6>[ 0.976678] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6056 16:35:30.873121 <6>[ 0.984427] 9p: Installing v9fs 9p2000 file system support
6057 16:35:30.901585 <5>[ 1.013730] Key type asymmetric registered
6058 16:35:30.904600 <5>[ 1.018073] Asymmetric key parser 'x509' registered
6059 16:35:30.914650 <6>[ 1.023226] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6060 16:35:30.917796 <6>[ 1.030844] io scheduler mq-deadline registered
6061 16:35:30.921476 <6>[ 1.035601] io scheduler kyber registered
6062 16:35:30.943786 <6>[ 1.056387] EINJ: ACPI disabled.
6063 16:35:30.950284 <4>[ 1.060148] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6064 16:35:30.988110 <6>[ 1.100517] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6065 16:35:30.996149 <6>[ 1.108864] printk: console [ttyS0] disabled
6066 16:35:31.024302 <6>[ 1.133514] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6067 16:35:31.031134 <6>[ 1.142986] printk: console [ttyS0] enabled
6068 16:35:31.034235 <6>[ 1.142986] printk: console [ttyS0] enabled
6069 16:35:31.040855 <6>[ 1.151903] printk: bootconsole [mtk8250] disabled
6070 16:35:31.044519 <6>[ 1.151903] printk: bootconsole [mtk8250] disabled
6071 16:35:31.054267 <3>[ 1.162396] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6072 16:35:31.060775 <3>[ 1.170777] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6073 16:35:31.090213 <6>[ 1.199164] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6074 16:35:31.096966 <6>[ 1.208808] serial serial0: tty port ttyS1 registered
6075 16:35:31.103211 <6>[ 1.215230] SuperH (H)SCI(F) driver initialized
6076 16:35:31.106717 <6>[ 1.220689] msm_serial: driver initialized
6077 16:35:31.121654 <6>[ 1.230902] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6078 16:35:31.131668 <6>[ 1.239487] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6079 16:35:31.138365 <6>[ 1.248055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6080 16:35:31.148272 <6>[ 1.256620] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6081 16:35:31.155020 <6>[ 1.265269] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6082 16:35:31.164501 <6>[ 1.273932] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6083 16:35:31.174773 <6>[ 1.282670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6084 16:35:31.181252 <6>[ 1.291407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6085 16:35:31.191252 <6>[ 1.299971] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6086 16:35:31.201054 <6>[ 1.308764] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6087 16:35:31.208250 <4>[ 1.320995] cacheinfo: Unable to detect cache hierarchy for CPU 0
6088 16:35:31.218180 <6>[ 1.330377] loop: module loaded
6089 16:35:31.229407 <6>[ 1.342112] vsim1: Bringing 1800000uV into 2700000-2700000uV
6090 16:35:31.246989 <6>[ 1.359766] megasas: 07.719.03.00-rc1
6091 16:35:31.256036 <6>[ 1.368406] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6092 16:35:31.264538 <6>[ 1.376949] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6093 16:35:31.281229 <6>[ 1.393690] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6094 16:35:31.337843 <6>[ 1.443724] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6095 16:35:31.376376 <6>[ 1.488563] Freeing initrd memory: 18300K
6096 16:35:31.391422 <4>[ 1.500396] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6097 16:35:31.397910 <4>[ 1.509627] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6098 16:35:31.404668 <4>[ 1.516326] Hardware name: Google juniper sku16 board (DT)
6099 16:35:31.407887 <4>[ 1.522065] Call trace:
6100 16:35:31.411633 <4>[ 1.524765] dump_backtrace.part.0+0xe0/0xf0
6101 16:35:31.414628 <4>[ 1.529302] show_stack+0x18/0x30
6102 16:35:31.418181 <4>[ 1.532874] dump_stack_lvl+0x68/0x84
6103 16:35:31.421690 <4>[ 1.536795] dump_stack+0x18/0x34
6104 16:35:31.427955 <4>[ 1.540365] sysfs_warn_dup+0x64/0x80
6105 16:35:31.431805 <4>[ 1.544286] sysfs_do_create_link_sd+0xf0/0x100
6106 16:35:31.434929 <4>[ 1.549073] sysfs_create_link+0x20/0x40
6107 16:35:31.437993 <4>[ 1.553253] bus_add_device+0x68/0x10c
6108 16:35:31.444740 <4>[ 1.557259] device_add+0x340/0x7ac
6109 16:35:31.448317 <4>[ 1.561002] of_device_add+0x44/0x60
6110 16:35:31.451484 <4>[ 1.564836] of_platform_device_create_pdata+0x90/0x120
6111 16:35:31.458198 <4>[ 1.570318] of_platform_bus_create+0x170/0x370
6112 16:35:31.461237 <4>[ 1.575104] of_platform_populate+0x50/0xfc
6113 16:35:31.467902 <4>[ 1.579544] parse_mtd_partitions+0x1dc/0x510
6114 16:35:31.471410 <4>[ 1.584157] mtd_device_parse_register+0xf8/0x2e0
6115 16:35:31.475217 <4>[ 1.589115] spi_nor_probe+0x21c/0x2f0
6116 16:35:31.478314 <4>[ 1.593121] spi_mem_probe+0x6c/0xb0
6117 16:35:31.481954 <4>[ 1.596954] spi_probe+0x84/0xe4
6118 16:35:31.485123 <4>[ 1.600435] really_probe+0xbc/0x2e0
6119 16:35:31.491741 <4>[ 1.604265] __driver_probe_device+0x78/0x11c
6120 16:35:31.495412 <4>[ 1.608878] driver_probe_device+0xd8/0x160
6121 16:35:31.501661 <4>[ 1.613316] __device_attach_driver+0xb8/0x134
6122 16:35:31.505307 <4>[ 1.618015] bus_for_each_drv+0x78/0xd0
6123 16:35:31.508357 <4>[ 1.622105] __device_attach+0xa8/0x1c0
6124 16:35:31.511492 <4>[ 1.626196] device_initial_probe+0x14/0x20
6125 16:35:31.518173 <4>[ 1.630634] bus_probe_device+0x9c/0xa4
6126 16:35:31.521883 <4>[ 1.634724] device_add+0x3ac/0x7ac
6127 16:35:31.525385 <4>[ 1.638466] __spi_add_device+0x78/0x120
6128 16:35:31.528297 <4>[ 1.642645] spi_add_device+0x40/0x7c
6129 16:35:31.535187 <4>[ 1.646562] spi_register_controller+0x610/0xad0
6130 16:35:31.538402 <4>[ 1.651435] devm_spi_register_controller+0x4c/0xa4
6131 16:35:31.541897 <4>[ 1.656568] mtk_spi_probe+0x3f8/0x650
6132 16:35:31.548795 <4>[ 1.660573] platform_probe+0x68/0xe0
6133 16:35:31.551645 <4>[ 1.664491] really_probe+0xbc/0x2e0
6134 16:35:31.555356 <4>[ 1.668322] __driver_probe_device+0x78/0x11c
6135 16:35:31.558544 <4>[ 1.672933] driver_probe_device+0xd8/0x160
6136 16:35:31.565232 <4>[ 1.677371] __driver_attach+0x94/0x19c
6137 16:35:31.568263 <4>[ 1.681462] bus_for_each_dev+0x70/0xd0
6138 16:35:31.572022 <4>[ 1.685552] driver_attach+0x24/0x30
6139 16:35:31.575081 <4>[ 1.689381] bus_add_driver+0x154/0x20c
6140 16:35:31.581859 <4>[ 1.693472] driver_register+0x78/0x130
6141 16:35:31.584824 <4>[ 1.697563] __platform_driver_register+0x28/0x34
6142 16:35:31.588047 <4>[ 1.702522] mtk_spi_driver_init+0x1c/0x28
6143 16:35:31.594838 <4>[ 1.706876] do_one_initcall+0x50/0x1d0
6144 16:35:31.598057 <4>[ 1.710967] kernel_init_freeable+0x21c/0x288
6145 16:35:31.601795 <4>[ 1.715581] kernel_init+0x24/0x12c
6146 16:35:31.604913 <4>[ 1.719326] ret_from_fork+0x10/0x20
6147 16:35:31.615624 <6>[ 1.728251] tun: Universal TUN/TAP device driver, 1.6
6148 16:35:31.619033 <6>[ 1.734537] thunder_xcv, ver 1.0
6149 16:35:31.622760 <6>[ 1.738056] thunder_bgx, ver 1.0
6150 16:35:31.625941 <6>[ 1.741562] nicpf, ver 1.0
6151 16:35:31.637319 <6>[ 1.745935] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6152 16:35:31.640459 <6>[ 1.753420] hns3: Copyright (c) 2017 Huawei Corporation.
6153 16:35:31.643557 <6>[ 1.759018] hclge is initializing
6154 16:35:31.650510 <6>[ 1.762602] e1000: Intel(R) PRO/1000 Network Driver
6155 16:35:31.657329 <6>[ 1.767737] e1000: Copyright (c) 1999-2006 Intel Corporation.
6156 16:35:31.660392 <6>[ 1.773759] e1000e: Intel(R) PRO/1000 Network Driver
6157 16:35:31.666733 <6>[ 1.778980] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6158 16:35:31.673299 <6>[ 1.785172] igb: Intel(R) Gigabit Ethernet Network Driver
6159 16:35:31.680101 <6>[ 1.790827] igb: Copyright (c) 2007-2014 Intel Corporation.
6160 16:35:31.686758 <6>[ 1.796670] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6161 16:35:31.693537 <6>[ 1.803193] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6162 16:35:31.696650 <6>[ 1.809753] sky2: driver version 1.30
6163 16:35:31.703442 <6>[ 1.815001] usbcore: registered new device driver r8152-cfgselector
6164 16:35:31.710348 <6>[ 1.821553] usbcore: registered new interface driver r8152
6165 16:35:31.717100 <6>[ 1.827380] VFIO - User Level meta-driver version: 0.3
6166 16:35:31.723476 <6>[ 1.835202] mtu3 11201000.usb: uwk - reg:0x420, version:101
6167 16:35:31.730600 <4>[ 1.841075] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6168 16:35:31.736712 <6>[ 1.848356] mtu3 11201000.usb: dr_mode: 1, drd: auto
6169 16:35:31.743367 <6>[ 1.853584] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6170 16:35:31.747166 <6>[ 1.859774] mtu3 11201000.usb: usb3-drd: 0
6171 16:35:31.753804 <6>[ 1.865343] mtu3 11201000.usb: xHCI platform device register success...
6172 16:35:31.764913 <4>[ 1.874064] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6173 16:35:31.771921 <6>[ 1.882038] xhci-mtk 11200000.usb: xHCI Host Controller
6174 16:35:31.778514 <6>[ 1.887550] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6175 16:35:31.785193 <6>[ 1.895270] xhci-mtk 11200000.usb: USB3 root hub has no ports
6176 16:35:31.791858 <6>[ 1.901279] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6177 16:35:31.798057 <6>[ 1.910706] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6178 16:35:31.805000 <6>[ 1.916781] xhci-mtk 11200000.usb: xHCI Host Controller
6179 16:35:31.811925 <6>[ 1.922269] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6180 16:35:31.818176 <6>[ 1.929925] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6181 16:35:31.821960 <6>[ 1.936746] hub 1-0:1.0: USB hub found
6182 16:35:31.828392 <6>[ 1.940775] hub 1-0:1.0: 1 port detected
6183 16:35:31.837872 <6>[ 1.946162] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6184 16:35:31.841514 <6>[ 1.954770] hub 2-0:1.0: USB hub found
6185 16:35:31.847905 <3>[ 1.958802] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6186 16:35:31.854796 <6>[ 1.966715] usbcore: registered new interface driver usb-storage
6187 16:35:31.861349 <6>[ 1.973301] usbcore: registered new device driver onboard-usb-hub
6188 16:35:31.872360 <4>[ 1.981655] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6189 16:35:31.881546 <6>[ 1.993918] mt6397-rtc mt6358-rtc: registered as rtc0
6190 16:35:31.891154 <6>[ 1.999396] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-17T16:35:31 UTC (1718642131)
6191 16:35:31.894761 <6>[ 2.009294] i2c_dev: i2c /dev entries driver
6192 16:35:31.906371 <6>[ 2.015701] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6193 16:35:31.916370 <6>[ 2.024085] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6194 16:35:31.923202 <6>[ 2.032991] i2c 4-0058: Fixed dependency cycle(s) with /panel
6195 16:35:31.929860 <6>[ 2.039060] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6196 16:35:31.936308 <3>[ 2.046518] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6197 16:35:31.953962 <6>[ 2.066527] cpu cpu0: EM: created perf domain
6198 16:35:31.964033 <6>[ 2.072013] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6199 16:35:31.970604 <6>[ 2.083295] cpu cpu4: EM: created perf domain
6200 16:35:31.978239 <6>[ 2.090367] sdhci: Secure Digital Host Controller Interface driver
6201 16:35:31.984378 <6>[ 2.096825] sdhci: Copyright(c) Pierre Ossman
6202 16:35:31.991092 <6>[ 2.102237] Synopsys Designware Multimedia Card Interface Driver
6203 16:35:31.998222 <6>[ 2.102728] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6204 16:35:32.001180 <6>[ 2.109304] sdhci-pltfm: SDHCI platform and OF driver helper
6205 16:35:32.009392 <6>[ 2.121787] ledtrig-cpu: registered to indicate activity on CPUs
6206 16:35:32.017468 <6>[ 2.129501] usbcore: registered new interface driver usbhid
6207 16:35:32.020740 <6>[ 2.135342] usbhid: USB HID core driver
6208 16:35:32.031183 <6>[ 2.139606] spi_master spi2: will run message pump with realtime priority
6209 16:35:32.034963 <4>[ 2.139618] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6210 16:35:32.044916 <4>[ 2.153870] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6211 16:35:32.055003 <6>[ 2.158308] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6212 16:35:32.074516 <6>[ 2.177206] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6213 16:35:32.081608 <4>[ 2.187047] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6214 16:35:32.088403 <6>[ 2.198345] cros-ec-spi spi2.0: Chrome EC device registered
6215 16:35:32.098856 <4>[ 2.207844] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6216 16:35:32.105529 <6>[ 2.218053] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x12c14
6217 16:35:32.115810 <4>[ 2.224447] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6218 16:35:32.118638 <6>[ 2.225870] mmc0: new HS400 MMC card at address 0001
6219 16:35:32.126139 <4>[ 2.238243] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6220 16:35:32.132342 <6>[ 2.239157] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6221 16:35:32.142926 <6>[ 2.255340] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6222 16:35:32.153178 <6>[ 2.261924] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6223 16:35:32.156050 <6>[ 2.264305] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6224 16:35:32.163198 <6>[ 2.275701] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6225 16:35:32.169768 <6>[ 2.282170] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6226 16:35:32.211858 <6>[ 2.317845] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6227 16:35:32.222231 <6>[ 2.330256] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6228 16:35:32.234627 <6>[ 2.343640] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6229 16:35:32.253822 <6>[ 2.359569] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6230 16:35:32.260472 <6>[ 2.365727] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6231 16:35:32.263990 <6>[ 2.372850] NET: Registered PF_PACKET protocol family
6232 16:35:32.270426 <6>[ 2.382769] 9pnet: Installing 9P2000 support
6233 16:35:32.273854 <5>[ 2.387381] Key type dns_resolver registered
6234 16:35:32.280549 <6>[ 2.392604] registered taskstats version 1
6235 16:35:32.283613 <5>[ 2.396990] Loading compiled-in X.509 certificates
6236 16:35:32.334226 <3>[ 2.443457] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6237 16:35:32.364867 <6>[ 2.470636] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6238 16:35:32.375356 <6>[ 2.484454] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6239 16:35:32.385027 <6>[ 2.493026] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6240 16:35:32.391796 <6>[ 2.501561] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6241 16:35:32.401938 <6>[ 2.510089] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6242 16:35:32.408251 <6>[ 2.518614] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6243 16:35:32.418159 <6>[ 2.527136] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6244 16:35:32.421695 <6>[ 2.529288] hub 1-1:1.0: USB hub found
6245 16:35:32.431480 <6>[ 2.535653] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6246 16:35:32.434531 <6>[ 2.540122] hub 1-1:1.0: 3 ports detected
6247 16:35:32.441428 <6>[ 2.548830] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6248 16:35:32.448157 <6>[ 2.559864] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6249 16:35:32.454968 <6>[ 2.567117] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6250 16:35:32.465446 <6>[ 2.574447] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6251 16:35:32.471889 <6>[ 2.581933] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6252 16:35:32.478241 <6>[ 2.590256] panfrost 13040000.gpu: clock rate = 511999970
6253 16:35:32.488641 <6>[ 2.595945] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6254 16:35:32.498260 <6>[ 2.606182] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6255 16:35:32.504952 <6>[ 2.614217] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6256 16:35:32.518015 <6>[ 2.622651] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6257 16:35:32.524833 <6>[ 2.634729] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6258 16:35:32.536780 <6>[ 2.645634] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6259 16:35:32.546743 <6>[ 2.654777] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6260 16:35:32.556816 <6>[ 2.663950] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6261 16:35:32.566289 <6>[ 2.673080] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6262 16:35:32.573056 <6>[ 2.682208] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6263 16:35:32.583189 <6>[ 2.691508] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6264 16:35:32.592807 <6>[ 2.700808] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6265 16:35:32.602680 <6>[ 2.710284] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6266 16:35:32.613008 <6>[ 2.719759] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6267 16:35:32.619266 <6>[ 2.728886] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6268 16:35:32.691884 <6>[ 2.800802] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6269 16:35:32.701333 <6>[ 2.810032] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6270 16:35:32.713084 <6>[ 2.822260] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6271 16:35:32.732407 <6>[ 2.841902] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6272 16:35:33.398402 <6>[ 3.030258] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6273 16:35:33.408177 <4>[ 3.133279] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6274 16:35:33.415161 <4>[ 3.133298] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6275 16:35:33.421650 <6>[ 3.171085] r8152 1-1.2:1.0 eth0: v1.12.13
6276 16:35:33.428274 <6>[ 3.249577] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6277 16:35:33.434779 <6>[ 3.491142] Console: switching to colour frame buffer device 170x48
6278 16:35:33.441557 <6>[ 3.551787] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6279 16:35:33.461975 <6>[ 3.567838] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6280 16:35:33.478839 <6>[ 3.584498] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6281 16:35:33.489115 <6>[ 3.598271] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6282 16:35:33.495978 <6>[ 3.606618] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6283 16:35:33.508985 <6>[ 3.610944] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6284 16:35:33.523915 <6>[ 3.629877] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6285 16:35:34.661368 <6>[ 4.773815] r8152 1-1.2:1.0 eth0: carrier on
6286 16:35:34.705098 <5>[ 4.801578] Sending DHCP requests ., OK
6287 16:35:34.711744 <6>[ 4.821948] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6288 16:35:34.715523 <6>[ 4.830397] IP-Config: Complete:
6289 16:35:34.728483 <6>[ 4.833963] device=eth0, hwaddr=00:e0:4c:72:3d:67, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6290 16:35:34.735221 <6>[ 4.844860] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1, domain=lava-rack, nis-domain=(none)
6291 16:35:34.750187 <6>[ 4.859143] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6292 16:35:34.758515 <6>[ 4.859153] nameserver0=192.168.201.1
6293 16:35:34.766597 <6>[ 4.878848] clk: Disabling unused clocks
6294 16:35:34.770985 <6>[ 4.886829] ALSA device list:
6295 16:35:34.780132 <6>[ 4.892847] No soundcards found.
6296 16:35:34.789581 <6>[ 4.902008] Freeing unused kernel memory: 8512K
6297 16:35:34.796910 <6>[ 4.909148] Run /init as init process
6298 16:35:34.807970 Loading, please wait...
6299 16:35:34.845172 Starting systemd-udevd version 252.22-1~deb12u1
6300 16:35:35.175573 <6>[ 5.285005] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6301 16:35:35.191379 <4>[ 5.300386] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6302 16:35:35.207809 <3>[ 5.313063] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6303 16:35:35.217520 <6>[ 5.316104] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6304 16:35:35.223874 <3>[ 5.323269] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6305 16:35:35.230674 <4>[ 5.335732] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6306 16:35:35.240562 <6>[ 5.339147] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6307 16:35:35.250637 <3>[ 5.340062] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6308 16:35:35.263905 <3>[ 5.342354] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6309 16:35:35.274481 <4>[ 5.351406] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6310 16:35:35.281495 <3>[ 5.358280] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6311 16:35:35.287507 <3>[ 5.358302] elan_i2c 2-0015: Error applying setting, reverse things back
6312 16:35:35.297874 <6>[ 5.383805] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6313 16:35:35.300925 <6>[ 5.384549] mc: Linux media interface: v0.10
6314 16:35:35.311361 <6>[ 5.388276] cs_system_cfg: CoreSight Configuration manager initialised
6315 16:35:35.321789 <3>[ 5.390858] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6316 16:35:35.327979 <5>[ 5.401413] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6317 16:35:35.337753 <3>[ 5.406353] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6318 16:35:35.344560 <5>[ 5.429651] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6319 16:35:35.354412 <3>[ 5.438245] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6320 16:35:35.364588 <5>[ 5.454904] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6321 16:35:35.370864 <3>[ 5.456483] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6322 16:35:35.381650 <4>[ 5.463205] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6323 16:35:35.388348 <6>[ 5.463213] cfg80211: failed to load regulatory.db
6324 16:35:35.398302 <6>[ 5.502620] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6325 16:35:35.404509 <3>[ 5.505555] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6326 16:35:35.412944 <6>[ 5.524920] videodev: Linux video capture interface: v2.00
6327 16:35:35.422798 <3>[ 5.525428] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6328 16:35:35.425785 <3>[ 5.525567] mtk-scp 10500000.scp: invalid resource
6329 16:35:35.435692 <6>[ 5.525628] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6330 16:35:35.439428 <6>[ 5.526960] remoteproc remoteproc0: scp is available
6331 16:35:35.449355 <4>[ 5.527065] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6332 16:35:35.452350 <6>[ 5.527073] remoteproc remoteproc0: powering up scp
6333 16:35:35.462256 <4>[ 5.527099] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6334 16:35:35.469134 <3>[ 5.527104] remoteproc remoteproc0: request_firmware failed: -2
6335 16:35:35.479171 <6>[ 5.532287] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6336 16:35:35.485878 <3>[ 5.539400] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6337 16:35:35.492487 <6>[ 5.544623] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6338 16:35:35.505295 <3>[ 5.544696] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6339 16:35:35.512641 <3>[ 5.545755] debugfs: File 'Playback' in directory 'dapm' already present!
6340 16:35:35.518708 <3>[ 5.545766] debugfs: File 'Capture' in directory 'dapm' already present!
6341 16:35:35.533113 <6>[ 5.547286] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6342 16:35:35.536360 <3>[ 5.549991] thermal_sys: Failed to find 'trips' node
6343 16:35:35.543014 <3>[ 5.549996] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6344 16:35:35.552969 <3>[ 5.550005] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6345 16:35:35.559253 <4>[ 5.550010] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6346 16:35:35.569191 <3>[ 5.552036] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6347 16:35:35.572270 <6>[ 5.552419] Bluetooth: Core ver 2.22
6348 16:35:35.579582 <6>[ 5.552466] NET: Registered PF_BLUETOOTH protocol family
6349 16:35:35.585844 <6>[ 5.552469] Bluetooth: HCI device and connection manager initialized
6350 16:35:35.592708 <6>[ 5.552481] Bluetooth: HCI socket layer initialized
6351 16:35:35.599411 <6>[ 5.552485] Bluetooth: L2CAP socket layer initialized
6352 16:35:35.606293 <6>[ 5.552492] Bluetooth: SCO socket layer initialized
6353 16:35:35.609386 <3>[ 5.552873] thermal_sys: Failed to find 'trips' node
6354 16:35:35.619675 <3>[ 5.552879] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6355 16:35:35.626404 <3>[ 5.552890] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6356 16:35:35.637314 <4>[ 5.552895] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6357 16:35:35.643752 <6>[ 5.557269] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6358 16:35:35.650792 <6>[ 5.581415] Bluetooth: HCI UART driver ver 2.3
6359 16:35:35.660810 <6>[ 5.587120] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6360 16:35:35.664052 <6>[ 5.594849] Bluetooth: HCI UART protocol H4 registered
6361 16:35:35.674322 <6>[ 5.595508] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6362 16:35:35.681149 <6>[ 5.595552] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6363 16:35:35.687531 <6>[ 5.595961] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6364 16:35:35.697396 <6>[ 5.596128] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6365 16:35:35.704160 <6>[ 5.596266] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6366 16:35:35.711062 <6>[ 5.603506] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6367 16:35:35.717817 <6>[ 5.611309] Bluetooth: HCI UART protocol LL registered
6368 16:35:35.730969 <6>[ 5.614585] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6369 16:35:35.737675 <6>[ 5.614784] usbcore: registered new interface driver uvcvideo
6370 16:35:35.747379 <6>[ 5.630143] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6371 16:35:35.753912 <6>[ 5.630920] Bluetooth: HCI UART protocol Three-wire (H5) registered
6372 16:35:35.760622 <6>[ 5.637932] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6373 16:35:35.770262 <6>[ 5.643322] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6374 16:35:35.785546 <6>[ 5.643334] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6375 16:35:35.802684 <6>[ 5.643669] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6376 16:35:35.812627 <6>[ 5.648883] Bluetooth: HCI UART protocol Broadcom registered
6377 16:35:35.827213 <6>[ 5.653944] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6378 16:35:35.837418 <6>[ 5.661097] Bluetooth: HCI UART protocol QCA registered
6379 16:35:35.848321 <6>[ 5.662385] Bluetooth: hci0: setting up ROME/QCA6390
6380 16:35:35.854957 <6>[ 5.791905] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6381 16:35:35.864792 Begin: Loading essential drivers<6>[ 5.797266] Bluetooth: HCI UART protocol Marvell registered
6382 16:35:35.864898 ... done.
6383 16:35:35.871205 Begin: Running /<3>[ 5.877013] Bluetooth: hci0: Frame reassembly failed (-84)
6384 16:35:35.874554 scripts/init-premount ... done.
6385 16:35:35.884326 <4>[ 5.960640] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6386 16:35:35.888177 <4>[ 5.960640] Fallback method does not support PEC.
6387 16:35:35.888273
6388 16:35:35.897577 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6389 16:35:35.904131 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6390 16:35:35.907811 Device /sys/class/net/eth0 found
6391 16:35:35.907917 done.
6392 16:35:35.917712 Begin: Waiting up to 180 secs for any network device to become available ... done.
6393 16:35:35.933160 <3>[ 6.042027] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6394 16:35:35.948687 <3>[ 6.057625] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6395 16:35:35.965105 IP-Config: eth0 hardware address 00:e0:4c:72:3d:67 mtu 1500 DHCP
6396 16:35:35.972063 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6397 16:35:35.978478 address: 192.168.201.13 broadcast: 192.168.201.255 netmask: 255.255.255.0
6398 16:35:35.985229 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6399 16:35:35.992117 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-1
6400 16:35:35.998410 domain : lava-rack
6401 16:35:36.001481 rootserver: 192.168.201.1 rootpath:
6402 16:35:36.001569 filename :
6403 16:35:36.005307 done.
6404 16:35:36.008278 Begin: Running /scripts/nfs-bottom ... done.
6405 16:35:36.018490 Begin: Running /scripts/init-bottom ... done.
6406 16:35:36.037526 <6>[ 6.150152] Bluetooth: hci0: QCA Product ID :0x00000008
6407 16:35:36.047968 <6>[ 6.160341] Bluetooth: hci0: QCA SOC Version :0x00000044
6408 16:35:36.058104 <6>[ 6.170349] Bluetooth: hci0: QCA ROM Version :0x00000302
6409 16:35:36.067429 <6>[ 6.179758] Bluetooth: hci0: QCA Patch Version:0x00000111
6410 16:35:36.075984 <6>[ 6.188439] Bluetooth: hci0: QCA controller version 0x00440302
6411 16:35:36.088133 <6>[ 6.197193] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6412 16:35:36.097890 <4>[ 6.206379] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6413 16:35:36.108901 <3>[ 6.217819] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6414 16:35:36.115494 <3>[ 6.227901] Bluetooth: hci0: QCA Failed to download patch (-2)
6415 16:35:36.160257 <6>[ 6.269239] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6416 16:35:36.247149 <4>[ 6.356140] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6417 16:35:36.268313 <4>[ 6.377227] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6418 16:35:36.284352 <4>[ 6.393211] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6419 16:35:36.295585 <4>[ 6.407784] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6420 16:35:37.398027 <6>[ 7.510311] NET: Registered PF_INET6 protocol family
6421 16:35:37.410326 <6>[ 7.522597] Segment Routing with IPv6
6422 16:35:37.418436 <6>[ 7.530793] In-situ OAM (IOAM) with IPv6
6423 16:35:37.589304 <30>[ 7.675311] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6424 16:35:37.610143 <30>[ 7.722196] systemd[1]: Detected architecture arm64.
6425 16:35:37.620165
6426 16:35:37.623284 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6427 16:35:37.623364
6428 16:35:37.645885 <30>[ 7.758383] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6429 16:35:38.573359 <30>[ 8.682292] systemd[1]: Queued start job for default target graphical.target.
6430 16:35:38.621402 <30>[ 8.730566] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6431 16:35:38.633943 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6432 16:35:38.654852 <30>[ 8.763956] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6433 16:35:38.667846 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6434 16:35:38.687070 <30>[ 8.796139] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6435 16:35:38.700712 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6436 16:35:38.717954 <30>[ 8.827172] systemd[1]: Created slice user.slice - User and Session Slice.
6437 16:35:38.730192 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6438 16:35:38.752141 <30>[ 8.858140] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6439 16:35:38.765219 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6440 16:35:38.784382 <30>[ 8.889965] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6441 16:35:38.796573 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6442 16:35:38.823163 <30>[ 8.921920] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6443 16:35:38.841426 <30>[ 8.950826] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6444 16:35:38.849112 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6445 16:35:38.868894 <30>[ 8.977749] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6446 16:35:38.881271 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6447 16:35:38.900749 <30>[ 9.009802] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6448 16:35:38.914835 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6449 16:35:38.929692 <30>[ 9.041848] systemd[1]: Reached target paths.target - Path Units.
6450 16:35:38.943635 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6451 16:35:38.960601 <30>[ 9.069740] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6452 16:35:38.973091 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6453 16:35:38.985168 <30>[ 9.097715] systemd[1]: Reached target slices.target - Slice Units.
6454 16:35:39.000128 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6455 16:35:39.013129 <30>[ 9.125761] systemd[1]: Reached target swap.target - Swaps.
6456 16:35:39.023992 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6457 16:35:39.044910 <30>[ 9.153795] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6458 16:35:39.058257 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6459 16:35:39.077005 <30>[ 9.186151] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6460 16:35:39.090906 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6461 16:35:39.111716 <30>[ 9.220580] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6462 16:35:39.122311 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6463 16:35:39.142547 <30>[ 9.251610] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6464 16:35:39.156666 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6465 16:35:39.173221 <30>[ 9.282475] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6466 16:35:39.185654 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6467 16:35:39.206486 <30>[ 9.315588] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6468 16:35:39.220097 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6469 16:35:39.239284 <30>[ 9.348280] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6470 16:35:39.252485 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6471 16:35:39.269252 <30>[ 9.378340] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6472 16:35:39.282187 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6473 16:35:39.325035 <30>[ 9.433907] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6474 16:35:39.336763 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6475 16:35:39.358911 <30>[ 9.467729] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6476 16:35:39.370392 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6477 16:35:39.421291 <30>[ 9.530208] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6478 16:35:39.433676 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6479 16:35:39.460267 <30>[ 9.562560] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6480 16:35:39.484853 <30>[ 9.593812] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6481 16:35:39.497342 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6482 16:35:39.523088 <30>[ 9.632180] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6483 16:35:39.534536 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6484 16:35:39.545665 <30>[ 9.654457] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6485 16:35:39.555255 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6486 16:35:39.577001 <30>[ 9.686194] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6487 16:35:39.590981 Startin<6>[ 9.697280] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6488 16:35:39.594027 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6489 16:35:39.618379 <30>[ 9.727548] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6490 16:35:39.632053 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6491 16:35:39.655469 <30>[ 9.764402] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6492 16:35:39.666879 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6493 16:35:39.697378 <6>[ 9.810061] fuse: init (API version 7.37)
6494 16:35:39.729648 <30>[ 9.838572] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6495 16:35:39.741773 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6496 16:35:39.771788 <30>[ 9.880851] systemd[1]: Starting systemd-journald.service - Journal Service...
6497 16:35:39.781727 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6498 16:35:39.806311 <30>[ 9.915438] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6499 16:35:39.817887 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6500 16:35:39.864486 <30>[ 9.970377] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6501 16:35:39.875928 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6502 16:35:39.896624 <30>[ 10.005434] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6503 16:35:39.908665 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6504 16:35:39.928131 <30>[ 10.037047] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6505 16:35:39.939257 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6506 16:35:39.953945 <3>[ 10.062387] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6507 16:35:39.968726 <3>[ 10.077387] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6508 16:35:39.975595 <30>[ 10.079561] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6509 16:35:39.992750 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 10.101833] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6510 16:35:39.996204 uge Pages File System.
6511 16:35:40.010620 <3>[ 10.119688] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6512 16:35:40.022076 <30>[ 10.128789] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6513 16:35:40.029000 <3>[ 10.136826] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6514 16:35:40.049447 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 10.156619] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6515 16:35:40.049591 File System.
6516 16:35:40.066508 <3>[ 10.175093] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6517 16:35:40.076230 <30>[ 10.184135] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6518 16:35:40.093913 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 10.201228] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6519 16:35:40.094055 File System.
6520 16:35:40.115461 <30>[ 10.222988] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6521 16:35:40.127223 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6522 16:35:40.145924 <30>[ 10.255049] systemd[1]: Started systemd-journald.service - Journal Service.
6523 16:35:40.157315 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6524 16:35:40.181864 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6525 16:35:40.203911 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6526 16:35:40.223567 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6527 16:35:40.241609 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6528 16:35:40.266213 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6529 16:35:40.289942 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6530 16:35:40.313595 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6531 16:35:40.337735 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6532 16:35:40.361463 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6533 16:35:40.385921 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6534 16:35:40.412897 <4>[ 10.515031] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6535 16:35:40.423929 <3>[ 10.532793] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6536 16:35:40.457711 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6537 16:35:40.487100 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6538 16:35:40.515654 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6539 16:35:40.541300 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6540 16:35:40.568920 Starting [0;1;39msystemd-sysctl.se…c<46>[ 10.678358] systemd-journald[320]: Received client request to flush runtime journal.
6541 16:35:40.571876 e[0m - Apply Kernel Variables...
6542 16:35:40.589763 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6543 16:35:40.624810 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6544 16:35:40.641783 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6545 16:35:40.661915 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6546 16:35:40.682224 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6547 16:35:41.690784 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6548 16:35:41.726576 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6549 16:35:41.777785 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6550 16:35:42.066261 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6551 16:35:42.154063 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6552 16:35:42.174180 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6553 16:35:42.193003 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6554 16:35:42.234153 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6555 16:35:42.258737 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6556 16:35:42.495120 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6557 16:35:42.519440 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6558 16:35:42.573595 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6559 16:35:42.729089 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6560 16:35:42.748096 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6561 16:35:42.795843 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6562 16:35:42.851425 <4>[ 12.962742] power_supply_show_property: 4 callbacks suppressed
6563 16:35:42.859663 <3>[ 12.962753] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6564 16:35:42.869464 <3>[ 12.963097] power_supply sbs-12-000b: driver failed to report `health' property: -6
6565 16:35:42.876022 <3>[ 12.974666] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6566 16:35:42.893320 <3>[ 13.001731] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6567 16:35:42.908071 <3>[ 13.016453] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6568 16:35:42.925052 <3>[ 13.033709] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6569 16:35:42.939793 <3>[ 13.048432] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6570 16:35:42.954308 <3>[ 13.063066] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6571 16:35:42.970046 <3>[ 13.078464] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6572 16:35:42.985052 <3>[ 13.093237] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6573 16:35:43.039309 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6574 16:35:43.057768 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6575 16:35:43.081893 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6576 16:35:43.138428 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6577 16:35:43.167941 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6578 16:35:43.197030 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6579 16:35:43.301710 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6580 16:35:43.332238 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6581 16:35:43.354317 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6582 16:35:43.391370 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6583 16:35:43.411221 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6584 16:35:43.429600 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6585 16:35:43.451249 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6586 16:35:43.474395 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6587 16:35:43.496994 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6588 16:35:43.519127 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6589 16:35:43.533882 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6590 16:35:43.554553 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6591 16:35:43.573570 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6592 16:35:43.597135 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6593 16:35:43.616912 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6594 16:35:43.638507 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6595 16:35:43.668239 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6596 16:35:43.690656 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6597 16:35:43.706894 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6598 16:35:43.725664 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6599 16:35:43.743190 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6600 16:35:43.760573 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6601 16:35:43.767426 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6602 16:35:43.822761 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6603 16:35:43.846784 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6604 16:35:43.903593 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6605 16:35:44.061824 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6606 16:35:44.088421 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6607 16:35:44.106420 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6608 16:35:44.123533 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6609 16:35:44.194270 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6610 16:35:44.230609 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6611 16:35:44.276211 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6612 16:35:44.296322 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6613 16:35:44.317095 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6614 16:35:44.364853 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6615 16:35:44.390571 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6616 16:35:44.415700 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6617 16:35:44.435822 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6618 16:35:44.481648 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6619 16:35:44.533427 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6620 16:35:44.598495
6621 16:35:44.602208 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6622 16:35:44.602300
6623 16:35:44.605304 debian-bookworm-arm64 login: root (automatic login)
6624 16:35:44.605385
6625 16:35:44.867247 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
6626 16:35:44.867375
6627 16:35:44.873671 The programs included with the Debian GNU/Linux system are free software;
6628 16:35:44.880708 the exact distribution terms for each program are described in the
6629 16:35:44.883837 individual files in /usr/share/doc/*/copyright.
6630 16:35:44.883958
6631 16:35:44.890572 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6632 16:35:44.894015 permitted by applicable law.
6633 16:35:45.983770 Matched prompt #10: / #
6635 16:35:45.984092 Setting prompt string to ['/ #']
6636 16:35:45.984228 end: 2.2.5.1 login-action (duration 00:00:17) [common]
6638 16:35:45.984538 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
6639 16:35:45.984659 start: 2.2.6 expect-shell-connection (timeout 00:03:51) [common]
6640 16:35:45.984761 Setting prompt string to ['/ #']
6641 16:35:45.984853 Forcing a shell prompt, looking for ['/ #']
6643 16:35:46.035101 / #
6644 16:35:46.035311 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6645 16:35:46.035386 Waiting using forced prompt support (timeout 00:02:30)
6646 16:35:46.040423
6647 16:35:46.040704 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6648 16:35:46.040825 start: 2.2.7 export-device-env (timeout 00:03:51) [common]
6650 16:35:46.141151 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto'
6651 16:35:46.146540 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396137/extract-nfsrootfs-alv_wvto'
6653 16:35:46.247041 / # export NFS_SERVER_IP='192.168.201.1'
6654 16:35:46.251623 export NFS_SERVER_IP='192.168.201.1'
6655 16:35:46.251928 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6656 16:35:46.252052 end: 2.2 depthcharge-retry (duration 00:01:10) [common]
6657 16:35:46.252167 end: 2 depthcharge-action (duration 00:01:10) [common]
6658 16:35:46.252282 start: 3 lava-test-retry (timeout 00:07:52) [common]
6659 16:35:46.252393 start: 3.1 lava-test-shell (timeout 00:07:52) [common]
6660 16:35:46.252489 Using namespace: common
6662 16:35:46.352859 / # #
6663 16:35:46.353064 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6664 16:35:46.357820 #
6665 16:35:46.358077 Using /lava-14396137
6667 16:35:46.458378 / # export SHELL=/bin/bash
6668 16:35:46.463184 export SHELL=/bin/bash
6670 16:35:46.563661 / # . /lava-14396137/environment
6671 16:35:46.568497 . /lava-14396137/environment
6673 16:35:46.673240 / # /lava-14396137/bin/lava-test-runner /lava-14396137/0
6674 16:35:46.673427 Test shell timeout: 10s (minimum of the action and connection timeout)
6675 16:35:46.678649 /lava-14396137/bin/lava-test-runner /lava-14396137/0
6676 16:35:46.908873 + export TESTRUN_ID=0_timesync-off
6677 16:35:46.911845 + TESTRUN_ID=0_timesync-off
6678 16:35:46.915381 + cd /lava-14396137/0/tests/0_timesync-off
6679 16:35:46.918765 ++ cat uuid
6680 16:35:46.924635 + UUID=14396137_1.6.2.3.1
6681 16:35:46.924722 + set +x
6682 16:35:46.931042 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14396137_1.6.2.3.1>
6683 16:35:46.931305 Received signal: <STARTRUN> 0_timesync-off 14396137_1.6.2.3.1
6684 16:35:46.931377 Starting test lava.0_timesync-off (14396137_1.6.2.3.1)
6685 16:35:46.931465 Skipping test definition patterns.
6686 16:35:46.934528 + systemctl stop systemd-timesyncd
6687 16:35:46.989102 + set +x
6688 16:35:46.992171 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14396137_1.6.2.3.1>
6689 16:35:46.992418 Received signal: <ENDRUN> 0_timesync-off 14396137_1.6.2.3.1
6690 16:35:46.992495 Ending use of test pattern.
6691 16:35:46.992552 Ending test lava.0_timesync-off (14396137_1.6.2.3.1), duration 0.06
6693 16:35:47.059642 + export TESTRUN_ID=1_kselftest-alsa
6694 16:35:47.062853 + TESTRUN_ID=1_kselftest-alsa
6695 16:35:47.069385 + cd /lava-14396137/0/tests/1_kselftest-alsa
6696 16:35:47.069536 ++ cat uuid
6697 16:35:47.072656 + UUID=14396137_1.6.2.3.5
6698 16:35:47.072758 + set +x
6699 16:35:47.079157 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14396137_1.6.2.3.5>
6700 16:35:47.079403 Received signal: <STARTRUN> 1_kselftest-alsa 14396137_1.6.2.3.5
6701 16:35:47.079499 Starting test lava.1_kselftest-alsa (14396137_1.6.2.3.5)
6702 16:35:47.079594 Skipping test definition patterns.
6703 16:35:47.082909 + cd ./automated/linux/kselftest/
6704 16:35:47.112083 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6705 16:35:47.141431 INFO: install_deps skipped
6706 16:35:47.626250 --2024-06-17 16:35:47-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6707 16:35:47.632574 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6708 16:35:47.759694 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6709 16:35:47.891224 HTTP request sent, awaiting response... 200 OK
6710 16:35:47.894409 Length: 1650228 (1.6M) [application/octet-stream]
6711 16:35:47.898150 Saving to: 'kselftest_armhf.tar.gz'
6712 16:35:47.898272
6713 16:35:47.898335
6714 16:35:48.154242 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6715 16:35:48.416874 kselftest_armhf.tar 2%[ ] 44.98K 167KB/s
6716 16:35:48.726980 kselftest_armhf.tar 13%[=> ] 214.67K 398KB/s
6717 16:35:48.861957 kselftest_armhf.tar 51%[=========> ] 829.78K 968KB/s
6718 16:35:48.868872 kselftest_armhf.tar 100%[===================>] 1.57M 1.58MB/s in 1.0s
6719 16:35:48.869010
6720 16:35:49.013329 2024-06-17 16:35:48 (1.58 MB/s) - 'kselftest_armhf.tar.gz' saved [1650228/1650228]
6721 16:35:49.013451
6722 16:35:52.950119 skiplist:
6723 16:35:52.953328 ========================================
6724 16:35:52.956382 ========================================
6725 16:35:52.998992 alsa:mixer-test
6726 16:35:53.018383 ============== Tests to run ===============
6727 16:35:53.018476 alsa:mixer-test
6728 16:35:53.022105 ===========End Tests to run ===============
6729 16:35:53.026393 shardfile-alsa pass
6730 16:35:53.129175 <12>[ 23.241240] kselftest: Running tests in alsa
6731 16:35:53.139601 TAP version 13
6732 16:35:53.153234 1..1
6733 16:35:53.172873 # selftests: alsa: mixer-test
6734 16:35:53.261175 <6>[ 23.366334] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6735 16:35:53.274194 <6>[ 23.378622] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6736 16:35:53.287536 <6>[ 23.390794] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6737 16:35:53.297284 <6>[ 23.402945] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6738 16:35:53.310409 <6>[ 23.415087] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6739 16:35:53.320338 <6>[ 23.427226] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6740 16:35:53.334058 <6>[ 23.438568] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6741 16:35:53.343576 <6>[ 23.449905] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6742 16:35:53.356984 <6>[ 23.461237] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6743 16:35:53.366717 <6>[ 23.472570] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6744 16:35:53.376989 <6>[ 23.483906] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6745 16:35:53.390223 <6>[ 23.495237] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6746 16:35:53.400389 <6>[ 23.506570] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6747 16:35:53.413307 <6>[ 23.517906] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6748 16:35:53.423651 <6>[ 23.529237] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6749 16:35:53.433442 <6>[ 23.540579] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6750 16:35:53.446814 <6>[ 23.551943] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6751 16:35:53.456361 <6>[ 23.563276] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6752 16:35:53.469483 <6>[ 23.574611] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6753 16:35:53.479877 <6>[ 23.585947] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6754 16:35:53.493354 <6>[ 23.597293] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6755 16:35:53.503087 <6>[ 23.608630] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6756 16:35:53.512698 <6>[ 23.619962] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6757 16:35:53.525785 <6>[ 23.631300] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6758 16:35:53.536213 <6>[ 23.642635] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6759 16:35:53.549003 <6>[ 23.653970] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6760 16:35:53.559155 <6>[ 23.665301] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6761 16:35:53.572224 <6>[ 23.676628] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6762 16:35:53.582625 <6>[ 23.687979] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6763 16:35:53.592312 <6>[ 23.699312] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6764 16:35:53.643523 # TAP version 13
6765 16:35:53.643640 # 1..658
6766 16:35:53.647178 # ok 1 get_value.0.93
6767 16:35:53.647258 # ok 2 name.0.93
6768 16:35:53.650251 # ok 3 write_default.0.93
6769 16:35:53.653626 # ok 4 write_valid.0.93
6770 16:35:53.653705 # ok 5 write_invalid.0.93
6771 16:35:53.657259 # ok 6 event_missing.0.93
6772 16:35:53.660487 # ok 7 event_spurious.0.93
6773 16:35:53.663657 # ok 8 get_value.0.92
6774 16:35:53.663737 # ok 9 name.0.92
6775 16:35:53.666705 # ok 10 write_default.0.92
6776 16:35:53.666785 # ok 11 write_valid.0.92
6777 16:35:53.670395 # ok 12 write_invalid.0.92
6778 16:35:53.673539 # ok 13 event_missing.0.92
6779 16:35:53.676846 # ok 14 event_spurious.0.92
6780 16:35:53.676920 # ok 15 get_value.0.91
6781 16:35:53.680031 # ok 16 name.0.91
6782 16:35:53.683279 # ok 17 write_default.0.91
6783 16:35:53.683351 # ok 18 write_valid.0.91
6784 16:35:53.686477 # ok 19 write_invalid.0.91
6785 16:35:53.689636 # ok 20 event_missing.0.91
6786 16:35:53.689708 # ok 21 event_spurious.0.91
6787 16:35:53.693586 # ok 22 get_value.0.90
6788 16:35:53.696275 # ok 23 name.0.90
6789 16:35:53.696344 # ok 24 write_default.0.90
6790 16:35:53.700155 # ok 25 write_valid.0.90
6791 16:35:53.703328 # ok 26 write_invalid.0.90
6792 16:35:53.703395 # ok 27 event_missing.0.90
6793 16:35:53.706505 # ok 28 event_spurious.0.90
6794 16:35:53.709478 # ok 29 get_value.0.89
6795 16:35:53.709546 # ok 30 name.0.89
6796 16:35:53.713340 # ok 31 write_default.0.89
6797 16:35:53.716526 # ok 32 write_valid.0.89
6798 16:35:53.719592 # ok 33 write_invalid.0.89
6799 16:35:53.719668 # ok 34 event_missing.0.89
6800 16:35:53.723199 # ok 35 event_spurious.0.89
6801 16:35:53.726556 # ok 36 get_value.0.88
6802 16:35:53.726628 # ok 37 name.0.88
6803 16:35:53.729405 # ok 38 write_default.0.88
6804 16:35:53.732980 # # Spurious event generated for AIF Out Mux
6805 16:35:53.739680 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6806 16:35:53.742931 # # Spurious event generated for AIF Out Mux
6807 16:35:53.746226 # not ok 39 write_valid.0.88
6808 16:35:53.749554 # ok 40 write_invalid.0.88
6809 16:35:53.749634 # ok 41 event_missing.0.88
6810 16:35:53.752847 # not ok 42 event_spurious.0.88
6811 16:35:53.755973 # ok 43 get_value.0.87
6812 16:35:53.756040 # ok 44 name.0.87
6813 16:35:53.759263 # ok 45 write_default.0.87
6814 16:35:53.762972 # ok 46 write_valid.0.87
6815 16:35:53.765853 # ok 47 write_invalid.0.87
6816 16:35:53.765927 # ok 48 event_missing.0.87
6817 16:35:53.769509 # ok 49 event_spurious.0.87
6818 16:35:53.772521 # ok 50 get_value.0.86
6819 16:35:53.772589 # ok 51 name.0.86
6820 16:35:53.776138 # ok 52 write_default.0.86
6821 16:35:53.779137 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6822 16:35:53.785866 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6823 16:35:53.789171 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6824 16:35:53.792334 # not ok 53 write_valid.0.86
6825 16:35:53.795601 # ok 54 write_invalid.0.86
6826 16:35:53.799023 # ok 55 event_missing.0.86
6827 16:35:53.799093 # ok 56 event_spurious.0.86
6828 16:35:53.802293 # ok 57 get_value.0.85
6829 16:35:53.806149 # ok 58 name.0.85
6830 16:35:53.806220 # ok 59 write_default.0.85
6831 16:35:53.812647 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6832 16:35:53.815688 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6833 16:35:53.822342 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6834 16:35:53.822421 # not ok 60 write_valid.0.85
6835 16:35:53.825624 # ok 61 write_invalid.0.85
6836 16:35:53.828821 # ok 62 event_missing.0.85
6837 16:35:53.832562 # ok 63 event_spurious.0.85
6838 16:35:53.832639 # ok 64 get_value.0.84
6839 16:35:53.835572 # ok 65 name.0.84
6840 16:35:53.838779 # ok 66 write_default.0.84
6841 16:35:53.838855 # ok 67 write_valid.0.84
6842 16:35:53.842462 # ok 68 write_invalid.0.84
6843 16:35:53.845400 # ok 69 event_missing.0.84
6844 16:35:53.849041 # ok 70 event_spurious.0.84
6845 16:35:53.849112 # ok 71 get_value.0.83
6846 16:35:53.852604 # ok 72 name.0.83
6847 16:35:53.852678 # ok 73 write_default.0.83
6848 16:35:53.855431 # ok 74 write_valid.0.83
6849 16:35:53.859065 # ok 75 write_invalid.0.83
6850 16:35:53.862223 # ok 76 event_missing.0.83
6851 16:35:53.862297 # ok 77 event_spurious.0.83
6852 16:35:53.865515 # ok 78 get_value.0.82
6853 16:35:53.868671 # ok 79 name.0.82
6854 16:35:53.872409 # # Headset Jack is not writeable
6855 16:35:53.872481 # ok 80 # SKIP write_default.0.82
6856 16:35:53.875458 # # Headset Jack is not writeable
6857 16:35:53.879072 # ok 81 # SKIP write_valid.0.82
6858 16:35:53.882649 # # Headset Jack is not writeable
6859 16:35:53.885694 # ok 82 # SKIP write_invalid.0.82
6860 16:35:53.889202 # ok 83 event_missing.0.82
6861 16:35:53.892158 # ok 84 event_spurious.0.82
6862 16:35:53.892243 # ok 85 get_value.0.81
6863 16:35:53.895960 # ok 86 name.0.81
6864 16:35:53.899208 # ok 87 write_default.0.81
6865 16:35:53.902413 # # No event generated for Wake-on-Voice Phase2 Switch
6866 16:35:53.908863 # # No event generated for Wake-on-Voice Phase2 Switch
6867 16:35:53.908961 # ok 88 write_valid.0.81
6868 16:35:53.915374 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6869 16:35:53.918431 # # No event generated for Wake-on-Voice Phase2 Switch
6870 16:35:53.922254 # not ok 89 write_invalid.0.81
6871 16:35:53.925563 # not ok 90 event_missing.0.81
6872 16:35:53.928811 # ok 91 event_spurious.0.81
6873 16:35:53.932069 # ok 92 get_value.0.80
6874 16:35:53.932149 # ok 93 name.0.80
6875 16:35:53.935316 # ok 94 write_default.0.80
6876 16:35:53.938402 # ok 95 write_valid.0.80
6877 16:35:53.938481 # ok 96 write_invalid.0.80
6878 16:35:53.942048 # ok 97 event_missing.0.80
6879 16:35:53.945318 # ok 98 event_spurious.0.80
6880 16:35:53.948457 # # Handset Volume.0 value -13 less than minimum 0
6881 16:35:53.951593 # not ok 99 get_value.0.79
6882 16:35:53.954726 # ok 100 name.0.79
6883 16:35:53.958392 # # snd_ctl_elem_write() failed: Invalid argument
6884 16:35:53.961490 # not ok 101 write_default.0.79
6885 16:35:53.965212 # # snd_ctl_elem_write() failed: Invalid argument
6886 16:35:53.968144 # not ok 102 write_valid.0.79
6887 16:35:53.971295 # # snd_ctl_elem_write() failed: Invalid argument
6888 16:35:53.975045 # not ok 103 write_invalid.0.79
6889 16:35:53.978124 # ok 104 event_missing.0.79
6890 16:35:53.981481 # ok 105 event_spurious.0.79
6891 16:35:53.984452 # # Lineout Volume.0 value -13 less than minimum 0
6892 16:35:53.991611 # # Lineout Volume.1 value -13 less than minimum 0
6893 16:35:53.994753 # not ok 106 get_value.0.78
6894 16:35:53.994835 # ok 107 name.0.78
6895 16:35:53.997760 # # snd_ctl_elem_write() failed: Invalid argument
6896 16:35:54.001287 # not ok 108 write_default.0.78
6897 16:35:54.007792 # # snd_ctl_elem_write() failed: Invalid argument
6898 16:35:54.011108 # not ok 109 write_valid.0.78
6899 16:35:54.014380 # # snd_ctl_elem_write() failed: Invalid argument
6900 16:35:54.017568 # not ok 110 write_invalid.0.78
6901 16:35:54.021422 # ok 111 event_missing.0.78
6902 16:35:54.021544 # ok 112 event_spurious.0.78
6903 16:35:54.027639 # # Headphone Volume.0 value -13 less than minimum 0
6904 16:35:54.030830 # # Headphone Volume.1 value -13 less than minimum 0
6905 16:35:54.034712 # not ok 113 get_value.0.77
6906 16:35:54.037359 # ok 114 name.0.77
6907 16:35:54.040608 # # snd_ctl_elem_write() failed: Invalid argument
6908 16:35:54.044411 # not ok 115 write_default.0.77
6909 16:35:54.047852 # # snd_ctl_elem_write() failed: Invalid argument
6910 16:35:54.050534 # not ok 116 write_valid.0.77
6911 16:35:54.057641 # # snd_ctl_elem_write() failed: Invalid argument
6912 16:35:54.057729 # not ok 117 write_invalid.0.77
6913 16:35:54.060855 # ok 118 event_missing.0.77
6914 16:35:54.063988 # ok 119 event_spurious.0.77
6915 16:35:54.067261 # ok 120 get_value.0.76
6916 16:35:54.073549 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6917 16:35:54.073660 # not ok 121 name.0.76
6918 16:35:54.076765 # ok 122 write_default.0.76
6919 16:35:54.080610 # ok 123 write_valid.0.76
6920 16:35:54.083860 # ok 124 write_invalid.0.76
6921 16:35:54.083961 # ok 125 event_missing.0.76
6922 16:35:54.086947 # ok 126 event_spurious.0.76
6923 16:35:54.090556 # ok 127 get_value.0.75
6924 16:35:54.096932 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6925 16:35:54.097040 # not ok 128 name.0.75
6926 16:35:54.100231 # ok 129 write_default.0.75
6927 16:35:54.103470 # ok 130 write_valid.0.75
6928 16:35:54.106675 # ok 131 write_invalid.0.75
6929 16:35:54.106755 # ok 132 event_missing.0.75
6930 16:35:54.110312 # ok 133 event_spurious.0.75
6931 16:35:54.113163 # ok 134 get_value.0.74
6932 16:35:54.119877 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6933 16:35:54.119968 # not ok 135 name.0.74
6934 16:35:54.123099 # ok 136 write_default.0.74
6935 16:35:54.126900 # ok 137 write_valid.0.74
6936 16:35:54.129772 # ok 138 write_invalid.0.74
6937 16:35:54.129871 # ok 139 event_missing.0.74
6938 16:35:54.133081 # ok 140 event_spurious.0.74
6939 16:35:54.136376 # ok 141 get_value.0.73
6940 16:35:54.142871 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6941 16:35:54.146827 # not ok 142 name.0.73
6942 16:35:54.146906 # ok 143 write_default.0.73
6943 16:35:54.149901 # ok 144 write_valid.0.73
6944 16:35:54.153048 # ok 145 write_invalid.0.73
6945 16:35:54.156566 # ok 146 event_missing.0.73
6946 16:35:54.160069 # ok 147 event_spurious.0.73
6947 16:35:54.160149 # ok 148 get_value.0.72
6948 16:35:54.166380 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6949 16:35:54.169497 # not ok 149 name.0.72
6950 16:35:54.173301 # ok 150 write_default.0.72
6951 16:35:54.173381 # ok 151 write_valid.0.72
6952 16:35:54.176490 # ok 152 write_invalid.0.72
6953 16:35:54.179570 # ok 153 event_missing.0.72
6954 16:35:54.183258 # ok 154 event_spurious.0.72
6955 16:35:54.183356 # ok 155 get_value.0.71
6956 16:35:54.189682 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6957 16:35:54.192794 # not ok 156 name.0.71
6958 16:35:54.196506 # ok 157 write_default.0.71
6959 16:35:54.199768 # ok 158 write_valid.0.71
6960 16:35:54.199876 # ok 159 write_invalid.0.71
6961 16:35:54.202827 # ok 160 event_missing.0.71
6962 16:35:54.206210 # ok 161 event_spurious.0.71
6963 16:35:54.209409 # ok 162 get_value.0.70
6964 16:35:54.215788 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6965 16:35:54.215900 # not ok 163 name.0.70
6966 16:35:54.219518 # ok 164 write_default.0.70
6967 16:35:54.222964 # ok 165 write_valid.0.70
6968 16:35:54.225970 # ok 166 write_invalid.0.70
6969 16:35:54.226082 # ok 167 event_missing.0.70
6970 16:35:54.229633 # ok 168 event_spurious.0.70
6971 16:35:54.232719 # ok 169 get_value.0.69
6972 16:35:54.239235 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6973 16:35:54.239321 # not ok 170 name.0.69
6974 16:35:54.242368 # ok 171 write_default.0.69
6975 16:35:54.246259 # ok 172 write_valid.0.69
6976 16:35:54.249364 # ok 173 write_invalid.0.69
6977 16:35:54.252611 # ok 174 event_missing.0.69
6978 16:35:54.252708 # ok 175 event_spurious.0.69
6979 16:35:54.255758 # ok 176 get_value.0.68
6980 16:35:54.262661 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6981 16:35:54.265690 # not ok 177 name.0.68
6982 16:35:54.265788 # ok 178 write_default.0.68
6983 16:35:54.268881 # ok 179 write_valid.0.68
6984 16:35:54.272301 # ok 180 write_invalid.0.68
6985 16:35:54.275296 # ok 181 event_missing.0.68
6986 16:35:54.279064 # ok 182 event_spurious.0.68
6987 16:35:54.279148 # ok 183 get_value.0.67
6988 16:35:54.285430 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6989 16:35:54.289155 # not ok 184 name.0.67
6990 16:35:54.292358 # ok 185 write_default.0.67
6991 16:35:54.292435 # ok 186 write_valid.0.67
6992 16:35:54.295548 # ok 187 write_invalid.0.67
6993 16:35:54.298809 # ok 188 event_missing.0.67
6994 16:35:54.302094 # ok 189 event_spurious.0.67
6995 16:35:54.302174 # ok 190 get_value.0.66
6996 16:35:54.308938 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6997 16:35:54.312134 # not ok 191 name.0.66
6998 16:35:54.315284 # ok 192 write_default.0.66
6999 16:35:54.315363 # ok 193 write_valid.0.66
7000 16:35:54.318523 # ok 194 write_invalid.0.66
7001 16:35:54.321946 # ok 195 event_missing.0.66
7002 16:35:54.325222 # ok 196 event_spurious.0.66
7003 16:35:54.325329 # ok 197 get_value.0.65
7004 16:35:54.331939 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
7005 16:35:54.335485 # not ok 198 name.0.65
7006 16:35:54.335578 # ok 199 write_default.0.65
7007 16:35:54.338480 # ok 200 write_valid.0.65
7008 16:35:54.341652 # ok 201 write_invalid.0.65
7009 16:35:54.345495 # ok 202 event_missing.0.65
7010 16:35:54.345570 # ok 203 event_spurious.0.65
7011 16:35:54.348646 # ok 204 get_value.0.64
7012 16:35:54.355063 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
7013 16:35:54.358289 # not ok 205 name.0.64
7014 16:35:54.358363 # ok 206 write_default.0.64
7015 16:35:54.362163 # ok 207 write_valid.0.64
7016 16:35:54.365322 # ok 208 write_invalid.0.64
7017 16:35:54.368594 # ok 209 event_missing.0.64
7018 16:35:54.371799 # ok 210 event_spurious.0.64
7019 16:35:54.371884 # ok 211 get_value.0.63
7020 16:35:54.378687 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
7021 16:35:54.381591 # not ok 212 name.0.63
7022 16:35:54.384956 # ok 213 write_default.0.63
7023 16:35:54.385070 # ok 214 write_valid.0.63
7024 16:35:54.388019 # ok 215 write_invalid.0.63
7025 16:35:54.391485 # ok 216 event_missing.0.63
7026 16:35:54.395222 # ok 217 event_spurious.0.63
7027 16:35:54.395323 # ok 218 get_value.0.62
7028 16:35:54.401447 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7029 16:35:54.404679 # not ok 219 name.0.62
7030 16:35:54.407858 # ok 220 write_default.0.62
7031 16:35:54.407957 # ok 221 write_valid.0.62
7032 16:35:54.411429 # ok 222 write_invalid.0.62
7033 16:35:54.414485 # ok 223 event_missing.0.62
7034 16:35:54.418353 # ok 224 event_spurious.0.62
7035 16:35:54.418472 # ok 225 get_value.0.61
7036 16:35:54.424807 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7037 16:35:54.428022 # not ok 226 name.0.61
7038 16:35:54.431322 # ok 227 write_default.0.61
7039 16:35:54.431429 # ok 228 write_valid.0.61
7040 16:35:54.434605 # ok 229 write_invalid.0.61
7041 16:35:54.437739 # ok 230 event_missing.0.61
7042 16:35:54.441349 # ok 231 event_spurious.0.61
7043 16:35:54.441467 # ok 232 get_value.0.60
7044 16:35:54.447752 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
7045 16:35:54.451236 # not ok 233 name.0.60
7046 16:35:54.454305 # ok 234 write_default.0.60
7047 16:35:54.454437 # ok 235 write_valid.0.60
7048 16:35:54.457501 # ok 236 write_invalid.0.60
7049 16:35:54.460678 # ok 237 event_missing.0.60
7050 16:35:54.463986 # ok 238 event_spurious.0.60
7051 16:35:54.464155 # ok 239 get_value.0.59
7052 16:35:54.471055 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
7053 16:35:54.474129 # not ok 240 name.0.59
7054 16:35:54.474268 # ok 241 write_default.0.59
7055 16:35:54.477349 # ok 242 write_valid.0.59
7056 16:35:54.481017 # ok 243 write_invalid.0.59
7057 16:35:54.484180 # ok 244 event_missing.0.59
7058 16:35:54.484297 # ok 245 event_spurious.0.59
7059 16:35:54.487327 # ok 246 get_value.0.58
7060 16:35:54.493998 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
7061 16:35:54.497003 # not ok 247 name.0.58
7062 16:35:54.497108 # ok 248 write_default.0.58
7063 16:35:54.500669 # ok 249 write_valid.0.58
7064 16:35:54.504150 # ok 250 write_invalid.0.58
7065 16:35:54.507296 # ok 251 event_missing.0.58
7066 16:35:54.507413 # ok 252 event_spurious.0.58
7067 16:35:54.510790 # ok 253 get_value.0.57
7068 16:35:54.517075 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
7069 16:35:54.517187 # not ok 254 name.0.57
7070 16:35:54.520622 # ok 255 write_default.0.57
7071 16:35:54.523848 # ok 256 write_valid.0.57
7072 16:35:54.526999 # ok 257 write_invalid.0.57
7073 16:35:54.527113 # ok 258 event_missing.0.57
7074 16:35:54.530191 # ok 259 event_spurious.0.57
7075 16:35:54.534073 # ok 260 get_value.0.56
7076 16:35:54.540448 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
7077 16:35:54.540570 # not ok 261 name.0.56
7078 16:35:54.543782 # ok 262 write_default.0.56
7079 16:35:54.546736 # ok 263 write_valid.0.56
7080 16:35:54.546834 # ok 264 write_invalid.0.56
7081 16:35:54.549884 # ok 265 event_missing.0.56
7082 16:35:54.553669 # ok 266 event_spurious.0.56
7083 16:35:54.556918 # ok 267 get_value.0.55
7084 16:35:54.560026 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
7085 16:35:54.563524 # not ok 268 name.0.55
7086 16:35:54.566446 # ok 269 write_default.0.55
7087 16:35:54.570285 # ok 270 write_valid.0.55
7088 16:35:54.570409 # ok 271 write_invalid.0.55
7089 16:35:54.573514 # ok 272 event_missing.0.55
7090 16:35:54.576655 # ok 273 event_spurious.0.55
7091 16:35:54.576807 # ok 274 get_value.0.54
7092 16:35:54.583038 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
7093 16:35:54.586341 # not ok 275 name.0.54
7094 16:35:54.589612 # ok 276 write_default.0.54
7095 16:35:54.589766 # ok 277 write_valid.0.54
7096 16:35:54.593461 # ok 278 write_invalid.0.54
7097 16:35:54.596591 # ok 279 event_missing.0.54
7098 16:35:54.599797 # ok 280 event_spurious.0.54
7099 16:35:54.599905 # ok 281 get_value.0.53
7100 16:35:54.606311 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
7101 16:35:54.610005 # not ok 282 name.0.53
7102 16:35:54.610085 # ok 283 write_default.0.53
7103 16:35:54.612992 # ok 284 write_valid.0.53
7104 16:35:54.616017 # ok 285 write_invalid.0.53
7105 16:35:54.619381 # ok 286 event_missing.0.53
7106 16:35:54.619466 # ok 287 event_spurious.0.53
7107 16:35:54.622667 # ok 288 get_value.0.52
7108 16:35:54.629550 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
7109 16:35:54.632656 # not ok 289 name.0.52
7110 16:35:54.632734 # ok 290 write_default.0.52
7111 16:35:54.635898 # ok 291 write_valid.0.52
7112 16:35:54.639159 # ok 292 write_invalid.0.52
7113 16:35:54.642894 # ok 293 event_missing.0.52
7114 16:35:54.642972 # ok 294 event_spurious.0.52
7115 16:35:54.646277 # ok 295 get_value.0.51
7116 16:35:54.652433 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
7117 16:35:54.652540 # not ok 296 name.0.51
7118 16:35:54.655702 # ok 297 write_default.0.51
7119 16:35:54.659549 # ok 298 write_valid.0.51
7120 16:35:54.662869 # ok 299 write_invalid.0.51
7121 16:35:54.662971 # ok 300 event_missing.0.51
7122 16:35:54.665970 # ok 301 event_spurious.0.51
7123 16:35:54.669237 # ok 302 get_value.0.50
7124 16:35:54.675650 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
7125 16:35:54.675731 # not ok 303 name.0.50
7126 16:35:54.679246 # ok 304 write_default.0.50
7127 16:35:54.682373 # ok 305 write_valid.0.50
7128 16:35:54.685977 # ok 306 write_invalid.0.50
7129 16:35:54.689375 # ok 307 event_missing.0.50
7130 16:35:54.689446 # ok 308 event_spurious.0.50
7131 16:35:54.692572 # ok 309 get_value.0.49
7132 16:35:54.698850 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
7133 16:35:54.702079 # not ok 310 name.0.49
7134 16:35:54.702149 # ok 311 write_default.0.49
7135 16:35:54.705682 # ok 312 write_valid.0.49
7136 16:35:54.708971 # ok 313 write_invalid.0.49
7137 16:35:54.711972 # ok 314 event_missing.0.49
7138 16:35:54.712063 # ok 315 event_spurious.0.49
7139 16:35:54.715790 # ok 316 get_value.0.48
7140 16:35:54.722401 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
7141 16:35:54.725541 # not ok 317 name.0.48
7142 16:35:54.725627 # ok 318 write_default.0.48
7143 16:35:54.728508 # ok 319 write_valid.0.48
7144 16:35:54.732092 # ok 320 write_invalid.0.48
7145 16:35:54.735433 # ok 321 event_missing.0.48
7146 16:35:54.738550 # ok 322 event_spurious.0.48
7147 16:35:54.738729 # ok 323 get_value.0.47
7148 16:35:54.745018 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
7149 16:35:54.748856 # not ok 324 name.0.47
7150 16:35:54.748927 # ok 325 write_default.0.47
7151 16:35:54.752195 # ok 326 write_valid.0.47
7152 16:35:54.755190 # ok 327 write_invalid.0.47
7153 16:35:54.758360 # ok 328 event_missing.0.47
7154 16:35:54.762156 # ok 329 event_spurious.0.47
7155 16:35:54.762231 # ok 330 get_value.0.46
7156 16:35:54.768666 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
7157 16:35:54.771886 # not ok 331 name.0.46
7158 16:35:54.771962 # ok 332 write_default.0.46
7159 16:35:54.775126 # ok 333 write_valid.0.46
7160 16:35:54.778268 # ok 334 write_invalid.0.46
7161 16:35:54.782080 # ok 335 event_missing.0.46
7162 16:35:54.784974 # ok 336 event_spurious.0.46
7163 16:35:54.785064 # ok 337 get_value.0.45
7164 16:35:54.791722 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
7165 16:35:54.795360 # not ok 338 name.0.45
7166 16:35:54.795439 # ok 339 write_default.0.45
7167 16:35:54.798479 # ok 340 write_valid.0.45
7168 16:35:54.801595 # ok 341 write_invalid.0.45
7169 16:35:54.804815 # ok 342 event_missing.0.45
7170 16:35:54.808408 # ok 343 event_spurious.0.45
7171 16:35:54.808486 # ok 344 get_value.0.44
7172 16:35:54.815087 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
7173 16:35:54.818223 # not ok 345 name.0.44
7174 16:35:54.818299 # ok 346 write_default.0.44
7175 16:35:54.821437 # ok 347 write_valid.0.44
7176 16:35:54.825123 # ok 348 write_invalid.0.44
7177 16:35:54.828362 # ok 349 event_missing.0.44
7178 16:35:54.828433 # ok 350 event_spurious.0.44
7179 16:35:54.831626 # ok 351 get_value.0.43
7180 16:35:54.838104 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
7181 16:35:54.838183 # not ok 352 name.0.43
7182 16:35:54.841754 # ok 353 write_default.0.43
7183 16:35:54.844852 # ok 354 write_valid.0.43
7184 16:35:54.848328 # ok 355 write_invalid.0.43
7185 16:35:54.848403 # ok 356 event_missing.0.43
7186 16:35:54.851125 # ok 357 event_spurious.0.43
7187 16:35:54.854669 # ok 358 get_value.0.42
7188 16:35:54.861193 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
7189 16:35:54.861270 # not ok 359 name.0.42
7190 16:35:54.864593 # ok 360 write_default.0.42
7191 16:35:54.867779 # ok 361 write_valid.0.42
7192 16:35:54.871028 # ok 362 write_invalid.0.42
7193 16:35:54.871109 # ok 363 event_missing.0.42
7194 16:35:54.874854 # ok 364 event_spurious.0.42
7195 16:35:54.878096 # ok 365 get_value.0.41
7196 16:35:54.884488 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
7197 16:35:54.884590 # not ok 366 name.0.41
7198 16:35:54.887764 # ok 367 write_default.0.41
7199 16:35:54.890981 # ok 368 write_valid.0.41
7200 16:35:54.894243 # ok 369 write_invalid.0.41
7201 16:35:54.897923 # ok 370 event_missing.0.41
7202 16:35:54.898065 # ok 371 event_spurious.0.41
7203 16:35:54.900853 # ok 372 get_value.0.40
7204 16:35:54.907452 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7205 16:35:54.907523 # not ok 373 name.0.40
7206 16:35:54.911010 # ok 374 write_default.0.40
7207 16:35:54.914205 # ok 375 write_valid.0.40
7208 16:35:54.918008 # ok 376 write_invalid.0.40
7209 16:35:54.921025 # ok 377 event_missing.0.40
7210 16:35:54.921122 # ok 378 event_spurious.0.40
7211 16:35:54.924180 # ok 379 get_value.0.39
7212 16:35:54.931181 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7213 16:35:54.934465 # not ok 380 name.0.39
7214 16:35:54.934537 # ok 381 write_default.0.39
7215 16:35:54.937597 # ok 382 write_valid.0.39
7216 16:35:54.940937 # ok 383 write_invalid.0.39
7217 16:35:54.944130 # ok 384 event_missing.0.39
7218 16:35:54.947273 # ok 385 event_spurious.0.39
7219 16:35:54.947344 # ok 386 get_value.0.38
7220 16:35:54.954210 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7221 16:35:54.957366 # not ok 387 name.0.38
7222 16:35:54.960994 # ok 388 write_default.0.38
7223 16:35:54.961062 # ok 389 write_valid.0.38
7224 16:35:54.964331 # ok 390 write_invalid.0.38
7225 16:35:54.967701 # ok 391 event_missing.0.38
7226 16:35:54.970658 # ok 392 event_spurious.0.38
7227 16:35:54.970725 # ok 393 get_value.0.37
7228 16:35:54.977245 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7229 16:35:54.981016 # not ok 394 name.0.37
7230 16:35:54.984224 # ok 395 write_default.0.37
7231 16:35:54.987453 # ok 396 write_valid.0.37
7232 16:35:54.987519 # ok 397 write_invalid.0.37
7233 16:35:54.990659 # ok 398 event_missing.0.37
7234 16:35:54.993816 # ok 399 event_spurious.0.37
7235 16:35:54.997059 # ok 400 get_value.0.36
7236 16:35:55.003969 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7237 16:35:55.004048 # not ok 401 name.0.36
7238 16:35:55.007088 # ok 402 write_default.0.36
7239 16:35:55.010869 # ok 403 write_valid.0.36
7240 16:35:55.010934 # ok 404 write_invalid.0.36
7241 16:35:55.014045 # ok 405 event_missing.0.36
7242 16:35:55.017092 # ok 406 event_spurious.0.36
7243 16:35:55.020606 # ok 407 get_value.0.35
7244 16:35:55.027436 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7245 16:35:55.027516 # not ok 408 name.0.35
7246 16:35:55.030791 # ok 409 write_default.0.35
7247 16:35:55.033757 # ok 410 write_valid.0.35
7248 16:35:55.037555 # ok 411 write_invalid.0.35
7249 16:35:55.037655 # ok 412 event_missing.0.35
7250 16:35:55.040830 # ok 413 event_spurious.0.35
7251 16:35:55.043893 # ok 414 get_value.0.34
7252 16:35:55.051013 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7253 16:35:55.051086 # not ok 415 name.0.34
7254 16:35:55.054061 # ok 416 write_default.0.34
7255 16:35:55.057307 # ok 417 write_valid.0.34
7256 16:35:55.060612 # ok 418 write_invalid.0.34
7257 16:35:55.060681 # ok 419 event_missing.0.34
7258 16:35:55.063830 # ok 420 event_spurious.0.34
7259 16:35:55.066966 # ok 421 get_value.0.33
7260 16:35:55.073836 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7261 16:35:55.073926 # not ok 422 name.0.33
7262 16:35:55.077455 # ok 423 write_default.0.33
7263 16:35:55.080289 # ok 424 write_valid.0.33
7264 16:35:55.083530 # ok 425 write_invalid.0.33
7265 16:35:55.087123 # ok 426 event_missing.0.33
7266 16:35:55.087216 # ok 427 event_spurious.0.33
7267 16:35:55.090358 # ok 428 get_value.0.32
7268 16:35:55.096858 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7269 16:35:55.100741 # not ok 429 name.0.32
7270 16:35:55.100810 # ok 430 write_default.0.32
7271 16:35:55.103850 # ok 431 write_valid.0.32
7272 16:35:55.107026 # ok 432 write_invalid.0.32
7273 16:35:55.110149 # ok 433 event_missing.0.32
7274 16:35:55.113467 # ok 434 event_spurious.0.32
7275 16:35:55.113542 # ok 435 get_value.0.31
7276 16:35:55.120463 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7277 16:35:55.123798 # not ok 436 name.0.31
7278 16:35:55.126865 # ok 437 write_default.0.31
7279 16:35:55.126934 # ok 438 write_valid.0.31
7280 16:35:55.129947 # ok 439 write_invalid.0.31
7281 16:35:55.133698 # ok 440 event_missing.0.31
7282 16:35:55.136746 # ok 441 event_spurious.0.31
7283 16:35:55.136814 # ok 442 get_value.0.30
7284 16:35:55.143470 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7285 16:35:55.146827 # not ok 443 name.0.30
7286 16:35:55.150137 # ok 444 write_default.0.30
7287 16:35:55.153357 # ok 445 write_valid.0.30
7288 16:35:55.153433 # ok 446 write_invalid.0.30
7289 16:35:55.157014 # ok 447 event_missing.0.30
7290 16:35:55.160173 # ok 448 event_spurious.0.30
7291 16:35:55.160249 # ok 449 get_value.0.29
7292 16:35:55.163384 # ok 450 name.0.29
7293 16:35:55.166688 # ok 451 write_default.0.29
7294 16:35:55.169850 # ok 452 write_valid.0.29
7295 16:35:55.169969 # ok 453 write_invalid.0.29
7296 16:35:55.172972 # ok 454 event_missing.0.29
7297 16:35:55.176769 # ok 455 event_spurious.0.29
7298 16:35:55.180011 # ok 456 get_value.0.28
7299 16:35:55.180087 # ok 457 name.0.28
7300 16:35:55.183184 # ok 458 write_default.0.28
7301 16:35:55.186466 # ok 459 write_valid.0.28
7302 16:35:55.186542 # ok 460 write_invalid.0.28
7303 16:35:55.190058 # ok 461 event_missing.0.28
7304 16:35:55.192991 # ok 462 event_spurious.0.28
7305 16:35:55.196284 # ok 463 get_value.0.27
7306 16:35:55.196354 # ok 464 name.0.27
7307 16:35:55.199852 # ok 465 write_default.0.27
7308 16:35:55.202998 # ok 466 write_valid.0.27
7309 16:35:55.206219 # ok 467 write_invalid.0.27
7310 16:35:55.206297 # ok 468 event_missing.0.27
7311 16:35:55.209879 # ok 469 event_spurious.0.27
7312 16:35:55.213082 # ok 470 get_value.0.26
7313 16:35:55.213151 # ok 471 name.0.26
7314 16:35:55.216214 # ok 472 write_default.0.26
7315 16:35:55.219403 # ok 473 write_valid.0.26
7316 16:35:55.222566 # ok 474 write_invalid.0.26
7317 16:35:55.226473 # ok 475 event_missing.0.26
7318 16:35:55.226575 # ok 476 event_spurious.0.26
7319 16:35:55.229563 # ok 477 get_value.0.25
7320 16:35:55.232842 # ok 478 name.0.25
7321 16:35:55.232910 # ok 479 write_default.0.25
7322 16:35:55.236141 # ok 480 write_valid.0.25
7323 16:35:55.239359 # ok 481 write_invalid.0.25
7324 16:35:55.242549 # ok 482 event_missing.0.25
7325 16:35:55.242620 # ok 483 event_spurious.0.25
7326 16:35:55.246383 # ok 484 get_value.0.24
7327 16:35:55.249496 # ok 485 name.0.24
7328 16:35:55.252580 # ok 486 write_default.0.24
7329 16:35:55.252649 # ok 487 write_valid.0.24
7330 16:35:55.256215 # ok 488 write_invalid.0.24
7331 16:35:55.259314 # ok 489 event_missing.0.24
7332 16:35:55.262347 # ok 490 event_spurious.0.24
7333 16:35:55.262435 # ok 491 get_value.0.23
7334 16:35:55.265887 # ok 492 name.0.23
7335 16:35:55.269513 # ok 493 write_default.0.23
7336 16:35:55.269594 # ok 494 write_valid.0.23
7337 16:35:55.272798 # ok 495 write_invalid.0.23
7338 16:35:55.276110 # ok 496 event_missing.0.23
7339 16:35:55.279135 # ok 497 event_spurious.0.23
7340 16:35:55.279214 # ok 498 get_value.0.22
7341 16:35:55.282382 # ok 499 name.0.22
7342 16:35:55.286254 # ok 500 write_default.0.22
7343 16:35:55.286327 # ok 501 write_valid.0.22
7344 16:35:55.289497 # ok 502 write_invalid.0.22
7345 16:35:55.292599 # ok 503 event_missing.0.22
7346 16:35:55.295723 # ok 504 event_spurious.0.22
7347 16:35:55.299546 # ok 505 get_value.0.21
7348 16:35:55.306137 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7349 16:35:55.306225 # not ok 506 name.0.21
7350 16:35:55.309080 # ok 507 write_default.0.21
7351 16:35:55.312396 # ok 508 write_valid.0.21
7352 16:35:55.312523 # ok 509 write_invalid.0.21
7353 16:35:55.315695 # ok 510 event_missing.0.21
7354 16:35:55.318971 # ok 511 event_spurious.0.21
7355 16:35:55.322253 # ok 512 get_value.0.20
7356 16:35:55.329350 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7357 16:35:55.329434 # not ok 513 name.0.20
7358 16:35:55.332570 # ok 514 write_default.0.20
7359 16:35:55.335593 # ok 515 write_valid.0.20
7360 16:35:55.338772 # ok 516 write_invalid.0.20
7361 16:35:55.342634 # ok 517 event_missing.0.20
7362 16:35:55.342817 # ok 518 event_spurious.0.20
7363 16:35:55.345735 # ok 519 get_value.0.19
7364 16:35:55.352146 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7365 16:35:55.355412 # not ok 520 name.0.19
7366 16:35:55.355490 # ok 521 write_default.0.19
7367 16:35:55.359251 # ok 522 write_valid.0.19
7368 16:35:55.362495 # ok 523 write_invalid.0.19
7369 16:35:55.365696 # ok 524 event_missing.0.19
7370 16:35:55.365788 # ok 525 event_spurious.0.19
7371 16:35:55.368666 # ok 526 get_value.0.18
7372 16:35:55.375580 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7373 16:35:55.378589 # not ok 527 name.0.18
7374 16:35:55.382435 # ok 528 write_default.0.18
7375 16:35:55.382511 # ok 529 write_valid.0.18
7376 16:35:55.385369 # ok 530 write_invalid.0.18
7377 16:35:55.388947 # ok 531 event_missing.0.18
7378 16:35:55.392375 # ok 532 event_spurious.0.18
7379 16:35:55.392480 # ok 533 get_value.0.17
7380 16:35:55.398531 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7381 16:35:55.401738 # not ok 534 name.0.17
7382 16:35:55.405478 # ok 535 write_default.0.17
7383 16:35:55.405570 # ok 536 write_valid.0.17
7384 16:35:55.408672 # ok 537 write_invalid.0.17
7385 16:35:55.411676 # ok 538 event_missing.0.17
7386 16:35:55.415538 # ok 539 event_spurious.0.17
7387 16:35:55.415613 # ok 540 get_value.0.16
7388 16:35:55.421755 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7389 16:35:55.425386 # not ok 541 name.0.16
7390 16:35:55.428197 # ok 542 write_default.0.16
7391 16:35:55.428267 # ok 543 write_valid.0.16
7392 16:35:55.431650 # ok 544 write_invalid.0.16
7393 16:35:55.435202 # ok 545 event_missing.0.16
7394 16:35:55.438318 # ok 546 event_spurious.0.16
7395 16:35:55.441576 # ok 547 get_value.0.15
7396 16:35:55.444981 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7397 16:35:55.448281 # not ok 548 name.0.15
7398 16:35:55.451587 # ok 549 write_default.0.15
7399 16:35:55.454877 # ok 550 write_valid.0.15
7400 16:35:55.454980 # ok 551 write_invalid.0.15
7401 16:35:55.458048 # ok 552 event_missing.0.15
7402 16:35:55.461791 # ok 553 event_spurious.0.15
7403 16:35:55.465016 # ok 554 get_value.0.14
7404 16:35:55.468323 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7405 16:35:55.471647 # not ok 555 name.0.14
7406 16:35:55.475018 # ok 556 write_default.0.14
7407 16:35:55.478181 # ok 557 write_valid.0.14
7408 16:35:55.478257 # ok 558 write_invalid.0.14
7409 16:35:55.481858 # ok 559 event_missing.0.14
7410 16:35:55.485058 # ok 560 event_spurious.0.14
7411 16:35:55.488365 # ok 561 get_value.0.13
7412 16:35:55.491580 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7413 16:35:55.494688 # not ok 562 name.0.13
7414 16:35:55.498866 # ok 563 write_default.0.13
7415 16:35:55.501515 # ok 564 write_valid.0.13
7416 16:35:55.501589 # ok 565 write_invalid.0.13
7417 16:35:55.504963 # ok 566 event_missing.0.13
7418 16:35:55.508001 # ok 567 event_spurious.0.13
7419 16:35:55.511461 # ok 568 get_value.0.12
7420 16:35:55.515059 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7421 16:35:55.518162 # not ok 569 name.0.12
7422 16:35:55.521354 # ok 570 write_default.0.12
7423 16:35:55.524469 # ok 571 write_valid.0.12
7424 16:35:55.524544 # ok 572 write_invalid.0.12
7425 16:35:55.528529 # ok 573 event_missing.0.12
7426 16:35:55.531741 # ok 574 event_spurious.0.12
7427 16:35:55.534755 # ok 575 get_value.0.11
7428 16:35:55.538277 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7429 16:35:55.541294 # not ok 576 name.0.11
7430 16:35:55.544430 # ok 577 write_default.0.11
7431 16:35:55.544536 # ok 578 write_valid.0.11
7432 16:35:55.548123 # ok 579 write_invalid.0.11
7433 16:35:55.551348 # ok 580 event_missing.0.11
7434 16:35:55.554608 # ok 581 event_spurious.0.11
7435 16:35:55.554706 # ok 582 get_value.0.10
7436 16:35:55.561218 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7437 16:35:55.564435 # not ok 583 name.0.10
7438 16:35:55.567608 # ok 584 write_default.0.10
7439 16:35:55.571420 # ok 585 write_valid.0.10
7440 16:35:55.571533 # ok 586 write_invalid.0.10
7441 16:35:55.574560 # ok 587 event_missing.0.10
7442 16:35:55.577691 # ok 588 event_spurious.0.10
7443 16:35:55.580879 # ok 589 get_value.0.9
7444 16:35:55.584121 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7445 16:35:55.587791 # not ok 590 name.0.9
7446 16:35:55.590923 # ok 591 write_default.0.9
7447 16:35:55.591038 # ok 592 write_valid.0.9
7448 16:35:55.594264 # ok 593 write_invalid.0.9
7449 16:35:55.597570 # ok 594 event_missing.0.9
7450 16:35:55.600787 # ok 595 event_spurious.0.9
7451 16:35:55.600895 # ok 596 get_value.0.8
7452 16:35:55.607855 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7453 16:35:55.610964 # not ok 597 name.0.8
7454 16:35:55.611044 # ok 598 write_default.0.8
7455 16:35:55.614095 # ok 599 write_valid.0.8
7456 16:35:55.617204 # ok 600 write_invalid.0.8
7457 16:35:55.620757 # ok 601 event_missing.0.8
7458 16:35:55.620890 # ok 602 event_spurious.0.8
7459 16:35:55.624007 # ok 603 get_value.0.7
7460 16:35:55.630757 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7461 16:35:55.630890 # not ok 604 name.0.7
7462 16:35:55.633853 # ok 605 write_default.0.7
7463 16:35:55.637045 # ok 606 write_valid.0.7
7464 16:35:55.637162 # ok 607 write_invalid.0.7
7465 16:35:55.640164 # ok 608 event_missing.0.7
7466 16:35:55.643914 # ok 609 event_spurious.0.7
7467 16:35:55.647055 # ok 610 get_value.0.6
7468 16:35:55.650546 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7469 16:35:55.653636 # not ok 611 name.0.6
7470 16:35:55.656642 # ok 612 write_default.0.6
7471 16:35:55.656742 # ok 613 write_valid.0.6
7472 16:35:55.660493 # ok 614 write_invalid.0.6
7473 16:35:55.663717 # ok 615 event_missing.0.6
7474 16:35:55.667111 # ok 616 event_spurious.0.6
7475 16:35:55.667212 # ok 617 get_value.0.5
7476 16:35:55.670406 # ok 618 name.0.5
7477 16:35:55.673511 # ok 619 write_default.0.5
7478 16:35:55.676537 # # No event generated for MTKAIF_DMIC
7479 16:35:55.680405 # # No event generated for MTKAIF_DMIC
7480 16:35:55.683653 # ok 620 write_valid.0.5
7481 16:35:55.683744 # ok 621 write_invalid.0.5
7482 16:35:55.686825 # not ok 622 event_missing.0.5
7483 16:35:55.689777 # ok 623 event_spurious.0.5
7484 16:35:55.693490 # ok 624 get_value.0.4
7485 16:35:55.693595 # ok 625 name.0.4
7486 16:35:55.696708 # ok 626 write_default.0.4
7487 16:35:55.699951 # # No event generated for I2S5_HD_Mux
7488 16:35:55.703220 # # No event generated for I2S5_HD_Mux
7489 16:35:55.706423 # ok 627 write_valid.0.4
7490 16:35:55.706507 # ok 628 write_invalid.0.4
7491 16:35:55.710214 # not ok 629 event_missing.0.4
7492 16:35:55.713338 # ok 630 event_spurious.0.4
7493 16:35:55.716549 # ok 631 get_value.0.3
7494 16:35:55.716633 # ok 632 name.0.3
7495 16:35:55.719736 # ok 633 write_default.0.3
7496 16:35:55.723488 # # No event generated for I2S3_HD_Mux
7497 16:35:55.726667 # # No event generated for I2S3_HD_Mux
7498 16:35:55.729887 # ok 634 write_valid.0.3
7499 16:35:55.732986 # ok 635 write_invalid.0.3
7500 16:35:55.733120 # not ok 636 event_missing.0.3
7501 16:35:55.736607 # ok 637 event_spurious.0.3
7502 16:35:55.739534 # ok 638 get_value.0.2
7503 16:35:55.739651 # ok 639 name.0.2
7504 16:35:55.742902 # ok 640 write_default.0.2
7505 16:35:55.746200 # # No event generated for I2S2_HD_Mux
7506 16:35:55.749738 # # No event generated for I2S2_HD_Mux
7507 16:35:55.752725 # ok 641 write_valid.0.2
7508 16:35:55.756448 # ok 642 write_invalid.0.2
7509 16:35:55.756586 # not ok 643 event_missing.0.2
7510 16:35:55.759395 # ok 644 event_spurious.0.2
7511 16:35:55.762782 # ok 645 get_value.0.1
7512 16:35:55.762864 # ok 646 name.0.1
7513 16:35:55.765734 # ok 647 write_default.0.1
7514 16:35:55.769011 # # No event generated for I2S1_HD_Mux
7515 16:35:55.772874 # # No event generated for I2S1_HD_Mux
7516 16:35:55.776319 # ok 648 write_valid.0.1
7517 16:35:55.779355 # ok 649 write_invalid.0.1
7518 16:35:55.779468 # not ok 650 event_missing.0.1
7519 16:35:55.782436 # ok 651 event_spurious.0.1
7520 16:35:55.786075 # ok 652 get_value.0.0
7521 16:35:55.786194 # ok 653 name.0.0
7522 16:35:55.789370 # ok 654 write_default.0.0
7523 16:35:55.792595 # # No event generated for I2S0_HD_Mux
7524 16:35:55.795659 # # No event generated for I2S0_HD_Mux
7525 16:35:55.799589 # ok 655 write_valid.0.0
7526 16:35:55.802657 # ok 656 write_invalid.0.0
7527 16:35:55.805836 # not ok 657 event_missing.0.0
7528 16:35:55.805939 # ok 658 event_spurious.0.0
7529 16:35:55.812321 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7530 16:35:55.816063 ok 1 selftests: alsa: mixer-test
7531 16:35:57.372335 alsa_mixer-test_get_value_0_93 pass
7532 16:35:57.376063 alsa_mixer-test_name_0_93 pass
7533 16:35:57.379349 alsa_mixer-test_write_default_0_93 pass
7534 16:35:57.382459 alsa_mixer-test_write_valid_0_93 pass
7535 16:35:57.389304 alsa_mixer-test_write_invalid_0_93 pass
7536 16:35:57.392413 alsa_mixer-test_event_missing_0_93 pass
7537 16:35:57.395612 alsa_mixer-test_event_spurious_0_93 pass
7538 16:35:57.399535 alsa_mixer-test_get_value_0_92 pass
7539 16:35:57.399611 alsa_mixer-test_name_0_92 pass
7540 16:35:57.406162 alsa_mixer-test_write_default_0_92 pass
7541 16:35:57.409234 alsa_mixer-test_write_valid_0_92 pass
7542 16:35:57.412506 alsa_mixer-test_write_invalid_0_92 pass
7543 16:35:57.415724 alsa_mixer-test_event_missing_0_92 pass
7544 16:35:57.419395 alsa_mixer-test_event_spurious_0_92 pass
7545 16:35:57.422641 alsa_mixer-test_get_value_0_91 pass
7546 16:35:57.425744 alsa_mixer-test_name_0_91 pass
7547 16:35:57.429363 alsa_mixer-test_write_default_0_91 pass
7548 16:35:57.432338 alsa_mixer-test_write_valid_0_91 pass
7549 16:35:57.435533 alsa_mixer-test_write_invalid_0_91 pass
7550 16:35:57.438751 alsa_mixer-test_event_missing_0_91 pass
7551 16:35:57.442594 alsa_mixer-test_event_spurious_0_91 pass
7552 16:35:57.445768 alsa_mixer-test_get_value_0_90 pass
7553 16:35:57.449026 alsa_mixer-test_name_0_90 pass
7554 16:35:57.452179 alsa_mixer-test_write_default_0_90 pass
7555 16:35:57.455383 alsa_mixer-test_write_valid_0_90 pass
7556 16:35:57.459168 alsa_mixer-test_write_invalid_0_90 pass
7557 16:35:57.465747 alsa_mixer-test_event_missing_0_90 pass
7558 16:35:57.468847 alsa_mixer-test_event_spurious_0_90 pass
7559 16:35:57.471965 alsa_mixer-test_get_value_0_89 pass
7560 16:35:57.475132 alsa_mixer-test_name_0_89 pass
7561 16:35:57.478940 alsa_mixer-test_write_default_0_89 pass
7562 16:35:57.482065 alsa_mixer-test_write_valid_0_89 pass
7563 16:35:57.485764 alsa_mixer-test_write_invalid_0_89 pass
7564 16:35:57.488890 alsa_mixer-test_event_missing_0_89 pass
7565 16:35:57.491788 alsa_mixer-test_event_spurious_0_89 pass
7566 16:35:57.495457 alsa_mixer-test_get_value_0_88 pass
7567 16:35:57.498419 alsa_mixer-test_name_0_88 pass
7568 16:35:57.501658 alsa_mixer-test_write_default_0_88 pass
7569 16:35:57.505222 alsa_mixer-test_write_valid_0_88 fail
7570 16:35:57.508435 alsa_mixer-test_write_invalid_0_88 pass
7571 16:35:57.511499 alsa_mixer-test_event_missing_0_88 pass
7572 16:35:57.518287 alsa_mixer-test_event_spurious_0_88 fail
7573 16:35:57.521429 alsa_mixer-test_get_value_0_87 pass
7574 16:35:57.521520 alsa_mixer-test_name_0_87 pass
7575 16:35:57.528345 alsa_mixer-test_write_default_0_87 pass
7576 16:35:57.531559 alsa_mixer-test_write_valid_0_87 pass
7577 16:35:57.534513 alsa_mixer-test_write_invalid_0_87 pass
7578 16:35:57.538112 alsa_mixer-test_event_missing_0_87 pass
7579 16:35:57.541226 alsa_mixer-test_event_spurious_0_87 pass
7580 16:35:57.544498 alsa_mixer-test_get_value_0_86 pass
7581 16:35:57.548340 alsa_mixer-test_name_0_86 pass
7582 16:35:57.551411 alsa_mixer-test_write_default_0_86 pass
7583 16:35:57.554575 alsa_mixer-test_write_valid_0_86 fail
7584 16:35:57.557709 alsa_mixer-test_write_invalid_0_86 pass
7585 16:35:57.561593 alsa_mixer-test_event_missing_0_86 pass
7586 16:35:57.564237 alsa_mixer-test_event_spurious_0_86 pass
7587 16:35:57.567931 alsa_mixer-test_get_value_0_85 pass
7588 16:35:57.571141 alsa_mixer-test_name_0_85 pass
7589 16:35:57.574320 alsa_mixer-test_write_default_0_85 pass
7590 16:35:57.581128 alsa_mixer-test_write_valid_0_85 fail
7591 16:35:57.584238 alsa_mixer-test_write_invalid_0_85 pass
7592 16:35:57.587343 alsa_mixer-test_event_missing_0_85 pass
7593 16:35:57.591203 alsa_mixer-test_event_spurious_0_85 pass
7594 16:35:57.594122 alsa_mixer-test_get_value_0_84 pass
7595 16:35:57.597268 alsa_mixer-test_name_0_84 pass
7596 16:35:57.601077 alsa_mixer-test_write_default_0_84 pass
7597 16:35:57.604166 alsa_mixer-test_write_valid_0_84 pass
7598 16:35:57.607260 alsa_mixer-test_write_invalid_0_84 pass
7599 16:35:57.610819 alsa_mixer-test_event_missing_0_84 pass
7600 16:35:57.614128 alsa_mixer-test_event_spurious_0_84 pass
7601 16:35:57.617159 alsa_mixer-test_get_value_0_83 pass
7602 16:35:57.620703 alsa_mixer-test_name_0_83 pass
7603 16:35:57.623679 alsa_mixer-test_write_default_0_83 pass
7604 16:35:57.627285 alsa_mixer-test_write_valid_0_83 pass
7605 16:35:57.633571 alsa_mixer-test_write_invalid_0_83 pass
7606 16:35:57.637379 alsa_mixer-test_event_missing_0_83 pass
7607 16:35:57.640848 alsa_mixer-test_event_spurious_0_83 pass
7608 16:35:57.643798 alsa_mixer-test_get_value_0_82 pass
7609 16:35:57.646896 alsa_mixer-test_name_0_82 pass
7610 16:35:57.650626 alsa_mixer-test_write_default_0_82 skip
7611 16:35:57.653838 alsa_mixer-test_write_valid_0_82 skip
7612 16:35:57.657162 alsa_mixer-test_write_invalid_0_82 skip
7613 16:35:57.660306 alsa_mixer-test_event_missing_0_82 pass
7614 16:35:57.664026 alsa_mixer-test_event_spurious_0_82 pass
7615 16:35:57.667324 alsa_mixer-test_get_value_0_81 pass
7616 16:35:57.670463 alsa_mixer-test_name_0_81 pass
7617 16:35:57.673693 alsa_mixer-test_write_default_0_81 pass
7618 16:35:57.677013 alsa_mixer-test_write_valid_0_81 pass
7619 16:35:57.680115 alsa_mixer-test_write_invalid_0_81 fail
7620 16:35:57.683855 alsa_mixer-test_event_missing_0_81 fail
7621 16:35:57.690207 alsa_mixer-test_event_spurious_0_81 pass
7622 16:35:57.693329 alsa_mixer-test_get_value_0_80 pass
7623 16:35:57.693425 alsa_mixer-test_name_0_80 pass
7624 16:35:57.700269 alsa_mixer-test_write_default_0_80 pass
7625 16:35:57.703567 alsa_mixer-test_write_valid_0_80 pass
7626 16:35:57.706779 alsa_mixer-test_write_invalid_0_80 pass
7627 16:35:57.709902 alsa_mixer-test_event_missing_0_80 pass
7628 16:35:57.713535 alsa_mixer-test_event_spurious_0_80 pass
7629 16:35:57.716649 alsa_mixer-test_get_value_0_79 fail
7630 16:35:57.720180 alsa_mixer-test_name_0_79 pass
7631 16:35:57.723236 alsa_mixer-test_write_default_0_79 fail
7632 16:35:57.727063 alsa_mixer-test_write_valid_0_79 fail
7633 16:35:57.730058 alsa_mixer-test_write_invalid_0_79 fail
7634 16:35:57.733169 alsa_mixer-test_event_missing_0_79 pass
7635 16:35:57.736674 alsa_mixer-test_event_spurious_0_79 pass
7636 16:35:57.739814 alsa_mixer-test_get_value_0_78 fail
7637 16:35:57.743443 alsa_mixer-test_name_0_78 pass
7638 16:35:57.746759 alsa_mixer-test_write_default_0_78 fail
7639 16:35:57.750133 alsa_mixer-test_write_valid_0_78 fail
7640 16:35:57.753538 alsa_mixer-test_write_invalid_0_78 fail
7641 16:35:57.756520 alsa_mixer-test_event_missing_0_78 pass
7642 16:35:57.763518 alsa_mixer-test_event_spurious_0_78 pass
7643 16:35:57.766618 alsa_mixer-test_get_value_0_77 fail
7644 16:35:57.769956 alsa_mixer-test_name_0_77 pass
7645 16:35:57.773692 alsa_mixer-test_write_default_0_77 fail
7646 16:35:57.776871 alsa_mixer-test_write_valid_0_77 fail
7647 16:35:57.780158 alsa_mixer-test_write_invalid_0_77 fail
7648 16:35:57.783322 alsa_mixer-test_event_missing_0_77 pass
7649 16:35:57.787101 alsa_mixer-test_event_spurious_0_77 pass
7650 16:35:57.790128 alsa_mixer-test_get_value_0_76 pass
7651 16:35:57.793292 alsa_mixer-test_name_0_76 fail
7652 16:35:57.796421 alsa_mixer-test_write_default_0_76 pass
7653 16:35:57.803496 alsa_mixer-test_write_valid_0_76 pass
7654 16:35:57.806544 alsa_mixer-test_write_invalid_0_76 pass
7655 16:35:57.810185 alsa_mixer-test_event_missing_0_76 pass
7656 16:35:57.813410 alsa_mixer-test_event_spurious_0_76 pass
7657 16:35:57.816518 alsa_mixer-test_get_value_0_75 pass
7658 16:35:57.819637 alsa_mixer-test_name_0_75 fail
7659 16:35:57.823489 alsa_mixer-test_write_default_0_75 pass
7660 16:35:57.826454 alsa_mixer-test_write_valid_0_75 pass
7661 16:35:57.833307 alsa_mixer-test_write_invalid_0_75 pass
7662 16:35:57.836392 alsa_mixer-test_event_missing_0_75 pass
7663 16:35:57.839507 alsa_mixer-test_event_spurious_0_75 pass
7664 16:35:57.843273 alsa_mixer-test_get_value_0_74 pass
7665 16:35:57.846185 alsa_mixer-test_name_0_74 fail
7666 16:35:57.849343 alsa_mixer-test_write_default_0_74 pass
7667 16:35:57.853169 alsa_mixer-test_write_valid_0_74 pass
7668 16:35:57.856400 alsa_mixer-test_write_invalid_0_74 pass
7669 16:35:57.859706 alsa_mixer-test_event_missing_0_74 pass
7670 16:35:57.862709 alsa_mixer-test_event_spurious_0_74 pass
7671 16:35:57.866222 alsa_mixer-test_get_value_0_73 pass
7672 16:35:57.869476 alsa_mixer-test_name_0_73 fail
7673 16:35:57.872642 alsa_mixer-test_write_default_0_73 pass
7674 16:35:57.875811 alsa_mixer-test_write_valid_0_73 pass
7675 16:35:57.879603 alsa_mixer-test_write_invalid_0_73 pass
7676 16:35:57.882778 alsa_mixer-test_event_missing_0_73 pass
7677 16:35:57.889321 alsa_mixer-test_event_spurious_0_73 pass
7678 16:35:57.892372 alsa_mixer-test_get_value_0_72 pass
7679 16:35:57.892475 alsa_mixer-test_name_0_72 fail
7680 16:35:57.899243 alsa_mixer-test_write_default_0_72 pass
7681 16:35:57.902449 alsa_mixer-test_write_valid_0_72 pass
7682 16:35:57.905602 alsa_mixer-test_write_invalid_0_72 pass
7683 16:35:57.909439 alsa_mixer-test_event_missing_0_72 pass
7684 16:35:57.912396 alsa_mixer-test_event_spurious_0_72 pass
7685 16:35:57.915593 alsa_mixer-test_get_value_0_71 pass
7686 16:35:57.918732 alsa_mixer-test_name_0_71 fail
7687 16:35:57.922122 alsa_mixer-test_write_default_0_71 pass
7688 16:35:57.925478 alsa_mixer-test_write_valid_0_71 pass
7689 16:35:57.929262 alsa_mixer-test_write_invalid_0_71 pass
7690 16:35:57.932235 alsa_mixer-test_event_missing_0_71 pass
7691 16:35:57.935890 alsa_mixer-test_event_spurious_0_71 pass
7692 16:35:57.938887 alsa_mixer-test_get_value_0_70 pass
7693 16:35:57.942634 alsa_mixer-test_name_0_70 fail
7694 16:35:57.945823 alsa_mixer-test_write_default_0_70 pass
7695 16:35:57.949001 alsa_mixer-test_write_valid_0_70 pass
7696 16:35:57.952086 alsa_mixer-test_write_invalid_0_70 pass
7697 16:35:57.958944 alsa_mixer-test_event_missing_0_70 pass
7698 16:35:57.962151 alsa_mixer-test_event_spurious_0_70 pass
7699 16:35:57.965235 alsa_mixer-test_get_value_0_69 pass
7700 16:35:57.968996 alsa_mixer-test_name_0_69 fail
7701 16:35:57.971941 alsa_mixer-test_write_default_0_69 pass
7702 16:35:57.975607 alsa_mixer-test_write_valid_0_69 pass
7703 16:35:57.978734 alsa_mixer-test_write_invalid_0_69 pass
7704 16:35:57.981938 alsa_mixer-test_event_missing_0_69 pass
7705 16:35:57.985586 alsa_mixer-test_event_spurious_0_69 pass
7706 16:35:57.988734 alsa_mixer-test_get_value_0_68 pass
7707 16:35:57.992057 alsa_mixer-test_name_0_68 fail
7708 16:35:57.995133 alsa_mixer-test_write_default_0_68 pass
7709 16:35:57.998945 alsa_mixer-test_write_valid_0_68 pass
7710 16:35:58.002131 alsa_mixer-test_write_invalid_0_68 pass
7711 16:35:58.005266 alsa_mixer-test_event_missing_0_68 pass
7712 16:35:58.008939 alsa_mixer-test_event_spurious_0_68 pass
7713 16:35:58.012069 alsa_mixer-test_get_value_0_67 pass
7714 16:35:58.015164 alsa_mixer-test_name_0_67 fail
7715 16:35:58.018759 alsa_mixer-test_write_default_0_67 pass
7716 16:35:58.021834 alsa_mixer-test_write_valid_0_67 pass
7717 16:35:58.028754 alsa_mixer-test_write_invalid_0_67 pass
7718 16:35:58.032050 alsa_mixer-test_event_missing_0_67 pass
7719 16:35:58.035211 alsa_mixer-test_event_spurious_0_67 pass
7720 16:35:58.038453 alsa_mixer-test_get_value_0_66 pass
7721 16:35:58.042164 alsa_mixer-test_name_0_66 fail
7722 16:35:58.045185 alsa_mixer-test_write_default_0_66 pass
7723 16:35:58.048463 alsa_mixer-test_write_valid_0_66 pass
7724 16:35:58.052173 alsa_mixer-test_write_invalid_0_66 pass
7725 16:35:58.055179 alsa_mixer-test_event_missing_0_66 pass
7726 16:35:58.058366 alsa_mixer-test_event_spurious_0_66 pass
7727 16:35:58.062063 alsa_mixer-test_get_value_0_65 pass
7728 16:35:58.065144 alsa_mixer-test_name_0_65 fail
7729 16:35:58.068604 alsa_mixer-test_write_default_0_65 pass
7730 16:35:58.071753 alsa_mixer-test_write_valid_0_65 pass
7731 16:35:58.074990 alsa_mixer-test_write_invalid_0_65 pass
7732 16:35:58.078204 alsa_mixer-test_event_missing_0_65 pass
7733 16:35:58.081816 alsa_mixer-test_event_spurious_0_65 pass
7734 16:35:58.085314 alsa_mixer-test_get_value_0_64 pass
7735 16:35:58.088561 alsa_mixer-test_name_0_64 fail
7736 16:35:58.091778 alsa_mixer-test_write_default_0_64 pass
7737 16:35:58.094803 alsa_mixer-test_write_valid_0_64 pass
7738 16:35:58.097998 alsa_mixer-test_write_invalid_0_64 pass
7739 16:35:58.104996 alsa_mixer-test_event_missing_0_64 pass
7740 16:35:58.108163 alsa_mixer-test_event_spurious_0_64 pass
7741 16:35:58.111391 alsa_mixer-test_get_value_0_63 pass
7742 16:35:58.114694 alsa_mixer-test_name_0_63 fail
7743 16:35:58.117969 alsa_mixer-test_write_default_0_63 pass
7744 16:35:58.121797 alsa_mixer-test_write_valid_0_63 pass
7745 16:35:58.124890 alsa_mixer-test_write_invalid_0_63 pass
7746 16:35:58.128410 alsa_mixer-test_event_missing_0_63 pass
7747 16:35:58.131526 alsa_mixer-test_event_spurious_0_63 pass
7748 16:35:58.134793 alsa_mixer-test_get_value_0_62 pass
7749 16:35:58.137937 alsa_mixer-test_name_0_62 fail
7750 16:35:58.141608 alsa_mixer-test_write_default_0_62 pass
7751 16:35:58.144672 alsa_mixer-test_write_valid_0_62 pass
7752 16:35:58.147922 alsa_mixer-test_write_invalid_0_62 pass
7753 16:35:58.151656 alsa_mixer-test_event_missing_0_62 pass
7754 16:35:58.154605 alsa_mixer-test_event_spurious_0_62 pass
7755 16:35:58.157691 alsa_mixer-test_get_value_0_61 pass
7756 16:35:58.161331 alsa_mixer-test_name_0_61 fail
7757 16:35:58.164503 alsa_mixer-test_write_default_0_61 pass
7758 16:35:58.171461 alsa_mixer-test_write_valid_0_61 pass
7759 16:35:58.174449 alsa_mixer-test_write_invalid_0_61 pass
7760 16:35:58.177725 alsa_mixer-test_event_missing_0_61 pass
7761 16:35:58.181141 alsa_mixer-test_event_spurious_0_61 pass
7762 16:35:58.184318 alsa_mixer-test_get_value_0_60 pass
7763 16:35:58.188003 alsa_mixer-test_name_0_60 fail
7764 16:35:58.191110 alsa_mixer-test_write_default_0_60 pass
7765 16:35:58.194709 alsa_mixer-test_write_valid_0_60 pass
7766 16:35:58.197918 alsa_mixer-test_write_invalid_0_60 pass
7767 16:35:58.201010 alsa_mixer-test_event_missing_0_60 pass
7768 16:35:58.204190 alsa_mixer-test_event_spurious_0_60 pass
7769 16:35:58.207475 alsa_mixer-test_get_value_0_59 pass
7770 16:35:58.211184 alsa_mixer-test_name_0_59 fail
7771 16:35:58.214435 alsa_mixer-test_write_default_0_59 pass
7772 16:35:58.217699 alsa_mixer-test_write_valid_0_59 pass
7773 16:35:58.220931 alsa_mixer-test_write_invalid_0_59 pass
7774 16:35:58.227200 alsa_mixer-test_event_missing_0_59 pass
7775 16:35:58.230792 alsa_mixer-test_event_spurious_0_59 pass
7776 16:35:58.233967 alsa_mixer-test_get_value_0_58 pass
7777 16:35:58.237583 alsa_mixer-test_name_0_58 fail
7778 16:35:58.240764 alsa_mixer-test_write_default_0_58 pass
7779 16:35:58.244023 alsa_mixer-test_write_valid_0_58 pass
7780 16:35:58.247683 alsa_mixer-test_write_invalid_0_58 pass
7781 16:35:58.250870 alsa_mixer-test_event_missing_0_58 pass
7782 16:35:58.253929 alsa_mixer-test_event_spurious_0_58 pass
7783 16:35:58.257582 alsa_mixer-test_get_value_0_57 pass
7784 16:35:58.260590 alsa_mixer-test_name_0_57 fail
7785 16:35:58.264215 alsa_mixer-test_write_default_0_57 pass
7786 16:35:58.267392 alsa_mixer-test_write_valid_0_57 pass
7787 16:35:58.270460 alsa_mixer-test_write_invalid_0_57 pass
7788 16:35:58.273687 alsa_mixer-test_event_missing_0_57 pass
7789 16:35:58.280466 alsa_mixer-test_event_spurious_0_57 pass
7790 16:35:58.280562 alsa_mixer-test_get_value_0_56 pass
7791 16:35:58.284312 alsa_mixer-test_name_0_56 fail
7792 16:35:58.287459 alsa_mixer-test_write_default_0_56 pass
7793 16:35:58.293923 alsa_mixer-test_write_valid_0_56 pass
7794 16:35:58.297264 alsa_mixer-test_write_invalid_0_56 pass
7795 16:35:58.300698 alsa_mixer-test_event_missing_0_56 pass
7796 16:35:58.303604 alsa_mixer-test_event_spurious_0_56 pass
7797 16:35:58.307193 alsa_mixer-test_get_value_0_55 pass
7798 16:35:58.310503 alsa_mixer-test_name_0_55 fail
7799 16:35:58.313311 alsa_mixer-test_write_default_0_55 pass
7800 16:35:58.317056 alsa_mixer-test_write_valid_0_55 pass
7801 16:35:58.320301 alsa_mixer-test_write_invalid_0_55 pass
7802 16:35:58.323564 alsa_mixer-test_event_missing_0_55 pass
7803 16:35:58.326728 alsa_mixer-test_event_spurious_0_55 pass
7804 16:35:58.329969 alsa_mixer-test_get_value_0_54 pass
7805 16:35:58.333662 alsa_mixer-test_name_0_54 fail
7806 16:35:58.336802 alsa_mixer-test_write_default_0_54 pass
7807 16:35:58.340460 alsa_mixer-test_write_valid_0_54 pass
7808 16:35:58.343487 alsa_mixer-test_write_invalid_0_54 pass
7809 16:35:58.349868 alsa_mixer-test_event_missing_0_54 pass
7810 16:35:58.353636 alsa_mixer-test_event_spurious_0_54 pass
7811 16:35:58.356862 alsa_mixer-test_get_value_0_53 pass
7812 16:35:58.360071 alsa_mixer-test_name_0_53 fail
7813 16:35:58.363144 alsa_mixer-test_write_default_0_53 pass
7814 16:35:58.366599 alsa_mixer-test_write_valid_0_53 pass
7815 16:35:58.369560 alsa_mixer-test_write_invalid_0_53 pass
7816 16:35:58.373263 alsa_mixer-test_event_missing_0_53 pass
7817 16:35:58.376391 alsa_mixer-test_event_spurious_0_53 pass
7818 16:35:58.379603 alsa_mixer-test_get_value_0_52 pass
7819 16:35:58.382760 alsa_mixer-test_name_0_52 fail
7820 16:35:58.386584 alsa_mixer-test_write_default_0_52 pass
7821 16:35:58.389790 alsa_mixer-test_write_valid_0_52 pass
7822 16:35:58.392942 alsa_mixer-test_write_invalid_0_52 pass
7823 16:35:58.396009 alsa_mixer-test_event_missing_0_52 pass
7824 16:35:58.399913 alsa_mixer-test_event_spurious_0_52 pass
7825 16:35:58.403014 alsa_mixer-test_get_value_0_51 pass
7826 16:35:58.406097 alsa_mixer-test_name_0_51 fail
7827 16:35:58.409594 alsa_mixer-test_write_default_0_51 pass
7828 16:35:58.412833 alsa_mixer-test_write_valid_0_51 pass
7829 16:35:58.419423 alsa_mixer-test_write_invalid_0_51 pass
7830 16:35:58.422627 alsa_mixer-test_event_missing_0_51 pass
7831 16:35:58.426339 alsa_mixer-test_event_spurious_0_51 pass
7832 16:35:58.429670 alsa_mixer-test_get_value_0_50 pass
7833 16:35:58.432703 alsa_mixer-test_name_0_50 fail
7834 16:35:58.435891 alsa_mixer-test_write_default_0_50 pass
7835 16:35:58.439674 alsa_mixer-test_write_valid_0_50 pass
7836 16:35:58.443013 alsa_mixer-test_write_invalid_0_50 pass
7837 16:35:58.446159 alsa_mixer-test_event_missing_0_50 pass
7838 16:35:58.449238 alsa_mixer-test_event_spurious_0_50 pass
7839 16:35:58.452426 alsa_mixer-test_get_value_0_49 pass
7840 16:35:58.456169 alsa_mixer-test_name_0_49 fail
7841 16:35:58.459460 alsa_mixer-test_write_default_0_49 pass
7842 16:35:58.462731 alsa_mixer-test_write_valid_0_49 pass
7843 16:35:58.465858 alsa_mixer-test_write_invalid_0_49 pass
7844 16:35:58.469531 alsa_mixer-test_event_missing_0_49 pass
7845 16:35:58.472550 alsa_mixer-test_event_spurious_0_49 pass
7846 16:35:58.475634 alsa_mixer-test_get_value_0_48 pass
7847 16:35:58.479174 alsa_mixer-test_name_0_48 fail
7848 16:35:58.482222 alsa_mixer-test_write_default_0_48 pass
7849 16:35:58.486136 alsa_mixer-test_write_valid_0_48 pass
7850 16:35:58.489182 alsa_mixer-test_write_invalid_0_48 pass
7851 16:35:58.495524 alsa_mixer-test_event_missing_0_48 pass
7852 16:35:58.498669 alsa_mixer-test_event_spurious_0_48 pass
7853 16:35:58.502671 alsa_mixer-test_get_value_0_47 pass
7854 16:35:58.505785 alsa_mixer-test_name_0_47 fail
7855 16:35:58.508984 alsa_mixer-test_write_default_0_47 pass
7856 16:35:58.512143 alsa_mixer-test_write_valid_0_47 pass
7857 16:35:58.515381 alsa_mixer-test_write_invalid_0_47 pass
7858 16:35:58.519273 alsa_mixer-test_event_missing_0_47 pass
7859 16:35:58.521835 alsa_mixer-test_event_spurious_0_47 pass
7860 16:35:58.525544 alsa_mixer-test_get_value_0_46 pass
7861 16:35:58.528619 alsa_mixer-test_name_0_46 fail
7862 16:35:58.532268 alsa_mixer-test_write_default_0_46 pass
7863 16:35:58.535623 alsa_mixer-test_write_valid_0_46 pass
7864 16:35:58.538881 alsa_mixer-test_write_invalid_0_46 pass
7865 16:35:58.542123 alsa_mixer-test_event_missing_0_46 pass
7866 16:35:58.545287 alsa_mixer-test_event_spurious_0_46 pass
7867 16:35:58.548454 alsa_mixer-test_get_value_0_45 pass
7868 16:35:58.552160 alsa_mixer-test_name_0_45 fail
7869 16:35:58.555098 alsa_mixer-test_write_default_0_45 pass
7870 16:35:58.558843 alsa_mixer-test_write_valid_0_45 pass
7871 16:35:58.562057 alsa_mixer-test_write_invalid_0_45 pass
7872 16:35:58.565369 alsa_mixer-test_event_missing_0_45 pass
7873 16:35:58.568565 alsa_mixer-test_event_spurious_0_45 pass
7874 16:35:58.571766 alsa_mixer-test_get_value_0_44 pass
7875 16:35:58.574870 alsa_mixer-test_name_0_44 fail
7876 16:35:58.578074 alsa_mixer-test_write_default_0_44 pass
7877 16:35:58.581724 alsa_mixer-test_write_valid_0_44 pass
7878 16:35:58.584721 alsa_mixer-test_write_invalid_0_44 pass
7879 16:35:58.588515 alsa_mixer-test_event_missing_0_44 pass
7880 16:35:58.594736 alsa_mixer-test_event_spurious_0_44 pass
7881 16:35:58.597976 alsa_mixer-test_get_value_0_43 pass
7882 16:35:58.598085 alsa_mixer-test_name_0_43 fail
7883 16:35:58.605007 alsa_mixer-test_write_default_0_43 pass
7884 16:35:58.608173 alsa_mixer-test_write_valid_0_43 pass
7885 16:35:58.611365 alsa_mixer-test_write_invalid_0_43 pass
7886 16:35:58.614494 alsa_mixer-test_event_missing_0_43 pass
7887 16:35:58.618261 alsa_mixer-test_event_spurious_0_43 pass
7888 16:35:58.620930 alsa_mixer-test_get_value_0_42 pass
7889 16:35:58.624282 alsa_mixer-test_name_0_42 fail
7890 16:35:58.628081 alsa_mixer-test_write_default_0_42 pass
7891 16:35:58.631174 alsa_mixer-test_write_valid_0_42 pass
7892 16:35:58.634716 alsa_mixer-test_write_invalid_0_42 pass
7893 16:35:58.637719 alsa_mixer-test_event_missing_0_42 pass
7894 16:35:58.641002 alsa_mixer-test_event_spurious_0_42 pass
7895 16:35:58.644142 alsa_mixer-test_get_value_0_41 pass
7896 16:35:58.648030 alsa_mixer-test_name_0_41 fail
7897 16:35:58.651197 alsa_mixer-test_write_default_0_41 pass
7898 16:35:58.657695 alsa_mixer-test_write_valid_0_41 pass
7899 16:35:58.660719 alsa_mixer-test_write_invalid_0_41 pass
7900 16:35:58.664106 alsa_mixer-test_event_missing_0_41 pass
7901 16:35:58.667181 alsa_mixer-test_event_spurious_0_41 pass
7902 16:35:58.670881 alsa_mixer-test_get_value_0_40 pass
7903 16:35:58.674140 alsa_mixer-test_name_0_40 fail
7904 16:35:58.677261 alsa_mixer-test_write_default_0_40 pass
7905 16:35:58.680454 alsa_mixer-test_write_valid_0_40 pass
7906 16:35:58.684189 alsa_mixer-test_write_invalid_0_40 pass
7907 16:35:58.687463 alsa_mixer-test_event_missing_0_40 pass
7908 16:35:58.690304 alsa_mixer-test_event_spurious_0_40 pass
7909 16:35:58.694081 alsa_mixer-test_get_value_0_39 pass
7910 16:35:58.697229 alsa_mixer-test_name_0_39 fail
7911 16:35:58.700389 alsa_mixer-test_write_default_0_39 pass
7912 16:35:58.703597 alsa_mixer-test_write_valid_0_39 pass
7913 16:35:58.707462 alsa_mixer-test_write_invalid_0_39 pass
7914 16:35:58.713947 alsa_mixer-test_event_missing_0_39 pass
7915 16:35:58.717137 alsa_mixer-test_event_spurious_0_39 pass
7916 16:35:58.720248 alsa_mixer-test_get_value_0_38 pass
7917 16:35:58.723937 alsa_mixer-test_name_0_38 fail
7918 16:35:58.727166 alsa_mixer-test_write_default_0_38 pass
7919 16:35:58.730461 alsa_mixer-test_write_valid_0_38 pass
7920 16:35:58.733568 alsa_mixer-test_write_invalid_0_38 pass
7921 16:35:58.736815 alsa_mixer-test_event_missing_0_38 pass
7922 16:35:58.740527 alsa_mixer-test_event_spurious_0_38 pass
7923 16:35:58.743472 alsa_mixer-test_get_value_0_37 pass
7924 16:35:58.747192 alsa_mixer-test_name_0_37 fail
7925 16:35:58.750292 alsa_mixer-test_write_default_0_37 pass
7926 16:35:58.753540 alsa_mixer-test_write_valid_0_37 pass
7927 16:35:58.756797 alsa_mixer-test_write_invalid_0_37 pass
7928 16:35:58.759821 alsa_mixer-test_event_missing_0_37 pass
7929 16:35:58.767013 alsa_mixer-test_event_spurious_0_37 pass
7930 16:35:58.770051 alsa_mixer-test_get_value_0_36 pass
7931 16:35:58.770162 alsa_mixer-test_name_0_36 fail
7932 16:35:58.776506 alsa_mixer-test_write_default_0_36 pass
7933 16:35:58.780052 alsa_mixer-test_write_valid_0_36 pass
7934 16:35:58.783148 alsa_mixer-test_write_invalid_0_36 pass
7935 16:35:58.786865 alsa_mixer-test_event_missing_0_36 pass
7936 16:35:58.790111 alsa_mixer-test_event_spurious_0_36 pass
7937 16:35:58.793112 alsa_mixer-test_get_value_0_35 pass
7938 16:35:58.796723 alsa_mixer-test_name_0_35 fail
7939 16:35:58.799855 alsa_mixer-test_write_default_0_35 pass
7940 16:35:58.802854 alsa_mixer-test_write_valid_0_35 pass
7941 16:35:58.806609 alsa_mixer-test_write_invalid_0_35 pass
7942 16:35:58.809806 alsa_mixer-test_event_missing_0_35 pass
7943 16:35:58.813015 alsa_mixer-test_event_spurious_0_35 pass
7944 16:35:58.816260 alsa_mixer-test_get_value_0_34 pass
7945 16:35:58.819956 alsa_mixer-test_name_0_34 fail
7946 16:35:58.823220 alsa_mixer-test_write_default_0_34 pass
7947 16:35:58.826422 alsa_mixer-test_write_valid_0_34 pass
7948 16:35:58.833336 alsa_mixer-test_write_invalid_0_34 pass
7949 16:35:58.836503 alsa_mixer-test_event_missing_0_34 pass
7950 16:35:58.839659 alsa_mixer-test_event_spurious_0_34 pass
7951 16:35:58.842891 alsa_mixer-test_get_value_0_33 pass
7952 16:35:58.846027 alsa_mixer-test_name_0_33 fail
7953 16:35:58.849806 alsa_mixer-test_write_default_0_33 pass
7954 16:35:58.852681 alsa_mixer-test_write_valid_0_33 pass
7955 16:35:58.856339 alsa_mixer-test_write_invalid_0_33 pass
7956 16:35:58.859460 alsa_mixer-test_event_missing_0_33 pass
7957 16:35:58.862669 alsa_mixer-test_event_spurious_0_33 pass
7958 16:35:58.865833 alsa_mixer-test_get_value_0_32 pass
7959 16:35:58.869857 alsa_mixer-test_name_0_32 fail
7960 16:35:58.873088 alsa_mixer-test_write_default_0_32 pass
7961 16:35:58.876269 alsa_mixer-test_write_valid_0_32 pass
7962 16:35:58.879484 alsa_mixer-test_write_invalid_0_32 pass
7963 16:35:58.882659 alsa_mixer-test_event_missing_0_32 pass
7964 16:35:58.889105 alsa_mixer-test_event_spurious_0_32 pass
7965 16:35:58.892522 alsa_mixer-test_get_value_0_31 pass
7966 16:35:58.892623 alsa_mixer-test_name_0_31 fail
7967 16:35:58.899143 alsa_mixer-test_write_default_0_31 pass
7968 16:35:58.902150 alsa_mixer-test_write_valid_0_31 pass
7969 16:35:58.905903 alsa_mixer-test_write_invalid_0_31 pass
7970 16:35:58.909021 alsa_mixer-test_event_missing_0_31 pass
7971 16:35:58.912167 alsa_mixer-test_event_spurious_0_31 pass
7972 16:35:58.915420 alsa_mixer-test_get_value_0_30 pass
7973 16:35:58.918745 alsa_mixer-test_name_0_30 fail
7974 16:35:58.922576 alsa_mixer-test_write_default_0_30 pass
7975 16:35:58.925911 alsa_mixer-test_write_valid_0_30 pass
7976 16:35:58.929163 alsa_mixer-test_write_invalid_0_30 pass
7977 16:35:58.932238 alsa_mixer-test_event_missing_0_30 pass
7978 16:35:58.935912 alsa_mixer-test_event_spurious_0_30 pass
7979 16:35:58.939048 alsa_mixer-test_get_value_0_29 pass
7980 16:35:58.942263 alsa_mixer-test_name_0_29 pass
7981 16:35:58.945420 alsa_mixer-test_write_default_0_29 pass
7982 16:35:58.948632 alsa_mixer-test_write_valid_0_29 pass
7983 16:35:58.955783 alsa_mixer-test_write_invalid_0_29 pass
7984 16:35:58.958897 alsa_mixer-test_event_missing_0_29 pass
7985 16:35:58.961963 alsa_mixer-test_event_spurious_0_29 pass
7986 16:35:58.965551 alsa_mixer-test_get_value_0_28 pass
7987 16:35:58.968944 alsa_mixer-test_name_0_28 pass
7988 16:35:58.971951 alsa_mixer-test_write_default_0_28 pass
7989 16:35:58.975133 alsa_mixer-test_write_valid_0_28 pass
7990 16:35:58.978366 alsa_mixer-test_write_invalid_0_28 pass
7991 16:35:58.981917 alsa_mixer-test_event_missing_0_28 pass
7992 16:35:58.985257 alsa_mixer-test_event_spurious_0_28 pass
7993 16:35:58.988531 alsa_mixer-test_get_value_0_27 pass
7994 16:35:58.991662 alsa_mixer-test_name_0_27 pass
7995 16:35:58.994965 alsa_mixer-test_write_default_0_27 pass
7996 16:35:58.998663 alsa_mixer-test_write_valid_0_27 pass
7997 16:35:59.001634 alsa_mixer-test_write_invalid_0_27 pass
7998 16:35:59.005231 alsa_mixer-test_event_missing_0_27 pass
7999 16:35:59.011565 alsa_mixer-test_event_spurious_0_27 pass
8000 16:35:59.015059 alsa_mixer-test_get_value_0_26 pass
8001 16:35:59.018344 alsa_mixer-test_name_0_26 pass
8002 16:35:59.021518 alsa_mixer-test_write_default_0_26 pass
8003 16:35:59.025010 alsa_mixer-test_write_valid_0_26 pass
8004 16:35:59.028264 alsa_mixer-test_write_invalid_0_26 pass
8005 16:35:59.031349 alsa_mixer-test_event_missing_0_26 pass
8006 16:35:59.034646 alsa_mixer-test_event_spurious_0_26 pass
8007 16:35:59.038410 alsa_mixer-test_get_value_0_25 pass
8008 16:35:59.041491 alsa_mixer-test_name_0_25 pass
8009 16:35:59.045205 alsa_mixer-test_write_default_0_25 pass
8010 16:35:59.048405 alsa_mixer-test_write_valid_0_25 pass
8011 16:35:59.051624 alsa_mixer-test_write_invalid_0_25 pass
8012 16:35:59.054788 alsa_mixer-test_event_missing_0_25 pass
8013 16:35:59.057970 alsa_mixer-test_event_spurious_0_25 pass
8014 16:35:59.061194 alsa_mixer-test_get_value_0_24 pass
8015 16:35:59.064409 alsa_mixer-test_name_0_24 pass
8016 16:35:59.068301 alsa_mixer-test_write_default_0_24 pass
8017 16:35:59.074562 alsa_mixer-test_write_valid_0_24 pass
8018 16:35:59.078273 alsa_mixer-test_write_invalid_0_24 pass
8019 16:35:59.081206 alsa_mixer-test_event_missing_0_24 pass
8020 16:35:59.084356 alsa_mixer-test_event_spurious_0_24 pass
8021 16:35:59.087948 alsa_mixer-test_get_value_0_23 pass
8022 16:35:59.091205 alsa_mixer-test_name_0_23 pass
8023 16:35:59.094316 alsa_mixer-test_write_default_0_23 pass
8024 16:35:59.097500 alsa_mixer-test_write_valid_0_23 pass
8025 16:35:59.101298 alsa_mixer-test_write_invalid_0_23 pass
8026 16:35:59.104441 alsa_mixer-test_event_missing_0_23 pass
8027 16:35:59.107667 alsa_mixer-test_event_spurious_0_23 pass
8028 16:35:59.110748 alsa_mixer-test_get_value_0_22 pass
8029 16:35:59.114405 alsa_mixer-test_name_0_22 pass
8030 16:35:59.117713 alsa_mixer-test_write_default_0_22 pass
8031 16:35:59.120922 alsa_mixer-test_write_valid_0_22 pass
8032 16:35:59.124048 alsa_mixer-test_write_invalid_0_22 pass
8033 16:35:59.130683 alsa_mixer-test_event_missing_0_22 pass
8034 16:35:59.134142 alsa_mixer-test_event_spurious_0_22 pass
8035 16:35:59.137514 alsa_mixer-test_get_value_0_21 pass
8036 16:35:59.140932 alsa_mixer-test_name_0_21 fail
8037 16:35:59.143909 alsa_mixer-test_write_default_0_21 pass
8038 16:35:59.147675 alsa_mixer-test_write_valid_0_21 pass
8039 16:35:59.150702 alsa_mixer-test_write_invalid_0_21 pass
8040 16:35:59.153834 alsa_mixer-test_event_missing_0_21 pass
8041 16:35:59.157039 alsa_mixer-test_event_spurious_0_21 pass
8042 16:35:59.160847 alsa_mixer-test_get_value_0_20 pass
8043 16:35:59.164231 alsa_mixer-test_name_0_20 fail
8044 16:35:59.167346 alsa_mixer-test_write_default_0_20 pass
8045 16:35:59.170612 alsa_mixer-test_write_valid_0_20 pass
8046 16:35:59.173829 alsa_mixer-test_write_invalid_0_20 pass
8047 16:35:59.176971 alsa_mixer-test_event_missing_0_20 pass
8048 16:35:59.184065 alsa_mixer-test_event_spurious_0_20 pass
8049 16:35:59.187106 alsa_mixer-test_get_value_0_19 pass
8050 16:35:59.187215 alsa_mixer-test_name_0_19 fail
8051 16:35:59.193749 alsa_mixer-test_write_default_0_19 pass
8052 16:35:59.197325 alsa_mixer-test_write_valid_0_19 pass
8053 16:35:59.200332 alsa_mixer-test_write_invalid_0_19 pass
8054 16:35:59.204024 alsa_mixer-test_event_missing_0_19 pass
8055 16:35:59.207174 alsa_mixer-test_event_spurious_0_19 pass
8056 16:35:59.210429 alsa_mixer-test_get_value_0_18 pass
8057 16:35:59.213531 alsa_mixer-test_name_0_18 fail
8058 16:35:59.217238 alsa_mixer-test_write_default_0_18 pass
8059 16:35:59.220198 alsa_mixer-test_write_valid_0_18 pass
8060 16:35:59.223846 alsa_mixer-test_write_invalid_0_18 pass
8061 16:35:59.227102 alsa_mixer-test_event_missing_0_18 pass
8062 16:35:59.230221 alsa_mixer-test_event_spurious_0_18 pass
8063 16:35:59.233466 alsa_mixer-test_get_value_0_17 pass
8064 16:35:59.236594 alsa_mixer-test_name_0_17 fail
8065 16:35:59.240357 alsa_mixer-test_write_default_0_17 pass
8066 16:35:59.243431 alsa_mixer-test_write_valid_0_17 pass
8067 16:35:59.246982 alsa_mixer-test_write_invalid_0_17 pass
8068 16:35:59.253331 alsa_mixer-test_event_missing_0_17 pass
8069 16:35:59.256772 alsa_mixer-test_event_spurious_0_17 pass
8070 16:35:59.260154 alsa_mixer-test_get_value_0_16 pass
8071 16:35:59.263569 alsa_mixer-test_name_0_16 fail
8072 16:35:59.266508 alsa_mixer-test_write_default_0_16 pass
8073 16:35:59.270355 alsa_mixer-test_write_valid_0_16 pass
8074 16:35:59.273560 alsa_mixer-test_write_invalid_0_16 pass
8075 16:35:59.276593 alsa_mixer-test_event_missing_0_16 pass
8076 16:35:59.279777 alsa_mixer-test_event_spurious_0_16 pass
8077 16:35:59.283530 alsa_mixer-test_get_value_0_15 pass
8078 16:35:59.286704 alsa_mixer-test_name_0_15 fail
8079 16:35:59.289872 alsa_mixer-test_write_default_0_15 pass
8080 16:35:59.293124 alsa_mixer-test_write_valid_0_15 pass
8081 16:35:59.296956 alsa_mixer-test_write_invalid_0_15 pass
8082 16:35:59.300157 alsa_mixer-test_event_missing_0_15 pass
8083 16:35:59.306816 alsa_mixer-test_event_spurious_0_15 pass
8084 16:35:59.309805 alsa_mixer-test_get_value_0_14 pass
8085 16:35:59.309903 alsa_mixer-test_name_0_14 fail
8086 16:35:59.316432 alsa_mixer-test_write_default_0_14 pass
8087 16:35:59.319663 alsa_mixer-test_write_valid_0_14 pass
8088 16:35:59.323400 alsa_mixer-test_write_invalid_0_14 pass
8089 16:35:59.326432 alsa_mixer-test_event_missing_0_14 pass
8090 16:35:59.329991 alsa_mixer-test_event_spurious_0_14 pass
8091 16:35:59.333262 alsa_mixer-test_get_value_0_13 pass
8092 16:35:59.336465 alsa_mixer-test_name_0_13 fail
8093 16:35:59.339608 alsa_mixer-test_write_default_0_13 pass
8094 16:35:59.343538 alsa_mixer-test_write_valid_0_13 pass
8095 16:35:59.346808 alsa_mixer-test_write_invalid_0_13 pass
8096 16:35:59.350010 alsa_mixer-test_event_missing_0_13 pass
8097 16:35:59.353176 alsa_mixer-test_event_spurious_0_13 pass
8098 16:35:59.356282 alsa_mixer-test_get_value_0_12 pass
8099 16:35:59.360089 alsa_mixer-test_name_0_12 fail
8100 16:35:59.363104 alsa_mixer-test_write_default_0_12 pass
8101 16:35:59.366822 alsa_mixer-test_write_valid_0_12 pass
8102 16:35:59.370030 alsa_mixer-test_write_invalid_0_12 pass
8103 16:35:59.376391 alsa_mixer-test_event_missing_0_12 pass
8104 16:35:59.379934 alsa_mixer-test_event_spurious_0_12 pass
8105 16:35:59.383111 alsa_mixer-test_get_value_0_11 pass
8106 16:35:59.386297 alsa_mixer-test_name_0_11 fail
8107 16:35:59.389442 alsa_mixer-test_write_default_0_11 pass
8108 16:35:59.393280 alsa_mixer-test_write_valid_0_11 pass
8109 16:35:59.396530 alsa_mixer-test_write_invalid_0_11 pass
8110 16:35:59.399648 alsa_mixer-test_event_missing_0_11 pass
8111 16:35:59.402988 alsa_mixer-test_event_spurious_0_11 pass
8112 16:35:59.406094 alsa_mixer-test_get_value_0_10 pass
8113 16:35:59.409883 alsa_mixer-test_name_0_10 fail
8114 16:35:59.413123 alsa_mixer-test_write_default_0_10 pass
8115 16:35:59.416140 alsa_mixer-test_write_valid_0_10 pass
8116 16:35:59.419786 alsa_mixer-test_write_invalid_0_10 pass
8117 16:35:59.422746 alsa_mixer-test_event_missing_0_10 pass
8118 16:35:59.429743 alsa_mixer-test_event_spurious_0_10 pass
8119 16:35:59.429827 alsa_mixer-test_get_value_0_9 pass
8120 16:35:59.432752 alsa_mixer-test_name_0_9 fail
8121 16:35:59.435695 alsa_mixer-test_write_default_0_9 pass
8122 16:35:59.439405 alsa_mixer-test_write_valid_0_9 pass
8123 16:35:59.446454 alsa_mixer-test_write_invalid_0_9 pass
8124 16:35:59.449628 alsa_mixer-test_event_missing_0_9 pass
8125 16:35:59.452784 alsa_mixer-test_event_spurious_0_9 pass
8126 16:35:59.456005 alsa_mixer-test_get_value_0_8 pass
8127 16:35:59.456083 alsa_mixer-test_name_0_8 fail
8128 16:35:59.459104 alsa_mixer-test_write_default_0_8 pass
8129 16:35:59.462348 alsa_mixer-test_write_valid_0_8 pass
8130 16:35:59.469264 alsa_mixer-test_write_invalid_0_8 pass
8131 16:35:59.472416 alsa_mixer-test_event_missing_0_8 pass
8132 16:35:59.475629 alsa_mixer-test_event_spurious_0_8 pass
8133 16:35:59.479331 alsa_mixer-test_get_value_0_7 pass
8134 16:35:59.479403 alsa_mixer-test_name_0_7 fail
8135 16:35:59.486071 alsa_mixer-test_write_default_0_7 pass
8136 16:35:59.489027 alsa_mixer-test_write_valid_0_7 pass
8137 16:35:59.492624 alsa_mixer-test_write_invalid_0_7 pass
8138 16:35:59.495668 alsa_mixer-test_event_missing_0_7 pass
8139 16:35:59.498957 alsa_mixer-test_event_spurious_0_7 pass
8140 16:35:59.502046 alsa_mixer-test_get_value_0_6 pass
8141 16:35:59.505903 alsa_mixer-test_name_0_6 fail
8142 16:35:59.509049 alsa_mixer-test_write_default_0_6 pass
8143 16:35:59.512168 alsa_mixer-test_write_valid_0_6 pass
8144 16:35:59.515327 alsa_mixer-test_write_invalid_0_6 pass
8145 16:35:59.519172 alsa_mixer-test_event_missing_0_6 pass
8146 16:35:59.522325 alsa_mixer-test_event_spurious_0_6 pass
8147 16:35:59.525525 alsa_mixer-test_get_value_0_5 pass
8148 16:35:59.528612 alsa_mixer-test_name_0_5 pass
8149 16:35:59.532346 alsa_mixer-test_write_default_0_5 pass
8150 16:35:59.535362 alsa_mixer-test_write_valid_0_5 pass
8151 16:35:59.538712 alsa_mixer-test_write_invalid_0_5 pass
8152 16:35:59.542140 alsa_mixer-test_event_missing_0_5 fail
8153 16:35:59.545375 alsa_mixer-test_event_spurious_0_5 pass
8154 16:35:59.548340 alsa_mixer-test_get_value_0_4 pass
8155 16:35:59.552166 alsa_mixer-test_name_0_4 pass
8156 16:35:59.555298 alsa_mixer-test_write_default_0_4 pass
8157 16:35:59.558443 alsa_mixer-test_write_valid_0_4 pass
8158 16:35:59.561657 alsa_mixer-test_write_invalid_0_4 pass
8159 16:35:59.565207 alsa_mixer-test_event_missing_0_4 fail
8160 16:35:59.568435 alsa_mixer-test_event_spurious_0_4 pass
8161 16:35:59.571574 alsa_mixer-test_get_value_0_3 pass
8162 16:35:59.575157 alsa_mixer-test_name_0_3 pass
8163 16:35:59.578368 alsa_mixer-test_write_default_0_3 pass
8164 16:35:59.581584 alsa_mixer-test_write_valid_0_3 pass
8165 16:35:59.584825 alsa_mixer-test_write_invalid_0_3 pass
8166 16:35:59.587939 alsa_mixer-test_event_missing_0_3 fail
8167 16:35:59.591678 alsa_mixer-test_event_spurious_0_3 pass
8168 16:35:59.594761 alsa_mixer-test_get_value_0_2 pass
8169 16:35:59.597814 alsa_mixer-test_name_0_2 pass
8170 16:35:59.601272 alsa_mixer-test_write_default_0_2 pass
8171 16:35:59.604772 alsa_mixer-test_write_valid_0_2 pass
8172 16:35:59.608006 alsa_mixer-test_write_invalid_0_2 pass
8173 16:35:59.611169 alsa_mixer-test_event_missing_0_2 fail
8174 16:35:59.614882 alsa_mixer-test_event_spurious_0_2 pass
8175 16:35:59.618090 alsa_mixer-test_get_value_0_1 pass
8176 16:35:59.621267 alsa_mixer-test_name_0_1 pass
8177 16:35:59.624522 alsa_mixer-test_write_default_0_1 pass
8178 16:35:59.627639 alsa_mixer-test_write_valid_0_1 pass
8179 16:35:59.630810 alsa_mixer-test_write_invalid_0_1 pass
8180 16:35:59.634731 alsa_mixer-test_event_missing_0_1 fail
8181 16:35:59.637944 alsa_mixer-test_event_spurious_0_1 pass
8182 16:35:59.641160 alsa_mixer-test_get_value_0_0 pass
8183 16:35:59.644299 alsa_mixer-test_name_0_0 pass
8184 16:35:59.647489 alsa_mixer-test_write_default_0_0 pass
8185 16:35:59.651128 alsa_mixer-test_write_valid_0_0 pass
8186 16:35:59.654484 alsa_mixer-test_write_invalid_0_0 pass
8187 16:35:59.657895 alsa_mixer-test_event_missing_0_0 fail
8188 16:35:59.661195 alsa_mixer-test_event_spurious_0_0 pass
8189 16:35:59.664443 alsa_mixer-test pass
8190 16:35:59.667950 + ../../utils/send-to-lava.sh ./output/result.txt
8191 16:35:59.673974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
8192 16:35:59.674305 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
8194 16:35:59.680798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
8195 16:35:59.681085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
8197 16:35:59.687248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
8198 16:35:59.687518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
8200 16:35:59.694155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
8201 16:35:59.694432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8203 16:35:59.700661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8204 16:35:59.700942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8206 16:35:59.707631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8208 16:35:59.710404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8209 16:35:59.753625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8210 16:35:59.753943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8212 16:35:59.799810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8213 16:35:59.800109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8215 16:35:59.841898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8216 16:35:59.842236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8218 16:35:59.883532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8219 16:35:59.883865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8221 16:35:59.927002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8222 16:35:59.927315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8224 16:35:59.967995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8225 16:35:59.968277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8227 16:36:00.007149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8228 16:36:00.007458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8230 16:36:00.046051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8231 16:36:00.046363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8233 16:36:00.084834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8234 16:36:00.085140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8236 16:36:00.121115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8237 16:36:00.121415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8239 16:36:00.156636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8240 16:36:00.156928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8242 16:36:00.201946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8243 16:36:00.202252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8245 16:36:00.245786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8246 16:36:00.246082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8248 16:36:00.283426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8249 16:36:00.283755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8251 16:36:00.321134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8252 16:36:00.321412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8254 16:36:00.358528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8255 16:36:00.358834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8257 16:36:00.399119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8258 16:36:00.399420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8260 16:36:00.429350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8261 16:36:00.429634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8263 16:36:00.475109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8264 16:36:00.475369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8266 16:36:00.516334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8267 16:36:00.516618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8269 16:36:00.556352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8270 16:36:00.556661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8272 16:36:00.594281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8273 16:36:00.594586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8275 16:36:00.631665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8276 16:36:00.631950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8278 16:36:00.669578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8279 16:36:00.669880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8281 16:36:00.703464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8282 16:36:00.703752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8284 16:36:00.743204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8285 16:36:00.743487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8287 16:36:00.780314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8288 16:36:00.780619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8290 16:36:00.820717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8291 16:36:00.821021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8293 16:36:00.859209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8294 16:36:00.859531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8296 16:36:00.899275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8297 16:36:00.899570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8299 16:36:00.940172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8300 16:36:00.940460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8302 16:36:00.978165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8303 16:36:00.978473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8305 16:36:01.020800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8306 16:36:01.021112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8308 16:36:01.061372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8309 16:36:01.061685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8311 16:36:01.105556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8312 16:36:01.105869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8314 16:36:01.144430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8315 16:36:01.144741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8317 16:36:01.184094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8318 16:36:01.184369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8320 16:36:01.224984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8321 16:36:01.225257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8323 16:36:01.264179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8324 16:36:01.264460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8326 16:36:01.314018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8327 16:36:01.314310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8329 16:36:01.350054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8330 16:36:01.350348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8332 16:36:01.388200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8333 16:36:01.388490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8335 16:36:01.430529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8336 16:36:01.430846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8338 16:36:01.467333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8339 16:36:01.467663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8341 16:36:01.504351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8342 16:36:01.504660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8344 16:36:01.537153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8345 16:36:01.537465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8347 16:36:01.576407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8348 16:36:01.576719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8350 16:36:01.614405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8351 16:36:01.614717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8353 16:36:01.653996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8354 16:36:01.654308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8356 16:36:01.695462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8357 16:36:01.695754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8359 16:36:01.733547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8360 16:36:01.733836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8362 16:36:01.769221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8363 16:36:01.769508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8365 16:36:01.802445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8366 16:36:01.802821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8368 16:36:01.842532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8369 16:36:01.842839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8371 16:36:01.882109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8372 16:36:01.882449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8374 16:36:01.917741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8375 16:36:01.918002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8377 16:36:01.949760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8378 16:36:01.950050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8380 16:36:01.983651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8381 16:36:01.983962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8383 16:36:02.018392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8384 16:36:02.018683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8386 16:36:02.050354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8387 16:36:02.050642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8389 16:36:02.091232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8390 16:36:02.091541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8392 16:36:02.126715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8393 16:36:02.127038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8395 16:36:02.162477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8396 16:36:02.162770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8398 16:36:02.197098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8399 16:36:02.197967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8401 16:36:02.235313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8402 16:36:02.235623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8404 16:36:02.271336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8405 16:36:02.271617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8407 16:36:02.308420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8408 16:36:02.308731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8410 16:36:02.347534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8411 16:36:02.347840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8413 16:36:02.385175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8414 16:36:02.385484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8416 16:36:02.421651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8417 16:36:02.421948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8419 16:36:02.460457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8420 16:36:02.460758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8422 16:36:02.500114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8423 16:36:02.500424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8425 16:36:02.549145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8426 16:36:02.549477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8428 16:36:02.595892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8429 16:36:02.596194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8431 16:36:02.644721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8432 16:36:02.645057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8434 16:36:02.690397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8435 16:36:02.690683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8437 16:36:02.744090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8438 16:36:02.744377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8440 16:36:02.790336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8441 16:36:02.790618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8443 16:36:02.836779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8444 16:36:02.837100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8446 16:36:02.882979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8447 16:36:02.883262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8449 16:36:02.928243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8450 16:36:02.928567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8452 16:36:02.978909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8453 16:36:02.979194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8455 16:36:03.026432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8456 16:36:03.026717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8458 16:36:03.069646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8459 16:36:03.069954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8461 16:36:03.115988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8462 16:36:03.116304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8464 16:36:03.164023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8465 16:36:03.164361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8467 16:36:03.214060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8468 16:36:03.214344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8470 16:36:03.258905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8471 16:36:03.259228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8473 16:36:03.308278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8474 16:36:03.308564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8476 16:36:03.353869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8477 16:36:03.354198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8479 16:36:03.400506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8480 16:36:03.400788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8482 16:36:03.444477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8483 16:36:03.444777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8485 16:36:03.489477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8486 16:36:03.489770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8488 16:36:03.533536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8489 16:36:03.533858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8491 16:36:03.577550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8492 16:36:03.577845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8494 16:36:03.630370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8495 16:36:03.630653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8497 16:36:03.678668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8498 16:36:03.678954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8500 16:36:03.727107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8501 16:36:03.727392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8503 16:36:03.771745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8504 16:36:03.772047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8506 16:36:03.820727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8507 16:36:03.821035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8509 16:36:03.869094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8510 16:36:03.869381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8512 16:36:03.906580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8513 16:36:03.906865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8515 16:36:03.947044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8516 16:36:03.947325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8518 16:36:03.987849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8519 16:36:03.988134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8521 16:36:04.023008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8522 16:36:04.023308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8524 16:36:04.059914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8525 16:36:04.060213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8527 16:36:04.103169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8528 16:36:04.103480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8530 16:36:04.140849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8531 16:36:04.141155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8533 16:36:04.179710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8534 16:36:04.179988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8536 16:36:04.220808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8537 16:36:04.221114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8539 16:36:04.258370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8540 16:36:04.258682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8542 16:36:04.296640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8543 16:36:04.296953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8545 16:36:04.338882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8546 16:36:04.339165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8548 16:36:04.377116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8549 16:36:04.377399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8551 16:36:04.417784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8552 16:36:04.418074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8554 16:36:04.461047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8555 16:36:04.461331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8557 16:36:04.510850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8558 16:36:04.511127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8560 16:36:04.554760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8561 16:36:04.555039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8563 16:36:04.596171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8564 16:36:04.596455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8566 16:36:04.633888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8567 16:36:04.634210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8569 16:36:04.673928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8570 16:36:04.674238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8572 16:36:04.713762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8573 16:36:04.714003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8575 16:36:04.758351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8576 16:36:04.758716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8578 16:36:04.803537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8579 16:36:04.803824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8581 16:36:04.840376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8582 16:36:04.840655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8584 16:36:04.877044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8585 16:36:04.877323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8587 16:36:04.915095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8588 16:36:04.915402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8590 16:36:04.952585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8591 16:36:04.952895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8593 16:36:04.986931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8594 16:36:04.987224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8596 16:36:05.016338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8597 16:36:05.016653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8599 16:36:05.058599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8600 16:36:05.058886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8602 16:36:05.101224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8603 16:36:05.101538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8605 16:36:05.147459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8606 16:36:05.147783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8608 16:36:05.193290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8609 16:36:05.193605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8611 16:36:05.240771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8612 16:36:05.241083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8614 16:36:05.284942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8615 16:36:05.285250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8617 16:36:05.330097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8618 16:36:05.330411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8620 16:36:05.380201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8621 16:36:05.380540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8623 16:36:05.432911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8624 16:36:05.433225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8626 16:36:05.477011 <LAVA_SIGNAL_TES<6>[ 35.589843] vaux18: disabling
8627 16:36:05.477319 Received signal: <TES<6>[> 35.589843] vaux18: disabling
TCASE TEST_CASE_<6
8628 16:36:05.480064 TCASE TEST_CASE_<6>[ 35.593637] vio28: disabling
8629 16:36:05.487188 ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8630 16:36:05.530083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8631 16:36:05.530381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8633 16:36:05.575258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8634 16:36:05.575567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8636 16:36:05.620782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8637 16:36:05.621111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8639 16:36:05.660955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8640 16:36:05.661276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8642 16:36:05.712158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8643 16:36:05.712481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8645 16:36:05.761589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8646 16:36:05.761912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8648 16:36:05.809309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8649 16:36:05.809641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8651 16:36:05.855390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8652 16:36:05.855696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8654 16:36:05.901764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8655 16:36:05.902085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8657 16:36:05.948243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8658 16:36:05.948524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8660 16:36:05.990123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8661 16:36:05.990456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8663 16:36:06.040364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8664 16:36:06.040687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8666 16:36:06.084450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8667 16:36:06.084735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8669 16:36:06.132558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8670 16:36:06.132848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8672 16:36:06.180166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8673 16:36:06.180449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8675 16:36:06.226008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8676 16:36:06.226297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8678 16:36:06.272081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8679 16:36:06.272372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8681 16:36:06.314999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8682 16:36:06.315290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8684 16:36:06.361749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8685 16:36:06.362054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8687 16:36:06.410510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8688 16:36:06.410812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8690 16:36:06.456978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8691 16:36:06.457305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8693 16:36:06.503737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8694 16:36:06.504070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8696 16:36:06.541744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8697 16:36:06.542067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8699 16:36:06.581923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8700 16:36:06.582231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8702 16:36:06.617793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8703 16:36:06.618107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8705 16:36:06.661667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8706 16:36:06.661987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8708 16:36:06.701414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8709 16:36:06.701702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8711 16:36:06.743848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8712 16:36:06.744180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8714 16:36:06.779732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8715 16:36:06.780019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8717 16:36:06.818459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8718 16:36:06.818803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8720 16:36:06.857099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8721 16:36:06.857425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8723 16:36:06.900661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8724 16:36:06.900946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8726 16:36:06.944334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8727 16:36:06.944631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8729 16:36:06.983851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8730 16:36:06.984139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8732 16:36:07.022762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8733 16:36:07.023050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8735 16:36:07.062749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8736 16:36:07.063032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8738 16:36:07.098958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8739 16:36:07.099279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8741 16:36:07.138952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8742 16:36:07.139274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8744 16:36:07.175008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8745 16:36:07.175330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8747 16:36:07.220588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8748 16:36:07.220898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8750 16:36:07.259176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8751 16:36:07.259474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8753 16:36:07.298227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8754 16:36:07.298530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8756 16:36:07.337591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8757 16:36:07.337905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8759 16:36:07.376807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8760 16:36:07.377134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8762 16:36:07.415853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8763 16:36:07.416182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8765 16:36:07.452726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8766 16:36:07.453068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8768 16:36:07.492116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8769 16:36:07.492427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8771 16:36:07.530955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8772 16:36:07.531248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8774 16:36:07.570230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8775 16:36:07.570513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8777 16:36:07.609740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8778 16:36:07.610055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8780 16:36:07.646573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8781 16:36:07.646876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8783 16:36:07.688755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8784 16:36:07.689068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8786 16:36:07.727027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8787 16:36:07.727334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8789 16:36:07.766877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8790 16:36:07.767183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8792 16:36:07.806961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8793 16:36:07.807292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8795 16:36:07.846506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8796 16:36:07.846824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8798 16:36:07.883217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8799 16:36:07.883528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8801 16:36:07.919935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8802 16:36:07.920239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8804 16:36:07.955015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8805 16:36:07.955291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8807 16:36:07.992670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8808 16:36:07.992981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8810 16:36:08.036418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8811 16:36:08.036726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8813 16:36:08.073086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8814 16:36:08.073395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8816 16:36:08.113045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8817 16:36:08.113319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8819 16:36:08.150695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8820 16:36:08.150992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8822 16:36:08.191233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8823 16:36:08.191545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8825 16:36:08.231158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8826 16:36:08.231473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8828 16:36:08.266790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8829 16:36:08.267079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8831 16:36:08.309424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8832 16:36:08.309710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8834 16:36:08.343206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8835 16:36:08.343508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8837 16:36:08.380143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8838 16:36:08.380437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8840 16:36:08.415268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8841 16:36:08.415601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8843 16:36:08.453143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8844 16:36:08.453448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8846 16:36:08.492884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8847 16:36:08.493205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8849 16:36:08.527138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8850 16:36:08.527453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8852 16:36:08.566455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8853 16:36:08.566729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8855 16:36:08.603155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8856 16:36:08.603431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8858 16:36:08.642213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8859 16:36:08.642498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8861 16:36:08.679572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8862 16:36:08.679845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8864 16:36:08.715290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8865 16:36:08.715552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8867 16:36:08.751586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8868 16:36:08.751880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8870 16:36:08.785028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8871 16:36:08.785323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8873 16:36:08.826557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8874 16:36:08.826839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8876 16:36:08.867635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8877 16:36:08.867940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8879 16:36:08.908116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8880 16:36:08.908416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8882 16:36:08.943673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8883 16:36:08.943975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8885 16:36:08.982040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8886 16:36:08.982364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8888 16:36:09.024273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8889 16:36:09.024579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8891 16:36:09.056642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8892 16:36:09.056930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8894 16:36:09.096644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8895 16:36:09.096924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8897 16:36:09.134135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8898 16:36:09.134444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8900 16:36:09.172449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8901 16:36:09.172743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8903 16:36:09.208511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8904 16:36:09.208813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8906 16:36:09.247793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8907 16:36:09.248094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8909 16:36:09.290242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8910 16:36:09.290530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8912 16:36:09.326026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8913 16:36:09.326334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8915 16:36:09.370828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8916 16:36:09.371123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8918 16:36:09.410957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8919 16:36:09.411255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8921 16:36:09.452275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8922 16:36:09.452601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8924 16:36:09.491902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8925 16:36:09.492210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8927 16:36:09.532066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8928 16:36:09.532401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8930 16:36:09.572857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8931 16:36:09.573158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8933 16:36:09.609123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8934 16:36:09.609428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8936 16:36:09.653779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8937 16:36:09.654081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8939 16:36:09.692995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8940 16:36:09.693288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8942 16:36:09.727667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8943 16:36:09.727961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8945 16:36:09.765286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8946 16:36:09.765657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8948 16:36:09.802660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8949 16:36:09.802989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8951 16:36:09.836066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8952 16:36:09.836405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8954 16:36:09.871216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8955 16:36:09.871523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8957 16:36:09.911268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8958 16:36:09.911607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8960 16:36:09.949910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8961 16:36:09.950249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8963 16:36:09.990182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8964 16:36:09.990534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8966 16:36:10.026865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8967 16:36:10.027188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8969 16:36:10.064127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8970 16:36:10.064446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8972 16:36:10.100136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8973 16:36:10.100430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8975 16:36:10.133369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8976 16:36:10.133664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8978 16:36:10.172640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8979 16:36:10.172945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8981 16:36:10.211341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8982 16:36:10.211627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8984 16:36:10.248368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8985 16:36:10.248666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8987 16:36:10.288209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8988 16:36:10.288479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8990 16:36:10.326601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8991 16:36:10.326900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8993 16:36:10.364094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8994 16:36:10.364404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8996 16:36:10.397053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8997 16:36:10.397337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8999 16:36:10.438116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
9000 16:36:10.438431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
9002 16:36:10.478218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
9003 16:36:10.478539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
9005 16:36:10.513485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
9006 16:36:10.513806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
9008 16:36:10.554096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
9009 16:36:10.554379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
9011 16:36:10.592224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
9012 16:36:10.592537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
9014 16:36:10.627257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
9015 16:36:10.627555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
9017 16:36:10.658512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
9018 16:36:10.658800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
9020 16:36:10.699882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
9021 16:36:10.700179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
9023 16:36:10.733722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
9024 16:36:10.734014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
9026 16:36:10.769966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
9027 16:36:10.770253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
9029 16:36:10.811373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
9030 16:36:10.811678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
9032 16:36:10.852126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
9033 16:36:10.852422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
9035 16:36:10.891213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
9036 16:36:10.891501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
9038 16:36:10.922332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
9039 16:36:10.922598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
9041 16:36:10.964064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
9042 16:36:10.964337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
9044 16:36:11.005891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
9045 16:36:11.006188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
9047 16:36:11.044002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
9048 16:36:11.044261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
9050 16:36:11.084582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
9051 16:36:11.084885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
9053 16:36:11.122057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
9054 16:36:11.122322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
9056 16:36:11.160416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
9057 16:36:11.160681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
9059 16:36:11.192856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
9060 16:36:11.193111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
9062 16:36:11.234766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
9063 16:36:11.235038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
9065 16:36:11.274696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
9066 16:36:11.274967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
9068 16:36:11.311507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
9069 16:36:11.311770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
9071 16:36:11.354414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
9072 16:36:11.354695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
9074 16:36:11.393030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
9075 16:36:11.393326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
9077 16:36:11.430988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
9078 16:36:11.431246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
9080 16:36:11.463721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
9081 16:36:11.463992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
9083 16:36:11.502471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
9084 16:36:11.502731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
9086 16:36:11.539402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
9087 16:36:11.539698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
9089 16:36:11.579433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
9090 16:36:11.579717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
9092 16:36:11.616785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
9093 16:36:11.617066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
9095 16:36:11.653856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
9096 16:36:11.654157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
9098 16:36:11.692066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
9099 16:36:11.692343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
9101 16:36:11.727323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
9102 16:36:11.727592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
9104 16:36:11.766564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
9105 16:36:11.766837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
9107 16:36:11.801669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
9108 16:36:11.801971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
9110 16:36:11.840871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
9111 16:36:11.841161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
9113 16:36:11.882172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
9114 16:36:11.882458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
9116 16:36:11.927272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
9117 16:36:11.927550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
9119 16:36:11.968363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
9120 16:36:11.968668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
9122 16:36:12.003067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
9123 16:36:12.003347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
9125 16:36:12.051383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
9126 16:36:12.051649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
9128 16:36:12.092706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
9129 16:36:12.093000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
9131 16:36:12.132063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
9132 16:36:12.132337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
9134 16:36:12.172979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
9135 16:36:12.173252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
9137 16:36:12.211248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
9138 16:36:12.211517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
9140 16:36:12.250430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
9141 16:36:12.250701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
9143 16:36:12.283572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
9144 16:36:12.283844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
9146 16:36:12.323342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
9147 16:36:12.323645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
9149 16:36:12.361275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
9150 16:36:12.361553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
9152 16:36:12.400991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
9153 16:36:12.401264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
9155 16:36:12.436643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
9156 16:36:12.436932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
9158 16:36:12.479514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
9159 16:36:12.479794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
9161 16:36:12.519363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
9162 16:36:12.519635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
9164 16:36:12.557529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
9165 16:36:12.557800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
9167 16:36:12.599962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
9168 16:36:12.600217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
9170 16:36:12.641271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
9171 16:36:12.641560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
9173 16:36:12.683262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
9174 16:36:12.683543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
9176 16:36:12.719678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
9177 16:36:12.719958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
9179 16:36:12.763017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
9180 16:36:12.763307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
9182 16:36:12.803179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
9183 16:36:12.803474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
9185 16:36:12.839886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
9186 16:36:12.840162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
9188 16:36:12.879162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
9189 16:36:12.879432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
9191 16:36:12.914880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
9192 16:36:12.915137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
9194 16:36:12.955051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
9195 16:36:12.955325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
9197 16:36:12.992492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
9198 16:36:12.992758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
9200 16:36:13.030082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9201 16:36:13.030342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9203 16:36:13.072465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9204 16:36:13.072725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9206 16:36:13.104335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9207 16:36:13.104586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9209 16:36:13.149923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9210 16:36:13.150234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9212 16:36:13.187590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9213 16:36:13.187852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9215 16:36:13.226387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9216 16:36:13.226663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9218 16:36:13.267245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9219 16:36:13.267511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9221 16:36:13.306090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9222 16:36:13.306352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9224 16:36:13.345154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9225 16:36:13.345445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9227 16:36:13.383477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9228 16:36:13.383743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9230 16:36:13.422540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9231 16:36:13.422808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9233 16:36:13.460267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9234 16:36:13.460538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9236 16:36:13.499372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9237 16:36:13.499651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9239 16:36:13.539264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9240 16:36:13.539518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9242 16:36:13.579884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9243 16:36:13.580184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9245 16:36:13.621940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9246 16:36:13.622236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9248 16:36:13.663433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9249 16:36:13.663696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9251 16:36:13.709429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9252 16:36:13.709691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9254 16:36:13.745875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9255 16:36:13.746206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9257 16:36:13.782232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9258 16:36:13.782501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9260 16:36:13.818487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9261 16:36:13.818758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9263 16:36:13.856459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9264 16:36:13.856765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9266 16:36:13.894709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9267 16:36:13.894997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9269 16:36:13.931919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9270 16:36:13.932188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9272 16:36:13.975337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9273 16:36:13.975631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9275 16:36:14.013158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9276 16:36:14.013452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9278 16:36:14.050367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9279 16:36:14.050658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9281 16:36:14.087215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9282 16:36:14.087475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9284 16:36:14.123951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9285 16:36:14.124236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9287 16:36:14.164057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9288 16:36:14.164370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9290 16:36:14.195973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9292 16:36:14.199116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9293 16:36:14.237101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9294 16:36:14.237359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9296 16:36:14.277911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9297 16:36:14.278210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9299 16:36:14.317393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9300 16:36:14.317673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9302 16:36:14.353133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9303 16:36:14.353403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9305 16:36:14.396585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9306 16:36:14.396856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9308 16:36:14.440089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9309 16:36:14.440368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9311 16:36:14.482073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9312 16:36:14.482363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9314 16:36:14.528652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9315 16:36:14.528914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9317 16:36:14.573041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9318 16:36:14.573379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9320 16:36:14.615325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9321 16:36:14.615586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9323 16:36:14.658664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9324 16:36:14.658947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9326 16:36:14.737545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9327 16:36:14.738248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9329 16:36:14.788997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9330 16:36:14.789279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9332 16:36:14.831783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9333 16:36:14.832089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9335 16:36:14.875141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9336 16:36:14.875411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9338 16:36:14.917749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9339 16:36:14.918002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9341 16:36:14.959826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9342 16:36:14.960088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9344 16:36:15.004654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9345 16:36:15.004914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9347 16:36:15.045436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9348 16:36:15.045695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9350 16:36:15.088807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9351 16:36:15.089065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9353 16:36:15.125660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9354 16:36:15.125919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9356 16:36:15.169927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9357 16:36:15.170240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9359 16:36:15.210885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9360 16:36:15.211138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9362 16:36:15.249173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9363 16:36:15.249427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9365 16:36:15.287070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9366 16:36:15.287394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9368 16:36:15.330197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9369 16:36:15.330462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9371 16:36:15.374318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9372 16:36:15.374596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9374 16:36:15.414675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9375 16:36:15.414945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9377 16:36:15.464103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9378 16:36:15.464413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9380 16:36:15.515559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9381 16:36:15.515833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9383 16:36:15.558928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9384 16:36:15.559206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9386 16:36:15.602562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9387 16:36:15.602826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9389 16:36:15.644154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9390 16:36:15.644443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9392 16:36:15.682662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9393 16:36:15.682923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9395 16:36:15.723582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9397 16:36:15.726639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9398 16:36:15.771192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9399 16:36:15.771449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9401 16:36:15.818424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9402 16:36:15.818687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9404 16:36:15.861750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9405 16:36:15.862016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9407 16:36:15.903755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9408 16:36:15.904038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9410 16:36:15.947100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9411 16:36:15.947365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9413 16:36:15.985111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9414 16:36:15.985374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9416 16:36:16.022158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9417 16:36:16.022452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9419 16:36:16.065199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9420 16:36:16.065470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9422 16:36:16.113076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9423 16:36:16.113339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9425 16:36:16.153692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9426 16:36:16.153955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9428 16:36:16.193702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9429 16:36:16.193986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9431 16:36:16.231472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9432 16:36:16.231745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9434 16:36:16.270941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9435 16:36:16.271204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9437 16:36:16.306517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9438 16:36:16.306774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9440 16:36:16.348245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9441 16:36:16.348504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9443 16:36:16.386732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9444 16:36:16.387014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9446 16:36:16.425508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9447 16:36:16.425788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9449 16:36:16.464046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9450 16:36:16.464404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9452 16:36:16.507328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9453 16:36:16.507634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9455 16:36:16.547109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9456 16:36:16.547392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9458 16:36:16.582754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9459 16:36:16.583032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9461 16:36:16.622530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9462 16:36:16.622819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9464 16:36:16.656451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9465 16:36:16.656735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9467 16:36:16.696008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9468 16:36:16.696324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9470 16:36:16.733462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9471 16:36:16.733758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9473 16:36:16.772439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9474 16:36:16.772721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9476 16:36:16.814386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9477 16:36:16.814667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9479 16:36:16.854682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9480 16:36:16.854997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9482 16:36:16.896987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9483 16:36:16.897291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9485 16:36:16.938512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9486 16:36:16.938847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9488 16:36:16.977335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9489 16:36:16.977615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9491 16:36:17.020468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9492 16:36:17.020753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9494 16:36:17.057914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9495 16:36:17.058220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9497 16:36:17.093513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9498 16:36:17.093795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9500 16:36:17.129396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9501 16:36:17.129703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9503 16:36:17.176822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9504 16:36:17.177168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9506 16:36:17.216120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9507 16:36:17.216408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9509 16:36:17.255160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9510 16:36:17.255447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9512 16:36:17.291960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9513 16:36:17.292246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9515 16:36:17.330376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9516 16:36:17.330675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9518 16:36:17.367981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9519 16:36:17.368267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9521 16:36:17.405414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9522 16:36:17.405703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9524 16:36:17.448478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9525 16:36:17.448767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9527 16:36:17.488334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9528 16:36:17.488624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9530 16:36:17.526900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9531 16:36:17.527191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9533 16:36:17.565551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9534 16:36:17.565853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9536 16:36:17.602708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9537 16:36:17.602996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9539 16:36:17.643418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9540 16:36:17.643729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9542 16:36:17.678765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9543 16:36:17.679050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9545 16:36:17.722397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9546 16:36:17.722699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9548 16:36:17.759256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9549 16:36:17.759548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9551 16:36:17.795469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9552 16:36:17.795762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9554 16:36:17.838072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9555 16:36:17.838374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9557 16:36:17.876589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9558 16:36:17.876873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9560 16:36:17.915301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9561 16:36:17.915618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9563 16:36:17.949204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9565 16:36:17.952240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9566 16:36:17.994413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9567 16:36:17.994727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9569 16:36:18.032953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9570 16:36:18.033233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9572 16:36:18.073312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9573 16:36:18.073599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9575 16:36:18.124673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9576 16:36:18.125021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9578 16:36:18.164978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9579 16:36:18.165289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9581 16:36:18.211537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9582 16:36:18.211824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9584 16:36:18.253833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9585 16:36:18.254119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9587 16:36:18.295683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9588 16:36:18.295963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9590 16:36:18.337800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9591 16:36:18.338087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9593 16:36:18.376203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9594 16:36:18.376482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9596 16:36:18.416248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9597 16:36:18.416598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9599 16:36:18.458071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9600 16:36:18.458369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9602 16:36:18.496528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9603 16:36:18.496838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9605 16:36:18.533912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9606 16:36:18.534233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9608 16:36:18.576661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9609 16:36:18.576968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9611 16:36:18.618661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9612 16:36:18.618967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9614 16:36:18.660158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9615 16:36:18.660448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9617 16:36:18.700459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9618 16:36:18.700794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9620 16:36:18.741025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9621 16:36:18.741317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9623 16:36:18.784085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9624 16:36:18.784404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9626 16:36:18.822120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9627 16:36:18.822405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9629 16:36:18.867963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9630 16:36:18.868248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9632 16:36:18.907519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9633 16:36:18.907843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9635 16:36:18.946300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9636 16:36:18.946600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9638 16:36:18.989431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9639 16:36:18.989723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9641 16:36:19.030594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9642 16:36:19.030884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9644 16:36:19.066172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9645 16:36:19.066483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9647 16:36:19.098527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9648 16:36:19.098821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9650 16:36:19.141329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9651 16:36:19.141629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9653 16:36:19.180149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9654 16:36:19.180490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9656 16:36:19.223411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9657 16:36:19.223766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9659 16:36:19.260940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9660 16:36:19.261280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9662 16:36:19.298512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9663 16:36:19.298818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9665 16:36:19.338273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9666 16:36:19.338579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9668 16:36:19.376079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9669 16:36:19.376414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9671 16:36:19.421900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9672 16:36:19.422241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9674 16:36:19.462857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9675 16:36:19.463149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9677 16:36:19.500982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9678 16:36:19.501292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9680 16:36:19.540054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9681 16:36:19.540344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9683 16:36:19.579142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9684 16:36:19.579476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9686 16:36:19.616131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9687 16:36:19.616424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9689 16:36:19.649902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9690 16:36:19.650214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9692 16:36:19.692247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9693 16:36:19.692576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9695 16:36:19.729228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9696 16:36:19.729530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9698 16:36:19.766227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9699 16:36:19.766544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9701 16:36:19.805179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9702 16:36:19.805482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9704 16:36:19.845685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9705 16:36:19.846039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9707 16:36:19.884431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9708 16:36:19.884754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9710 16:36:19.918393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9711 16:36:19.918691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9713 16:36:19.961335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9714 16:36:19.961726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9716 16:36:20.004264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9717 16:36:20.004570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9719 16:36:20.043816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9720 16:36:20.044123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9722 16:36:20.082582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9723 16:36:20.082870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9725 16:36:20.117959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9726 16:36:20.118266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9728 16:36:20.155872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9729 16:36:20.156223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9731 16:36:20.189636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9732 16:36:20.189921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9734 16:36:20.226720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9735 16:36:20.227023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9737 16:36:20.267372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9738 16:36:20.267655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9740 16:36:20.307939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9741 16:36:20.308259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9743 16:36:20.349530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9744 16:36:20.349836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9746 16:36:20.385105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9747 16:36:20.385393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9749 16:36:20.427817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9750 16:36:20.428106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9752 16:36:20.468409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9753 16:36:20.468697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9755 16:36:20.511834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9756 16:36:20.512142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9758 16:36:20.552684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9759 16:36:20.552967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9761 16:36:20.590922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9762 16:36:20.591210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9764 16:36:20.629356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9765 16:36:20.629652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9767 16:36:20.670271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9768 16:36:20.670577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9770 16:36:20.710358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9771 16:36:20.710678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9773 16:36:20.746002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9774 16:36:20.746295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9776 16:36:20.785914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9777 16:36:20.786236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9779 16:36:20.830296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9780 16:36:20.830598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9782 16:36:20.869671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9783 16:36:20.869991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9785 16:36:20.908125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9786 16:36:20.908415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9788 16:36:20.949074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9789 16:36:20.949339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9791 16:36:20.985290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9792 16:36:20.985599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9794 16:36:21.020346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9795 16:36:21.020677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9797 16:36:21.064690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9798 16:36:21.065029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9800 16:36:21.105245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9801 16:36:21.105540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9803 16:36:21.144187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9804 16:36:21.144494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9806 16:36:21.180535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9807 16:36:21.180822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9809 16:36:21.221838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9810 16:36:21.222147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9812 16:36:21.258976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9813 16:36:21.259295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9815 16:36:21.292277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9816 16:36:21.292561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9818 16:36:21.336127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9819 16:36:21.336425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9821 16:36:21.374479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9822 16:36:21.374767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9824 16:36:21.413238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9825 16:36:21.413516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9827 16:36:21.448974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9828 16:36:21.449259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9830 16:36:21.493400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9831 16:36:21.493687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9833 16:36:21.527990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9834 16:36:21.528305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9836 16:36:21.560869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9837 16:36:21.561174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9839 16:36:21.602699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9840 16:36:21.603011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9842 16:36:21.642685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9843 16:36:21.642982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9845 16:36:21.681027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9846 16:36:21.681334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9848 16:36:21.721449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9849 16:36:21.721732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9851 16:36:21.762368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9852 16:36:21.762686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9854 16:36:21.803099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9855 16:36:21.803380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9857 16:36:21.840673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9858 16:36:21.841000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9860 16:36:21.880656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9861 16:36:21.880974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9863 16:36:21.919613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9864 16:36:21.919922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9866 16:36:21.958396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9867 16:36:21.958691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9869 16:36:21.994520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9870 16:36:21.994836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9872 16:36:22.030538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9873 16:36:22.030827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9875 16:36:22.066450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9876 16:36:22.066738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9878 16:36:22.101230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9879 16:36:22.101514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9881 16:36:22.139617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9882 16:36:22.139903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9884 16:36:22.174910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9885 16:36:22.175201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9887 16:36:22.211493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9888 16:36:22.211780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9890 16:36:22.246026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9891 16:36:22.246323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9893 16:36:22.286990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9894 16:36:22.287273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9896 16:36:22.326015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9897 16:36:22.326321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9899 16:36:22.357873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9900 16:36:22.358192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9902 16:36:22.398844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9903 16:36:22.399143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9905 16:36:22.434577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9906 16:36:22.434878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9908 16:36:22.468156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9909 16:36:22.468445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9911 16:36:22.503426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9912 16:36:22.503717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9914 16:36:22.539929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9915 16:36:22.540215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9917 16:36:22.574866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9918 16:36:22.575151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9920 16:36:22.607615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9921 16:36:22.607902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9923 16:36:22.644775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9924 16:36:22.645064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9926 16:36:22.680963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9927 16:36:22.681251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9929 16:36:22.717652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9930 16:36:22.717969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9932 16:36:22.754674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9933 16:36:22.754968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9935 16:36:22.793591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9936 16:36:22.793898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9938 16:36:22.833855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9939 16:36:22.834169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9941 16:36:22.869603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9942 16:36:22.869913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9944 16:36:22.910293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9945 16:36:22.910575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9947 16:36:22.947102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9948 16:36:22.947408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9950 16:36:22.986510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9951 16:36:22.986793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9953 16:36:23.026938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9954 16:36:23.027240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9956 16:36:23.064381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9957 16:36:23.064685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9959 16:36:23.104656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9960 16:36:23.104958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9962 16:36:23.139292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9963 16:36:23.139617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9965 16:36:23.180116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9966 16:36:23.180420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9968 16:36:23.215127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9969 16:36:23.215407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9971 16:36:23.250340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9972 16:36:23.250647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9974 16:36:23.286160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9975 16:36:23.286442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9977 16:36:23.325360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9978 16:36:23.325668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9980 16:36:23.365356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9981 16:36:23.365660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9983 16:36:23.403779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9984 16:36:23.404084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9986 16:36:23.445562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9987 16:36:23.445874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9989 16:36:23.486545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9990 16:36:23.486850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9992 16:36:23.522690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9993 16:36:23.522974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9995 16:36:23.563140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9996 16:36:23.563420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9998 16:36:23.601675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9999 16:36:23.601998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
10001 16:36:23.638109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
10002 16:36:23.638397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
10004 16:36:23.675573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
10005 16:36:23.675881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
10007 16:36:23.717588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
10008 16:36:23.717899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
10010 16:36:23.757021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
10011 16:36:23.757330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
10013 16:36:23.792956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
10014 16:36:23.793265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
10016 16:36:23.833836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
10017 16:36:23.834145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
10019 16:36:23.872460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
10020 16:36:23.872774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
10022 16:36:23.913065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
10023 16:36:23.913380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
10025 16:36:23.951677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
10026 16:36:23.951990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
10028 16:36:23.998514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
10029 16:36:23.998803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
10031 16:36:24.039100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
10032 16:36:24.039432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
10034 16:36:24.082310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
10035 16:36:24.082620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
10037 16:36:24.121156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
10038 16:36:24.121462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
10040 16:36:24.160568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
10041 16:36:24.160873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
10043 16:36:24.201125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
10044 16:36:24.201445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
10046 16:36:24.239420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
10047 16:36:24.239727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
10049 16:36:24.282084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
10050 16:36:24.282398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
10052 16:36:24.325069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
10053 16:36:24.325376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
10055 16:36:24.364470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
10056 16:36:24.364775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
10058 16:36:24.409486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
10059 16:36:24.409795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
10061 16:36:24.450530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
10062 16:36:24.450838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
10064 16:36:24.490267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
10065 16:36:24.490566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
10067 16:36:24.528278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
10068 16:36:24.528586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
10070 16:36:24.570109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
10071 16:36:24.570505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
10073 16:36:24.610589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
10074 16:36:24.610866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
10076 16:36:24.648933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
10077 16:36:24.649248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
10079 16:36:24.691545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
10080 16:36:24.691827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
10082 16:36:24.732038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
10083 16:36:24.732336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
10085 16:36:24.774062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
10086 16:36:24.774351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
10088 16:36:24.815452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
10089 16:36:24.815760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
10091 16:36:24.858473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
10092 16:36:24.858762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
10094 16:36:24.896795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
10095 16:36:24.897133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
10097 16:36:24.937693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
10098 16:36:24.938024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
10100 16:36:24.978913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
10101 16:36:24.979221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
10103 16:36:25.017687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
10104 16:36:25.018002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
10106 16:36:25.055897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
10107 16:36:25.056220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
10109 16:36:25.089579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
10110 16:36:25.089885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
10112 16:36:25.132457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
10113 16:36:25.132773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
10115 16:36:25.173570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
10116 16:36:25.173903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
10118 16:36:25.214131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
10119 16:36:25.214415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
10121 16:36:25.253893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
10122 16:36:25.254224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
10124 16:36:25.291352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
10125 16:36:25.291660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
10127 16:36:25.332425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
10128 16:36:25.332738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
10130 16:36:25.363912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
10131 16:36:25.364195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
10133 16:36:25.404954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
10134 16:36:25.405247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
10136 16:36:25.443193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
10137 16:36:25.443482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
10139 16:36:25.486362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
10140 16:36:25.486683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
10142 16:36:25.527132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
10143 16:36:25.527478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
10145 16:36:25.567754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
10146 16:36:25.568076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
10148 16:36:25.605427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
10149 16:36:25.605766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
10151 16:36:25.639636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
10152 16:36:25.639959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
10154 16:36:25.679455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
10155 16:36:25.679775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
10157 16:36:25.720556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
10158 16:36:25.720861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
10160 16:36:25.759969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
10161 16:36:25.760272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
10163 16:36:25.799586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
10164 16:36:25.799876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
10166 16:36:25.838371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
10167 16:36:25.838648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
10169 16:36:25.874894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10170 16:36:25.875004 + set +x
10171 16:36:25.875273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10173 16:36:25.881311 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14396137_1.6.2.3.5>
10174 16:36:25.881576 Received signal: <ENDRUN> 1_kselftest-alsa 14396137_1.6.2.3.5
10175 16:36:25.881676 Ending use of test pattern.
10176 16:36:25.881766 Ending test lava.1_kselftest-alsa (14396137_1.6.2.3.5), duration 38.80
10178 16:36:25.884433 <LAVA_TEST_RUNNER EXIT>
10179 16:36:25.884693 ok: lava_test_shell seems to have completed
10180 16:36:25.891275 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
10181 16:36:25.891731 end: 3.1 lava-test-shell (duration 00:00:40) [common]
10182 16:36:25.891851 end: 3 lava-test-retry (duration 00:00:40) [common]
10183 16:36:25.891963 start: 4 finalize (timeout 00:07:12) [common]
10184 16:36:25.892083 start: 4.1 power-off (timeout 00:00:30) [common]
10185 16:36:25.892346 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1', '--port=1', '--command=off']
10186 16:36:27.101968 >> Command sent successfully.
10187 16:36:27.105425 Returned 0 in 1 seconds
10188 16:36:27.205772 end: 4.1 power-off (duration 00:00:01) [common]
10190 16:36:27.206182 start: 4.2 read-feedback (timeout 00:07:11) [common]
10191 16:36:27.206488 Listened to connection for namespace 'common' for up to 1s
10192 16:36:28.206661 Finalising connection for namespace 'common'
10193 16:36:28.206803 Disconnecting from shell: Finalise
10194 16:36:28.206885 / #
10195 16:36:28.307118 end: 4.2 read-feedback (duration 00:00:01) [common]
10196 16:36:28.307289 end: 4 finalize (duration 00:00:02) [common]
10197 16:36:28.307442 Cleaning after the job
10198 16:36:28.307576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/ramdisk
10199 16:36:28.309842 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/kernel
10200 16:36:28.321076 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/dtb
10201 16:36:28.321281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/nfsrootfs
10202 16:36:28.383706 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396137/tftp-deploy-tx65ao95/modules
10203 16:36:28.389187 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396137
10204 16:36:28.994417 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396137
10205 16:36:28.994595 Job finished correctly