Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 16:28:42.879597 lava-dispatcher, installed at version: 2024.03
2 16:28:42.879852 start: 0 validate
3 16:28:42.879970 Start time: 2024-06-17 16:28:42.879963+00:00 (UTC)
4 16:28:42.880108 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:28:42.880256 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:28:43.145774 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:28:43.145946 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:29:11.906733 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:29:11.906912 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:29:12.170031 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:29:12.170216 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:29:12.686063 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:29:12.686254 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:29:15.189345 validate duration: 32.31
16 16:29:15.189762 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:29:15.189900 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:29:15.190031 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:29:15.190233 Not decompressing ramdisk as can be used compressed.
20 16:29:15.190371 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:29:15.190466 saving as /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/ramdisk/initrd.cpio.gz
22 16:29:15.190557 total size: 5628169 (5 MB)
23 16:29:15.454292 progress 0 % (0 MB)
24 16:29:15.456123 progress 5 % (0 MB)
25 16:29:15.457955 progress 10 % (0 MB)
26 16:29:15.459635 progress 15 % (0 MB)
27 16:29:15.461382 progress 20 % (1 MB)
28 16:29:15.462955 progress 25 % (1 MB)
29 16:29:15.464771 progress 30 % (1 MB)
30 16:29:15.466462 progress 35 % (1 MB)
31 16:29:15.468050 progress 40 % (2 MB)
32 16:29:15.469763 progress 45 % (2 MB)
33 16:29:15.471227 progress 50 % (2 MB)
34 16:29:15.472933 progress 55 % (2 MB)
35 16:29:15.474559 progress 60 % (3 MB)
36 16:29:15.476151 progress 65 % (3 MB)
37 16:29:15.477838 progress 70 % (3 MB)
38 16:29:15.479378 progress 75 % (4 MB)
39 16:29:15.481183 progress 80 % (4 MB)
40 16:29:15.482663 progress 85 % (4 MB)
41 16:29:15.484462 progress 90 % (4 MB)
42 16:29:15.486102 progress 95 % (5 MB)
43 16:29:15.487595 progress 100 % (5 MB)
44 16:29:15.487845 5 MB downloaded in 0.30 s (18.06 MB/s)
45 16:29:15.488043 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:29:15.488417 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:29:15.488531 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:29:15.488648 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:29:15.488810 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:29:15.488911 saving as /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/kernel/Image
52 16:29:15.488993 total size: 54813184 (52 MB)
53 16:29:15.489097 No compression specified
54 16:29:15.490701 progress 0 % (0 MB)
55 16:29:15.513100 progress 5 % (2 MB)
56 16:29:15.535652 progress 10 % (5 MB)
57 16:29:15.558094 progress 15 % (7 MB)
58 16:29:15.572608 progress 20 % (10 MB)
59 16:29:15.586764 progress 25 % (13 MB)
60 16:29:15.600702 progress 30 % (15 MB)
61 16:29:15.614897 progress 35 % (18 MB)
62 16:29:15.629183 progress 40 % (20 MB)
63 16:29:15.643683 progress 45 % (23 MB)
64 16:29:15.658480 progress 50 % (26 MB)
65 16:29:15.673084 progress 55 % (28 MB)
66 16:29:15.687513 progress 60 % (31 MB)
67 16:29:15.702359 progress 65 % (34 MB)
68 16:29:15.716577 progress 70 % (36 MB)
69 16:29:15.730648 progress 75 % (39 MB)
70 16:29:15.745458 progress 80 % (41 MB)
71 16:29:15.760076 progress 85 % (44 MB)
72 16:29:15.775198 progress 90 % (47 MB)
73 16:29:15.789273 progress 95 % (49 MB)
74 16:29:15.803148 progress 100 % (52 MB)
75 16:29:15.803407 52 MB downloaded in 0.31 s (166.26 MB/s)
76 16:29:15.803559 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:29:15.803777 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:29:15.803859 start: 1.3 download-retry (timeout 00:09:59) [common]
80 16:29:15.803935 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 16:29:15.804075 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:29:15.804141 saving as /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/dtb/mt8192-asurada-spherion-r0.dtb
83 16:29:15.804203 total size: 47258 (0 MB)
84 16:29:15.804259 No compression specified
85 16:29:15.805486 progress 69 % (0 MB)
86 16:29:15.805794 progress 100 % (0 MB)
87 16:29:15.805950 0 MB downloaded in 0.00 s (25.84 MB/s)
88 16:29:15.806069 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:29:15.806294 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:29:15.806372 start: 1.4 download-retry (timeout 00:09:59) [common]
92 16:29:15.806449 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 16:29:15.806578 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:29:15.806640 saving as /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/nfsrootfs/full.rootfs.tar
95 16:29:15.806717 total size: 120894716 (115 MB)
96 16:29:15.806773 Using unxz to decompress xz
97 16:29:15.808369 progress 0 % (0 MB)
98 16:29:16.168671 progress 5 % (5 MB)
99 16:29:16.525621 progress 10 % (11 MB)
100 16:29:16.884379 progress 15 % (17 MB)
101 16:29:17.220627 progress 20 % (23 MB)
102 16:29:17.530414 progress 25 % (28 MB)
103 16:29:17.899175 progress 30 % (34 MB)
104 16:29:18.250670 progress 35 % (40 MB)
105 16:29:18.429829 progress 40 % (46 MB)
106 16:29:18.620596 progress 45 % (51 MB)
107 16:29:18.941047 progress 50 % (57 MB)
108 16:29:19.329310 progress 55 % (63 MB)
109 16:29:19.724381 progress 60 % (69 MB)
110 16:29:20.101992 progress 65 % (74 MB)
111 16:29:20.488823 progress 70 % (80 MB)
112 16:29:20.859711 progress 75 % (86 MB)
113 16:29:21.218668 progress 80 % (92 MB)
114 16:29:21.588008 progress 85 % (98 MB)
115 16:29:21.956176 progress 90 % (103 MB)
116 16:29:22.309265 progress 95 % (109 MB)
117 16:29:22.690686 progress 100 % (115 MB)
118 16:29:22.696301 115 MB downloaded in 6.89 s (16.73 MB/s)
119 16:29:22.696562 end: 1.4.1 http-download (duration 00:00:07) [common]
121 16:29:22.696830 end: 1.4 download-retry (duration 00:00:07) [common]
122 16:29:22.696919 start: 1.5 download-retry (timeout 00:09:52) [common]
123 16:29:22.697016 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 16:29:22.697147 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:29:22.697210 saving as /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/modules/modules.tar
126 16:29:22.697266 total size: 8628772 (8 MB)
127 16:29:22.697351 Using unxz to decompress xz
128 16:29:22.698701 progress 0 % (0 MB)
129 16:29:22.721167 progress 5 % (0 MB)
130 16:29:22.747204 progress 10 % (0 MB)
131 16:29:22.772936 progress 15 % (1 MB)
132 16:29:22.799116 progress 20 % (1 MB)
133 16:29:22.825706 progress 25 % (2 MB)
134 16:29:22.851632 progress 30 % (2 MB)
135 16:29:22.878769 progress 35 % (2 MB)
136 16:29:22.904278 progress 40 % (3 MB)
137 16:29:22.928898 progress 45 % (3 MB)
138 16:29:22.956198 progress 50 % (4 MB)
139 16:29:22.980877 progress 55 % (4 MB)
140 16:29:23.006674 progress 60 % (4 MB)
141 16:29:23.034203 progress 65 % (5 MB)
142 16:29:23.059148 progress 70 % (5 MB)
143 16:29:23.083981 progress 75 % (6 MB)
144 16:29:23.110709 progress 80 % (6 MB)
145 16:29:23.139613 progress 85 % (7 MB)
146 16:29:23.168413 progress 90 % (7 MB)
147 16:29:23.194933 progress 95 % (7 MB)
148 16:29:23.220002 progress 100 % (8 MB)
149 16:29:23.225102 8 MB downloaded in 0.53 s (15.59 MB/s)
150 16:29:23.225361 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:29:23.225705 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:29:23.225825 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 16:29:23.225943 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 16:29:27.207293 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac
156 16:29:27.207488 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 16:29:27.207580 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 16:29:27.207759 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo
159 16:29:27.207884 makedir: /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin
160 16:29:27.207980 makedir: /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/tests
161 16:29:27.208070 makedir: /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/results
162 16:29:27.208159 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-add-keys
163 16:29:27.208291 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-add-sources
164 16:29:27.208411 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-background-process-start
165 16:29:27.208529 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-background-process-stop
166 16:29:27.208655 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-common-functions
167 16:29:27.208772 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-echo-ipv4
168 16:29:27.208897 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-install-packages
169 16:29:27.209023 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-installed-packages
170 16:29:27.209142 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-os-build
171 16:29:27.209277 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-probe-channel
172 16:29:27.209423 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-probe-ip
173 16:29:27.209583 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-target-ip
174 16:29:27.209701 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-target-mac
175 16:29:27.209814 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-target-storage
176 16:29:27.209932 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-case
177 16:29:27.210047 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-event
178 16:29:27.210162 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-feedback
179 16:29:27.210276 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-raise
180 16:29:27.210398 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-reference
181 16:29:27.210532 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-runner
182 16:29:27.210649 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-set
183 16:29:27.210762 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-test-shell
184 16:29:27.210887 Updating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-add-keys (debian)
185 16:29:27.211032 Updating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-add-sources (debian)
186 16:29:27.211167 Updating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-install-packages (debian)
187 16:29:27.211297 Updating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-installed-packages (debian)
188 16:29:27.211425 Updating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/bin/lava-os-build (debian)
189 16:29:27.211544 Creating /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/environment
190 16:29:27.211636 LAVA metadata
191 16:29:27.211706 - LAVA_JOB_ID=14396104
192 16:29:27.211763 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:29:27.211896 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 16:29:27.211980 skipped lava-vland-overlay
195 16:29:27.212094 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:29:27.212223 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 16:29:27.212310 skipped lava-multinode-overlay
198 16:29:27.212432 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:29:27.212541 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 16:29:27.212636 Loading test definitions
201 16:29:27.212744 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 16:29:27.212830 Using /lava-14396104 at stage 0
203 16:29:27.213208 uuid=14396104_1.6.2.3.1 testdef=None
204 16:29:27.213319 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:29:27.213424 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 16:29:27.214132 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:29:27.214339 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 16:29:27.214975 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:29:27.215333 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 16:29:27.216016 runner path: /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/0/tests/0_timesync-off test_uuid 14396104_1.6.2.3.1
213 16:29:27.216168 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:29:27.216380 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 16:29:27.216448 Using /lava-14396104 at stage 0
217 16:29:27.216546 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:29:27.216620 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/0/tests/1_kselftest-alsa'
219 16:29:29.865488 Running '/usr/bin/git checkout kernelci.org
220 16:29:30.038622 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 16:29:30.038991 uuid=14396104_1.6.2.3.5 testdef=None
222 16:29:30.039096 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 16:29:30.039293 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 16:29:30.039945 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:29:30.040152 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 16:29:30.041018 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:29:30.041235 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 16:29:30.089310 runner path: /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/0/tests/1_kselftest-alsa test_uuid 14396104_1.6.2.3.5
232 16:29:30.089416 BOARD='mt8192-asurada-spherion-r0'
233 16:29:30.089503 BRANCH='cip-gitlab'
234 16:29:30.089586 SKIPFILE='/dev/null'
235 16:29:30.089641 SKIP_INSTALL='True'
236 16:29:30.089692 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:29:30.089745 TST_CASENAME=''
238 16:29:30.089796 TST_CMDFILES='alsa'
239 16:29:30.089960 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:29:30.090154 Creating lava-test-runner.conf files
242 16:29:30.090210 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396104/lava-overlay-pb7zsafo/lava-14396104/0 for stage 0
243 16:29:30.090295 - 0_timesync-off
244 16:29:30.090357 - 1_kselftest-alsa
245 16:29:30.090449 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 16:29:30.090529 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 16:29:37.967440 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 16:29:37.967587 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 16:29:37.967672 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:29:37.967756 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 16:29:37.967836 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 16:29:38.134657 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:29:38.134792 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 16:29:38.134870 extracting modules file /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac
255 16:29:38.379280 extracting modules file /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396104/extract-overlay-ramdisk-rgjpsn31/ramdisk
256 16:29:38.612818 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:29:38.612960 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 16:29:38.613048 [common] Applying overlay to NFS
259 16:29:38.613108 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396104/compress-overlay-d1omdtay/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac
260 16:29:39.517863 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:29:39.518032 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 16:29:39.518150 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:29:39.518259 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 16:29:39.518363 Building ramdisk /var/lib/lava/dispatcher/tmp/14396104/extract-overlay-ramdisk-rgjpsn31/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396104/extract-overlay-ramdisk-rgjpsn31/ramdisk
265 16:29:39.832015 >> 130466 blocks
266 16:29:42.029414 rename /var/lib/lava/dispatcher/tmp/14396104/extract-overlay-ramdisk-rgjpsn31/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/ramdisk/ramdisk.cpio.gz
267 16:29:42.029666 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 16:29:42.029760 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 16:29:42.029854 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 16:29:42.029949 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/kernel/Image']
271 16:29:56.458496 Returned 0 in 14 seconds
272 16:29:56.558967 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/kernel/image.itb
273 16:29:57.057690 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:29:57.057828 output: Created: Mon Jun 17 17:29:56 2024
275 16:29:57.057895 output: Image 0 (kernel-1)
276 16:29:57.057953 output: Description:
277 16:29:57.058015 output: Created: Mon Jun 17 17:29:56 2024
278 16:29:57.058081 output: Type: Kernel Image
279 16:29:57.058138 output: Compression: lzma compressed
280 16:29:57.058193 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
281 16:29:57.058252 output: Architecture: AArch64
282 16:29:57.058320 output: OS: Linux
283 16:29:57.058397 output: Load Address: 0x00000000
284 16:29:57.058475 output: Entry Point: 0x00000000
285 16:29:57.058554 output: Hash algo: crc32
286 16:29:57.058616 output: Hash value: 106ffd6f
287 16:29:57.058695 output: Image 1 (fdt-1)
288 16:29:57.058784 output: Description: mt8192-asurada-spherion-r0
289 16:29:57.058866 output: Created: Mon Jun 17 17:29:56 2024
290 16:29:57.058945 output: Type: Flat Device Tree
291 16:29:57.059031 output: Compression: uncompressed
292 16:29:57.059117 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 16:29:57.059201 output: Architecture: AArch64
294 16:29:57.059293 output: Hash algo: crc32
295 16:29:57.059374 output: Hash value: 0f8e4d2e
296 16:29:57.059449 output: Image 2 (ramdisk-1)
297 16:29:57.059533 output: Description: unavailable
298 16:29:57.059611 output: Created: Mon Jun 17 17:29:56 2024
299 16:29:57.059686 output: Type: RAMDisk Image
300 16:29:57.059769 output: Compression: uncompressed
301 16:29:57.059847 output: Data Size: 18745541 Bytes = 18306.19 KiB = 17.88 MiB
302 16:29:57.059921 output: Architecture: AArch64
303 16:29:57.059996 output: OS: Linux
304 16:29:57.060081 output: Load Address: unavailable
305 16:29:57.060157 output: Entry Point: unavailable
306 16:29:57.060232 output: Hash algo: crc32
307 16:29:57.060317 output: Hash value: 94a11767
308 16:29:57.060391 output: Default Configuration: 'conf-1'
309 16:29:57.060465 output: Configuration 0 (conf-1)
310 16:29:57.060549 output: Description: mt8192-asurada-spherion-r0
311 16:29:57.060626 output: Kernel: kernel-1
312 16:29:57.060699 output: Init Ramdisk: ramdisk-1
313 16:29:57.060782 output: FDT: fdt-1
314 16:29:57.060859 output: Loadables: kernel-1
315 16:29:57.060932 output:
316 16:29:57.061103 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 16:29:57.061219 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 16:29:57.061349 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 16:29:57.061458 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 16:29:57.061588 No LXC device requested
321 16:29:57.061680 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:29:57.061769 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 16:29:57.061846 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:29:57.061910 Checking files for TFTP limit of 4294967296 bytes.
325 16:29:57.062444 end: 1 tftp-deploy (duration 00:00:42) [common]
326 16:29:57.062578 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:29:57.062690 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:29:57.062851 substitutions:
329 16:29:57.062938 - {DTB}: 14396104/tftp-deploy-sqzd0v25/dtb/mt8192-asurada-spherion-r0.dtb
330 16:29:57.063030 - {INITRD}: 14396104/tftp-deploy-sqzd0v25/ramdisk/ramdisk.cpio.gz
331 16:29:57.063114 - {KERNEL}: 14396104/tftp-deploy-sqzd0v25/kernel/Image
332 16:29:57.063193 - {LAVA_MAC}: None
333 16:29:57.063280 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac
334 16:29:57.063360 - {NFS_SERVER_IP}: 192.168.201.1
335 16:29:57.063437 - {PRESEED_CONFIG}: None
336 16:29:57.063529 - {PRESEED_LOCAL}: None
337 16:29:57.063611 - {RAMDISK}: 14396104/tftp-deploy-sqzd0v25/ramdisk/ramdisk.cpio.gz
338 16:29:57.063687 - {ROOT_PART}: None
339 16:29:57.063771 - {ROOT}: None
340 16:29:57.063849 - {SERVER_IP}: 192.168.201.1
341 16:29:57.063924 - {TEE}: None
342 16:29:57.064004 Parsed boot commands:
343 16:29:57.064084 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:29:57.064281 Parsed boot commands: tftpboot 192.168.201.1 14396104/tftp-deploy-sqzd0v25/kernel/image.itb 14396104/tftp-deploy-sqzd0v25/kernel/cmdline
345 16:29:57.064387 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:29:57.064490 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:29:57.064611 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:29:57.064688 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:29:57.064756 Not connected, no need to disconnect.
350 16:29:57.064856 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:29:57.064953 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:29:57.065048 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 16:29:57.068487 Setting prompt string to ['lava-test: # ']
354 16:29:57.068843 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:29:57.068976 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:29:57.069096 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:29:57.069229 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:29:57.069579 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 16:30:06.215373 >> Command sent successfully.
360 16:30:06.218440 Returned 0 in 9 seconds
361 16:30:06.318738 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 16:30:06.319128 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 16:30:06.319253 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 16:30:06.319367 Setting prompt string to 'Starting depthcharge on Spherion...'
366 16:30:06.319456 Changing prompt to 'Starting depthcharge on Spherion...'
367 16:30:06.319551 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 16:30:06.320048 [Enter `^Ec?' for help]
369 16:30:07.630530
370 16:30:07.630651
371 16:30:07.630717 F0: 102B 0000
372 16:30:07.630778
373 16:30:07.630835 F3: 1001 0000 [0200]
374 16:30:07.630891
375 16:30:07.634641 F3: 1001 0000
376 16:30:07.634716
377 16:30:07.634774 F7: 102D 0000
378 16:30:07.634828
379 16:30:07.634880 F1: 0000 0000
380 16:30:07.637979
381 16:30:07.638059 V0: 0000 0000 [0001]
382 16:30:07.638118
383 16:30:07.638194 00: 0007 8000
384 16:30:07.638272
385 16:30:07.641652 01: 0000 0000
386 16:30:07.641735
387 16:30:07.641799 BP: 0C00 0209 [0000]
388 16:30:07.641856
389 16:30:07.645171 G0: 1182 0000
390 16:30:07.645248
391 16:30:07.645307 EC: 0000 0021 [4000]
392 16:30:07.645362
393 16:30:07.648846 S7: 0000 0000 [0000]
394 16:30:07.648955
395 16:30:07.649041 CC: 0000 0000 [0001]
396 16:30:07.649123
397 16:30:07.652580 T0: 0000 0040 [010F]
398 16:30:07.652672
399 16:30:07.652737 Jump to BL
400 16:30:07.652794
401 16:30:07.677783
402 16:30:07.677923
403 16:30:07.684459 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 16:30:07.688194 ARM64: Exception handlers installed.
405 16:30:07.691231 ARM64: Testing exception
406 16:30:07.694915 ARM64: Done test exception
407 16:30:07.702080 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 16:30:07.713357 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 16:30:07.721279 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 16:30:07.728002 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 16:30:07.735158 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 16:30:07.742030 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 16:30:07.754080 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 16:30:07.760826 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 16:30:07.780233 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 16:30:07.783930 WDT: Last reset was cold boot
417 16:30:07.787162 SPI1(PAD0) initialized at 2873684 Hz
418 16:30:07.790670 SPI5(PAD0) initialized at 992727 Hz
419 16:30:07.793600 VBOOT: Loading verstage.
420 16:30:07.800275 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 16:30:07.803967 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 16:30:07.806954 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 16:30:07.810629 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 16:30:07.817887 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 16:30:07.824463 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 16:30:07.835405 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 16:30:07.835513
428 16:30:07.835576
429 16:30:07.845933 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 16:30:07.848732 ARM64: Exception handlers installed.
431 16:30:07.852299 ARM64: Testing exception
432 16:30:07.852407 ARM64: Done test exception
433 16:30:07.859057 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 16:30:07.862634 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 16:30:07.876305 Probing TPM: . done!
436 16:30:07.876428 TPM ready after 0 ms
437 16:30:07.883472 Connected to device vid:did:rid of 1ae0:0028:00
438 16:30:07.892986 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 16:30:07.930589 Initialized TPM device CR50 revision 0
440 16:30:07.941776 tlcl_send_startup: Startup return code is 0
441 16:30:07.941896 TPM: setup succeeded
442 16:30:07.953440 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 16:30:07.962237 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 16:30:07.972611 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 16:30:07.981269 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 16:30:07.984946 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 16:30:07.987862 in-header: 03 07 00 00 08 00 00 00
448 16:30:07.991603 in-data: aa e4 47 04 13 02 00 00
449 16:30:07.994620 Chrome EC: UHEPI supported
450 16:30:08.001242 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 16:30:08.005019 in-header: 03 a9 00 00 08 00 00 00
452 16:30:08.007901 in-data: 84 60 60 08 00 00 00 00
453 16:30:08.007990 Phase 1
454 16:30:08.014335 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 16:30:08.021086 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 16:30:08.024786 VB2:vb2_check_recovery() Recovery was requested manually
457 16:30:08.031132 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 16:30:08.034364 Recovery requested (1009000e)
459 16:30:08.040331 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 16:30:08.046132 tlcl_extend: response is 0
461 16:30:08.054115 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 16:30:08.059619 tlcl_extend: response is 0
463 16:30:08.066376 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 16:30:08.086786 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 16:30:08.093325 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 16:30:08.093459
467 16:30:08.093560
468 16:30:08.103598 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 16:30:08.107212 ARM64: Exception handlers installed.
470 16:30:08.110183 ARM64: Testing exception
471 16:30:08.110256 ARM64: Done test exception
472 16:30:08.132313 pmic_efuse_setting: Set efuses in 11 msecs
473 16:30:08.135750 pmwrap_interface_init: Select PMIF_VLD_RDY
474 16:30:08.142464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 16:30:08.146022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 16:30:08.152578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 16:30:08.155618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 16:30:08.162556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 16:30:08.165882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 16:30:08.169159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 16:30:08.175466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 16:30:08.178778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 16:30:08.186036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 16:30:08.189083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 16:30:08.192623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 16:30:08.199432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 16:30:08.205971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 16:30:08.209030 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 16:30:08.215623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 16:30:08.222378 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 16:30:08.225949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 16:30:08.232600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 16:30:08.239070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 16:30:08.242973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 16:30:08.248901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 16:30:08.255680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 16:30:08.259231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 16:30:08.266099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 16:30:08.274037 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 16:30:08.277786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 16:30:08.281471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 16:30:08.288222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 16:30:08.291138 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 16:30:08.295310 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 16:30:08.302796 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 16:30:08.306209 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 16:30:08.312791 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 16:30:08.316154 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 16:30:08.322432 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 16:30:08.325791 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 16:30:08.333100 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 16:30:08.336937 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 16:30:08.340111 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 16:30:08.343275 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 16:30:08.350426 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 16:30:08.353636 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 16:30:08.356666 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 16:30:08.363820 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 16:30:08.367113 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 16:30:08.370385 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 16:30:08.373966 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 16:30:08.380500 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 16:30:08.383410 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 16:30:08.387123 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 16:30:08.394242 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 16:30:08.404278 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 16:30:08.407274 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 16:30:08.417029 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 16:30:08.424057 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 16:30:08.430165 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 16:30:08.433606 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 16:30:08.437037 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 16:30:08.445427 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x9
534 16:30:08.451730 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 16:30:08.455554 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 16:30:08.458449 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 16:30:08.469801 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 16:30:08.479175 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 16:30:08.488471 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 16:30:08.498341 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 16:30:08.508087 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 16:30:08.517437 [RTC]rtc_get_frequency_meter,154: input=16, output=783
543 16:30:08.526936 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 16:30:08.529929 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 16:30:08.537220 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 16:30:08.540763 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 16:30:08.544369 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 16:30:08.547276 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 16:30:08.554272 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 16:30:08.557107 ADC[4]: Raw value=905834 ID=7
551 16:30:08.557205 ADC[3]: Raw value=213441 ID=1
552 16:30:08.560472 RAM Code: 0x71
553 16:30:08.563749 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 16:30:08.570279 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 16:30:08.577146 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 16:30:08.583784 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 16:30:08.587456 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 16:30:08.591073 in-header: 03 07 00 00 08 00 00 00
559 16:30:08.593902 in-data: aa e4 47 04 13 02 00 00
560 16:30:08.597456 Chrome EC: UHEPI supported
561 16:30:08.604321 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 16:30:08.607125 in-header: 03 a9 00 00 08 00 00 00
563 16:30:08.610998 in-data: 84 60 60 08 00 00 00 00
564 16:30:08.614230 MRC: failed to locate region type 0.
565 16:30:08.620613 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 16:30:08.624227 DRAM-K: Running full calibration
567 16:30:08.630786 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 16:30:08.630885 header.status = 0x0
569 16:30:08.634499 header.version = 0x6 (expected: 0x6)
570 16:30:08.637412 header.size = 0xd00 (expected: 0xd00)
571 16:30:08.640865 header.flags = 0x0
572 16:30:08.644440 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 16:30:08.663262 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 16:30:08.669828 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 16:30:08.673302 dram_init: ddr_geometry: 2
576 16:30:08.673399 [EMI] MDL number = 2
577 16:30:08.676829 [EMI] Get MDL freq = 0
578 16:30:08.680078 dram_init: ddr_type: 0
579 16:30:08.680172 is_discrete_lpddr4: 1
580 16:30:08.683303 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 16:30:08.683373
582 16:30:08.683434
583 16:30:08.686613 [Bian_co] ETT version 0.0.0.1
584 16:30:08.693659 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 16:30:08.693772
586 16:30:08.697035 dramc_set_vcore_voltage set vcore to 650000
587 16:30:08.697146 Read voltage for 800, 4
588 16:30:08.700500 Vio18 = 0
589 16:30:08.700605 Vcore = 650000
590 16:30:08.700695 Vdram = 0
591 16:30:08.703477 Vddq = 0
592 16:30:08.703577 Vmddr = 0
593 16:30:08.706898 dram_init: config_dvfs: 1
594 16:30:08.710451 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 16:30:08.716848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 16:30:08.720193 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 16:30:08.723567 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 16:30:08.726921 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 16:30:08.730193 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 16:30:08.734022 MEM_TYPE=3, freq_sel=18
601 16:30:08.736993 sv_algorithm_assistance_LP4_1600
602 16:30:08.740697 ============ PULL DRAM RESETB DOWN ============
603 16:30:08.743649 ========== PULL DRAM RESETB DOWN end =========
604 16:30:08.750721 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 16:30:08.753730 ===================================
606 16:30:08.753826 LPDDR4 DRAM CONFIGURATION
607 16:30:08.757416 ===================================
608 16:30:08.760277 EX_ROW_EN[0] = 0x0
609 16:30:08.763938 EX_ROW_EN[1] = 0x0
610 16:30:08.764035 LP4Y_EN = 0x0
611 16:30:08.766850 WORK_FSP = 0x0
612 16:30:08.766942 WL = 0x2
613 16:30:08.770433 RL = 0x2
614 16:30:08.770529 BL = 0x2
615 16:30:08.774195 RPST = 0x0
616 16:30:08.774272 RD_PRE = 0x0
617 16:30:08.777147 WR_PRE = 0x1
618 16:30:08.777241 WR_PST = 0x0
619 16:30:08.780915 DBI_WR = 0x0
620 16:30:08.781010 DBI_RD = 0x0
621 16:30:08.783920 OTF = 0x1
622 16:30:08.786835 ===================================
623 16:30:08.790438 ===================================
624 16:30:08.790539 ANA top config
625 16:30:08.794248 ===================================
626 16:30:08.797092 DLL_ASYNC_EN = 0
627 16:30:08.800679 ALL_SLAVE_EN = 1
628 16:30:08.800773 NEW_RANK_MODE = 1
629 16:30:08.804178 DLL_IDLE_MODE = 1
630 16:30:08.807630 LP45_APHY_COMB_EN = 1
631 16:30:08.810726 TX_ODT_DIS = 1
632 16:30:08.813868 NEW_8X_MODE = 1
633 16:30:08.817489 ===================================
634 16:30:08.820346 ===================================
635 16:30:08.820446 data_rate = 1600
636 16:30:08.824262 CKR = 1
637 16:30:08.827498 DQ_P2S_RATIO = 8
638 16:30:08.830908 ===================================
639 16:30:08.834323 CA_P2S_RATIO = 8
640 16:30:08.837761 DQ_CA_OPEN = 0
641 16:30:08.837833 DQ_SEMI_OPEN = 0
642 16:30:08.840757 CA_SEMI_OPEN = 0
643 16:30:08.843923 CA_FULL_RATE = 0
644 16:30:08.847424 DQ_CKDIV4_EN = 1
645 16:30:08.850785 CA_CKDIV4_EN = 1
646 16:30:08.854260 CA_PREDIV_EN = 0
647 16:30:08.854332 PH8_DLY = 0
648 16:30:08.857220 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 16:30:08.860944 DQ_AAMCK_DIV = 4
650 16:30:08.863705 CA_AAMCK_DIV = 4
651 16:30:08.867394 CA_ADMCK_DIV = 4
652 16:30:08.870441 DQ_TRACK_CA_EN = 0
653 16:30:08.870537 CA_PICK = 800
654 16:30:08.874143 CA_MCKIO = 800
655 16:30:08.877123 MCKIO_SEMI = 0
656 16:30:08.880677 PLL_FREQ = 3068
657 16:30:08.884296 DQ_UI_PI_RATIO = 32
658 16:30:08.887142 CA_UI_PI_RATIO = 0
659 16:30:08.890672 ===================================
660 16:30:08.894151 ===================================
661 16:30:08.894228 memory_type:LPDDR4
662 16:30:08.897242 GP_NUM : 10
663 16:30:08.900830 SRAM_EN : 1
664 16:30:08.900904 MD32_EN : 0
665 16:30:08.903797 ===================================
666 16:30:08.907633 [ANA_INIT] >>>>>>>>>>>>>>
667 16:30:08.910470 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 16:30:08.914119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 16:30:08.917733 ===================================
670 16:30:08.920592 data_rate = 1600,PCW = 0X7600
671 16:30:08.924039 ===================================
672 16:30:08.927462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 16:30:08.930761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 16:30:08.938531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 16:30:08.942222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 16:30:08.945797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 16:30:08.949926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 16:30:08.950027 [ANA_INIT] flow start
679 16:30:08.953291 [ANA_INIT] PLL >>>>>>>>
680 16:30:08.956942 [ANA_INIT] PLL <<<<<<<<
681 16:30:08.957021 [ANA_INIT] MIDPI >>>>>>>>
682 16:30:08.960731 [ANA_INIT] MIDPI <<<<<<<<
683 16:30:08.960834 [ANA_INIT] DLL >>>>>>>>
684 16:30:08.964520 [ANA_INIT] flow end
685 16:30:08.968147 ============ LP4 DIFF to SE enter ============
686 16:30:08.971619 ============ LP4 DIFF to SE exit ============
687 16:30:08.974710 [ANA_INIT] <<<<<<<<<<<<<
688 16:30:08.978431 [Flow] Enable top DCM control >>>>>
689 16:30:08.981808 [Flow] Enable top DCM control <<<<<
690 16:30:08.984748 Enable DLL master slave shuffle
691 16:30:08.991331 ==============================================================
692 16:30:08.991440 Gating Mode config
693 16:30:08.997933 ==============================================================
694 16:30:08.998035 Config description:
695 16:30:09.008276 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 16:30:09.014867 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 16:30:09.021498 SELPH_MODE 0: By rank 1: By Phase
698 16:30:09.024486 ==============================================================
699 16:30:09.028024 GAT_TRACK_EN = 1
700 16:30:09.031697 RX_GATING_MODE = 2
701 16:30:09.034654 RX_GATING_TRACK_MODE = 2
702 16:30:09.038312 SELPH_MODE = 1
703 16:30:09.041194 PICG_EARLY_EN = 1
704 16:30:09.044797 VALID_LAT_VALUE = 1
705 16:30:09.048320 ==============================================================
706 16:30:09.051318 Enter into Gating configuration >>>>
707 16:30:09.054919 Exit from Gating configuration <<<<
708 16:30:09.058388 Enter into DVFS_PRE_config >>>>>
709 16:30:09.071660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 16:30:09.074870 Exit from DVFS_PRE_config <<<<<
711 16:30:09.074955 Enter into PICG configuration >>>>
712 16:30:09.078228 Exit from PICG configuration <<<<
713 16:30:09.081745 [RX_INPUT] configuration >>>>>
714 16:30:09.084954 [RX_INPUT] configuration <<<<<
715 16:30:09.092454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 16:30:09.095396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 16:30:09.101839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 16:30:09.108640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 16:30:09.115365 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 16:30:09.121859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 16:30:09.124807 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 16:30:09.128390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 16:30:09.131415 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 16:30:09.137976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 16:30:09.141680 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 16:30:09.145246 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 16:30:09.148096 ===================================
728 16:30:09.151568 LPDDR4 DRAM CONFIGURATION
729 16:30:09.155195 ===================================
730 16:30:09.155283 EX_ROW_EN[0] = 0x0
731 16:30:09.158120 EX_ROW_EN[1] = 0x0
732 16:30:09.161707 LP4Y_EN = 0x0
733 16:30:09.161787 WORK_FSP = 0x0
734 16:30:09.165339 WL = 0x2
735 16:30:09.165419 RL = 0x2
736 16:30:09.168249 BL = 0x2
737 16:30:09.168330 RPST = 0x0
738 16:30:09.171797 RD_PRE = 0x0
739 16:30:09.171878 WR_PRE = 0x1
740 16:30:09.175227 WR_PST = 0x0
741 16:30:09.175332 DBI_WR = 0x0
742 16:30:09.178747 DBI_RD = 0x0
743 16:30:09.178853 OTF = 0x1
744 16:30:09.181591 ===================================
745 16:30:09.185066 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 16:30:09.191401 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 16:30:09.195085 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 16:30:09.198665 ===================================
749 16:30:09.201593 LPDDR4 DRAM CONFIGURATION
750 16:30:09.205048 ===================================
751 16:30:09.205150 EX_ROW_EN[0] = 0x10
752 16:30:09.208637 EX_ROW_EN[1] = 0x0
753 16:30:09.208742 LP4Y_EN = 0x0
754 16:30:09.212053 WORK_FSP = 0x0
755 16:30:09.212161 WL = 0x2
756 16:30:09.215428 RL = 0x2
757 16:30:09.215526 BL = 0x2
758 16:30:09.218746 RPST = 0x0
759 16:30:09.218840 RD_PRE = 0x0
760 16:30:09.221918 WR_PRE = 0x1
761 16:30:09.222009 WR_PST = 0x0
762 16:30:09.225145 DBI_WR = 0x0
763 16:30:09.225243 DBI_RD = 0x0
764 16:30:09.228332 OTF = 0x1
765 16:30:09.232208 ===================================
766 16:30:09.238330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 16:30:09.241693 nWR fixed to 40
768 16:30:09.245251 [ModeRegInit_LP4] CH0 RK0
769 16:30:09.245354 [ModeRegInit_LP4] CH0 RK1
770 16:30:09.248895 [ModeRegInit_LP4] CH1 RK0
771 16:30:09.251833 [ModeRegInit_LP4] CH1 RK1
772 16:30:09.251929 match AC timing 13
773 16:30:09.259000 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 16:30:09.261892 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 16:30:09.265614 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 16:30:09.271889 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 16:30:09.275427 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 16:30:09.275525 [EMI DOE] emi_dcm 0
779 16:30:09.282339 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 16:30:09.282427 ==
781 16:30:09.285189 Dram Type= 6, Freq= 0, CH_0, rank 0
782 16:30:09.288731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 16:30:09.288806 ==
784 16:30:09.295069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 16:30:09.298772 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 16:30:09.309395 [CA 0] Center 36 (6~67) winsize 62
787 16:30:09.312903 [CA 1] Center 36 (6~67) winsize 62
788 16:30:09.315819 [CA 2] Center 34 (4~65) winsize 62
789 16:30:09.319457 [CA 3] Center 33 (3~64) winsize 62
790 16:30:09.322373 [CA 4] Center 33 (2~64) winsize 63
791 16:30:09.326065 [CA 5] Center 32 (2~62) winsize 61
792 16:30:09.326136
793 16:30:09.329621 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 16:30:09.329716
795 16:30:09.333215 [CATrainingPosCal] consider 1 rank data
796 16:30:09.336867 u2DelayCellTimex100 = 270/100 ps
797 16:30:09.339799 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 16:30:09.343242 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 16:30:09.346823 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 16:30:09.350185 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 16:30:09.353599 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
802 16:30:09.359783 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 16:30:09.359865
804 16:30:09.363478 CA PerBit enable=1, Macro0, CA PI delay=32
805 16:30:09.363563
806 16:30:09.366583 [CBTSetCACLKResult] CA Dly = 32
807 16:30:09.366663 CS Dly: 4 (0~35)
808 16:30:09.366742 ==
809 16:30:09.370223 Dram Type= 6, Freq= 0, CH_0, rank 1
810 16:30:09.373072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 16:30:09.376617 ==
812 16:30:09.380207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 16:30:09.386821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 16:30:09.395136 [CA 0] Center 36 (6~67) winsize 62
815 16:30:09.398737 [CA 1] Center 36 (6~67) winsize 62
816 16:30:09.402250 [CA 2] Center 34 (4~65) winsize 62
817 16:30:09.405216 [CA 3] Center 33 (3~64) winsize 62
818 16:30:09.408847 [CA 4] Center 32 (2~63) winsize 62
819 16:30:09.412347 [CA 5] Center 32 (2~63) winsize 62
820 16:30:09.412453
821 16:30:09.415271 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 16:30:09.415365
823 16:30:09.418724 [CATrainingPosCal] consider 2 rank data
824 16:30:09.422205 u2DelayCellTimex100 = 270/100 ps
825 16:30:09.425092 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 16:30:09.428889 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 16:30:09.435162 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 16:30:09.438744 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 16:30:09.442459 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
830 16:30:09.445461 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 16:30:09.445566
832 16:30:09.449276 CA PerBit enable=1, Macro0, CA PI delay=32
833 16:30:09.449357
834 16:30:09.452191 [CBTSetCACLKResult] CA Dly = 32
835 16:30:09.452271 CS Dly: 5 (0~37)
836 16:30:09.452351
837 16:30:09.455819 ----->DramcWriteLeveling(PI) begin...
838 16:30:09.458665 ==
839 16:30:09.458746 Dram Type= 6, Freq= 0, CH_0, rank 0
840 16:30:09.465221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 16:30:09.465303 ==
842 16:30:09.468764 Write leveling (Byte 0): 31 => 31
843 16:30:09.472235 Write leveling (Byte 1): 29 => 29
844 16:30:09.475613 DramcWriteLeveling(PI) end<-----
845 16:30:09.475695
846 16:30:09.475775 ==
847 16:30:09.479100 Dram Type= 6, Freq= 0, CH_0, rank 0
848 16:30:09.482684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 16:30:09.482760 ==
850 16:30:09.485832 [Gating] SW mode calibration
851 16:30:09.492018 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 16:30:09.495835 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 16:30:09.502204 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 16:30:09.505707 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 16:30:09.508955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 16:30:09.513285 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:30:09.519631 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:30:09.523330 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:30:09.526315 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:30:09.532942 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:30:09.536644 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:30:09.540247 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:30:09.546737 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:30:09.549886 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:30:09.553757 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:30:09.560364 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:30:09.563249 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 16:30:09.566918 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 16:30:09.569744 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 16:30:09.576406 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 16:30:09.579948 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
872 16:30:09.583489 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 16:30:09.590057 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:30:09.593092 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:30:09.596677 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 16:30:09.603109 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 16:30:09.606420 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 16:30:09.609737 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 16:30:09.616419 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
880 16:30:09.619830 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
881 16:30:09.622974 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:30:09.629941 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 16:30:09.633181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 16:30:09.636422 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 16:30:09.643328 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 16:30:09.646169 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
887 16:30:09.649827 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
888 16:30:09.656446 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 16:30:09.660119 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:30:09.662985 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:30:09.669722 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 16:30:09.673325 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 16:30:09.676357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 16:30:09.680158 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 16:30:09.686768 0 11 8 | B1->B0 | 3131 3e3e | 0 1 | (0 0) (0 0)
896 16:30:09.689643 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 16:30:09.693379 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:30:09.700193 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:30:09.702919 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 16:30:09.706688 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 16:30:09.713118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 16:30:09.716823 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 16:30:09.720232 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 16:30:09.726351 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 16:30:09.729832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:30:09.733216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:30:09.740329 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:30:09.743258 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:30:09.746826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:30:09.750221 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:30:09.756978 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:30:09.759984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:30:09.763650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:30:09.770317 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 16:30:09.773302 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 16:30:09.776894 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 16:30:09.783455 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 16:30:09.787188 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 16:30:09.790026 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 16:30:09.793642 Total UI for P1: 0, mck2ui 16
921 16:30:09.797184 best dqsien dly found for B0: ( 0, 14, 4)
922 16:30:09.803798 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 16:30:09.803900 Total UI for P1: 0, mck2ui 16
924 16:30:09.810434 best dqsien dly found for B1: ( 0, 14, 8)
925 16:30:09.813341 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 16:30:09.816886 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 16:30:09.816984
928 16:30:09.820609 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 16:30:09.823467 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 16:30:09.826967 [Gating] SW calibration Done
931 16:30:09.827063 ==
932 16:30:09.829867 Dram Type= 6, Freq= 0, CH_0, rank 0
933 16:30:09.833349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 16:30:09.833450 ==
935 16:30:09.836801 RX Vref Scan: 0
936 16:30:09.836896
937 16:30:09.836985 RX Vref 0 -> 0, step: 1
938 16:30:09.837070
939 16:30:09.840368 RX Delay -130 -> 252, step: 16
940 16:30:09.843427 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
941 16:30:09.849961 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 16:30:09.853679 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
943 16:30:09.856740 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
944 16:30:09.859784 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 16:30:09.863466 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 16:30:09.869798 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
947 16:30:09.873276 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
948 16:30:09.876522 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
949 16:30:09.879772 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
950 16:30:09.883273 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
951 16:30:09.889609 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
952 16:30:09.893398 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
953 16:30:09.896249 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
954 16:30:09.899769 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
955 16:30:09.903427 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
956 16:30:09.906322 ==
957 16:30:09.906415 Dram Type= 6, Freq= 0, CH_0, rank 0
958 16:30:09.912839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 16:30:09.912939 ==
960 16:30:09.913035 DQS Delay:
961 16:30:09.916504 DQS0 = 0, DQS1 = 0
962 16:30:09.916573 DQM Delay:
963 16:30:09.920019 DQM0 = 91, DQM1 = 82
964 16:30:09.920086 DQ Delay:
965 16:30:09.922916 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
966 16:30:09.926625 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
967 16:30:09.930219 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
968 16:30:09.932977 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
969 16:30:09.933055
970 16:30:09.933113
971 16:30:09.933168 ==
972 16:30:09.936638 Dram Type= 6, Freq= 0, CH_0, rank 0
973 16:30:09.940186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 16:30:09.940293 ==
975 16:30:09.940382
976 16:30:09.940466
977 16:30:09.942907 TX Vref Scan disable
978 16:30:09.946564 == TX Byte 0 ==
979 16:30:09.949485 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 16:30:09.953102 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 16:30:09.956776 == TX Byte 1 ==
982 16:30:09.959726 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 16:30:09.963343 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 16:30:09.963447 ==
985 16:30:09.967038 Dram Type= 6, Freq= 0, CH_0, rank 0
986 16:30:09.970021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 16:30:09.970116 ==
988 16:30:09.984671 TX Vref=22, minBit 4, minWin=27, winSum=444
989 16:30:09.987422 TX Vref=24, minBit 7, minWin=27, winSum=449
990 16:30:09.991123 TX Vref=26, minBit 0, minWin=28, winSum=455
991 16:30:09.994672 TX Vref=28, minBit 0, minWin=28, winSum=459
992 16:30:09.998004 TX Vref=30, minBit 0, minWin=28, winSum=458
993 16:30:10.001394 TX Vref=32, minBit 8, minWin=28, winSum=458
994 16:30:10.008303 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
995 16:30:10.008410
996 16:30:10.011039 Final TX Range 1 Vref 28
997 16:30:10.011136
998 16:30:10.011225 ==
999 16:30:10.015491 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 16:30:10.017697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 16:30:10.017791 ==
1002 16:30:10.017878
1003 16:30:10.017963
1004 16:30:10.021621 TX Vref Scan disable
1005 16:30:10.024969 == TX Byte 0 ==
1006 16:30:10.027789 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 16:30:10.031307 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 16:30:10.034979 == TX Byte 1 ==
1009 16:30:10.037863 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 16:30:10.041229 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 16:30:10.041324
1012 16:30:10.044790 [DATLAT]
1013 16:30:10.044887 Freq=800, CH0 RK0
1014 16:30:10.044973
1015 16:30:10.048297 DATLAT Default: 0xa
1016 16:30:10.048397 0, 0xFFFF, sum = 0
1017 16:30:10.051316 1, 0xFFFF, sum = 0
1018 16:30:10.051413 2, 0xFFFF, sum = 0
1019 16:30:10.054889 3, 0xFFFF, sum = 0
1020 16:30:10.054992 4, 0xFFFF, sum = 0
1021 16:30:10.058310 5, 0xFFFF, sum = 0
1022 16:30:10.058411 6, 0xFFFF, sum = 0
1023 16:30:10.061348 7, 0xFFFF, sum = 0
1024 16:30:10.061442 8, 0xFFFF, sum = 0
1025 16:30:10.064745 9, 0x0, sum = 1
1026 16:30:10.064839 10, 0x0, sum = 2
1027 16:30:10.067768 11, 0x0, sum = 3
1028 16:30:10.067866 12, 0x0, sum = 4
1029 16:30:10.071450 best_step = 10
1030 16:30:10.071542
1031 16:30:10.071627 ==
1032 16:30:10.074466 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 16:30:10.078016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 16:30:10.078114 ==
1035 16:30:10.081812 RX Vref Scan: 1
1036 16:30:10.081893
1037 16:30:10.081955 Set Vref Range= 32 -> 127
1038 16:30:10.082013
1039 16:30:10.084670 RX Vref 32 -> 127, step: 1
1040 16:30:10.084742
1041 16:30:10.088301 RX Delay -95 -> 252, step: 8
1042 16:30:10.088382
1043 16:30:10.091828 Set Vref, RX VrefLevel [Byte0]: 32
1044 16:30:10.094779 [Byte1]: 32
1045 16:30:10.094887
1046 16:30:10.098340 Set Vref, RX VrefLevel [Byte0]: 33
1047 16:30:10.102046 [Byte1]: 33
1048 16:30:10.102147
1049 16:30:10.105057 Set Vref, RX VrefLevel [Byte0]: 34
1050 16:30:10.107971 [Byte1]: 34
1051 16:30:10.112376
1052 16:30:10.112486 Set Vref, RX VrefLevel [Byte0]: 35
1053 16:30:10.115253 [Byte1]: 35
1054 16:30:10.119586
1055 16:30:10.119682 Set Vref, RX VrefLevel [Byte0]: 36
1056 16:30:10.123218 [Byte1]: 36
1057 16:30:10.127319
1058 16:30:10.127415 Set Vref, RX VrefLevel [Byte0]: 37
1059 16:30:10.130660 [Byte1]: 37
1060 16:30:10.135260
1061 16:30:10.135359 Set Vref, RX VrefLevel [Byte0]: 38
1062 16:30:10.138308 [Byte1]: 38
1063 16:30:10.142462
1064 16:30:10.142565 Set Vref, RX VrefLevel [Byte0]: 39
1065 16:30:10.146057 [Byte1]: 39
1066 16:30:10.150592
1067 16:30:10.150698 Set Vref, RX VrefLevel [Byte0]: 40
1068 16:30:10.153801 [Byte1]: 40
1069 16:30:10.157655
1070 16:30:10.157760 Set Vref, RX VrefLevel [Byte0]: 41
1071 16:30:10.160802 [Byte1]: 41
1072 16:30:10.165415
1073 16:30:10.165521 Set Vref, RX VrefLevel [Byte0]: 42
1074 16:30:10.168862 [Byte1]: 42
1075 16:30:10.173149
1076 16:30:10.176066 Set Vref, RX VrefLevel [Byte0]: 43
1077 16:30:10.176164 [Byte1]: 43
1078 16:30:10.180275
1079 16:30:10.180370 Set Vref, RX VrefLevel [Byte0]: 44
1080 16:30:10.183944 [Byte1]: 44
1081 16:30:10.188439
1082 16:30:10.188545 Set Vref, RX VrefLevel [Byte0]: 45
1083 16:30:10.191289 [Byte1]: 45
1084 16:30:10.195567
1085 16:30:10.195672 Set Vref, RX VrefLevel [Byte0]: 46
1086 16:30:10.199339 [Byte1]: 46
1087 16:30:10.203735
1088 16:30:10.203817 Set Vref, RX VrefLevel [Byte0]: 47
1089 16:30:10.206624 [Byte1]: 47
1090 16:30:10.210730
1091 16:30:10.210811 Set Vref, RX VrefLevel [Byte0]: 48
1092 16:30:10.214387 [Byte1]: 48
1093 16:30:10.218777
1094 16:30:10.218860 Set Vref, RX VrefLevel [Byte0]: 49
1095 16:30:10.221627 [Byte1]: 49
1096 16:30:10.225994
1097 16:30:10.226084 Set Vref, RX VrefLevel [Byte0]: 50
1098 16:30:10.229682 [Byte1]: 50
1099 16:30:10.233901
1100 16:30:10.233981 Set Vref, RX VrefLevel [Byte0]: 51
1101 16:30:10.236960 [Byte1]: 51
1102 16:30:10.241304
1103 16:30:10.241409 Set Vref, RX VrefLevel [Byte0]: 52
1104 16:30:10.245018 [Byte1]: 52
1105 16:30:10.248622
1106 16:30:10.248731 Set Vref, RX VrefLevel [Byte0]: 53
1107 16:30:10.252064 [Byte1]: 53
1108 16:30:10.256262
1109 16:30:10.256373 Set Vref, RX VrefLevel [Byte0]: 54
1110 16:30:10.259762 [Byte1]: 54
1111 16:30:10.264119
1112 16:30:10.264226 Set Vref, RX VrefLevel [Byte0]: 55
1113 16:30:10.267362 [Byte1]: 55
1114 16:30:10.271785
1115 16:30:10.274829 Set Vref, RX VrefLevel [Byte0]: 56
1116 16:30:10.274911 [Byte1]: 56
1117 16:30:10.279623
1118 16:30:10.279700 Set Vref, RX VrefLevel [Byte0]: 57
1119 16:30:10.282340 [Byte1]: 57
1120 16:30:10.286834
1121 16:30:10.286915 Set Vref, RX VrefLevel [Byte0]: 58
1122 16:30:10.290012 [Byte1]: 58
1123 16:30:10.294412
1124 16:30:10.294516 Set Vref, RX VrefLevel [Byte0]: 59
1125 16:30:10.297711 [Byte1]: 59
1126 16:30:10.301980
1127 16:30:10.302059 Set Vref, RX VrefLevel [Byte0]: 60
1128 16:30:10.305780 [Byte1]: 60
1129 16:30:10.310072
1130 16:30:10.310150 Set Vref, RX VrefLevel [Byte0]: 61
1131 16:30:10.313044 [Byte1]: 61
1132 16:30:10.317348
1133 16:30:10.317452 Set Vref, RX VrefLevel [Byte0]: 62
1134 16:30:10.320991 [Byte1]: 62
1135 16:30:10.325140
1136 16:30:10.325219 Set Vref, RX VrefLevel [Byte0]: 63
1137 16:30:10.328086 [Byte1]: 63
1138 16:30:10.332433
1139 16:30:10.332536 Set Vref, RX VrefLevel [Byte0]: 64
1140 16:30:10.336104 [Byte1]: 64
1141 16:30:10.340444
1142 16:30:10.340542 Set Vref, RX VrefLevel [Byte0]: 65
1143 16:30:10.343474 [Byte1]: 65
1144 16:30:10.347984
1145 16:30:10.348057 Set Vref, RX VrefLevel [Byte0]: 66
1146 16:30:10.350933 [Byte1]: 66
1147 16:30:10.355261
1148 16:30:10.355362 Set Vref, RX VrefLevel [Byte0]: 67
1149 16:30:10.358970 [Byte1]: 67
1150 16:30:10.363198
1151 16:30:10.363271 Set Vref, RX VrefLevel [Byte0]: 68
1152 16:30:10.366097 [Byte1]: 68
1153 16:30:10.370394
1154 16:30:10.370466 Set Vref, RX VrefLevel [Byte0]: 69
1155 16:30:10.373731 [Byte1]: 69
1156 16:30:10.378094
1157 16:30:10.378168 Set Vref, RX VrefLevel [Byte0]: 70
1158 16:30:10.381699 [Byte1]: 70
1159 16:30:10.386022
1160 16:30:10.386092 Set Vref, RX VrefLevel [Byte0]: 71
1161 16:30:10.388805 [Byte1]: 71
1162 16:30:10.393411
1163 16:30:10.393509 Set Vref, RX VrefLevel [Byte0]: 72
1164 16:30:10.396771 [Byte1]: 72
1165 16:30:10.400720
1166 16:30:10.400792 Set Vref, RX VrefLevel [Byte0]: 73
1167 16:30:10.403997 [Byte1]: 73
1168 16:30:10.408746
1169 16:30:10.408819 Set Vref, RX VrefLevel [Byte0]: 74
1170 16:30:10.411593 [Byte1]: 74
1171 16:30:10.416453
1172 16:30:10.416558 Set Vref, RX VrefLevel [Byte0]: 75
1173 16:30:10.419364 [Byte1]: 75
1174 16:30:10.423724
1175 16:30:10.423827 Set Vref, RX VrefLevel [Byte0]: 76
1176 16:30:10.427070 [Byte1]: 76
1177 16:30:10.431394
1178 16:30:10.431465 Final RX Vref Byte 0 = 54 to rank0
1179 16:30:10.434820 Final RX Vref Byte 1 = 56 to rank0
1180 16:30:10.437927 Final RX Vref Byte 0 = 54 to rank1
1181 16:30:10.441601 Final RX Vref Byte 1 = 56 to rank1==
1182 16:30:10.444612 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 16:30:10.448390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 16:30:10.451339 ==
1185 16:30:10.451427 DQS Delay:
1186 16:30:10.451502 DQS0 = 0, DQS1 = 0
1187 16:30:10.455042 DQM Delay:
1188 16:30:10.455147 DQM0 = 91, DQM1 = 85
1189 16:30:10.457869 DQ Delay:
1190 16:30:10.457944 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1191 16:30:10.461578 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1192 16:30:10.465173 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1193 16:30:10.468191 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1194 16:30:10.471777
1195 16:30:10.471857
1196 16:30:10.478326 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1197 16:30:10.481350 CH0 RK0: MR19=606, MR18=4C42
1198 16:30:10.488305 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1199 16:30:10.488388
1200 16:30:10.492050 ----->DramcWriteLeveling(PI) begin...
1201 16:30:10.492133 ==
1202 16:30:10.494908 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 16:30:10.498325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 16:30:10.498404 ==
1205 16:30:10.502096 Write leveling (Byte 0): 33 => 33
1206 16:30:10.504894 Write leveling (Byte 1): 29 => 29
1207 16:30:10.508643 DramcWriteLeveling(PI) end<-----
1208 16:30:10.508720
1209 16:30:10.508785 ==
1210 16:30:10.511456 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 16:30:10.515150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 16:30:10.515229 ==
1213 16:30:10.518599 [Gating] SW mode calibration
1214 16:30:10.525290 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 16:30:10.532305 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 16:30:10.535197 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 16:30:10.538698 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 16:30:10.585833 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1219 16:30:10.585948 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 16:30:10.586198 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 16:30:10.586262 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 16:30:10.586319 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 16:30:10.586373 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:30:10.586425 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 16:30:10.586487 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:30:10.586541 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:30:10.586593 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:30:10.586645 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:30:10.626160 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:30:10.626458 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:30:10.626527 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:30:10.626594 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 16:30:10.626657 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 16:30:10.626710 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1235 16:30:10.626774 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 16:30:10.626833 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 16:30:10.629816 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 16:30:10.629914 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 16:30:10.636514 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 16:30:10.639866 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 16:30:10.643311 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 16:30:10.649875 0 9 8 | B1->B0 | 3030 2e2d | 1 1 | (1 1) (1 1)
1243 16:30:10.653597 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 16:30:10.656466 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 16:30:10.663146 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 16:30:10.666758 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 16:30:10.670102 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 16:30:10.676821 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 16:30:10.679887 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1250 16:30:10.683744 0 10 8 | B1->B0 | 2727 2525 | 0 0 | (1 0) (1 0)
1251 16:30:10.690080 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 16:30:10.693790 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 16:30:10.696605 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 16:30:10.700040 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 16:30:10.706701 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 16:30:10.710177 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 16:30:10.713863 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1258 16:30:10.720650 0 11 8 | B1->B0 | 3d3d 3737 | 1 1 | (0 0) (0 0)
1259 16:30:10.723499 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 16:30:10.727172 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 16:30:10.733637 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 16:30:10.737409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 16:30:10.740197 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 16:30:10.747214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 16:30:10.750694 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 16:30:10.753382 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1267 16:30:10.760512 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 16:30:10.763281 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 16:30:10.767040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 16:30:10.773505 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 16:30:10.777226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 16:30:10.780179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 16:30:10.787100 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 16:30:10.790024 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 16:30:10.793732 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 16:30:10.796633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 16:30:10.803850 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 16:30:10.806828 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 16:30:10.810380 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 16:30:10.817063 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 16:30:10.820137 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 16:30:10.823297 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 16:30:10.826840 Total UI for P1: 0, mck2ui 16
1284 16:30:10.829997 best dqsien dly found for B0: ( 0, 14, 6)
1285 16:30:10.837159 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1286 16:30:10.837267 Total UI for P1: 0, mck2ui 16
1287 16:30:10.843493 best dqsien dly found for B1: ( 0, 14, 8)
1288 16:30:10.846942 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1289 16:30:10.850602 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 16:30:10.850682
1291 16:30:10.853428 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 16:30:10.856657 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 16:30:10.860325 [Gating] SW calibration Done
1294 16:30:10.860438 ==
1295 16:30:10.863875 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 16:30:10.866802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 16:30:10.866901 ==
1298 16:30:10.870510 RX Vref Scan: 0
1299 16:30:10.870592
1300 16:30:10.870653 RX Vref 0 -> 0, step: 1
1301 16:30:10.870709
1302 16:30:10.873377 RX Delay -130 -> 252, step: 16
1303 16:30:10.877103 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1304 16:30:10.883235 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1305 16:30:10.886827 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1306 16:30:10.890395 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1307 16:30:10.893244 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1308 16:30:10.896874 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1309 16:30:10.903422 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1310 16:30:10.906967 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1311 16:30:10.909915 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1312 16:30:10.913443 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1313 16:30:10.917326 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1314 16:30:10.923258 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1315 16:30:10.927075 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1316 16:30:10.929923 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1317 16:30:10.933402 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1318 16:30:10.936821 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1319 16:30:10.936902 ==
1320 16:30:10.940158 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 16:30:10.947238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 16:30:10.947321 ==
1323 16:30:10.947390 DQS Delay:
1324 16:30:10.950507 DQS0 = 0, DQS1 = 0
1325 16:30:10.950584 DQM Delay:
1326 16:30:10.950648 DQM0 = 93, DQM1 = 82
1327 16:30:10.953773 DQ Delay:
1328 16:30:10.957020 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1329 16:30:10.960181 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1330 16:30:10.963726 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1331 16:30:10.966589 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1332 16:30:10.966661
1333 16:30:10.966737
1334 16:30:10.966798 ==
1335 16:30:10.970010 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 16:30:10.973349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 16:30:10.973422 ==
1338 16:30:10.973512
1339 16:30:10.973602
1340 16:30:10.976778 TX Vref Scan disable
1341 16:30:10.980174 == TX Byte 0 ==
1342 16:30:10.983488 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1343 16:30:10.987116 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1344 16:30:10.990007 == TX Byte 1 ==
1345 16:30:10.993614 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1346 16:30:10.997067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1347 16:30:10.997165 ==
1348 16:30:11.000588 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 16:30:11.003620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 16:30:11.003691 ==
1351 16:30:11.018378 TX Vref=22, minBit 1, minWin=28, winSum=449
1352 16:30:11.021913 TX Vref=24, minBit 9, minWin=27, winSum=451
1353 16:30:11.024841 TX Vref=26, minBit 11, minWin=27, winSum=454
1354 16:30:11.028558 TX Vref=28, minBit 7, minWin=28, winSum=458
1355 16:30:11.031577 TX Vref=30, minBit 2, minWin=28, winSum=457
1356 16:30:11.038236 TX Vref=32, minBit 4, minWin=28, winSum=457
1357 16:30:11.041902 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 28
1358 16:30:11.041982
1359 16:30:11.044705 Final TX Range 1 Vref 28
1360 16:30:11.044812
1361 16:30:11.044898 ==
1362 16:30:11.048175 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 16:30:11.051768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 16:30:11.051878 ==
1365 16:30:11.055174
1366 16:30:11.055253
1367 16:30:11.055315 TX Vref Scan disable
1368 16:30:11.058776 == TX Byte 0 ==
1369 16:30:11.061762 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1370 16:30:11.065462 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1371 16:30:11.068438 == TX Byte 1 ==
1372 16:30:11.072041 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1373 16:30:11.075332 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1374 16:30:11.078718
1375 16:30:11.078790 [DATLAT]
1376 16:30:11.078873 Freq=800, CH0 RK1
1377 16:30:11.078933
1378 16:30:11.081585 DATLAT Default: 0xa
1379 16:30:11.081680 0, 0xFFFF, sum = 0
1380 16:30:11.084832 1, 0xFFFF, sum = 0
1381 16:30:11.084911 2, 0xFFFF, sum = 0
1382 16:30:11.088172 3, 0xFFFF, sum = 0
1383 16:30:11.088272 4, 0xFFFF, sum = 0
1384 16:30:11.092020 5, 0xFFFF, sum = 0
1385 16:30:11.092099 6, 0xFFFF, sum = 0
1386 16:30:11.095087 7, 0xFFFF, sum = 0
1387 16:30:11.098158 8, 0xFFFF, sum = 0
1388 16:30:11.098233 9, 0x0, sum = 1
1389 16:30:11.098296 10, 0x0, sum = 2
1390 16:30:11.101664 11, 0x0, sum = 3
1391 16:30:11.101736 12, 0x0, sum = 4
1392 16:30:11.105111 best_step = 10
1393 16:30:11.105181
1394 16:30:11.105240 ==
1395 16:30:11.108580 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 16:30:11.111937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 16:30:11.112009 ==
1398 16:30:11.114837 RX Vref Scan: 0
1399 16:30:11.114913
1400 16:30:11.114971 RX Vref 0 -> 0, step: 1
1401 16:30:11.115024
1402 16:30:11.118636 RX Delay -79 -> 252, step: 8
1403 16:30:11.124983 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1404 16:30:11.128682 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1405 16:30:11.131567 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1406 16:30:11.135343 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1407 16:30:11.138319 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1408 16:30:11.144977 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1409 16:30:11.148754 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1410 16:30:11.151641 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1411 16:30:11.155291 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1412 16:30:11.158752 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1413 16:30:11.165099 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1414 16:30:11.168594 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1415 16:30:11.171550 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1416 16:30:11.175175 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1417 16:30:11.178915 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1418 16:30:11.185317 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1419 16:30:11.185394 ==
1420 16:30:11.188901 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 16:30:11.191841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 16:30:11.191919 ==
1423 16:30:11.191984 DQS Delay:
1424 16:30:11.195566 DQS0 = 0, DQS1 = 0
1425 16:30:11.195668 DQM Delay:
1426 16:30:11.198597 DQM0 = 92, DQM1 = 83
1427 16:30:11.198668 DQ Delay:
1428 16:30:11.202102 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1429 16:30:11.205647 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1430 16:30:11.208555 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1431 16:30:11.211950 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1432 16:30:11.212047
1433 16:30:11.212149
1434 16:30:11.218706 [DQSOSCAuto] RK1, (LSB)MR18= 0x4313, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1435 16:30:11.222049 CH0 RK1: MR19=606, MR18=4313
1436 16:30:11.229038 CH0_RK1: MR19=0x606, MR18=0x4313, DQSOSC=393, MR23=63, INC=95, DEC=63
1437 16:30:11.232229 [RxdqsGatingPostProcess] freq 800
1438 16:30:11.238905 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 16:30:11.239010 Pre-setting of DQS Precalculation
1440 16:30:11.245756 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 16:30:11.245835 ==
1442 16:30:11.248895 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 16:30:11.252569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 16:30:11.252682 ==
1445 16:30:11.259145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 16:30:11.265141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 16:30:11.273728 [CA 0] Center 36 (6~67) winsize 62
1448 16:30:11.277000 [CA 1] Center 36 (6~67) winsize 62
1449 16:30:11.280586 [CA 2] Center 35 (5~66) winsize 62
1450 16:30:11.283604 [CA 3] Center 34 (4~65) winsize 62
1451 16:30:11.287215 [CA 4] Center 35 (5~65) winsize 61
1452 16:30:11.290600 [CA 5] Center 34 (4~65) winsize 62
1453 16:30:11.290704
1454 16:30:11.293365 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 16:30:11.293447
1456 16:30:11.297031 [CATrainingPosCal] consider 1 rank data
1457 16:30:11.300722 u2DelayCellTimex100 = 270/100 ps
1458 16:30:11.303624 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 16:30:11.307021 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 16:30:11.310697 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1461 16:30:11.317242 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 16:30:11.320893 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 16:30:11.323785 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 16:30:11.323895
1465 16:30:11.327582 CA PerBit enable=1, Macro0, CA PI delay=34
1466 16:30:11.327681
1467 16:30:11.331077 [CBTSetCACLKResult] CA Dly = 34
1468 16:30:11.331178 CS Dly: 5 (0~36)
1469 16:30:11.331273 ==
1470 16:30:11.333912 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 16:30:11.341090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 16:30:11.341197 ==
1473 16:30:11.344082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 16:30:11.350403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 16:30:11.359501 [CA 0] Center 37 (6~68) winsize 63
1476 16:30:11.363297 [CA 1] Center 37 (6~68) winsize 63
1477 16:30:11.366479 [CA 2] Center 35 (4~66) winsize 63
1478 16:30:11.369593 [CA 3] Center 34 (4~65) winsize 62
1479 16:30:11.373188 [CA 4] Center 35 (5~65) winsize 61
1480 16:30:11.376418 [CA 5] Center 34 (4~65) winsize 62
1481 16:30:11.376529
1482 16:30:11.379728 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 16:30:11.379830
1484 16:30:11.383176 [CATrainingPosCal] consider 2 rank data
1485 16:30:11.386636 u2DelayCellTimex100 = 270/100 ps
1486 16:30:11.390035 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 16:30:11.393029 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1488 16:30:11.399876 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1489 16:30:11.402766 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 16:30:11.406374 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1491 16:30:11.410115 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 16:30:11.410190
1493 16:30:11.412860 CA PerBit enable=1, Macro0, CA PI delay=34
1494 16:30:11.412937
1495 16:30:11.416653 [CBTSetCACLKResult] CA Dly = 34
1496 16:30:11.416723 CS Dly: 6 (0~38)
1497 16:30:11.416781
1498 16:30:11.419504 ----->DramcWriteLeveling(PI) begin...
1499 16:30:11.423255 ==
1500 16:30:11.423355 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 16:30:11.429824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 16:30:11.429925 ==
1503 16:30:11.433562 Write leveling (Byte 0): 27 => 27
1504 16:30:11.436475 Write leveling (Byte 1): 26 => 26
1505 16:30:11.439469 DramcWriteLeveling(PI) end<-----
1506 16:30:11.439567
1507 16:30:11.439661 ==
1508 16:30:11.442908 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 16:30:11.446726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 16:30:11.446798 ==
1511 16:30:11.449430 [Gating] SW mode calibration
1512 16:30:11.455993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 16:30:11.459679 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 16:30:11.466431 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1515 16:30:11.470007 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1516 16:30:11.473618 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 16:30:11.479910 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 16:30:11.483345 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 16:30:11.486793 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 16:30:11.493183 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 16:30:11.496372 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:30:11.499640 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:30:11.506704 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 16:30:11.509678 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:30:11.513139 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:30:11.516388 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:30:11.523071 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:30:11.526938 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:30:11.530356 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 16:30:11.537118 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 16:30:11.539953 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1532 16:30:11.543434 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 16:30:11.549894 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 16:30:11.553503 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 16:30:11.557093 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 16:30:11.563739 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 16:30:11.566770 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 16:30:11.570523 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 16:30:11.577021 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (1 1) (1 1)
1540 16:30:11.580019 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1541 16:30:11.583697 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 16:30:11.587413 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 16:30:11.593910 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 16:30:11.596763 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 16:30:11.600340 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 16:30:11.606744 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 16:30:11.610676 0 10 4 | B1->B0 | 3333 2e2e | 0 1 | (1 1) (0 0)
1548 16:30:11.613491 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1549 16:30:11.620872 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 16:30:11.623507 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 16:30:11.627000 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 16:30:11.633767 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 16:30:11.637336 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 16:30:11.640457 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1555 16:30:11.647310 0 11 4 | B1->B0 | 2626 3b3b | 0 1 | (1 1) (0 0)
1556 16:30:11.650325 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1557 16:30:11.653740 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 16:30:11.660833 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 16:30:11.664224 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 16:30:11.667313 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 16:30:11.670429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 16:30:11.676961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 16:30:11.680566 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1564 16:30:11.684119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 16:30:11.690368 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 16:30:11.693964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 16:30:11.697697 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 16:30:11.704169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 16:30:11.707793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 16:30:11.710802 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 16:30:11.717439 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 16:30:11.720422 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 16:30:11.724133 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 16:30:11.730753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 16:30:11.734408 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 16:30:11.737371 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 16:30:11.741036 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 16:30:11.747652 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 16:30:11.750570 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1580 16:30:11.753953 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 16:30:11.757233 Total UI for P1: 0, mck2ui 16
1582 16:30:11.760741 best dqsien dly found for B0: ( 0, 14, 6)
1583 16:30:11.764228 Total UI for P1: 0, mck2ui 16
1584 16:30:11.767766 best dqsien dly found for B1: ( 0, 14, 4)
1585 16:30:11.771226 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1586 16:30:11.773996 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1587 16:30:11.774067
1588 16:30:11.780753 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1589 16:30:11.784102 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1590 16:30:11.784182 [Gating] SW calibration Done
1591 16:30:11.787834 ==
1592 16:30:11.787913 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 16:30:11.794391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 16:30:11.794475 ==
1595 16:30:11.794536 RX Vref Scan: 0
1596 16:30:11.794592
1597 16:30:11.797842 RX Vref 0 -> 0, step: 1
1598 16:30:11.797921
1599 16:30:11.801077 RX Delay -130 -> 252, step: 16
1600 16:30:11.804243 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 16:30:11.807945 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1602 16:30:11.811119 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1603 16:30:11.817403 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1604 16:30:11.821251 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1605 16:30:11.824132 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1606 16:30:11.827757 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1607 16:30:11.831399 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1608 16:30:11.838053 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1609 16:30:11.840958 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1610 16:30:11.844532 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1611 16:30:11.848218 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1612 16:30:11.851154 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1613 16:30:11.857621 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1614 16:30:11.861243 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1615 16:30:11.864662 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1616 16:30:11.864767 ==
1617 16:30:11.867933 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 16:30:11.871417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 16:30:11.871490 ==
1620 16:30:11.874222 DQS Delay:
1621 16:30:11.874297 DQS0 = 0, DQS1 = 0
1622 16:30:11.877905 DQM Delay:
1623 16:30:11.877980 DQM0 = 93, DQM1 = 89
1624 16:30:11.878039 DQ Delay:
1625 16:30:11.880838 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1626 16:30:11.884526 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1627 16:30:11.887492 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1628 16:30:11.891039 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1629 16:30:11.891117
1630 16:30:11.891178
1631 16:30:11.894747 ==
1632 16:30:11.897537 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 16:30:11.901166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 16:30:11.901246 ==
1635 16:30:11.901306
1636 16:30:11.901361
1637 16:30:11.904669 TX Vref Scan disable
1638 16:30:11.904772 == TX Byte 0 ==
1639 16:30:11.908127 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1640 16:30:11.914708 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1641 16:30:11.914813 == TX Byte 1 ==
1642 16:30:11.918026 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1643 16:30:11.924243 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1644 16:30:11.924348 ==
1645 16:30:11.928037 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 16:30:11.930948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 16:30:11.931051 ==
1648 16:30:11.944519 TX Vref=22, minBit 1, minWin=26, winSum=435
1649 16:30:11.947421 TX Vref=24, minBit 3, minWin=26, winSum=438
1650 16:30:11.951117 TX Vref=26, minBit 2, minWin=27, winSum=447
1651 16:30:11.954698 TX Vref=28, minBit 1, minWin=27, winSum=448
1652 16:30:11.957648 TX Vref=30, minBit 0, minWin=27, winSum=449
1653 16:30:11.961294 TX Vref=32, minBit 2, minWin=26, winSum=440
1654 16:30:11.967246 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1655 16:30:11.967351
1656 16:30:11.970830 Final TX Range 1 Vref 30
1657 16:30:11.970930
1658 16:30:11.971015 ==
1659 16:30:11.974292 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 16:30:11.977753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 16:30:11.977828 ==
1662 16:30:11.977887
1663 16:30:11.977941
1664 16:30:11.981102 TX Vref Scan disable
1665 16:30:11.984619 == TX Byte 0 ==
1666 16:30:11.988025 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1667 16:30:11.990717 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1668 16:30:11.994424 == TX Byte 1 ==
1669 16:30:11.998077 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1670 16:30:12.000976 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1671 16:30:12.001082
1672 16:30:12.004570 [DATLAT]
1673 16:30:12.004667 Freq=800, CH1 RK0
1674 16:30:12.004753
1675 16:30:12.007566 DATLAT Default: 0xa
1676 16:30:12.007635 0, 0xFFFF, sum = 0
1677 16:30:12.011196 1, 0xFFFF, sum = 0
1678 16:30:12.011275 2, 0xFFFF, sum = 0
1679 16:30:12.014272 3, 0xFFFF, sum = 0
1680 16:30:12.014344 4, 0xFFFF, sum = 0
1681 16:30:12.017833 5, 0xFFFF, sum = 0
1682 16:30:12.017912 6, 0xFFFF, sum = 0
1683 16:30:12.020716 7, 0xFFFF, sum = 0
1684 16:30:12.020796 8, 0xFFFF, sum = 0
1685 16:30:12.024423 9, 0x0, sum = 1
1686 16:30:12.024496 10, 0x0, sum = 2
1687 16:30:12.028046 11, 0x0, sum = 3
1688 16:30:12.028118 12, 0x0, sum = 4
1689 16:30:12.031001 best_step = 10
1690 16:30:12.031068
1691 16:30:12.031124 ==
1692 16:30:12.034651 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 16:30:12.037527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 16:30:12.037617 ==
1695 16:30:12.041214 RX Vref Scan: 1
1696 16:30:12.041315
1697 16:30:12.041395 Set Vref Range= 32 -> 127
1698 16:30:12.041489
1699 16:30:12.044195 RX Vref 32 -> 127, step: 1
1700 16:30:12.044296
1701 16:30:12.048089 RX Delay -79 -> 252, step: 8
1702 16:30:12.048186
1703 16:30:12.051260 Set Vref, RX VrefLevel [Byte0]: 32
1704 16:30:12.054583 [Byte1]: 32
1705 16:30:12.054685
1706 16:30:12.057878 Set Vref, RX VrefLevel [Byte0]: 33
1707 16:30:12.061055 [Byte1]: 33
1708 16:30:12.064244
1709 16:30:12.064335 Set Vref, RX VrefLevel [Byte0]: 34
1710 16:30:12.067866 [Byte1]: 34
1711 16:30:12.071872
1712 16:30:12.071949 Set Vref, RX VrefLevel [Byte0]: 35
1713 16:30:12.074981 [Byte1]: 35
1714 16:30:12.079409
1715 16:30:12.079508 Set Vref, RX VrefLevel [Byte0]: 36
1716 16:30:12.082932 [Byte1]: 36
1717 16:30:12.087065
1718 16:30:12.087176 Set Vref, RX VrefLevel [Byte0]: 37
1719 16:30:12.090064 [Byte1]: 37
1720 16:30:12.094874
1721 16:30:12.094952 Set Vref, RX VrefLevel [Byte0]: 38
1722 16:30:12.098110 [Byte1]: 38
1723 16:30:12.102008
1724 16:30:12.102106 Set Vref, RX VrefLevel [Byte0]: 39
1725 16:30:12.105178 [Byte1]: 39
1726 16:30:12.109897
1727 16:30:12.110005 Set Vref, RX VrefLevel [Byte0]: 40
1728 16:30:12.112834 [Byte1]: 40
1729 16:30:12.117203
1730 16:30:12.117301 Set Vref, RX VrefLevel [Byte0]: 41
1731 16:30:12.120864 [Byte1]: 41
1732 16:30:12.124490
1733 16:30:12.124588 Set Vref, RX VrefLevel [Byte0]: 42
1734 16:30:12.128186 [Byte1]: 42
1735 16:30:12.132446
1736 16:30:12.132548 Set Vref, RX VrefLevel [Byte0]: 43
1737 16:30:12.135419 [Byte1]: 43
1738 16:30:12.140018
1739 16:30:12.140100 Set Vref, RX VrefLevel [Byte0]: 44
1740 16:30:12.143010 [Byte1]: 44
1741 16:30:12.147457
1742 16:30:12.147552 Set Vref, RX VrefLevel [Byte0]: 45
1743 16:30:12.150515 [Byte1]: 45
1744 16:30:12.154729
1745 16:30:12.154831 Set Vref, RX VrefLevel [Byte0]: 46
1746 16:30:12.158496 [Byte1]: 46
1747 16:30:12.162837
1748 16:30:12.162915 Set Vref, RX VrefLevel [Byte0]: 47
1749 16:30:12.165735 [Byte1]: 47
1750 16:30:12.169952
1751 16:30:12.170031 Set Vref, RX VrefLevel [Byte0]: 48
1752 16:30:12.173464 [Byte1]: 48
1753 16:30:12.177594
1754 16:30:12.177672 Set Vref, RX VrefLevel [Byte0]: 49
1755 16:30:12.180825 [Byte1]: 49
1756 16:30:12.185270
1757 16:30:12.185347 Set Vref, RX VrefLevel [Byte0]: 50
1758 16:30:12.188619 [Byte1]: 50
1759 16:30:12.192340
1760 16:30:12.192419 Set Vref, RX VrefLevel [Byte0]: 51
1761 16:30:12.196190 [Byte1]: 51
1762 16:30:12.200034
1763 16:30:12.200156 Set Vref, RX VrefLevel [Byte0]: 52
1764 16:30:12.203691 [Byte1]: 52
1765 16:30:12.207955
1766 16:30:12.208067 Set Vref, RX VrefLevel [Byte0]: 53
1767 16:30:12.210819 [Byte1]: 53
1768 16:30:12.215179
1769 16:30:12.215255 Set Vref, RX VrefLevel [Byte0]: 54
1770 16:30:12.218528 [Byte1]: 54
1771 16:30:12.222664
1772 16:30:12.222773 Set Vref, RX VrefLevel [Byte0]: 55
1773 16:30:12.226270 [Byte1]: 55
1774 16:30:12.230553
1775 16:30:12.230665 Set Vref, RX VrefLevel [Byte0]: 56
1776 16:30:12.233329 [Byte1]: 56
1777 16:30:12.237748
1778 16:30:12.237863 Set Vref, RX VrefLevel [Byte0]: 57
1779 16:30:12.241404 [Byte1]: 57
1780 16:30:12.245775
1781 16:30:12.245884 Set Vref, RX VrefLevel [Byte0]: 58
1782 16:30:12.248722 [Byte1]: 58
1783 16:30:12.252895
1784 16:30:12.253008 Set Vref, RX VrefLevel [Byte0]: 59
1785 16:30:12.256532 [Byte1]: 59
1786 16:30:12.260630
1787 16:30:12.260742 Set Vref, RX VrefLevel [Byte0]: 60
1788 16:30:12.263665 [Byte1]: 60
1789 16:30:12.268130
1790 16:30:12.268242 Set Vref, RX VrefLevel [Byte0]: 61
1791 16:30:12.271693 [Byte1]: 61
1792 16:30:12.275436
1793 16:30:12.275546 Set Vref, RX VrefLevel [Byte0]: 62
1794 16:30:12.279145 [Byte1]: 62
1795 16:30:12.283510
1796 16:30:12.283620 Set Vref, RX VrefLevel [Byte0]: 63
1797 16:30:12.286486 [Byte1]: 63
1798 16:30:12.290808
1799 16:30:12.290918 Set Vref, RX VrefLevel [Byte0]: 64
1800 16:30:12.293771 [Byte1]: 64
1801 16:30:12.298153
1802 16:30:12.298269 Set Vref, RX VrefLevel [Byte0]: 65
1803 16:30:12.301653 [Byte1]: 65
1804 16:30:12.305751
1805 16:30:12.305863 Set Vref, RX VrefLevel [Byte0]: 66
1806 16:30:12.309062 [Byte1]: 66
1807 16:30:12.313464
1808 16:30:12.313572 Set Vref, RX VrefLevel [Byte0]: 67
1809 16:30:12.316758 [Byte1]: 67
1810 16:30:12.321040
1811 16:30:12.321119 Set Vref, RX VrefLevel [Byte0]: 68
1812 16:30:12.324075 [Byte1]: 68
1813 16:30:12.328748
1814 16:30:12.328822 Set Vref, RX VrefLevel [Byte0]: 69
1815 16:30:12.331603 [Byte1]: 69
1816 16:30:12.336197
1817 16:30:12.336273 Set Vref, RX VrefLevel [Byte0]: 70
1818 16:30:12.339422 [Byte1]: 70
1819 16:30:12.343319
1820 16:30:12.343434 Set Vref, RX VrefLevel [Byte0]: 71
1821 16:30:12.347109 [Byte1]: 71
1822 16:30:12.350796
1823 16:30:12.350906 Set Vref, RX VrefLevel [Byte0]: 72
1824 16:30:12.354305 [Byte1]: 72
1825 16:30:12.358541
1826 16:30:12.358658 Set Vref, RX VrefLevel [Byte0]: 73
1827 16:30:12.362120 [Byte1]: 73
1828 16:30:12.366493
1829 16:30:12.366610 Set Vref, RX VrefLevel [Byte0]: 74
1830 16:30:12.369426 [Byte1]: 74
1831 16:30:12.373787
1832 16:30:12.373893 Set Vref, RX VrefLevel [Byte0]: 75
1833 16:30:12.377285 [Byte1]: 75
1834 16:30:12.381613
1835 16:30:12.381727 Final RX Vref Byte 0 = 57 to rank0
1836 16:30:12.384620 Final RX Vref Byte 1 = 57 to rank0
1837 16:30:12.388243 Final RX Vref Byte 0 = 57 to rank1
1838 16:30:12.391083 Final RX Vref Byte 1 = 57 to rank1==
1839 16:30:12.394596 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 16:30:12.398168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 16:30:12.401032 ==
1842 16:30:12.401146 DQS Delay:
1843 16:30:12.401249 DQS0 = 0, DQS1 = 0
1844 16:30:12.404714 DQM Delay:
1845 16:30:12.404826 DQM0 = 95, DQM1 = 89
1846 16:30:12.408319 DQ Delay:
1847 16:30:12.411236 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1848 16:30:12.414826 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1849 16:30:12.417707 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1850 16:30:12.421483 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1851 16:30:12.421603
1852 16:30:12.421703
1853 16:30:12.428071 [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1854 16:30:12.431010 CH1 RK0: MR19=606, MR18=304C
1855 16:30:12.438239 CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64
1856 16:30:12.438363
1857 16:30:12.441016 ----->DramcWriteLeveling(PI) begin...
1858 16:30:12.441136 ==
1859 16:30:12.444532 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 16:30:12.447834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 16:30:12.447945 ==
1862 16:30:12.451197 Write leveling (Byte 0): 25 => 25
1863 16:30:12.454981 Write leveling (Byte 1): 28 => 28
1864 16:30:12.457921 DramcWriteLeveling(PI) end<-----
1865 16:30:12.458034
1866 16:30:12.458131 ==
1867 16:30:12.461050 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 16:30:12.464740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 16:30:12.464854 ==
1870 16:30:12.467968 [Gating] SW mode calibration
1871 16:30:12.474073 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 16:30:12.481097 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 16:30:12.484164 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 16:30:12.487988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1875 16:30:12.494470 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 16:30:12.498007 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 16:30:12.500818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 16:30:12.507467 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 16:30:12.511140 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 16:30:12.514079 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 16:30:12.521155 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:30:12.524082 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:30:12.527756 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:30:12.534282 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:30:12.537976 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:30:12.541058 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:30:12.547662 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 16:30:12.551370 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 16:30:12.554385 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1890 16:30:12.560928 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1891 16:30:12.564467 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1892 16:30:12.568140 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 16:30:12.570933 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 16:30:12.577458 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 16:30:12.580959 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 16:30:12.584296 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 16:30:12.591159 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 16:30:12.594357 0 9 4 | B1->B0 | 2c2c 2323 | 0 1 | (0 0) (1 1)
1899 16:30:12.597712 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1900 16:30:12.604680 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 16:30:12.607647 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 16:30:12.611115 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 16:30:12.617567 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 16:30:12.621210 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 16:30:12.624905 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1906 16:30:12.631359 0 10 4 | B1->B0 | 2b2b 3030 | 1 1 | (1 0) (1 0)
1907 16:30:12.634363 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1908 16:30:12.638107 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 16:30:12.644475 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 16:30:12.647969 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 16:30:12.651491 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 16:30:12.654457 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 16:30:12.661135 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1914 16:30:12.664641 0 11 4 | B1->B0 | 3d3d 2b2b | 0 0 | (0 0) (0 0)
1915 16:30:12.668212 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 16:30:12.674897 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 16:30:12.677846 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 16:30:12.681381 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 16:30:12.688303 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 16:30:12.691520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 16:30:12.694767 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 16:30:12.701717 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1923 16:30:12.704632 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 16:30:12.708200 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 16:30:12.714897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 16:30:12.718412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 16:30:12.721168 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 16:30:12.727845 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 16:30:12.731188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 16:30:12.734603 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 16:30:12.738064 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 16:30:12.745029 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 16:30:12.747984 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 16:30:12.751759 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 16:30:12.758446 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 16:30:12.761411 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 16:30:12.765126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 16:30:12.771656 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1939 16:30:12.775349 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 16:30:12.778241 Total UI for P1: 0, mck2ui 16
1941 16:30:12.781370 best dqsien dly found for B0: ( 0, 14, 4)
1942 16:30:12.785095 Total UI for P1: 0, mck2ui 16
1943 16:30:12.788149 best dqsien dly found for B1: ( 0, 14, 4)
1944 16:30:12.791756 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1945 16:30:12.795371 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1946 16:30:12.795492
1947 16:30:12.798190 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1948 16:30:12.801609 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1949 16:30:12.804934 [Gating] SW calibration Done
1950 16:30:12.805046 ==
1951 16:30:12.808197 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 16:30:12.811939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 16:30:12.812054 ==
1954 16:30:12.814946 RX Vref Scan: 0
1955 16:30:12.815052
1956 16:30:12.818794 RX Vref 0 -> 0, step: 1
1957 16:30:12.818905
1958 16:30:12.818996 RX Delay -130 -> 252, step: 16
1959 16:30:12.824801 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1960 16:30:12.828246 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1961 16:30:12.831926 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1962 16:30:12.834784 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1963 16:30:12.838254 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1964 16:30:12.845210 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1965 16:30:12.848461 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1966 16:30:12.851761 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1967 16:30:12.854801 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1968 16:30:12.858484 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1969 16:30:12.865361 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1970 16:30:12.868660 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1971 16:30:12.871651 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1972 16:30:12.875132 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1973 16:30:12.878129 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1974 16:30:12.884818 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1975 16:30:12.884934 ==
1976 16:30:12.888598 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 16:30:12.891547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 16:30:12.891656 ==
1979 16:30:12.891751 DQS Delay:
1980 16:30:12.895300 DQS0 = 0, DQS1 = 0
1981 16:30:12.895409 DQM Delay:
1982 16:30:12.898217 DQM0 = 92, DQM1 = 87
1983 16:30:12.898330 DQ Delay:
1984 16:30:12.901959 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1985 16:30:12.904959 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1986 16:30:12.908521 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1987 16:30:12.912312 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1988 16:30:12.912472
1989 16:30:12.912570
1990 16:30:12.912661 ==
1991 16:30:12.915163 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 16:30:12.918608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 16:30:12.918752 ==
1994 16:30:12.918849
1995 16:30:12.922152
1996 16:30:12.922266 TX Vref Scan disable
1997 16:30:12.924917 == TX Byte 0 ==
1998 16:30:12.928442 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1999 16:30:12.931736 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2000 16:30:12.935367 == TX Byte 1 ==
2001 16:30:12.938841 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2002 16:30:12.941852 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2003 16:30:12.941939 ==
2004 16:30:12.944997 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 16:30:12.951480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 16:30:12.951565 ==
2007 16:30:12.963951 TX Vref=22, minBit 1, minWin=26, winSum=440
2008 16:30:12.967234 TX Vref=24, minBit 0, minWin=27, winSum=443
2009 16:30:12.970633 TX Vref=26, minBit 0, minWin=27, winSum=450
2010 16:30:12.973964 TX Vref=28, minBit 2, minWin=27, winSum=449
2011 16:30:12.976753 TX Vref=30, minBit 0, minWin=27, winSum=452
2012 16:30:12.980139 TX Vref=32, minBit 0, minWin=27, winSum=448
2013 16:30:12.987020 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 30
2014 16:30:12.987129
2015 16:30:12.990753 Final TX Range 1 Vref 30
2016 16:30:12.990854
2017 16:30:12.990940 ==
2018 16:30:12.993604 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 16:30:12.996802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 16:30:12.996906 ==
2021 16:30:12.996993
2022 16:30:13.000459
2023 16:30:13.000563 TX Vref Scan disable
2024 16:30:13.003351 == TX Byte 0 ==
2025 16:30:13.006963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2026 16:30:13.010596 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2027 16:30:13.013628 == TX Byte 1 ==
2028 16:30:13.017224 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2029 16:30:13.020108 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2030 16:30:13.023835
2031 16:30:13.023942 [DATLAT]
2032 16:30:13.024029 Freq=800, CH1 RK1
2033 16:30:13.024111
2034 16:30:13.026771 DATLAT Default: 0xa
2035 16:30:13.026877 0, 0xFFFF, sum = 0
2036 16:30:13.030468 1, 0xFFFF, sum = 0
2037 16:30:13.030547 2, 0xFFFF, sum = 0
2038 16:30:13.034192 3, 0xFFFF, sum = 0
2039 16:30:13.034273 4, 0xFFFF, sum = 0
2040 16:30:13.037158 5, 0xFFFF, sum = 0
2041 16:30:13.037237 6, 0xFFFF, sum = 0
2042 16:30:13.040243 7, 0xFFFF, sum = 0
2043 16:30:13.040323 8, 0x0, sum = 1
2044 16:30:13.043840 9, 0x0, sum = 2
2045 16:30:13.043918 10, 0x0, sum = 3
2046 16:30:13.047441 11, 0x0, sum = 4
2047 16:30:13.047516 best_step = 9
2048 16:30:13.047575
2049 16:30:13.047629 ==
2050 16:30:13.050488 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 16:30:13.057053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 16:30:13.057159 ==
2053 16:30:13.057240 RX Vref Scan: 0
2054 16:30:13.057296
2055 16:30:13.060322 RX Vref 0 -> 0, step: 1
2056 16:30:13.060399
2057 16:30:13.064091 RX Delay -79 -> 252, step: 8
2058 16:30:13.066954 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2059 16:30:13.070296 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2060 16:30:13.073858 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2061 16:30:13.080666 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2062 16:30:13.083912 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2063 16:30:13.087027 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2064 16:30:13.090339 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2065 16:30:13.093472 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2066 16:30:13.096693 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2067 16:30:13.104025 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2068 16:30:13.106754 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2069 16:30:13.110312 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2070 16:30:13.114034 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2071 16:30:13.116921 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2072 16:30:13.123629 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2073 16:30:13.127138 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2074 16:30:13.127222 ==
2075 16:30:13.130173 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 16:30:13.133905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 16:30:13.133988 ==
2078 16:30:13.136833 DQS Delay:
2079 16:30:13.136911 DQS0 = 0, DQS1 = 0
2080 16:30:13.136971 DQM Delay:
2081 16:30:13.140495 DQM0 = 97, DQM1 = 91
2082 16:30:13.140573 DQ Delay:
2083 16:30:13.144072 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2084 16:30:13.146967 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2085 16:30:13.150493 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2086 16:30:13.153424 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2087 16:30:13.153527
2088 16:30:13.153604
2089 16:30:13.163852 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2090 16:30:13.163934 CH1 RK1: MR19=606, MR18=4711
2091 16:30:13.170275 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2092 16:30:13.173810 [RxdqsGatingPostProcess] freq 800
2093 16:30:13.180160 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 16:30:13.183806 Pre-setting of DQS Precalculation
2095 16:30:13.187035 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
2096 16:30:13.194072 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 16:30:13.203711 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 16:30:13.203816
2099 16:30:13.203879
2100 16:30:13.203935 [Calibration Summary] 1600 Mbps
2101 16:30:13.207303 CH 0, Rank 0
2102 16:30:13.210719 SW Impedance : PASS
2103 16:30:13.210809 DUTY Scan : NO K
2104 16:30:13.213976 ZQ Calibration : PASS
2105 16:30:13.214048 Jitter Meter : NO K
2106 16:30:13.217081 CBT Training : PASS
2107 16:30:13.220877 Write leveling : PASS
2108 16:30:13.220952 RX DQS gating : PASS
2109 16:30:13.224127 RX DQ/DQS(RDDQC) : PASS
2110 16:30:13.227461 TX DQ/DQS : PASS
2111 16:30:13.227536 RX DATLAT : PASS
2112 16:30:13.230777 RX DQ/DQS(Engine): PASS
2113 16:30:13.234252 TX OE : NO K
2114 16:30:13.234400 All Pass.
2115 16:30:13.234501
2116 16:30:13.234599 CH 0, Rank 1
2117 16:30:13.237008 SW Impedance : PASS
2118 16:30:13.240749 DUTY Scan : NO K
2119 16:30:13.240850 ZQ Calibration : PASS
2120 16:30:13.243669 Jitter Meter : NO K
2121 16:30:13.247401 CBT Training : PASS
2122 16:30:13.247537 Write leveling : PASS
2123 16:30:13.251155 RX DQS gating : PASS
2124 16:30:13.251274 RX DQ/DQS(RDDQC) : PASS
2125 16:30:13.254149 TX DQ/DQS : PASS
2126 16:30:13.257215 RX DATLAT : PASS
2127 16:30:13.257324 RX DQ/DQS(Engine): PASS
2128 16:30:13.260912 TX OE : NO K
2129 16:30:13.260993 All Pass.
2130 16:30:13.261055
2131 16:30:13.264187 CH 1, Rank 0
2132 16:30:13.264268 SW Impedance : PASS
2133 16:30:13.267307 DUTY Scan : NO K
2134 16:30:13.270248 ZQ Calibration : PASS
2135 16:30:13.270326 Jitter Meter : NO K
2136 16:30:13.273995 CBT Training : PASS
2137 16:30:13.276969 Write leveling : PASS
2138 16:30:13.277042 RX DQS gating : PASS
2139 16:30:13.280528 RX DQ/DQS(RDDQC) : PASS
2140 16:30:13.284276 TX DQ/DQS : PASS
2141 16:30:13.284349 RX DATLAT : PASS
2142 16:30:13.287082 RX DQ/DQS(Engine): PASS
2143 16:30:13.287154 TX OE : NO K
2144 16:30:13.290644 All Pass.
2145 16:30:13.290715
2146 16:30:13.290774 CH 1, Rank 1
2147 16:30:13.293601 SW Impedance : PASS
2148 16:30:13.293669 DUTY Scan : NO K
2149 16:30:13.297115 ZQ Calibration : PASS
2150 16:30:13.300379 Jitter Meter : NO K
2151 16:30:13.300462 CBT Training : PASS
2152 16:30:13.304171 Write leveling : PASS
2153 16:30:13.307089 RX DQS gating : PASS
2154 16:30:13.307188 RX DQ/DQS(RDDQC) : PASS
2155 16:30:13.310797 TX DQ/DQS : PASS
2156 16:30:13.313688 RX DATLAT : PASS
2157 16:30:13.313796 RX DQ/DQS(Engine): PASS
2158 16:30:13.317564 TX OE : NO K
2159 16:30:13.317647 All Pass.
2160 16:30:13.317709
2161 16:30:13.320733 DramC Write-DBI off
2162 16:30:13.323815 PER_BANK_REFRESH: Hybrid Mode
2163 16:30:13.323895 TX_TRACKING: ON
2164 16:30:13.327314 [GetDramInforAfterCalByMRR] Vendor 6.
2165 16:30:13.330908 [GetDramInforAfterCalByMRR] Revision 606.
2166 16:30:13.334288 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 16:30:13.337428 MR0 0x3b3b
2168 16:30:13.337532 MR8 0x5151
2169 16:30:13.340797 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 16:30:13.340883
2171 16:30:13.340944 MR0 0x3b3b
2172 16:30:13.344066 MR8 0x5151
2173 16:30:13.347240 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 16:30:13.347340
2175 16:30:13.353988 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 16:30:13.360921 [FAST_K] Save calibration result to emmc
2177 16:30:13.363835 [FAST_K] Save calibration result to emmc
2178 16:30:13.363980 dram_init: config_dvfs: 1
2179 16:30:13.367703 dramc_set_vcore_voltage set vcore to 662500
2180 16:30:13.370843 Read voltage for 1200, 2
2181 16:30:13.370927 Vio18 = 0
2182 16:30:13.374601 Vcore = 662500
2183 16:30:13.374696 Vdram = 0
2184 16:30:13.374788 Vddq = 0
2185 16:30:13.377709 Vmddr = 0
2186 16:30:13.380719 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 16:30:13.387740 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 16:30:13.387855 MEM_TYPE=3, freq_sel=15
2189 16:30:13.390687 sv_algorithm_assistance_LP4_1600
2190 16:30:13.397936 ============ PULL DRAM RESETB DOWN ============
2191 16:30:13.400845 ========== PULL DRAM RESETB DOWN end =========
2192 16:30:13.404387 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 16:30:13.408022 ===================================
2194 16:30:13.410670 LPDDR4 DRAM CONFIGURATION
2195 16:30:13.414125 ===================================
2196 16:30:13.414240 EX_ROW_EN[0] = 0x0
2197 16:30:13.417689 EX_ROW_EN[1] = 0x0
2198 16:30:13.420666 LP4Y_EN = 0x0
2199 16:30:13.420773 WORK_FSP = 0x0
2200 16:30:13.424274 WL = 0x4
2201 16:30:13.424373 RL = 0x4
2202 16:30:13.427366 BL = 0x2
2203 16:30:13.427448 RPST = 0x0
2204 16:30:13.430983 RD_PRE = 0x0
2205 16:30:13.431064 WR_PRE = 0x1
2206 16:30:13.434553 WR_PST = 0x0
2207 16:30:13.434630 DBI_WR = 0x0
2208 16:30:13.437373 DBI_RD = 0x0
2209 16:30:13.437474 OTF = 0x1
2210 16:30:13.440916 ===================================
2211 16:30:13.444291 ===================================
2212 16:30:13.447302 ANA top config
2213 16:30:13.450872 ===================================
2214 16:30:13.450958 DLL_ASYNC_EN = 0
2215 16:30:13.454372 ALL_SLAVE_EN = 0
2216 16:30:13.457141 NEW_RANK_MODE = 1
2217 16:30:13.460464 DLL_IDLE_MODE = 1
2218 16:30:13.463894 LP45_APHY_COMB_EN = 1
2219 16:30:13.463975 TX_ODT_DIS = 1
2220 16:30:13.467210 NEW_8X_MODE = 1
2221 16:30:13.471126 ===================================
2222 16:30:13.474390 ===================================
2223 16:30:13.477806 data_rate = 2400
2224 16:30:13.480692 CKR = 1
2225 16:30:13.484409 DQ_P2S_RATIO = 8
2226 16:30:13.487331 ===================================
2227 16:30:13.487403 CA_P2S_RATIO = 8
2228 16:30:13.491043 DQ_CA_OPEN = 0
2229 16:30:13.494001 DQ_SEMI_OPEN = 0
2230 16:30:13.497463 CA_SEMI_OPEN = 0
2231 16:30:13.500924 CA_FULL_RATE = 0
2232 16:30:13.503852 DQ_CKDIV4_EN = 0
2233 16:30:13.503959 CA_CKDIV4_EN = 0
2234 16:30:13.507394 CA_PREDIV_EN = 0
2235 16:30:13.511037 PH8_DLY = 17
2236 16:30:13.513936 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 16:30:13.517333 DQ_AAMCK_DIV = 4
2238 16:30:13.520875 CA_AAMCK_DIV = 4
2239 16:30:13.520988 CA_ADMCK_DIV = 4
2240 16:30:13.524522 DQ_TRACK_CA_EN = 0
2241 16:30:13.527854 CA_PICK = 1200
2242 16:30:13.530689 CA_MCKIO = 1200
2243 16:30:13.534216 MCKIO_SEMI = 0
2244 16:30:13.537865 PLL_FREQ = 2366
2245 16:30:13.540635 DQ_UI_PI_RATIO = 32
2246 16:30:13.540707 CA_UI_PI_RATIO = 0
2247 16:30:13.544355 ===================================
2248 16:30:13.547793 ===================================
2249 16:30:13.551100 memory_type:LPDDR4
2250 16:30:13.554052 GP_NUM : 10
2251 16:30:13.554130 SRAM_EN : 1
2252 16:30:13.557815 MD32_EN : 0
2253 16:30:13.560713 ===================================
2254 16:30:13.564447 [ANA_INIT] >>>>>>>>>>>>>>
2255 16:30:13.564519 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 16:30:13.570964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 16:30:13.574507 ===================================
2258 16:30:13.574593 data_rate = 2400,PCW = 0X5b00
2259 16:30:13.577344 ===================================
2260 16:30:13.580959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 16:30:13.587874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 16:30:13.594406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 16:30:13.597757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 16:30:13.600670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 16:30:13.604314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 16:30:13.608074 [ANA_INIT] flow start
2267 16:30:13.608149 [ANA_INIT] PLL >>>>>>>>
2268 16:30:13.611049 [ANA_INIT] PLL <<<<<<<<
2269 16:30:13.614741 [ANA_INIT] MIDPI >>>>>>>>
2270 16:30:13.614819 [ANA_INIT] MIDPI <<<<<<<<
2271 16:30:13.617506 [ANA_INIT] DLL >>>>>>>>
2272 16:30:13.621130 [ANA_INIT] DLL <<<<<<<<
2273 16:30:13.621209 [ANA_INIT] flow end
2274 16:30:13.627360 ============ LP4 DIFF to SE enter ============
2275 16:30:13.631046 ============ LP4 DIFF to SE exit ============
2276 16:30:13.633894 [ANA_INIT] <<<<<<<<<<<<<
2277 16:30:13.637419 [Flow] Enable top DCM control >>>>>
2278 16:30:13.640850 [Flow] Enable top DCM control <<<<<
2279 16:30:13.640963 Enable DLL master slave shuffle
2280 16:30:13.647577 ==============================================================
2281 16:30:13.651157 Gating Mode config
2282 16:30:13.654023 ==============================================================
2283 16:30:13.657474 Config description:
2284 16:30:13.667478 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 16:30:13.674569 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 16:30:13.677498 SELPH_MODE 0: By rank 1: By Phase
2287 16:30:13.684537 ==============================================================
2288 16:30:13.687404 GAT_TRACK_EN = 1
2289 16:30:13.691048 RX_GATING_MODE = 2
2290 16:30:13.694630 RX_GATING_TRACK_MODE = 2
2291 16:30:13.694711 SELPH_MODE = 1
2292 16:30:13.697422 PICG_EARLY_EN = 1
2293 16:30:13.700941 VALID_LAT_VALUE = 1
2294 16:30:13.707858 ==============================================================
2295 16:30:13.711188 Enter into Gating configuration >>>>
2296 16:30:13.714610 Exit from Gating configuration <<<<
2297 16:30:13.717776 Enter into DVFS_PRE_config >>>>>
2298 16:30:13.727865 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 16:30:13.730788 Exit from DVFS_PRE_config <<<<<
2300 16:30:13.734251 Enter into PICG configuration >>>>
2301 16:30:13.737658 Exit from PICG configuration <<<<
2302 16:30:13.741324 [RX_INPUT] configuration >>>>>
2303 16:30:13.744753 [RX_INPUT] configuration <<<<<
2304 16:30:13.748124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 16:30:13.754208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 16:30:13.761111 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 16:30:13.764579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 16:30:13.770838 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 16:30:13.777471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 16:30:13.781194 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 16:30:13.787564 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 16:30:13.791196 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 16:30:13.794803 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 16:30:13.797519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 16:30:13.804151 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 16:30:13.807817 ===================================
2317 16:30:13.807896 LPDDR4 DRAM CONFIGURATION
2318 16:30:13.811389 ===================================
2319 16:30:13.814316 EX_ROW_EN[0] = 0x0
2320 16:30:13.817852 EX_ROW_EN[1] = 0x0
2321 16:30:13.817929 LP4Y_EN = 0x0
2322 16:30:13.820822 WORK_FSP = 0x0
2323 16:30:13.820899 WL = 0x4
2324 16:30:13.824310 RL = 0x4
2325 16:30:13.824388 BL = 0x2
2326 16:30:13.827805 RPST = 0x0
2327 16:30:13.827883 RD_PRE = 0x0
2328 16:30:13.831143 WR_PRE = 0x1
2329 16:30:13.831239 WR_PST = 0x0
2330 16:30:13.834266 DBI_WR = 0x0
2331 16:30:13.834359 DBI_RD = 0x0
2332 16:30:13.837607 OTF = 0x1
2333 16:30:13.840916 ===================================
2334 16:30:13.844112 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 16:30:13.847864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 16:30:13.854229 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 16:30:13.854328 ===================================
2338 16:30:13.857867 LPDDR4 DRAM CONFIGURATION
2339 16:30:13.861216 ===================================
2340 16:30:13.864772 EX_ROW_EN[0] = 0x10
2341 16:30:13.864870 EX_ROW_EN[1] = 0x0
2342 16:30:13.868137 LP4Y_EN = 0x0
2343 16:30:13.868232 WORK_FSP = 0x0
2344 16:30:13.871457 WL = 0x4
2345 16:30:13.871548 RL = 0x4
2346 16:30:13.874860 BL = 0x2
2347 16:30:13.874951 RPST = 0x0
2348 16:30:13.877637 RD_PRE = 0x0
2349 16:30:13.877732 WR_PRE = 0x1
2350 16:30:13.881288 WR_PST = 0x0
2351 16:30:13.884870 DBI_WR = 0x0
2352 16:30:13.884967 DBI_RD = 0x0
2353 16:30:13.887684 OTF = 0x1
2354 16:30:13.891329 ===================================
2355 16:30:13.894826 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 16:30:13.894923 ==
2357 16:30:13.897606 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 16:30:13.904938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 16:30:13.905039 ==
2360 16:30:13.905130 [Duty_Offset_Calibration]
2361 16:30:13.907879 B0:2 B1:1 CA:1
2362 16:30:13.907968
2363 16:30:13.911483 [DutyScan_Calibration_Flow] k_type=0
2364 16:30:13.920672
2365 16:30:13.920772 ==CLK 0==
2366 16:30:13.923512 Final CLK duty delay cell = 0
2367 16:30:13.927131 [0] MAX Duty = 5187%(X100), DQS PI = 24
2368 16:30:13.930672 [0] MIN Duty = 4844%(X100), DQS PI = 48
2369 16:30:13.930767 [0] AVG Duty = 5015%(X100)
2370 16:30:13.930854
2371 16:30:13.933648 CH0 CLK Duty spec in!! Max-Min= 343%
2372 16:30:13.940819 [DutyScan_Calibration_Flow] ====Done====
2373 16:30:13.940919
2374 16:30:13.943552 [DutyScan_Calibration_Flow] k_type=1
2375 16:30:13.959086
2376 16:30:13.959187 ==DQS 0 ==
2377 16:30:13.962366 Final DQS duty delay cell = -4
2378 16:30:13.965880 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2379 16:30:13.968724 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2380 16:30:13.972134 [-4] AVG Duty = 4937%(X100)
2381 16:30:13.972256
2382 16:30:13.972341 ==DQS 1 ==
2383 16:30:13.975519 Final DQS duty delay cell = 0
2384 16:30:13.978896 [0] MAX Duty = 5156%(X100), DQS PI = 46
2385 16:30:13.982305 [0] MIN Duty = 5000%(X100), DQS PI = 32
2386 16:30:13.985981 [0] AVG Duty = 5078%(X100)
2387 16:30:13.986089
2388 16:30:13.988811 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2389 16:30:13.988919
2390 16:30:13.992378 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2391 16:30:13.995948 [DutyScan_Calibration_Flow] ====Done====
2392 16:30:13.996062
2393 16:30:13.998736 [DutyScan_Calibration_Flow] k_type=3
2394 16:30:14.015846
2395 16:30:14.015942 ==DQM 0 ==
2396 16:30:14.019465 Final DQM duty delay cell = 0
2397 16:30:14.022488 [0] MAX Duty = 5125%(X100), DQS PI = 22
2398 16:30:14.026014 [0] MIN Duty = 4906%(X100), DQS PI = 50
2399 16:30:14.028919 [0] AVG Duty = 5015%(X100)
2400 16:30:14.029012
2401 16:30:14.029097 ==DQM 1 ==
2402 16:30:14.032741 Final DQM duty delay cell = 0
2403 16:30:14.036322 [0] MAX Duty = 5093%(X100), DQS PI = 0
2404 16:30:14.039292 [0] MIN Duty = 5031%(X100), DQS PI = 16
2405 16:30:14.039398 [0] AVG Duty = 5062%(X100)
2406 16:30:14.042946
2407 16:30:14.046372 CH0 DQM 0 Duty spec in!! Max-Min= 219%
2408 16:30:14.046507
2409 16:30:14.049150 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2410 16:30:14.052719 [DutyScan_Calibration_Flow] ====Done====
2411 16:30:14.052836
2412 16:30:14.055745 [DutyScan_Calibration_Flow] k_type=2
2413 16:30:14.072279
2414 16:30:14.072364 ==DQ 0 ==
2415 16:30:14.075580 Final DQ duty delay cell = 0
2416 16:30:14.078805 [0] MAX Duty = 5031%(X100), DQS PI = 26
2417 16:30:14.082158 [0] MIN Duty = 4844%(X100), DQS PI = 62
2418 16:30:14.082239 [0] AVG Duty = 4937%(X100)
2419 16:30:14.085788
2420 16:30:14.085864 ==DQ 1 ==
2421 16:30:14.088709 Final DQ duty delay cell = 0
2422 16:30:14.092130 [0] MAX Duty = 5093%(X100), DQS PI = 24
2423 16:30:14.095550 [0] MIN Duty = 4938%(X100), DQS PI = 36
2424 16:30:14.095654 [0] AVG Duty = 5015%(X100)
2425 16:30:14.098763
2426 16:30:14.102326 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2427 16:30:14.102423
2428 16:30:14.105296 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2429 16:30:14.108535 [DutyScan_Calibration_Flow] ====Done====
2430 16:30:14.108631 ==
2431 16:30:14.111954 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 16:30:14.115534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 16:30:14.115634 ==
2434 16:30:14.119290 [Duty_Offset_Calibration]
2435 16:30:14.119365 B0:1 B1:0 CA:0
2436 16:30:14.119452
2437 16:30:14.122215 [DutyScan_Calibration_Flow] k_type=0
2438 16:30:14.131599
2439 16:30:14.131697 ==CLK 0==
2440 16:30:14.135152 Final CLK duty delay cell = -4
2441 16:30:14.138098 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2442 16:30:14.141120 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2443 16:30:14.144905 [-4] AVG Duty = 4953%(X100)
2444 16:30:14.145068
2445 16:30:14.148374 CH1 CLK Duty spec in!! Max-Min= 93%
2446 16:30:14.151351 [DutyScan_Calibration_Flow] ====Done====
2447 16:30:14.151463
2448 16:30:14.154248 [DutyScan_Calibration_Flow] k_type=1
2449 16:30:14.171595
2450 16:30:14.171735 ==DQS 0 ==
2451 16:30:14.174402 Final DQS duty delay cell = 0
2452 16:30:14.177953 [0] MAX Duty = 5062%(X100), DQS PI = 16
2453 16:30:14.181467 [0] MIN Duty = 4844%(X100), DQS PI = 0
2454 16:30:14.181576 [0] AVG Duty = 4953%(X100)
2455 16:30:14.184871
2456 16:30:14.184966 ==DQS 1 ==
2457 16:30:14.188224 Final DQS duty delay cell = 0
2458 16:30:14.191475 [0] MAX Duty = 5187%(X100), DQS PI = 18
2459 16:30:14.194370 [0] MIN Duty = 4938%(X100), DQS PI = 58
2460 16:30:14.194466 [0] AVG Duty = 5062%(X100)
2461 16:30:14.197646
2462 16:30:14.201179 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2463 16:30:14.201254
2464 16:30:14.204764 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2465 16:30:14.208379 [DutyScan_Calibration_Flow] ====Done====
2466 16:30:14.208488
2467 16:30:14.211217 [DutyScan_Calibration_Flow] k_type=3
2468 16:30:14.227790
2469 16:30:14.227897 ==DQM 0 ==
2470 16:30:14.230895 Final DQM duty delay cell = 0
2471 16:30:14.234096 [0] MAX Duty = 5156%(X100), DQS PI = 6
2472 16:30:14.237393 [0] MIN Duty = 5000%(X100), DQS PI = 46
2473 16:30:14.241087 [0] AVG Duty = 5078%(X100)
2474 16:30:14.241185
2475 16:30:14.241274 ==DQM 1 ==
2476 16:30:14.244666 Final DQM duty delay cell = 0
2477 16:30:14.247670 [0] MAX Duty = 5031%(X100), DQS PI = 26
2478 16:30:14.251141 [0] MIN Duty = 4875%(X100), DQS PI = 52
2479 16:30:14.254067 [0] AVG Duty = 4953%(X100)
2480 16:30:14.254150
2481 16:30:14.257879 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2482 16:30:14.258010
2483 16:30:14.260817 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2484 16:30:14.264342 [DutyScan_Calibration_Flow] ====Done====
2485 16:30:14.264425
2486 16:30:14.267917 [DutyScan_Calibration_Flow] k_type=2
2487 16:30:14.283922
2488 16:30:14.284035 ==DQ 0 ==
2489 16:30:14.286852 Final DQ duty delay cell = -4
2490 16:30:14.290581 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2491 16:30:14.293424 [-4] MIN Duty = 4906%(X100), DQS PI = 38
2492 16:30:14.297021 [-4] AVG Duty = 4984%(X100)
2493 16:30:14.297097
2494 16:30:14.297156 ==DQ 1 ==
2495 16:30:14.300551 Final DQ duty delay cell = 0
2496 16:30:14.304000 [0] MAX Duty = 5125%(X100), DQS PI = 18
2497 16:30:14.307434 [0] MIN Duty = 4969%(X100), DQS PI = 10
2498 16:30:14.307512 [0] AVG Duty = 5047%(X100)
2499 16:30:14.310636
2500 16:30:14.313875 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2501 16:30:14.313953
2502 16:30:14.317119 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2503 16:30:14.320541 [DutyScan_Calibration_Flow] ====Done====
2504 16:30:14.323474 nWR fixed to 30
2505 16:30:14.323573 [ModeRegInit_LP4] CH0 RK0
2506 16:30:14.326902 [ModeRegInit_LP4] CH0 RK1
2507 16:30:14.330339 [ModeRegInit_LP4] CH1 RK0
2508 16:30:14.330429 [ModeRegInit_LP4] CH1 RK1
2509 16:30:14.333652 match AC timing 7
2510 16:30:14.337232 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 16:30:14.340686 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 16:30:14.346791 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 16:30:14.350090 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 16:30:14.357067 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 16:30:14.357199 ==
2516 16:30:14.360654 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 16:30:14.363479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 16:30:14.363559 ==
2519 16:30:14.370127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 16:30:14.373743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 16:30:14.383846 [CA 0] Center 39 (8~70) winsize 63
2522 16:30:14.387454 [CA 1] Center 39 (8~70) winsize 63
2523 16:30:14.390365 [CA 2] Center 35 (5~66) winsize 62
2524 16:30:14.394021 [CA 3] Center 34 (4~65) winsize 62
2525 16:30:14.396966 [CA 4] Center 33 (3~64) winsize 62
2526 16:30:14.400539 [CA 5] Center 32 (3~62) winsize 60
2527 16:30:14.400617
2528 16:30:14.404192 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2529 16:30:14.404271
2530 16:30:14.407080 [CATrainingPosCal] consider 1 rank data
2531 16:30:14.410715 u2DelayCellTimex100 = 270/100 ps
2532 16:30:14.413591 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2533 16:30:14.417195 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2534 16:30:14.423989 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2535 16:30:14.427400 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2536 16:30:14.430771 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2537 16:30:14.434037 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2538 16:30:14.434116
2539 16:30:14.437159 CA PerBit enable=1, Macro0, CA PI delay=32
2540 16:30:14.437239
2541 16:30:14.440730 [CBTSetCACLKResult] CA Dly = 32
2542 16:30:14.440809 CS Dly: 6 (0~37)
2543 16:30:14.440871 ==
2544 16:30:14.444416 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 16:30:14.450458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 16:30:14.450569 ==
2547 16:30:14.453914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 16:30:14.460905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2549 16:30:14.469409 [CA 0] Center 38 (8~69) winsize 62
2550 16:30:14.473184 [CA 1] Center 38 (8~69) winsize 62
2551 16:30:14.476441 [CA 2] Center 35 (4~66) winsize 63
2552 16:30:14.479807 [CA 3] Center 34 (4~65) winsize 62
2553 16:30:14.483213 [CA 4] Center 33 (3~64) winsize 62
2554 16:30:14.486115 [CA 5] Center 32 (3~62) winsize 60
2555 16:30:14.486188
2556 16:30:14.489687 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 16:30:14.489765
2558 16:30:14.493301 [CATrainingPosCal] consider 2 rank data
2559 16:30:14.496276 u2DelayCellTimex100 = 270/100 ps
2560 16:30:14.499259 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2561 16:30:14.503018 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2562 16:30:14.509686 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2563 16:30:14.513278 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2564 16:30:14.516139 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2565 16:30:14.519881 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2566 16:30:14.519963
2567 16:30:14.522772 CA PerBit enable=1, Macro0, CA PI delay=32
2568 16:30:14.522850
2569 16:30:14.526252 [CBTSetCACLKResult] CA Dly = 32
2570 16:30:14.526330 CS Dly: 6 (0~38)
2571 16:30:14.526392
2572 16:30:14.529849 ----->DramcWriteLeveling(PI) begin...
2573 16:30:14.532714 ==
2574 16:30:14.536218 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 16:30:14.539945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 16:30:14.540080 ==
2577 16:30:14.542878 Write leveling (Byte 0): 33 => 33
2578 16:30:14.546473 Write leveling (Byte 1): 30 => 30
2579 16:30:14.549820 DramcWriteLeveling(PI) end<-----
2580 16:30:14.549962
2581 16:30:14.550052 ==
2582 16:30:14.553262 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 16:30:14.556541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 16:30:14.556635 ==
2585 16:30:14.559683 [Gating] SW mode calibration
2586 16:30:14.566429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 16:30:14.569392 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 16:30:14.575966 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2589 16:30:14.579331 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2590 16:30:14.582630 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 16:30:14.589915 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 16:30:14.592881 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 16:30:14.596450 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 16:30:14.602783 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
2595 16:30:14.606774 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
2596 16:30:14.609835 1 0 0 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
2597 16:30:14.616488 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 16:30:14.619382 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 16:30:14.623096 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 16:30:14.629624 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 16:30:14.633196 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 16:30:14.636173 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2603 16:30:14.642705 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2604 16:30:14.646299 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2605 16:30:14.649863 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 16:30:14.652814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 16:30:14.659431 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 16:30:14.663079 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 16:30:14.666656 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 16:30:14.672868 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 16:30:14.676275 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 16:30:14.679844 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 16:30:14.686720 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 16:30:14.689794 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 16:30:14.692970 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 16:30:14.699516 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 16:30:14.703462 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 16:30:14.706204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 16:30:14.713257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 16:30:14.716377 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 16:30:14.720144 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 16:30:14.723263 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 16:30:14.729696 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 16:30:14.733224 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 16:30:14.736908 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 16:30:14.743521 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 16:30:14.746485 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 16:30:14.750155 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 16:30:14.753707 Total UI for P1: 0, mck2ui 16
2630 16:30:14.756665 best dqsien dly found for B0: ( 1, 3, 26)
2631 16:30:14.760442 Total UI for P1: 0, mck2ui 16
2632 16:30:14.763463 best dqsien dly found for B1: ( 1, 3, 30)
2633 16:30:14.767048 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2634 16:30:14.769967 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2635 16:30:14.770065
2636 16:30:14.776977 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2637 16:30:14.780422 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2638 16:30:14.780529 [Gating] SW calibration Done
2639 16:30:14.783337 ==
2640 16:30:14.783417 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 16:30:14.790173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 16:30:14.790271 ==
2643 16:30:14.790335 RX Vref Scan: 0
2644 16:30:14.790392
2645 16:30:14.793820 RX Vref 0 -> 0, step: 1
2646 16:30:14.793901
2647 16:30:14.796614 RX Delay -40 -> 252, step: 8
2648 16:30:14.799950 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2649 16:30:14.803303 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2650 16:30:14.806811 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2651 16:30:14.813563 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2652 16:30:14.817004 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2653 16:30:14.819926 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2654 16:30:14.823287 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2655 16:30:14.826849 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2656 16:30:14.833751 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2657 16:30:14.836831 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2658 16:30:14.840092 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2659 16:30:14.843350 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2660 16:30:14.846579 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2661 16:30:14.853467 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2662 16:30:14.857155 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2663 16:30:14.860320 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2664 16:30:14.860421 ==
2665 16:30:14.863195 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 16:30:14.866862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 16:30:14.866978 ==
2668 16:30:14.869869 DQS Delay:
2669 16:30:14.869968 DQS0 = 0, DQS1 = 0
2670 16:30:14.873436 DQM Delay:
2671 16:30:14.873557 DQM0 = 121, DQM1 = 113
2672 16:30:14.873649 DQ Delay:
2673 16:30:14.879914 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2674 16:30:14.883451 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2675 16:30:14.886790 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2676 16:30:14.889681 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2677 16:30:14.889759
2678 16:30:14.889824
2679 16:30:14.889880 ==
2680 16:30:14.893279 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 16:30:14.896892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 16:30:14.897017 ==
2683 16:30:14.897109
2684 16:30:14.897198
2685 16:30:14.899806 TX Vref Scan disable
2686 16:30:14.903453 == TX Byte 0 ==
2687 16:30:14.906836 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2688 16:30:14.909561 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2689 16:30:14.913129 == TX Byte 1 ==
2690 16:30:14.916616 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2691 16:30:14.920217 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2692 16:30:14.920319 ==
2693 16:30:14.922968 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 16:30:14.926313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 16:30:14.929730 ==
2696 16:30:14.940159 TX Vref=22, minBit 0, minWin=25, winSum=407
2697 16:30:14.942990 TX Vref=24, minBit 0, minWin=25, winSum=416
2698 16:30:14.946673 TX Vref=26, minBit 0, minWin=26, winSum=420
2699 16:30:14.950372 TX Vref=28, minBit 0, minWin=26, winSum=422
2700 16:30:14.953147 TX Vref=30, minBit 0, minWin=26, winSum=422
2701 16:30:14.956538 TX Vref=32, minBit 0, minWin=26, winSum=424
2702 16:30:14.963396 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
2703 16:30:14.963481
2704 16:30:14.966880 Final TX Range 1 Vref 32
2705 16:30:14.966976
2706 16:30:14.967078 ==
2707 16:30:14.970205 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 16:30:14.973903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 16:30:14.973983 ==
2710 16:30:14.974044
2711 16:30:14.974100
2712 16:30:14.976828 TX Vref Scan disable
2713 16:30:14.980519 == TX Byte 0 ==
2714 16:30:14.983384 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2715 16:30:14.986978 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2716 16:30:14.990354 == TX Byte 1 ==
2717 16:30:14.993827 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2718 16:30:14.996645 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2719 16:30:14.996724
2720 16:30:15.000222 [DATLAT]
2721 16:30:15.000302 Freq=1200, CH0 RK0
2722 16:30:15.000363
2723 16:30:15.003950 DATLAT Default: 0xd
2724 16:30:15.004029 0, 0xFFFF, sum = 0
2725 16:30:15.006900 1, 0xFFFF, sum = 0
2726 16:30:15.006981 2, 0xFFFF, sum = 0
2727 16:30:15.009887 3, 0xFFFF, sum = 0
2728 16:30:15.009967 4, 0xFFFF, sum = 0
2729 16:30:15.013453 5, 0xFFFF, sum = 0
2730 16:30:15.013566 6, 0xFFFF, sum = 0
2731 16:30:15.017015 7, 0xFFFF, sum = 0
2732 16:30:15.017125 8, 0xFFFF, sum = 0
2733 16:30:15.020329 9, 0xFFFF, sum = 0
2734 16:30:15.020410 10, 0xFFFF, sum = 0
2735 16:30:15.023133 11, 0xFFFF, sum = 0
2736 16:30:15.026678 12, 0x0, sum = 1
2737 16:30:15.026759 13, 0x0, sum = 2
2738 16:30:15.026822 14, 0x0, sum = 3
2739 16:30:15.030247 15, 0x0, sum = 4
2740 16:30:15.030327 best_step = 13
2741 16:30:15.030387
2742 16:30:15.030443 ==
2743 16:30:15.033777 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 16:30:15.040147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 16:30:15.040229 ==
2746 16:30:15.040290 RX Vref Scan: 1
2747 16:30:15.040346
2748 16:30:15.043827 Set Vref Range= 32 -> 127
2749 16:30:15.043905
2750 16:30:15.048343 RX Vref 32 -> 127, step: 1
2751 16:30:15.048441
2752 16:30:15.049931 RX Delay -13 -> 252, step: 4
2753 16:30:15.050012
2754 16:30:15.053471 Set Vref, RX VrefLevel [Byte0]: 32
2755 16:30:15.053582 [Byte1]: 32
2756 16:30:15.058532
2757 16:30:15.058611 Set Vref, RX VrefLevel [Byte0]: 33
2758 16:30:15.061398 [Byte1]: 33
2759 16:30:15.066375
2760 16:30:15.066479 Set Vref, RX VrefLevel [Byte0]: 34
2761 16:30:15.069096 [Byte1]: 34
2762 16:30:15.074012
2763 16:30:15.074116 Set Vref, RX VrefLevel [Byte0]: 35
2764 16:30:15.077482 [Byte1]: 35
2765 16:30:15.081954
2766 16:30:15.082034 Set Vref, RX VrefLevel [Byte0]: 36
2767 16:30:15.085488 [Byte1]: 36
2768 16:30:15.089844
2769 16:30:15.089919 Set Vref, RX VrefLevel [Byte0]: 37
2770 16:30:15.092819 [Byte1]: 37
2771 16:30:15.097778
2772 16:30:15.097883 Set Vref, RX VrefLevel [Byte0]: 38
2773 16:30:15.101233 [Byte1]: 38
2774 16:30:15.105296
2775 16:30:15.105414 Set Vref, RX VrefLevel [Byte0]: 39
2776 16:30:15.108925 [Byte1]: 39
2777 16:30:15.113229
2778 16:30:15.113331 Set Vref, RX VrefLevel [Byte0]: 40
2779 16:30:15.116837 [Byte1]: 40
2780 16:30:15.121243
2781 16:30:15.121349 Set Vref, RX VrefLevel [Byte0]: 41
2782 16:30:15.124564 [Byte1]: 41
2783 16:30:15.129431
2784 16:30:15.129543 Set Vref, RX VrefLevel [Byte0]: 42
2785 16:30:15.132354 [Byte1]: 42
2786 16:30:15.137073
2787 16:30:15.137157 Set Vref, RX VrefLevel [Byte0]: 43
2788 16:30:15.140760 [Byte1]: 43
2789 16:30:15.144800
2790 16:30:15.144889 Set Vref, RX VrefLevel [Byte0]: 44
2791 16:30:15.148523 [Byte1]: 44
2792 16:30:15.152765
2793 16:30:15.152845 Set Vref, RX VrefLevel [Byte0]: 45
2794 16:30:15.156204 [Byte1]: 45
2795 16:30:15.161170
2796 16:30:15.161269 Set Vref, RX VrefLevel [Byte0]: 46
2797 16:30:15.164146 [Byte1]: 46
2798 16:30:15.168413
2799 16:30:15.168518 Set Vref, RX VrefLevel [Byte0]: 47
2800 16:30:15.171980 [Byte1]: 47
2801 16:30:15.176763
2802 16:30:15.176872 Set Vref, RX VrefLevel [Byte0]: 48
2803 16:30:15.179704 [Byte1]: 48
2804 16:30:15.184725
2805 16:30:15.184804 Set Vref, RX VrefLevel [Byte0]: 49
2806 16:30:15.187489 [Byte1]: 49
2807 16:30:15.192195
2808 16:30:15.192303 Set Vref, RX VrefLevel [Byte0]: 50
2809 16:30:15.195431 [Byte1]: 50
2810 16:30:15.200515
2811 16:30:15.200620 Set Vref, RX VrefLevel [Byte0]: 51
2812 16:30:15.203468 [Byte1]: 51
2813 16:30:15.208463
2814 16:30:15.208559 Set Vref, RX VrefLevel [Byte0]: 52
2815 16:30:15.211192 [Byte1]: 52
2816 16:30:15.216115
2817 16:30:15.216195 Set Vref, RX VrefLevel [Byte0]: 53
2818 16:30:15.219018 [Byte1]: 53
2819 16:30:15.224204
2820 16:30:15.224311 Set Vref, RX VrefLevel [Byte0]: 54
2821 16:30:15.227049 [Byte1]: 54
2822 16:30:15.231987
2823 16:30:15.232070 Set Vref, RX VrefLevel [Byte0]: 55
2824 16:30:15.234855 [Byte1]: 55
2825 16:30:15.239913
2826 16:30:15.239992 Set Vref, RX VrefLevel [Byte0]: 56
2827 16:30:15.243274 [Byte1]: 56
2828 16:30:15.247481
2829 16:30:15.247608 Set Vref, RX VrefLevel [Byte0]: 57
2830 16:30:15.250896 [Byte1]: 57
2831 16:30:15.255707
2832 16:30:15.255782 Set Vref, RX VrefLevel [Byte0]: 58
2833 16:30:15.258589 [Byte1]: 58
2834 16:30:15.263374
2835 16:30:15.263458 Set Vref, RX VrefLevel [Byte0]: 59
2836 16:30:15.266825 [Byte1]: 59
2837 16:30:15.271054
2838 16:30:15.271140 Set Vref, RX VrefLevel [Byte0]: 60
2839 16:30:15.274721 [Byte1]: 60
2840 16:30:15.279011
2841 16:30:15.279096 Set Vref, RX VrefLevel [Byte0]: 61
2842 16:30:15.282402 [Byte1]: 61
2843 16:30:15.287190
2844 16:30:15.287277 Set Vref, RX VrefLevel [Byte0]: 62
2845 16:30:15.290197 [Byte1]: 62
2846 16:30:15.294719
2847 16:30:15.294802 Set Vref, RX VrefLevel [Byte0]: 63
2848 16:30:15.298258 [Byte1]: 63
2849 16:30:15.302445
2850 16:30:15.302535 Set Vref, RX VrefLevel [Byte0]: 64
2851 16:30:15.305818 [Byte1]: 64
2852 16:30:15.310686
2853 16:30:15.310785 Set Vref, RX VrefLevel [Byte0]: 65
2854 16:30:15.314793 [Byte1]: 65
2855 16:30:15.318374
2856 16:30:15.318454 Set Vref, RX VrefLevel [Byte0]: 66
2857 16:30:15.321938 [Byte1]: 66
2858 16:30:15.326221
2859 16:30:15.326307 Set Vref, RX VrefLevel [Byte0]: 67
2860 16:30:15.329781 [Byte1]: 67
2861 16:30:15.334111
2862 16:30:15.334197 Set Vref, RX VrefLevel [Byte0]: 68
2863 16:30:15.337512 [Byte1]: 68
2864 16:30:15.342432
2865 16:30:15.342521 Final RX Vref Byte 0 = 55 to rank0
2866 16:30:15.345233 Final RX Vref Byte 1 = 49 to rank0
2867 16:30:15.348904 Final RX Vref Byte 0 = 55 to rank1
2868 16:30:15.352669 Final RX Vref Byte 1 = 49 to rank1==
2869 16:30:15.355377 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 16:30:15.362322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 16:30:15.362435 ==
2872 16:30:15.362504 DQS Delay:
2873 16:30:15.362561 DQS0 = 0, DQS1 = 0
2874 16:30:15.365786 DQM Delay:
2875 16:30:15.365872 DQM0 = 120, DQM1 = 112
2876 16:30:15.368579 DQ Delay:
2877 16:30:15.372095 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2878 16:30:15.375440 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2879 16:30:15.378903 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2880 16:30:15.382477 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2881 16:30:15.382560
2882 16:30:15.382638
2883 16:30:15.389102 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2884 16:30:15.392508 CH0 RK0: MR19=404, MR18=160F
2885 16:30:15.399014 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2886 16:30:15.399118
2887 16:30:15.402685 ----->DramcWriteLeveling(PI) begin...
2888 16:30:15.402769 ==
2889 16:30:15.405557 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 16:30:15.409137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 16:30:15.412685 ==
2892 16:30:15.412780 Write leveling (Byte 0): 34 => 34
2893 16:30:15.416066 Write leveling (Byte 1): 32 => 32
2894 16:30:15.419133 DramcWriteLeveling(PI) end<-----
2895 16:30:15.419246
2896 16:30:15.419321 ==
2897 16:30:15.422721 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 16:30:15.426317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 16:30:15.429064 ==
2900 16:30:15.429185 [Gating] SW mode calibration
2901 16:30:15.439293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 16:30:15.442790 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 16:30:15.445482 0 15 0 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
2904 16:30:15.452637 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 16:30:15.456320 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 16:30:15.459220 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 16:30:15.465720 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 16:30:15.469368 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 16:30:15.472951 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 16:30:15.479740 0 15 28 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
2911 16:30:15.483224 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2912 16:30:15.486034 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 16:30:15.489346 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 16:30:15.496274 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 16:30:15.499806 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 16:30:15.503160 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 16:30:15.509811 1 0 24 | B1->B0 | 2525 2525 | 0 1 | (0 0) (0 0)
2918 16:30:15.513422 1 0 28 | B1->B0 | 3c3c 3939 | 0 0 | (0 0) (1 1)
2919 16:30:15.516350 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 16:30:15.522860 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 16:30:15.526336 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 16:30:15.529568 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 16:30:15.536648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 16:30:15.539949 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 16:30:15.542655 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2926 16:30:15.549542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2927 16:30:15.553337 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2928 16:30:15.556235 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 16:30:15.562732 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 16:30:15.566351 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 16:30:15.569893 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 16:30:15.572778 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 16:30:15.579394 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 16:30:15.582971 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 16:30:15.586425 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 16:30:15.592958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 16:30:15.596486 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 16:30:15.599685 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 16:30:15.606386 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 16:30:15.609195 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 16:30:15.612815 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 16:30:15.619414 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2943 16:30:15.623196 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 16:30:15.626150 Total UI for P1: 0, mck2ui 16
2945 16:30:15.629824 best dqsien dly found for B0: ( 1, 3, 28)
2946 16:30:15.632693 Total UI for P1: 0, mck2ui 16
2947 16:30:15.636364 best dqsien dly found for B1: ( 1, 3, 28)
2948 16:30:15.639210 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2949 16:30:15.642922 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2950 16:30:15.643093
2951 16:30:15.646258 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2952 16:30:15.649331 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2953 16:30:15.652643 [Gating] SW calibration Done
2954 16:30:15.652812 ==
2955 16:30:15.656477 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 16:30:15.659725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 16:30:15.663115 ==
2958 16:30:15.663294 RX Vref Scan: 0
2959 16:30:15.663425
2960 16:30:15.666439 RX Vref 0 -> 0, step: 1
2961 16:30:15.666596
2962 16:30:15.666724 RX Delay -40 -> 252, step: 8
2963 16:30:15.673179 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2964 16:30:15.676277 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2965 16:30:15.679810 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2966 16:30:15.682728 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2967 16:30:15.686325 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2968 16:30:15.692877 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2969 16:30:15.696519 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2970 16:30:15.699523 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2971 16:30:15.703201 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2972 16:30:15.706432 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2973 16:30:15.713314 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2974 16:30:15.716836 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2975 16:30:15.719753 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2976 16:30:15.723257 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2977 16:30:15.726289 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2978 16:30:15.733042 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2979 16:30:15.733130 ==
2980 16:30:15.736772 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 16:30:15.739590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 16:30:15.739695 ==
2983 16:30:15.739782 DQS Delay:
2984 16:30:15.743322 DQS0 = 0, DQS1 = 0
2985 16:30:15.743428 DQM Delay:
2986 16:30:15.746303 DQM0 = 122, DQM1 = 113
2987 16:30:15.746409 DQ Delay:
2988 16:30:15.749889 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2989 16:30:15.753591 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2990 16:30:15.756467 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2991 16:30:15.760117 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2992 16:30:15.760228
2993 16:30:15.760316
2994 16:30:15.763073 ==
2995 16:30:15.763176 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 16:30:15.770240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 16:30:15.770390 ==
2998 16:30:15.770481
2999 16:30:15.770564
3000 16:30:15.770664 TX Vref Scan disable
3001 16:30:15.773771 == TX Byte 0 ==
3002 16:30:15.777310 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3003 16:30:15.780095 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3004 16:30:15.784053 == TX Byte 1 ==
3005 16:30:15.786801 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3006 16:30:15.790179 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3007 16:30:15.793799 ==
3008 16:30:15.797408 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 16:30:15.800264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 16:30:15.800392 ==
3011 16:30:15.811796 TX Vref=22, minBit 1, minWin=25, winSum=416
3012 16:30:15.815332 TX Vref=24, minBit 3, minWin=25, winSum=421
3013 16:30:15.818153 TX Vref=26, minBit 3, minWin=25, winSum=424
3014 16:30:15.821819 TX Vref=28, minBit 1, minWin=26, winSum=423
3015 16:30:15.825418 TX Vref=30, minBit 1, minWin=26, winSum=427
3016 16:30:15.828345 TX Vref=32, minBit 0, minWin=26, winSum=428
3017 16:30:15.835216 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 32
3018 16:30:15.835366
3019 16:30:15.838916 Final TX Range 1 Vref 32
3020 16:30:15.839059
3021 16:30:15.839162 ==
3022 16:30:15.841929 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 16:30:15.845443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 16:30:15.845588 ==
3025 16:30:15.845667
3026 16:30:15.845759
3027 16:30:15.848357 TX Vref Scan disable
3028 16:30:15.851949 == TX Byte 0 ==
3029 16:30:15.855729 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3030 16:30:15.858668 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3031 16:30:15.861619 == TX Byte 1 ==
3032 16:30:15.865292 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3033 16:30:15.868817 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3034 16:30:15.868934
3035 16:30:15.871550 [DATLAT]
3036 16:30:15.871654 Freq=1200, CH0 RK1
3037 16:30:15.871759
3038 16:30:15.875246 DATLAT Default: 0xd
3039 16:30:15.875342 0, 0xFFFF, sum = 0
3040 16:30:15.878865 1, 0xFFFF, sum = 0
3041 16:30:15.878972 2, 0xFFFF, sum = 0
3042 16:30:15.881739 3, 0xFFFF, sum = 0
3043 16:30:15.881847 4, 0xFFFF, sum = 0
3044 16:30:15.885397 5, 0xFFFF, sum = 0
3045 16:30:15.885513 6, 0xFFFF, sum = 0
3046 16:30:15.888215 7, 0xFFFF, sum = 0
3047 16:30:15.888323 8, 0xFFFF, sum = 0
3048 16:30:15.891885 9, 0xFFFF, sum = 0
3049 16:30:15.895393 10, 0xFFFF, sum = 0
3050 16:30:15.895498 11, 0xFFFF, sum = 0
3051 16:30:15.898079 12, 0x0, sum = 1
3052 16:30:15.898191 13, 0x0, sum = 2
3053 16:30:15.898290 14, 0x0, sum = 3
3054 16:30:15.901662 15, 0x0, sum = 4
3055 16:30:15.901819 best_step = 13
3056 16:30:15.901944
3057 16:30:15.905092 ==
3058 16:30:15.905231 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 16:30:15.911755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 16:30:15.911918 ==
3061 16:30:15.912044 RX Vref Scan: 0
3062 16:30:15.912160
3063 16:30:15.915257 RX Vref 0 -> 0, step: 1
3064 16:30:15.915397
3065 16:30:15.918829 RX Delay -13 -> 252, step: 4
3066 16:30:15.921464 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3067 16:30:15.925105 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3068 16:30:15.932079 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3069 16:30:15.935328 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3070 16:30:15.938184 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3071 16:30:15.941488 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3072 16:30:15.945158 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3073 16:30:15.951842 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3074 16:30:15.954787 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3075 16:30:15.958378 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3076 16:30:15.962057 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3077 16:30:15.965042 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3078 16:30:15.971840 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3079 16:30:15.974714 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3080 16:30:15.978206 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3081 16:30:15.981927 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3082 16:30:15.982033 ==
3083 16:30:15.984886 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 16:30:15.991341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 16:30:15.991434 ==
3086 16:30:15.991495 DQS Delay:
3087 16:30:15.994986 DQS0 = 0, DQS1 = 0
3088 16:30:15.995088 DQM Delay:
3089 16:30:15.995177 DQM0 = 120, DQM1 = 110
3090 16:30:15.998008 DQ Delay:
3091 16:30:16.001633 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3092 16:30:16.004967 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3093 16:30:16.008500 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3094 16:30:16.011322 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3095 16:30:16.011416
3096 16:30:16.011500
3097 16:30:16.021405 [DQSOSCAuto] RK1, (LSB)MR18= 0xeef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3098 16:30:16.021512 CH0 RK1: MR19=403, MR18=EEF
3099 16:30:16.028166 CH0_RK1: MR19=0x403, MR18=0xEEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3100 16:30:16.031330 [RxdqsGatingPostProcess] freq 1200
3101 16:30:16.037692 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 16:30:16.040903 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 16:30:16.044298 best DQS1 dly(2T, 0.5T) = (0, 11)
3104 16:30:16.047593 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 16:30:16.051070 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3106 16:30:16.051170 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 16:30:16.054675 best DQS1 dly(2T, 0.5T) = (0, 11)
3108 16:30:16.057713 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 16:30:16.061381 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3110 16:30:16.064368 Pre-setting of DQS Precalculation
3111 16:30:16.071227 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 16:30:16.071303 ==
3113 16:30:16.074147 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 16:30:16.077734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 16:30:16.077839 ==
3116 16:30:16.084595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 16:30:16.091086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 16:30:16.097572 [CA 0] Center 37 (7~68) winsize 62
3119 16:30:16.101285 [CA 1] Center 37 (7~68) winsize 62
3120 16:30:16.104297 [CA 2] Center 35 (5~65) winsize 61
3121 16:30:16.107816 [CA 3] Center 34 (4~64) winsize 61
3122 16:30:16.110829 [CA 4] Center 34 (4~64) winsize 61
3123 16:30:16.114261 [CA 5] Center 33 (3~63) winsize 61
3124 16:30:16.114364
3125 16:30:16.117932 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3126 16:30:16.118031
3127 16:30:16.121014 [CATrainingPosCal] consider 1 rank data
3128 16:30:16.124716 u2DelayCellTimex100 = 270/100 ps
3129 16:30:16.127657 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 16:30:16.131302 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 16:30:16.137955 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3132 16:30:16.140852 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 16:30:16.144473 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 16:30:16.147973 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3135 16:30:16.148074
3136 16:30:16.150798 CA PerBit enable=1, Macro0, CA PI delay=33
3137 16:30:16.150895
3138 16:30:16.154137 [CBTSetCACLKResult] CA Dly = 33
3139 16:30:16.154216 CS Dly: 8 (0~39)
3140 16:30:16.157518 ==
3141 16:30:16.157600 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 16:30:16.164426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 16:30:16.164550 ==
3144 16:30:16.167913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 16:30:16.174387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3146 16:30:16.183842 [CA 0] Center 37 (7~68) winsize 62
3147 16:30:16.186665 [CA 1] Center 38 (8~68) winsize 61
3148 16:30:16.190187 [CA 2] Center 35 (5~65) winsize 61
3149 16:30:16.193669 [CA 3] Center 34 (4~65) winsize 62
3150 16:30:16.196442 [CA 4] Center 34 (4~65) winsize 62
3151 16:30:16.200387 [CA 5] Center 34 (4~64) winsize 61
3152 16:30:16.200465
3153 16:30:16.203590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3154 16:30:16.203669
3155 16:30:16.206605 [CATrainingPosCal] consider 2 rank data
3156 16:30:16.210238 u2DelayCellTimex100 = 270/100 ps
3157 16:30:16.213130 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3158 16:30:16.216718 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 16:30:16.223409 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3160 16:30:16.226386 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 16:30:16.229918 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 16:30:16.233655 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3163 16:30:16.233772
3164 16:30:16.236637 CA PerBit enable=1, Macro0, CA PI delay=33
3165 16:30:16.236722
3166 16:30:16.240236 [CBTSetCACLKResult] CA Dly = 33
3167 16:30:16.240334 CS Dly: 9 (0~41)
3168 16:30:16.240418
3169 16:30:16.243186 ----->DramcWriteLeveling(PI) begin...
3170 16:30:16.246845 ==
3171 16:30:16.249734 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 16:30:16.253272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 16:30:16.253382 ==
3174 16:30:16.256843 Write leveling (Byte 0): 28 => 28
3175 16:30:16.259856 Write leveling (Byte 1): 28 => 28
3176 16:30:16.263597 DramcWriteLeveling(PI) end<-----
3177 16:30:16.263689
3178 16:30:16.263764 ==
3179 16:30:16.267161 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 16:30:16.269957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 16:30:16.270033 ==
3182 16:30:16.273230 [Gating] SW mode calibration
3183 16:30:16.280030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 16:30:16.283124 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 16:30:16.290147 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 16:30:16.293337 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 16:30:16.296904 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 16:30:16.303403 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 16:30:16.306816 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 16:30:16.310095 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 16:30:16.316843 0 15 24 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 0)
3192 16:30:16.320251 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3193 16:30:16.323215 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 16:30:16.329589 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 16:30:16.333247 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 16:30:16.336206 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 16:30:16.342805 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 16:30:16.346393 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 16:30:16.349992 1 0 24 | B1->B0 | 3434 4040 | 0 0 | (0 0) (0 0)
3200 16:30:16.356582 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3201 16:30:16.359379 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 16:30:16.363128 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 16:30:16.369641 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 16:30:16.372768 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 16:30:16.376423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 16:30:16.383029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 16:30:16.386134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3208 16:30:16.389767 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3209 16:30:16.396135 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 16:30:16.399883 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 16:30:16.402769 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 16:30:16.406316 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 16:30:16.413302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 16:30:16.416227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 16:30:16.419327 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 16:30:16.426328 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 16:30:16.429729 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 16:30:16.432951 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 16:30:16.439252 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 16:30:16.442540 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 16:30:16.446297 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 16:30:16.453105 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 16:30:16.456026 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 16:30:16.459863 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3225 16:30:16.462776 Total UI for P1: 0, mck2ui 16
3226 16:30:16.466505 best dqsien dly found for B0: ( 1, 3, 24)
3227 16:30:16.473046 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 16:30:16.473167 Total UI for P1: 0, mck2ui 16
3229 16:30:16.479633 best dqsien dly found for B1: ( 1, 3, 26)
3230 16:30:16.482558 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3231 16:30:16.486048 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3232 16:30:16.486152
3233 16:30:16.489683 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3234 16:30:16.492589 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 16:30:16.496110 [Gating] SW calibration Done
3236 16:30:16.496207 ==
3237 16:30:16.499064 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 16:30:16.502386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 16:30:16.502496 ==
3240 16:30:16.506102 RX Vref Scan: 0
3241 16:30:16.506205
3242 16:30:16.506302 RX Vref 0 -> 0, step: 1
3243 16:30:16.506401
3244 16:30:16.509216 RX Delay -40 -> 252, step: 8
3245 16:30:16.512326 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3246 16:30:16.519043 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3247 16:30:16.522827 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3248 16:30:16.525609 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3249 16:30:16.529217 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3250 16:30:16.532855 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3251 16:30:16.539336 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3252 16:30:16.542215 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3253 16:30:16.545538 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3254 16:30:16.549241 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3255 16:30:16.552732 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3256 16:30:16.558867 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3257 16:30:16.562191 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3258 16:30:16.565484 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3259 16:30:16.568755 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3260 16:30:16.575352 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3261 16:30:16.575456 ==
3262 16:30:16.579157 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 16:30:16.582113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 16:30:16.582212 ==
3265 16:30:16.582273 DQS Delay:
3266 16:30:16.585746 DQS0 = 0, DQS1 = 0
3267 16:30:16.585849 DQM Delay:
3268 16:30:16.588638 DQM0 = 120, DQM1 = 117
3269 16:30:16.588712 DQ Delay:
3270 16:30:16.592344 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3271 16:30:16.595844 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3272 16:30:16.598832 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =111
3273 16:30:16.602451 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3274 16:30:16.602533
3275 16:30:16.602595
3276 16:30:16.605342 ==
3277 16:30:16.605445 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 16:30:16.612501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 16:30:16.612607 ==
3280 16:30:16.612671
3281 16:30:16.612753
3282 16:30:16.615613 TX Vref Scan disable
3283 16:30:16.615713 == TX Byte 0 ==
3284 16:30:16.618475 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3285 16:30:16.625746 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3286 16:30:16.625861 == TX Byte 1 ==
3287 16:30:16.628569 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3288 16:30:16.635841 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3289 16:30:16.635921 ==
3290 16:30:16.638584 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 16:30:16.642242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 16:30:16.642315 ==
3293 16:30:16.653527 TX Vref=22, minBit 1, minWin=25, winSum=413
3294 16:30:16.656909 TX Vref=24, minBit 1, minWin=25, winSum=415
3295 16:30:16.660353 TX Vref=26, minBit 11, minWin=25, winSum=423
3296 16:30:16.664014 TX Vref=28, minBit 10, minWin=25, winSum=426
3297 16:30:16.667041 TX Vref=30, minBit 11, minWin=25, winSum=428
3298 16:30:16.673288 TX Vref=32, minBit 11, minWin=25, winSum=427
3299 16:30:16.676726 [TxChooseVref] Worse bit 11, Min win 25, Win sum 428, Final Vref 30
3300 16:30:16.676797
3301 16:30:16.680181 Final TX Range 1 Vref 30
3302 16:30:16.680284
3303 16:30:16.680365 ==
3304 16:30:16.683733 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 16:30:16.687139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 16:30:16.690344 ==
3307 16:30:16.690420
3308 16:30:16.690481
3309 16:30:16.690537 TX Vref Scan disable
3310 16:30:16.693745 == TX Byte 0 ==
3311 16:30:16.696766 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3312 16:30:16.703464 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3313 16:30:16.703542 == TX Byte 1 ==
3314 16:30:16.707175 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3315 16:30:16.713790 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3316 16:30:16.713869
3317 16:30:16.713931 [DATLAT]
3318 16:30:16.713986 Freq=1200, CH1 RK0
3319 16:30:16.714055
3320 16:30:16.717244 DATLAT Default: 0xd
3321 16:30:16.717339 0, 0xFFFF, sum = 0
3322 16:30:16.720070 1, 0xFFFF, sum = 0
3323 16:30:16.723507 2, 0xFFFF, sum = 0
3324 16:30:16.723604 3, 0xFFFF, sum = 0
3325 16:30:16.727143 4, 0xFFFF, sum = 0
3326 16:30:16.727248 5, 0xFFFF, sum = 0
3327 16:30:16.730060 6, 0xFFFF, sum = 0
3328 16:30:16.730166 7, 0xFFFF, sum = 0
3329 16:30:16.733003 8, 0xFFFF, sum = 0
3330 16:30:16.733108 9, 0xFFFF, sum = 0
3331 16:30:16.736498 10, 0xFFFF, sum = 0
3332 16:30:16.736569 11, 0xFFFF, sum = 0
3333 16:30:16.740062 12, 0x0, sum = 1
3334 16:30:16.740169 13, 0x0, sum = 2
3335 16:30:16.743754 14, 0x0, sum = 3
3336 16:30:16.743862 15, 0x0, sum = 4
3337 16:30:16.746685 best_step = 13
3338 16:30:16.746774
3339 16:30:16.746857 ==
3340 16:30:16.750116 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 16:30:16.753683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 16:30:16.753753 ==
3343 16:30:16.753810 RX Vref Scan: 1
3344 16:30:16.753866
3345 16:30:16.756619 Set Vref Range= 32 -> 127
3346 16:30:16.756688
3347 16:30:16.760217 RX Vref 32 -> 127, step: 1
3348 16:30:16.760295
3349 16:30:16.763580 RX Delay -5 -> 252, step: 4
3350 16:30:16.763648
3351 16:30:16.766899 Set Vref, RX VrefLevel [Byte0]: 32
3352 16:30:16.769725 [Byte1]: 32
3353 16:30:16.769794
3354 16:30:16.773311 Set Vref, RX VrefLevel [Byte0]: 33
3355 16:30:16.776375 [Byte1]: 33
3356 16:30:16.780067
3357 16:30:16.780167 Set Vref, RX VrefLevel [Byte0]: 34
3358 16:30:16.782918 [Byte1]: 34
3359 16:30:16.787845
3360 16:30:16.787952 Set Vref, RX VrefLevel [Byte0]: 35
3361 16:30:16.790797 [Byte1]: 35
3362 16:30:16.795753
3363 16:30:16.795854 Set Vref, RX VrefLevel [Byte0]: 36
3364 16:30:16.799022 [Byte1]: 36
3365 16:30:16.803798
3366 16:30:16.803902 Set Vref, RX VrefLevel [Byte0]: 37
3367 16:30:16.806504 [Byte1]: 37
3368 16:30:16.810956
3369 16:30:16.811058 Set Vref, RX VrefLevel [Byte0]: 38
3370 16:30:16.814764 [Byte1]: 38
3371 16:30:16.819197
3372 16:30:16.819297 Set Vref, RX VrefLevel [Byte0]: 39
3373 16:30:16.822681 [Byte1]: 39
3374 16:30:16.827034
3375 16:30:16.827132 Set Vref, RX VrefLevel [Byte0]: 40
3376 16:30:16.830582 [Byte1]: 40
3377 16:30:16.834983
3378 16:30:16.835082 Set Vref, RX VrefLevel [Byte0]: 41
3379 16:30:16.838008 [Byte1]: 41
3380 16:30:16.842418
3381 16:30:16.842515 Set Vref, RX VrefLevel [Byte0]: 42
3382 16:30:16.845992 [Byte1]: 42
3383 16:30:16.850253
3384 16:30:16.850350 Set Vref, RX VrefLevel [Byte0]: 43
3385 16:30:16.853936 [Byte1]: 43
3386 16:30:16.858251
3387 16:30:16.858351 Set Vref, RX VrefLevel [Byte0]: 44
3388 16:30:16.861832 [Byte1]: 44
3389 16:30:16.866305
3390 16:30:16.866400 Set Vref, RX VrefLevel [Byte0]: 45
3391 16:30:16.869809 [Byte1]: 45
3392 16:30:16.873963
3393 16:30:16.874067 Set Vref, RX VrefLevel [Byte0]: 46
3394 16:30:16.877561 [Byte1]: 46
3395 16:30:16.881770
3396 16:30:16.881840 Set Vref, RX VrefLevel [Byte0]: 47
3397 16:30:16.885370 [Byte1]: 47
3398 16:30:16.889790
3399 16:30:16.889884 Set Vref, RX VrefLevel [Byte0]: 48
3400 16:30:16.893217 [Byte1]: 48
3401 16:30:16.897579
3402 16:30:16.897678 Set Vref, RX VrefLevel [Byte0]: 49
3403 16:30:16.901264 [Byte1]: 49
3404 16:30:16.905583
3405 16:30:16.905687 Set Vref, RX VrefLevel [Byte0]: 50
3406 16:30:16.908859 [Byte1]: 50
3407 16:30:16.913474
3408 16:30:16.913576 Set Vref, RX VrefLevel [Byte0]: 51
3409 16:30:16.916959 [Byte1]: 51
3410 16:30:16.921204
3411 16:30:16.921304 Set Vref, RX VrefLevel [Byte0]: 52
3412 16:30:16.924770 [Byte1]: 52
3413 16:30:16.929053
3414 16:30:16.929149 Set Vref, RX VrefLevel [Byte0]: 53
3415 16:30:16.932033 [Byte1]: 53
3416 16:30:16.937093
3417 16:30:16.937171 Set Vref, RX VrefLevel [Byte0]: 54
3418 16:30:16.939972 [Byte1]: 54
3419 16:30:16.944972
3420 16:30:16.945049 Set Vref, RX VrefLevel [Byte0]: 55
3421 16:30:16.947866 [Byte1]: 55
3422 16:30:16.952896
3423 16:30:16.952983 Set Vref, RX VrefLevel [Byte0]: 56
3424 16:30:16.955735 [Byte1]: 56
3425 16:30:16.960122
3426 16:30:16.960199 Set Vref, RX VrefLevel [Byte0]: 57
3427 16:30:16.963710 [Byte1]: 57
3428 16:30:16.968145
3429 16:30:16.968221 Set Vref, RX VrefLevel [Byte0]: 58
3430 16:30:16.971728 [Byte1]: 58
3431 16:30:16.976054
3432 16:30:16.976130 Set Vref, RX VrefLevel [Byte0]: 59
3433 16:30:16.979500 [Byte1]: 59
3434 16:30:16.984386
3435 16:30:16.984482 Set Vref, RX VrefLevel [Byte0]: 60
3436 16:30:16.987266 [Byte1]: 60
3437 16:30:16.991739
3438 16:30:16.991839 Set Vref, RX VrefLevel [Byte0]: 61
3439 16:30:16.994779 [Byte1]: 61
3440 16:30:16.999895
3441 16:30:16.999999 Set Vref, RX VrefLevel [Byte0]: 62
3442 16:30:17.003220 [Byte1]: 62
3443 16:30:17.007586
3444 16:30:17.007684 Set Vref, RX VrefLevel [Byte0]: 63
3445 16:30:17.010614 [Byte1]: 63
3446 16:30:17.015158
3447 16:30:17.015237 Set Vref, RX VrefLevel [Byte0]: 64
3448 16:30:17.018720 [Byte1]: 64
3449 16:30:17.023409
3450 16:30:17.023509 Set Vref, RX VrefLevel [Byte0]: 65
3451 16:30:17.026736 [Byte1]: 65
3452 16:30:17.031004
3453 16:30:17.031101 Set Vref, RX VrefLevel [Byte0]: 66
3454 16:30:17.034296 [Byte1]: 66
3455 16:30:17.038740
3456 16:30:17.038847 Set Vref, RX VrefLevel [Byte0]: 67
3457 16:30:17.042246 [Byte1]: 67
3458 16:30:17.046585
3459 16:30:17.046663 Set Vref, RX VrefLevel [Byte0]: 68
3460 16:30:17.050152 [Byte1]: 68
3461 16:30:17.054597
3462 16:30:17.054663 Set Vref, RX VrefLevel [Byte0]: 69
3463 16:30:17.058176 [Byte1]: 69
3464 16:30:17.062192
3465 16:30:17.062280 Set Vref, RX VrefLevel [Byte0]: 70
3466 16:30:17.065730 [Byte1]: 70
3467 16:30:17.070733
3468 16:30:17.070828 Final RX Vref Byte 0 = 54 to rank0
3469 16:30:17.073613 Final RX Vref Byte 1 = 53 to rank0
3470 16:30:17.077378 Final RX Vref Byte 0 = 54 to rank1
3471 16:30:17.080141 Final RX Vref Byte 1 = 53 to rank1==
3472 16:30:17.083728 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 16:30:17.090125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 16:30:17.090201 ==
3475 16:30:17.090275 DQS Delay:
3476 16:30:17.090361 DQS0 = 0, DQS1 = 0
3477 16:30:17.093732 DQM Delay:
3478 16:30:17.093829 DQM0 = 120, DQM1 = 117
3479 16:30:17.096749 DQ Delay:
3480 16:30:17.100430 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3481 16:30:17.103365 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3482 16:30:17.106871 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3483 16:30:17.110419 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3484 16:30:17.110596
3485 16:30:17.110685
3486 16:30:17.116856 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3487 16:30:17.120004 CH1 RK0: MR19=404, MR18=114
3488 16:30:17.126769 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3489 16:30:17.126895
3490 16:30:17.130442 ----->DramcWriteLeveling(PI) begin...
3491 16:30:17.130542 ==
3492 16:30:17.133958 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 16:30:17.136589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 16:30:17.139888 ==
3495 16:30:17.139982 Write leveling (Byte 0): 26 => 26
3496 16:30:17.143208 Write leveling (Byte 1): 28 => 28
3497 16:30:17.146659 DramcWriteLeveling(PI) end<-----
3498 16:30:17.146730
3499 16:30:17.146789 ==
3500 16:30:17.150006 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 16:30:17.156271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 16:30:17.156373 ==
3503 16:30:17.160090 [Gating] SW mode calibration
3504 16:30:17.166871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 16:30:17.169699 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 16:30:17.176675 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 16:30:17.180258 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 16:30:17.182967 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 16:30:17.189647 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 16:30:17.193255 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 16:30:17.196817 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3512 16:30:17.203340 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (1 0) (0 1)
3513 16:30:17.206246 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
3514 16:30:17.210019 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 16:30:17.212969 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 16:30:17.219375 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 16:30:17.223054 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 16:30:17.229725 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 16:30:17.232696 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3520 16:30:17.236354 1 0 24 | B1->B0 | 4545 2d2d | 0 1 | (0 0) (0 0)
3521 16:30:17.239254 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 16:30:17.245853 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 16:30:17.249301 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 16:30:17.252727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 16:30:17.259506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 16:30:17.262918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 16:30:17.266206 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 16:30:17.272660 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3529 16:30:17.276167 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3530 16:30:17.279089 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 16:30:17.286080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 16:30:17.289494 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 16:30:17.292885 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 16:30:17.299216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 16:30:17.302781 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 16:30:17.306110 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 16:30:17.312735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 16:30:17.316402 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 16:30:17.319400 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 16:30:17.325712 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 16:30:17.329227 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 16:30:17.332923 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 16:30:17.335926 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3544 16:30:17.342454 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3545 16:30:17.346261 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3546 16:30:17.349281 Total UI for P1: 0, mck2ui 16
3547 16:30:17.352216 best dqsien dly found for B1: ( 1, 3, 22)
3548 16:30:17.355838 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 16:30:17.359375 Total UI for P1: 0, mck2ui 16
3550 16:30:17.362390 best dqsien dly found for B0: ( 1, 3, 26)
3551 16:30:17.365896 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3552 16:30:17.372239 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3553 16:30:17.372335
3554 16:30:17.375733 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3555 16:30:17.378558 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3556 16:30:17.382216 [Gating] SW calibration Done
3557 16:30:17.382286 ==
3558 16:30:17.385214 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 16:30:17.388953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 16:30:17.389058 ==
3561 16:30:17.391908 RX Vref Scan: 0
3562 16:30:17.391999
3563 16:30:17.392084 RX Vref 0 -> 0, step: 1
3564 16:30:17.392166
3565 16:30:17.395577 RX Delay -40 -> 252, step: 8
3566 16:30:17.399024 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3567 16:30:17.402446 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3568 16:30:17.408739 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3569 16:30:17.412161 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3570 16:30:17.415560 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3571 16:30:17.418951 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3572 16:30:17.421795 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3573 16:30:17.428426 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3574 16:30:17.432053 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3575 16:30:17.435412 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3576 16:30:17.438403 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3577 16:30:17.445042 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3578 16:30:17.448838 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3579 16:30:17.451728 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3580 16:30:17.455417 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3581 16:30:17.458411 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3582 16:30:17.458477 ==
3583 16:30:17.461990 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 16:30:17.468777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 16:30:17.468857 ==
3586 16:30:17.468918 DQS Delay:
3587 16:30:17.471652 DQS0 = 0, DQS1 = 0
3588 16:30:17.471752 DQM Delay:
3589 16:30:17.475410 DQM0 = 121, DQM1 = 117
3590 16:30:17.475499 DQ Delay:
3591 16:30:17.478313 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3592 16:30:17.481794 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3593 16:30:17.485087 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3594 16:30:17.488708 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3595 16:30:17.488782
3596 16:30:17.488848
3597 16:30:17.488902 ==
3598 16:30:17.491728 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 16:30:17.498426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 16:30:17.498496 ==
3601 16:30:17.498553
3602 16:30:17.498607
3603 16:30:17.498658 TX Vref Scan disable
3604 16:30:17.501474 == TX Byte 0 ==
3605 16:30:17.505047 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3606 16:30:17.511418 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3607 16:30:17.511560 == TX Byte 1 ==
3608 16:30:17.515058 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3609 16:30:17.521375 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3610 16:30:17.521475 ==
3611 16:30:17.524850 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 16:30:17.528323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 16:30:17.528429 ==
3614 16:30:17.539321 TX Vref=22, minBit 9, minWin=25, winSum=418
3615 16:30:17.542790 TX Vref=24, minBit 1, minWin=26, winSum=427
3616 16:30:17.546484 TX Vref=26, minBit 9, minWin=26, winSum=428
3617 16:30:17.549343 TX Vref=28, minBit 2, minWin=26, winSum=431
3618 16:30:17.553054 TX Vref=30, minBit 9, minWin=26, winSum=435
3619 16:30:17.555947 TX Vref=32, minBit 9, minWin=26, winSum=432
3620 16:30:17.563218 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3621 16:30:17.563324
3622 16:30:17.566246 Final TX Range 1 Vref 30
3623 16:30:17.566400
3624 16:30:17.566497 ==
3625 16:30:17.569823 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 16:30:17.572661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 16:30:17.572795 ==
3628 16:30:17.572892
3629 16:30:17.576055
3630 16:30:17.576170 TX Vref Scan disable
3631 16:30:17.579621 == TX Byte 0 ==
3632 16:30:17.582676 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3633 16:30:17.586229 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3634 16:30:17.589510 == TX Byte 1 ==
3635 16:30:17.592836 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3636 16:30:17.596151 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3637 16:30:17.596247
3638 16:30:17.599611 [DATLAT]
3639 16:30:17.599685 Freq=1200, CH1 RK1
3640 16:30:17.599745
3641 16:30:17.602453 DATLAT Default: 0xd
3642 16:30:17.602532 0, 0xFFFF, sum = 0
3643 16:30:17.606083 1, 0xFFFF, sum = 0
3644 16:30:17.606179 2, 0xFFFF, sum = 0
3645 16:30:17.609081 3, 0xFFFF, sum = 0
3646 16:30:17.609186 4, 0xFFFF, sum = 0
3647 16:30:17.612766 5, 0xFFFF, sum = 0
3648 16:30:17.615622 6, 0xFFFF, sum = 0
3649 16:30:17.615718 7, 0xFFFF, sum = 0
3650 16:30:17.619285 8, 0xFFFF, sum = 0
3651 16:30:17.619389 9, 0xFFFF, sum = 0
3652 16:30:17.622605 10, 0xFFFF, sum = 0
3653 16:30:17.622723 11, 0xFFFF, sum = 0
3654 16:30:17.625441 12, 0x0, sum = 1
3655 16:30:17.625540 13, 0x0, sum = 2
3656 16:30:17.629196 14, 0x0, sum = 3
3657 16:30:17.629294 15, 0x0, sum = 4
3658 16:30:17.629382 best_step = 13
3659 16:30:17.632805
3660 16:30:17.632901 ==
3661 16:30:17.635723 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 16:30:17.639396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 16:30:17.639493 ==
3664 16:30:17.639581 RX Vref Scan: 0
3665 16:30:17.639671
3666 16:30:17.642151 RX Vref 0 -> 0, step: 1
3667 16:30:17.642240
3668 16:30:17.645568 RX Delay -5 -> 252, step: 4
3669 16:30:17.648978 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3670 16:30:17.655762 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3671 16:30:17.659304 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3672 16:30:17.662326 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3673 16:30:17.665900 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3674 16:30:17.668940 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3675 16:30:17.672581 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3676 16:30:17.678920 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3677 16:30:17.682523 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3678 16:30:17.685993 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3679 16:30:17.688817 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3680 16:30:17.692405 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3681 16:30:17.699080 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3682 16:30:17.702495 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3683 16:30:17.705951 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3684 16:30:17.709159 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3685 16:30:17.709258 ==
3686 16:30:17.712585 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 16:30:17.718945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 16:30:17.719058 ==
3689 16:30:17.719147 DQS Delay:
3690 16:30:17.722530 DQS0 = 0, DQS1 = 0
3691 16:30:17.722611 DQM Delay:
3692 16:30:17.725367 DQM0 = 120, DQM1 = 118
3693 16:30:17.725474 DQ Delay:
3694 16:30:17.728923 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3695 16:30:17.732618 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3696 16:30:17.735397 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3697 16:30:17.739022 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3698 16:30:17.739096
3699 16:30:17.739181
3700 16:30:17.748955 [DQSOSCAuto] RK1, (LSB)MR18= 0x13ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 402 ps
3701 16:30:17.749037 CH1 RK1: MR19=403, MR18=13EF
3702 16:30:17.755847 CH1_RK1: MR19=0x403, MR18=0x13EF, DQSOSC=402, MR23=63, INC=40, DEC=27
3703 16:30:17.758666 [RxdqsGatingPostProcess] freq 1200
3704 16:30:17.765453 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 16:30:17.768932 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 16:30:17.772638 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 16:30:17.775403 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 16:30:17.779222 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 16:30:17.782227 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 16:30:17.782305 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 16:30:17.785727 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 16:30:17.788626 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 16:30:17.792281 Pre-setting of DQS Precalculation
3714 16:30:17.799353 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 16:30:17.805960 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 16:30:17.812332 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 16:30:17.812431
3718 16:30:17.812522
3719 16:30:17.815671 [Calibration Summary] 2400 Mbps
3720 16:30:17.815769 CH 0, Rank 0
3721 16:30:17.819131 SW Impedance : PASS
3722 16:30:17.822564 DUTY Scan : NO K
3723 16:30:17.822661 ZQ Calibration : PASS
3724 16:30:17.825405 Jitter Meter : NO K
3725 16:30:17.828650 CBT Training : PASS
3726 16:30:17.828728 Write leveling : PASS
3727 16:30:17.832403 RX DQS gating : PASS
3728 16:30:17.835658 RX DQ/DQS(RDDQC) : PASS
3729 16:30:17.835736 TX DQ/DQS : PASS
3730 16:30:17.839034 RX DATLAT : PASS
3731 16:30:17.842481 RX DQ/DQS(Engine): PASS
3732 16:30:17.842559 TX OE : NO K
3733 16:30:17.845243 All Pass.
3734 16:30:17.845321
3735 16:30:17.845382 CH 0, Rank 1
3736 16:30:17.848926 SW Impedance : PASS
3737 16:30:17.849004 DUTY Scan : NO K
3738 16:30:17.851805 ZQ Calibration : PASS
3739 16:30:17.855344 Jitter Meter : NO K
3740 16:30:17.855422 CBT Training : PASS
3741 16:30:17.859027 Write leveling : PASS
3742 16:30:17.861796 RX DQS gating : PASS
3743 16:30:17.861874 RX DQ/DQS(RDDQC) : PASS
3744 16:30:17.865274 TX DQ/DQS : PASS
3745 16:30:17.865352 RX DATLAT : PASS
3746 16:30:17.868598 RX DQ/DQS(Engine): PASS
3747 16:30:17.872028 TX OE : NO K
3748 16:30:17.872136 All Pass.
3749 16:30:17.872234
3750 16:30:17.872322 CH 1, Rank 0
3751 16:30:17.874843 SW Impedance : PASS
3752 16:30:17.878338 DUTY Scan : NO K
3753 16:30:17.878420 ZQ Calibration : PASS
3754 16:30:17.882046 Jitter Meter : NO K
3755 16:30:17.885007 CBT Training : PASS
3756 16:30:17.885085 Write leveling : PASS
3757 16:30:17.888501 RX DQS gating : PASS
3758 16:30:17.892121 RX DQ/DQS(RDDQC) : PASS
3759 16:30:17.892198 TX DQ/DQS : PASS
3760 16:30:17.895099 RX DATLAT : PASS
3761 16:30:17.898641 RX DQ/DQS(Engine): PASS
3762 16:30:17.898719 TX OE : NO K
3763 16:30:17.902071 All Pass.
3764 16:30:17.902150
3765 16:30:17.902225 CH 1, Rank 1
3766 16:30:17.904957 SW Impedance : PASS
3767 16:30:17.905034 DUTY Scan : NO K
3768 16:30:17.908759 ZQ Calibration : PASS
3769 16:30:17.911700 Jitter Meter : NO K
3770 16:30:17.911779 CBT Training : PASS
3771 16:30:17.914734 Write leveling : PASS
3772 16:30:17.918451 RX DQS gating : PASS
3773 16:30:17.918528 RX DQ/DQS(RDDQC) : PASS
3774 16:30:17.921949 TX DQ/DQS : PASS
3775 16:30:17.922028 RX DATLAT : PASS
3776 16:30:17.924757 RX DQ/DQS(Engine): PASS
3777 16:30:17.928226 TX OE : NO K
3778 16:30:17.928305 All Pass.
3779 16:30:17.928366
3780 16:30:17.932033 DramC Write-DBI off
3781 16:30:17.932111 PER_BANK_REFRESH: Hybrid Mode
3782 16:30:17.935061 TX_TRACKING: ON
3783 16:30:17.944918 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 16:30:17.948105 [FAST_K] Save calibration result to emmc
3785 16:30:17.951492 dramc_set_vcore_voltage set vcore to 650000
3786 16:30:17.951570 Read voltage for 600, 5
3787 16:30:17.954684 Vio18 = 0
3788 16:30:17.954783 Vcore = 650000
3789 16:30:17.954871 Vdram = 0
3790 16:30:17.958475 Vddq = 0
3791 16:30:17.958574 Vmddr = 0
3792 16:30:17.961975 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 16:30:17.968382 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 16:30:17.971781 MEM_TYPE=3, freq_sel=19
3795 16:30:17.974830 sv_algorithm_assistance_LP4_1600
3796 16:30:17.978271 ============ PULL DRAM RESETB DOWN ============
3797 16:30:17.981783 ========== PULL DRAM RESETB DOWN end =========
3798 16:30:17.988575 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 16:30:17.992028 ===================================
3800 16:30:17.992111 LPDDR4 DRAM CONFIGURATION
3801 16:30:17.994908 ===================================
3802 16:30:17.998446 EX_ROW_EN[0] = 0x0
3803 16:30:17.998541 EX_ROW_EN[1] = 0x0
3804 16:30:18.001317 LP4Y_EN = 0x0
3805 16:30:18.001413 WORK_FSP = 0x0
3806 16:30:18.004935 WL = 0x2
3807 16:30:18.007839 RL = 0x2
3808 16:30:18.007933 BL = 0x2
3809 16:30:18.011159 RPST = 0x0
3810 16:30:18.011259 RD_PRE = 0x0
3811 16:30:18.014804 WR_PRE = 0x1
3812 16:30:18.014905 WR_PST = 0x0
3813 16:30:18.018380 DBI_WR = 0x0
3814 16:30:18.018478 DBI_RD = 0x0
3815 16:30:18.021283 OTF = 0x1
3816 16:30:18.024959 ===================================
3817 16:30:18.028435 ===================================
3818 16:30:18.028535 ANA top config
3819 16:30:18.031056 ===================================
3820 16:30:18.034601 DLL_ASYNC_EN = 0
3821 16:30:18.038150 ALL_SLAVE_EN = 1
3822 16:30:18.038246 NEW_RANK_MODE = 1
3823 16:30:18.041730 DLL_IDLE_MODE = 1
3824 16:30:18.044658 LP45_APHY_COMB_EN = 1
3825 16:30:18.048293 TX_ODT_DIS = 1
3826 16:30:18.048369 NEW_8X_MODE = 1
3827 16:30:18.051147 ===================================
3828 16:30:18.054772 ===================================
3829 16:30:18.058312 data_rate = 1200
3830 16:30:18.061210 CKR = 1
3831 16:30:18.064713 DQ_P2S_RATIO = 8
3832 16:30:18.068143 ===================================
3833 16:30:18.071429 CA_P2S_RATIO = 8
3834 16:30:18.074759 DQ_CA_OPEN = 0
3835 16:30:18.078228 DQ_SEMI_OPEN = 0
3836 16:30:18.078307 CA_SEMI_OPEN = 0
3837 16:30:18.081256 CA_FULL_RATE = 0
3838 16:30:18.084524 DQ_CKDIV4_EN = 1
3839 16:30:18.087593 CA_CKDIV4_EN = 1
3840 16:30:18.090996 CA_PREDIV_EN = 0
3841 16:30:18.091066 PH8_DLY = 0
3842 16:30:18.094518 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 16:30:18.097848 DQ_AAMCK_DIV = 4
3844 16:30:18.101174 CA_AAMCK_DIV = 4
3845 16:30:18.104350 CA_ADMCK_DIV = 4
3846 16:30:18.107714 DQ_TRACK_CA_EN = 0
3847 16:30:18.111354 CA_PICK = 600
3848 16:30:18.111432 CA_MCKIO = 600
3849 16:30:18.114315 MCKIO_SEMI = 0
3850 16:30:18.117922 PLL_FREQ = 2288
3851 16:30:18.120830 DQ_UI_PI_RATIO = 32
3852 16:30:18.124457 CA_UI_PI_RATIO = 0
3853 16:30:18.127386 ===================================
3854 16:30:18.130971 ===================================
3855 16:30:18.134493 memory_type:LPDDR4
3856 16:30:18.134597 GP_NUM : 10
3857 16:30:18.138170 SRAM_EN : 1
3858 16:30:18.138267 MD32_EN : 0
3859 16:30:18.140874 ===================================
3860 16:30:18.144521 [ANA_INIT] >>>>>>>>>>>>>>
3861 16:30:18.147393 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 16:30:18.151121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 16:30:18.154672 ===================================
3864 16:30:18.157515 data_rate = 1200,PCW = 0X5800
3865 16:30:18.161216 ===================================
3866 16:30:18.164117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 16:30:18.167854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 16:30:18.174312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 16:30:18.180763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 16:30:18.183805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 16:30:18.187240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 16:30:18.187343 [ANA_INIT] flow start
3873 16:30:18.190628 [ANA_INIT] PLL >>>>>>>>
3874 16:30:18.194188 [ANA_INIT] PLL <<<<<<<<
3875 16:30:18.194294 [ANA_INIT] MIDPI >>>>>>>>
3876 16:30:18.197075 [ANA_INIT] MIDPI <<<<<<<<
3877 16:30:18.200582 [ANA_INIT] DLL >>>>>>>>
3878 16:30:18.200692 [ANA_INIT] flow end
3879 16:30:18.207265 ============ LP4 DIFF to SE enter ============
3880 16:30:18.210729 ============ LP4 DIFF to SE exit ============
3881 16:30:18.210828 [ANA_INIT] <<<<<<<<<<<<<
3882 16:30:18.214143 [Flow] Enable top DCM control >>>>>
3883 16:30:18.217447 [Flow] Enable top DCM control <<<<<
3884 16:30:18.220561 Enable DLL master slave shuffle
3885 16:30:18.226946 ==============================================================
3886 16:30:18.230237 Gating Mode config
3887 16:30:18.233610 ==============================================================
3888 16:30:18.237224 Config description:
3889 16:30:18.246598 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 16:30:18.254015 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 16:30:18.256844 SELPH_MODE 0: By rank 1: By Phase
3892 16:30:18.263307 ==============================================================
3893 16:30:18.267060 GAT_TRACK_EN = 1
3894 16:30:18.270011 RX_GATING_MODE = 2
3895 16:30:18.273767 RX_GATING_TRACK_MODE = 2
3896 16:30:18.273927 SELPH_MODE = 1
3897 16:30:18.276617 PICG_EARLY_EN = 1
3898 16:30:18.280168 VALID_LAT_VALUE = 1
3899 16:30:18.286796 ==============================================================
3900 16:30:18.289767 Enter into Gating configuration >>>>
3901 16:30:18.293460 Exit from Gating configuration <<<<
3902 16:30:18.297157 Enter into DVFS_PRE_config >>>>>
3903 16:30:18.306781 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 16:30:18.310332 Exit from DVFS_PRE_config <<<<<
3905 16:30:18.313900 Enter into PICG configuration >>>>
3906 16:30:18.316755 Exit from PICG configuration <<<<
3907 16:30:18.320177 [RX_INPUT] configuration >>>>>
3908 16:30:18.323226 [RX_INPUT] configuration <<<<<
3909 16:30:18.327027 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 16:30:18.333387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 16:30:18.340245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 16:30:18.346625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 16:30:18.349897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 16:30:18.356540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 16:30:18.360142 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 16:30:18.366703 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 16:30:18.369769 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 16:30:18.372865 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 16:30:18.379562 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 16:30:18.383116 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 16:30:18.386092 ===================================
3922 16:30:18.389869 LPDDR4 DRAM CONFIGURATION
3923 16:30:18.392768 ===================================
3924 16:30:18.392871 EX_ROW_EN[0] = 0x0
3925 16:30:18.396520 EX_ROW_EN[1] = 0x0
3926 16:30:18.396617 LP4Y_EN = 0x0
3927 16:30:18.399455 WORK_FSP = 0x0
3928 16:30:18.399553 WL = 0x2
3929 16:30:18.403155 RL = 0x2
3930 16:30:18.403262 BL = 0x2
3931 16:30:18.406182 RPST = 0x0
3932 16:30:18.406290 RD_PRE = 0x0
3933 16:30:18.410039 WR_PRE = 0x1
3934 16:30:18.410120 WR_PST = 0x0
3935 16:30:18.412962 DBI_WR = 0x0
3936 16:30:18.413065 DBI_RD = 0x0
3937 16:30:18.416050 OTF = 0x1
3938 16:30:18.419675 ===================================
3939 16:30:18.422683 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 16:30:18.426387 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 16:30:18.432711 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 16:30:18.436350 ===================================
3943 16:30:18.436429 LPDDR4 DRAM CONFIGURATION
3944 16:30:18.439360 ===================================
3945 16:30:18.443059 EX_ROW_EN[0] = 0x10
3946 16:30:18.445974 EX_ROW_EN[1] = 0x0
3947 16:30:18.446054 LP4Y_EN = 0x0
3948 16:30:18.449720 WORK_FSP = 0x0
3949 16:30:18.449800 WL = 0x2
3950 16:30:18.452737 RL = 0x2
3951 16:30:18.452811 BL = 0x2
3952 16:30:18.455796 RPST = 0x0
3953 16:30:18.455877 RD_PRE = 0x0
3954 16:30:18.459436 WR_PRE = 0x1
3955 16:30:18.459508 WR_PST = 0x0
3956 16:30:18.463041 DBI_WR = 0x0
3957 16:30:18.463118 DBI_RD = 0x0
3958 16:30:18.465884 OTF = 0x1
3959 16:30:18.469161 ===================================
3960 16:30:18.475832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 16:30:18.479213 nWR fixed to 30
3962 16:30:18.482456 [ModeRegInit_LP4] CH0 RK0
3963 16:30:18.482536 [ModeRegInit_LP4] CH0 RK1
3964 16:30:18.485748 [ModeRegInit_LP4] CH1 RK0
3965 16:30:18.489445 [ModeRegInit_LP4] CH1 RK1
3966 16:30:18.489563 match AC timing 17
3967 16:30:18.496084 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 16:30:18.499353 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 16:30:18.502577 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 16:30:18.509217 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 16:30:18.512967 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 16:30:18.513041 ==
3973 16:30:18.515868 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 16:30:18.518858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 16:30:18.518931 ==
3976 16:30:18.525595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 16:30:18.532359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3978 16:30:18.536007 [CA 0] Center 35 (5~66) winsize 62
3979 16:30:18.539341 [CA 1] Center 35 (5~66) winsize 62
3980 16:30:18.542430 [CA 2] Center 34 (3~65) winsize 63
3981 16:30:18.546127 [CA 3] Center 33 (2~64) winsize 63
3982 16:30:18.549043 [CA 4] Center 33 (2~64) winsize 63
3983 16:30:18.552844 [CA 5] Center 32 (2~63) winsize 62
3984 16:30:18.552926
3985 16:30:18.555725 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3986 16:30:18.555797
3987 16:30:18.559231 [CATrainingPosCal] consider 1 rank data
3988 16:30:18.563052 u2DelayCellTimex100 = 270/100 ps
3989 16:30:18.565951 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3990 16:30:18.568922 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3991 16:30:18.572598 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3992 16:30:18.575646 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3993 16:30:18.579350 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3994 16:30:18.582282 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3995 16:30:18.582363
3996 16:30:18.589042 CA PerBit enable=1, Macro0, CA PI delay=32
3997 16:30:18.589122
3998 16:30:18.589182 [CBTSetCACLKResult] CA Dly = 32
3999 16:30:18.592800 CS Dly: 4 (0~35)
4000 16:30:18.592888 ==
4001 16:30:18.595723 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 16:30:18.599362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 16:30:18.599456 ==
4004 16:30:18.605934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 16:30:18.612511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 16:30:18.615848 [CA 0] Center 35 (5~66) winsize 62
4007 16:30:18.619170 [CA 1] Center 35 (5~66) winsize 62
4008 16:30:18.622255 [CA 2] Center 34 (3~65) winsize 63
4009 16:30:18.625954 [CA 3] Center 33 (3~64) winsize 62
4010 16:30:18.629295 [CA 4] Center 33 (2~64) winsize 63
4011 16:30:18.632532 [CA 5] Center 32 (2~63) winsize 62
4012 16:30:18.632642
4013 16:30:18.635491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 16:30:18.635604
4015 16:30:18.639317 [CATrainingPosCal] consider 2 rank data
4016 16:30:18.642298 u2DelayCellTimex100 = 270/100 ps
4017 16:30:18.645684 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4018 16:30:18.649323 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4019 16:30:18.652335 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4020 16:30:18.655423 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4021 16:30:18.658980 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4022 16:30:18.661986 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4023 16:30:18.665755
4024 16:30:18.668825 CA PerBit enable=1, Macro0, CA PI delay=32
4025 16:30:18.668904
4026 16:30:18.672474 [CBTSetCACLKResult] CA Dly = 32
4027 16:30:18.672554 CS Dly: 4 (0~36)
4028 16:30:18.672615
4029 16:30:18.675442 ----->DramcWriteLeveling(PI) begin...
4030 16:30:18.675521 ==
4031 16:30:18.679026 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 16:30:18.682666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 16:30:18.685447 ==
4034 16:30:18.685557 Write leveling (Byte 0): 32 => 32
4035 16:30:18.689158 Write leveling (Byte 1): 32 => 32
4036 16:30:18.692087 DramcWriteLeveling(PI) end<-----
4037 16:30:18.692165
4038 16:30:18.692226 ==
4039 16:30:18.695842 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 16:30:18.699573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 16:30:18.702548 ==
4042 16:30:18.702627 [Gating] SW mode calibration
4043 16:30:18.712208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 16:30:18.715892 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 16:30:18.719007 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 16:30:18.725725 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 16:30:18.729371 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 16:30:18.732198 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4049 16:30:18.739088 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
4050 16:30:18.742390 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 16:30:18.745363 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 16:30:18.751935 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 16:30:18.755262 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 16:30:18.758529 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 16:30:18.765500 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 16:30:18.768604 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4057 16:30:18.771974 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4058 16:30:18.779215 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 16:30:18.782231 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 16:30:18.785918 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 16:30:18.792412 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 16:30:18.795362 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 16:30:18.798992 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 16:30:18.805779 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 16:30:18.808790 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4066 16:30:18.811770 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 16:30:18.815446 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 16:30:18.822105 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 16:30:18.825067 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 16:30:18.828692 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 16:30:18.835435 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 16:30:18.838484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 16:30:18.842125 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 16:30:18.848178 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 16:30:18.851541 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 16:30:18.854970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 16:30:18.861466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 16:30:18.865127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 16:30:18.867937 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 16:30:18.874976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4081 16:30:18.878422 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 16:30:18.881787 Total UI for P1: 0, mck2ui 16
4083 16:30:18.885034 best dqsien dly found for B0: ( 0, 13, 12)
4084 16:30:18.888132 Total UI for P1: 0, mck2ui 16
4085 16:30:18.891313 best dqsien dly found for B1: ( 0, 13, 14)
4086 16:30:18.894570 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4087 16:30:18.898261 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4088 16:30:18.898339
4089 16:30:18.901407 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4090 16:30:18.908181 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4091 16:30:18.908294 [Gating] SW calibration Done
4092 16:30:18.908385 ==
4093 16:30:18.911625 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 16:30:18.918238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 16:30:18.918320 ==
4096 16:30:18.918382 RX Vref Scan: 0
4097 16:30:18.918440
4098 16:30:18.921201 RX Vref 0 -> 0, step: 1
4099 16:30:18.921292
4100 16:30:18.924876 RX Delay -230 -> 252, step: 16
4101 16:30:18.927826 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4102 16:30:18.931580 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4103 16:30:18.934675 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4104 16:30:18.941284 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4105 16:30:18.944907 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4106 16:30:18.947847 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4107 16:30:18.951498 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4108 16:30:18.957944 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4109 16:30:18.960880 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4110 16:30:18.964614 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4111 16:30:18.967460 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4112 16:30:18.971194 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4113 16:30:18.977865 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4114 16:30:18.980878 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4115 16:30:18.984693 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4116 16:30:18.987612 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4117 16:30:18.991573 ==
4118 16:30:18.994466 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 16:30:18.998102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 16:30:18.998180 ==
4121 16:30:18.998241 DQS Delay:
4122 16:30:19.001141 DQS0 = 0, DQS1 = 0
4123 16:30:19.001218 DQM Delay:
4124 16:30:19.004081 DQM0 = 52, DQM1 = 46
4125 16:30:19.004184 DQ Delay:
4126 16:30:19.007709 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4127 16:30:19.011058 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4128 16:30:19.013911 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4129 16:30:19.017494 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4130 16:30:19.017599
4131 16:30:19.017684
4132 16:30:19.017765 ==
4133 16:30:19.020901 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 16:30:19.024285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 16:30:19.024363 ==
4136 16:30:19.024425
4137 16:30:19.024480
4138 16:30:19.027702 TX Vref Scan disable
4139 16:30:19.031046 == TX Byte 0 ==
4140 16:30:19.034218 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4141 16:30:19.037268 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4142 16:30:19.040765 == TX Byte 1 ==
4143 16:30:19.043748 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4144 16:30:19.046973 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4145 16:30:19.047051 ==
4146 16:30:19.050826 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 16:30:19.057109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 16:30:19.057189 ==
4149 16:30:19.057250
4150 16:30:19.057306
4151 16:30:19.057358 TX Vref Scan disable
4152 16:30:19.061371 == TX Byte 0 ==
4153 16:30:19.065101 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4154 16:30:19.068075 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4155 16:30:19.071969 == TX Byte 1 ==
4156 16:30:19.074942 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4157 16:30:19.078106 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4158 16:30:19.078183
4159 16:30:19.081817 [DATLAT]
4160 16:30:19.081895 Freq=600, CH0 RK0
4161 16:30:19.081957
4162 16:30:19.084834 DATLAT Default: 0x9
4163 16:30:19.084911 0, 0xFFFF, sum = 0
4164 16:30:19.088387 1, 0xFFFF, sum = 0
4165 16:30:19.088467 2, 0xFFFF, sum = 0
4166 16:30:19.091415 3, 0xFFFF, sum = 0
4167 16:30:19.091494 4, 0xFFFF, sum = 0
4168 16:30:19.095145 5, 0xFFFF, sum = 0
4169 16:30:19.095223 6, 0xFFFF, sum = 0
4170 16:30:19.098057 7, 0xFFFF, sum = 0
4171 16:30:19.098136 8, 0x0, sum = 1
4172 16:30:19.101545 9, 0x0, sum = 2
4173 16:30:19.101632 10, 0x0, sum = 3
4174 16:30:19.105147 11, 0x0, sum = 4
4175 16:30:19.105253 best_step = 9
4176 16:30:19.105340
4177 16:30:19.105423 ==
4178 16:30:19.108199 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 16:30:19.114901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 16:30:19.114980 ==
4181 16:30:19.115042 RX Vref Scan: 1
4182 16:30:19.115098
4183 16:30:19.118510 RX Vref 0 -> 0, step: 1
4184 16:30:19.118588
4185 16:30:19.121481 RX Delay -163 -> 252, step: 8
4186 16:30:19.121586
4187 16:30:19.125256 Set Vref, RX VrefLevel [Byte0]: 55
4188 16:30:19.127890 [Byte1]: 49
4189 16:30:19.127968
4190 16:30:19.131354 Final RX Vref Byte 0 = 55 to rank0
4191 16:30:19.135033 Final RX Vref Byte 1 = 49 to rank0
4192 16:30:19.138059 Final RX Vref Byte 0 = 55 to rank1
4193 16:30:19.141515 Final RX Vref Byte 1 = 49 to rank1==
4194 16:30:19.144431 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 16:30:19.147988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 16:30:19.148066 ==
4197 16:30:19.151573 DQS Delay:
4198 16:30:19.151650 DQS0 = 0, DQS1 = 0
4199 16:30:19.151711 DQM Delay:
4200 16:30:19.154902 DQM0 = 52, DQM1 = 46
4201 16:30:19.154979 DQ Delay:
4202 16:30:19.158319 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4203 16:30:19.161138 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4204 16:30:19.164700 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4205 16:30:19.167916 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4206 16:30:19.167991
4207 16:30:19.168050
4208 16:30:19.177820 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4209 16:30:19.177898 CH0 RK0: MR19=808, MR18=7366
4210 16:30:19.184268 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4211 16:30:19.184361
4212 16:30:19.187802 ----->DramcWriteLeveling(PI) begin...
4213 16:30:19.190958 ==
4214 16:30:19.191036 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 16:30:19.197662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 16:30:19.197744 ==
4217 16:30:19.201280 Write leveling (Byte 0): 35 => 35
4218 16:30:19.204843 Write leveling (Byte 1): 30 => 30
4219 16:30:19.204920 DramcWriteLeveling(PI) end<-----
4220 16:30:19.207723
4221 16:30:19.207798 ==
4222 16:30:19.211378 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 16:30:19.214185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 16:30:19.214261 ==
4225 16:30:19.217812 [Gating] SW mode calibration
4226 16:30:19.224415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 16:30:19.227552 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4228 16:30:19.234103 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 16:30:19.237709 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 16:30:19.241375 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 16:30:19.247779 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 0)
4232 16:30:19.251297 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4233 16:30:19.254189 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 16:30:19.260770 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 16:30:19.264379 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 16:30:19.267399 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 16:30:19.274003 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 16:30:19.277698 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 16:30:19.281234 0 10 12 | B1->B0 | 2828 2b2b | 0 1 | (0 0) (0 0)
4240 16:30:19.287843 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4241 16:30:19.290771 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 16:30:19.294199 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 16:30:19.300857 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 16:30:19.304222 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 16:30:19.307534 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 16:30:19.314440 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4247 16:30:19.317528 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 16:30:19.320708 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4249 16:30:19.324237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:30:19.330954 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 16:30:19.333973 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 16:30:19.337688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 16:30:19.344190 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 16:30:19.347862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 16:30:19.350830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 16:30:19.357463 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 16:30:19.361193 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 16:30:19.364254 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 16:30:19.370664 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 16:30:19.374205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 16:30:19.377110 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 16:30:19.383843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 16:30:19.387431 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 16:30:19.391025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 16:30:19.394088 Total UI for P1: 0, mck2ui 16
4266 16:30:19.397681 best dqsien dly found for B0: ( 0, 13, 14)
4267 16:30:19.400695 Total UI for P1: 0, mck2ui 16
4268 16:30:19.404163 best dqsien dly found for B1: ( 0, 13, 14)
4269 16:30:19.406954 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4270 16:30:19.410958 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4271 16:30:19.411106
4272 16:30:19.417193 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4273 16:30:19.420186 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4274 16:30:19.423908 [Gating] SW calibration Done
4275 16:30:19.423989 ==
4276 16:30:19.427169 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 16:30:19.430470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 16:30:19.430545 ==
4279 16:30:19.430630 RX Vref Scan: 0
4280 16:30:19.430704
4281 16:30:19.433814 RX Vref 0 -> 0, step: 1
4282 16:30:19.433882
4283 16:30:19.437117 RX Delay -230 -> 252, step: 16
4284 16:30:19.440490 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4285 16:30:19.443828 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4286 16:30:19.450725 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4287 16:30:19.454066 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4288 16:30:19.456936 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4289 16:30:19.460415 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4290 16:30:19.466953 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4291 16:30:19.470010 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4292 16:30:19.473728 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4293 16:30:19.477373 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4294 16:30:19.480150 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4295 16:30:19.487335 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4296 16:30:19.490200 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4297 16:30:19.493808 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4298 16:30:19.496691 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4299 16:30:19.503480 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4300 16:30:19.503558 ==
4301 16:30:19.507136 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 16:30:19.510041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 16:30:19.510116 ==
4304 16:30:19.510176 DQS Delay:
4305 16:30:19.513365 DQS0 = 0, DQS1 = 0
4306 16:30:19.513463 DQM Delay:
4307 16:30:19.517204 DQM0 = 52, DQM1 = 45
4308 16:30:19.517298 DQ Delay:
4309 16:30:19.520097 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4310 16:30:19.523254 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4311 16:30:19.527068 DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =41
4312 16:30:19.530178 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4313 16:30:19.530288
4314 16:30:19.530386
4315 16:30:19.530484 ==
4316 16:30:19.533804 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 16:30:19.536729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 16:30:19.536842 ==
4319 16:30:19.540334
4320 16:30:19.540430
4321 16:30:19.540516 TX Vref Scan disable
4322 16:30:19.543844 == TX Byte 0 ==
4323 16:30:19.546902 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4324 16:30:19.550015 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4325 16:30:19.553729 == TX Byte 1 ==
4326 16:30:19.556639 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4327 16:30:19.560280 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4328 16:30:19.560362 ==
4329 16:30:19.563528 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 16:30:19.570105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 16:30:19.570189 ==
4332 16:30:19.570251
4333 16:30:19.570306
4334 16:30:19.570359 TX Vref Scan disable
4335 16:30:19.575047 == TX Byte 0 ==
4336 16:30:19.578180 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4337 16:30:19.585213 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4338 16:30:19.585311 == TX Byte 1 ==
4339 16:30:19.588037 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4340 16:30:19.591534 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4341 16:30:19.595097
4342 16:30:19.595181 [DATLAT]
4343 16:30:19.595243 Freq=600, CH0 RK1
4344 16:30:19.595301
4345 16:30:19.597900 DATLAT Default: 0x9
4346 16:30:19.597983 0, 0xFFFF, sum = 0
4347 16:30:19.601394 1, 0xFFFF, sum = 0
4348 16:30:19.601501 2, 0xFFFF, sum = 0
4349 16:30:19.605017 3, 0xFFFF, sum = 0
4350 16:30:19.605105 4, 0xFFFF, sum = 0
4351 16:30:19.607944 5, 0xFFFF, sum = 0
4352 16:30:19.611437 6, 0xFFFF, sum = 0
4353 16:30:19.611539 7, 0xFFFF, sum = 0
4354 16:30:19.611628 8, 0x0, sum = 1
4355 16:30:19.615160 9, 0x0, sum = 2
4356 16:30:19.615272 10, 0x0, sum = 3
4357 16:30:19.617976 11, 0x0, sum = 4
4358 16:30:19.618079 best_step = 9
4359 16:30:19.618166
4360 16:30:19.618258 ==
4361 16:30:19.621954 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 16:30:19.628249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 16:30:19.628357 ==
4364 16:30:19.628447 RX Vref Scan: 0
4365 16:30:19.628533
4366 16:30:19.631967 RX Vref 0 -> 0, step: 1
4367 16:30:19.632034
4368 16:30:19.634936 RX Delay -163 -> 252, step: 8
4369 16:30:19.638579 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4370 16:30:19.641565 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4371 16:30:19.647861 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4372 16:30:19.651371 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4373 16:30:19.654958 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4374 16:30:19.657854 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4375 16:30:19.661440 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4376 16:30:19.667870 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4377 16:30:19.671584 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4378 16:30:19.674519 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4379 16:30:19.678038 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4380 16:30:19.684368 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4381 16:30:19.687610 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4382 16:30:19.690842 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4383 16:30:19.694073 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4384 16:30:19.697922 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4385 16:30:19.701037 ==
4386 16:30:19.704350 Dram Type= 6, Freq= 0, CH_0, rank 1
4387 16:30:19.707592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 16:30:19.707695 ==
4389 16:30:19.707785 DQS Delay:
4390 16:30:19.711208 DQS0 = 0, DQS1 = 0
4391 16:30:19.711300 DQM Delay:
4392 16:30:19.731157 DQM0 = 53, DQM1 = 46
4393 16:30:19.731248 DQ Delay:
4394 16:30:19.731308 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4395 16:30:19.731368 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4396 16:30:19.731421 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4397 16:30:19.731473 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4398 16:30:19.731524
4399 16:30:19.731575
4400 16:30:19.734255 [DQSOSCAuto] RK1, (LSB)MR18= 0x6424, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4401 16:30:19.737948 CH0 RK1: MR19=808, MR18=6424
4402 16:30:19.744471 CH0_RK1: MR19=0x808, MR18=0x6424, DQSOSC=391, MR23=63, INC=171, DEC=114
4403 16:30:19.747417 [RxdqsGatingPostProcess] freq 600
4404 16:30:19.753939 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4405 16:30:19.754013 Pre-setting of DQS Precalculation
4406 16:30:19.761007 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4407 16:30:19.761088 ==
4408 16:30:19.763888 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 16:30:19.767752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 16:30:19.767830 ==
4411 16:30:19.774393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4412 16:30:19.781011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4413 16:30:19.783992 [CA 0] Center 35 (5~66) winsize 62
4414 16:30:19.787780 [CA 1] Center 36 (6~67) winsize 62
4415 16:30:19.790833 [CA 2] Center 34 (4~65) winsize 62
4416 16:30:19.793808 [CA 3] Center 34 (4~65) winsize 62
4417 16:30:19.797411 [CA 4] Center 34 (4~65) winsize 62
4418 16:30:19.800771 [CA 5] Center 34 (4~64) winsize 61
4419 16:30:19.800866
4420 16:30:19.804264 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4421 16:30:19.804360
4422 16:30:19.807217 [CATrainingPosCal] consider 1 rank data
4423 16:30:19.810686 u2DelayCellTimex100 = 270/100 ps
4424 16:30:19.813844 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4425 16:30:19.817629 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4426 16:30:19.820440 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4427 16:30:19.823826 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4428 16:30:19.827328 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4429 16:30:19.830579 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4430 16:30:19.830684
4431 16:30:19.837324 CA PerBit enable=1, Macro0, CA PI delay=34
4432 16:30:19.837424
4433 16:30:19.837519 [CBTSetCACLKResult] CA Dly = 34
4434 16:30:19.840416 CS Dly: 5 (0~36)
4435 16:30:19.840526 ==
4436 16:30:19.843614 Dram Type= 6, Freq= 0, CH_1, rank 1
4437 16:30:19.847273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 16:30:19.847371 ==
4439 16:30:19.853711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4440 16:30:19.860994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4441 16:30:19.863912 [CA 0] Center 36 (5~67) winsize 63
4442 16:30:19.866954 [CA 1] Center 36 (6~67) winsize 62
4443 16:30:19.870559 [CA 2] Center 35 (4~66) winsize 63
4444 16:30:19.874279 [CA 3] Center 35 (4~66) winsize 63
4445 16:30:19.877186 [CA 4] Center 35 (4~66) winsize 63
4446 16:30:19.881036 [CA 5] Center 34 (4~65) winsize 62
4447 16:30:19.881141
4448 16:30:19.883911 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4449 16:30:19.883981
4450 16:30:19.887632 [CATrainingPosCal] consider 2 rank data
4451 16:30:19.890498 u2DelayCellTimex100 = 270/100 ps
4452 16:30:19.893657 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4453 16:30:19.897246 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4454 16:30:19.900261 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4455 16:30:19.903850 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4456 16:30:19.907513 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4457 16:30:19.910982 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4458 16:30:19.911064
4459 16:30:19.917128 CA PerBit enable=1, Macro0, CA PI delay=34
4460 16:30:19.917213
4461 16:30:19.917275 [CBTSetCACLKResult] CA Dly = 34
4462 16:30:19.920742 CS Dly: 6 (0~38)
4463 16:30:19.920845
4464 16:30:19.923784 ----->DramcWriteLeveling(PI) begin...
4465 16:30:19.923885 ==
4466 16:30:19.926806 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 16:30:19.930515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 16:30:19.930591 ==
4469 16:30:19.934129 Write leveling (Byte 0): 30 => 30
4470 16:30:19.937077 Write leveling (Byte 1): 31 => 31
4471 16:30:19.940862 DramcWriteLeveling(PI) end<-----
4472 16:30:19.940936
4473 16:30:19.940995 ==
4474 16:30:19.943759 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 16:30:19.950552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 16:30:19.950656 ==
4477 16:30:19.950758 [Gating] SW mode calibration
4478 16:30:19.960480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4479 16:30:19.963842 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4480 16:30:19.967134 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 16:30:19.973625 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 16:30:19.977333 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4483 16:30:19.980703 0 9 12 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (0 0)
4484 16:30:19.987038 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 16:30:19.990153 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 16:30:19.993740 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 16:30:20.000194 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 16:30:20.003966 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 16:30:20.007009 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 16:30:20.013440 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4491 16:30:20.017146 0 10 12 | B1->B0 | 3232 3d3d | 1 0 | (0 0) (0 0)
4492 16:30:20.020420 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4493 16:30:20.026958 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 16:30:20.030342 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 16:30:20.033958 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 16:30:20.036930 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 16:30:20.043522 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 16:30:20.047181 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 16:30:20.050136 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4500 16:30:20.057295 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:30:20.060193 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:30:20.063834 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 16:30:20.070209 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 16:30:20.073232 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 16:30:20.076830 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 16:30:20.083287 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 16:30:20.086863 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 16:30:20.089637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 16:30:20.096292 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 16:30:20.099724 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 16:30:20.103023 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 16:30:20.110200 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 16:30:20.113470 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 16:30:20.116048 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 16:30:20.122690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4516 16:30:20.126393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 16:30:20.129233 Total UI for P1: 0, mck2ui 16
4518 16:30:20.132759 best dqsien dly found for B0: ( 0, 13, 12)
4519 16:30:20.136073 Total UI for P1: 0, mck2ui 16
4520 16:30:20.139442 best dqsien dly found for B1: ( 0, 13, 12)
4521 16:30:20.143174 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4522 16:30:20.146140 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4523 16:30:20.146226
4524 16:30:20.149849 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4525 16:30:20.152716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4526 16:30:20.156238 [Gating] SW calibration Done
4527 16:30:20.156310 ==
4528 16:30:20.159747 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 16:30:20.165857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 16:30:20.165932 ==
4531 16:30:20.166008 RX Vref Scan: 0
4532 16:30:20.166066
4533 16:30:20.169452 RX Vref 0 -> 0, step: 1
4534 16:30:20.169537
4535 16:30:20.172819 RX Delay -230 -> 252, step: 16
4536 16:30:20.176331 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4537 16:30:20.179365 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4538 16:30:20.183024 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4539 16:30:20.189471 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4540 16:30:20.192440 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4541 16:30:20.196205 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4542 16:30:20.199244 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4543 16:30:20.203044 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4544 16:30:20.209414 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4545 16:30:20.212440 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4546 16:30:20.216119 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4547 16:30:20.219686 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4548 16:30:20.226119 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4549 16:30:20.229620 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4550 16:30:20.232895 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4551 16:30:20.236200 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4552 16:30:20.236271 ==
4553 16:30:20.239342 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 16:30:20.246100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 16:30:20.246182 ==
4556 16:30:20.246244 DQS Delay:
4557 16:30:20.249626 DQS0 = 0, DQS1 = 0
4558 16:30:20.249722 DQM Delay:
4559 16:30:20.252399 DQM0 = 52, DQM1 = 48
4560 16:30:20.252511 DQ Delay:
4561 16:30:20.255654 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4562 16:30:20.258973 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4563 16:30:20.262986 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4564 16:30:20.265885 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4565 16:30:20.266014
4566 16:30:20.266080
4567 16:30:20.266136 ==
4568 16:30:20.269374 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 16:30:20.272845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 16:30:20.272977 ==
4571 16:30:20.273072
4572 16:30:20.273156
4573 16:30:20.275686 TX Vref Scan disable
4574 16:30:20.279364 == TX Byte 0 ==
4575 16:30:20.282317 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 16:30:20.286043 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 16:30:20.289059 == TX Byte 1 ==
4578 16:30:20.292615 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4579 16:30:20.296036 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4580 16:30:20.296167 ==
4581 16:30:20.298964 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 16:30:20.302607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 16:30:20.302729 ==
4584 16:30:20.302818
4585 16:30:20.305559
4586 16:30:20.305646 TX Vref Scan disable
4587 16:30:20.309206 == TX Byte 0 ==
4588 16:30:20.312787 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 16:30:20.316377 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 16:30:20.319403 == TX Byte 1 ==
4591 16:30:20.322520 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4592 16:30:20.326230 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4593 16:30:20.329205
4594 16:30:20.329299 [DATLAT]
4595 16:30:20.329393 Freq=600, CH1 RK0
4596 16:30:20.329477
4597 16:30:20.332846 DATLAT Default: 0x9
4598 16:30:20.332936 0, 0xFFFF, sum = 0
4599 16:30:20.336390 1, 0xFFFF, sum = 0
4600 16:30:20.336488 2, 0xFFFF, sum = 0
4601 16:30:20.339454 3, 0xFFFF, sum = 0
4602 16:30:20.339524 4, 0xFFFF, sum = 0
4603 16:30:20.343103 5, 0xFFFF, sum = 0
4604 16:30:20.343173 6, 0xFFFF, sum = 0
4605 16:30:20.345930 7, 0xFFFF, sum = 0
4606 16:30:20.346025 8, 0x0, sum = 1
4607 16:30:20.349326 9, 0x0, sum = 2
4608 16:30:20.349428 10, 0x0, sum = 3
4609 16:30:20.352734 11, 0x0, sum = 4
4610 16:30:20.352808 best_step = 9
4611 16:30:20.352865
4612 16:30:20.352919 ==
4613 16:30:20.356498 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 16:30:20.362657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 16:30:20.362764 ==
4616 16:30:20.362853 RX Vref Scan: 1
4617 16:30:20.362944
4618 16:30:20.366177 RX Vref 0 -> 0, step: 1
4619 16:30:20.366269
4620 16:30:20.369682 RX Delay -147 -> 252, step: 8
4621 16:30:20.369777
4622 16:30:20.373105 Set Vref, RX VrefLevel [Byte0]: 54
4623 16:30:20.375694 [Byte1]: 53
4624 16:30:20.375789
4625 16:30:20.379177 Final RX Vref Byte 0 = 54 to rank0
4626 16:30:20.382961 Final RX Vref Byte 1 = 53 to rank0
4627 16:30:20.385967 Final RX Vref Byte 0 = 54 to rank1
4628 16:30:20.389320 Final RX Vref Byte 1 = 53 to rank1==
4629 16:30:20.393081 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 16:30:20.395973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 16:30:20.396053 ==
4632 16:30:20.399561 DQS Delay:
4633 16:30:20.399639 DQS0 = 0, DQS1 = 0
4634 16:30:20.399700 DQM Delay:
4635 16:30:20.403105 DQM0 = 48, DQM1 = 44
4636 16:30:20.403184 DQ Delay:
4637 16:30:20.406108 DQ0 =48, DQ1 =44, DQ2 =36, DQ3 =44
4638 16:30:20.409858 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4639 16:30:20.412820 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4640 16:30:20.415899 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4641 16:30:20.415974
4642 16:30:20.416034
4643 16:30:20.425850 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4644 16:30:20.425933 CH1 RK0: MR19=808, MR18=4D72
4645 16:30:20.432691 CH1_RK0: MR19=0x808, MR18=0x4D72, DQSOSC=388, MR23=63, INC=174, DEC=116
4646 16:30:20.432797
4647 16:30:20.435494 ----->DramcWriteLeveling(PI) begin...
4648 16:30:20.438943 ==
4649 16:30:20.439022 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 16:30:20.445717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 16:30:20.445799 ==
4652 16:30:20.449247 Write leveling (Byte 0): 31 => 31
4653 16:30:20.452368 Write leveling (Byte 1): 30 => 30
4654 16:30:20.452445 DramcWriteLeveling(PI) end<-----
4655 16:30:20.456009
4656 16:30:20.456086 ==
4657 16:30:20.459119 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 16:30:20.462732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 16:30:20.462810 ==
4660 16:30:20.466133 [Gating] SW mode calibration
4661 16:30:20.472700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4662 16:30:20.475915 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4663 16:30:20.482060 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 16:30:20.485733 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 16:30:20.488719 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4666 16:30:20.495717 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4667 16:30:20.498812 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 16:30:20.502142 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 16:30:20.508892 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 16:30:20.512067 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 16:30:20.515269 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 16:30:20.521897 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 16:30:20.525464 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4674 16:30:20.528365 0 10 12 | B1->B0 | 3636 3434 | 1 0 | (0 0) (0 0)
4675 16:30:20.534902 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 16:30:20.538665 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 16:30:20.541663 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 16:30:20.548560 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 16:30:20.551465 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 16:30:20.555101 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 16:30:20.561736 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 16:30:20.564666 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4683 16:30:20.568314 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4684 16:30:20.574963 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:30:20.578552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 16:30:20.581412 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 16:30:20.588205 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 16:30:20.591653 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 16:30:20.594980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 16:30:20.601469 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 16:30:20.605056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 16:30:20.607977 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 16:30:20.614377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 16:30:20.617800 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 16:30:20.621221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 16:30:20.628225 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 16:30:20.631324 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 16:30:20.634581 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4699 16:30:20.641227 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 16:30:20.641313 Total UI for P1: 0, mck2ui 16
4701 16:30:20.644351 best dqsien dly found for B0: ( 0, 13, 12)
4702 16:30:20.648223 Total UI for P1: 0, mck2ui 16
4703 16:30:20.651075 best dqsien dly found for B1: ( 0, 13, 12)
4704 16:30:20.657786 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4705 16:30:20.661452 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4706 16:30:20.661538
4707 16:30:20.664453 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4708 16:30:20.668041 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4709 16:30:20.670929 [Gating] SW calibration Done
4710 16:30:20.671043 ==
4711 16:30:20.674474 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 16:30:20.678179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 16:30:20.678260 ==
4714 16:30:20.681274 RX Vref Scan: 0
4715 16:30:20.681352
4716 16:30:20.681413 RX Vref 0 -> 0, step: 1
4717 16:30:20.681470
4718 16:30:20.684211 RX Delay -230 -> 252, step: 16
4719 16:30:20.687829 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4720 16:30:20.694172 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4721 16:30:20.697684 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4722 16:30:20.701304 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4723 16:30:20.704686 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4724 16:30:20.707499 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4725 16:30:20.714479 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4726 16:30:20.717432 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4727 16:30:20.721074 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4728 16:30:20.724023 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4729 16:30:20.731247 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4730 16:30:20.734098 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4731 16:30:20.737809 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4732 16:30:20.740746 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4733 16:30:20.747720 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4734 16:30:20.751095 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4735 16:30:20.751170 ==
4736 16:30:20.754415 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 16:30:20.757645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 16:30:20.757722 ==
4739 16:30:20.760927 DQS Delay:
4740 16:30:20.761003 DQS0 = 0, DQS1 = 0
4741 16:30:20.761067 DQM Delay:
4742 16:30:20.764156 DQM0 = 50, DQM1 = 46
4743 16:30:20.764225 DQ Delay:
4744 16:30:20.767480 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4745 16:30:20.770734 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4746 16:30:20.774268 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4747 16:30:20.777748 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4748 16:30:20.777847
4749 16:30:20.777946
4750 16:30:20.778038 ==
4751 16:30:20.780647 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 16:30:20.787143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 16:30:20.787221 ==
4754 16:30:20.787278
4755 16:30:20.787331
4756 16:30:20.787391 TX Vref Scan disable
4757 16:30:20.790831 == TX Byte 0 ==
4758 16:30:20.794451 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4759 16:30:20.800770 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4760 16:30:20.800840 == TX Byte 1 ==
4761 16:30:20.803814 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4762 16:30:20.811081 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4763 16:30:20.811158 ==
4764 16:30:20.813947 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 16:30:20.817335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 16:30:20.817400 ==
4767 16:30:20.817461
4768 16:30:20.817518
4769 16:30:20.820938 TX Vref Scan disable
4770 16:30:20.821009 == TX Byte 0 ==
4771 16:30:20.827389 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4772 16:30:20.830884 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4773 16:30:20.833649 == TX Byte 1 ==
4774 16:30:20.837116 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4775 16:30:20.840814 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4776 16:30:20.840885
4777 16:30:20.840979 [DATLAT]
4778 16:30:20.843795 Freq=600, CH1 RK1
4779 16:30:20.843868
4780 16:30:20.843923 DATLAT Default: 0x9
4781 16:30:20.847531 0, 0xFFFF, sum = 0
4782 16:30:20.847601 1, 0xFFFF, sum = 0
4783 16:30:20.850528 2, 0xFFFF, sum = 0
4784 16:30:20.854082 3, 0xFFFF, sum = 0
4785 16:30:20.854171 4, 0xFFFF, sum = 0
4786 16:30:20.857638 5, 0xFFFF, sum = 0
4787 16:30:20.857703 6, 0xFFFF, sum = 0
4788 16:30:20.860597 7, 0xFFFF, sum = 0
4789 16:30:20.860676 8, 0x0, sum = 1
4790 16:30:20.860730 9, 0x0, sum = 2
4791 16:30:20.864189 10, 0x0, sum = 3
4792 16:30:20.864252 11, 0x0, sum = 4
4793 16:30:20.867041 best_step = 9
4794 16:30:20.867101
4795 16:30:20.867161 ==
4796 16:30:20.870537 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 16:30:20.874133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 16:30:20.874198 ==
4799 16:30:20.877014 RX Vref Scan: 0
4800 16:30:20.877080
4801 16:30:20.877137 RX Vref 0 -> 0, step: 1
4802 16:30:20.877189
4803 16:30:20.880640 RX Delay -179 -> 252, step: 8
4804 16:30:20.888044 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4805 16:30:20.891329 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4806 16:30:20.894562 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4807 16:30:20.897759 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4808 16:30:20.904557 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4809 16:30:20.908063 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4810 16:30:20.910965 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4811 16:30:20.914441 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4812 16:30:20.917449 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4813 16:30:20.924047 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4814 16:30:20.927416 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4815 16:30:20.930992 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4816 16:30:20.933993 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4817 16:30:20.937663 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4818 16:30:20.944162 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4819 16:30:20.947868 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4820 16:30:20.947959 ==
4821 16:30:20.950973 Dram Type= 6, Freq= 0, CH_1, rank 1
4822 16:30:20.954783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4823 16:30:20.954874 ==
4824 16:30:20.957653 DQS Delay:
4825 16:30:20.957739 DQS0 = 0, DQS1 = 0
4826 16:30:20.957799 DQM Delay:
4827 16:30:20.960636 DQM0 = 49, DQM1 = 46
4828 16:30:20.960710 DQ Delay:
4829 16:30:20.964372 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4830 16:30:20.967392 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4831 16:30:20.971010 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4832 16:30:20.974706 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4833 16:30:20.974784
4834 16:30:20.974847
4835 16:30:20.984569 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4836 16:30:20.984647 CH1 RK1: MR19=808, MR18=6A21
4837 16:30:20.991152 CH1_RK1: MR19=0x808, MR18=0x6A21, DQSOSC=389, MR23=63, INC=173, DEC=115
4838 16:30:20.994255 [RxdqsGatingPostProcess] freq 600
4839 16:30:21.000891 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4840 16:30:21.004461 Pre-setting of DQS Precalculation
4841 16:30:21.007773 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4842 16:30:21.013988 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4843 16:30:21.024121 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4844 16:30:21.024207
4845 16:30:21.024269
4846 16:30:21.027567 [Calibration Summary] 1200 Mbps
4847 16:30:21.027645 CH 0, Rank 0
4848 16:30:21.030753 SW Impedance : PASS
4849 16:30:21.030835 DUTY Scan : NO K
4850 16:30:21.034198 ZQ Calibration : PASS
4851 16:30:21.034303 Jitter Meter : NO K
4852 16:30:21.037688 CBT Training : PASS
4853 16:30:21.040565 Write leveling : PASS
4854 16:30:21.040644 RX DQS gating : PASS
4855 16:30:21.044035 RX DQ/DQS(RDDQC) : PASS
4856 16:30:21.047412 TX DQ/DQS : PASS
4857 16:30:21.047490 RX DATLAT : PASS
4858 16:30:21.050314 RX DQ/DQS(Engine): PASS
4859 16:30:21.054010 TX OE : NO K
4860 16:30:21.054089 All Pass.
4861 16:30:21.054151
4862 16:30:21.054209 CH 0, Rank 1
4863 16:30:21.057061 SW Impedance : PASS
4864 16:30:21.060681 DUTY Scan : NO K
4865 16:30:21.060748 ZQ Calibration : PASS
4866 16:30:21.064169 Jitter Meter : NO K
4867 16:30:21.067118 CBT Training : PASS
4868 16:30:21.067195 Write leveling : PASS
4869 16:30:21.070766 RX DQS gating : PASS
4870 16:30:21.073744 RX DQ/DQS(RDDQC) : PASS
4871 16:30:21.073821 TX DQ/DQS : PASS
4872 16:30:21.077405 RX DATLAT : PASS
4873 16:30:21.080475 RX DQ/DQS(Engine): PASS
4874 16:30:21.080551 TX OE : NO K
4875 16:30:21.080615 All Pass.
4876 16:30:21.084220
4877 16:30:21.084295 CH 1, Rank 0
4878 16:30:21.087169 SW Impedance : PASS
4879 16:30:21.087238 DUTY Scan : NO K
4880 16:30:21.090217 ZQ Calibration : PASS
4881 16:30:21.090296 Jitter Meter : NO K
4882 16:30:21.093925 CBT Training : PASS
4883 16:30:21.096949 Write leveling : PASS
4884 16:30:21.097027 RX DQS gating : PASS
4885 16:30:21.100597 RX DQ/DQS(RDDQC) : PASS
4886 16:30:21.104122 TX DQ/DQS : PASS
4887 16:30:21.104200 RX DATLAT : PASS
4888 16:30:21.107113 RX DQ/DQS(Engine): PASS
4889 16:30:21.110111 TX OE : NO K
4890 16:30:21.110185 All Pass.
4891 16:30:21.110245
4892 16:30:21.110300 CH 1, Rank 1
4893 16:30:21.113696 SW Impedance : PASS
4894 16:30:21.117163 DUTY Scan : NO K
4895 16:30:21.117232 ZQ Calibration : PASS
4896 16:30:21.120195 Jitter Meter : NO K
4897 16:30:21.123821 CBT Training : PASS
4898 16:30:21.123892 Write leveling : PASS
4899 16:30:21.126822 RX DQS gating : PASS
4900 16:30:21.130404 RX DQ/DQS(RDDQC) : PASS
4901 16:30:21.130476 TX DQ/DQS : PASS
4902 16:30:21.133258 RX DATLAT : PASS
4903 16:30:21.137370 RX DQ/DQS(Engine): PASS
4904 16:30:21.137476 TX OE : NO K
4905 16:30:21.137575 All Pass.
4906 16:30:21.137635
4907 16:30:21.140034 DramC Write-DBI off
4908 16:30:21.143706 PER_BANK_REFRESH: Hybrid Mode
4909 16:30:21.143783 TX_TRACKING: ON
4910 16:30:21.153223 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4911 16:30:21.156474 [FAST_K] Save calibration result to emmc
4912 16:30:21.160304 dramc_set_vcore_voltage set vcore to 662500
4913 16:30:21.163604 Read voltage for 933, 3
4914 16:30:21.163683 Vio18 = 0
4915 16:30:21.166723 Vcore = 662500
4916 16:30:21.166801 Vdram = 0
4917 16:30:21.166863 Vddq = 0
4918 16:30:21.166919 Vmddr = 0
4919 16:30:21.173365 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4920 16:30:21.179894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4921 16:30:21.179976 MEM_TYPE=3, freq_sel=17
4922 16:30:21.183491 sv_algorithm_assistance_LP4_1600
4923 16:30:21.186515 ============ PULL DRAM RESETB DOWN ============
4924 16:30:21.193193 ========== PULL DRAM RESETB DOWN end =========
4925 16:30:21.196364 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4926 16:30:21.200020 ===================================
4927 16:30:21.203668 LPDDR4 DRAM CONFIGURATION
4928 16:30:21.206643 ===================================
4929 16:30:21.206721 EX_ROW_EN[0] = 0x0
4930 16:30:21.210136 EX_ROW_EN[1] = 0x0
4931 16:30:21.210216 LP4Y_EN = 0x0
4932 16:30:21.212988 WORK_FSP = 0x0
4933 16:30:21.213067 WL = 0x3
4934 16:30:21.216812 RL = 0x3
4935 16:30:21.216886 BL = 0x2
4936 16:30:21.219859 RPST = 0x0
4937 16:30:21.222763 RD_PRE = 0x0
4938 16:30:21.222840 WR_PRE = 0x1
4939 16:30:21.226405 WR_PST = 0x0
4940 16:30:21.226476 DBI_WR = 0x0
4941 16:30:21.229404 DBI_RD = 0x0
4942 16:30:21.229477 OTF = 0x1
4943 16:30:21.233184 ===================================
4944 16:30:21.236146 ===================================
4945 16:30:21.239736 ANA top config
4946 16:30:21.242670 ===================================
4947 16:30:21.242745 DLL_ASYNC_EN = 0
4948 16:30:21.246372 ALL_SLAVE_EN = 1
4949 16:30:21.249318 NEW_RANK_MODE = 1
4950 16:30:21.252795 DLL_IDLE_MODE = 1
4951 16:30:21.252866 LP45_APHY_COMB_EN = 1
4952 16:30:21.256412 TX_ODT_DIS = 1
4953 16:30:21.259291 NEW_8X_MODE = 1
4954 16:30:21.262887 ===================================
4955 16:30:21.265890 ===================================
4956 16:30:21.269539 data_rate = 1866
4957 16:30:21.272973 CKR = 1
4958 16:30:21.273055 DQ_P2S_RATIO = 8
4959 16:30:21.276299 ===================================
4960 16:30:21.279673 CA_P2S_RATIO = 8
4961 16:30:21.283004 DQ_CA_OPEN = 0
4962 16:30:21.286307 DQ_SEMI_OPEN = 0
4963 16:30:21.289384 CA_SEMI_OPEN = 0
4964 16:30:21.292527 CA_FULL_RATE = 0
4965 16:30:21.292610 DQ_CKDIV4_EN = 1
4966 16:30:21.296252 CA_CKDIV4_EN = 1
4967 16:30:21.299479 CA_PREDIV_EN = 0
4968 16:30:21.302705 PH8_DLY = 0
4969 16:30:21.306272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4970 16:30:21.309353 DQ_AAMCK_DIV = 4
4971 16:30:21.309453 CA_AAMCK_DIV = 4
4972 16:30:21.313037 CA_ADMCK_DIV = 4
4973 16:30:21.316088 DQ_TRACK_CA_EN = 0
4974 16:30:21.319153 CA_PICK = 933
4975 16:30:21.322915 CA_MCKIO = 933
4976 16:30:21.326053 MCKIO_SEMI = 0
4977 16:30:21.329745 PLL_FREQ = 3732
4978 16:30:21.329823 DQ_UI_PI_RATIO = 32
4979 16:30:21.332474 CA_UI_PI_RATIO = 0
4980 16:30:21.336063 ===================================
4981 16:30:21.339784 ===================================
4982 16:30:21.342783 memory_type:LPDDR4
4983 16:30:21.345770 GP_NUM : 10
4984 16:30:21.345841 SRAM_EN : 1
4985 16:30:21.349426 MD32_EN : 0
4986 16:30:21.352303 ===================================
4987 16:30:21.355964 [ANA_INIT] >>>>>>>>>>>>>>
4988 16:30:21.356037 <<<<<< [CONFIGURE PHASE]: ANA_TX
4989 16:30:21.359383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4990 16:30:21.362956 ===================================
4991 16:30:21.365844 data_rate = 1866,PCW = 0X8f00
4992 16:30:21.369240 ===================================
4993 16:30:21.372862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4994 16:30:21.379532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 16:30:21.386015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 16:30:21.388985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4997 16:30:21.392857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4998 16:30:21.395634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4999 16:30:21.399197 [ANA_INIT] flow start
5000 16:30:21.399274 [ANA_INIT] PLL >>>>>>>>
5001 16:30:21.402804 [ANA_INIT] PLL <<<<<<<<
5002 16:30:21.405656 [ANA_INIT] MIDPI >>>>>>>>
5003 16:30:21.405727 [ANA_INIT] MIDPI <<<<<<<<
5004 16:30:21.408991 [ANA_INIT] DLL >>>>>>>>
5005 16:30:21.412334 [ANA_INIT] flow end
5006 16:30:21.415646 ============ LP4 DIFF to SE enter ============
5007 16:30:21.419335 ============ LP4 DIFF to SE exit ============
5008 16:30:21.422449 [ANA_INIT] <<<<<<<<<<<<<
5009 16:30:21.425688 [Flow] Enable top DCM control >>>>>
5010 16:30:21.429204 [Flow] Enable top DCM control <<<<<
5011 16:30:21.432623 Enable DLL master slave shuffle
5012 16:30:21.435603 ==============================================================
5013 16:30:21.439145 Gating Mode config
5014 16:30:21.445901 ==============================================================
5015 16:30:21.445980 Config description:
5016 16:30:21.455429 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5017 16:30:21.462654 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5018 16:30:21.465623 SELPH_MODE 0: By rank 1: By Phase
5019 16:30:21.472166 ==============================================================
5020 16:30:21.475793 GAT_TRACK_EN = 1
5021 16:30:21.479275 RX_GATING_MODE = 2
5022 16:30:21.482727 RX_GATING_TRACK_MODE = 2
5023 16:30:21.485862 SELPH_MODE = 1
5024 16:30:21.489227 PICG_EARLY_EN = 1
5025 16:30:21.491960 VALID_LAT_VALUE = 1
5026 16:30:21.495592 ==============================================================
5027 16:30:21.499305 Enter into Gating configuration >>>>
5028 16:30:21.502190 Exit from Gating configuration <<<<
5029 16:30:21.505805 Enter into DVFS_PRE_config >>>>>
5030 16:30:21.515940 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5031 16:30:21.518988 Exit from DVFS_PRE_config <<<<<
5032 16:30:21.522686 Enter into PICG configuration >>>>
5033 16:30:21.525567 Exit from PICG configuration <<<<
5034 16:30:21.529054 [RX_INPUT] configuration >>>>>
5035 16:30:21.532459 [RX_INPUT] configuration <<<<<
5036 16:30:21.538973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5037 16:30:21.542072 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5038 16:30:21.548613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5039 16:30:21.555710 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5040 16:30:21.562177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 16:30:21.568551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 16:30:21.572182 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5043 16:30:21.575104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5044 16:30:21.578770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5045 16:30:21.585317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5046 16:30:21.588942 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5047 16:30:21.591859 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 16:30:21.595252 ===================================
5049 16:30:21.598784 LPDDR4 DRAM CONFIGURATION
5050 16:30:21.601520 ===================================
5051 16:30:21.601635 EX_ROW_EN[0] = 0x0
5052 16:30:21.604818 EX_ROW_EN[1] = 0x0
5053 16:30:21.608103 LP4Y_EN = 0x0
5054 16:30:21.608249 WORK_FSP = 0x0
5055 16:30:21.611392 WL = 0x3
5056 16:30:21.611469 RL = 0x3
5057 16:30:21.614867 BL = 0x2
5058 16:30:21.614959 RPST = 0x0
5059 16:30:21.618294 RD_PRE = 0x0
5060 16:30:21.618395 WR_PRE = 0x1
5061 16:30:21.621907 WR_PST = 0x0
5062 16:30:21.621983 DBI_WR = 0x0
5063 16:30:21.624839 DBI_RD = 0x0
5064 16:30:21.624915 OTF = 0x1
5065 16:30:21.628457 ===================================
5066 16:30:21.631390 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5067 16:30:21.638239 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5068 16:30:21.641909 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5069 16:30:21.644749 ===================================
5070 16:30:21.648281 LPDDR4 DRAM CONFIGURATION
5071 16:30:21.651780 ===================================
5072 16:30:21.651856 EX_ROW_EN[0] = 0x10
5073 16:30:21.655254 EX_ROW_EN[1] = 0x0
5074 16:30:21.657949 LP4Y_EN = 0x0
5075 16:30:21.658025 WORK_FSP = 0x0
5076 16:30:21.661276 WL = 0x3
5077 16:30:21.661380 RL = 0x3
5078 16:30:21.664667 BL = 0x2
5079 16:30:21.664744 RPST = 0x0
5080 16:30:21.668025 RD_PRE = 0x0
5081 16:30:21.668102 WR_PRE = 0x1
5082 16:30:21.671254 WR_PST = 0x0
5083 16:30:21.671345 DBI_WR = 0x0
5084 16:30:21.674982 DBI_RD = 0x0
5085 16:30:21.675064 OTF = 0x1
5086 16:30:21.678107 ===================================
5087 16:30:21.684608 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5088 16:30:21.688946 nWR fixed to 30
5089 16:30:21.692554 [ModeRegInit_LP4] CH0 RK0
5090 16:30:21.692648 [ModeRegInit_LP4] CH0 RK1
5091 16:30:21.695553 [ModeRegInit_LP4] CH1 RK0
5092 16:30:21.698630 [ModeRegInit_LP4] CH1 RK1
5093 16:30:21.698708 match AC timing 9
5094 16:30:21.705078 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5095 16:30:21.708751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5096 16:30:21.712274 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5097 16:30:21.718448 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5098 16:30:21.721641 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5099 16:30:21.721720 ==
5100 16:30:21.725047 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 16:30:21.728369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 16:30:21.728447 ==
5103 16:30:21.735390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 16:30:21.742014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5105 16:30:21.744953 [CA 0] Center 37 (6~68) winsize 63
5106 16:30:21.748584 [CA 1] Center 37 (7~68) winsize 62
5107 16:30:21.752069 [CA 2] Center 34 (4~65) winsize 62
5108 16:30:21.754798 [CA 3] Center 34 (3~65) winsize 63
5109 16:30:21.758409 [CA 4] Center 32 (2~63) winsize 62
5110 16:30:21.762098 [CA 5] Center 32 (2~62) winsize 61
5111 16:30:21.762166
5112 16:30:21.764912 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5113 16:30:21.764978
5114 16:30:21.768591 [CATrainingPosCal] consider 1 rank data
5115 16:30:21.771340 u2DelayCellTimex100 = 270/100 ps
5116 16:30:21.774874 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5117 16:30:21.778949 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5118 16:30:21.781643 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5119 16:30:21.785043 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5120 16:30:21.788339 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5121 16:30:21.794655 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5122 16:30:21.794732
5123 16:30:21.798536 CA PerBit enable=1, Macro0, CA PI delay=32
5124 16:30:21.798611
5125 16:30:21.801332 [CBTSetCACLKResult] CA Dly = 32
5126 16:30:21.801404 CS Dly: 5 (0~36)
5127 16:30:21.801467 ==
5128 16:30:21.805139 Dram Type= 6, Freq= 0, CH_0, rank 1
5129 16:30:21.808150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 16:30:21.811712 ==
5131 16:30:21.814787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5132 16:30:21.821280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5133 16:30:21.824242 [CA 0] Center 37 (7~68) winsize 62
5134 16:30:21.828015 [CA 1] Center 37 (7~68) winsize 62
5135 16:30:21.831689 [CA 2] Center 34 (4~65) winsize 62
5136 16:30:21.834676 [CA 3] Center 34 (4~65) winsize 62
5137 16:30:21.837616 [CA 4] Center 33 (3~63) winsize 61
5138 16:30:21.841063 [CA 5] Center 32 (2~62) winsize 61
5139 16:30:21.841136
5140 16:30:21.844586 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5141 16:30:21.844655
5142 16:30:21.847893 [CATrainingPosCal] consider 2 rank data
5143 16:30:21.851078 u2DelayCellTimex100 = 270/100 ps
5144 16:30:21.854271 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5145 16:30:21.857718 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5146 16:30:21.861216 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5147 16:30:21.867668 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5148 16:30:21.870653 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5149 16:30:21.874399 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5150 16:30:21.874468
5151 16:30:21.877848 CA PerBit enable=1, Macro0, CA PI delay=32
5152 16:30:21.877914
5153 16:30:21.880708 [CBTSetCACLKResult] CA Dly = 32
5154 16:30:21.880775 CS Dly: 5 (0~37)
5155 16:30:21.880831
5156 16:30:21.884574 ----->DramcWriteLeveling(PI) begin...
5157 16:30:21.887444 ==
5158 16:30:21.891192 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 16:30:21.894150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 16:30:21.894221 ==
5161 16:30:21.897797 Write leveling (Byte 0): 34 => 34
5162 16:30:21.900595 Write leveling (Byte 1): 29 => 29
5163 16:30:21.904021 DramcWriteLeveling(PI) end<-----
5164 16:30:21.904095
5165 16:30:21.904159 ==
5166 16:30:21.907365 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 16:30:21.910723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 16:30:21.910804 ==
5169 16:30:21.913772 [Gating] SW mode calibration
5170 16:30:21.920664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5171 16:30:21.927279 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5172 16:30:21.930915 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5173 16:30:21.933777 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 16:30:21.937404 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 16:30:21.944151 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 16:30:21.947049 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 16:30:21.950639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 16:30:21.957659 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5179 16:30:21.960337 0 14 28 | B1->B0 | 3434 2727 | 1 1 | (0 0) (0 1)
5180 16:30:21.964265 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5181 16:30:21.970435 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 16:30:21.973831 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 16:30:21.976988 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 16:30:21.983942 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 16:30:21.987468 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 16:30:21.990758 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5187 16:30:21.997445 0 15 28 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
5188 16:30:22.000399 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5189 16:30:22.004042 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 16:30:22.010725 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 16:30:22.013732 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 16:30:22.017308 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 16:30:22.023785 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 16:30:22.027257 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 16:30:22.030627 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5196 16:30:22.037192 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5197 16:30:22.040620 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:30:22.043312 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 16:30:22.050303 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 16:30:22.053298 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 16:30:22.057108 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 16:30:22.063744 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 16:30:22.067308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 16:30:22.070112 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 16:30:22.073636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 16:30:22.079902 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 16:30:22.083635 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 16:30:22.086484 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 16:30:22.093660 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 16:30:22.096904 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 16:30:22.099646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5212 16:30:22.106261 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 16:30:22.109536 Total UI for P1: 0, mck2ui 16
5214 16:30:22.113114 best dqsien dly found for B0: ( 1, 2, 28)
5215 16:30:22.116082 Total UI for P1: 0, mck2ui 16
5216 16:30:22.119797 best dqsien dly found for B1: ( 1, 2, 30)
5217 16:30:22.123456 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5218 16:30:22.126343 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5219 16:30:22.126443
5220 16:30:22.129891 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5221 16:30:22.132861 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5222 16:30:22.136486 [Gating] SW calibration Done
5223 16:30:22.136594 ==
5224 16:30:22.139468 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 16:30:22.142930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 16:30:22.142995 ==
5227 16:30:22.146210 RX Vref Scan: 0
5228 16:30:22.146305
5229 16:30:22.149442 RX Vref 0 -> 0, step: 1
5230 16:30:22.149537
5231 16:30:22.149697 RX Delay -80 -> 252, step: 8
5232 16:30:22.156349 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5233 16:30:22.159692 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5234 16:30:22.162944 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5235 16:30:22.165711 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5236 16:30:22.169397 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5237 16:30:22.172383 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5238 16:30:22.179552 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5239 16:30:22.182350 iDelay=208, Bit 7, Center 111 (24 ~ 199) 176
5240 16:30:22.186018 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5241 16:30:22.189053 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5242 16:30:22.192708 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5243 16:30:22.199311 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5244 16:30:22.202746 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5245 16:30:22.205670 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5246 16:30:22.209398 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5247 16:30:22.212812 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5248 16:30:22.212885 ==
5249 16:30:22.216224 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 16:30:22.222877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 16:30:22.222987 ==
5252 16:30:22.223086 DQS Delay:
5253 16:30:22.223159 DQS0 = 0, DQS1 = 0
5254 16:30:22.226246 DQM Delay:
5255 16:30:22.226323 DQM0 = 104, DQM1 = 94
5256 16:30:22.229395 DQ Delay:
5257 16:30:22.232638 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5258 16:30:22.236234 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5259 16:30:22.239121 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =91
5260 16:30:22.242785 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5261 16:30:22.242862
5262 16:30:22.242937
5263 16:30:22.243007 ==
5264 16:30:22.245777 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 16:30:22.249372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 16:30:22.249474 ==
5267 16:30:22.249577
5268 16:30:22.249652
5269 16:30:22.252737 TX Vref Scan disable
5270 16:30:22.256223 == TX Byte 0 ==
5271 16:30:22.259157 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5272 16:30:22.262816 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5273 16:30:22.265735 == TX Byte 1 ==
5274 16:30:22.269230 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5275 16:30:22.272741 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5276 16:30:22.272818 ==
5277 16:30:22.276100 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 16:30:22.279351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 16:30:22.282807 ==
5280 16:30:22.282886
5281 16:30:22.282947
5282 16:30:22.283002 TX Vref Scan disable
5283 16:30:22.286002 == TX Byte 0 ==
5284 16:30:22.289393 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5285 16:30:22.293116 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5286 16:30:22.296061 == TX Byte 1 ==
5287 16:30:22.299804 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5288 16:30:22.302766 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5289 16:30:22.306465
5290 16:30:22.306559 [DATLAT]
5291 16:30:22.306642 Freq=933, CH0 RK0
5292 16:30:22.306723
5293 16:30:22.309194 DATLAT Default: 0xd
5294 16:30:22.309288 0, 0xFFFF, sum = 0
5295 16:30:22.312860 1, 0xFFFF, sum = 0
5296 16:30:22.312970 2, 0xFFFF, sum = 0
5297 16:30:22.316424 3, 0xFFFF, sum = 0
5298 16:30:22.316521 4, 0xFFFF, sum = 0
5299 16:30:22.319277 5, 0xFFFF, sum = 0
5300 16:30:22.322834 6, 0xFFFF, sum = 0
5301 16:30:22.322933 7, 0xFFFF, sum = 0
5302 16:30:22.326328 8, 0xFFFF, sum = 0
5303 16:30:22.326396 9, 0xFFFF, sum = 0
5304 16:30:22.329717 10, 0x0, sum = 1
5305 16:30:22.329784 11, 0x0, sum = 2
5306 16:30:22.329840 12, 0x0, sum = 3
5307 16:30:22.332646 13, 0x0, sum = 4
5308 16:30:22.332713 best_step = 11
5309 16:30:22.332768
5310 16:30:22.336147 ==
5311 16:30:22.336301 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 16:30:22.342706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 16:30:22.342777 ==
5314 16:30:22.342837 RX Vref Scan: 1
5315 16:30:22.342892
5316 16:30:22.345979 RX Vref 0 -> 0, step: 1
5317 16:30:22.346152
5318 16:30:22.349628 RX Delay -53 -> 252, step: 4
5319 16:30:22.349722
5320 16:30:22.352642 Set Vref, RX VrefLevel [Byte0]: 55
5321 16:30:22.356107 [Byte1]: 49
5322 16:30:22.356173
5323 16:30:22.359017 Final RX Vref Byte 0 = 55 to rank0
5324 16:30:22.362616 Final RX Vref Byte 1 = 49 to rank0
5325 16:30:22.366117 Final RX Vref Byte 0 = 55 to rank1
5326 16:30:22.369072 Final RX Vref Byte 1 = 49 to rank1==
5327 16:30:22.372868 Dram Type= 6, Freq= 0, CH_0, rank 0
5328 16:30:22.375610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 16:30:22.375679 ==
5330 16:30:22.379071 DQS Delay:
5331 16:30:22.379140 DQS0 = 0, DQS1 = 0
5332 16:30:22.382830 DQM Delay:
5333 16:30:22.382897 DQM0 = 104, DQM1 = 95
5334 16:30:22.382953 DQ Delay:
5335 16:30:22.389720 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =102
5336 16:30:22.392361 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5337 16:30:22.395858 DQ8 =82, DQ9 =88, DQ10 =98, DQ11 =90
5338 16:30:22.399163 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5339 16:30:22.399363
5340 16:30:22.399452
5341 16:30:22.405723 [DQSOSCAuto] RK0, (LSB)MR18= 0x3127, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5342 16:30:22.409363 CH0 RK0: MR19=505, MR18=3127
5343 16:30:22.415731 CH0_RK0: MR19=0x505, MR18=0x3127, DQSOSC=406, MR23=63, INC=65, DEC=43
5344 16:30:22.415853
5345 16:30:22.418726 ----->DramcWriteLeveling(PI) begin...
5346 16:30:22.418793 ==
5347 16:30:22.422511 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 16:30:22.425454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 16:30:22.425556 ==
5350 16:30:22.429281 Write leveling (Byte 0): 33 => 33
5351 16:30:22.432093 Write leveling (Byte 1): 29 => 29
5352 16:30:22.435442 DramcWriteLeveling(PI) end<-----
5353 16:30:22.435543
5354 16:30:22.435664 ==
5355 16:30:22.438803 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 16:30:22.442401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 16:30:22.442493 ==
5358 16:30:22.445404 [Gating] SW mode calibration
5359 16:30:22.452374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 16:30:22.459023 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5361 16:30:22.462198 0 14 0 | B1->B0 | 3131 3130 | 1 1 | (0 0) (1 1)
5362 16:30:22.469067 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 16:30:22.472600 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 16:30:22.475394 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 16:30:22.481938 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 16:30:22.485416 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 16:30:22.488320 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5368 16:30:22.495558 0 14 28 | B1->B0 | 2b2b 2b2b | 1 0 | (1 1) (1 0)
5369 16:30:22.498474 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 16:30:22.501980 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 16:30:22.508348 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 16:30:22.511770 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 16:30:22.515001 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 16:30:22.521931 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 16:30:22.525266 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5376 16:30:22.528177 0 15 28 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (0 0)
5377 16:30:22.531871 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:30:22.538348 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 16:30:22.541995 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 16:30:22.545378 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 16:30:22.551891 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 16:30:22.555068 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 16:30:22.558087 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 16:30:22.564729 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5385 16:30:22.568258 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 16:30:22.571679 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:30:22.579067 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:30:22.582042 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 16:30:22.585163 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 16:30:22.591445 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 16:30:22.595059 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 16:30:22.598721 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 16:30:22.605320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 16:30:22.608184 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 16:30:22.611811 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 16:30:22.618431 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 16:30:22.621179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 16:30:22.624808 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 16:30:22.631080 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 16:30:22.634474 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5401 16:30:22.637785 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5402 16:30:22.641024 Total UI for P1: 0, mck2ui 16
5403 16:30:22.644285 best dqsien dly found for B1: ( 1, 2, 30)
5404 16:30:22.651123 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 16:30:22.651222 Total UI for P1: 0, mck2ui 16
5406 16:30:22.654413 best dqsien dly found for B0: ( 1, 2, 30)
5407 16:30:22.661301 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5408 16:30:22.664998 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5409 16:30:22.665115
5410 16:30:22.667868 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5411 16:30:22.671434 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5412 16:30:22.674546 [Gating] SW calibration Done
5413 16:30:22.674655 ==
5414 16:30:22.678052 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 16:30:22.680983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 16:30:22.681078 ==
5417 16:30:22.684596 RX Vref Scan: 0
5418 16:30:22.684672
5419 16:30:22.684733 RX Vref 0 -> 0, step: 1
5420 16:30:22.684788
5421 16:30:22.687685 RX Delay -80 -> 252, step: 8
5422 16:30:22.691257 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5423 16:30:22.697749 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5424 16:30:22.701050 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5425 16:30:22.704345 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5426 16:30:22.707701 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5427 16:30:22.711415 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5428 16:30:22.714873 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5429 16:30:22.721427 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5430 16:30:22.724515 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5431 16:30:22.728035 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5432 16:30:22.731042 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5433 16:30:22.734661 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5434 16:30:22.738252 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5435 16:30:22.741287 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5436 16:30:22.747603 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5437 16:30:22.751166 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5438 16:30:22.751271 ==
5439 16:30:22.754621 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 16:30:22.757998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 16:30:22.758077 ==
5442 16:30:22.761365 DQS Delay:
5443 16:30:22.761479 DQS0 = 0, DQS1 = 0
5444 16:30:22.761584 DQM Delay:
5445 16:30:22.764196 DQM0 = 104, DQM1 = 93
5446 16:30:22.764303 DQ Delay:
5447 16:30:22.767612 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5448 16:30:22.770976 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5449 16:30:22.774364 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5450 16:30:22.777746 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5451 16:30:22.777841
5452 16:30:22.777902
5453 16:30:22.780772 ==
5454 16:30:22.780842 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 16:30:22.787353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 16:30:22.787438 ==
5457 16:30:22.787498
5458 16:30:22.787553
5459 16:30:22.790946 TX Vref Scan disable
5460 16:30:22.791048 == TX Byte 0 ==
5461 16:30:22.794060 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5462 16:30:22.801273 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5463 16:30:22.801345 == TX Byte 1 ==
5464 16:30:22.804306 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 16:30:22.810773 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 16:30:22.810849 ==
5467 16:30:22.814197 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 16:30:22.817697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 16:30:22.817785 ==
5470 16:30:22.817847
5471 16:30:22.817902
5472 16:30:22.820850 TX Vref Scan disable
5473 16:30:22.824136 == TX Byte 0 ==
5474 16:30:22.827309 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5475 16:30:22.830648 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5476 16:30:22.834192 == TX Byte 1 ==
5477 16:30:22.837930 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5478 16:30:22.840945 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5479 16:30:22.841032
5480 16:30:22.841092 [DATLAT]
5481 16:30:22.843885 Freq=933, CH0 RK1
5482 16:30:22.843957
5483 16:30:22.847477 DATLAT Default: 0xb
5484 16:30:22.847544 0, 0xFFFF, sum = 0
5485 16:30:22.851060 1, 0xFFFF, sum = 0
5486 16:30:22.851136 2, 0xFFFF, sum = 0
5487 16:30:22.854626 3, 0xFFFF, sum = 0
5488 16:30:22.854694 4, 0xFFFF, sum = 0
5489 16:30:22.857447 5, 0xFFFF, sum = 0
5490 16:30:22.857541 6, 0xFFFF, sum = 0
5491 16:30:22.861001 7, 0xFFFF, sum = 0
5492 16:30:22.861071 8, 0xFFFF, sum = 0
5493 16:30:22.864430 9, 0xFFFF, sum = 0
5494 16:30:22.864512 10, 0x0, sum = 1
5495 16:30:22.867373 11, 0x0, sum = 2
5496 16:30:22.867452 12, 0x0, sum = 3
5497 16:30:22.870962 13, 0x0, sum = 4
5498 16:30:22.871040 best_step = 11
5499 16:30:22.871118
5500 16:30:22.871210 ==
5501 16:30:22.874497 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 16:30:22.877396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 16:30:22.877473 ==
5504 16:30:22.880762 RX Vref Scan: 0
5505 16:30:22.880838
5506 16:30:22.884224 RX Vref 0 -> 0, step: 1
5507 16:30:22.884299
5508 16:30:22.884358 RX Delay -53 -> 252, step: 4
5509 16:30:22.892094 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5510 16:30:22.895245 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5511 16:30:22.898607 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5512 16:30:22.902246 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5513 16:30:22.905225 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5514 16:30:22.911901 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5515 16:30:22.915472 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5516 16:30:22.918516 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5517 16:30:22.922068 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5518 16:30:22.924998 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5519 16:30:22.928459 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5520 16:30:22.935093 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5521 16:30:22.938469 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5522 16:30:22.941940 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5523 16:30:22.945261 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5524 16:30:22.948452 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5525 16:30:22.951717 ==
5526 16:30:22.955348 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 16:30:22.958112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 16:30:22.958188 ==
5529 16:30:22.958248 DQS Delay:
5530 16:30:22.961768 DQS0 = 0, DQS1 = 0
5531 16:30:22.961844 DQM Delay:
5532 16:30:22.965405 DQM0 = 104, DQM1 = 94
5533 16:30:22.965494 DQ Delay:
5534 16:30:22.968271 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5535 16:30:22.971994 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5536 16:30:22.974973 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =88
5537 16:30:22.978600 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5538 16:30:22.978676
5539 16:30:22.978735
5540 16:30:22.988685 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5541 16:30:22.988762 CH0 RK1: MR19=505, MR18=2C05
5542 16:30:22.995151 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5543 16:30:22.998036 [RxdqsGatingPostProcess] freq 933
5544 16:30:23.004817 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 16:30:23.008072 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 16:30:23.011997 best DQS1 dly(2T, 0.5T) = (0, 10)
5547 16:30:23.014893 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 16:30:23.018416 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5549 16:30:23.018492 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 16:30:23.021416 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 16:30:23.025018 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 16:30:23.028620 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 16:30:23.031599 Pre-setting of DQS Precalculation
5554 16:30:23.038147 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 16:30:23.038223 ==
5556 16:30:23.041731 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 16:30:23.045187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 16:30:23.045288 ==
5559 16:30:23.051553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 16:30:23.057852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5561 16:30:23.061235 [CA 0] Center 36 (6~67) winsize 62
5562 16:30:23.064758 [CA 1] Center 36 (6~67) winsize 62
5563 16:30:23.068020 [CA 2] Center 34 (4~65) winsize 62
5564 16:30:23.071270 [CA 3] Center 34 (4~65) winsize 62
5565 16:30:23.074446 [CA 4] Center 34 (4~64) winsize 61
5566 16:30:23.074522 [CA 5] Center 33 (3~64) winsize 62
5567 16:30:23.078099
5568 16:30:23.081799 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5569 16:30:23.081868
5570 16:30:23.084601 [CATrainingPosCal] consider 1 rank data
5571 16:30:23.087990 u2DelayCellTimex100 = 270/100 ps
5572 16:30:23.091436 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5573 16:30:23.094880 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5574 16:30:23.097862 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5575 16:30:23.101426 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 16:30:23.104433 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5577 16:30:23.108023 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 16:30:23.108095
5579 16:30:23.111621 CA PerBit enable=1, Macro0, CA PI delay=33
5580 16:30:23.111690
5581 16:30:23.114457 [CBTSetCACLKResult] CA Dly = 33
5582 16:30:23.117833 CS Dly: 6 (0~37)
5583 16:30:23.117903 ==
5584 16:30:23.121158 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 16:30:23.124289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 16:30:23.124354 ==
5587 16:30:23.131369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 16:30:23.138109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5589 16:30:23.141063 [CA 0] Center 37 (6~68) winsize 63
5590 16:30:23.144636 [CA 1] Center 37 (6~68) winsize 63
5591 16:30:23.147446 [CA 2] Center 35 (4~66) winsize 63
5592 16:30:23.151026 [CA 3] Center 34 (4~65) winsize 62
5593 16:30:23.153852 [CA 4] Center 34 (4~65) winsize 62
5594 16:30:23.157431 [CA 5] Center 34 (4~64) winsize 61
5595 16:30:23.157521
5596 16:30:23.161231 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5597 16:30:23.161296
5598 16:30:23.164074 [CATrainingPosCal] consider 2 rank data
5599 16:30:23.167612 u2DelayCellTimex100 = 270/100 ps
5600 16:30:23.170417 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5601 16:30:23.173905 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5602 16:30:23.177457 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5603 16:30:23.180252 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5604 16:30:23.183738 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5605 16:30:23.188194 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5606 16:30:23.188305
5607 16:30:23.193723 CA PerBit enable=1, Macro0, CA PI delay=34
5608 16:30:23.193816
5609 16:30:23.193913 [CBTSetCACLKResult] CA Dly = 34
5610 16:30:23.197376 CS Dly: 7 (0~39)
5611 16:30:23.197479
5612 16:30:23.200235 ----->DramcWriteLeveling(PI) begin...
5613 16:30:23.200331 ==
5614 16:30:23.203708 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 16:30:23.207527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 16:30:23.207616 ==
5617 16:30:23.210313 Write leveling (Byte 0): 26 => 26
5618 16:30:23.213967 Write leveling (Byte 1): 28 => 28
5619 16:30:23.217426 DramcWriteLeveling(PI) end<-----
5620 16:30:23.217539
5621 16:30:23.217627 ==
5622 16:30:23.220346 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 16:30:23.226967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 16:30:23.227039 ==
5625 16:30:23.227143 [Gating] SW mode calibration
5626 16:30:23.237171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 16:30:23.240206 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 16:30:23.243826 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 16:30:23.250454 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 16:30:23.253456 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 16:30:23.256978 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 16:30:23.263277 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 16:30:23.266756 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 16:30:23.270269 0 14 24 | B1->B0 | 3333 2e2e | 0 1 | (0 1) (1 0)
5635 16:30:23.277076 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5636 16:30:23.280064 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 16:30:23.283628 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 16:30:23.290140 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 16:30:23.293471 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 16:30:23.296807 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 16:30:23.303885 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5642 16:30:23.306899 0 15 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5643 16:30:23.310434 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5644 16:30:23.317121 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 16:30:23.319907 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 16:30:23.323588 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 16:30:23.330262 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 16:30:23.333324 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 16:30:23.336730 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 16:30:23.343656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5651 16:30:23.347113 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:30:23.349754 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:30:23.353454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:30:23.360192 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 16:30:23.363135 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 16:30:23.366815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 16:30:23.373159 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 16:30:23.376640 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 16:30:23.380050 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 16:30:23.386942 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 16:30:23.390159 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 16:30:23.393157 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 16:30:23.400316 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 16:30:23.403223 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 16:30:23.406803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5666 16:30:23.413684 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5667 16:30:23.417125 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5668 16:30:23.419974 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 16:30:23.423635 Total UI for P1: 0, mck2ui 16
5670 16:30:23.427094 best dqsien dly found for B0: ( 1, 2, 24)
5671 16:30:23.429937 Total UI for P1: 0, mck2ui 16
5672 16:30:23.433715 best dqsien dly found for B1: ( 1, 2, 26)
5673 16:30:23.436680 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5674 16:30:23.440399 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5675 16:30:23.440462
5676 16:30:23.443414 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5677 16:30:23.450366 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5678 16:30:23.450431 [Gating] SW calibration Done
5679 16:30:23.450502 ==
5680 16:30:23.453694 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 16:30:23.460072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 16:30:23.460147 ==
5683 16:30:23.460204 RX Vref Scan: 0
5684 16:30:23.460259
5685 16:30:23.463634 RX Vref 0 -> 0, step: 1
5686 16:30:23.463700
5687 16:30:23.466661 RX Delay -80 -> 252, step: 8
5688 16:30:23.470324 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5689 16:30:23.473251 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5690 16:30:23.476292 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5691 16:30:23.479857 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5692 16:30:23.486909 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5693 16:30:23.489670 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5694 16:30:23.493133 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5695 16:30:23.496569 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5696 16:30:23.500048 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5697 16:30:23.503392 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5698 16:30:23.509797 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5699 16:30:23.512802 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5700 16:30:23.516352 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5701 16:30:23.519746 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5702 16:30:23.523319 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5703 16:30:23.529626 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5704 16:30:23.529692 ==
5705 16:30:23.532910 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 16:30:23.536289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 16:30:23.536357 ==
5708 16:30:23.536414 DQS Delay:
5709 16:30:23.539157 DQS0 = 0, DQS1 = 0
5710 16:30:23.539216 DQM Delay:
5711 16:30:23.542747 DQM0 = 102, DQM1 = 98
5712 16:30:23.542816 DQ Delay:
5713 16:30:23.546576 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5714 16:30:23.549599 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5715 16:30:23.553318 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5716 16:30:23.556298 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5717 16:30:23.556394
5718 16:30:23.556477
5719 16:30:23.556557 ==
5720 16:30:23.559282 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 16:30:23.566041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 16:30:23.566113 ==
5723 16:30:23.566171
5724 16:30:23.566225
5725 16:30:23.566282 TX Vref Scan disable
5726 16:30:23.569431 == TX Byte 0 ==
5727 16:30:23.572922 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5728 16:30:23.579536 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5729 16:30:23.579603 == TX Byte 1 ==
5730 16:30:23.583090 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5731 16:30:23.589532 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5732 16:30:23.589641 ==
5733 16:30:23.592524 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 16:30:23.596263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 16:30:23.596344 ==
5736 16:30:23.596405
5737 16:30:23.596465
5738 16:30:23.599112 TX Vref Scan disable
5739 16:30:23.599179 == TX Byte 0 ==
5740 16:30:23.605828 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5741 16:30:23.609213 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5742 16:30:23.612640 == TX Byte 1 ==
5743 16:30:23.615927 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5744 16:30:23.619358 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5745 16:30:23.619428
5746 16:30:23.619490 [DATLAT]
5747 16:30:23.622308 Freq=933, CH1 RK0
5748 16:30:23.622378
5749 16:30:23.622435 DATLAT Default: 0xd
5750 16:30:23.625907 0, 0xFFFF, sum = 0
5751 16:30:23.628924 1, 0xFFFF, sum = 0
5752 16:30:23.628991 2, 0xFFFF, sum = 0
5753 16:30:23.632621 3, 0xFFFF, sum = 0
5754 16:30:23.632689 4, 0xFFFF, sum = 0
5755 16:30:23.636086 5, 0xFFFF, sum = 0
5756 16:30:23.636160 6, 0xFFFF, sum = 0
5757 16:30:23.638867 7, 0xFFFF, sum = 0
5758 16:30:23.638936 8, 0xFFFF, sum = 0
5759 16:30:23.642302 9, 0xFFFF, sum = 0
5760 16:30:23.642371 10, 0x0, sum = 1
5761 16:30:23.645772 11, 0x0, sum = 2
5762 16:30:23.645839 12, 0x0, sum = 3
5763 16:30:23.649040 13, 0x0, sum = 4
5764 16:30:23.649121 best_step = 11
5765 16:30:23.649179
5766 16:30:23.649278 ==
5767 16:30:23.652789 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 16:30:23.655781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 16:30:23.655858 ==
5770 16:30:23.658780 RX Vref Scan: 1
5771 16:30:23.658848
5772 16:30:23.662237 RX Vref 0 -> 0, step: 1
5773 16:30:23.662305
5774 16:30:23.662360 RX Delay -45 -> 252, step: 4
5775 16:30:23.662420
5776 16:30:23.665934 Set Vref, RX VrefLevel [Byte0]: 54
5777 16:30:23.668814 [Byte1]: 53
5778 16:30:23.673619
5779 16:30:23.673689 Final RX Vref Byte 0 = 54 to rank0
5780 16:30:23.677077 Final RX Vref Byte 1 = 53 to rank0
5781 16:30:23.679906 Final RX Vref Byte 0 = 54 to rank1
5782 16:30:23.683421 Final RX Vref Byte 1 = 53 to rank1==
5783 16:30:23.687173 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 16:30:23.693681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 16:30:23.693764 ==
5786 16:30:23.693823 DQS Delay:
5787 16:30:23.693879 DQS0 = 0, DQS1 = 0
5788 16:30:23.696637 DQM Delay:
5789 16:30:23.696704 DQM0 = 103, DQM1 = 99
5790 16:30:23.700416 DQ Delay:
5791 16:30:23.703387 DQ0 =106, DQ1 =96, DQ2 =96, DQ3 =102
5792 16:30:23.707162 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =104
5793 16:30:23.710027 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =94
5794 16:30:23.713610 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5795 16:30:23.713727
5796 16:30:23.713850
5797 16:30:23.720378 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5798 16:30:23.723626 CH1 RK0: MR19=505, MR18=1D34
5799 16:30:23.729954 CH1_RK0: MR19=0x505, MR18=0x1D34, DQSOSC=405, MR23=63, INC=66, DEC=44
5800 16:30:23.730063
5801 16:30:23.733387 ----->DramcWriteLeveling(PI) begin...
5802 16:30:23.733484 ==
5803 16:30:23.736875 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 16:30:23.740583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 16:30:23.740671 ==
5806 16:30:23.743460 Write leveling (Byte 0): 26 => 26
5807 16:30:23.747213 Write leveling (Byte 1): 26 => 26
5808 16:30:23.750078 DramcWriteLeveling(PI) end<-----
5809 16:30:23.750141
5810 16:30:23.750199 ==
5811 16:30:23.753666 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 16:30:23.757078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 16:30:23.760430 ==
5814 16:30:23.760494 [Gating] SW mode calibration
5815 16:30:23.767199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5816 16:30:23.773095 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5817 16:30:23.776901 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 16:30:23.783110 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 16:30:23.786625 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 16:30:23.789909 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 16:30:23.796968 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 16:30:23.799777 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 16:30:23.803498 0 14 24 | B1->B0 | 2d2d 3131 | 0 1 | (0 0) (1 1)
5824 16:30:23.809584 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
5825 16:30:23.813302 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 16:30:23.816977 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 16:30:23.823365 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 16:30:23.826375 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 16:30:23.829915 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 16:30:23.836796 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 16:30:23.840071 0 15 24 | B1->B0 | 3535 2828 | 0 1 | (0 0) (0 0)
5832 16:30:23.843415 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
5833 16:30:23.849642 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 16:30:23.853217 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 16:30:23.856283 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 16:30:23.862779 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 16:30:23.866299 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 16:30:23.869934 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 16:30:23.876148 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5840 16:30:23.879445 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5841 16:30:23.882987 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:30:23.886018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:30:23.892631 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 16:30:23.896072 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 16:30:23.899379 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 16:30:23.906248 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 16:30:23.909739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 16:30:23.912600 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 16:30:23.919859 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 16:30:23.922760 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 16:30:23.926231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 16:30:23.932893 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 16:30:23.935922 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 16:30:23.939678 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 16:30:23.946009 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5856 16:30:23.949426 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5857 16:30:23.952765 Total UI for P1: 0, mck2ui 16
5858 16:30:23.956175 best dqsien dly found for B1: ( 1, 2, 24)
5859 16:30:23.959505 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 16:30:23.962647 Total UI for P1: 0, mck2ui 16
5861 16:30:23.965946 best dqsien dly found for B0: ( 1, 2, 28)
5862 16:30:23.969351 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5863 16:30:23.972264 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5864 16:30:23.972341
5865 16:30:23.979607 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5866 16:30:23.982427 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5867 16:30:23.982499 [Gating] SW calibration Done
5868 16:30:23.985964 ==
5869 16:30:23.989364 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 16:30:23.992645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 16:30:23.992720 ==
5872 16:30:23.992794 RX Vref Scan: 0
5873 16:30:23.992867
5874 16:30:23.996184 RX Vref 0 -> 0, step: 1
5875 16:30:23.996257
5876 16:30:23.999107 RX Delay -80 -> 252, step: 8
5877 16:30:24.002604 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5878 16:30:24.006074 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5879 16:30:24.008998 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5880 16:30:24.016136 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5881 16:30:24.019506 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5882 16:30:24.022959 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5883 16:30:24.025962 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5884 16:30:24.029506 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5885 16:30:24.032436 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5886 16:30:24.036146 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5887 16:30:24.042652 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5888 16:30:24.045424 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5889 16:30:24.049170 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5890 16:30:24.052069 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5891 16:30:24.055717 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5892 16:30:24.062186 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5893 16:30:24.062263 ==
5894 16:30:24.065779 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 16:30:24.069336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 16:30:24.069428 ==
5897 16:30:24.069524 DQS Delay:
5898 16:30:24.072060 DQS0 = 0, DQS1 = 0
5899 16:30:24.072127 DQM Delay:
5900 16:30:24.076027 DQM0 = 102, DQM1 = 99
5901 16:30:24.076095 DQ Delay:
5902 16:30:24.078788 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5903 16:30:24.082234 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5904 16:30:24.085689 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5905 16:30:24.089463 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5906 16:30:24.089554
5907 16:30:24.089641
5908 16:30:24.089710 ==
5909 16:30:24.092276 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 16:30:24.098833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 16:30:24.098911 ==
5912 16:30:24.098989
5913 16:30:24.099058
5914 16:30:24.099131 TX Vref Scan disable
5915 16:30:24.102398 == TX Byte 0 ==
5916 16:30:24.105939 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5917 16:30:24.112307 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5918 16:30:24.112470 == TX Byte 1 ==
5919 16:30:24.115766 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5920 16:30:24.122202 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5921 16:30:24.122275 ==
5922 16:30:24.125765 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 16:30:24.129187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 16:30:24.129279 ==
5925 16:30:24.129379
5926 16:30:24.129468
5927 16:30:24.132659 TX Vref Scan disable
5928 16:30:24.132726 == TX Byte 0 ==
5929 16:30:24.139393 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5930 16:30:24.142293 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5931 16:30:24.142373 == TX Byte 1 ==
5932 16:30:24.148864 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5933 16:30:24.152451 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5934 16:30:24.152562
5935 16:30:24.152638 [DATLAT]
5936 16:30:24.155364 Freq=933, CH1 RK1
5937 16:30:24.155440
5938 16:30:24.155499 DATLAT Default: 0xb
5939 16:30:24.159023 0, 0xFFFF, sum = 0
5940 16:30:24.159116 1, 0xFFFF, sum = 0
5941 16:30:24.162551 2, 0xFFFF, sum = 0
5942 16:30:24.162638 3, 0xFFFF, sum = 0
5943 16:30:24.165464 4, 0xFFFF, sum = 0
5944 16:30:24.165566 5, 0xFFFF, sum = 0
5945 16:30:24.169188 6, 0xFFFF, sum = 0
5946 16:30:24.169293 7, 0xFFFF, sum = 0
5947 16:30:24.172126 8, 0xFFFF, sum = 0
5948 16:30:24.175746 9, 0xFFFF, sum = 0
5949 16:30:24.175812 10, 0x0, sum = 1
5950 16:30:24.175875 11, 0x0, sum = 2
5951 16:30:24.178599 12, 0x0, sum = 3
5952 16:30:24.178688 13, 0x0, sum = 4
5953 16:30:24.182084 best_step = 11
5954 16:30:24.182177
5955 16:30:24.182258 ==
5956 16:30:24.185636 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 16:30:24.188931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 16:30:24.188993 ==
5959 16:30:24.191741 RX Vref Scan: 0
5960 16:30:24.191806
5961 16:30:24.191859 RX Vref 0 -> 0, step: 1
5962 16:30:24.195131
5963 16:30:24.195193 RX Delay -45 -> 252, step: 4
5964 16:30:24.202649 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5965 16:30:24.206267 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5966 16:30:24.209256 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5967 16:30:24.212262 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5968 16:30:24.215863 iDelay=203, Bit 4, Center 102 (23 ~ 182) 160
5969 16:30:24.222707 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5970 16:30:24.226147 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5971 16:30:24.229276 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5972 16:30:24.232318 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5973 16:30:24.235547 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5974 16:30:24.242563 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5975 16:30:24.245321 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5976 16:30:24.248701 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5977 16:30:24.252668 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5978 16:30:24.255924 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5979 16:30:24.262617 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5980 16:30:24.262693 ==
5981 16:30:24.265461 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 16:30:24.269097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 16:30:24.269174 ==
5984 16:30:24.269233 DQS Delay:
5985 16:30:24.272079 DQS0 = 0, DQS1 = 0
5986 16:30:24.272155 DQM Delay:
5987 16:30:24.275795 DQM0 = 104, DQM1 = 99
5988 16:30:24.275870 DQ Delay:
5989 16:30:24.278736 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5990 16:30:24.282377 DQ4 =102, DQ5 =118, DQ6 =114, DQ7 =102
5991 16:30:24.285958 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5992 16:30:24.288897 DQ12 =110, DQ13 =108, DQ14 =104, DQ15 =108
5993 16:30:24.288973
5994 16:30:24.289032
5995 16:30:24.298801 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5996 16:30:24.302358 CH1 RK1: MR19=505, MR18=2F01
5997 16:30:24.305893 CH1_RK1: MR19=0x505, MR18=0x2F01, DQSOSC=407, MR23=63, INC=65, DEC=43
5998 16:30:24.308566 [RxdqsGatingPostProcess] freq 933
5999 16:30:24.315589 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6000 16:30:24.319341 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 16:30:24.322336 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 16:30:24.325981 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 16:30:24.328933 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 16:30:24.331973 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 16:30:24.335582 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 16:30:24.339238 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 16:30:24.342013 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 16:30:24.342089 Pre-setting of DQS Precalculation
6009 16:30:24.348810 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6010 16:30:24.355302 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6011 16:30:24.362156 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6012 16:30:24.362233
6013 16:30:24.362330
6014 16:30:24.365597 [Calibration Summary] 1866 Mbps
6015 16:30:24.369037 CH 0, Rank 0
6016 16:30:24.369112 SW Impedance : PASS
6017 16:30:24.372287 DUTY Scan : NO K
6018 16:30:24.375575 ZQ Calibration : PASS
6019 16:30:24.375661 Jitter Meter : NO K
6020 16:30:24.378983 CBT Training : PASS
6021 16:30:24.379059 Write leveling : PASS
6022 16:30:24.381891 RX DQS gating : PASS
6023 16:30:24.385652 RX DQ/DQS(RDDQC) : PASS
6024 16:30:24.385727 TX DQ/DQS : PASS
6025 16:30:24.388384 RX DATLAT : PASS
6026 16:30:24.392031 RX DQ/DQS(Engine): PASS
6027 16:30:24.392106 TX OE : NO K
6028 16:30:24.394970 All Pass.
6029 16:30:24.395046
6030 16:30:24.395106 CH 0, Rank 1
6031 16:30:24.398620 SW Impedance : PASS
6032 16:30:24.398695 DUTY Scan : NO K
6033 16:30:24.402254 ZQ Calibration : PASS
6034 16:30:24.405155 Jitter Meter : NO K
6035 16:30:24.405230 CBT Training : PASS
6036 16:30:24.408615 Write leveling : PASS
6037 16:30:24.412052 RX DQS gating : PASS
6038 16:30:24.412157 RX DQ/DQS(RDDQC) : PASS
6039 16:30:24.415417 TX DQ/DQS : PASS
6040 16:30:24.418165 RX DATLAT : PASS
6041 16:30:24.418271 RX DQ/DQS(Engine): PASS
6042 16:30:24.421771 TX OE : NO K
6043 16:30:24.421847 All Pass.
6044 16:30:24.421924
6045 16:30:24.425343 CH 1, Rank 0
6046 16:30:24.425425 SW Impedance : PASS
6047 16:30:24.428321 DUTY Scan : NO K
6048 16:30:24.428387 ZQ Calibration : PASS
6049 16:30:24.431945 Jitter Meter : NO K
6050 16:30:24.434961 CBT Training : PASS
6051 16:30:24.435085 Write leveling : PASS
6052 16:30:24.438572 RX DQS gating : PASS
6053 16:30:24.441444 RX DQ/DQS(RDDQC) : PASS
6054 16:30:24.441513 TX DQ/DQS : PASS
6055 16:30:24.445199 RX DATLAT : PASS
6056 16:30:24.448164 RX DQ/DQS(Engine): PASS
6057 16:30:24.448226 TX OE : NO K
6058 16:30:24.451792 All Pass.
6059 16:30:24.451861
6060 16:30:24.451944 CH 1, Rank 1
6061 16:30:24.455287 SW Impedance : PASS
6062 16:30:24.455349 DUTY Scan : NO K
6063 16:30:24.458117 ZQ Calibration : PASS
6064 16:30:24.461646 Jitter Meter : NO K
6065 16:30:24.461712 CBT Training : PASS
6066 16:30:24.465111 Write leveling : PASS
6067 16:30:24.468758 RX DQS gating : PASS
6068 16:30:24.468827 RX DQ/DQS(RDDQC) : PASS
6069 16:30:24.472049 TX DQ/DQS : PASS
6070 16:30:24.472120 RX DATLAT : PASS
6071 16:30:24.475372 RX DQ/DQS(Engine): PASS
6072 16:30:24.478944 TX OE : NO K
6073 16:30:24.479015 All Pass.
6074 16:30:24.479073
6075 16:30:24.481798 DramC Write-DBI off
6076 16:30:24.481870 PER_BANK_REFRESH: Hybrid Mode
6077 16:30:24.485034 TX_TRACKING: ON
6078 16:30:24.495432 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6079 16:30:24.498366 [FAST_K] Save calibration result to emmc
6080 16:30:24.501859 dramc_set_vcore_voltage set vcore to 650000
6081 16:30:24.501931 Read voltage for 400, 6
6082 16:30:24.504725 Vio18 = 0
6083 16:30:24.504793 Vcore = 650000
6084 16:30:24.504849 Vdram = 0
6085 16:30:24.508321 Vddq = 0
6086 16:30:24.508388 Vmddr = 0
6087 16:30:24.514973 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6088 16:30:24.518632 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6089 16:30:24.521406 MEM_TYPE=3, freq_sel=20
6090 16:30:24.524710 sv_algorithm_assistance_LP4_800
6091 16:30:24.528128 ============ PULL DRAM RESETB DOWN ============
6092 16:30:24.531609 ========== PULL DRAM RESETB DOWN end =========
6093 16:30:24.538184 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6094 16:30:24.541764 ===================================
6095 16:30:24.541833 LPDDR4 DRAM CONFIGURATION
6096 16:30:24.544559 ===================================
6097 16:30:24.548201 EX_ROW_EN[0] = 0x0
6098 16:30:24.548266 EX_ROW_EN[1] = 0x0
6099 16:30:24.551253 LP4Y_EN = 0x0
6100 16:30:24.551329 WORK_FSP = 0x0
6101 16:30:24.554889 WL = 0x2
6102 16:30:24.558480 RL = 0x2
6103 16:30:24.558555 BL = 0x2
6104 16:30:24.561490 RPST = 0x0
6105 16:30:24.561634 RD_PRE = 0x0
6106 16:30:24.564395 WR_PRE = 0x1
6107 16:30:24.564506 WR_PST = 0x0
6108 16:30:24.568093 DBI_WR = 0x0
6109 16:30:24.568162 DBI_RD = 0x0
6110 16:30:24.571606 OTF = 0x1
6111 16:30:24.574450 ===================================
6112 16:30:24.578045 ===================================
6113 16:30:24.578136 ANA top config
6114 16:30:24.581405 ===================================
6115 16:30:24.584924 DLL_ASYNC_EN = 0
6116 16:30:24.587882 ALL_SLAVE_EN = 1
6117 16:30:24.587955 NEW_RANK_MODE = 1
6118 16:30:24.590948 DLL_IDLE_MODE = 1
6119 16:30:24.594359 LP45_APHY_COMB_EN = 1
6120 16:30:24.597656 TX_ODT_DIS = 1
6121 16:30:24.600911 NEW_8X_MODE = 1
6122 16:30:24.604274 ===================================
6123 16:30:24.607655 ===================================
6124 16:30:24.607750 data_rate = 800
6125 16:30:24.611340 CKR = 1
6126 16:30:24.614231 DQ_P2S_RATIO = 4
6127 16:30:24.617909 ===================================
6128 16:30:24.620870 CA_P2S_RATIO = 4
6129 16:30:24.623878 DQ_CA_OPEN = 0
6130 16:30:24.627359 DQ_SEMI_OPEN = 1
6131 16:30:24.627462 CA_SEMI_OPEN = 1
6132 16:30:24.630985 CA_FULL_RATE = 0
6133 16:30:24.635103 DQ_CKDIV4_EN = 0
6134 16:30:24.637670 CA_CKDIV4_EN = 1
6135 16:30:24.640560 CA_PREDIV_EN = 0
6136 16:30:24.644207 PH8_DLY = 0
6137 16:30:24.644302 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6138 16:30:24.647084 DQ_AAMCK_DIV = 0
6139 16:30:24.650723 CA_AAMCK_DIV = 0
6140 16:30:24.654286 CA_ADMCK_DIV = 4
6141 16:30:24.657212 DQ_TRACK_CA_EN = 0
6142 16:30:24.660896 CA_PICK = 800
6143 16:30:24.663882 CA_MCKIO = 400
6144 16:30:24.663951 MCKIO_SEMI = 400
6145 16:30:24.667285 PLL_FREQ = 3016
6146 16:30:24.670891 DQ_UI_PI_RATIO = 32
6147 16:30:24.673812 CA_UI_PI_RATIO = 32
6148 16:30:24.677437 ===================================
6149 16:30:24.680414 ===================================
6150 16:30:24.683973 memory_type:LPDDR4
6151 16:30:24.684043 GP_NUM : 10
6152 16:30:24.687397 SRAM_EN : 1
6153 16:30:24.690402 MD32_EN : 0
6154 16:30:24.693840 ===================================
6155 16:30:24.693910 [ANA_INIT] >>>>>>>>>>>>>>
6156 16:30:24.697493 <<<<<< [CONFIGURE PHASE]: ANA_TX
6157 16:30:24.700442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6158 16:30:24.704097 ===================================
6159 16:30:24.707607 data_rate = 800,PCW = 0X7400
6160 16:30:24.710331 ===================================
6161 16:30:24.713621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6162 16:30:24.720359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6163 16:30:24.730393 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 16:30:24.734051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6165 16:30:24.740590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6166 16:30:24.743387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6167 16:30:24.743465 [ANA_INIT] flow start
6168 16:30:24.746819 [ANA_INIT] PLL >>>>>>>>
6169 16:30:24.750036 [ANA_INIT] PLL <<<<<<<<
6170 16:30:24.750114 [ANA_INIT] MIDPI >>>>>>>>
6171 16:30:24.753953 [ANA_INIT] MIDPI <<<<<<<<
6172 16:30:24.757341 [ANA_INIT] DLL >>>>>>>>
6173 16:30:24.757419 [ANA_INIT] flow end
6174 16:30:24.760265 ============ LP4 DIFF to SE enter ============
6175 16:30:24.766739 ============ LP4 DIFF to SE exit ============
6176 16:30:24.766843 [ANA_INIT] <<<<<<<<<<<<<
6177 16:30:24.770248 [Flow] Enable top DCM control >>>>>
6178 16:30:24.773825 [Flow] Enable top DCM control <<<<<
6179 16:30:24.776820 Enable DLL master slave shuffle
6180 16:30:24.783412 ==============================================================
6181 16:30:24.783512 Gating Mode config
6182 16:30:24.790714 ==============================================================
6183 16:30:24.793382 Config description:
6184 16:30:24.803597 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6185 16:30:24.810255 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6186 16:30:24.814068 SELPH_MODE 0: By rank 1: By Phase
6187 16:30:24.820096 ==============================================================
6188 16:30:24.823460 GAT_TRACK_EN = 0
6189 16:30:24.823535 RX_GATING_MODE = 2
6190 16:30:24.826816 RX_GATING_TRACK_MODE = 2
6191 16:30:24.830339 SELPH_MODE = 1
6192 16:30:24.833736 PICG_EARLY_EN = 1
6193 16:30:24.837104 VALID_LAT_VALUE = 1
6194 16:30:24.843647 ==============================================================
6195 16:30:24.847287 Enter into Gating configuration >>>>
6196 16:30:24.850196 Exit from Gating configuration <<<<
6197 16:30:24.853880 Enter into DVFS_PRE_config >>>>>
6198 16:30:24.863667 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6199 16:30:24.866955 Exit from DVFS_PRE_config <<<<<
6200 16:30:24.870155 Enter into PICG configuration >>>>
6201 16:30:24.873475 Exit from PICG configuration <<<<
6202 16:30:24.876437 [RX_INPUT] configuration >>>>>
6203 16:30:24.880150 [RX_INPUT] configuration <<<<<
6204 16:30:24.883730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6205 16:30:24.890315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6206 16:30:24.896902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 16:30:24.899761 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 16:30:24.907049 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6209 16:30:24.913397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6210 16:30:24.916371 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6211 16:30:24.923066 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6212 16:30:24.926687 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6213 16:30:24.930243 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6214 16:30:24.933074 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6215 16:30:24.939989 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 16:30:24.943532 ===================================
6217 16:30:24.943610 LPDDR4 DRAM CONFIGURATION
6218 16:30:24.946207 ===================================
6219 16:30:24.949791 EX_ROW_EN[0] = 0x0
6220 16:30:24.953342 EX_ROW_EN[1] = 0x0
6221 16:30:24.953435 LP4Y_EN = 0x0
6222 16:30:24.956308 WORK_FSP = 0x0
6223 16:30:24.956399 WL = 0x2
6224 16:30:24.959976 RL = 0x2
6225 16:30:24.960054 BL = 0x2
6226 16:30:24.963454 RPST = 0x0
6227 16:30:24.963563 RD_PRE = 0x0
6228 16:30:24.966252 WR_PRE = 0x1
6229 16:30:24.966331 WR_PST = 0x0
6230 16:30:24.969999 DBI_WR = 0x0
6231 16:30:24.970078 DBI_RD = 0x0
6232 16:30:24.972912 OTF = 0x1
6233 16:30:24.976307 ===================================
6234 16:30:24.979773 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6235 16:30:24.983114 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6236 16:30:24.989810 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6237 16:30:24.992811 ===================================
6238 16:30:24.992888 LPDDR4 DRAM CONFIGURATION
6239 16:30:24.996602 ===================================
6240 16:30:24.999656 EX_ROW_EN[0] = 0x10
6241 16:30:24.999743 EX_ROW_EN[1] = 0x0
6242 16:30:25.003270 LP4Y_EN = 0x0
6243 16:30:25.003364 WORK_FSP = 0x0
6244 16:30:25.006158 WL = 0x2
6245 16:30:25.009676 RL = 0x2
6246 16:30:25.009753 BL = 0x2
6247 16:30:25.013124 RPST = 0x0
6248 16:30:25.013217 RD_PRE = 0x0
6249 16:30:25.016036 WR_PRE = 0x1
6250 16:30:25.016159 WR_PST = 0x0
6251 16:30:25.020226 DBI_WR = 0x0
6252 16:30:25.020318 DBI_RD = 0x0
6253 16:30:25.023185 OTF = 0x1
6254 16:30:25.026236 ===================================
6255 16:30:25.029939 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6256 16:30:25.035258 nWR fixed to 30
6257 16:30:25.038785 [ModeRegInit_LP4] CH0 RK0
6258 16:30:25.038863 [ModeRegInit_LP4] CH0 RK1
6259 16:30:25.041666 [ModeRegInit_LP4] CH1 RK0
6260 16:30:25.045300 [ModeRegInit_LP4] CH1 RK1
6261 16:30:25.045397 match AC timing 19
6262 16:30:25.051591 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6263 16:30:25.055137 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6264 16:30:25.058767 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6265 16:30:25.065554 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6266 16:30:25.068398 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6267 16:30:25.068480 ==
6268 16:30:25.071930 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 16:30:25.074975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 16:30:25.075056 ==
6271 16:30:25.081450 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6272 16:30:25.088168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6273 16:30:25.091636 [CA 0] Center 36 (8~64) winsize 57
6274 16:30:25.095048 [CA 1] Center 36 (8~64) winsize 57
6275 16:30:25.098323 [CA 2] Center 36 (8~64) winsize 57
6276 16:30:25.098470 [CA 3] Center 36 (8~64) winsize 57
6277 16:30:25.101628 [CA 4] Center 36 (8~64) winsize 57
6278 16:30:25.105344 [CA 5] Center 36 (8~64) winsize 57
6279 16:30:25.105473
6280 16:30:25.111273 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6281 16:30:25.111414
6282 16:30:25.114939 [CATrainingPosCal] consider 1 rank data
6283 16:30:25.118268 u2DelayCellTimex100 = 270/100 ps
6284 16:30:25.121829 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 16:30:25.124683 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 16:30:25.127582 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 16:30:25.131157 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 16:30:25.134993 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 16:30:25.138020 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 16:30:25.138109
6291 16:30:25.141539 CA PerBit enable=1, Macro0, CA PI delay=36
6292 16:30:25.141658
6293 16:30:25.144445 [CBTSetCACLKResult] CA Dly = 36
6294 16:30:25.147839 CS Dly: 1 (0~32)
6295 16:30:25.147917 ==
6296 16:30:25.151389 Dram Type= 6, Freq= 0, CH_0, rank 1
6297 16:30:25.154850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 16:30:25.154923 ==
6299 16:30:25.161252 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 16:30:25.164679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6301 16:30:25.167521 [CA 0] Center 36 (8~64) winsize 57
6302 16:30:25.170962 [CA 1] Center 36 (8~64) winsize 57
6303 16:30:25.174605 [CA 2] Center 36 (8~64) winsize 57
6304 16:30:25.178156 [CA 3] Center 36 (8~64) winsize 57
6305 16:30:25.181075 [CA 4] Center 36 (8~64) winsize 57
6306 16:30:25.184785 [CA 5] Center 36 (8~64) winsize 57
6307 16:30:25.184879
6308 16:30:25.187723 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6309 16:30:25.187834
6310 16:30:25.191406 [CATrainingPosCal] consider 2 rank data
6311 16:30:25.194373 u2DelayCellTimex100 = 270/100 ps
6312 16:30:25.197933 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 16:30:25.200819 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 16:30:25.207710 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 16:30:25.211348 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 16:30:25.214310 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 16:30:25.218037 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 16:30:25.218110
6319 16:30:25.220977 CA PerBit enable=1, Macro0, CA PI delay=36
6320 16:30:25.221083
6321 16:30:25.224394 [CBTSetCACLKResult] CA Dly = 36
6322 16:30:25.224485 CS Dly: 1 (0~32)
6323 16:30:25.224579
6324 16:30:25.228008 ----->DramcWriteLeveling(PI) begin...
6325 16:30:25.231439 ==
6326 16:30:25.231549 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 16:30:25.237719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 16:30:25.237864 ==
6329 16:30:25.241259 Write leveling (Byte 0): 40 => 8
6330 16:30:25.244296 Write leveling (Byte 1): 40 => 8
6331 16:30:25.244403 DramcWriteLeveling(PI) end<-----
6332 16:30:25.247987
6333 16:30:25.248089 ==
6334 16:30:25.250897 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 16:30:25.254503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 16:30:25.254577 ==
6337 16:30:25.257396 [Gating] SW mode calibration
6338 16:30:25.264325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6339 16:30:25.267132 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6340 16:30:25.274250 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6341 16:30:25.277196 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 16:30:25.280827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 16:30:25.287187 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 16:30:25.291000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 16:30:25.293884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 16:30:25.300441 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 16:30:25.304026 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 16:30:25.306900 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 16:30:25.310375 Total UI for P1: 0, mck2ui 16
6350 16:30:25.313921 best dqsien dly found for B0: ( 0, 14, 24)
6351 16:30:25.317501 Total UI for P1: 0, mck2ui 16
6352 16:30:25.320572 best dqsien dly found for B1: ( 0, 14, 24)
6353 16:30:25.323598 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6354 16:30:25.327261 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6355 16:30:25.330259
6356 16:30:25.333828 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6357 16:30:25.337463 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 16:30:25.340284 [Gating] SW calibration Done
6359 16:30:25.340422 ==
6360 16:30:25.343877 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 16:30:25.346633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 16:30:25.346768 ==
6363 16:30:25.346857 RX Vref Scan: 0
6364 16:30:25.349957
6365 16:30:25.350077 RX Vref 0 -> 0, step: 1
6366 16:30:25.350166
6367 16:30:25.353647 RX Delay -410 -> 252, step: 16
6368 16:30:25.356639 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6369 16:30:25.363269 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6370 16:30:25.366789 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6371 16:30:25.370407 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6372 16:30:25.373947 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6373 16:30:25.380231 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6374 16:30:25.383744 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6375 16:30:25.386549 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6376 16:30:25.390060 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6377 16:30:25.396505 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6378 16:30:25.400122 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6379 16:30:25.403734 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6380 16:30:25.406740 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6381 16:30:25.413210 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6382 16:30:25.416865 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6383 16:30:25.420298 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6384 16:30:25.420381 ==
6385 16:30:25.423324 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 16:30:25.426865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 16:30:25.429912 ==
6388 16:30:25.429993 DQS Delay:
6389 16:30:25.430053 DQS0 = 27, DQS1 = 35
6390 16:30:25.432983 DQM Delay:
6391 16:30:25.433052 DQM0 = 12, DQM1 = 11
6392 16:30:25.436566 DQ Delay:
6393 16:30:25.436661 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6394 16:30:25.440072 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6395 16:30:25.443550 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6396 16:30:25.446535 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6397 16:30:25.446616
6398 16:30:25.446676
6399 16:30:25.450195 ==
6400 16:30:25.450269 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 16:30:25.456777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 16:30:25.456861 ==
6403 16:30:25.456928
6404 16:30:25.456988
6405 16:30:25.460066 TX Vref Scan disable
6406 16:30:25.460139 == TX Byte 0 ==
6407 16:30:25.462988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 16:30:25.469559 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 16:30:25.469649 == TX Byte 1 ==
6410 16:30:25.473129 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 16:30:25.479653 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 16:30:25.479738 ==
6413 16:30:25.483170 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 16:30:25.486000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 16:30:25.486086 ==
6416 16:30:25.486147
6417 16:30:25.486201
6418 16:30:25.489582 TX Vref Scan disable
6419 16:30:25.489663 == TX Byte 0 ==
6420 16:30:25.493217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 16:30:25.499598 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 16:30:25.499717 == TX Byte 1 ==
6423 16:30:25.503089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 16:30:25.509437 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 16:30:25.509564
6426 16:30:25.509662 [DATLAT]
6427 16:30:25.509752 Freq=400, CH0 RK0
6428 16:30:25.509837
6429 16:30:25.513124 DATLAT Default: 0xf
6430 16:30:25.513249 0, 0xFFFF, sum = 0
6431 16:30:25.515940 1, 0xFFFF, sum = 0
6432 16:30:25.519683 2, 0xFFFF, sum = 0
6433 16:30:25.519799 3, 0xFFFF, sum = 0
6434 16:30:25.522643 4, 0xFFFF, sum = 0
6435 16:30:25.522720 5, 0xFFFF, sum = 0
6436 16:30:25.525952 6, 0xFFFF, sum = 0
6437 16:30:25.526038 7, 0xFFFF, sum = 0
6438 16:30:25.529624 8, 0xFFFF, sum = 0
6439 16:30:25.529704 9, 0xFFFF, sum = 0
6440 16:30:25.533290 10, 0xFFFF, sum = 0
6441 16:30:25.533374 11, 0xFFFF, sum = 0
6442 16:30:25.536211 12, 0xFFFF, sum = 0
6443 16:30:25.536287 13, 0x0, sum = 1
6444 16:30:25.539287 14, 0x0, sum = 2
6445 16:30:25.539361 15, 0x0, sum = 3
6446 16:30:25.543026 16, 0x0, sum = 4
6447 16:30:25.543126 best_step = 14
6448 16:30:25.543187
6449 16:30:25.543249 ==
6450 16:30:25.545956 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 16:30:25.549680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 16:30:25.552618 ==
6453 16:30:25.552695 RX Vref Scan: 1
6454 16:30:25.552754
6455 16:30:25.556328 RX Vref 0 -> 0, step: 1
6456 16:30:25.556393
6457 16:30:25.556449 RX Delay -311 -> 252, step: 8
6458 16:30:25.559317
6459 16:30:25.559380 Set Vref, RX VrefLevel [Byte0]: 55
6460 16:30:25.562915 [Byte1]: 49
6461 16:30:25.567971
6462 16:30:25.568069 Final RX Vref Byte 0 = 55 to rank0
6463 16:30:25.571533 Final RX Vref Byte 1 = 49 to rank0
6464 16:30:25.575048 Final RX Vref Byte 0 = 55 to rank1
6465 16:30:25.578535 Final RX Vref Byte 1 = 49 to rank1==
6466 16:30:25.581361 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 16:30:25.588166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 16:30:25.588248 ==
6469 16:30:25.588310 DQS Delay:
6470 16:30:25.588370 DQS0 = 28, DQS1 = 32
6471 16:30:25.591825 DQM Delay:
6472 16:30:25.591921 DQM0 = 11, DQM1 = 9
6473 16:30:25.594743 DQ Delay:
6474 16:30:25.594812 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6475 16:30:25.598459 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6476 16:30:25.601390 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6477 16:30:25.604950 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6478 16:30:25.605046
6479 16:30:25.605137
6480 16:30:25.615295 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfbc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6481 16:30:25.618591 CH0 RK0: MR19=C0C, MR18=CFBC
6482 16:30:25.624899 CH0_RK0: MR19=0xC0C, MR18=0xCFBC, DQSOSC=384, MR23=63, INC=400, DEC=267
6483 16:30:25.624976 ==
6484 16:30:25.628443 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 16:30:25.631415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 16:30:25.631489 ==
6487 16:30:25.634792 [Gating] SW mode calibration
6488 16:30:25.641531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6489 16:30:25.644475 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6490 16:30:25.651804 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 16:30:25.654708 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 16:30:25.658445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 16:30:25.664430 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 16:30:25.668075 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 16:30:25.671756 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 16:30:25.678338 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 16:30:25.681110 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 16:30:25.685172 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 16:30:25.688414 Total UI for P1: 0, mck2ui 16
6500 16:30:25.691613 best dqsien dly found for B0: ( 0, 14, 24)
6501 16:30:25.694806 Total UI for P1: 0, mck2ui 16
6502 16:30:25.698316 best dqsien dly found for B1: ( 0, 14, 24)
6503 16:30:25.701142 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6504 16:30:25.704601 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6505 16:30:25.704676
6506 16:30:25.711278 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6507 16:30:25.714927 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 16:30:25.717700 [Gating] SW calibration Done
6509 16:30:25.717772 ==
6510 16:30:25.721258 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 16:30:25.724766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 16:30:25.724839 ==
6513 16:30:25.724899 RX Vref Scan: 0
6514 16:30:25.724963
6515 16:30:25.728101 RX Vref 0 -> 0, step: 1
6516 16:30:25.728194
6517 16:30:25.730963 RX Delay -410 -> 252, step: 16
6518 16:30:25.734396 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6519 16:30:25.741381 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6520 16:30:25.744090 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6521 16:30:25.747809 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6522 16:30:25.750637 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6523 16:30:25.757274 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6524 16:30:25.760862 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6525 16:30:25.764482 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6526 16:30:25.767278 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6527 16:30:25.774552 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6528 16:30:25.777589 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6529 16:30:25.781126 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6530 16:30:25.784120 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6531 16:30:25.790778 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6532 16:30:25.794293 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6533 16:30:25.797099 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6534 16:30:25.797191 ==
6535 16:30:25.800628 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 16:30:25.804153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 16:30:25.807399 ==
6538 16:30:25.807475 DQS Delay:
6539 16:30:25.807546 DQS0 = 27, DQS1 = 35
6540 16:30:25.810662 DQM Delay:
6541 16:30:25.810728 DQM0 = 12, DQM1 = 12
6542 16:30:25.813916 DQ Delay:
6543 16:30:25.813989 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6544 16:30:25.817398 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6545 16:30:25.820200 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6546 16:30:25.824210 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6547 16:30:25.824293
6548 16:30:25.824373
6549 16:30:25.827074 ==
6550 16:30:25.827145 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 16:30:25.834033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 16:30:25.834117 ==
6553 16:30:25.834186
6554 16:30:25.834242
6555 16:30:25.837355 TX Vref Scan disable
6556 16:30:25.837451 == TX Byte 0 ==
6557 16:30:25.840115 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6558 16:30:25.847437 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6559 16:30:25.847511 == TX Byte 1 ==
6560 16:30:25.850195 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6561 16:30:25.853715 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6562 16:30:25.857346 ==
6563 16:30:25.860269 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 16:30:25.863868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 16:30:25.863948 ==
6566 16:30:25.864008
6567 16:30:25.864062
6568 16:30:25.866838 TX Vref Scan disable
6569 16:30:25.866912 == TX Byte 0 ==
6570 16:30:25.870423 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6571 16:30:25.876777 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6572 16:30:25.876852 == TX Byte 1 ==
6573 16:30:25.880572 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6574 16:30:25.883439 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6575 16:30:25.887144
6576 16:30:25.887216 [DATLAT]
6577 16:30:25.887276 Freq=400, CH0 RK1
6578 16:30:25.887333
6579 16:30:25.890131 DATLAT Default: 0xe
6580 16:30:25.890201 0, 0xFFFF, sum = 0
6581 16:30:25.893753 1, 0xFFFF, sum = 0
6582 16:30:25.893824 2, 0xFFFF, sum = 0
6583 16:30:25.897267 3, 0xFFFF, sum = 0
6584 16:30:25.897338 4, 0xFFFF, sum = 0
6585 16:30:25.900164 5, 0xFFFF, sum = 0
6586 16:30:25.903714 6, 0xFFFF, sum = 0
6587 16:30:25.903787 7, 0xFFFF, sum = 0
6588 16:30:25.907303 8, 0xFFFF, sum = 0
6589 16:30:25.907380 9, 0xFFFF, sum = 0
6590 16:30:25.910148 10, 0xFFFF, sum = 0
6591 16:30:25.910247 11, 0xFFFF, sum = 0
6592 16:30:25.913835 12, 0xFFFF, sum = 0
6593 16:30:25.913909 13, 0x0, sum = 1
6594 16:30:25.917201 14, 0x0, sum = 2
6595 16:30:25.917296 15, 0x0, sum = 3
6596 16:30:25.920082 16, 0x0, sum = 4
6597 16:30:25.920151 best_step = 14
6598 16:30:25.920206
6599 16:30:25.920262 ==
6600 16:30:25.923467 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 16:30:25.926868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 16:30:25.926944 ==
6603 16:30:25.930225 RX Vref Scan: 0
6604 16:30:25.930299
6605 16:30:25.933520 RX Vref 0 -> 0, step: 1
6606 16:30:25.933620
6607 16:30:25.933683 RX Delay -311 -> 252, step: 8
6608 16:30:25.942122 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6609 16:30:25.945438 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6610 16:30:25.948689 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6611 16:30:25.951951 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6612 16:30:25.958905 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6613 16:30:25.962200 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6614 16:30:25.965684 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6615 16:30:25.969116 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6616 16:30:25.975670 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6617 16:30:25.978599 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6618 16:30:25.982299 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6619 16:30:25.985233 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6620 16:30:25.992091 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6621 16:30:25.995529 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6622 16:30:25.998533 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6623 16:30:26.005704 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6624 16:30:26.005787 ==
6625 16:30:26.008712 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 16:30:26.012411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 16:30:26.012510 ==
6628 16:30:26.012606 DQS Delay:
6629 16:30:26.015281 DQS0 = 24, DQS1 = 32
6630 16:30:26.015376 DQM Delay:
6631 16:30:26.018962 DQM0 = 8, DQM1 = 9
6632 16:30:26.019059 DQ Delay:
6633 16:30:26.022004 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6634 16:30:26.025481 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6635 16:30:26.028523 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6636 16:30:26.032224 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6637 16:30:26.032333
6638 16:30:26.032427
6639 16:30:26.038701 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6640 16:30:26.041575 CH0 RK1: MR19=C0C, MR18=BE5E
6641 16:30:26.048374 CH0_RK1: MR19=0xC0C, MR18=0xBE5E, DQSOSC=386, MR23=63, INC=396, DEC=264
6642 16:30:26.051854 [RxdqsGatingPostProcess] freq 400
6643 16:30:26.055577 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6644 16:30:26.058324 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 16:30:26.061727 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 16:30:26.065295 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 16:30:26.068418 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 16:30:26.072017 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 16:30:26.074898 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 16:30:26.078453 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 16:30:26.081931 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 16:30:26.085080 Pre-setting of DQS Precalculation
6653 16:30:26.088446 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6654 16:30:26.088544 ==
6655 16:30:26.091380 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 16:30:26.098706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 16:30:26.098782 ==
6658 16:30:26.101622 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6659 16:30:26.108163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6660 16:30:26.111682 [CA 0] Center 36 (8~64) winsize 57
6661 16:30:26.115147 [CA 1] Center 36 (8~64) winsize 57
6662 16:30:26.118230 [CA 2] Center 36 (8~64) winsize 57
6663 16:30:26.121811 [CA 3] Center 36 (8~64) winsize 57
6664 16:30:26.124856 [CA 4] Center 36 (8~64) winsize 57
6665 16:30:26.128421 [CA 5] Center 36 (8~64) winsize 57
6666 16:30:26.128501
6667 16:30:26.131927 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6668 16:30:26.132030
6669 16:30:26.134817 [CATrainingPosCal] consider 1 rank data
6670 16:30:26.138605 u2DelayCellTimex100 = 270/100 ps
6671 16:30:26.141430 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 16:30:26.145239 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 16:30:26.148231 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 16:30:26.151690 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 16:30:26.154813 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 16:30:26.161868 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 16:30:26.161942
6678 16:30:26.164858 CA PerBit enable=1, Macro0, CA PI delay=36
6679 16:30:26.164960
6680 16:30:26.168331 [CBTSetCACLKResult] CA Dly = 36
6681 16:30:26.168426 CS Dly: 1 (0~32)
6682 16:30:26.168510 ==
6683 16:30:26.171209 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 16:30:26.174880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 16:30:26.174952 ==
6686 16:30:26.181584 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 16:30:26.187870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6688 16:30:26.191461 [CA 0] Center 36 (8~64) winsize 57
6689 16:30:26.195037 [CA 1] Center 36 (8~64) winsize 57
6690 16:30:26.197886 [CA 2] Center 36 (8~64) winsize 57
6691 16:30:26.201169 [CA 3] Center 36 (8~64) winsize 57
6692 16:30:26.204684 [CA 4] Center 36 (8~64) winsize 57
6693 16:30:26.204756 [CA 5] Center 36 (8~64) winsize 57
6694 16:30:26.208545
6695 16:30:26.211449 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6696 16:30:26.211521
6697 16:30:26.215242 [CATrainingPosCal] consider 2 rank data
6698 16:30:26.218009 u2DelayCellTimex100 = 270/100 ps
6699 16:30:26.221602 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 16:30:26.224487 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 16:30:26.228225 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 16:30:26.231200 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 16:30:26.234816 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 16:30:26.238385 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 16:30:26.238455
6706 16:30:26.241309 CA PerBit enable=1, Macro0, CA PI delay=36
6707 16:30:26.241406
6708 16:30:26.245117 [CBTSetCACLKResult] CA Dly = 36
6709 16:30:26.248071 CS Dly: 1 (0~32)
6710 16:30:26.248166
6711 16:30:26.251820 ----->DramcWriteLeveling(PI) begin...
6712 16:30:26.251922 ==
6713 16:30:26.254854 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 16:30:26.258411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 16:30:26.258481 ==
6716 16:30:26.261259 Write leveling (Byte 0): 40 => 8
6717 16:30:26.264810 Write leveling (Byte 1): 40 => 8
6718 16:30:26.268320 DramcWriteLeveling(PI) end<-----
6719 16:30:26.268392
6720 16:30:26.268452 ==
6721 16:30:26.270988 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 16:30:26.274330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 16:30:26.274411 ==
6724 16:30:26.277980 [Gating] SW mode calibration
6725 16:30:26.284565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6726 16:30:26.291101 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6727 16:30:26.294630 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6728 16:30:26.297984 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 16:30:26.304898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 16:30:26.308280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 16:30:26.311172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 16:30:26.317713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 16:30:26.321288 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 16:30:26.325001 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 16:30:26.331348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 16:30:26.331421 Total UI for P1: 0, mck2ui 16
6737 16:30:26.337951 best dqsien dly found for B0: ( 0, 14, 24)
6738 16:30:26.338023 Total UI for P1: 0, mck2ui 16
6739 16:30:26.344599 best dqsien dly found for B1: ( 0, 14, 24)
6740 16:30:26.347377 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6741 16:30:26.351130 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6742 16:30:26.351211
6743 16:30:26.354094 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6744 16:30:26.357809 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 16:30:26.360805 [Gating] SW calibration Done
6746 16:30:26.360886 ==
6747 16:30:26.364407 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 16:30:26.367951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 16:30:26.368033 ==
6750 16:30:26.370908 RX Vref Scan: 0
6751 16:30:26.370988
6752 16:30:26.371069 RX Vref 0 -> 0, step: 1
6753 16:30:26.373887
6754 16:30:26.373967 RX Delay -410 -> 252, step: 16
6755 16:30:26.380434 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6756 16:30:26.384137 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6757 16:30:26.387427 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6758 16:30:26.390998 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6759 16:30:26.397594 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6760 16:30:26.400386 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6761 16:30:26.403825 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6762 16:30:26.407107 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6763 16:30:26.413975 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6764 16:30:26.417325 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6765 16:30:26.420707 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6766 16:30:26.424098 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6767 16:30:26.430681 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6768 16:30:26.433972 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6769 16:30:26.436812 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6770 16:30:26.443821 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6771 16:30:26.443911 ==
6772 16:30:26.446703 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 16:30:26.450467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 16:30:26.450538 ==
6775 16:30:26.450596 DQS Delay:
6776 16:30:26.453450 DQS0 = 35, DQS1 = 35
6777 16:30:26.453542 DQM Delay:
6778 16:30:26.457222 DQM0 = 17, DQM1 = 13
6779 16:30:26.457290 DQ Delay:
6780 16:30:26.460256 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6781 16:30:26.464054 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6782 16:30:26.466914 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6783 16:30:26.470414 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6784 16:30:26.470482
6785 16:30:26.470540
6786 16:30:26.470593 ==
6787 16:30:26.473295 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 16:30:26.476899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 16:30:26.476966 ==
6790 16:30:26.477066
6791 16:30:26.477118
6792 16:30:26.479901 TX Vref Scan disable
6793 16:30:26.483359 == TX Byte 0 ==
6794 16:30:26.487030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 16:30:26.489957 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 16:30:26.490021 == TX Byte 1 ==
6797 16:30:26.497016 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 16:30:26.500380 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 16:30:26.500460 ==
6800 16:30:26.503274 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 16:30:26.506946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 16:30:26.507025 ==
6803 16:30:26.507103
6804 16:30:26.507177
6805 16:30:26.509946 TX Vref Scan disable
6806 16:30:26.513439 == TX Byte 0 ==
6807 16:30:26.516774 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 16:30:26.520431 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 16:30:26.520509 == TX Byte 1 ==
6810 16:30:26.526660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 16:30:26.530222 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 16:30:26.530293
6813 16:30:26.530353 [DATLAT]
6814 16:30:26.533288 Freq=400, CH1 RK0
6815 16:30:26.533388
6816 16:30:26.533475 DATLAT Default: 0xf
6817 16:30:26.536691 0, 0xFFFF, sum = 0
6818 16:30:26.536792 1, 0xFFFF, sum = 0
6819 16:30:26.540015 2, 0xFFFF, sum = 0
6820 16:30:26.540117 3, 0xFFFF, sum = 0
6821 16:30:26.543580 4, 0xFFFF, sum = 0
6822 16:30:26.543711 5, 0xFFFF, sum = 0
6823 16:30:26.546999 6, 0xFFFF, sum = 0
6824 16:30:26.547093 7, 0xFFFF, sum = 0
6825 16:30:26.550277 8, 0xFFFF, sum = 0
6826 16:30:26.553716 9, 0xFFFF, sum = 0
6827 16:30:26.553808 10, 0xFFFF, sum = 0
6828 16:30:26.556579 11, 0xFFFF, sum = 0
6829 16:30:26.556672 12, 0xFFFF, sum = 0
6830 16:30:26.560207 13, 0x0, sum = 1
6831 16:30:26.560299 14, 0x0, sum = 2
6832 16:30:26.563223 15, 0x0, sum = 3
6833 16:30:26.563302 16, 0x0, sum = 4
6834 16:30:26.563364 best_step = 14
6835 16:30:26.563421
6836 16:30:26.566832 ==
6837 16:30:26.570552 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 16:30:26.573652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 16:30:26.573761 ==
6840 16:30:26.573850 RX Vref Scan: 1
6841 16:30:26.573935
6842 16:30:26.576589 RX Vref 0 -> 0, step: 1
6843 16:30:26.576682
6844 16:30:26.580287 RX Delay -311 -> 252, step: 8
6845 16:30:26.580380
6846 16:30:26.583276 Set Vref, RX VrefLevel [Byte0]: 54
6847 16:30:26.586749 [Byte1]: 53
6848 16:30:26.590380
6849 16:30:26.590462 Final RX Vref Byte 0 = 54 to rank0
6850 16:30:26.593444 Final RX Vref Byte 1 = 53 to rank0
6851 16:30:26.597115 Final RX Vref Byte 0 = 54 to rank1
6852 16:30:26.599926 Final RX Vref Byte 1 = 53 to rank1==
6853 16:30:26.603337 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 16:30:26.610439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 16:30:26.610547 ==
6856 16:30:26.610637 DQS Delay:
6857 16:30:26.613393 DQS0 = 32, DQS1 = 32
6858 16:30:26.613488 DQM Delay:
6859 16:30:26.613594 DQM0 = 13, DQM1 = 10
6860 16:30:26.617151 DQ Delay:
6861 16:30:26.620059 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6862 16:30:26.623560 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6863 16:30:26.623654 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6864 16:30:26.626964 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6865 16:30:26.629668
6866 16:30:26.629748
6867 16:30:26.636807 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6868 16:30:26.639731 CH1 RK0: MR19=C0C, MR18=93CC
6869 16:30:26.646270 CH1_RK0: MR19=0xC0C, MR18=0x93CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6870 16:30:26.646354 ==
6871 16:30:26.649997 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 16:30:26.653638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 16:30:26.653724 ==
6874 16:30:26.656459 [Gating] SW mode calibration
6875 16:30:26.663436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6876 16:30:26.670085 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6877 16:30:26.673050 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6878 16:30:26.676743 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 16:30:26.683046 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 16:30:26.686594 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 16:30:26.689525 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 16:30:26.696082 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 16:30:26.699746 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 16:30:26.702708 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 16:30:26.709965 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 16:30:26.710038 Total UI for P1: 0, mck2ui 16
6887 16:30:26.712775 best dqsien dly found for B0: ( 0, 14, 24)
6888 16:30:26.716105 Total UI for P1: 0, mck2ui 16
6889 16:30:26.719414 best dqsien dly found for B1: ( 0, 14, 24)
6890 16:30:26.725956 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6891 16:30:26.729696 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6892 16:30:26.729775
6893 16:30:26.733083 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6894 16:30:26.735862 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 16:30:26.739487 [Gating] SW calibration Done
6896 16:30:26.739566 ==
6897 16:30:26.742863 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 16:30:26.746468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 16:30:26.746547 ==
6900 16:30:26.749234 RX Vref Scan: 0
6901 16:30:26.749312
6902 16:30:26.749372 RX Vref 0 -> 0, step: 1
6903 16:30:26.749428
6904 16:30:26.752778 RX Delay -410 -> 252, step: 16
6905 16:30:26.756465 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6906 16:30:26.762948 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6907 16:30:26.766438 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6908 16:30:26.769737 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6909 16:30:26.772608 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6910 16:30:26.779688 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6911 16:30:26.782489 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6912 16:30:26.785989 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6913 16:30:26.789409 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6914 16:30:26.795942 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6915 16:30:26.798998 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6916 16:30:26.802603 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6917 16:30:26.805563 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6918 16:30:26.812176 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6919 16:30:26.815736 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6920 16:30:26.818650 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6921 16:30:26.818716 ==
6922 16:30:26.822211 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 16:30:26.829073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 16:30:26.829171 ==
6925 16:30:26.829257 DQS Delay:
6926 16:30:26.832049 DQS0 = 35, DQS1 = 35
6927 16:30:26.832116 DQM Delay:
6928 16:30:26.832173 DQM0 = 18, DQM1 = 13
6929 16:30:26.835643 DQ Delay:
6930 16:30:26.839136 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6931 16:30:26.842383 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6932 16:30:26.845863 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6933 16:30:26.848740 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6934 16:30:26.848820
6935 16:30:26.848901
6936 16:30:26.848976 ==
6937 16:30:26.852341 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 16:30:26.855703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 16:30:26.855796 ==
6940 16:30:26.855879
6941 16:30:26.855960
6942 16:30:26.858459 TX Vref Scan disable
6943 16:30:26.858550 == TX Byte 0 ==
6944 16:30:26.865797 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 16:30:26.868711 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 16:30:26.868780 == TX Byte 1 ==
6947 16:30:26.872466 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 16:30:26.879125 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 16:30:26.879204 ==
6950 16:30:26.882271 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 16:30:26.885701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 16:30:26.885780 ==
6953 16:30:26.885858
6954 16:30:26.885961
6955 16:30:26.889121 TX Vref Scan disable
6956 16:30:26.889242 == TX Byte 0 ==
6957 16:30:26.895436 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6958 16:30:26.898948 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6959 16:30:26.899042 == TX Byte 1 ==
6960 16:30:26.901807 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6961 16:30:26.909069 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6962 16:30:26.909148
6963 16:30:26.909226 [DATLAT]
6964 16:30:26.911845 Freq=400, CH1 RK1
6965 16:30:26.911940
6966 16:30:26.912032 DATLAT Default: 0xe
6967 16:30:26.915341 0, 0xFFFF, sum = 0
6968 16:30:26.915422 1, 0xFFFF, sum = 0
6969 16:30:26.918386 2, 0xFFFF, sum = 0
6970 16:30:26.918466 3, 0xFFFF, sum = 0
6971 16:30:26.922038 4, 0xFFFF, sum = 0
6972 16:30:26.922118 5, 0xFFFF, sum = 0
6973 16:30:26.925740 6, 0xFFFF, sum = 0
6974 16:30:26.925820 7, 0xFFFF, sum = 0
6975 16:30:26.928627 8, 0xFFFF, sum = 0
6976 16:30:26.928708 9, 0xFFFF, sum = 0
6977 16:30:26.932175 10, 0xFFFF, sum = 0
6978 16:30:26.932257 11, 0xFFFF, sum = 0
6979 16:30:26.935637 12, 0xFFFF, sum = 0
6980 16:30:26.935734 13, 0x0, sum = 1
6981 16:30:26.938677 14, 0x0, sum = 2
6982 16:30:26.938760 15, 0x0, sum = 3
6983 16:30:26.941418 16, 0x0, sum = 4
6984 16:30:26.941515 best_step = 14
6985 16:30:26.941613
6986 16:30:26.941685 ==
6987 16:30:26.945025 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 16:30:26.952119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 16:30:26.952202 ==
6990 16:30:26.952282 RX Vref Scan: 0
6991 16:30:26.952356
6992 16:30:26.954887 RX Vref 0 -> 0, step: 1
6993 16:30:26.954966
6994 16:30:26.958393 RX Delay -311 -> 252, step: 8
6995 16:30:26.964777 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6996 16:30:26.968133 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6997 16:30:26.971931 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6998 16:30:26.974822 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6999 16:30:26.981354 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7000 16:30:26.985000 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7001 16:30:26.988413 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7002 16:30:26.991810 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
7003 16:30:26.995315 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7004 16:30:27.002031 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7005 16:30:27.004895 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7006 16:30:27.008300 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7007 16:30:27.012076 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7008 16:30:27.018740 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7009 16:30:27.021760 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7010 16:30:27.025356 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7011 16:30:27.025453 ==
7012 16:30:27.028289 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 16:30:27.034851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 16:30:27.034948 ==
7015 16:30:27.035035 DQS Delay:
7016 16:30:27.038478 DQS0 = 28, DQS1 = 36
7017 16:30:27.038575 DQM Delay:
7018 16:30:27.038661 DQM0 = 10, DQM1 = 15
7019 16:30:27.041326 DQ Delay:
7020 16:30:27.045129 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7021 16:30:27.048073 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7022 16:30:27.048162 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7023 16:30:27.055381 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7024 16:30:27.055479
7025 16:30:27.055566
7026 16:30:27.061700 [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7027 16:30:27.064756 CH1 RK1: MR19=C0C, MR18=C758
7028 16:30:27.071908 CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265
7029 16:30:27.074874 [RxdqsGatingPostProcess] freq 400
7030 16:30:27.078423 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7031 16:30:27.081765 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 16:30:27.084739 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 16:30:27.088500 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 16:30:27.091373 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 16:30:27.095106 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 16:30:27.098624 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 16:30:27.101559 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 16:30:27.105160 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 16:30:27.108729 Pre-setting of DQS Precalculation
7040 16:30:27.111569 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7041 16:30:27.118675 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7042 16:30:27.128431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7043 16:30:27.128506
7044 16:30:27.128565
7045 16:30:27.128620 [Calibration Summary] 800 Mbps
7046 16:30:27.132047 CH 0, Rank 0
7047 16:30:27.132125 SW Impedance : PASS
7048 16:30:27.134897 DUTY Scan : NO K
7049 16:30:27.138621 ZQ Calibration : PASS
7050 16:30:27.138698 Jitter Meter : NO K
7051 16:30:27.141417 CBT Training : PASS
7052 16:30:27.144983 Write leveling : PASS
7053 16:30:27.145063 RX DQS gating : PASS
7054 16:30:27.148590 RX DQ/DQS(RDDQC) : PASS
7055 16:30:27.151579 TX DQ/DQS : PASS
7056 16:30:27.151657 RX DATLAT : PASS
7057 16:30:27.155339 RX DQ/DQS(Engine): PASS
7058 16:30:27.158343 TX OE : NO K
7059 16:30:27.158429 All Pass.
7060 16:30:27.158490
7061 16:30:27.158544 CH 0, Rank 1
7062 16:30:27.162082 SW Impedance : PASS
7063 16:30:27.164891 DUTY Scan : NO K
7064 16:30:27.164969 ZQ Calibration : PASS
7065 16:30:27.168370 Jitter Meter : NO K
7066 16:30:27.171298 CBT Training : PASS
7067 16:30:27.171375 Write leveling : NO K
7068 16:30:27.174660 RX DQS gating : PASS
7069 16:30:27.174736 RX DQ/DQS(RDDQC) : PASS
7070 16:30:27.178388 TX DQ/DQS : PASS
7071 16:30:27.181324 RX DATLAT : PASS
7072 16:30:27.181402 RX DQ/DQS(Engine): PASS
7073 16:30:27.184977 TX OE : NO K
7074 16:30:27.185054 All Pass.
7075 16:30:27.185114
7076 16:30:27.188518 CH 1, Rank 0
7077 16:30:27.188596 SW Impedance : PASS
7078 16:30:27.191109 DUTY Scan : NO K
7079 16:30:27.194550 ZQ Calibration : PASS
7080 16:30:27.194650 Jitter Meter : NO K
7081 16:30:27.198065 CBT Training : PASS
7082 16:30:27.201721 Write leveling : PASS
7083 16:30:27.201814 RX DQS gating : PASS
7084 16:30:27.204692 RX DQ/DQS(RDDQC) : PASS
7085 16:30:27.208316 TX DQ/DQS : PASS
7086 16:30:27.208411 RX DATLAT : PASS
7087 16:30:27.211257 RX DQ/DQS(Engine): PASS
7088 16:30:27.214722 TX OE : NO K
7089 16:30:27.214797 All Pass.
7090 16:30:27.214856
7091 16:30:27.214910 CH 1, Rank 1
7092 16:30:27.218349 SW Impedance : PASS
7093 16:30:27.221270 DUTY Scan : NO K
7094 16:30:27.221361 ZQ Calibration : PASS
7095 16:30:27.224778 Jitter Meter : NO K
7096 16:30:27.228175 CBT Training : PASS
7097 16:30:27.228240 Write leveling : NO K
7098 16:30:27.231608 RX DQS gating : PASS
7099 16:30:27.231679 RX DQ/DQS(RDDQC) : PASS
7100 16:30:27.234444 TX DQ/DQS : PASS
7101 16:30:27.238082 RX DATLAT : PASS
7102 16:30:27.238154 RX DQ/DQS(Engine): PASS
7103 16:30:27.240921 TX OE : NO K
7104 16:30:27.240988 All Pass.
7105 16:30:27.241045
7106 16:30:27.244671 DramC Write-DBI off
7107 16:30:27.247666 PER_BANK_REFRESH: Hybrid Mode
7108 16:30:27.247741 TX_TRACKING: ON
7109 16:30:27.257715 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7110 16:30:27.261261 [FAST_K] Save calibration result to emmc
7111 16:30:27.264916 dramc_set_vcore_voltage set vcore to 725000
7112 16:30:27.268260 Read voltage for 1600, 0
7113 16:30:27.268348 Vio18 = 0
7114 16:30:27.271090 Vcore = 725000
7115 16:30:27.271175 Vdram = 0
7116 16:30:27.271256 Vddq = 0
7117 16:30:27.271333 Vmddr = 0
7118 16:30:27.278235 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7119 16:30:27.281035 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7120 16:30:27.284722 MEM_TYPE=3, freq_sel=13
7121 16:30:27.287682 sv_algorithm_assistance_LP4_3733
7122 16:30:27.291502 ============ PULL DRAM RESETB DOWN ============
7123 16:30:27.297345 ========== PULL DRAM RESETB DOWN end =========
7124 16:30:27.300935 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7125 16:30:27.304198 ===================================
7126 16:30:27.307576 LPDDR4 DRAM CONFIGURATION
7127 16:30:27.310816 ===================================
7128 16:30:27.310895 EX_ROW_EN[0] = 0x0
7129 16:30:27.314671 EX_ROW_EN[1] = 0x0
7130 16:30:27.314750 LP4Y_EN = 0x0
7131 16:30:27.317902 WORK_FSP = 0x1
7132 16:30:27.317981 WL = 0x5
7133 16:30:27.320750 RL = 0x5
7134 16:30:27.320827 BL = 0x2
7135 16:30:27.324354 RPST = 0x0
7136 16:30:27.324432 RD_PRE = 0x0
7137 16:30:27.327385 WR_PRE = 0x1
7138 16:30:27.327463 WR_PST = 0x1
7139 16:30:27.331046 DBI_WR = 0x0
7140 16:30:27.334543 DBI_RD = 0x0
7141 16:30:27.334634 OTF = 0x1
7142 16:30:27.337347 ===================================
7143 16:30:27.340929 ===================================
7144 16:30:27.341007 ANA top config
7145 16:30:27.344450 ===================================
7146 16:30:27.347350 DLL_ASYNC_EN = 0
7147 16:30:27.350827 ALL_SLAVE_EN = 0
7148 16:30:27.353720 NEW_RANK_MODE = 1
7149 16:30:27.357122 DLL_IDLE_MODE = 1
7150 16:30:27.357243 LP45_APHY_COMB_EN = 1
7151 16:30:27.360547 TX_ODT_DIS = 0
7152 16:30:27.364189 NEW_8X_MODE = 1
7153 16:30:27.367132 ===================================
7154 16:30:27.370775 ===================================
7155 16:30:27.373705 data_rate = 3200
7156 16:30:27.377277 CKR = 1
7157 16:30:27.377406 DQ_P2S_RATIO = 8
7158 16:30:27.380701 ===================================
7159 16:30:27.384171 CA_P2S_RATIO = 8
7160 16:30:27.386904 DQ_CA_OPEN = 0
7161 16:30:27.390618 DQ_SEMI_OPEN = 0
7162 16:30:27.393618 CA_SEMI_OPEN = 0
7163 16:30:27.397408 CA_FULL_RATE = 0
7164 16:30:27.397521 DQ_CKDIV4_EN = 0
7165 16:30:27.400357 CA_CKDIV4_EN = 0
7166 16:30:27.404018 CA_PREDIV_EN = 0
7167 16:30:27.406958 PH8_DLY = 12
7168 16:30:27.410535 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7169 16:30:27.413398 DQ_AAMCK_DIV = 4
7170 16:30:27.413496 CA_AAMCK_DIV = 4
7171 16:30:27.417110 CA_ADMCK_DIV = 4
7172 16:30:27.420746 DQ_TRACK_CA_EN = 0
7173 16:30:27.424176 CA_PICK = 1600
7174 16:30:27.426901 CA_MCKIO = 1600
7175 16:30:27.430175 MCKIO_SEMI = 0
7176 16:30:27.433984 PLL_FREQ = 3068
7177 16:30:27.434102 DQ_UI_PI_RATIO = 32
7178 16:30:27.437315 CA_UI_PI_RATIO = 0
7179 16:30:27.440349 ===================================
7180 16:30:27.443935 ===================================
7181 16:30:27.447431 memory_type:LPDDR4
7182 16:30:27.450286 GP_NUM : 10
7183 16:30:27.450364 SRAM_EN : 1
7184 16:30:27.453935 MD32_EN : 0
7185 16:30:27.457529 ===================================
7186 16:30:27.457612 [ANA_INIT] >>>>>>>>>>>>>>
7187 16:30:27.460501 <<<<<< [CONFIGURE PHASE]: ANA_TX
7188 16:30:27.464073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7189 16:30:27.467664 ===================================
7190 16:30:27.470550 data_rate = 3200,PCW = 0X7600
7191 16:30:27.474172 ===================================
7192 16:30:27.477037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7193 16:30:27.484107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7194 16:30:27.490549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 16:30:27.494005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7196 16:30:27.498350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7197 16:30:27.500467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7198 16:30:27.503445 [ANA_INIT] flow start
7199 16:30:27.503542 [ANA_INIT] PLL >>>>>>>>
7200 16:30:27.507012 [ANA_INIT] PLL <<<<<<<<
7201 16:30:27.510612 [ANA_INIT] MIDPI >>>>>>>>
7202 16:30:27.510685 [ANA_INIT] MIDPI <<<<<<<<
7203 16:30:27.514192 [ANA_INIT] DLL >>>>>>>>
7204 16:30:27.517106 [ANA_INIT] DLL <<<<<<<<
7205 16:30:27.517216 [ANA_INIT] flow end
7206 16:30:27.523623 ============ LP4 DIFF to SE enter ============
7207 16:30:27.527278 ============ LP4 DIFF to SE exit ============
7208 16:30:27.527381 [ANA_INIT] <<<<<<<<<<<<<
7209 16:30:27.533746 [Flow] Enable top DCM control >>>>>
7210 16:30:27.536567 [Flow] Enable top DCM control <<<<<
7211 16:30:27.536638 Enable DLL master slave shuffle
7212 16:30:27.543199 ==============================================================
7213 16:30:27.546600 Gating Mode config
7214 16:30:27.549983 ==============================================================
7215 16:30:27.553290 Config description:
7216 16:30:27.563583 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7217 16:30:27.569921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7218 16:30:27.573333 SELPH_MODE 0: By rank 1: By Phase
7219 16:30:27.579716 ==============================================================
7220 16:30:27.583340 GAT_TRACK_EN = 1
7221 16:30:27.586298 RX_GATING_MODE = 2
7222 16:30:27.589754 RX_GATING_TRACK_MODE = 2
7223 16:30:27.593171 SELPH_MODE = 1
7224 16:30:27.593255 PICG_EARLY_EN = 1
7225 16:30:27.596137 VALID_LAT_VALUE = 1
7226 16:30:27.603193 ==============================================================
7227 16:30:27.605998 Enter into Gating configuration >>>>
7228 16:30:27.609803 Exit from Gating configuration <<<<
7229 16:30:27.612809 Enter into DVFS_PRE_config >>>>>
7230 16:30:27.623249 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7231 16:30:27.626281 Exit from DVFS_PRE_config <<<<<
7232 16:30:27.630064 Enter into PICG configuration >>>>
7233 16:30:27.632996 Exit from PICG configuration <<<<
7234 16:30:27.636638 [RX_INPUT] configuration >>>>>
7235 16:30:27.639622 [RX_INPUT] configuration <<<<<
7236 16:30:27.643182 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7237 16:30:27.649405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7238 16:30:27.655937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 16:30:27.663019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 16:30:27.669744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7241 16:30:27.673196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7242 16:30:27.679587 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7243 16:30:27.683039 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7244 16:30:27.686351 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7245 16:30:27.689758 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7246 16:30:27.696504 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7247 16:30:27.699220 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 16:30:27.702690 ===================================
7249 16:30:27.706180 LPDDR4 DRAM CONFIGURATION
7250 16:30:27.709463 ===================================
7251 16:30:27.709539 EX_ROW_EN[0] = 0x0
7252 16:30:27.712377 EX_ROW_EN[1] = 0x0
7253 16:30:27.712446 LP4Y_EN = 0x0
7254 16:30:27.716138 WORK_FSP = 0x1
7255 16:30:27.716204 WL = 0x5
7256 16:30:27.719819 RL = 0x5
7257 16:30:27.719896 BL = 0x2
7258 16:30:27.722788 RPST = 0x0
7259 16:30:27.722864 RD_PRE = 0x0
7260 16:30:27.726240 WR_PRE = 0x1
7261 16:30:27.729151 WR_PST = 0x1
7262 16:30:27.729274 DBI_WR = 0x0
7263 16:30:27.732844 DBI_RD = 0x0
7264 16:30:27.732958 OTF = 0x1
7265 16:30:27.735999 ===================================
7266 16:30:27.738963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7267 16:30:27.742539 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7268 16:30:27.749225 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7269 16:30:27.752680 ===================================
7270 16:30:27.756107 LPDDR4 DRAM CONFIGURATION
7271 16:30:27.759539 ===================================
7272 16:30:27.759627 EX_ROW_EN[0] = 0x10
7273 16:30:27.762391 EX_ROW_EN[1] = 0x0
7274 16:30:27.762470 LP4Y_EN = 0x0
7275 16:30:27.766013 WORK_FSP = 0x1
7276 16:30:27.766094 WL = 0x5
7277 16:30:27.768900 RL = 0x5
7278 16:30:27.768978 BL = 0x2
7279 16:30:27.772663 RPST = 0x0
7280 16:30:27.772746 RD_PRE = 0x0
7281 16:30:27.776106 WR_PRE = 0x1
7282 16:30:27.776184 WR_PST = 0x1
7283 16:30:27.779414 DBI_WR = 0x0
7284 16:30:27.779493 DBI_RD = 0x0
7285 16:30:27.782163 OTF = 0x1
7286 16:30:27.785696 ===================================
7287 16:30:27.792270 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7288 16:30:27.792364 ==
7289 16:30:27.795816 Dram Type= 6, Freq= 0, CH_0, rank 0
7290 16:30:27.799266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 16:30:27.799347 ==
7292 16:30:27.802607 [Duty_Offset_Calibration]
7293 16:30:27.802684 B0:2 B1:1 CA:1
7294 16:30:27.802744
7295 16:30:27.806017 [DutyScan_Calibration_Flow] k_type=0
7296 16:30:27.816950
7297 16:30:27.817055 ==CLK 0==
7298 16:30:27.820206 Final CLK duty delay cell = 0
7299 16:30:27.823458 [0] MAX Duty = 5156%(X100), DQS PI = 22
7300 16:30:27.826938 [0] MIN Duty = 4876%(X100), DQS PI = 48
7301 16:30:27.829856 [0] AVG Duty = 5016%(X100)
7302 16:30:27.829956
7303 16:30:27.833438 CH0 CLK Duty spec in!! Max-Min= 280%
7304 16:30:27.836395 [DutyScan_Calibration_Flow] ====Done====
7305 16:30:27.836496
7306 16:30:27.840005 [DutyScan_Calibration_Flow] k_type=1
7307 16:30:27.856067
7308 16:30:27.856190 ==DQS 0 ==
7309 16:30:27.859635 Final DQS duty delay cell = -4
7310 16:30:27.862475 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7311 16:30:27.865807 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7312 16:30:27.869137 [-4] AVG Duty = 4891%(X100)
7313 16:30:27.869212
7314 16:30:27.869271 ==DQS 1 ==
7315 16:30:27.872474 Final DQS duty delay cell = 0
7316 16:30:27.876150 [0] MAX Duty = 5187%(X100), DQS PI = 20
7317 16:30:27.879129 [0] MIN Duty = 5031%(X100), DQS PI = 30
7318 16:30:27.882749 [0] AVG Duty = 5109%(X100)
7319 16:30:27.882829
7320 16:30:27.885689 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7321 16:30:27.885765
7322 16:30:27.889166 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7323 16:30:27.892756 [DutyScan_Calibration_Flow] ====Done====
7324 16:30:27.892855
7325 16:30:27.895576 [DutyScan_Calibration_Flow] k_type=3
7326 16:30:27.913435
7327 16:30:27.913537 ==DQM 0 ==
7328 16:30:27.916976 Final DQM duty delay cell = 0
7329 16:30:27.919818 [0] MAX Duty = 5187%(X100), DQS PI = 26
7330 16:30:27.923470 [0] MIN Duty = 4907%(X100), DQS PI = 54
7331 16:30:27.923547 [0] AVG Duty = 5047%(X100)
7332 16:30:27.927167
7333 16:30:27.927243 ==DQM 1 ==
7334 16:30:27.929994 Final DQM duty delay cell = 0
7335 16:30:27.933367 [0] MAX Duty = 5187%(X100), DQS PI = 4
7336 16:30:27.936792 [0] MIN Duty = 5062%(X100), DQS PI = 14
7337 16:30:27.936861 [0] AVG Duty = 5124%(X100)
7338 16:30:27.940122
7339 16:30:27.943499 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7340 16:30:27.943574
7341 16:30:27.946503 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7342 16:30:27.950195 [DutyScan_Calibration_Flow] ====Done====
7343 16:30:27.950360
7344 16:30:27.953125 [DutyScan_Calibration_Flow] k_type=2
7345 16:30:27.970769
7346 16:30:27.970852 ==DQ 0 ==
7347 16:30:27.973663 Final DQ duty delay cell = 0
7348 16:30:27.977125 [0] MAX Duty = 5062%(X100), DQS PI = 26
7349 16:30:27.980473 [0] MIN Duty = 4907%(X100), DQS PI = 0
7350 16:30:27.980593 [0] AVG Duty = 4984%(X100)
7351 16:30:27.980704
7352 16:30:27.983768 ==DQ 1 ==
7353 16:30:27.987271 Final DQ duty delay cell = 0
7354 16:30:27.990201 [0] MAX Duty = 5125%(X100), DQS PI = 6
7355 16:30:27.993849 [0] MIN Duty = 4907%(X100), DQS PI = 34
7356 16:30:27.993927 [0] AVG Duty = 5016%(X100)
7357 16:30:27.994011
7358 16:30:27.997401 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7359 16:30:27.997510
7360 16:30:28.000941 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7361 16:30:28.007521 [DutyScan_Calibration_Flow] ====Done====
7362 16:30:28.007646 ==
7363 16:30:28.010440 Dram Type= 6, Freq= 0, CH_1, rank 0
7364 16:30:28.014010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7365 16:30:28.014126 ==
7366 16:30:28.017485 [Duty_Offset_Calibration]
7367 16:30:28.017640 B0:1 B1:0 CA:0
7368 16:30:28.017701
7369 16:30:28.020252 [DutyScan_Calibration_Flow] k_type=0
7370 16:30:28.029644
7371 16:30:28.029779 ==CLK 0==
7372 16:30:28.033224 Final CLK duty delay cell = -4
7373 16:30:28.036808 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7374 16:30:28.039674 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7375 16:30:28.043071 [-4] AVG Duty = 4922%(X100)
7376 16:30:28.043145
7377 16:30:28.046681 CH1 CLK Duty spec in!! Max-Min= 156%
7378 16:30:28.049605 [DutyScan_Calibration_Flow] ====Done====
7379 16:30:28.049682
7380 16:30:28.052992 [DutyScan_Calibration_Flow] k_type=1
7381 16:30:28.069818
7382 16:30:28.069895 ==DQS 0 ==
7383 16:30:28.073579 Final DQS duty delay cell = 0
7384 16:30:28.076521 [0] MAX Duty = 5062%(X100), DQS PI = 8
7385 16:30:28.080201 [0] MIN Duty = 4844%(X100), DQS PI = 0
7386 16:30:28.080277 [0] AVG Duty = 4953%(X100)
7387 16:30:28.083100
7388 16:30:28.083175 ==DQS 1 ==
7389 16:30:28.086636 Final DQS duty delay cell = 0
7390 16:30:28.089361 [0] MAX Duty = 5249%(X100), DQS PI = 18
7391 16:30:28.092792 [0] MIN Duty = 4938%(X100), DQS PI = 8
7392 16:30:28.092868 [0] AVG Duty = 5093%(X100)
7393 16:30:28.096451
7394 16:30:28.099738 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7395 16:30:28.099804
7396 16:30:28.103072 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7397 16:30:28.106354 [DutyScan_Calibration_Flow] ====Done====
7398 16:30:28.106422
7399 16:30:28.109177 [DutyScan_Calibration_Flow] k_type=3
7400 16:30:28.126718
7401 16:30:28.126797 ==DQM 0 ==
7402 16:30:28.129688 Final DQM duty delay cell = 0
7403 16:30:28.133329 [0] MAX Duty = 5187%(X100), DQS PI = 10
7404 16:30:28.136197 [0] MIN Duty = 4969%(X100), DQS PI = 48
7405 16:30:28.139837 [0] AVG Duty = 5078%(X100)
7406 16:30:28.139912
7407 16:30:28.139973 ==DQM 1 ==
7408 16:30:28.142749 Final DQM duty delay cell = 0
7409 16:30:28.146353 [0] MAX Duty = 5093%(X100), DQS PI = 16
7410 16:30:28.149885 [0] MIN Duty = 4907%(X100), DQS PI = 34
7411 16:30:28.152857 [0] AVG Duty = 5000%(X100)
7412 16:30:28.152932
7413 16:30:28.156596 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7414 16:30:28.156673
7415 16:30:28.159334 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7416 16:30:28.162736 [DutyScan_Calibration_Flow] ====Done====
7417 16:30:28.162810
7418 16:30:28.166412 [DutyScan_Calibration_Flow] k_type=2
7419 16:30:28.182338
7420 16:30:28.182412 ==DQ 0 ==
7421 16:30:28.185887 Final DQ duty delay cell = -4
7422 16:30:28.189688 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7423 16:30:28.192454 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7424 16:30:28.196035 [-4] AVG Duty = 4937%(X100)
7425 16:30:28.196104
7426 16:30:28.196160 ==DQ 1 ==
7427 16:30:28.199645 Final DQ duty delay cell = 0
7428 16:30:28.202396 [0] MAX Duty = 5124%(X100), DQS PI = 18
7429 16:30:28.206001 [0] MIN Duty = 4938%(X100), DQS PI = 10
7430 16:30:28.208905 [0] AVG Duty = 5031%(X100)
7431 16:30:28.209004
7432 16:30:28.212400 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7433 16:30:28.212481
7434 16:30:28.215778 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7435 16:30:28.219196 [DutyScan_Calibration_Flow] ====Done====
7436 16:30:28.222476 nWR fixed to 30
7437 16:30:28.225858 [ModeRegInit_LP4] CH0 RK0
7438 16:30:28.225928 [ModeRegInit_LP4] CH0 RK1
7439 16:30:28.229218 [ModeRegInit_LP4] CH1 RK0
7440 16:30:28.232182 [ModeRegInit_LP4] CH1 RK1
7441 16:30:28.232246 match AC timing 5
7442 16:30:28.239236 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7443 16:30:28.242224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7444 16:30:28.245799 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7445 16:30:28.252148 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7446 16:30:28.255744 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7447 16:30:28.255819 [MiockJmeterHQA]
7448 16:30:28.255877
7449 16:30:28.258705 [DramcMiockJmeter] u1RxGatingPI = 0
7450 16:30:28.262391 0 : 4255, 4027
7451 16:30:28.262468 4 : 4253, 4027
7452 16:30:28.265207 8 : 4252, 4027
7453 16:30:28.265306 12 : 4363, 4138
7454 16:30:28.268610 16 : 4252, 4027
7455 16:30:28.268691 20 : 4253, 4026
7456 16:30:28.268754 24 : 4252, 4027
7457 16:30:28.272044 28 : 4363, 4137
7458 16:30:28.272119 32 : 4253, 4027
7459 16:30:28.275478 36 : 4363, 4138
7460 16:30:28.275554 40 : 4253, 4026
7461 16:30:28.278457 44 : 4252, 4027
7462 16:30:28.278532 48 : 4253, 4026
7463 16:30:28.282203 52 : 4255, 4030
7464 16:30:28.282278 56 : 4362, 4137
7465 16:30:28.282337 60 : 4250, 4026
7466 16:30:28.285318 64 : 4360, 4138
7467 16:30:28.285418 68 : 4249, 4027
7468 16:30:28.289050 72 : 4250, 4027
7469 16:30:28.289125 76 : 4249, 4027
7470 16:30:28.292404 80 : 4363, 4137
7471 16:30:28.292504 84 : 4250, 4026
7472 16:30:28.292590 88 : 4360, 48
7473 16:30:28.295462 92 : 4363, 0
7474 16:30:28.295538 96 : 4248, 0
7475 16:30:28.298927 100 : 4363, 0
7476 16:30:28.299003 104 : 4361, 0
7477 16:30:28.299061 108 : 4249, 0
7478 16:30:28.301831 112 : 4250, 0
7479 16:30:28.301907 116 : 4250, 0
7480 16:30:28.301965 120 : 4250, 0
7481 16:30:28.305304 124 : 4250, 0
7482 16:30:28.305404 128 : 4360, 0
7483 16:30:28.308735 132 : 4250, 0
7484 16:30:28.308811 136 : 4250, 0
7485 16:30:28.308869 140 : 4250, 0
7486 16:30:28.312195 144 : 4360, 0
7487 16:30:28.312271 148 : 4250, 0
7488 16:30:28.315120 152 : 4250, 0
7489 16:30:28.315201 156 : 4252, 0
7490 16:30:28.315262 160 : 4250, 0
7491 16:30:28.318701 164 : 4250, 0
7492 16:30:28.318777 168 : 4249, 0
7493 16:30:28.322315 172 : 4250, 0
7494 16:30:28.322391 176 : 4250, 0
7495 16:30:28.322449 180 : 4360, 0
7496 16:30:28.325161 184 : 4250, 0
7497 16:30:28.325268 188 : 4250, 0
7498 16:30:28.325377 192 : 4250, 0
7499 16:30:28.328713 196 : 4361, 0
7500 16:30:28.328788 200 : 4360, 0
7501 16:30:28.332234 204 : 4250, 1326
7502 16:30:28.332309 208 : 4250, 3989
7503 16:30:28.335614 212 : 4253, 4029
7504 16:30:28.335689 216 : 4249, 4027
7505 16:30:28.338859 220 : 4360, 4137
7506 16:30:28.338935 224 : 4250, 4026
7507 16:30:28.342224 228 : 4250, 4027
7508 16:30:28.342299 232 : 4360, 4138
7509 16:30:28.342358 236 : 4360, 4137
7510 16:30:28.345697 240 : 4250, 4026
7511 16:30:28.345785 244 : 4361, 4137
7512 16:30:28.348932 248 : 4250, 4027
7513 16:30:28.349012 252 : 4252, 4027
7514 16:30:28.351710 256 : 4253, 4026
7515 16:30:28.351787 260 : 4250, 4026
7516 16:30:28.355052 264 : 4250, 4027
7517 16:30:28.355129 268 : 4249, 4027
7518 16:30:28.358480 272 : 4250, 4026
7519 16:30:28.358557 276 : 4250, 4026
7520 16:30:28.362017 280 : 4250, 4027
7521 16:30:28.362094 284 : 4360, 4138
7522 16:30:28.365076 288 : 4360, 4137
7523 16:30:28.365152 292 : 4250, 4027
7524 16:30:28.365213 296 : 4361, 4137
7525 16:30:28.368730 300 : 4250, 4027
7526 16:30:28.368807 304 : 4249, 4027
7527 16:30:28.371726 308 : 4250, 3979
7528 16:30:28.371803 312 : 4250, 2140
7529 16:30:28.375378 316 : 4250, 7
7530 16:30:28.375455
7531 16:30:28.375513 MIOCK jitter meter ch=0
7532 16:30:28.378334
7533 16:30:28.378409 1T = (316-88) = 228 dly cells
7534 16:30:28.385121 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7535 16:30:28.385214 ==
7536 16:30:28.388134 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 16:30:28.391960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 16:30:28.392036 ==
7539 16:30:28.398342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 16:30:28.401991 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 16:30:28.408452 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 16:30:28.411437 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 16:30:28.421760 [CA 0] Center 43 (12~74) winsize 63
7544 16:30:28.424608 [CA 1] Center 43 (12~74) winsize 63
7545 16:30:28.428387 [CA 2] Center 38 (9~68) winsize 60
7546 16:30:28.431301 [CA 3] Center 38 (8~68) winsize 61
7547 16:30:28.434890 [CA 4] Center 36 (7~66) winsize 60
7548 16:30:28.437887 [CA 5] Center 36 (7~65) winsize 59
7549 16:30:28.437963
7550 16:30:28.441460 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 16:30:28.441596
7552 16:30:28.444902 [CATrainingPosCal] consider 1 rank data
7553 16:30:28.448327 u2DelayCellTimex100 = 285/100 ps
7554 16:30:28.451746 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7555 16:30:28.458573 CA1 delay=43 (12~74),Diff = 7 PI (23 cell)
7556 16:30:28.461260 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7557 16:30:28.464883 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7558 16:30:28.468409 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7559 16:30:28.471906 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7560 16:30:28.471981
7561 16:30:28.474857 CA PerBit enable=1, Macro0, CA PI delay=36
7562 16:30:28.474932
7563 16:30:28.478437 [CBTSetCACLKResult] CA Dly = 36
7564 16:30:28.478513 CS Dly: 9 (0~40)
7565 16:30:28.484990 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 16:30:28.488539 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 16:30:28.488609 ==
7568 16:30:28.491836 Dram Type= 6, Freq= 0, CH_0, rank 1
7569 16:30:28.495268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 16:30:28.495341 ==
7571 16:30:28.501177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 16:30:28.504814 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 16:30:28.511216 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 16:30:28.515028 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 16:30:28.525142 [CA 0] Center 42 (12~72) winsize 61
7576 16:30:28.527960 [CA 1] Center 42 (12~73) winsize 62
7577 16:30:28.531397 [CA 2] Center 37 (8~67) winsize 60
7578 16:30:28.535009 [CA 3] Center 37 (7~68) winsize 62
7579 16:30:28.537982 [CA 4] Center 35 (5~65) winsize 61
7580 16:30:28.541702 [CA 5] Center 35 (5~65) winsize 61
7581 16:30:28.541777
7582 16:30:28.544507 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7583 16:30:28.544581
7584 16:30:28.548170 [CATrainingPosCal] consider 2 rank data
7585 16:30:28.551070 u2DelayCellTimex100 = 285/100 ps
7586 16:30:28.554491 CA0 delay=42 (12~72),Diff = 6 PI (20 cell)
7587 16:30:28.561430 CA1 delay=42 (12~73),Diff = 6 PI (20 cell)
7588 16:30:28.564817 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7589 16:30:28.568126 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7590 16:30:28.571407 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7591 16:30:28.574774 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7592 16:30:28.574849
7593 16:30:28.578122 CA PerBit enable=1, Macro0, CA PI delay=36
7594 16:30:28.578197
7595 16:30:28.581583 [CBTSetCACLKResult] CA Dly = 36
7596 16:30:28.581657 CS Dly: 10 (0~42)
7597 16:30:28.588187 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 16:30:28.591082 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 16:30:28.591156
7600 16:30:28.594750 ----->DramcWriteLeveling(PI) begin...
7601 16:30:28.594825 ==
7602 16:30:28.598309 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 16:30:28.601687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 16:30:28.604405 ==
7605 16:30:28.604506 Write leveling (Byte 0): 34 => 34
7606 16:30:28.608180 Write leveling (Byte 1): 26 => 26
7607 16:30:28.611132 DramcWriteLeveling(PI) end<-----
7608 16:30:28.611207
7609 16:30:28.611268 ==
7610 16:30:28.614606 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 16:30:28.621149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 16:30:28.621227 ==
7613 16:30:28.621286 [Gating] SW mode calibration
7614 16:30:28.631466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7615 16:30:28.634363 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7616 16:30:28.637945 1 4 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7617 16:30:28.644781 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 16:30:28.647672 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7619 16:30:28.651320 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7620 16:30:28.658090 1 4 16 | B1->B0 | 2525 3636 | 0 1 | (0 0) (1 1)
7621 16:30:28.660968 1 4 20 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7622 16:30:28.664505 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7623 16:30:28.671136 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7624 16:30:28.674497 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7625 16:30:28.677887 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7626 16:30:28.684317 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7627 16:30:28.687854 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7628 16:30:28.691368 1 5 16 | B1->B0 | 3333 2424 | 0 0 | (0 0) (1 0)
7629 16:30:28.697479 1 5 20 | B1->B0 | 2828 2525 | 0 0 | (1 0) (1 1)
7630 16:30:28.701023 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7631 16:30:28.704549 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 16:30:28.710763 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7633 16:30:28.714169 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7634 16:30:28.717821 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
7635 16:30:28.724280 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7636 16:30:28.727905 1 6 16 | B1->B0 | 2a29 4645 | 1 1 | (0 0) (0 0)
7637 16:30:28.730906 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 16:30:28.737488 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7639 16:30:28.741136 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 16:30:28.743987 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 16:30:28.750856 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 16:30:28.753798 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 16:30:28.757303 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 16:30:28.764040 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 16:30:28.767684 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 16:30:28.770525 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 16:30:28.777765 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 16:30:28.780564 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 16:30:28.783959 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 16:30:28.787541 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 16:30:28.794155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 16:30:28.797723 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 16:30:28.800381 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 16:30:28.807118 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 16:30:28.810571 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 16:30:28.813927 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 16:30:28.820722 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 16:30:28.824017 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 16:30:28.827626 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 16:30:28.833520 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7661 16:30:28.833657 Total UI for P1: 0, mck2ui 16
7662 16:30:28.840254 best dqsien dly found for B0: ( 1, 9, 10)
7663 16:30:28.843975 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7664 16:30:28.846947 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 16:30:28.850608 Total UI for P1: 0, mck2ui 16
7666 16:30:28.854129 best dqsien dly found for B1: ( 1, 9, 18)
7667 16:30:28.856927 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7668 16:30:28.860294 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7669 16:30:28.860369
7670 16:30:28.867165 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7671 16:30:28.870081 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7672 16:30:28.873691 [Gating] SW calibration Done
7673 16:30:28.873766 ==
7674 16:30:28.876679 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 16:30:28.880324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 16:30:28.880400 ==
7677 16:30:28.880458 RX Vref Scan: 0
7678 16:30:28.880512
7679 16:30:28.884026 RX Vref 0 -> 0, step: 1
7680 16:30:28.884101
7681 16:30:28.886743 RX Delay 0 -> 252, step: 8
7682 16:30:28.890066 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7683 16:30:28.893841 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7684 16:30:28.896763 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7685 16:30:28.903412 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7686 16:30:28.907182 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7687 16:30:28.910135 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7688 16:30:28.913776 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7689 16:30:28.917152 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7690 16:30:28.923334 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7691 16:30:28.926839 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7692 16:30:28.930117 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7693 16:30:28.933397 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7694 16:30:28.936718 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7695 16:30:28.943441 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7696 16:30:28.946876 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7697 16:30:28.950357 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7698 16:30:28.950431 ==
7699 16:30:28.953250 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 16:30:28.956857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 16:30:28.959793 ==
7702 16:30:28.959868 DQS Delay:
7703 16:30:28.959926 DQS0 = 0, DQS1 = 0
7704 16:30:28.963426 DQM Delay:
7705 16:30:28.963501 DQM0 = 137, DQM1 = 130
7706 16:30:28.966332 DQ Delay:
7707 16:30:28.969751 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7708 16:30:28.973230 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7709 16:30:28.976448 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7710 16:30:28.979381 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7711 16:30:28.979456
7712 16:30:28.979515
7713 16:30:28.979568 ==
7714 16:30:28.983155 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 16:30:28.986111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 16:30:28.989130 ==
7717 16:30:28.989205
7718 16:30:28.989262
7719 16:30:28.989314 TX Vref Scan disable
7720 16:30:28.992753 == TX Byte 0 ==
7721 16:30:28.996299 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7722 16:30:28.999118 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7723 16:30:29.002742 == TX Byte 1 ==
7724 16:30:29.006128 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7725 16:30:29.009061 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7726 16:30:29.012187 ==
7727 16:30:29.015878 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 16:30:29.018971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 16:30:29.019050 ==
7730 16:30:29.032098
7731 16:30:29.035500 TX Vref early break, caculate TX vref
7732 16:30:29.038419 TX Vref=16, minBit 0, minWin=23, winSum=378
7733 16:30:29.042166 TX Vref=18, minBit 3, minWin=23, winSum=386
7734 16:30:29.045024 TX Vref=20, minBit 0, minWin=24, winSum=399
7735 16:30:29.048525 TX Vref=22, minBit 1, minWin=25, winSum=413
7736 16:30:29.051997 TX Vref=24, minBit 7, minWin=25, winSum=416
7737 16:30:29.058616 TX Vref=26, minBit 8, minWin=25, winSum=428
7738 16:30:29.061766 TX Vref=28, minBit 6, minWin=25, winSum=427
7739 16:30:29.065088 TX Vref=30, minBit 0, minWin=25, winSum=416
7740 16:30:29.068733 TX Vref=32, minBit 1, minWin=24, winSum=409
7741 16:30:29.071716 TX Vref=34, minBit 6, minWin=23, winSum=398
7742 16:30:29.078889 [TxChooseVref] Worse bit 8, Min win 25, Win sum 428, Final Vref 26
7743 16:30:29.078964
7744 16:30:29.082467 Final TX Range 0 Vref 26
7745 16:30:29.082542
7746 16:30:29.082599 ==
7747 16:30:29.085223 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 16:30:29.088909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 16:30:29.088984 ==
7750 16:30:29.089056
7751 16:30:29.089124
7752 16:30:29.092020 TX Vref Scan disable
7753 16:30:29.099019 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7754 16:30:29.099097 == TX Byte 0 ==
7755 16:30:29.101892 u2DelayCellOfst[0]=10 cells (3 PI)
7756 16:30:29.105478 u2DelayCellOfst[1]=13 cells (4 PI)
7757 16:30:29.108444 u2DelayCellOfst[2]=10 cells (3 PI)
7758 16:30:29.112039 u2DelayCellOfst[3]=10 cells (3 PI)
7759 16:30:29.115606 u2DelayCellOfst[4]=10 cells (3 PI)
7760 16:30:29.118660 u2DelayCellOfst[5]=0 cells (0 PI)
7761 16:30:29.122226 u2DelayCellOfst[6]=17 cells (5 PI)
7762 16:30:29.122301 u2DelayCellOfst[7]=13 cells (4 PI)
7763 16:30:29.128806 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7764 16:30:29.131674 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7765 16:30:29.131774 == TX Byte 1 ==
7766 16:30:29.135140 u2DelayCellOfst[8]=0 cells (0 PI)
7767 16:30:29.138735 u2DelayCellOfst[9]=0 cells (0 PI)
7768 16:30:29.142255 u2DelayCellOfst[10]=3 cells (1 PI)
7769 16:30:29.145205 u2DelayCellOfst[11]=3 cells (1 PI)
7770 16:30:29.148718 u2DelayCellOfst[12]=10 cells (3 PI)
7771 16:30:29.151612 u2DelayCellOfst[13]=6 cells (2 PI)
7772 16:30:29.155269 u2DelayCellOfst[14]=10 cells (3 PI)
7773 16:30:29.158857 u2DelayCellOfst[15]=6 cells (2 PI)
7774 16:30:29.161856 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7775 16:30:29.168224 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7776 16:30:29.168299 DramC Write-DBI on
7777 16:30:29.168357 ==
7778 16:30:29.171741 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 16:30:29.175087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 16:30:29.175162 ==
7781 16:30:29.177910
7782 16:30:29.177983
7783 16:30:29.178041 TX Vref Scan disable
7784 16:30:29.181581 == TX Byte 0 ==
7785 16:30:29.184656 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7786 16:30:29.188381 == TX Byte 1 ==
7787 16:30:29.191294 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7788 16:30:29.194961 DramC Write-DBI off
7789 16:30:29.195035
7790 16:30:29.195092 [DATLAT]
7791 16:30:29.195145 Freq=1600, CH0 RK0
7792 16:30:29.195197
7793 16:30:29.198409 DATLAT Default: 0xf
7794 16:30:29.198482 0, 0xFFFF, sum = 0
7795 16:30:29.201720 1, 0xFFFF, sum = 0
7796 16:30:29.204471 2, 0xFFFF, sum = 0
7797 16:30:29.204547 3, 0xFFFF, sum = 0
7798 16:30:29.207854 4, 0xFFFF, sum = 0
7799 16:30:29.207929 5, 0xFFFF, sum = 0
7800 16:30:29.211684 6, 0xFFFF, sum = 0
7801 16:30:29.211760 7, 0xFFFF, sum = 0
7802 16:30:29.215044 8, 0xFFFF, sum = 0
7803 16:30:29.215119 9, 0xFFFF, sum = 0
7804 16:30:29.218277 10, 0xFFFF, sum = 0
7805 16:30:29.218353 11, 0xFFFF, sum = 0
7806 16:30:29.221578 12, 0xFFFF, sum = 0
7807 16:30:29.221655 13, 0xFFFF, sum = 0
7808 16:30:29.225015 14, 0x0, sum = 1
7809 16:30:29.225091 15, 0x0, sum = 2
7810 16:30:29.227970 16, 0x0, sum = 3
7811 16:30:29.228045 17, 0x0, sum = 4
7812 16:30:29.231621 best_step = 15
7813 16:30:29.231695
7814 16:30:29.231753 ==
7815 16:30:29.234502 Dram Type= 6, Freq= 0, CH_0, rank 0
7816 16:30:29.237902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7817 16:30:29.237976 ==
7818 16:30:29.241407 RX Vref Scan: 1
7819 16:30:29.241503
7820 16:30:29.241613 Set Vref Range= 24 -> 127
7821 16:30:29.241670
7822 16:30:29.244399 RX Vref 24 -> 127, step: 1
7823 16:30:29.244473
7824 16:30:29.248059 RX Delay 27 -> 252, step: 4
7825 16:30:29.248134
7826 16:30:29.251507 Set Vref, RX VrefLevel [Byte0]: 24
7827 16:30:29.254325 [Byte1]: 24
7828 16:30:29.254400
7829 16:30:29.258099 Set Vref, RX VrefLevel [Byte0]: 25
7830 16:30:29.260967 [Byte1]: 25
7831 16:30:29.261067
7832 16:30:29.264610 Set Vref, RX VrefLevel [Byte0]: 26
7833 16:30:29.267477 [Byte1]: 26
7834 16:30:29.271792
7835 16:30:29.271870 Set Vref, RX VrefLevel [Byte0]: 27
7836 16:30:29.274664 [Byte1]: 27
7837 16:30:29.278944
7838 16:30:29.279018 Set Vref, RX VrefLevel [Byte0]: 28
7839 16:30:29.282331 [Byte1]: 28
7840 16:30:29.286622
7841 16:30:29.286696 Set Vref, RX VrefLevel [Byte0]: 29
7842 16:30:29.290153 [Byte1]: 29
7843 16:30:29.294510
7844 16:30:29.294584 Set Vref, RX VrefLevel [Byte0]: 30
7845 16:30:29.297409 [Byte1]: 30
7846 16:30:29.301938
7847 16:30:29.302011 Set Vref, RX VrefLevel [Byte0]: 31
7848 16:30:29.304805 [Byte1]: 31
7849 16:30:29.309171
7850 16:30:29.312726 Set Vref, RX VrefLevel [Byte0]: 32
7851 16:30:29.315528 [Byte1]: 32
7852 16:30:29.315602
7853 16:30:29.319150 Set Vref, RX VrefLevel [Byte0]: 33
7854 16:30:29.322825 [Byte1]: 33
7855 16:30:29.322900
7856 16:30:29.325697 Set Vref, RX VrefLevel [Byte0]: 34
7857 16:30:29.329135 [Byte1]: 34
7858 16:30:29.329213
7859 16:30:29.332432 Set Vref, RX VrefLevel [Byte0]: 35
7860 16:30:29.335727 [Byte1]: 35
7861 16:30:29.339684
7862 16:30:29.339758 Set Vref, RX VrefLevel [Byte0]: 36
7863 16:30:29.342984 [Byte1]: 36
7864 16:30:29.347242
7865 16:30:29.347316 Set Vref, RX VrefLevel [Byte0]: 37
7866 16:30:29.350134 [Byte1]: 37
7867 16:30:29.354433
7868 16:30:29.354507 Set Vref, RX VrefLevel [Byte0]: 38
7869 16:30:29.357973 [Byte1]: 38
7870 16:30:29.362030
7871 16:30:29.362128 Set Vref, RX VrefLevel [Byte0]: 39
7872 16:30:29.365434 [Byte1]: 39
7873 16:30:29.369810
7874 16:30:29.369884 Set Vref, RX VrefLevel [Byte0]: 40
7875 16:30:29.372673 [Byte1]: 40
7876 16:30:29.376934
7877 16:30:29.377008 Set Vref, RX VrefLevel [Byte0]: 41
7878 16:30:29.380586 [Byte1]: 41
7879 16:30:29.384816
7880 16:30:29.384914 Set Vref, RX VrefLevel [Byte0]: 42
7881 16:30:29.387614 [Byte1]: 42
7882 16:30:29.392479
7883 16:30:29.392553 Set Vref, RX VrefLevel [Byte0]: 43
7884 16:30:29.395426 [Byte1]: 43
7885 16:30:29.399749
7886 16:30:29.399823 Set Vref, RX VrefLevel [Byte0]: 44
7887 16:30:29.402799 [Byte1]: 44
7888 16:30:29.407134
7889 16:30:29.407209 Set Vref, RX VrefLevel [Byte0]: 45
7890 16:30:29.410657 [Byte1]: 45
7891 16:30:29.414758
7892 16:30:29.414836 Set Vref, RX VrefLevel [Byte0]: 46
7893 16:30:29.418520 [Byte1]: 46
7894 16:30:29.422054
7895 16:30:29.422129 Set Vref, RX VrefLevel [Byte0]: 47
7896 16:30:29.425693 [Byte1]: 47
7897 16:30:29.430030
7898 16:30:29.430105 Set Vref, RX VrefLevel [Byte0]: 48
7899 16:30:29.433071 [Byte1]: 48
7900 16:30:29.437350
7901 16:30:29.437425 Set Vref, RX VrefLevel [Byte0]: 49
7902 16:30:29.440790 [Byte1]: 49
7903 16:30:29.444826
7904 16:30:29.444901 Set Vref, RX VrefLevel [Byte0]: 50
7905 16:30:29.448298 [Byte1]: 50
7906 16:30:29.452317
7907 16:30:29.452392 Set Vref, RX VrefLevel [Byte0]: 51
7908 16:30:29.455520 [Byte1]: 51
7909 16:30:29.459836
7910 16:30:29.459912 Set Vref, RX VrefLevel [Byte0]: 52
7911 16:30:29.463498 [Byte1]: 52
7912 16:30:29.467906
7913 16:30:29.467980 Set Vref, RX VrefLevel [Byte0]: 53
7914 16:30:29.470660 [Byte1]: 53
7915 16:30:29.474758
7916 16:30:29.474833 Set Vref, RX VrefLevel [Byte0]: 54
7917 16:30:29.478270 [Byte1]: 54
7918 16:30:29.482640
7919 16:30:29.482715 Set Vref, RX VrefLevel [Byte0]: 55
7920 16:30:29.486269 [Byte1]: 55
7921 16:30:29.489883
7922 16:30:29.489958 Set Vref, RX VrefLevel [Byte0]: 56
7923 16:30:29.493469 [Byte1]: 56
7924 16:30:29.497651
7925 16:30:29.497726 Set Vref, RX VrefLevel [Byte0]: 57
7926 16:30:29.500610 [Byte1]: 57
7927 16:30:29.505121
7928 16:30:29.505195 Set Vref, RX VrefLevel [Byte0]: 58
7929 16:30:29.508776 [Byte1]: 58
7930 16:30:29.512378
7931 16:30:29.512452 Set Vref, RX VrefLevel [Byte0]: 59
7932 16:30:29.515999 [Byte1]: 59
7933 16:30:29.520073
7934 16:30:29.520148 Set Vref, RX VrefLevel [Byte0]: 60
7935 16:30:29.523602 [Byte1]: 60
7936 16:30:29.527877
7937 16:30:29.527952 Set Vref, RX VrefLevel [Byte0]: 61
7938 16:30:29.530698 [Byte1]: 61
7939 16:30:29.535081
7940 16:30:29.535156 Set Vref, RX VrefLevel [Byte0]: 62
7941 16:30:29.538746 [Byte1]: 62
7942 16:30:29.543106
7943 16:30:29.543181 Set Vref, RX VrefLevel [Byte0]: 63
7944 16:30:29.545980 [Byte1]: 63
7945 16:30:29.550301
7946 16:30:29.550375 Set Vref, RX VrefLevel [Byte0]: 64
7947 16:30:29.553784 [Byte1]: 64
7948 16:30:29.558220
7949 16:30:29.558295 Set Vref, RX VrefLevel [Byte0]: 65
7950 16:30:29.561111 [Byte1]: 65
7951 16:30:29.565303
7952 16:30:29.565378 Set Vref, RX VrefLevel [Byte0]: 66
7953 16:30:29.568677 [Byte1]: 66
7954 16:30:29.573048
7955 16:30:29.573122 Set Vref, RX VrefLevel [Byte0]: 67
7956 16:30:29.576189 [Byte1]: 67
7957 16:30:29.580415
7958 16:30:29.580489 Set Vref, RX VrefLevel [Byte0]: 68
7959 16:30:29.583904 [Byte1]: 68
7960 16:30:29.588153
7961 16:30:29.588228 Set Vref, RX VrefLevel [Byte0]: 69
7962 16:30:29.591037 [Byte1]: 69
7963 16:30:29.595280
7964 16:30:29.595355 Set Vref, RX VrefLevel [Byte0]: 70
7965 16:30:29.598863 [Byte1]: 70
7966 16:30:29.603136
7967 16:30:29.603214 Set Vref, RX VrefLevel [Byte0]: 71
7968 16:30:29.606043 [Byte1]: 71
7969 16:30:29.610454
7970 16:30:29.610528 Set Vref, RX VrefLevel [Byte0]: 72
7971 16:30:29.614198 [Byte1]: 72
7972 16:30:29.617842
7973 16:30:29.617916 Final RX Vref Byte 0 = 56 to rank0
7974 16:30:29.621650 Final RX Vref Byte 1 = 61 to rank0
7975 16:30:29.625261 Final RX Vref Byte 0 = 56 to rank1
7976 16:30:29.628097 Final RX Vref Byte 1 = 61 to rank1==
7977 16:30:29.631758 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 16:30:29.637992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 16:30:29.638068 ==
7980 16:30:29.638126 DQS Delay:
7981 16:30:29.638179 DQS0 = 0, DQS1 = 0
7982 16:30:29.641580 DQM Delay:
7983 16:30:29.641670 DQM0 = 133, DQM1 = 127
7984 16:30:29.644549 DQ Delay:
7985 16:30:29.648212 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =132
7986 16:30:29.651931 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7987 16:30:29.654882 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7988 16:30:29.658384 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7989 16:30:29.658458
7990 16:30:29.658557
7991 16:30:29.658612
7992 16:30:29.661384 [DramC_TX_OE_Calibration] TA2
7993 16:30:29.665010 Original DQ_B0 (3 6) =30, OEN = 27
7994 16:30:29.668014 Original DQ_B1 (3 6) =30, OEN = 27
7995 16:30:29.671671 24, 0x0, End_B0=24 End_B1=24
7996 16:30:29.671751 25, 0x0, End_B0=25 End_B1=25
7997 16:30:29.674592 26, 0x0, End_B0=26 End_B1=26
7998 16:30:29.678360 27, 0x0, End_B0=27 End_B1=27
7999 16:30:29.681201 28, 0x0, End_B0=28 End_B1=28
8000 16:30:29.681277 29, 0x0, End_B0=29 End_B1=29
8001 16:30:29.684865 30, 0x0, End_B0=30 End_B1=30
8002 16:30:29.687815 31, 0x5151, End_B0=30 End_B1=30
8003 16:30:29.691187 Byte0 end_step=30 best_step=27
8004 16:30:29.694421 Byte1 end_step=30 best_step=27
8005 16:30:29.697670 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 16:30:29.697746 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 16:30:29.701045
8008 16:30:29.701120
8009 16:30:29.707545 [DQSOSCAuto] RK0, (LSB)MR18= 0x2621, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
8010 16:30:29.711214 CH0 RK0: MR19=303, MR18=2621
8011 16:30:29.717812 CH0_RK0: MR19=0x303, MR18=0x2621, DQSOSC=390, MR23=63, INC=24, DEC=16
8012 16:30:29.717888
8013 16:30:29.720797 ----->DramcWriteLeveling(PI) begin...
8014 16:30:29.720890 ==
8015 16:30:29.724391 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 16:30:29.727893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 16:30:29.727971 ==
8018 16:30:29.730738 Write leveling (Byte 0): 35 => 35
8019 16:30:29.734389 Write leveling (Byte 1): 27 => 27
8020 16:30:29.737984 DramcWriteLeveling(PI) end<-----
8021 16:30:29.738065
8022 16:30:29.738127 ==
8023 16:30:29.740752 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 16:30:29.744201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 16:30:29.744302 ==
8026 16:30:29.747841 [Gating] SW mode calibration
8027 16:30:29.753874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 16:30:29.761150 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 16:30:29.764149 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8030 16:30:29.767803 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 16:30:29.774531 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8032 16:30:29.777432 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8033 16:30:29.781165 1 4 16 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (1 1)
8034 16:30:29.787723 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8035 16:30:29.790579 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8036 16:30:29.794187 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8037 16:30:29.800592 1 5 0 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8038 16:30:29.804141 1 5 4 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
8039 16:30:29.807603 1 5 8 | B1->B0 | 3434 3838 | 1 0 | (1 0) (0 1)
8040 16:30:29.814010 1 5 12 | B1->B0 | 3434 3332 | 1 1 | (1 0) (1 0)
8041 16:30:29.817747 1 5 16 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (0 0)
8042 16:30:29.820610 1 5 20 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
8043 16:30:29.827714 1 5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8044 16:30:29.830943 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
8045 16:30:29.834261 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8046 16:30:29.840633 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8047 16:30:29.844318 1 6 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8048 16:30:29.847212 1 6 12 | B1->B0 | 2424 3635 | 0 1 | (0 0) (0 0)
8049 16:30:29.850928 1 6 16 | B1->B0 | 3f3f 4645 | 0 1 | (0 0) (1 1)
8050 16:30:29.857720 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
8051 16:30:29.860996 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 16:30:29.864226 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 16:30:29.870603 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 16:30:29.874191 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 16:30:29.877711 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 16:30:29.884286 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 16:30:29.887266 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8058 16:30:29.890869 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 16:30:29.897387 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 16:30:29.900371 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 16:30:29.904019 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 16:30:29.910752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 16:30:29.914264 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 16:30:29.917271 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 16:30:29.923831 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 16:30:29.927486 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 16:30:29.930334 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 16:30:29.937040 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 16:30:29.940711 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 16:30:29.943599 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 16:30:29.950104 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 16:30:29.953687 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8073 16:30:29.957238 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8074 16:30:29.963516 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 16:30:29.963593 Total UI for P1: 0, mck2ui 16
8076 16:30:29.970299 best dqsien dly found for B0: ( 1, 9, 14)
8077 16:30:29.970377 Total UI for P1: 0, mck2ui 16
8078 16:30:29.973463 best dqsien dly found for B1: ( 1, 9, 14)
8079 16:30:29.980270 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8080 16:30:29.983919 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8081 16:30:29.983996
8082 16:30:29.986962 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8083 16:30:29.990095 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8084 16:30:29.993698 [Gating] SW calibration Done
8085 16:30:29.993774 ==
8086 16:30:29.996659 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 16:30:29.999914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 16:30:29.999992 ==
8089 16:30:30.003746 RX Vref Scan: 0
8090 16:30:30.003823
8091 16:30:30.003883 RX Vref 0 -> 0, step: 1
8092 16:30:30.003939
8093 16:30:30.007227 RX Delay 0 -> 252, step: 8
8094 16:30:30.010196 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8095 16:30:30.017001 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8096 16:30:30.019859 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8097 16:30:30.023443 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8098 16:30:30.026938 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8099 16:30:30.029860 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8100 16:30:30.033470 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8101 16:30:30.040088 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8102 16:30:30.043734 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8103 16:30:30.046598 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8104 16:30:30.050118 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8105 16:30:30.056810 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8106 16:30:30.059793 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8107 16:30:30.063266 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8108 16:30:30.066835 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8109 16:30:30.069863 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8110 16:30:30.073597 ==
8111 16:30:30.073705 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 16:30:30.080141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 16:30:30.080255 ==
8114 16:30:30.080369 DQS Delay:
8115 16:30:30.082973 DQS0 = 0, DQS1 = 0
8116 16:30:30.083038 DQM Delay:
8117 16:30:30.086539 DQM0 = 137, DQM1 = 129
8118 16:30:30.086633 DQ Delay:
8119 16:30:30.089911 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8120 16:30:30.093447 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8121 16:30:30.096379 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8122 16:30:30.099315 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8123 16:30:30.099391
8124 16:30:30.099479
8125 16:30:30.099532 ==
8126 16:30:30.102935 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 16:30:30.109725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 16:30:30.109823 ==
8129 16:30:30.109909
8130 16:30:30.109989
8131 16:30:30.110067 TX Vref Scan disable
8132 16:30:30.113022 == TX Byte 0 ==
8133 16:30:30.116908 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8134 16:30:30.123207 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8135 16:30:30.123286 == TX Byte 1 ==
8136 16:30:30.126743 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8137 16:30:30.133278 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8138 16:30:30.133353 ==
8139 16:30:30.136319 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 16:30:30.139633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 16:30:30.139712 ==
8142 16:30:30.151755
8143 16:30:30.155423 TX Vref early break, caculate TX vref
8144 16:30:30.158358 TX Vref=16, minBit 2, minWin=23, winSum=388
8145 16:30:30.161907 TX Vref=18, minBit 0, minWin=23, winSum=394
8146 16:30:30.165654 TX Vref=20, minBit 0, minWin=24, winSum=407
8147 16:30:30.168490 TX Vref=22, minBit 7, minWin=24, winSum=414
8148 16:30:30.171975 TX Vref=24, minBit 1, minWin=25, winSum=422
8149 16:30:30.178588 TX Vref=26, minBit 3, minWin=25, winSum=432
8150 16:30:30.182299 TX Vref=28, minBit 3, minWin=24, winSum=422
8151 16:30:30.185264 TX Vref=30, minBit 1, minWin=25, winSum=415
8152 16:30:30.188848 TX Vref=32, minBit 2, minWin=24, winSum=408
8153 16:30:30.195207 [TxChooseVref] Worse bit 3, Min win 25, Win sum 432, Final Vref 26
8154 16:30:30.195287
8155 16:30:30.195347 Final TX Range 0 Vref 26
8156 16:30:30.198672
8157 16:30:30.198749 ==
8158 16:30:30.202182 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 16:30:30.205148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 16:30:30.205226 ==
8161 16:30:30.205285
8162 16:30:30.205339
8163 16:30:30.208731 TX Vref Scan disable
8164 16:30:30.212307 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8165 16:30:30.215204 == TX Byte 0 ==
8166 16:30:30.218878 u2DelayCellOfst[0]=10 cells (3 PI)
8167 16:30:30.221799 u2DelayCellOfst[1]=13 cells (4 PI)
8168 16:30:30.225519 u2DelayCellOfst[2]=10 cells (3 PI)
8169 16:30:30.228364 u2DelayCellOfst[3]=10 cells (3 PI)
8170 16:30:30.228442 u2DelayCellOfst[4]=6 cells (2 PI)
8171 16:30:30.231931 u2DelayCellOfst[5]=0 cells (0 PI)
8172 16:30:30.235422 u2DelayCellOfst[6]=13 cells (4 PI)
8173 16:30:30.238872 u2DelayCellOfst[7]=13 cells (4 PI)
8174 16:30:30.242277 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8175 16:30:30.248594 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8176 16:30:30.248674 == TX Byte 1 ==
8177 16:30:30.251978 u2DelayCellOfst[8]=0 cells (0 PI)
8178 16:30:30.255549 u2DelayCellOfst[9]=0 cells (0 PI)
8179 16:30:30.258936 u2DelayCellOfst[10]=3 cells (1 PI)
8180 16:30:30.262299 u2DelayCellOfst[11]=0 cells (0 PI)
8181 16:30:30.265506 u2DelayCellOfst[12]=10 cells (3 PI)
8182 16:30:30.268764 u2DelayCellOfst[13]=6 cells (2 PI)
8183 16:30:30.272015 u2DelayCellOfst[14]=13 cells (4 PI)
8184 16:30:30.275535 u2DelayCellOfst[15]=6 cells (2 PI)
8185 16:30:30.278840 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8186 16:30:30.281994 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8187 16:30:30.285486 DramC Write-DBI on
8188 16:30:30.285577 ==
8189 16:30:30.288478 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 16:30:30.292155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 16:30:30.292234 ==
8192 16:30:30.292294
8193 16:30:30.292350
8194 16:30:30.295089 TX Vref Scan disable
8195 16:30:30.298665 == TX Byte 0 ==
8196 16:30:30.302180 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8197 16:30:30.302259 == TX Byte 1 ==
8198 16:30:30.308386 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8199 16:30:30.308464 DramC Write-DBI off
8200 16:30:30.308524
8201 16:30:30.308579 [DATLAT]
8202 16:30:30.311842 Freq=1600, CH0 RK1
8203 16:30:30.311920
8204 16:30:30.315400 DATLAT Default: 0xf
8205 16:30:30.315476 0, 0xFFFF, sum = 0
8206 16:30:30.318307 1, 0xFFFF, sum = 0
8207 16:30:30.318384 2, 0xFFFF, sum = 0
8208 16:30:30.321925 3, 0xFFFF, sum = 0
8209 16:30:30.322001 4, 0xFFFF, sum = 0
8210 16:30:30.325543 5, 0xFFFF, sum = 0
8211 16:30:30.325619 6, 0xFFFF, sum = 0
8212 16:30:30.328418 7, 0xFFFF, sum = 0
8213 16:30:30.328481 8, 0xFFFF, sum = 0
8214 16:30:30.331995 9, 0xFFFF, sum = 0
8215 16:30:30.332073 10, 0xFFFF, sum = 0
8216 16:30:30.334897 11, 0xFFFF, sum = 0
8217 16:30:30.334975 12, 0xFFFF, sum = 0
8218 16:30:30.338610 13, 0xFFFF, sum = 0
8219 16:30:30.338689 14, 0x0, sum = 1
8220 16:30:30.341570 15, 0x0, sum = 2
8221 16:30:30.341648 16, 0x0, sum = 3
8222 16:30:30.345392 17, 0x0, sum = 4
8223 16:30:30.345457 best_step = 15
8224 16:30:30.345510
8225 16:30:30.345569 ==
8226 16:30:30.349039 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 16:30:30.355412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 16:30:30.355494 ==
8229 16:30:30.355556 RX Vref Scan: 0
8230 16:30:30.355612
8231 16:30:30.358940 RX Vref 0 -> 0, step: 1
8232 16:30:30.359017
8233 16:30:30.361904 RX Delay 19 -> 252, step: 4
8234 16:30:30.365667 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8235 16:30:30.368495 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8236 16:30:30.372202 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8237 16:30:30.378982 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8238 16:30:30.382298 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8239 16:30:30.385036 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8240 16:30:30.389024 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8241 16:30:30.391728 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8242 16:30:30.395504 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8243 16:30:30.402056 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8244 16:30:30.405028 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8245 16:30:30.408667 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8246 16:30:30.412035 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8247 16:30:30.418661 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8248 16:30:30.421662 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8249 16:30:30.425291 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8250 16:30:30.425390 ==
8251 16:30:30.428970 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 16:30:30.431761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 16:30:30.431837 ==
8254 16:30:30.435223 DQS Delay:
8255 16:30:30.435299 DQS0 = 0, DQS1 = 0
8256 16:30:30.438919 DQM Delay:
8257 16:30:30.438994 DQM0 = 134, DQM1 = 127
8258 16:30:30.439052 DQ Delay:
8259 16:30:30.441854 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8260 16:30:30.445461 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8261 16:30:30.452113 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8262 16:30:30.454910 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8263 16:30:30.454987
8264 16:30:30.455046
8265 16:30:30.455100
8266 16:30:30.458501 [DramC_TX_OE_Calibration] TA2
8267 16:30:30.461820 Original DQ_B0 (3 6) =30, OEN = 27
8268 16:30:30.465100 Original DQ_B1 (3 6) =30, OEN = 27
8269 16:30:30.465177 24, 0x0, End_B0=24 End_B1=24
8270 16:30:30.468637 25, 0x0, End_B0=25 End_B1=25
8271 16:30:30.472246 26, 0x0, End_B0=26 End_B1=26
8272 16:30:30.475251 27, 0x0, End_B0=27 End_B1=27
8273 16:30:30.475327 28, 0x0, End_B0=28 End_B1=28
8274 16:30:30.478262 29, 0x0, End_B0=29 End_B1=29
8275 16:30:30.481747 30, 0x0, End_B0=30 End_B1=30
8276 16:30:30.485360 31, 0x4545, End_B0=30 End_B1=30
8277 16:30:30.488804 Byte0 end_step=30 best_step=27
8278 16:30:30.491672 Byte1 end_step=30 best_step=27
8279 16:30:30.491748 Byte0 TX OE(2T, 0.5T) = (3, 3)
8280 16:30:30.495365 Byte1 TX OE(2T, 0.5T) = (3, 3)
8281 16:30:30.495439
8282 16:30:30.495498
8283 16:30:30.504951 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8284 16:30:30.508389 CH0 RK1: MR19=303, MR18=1F08
8285 16:30:30.511741 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8286 16:30:30.515005 [RxdqsGatingPostProcess] freq 1600
8287 16:30:30.521920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8288 16:30:30.524798 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 16:30:30.528199 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 16:30:30.531724 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 16:30:30.534746 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 16:30:30.538190 best DQS0 dly(2T, 0.5T) = (1, 1)
8293 16:30:30.538289 best DQS1 dly(2T, 0.5T) = (1, 1)
8294 16:30:30.541728 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8295 16:30:30.544782 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8296 16:30:30.548357 Pre-setting of DQS Precalculation
8297 16:30:30.555021 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8298 16:30:30.555097 ==
8299 16:30:30.557944 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 16:30:30.561667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 16:30:30.561743 ==
8302 16:30:30.568010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 16:30:30.571371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 16:30:30.574668 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 16:30:30.581467 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 16:30:30.590279 [CA 0] Center 41 (12~71) winsize 60
8307 16:30:30.593743 [CA 1] Center 41 (12~71) winsize 60
8308 16:30:30.597221 [CA 2] Center 38 (9~68) winsize 60
8309 16:30:30.600277 [CA 3] Center 37 (8~66) winsize 59
8310 16:30:30.604070 [CA 4] Center 37 (8~67) winsize 60
8311 16:30:30.606978 [CA 5] Center 36 (7~66) winsize 60
8312 16:30:30.607054
8313 16:30:30.610352 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8314 16:30:30.610428
8315 16:30:30.613967 [CATrainingPosCal] consider 1 rank data
8316 16:30:30.616822 u2DelayCellTimex100 = 285/100 ps
8317 16:30:30.620383 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8318 16:30:30.627317 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8319 16:30:30.630704 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8320 16:30:30.633795 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8321 16:30:30.636892 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8322 16:30:30.640401 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 16:30:30.640482
8324 16:30:30.643780 CA PerBit enable=1, Macro0, CA PI delay=36
8325 16:30:30.643856
8326 16:30:30.647380 [CBTSetCACLKResult] CA Dly = 36
8327 16:30:30.650073 CS Dly: 10 (0~41)
8328 16:30:30.653747 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 16:30:30.656740 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 16:30:30.656831 ==
8331 16:30:30.660473 Dram Type= 6, Freq= 0, CH_1, rank 1
8332 16:30:30.663273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 16:30:30.666979 ==
8334 16:30:30.669997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 16:30:30.673426 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 16:30:30.680044 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 16:30:30.683563 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 16:30:30.693423 [CA 0] Center 41 (12~71) winsize 60
8339 16:30:30.696947 [CA 1] Center 41 (12~71) winsize 60
8340 16:30:30.700507 [CA 2] Center 38 (9~68) winsize 60
8341 16:30:30.703217 [CA 3] Center 38 (8~68) winsize 61
8342 16:30:30.706717 [CA 4] Center 38 (8~68) winsize 61
8343 16:30:30.710315 [CA 5] Center 37 (7~67) winsize 61
8344 16:30:30.710393
8345 16:30:30.713909 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8346 16:30:30.713986
8347 16:30:30.716762 [CATrainingPosCal] consider 2 rank data
8348 16:30:30.720527 u2DelayCellTimex100 = 285/100 ps
8349 16:30:30.723461 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8350 16:30:30.730017 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8351 16:30:30.733738 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8352 16:30:30.736747 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8353 16:30:30.740355 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8354 16:30:30.743232 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8355 16:30:30.743308
8356 16:30:30.746648 CA PerBit enable=1, Macro0, CA PI delay=36
8357 16:30:30.746723
8358 16:30:30.749950 [CBTSetCACLKResult] CA Dly = 36
8359 16:30:30.753229 CS Dly: 12 (0~45)
8360 16:30:30.756866 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 16:30:30.760073 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 16:30:30.760151
8363 16:30:30.763064 ----->DramcWriteLeveling(PI) begin...
8364 16:30:30.763142 ==
8365 16:30:30.766744 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 16:30:30.769854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 16:30:30.773729 ==
8368 16:30:30.773806 Write leveling (Byte 0): 26 => 26
8369 16:30:30.776591 Write leveling (Byte 1): 29 => 29
8370 16:30:30.780193 DramcWriteLeveling(PI) end<-----
8371 16:30:30.780269
8372 16:30:30.780327 ==
8373 16:30:30.783137 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 16:30:30.790257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 16:30:30.790339 ==
8376 16:30:30.793069 [Gating] SW mode calibration
8377 16:30:30.800012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8378 16:30:30.803528 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8379 16:30:30.809847 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 16:30:30.813471 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 16:30:30.816296 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8382 16:30:30.822899 1 4 12 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
8383 16:30:30.826516 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 16:30:30.829420 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 16:30:30.836646 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 16:30:30.839682 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 16:30:30.843357 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 16:30:30.846854 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 16:30:30.853445 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
8390 16:30:30.856428 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
8391 16:30:30.859970 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 16:30:30.866620 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 16:30:30.869465 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 16:30:30.873068 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 16:30:30.879530 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 16:30:30.882714 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 16:30:30.886329 1 6 8 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (0 0)
8398 16:30:30.893068 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 16:30:30.896123 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 16:30:30.899796 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 16:30:30.906444 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 16:30:30.909664 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 16:30:30.913056 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 16:30:30.919974 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 16:30:30.922693 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 16:30:30.926376 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8407 16:30:30.932955 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 16:30:30.935837 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 16:30:30.939477 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 16:30:30.945961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 16:30:30.949557 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 16:30:30.952464 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 16:30:30.959163 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 16:30:30.962777 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 16:30:30.966358 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 16:30:30.972277 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 16:30:30.975922 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 16:30:30.979474 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 16:30:30.986199 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 16:30:30.989091 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 16:30:30.992605 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 16:30:30.995537 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8423 16:30:31.002457 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 16:30:31.005883 Total UI for P1: 0, mck2ui 16
8425 16:30:31.009263 best dqsien dly found for B0: ( 1, 9, 10)
8426 16:30:31.012495 Total UI for P1: 0, mck2ui 16
8427 16:30:31.015502 best dqsien dly found for B1: ( 1, 9, 10)
8428 16:30:31.019313 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8429 16:30:31.022629 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8430 16:30:31.022710
8431 16:30:31.025792 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 16:30:31.028871 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8433 16:30:31.032453 [Gating] SW calibration Done
8434 16:30:31.032550 ==
8435 16:30:31.035914 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 16:30:31.038908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 16:30:31.039023 ==
8438 16:30:31.042539 RX Vref Scan: 0
8439 16:30:31.042608
8440 16:30:31.045467 RX Vref 0 -> 0, step: 1
8441 16:30:31.045594
8442 16:30:31.045653 RX Delay 0 -> 252, step: 8
8443 16:30:31.052628 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8444 16:30:31.055542 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8445 16:30:31.059237 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8446 16:30:31.062167 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8447 16:30:31.065893 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8448 16:30:31.068928 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8449 16:30:31.075392 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8450 16:30:31.079261 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8451 16:30:31.082271 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8452 16:30:31.085918 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8453 16:30:31.088900 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8454 16:30:31.095682 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8455 16:30:31.099288 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8456 16:30:31.102237 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8457 16:30:31.105182 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8458 16:30:31.108825 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8459 16:30:31.112295 ==
8460 16:30:31.115217 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 16:30:31.118866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 16:30:31.118970 ==
8463 16:30:31.119084 DQS Delay:
8464 16:30:31.122382 DQS0 = 0, DQS1 = 0
8465 16:30:31.122486 DQM Delay:
8466 16:30:31.125138 DQM0 = 136, DQM1 = 132
8467 16:30:31.125245 DQ Delay:
8468 16:30:31.128750 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8469 16:30:31.132397 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8470 16:30:31.135461 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8471 16:30:31.138982 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8472 16:30:31.139052
8473 16:30:31.139123
8474 16:30:31.139189 ==
8475 16:30:31.141819 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 16:30:31.148597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 16:30:31.148700 ==
8478 16:30:31.148783
8479 16:30:31.148862
8480 16:30:31.151825 TX Vref Scan disable
8481 16:30:31.151922 == TX Byte 0 ==
8482 16:30:31.155193 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8483 16:30:31.161820 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 16:30:31.161902 == TX Byte 1 ==
8485 16:30:31.165041 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8486 16:30:31.171594 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8487 16:30:31.171674 ==
8488 16:30:31.174791 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 16:30:31.178173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 16:30:31.178245 ==
8491 16:30:31.191372
8492 16:30:31.194357 TX Vref early break, caculate TX vref
8493 16:30:31.198062 TX Vref=16, minBit 0, minWin=22, winSum=374
8494 16:30:31.201053 TX Vref=18, minBit 0, minWin=23, winSum=383
8495 16:30:31.204520 TX Vref=20, minBit 0, minWin=24, winSum=397
8496 16:30:31.208074 TX Vref=22, minBit 1, minWin=24, winSum=405
8497 16:30:31.211040 TX Vref=24, minBit 1, minWin=25, winSum=414
8498 16:30:31.217654 TX Vref=26, minBit 0, minWin=25, winSum=422
8499 16:30:31.221429 TX Vref=28, minBit 0, minWin=25, winSum=428
8500 16:30:31.224371 TX Vref=30, minBit 0, minWin=25, winSum=418
8501 16:30:31.228020 TX Vref=32, minBit 0, minWin=25, winSum=411
8502 16:30:31.231304 TX Vref=34, minBit 0, minWin=24, winSum=400
8503 16:30:31.237711 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8504 16:30:31.237793
8505 16:30:31.240713 Final TX Range 0 Vref 28
8506 16:30:31.240796
8507 16:30:31.240857 ==
8508 16:30:31.244471 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 16:30:31.247372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 16:30:31.247453 ==
8511 16:30:31.247513
8512 16:30:31.247569
8513 16:30:31.251042 TX Vref Scan disable
8514 16:30:31.257430 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8515 16:30:31.257510 == TX Byte 0 ==
8516 16:30:31.260864 u2DelayCellOfst[0]=17 cells (5 PI)
8517 16:30:31.264530 u2DelayCellOfst[1]=13 cells (4 PI)
8518 16:30:31.267473 u2DelayCellOfst[2]=0 cells (0 PI)
8519 16:30:31.271186 u2DelayCellOfst[3]=10 cells (3 PI)
8520 16:30:31.274163 u2DelayCellOfst[4]=10 cells (3 PI)
8521 16:30:31.277600 u2DelayCellOfst[5]=20 cells (6 PI)
8522 16:30:31.280810 u2DelayCellOfst[6]=20 cells (6 PI)
8523 16:30:31.280886 u2DelayCellOfst[7]=6 cells (2 PI)
8524 16:30:31.287349 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8525 16:30:31.291195 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8526 16:30:31.291272 == TX Byte 1 ==
8527 16:30:31.294118 u2DelayCellOfst[8]=0 cells (0 PI)
8528 16:30:31.297605 u2DelayCellOfst[9]=6 cells (2 PI)
8529 16:30:31.300776 u2DelayCellOfst[10]=13 cells (4 PI)
8530 16:30:31.304352 u2DelayCellOfst[11]=6 cells (2 PI)
8531 16:30:31.307673 u2DelayCellOfst[12]=17 cells (5 PI)
8532 16:30:31.311181 u2DelayCellOfst[13]=17 cells (5 PI)
8533 16:30:31.314111 u2DelayCellOfst[14]=17 cells (5 PI)
8534 16:30:31.317515 u2DelayCellOfst[15]=17 cells (5 PI)
8535 16:30:31.321198 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8536 16:30:31.324336 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8537 16:30:31.327990 DramC Write-DBI on
8538 16:30:31.328067 ==
8539 16:30:31.330881 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 16:30:31.334638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 16:30:31.334763 ==
8542 16:30:31.334824
8543 16:30:31.337370
8544 16:30:31.337485 TX Vref Scan disable
8545 16:30:31.340894 == TX Byte 0 ==
8546 16:30:31.344318 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8547 16:30:31.347907 == TX Byte 1 ==
8548 16:30:31.350930 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8549 16:30:31.351009 DramC Write-DBI off
8550 16:30:31.351084
8551 16:30:31.354470 [DATLAT]
8552 16:30:31.354546 Freq=1600, CH1 RK0
8553 16:30:31.354606
8554 16:30:31.357459 DATLAT Default: 0xf
8555 16:30:31.357579 0, 0xFFFF, sum = 0
8556 16:30:31.361007 1, 0xFFFF, sum = 0
8557 16:30:31.361085 2, 0xFFFF, sum = 0
8558 16:30:31.364488 3, 0xFFFF, sum = 0
8559 16:30:31.364566 4, 0xFFFF, sum = 0
8560 16:30:31.367904 5, 0xFFFF, sum = 0
8561 16:30:31.368012 6, 0xFFFF, sum = 0
8562 16:30:31.370817 7, 0xFFFF, sum = 0
8563 16:30:31.370911 8, 0xFFFF, sum = 0
8564 16:30:31.374528 9, 0xFFFF, sum = 0
8565 16:30:31.378084 10, 0xFFFF, sum = 0
8566 16:30:31.378162 11, 0xFFFF, sum = 0
8567 16:30:31.380933 12, 0xFFFF, sum = 0
8568 16:30:31.381011 13, 0xFFFF, sum = 0
8569 16:30:31.383914 14, 0x0, sum = 1
8570 16:30:31.384026 15, 0x0, sum = 2
8571 16:30:31.387453 16, 0x0, sum = 3
8572 16:30:31.387561 17, 0x0, sum = 4
8573 16:30:31.387622 best_step = 15
8574 16:30:31.390509
8575 16:30:31.390584 ==
8576 16:30:31.394209 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 16:30:31.397132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 16:30:31.397223 ==
8579 16:30:31.397283 RX Vref Scan: 1
8580 16:30:31.397338
8581 16:30:31.400764 Set Vref Range= 24 -> 127
8582 16:30:31.400840
8583 16:30:31.404289 RX Vref 24 -> 127, step: 1
8584 16:30:31.404367
8585 16:30:31.407570 RX Delay 27 -> 252, step: 4
8586 16:30:31.407676
8587 16:30:31.410884 Set Vref, RX VrefLevel [Byte0]: 24
8588 16:30:31.414064 [Byte1]: 24
8589 16:30:31.414132
8590 16:30:31.417288 Set Vref, RX VrefLevel [Byte0]: 25
8591 16:30:31.420446 [Byte1]: 25
8592 16:30:31.420515
8593 16:30:31.424127 Set Vref, RX VrefLevel [Byte0]: 26
8594 16:30:31.427278 [Byte1]: 26
8595 16:30:31.430425
8596 16:30:31.430520 Set Vref, RX VrefLevel [Byte0]: 27
8597 16:30:31.433773 [Byte1]: 27
8598 16:30:31.437975
8599 16:30:31.438070 Set Vref, RX VrefLevel [Byte0]: 28
8600 16:30:31.441311 [Byte1]: 28
8601 16:30:31.445453
8602 16:30:31.445569 Set Vref, RX VrefLevel [Byte0]: 29
8603 16:30:31.449046 [Byte1]: 29
8604 16:30:31.453386
8605 16:30:31.453479 Set Vref, RX VrefLevel [Byte0]: 30
8606 16:30:31.456902 [Byte1]: 30
8607 16:30:31.460539
8608 16:30:31.460607 Set Vref, RX VrefLevel [Byte0]: 31
8609 16:30:31.464209 [Byte1]: 31
8610 16:30:31.468733
8611 16:30:31.468813 Set Vref, RX VrefLevel [Byte0]: 32
8612 16:30:31.471561 [Byte1]: 32
8613 16:30:31.475797
8614 16:30:31.475875 Set Vref, RX VrefLevel [Byte0]: 33
8615 16:30:31.479478 [Byte1]: 33
8616 16:30:31.483770
8617 16:30:31.483848 Set Vref, RX VrefLevel [Byte0]: 34
8618 16:30:31.486680 [Byte1]: 34
8619 16:30:31.491122
8620 16:30:31.491201 Set Vref, RX VrefLevel [Byte0]: 35
8621 16:30:31.494117 [Byte1]: 35
8622 16:30:31.498407
8623 16:30:31.498491 Set Vref, RX VrefLevel [Byte0]: 36
8624 16:30:31.502006 [Byte1]: 36
8625 16:30:31.506418
8626 16:30:31.506490 Set Vref, RX VrefLevel [Byte0]: 37
8627 16:30:31.509363 [Byte1]: 37
8628 16:30:31.513746
8629 16:30:31.513818 Set Vref, RX VrefLevel [Byte0]: 38
8630 16:30:31.516780 [Byte1]: 38
8631 16:30:31.521121
8632 16:30:31.521192 Set Vref, RX VrefLevel [Byte0]: 39
8633 16:30:31.524607 [Byte1]: 39
8634 16:30:31.528939
8635 16:30:31.529023 Set Vref, RX VrefLevel [Byte0]: 40
8636 16:30:31.531877 [Byte1]: 40
8637 16:30:31.536019
8638 16:30:31.536094 Set Vref, RX VrefLevel [Byte0]: 41
8639 16:30:31.539633 [Byte1]: 41
8640 16:30:31.544003
8641 16:30:31.544083 Set Vref, RX VrefLevel [Byte0]: 42
8642 16:30:31.547245 [Byte1]: 42
8643 16:30:31.551231
8644 16:30:31.551313 Set Vref, RX VrefLevel [Byte0]: 43
8645 16:30:31.554477 [Byte1]: 43
8646 16:30:31.558571
8647 16:30:31.558650 Set Vref, RX VrefLevel [Byte0]: 44
8648 16:30:31.561954 [Byte1]: 44
8649 16:30:31.566321
8650 16:30:31.566399 Set Vref, RX VrefLevel [Byte0]: 45
8651 16:30:31.569308 [Byte1]: 45
8652 16:30:31.573897
8653 16:30:31.573976 Set Vref, RX VrefLevel [Byte0]: 46
8654 16:30:31.577026 [Byte1]: 46
8655 16:30:31.581472
8656 16:30:31.581562 Set Vref, RX VrefLevel [Byte0]: 47
8657 16:30:31.584727 [Byte1]: 47
8658 16:30:31.588742
8659 16:30:31.588822 Set Vref, RX VrefLevel [Byte0]: 48
8660 16:30:31.592386 [Byte1]: 48
8661 16:30:31.596691
8662 16:30:31.596763 Set Vref, RX VrefLevel [Byte0]: 49
8663 16:30:31.599619 [Byte1]: 49
8664 16:30:31.603738
8665 16:30:31.603817 Set Vref, RX VrefLevel [Byte0]: 50
8666 16:30:31.607425 [Byte1]: 50
8667 16:30:31.611790
8668 16:30:31.611869 Set Vref, RX VrefLevel [Byte0]: 51
8669 16:30:31.614798 [Byte1]: 51
8670 16:30:31.619123
8671 16:30:31.619196 Set Vref, RX VrefLevel [Byte0]: 52
8672 16:30:31.622018 [Byte1]: 52
8673 16:30:31.626470
8674 16:30:31.626575 Set Vref, RX VrefLevel [Byte0]: 53
8675 16:30:31.629938 [Byte1]: 53
8676 16:30:31.634253
8677 16:30:31.634375 Set Vref, RX VrefLevel [Byte0]: 54
8678 16:30:31.637088 [Byte1]: 54
8679 16:30:31.642025
8680 16:30:31.642131 Set Vref, RX VrefLevel [Byte0]: 55
8681 16:30:31.644731 [Byte1]: 55
8682 16:30:31.649057
8683 16:30:31.649180 Set Vref, RX VrefLevel [Byte0]: 56
8684 16:30:31.652606 [Byte1]: 56
8685 16:30:31.656862
8686 16:30:31.656963 Set Vref, RX VrefLevel [Byte0]: 57
8687 16:30:31.659707 [Byte1]: 57
8688 16:30:31.664416
8689 16:30:31.664531 Set Vref, RX VrefLevel [Byte0]: 58
8690 16:30:31.667417 [Byte1]: 58
8691 16:30:31.671839
8692 16:30:31.671974 Set Vref, RX VrefLevel [Byte0]: 59
8693 16:30:31.675283 [Byte1]: 59
8694 16:30:31.679511
8695 16:30:31.679654 Set Vref, RX VrefLevel [Byte0]: 60
8696 16:30:31.682322 [Byte1]: 60
8697 16:30:31.687196
8698 16:30:31.687346 Set Vref, RX VrefLevel [Byte0]: 61
8699 16:30:31.689957 [Byte1]: 61
8700 16:30:31.694214
8701 16:30:31.694334 Set Vref, RX VrefLevel [Byte0]: 62
8702 16:30:31.697479 [Byte1]: 62
8703 16:30:31.702192
8704 16:30:31.702274 Set Vref, RX VrefLevel [Byte0]: 63
8705 16:30:31.705346 [Byte1]: 63
8706 16:30:31.709349
8707 16:30:31.709421 Set Vref, RX VrefLevel [Byte0]: 64
8708 16:30:31.713012 [Byte1]: 64
8709 16:30:31.716761
8710 16:30:31.716834 Set Vref, RX VrefLevel [Byte0]: 65
8711 16:30:31.720308 [Byte1]: 65
8712 16:30:31.724742
8713 16:30:31.724821 Set Vref, RX VrefLevel [Byte0]: 66
8714 16:30:31.727713 [Byte1]: 66
8715 16:30:31.732124
8716 16:30:31.732196 Set Vref, RX VrefLevel [Byte0]: 67
8717 16:30:31.735608 [Byte1]: 67
8718 16:30:31.739949
8719 16:30:31.740055 Set Vref, RX VrefLevel [Byte0]: 68
8720 16:30:31.742943 [Byte1]: 68
8721 16:30:31.747412
8722 16:30:31.747501 Set Vref, RX VrefLevel [Byte0]: 69
8723 16:30:31.750276 [Byte1]: 69
8724 16:30:31.754321
8725 16:30:31.754436 Set Vref, RX VrefLevel [Byte0]: 70
8726 16:30:31.757868 [Byte1]: 70
8727 16:30:31.762316
8728 16:30:31.762429 Set Vref, RX VrefLevel [Byte0]: 71
8729 16:30:31.765278 [Byte1]: 71
8730 16:30:31.769398
8731 16:30:31.769484 Set Vref, RX VrefLevel [Byte0]: 72
8732 16:30:31.773272 [Byte1]: 72
8733 16:30:31.777048
8734 16:30:31.777158 Set Vref, RX VrefLevel [Byte0]: 73
8735 16:30:31.780740 [Byte1]: 73
8736 16:30:31.785068
8737 16:30:31.785154 Set Vref, RX VrefLevel [Byte0]: 74
8738 16:30:31.787926 [Byte1]: 74
8739 16:30:31.792253
8740 16:30:31.792337 Final RX Vref Byte 0 = 57 to rank0
8741 16:30:31.795775 Final RX Vref Byte 1 = 58 to rank0
8742 16:30:31.799402 Final RX Vref Byte 0 = 57 to rank1
8743 16:30:31.802261 Final RX Vref Byte 1 = 58 to rank1==
8744 16:30:31.805787 Dram Type= 6, Freq= 0, CH_1, rank 0
8745 16:30:31.812448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 16:30:31.812541 ==
8747 16:30:31.812622 DQS Delay:
8748 16:30:31.812719 DQS0 = 0, DQS1 = 0
8749 16:30:31.815960 DQM Delay:
8750 16:30:31.816059 DQM0 = 134, DQM1 = 131
8751 16:30:31.819039 DQ Delay:
8752 16:30:31.822084 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8753 16:30:31.825568 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8754 16:30:31.829047 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =124
8755 16:30:31.832234 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8756 16:30:31.832319
8757 16:30:31.832377
8758 16:30:31.832431
8759 16:30:31.835546 [DramC_TX_OE_Calibration] TA2
8760 16:30:31.838923 Original DQ_B0 (3 6) =30, OEN = 27
8761 16:30:31.841975 Original DQ_B1 (3 6) =30, OEN = 27
8762 16:30:31.845610 24, 0x0, End_B0=24 End_B1=24
8763 16:30:31.845730 25, 0x0, End_B0=25 End_B1=25
8764 16:30:31.848516 26, 0x0, End_B0=26 End_B1=26
8765 16:30:31.852177 27, 0x0, End_B0=27 End_B1=27
8766 16:30:31.855818 28, 0x0, End_B0=28 End_B1=28
8767 16:30:31.855914 29, 0x0, End_B0=29 End_B1=29
8768 16:30:31.858664 30, 0x0, End_B0=30 End_B1=30
8769 16:30:31.862332 31, 0x5151, End_B0=30 End_B1=30
8770 16:30:31.865739 Byte0 end_step=30 best_step=27
8771 16:30:31.868700 Byte1 end_step=30 best_step=27
8772 16:30:31.872176 Byte0 TX OE(2T, 0.5T) = (3, 3)
8773 16:30:31.872266 Byte1 TX OE(2T, 0.5T) = (3, 3)
8774 16:30:31.875166
8775 16:30:31.875280
8776 16:30:31.882067 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8777 16:30:31.885130 CH1 RK0: MR19=303, MR18=1927
8778 16:30:31.892135 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8779 16:30:31.892261
8780 16:30:31.895179 ----->DramcWriteLeveling(PI) begin...
8781 16:30:31.895265 ==
8782 16:30:31.898934 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 16:30:31.901872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 16:30:31.901946 ==
8785 16:30:31.905591 Write leveling (Byte 0): 26 => 26
8786 16:30:31.908578 Write leveling (Byte 1): 28 => 28
8787 16:30:31.912292 DramcWriteLeveling(PI) end<-----
8788 16:30:31.912368
8789 16:30:31.912431 ==
8790 16:30:31.915286 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 16:30:31.918910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 16:30:31.918984 ==
8793 16:30:31.921953 [Gating] SW mode calibration
8794 16:30:31.928587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8795 16:30:31.935083 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8796 16:30:31.938343 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 16:30:31.941696 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 16:30:31.948086 1 4 8 | B1->B0 | 3232 2323 | 1 1 | (1 1) (1 1)
8799 16:30:31.951549 1 4 12 | B1->B0 | 3434 2d2c | 1 1 | (1 1) (0 0)
8800 16:30:31.954818 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 16:30:31.961758 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 16:30:31.964715 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 16:30:31.968305 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 16:30:31.975118 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 16:30:31.978348 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8806 16:30:31.981667 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8807 16:30:31.988030 1 5 12 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (1 0)
8808 16:30:31.991650 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 16:30:31.995142 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 16:30:32.001685 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 16:30:32.004702 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 16:30:32.008246 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 16:30:32.014853 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 16:30:32.018377 1 6 8 | B1->B0 | 4040 2525 | 0 0 | (0 0) (0 0)
8815 16:30:32.021231 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8816 16:30:32.027789 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 16:30:32.031383 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 16:30:32.035187 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 16:30:32.041734 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 16:30:32.044565 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 16:30:32.048085 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 16:30:32.051684 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8823 16:30:32.058214 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8824 16:30:32.061838 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 16:30:32.064627 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 16:30:32.071415 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 16:30:32.074991 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 16:30:32.077827 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 16:30:32.084315 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 16:30:32.088258 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 16:30:32.091230 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 16:30:32.098071 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 16:30:32.101054 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 16:30:32.104674 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 16:30:32.111412 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 16:30:32.114554 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 16:30:32.117779 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8838 16:30:32.124845 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8839 16:30:32.127778 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8840 16:30:32.131395 Total UI for P1: 0, mck2ui 16
8841 16:30:32.135042 best dqsien dly found for B1: ( 1, 9, 6)
8842 16:30:32.137916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 16:30:32.141012 Total UI for P1: 0, mck2ui 16
8844 16:30:32.144670 best dqsien dly found for B0: ( 1, 9, 12)
8845 16:30:32.147563 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8846 16:30:32.151196 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8847 16:30:32.151283
8848 16:30:32.154836 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8849 16:30:32.161294 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8850 16:30:32.161386 [Gating] SW calibration Done
8851 16:30:32.161482 ==
8852 16:30:32.164850 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 16:30:32.171108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 16:30:32.171201 ==
8855 16:30:32.171265 RX Vref Scan: 0
8856 16:30:32.171321
8857 16:30:32.174627 RX Vref 0 -> 0, step: 1
8858 16:30:32.174725
8859 16:30:32.178091 RX Delay 0 -> 252, step: 8
8860 16:30:32.181000 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8861 16:30:32.184806 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8862 16:30:32.187791 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8863 16:30:32.191504 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8864 16:30:32.198162 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8865 16:30:32.201113 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8866 16:30:32.204644 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8867 16:30:32.207445 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8868 16:30:32.210907 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8869 16:30:32.217850 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8870 16:30:32.221098 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8871 16:30:32.224287 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8872 16:30:32.227511 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8873 16:30:32.234233 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8874 16:30:32.237614 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8875 16:30:32.240915 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8876 16:30:32.241019 ==
8877 16:30:32.244095 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 16:30:32.247319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 16:30:32.247421 ==
8880 16:30:32.250883 DQS Delay:
8881 16:30:32.250987 DQS0 = 0, DQS1 = 0
8882 16:30:32.254390 DQM Delay:
8883 16:30:32.254471 DQM0 = 136, DQM1 = 134
8884 16:30:32.254554 DQ Delay:
8885 16:30:32.257266 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8886 16:30:32.260938 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8887 16:30:32.267481 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =131
8888 16:30:32.271189 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8889 16:30:32.271274
8890 16:30:32.271352
8891 16:30:32.271423 ==
8892 16:30:32.274092 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 16:30:32.277815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 16:30:32.277934 ==
8895 16:30:32.278062
8896 16:30:32.278176
8897 16:30:32.280644 TX Vref Scan disable
8898 16:30:32.284316 == TX Byte 0 ==
8899 16:30:32.287916 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8900 16:30:32.290858 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8901 16:30:32.294551 == TX Byte 1 ==
8902 16:30:32.297453 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8903 16:30:32.300996 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8904 16:30:32.301108 ==
8905 16:30:32.303957 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 16:30:32.307705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 16:30:32.307871 ==
8908 16:30:32.322406
8909 16:30:32.326186 TX Vref early break, caculate TX vref
8910 16:30:32.328994 TX Vref=16, minBit 0, minWin=23, winSum=382
8911 16:30:32.332661 TX Vref=18, minBit 0, minWin=23, winSum=392
8912 16:30:32.335566 TX Vref=20, minBit 0, minWin=24, winSum=400
8913 16:30:32.339217 TX Vref=22, minBit 0, minWin=25, winSum=410
8914 16:30:32.342853 TX Vref=24, minBit 0, minWin=24, winSum=417
8915 16:30:32.349000 TX Vref=26, minBit 0, minWin=25, winSum=425
8916 16:30:32.352504 TX Vref=28, minBit 0, minWin=24, winSum=425
8917 16:30:32.355876 TX Vref=30, minBit 0, minWin=26, winSum=421
8918 16:30:32.359187 TX Vref=32, minBit 4, minWin=25, winSum=415
8919 16:30:32.362823 TX Vref=34, minBit 0, minWin=24, winSum=408
8920 16:30:32.365666 TX Vref=36, minBit 0, minWin=24, winSum=398
8921 16:30:32.372300 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
8922 16:30:32.372411
8923 16:30:32.375486 Final TX Range 0 Vref 30
8924 16:30:32.375562
8925 16:30:32.375648 ==
8926 16:30:32.378879 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 16:30:32.382127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 16:30:32.382212 ==
8929 16:30:32.382273
8930 16:30:32.382328
8931 16:30:32.385784 TX Vref Scan disable
8932 16:30:32.392397 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8933 16:30:32.392476 == TX Byte 0 ==
8934 16:30:32.396152 u2DelayCellOfst[0]=17 cells (5 PI)
8935 16:30:32.398976 u2DelayCellOfst[1]=13 cells (4 PI)
8936 16:30:32.402731 u2DelayCellOfst[2]=0 cells (0 PI)
8937 16:30:32.405610 u2DelayCellOfst[3]=6 cells (2 PI)
8938 16:30:32.409313 u2DelayCellOfst[4]=10 cells (3 PI)
8939 16:30:32.412283 u2DelayCellOfst[5]=17 cells (5 PI)
8940 16:30:32.416050 u2DelayCellOfst[6]=20 cells (6 PI)
8941 16:30:32.419045 u2DelayCellOfst[7]=6 cells (2 PI)
8942 16:30:32.422640 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8943 16:30:32.425674 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8944 16:30:32.428746 == TX Byte 1 ==
8945 16:30:32.428826 u2DelayCellOfst[8]=0 cells (0 PI)
8946 16:30:32.432277 u2DelayCellOfst[9]=3 cells (1 PI)
8947 16:30:32.435980 u2DelayCellOfst[10]=10 cells (3 PI)
8948 16:30:32.438938 u2DelayCellOfst[11]=3 cells (1 PI)
8949 16:30:32.442572 u2DelayCellOfst[12]=13 cells (4 PI)
8950 16:30:32.445441 u2DelayCellOfst[13]=13 cells (4 PI)
8951 16:30:32.449210 u2DelayCellOfst[14]=13 cells (4 PI)
8952 16:30:32.452033 u2DelayCellOfst[15]=17 cells (5 PI)
8953 16:30:32.455731 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8954 16:30:32.461803 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8955 16:30:32.461925 DramC Write-DBI on
8956 16:30:32.462013 ==
8957 16:30:32.465456 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 16:30:32.471934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 16:30:32.472067 ==
8960 16:30:32.472133
8961 16:30:32.472189
8962 16:30:32.472249 TX Vref Scan disable
8963 16:30:32.476165 == TX Byte 0 ==
8964 16:30:32.478737 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8965 16:30:32.482130 == TX Byte 1 ==
8966 16:30:32.485377 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8967 16:30:32.488918 DramC Write-DBI off
8968 16:30:32.489060
8969 16:30:32.489153 [DATLAT]
8970 16:30:32.489260 Freq=1600, CH1 RK1
8971 16:30:32.489346
8972 16:30:32.492597 DATLAT Default: 0xf
8973 16:30:32.492720 0, 0xFFFF, sum = 0
8974 16:30:32.495828 1, 0xFFFF, sum = 0
8975 16:30:32.499315 2, 0xFFFF, sum = 0
8976 16:30:32.499431 3, 0xFFFF, sum = 0
8977 16:30:32.502277 4, 0xFFFF, sum = 0
8978 16:30:32.502382 5, 0xFFFF, sum = 0
8979 16:30:32.505383 6, 0xFFFF, sum = 0
8980 16:30:32.505480 7, 0xFFFF, sum = 0
8981 16:30:32.508662 8, 0xFFFF, sum = 0
8982 16:30:32.508735 9, 0xFFFF, sum = 0
8983 16:30:32.512479 10, 0xFFFF, sum = 0
8984 16:30:32.512576 11, 0xFFFF, sum = 0
8985 16:30:32.515752 12, 0xFFFF, sum = 0
8986 16:30:32.515848 13, 0xFFFF, sum = 0
8987 16:30:32.518867 14, 0x0, sum = 1
8988 16:30:32.518960 15, 0x0, sum = 2
8989 16:30:32.522337 16, 0x0, sum = 3
8990 16:30:32.522414 17, 0x0, sum = 4
8991 16:30:32.525274 best_step = 15
8992 16:30:32.525373
8993 16:30:32.525458 ==
8994 16:30:32.529022 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 16:30:32.531878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 16:30:32.531960 ==
8997 16:30:32.535558 RX Vref Scan: 0
8998 16:30:32.535634
8999 16:30:32.535693 RX Vref 0 -> 0, step: 1
9000 16:30:32.535748
9001 16:30:32.538335 RX Delay 19 -> 252, step: 4
9002 16:30:32.542047 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9003 16:30:32.548688 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9004 16:30:32.551742 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9005 16:30:32.555232 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9006 16:30:32.558967 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9007 16:30:32.562287 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9008 16:30:32.568418 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9009 16:30:32.572130 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9010 16:30:32.575007 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9011 16:30:32.578643 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9012 16:30:32.581505 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9013 16:30:32.588076 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9014 16:30:32.591817 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
9015 16:30:32.594906 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9016 16:30:32.598524 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9017 16:30:32.601531 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9018 16:30:32.604851 ==
9019 16:30:32.604956 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 16:30:32.611925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 16:30:32.612027 ==
9022 16:30:32.612117 DQS Delay:
9023 16:30:32.614810 DQS0 = 0, DQS1 = 0
9024 16:30:32.614907 DQM Delay:
9025 16:30:32.618276 DQM0 = 134, DQM1 = 131
9026 16:30:32.618378 DQ Delay:
9027 16:30:32.621739 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9028 16:30:32.625089 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9029 16:30:32.628634 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9030 16:30:32.631755 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9031 16:30:32.631854
9032 16:30:32.631941
9033 16:30:32.632025
9034 16:30:32.634979 [DramC_TX_OE_Calibration] TA2
9035 16:30:32.638289 Original DQ_B0 (3 6) =30, OEN = 27
9036 16:30:32.641683 Original DQ_B1 (3 6) =30, OEN = 27
9037 16:30:32.644989 24, 0x0, End_B0=24 End_B1=24
9038 16:30:32.647708 25, 0x0, End_B0=25 End_B1=25
9039 16:30:32.647792 26, 0x0, End_B0=26 End_B1=26
9040 16:30:32.651084 27, 0x0, End_B0=27 End_B1=27
9041 16:30:32.654752 28, 0x0, End_B0=28 End_B1=28
9042 16:30:32.657666 29, 0x0, End_B0=29 End_B1=29
9043 16:30:32.661198 30, 0x0, End_B0=30 End_B1=30
9044 16:30:32.661301 31, 0x4141, End_B0=30 End_B1=30
9045 16:30:32.665068 Byte0 end_step=30 best_step=27
9046 16:30:32.667875 Byte1 end_step=30 best_step=27
9047 16:30:32.671650 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 16:30:32.674556 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 16:30:32.674687
9050 16:30:32.674776
9051 16:30:32.681283 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9052 16:30:32.684950 CH1 RK1: MR19=303, MR18=2308
9053 16:30:32.691668 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9054 16:30:32.694675 [RxdqsGatingPostProcess] freq 1600
9055 16:30:32.701291 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 16:30:32.701404 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 16:30:32.704289 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 16:30:32.708084 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 16:30:32.710880 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 16:30:32.714436 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 16:30:32.718000 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 16:30:32.721409 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 16:30:32.724330 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 16:30:32.727838 Pre-setting of DQS Precalculation
9065 16:30:32.730794 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 16:30:32.740841 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 16:30:32.747364 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 16:30:32.747471
9069 16:30:32.747568
9070 16:30:32.750865 [Calibration Summary] 3200 Mbps
9071 16:30:32.750967 CH 0, Rank 0
9072 16:30:32.754282 SW Impedance : PASS
9073 16:30:32.754378 DUTY Scan : NO K
9074 16:30:32.757600 ZQ Calibration : PASS
9075 16:30:32.760842 Jitter Meter : NO K
9076 16:30:32.760946 CBT Training : PASS
9077 16:30:32.764185 Write leveling : PASS
9078 16:30:32.767816 RX DQS gating : PASS
9079 16:30:32.767928 RX DQ/DQS(RDDQC) : PASS
9080 16:30:32.770548 TX DQ/DQS : PASS
9081 16:30:32.770642 RX DATLAT : PASS
9082 16:30:32.774050 RX DQ/DQS(Engine): PASS
9083 16:30:32.777416 TX OE : PASS
9084 16:30:32.777519 All Pass.
9085 16:30:32.777607
9086 16:30:32.777685 CH 0, Rank 1
9087 16:30:32.781175 SW Impedance : PASS
9088 16:30:32.784198 DUTY Scan : NO K
9089 16:30:32.784298 ZQ Calibration : PASS
9090 16:30:32.787733 Jitter Meter : NO K
9091 16:30:32.790793 CBT Training : PASS
9092 16:30:32.790901 Write leveling : PASS
9093 16:30:32.794297 RX DQS gating : PASS
9094 16:30:32.797186 RX DQ/DQS(RDDQC) : PASS
9095 16:30:32.797292 TX DQ/DQS : PASS
9096 16:30:32.800792 RX DATLAT : PASS
9097 16:30:32.803706 RX DQ/DQS(Engine): PASS
9098 16:30:32.803814 TX OE : PASS
9099 16:30:32.807391 All Pass.
9100 16:30:32.807489
9101 16:30:32.807586 CH 1, Rank 0
9102 16:30:32.810384 SW Impedance : PASS
9103 16:30:32.810485 DUTY Scan : NO K
9104 16:30:32.814252 ZQ Calibration : PASS
9105 16:30:32.817116 Jitter Meter : NO K
9106 16:30:32.817221 CBT Training : PASS
9107 16:30:32.820795 Write leveling : PASS
9108 16:30:32.823714 RX DQS gating : PASS
9109 16:30:32.823823 RX DQ/DQS(RDDQC) : PASS
9110 16:30:32.827242 TX DQ/DQS : PASS
9111 16:30:32.827344 RX DATLAT : PASS
9112 16:30:32.830165 RX DQ/DQS(Engine): PASS
9113 16:30:32.833498 TX OE : PASS
9114 16:30:32.833595 All Pass.
9115 16:30:32.833661
9116 16:30:32.837033 CH 1, Rank 1
9117 16:30:32.837131 SW Impedance : PASS
9118 16:30:32.840468 DUTY Scan : NO K
9119 16:30:32.840569 ZQ Calibration : PASS
9120 16:30:32.843882 Jitter Meter : NO K
9121 16:30:32.847359 CBT Training : PASS
9122 16:30:32.847472 Write leveling : PASS
9123 16:30:32.850542 RX DQS gating : PASS
9124 16:30:32.853502 RX DQ/DQS(RDDQC) : PASS
9125 16:30:32.853614 TX DQ/DQS : PASS
9126 16:30:32.857180 RX DATLAT : PASS
9127 16:30:32.860064 RX DQ/DQS(Engine): PASS
9128 16:30:32.860147 TX OE : PASS
9129 16:30:32.863844 All Pass.
9130 16:30:32.863949
9131 16:30:32.864044 DramC Write-DBI on
9132 16:30:32.867399 PER_BANK_REFRESH: Hybrid Mode
9133 16:30:32.867484 TX_TRACKING: ON
9134 16:30:32.877239 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 16:30:32.887133 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 16:30:32.893390 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 16:30:32.897006 [FAST_K] Save calibration result to emmc
9138 16:30:32.900029 sync common calibartion params.
9139 16:30:32.900103 sync cbt_mode0:1, 1:1
9140 16:30:32.903753 dram_init: ddr_geometry: 2
9141 16:30:32.906705 dram_init: ddr_geometry: 2
9142 16:30:32.906782 dram_init: ddr_geometry: 2
9143 16:30:32.909798 0:dram_rank_size:100000000
9144 16:30:32.913431 1:dram_rank_size:100000000
9145 16:30:32.920122 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 16:30:32.920233 DFS_SHUFFLE_HW_MODE: ON
9147 16:30:32.923176 dramc_set_vcore_voltage set vcore to 725000
9148 16:30:32.926875 Read voltage for 1600, 0
9149 16:30:32.926986 Vio18 = 0
9150 16:30:32.929962 Vcore = 725000
9151 16:30:32.930061 Vdram = 0
9152 16:30:32.930158 Vddq = 0
9153 16:30:32.933704 Vmddr = 0
9154 16:30:32.933807 switch to 3200 Mbps bootup
9155 16:30:32.936672 [DramcRunTimeConfig]
9156 16:30:32.936772 PHYPLL
9157 16:30:32.939732 DPM_CONTROL_AFTERK: ON
9158 16:30:32.939832 PER_BANK_REFRESH: ON
9159 16:30:32.943276 REFRESH_OVERHEAD_REDUCTION: ON
9160 16:30:32.947036 CMD_PICG_NEW_MODE: OFF
9161 16:30:32.947138 XRTWTW_NEW_MODE: ON
9162 16:30:32.949742 XRTRTR_NEW_MODE: ON
9163 16:30:32.949820 TX_TRACKING: ON
9164 16:30:32.953130 RDSEL_TRACKING: OFF
9165 16:30:32.956484 DQS Precalculation for DVFS: ON
9166 16:30:32.956564 RX_TRACKING: OFF
9167 16:30:32.959630 HW_GATING DBG: ON
9168 16:30:32.959732 ZQCS_ENABLE_LP4: ON
9169 16:30:32.962855 RX_PICG_NEW_MODE: ON
9170 16:30:32.962935 TX_PICG_NEW_MODE: ON
9171 16:30:32.966294 ENABLE_RX_DCM_DPHY: ON
9172 16:30:32.969688 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 16:30:32.973095 DUMMY_READ_FOR_TRACKING: OFF
9174 16:30:32.973175 !!! SPM_CONTROL_AFTERK: OFF
9175 16:30:32.976700 !!! SPM could not control APHY
9176 16:30:32.979386 IMPEDANCE_TRACKING: ON
9177 16:30:32.979482 TEMP_SENSOR: ON
9178 16:30:32.982981 HW_SAVE_FOR_SR: OFF
9179 16:30:32.986548 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 16:30:32.989622 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 16:30:32.989727 Read ODT Tracking: ON
9182 16:30:32.993222 Refresh Rate DeBounce: ON
9183 16:30:32.996550 DFS_NO_QUEUE_FLUSH: ON
9184 16:30:32.999325 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 16:30:33.003147 ENABLE_DFS_RUNTIME_MRW: OFF
9186 16:30:33.003252 DDR_RESERVE_NEW_MODE: ON
9187 16:30:33.006680 MR_CBT_SWITCH_FREQ: ON
9188 16:30:33.009365 =========================
9189 16:30:33.026775 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 16:30:33.029839 dram_init: ddr_geometry: 2
9191 16:30:33.048267 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 16:30:33.051476 dram_init: dram init end (result: 0)
9193 16:30:33.058066 DRAM-K: Full calibration passed in 24423 msecs
9194 16:30:33.061807 MRC: failed to locate region type 0.
9195 16:30:33.061910 DRAM rank0 size:0x100000000,
9196 16:30:33.064686 DRAM rank1 size=0x100000000
9197 16:30:33.075263 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 16:30:33.081543 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 16:30:33.088771 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 16:30:33.094965 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 16:30:33.098294 DRAM rank0 size:0x100000000,
9202 16:30:33.102073 DRAM rank1 size=0x100000000
9203 16:30:33.102184 CBMEM:
9204 16:30:33.105197 IMD: root @ 0xfffff000 254 entries.
9205 16:30:33.108079 IMD: root @ 0xffffec00 62 entries.
9206 16:30:33.111647 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 16:30:33.115046 WARNING: RO_VPD is uninitialized or empty.
9208 16:30:33.121891 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 16:30:33.128360 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 16:30:33.141236 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9211 16:30:33.153271 BS: romstage times (exec / console): total (unknown) / 23958 ms
9212 16:30:33.153386
9213 16:30:33.153475
9214 16:30:33.162533 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 16:30:33.166174 ARM64: Exception handlers installed.
9216 16:30:33.169156 ARM64: Testing exception
9217 16:30:33.172959 ARM64: Done test exception
9218 16:30:33.173039 Enumerating buses...
9219 16:30:33.175992 Show all devs... Before device enumeration.
9220 16:30:33.179634 Root Device: enabled 1
9221 16:30:33.182609 CPU_CLUSTER: 0: enabled 1
9222 16:30:33.182704 CPU: 00: enabled 1
9223 16:30:33.186159 Compare with tree...
9224 16:30:33.186254 Root Device: enabled 1
9225 16:30:33.189620 CPU_CLUSTER: 0: enabled 1
9226 16:30:33.192418 CPU: 00: enabled 1
9227 16:30:33.192618 Root Device scanning...
9228 16:30:33.196029 scan_static_bus for Root Device
9229 16:30:33.199440 CPU_CLUSTER: 0 enabled
9230 16:30:33.202800 scan_static_bus for Root Device done
9231 16:30:33.206166 scan_bus: bus Root Device finished in 8 msecs
9232 16:30:33.206271 done
9233 16:30:33.212701 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 16:30:33.215861 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 16:30:33.222150 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 16:30:33.225519 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 16:30:33.228959 Allocating resources...
9238 16:30:33.229044 Reading resources...
9239 16:30:33.236016 Root Device read_resources bus 0 link: 0
9240 16:30:33.236096 DRAM rank0 size:0x100000000,
9241 16:30:33.239153 DRAM rank1 size=0x100000000
9242 16:30:33.242698 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 16:30:33.245559 CPU: 00 missing read_resources
9244 16:30:33.249103 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 16:30:33.255385 Root Device read_resources bus 0 link: 0 done
9246 16:30:33.255466 Done reading resources.
9247 16:30:33.262077 Show resources in subtree (Root Device)...After reading.
9248 16:30:33.265789 Root Device child on link 0 CPU_CLUSTER: 0
9249 16:30:33.268793 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 16:30:33.279213 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 16:30:33.279290 CPU: 00
9252 16:30:33.282158 Root Device assign_resources, bus 0 link: 0
9253 16:30:33.285855 CPU_CLUSTER: 0 missing set_resources
9254 16:30:33.288974 Root Device assign_resources, bus 0 link: 0 done
9255 16:30:33.292414 Done setting resources.
9256 16:30:33.298996 Show resources in subtree (Root Device)...After assigning values.
9257 16:30:33.302052 Root Device child on link 0 CPU_CLUSTER: 0
9258 16:30:33.305690 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 16:30:33.315181 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 16:30:33.315271 CPU: 00
9261 16:30:33.318689 Done allocating resources.
9262 16:30:33.321622 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 16:30:33.325265 Enabling resources...
9264 16:30:33.325340 done.
9265 16:30:33.332227 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 16:30:33.332322 Initializing devices...
9267 16:30:33.335732 Root Device init
9268 16:30:33.335836 init hardware done!
9269 16:30:33.338665 0x00000018: ctrlr->caps
9270 16:30:33.342264 52.000 MHz: ctrlr->f_max
9271 16:30:33.342358 0.400 MHz: ctrlr->f_min
9272 16:30:33.345014 0x40ff8080: ctrlr->voltages
9273 16:30:33.345103 sclk: 390625
9274 16:30:33.348368 Bus Width = 1
9275 16:30:33.348450 sclk: 390625
9276 16:30:33.351817 Bus Width = 1
9277 16:30:33.351906 Early init status = 3
9278 16:30:33.358672 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 16:30:33.361600 in-header: 03 fc 00 00 01 00 00 00
9280 16:30:33.364836 in-data: 00
9281 16:30:33.368537 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9282 16:30:33.372944 in-header: 03 fd 00 00 00 00 00 00
9283 16:30:33.376540 in-data:
9284 16:30:33.379415 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9285 16:30:33.383834 in-header: 03 fc 00 00 01 00 00 00
9286 16:30:33.387514 in-data: 00
9287 16:30:33.390503 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9288 16:30:33.396473 in-header: 03 fd 00 00 00 00 00 00
9289 16:30:33.399361 in-data:
9290 16:30:33.402937 [SSUSB] Setting up USB HOST controller...
9291 16:30:33.406373 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9292 16:30:33.409314 [SSUSB] phy power-on done.
9293 16:30:33.413044 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9294 16:30:33.419485 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9295 16:30:33.422403 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9296 16:30:33.429650 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9297 16:30:33.436144 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9298 16:30:33.442462 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9299 16:30:33.449173 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9300 16:30:33.455914 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9301 16:30:33.459658 SPM: binary array size = 0x9dc
9302 16:30:33.462643 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9303 16:30:33.468894 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9304 16:30:33.475991 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9305 16:30:33.479167 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9306 16:30:33.485673 configure_display: Starting display init
9307 16:30:33.519659 anx7625_power_on_init: Init interface.
9308 16:30:33.522637 anx7625_disable_pd_protocol: Disabled PD feature.
9309 16:30:33.525751 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9310 16:30:33.553896 anx7625_start_dp_work: Secure OCM version=00
9311 16:30:33.557376 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9312 16:30:33.571749 sp_tx_get_edid_block: EDID Block = 1
9313 16:30:33.674840 Extracted contents:
9314 16:30:33.677914 header: 00 ff ff ff ff ff ff 00
9315 16:30:33.681364 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9316 16:30:33.684306 version: 01 04
9317 16:30:33.688008 basic params: 95 1f 11 78 0a
9318 16:30:33.691077 chroma info: 76 90 94 55 54 90 27 21 50 54
9319 16:30:33.694157 established: 00 00 00
9320 16:30:33.700604 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9321 16:30:33.704115 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9322 16:30:33.710970 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 16:30:33.717161 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9324 16:30:33.724076 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9325 16:30:33.727557 extensions: 00
9326 16:30:33.727668 checksum: fb
9327 16:30:33.727757
9328 16:30:33.730333 Manufacturer: IVO Model 57d Serial Number 0
9329 16:30:33.734030 Made week 0 of 2020
9330 16:30:33.734135 EDID version: 1.4
9331 16:30:33.737053 Digital display
9332 16:30:33.740613 6 bits per primary color channel
9333 16:30:33.740713 DisplayPort interface
9334 16:30:33.744205 Maximum image size: 31 cm x 17 cm
9335 16:30:33.747189 Gamma: 220%
9336 16:30:33.747291 Check DPMS levels
9337 16:30:33.750812 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9338 16:30:33.757444 First detailed timing is preferred timing
9339 16:30:33.757524 Established timings supported:
9340 16:30:33.760249 Standard timings supported:
9341 16:30:33.763950 Detailed timings
9342 16:30:33.766911 Hex of detail: 383680a07038204018303c0035ae10000019
9343 16:30:33.770591 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9344 16:30:33.777158 0780 0798 07c8 0820 hborder 0
9345 16:30:33.780691 0438 043b 0447 0458 vborder 0
9346 16:30:33.784136 -hsync -vsync
9347 16:30:33.784223 Did detailed timing
9348 16:30:33.790430 Hex of detail: 000000000000000000000000000000000000
9349 16:30:33.790539 Manufacturer-specified data, tag 0
9350 16:30:33.797162 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9351 16:30:33.800677 ASCII string: InfoVision
9352 16:30:33.803686 Hex of detail: 000000fe00523134304e574635205248200a
9353 16:30:33.807382 ASCII string: R140NWF5 RH
9354 16:30:33.807461 Checksum
9355 16:30:33.810173 Checksum: 0xfb (valid)
9356 16:30:33.813737 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9357 16:30:33.816780 DSI data_rate: 832800000 bps
9358 16:30:33.823645 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9359 16:30:33.827209 anx7625_parse_edid: pixelclock(138800).
9360 16:30:33.830725 hactive(1920), hsync(48), hfp(24), hbp(88)
9361 16:30:33.833403 vactive(1080), vsync(12), vfp(3), vbp(17)
9362 16:30:33.837342 anx7625_dsi_config: config dsi.
9363 16:30:33.843286 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9364 16:30:33.856426 anx7625_dsi_config: success to config DSI
9365 16:30:33.859762 anx7625_dp_start: MIPI phy setup OK.
9366 16:30:33.863433 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9367 16:30:33.866480 mtk_ddp_mode_set invalid vrefresh 60
9368 16:30:33.869410 main_disp_path_setup
9369 16:30:33.869507 ovl_layer_smi_id_en
9370 16:30:33.873186 ovl_layer_smi_id_en
9371 16:30:33.873294 ccorr_config
9372 16:30:33.873380 aal_config
9373 16:30:33.876139 gamma_config
9374 16:30:33.876239 postmask_config
9375 16:30:33.879844 dither_config
9376 16:30:33.882852 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9377 16:30:33.889794 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9378 16:30:33.893363 Root Device init finished in 555 msecs
9379 16:30:33.893464 CPU_CLUSTER: 0 init
9380 16:30:33.903337 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9381 16:30:33.906337 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9382 16:30:33.910028 APU_MBOX 0x190000b0 = 0x10001
9383 16:30:33.912928 APU_MBOX 0x190001b0 = 0x10001
9384 16:30:33.916504 APU_MBOX 0x190005b0 = 0x10001
9385 16:30:33.919505 APU_MBOX 0x190006b0 = 0x10001
9386 16:30:33.923291 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9387 16:30:33.935604 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9388 16:30:33.947777 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9389 16:30:33.954699 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9390 16:30:33.965862 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9391 16:30:33.975485 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9392 16:30:33.978887 CPU_CLUSTER: 0 init finished in 81 msecs
9393 16:30:33.981811 Devices initialized
9394 16:30:33.985462 Show all devs... After init.
9395 16:30:33.985573 Root Device: enabled 1
9396 16:30:33.988358 CPU_CLUSTER: 0: enabled 1
9397 16:30:33.992061 CPU: 00: enabled 1
9398 16:30:33.994964 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9399 16:30:33.998673 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9400 16:30:34.001590 ELOG: NV offset 0x57f000 size 0x1000
9401 16:30:34.008864 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9402 16:30:34.014897 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9403 16:30:34.018629 ELOG: Event(17) added with size 13 at 2024-06-17 16:30:33 UTC
9404 16:30:34.021502 out: cmd=0x121: 03 db 21 01 00 00 00 00
9405 16:30:34.025187 in-header: 03 53 00 00 2c 00 00 00
9406 16:30:34.039010 in-data: eb 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 16:30:34.045709 ELOG: Event(A1) added with size 10 at 2024-06-17 16:30:33 UTC
9408 16:30:34.052329 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9409 16:30:34.055369 ELOG: Event(A0) added with size 9 at 2024-06-17 16:30:33 UTC
9410 16:30:34.062269 elog_add_boot_reason: Logged dev mode boot
9411 16:30:34.065926 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9412 16:30:34.068697 Finalize devices...
9413 16:30:34.068774 Devices finalized
9414 16:30:34.075563 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9415 16:30:34.078977 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9416 16:30:34.082560 in-header: 03 07 00 00 08 00 00 00
9417 16:30:34.085317 in-data: aa e4 47 04 13 02 00 00
9418 16:30:34.088766 Chrome EC: UHEPI supported
9419 16:30:34.095642 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9420 16:30:34.098594 in-header: 03 a9 00 00 08 00 00 00
9421 16:30:34.102178 in-data: 84 60 60 08 00 00 00 00
9422 16:30:34.105788 ELOG: Event(91) added with size 10 at 2024-06-17 16:30:33 UTC
9423 16:30:34.112249 Chrome EC: clear events_b mask to 0x0000000020004000
9424 16:30:34.118789 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9425 16:30:34.122661 in-header: 03 fd 00 00 00 00 00 00
9426 16:30:34.122749 in-data:
9427 16:30:34.129151 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9428 16:30:34.132815 Writing coreboot table at 0xffe64000
9429 16:30:34.135811 0. 000000000010a000-0000000000113fff: RAMSTAGE
9430 16:30:34.139310 1. 0000000040000000-00000000400fffff: RAM
9431 16:30:34.142971 2. 0000000040100000-000000004032afff: RAMSTAGE
9432 16:30:34.149692 3. 000000004032b000-00000000545fffff: RAM
9433 16:30:34.152693 4. 0000000054600000-000000005465ffff: BL31
9434 16:30:34.155665 5. 0000000054660000-00000000ffe63fff: RAM
9435 16:30:34.159358 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9436 16:30:34.166031 7. 0000000100000000-000000023fffffff: RAM
9437 16:30:34.166117 Passing 5 GPIOs to payload:
9438 16:30:34.172632 NAME | PORT | POLARITY | VALUE
9439 16:30:34.176207 EC in RW | 0x000000aa | low | undefined
9440 16:30:34.182548 EC interrupt | 0x00000005 | low | undefined
9441 16:30:34.186141 TPM interrupt | 0x000000ab | high | undefined
9442 16:30:34.189154 SD card detect | 0x00000011 | high | undefined
9443 16:30:34.195918 speaker enable | 0x00000093 | high | undefined
9444 16:30:34.199406 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9445 16:30:34.202093 in-header: 03 f9 00 00 02 00 00 00
9446 16:30:34.202195 in-data: 02 00
9447 16:30:34.205514 ADC[4]: Raw value=903988 ID=7
9448 16:30:34.208792 ADC[3]: Raw value=213810 ID=1
9449 16:30:34.208867 RAM Code: 0x71
9450 16:30:34.212225 ADC[6]: Raw value=75701 ID=0
9451 16:30:34.216095 ADC[5]: Raw value=212703 ID=1
9452 16:30:34.216176 SKU Code: 0x1
9453 16:30:34.222567 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6d76
9454 16:30:34.225421 coreboot table: 964 bytes.
9455 16:30:34.229031 IMD ROOT 0. 0xfffff000 0x00001000
9456 16:30:34.232656 IMD SMALL 1. 0xffffe000 0x00001000
9457 16:30:34.235571 RO MCACHE 2. 0xffffc000 0x00001104
9458 16:30:34.239337 CONSOLE 3. 0xfff7c000 0x00080000
9459 16:30:34.242256 FMAP 4. 0xfff7b000 0x00000452
9460 16:30:34.245812 TIME STAMP 5. 0xfff7a000 0x00000910
9461 16:30:34.248690 VBOOT WORK 6. 0xfff66000 0x00014000
9462 16:30:34.252059 RAMOOPS 7. 0xffe66000 0x00100000
9463 16:30:34.255756 COREBOOT 8. 0xffe64000 0x00002000
9464 16:30:34.255846 IMD small region:
9465 16:30:34.258732 IMD ROOT 0. 0xffffec00 0x00000400
9466 16:30:34.262450 VPD 1. 0xffffeb80 0x0000006c
9467 16:30:34.265377 MMC STATUS 2. 0xffffeb60 0x00000004
9468 16:30:34.272003 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9469 16:30:34.278648 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9470 16:30:34.318128 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9471 16:30:34.321702 Checking segment from ROM address 0x40100000
9472 16:30:34.325106 Checking segment from ROM address 0x4010001c
9473 16:30:34.331641 Loading segment from ROM address 0x40100000
9474 16:30:34.331755 code (compression=0)
9475 16:30:34.341140 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9476 16:30:34.347802 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9477 16:30:34.347918 it's not compressed!
9478 16:30:34.354358 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9479 16:30:34.360869 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9480 16:30:34.378341 Loading segment from ROM address 0x4010001c
9481 16:30:34.378457 Entry Point 0x80000000
9482 16:30:34.382065 Loaded segments
9483 16:30:34.384986 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9484 16:30:34.391408 Jumping to boot code at 0x80000000(0xffe64000)
9485 16:30:34.398423 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9486 16:30:34.404834 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9487 16:30:34.413092 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9488 16:30:34.416600 Checking segment from ROM address 0x40100000
9489 16:30:34.419962 Checking segment from ROM address 0x4010001c
9490 16:30:34.426521 Loading segment from ROM address 0x40100000
9491 16:30:34.426607 code (compression=1)
9492 16:30:34.432956 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9493 16:30:34.443081 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9494 16:30:34.443197 using LZMA
9495 16:30:34.451130 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9496 16:30:34.458232 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9497 16:30:34.461160 Loading segment from ROM address 0x4010001c
9498 16:30:34.461244 Entry Point 0x54601000
9499 16:30:34.464870 Loaded segments
9500 16:30:34.467554 NOTICE: MT8192 bl31_setup
9501 16:30:34.474805 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9502 16:30:34.478385 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9503 16:30:34.482144 WARNING: region 0:
9504 16:30:34.485146 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 16:30:34.485250 WARNING: region 1:
9506 16:30:34.491750 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9507 16:30:34.494731 WARNING: region 2:
9508 16:30:34.498546 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9509 16:30:34.501385 WARNING: region 3:
9510 16:30:34.504973 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9511 16:30:34.508457 WARNING: region 4:
9512 16:30:34.511496 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9513 16:30:34.515280 WARNING: region 5:
9514 16:30:34.518303 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 16:30:34.521979 WARNING: region 6:
9516 16:30:34.524947 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 16:30:34.528422 WARNING: region 7:
9518 16:30:34.531753 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 16:30:34.538361 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9520 16:30:34.541767 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9521 16:30:34.544772 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9522 16:30:34.551334 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9523 16:30:34.554715 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9524 16:30:34.558087 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9525 16:30:34.564989 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9526 16:30:34.568405 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9527 16:30:34.575111 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9528 16:30:34.577958 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9529 16:30:34.581672 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9530 16:30:34.588246 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9531 16:30:34.591808 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9532 16:30:34.594805 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9533 16:30:34.601350 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9534 16:30:34.605040 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9535 16:30:34.611603 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9536 16:30:34.615047 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9537 16:30:34.617969 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9538 16:30:34.624669 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9539 16:30:34.628465 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9540 16:30:34.631449 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9541 16:30:34.637991 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9542 16:30:34.641365 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9543 16:30:34.648181 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9544 16:30:34.651790 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9545 16:30:34.654757 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9546 16:30:34.661049 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9547 16:30:34.664585 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9548 16:30:34.671382 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9549 16:30:34.674997 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9550 16:30:34.677930 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9551 16:30:34.684726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9552 16:30:34.687524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9553 16:30:34.691091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9554 16:30:34.694843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9555 16:30:34.701562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9556 16:30:34.704561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9557 16:30:34.707550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9558 16:30:34.711216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9559 16:30:34.717879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9560 16:30:34.721334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9561 16:30:34.724790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9562 16:30:34.727637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9563 16:30:34.734290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9564 16:30:34.737808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9565 16:30:34.741536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9566 16:30:34.744532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9567 16:30:34.751022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9568 16:30:34.754543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9569 16:30:34.761338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9570 16:30:34.764147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9571 16:30:34.771472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9572 16:30:34.774895 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9573 16:30:34.778186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9574 16:30:34.784171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9575 16:30:34.787707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9576 16:30:34.794583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9577 16:30:34.797903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9578 16:30:34.804354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9579 16:30:34.808048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9580 16:30:34.811031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9581 16:30:34.817668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9582 16:30:34.821408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9583 16:30:34.827795 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9584 16:30:34.831232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9585 16:30:34.837867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9586 16:30:34.840858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9587 16:30:34.844668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9588 16:30:34.851416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9589 16:30:34.854319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9590 16:30:34.861279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9591 16:30:34.864186 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9592 16:30:34.870872 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9593 16:30:34.874536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9594 16:30:34.878191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9595 16:30:34.884541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9596 16:30:34.888086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9597 16:30:34.894242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9598 16:30:34.897770 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9599 16:30:34.904430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9600 16:30:34.907948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9601 16:30:34.914100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9602 16:30:34.917663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9603 16:30:34.921443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9604 16:30:34.928155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9605 16:30:34.931149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9606 16:30:34.938165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9607 16:30:34.940950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9608 16:30:34.944619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9609 16:30:34.951347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9610 16:30:34.954375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9611 16:30:34.961086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9612 16:30:34.964133 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9613 16:30:34.970707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9614 16:30:34.974405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9615 16:30:34.977286 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9616 16:30:34.984095 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9617 16:30:34.988060 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9618 16:30:34.990786 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9619 16:30:34.994174 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9620 16:30:35.001318 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9621 16:30:35.004378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9622 16:30:35.010839 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9623 16:30:35.014351 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9624 16:30:35.017541 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9625 16:30:35.024169 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9626 16:30:35.027856 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9627 16:30:35.034569 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9628 16:30:35.037571 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9629 16:30:35.041224 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9630 16:30:35.047743 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9631 16:30:35.051312 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9632 16:30:35.057953 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9633 16:30:35.060998 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9634 16:30:35.064698 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9635 16:30:35.067592 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9636 16:30:35.074216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9637 16:30:35.078032 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9638 16:30:35.081315 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9639 16:30:35.087994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9640 16:30:35.090978 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9641 16:30:35.094466 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9642 16:30:35.097952 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9643 16:30:35.104658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9644 16:30:35.108075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9645 16:30:35.114831 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9646 16:30:35.117673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9647 16:30:35.121363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9648 16:30:35.127774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9649 16:30:35.131399 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9650 16:30:35.134657 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9651 16:30:35.141284 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9652 16:30:35.144402 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9653 16:30:35.151044 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9654 16:30:35.154338 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9655 16:30:35.157857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9656 16:30:35.164346 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9657 16:30:35.167406 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9658 16:30:35.174880 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9659 16:30:35.177931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9660 16:30:35.180904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9661 16:30:35.187631 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9662 16:30:35.191298 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9663 16:30:35.194303 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9664 16:30:35.200920 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9665 16:30:35.204405 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9666 16:30:35.211279 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9667 16:30:35.214174 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9668 16:30:35.217523 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9669 16:30:35.224745 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9670 16:30:35.227477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9671 16:30:35.234723 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9672 16:30:35.237519 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9673 16:30:35.241187 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9674 16:30:35.247751 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9675 16:30:35.250961 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9676 16:30:35.257376 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9677 16:30:35.260813 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9678 16:30:35.264353 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9679 16:30:35.270633 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9680 16:30:35.274351 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9681 16:30:35.280915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9682 16:30:35.283906 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9683 16:30:35.287635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9684 16:30:35.294326 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9685 16:30:35.297277 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9686 16:30:35.301131 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9687 16:30:35.307190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9688 16:30:35.310642 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9689 16:30:35.317784 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9690 16:30:35.320731 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9691 16:30:35.324362 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9692 16:30:35.330757 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9693 16:30:35.334222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9694 16:30:35.340591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9695 16:30:35.343987 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9696 16:30:35.347336 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9697 16:30:35.354158 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9698 16:30:35.357819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9699 16:30:35.361112 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9700 16:30:35.367282 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9701 16:30:35.370816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9702 16:30:35.377796 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9703 16:30:35.380594 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9704 16:30:35.384145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9705 16:30:35.390731 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9706 16:30:35.394438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9707 16:30:35.401190 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9708 16:30:35.404094 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9709 16:30:35.407145 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9710 16:30:35.413874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9711 16:30:35.417431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9712 16:30:35.423934 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9713 16:30:35.427017 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9714 16:30:35.433507 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9715 16:30:35.437003 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9716 16:30:35.440624 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9717 16:30:35.447568 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9718 16:30:35.450551 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9719 16:30:35.457149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9720 16:30:35.460303 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9721 16:30:35.463576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9722 16:30:35.470592 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9723 16:30:35.474102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9724 16:30:35.480238 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9725 16:30:35.483721 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9726 16:30:35.487500 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9727 16:30:35.493979 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9728 16:30:35.497255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9729 16:30:35.503701 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9730 16:30:35.507408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9731 16:30:35.514155 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9732 16:30:35.517130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9733 16:30:35.520815 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9734 16:30:35.527038 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9735 16:30:35.530722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9736 16:30:35.537178 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9737 16:30:35.540903 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9738 16:30:35.543707 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9739 16:30:35.550442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9740 16:30:35.554035 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9741 16:30:35.560744 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9742 16:30:35.563809 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9743 16:30:35.567189 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9744 16:30:35.574236 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9745 16:30:35.577072 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9746 16:30:35.583740 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9747 16:30:35.587350 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9748 16:30:35.590926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9749 16:30:35.593610 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9750 16:30:35.600649 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9751 16:30:35.603427 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9752 16:30:35.606954 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9753 16:30:35.613954 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9754 16:30:35.616878 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9755 16:30:35.620593 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9756 16:30:35.627309 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9757 16:30:35.630198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9758 16:30:35.633667 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9759 16:30:35.640784 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9760 16:30:35.643621 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9761 16:30:35.650182 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9762 16:30:35.653930 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9763 16:30:35.656985 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9764 16:30:35.663537 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9765 16:30:35.667154 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9766 16:30:35.670152 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9767 16:30:35.676631 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9768 16:30:35.680151 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9769 16:30:35.683817 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9770 16:30:35.690108 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9771 16:30:35.693909 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9772 16:30:35.696897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9773 16:30:35.703304 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9774 16:30:35.706809 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9775 16:30:35.713636 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9776 16:30:35.717138 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9777 16:30:35.720021 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9778 16:30:35.726629 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9779 16:30:35.730243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9780 16:30:35.733870 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9781 16:30:35.740314 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9782 16:30:35.743906 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9783 16:30:35.746689 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9784 16:30:35.753596 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9785 16:30:35.757153 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9786 16:30:35.763142 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9787 16:30:35.766772 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9788 16:30:35.769906 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9789 16:30:35.773402 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9790 16:30:35.777054 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9791 16:30:35.783696 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9792 16:30:35.786752 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9793 16:30:35.789805 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9794 16:30:35.793344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9795 16:30:35.799925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9796 16:30:35.802966 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9797 16:30:35.806671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9798 16:30:35.809563 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9799 16:30:35.816281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9800 16:30:35.819805 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9801 16:30:35.823422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9802 16:30:35.829972 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9803 16:30:35.833362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9804 16:30:35.839621 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9805 16:30:35.842828 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9806 16:30:35.849634 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9807 16:30:35.852933 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9808 16:30:35.856314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9809 16:30:35.863041 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9810 16:30:35.866643 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9811 16:30:35.873210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9812 16:30:35.876908 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9813 16:30:35.879676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9814 16:30:35.886404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9815 16:30:35.890083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9816 16:30:35.896775 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9817 16:30:35.899704 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9818 16:30:35.902686 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9819 16:30:35.910112 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9820 16:30:35.913076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9821 16:30:35.919899 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9822 16:30:35.922782 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9823 16:30:35.929726 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9824 16:30:35.933241 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9825 16:30:35.936208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9826 16:30:35.942755 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9827 16:30:35.945823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9828 16:30:35.953050 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9829 16:30:35.956563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9830 16:30:35.959367 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9831 16:30:35.966333 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9832 16:30:35.969924 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9833 16:30:35.972797 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9834 16:30:35.979514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9835 16:30:35.982822 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9836 16:30:35.989523 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9837 16:30:35.993232 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9838 16:30:35.996177 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9839 16:30:36.002920 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9840 16:30:36.006652 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9841 16:30:36.012727 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9842 16:30:36.016382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9843 16:30:36.019973 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9844 16:30:36.026719 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9845 16:30:36.029667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9846 16:30:36.036172 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9847 16:30:36.039651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9848 16:30:36.042990 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9849 16:30:36.049584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9850 16:30:36.053160 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9851 16:30:36.059928 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9852 16:30:36.062805 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9853 16:30:36.069449 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9854 16:30:36.073078 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9855 16:30:36.076161 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9856 16:30:36.083137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9857 16:30:36.086550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9858 16:30:36.089352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9859 16:30:36.096268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9860 16:30:36.099330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9861 16:30:36.106360 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9862 16:30:36.109343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9863 16:30:36.116211 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9864 16:30:36.119773 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9865 16:30:36.122821 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9866 16:30:36.129391 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9867 16:30:36.133113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9868 16:30:36.139749 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9869 16:30:36.142655 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9870 16:30:36.146257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9871 16:30:36.152961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9872 16:30:36.156384 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9873 16:30:36.162859 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9874 16:30:36.165918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9875 16:30:36.172616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9876 16:30:36.175604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9877 16:30:36.179430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9878 16:30:36.185676 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9879 16:30:36.189083 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9880 16:30:36.195689 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9881 16:30:36.199184 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9882 16:30:36.205896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9883 16:30:36.208829 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9884 16:30:36.212660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9885 16:30:36.218791 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9886 16:30:36.222735 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9887 16:30:36.229278 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9888 16:30:36.232356 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9889 16:30:36.238982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9890 16:30:36.242164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9891 16:30:36.245942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9892 16:30:36.252654 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9893 16:30:36.255693 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9894 16:30:36.262277 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9895 16:30:36.265844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9896 16:30:36.272193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9897 16:30:36.275967 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9898 16:30:36.278888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9899 16:30:36.285833 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9900 16:30:36.289349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9901 16:30:36.295914 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9902 16:30:36.298703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9903 16:30:36.305632 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9904 16:30:36.308651 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9905 16:30:36.312296 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9906 16:30:36.319060 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9907 16:30:36.321963 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9908 16:30:36.328681 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9909 16:30:36.332297 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9910 16:30:36.338815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9911 16:30:36.342178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9912 16:30:36.345712 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9913 16:30:36.352002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9914 16:30:36.355852 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9915 16:30:36.362080 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9916 16:30:36.366142 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9917 16:30:36.372569 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9918 16:30:36.376045 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9919 16:30:36.378851 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9920 16:30:36.385899 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9921 16:30:36.388973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9922 16:30:36.396032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9923 16:30:36.398899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9924 16:30:36.405882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9925 16:30:36.408594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9926 16:30:36.412031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9927 16:30:36.419122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9928 16:30:36.422155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9929 16:30:36.428574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9930 16:30:36.432038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9931 16:30:36.438667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9932 16:30:36.442213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9933 16:30:36.448385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9934 16:30:36.451723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9935 16:30:36.458217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9936 16:30:36.461910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9937 16:30:36.468173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9938 16:30:36.471701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9939 16:30:36.478528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9940 16:30:36.481731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9941 16:30:36.488273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9942 16:30:36.492246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9943 16:30:36.498254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9944 16:30:36.501721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9945 16:30:36.508814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9946 16:30:36.511886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9947 16:30:36.518341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9948 16:30:36.521914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9949 16:30:36.528316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9950 16:30:36.531748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9951 16:30:36.538335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9952 16:30:36.541902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9953 16:30:36.544882 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9954 16:30:36.548566 INFO: [APUAPC] vio 0
9955 16:30:36.554875 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9956 16:30:36.558191 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9957 16:30:36.561708 INFO: [APUAPC] D0_APC_0: 0x400510
9958 16:30:36.565378 INFO: [APUAPC] D0_APC_1: 0x0
9959 16:30:36.568198 INFO: [APUAPC] D0_APC_2: 0x1540
9960 16:30:36.571940 INFO: [APUAPC] D0_APC_3: 0x0
9961 16:30:36.574802 INFO: [APUAPC] D1_APC_0: 0xffffffff
9962 16:30:36.578389 INFO: [APUAPC] D1_APC_1: 0xffffffff
9963 16:30:36.582039 INFO: [APUAPC] D1_APC_2: 0x3fffff
9964 16:30:36.584815 INFO: [APUAPC] D1_APC_3: 0x0
9965 16:30:36.588301 INFO: [APUAPC] D2_APC_0: 0xffffffff
9966 16:30:36.591955 INFO: [APUAPC] D2_APC_1: 0xffffffff
9967 16:30:36.594897 INFO: [APUAPC] D2_APC_2: 0x3fffff
9968 16:30:36.594976 INFO: [APUAPC] D2_APC_3: 0x0
9969 16:30:36.598391 INFO: [APUAPC] D3_APC_0: 0xffffffff
9970 16:30:36.605155 INFO: [APUAPC] D3_APC_1: 0xffffffff
9971 16:30:36.608517 INFO: [APUAPC] D3_APC_2: 0x3fffff
9972 16:30:36.608596 INFO: [APUAPC] D3_APC_3: 0x0
9973 16:30:36.611775 INFO: [APUAPC] D4_APC_0: 0xffffffff
9974 16:30:36.615133 INFO: [APUAPC] D4_APC_1: 0xffffffff
9975 16:30:36.618372 INFO: [APUAPC] D4_APC_2: 0x3fffff
9976 16:30:36.621826 INFO: [APUAPC] D4_APC_3: 0x0
9977 16:30:36.625311 INFO: [APUAPC] D5_APC_0: 0xffffffff
9978 16:30:36.628754 INFO: [APUAPC] D5_APC_1: 0xffffffff
9979 16:30:36.631558 INFO: [APUAPC] D5_APC_2: 0x3fffff
9980 16:30:36.634970 INFO: [APUAPC] D5_APC_3: 0x0
9981 16:30:36.638355 INFO: [APUAPC] D6_APC_0: 0xffffffff
9982 16:30:36.641882 INFO: [APUAPC] D6_APC_1: 0xffffffff
9983 16:30:36.644791 INFO: [APUAPC] D6_APC_2: 0x3fffff
9984 16:30:36.648419 INFO: [APUAPC] D6_APC_3: 0x0
9985 16:30:36.651380 INFO: [APUAPC] D7_APC_0: 0xffffffff
9986 16:30:36.654909 INFO: [APUAPC] D7_APC_1: 0xffffffff
9987 16:30:36.658544 INFO: [APUAPC] D7_APC_2: 0x3fffff
9988 16:30:36.662115 INFO: [APUAPC] D7_APC_3: 0x0
9989 16:30:36.664861 INFO: [APUAPC] D8_APC_0: 0xffffffff
9990 16:30:36.668184 INFO: [APUAPC] D8_APC_1: 0xffffffff
9991 16:30:36.671941 INFO: [APUAPC] D8_APC_2: 0x3fffff
9992 16:30:36.674909 INFO: [APUAPC] D8_APC_3: 0x0
9993 16:30:36.678516 INFO: [APUAPC] D9_APC_0: 0xffffffff
9994 16:30:36.681406 INFO: [APUAPC] D9_APC_1: 0xffffffff
9995 16:30:36.685082 INFO: [APUAPC] D9_APC_2: 0x3fffff
9996 16:30:36.688703 INFO: [APUAPC] D9_APC_3: 0x0
9997 16:30:36.691390 INFO: [APUAPC] D10_APC_0: 0xffffffff
9998 16:30:36.694911 INFO: [APUAPC] D10_APC_1: 0xffffffff
9999 16:30:36.698724 INFO: [APUAPC] D10_APC_2: 0x3fffff
10000 16:30:36.701691 INFO: [APUAPC] D10_APC_3: 0x0
10001 16:30:36.705204 INFO: [APUAPC] D11_APC_0: 0xffffffff
10002 16:30:36.708072 INFO: [APUAPC] D11_APC_1: 0xffffffff
10003 16:30:36.711688 INFO: [APUAPC] D11_APC_2: 0x3fffff
10004 16:30:36.715201 INFO: [APUAPC] D11_APC_3: 0x0
10005 16:30:36.718791 INFO: [APUAPC] D12_APC_0: 0xffffffff
10006 16:30:36.721488 INFO: [APUAPC] D12_APC_1: 0xffffffff
10007 16:30:36.724968 INFO: [APUAPC] D12_APC_2: 0x3fffff
10008 16:30:36.728258 INFO: [APUAPC] D12_APC_3: 0x0
10009 16:30:36.731555 INFO: [APUAPC] D13_APC_0: 0xffffffff
10010 16:30:36.734919 INFO: [APUAPC] D13_APC_1: 0xffffffff
10011 16:30:36.738187 INFO: [APUAPC] D13_APC_2: 0x3fffff
10012 16:30:36.741986 INFO: [APUAPC] D13_APC_3: 0x0
10013 16:30:36.745222 INFO: [APUAPC] D14_APC_0: 0xffffffff
10014 16:30:36.748328 INFO: [APUAPC] D14_APC_1: 0xffffffff
10015 16:30:36.751687 INFO: [APUAPC] D14_APC_2: 0x3fffff
10016 16:30:36.755067 INFO: [APUAPC] D14_APC_3: 0x0
10017 16:30:36.758576 INFO: [APUAPC] D15_APC_0: 0xffffffff
10018 16:30:36.761523 INFO: [APUAPC] D15_APC_1: 0xffffffff
10019 16:30:36.764488 INFO: [APUAPC] D15_APC_2: 0x3fffff
10020 16:30:36.768157 INFO: [APUAPC] D15_APC_3: 0x0
10021 16:30:36.771639 INFO: [APUAPC] APC_CON: 0x4
10022 16:30:36.775000 INFO: [NOCDAPC] D0_APC_0: 0x0
10023 16:30:36.775101 INFO: [NOCDAPC] D0_APC_1: 0x0
10024 16:30:36.778333 INFO: [NOCDAPC] D1_APC_0: 0x0
10025 16:30:36.781223 INFO: [NOCDAPC] D1_APC_1: 0xfff
10026 16:30:36.784829 INFO: [NOCDAPC] D2_APC_0: 0x0
10027 16:30:36.788397 INFO: [NOCDAPC] D2_APC_1: 0xfff
10028 16:30:36.791437 INFO: [NOCDAPC] D3_APC_0: 0x0
10029 16:30:36.794977 INFO: [NOCDAPC] D3_APC_1: 0xfff
10030 16:30:36.797844 INFO: [NOCDAPC] D4_APC_0: 0x0
10031 16:30:36.801407 INFO: [NOCDAPC] D4_APC_1: 0xfff
10032 16:30:36.804953 INFO: [NOCDAPC] D5_APC_0: 0x0
10033 16:30:36.807815 INFO: [NOCDAPC] D5_APC_1: 0xfff
10034 16:30:36.807892 INFO: [NOCDAPC] D6_APC_0: 0x0
10035 16:30:36.811412 INFO: [NOCDAPC] D6_APC_1: 0xfff
10036 16:30:36.814947 INFO: [NOCDAPC] D7_APC_0: 0x0
10037 16:30:36.817846 INFO: [NOCDAPC] D7_APC_1: 0xfff
10038 16:30:36.821316 INFO: [NOCDAPC] D8_APC_0: 0x0
10039 16:30:36.824890 INFO: [NOCDAPC] D8_APC_1: 0xfff
10040 16:30:36.827796 INFO: [NOCDAPC] D9_APC_0: 0x0
10041 16:30:36.831448 INFO: [NOCDAPC] D9_APC_1: 0xfff
10042 16:30:36.834934 INFO: [NOCDAPC] D10_APC_0: 0x0
10043 16:30:36.837718 INFO: [NOCDAPC] D10_APC_1: 0xfff
10044 16:30:36.841439 INFO: [NOCDAPC] D11_APC_0: 0x0
10045 16:30:36.844325 INFO: [NOCDAPC] D11_APC_1: 0xfff
10046 16:30:36.844441 INFO: [NOCDAPC] D12_APC_0: 0x0
10047 16:30:36.847970 INFO: [NOCDAPC] D12_APC_1: 0xfff
10048 16:30:36.851466 INFO: [NOCDAPC] D13_APC_0: 0x0
10049 16:30:36.854488 INFO: [NOCDAPC] D13_APC_1: 0xfff
10050 16:30:36.857925 INFO: [NOCDAPC] D14_APC_0: 0x0
10051 16:30:36.861203 INFO: [NOCDAPC] D14_APC_1: 0xfff
10052 16:30:36.864579 INFO: [NOCDAPC] D15_APC_0: 0x0
10053 16:30:36.867780 INFO: [NOCDAPC] D15_APC_1: 0xfff
10054 16:30:36.870943 INFO: [NOCDAPC] APC_CON: 0x4
10055 16:30:36.874181 INFO: [APUAPC] set_apusys_apc done
10056 16:30:36.877567 INFO: [DEVAPC] devapc_init done
10057 16:30:36.880990 INFO: GICv3 without legacy support detected.
10058 16:30:36.884510 INFO: ARM GICv3 driver initialized in EL3
10059 16:30:36.888010 INFO: Maximum SPI INTID supported: 639
10060 16:30:36.894713 INFO: BL31: Initializing runtime services
10061 16:30:36.897662 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10062 16:30:36.901121 INFO: SPM: enable CPC mode
10063 16:30:36.907442 INFO: mcdi ready for mcusys-off-idle and system suspend
10064 16:30:36.911142 INFO: BL31: Preparing for EL3 exit to normal world
10065 16:30:36.914004 INFO: Entry point address = 0x80000000
10066 16:30:36.917641 INFO: SPSR = 0x8
10067 16:30:36.922651
10068 16:30:36.922728
10069 16:30:36.922786
10070 16:30:36.923483 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10071 16:30:36.923582 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10072 16:30:36.923657 Setting prompt string to ['asurada:']
10073 16:30:36.923729 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10074 16:30:36.926195 Starting depthcharge on Spherion...
10075 16:30:36.926274
10076 16:30:36.926334 Wipe memory regions:
10077 16:30:36.926391
10078 16:30:36.929891 [0x00000040000000, 0x00000054600000)
10079 16:30:37.051391
10080 16:30:37.051508 [0x00000054660000, 0x00000080000000)
10081 16:30:37.311954
10082 16:30:37.312073 [0x000000821a7280, 0x000000ffe64000)
10083 16:30:38.056609
10084 16:30:38.056740 [0x00000100000000, 0x00000240000000)
10085 16:30:39.945314
10086 16:30:39.948072 Initializing XHCI USB controller at 0x11200000.
10087 16:30:40.987253
10088 16:30:40.990736 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10089 16:30:40.990852
10090 16:30:40.990925
10091 16:30:40.991200 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 16:30:41.091559 asurada: tftpboot 192.168.201.1 14396104/tftp-deploy-sqzd0v25/kernel/image.itb 14396104/tftp-deploy-sqzd0v25/kernel/cmdline
10094 16:30:41.091770 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10095 16:30:41.091857 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10096 16:30:41.096680 tftpboot 192.168.201.1 14396104/tftp-deploy-sqzd0v25/kernel/image.ittp-deploy-sqzd0v25/kernel/cmdline
10097 16:30:41.096757
10098 16:30:41.096832 Waiting for link
10099 16:30:41.254401
10100 16:30:41.254546 R8152: Initializing
10101 16:30:41.254626
10102 16:30:41.258156 Version 9 (ocp_data = 6010)
10103 16:30:41.258233
10104 16:30:41.261477 R8152: Done initializing
10105 16:30:41.261612
10106 16:30:41.261672 Adding net device
10107 16:30:43.135020
10108 16:30:43.135137 done.
10109 16:30:43.135199
10110 16:30:43.135255 MAC: 00:e0:4c:78:7a:aa
10111 16:30:43.135308
10112 16:30:43.138711 Sending DHCP discover... done.
10113 16:30:43.138793
10114 16:30:43.142064 Waiting for reply... done.
10115 16:30:43.142167
10116 16:30:43.144641 Sending DHCP request... done.
10117 16:30:43.144748
10118 16:30:43.149825 Waiting for reply... done.
10119 16:30:43.149904
10120 16:30:43.149983 My ip is 192.168.201.12
10121 16:30:43.150060
10122 16:30:43.152851 The DHCP server ip is 192.168.201.1
10123 16:30:43.152943
10124 16:30:43.159528 TFTP server IP predefined by user: 192.168.201.1
10125 16:30:43.159608
10126 16:30:43.166525 Bootfile predefined by user: 14396104/tftp-deploy-sqzd0v25/kernel/image.itb
10127 16:30:43.166629
10128 16:30:43.166737 Sending tftp read request... done.
10129 16:30:43.169302
10130 16:30:43.172814 Waiting for the transfer...
10131 16:30:43.172922
10132 16:30:43.419211 00000000 ################################################################
10133 16:30:43.419351
10134 16:30:43.669502 00080000 ################################################################
10135 16:30:43.669654
10136 16:30:43.918943 00100000 ################################################################
10137 16:30:43.919081
10138 16:30:44.167930 00180000 ################################################################
10139 16:30:44.168048
10140 16:30:44.422188 00200000 ################################################################
10141 16:30:44.422321
10142 16:30:44.677090 00280000 ################################################################
10143 16:30:44.677200
10144 16:30:44.929251 00300000 ################################################################
10145 16:30:44.929411
10146 16:30:45.177777 00380000 ################################################################
10147 16:30:45.177895
10148 16:30:45.427305 00400000 ################################################################
10149 16:30:45.427457
10150 16:30:45.674881 00480000 ################################################################
10151 16:30:45.675036
10152 16:30:45.923900 00500000 ################################################################
10153 16:30:45.924021
10154 16:30:46.172974 00580000 ################################################################
10155 16:30:46.173116
10156 16:30:46.425107 00600000 ################################################################
10157 16:30:46.425268
10158 16:30:46.682172 00680000 ################################################################
10159 16:30:46.682310
10160 16:30:46.935711 00700000 ################################################################
10161 16:30:46.935850
10162 16:30:47.183667 00780000 ################################################################
10163 16:30:47.183793
10164 16:30:47.439816 00800000 ################################################################
10165 16:30:47.439955
10166 16:30:47.686516 00880000 ################################################################
10167 16:30:47.686681
10168 16:30:47.936620 00900000 ################################################################
10169 16:30:47.936734
10170 16:30:48.184044 00980000 ################################################################
10171 16:30:48.184162
10172 16:30:48.433316 00a00000 ################################################################
10173 16:30:48.433450
10174 16:30:48.689775 00a80000 ################################################################
10175 16:30:48.689921
10176 16:30:48.947019 00b00000 ################################################################
10177 16:30:48.947166
10178 16:30:49.201299 00b80000 ################################################################
10179 16:30:49.201428
10180 16:30:49.448014 00c00000 ################################################################
10181 16:30:49.448134
10182 16:30:49.701826 00c80000 ################################################################
10183 16:30:49.701993
10184 16:30:49.980641 00d00000 ################################################################
10185 16:30:49.980765
10186 16:30:50.236220 00d80000 ################################################################
10187 16:30:50.236348
10188 16:30:50.493733 00e00000 ################################################################
10189 16:30:50.493869
10190 16:30:50.754323 00e80000 ################################################################
10191 16:30:50.754457
10192 16:30:51.030851 00f00000 ################################################################
10193 16:30:51.030977
10194 16:30:51.284404 00f80000 ################################################################
10195 16:30:51.284563
10196 16:30:51.536433 01000000 ################################################################
10197 16:30:51.536574
10198 16:30:51.785171 01080000 ################################################################
10199 16:30:51.785318
10200 16:30:52.034859 01100000 ################################################################
10201 16:30:52.035010
10202 16:30:52.291711 01180000 ################################################################
10203 16:30:52.291866
10204 16:30:52.560965 01200000 ################################################################
10205 16:30:52.561094
10206 16:30:52.805743 01280000 ################################################################
10207 16:30:52.805876
10208 16:30:53.061310 01300000 ################################################################
10209 16:30:53.061457
10210 16:30:53.321422 01380000 ################################################################
10211 16:30:53.321584
10212 16:30:53.577138 01400000 ################################################################
10213 16:30:53.577267
10214 16:30:53.829309 01480000 ################################################################
10215 16:30:53.829433
10216 16:30:54.088888 01500000 ################################################################
10217 16:30:54.089038
10218 16:30:54.339163 01580000 ################################################################
10219 16:30:54.339302
10220 16:30:54.599712 01600000 ################################################################
10221 16:30:54.599903
10222 16:30:54.862607 01680000 ################################################################
10223 16:30:54.862735
10224 16:30:55.114751 01700000 ################################################################
10225 16:30:55.114865
10226 16:30:55.371554 01780000 ################################################################
10227 16:30:55.371674
10228 16:30:55.635419 01800000 ################################################################
10229 16:30:55.635540
10230 16:30:55.890118 01880000 ################################################################
10231 16:30:55.890310
10232 16:30:56.149239 01900000 ################################################################
10233 16:30:56.149361
10234 16:30:56.413797 01980000 ################################################################
10235 16:30:56.413923
10236 16:30:56.668307 01a00000 ################################################################
10237 16:30:56.668421
10238 16:30:56.920645 01a80000 ################################################################
10239 16:30:56.920764
10240 16:30:57.178637 01b00000 ################################################################
10241 16:30:57.178761
10242 16:30:57.431235 01b80000 ################################################################
10243 16:30:57.431352
10244 16:30:57.684143 01c00000 ################################################################
10245 16:30:57.684287
10246 16:30:57.940943 01c80000 ################################################################
10247 16:30:57.941086
10248 16:30:58.195592 01d00000 ################################################################
10249 16:30:58.195727
10250 16:30:58.454691 01d80000 ################################################################
10251 16:30:58.454819
10252 16:30:58.684880 01e00000 ######################################################### done.
10253 16:30:58.685028
10254 16:30:58.688352 The bootfile was 31923582 bytes long.
10255 16:30:58.688457
10256 16:30:58.692001 Sending tftp read request... done.
10257 16:30:58.692082
10258 16:30:58.692142 Waiting for the transfer...
10259 16:30:58.692235
10260 16:30:58.694965 00000000 # done.
10261 16:30:58.695044
10262 16:30:58.702185 Command line loaded dynamically from TFTP file: 14396104/tftp-deploy-sqzd0v25/kernel/cmdline
10263 16:30:58.702264
10264 16:30:58.724934 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10265 16:30:58.725048
10266 16:30:58.725118 Loading FIT.
10267 16:30:58.725174
10268 16:30:58.728563 Image ramdisk-1 has 18745541 bytes.
10269 16:30:58.728640
10270 16:30:58.731434 Image fdt-1 has 47258 bytes.
10271 16:30:58.731510
10272 16:30:58.734637 Image kernel-1 has 13128753 bytes.
10273 16:30:58.734737
10274 16:30:58.744728 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10275 16:30:58.744809
10276 16:30:58.761119 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10277 16:30:58.761202
10278 16:30:58.767710 Choosing best match conf-1 for compat google,spherion-rev2.
10279 16:30:58.767792
10280 16:30:58.775571 Connected to device vid:did:rid of 1ae0:0028:00
10281 16:30:58.783915
10282 16:30:58.787236 tpm_get_response: command 0x17b, return code 0x0
10283 16:30:58.787313
10284 16:30:58.790128 ec_init: CrosEC protocol v3 supported (256, 248)
10285 16:30:58.794203
10286 16:30:58.797929 tpm_cleanup: add release locality here.
10287 16:30:58.798006
10288 16:30:58.798064 Shutting down all USB controllers.
10289 16:30:58.798119
10290 16:30:58.800840 Removing current net device
10291 16:30:58.800915
10292 16:30:58.807477 Exiting depthcharge with code 4 at timestamp: 51126156
10293 16:30:58.807554
10294 16:30:58.811194 LZMA decompressing kernel-1 to 0x821a6718
10295 16:30:58.811270
10296 16:30:58.814087 LZMA decompressing kernel-1 to 0x40000000
10297 16:31:00.430920
10298 16:31:00.431033 jumping to kernel
10299 16:31:00.431478 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10300 16:31:00.431571 start: 2.2.5 auto-login-action (timeout 00:03:57) [common]
10301 16:31:00.431641 Setting prompt string to ['Linux version [0-9]']
10302 16:31:00.431703 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10303 16:31:00.431766 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10304 16:31:00.513225
10305 16:31:00.516060 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10306 16:31:00.519889 start: 2.2.5.1 login-action (timeout 00:03:57) [common]
10307 16:31:00.519985 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10308 16:31:00.520053 Setting prompt string to []
10309 16:31:00.520125 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10310 16:31:00.520191 Using line separator: #'\n'#
10311 16:31:00.520246 No login prompt set.
10312 16:31:00.520304 Parsing kernel messages
10313 16:31:00.520355 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10314 16:31:00.520507 [login-action] Waiting for messages, (timeout 00:03:57)
10315 16:31:00.520574 Waiting using forced prompt support (timeout 00:01:58)
10316 16:31:00.539558 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10317 16:31:00.542488 [ 0.000000] random: crng init done
10318 16:31:00.549557 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10319 16:31:00.553034 [ 0.000000] efi: UEFI not found.
10320 16:31:00.559593 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10321 16:31:00.565878 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10322 16:31:00.576329 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10323 16:31:00.586392 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10324 16:31:00.593066 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10325 16:31:00.596215 [ 0.000000] printk: bootconsole [mtk8250] enabled
10326 16:31:00.604997 [ 0.000000] NUMA: No NUMA configuration found
10327 16:31:00.611511 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10328 16:31:00.617956 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10329 16:31:00.618032 [ 0.000000] Zone ranges:
10330 16:31:00.624408 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10331 16:31:00.627941 [ 0.000000] DMA32 empty
10332 16:31:00.634941 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10333 16:31:00.638314 [ 0.000000] Movable zone start for each node
10334 16:31:00.641141 [ 0.000000] Early memory node ranges
10335 16:31:00.647669 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10336 16:31:00.654895 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10337 16:31:00.661085 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10338 16:31:00.668102 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10339 16:31:00.674266 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10340 16:31:00.681196 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10341 16:31:00.737251 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10342 16:31:00.744035 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10343 16:31:00.751226 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10344 16:31:00.753946 [ 0.000000] psci: probing for conduit method from DT.
10345 16:31:00.760403 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10346 16:31:00.763972 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10347 16:31:00.770347 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10348 16:31:00.773756 [ 0.000000] psci: SMC Calling Convention v1.2
10349 16:31:00.780838 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10350 16:31:00.783682 [ 0.000000] Detected VIPT I-cache on CPU0
10351 16:31:00.790765 [ 0.000000] CPU features: detected: GIC system register CPU interface
10352 16:31:00.797359 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10353 16:31:00.803842 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10354 16:31:00.810608 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10355 16:31:00.817107 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10356 16:31:00.827199 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10357 16:31:00.830333 [ 0.000000] alternatives: applying boot alternatives
10358 16:31:00.837047 [ 0.000000] Fallback order for Node 0: 0
10359 16:31:00.843560 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10360 16:31:00.847028 [ 0.000000] Policy zone: Normal
10361 16:31:00.869763 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10362 16:31:00.879915 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10363 16:31:00.889856 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10364 16:31:00.899933 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10365 16:31:00.906512 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10366 16:31:00.909979 <6>[ 0.000000] software IO TLB: area num 8.
10367 16:31:00.966363 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10368 16:31:01.115608 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10369 16:31:01.121783 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10370 16:31:01.128286 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10371 16:31:01.131963 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10372 16:31:01.138316 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10373 16:31:01.145391 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10374 16:31:01.149003 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10375 16:31:01.158305 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10376 16:31:01.165097 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10377 16:31:01.168473 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10378 16:31:01.176214 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10379 16:31:01.179594 <6>[ 0.000000] GICv3: 608 SPIs implemented
10380 16:31:01.186320 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10381 16:31:01.189515 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10382 16:31:01.192762 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10383 16:31:01.202987 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10384 16:31:01.212781 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10385 16:31:01.226545 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10386 16:31:01.232991 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10387 16:31:01.242024 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10388 16:31:01.254845 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10389 16:31:01.261315 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10390 16:31:01.268533 <6>[ 0.009237] Console: colour dummy device 80x25
10391 16:31:01.277915 <6>[ 0.013967] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10392 16:31:01.284511 <6>[ 0.024474] pid_max: default: 32768 minimum: 301
10393 16:31:01.288075 <6>[ 0.029375] LSM: Security Framework initializing
10394 16:31:01.294474 <6>[ 0.034314] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 16:31:01.304776 <6>[ 0.042127] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 16:31:01.311675 <6>[ 0.051597] cblist_init_generic: Setting adjustable number of callback queues.
10397 16:31:01.318322 <6>[ 0.059043] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 16:31:01.327707 <6>[ 0.065383] cblist_init_generic: Setting adjustable number of callback queues.
10399 16:31:01.334291 <6>[ 0.072809] cblist_init_generic: Setting shift to 3 and lim to 1.
10400 16:31:01.337805 <6>[ 0.079246] rcu: Hierarchical SRCU implementation.
10401 16:31:01.344717 <6>[ 0.084292] rcu: Max phase no-delay instances is 1000.
10402 16:31:01.351179 <6>[ 0.091356] EFI services will not be available.
10403 16:31:01.354792 <6>[ 0.096312] smp: Bringing up secondary CPUs ...
10404 16:31:01.362795 <6>[ 0.101391] Detected VIPT I-cache on CPU1
10405 16:31:01.369291 <6>[ 0.101464] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10406 16:31:01.375956 <6>[ 0.101493] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10407 16:31:01.379308 <6>[ 0.101835] Detected VIPT I-cache on CPU2
10408 16:31:01.386319 <6>[ 0.101890] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10409 16:31:01.392713 <6>[ 0.101908] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10410 16:31:01.399522 <6>[ 0.102166] Detected VIPT I-cache on CPU3
10411 16:31:01.405984 <6>[ 0.102213] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10412 16:31:01.412267 <6>[ 0.102228] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10413 16:31:01.415720 <6>[ 0.102530] CPU features: detected: Spectre-v4
10414 16:31:01.422161 <6>[ 0.102536] CPU features: detected: Spectre-BHB
10415 16:31:01.425723 <6>[ 0.102542] Detected PIPT I-cache on CPU4
10416 16:31:01.432108 <6>[ 0.102600] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10417 16:31:01.439231 <6>[ 0.102616] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10418 16:31:01.445872 <6>[ 0.102909] Detected PIPT I-cache on CPU5
10419 16:31:01.452627 <6>[ 0.102972] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10420 16:31:01.459045 <6>[ 0.102988] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10421 16:31:01.462235 <6>[ 0.103269] Detected PIPT I-cache on CPU6
10422 16:31:01.468913 <6>[ 0.103334] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10423 16:31:01.475971 <6>[ 0.103350] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10424 16:31:01.478799 <6>[ 0.103644] Detected PIPT I-cache on CPU7
10425 16:31:01.489037 <6>[ 0.103709] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10426 16:31:01.495532 <6>[ 0.103725] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10427 16:31:01.499139 <6>[ 0.103772] smp: Brought up 1 node, 8 CPUs
10428 16:31:01.502685 <6>[ 0.245008] SMP: Total of 8 processors activated.
10429 16:31:01.508758 <6>[ 0.249959] CPU features: detected: 32-bit EL0 Support
10430 16:31:01.518726 <6>[ 0.255323] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10431 16:31:01.525473 <6>[ 0.264123] CPU features: detected: Common not Private translations
10432 16:31:01.528962 <6>[ 0.270599] CPU features: detected: CRC32 instructions
10433 16:31:01.535563 <6>[ 0.275951] CPU features: detected: RCpc load-acquire (LDAPR)
10434 16:31:01.541895 <6>[ 0.281947] CPU features: detected: LSE atomic instructions
10435 16:31:01.548984 <6>[ 0.287729] CPU features: detected: Privileged Access Never
10436 16:31:01.551805 <6>[ 0.293509] CPU features: detected: RAS Extension Support
10437 16:31:01.558926 <6>[ 0.299118] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10438 16:31:01.565031 <6>[ 0.306341] CPU: All CPU(s) started at EL2
10439 16:31:01.571721 <6>[ 0.310657] alternatives: applying system-wide alternatives
10440 16:31:01.580592 <6>[ 0.321542] devtmpfs: initialized
10441 16:31:01.595634 <6>[ 0.330367] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10442 16:31:01.602792 <6>[ 0.340329] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10443 16:31:01.609324 <6>[ 0.348356] pinctrl core: initialized pinctrl subsystem
10444 16:31:01.612912 <6>[ 0.355040] DMI not present or invalid.
10445 16:31:01.619282 <6>[ 0.359455] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10446 16:31:01.628916 <6>[ 0.366323] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10447 16:31:01.635330 <6>[ 0.373914] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10448 16:31:01.645611 <6>[ 0.382136] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10449 16:31:01.649001 <6>[ 0.390380] audit: initializing netlink subsys (disabled)
10450 16:31:01.659158 <5>[ 0.396074] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10451 16:31:01.665740 <6>[ 0.396758] thermal_sys: Registered thermal governor 'step_wise'
10452 16:31:01.672168 <6>[ 0.404042] thermal_sys: Registered thermal governor 'power_allocator'
10453 16:31:01.675099 <6>[ 0.410299] cpuidle: using governor menu
10454 16:31:01.682163 <6>[ 0.421261] NET: Registered PF_QIPCRTR protocol family
10455 16:31:01.688708 <6>[ 0.426752] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10456 16:31:01.691639 <6>[ 0.433858] ASID allocator initialised with 32768 entries
10457 16:31:01.699259 <6>[ 0.440440] Serial: AMBA PL011 UART driver
10458 16:31:01.708438 <4>[ 0.449265] Trying to register duplicate clock ID: 134
10459 16:31:01.766429 <6>[ 0.510786] KASLR enabled
10460 16:31:01.780708 <6>[ 0.518480] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10461 16:31:01.787122 <6>[ 0.525493] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10462 16:31:01.794220 <6>[ 0.531983] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10463 16:31:01.800787 <6>[ 0.538990] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10464 16:31:01.807052 <6>[ 0.545478] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10465 16:31:01.813966 <6>[ 0.552486] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10466 16:31:01.820190 <6>[ 0.558974] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10467 16:31:01.826713 <6>[ 0.565980] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10468 16:31:01.830182 <6>[ 0.573515] ACPI: Interpreter disabled.
10469 16:31:01.838659 <6>[ 0.579957] iommu: Default domain type: Translated
10470 16:31:01.845558 <6>[ 0.585067] iommu: DMA domain TLB invalidation policy: strict mode
10471 16:31:01.848788 <5>[ 0.591727] SCSI subsystem initialized
10472 16:31:01.855458 <6>[ 0.595890] usbcore: registered new interface driver usbfs
10473 16:31:01.861991 <6>[ 0.601622] usbcore: registered new interface driver hub
10474 16:31:01.865335 <6>[ 0.607175] usbcore: registered new device driver usb
10475 16:31:01.872021 <6>[ 0.613275] pps_core: LinuxPPS API ver. 1 registered
10476 16:31:01.882078 <6>[ 0.618469] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10477 16:31:01.885680 <6>[ 0.627815] PTP clock support registered
10478 16:31:01.888601 <6>[ 0.632060] EDAC MC: Ver: 3.0.0
10479 16:31:01.896287 <6>[ 0.637208] FPGA manager framework
10480 16:31:01.899843 <6>[ 0.640893] Advanced Linux Sound Architecture Driver Initialized.
10481 16:31:01.903471 <6>[ 0.647661] vgaarb: loaded
10482 16:31:01.909874 <6>[ 0.650813] clocksource: Switched to clocksource arch_sys_counter
10483 16:31:01.916202 <5>[ 0.657254] VFS: Disk quotas dquot_6.6.0
10484 16:31:01.923020 <6>[ 0.661440] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10485 16:31:01.926479 <6>[ 0.668632] pnp: PnP ACPI: disabled
10486 16:31:01.934323 <6>[ 0.675360] NET: Registered PF_INET protocol family
10487 16:31:01.940798 <6>[ 0.680953] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10488 16:31:01.955807 <6>[ 0.693275] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10489 16:31:01.965823 <6>[ 0.702087] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10490 16:31:01.972403 <6>[ 0.710057] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10491 16:31:01.978906 <6>[ 0.718759] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10492 16:31:01.990442 <6>[ 0.728517] TCP: Hash tables configured (established 65536 bind 65536)
10493 16:31:01.997634 <6>[ 0.735382] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 16:31:02.004181 <6>[ 0.742583] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10495 16:31:02.010738 <6>[ 0.750289] NET: Registered PF_UNIX/PF_LOCAL protocol family
10496 16:31:02.017223 <6>[ 0.756453] RPC: Registered named UNIX socket transport module.
10497 16:31:02.020634 <6>[ 0.762608] RPC: Registered udp transport module.
10498 16:31:02.026965 <6>[ 0.767541] RPC: Registered tcp transport module.
10499 16:31:02.033842 <6>[ 0.772473] RPC: Registered tcp NFSv4.1 backchannel transport module.
10500 16:31:02.037205 <6>[ 0.779137] PCI: CLS 0 bytes, default 64
10501 16:31:02.040715 <6>[ 0.783472] Unpacking initramfs...
10502 16:31:02.065406 <6>[ 0.802904] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10503 16:31:02.074627 <6>[ 0.811557] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10504 16:31:02.077963 <6>[ 0.820397] kvm [1]: IPA Size Limit: 40 bits
10505 16:31:02.084702 <6>[ 0.824923] kvm [1]: GICv3: no GICV resource entry
10506 16:31:02.088070 <6>[ 0.829943] kvm [1]: disabling GICv2 emulation
10507 16:31:02.094940 <6>[ 0.834629] kvm [1]: GIC system register CPU interface enabled
10508 16:31:02.098382 <6>[ 0.840788] kvm [1]: vgic interrupt IRQ18
10509 16:31:02.104814 <6>[ 0.845141] kvm [1]: VHE mode initialized successfully
10510 16:31:02.111611 <5>[ 0.851539] Initialise system trusted keyrings
10511 16:31:02.117950 <6>[ 0.856390] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10512 16:31:02.124984 <6>[ 0.866365] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10513 16:31:02.132098 <5>[ 0.872798] NFS: Registering the id_resolver key type
10514 16:31:02.135170 <5>[ 0.878093] Key type id_resolver registered
10515 16:31:02.141858 <5>[ 0.882510] Key type id_legacy registered
10516 16:31:02.148365 <6>[ 0.886789] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10517 16:31:02.154830 <6>[ 0.893708] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10518 16:31:02.162030 <6>[ 0.901422] 9p: Installing v9fs 9p2000 file system support
10519 16:31:02.198486 <5>[ 0.939939] Key type asymmetric registered
10520 16:31:02.202048 <5>[ 0.944283] Asymmetric key parser 'x509' registered
10521 16:31:02.212117 <6>[ 0.949431] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10522 16:31:02.215455 <6>[ 0.957045] io scheduler mq-deadline registered
10523 16:31:02.218919 <6>[ 0.961806] io scheduler kyber registered
10524 16:31:02.237019 <6>[ 0.978472] EINJ: ACPI disabled.
10525 16:31:02.269457 <4>[ 1.004232] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 16:31:02.279666 <4>[ 1.014867] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 16:31:02.295220 <6>[ 1.035874] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10528 16:31:02.302359 <6>[ 1.043813] printk: console [ttyS0] disabled
10529 16:31:02.330518 <6>[ 1.068438] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10530 16:31:02.337408 <6>[ 1.077910] printk: console [ttyS0] enabled
10531 16:31:02.340360 <6>[ 1.077910] printk: console [ttyS0] enabled
10532 16:31:02.347359 <6>[ 1.086805] printk: bootconsole [mtk8250] disabled
10533 16:31:02.350913 <6>[ 1.086805] printk: bootconsole [mtk8250] disabled
10534 16:31:02.357385 <6>[ 1.097811] SuperH (H)SCI(F) driver initialized
10535 16:31:02.360265 <6>[ 1.103091] msm_serial: driver initialized
10536 16:31:02.374076 <6>[ 1.111983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10537 16:31:02.384036 <6>[ 1.120532] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10538 16:31:02.390498 <6>[ 1.129074] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10539 16:31:02.401035 <6>[ 1.137701] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10540 16:31:02.407342 <6>[ 1.146407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10541 16:31:02.417099 <6>[ 1.155121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10542 16:31:02.427063 <6>[ 1.163660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10543 16:31:02.433960 <6>[ 1.172452] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10544 16:31:02.443974 <6>[ 1.180992] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10545 16:31:02.454955 <6>[ 1.196450] loop: module loaded
10546 16:31:02.461656 <6>[ 1.202231] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10547 16:31:02.484048 <4>[ 1.225528] mtk-pmic-keys: Failed to locate of_node [id: -1]
10548 16:31:02.491322 <6>[ 1.232318] megasas: 07.719.03.00-rc1
10549 16:31:02.501194 <6>[ 1.242085] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10550 16:31:02.508855 <6>[ 1.250191] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10551 16:31:02.525464 <6>[ 1.266733] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10552 16:31:02.582135 <6>[ 1.316573] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10553 16:31:02.833982 <6>[ 1.575334] Freeing initrd memory: 18304K
10554 16:31:02.845737 <6>[ 1.587096] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10555 16:31:02.857100 <6>[ 1.598238] tun: Universal TUN/TAP device driver, 1.6
10556 16:31:02.860578 <6>[ 1.604320] thunder_xcv, ver 1.0
10557 16:31:02.864152 <6>[ 1.607826] thunder_bgx, ver 1.0
10558 16:31:02.867123 <6>[ 1.611322] nicpf, ver 1.0
10559 16:31:02.877772 <6>[ 1.615351] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10560 16:31:02.880575 <6>[ 1.622828] hns3: Copyright (c) 2017 Huawei Corporation.
10561 16:31:02.884061 <6>[ 1.628416] hclge is initializing
10562 16:31:02.891130 <6>[ 1.631996] e1000: Intel(R) PRO/1000 Network Driver
10563 16:31:02.897432 <6>[ 1.637125] e1000: Copyright (c) 1999-2006 Intel Corporation.
10564 16:31:02.900991 <6>[ 1.643139] e1000e: Intel(R) PRO/1000 Network Driver
10565 16:31:02.907468 <6>[ 1.648355] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10566 16:31:02.913940 <6>[ 1.654542] igb: Intel(R) Gigabit Ethernet Network Driver
10567 16:31:02.920880 <6>[ 1.660192] igb: Copyright (c) 2007-2014 Intel Corporation.
10568 16:31:02.927670 <6>[ 1.666030] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10569 16:31:02.930721 <6>[ 1.672547] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10570 16:31:02.937680 <6>[ 1.679010] sky2: driver version 1.30
10571 16:31:02.944733 <6>[ 1.683942] usbcore: registered new device driver r8152-cfgselector
10572 16:31:02.951250 <6>[ 1.690476] usbcore: registered new interface driver r8152
10573 16:31:02.954189 <6>[ 1.696291] VFIO - User Level meta-driver version: 0.3
10574 16:31:02.963418 <6>[ 1.704555] usbcore: registered new interface driver usb-storage
10575 16:31:02.970041 <6>[ 1.710999] usbcore: registered new device driver onboard-usb-hub
10576 16:31:02.979257 <6>[ 1.720177] mt6397-rtc mt6359-rtc: registered as rtc0
10577 16:31:02.989287 <6>[ 1.725644] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:31:02 UTC (1718641862)
10578 16:31:02.992131 <6>[ 1.735214] i2c_dev: i2c /dev entries driver
10579 16:31:03.006101 <4>[ 1.747319] cpu cpu0: supply cpu not found, using dummy regulator
10580 16:31:03.012556 <4>[ 1.753736] cpu cpu1: supply cpu not found, using dummy regulator
10581 16:31:03.019732 <4>[ 1.760144] cpu cpu2: supply cpu not found, using dummy regulator
10582 16:31:03.026184 <4>[ 1.766542] cpu cpu3: supply cpu not found, using dummy regulator
10583 16:31:03.033106 <4>[ 1.772958] cpu cpu4: supply cpu not found, using dummy regulator
10584 16:31:03.039699 <4>[ 1.779352] cpu cpu5: supply cpu not found, using dummy regulator
10585 16:31:03.046530 <4>[ 1.785752] cpu cpu6: supply cpu not found, using dummy regulator
10586 16:31:03.053269 <4>[ 1.792149] cpu cpu7: supply cpu not found, using dummy regulator
10587 16:31:03.071865 <6>[ 1.812776] cpu cpu0: EM: created perf domain
10588 16:31:03.074774 <6>[ 1.817710] cpu cpu4: EM: created perf domain
10589 16:31:03.081796 <6>[ 1.823313] sdhci: Secure Digital Host Controller Interface driver
10590 16:31:03.088890 <6>[ 1.829745] sdhci: Copyright(c) Pierre Ossman
10591 16:31:03.095249 <6>[ 1.834699] Synopsys Designware Multimedia Card Interface Driver
10592 16:31:03.102326 <6>[ 1.841332] sdhci-pltfm: SDHCI platform and OF driver helper
10593 16:31:03.105723 <6>[ 1.841481] mmc0: CQHCI version 5.10
10594 16:31:03.111865 <6>[ 1.851414] ledtrig-cpu: registered to indicate activity on CPUs
10595 16:31:03.118550 <6>[ 1.858411] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10596 16:31:03.125896 <6>[ 1.865463] usbcore: registered new interface driver usbhid
10597 16:31:03.128647 <6>[ 1.871284] usbhid: USB HID core driver
10598 16:31:03.135144 <6>[ 1.875500] spi_master spi0: will run message pump with realtime priority
10599 16:31:03.178913 <6>[ 1.913224] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10600 16:31:03.194304 <6>[ 1.928574] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10601 16:31:03.200650 <6>[ 1.941094] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10602 16:31:03.207738 <6>[ 1.948932] cros-ec-spi spi0.0: Chrome EC device registered
10603 16:31:03.214655 <6>[ 1.954919] mmc0: Command Queue Engine enabled
10604 16:31:03.221686 <6>[ 1.959684] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10605 16:31:03.224438 <6>[ 1.967364] mmcblk0: mmc0:0001 DA4128 116 GiB
10606 16:31:03.235349 <6>[ 1.976382] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10607 16:31:03.242627 <6>[ 1.983795] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10608 16:31:03.249601 <6>[ 1.989990] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10609 16:31:03.259043 <6>[ 1.995994] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10610 16:31:03.266254 <6>[ 1.996257] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10611 16:31:03.269154 <6>[ 2.006610] NET: Registered PF_PACKET protocol family
10612 16:31:03.276306 <6>[ 2.017220] 9pnet: Installing 9P2000 support
10613 16:31:03.279090 <5>[ 2.021781] Key type dns_resolver registered
10614 16:31:03.286312 <6>[ 2.026767] registered taskstats version 1
10615 16:31:03.289409 <5>[ 2.031154] Loading compiled-in X.509 certificates
10616 16:31:03.320616 <4>[ 2.054882] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 16:31:03.330670 <4>[ 2.065773] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 16:31:03.345417 <6>[ 2.086467] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10619 16:31:03.352592 <6>[ 2.093432] xhci-mtk 11200000.usb: xHCI Host Controller
10620 16:31:03.358984 <6>[ 2.098940] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10621 16:31:03.369203 <6>[ 2.106794] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10622 16:31:03.375683 <6>[ 2.116214] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10623 16:31:03.382047 <6>[ 2.122302] xhci-mtk 11200000.usb: xHCI Host Controller
10624 16:31:03.389069 <6>[ 2.127781] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10625 16:31:03.395519 <6>[ 2.135429] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10626 16:31:03.402153 <6>[ 2.143057] hub 1-0:1.0: USB hub found
10627 16:31:03.405119 <6>[ 2.147069] hub 1-0:1.0: 1 port detected
10628 16:31:03.412175 <6>[ 2.151348] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10629 16:31:03.418475 <6>[ 2.159874] hub 2-0:1.0: USB hub found
10630 16:31:03.421977 <6>[ 2.163882] hub 2-0:1.0: 1 port detected
10631 16:31:03.430004 <6>[ 2.171035] mtk-msdc 11f70000.mmc: Got CD GPIO
10632 16:31:03.447128 <6>[ 2.184806] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10633 16:31:03.456604 <6>[ 2.193330] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10634 16:31:03.463871 <6>[ 2.201675] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10635 16:31:03.473841 <6>[ 2.210031] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10636 16:31:03.480396 <6>[ 2.218372] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10637 16:31:03.490017 <6>[ 2.226726] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10638 16:31:03.497157 <6>[ 2.235064] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10639 16:31:03.506638 <6>[ 2.243413] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10640 16:31:03.513817 <6>[ 2.251752] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10641 16:31:03.523790 <6>[ 2.260102] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10642 16:31:03.530207 <6>[ 2.268440] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10643 16:31:03.540304 <6>[ 2.276794] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10644 16:31:03.547010 <6>[ 2.285133] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10645 16:31:03.556570 <6>[ 2.293484] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10646 16:31:03.563445 <6>[ 2.301822] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10647 16:31:03.570123 <6>[ 2.310532] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10648 16:31:03.576617 <6>[ 2.317688] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10649 16:31:03.583050 <6>[ 2.324481] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10650 16:31:03.589911 <6>[ 2.331252] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10651 16:31:03.600020 <6>[ 2.338189] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10652 16:31:03.607167 <6>[ 2.345039] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10653 16:31:03.616527 <6>[ 2.354169] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10654 16:31:03.626553 <6>[ 2.363288] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10655 16:31:03.636269 <6>[ 2.372583] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10656 16:31:03.646299 <6>[ 2.382050] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10657 16:31:03.653026 <6>[ 2.391517] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10658 16:31:03.663352 <6>[ 2.400637] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10659 16:31:03.672831 <6>[ 2.410104] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10660 16:31:03.682714 <6>[ 2.419223] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10661 16:31:03.692733 <6>[ 2.428522] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10662 16:31:03.703063 <6>[ 2.438710] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10663 16:31:03.712515 <6>[ 2.450258] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10664 16:31:03.720123 <6>[ 2.461420] Trying to probe devices needed for running init ...
10665 16:31:03.730361 <3>[ 2.468671] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10666 16:31:03.837117 <6>[ 2.575035] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 16:31:03.991736 <6>[ 2.733200] hub 1-1:1.0: USB hub found
10668 16:31:03.995289 <6>[ 2.737769] hub 1-1:1.0: 4 ports detected
10669 16:31:04.007452 <6>[ 2.748658] hub 1-1:1.0: USB hub found
10670 16:31:04.010970 <6>[ 2.753111] hub 1-1:1.0: 4 ports detected
10671 16:31:04.116998 <6>[ 2.855277] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10672 16:31:04.142990 <6>[ 2.884027] hub 2-1:1.0: USB hub found
10673 16:31:04.145831 <6>[ 2.888463] hub 2-1:1.0: 3 ports detected
10674 16:31:04.156510 <6>[ 2.898111] hub 2-1:1.0: USB hub found
10675 16:31:04.160148 <6>[ 2.902450] hub 2-1:1.0: 3 ports detected
10676 16:31:04.332614 <6>[ 3.071133] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10677 16:31:04.465709 <6>[ 3.207016] hub 1-1.4:1.0: USB hub found
10678 16:31:04.469125 <6>[ 3.211687] hub 1-1.4:1.0: 2 ports detected
10679 16:31:04.481291 <6>[ 3.222898] hub 1-1.4:1.0: USB hub found
10680 16:31:04.484900 <6>[ 3.227471] hub 1-1.4:1.0: 2 ports detected
10681 16:31:04.544987 <6>[ 3.283352] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10682 16:31:04.653565 <6>[ 3.391783] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10683 16:31:04.688833 <4>[ 3.427157] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10684 16:31:04.698726 <4>[ 3.436249] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10685 16:31:04.739003 <6>[ 3.480639] r8152 2-1.3:1.0 eth0: v1.12.13
10686 16:31:04.780957 <6>[ 3.518938] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10687 16:31:04.976695 <6>[ 3.714970] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10688 16:31:06.365936 <6>[ 5.107640] r8152 2-1.3:1.0 eth0: carrier on
10689 16:31:08.633297 <5>[ 5.134963] Sending DHCP requests .., OK
10690 16:31:08.639494 <6>[ 7.379284] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10691 16:31:08.642916 <6>[ 7.387574] IP-Config: Complete:
10692 16:31:08.653419 <6>[ 7.391073] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10693 16:31:08.663103 <6>[ 7.401783] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10694 16:31:08.670165 <6>[ 7.410398] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10695 16:31:08.676482 <6>[ 7.410408] nameserver0=192.168.201.1
10696 16:31:08.680201 <6>[ 7.422550] clk: Disabling unused clocks
10697 16:31:08.683170 <6>[ 7.428066] ALSA device list:
10698 16:31:08.686779 <6>[ 7.431316] No soundcards found.
10699 16:31:08.697458 <6>[ 7.439134] Freeing unused kernel memory: 8512K
10700 16:31:08.700295 <6>[ 7.444131] Run /init as init process
10701 16:31:08.710659 Loading, please wait...
10702 16:31:08.737111 Starting systemd-udevd version 252.22-1~deb12u1
10703 16:31:08.994696 <6>[ 7.733421] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10704 16:31:09.004808 <6>[ 7.742316] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10705 16:31:09.011871 <6>[ 7.743993] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10706 16:31:09.021248 <6>[ 7.751033] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10707 16:31:09.042350 <6>[ 7.780766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10708 16:31:09.048592 <6>[ 7.785437] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10709 16:31:09.058941 <6>[ 7.788846] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10710 16:31:09.062480 <6>[ 7.800670] remoteproc remoteproc0: scp is available
10711 16:31:09.068842 <4>[ 7.802994] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10712 16:31:09.078897 <4>[ 7.804319] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10713 16:31:09.085252 <4>[ 7.804712] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10714 16:31:09.095122 <6>[ 7.805436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10715 16:31:09.101687 <6>[ 7.805443] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10716 16:31:09.108482 <6>[ 7.809715] remoteproc remoteproc0: powering up scp
10717 16:31:09.115178 <3>[ 7.815442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 16:31:09.125093 <3>[ 7.815455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 16:31:09.131688 <3>[ 7.815459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 16:31:09.141070 <6>[ 7.816633] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10721 16:31:09.148240 <6>[ 7.816663] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10722 16:31:09.154397 <6>[ 7.816667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10723 16:31:09.164702 <6>[ 7.816674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10724 16:31:09.174476 <3>[ 7.827830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 16:31:09.180655 <6>[ 7.833391] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10726 16:31:09.191228 <3>[ 7.841632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 16:31:09.194106 <6>[ 7.849341] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10728 16:31:09.200550 <6>[ 7.888726] mc: Linux media interface: v0.10
10729 16:31:09.207505 <3>[ 7.894754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 16:31:09.214297 <6>[ 7.896553] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10731 16:31:09.221081 <6>[ 7.896569] pci_bus 0000:00: root bus resource [bus 00-ff]
10732 16:31:09.227350 <6>[ 7.896576] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10733 16:31:09.237504 <6>[ 7.896580] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10734 16:31:09.244044 <6>[ 7.896621] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10735 16:31:09.250788 <6>[ 7.896635] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10736 16:31:09.257238 <6>[ 7.896709] pci 0000:00:00.0: supports D1 D2
10737 16:31:09.263797 <6>[ 7.896711] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10738 16:31:09.270514 <6>[ 7.907114] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10739 16:31:09.277408 <6>[ 7.909350] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10740 16:31:09.284003 <6>[ 7.909514] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10741 16:31:09.293572 <6>[ 7.909543] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10742 16:31:09.300619 <6>[ 7.909563] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10743 16:31:09.307253 <6>[ 7.909579] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10744 16:31:09.313529 <6>[ 7.909700] pci 0000:01:00.0: supports D1 D2
10745 16:31:09.320717 <6>[ 7.909703] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10746 16:31:09.327551 <3>[ 7.911731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 16:31:09.334701 <6>[ 7.919917] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10748 16:31:09.344541 <6>[ 7.926055] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10749 16:31:09.350816 <3>[ 7.928250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 16:31:09.357957 <6>[ 7.936409] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10751 16:31:09.367833 <3>[ 7.942018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 16:31:09.374913 <6>[ 7.946572] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10753 16:31:09.384203 <3>[ 7.954714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 16:31:09.394849 <6>[ 7.960163] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10755 16:31:09.401103 <6>[ 7.960534] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10756 16:31:09.411558 <6>[ 7.962464] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10757 16:31:09.418076 <3>[ 7.967262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 16:31:09.427471 <3>[ 7.967270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 16:31:09.434561 <6>[ 7.974601] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10760 16:31:09.440789 <6>[ 7.975218] videodev: Linux video capture interface: v2.00
10761 16:31:09.447900 <6>[ 7.975250] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10762 16:31:09.457551 <6>[ 7.984340] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10763 16:31:09.464397 <4>[ 7.984356] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10764 16:31:09.470983 <4>[ 7.984356] Fallback method does not support PEC.
10765 16:31:09.477356 <6>[ 7.984361] remoteproc remoteproc0: remote processor scp is now up
10766 16:31:09.483916 <3>[ 7.984582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 16:31:09.493980 <3>[ 7.984591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 16:31:09.500969 <3>[ 7.984594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 16:31:09.507448 <3>[ 7.984605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 16:31:09.516833 <3>[ 7.984610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 16:31:09.523583 <3>[ 7.984662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 16:31:09.527190 <6>[ 7.985520] Bluetooth: Core ver 2.22
10773 16:31:09.533611 <6>[ 7.985574] NET: Registered PF_BLUETOOTH protocol family
10774 16:31:09.540703 <6>[ 7.985576] Bluetooth: HCI device and connection manager initialized
10775 16:31:09.546906 <6>[ 7.985643] Bluetooth: HCI socket layer initialized
10776 16:31:09.550459 <6>[ 7.985649] Bluetooth: L2CAP socket layer initialized
10777 16:31:09.556869 <6>[ 7.985661] Bluetooth: SCO socket layer initialized
10778 16:31:09.563788 <6>[ 7.991017] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10779 16:31:09.573528 <6>[ 7.992269] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10780 16:31:09.580208 <6>[ 7.994530] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10781 16:31:09.587283 <6>[ 8.027163] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10782 16:31:09.593815 <6>[ 8.031950] pci 0000:00:00.0: PCI bridge to [bus 01]
10783 16:31:09.606872 <6>[ 8.040793] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10784 16:31:09.613143 <6>[ 8.046902] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10785 16:31:09.619633 <6>[ 8.047159] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 16:31:09.626337 <6>[ 8.047739] usbcore: registered new interface driver btusb
10787 16:31:09.633044 <6>[ 8.047885] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10788 16:31:09.636589 <6>[ 8.054785] usbcore: registered new interface driver uvcvideo
10789 16:31:09.650071 <4>[ 8.054822] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10790 16:31:09.652706 <3>[ 8.054832] Bluetooth: hci0: Failed to load firmware file (-2)
10791 16:31:09.659840 <3>[ 8.054834] Bluetooth: hci0: Failed to set up firmware (-2)
10792 16:31:09.669390 <4>[ 8.054837] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10793 16:31:09.676267 <6>[ 8.059442] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10794 16:31:09.686030 <3>[ 8.072386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10795 16:31:09.692490 <6>[ 8.074206] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10796 16:31:09.699623 <3>[ 8.101928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10797 16:31:09.709440 <5>[ 8.126911] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10798 16:31:09.729035 <5>[ 8.467531] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10799 16:31:09.735376 <5>[ 8.474686] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10800 16:31:09.745617 <4>[ 8.483108] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10801 16:31:09.748591 <6>[ 8.491988] cfg80211: failed to load regulatory.db
10802 16:31:09.790932 <6>[ 8.529915] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10803 16:31:09.797725 <6>[ 8.537417] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10804 16:31:09.822046 <6>[ 8.564052] mt7921e 0000:01:00.0: ASIC revision: 79610010
10805 16:31:09.923691 <6>[ 8.662634] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10806 16:31:09.927134 <6>[ 8.662634]
10807 16:31:09.930551 Begin: Loading essential drivers ... done.
10808 16:31:09.937490 Begin: Running /scripts/init-premount ... done.
10809 16:31:09.944064 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10810 16:31:09.950223 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10811 16:31:09.953429 Device /sys/class/net/eth0 found
10812 16:31:09.953534 done.
10813 16:31:09.963771 Begin: Waiting up to 180 secs for any network device to become available ... done.
10814 16:31:10.017106 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10815 16:31:10.024066 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10816 16:31:10.030651 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10817 16:31:10.037216 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10818 16:31:10.043694 host : mt8192-asurada-spherion-r0-cbg-0
10819 16:31:10.050579 domain : lava-rack
10820 16:31:10.053347 rootserver: 192.168.201.1 rootpath:
10821 16:31:10.053452 filename :
10822 16:31:10.074870 done.
10823 16:31:10.077609 Begin: Running /scripts/nfs-bottom ... done.
10824 16:31:10.095288 Begin: Running /scripts/init-bottom ... done.
10825 16:31:10.193778 <6>[ 8.932829] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10826 16:31:11.396001 <6>[ 10.138484] NET: Registered PF_INET6 protocol family
10827 16:31:11.403538 <6>[ 10.145744] Segment Routing with IPv6
10828 16:31:11.406599 <6>[ 10.149716] In-situ OAM (IOAM) with IPv6
10829 16:31:11.567478 <30>[ 10.283166] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10830 16:31:11.574034 <30>[ 10.316323] systemd[1]: Detected architecture arm64.
10831 16:31:11.581187
10832 16:31:11.584798 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10833 16:31:11.584880
10834 16:31:11.613217 <30>[ 10.355744] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10835 16:31:12.547016 <30>[ 11.285787] systemd[1]: Queued start job for default target graphical.target.
10836 16:31:12.597233 <30>[ 11.336010] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10837 16:31:12.603544 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10838 16:31:12.626033 <30>[ 11.364993] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10839 16:31:12.635937 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10840 16:31:12.653596 <30>[ 11.392851] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10841 16:31:12.663661 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10842 16:31:12.681485 <30>[ 11.420611] systemd[1]: Created slice user.slice - User and Session Slice.
10843 16:31:12.688026 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10844 16:31:12.712626 <30>[ 11.447983] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10845 16:31:12.722083 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10846 16:31:12.739453 <30>[ 11.475343] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10847 16:31:12.746419 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10848 16:31:12.774852 <30>[ 11.503754] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10849 16:31:12.785020 <30>[ 11.523649] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10850 16:31:12.790859 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10851 16:31:12.808048 <30>[ 11.547111] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10852 16:31:12.815058 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10853 16:31:12.831847 <30>[ 11.571185] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10854 16:31:12.842285 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10855 16:31:12.856855 <30>[ 11.599200] systemd[1]: Reached target paths.target - Path Units.
10856 16:31:12.866815 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10857 16:31:12.884368 <30>[ 11.623540] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10858 16:31:12.890758 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10859 16:31:12.905049 <30>[ 11.647110] systemd[1]: Reached target slices.target - Slice Units.
10860 16:31:12.914986 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10861 16:31:12.929720 <30>[ 11.671618] systemd[1]: Reached target swap.target - Swaps.
10862 16:31:12.935642 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10863 16:31:12.956604 <30>[ 11.695593] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10864 16:31:12.966843 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10865 16:31:12.984825 <30>[ 11.723601] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10866 16:31:12.994213 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10867 16:31:13.013666 <30>[ 11.752995] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10868 16:31:13.023818 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10869 16:31:13.041069 <30>[ 11.780314] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10870 16:31:13.051065 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10871 16:31:13.068897 <30>[ 11.807748] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10872 16:31:13.075114 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10873 16:31:13.093141 <30>[ 11.832364] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10874 16:31:13.103275 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10875 16:31:13.122814 <30>[ 11.862099] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10876 16:31:13.132676 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10877 16:31:13.149124 <30>[ 11.888306] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10878 16:31:13.158893 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10879 16:31:13.220503 <30>[ 11.959309] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10880 16:31:13.226970 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10881 16:31:13.249322 <30>[ 11.988245] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10882 16:31:13.255926 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10883 16:31:13.308672 <30>[ 12.047385] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10884 16:31:13.315090 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10885 16:31:13.343588 <30>[ 12.075788] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10886 16:31:13.358016 <30>[ 12.097351] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10887 16:31:13.368323 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10888 16:31:13.389420 <30>[ 12.128596] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10889 16:31:13.396178 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10890 16:31:13.421386 <30>[ 12.160601] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10891 16:31:13.427823 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10892 16:31:13.452598 <30>[ 12.191398] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10893 16:31:13.465673 Starting [0;1;39mmodpr<6>[ 12.201660] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10894 16:31:13.469118 obe@drm.service[0m - Load Kernel Module drm...
10895 16:31:13.491222 <30>[ 12.230029] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10896 16:31:13.500592 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10897 16:31:13.519643 <30>[ 12.258255] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10898 16:31:13.525969 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10899 16:31:13.549409 <30>[ 12.288117] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10900 16:31:13.555903 Startin<6>[ 12.297004] fuse: init (API version 7.37)
10901 16:31:13.562351 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10902 16:31:13.605049 <30>[ 12.344039] systemd[1]: Starting systemd-journald.service - Journal Service...
10903 16:31:13.611266 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10904 16:31:13.643142 <30>[ 12.382323] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10905 16:31:13.649436 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10906 16:31:13.677569 <30>[ 12.413437] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10907 16:31:13.684010 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10908 16:31:13.728872 <30>[ 12.468028] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10909 16:31:13.738617 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10910 16:31:13.762455 <3>[ 12.501629] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 16:31:13.772499 <30>[ 12.503500] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10912 16:31:13.778938 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10913 16:31:13.799518 <3>[ 12.538594] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 16:31:13.806041 <30>[ 12.539977] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10915 16:31:13.816048 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10916 16:31:13.832711 <30>[ 12.571544] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10917 16:31:13.839343 <3>[ 12.573330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 16:31:13.849444 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10919 16:31:13.870021 <3>[ 12.608859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 16:31:13.879691 <30>[ 12.618244] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10921 16:31:13.886601 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10922 16:31:13.904861 <30>[ 12.643949] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10923 16:31:13.915787 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10924 16:31:13.922358 <3>[ 12.661499] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 16:31:13.933115 <30>[ 12.672177] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10926 16:31:13.939759 <30>[ 12.680494] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10927 16:31:13.956912 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 12.693260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 16:31:13.960399 Load Kernel Module configfs.
10929 16:31:13.974238 <30>[ 12.715823] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10930 16:31:13.984776 <30>[ 12.723765] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10931 16:31:13.994580 <3>[ 12.724847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 16:31:14.001243 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10933 16:31:14.018490 <30>[ 12.760747] systemd[1]: modprobe@drm.service: Deactivated successfully.
10934 16:31:14.028319 <3>[ 12.763218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 16:31:14.034859 <30>[ 12.768180] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10936 16:31:14.045543 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10937 16:31:14.065464 <30>[ 12.804874] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10938 16:31:14.072709 <30>[ 12.812909] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10939 16:31:14.082935 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10940 16:31:14.100713 <30>[ 12.840077] systemd[1]: Started systemd-journald.service - Journal Service.
10941 16:31:14.107827 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10942 16:31:14.129581 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10943 16:31:14.150349 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10944 16:31:14.170453 <4>[ 12.903124] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10945 16:31:14.177679 <3>[ 12.918832] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10946 16:31:14.187795 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10947 16:31:14.210614 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10948 16:31:14.233668 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10949 16:31:14.253675 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10950 16:31:14.279172 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10951 16:31:14.324183 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10952 16:31:14.344978 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10953 16:31:14.369455 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10954 16:31:14.396781 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10955 16:31:14.434287 Starting [0;1;39msyste<46>[ 13.171966] systemd-journald[309]: Received client request to flush runtime journal.
10956 16:31:14.437239 md-sysctl.se…ce[0m - Apply Kernel Variables...
10957 16:31:14.461436 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10958 16:31:14.492558 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10959 16:31:14.513369 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10960 16:31:14.537441 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10961 16:31:15.218385 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10962 16:31:15.542969 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10963 16:31:15.592700 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10964 16:31:15.853743 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10965 16:31:15.947376 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10966 16:31:15.968342 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10967 16:31:15.983828 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10968 16:31:16.028526 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10969 16:31:16.056089 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10970 16:31:16.253322 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10971 16:31:16.318817 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10972 16:31:16.343988 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10973 16:31:16.592874 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10974 16:31:16.621197 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10975 16:31:16.654760 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10976 16:31:16.682841 <6>[ 15.425566] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10977 16:31:16.747854 <4>[ 15.490628] power_supply_show_property: 4 callbacks suppressed
10978 16:31:16.757998 <3>[ 15.490670] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10979 16:31:16.776330 [[0;32m OK [0m] Finished [0<3>[ 15.513892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 16:31:16.779649 ;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10981 16:31:16.793993 <3>[ 15.532702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 16:31:16.826267 <3>[ 15.565485] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 16:31:16.861643 <3>[ 15.600986] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 16:31:16.877379 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10985 16:31:16.893124 <3>[ 15.632229] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 16:31:16.904267 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10987 16:31:16.927456 [[0;32m OK [0m] Listening on [0;1;39msystem<3>[ 15.667420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 16:31:16.934603 d-rfkil…l Switch Status /dev/rfkill Watch.
10989 16:31:16.960275 <3>[ 15.699734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 16:31:16.991809 Starting [0;1;39msyste<3>[ 15.729783] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 16:31:16.995426 md-backlight…ess of leds:white:kbd_backlight...
10992 16:31:17.019188 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10993 16:31:17.037204 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10994 16:31:17.048481 <3>[ 15.787620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 16:31:17.059566 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10996 16:31:17.081928 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10997 16:31:17.100556 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10998 16:31:17.116319 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10999 16:31:17.131568 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11000 16:31:17.157371 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11001 16:31:17.182817 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11002 16:31:17.199935 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11003 16:31:17.218575 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11004 16:31:17.238627 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11005 16:31:17.255676 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11006 16:31:17.273537 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11007 16:31:17.291791 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11008 16:31:17.307775 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11009 16:31:17.353593 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11010 16:31:17.385758 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11011 16:31:17.520804 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11012 16:31:17.552247 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11013 16:31:17.570759 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11014 16:31:17.612582 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11015 16:31:17.680821 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11016 16:31:17.700368 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11017 16:31:17.726493 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11018 16:31:17.748472 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11019 16:31:17.768132 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11020 16:31:17.807211 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11021 16:31:17.911875 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11022 16:31:17.931365 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11023 16:31:17.948629 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11024 16:31:18.010202 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11025 16:31:18.073829 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11026 16:31:18.182194
11027 16:31:18.185666 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11028 16:31:18.185754
11029 16:31:18.189224 debian-bookworm-arm64 login: root (automatic login)
11030 16:31:18.189299
11031 16:31:18.439028 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11032 16:31:18.439173
11033 16:31:18.445313 The programs included with the Debian GNU/Linux system are free software;
11034 16:31:18.452018 the exact distribution terms for each program are described in the
11035 16:31:18.455235 individual files in /usr/share/doc/*/copyright.
11036 16:31:18.455366
11037 16:31:18.462347 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11038 16:31:18.465213 permitted by applicable law.
11039 16:31:19.303006 Matched prompt #10: / #
11041 16:31:19.303252 Setting prompt string to ['/ #']
11042 16:31:19.303342 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11044 16:31:19.303547 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11045 16:31:19.303668 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11046 16:31:19.303763 Setting prompt string to ['/ #']
11047 16:31:19.303847 Forcing a shell prompt, looking for ['/ #']
11049 16:31:19.354120 / #
11050 16:31:19.354331 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11051 16:31:19.354418 Waiting using forced prompt support (timeout 00:02:30)
11052 16:31:19.359613
11053 16:31:19.359905 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11054 16:31:19.360000 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11056 16:31:19.460422 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac'
11057 16:31:19.465055 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396104/extract-nfsrootfs-bcg58fac'
11059 16:31:19.565581 / # export NFS_SERVER_IP='192.168.201.1'
11060 16:31:19.570671 export NFS_SERVER_IP='192.168.201.1'
11061 16:31:19.570978 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11062 16:31:19.571097 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11063 16:31:19.571190 end: 2 depthcharge-action (duration 00:01:23) [common]
11064 16:31:19.571281 start: 3 lava-test-retry (timeout 00:07:56) [common]
11065 16:31:19.571366 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11066 16:31:19.571436 Using namespace: common
11068 16:31:19.671727 / # #
11069 16:31:19.671947 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11070 16:31:19.677146 #
11071 16:31:19.677421 Using /lava-14396104
11073 16:31:19.777775 / # export SHELL=/bin/bash
11074 16:31:19.782865 export SHELL=/bin/bash
11076 16:31:19.883368 / # . /lava-14396104/environment
11077 16:31:19.888890 . /lava-14396104/environment
11079 16:31:19.993346 / # /lava-14396104/bin/lava-test-runner /lava-14396104/0
11080 16:31:19.993561 Test shell timeout: 10s (minimum of the action and connection timeout)
11081 16:31:19.998704 /lava-14396104/bin/lava-test-runner /lava-14396104/0
11082 16:31:20.192516 + export TESTRUN_ID=0_timesync-off
11083 16:31:20.195486 + TESTRUN_ID=0_timesync-off
11084 16:31:20.199228 + cd /lava-14396104/0/tests/0_timesync-off
11085 16:31:20.202134 ++ cat uuid
11086 16:31:20.202236 + UUID=14396104_1.6.2.3.1
11087 16:31:20.205755 + set +x
11088 16:31:20.208563 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14396104_1.6.2.3.1>
11089 16:31:20.208824 Received signal: <STARTRUN> 0_timesync-off 14396104_1.6.2.3.1
11090 16:31:20.208903 Starting test lava.0_timesync-off (14396104_1.6.2.3.1)
11091 16:31:20.208988 Skipping test definition patterns.
11092 16:31:20.212131 + systemctl stop systemd-timesyncd
11093 16:31:20.270090 + set +x
11094 16:31:20.273321 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14396104_1.6.2.3.1>
11095 16:31:20.273629 Received signal: <ENDRUN> 0_timesync-off 14396104_1.6.2.3.1
11096 16:31:20.273720 Ending use of test pattern.
11097 16:31:20.273796 Ending test lava.0_timesync-off (14396104_1.6.2.3.1), duration 0.06
11099 16:31:20.321333 + export TESTRUN_ID=1_kselftest-alsa
11100 16:31:20.324814 + TESTRUN_ID=1_kselftest-alsa
11101 16:31:20.331795 + cd /lava-14396104/0/tests/1_kselftest-alsa
11102 16:31:20.331917 ++ cat uuid
11103 16:31:20.335111 + UUID=14396104_1.6.2.3.5
11104 16:31:20.335219 + set +x
11105 16:31:20.338487 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14396104_1.6.2.3.5>
11106 16:31:20.338752 Received signal: <STARTRUN> 1_kselftest-alsa 14396104_1.6.2.3.5
11107 16:31:20.338822 Starting test lava.1_kselftest-alsa (14396104_1.6.2.3.5)
11108 16:31:20.338912 Skipping test definition patterns.
11109 16:31:20.341347 + cd ./automated/linux/kselftest/
11110 16:31:20.370936 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11111 16:31:20.393490 INFO: install_deps skipped
11112 16:31:20.878266 --2024-06-17 16:31:20-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11113 16:31:20.888110 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11114 16:31:21.019631 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11115 16:31:21.151618 HTTP request sent, awaiting response... 200 OK
11116 16:31:21.154664 Length: 1650228 (1.6M) [application/octet-stream]
11117 16:31:21.157990 Saving to: 'kselftest_armhf.tar.gz'
11118 16:31:21.158078
11119 16:31:21.158141
11120 16:31:21.414452 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11121 16:31:21.677940 kselftest_armhf.tar 3%[ ] 49.22K 187KB/s
11122 16:31:21.984052 kselftest_armhf.tar 13%[=> ] 218.91K 416KB/s
11123 16:31:22.125225 kselftest_armhf.tar 47%[========> ] 757.67K 910KB/s
11124 16:31:22.131945 kselftest_armhf.tar 100%[===================>] 1.57M 1.62MB/s in 1.0s
11125 16:31:22.132065
11126 16:31:22.276538 2024-06-17 16:31:22 (1.62 MB/s) - 'kselftest_armhf.tar.gz' saved [1650228/1650228]
11127 16:31:22.276672
11128 16:31:26.046574 skiplist:
11129 16:31:26.050153 ========================================
11130 16:31:26.053041 ========================================
11131 16:31:26.090583 alsa:mixer-test
11132 16:31:26.108662 ============== Tests to run ===============
11133 16:31:26.108781 alsa:mixer-test
11134 16:31:26.111535 ===========End Tests to run ===============
11135 16:31:26.114962 shardfile-alsa pass
11136 16:31:26.203973 <12>[ 24.947570] kselftest: Running tests in alsa
11137 16:31:26.211465 TAP version 13
11138 16:31:26.224405 1..1
11139 16:31:26.236108 # selftests: alsa: mixer-test
11140 16:31:26.705080 # TAP version 13
11141 16:31:26.705232 # 1..0
11142 16:31:26.711648 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11143 16:31:26.715177 ok 1 selftests: alsa: mixer-test
11144 16:31:28.136338 alsa_mixer-test pass
11145 16:31:28.208979 + ../../utils/send-to-lava.sh ./output/result.txt
11146 16:31:28.264427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11147 16:31:28.264717 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11149 16:31:28.298468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11150 16:31:28.298579 + set +x
11151 16:31:28.298814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11153 16:31:28.304534 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14396104_1.6.2.3.5>
11154 16:31:28.304791 Received signal: <ENDRUN> 1_kselftest-alsa 14396104_1.6.2.3.5
11155 16:31:28.304864 Ending use of test pattern.
11156 16:31:28.304923 Ending test lava.1_kselftest-alsa (14396104_1.6.2.3.5), duration 7.97
11158 16:31:28.308153 <LAVA_TEST_RUNNER EXIT>
11159 16:31:28.308399 ok: lava_test_shell seems to have completed
11160 16:31:28.308525 alsa_mixer-test: pass
shardfile-alsa: pass
11161 16:31:28.308629 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11162 16:31:28.308710 end: 3 lava-test-retry (duration 00:00:09) [common]
11163 16:31:28.308799 start: 4 finalize (timeout 00:07:47) [common]
11164 16:31:28.308881 start: 4.1 power-off (timeout 00:00:30) [common]
11165 16:31:28.309013 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11166 16:31:30.386535 >> Command sent successfully.
11167 16:31:30.389534 Returned 0 in 2 seconds
11168 16:31:30.489929 end: 4.1 power-off (duration 00:00:02) [common]
11170 16:31:30.490374 start: 4.2 read-feedback (timeout 00:07:45) [common]
11171 16:31:30.490672 Listened to connection for namespace 'common' for up to 1s
11172 16:31:31.491044 Finalising connection for namespace 'common'
11173 16:31:31.491231 Disconnecting from shell: Finalise
11174 16:31:31.491340 / #
11175 16:31:31.591621 end: 4.2 read-feedback (duration 00:00:01) [common]
11176 16:31:31.591804 end: 4 finalize (duration 00:00:03) [common]
11177 16:31:31.591964 Cleaning after the job
11178 16:31:31.592126 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/ramdisk
11179 16:31:31.595335 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/kernel
11180 16:31:31.611288 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/dtb
11181 16:31:31.611542 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/nfsrootfs
11182 16:31:31.684209 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396104/tftp-deploy-sqzd0v25/modules
11183 16:31:31.689660 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396104
11184 16:31:32.261777 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396104
11185 16:31:32.261934 Job finished correctly