Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 16:28:47.238591 lava-dispatcher, installed at version: 2024.03
2 16:28:47.238797 start: 0 validate
3 16:28:47.238952 Start time: 2024-06-17 16:28:47.238941+00:00 (UTC)
4 16:28:47.239094 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:28:47.239267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:28:47.499627 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:28:47.499805 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:28:47.765633 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:28:47.765869 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:29:36.336639 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:29:36.337262 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:29:36.855584 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:29:36.856266 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:29:37.124333 validate duration: 49.89
16 16:29:37.124608 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:29:37.124711 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:29:37.124798 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:29:37.124919 Not decompressing ramdisk as can be used compressed.
20 16:29:37.125005 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:29:37.125072 saving as /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/ramdisk/initrd.cpio.gz
22 16:29:37.125138 total size: 5628169 (5 MB)
23 16:29:40.140022 progress 0 % (0 MB)
24 16:29:40.149160 progress 5 % (0 MB)
25 16:29:40.158573 progress 10 % (0 MB)
26 16:29:40.165611 progress 15 % (0 MB)
27 16:29:40.171074 progress 20 % (1 MB)
28 16:29:40.174568 progress 25 % (1 MB)
29 16:29:40.177899 progress 30 % (1 MB)
30 16:29:40.180807 progress 35 % (1 MB)
31 16:29:40.183286 progress 40 % (2 MB)
32 16:29:40.185742 progress 45 % (2 MB)
33 16:29:40.187913 progress 50 % (2 MB)
34 16:29:40.190037 progress 55 % (2 MB)
35 16:29:40.192154 progress 60 % (3 MB)
36 16:29:40.193962 progress 65 % (3 MB)
37 16:29:40.195866 progress 70 % (3 MB)
38 16:29:40.197551 progress 75 % (4 MB)
39 16:29:40.199301 progress 80 % (4 MB)
40 16:29:40.200857 progress 85 % (4 MB)
41 16:29:40.202444 progress 90 % (4 MB)
42 16:29:40.204109 progress 95 % (5 MB)
43 16:29:40.205594 progress 100 % (5 MB)
44 16:29:40.205835 5 MB downloaded in 3.08 s (1.74 MB/s)
45 16:29:40.206039 end: 1.1.1 http-download (duration 00:00:03) [common]
47 16:29:40.206441 end: 1.1 download-retry (duration 00:00:03) [common]
48 16:29:40.206560 start: 1.2 download-retry (timeout 00:09:57) [common]
49 16:29:40.206678 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 16:29:40.206851 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:29:40.206964 saving as /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/kernel/Image
52 16:29:40.207058 total size: 54813184 (52 MB)
53 16:29:40.207151 No compression specified
54 16:29:40.208782 progress 0 % (0 MB)
55 16:29:40.223271 progress 5 % (2 MB)
56 16:29:40.237610 progress 10 % (5 MB)
57 16:29:40.251926 progress 15 % (7 MB)
58 16:29:40.266175 progress 20 % (10 MB)
59 16:29:40.280388 progress 25 % (13 MB)
60 16:29:40.294456 progress 30 % (15 MB)
61 16:29:40.309024 progress 35 % (18 MB)
62 16:29:40.323530 progress 40 % (20 MB)
63 16:29:40.337686 progress 45 % (23 MB)
64 16:29:40.351895 progress 50 % (26 MB)
65 16:29:40.366073 progress 55 % (28 MB)
66 16:29:40.380144 progress 60 % (31 MB)
67 16:29:40.394428 progress 65 % (34 MB)
68 16:29:40.408392 progress 70 % (36 MB)
69 16:29:40.422726 progress 75 % (39 MB)
70 16:29:40.437213 progress 80 % (41 MB)
71 16:29:40.451683 progress 85 % (44 MB)
72 16:29:40.465985 progress 90 % (47 MB)
73 16:29:40.480384 progress 95 % (49 MB)
74 16:29:40.494512 progress 100 % (52 MB)
75 16:29:40.494792 52 MB downloaded in 0.29 s (181.68 MB/s)
76 16:29:40.494999 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:29:40.495392 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:29:40.495515 start: 1.3 download-retry (timeout 00:09:57) [common]
80 16:29:40.495646 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 16:29:40.495829 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:29:40.495946 saving as /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/dtb/mt8192-asurada-spherion-r0.dtb
83 16:29:40.496055 total size: 47258 (0 MB)
84 16:29:40.496151 No compression specified
85 16:29:40.497855 progress 69 % (0 MB)
86 16:29:40.498174 progress 100 % (0 MB)
87 16:29:40.498366 0 MB downloaded in 0.00 s (19.53 MB/s)
88 16:29:40.498537 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:29:40.498898 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:29:40.498999 start: 1.4 download-retry (timeout 00:09:57) [common]
92 16:29:40.499086 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 16:29:40.499203 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:29:40.499275 saving as /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/nfsrootfs/full.rootfs.tar
95 16:29:40.499337 total size: 120894716 (115 MB)
96 16:29:40.499402 Using unxz to decompress xz
97 16:29:40.506070 progress 0 % (0 MB)
98 16:29:40.859467 progress 5 % (5 MB)
99 16:29:41.229054 progress 10 % (11 MB)
100 16:29:41.591907 progress 15 % (17 MB)
101 16:29:41.926719 progress 20 % (23 MB)
102 16:29:42.223199 progress 25 % (28 MB)
103 16:29:42.591181 progress 30 % (34 MB)
104 16:29:42.942697 progress 35 % (40 MB)
105 16:29:43.109663 progress 40 % (46 MB)
106 16:29:43.289963 progress 45 % (51 MB)
107 16:29:43.604466 progress 50 % (57 MB)
108 16:29:43.989959 progress 55 % (63 MB)
109 16:29:44.339829 progress 60 % (69 MB)
110 16:29:44.679371 progress 65 % (74 MB)
111 16:29:45.027023 progress 70 % (80 MB)
112 16:29:45.387110 progress 75 % (86 MB)
113 16:29:45.728500 progress 80 % (92 MB)
114 16:29:46.069080 progress 85 % (98 MB)
115 16:29:46.426227 progress 90 % (103 MB)
116 16:29:46.755441 progress 95 % (109 MB)
117 16:29:47.114690 progress 100 % (115 MB)
118 16:29:47.120085 115 MB downloaded in 6.62 s (17.41 MB/s)
119 16:29:47.120338 end: 1.4.1 http-download (duration 00:00:07) [common]
121 16:29:47.120606 end: 1.4 download-retry (duration 00:00:07) [common]
122 16:29:47.120698 start: 1.5 download-retry (timeout 00:09:50) [common]
123 16:29:47.120784 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 16:29:47.120930 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:29:47.121000 saving as /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/modules/modules.tar
126 16:29:47.121061 total size: 8628772 (8 MB)
127 16:29:47.121122 Using unxz to decompress xz
128 16:29:47.124992 progress 0 % (0 MB)
129 16:29:47.146007 progress 5 % (0 MB)
130 16:29:47.170134 progress 10 % (0 MB)
131 16:29:47.193854 progress 15 % (1 MB)
132 16:29:47.218211 progress 20 % (1 MB)
133 16:29:47.243397 progress 25 % (2 MB)
134 16:29:47.267358 progress 30 % (2 MB)
135 16:29:47.294028 progress 35 % (2 MB)
136 16:29:47.318717 progress 40 % (3 MB)
137 16:29:47.343252 progress 45 % (3 MB)
138 16:29:47.368925 progress 50 % (4 MB)
139 16:29:47.393226 progress 55 % (4 MB)
140 16:29:47.417774 progress 60 % (4 MB)
141 16:29:47.444934 progress 65 % (5 MB)
142 16:29:47.469795 progress 70 % (5 MB)
143 16:29:47.493020 progress 75 % (6 MB)
144 16:29:47.516848 progress 80 % (6 MB)
145 16:29:47.544438 progress 85 % (7 MB)
146 16:29:47.571972 progress 90 % (7 MB)
147 16:29:47.599714 progress 95 % (7 MB)
148 16:29:47.625019 progress 100 % (8 MB)
149 16:29:47.630113 8 MB downloaded in 0.51 s (16.17 MB/s)
150 16:29:47.630412 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:29:47.630680 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:29:47.630777 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 16:29:47.630871 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 16:29:51.044573 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3
156 16:29:51.044781 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 16:29:51.044885 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 16:29:51.045065 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v
159 16:29:51.045199 makedir: /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin
160 16:29:51.045304 makedir: /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/tests
161 16:29:51.045406 makedir: /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/results
162 16:29:51.045508 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-add-keys
163 16:29:51.045652 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-add-sources
164 16:29:51.045783 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-background-process-start
165 16:29:51.045913 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-background-process-stop
166 16:29:51.046041 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-common-functions
167 16:29:51.046180 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-echo-ipv4
168 16:29:51.046309 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-install-packages
169 16:29:51.046435 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-installed-packages
170 16:29:51.046561 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-os-build
171 16:29:51.046688 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-probe-channel
172 16:29:51.046815 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-probe-ip
173 16:29:51.046942 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-target-ip
174 16:29:51.047066 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-target-mac
175 16:29:51.047190 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-target-storage
176 16:29:51.047318 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-case
177 16:29:51.047444 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-event
178 16:29:51.047568 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-feedback
179 16:29:51.047694 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-raise
180 16:29:51.047819 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-reference
181 16:29:51.047944 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-runner
182 16:29:51.048069 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-set
183 16:29:51.048209 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-test-shell
184 16:29:51.048632 Updating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-add-keys (debian)
185 16:29:51.049492 Updating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-add-sources (debian)
186 16:29:51.049850 Updating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-install-packages (debian)
187 16:29:51.052138 Updating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-installed-packages (debian)
188 16:29:51.052452 Updating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/bin/lava-os-build (debian)
189 16:29:51.052993 Creating /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/environment
190 16:29:51.053386 LAVA metadata
191 16:29:51.053639 - LAVA_JOB_ID=14396117
192 16:29:51.053878 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:29:51.054277 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 16:29:51.054530 skipped lava-vland-overlay
195 16:29:51.054810 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:29:51.055148 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 16:29:51.055393 skipped lava-multinode-overlay
198 16:29:51.055683 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:29:51.055999 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 16:29:51.056293 Loading test definitions
201 16:29:51.056651 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 16:29:51.056933 Using /lava-14396117 at stage 0
203 16:29:51.058051 uuid=14396117_1.6.2.3.1 testdef=None
204 16:29:51.058669 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:29:51.058934 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 16:29:51.060262 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:29:51.060900 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 16:29:51.062567 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:29:51.063187 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 16:29:51.064442 runner path: /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/0/tests/0_timesync-off test_uuid 14396117_1.6.2.3.1
213 16:29:51.064816 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:29:51.065346 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 16:29:51.065517 Using /lava-14396117 at stage 0
217 16:29:51.065741 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:29:51.065938 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/0/tests/1_kselftest-arm64'
219 16:29:54.102588 Running '/usr/bin/git checkout kernelci.org
220 16:29:54.183733 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 16:29:54.184484 uuid=14396117_1.6.2.3.5 testdef=None
222 16:29:54.184647 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 16:29:54.184896 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 16:29:54.185648 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:29:54.185890 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 16:29:54.186915 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:29:54.187158 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 16:29:54.188093 runner path: /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/0/tests/1_kselftest-arm64 test_uuid 14396117_1.6.2.3.5
232 16:29:54.188187 BOARD='mt8192-asurada-spherion-r0'
233 16:29:54.188252 BRANCH='cip-gitlab'
234 16:29:54.188312 SKIPFILE='/dev/null'
235 16:29:54.188371 SKIP_INSTALL='True'
236 16:29:54.188428 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:29:54.188486 TST_CASENAME=''
238 16:29:54.188542 TST_CMDFILES='arm64'
239 16:29:54.188683 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:29:54.188892 Creating lava-test-runner.conf files
242 16:29:54.188956 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396117/lava-overlay-5iaa396v/lava-14396117/0 for stage 0
243 16:29:54.189051 - 0_timesync-off
244 16:29:54.189123 - 1_kselftest-arm64
245 16:29:54.189217 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 16:29:54.189309 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 16:30:01.699674 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 16:30:01.699836 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 16:30:01.699940 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:30:01.700047 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 16:30:01.700159 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 16:30:01.866075 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:30:01.866499 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 16:30:01.866614 extracting modules file /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3
255 16:30:02.088328 extracting modules file /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396117/extract-overlay-ramdisk-49ep8nd7/ramdisk
256 16:30:02.325418 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:30:02.325592 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 16:30:02.325695 [common] Applying overlay to NFS
259 16:30:02.325768 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396117/compress-overlay-w_1dfkx_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3
260 16:30:03.269643 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:30:03.269895 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 16:30:03.270052 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:30:03.270218 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 16:30:03.270308 Building ramdisk /var/lib/lava/dispatcher/tmp/14396117/extract-overlay-ramdisk-49ep8nd7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396117/extract-overlay-ramdisk-49ep8nd7/ramdisk
265 16:30:03.612469 >> 130466 blocks
266 16:30:05.656064 rename /var/lib/lava/dispatcher/tmp/14396117/extract-overlay-ramdisk-49ep8nd7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/ramdisk/ramdisk.cpio.gz
267 16:30:05.656524 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 16:30:05.656647 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 16:30:05.656754 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 16:30:05.656861 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/kernel/Image']
271 16:30:18.850483 Returned 0 in 13 seconds
272 16:30:18.951441 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/kernel/image.itb
273 16:30:19.356660 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:30:19.357062 output: Created: Mon Jun 17 17:30:19 2024
275 16:30:19.357171 output: Image 0 (kernel-1)
276 16:30:19.357270 output: Description:
277 16:30:19.357365 output: Created: Mon Jun 17 17:30:19 2024
278 16:30:19.357459 output: Type: Kernel Image
279 16:30:19.357554 output: Compression: lzma compressed
280 16:30:19.357643 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
281 16:30:19.357734 output: Architecture: AArch64
282 16:30:19.357821 output: OS: Linux
283 16:30:19.357911 output: Load Address: 0x00000000
284 16:30:19.357999 output: Entry Point: 0x00000000
285 16:30:19.358084 output: Hash algo: crc32
286 16:30:19.358195 output: Hash value: 106ffd6f
287 16:30:19.358274 output: Image 1 (fdt-1)
288 16:30:19.358332 output: Description: mt8192-asurada-spherion-r0
289 16:30:19.358389 output: Created: Mon Jun 17 17:30:19 2024
290 16:30:19.358450 output: Type: Flat Device Tree
291 16:30:19.358510 output: Compression: uncompressed
292 16:30:19.358593 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 16:30:19.358692 output: Architecture: AArch64
294 16:30:19.358779 output: Hash algo: crc32
295 16:30:19.358865 output: Hash value: 0f8e4d2e
296 16:30:19.358951 output: Image 2 (ramdisk-1)
297 16:30:19.359035 output: Description: unavailable
298 16:30:19.359118 output: Created: Mon Jun 17 17:30:19 2024
299 16:30:19.359201 output: Type: RAMDisk Image
300 16:30:19.359285 output: Compression: Unknown Compression
301 16:30:19.359370 output: Data Size: 18748034 Bytes = 18308.63 KiB = 17.88 MiB
302 16:30:19.359453 output: Architecture: AArch64
303 16:30:19.359536 output: OS: Linux
304 16:30:19.359619 output: Load Address: unavailable
305 16:30:19.359704 output: Entry Point: unavailable
306 16:30:19.359788 output: Hash algo: crc32
307 16:30:19.359870 output: Hash value: 4b6c9dd4
308 16:30:19.359955 output: Default Configuration: 'conf-1'
309 16:30:19.360040 output: Configuration 0 (conf-1)
310 16:30:19.360124 output: Description: mt8192-asurada-spherion-r0
311 16:30:19.360207 output: Kernel: kernel-1
312 16:30:19.360291 output: Init Ramdisk: ramdisk-1
313 16:30:19.360375 output: FDT: fdt-1
314 16:30:19.360458 output: Loadables: kernel-1
315 16:30:19.360540 output:
316 16:30:19.360778 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 16:30:19.360908 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 16:30:19.361048 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 16:30:19.361175 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 16:30:19.361286 No LXC device requested
321 16:30:19.361397 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:30:19.361524 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 16:30:19.361635 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:30:19.361728 Checking files for TFTP limit of 4294967296 bytes.
325 16:30:19.362440 end: 1 tftp-deploy (duration 00:00:42) [common]
326 16:30:19.362579 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:30:19.362704 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:30:19.362874 substitutions:
329 16:30:19.362973 - {DTB}: 14396117/tftp-deploy-7cy_9ryj/dtb/mt8192-asurada-spherion-r0.dtb
330 16:30:19.363069 - {INITRD}: 14396117/tftp-deploy-7cy_9ryj/ramdisk/ramdisk.cpio.gz
331 16:30:19.363161 - {KERNEL}: 14396117/tftp-deploy-7cy_9ryj/kernel/Image
332 16:30:19.363252 - {LAVA_MAC}: None
333 16:30:19.363342 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3
334 16:30:19.363429 - {NFS_SERVER_IP}: 192.168.201.1
335 16:30:19.363515 - {PRESEED_CONFIG}: None
336 16:30:19.363602 - {PRESEED_LOCAL}: None
337 16:30:19.363688 - {RAMDISK}: 14396117/tftp-deploy-7cy_9ryj/ramdisk/ramdisk.cpio.gz
338 16:30:19.363773 - {ROOT_PART}: None
339 16:30:19.363860 - {ROOT}: None
340 16:30:19.363948 - {SERVER_IP}: 192.168.201.1
341 16:30:19.364033 - {TEE}: None
342 16:30:19.364119 Parsed boot commands:
343 16:30:19.364206 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:30:19.364437 Parsed boot commands: tftpboot 192.168.201.1 14396117/tftp-deploy-7cy_9ryj/kernel/image.itb 14396117/tftp-deploy-7cy_9ryj/kernel/cmdline
345 16:30:19.364558 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:30:19.364692 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:30:19.364817 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:30:19.364939 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:30:19.365044 Not connected, no need to disconnect.
350 16:30:19.365152 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:30:19.365268 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:30:19.365351 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 16:30:19.368969 Setting prompt string to ['lava-test: # ']
354 16:30:19.369374 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:30:19.369514 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:30:19.369700 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:30:19.369827 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:30:19.370107 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 16:30:33.080966 Returned 0 in 13 seconds
360 16:30:33.182040 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 16:30:33.183618 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 16:30:33.184127 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 16:30:33.184770 Setting prompt string to 'Starting depthcharge on Spherion...'
365 16:30:33.185154 Changing prompt to 'Starting depthcharge on Spherion...'
366 16:30:33.185522 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 16:30:33.187735 [Enter `^Ec?' for help]
368 16:30:33.188166
369 16:30:33.188541 F0: 102B 0000
370 16:30:33.188887
371 16:30:33.189234 F3: 1001 0000 [0200]
372 16:30:33.189546
373 16:30:33.189861 F3: 1001 0000
374 16:30:33.190220
375 16:30:33.190542 F7: 102D 0000
376 16:30:33.190862
377 16:30:33.191159 F1: 0000 0000
378 16:30:33.191447
379 16:30:33.191773 V0: 0000 0000 [0001]
380 16:30:33.192213
381 16:30:33.192528 00: 0007 8000
382 16:30:33.192835
383 16:30:33.193125 01: 0000 0000
384 16:30:33.193417
385 16:30:33.193701 BP: 0C00 0209 [0000]
386 16:30:33.193983
387 16:30:33.194488 G0: 1182 0000
388 16:30:33.194939
389 16:30:33.195269 EC: 0000 0021 [4000]
390 16:30:33.195602
391 16:30:33.196063 S7: 0000 0000 [0000]
392 16:30:33.196511
393 16:30:33.196996 CC: 0000 0000 [0001]
394 16:30:33.197490
395 16:30:33.197944 T0: 0000 0040 [010F]
396 16:30:33.198428
397 16:30:33.198881 Jump to BL
398 16:30:33.199324
399 16:30:33.199741
400 16:30:33.200056
401 16:30:33.200395 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
402 16:30:33.200883 ARM64: Exception handlers installed.
403 16:30:33.201272 ARM64: Testing exception
404 16:30:33.201744 ARM64: Done test exception
405 16:30:33.202298 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
406 16:30:33.202759 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
407 16:30:33.203211 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
408 16:30:33.203658 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
409 16:30:33.204104 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
410 16:30:33.204622 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
411 16:30:33.205143 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
412 16:30:33.205462 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
413 16:30:33.205755 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
414 16:30:33.206047 WDT: Last reset was cold boot
415 16:30:33.206397 SPI1(PAD0) initialized at 2873684 Hz
416 16:30:33.206691 SPI5(PAD0) initialized at 992727 Hz
417 16:30:33.206977 VBOOT: Loading verstage.
418 16:30:33.207282 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
419 16:30:33.207605 FMAP: Found "FLASH" version 1.1 at 0x20000.
420 16:30:33.207855 FMAP: base = 0x0 size = 0x800000 #areas = 25
421 16:30:33.208060 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
422 16:30:33.208280 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
423 16:30:33.208494 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
424 16:30:33.208699 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
425 16:30:33.208905
426 16:30:33.209113
427 16:30:33.209343 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
428 16:30:33.209564 ARM64: Exception handlers installed.
429 16:30:33.209811 ARM64: Testing exception
430 16:30:33.210017 ARM64: Done test exception
431 16:30:33.210250 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
432 16:30:33.210462 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
433 16:30:33.210669 Probing TPM: . done!
434 16:30:33.210871 TPM ready after 0 ms
435 16:30:33.211098 Connected to device vid:did:rid of 1ae0:0028:00
436 16:30:33.211306 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
437 16:30:33.211514 Initialized TPM device CR50 revision 0
438 16:30:33.211719 tlcl_send_startup: Startup return code is 0
439 16:30:33.211922 TPM: setup succeeded
440 16:30:33.212140 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
441 16:30:33.212390 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
442 16:30:33.212595 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
443 16:30:33.212789 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 16:30:33.212942 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
445 16:30:33.213097 in-header: 03 07 00 00 08 00 00 00
446 16:30:33.213249 in-data: aa e4 47 04 13 02 00 00
447 16:30:33.213400 Chrome EC: UHEPI supported
448 16:30:33.213554 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
449 16:30:33.213832 in-header: 03 a9 00 00 08 00 00 00
450 16:30:33.214113 in-data: 84 60 60 08 00 00 00 00
451 16:30:33.214320 Phase 1
452 16:30:33.214478 FMAP: area GBB found @ 3f5000 (12032 bytes)
453 16:30:33.214636 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
454 16:30:33.214816 VB2:vb2_check_recovery() Recovery was requested manually
455 16:30:33.214980 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
456 16:30:33.215133 Recovery requested (1009000e)
457 16:30:33.215286 TPM: Extending digest for VBOOT: boot mode into PCR 0
458 16:30:33.215439 tlcl_extend: response is 0
459 16:30:33.215592 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
460 16:30:33.215746 tlcl_extend: response is 0
461 16:30:33.215899 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
462 16:30:33.216053 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
463 16:30:33.216207 BS: bootblock times (exec / console): total (unknown) / 148 ms
464 16:30:33.216398
465 16:30:33.216555
466 16:30:33.216706 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
467 16:30:33.216862 ARM64: Exception handlers installed.
468 16:30:33.217015 ARM64: Testing exception
469 16:30:33.217168 ARM64: Done test exception
470 16:30:33.217320 pmic_efuse_setting: Set efuses in 11 msecs
471 16:30:33.217475 pmwrap_interface_init: Select PMIF_VLD_RDY
472 16:30:33.217643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
473 16:30:33.218032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
474 16:30:33.218201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
475 16:30:33.218333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
476 16:30:33.218469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
477 16:30:33.218612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
478 16:30:33.218754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
479 16:30:33.218889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
480 16:30:33.219014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
481 16:30:33.219160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
482 16:30:33.219285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
483 16:30:33.219408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
484 16:30:33.219529 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
485 16:30:33.219652 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
486 16:30:33.219775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
487 16:30:33.219898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
488 16:30:33.220021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
489 16:30:33.220155 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
490 16:30:33.220281 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
491 16:30:33.220402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
492 16:30:33.220525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
493 16:30:33.220648 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
494 16:30:33.220769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
495 16:30:33.220921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
496 16:30:33.221139 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
497 16:30:33.221340 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
498 16:30:33.221530 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
499 16:30:33.221721 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
500 16:30:33.221911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
501 16:30:33.222123 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
502 16:30:33.222349 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
503 16:30:33.222482 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
504 16:30:33.222607 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
505 16:30:33.222742 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
506 16:30:33.222845 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
507 16:30:33.222949 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
508 16:30:33.223059 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
509 16:30:33.223204 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
510 16:30:33.223309 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
511 16:30:33.223411 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
512 16:30:33.223514 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
513 16:30:33.223617 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
514 16:30:33.223720 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
515 16:30:33.223822 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
516 16:30:33.223924 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
517 16:30:33.224046 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
518 16:30:33.224172 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
519 16:30:33.224277 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
520 16:30:33.224380 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
521 16:30:33.224482 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
522 16:30:33.224583 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
523 16:30:33.224684 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
524 16:30:33.224788 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
525 16:30:33.224892 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
526 16:30:33.225048 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
527 16:30:33.225156 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
528 16:30:33.225261 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
529 16:30:33.225364 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
530 16:30:33.225466 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 16:30:33.225568 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
532 16:30:33.225671 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
533 16:30:33.225773 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
534 16:30:33.225875 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
535 16:30:33.226048 [RTC]rtc_get_frequency_meter,154: input=15, output=834
536 16:30:33.226211 [RTC]rtc_get_frequency_meter,154: input=7, output=709
537 16:30:33.226319 [RTC]rtc_get_frequency_meter,154: input=11, output=771
538 16:30:33.226422 [RTC]rtc_get_frequency_meter,154: input=13, output=803
539 16:30:33.226524 [RTC]rtc_get_frequency_meter,154: input=12, output=787
540 16:30:33.226626 [RTC]rtc_get_frequency_meter,154: input=12, output=788
541 16:30:33.226728 [RTC]rtc_get_frequency_meter,154: input=13, output=804
542 16:30:33.226830 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
543 16:30:33.227208 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
544 16:30:33.227338 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
545 16:30:33.227522 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
546 16:30:33.227722 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
547 16:30:33.227836 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
548 16:30:33.227963 ADC[4]: Raw value=905618 ID=7
549 16:30:33.228073 ADC[3]: Raw value=213282 ID=1
550 16:30:33.228164 RAM Code: 0x71
551 16:30:33.228255 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
552 16:30:33.228344 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
553 16:30:33.228433 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
554 16:30:33.228523 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
555 16:30:33.228615 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
556 16:30:33.228763 in-header: 03 07 00 00 08 00 00 00
557 16:30:33.228865 in-data: aa e4 47 04 13 02 00 00
558 16:30:33.228955 Chrome EC: UHEPI supported
559 16:30:33.229045 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
560 16:30:33.229135 in-header: 03 a9 00 00 08 00 00 00
561 16:30:33.229223 in-data: 84 60 60 08 00 00 00 00
562 16:30:33.229310 MRC: failed to locate region type 0.
563 16:30:33.229397 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
564 16:30:33.229510 DRAM-K: Running full calibration
565 16:30:33.229654 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
566 16:30:33.229790 header.status = 0x0
567 16:30:33.229925 header.version = 0x6 (expected: 0x6)
568 16:30:33.230060 header.size = 0xd00 (expected: 0xd00)
569 16:30:33.230218 header.flags = 0x0
570 16:30:33.230365 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
571 16:30:33.230513 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
572 16:30:33.230651 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
573 16:30:33.230788 dram_init: ddr_geometry: 2
574 16:30:33.230925 [EMI] MDL number = 2
575 16:30:33.231055 [EMI] Get MDL freq = 0
576 16:30:33.231147 dram_init: ddr_type: 0
577 16:30:33.231234 is_discrete_lpddr4: 1
578 16:30:33.231321 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
579 16:30:33.231412
580 16:30:33.231499
581 16:30:33.231623 [Bian_co] ETT version 0.0.0.1
582 16:30:33.231768 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
583 16:30:33.231904
584 16:30:33.232039 dramc_set_vcore_voltage set vcore to 650000
585 16:30:33.232179 Read voltage for 800, 4
586 16:30:33.232321 Vio18 = 0
587 16:30:33.232419 Vcore = 650000
588 16:30:33.232511 Vdram = 0
589 16:30:33.232599 Vddq = 0
590 16:30:33.232686 Vmddr = 0
591 16:30:33.232776 dram_init: config_dvfs: 1
592 16:30:33.232897 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
593 16:30:33.232978 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
594 16:30:33.233074 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
595 16:30:33.233197 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
596 16:30:33.233342 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
597 16:30:33.233466 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
598 16:30:33.233592 MEM_TYPE=3, freq_sel=18
599 16:30:33.233682 sv_algorithm_assistance_LP4_1600
600 16:30:33.233762 ============ PULL DRAM RESETB DOWN ============
601 16:30:33.233841 ========== PULL DRAM RESETB DOWN end =========
602 16:30:33.233919 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
603 16:30:33.234038 ===================================
604 16:30:33.234170 LPDDR4 DRAM CONFIGURATION
605 16:30:33.234259 ===================================
606 16:30:33.234337 EX_ROW_EN[0] = 0x0
607 16:30:33.234414 EX_ROW_EN[1] = 0x0
608 16:30:33.234490 LP4Y_EN = 0x0
609 16:30:33.234567 WORK_FSP = 0x0
610 16:30:33.234643 WL = 0x2
611 16:30:33.234719 RL = 0x2
612 16:30:33.234795 BL = 0x2
613 16:30:33.234893 RPST = 0x0
614 16:30:33.235012 RD_PRE = 0x0
615 16:30:33.235132 WR_PRE = 0x1
616 16:30:33.235212 WR_PST = 0x0
617 16:30:33.235289 DBI_WR = 0x0
618 16:30:33.235365 DBI_RD = 0x0
619 16:30:33.235442 OTF = 0x1
620 16:30:33.235519 ===================================
621 16:30:33.235603 ===================================
622 16:30:33.235716 ANA top config
623 16:30:33.235796 ===================================
624 16:30:33.235873 DLL_ASYNC_EN = 0
625 16:30:33.235950 ALL_SLAVE_EN = 1
626 16:30:33.236026 NEW_RANK_MODE = 1
627 16:30:33.236107 DLL_IDLE_MODE = 1
628 16:30:33.236183 LP45_APHY_COMB_EN = 1
629 16:30:33.236259 TX_ODT_DIS = 1
630 16:30:33.236340 NEW_8X_MODE = 1
631 16:30:33.236457 ===================================
632 16:30:33.236536 ===================================
633 16:30:33.236614 data_rate = 1600
634 16:30:33.236690 CKR = 1
635 16:30:33.236795 DQ_P2S_RATIO = 8
636 16:30:33.236919 ===================================
637 16:30:33.237031 CA_P2S_RATIO = 8
638 16:30:33.237114 DQ_CA_OPEN = 0
639 16:30:33.237191 DQ_SEMI_OPEN = 0
640 16:30:33.237268 CA_SEMI_OPEN = 0
641 16:30:33.237345 CA_FULL_RATE = 0
642 16:30:33.237421 DQ_CKDIV4_EN = 1
643 16:30:33.237497 CA_CKDIV4_EN = 1
644 16:30:33.237572 CA_PREDIV_EN = 0
645 16:30:33.237648 PH8_DLY = 0
646 16:30:33.237765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
647 16:30:33.237870 DQ_AAMCK_DIV = 4
648 16:30:33.237942 CA_AAMCK_DIV = 4
649 16:30:33.238010 CA_ADMCK_DIV = 4
650 16:30:33.238079 DQ_TRACK_CA_EN = 0
651 16:30:33.238147 CA_PICK = 800
652 16:30:33.238266 CA_MCKIO = 800
653 16:30:33.238340 MCKIO_SEMI = 0
654 16:30:33.238408 PLL_FREQ = 3068
655 16:30:33.238477 DQ_UI_PI_RATIO = 32
656 16:30:33.238545 CA_UI_PI_RATIO = 0
657 16:30:33.238614 ===================================
658 16:30:33.238682 ===================================
659 16:30:33.238749 memory_type:LPDDR4
660 16:30:33.238817 GP_NUM : 10
661 16:30:33.238885 SRAM_EN : 1
662 16:30:33.238952 MD32_EN : 0
663 16:30:33.239284 ===================================
664 16:30:33.239366 [ANA_INIT] >>>>>>>>>>>>>>
665 16:30:33.239476 <<<<<< [CONFIGURE PHASE]: ANA_TX
666 16:30:33.239554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
667 16:30:33.239625 ===================================
668 16:30:33.239695 data_rate = 1600,PCW = 0X7600
669 16:30:33.239764 ===================================
670 16:30:33.239832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
671 16:30:33.239901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 16:30:33.239970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 16:30:33.240046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
674 16:30:33.240151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
675 16:30:33.240223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
676 16:30:33.240291 [ANA_INIT] flow start
677 16:30:33.240359 [ANA_INIT] PLL >>>>>>>>
678 16:30:33.240427 [ANA_INIT] PLL <<<<<<<<
679 16:30:33.240495 [ANA_INIT] MIDPI >>>>>>>>
680 16:30:33.240571 [ANA_INIT] MIDPI <<<<<<<<
681 16:30:33.240672 [ANA_INIT] DLL >>>>>>>>
682 16:30:33.240743 [ANA_INIT] flow end
683 16:30:33.240811 ============ LP4 DIFF to SE enter ============
684 16:30:33.240880 ============ LP4 DIFF to SE exit ============
685 16:30:33.240949 [ANA_INIT] <<<<<<<<<<<<<
686 16:30:33.241031 [Flow] Enable top DCM control >>>>>
687 16:30:33.241143 [Flow] Enable top DCM control <<<<<
688 16:30:33.241249 Enable DLL master slave shuffle
689 16:30:33.241355 ==============================================================
690 16:30:33.241469 Gating Mode config
691 16:30:33.241542 ==============================================================
692 16:30:33.241612 Config description:
693 16:30:33.241681 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
694 16:30:33.241751 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
695 16:30:33.241821 SELPH_MODE 0: By rank 1: By Phase
696 16:30:33.241890 ==============================================================
697 16:30:33.241962 GAT_TRACK_EN = 1
698 16:30:33.242074 RX_GATING_MODE = 2
699 16:30:33.242190 RX_GATING_TRACK_MODE = 2
700 16:30:33.242297 SELPH_MODE = 1
701 16:30:33.242407 PICG_EARLY_EN = 1
702 16:30:33.242519 VALID_LAT_VALUE = 1
703 16:30:33.242596 ==============================================================
704 16:30:33.242666 Enter into Gating configuration >>>>
705 16:30:33.242743 Exit from Gating configuration <<<<
706 16:30:33.242804 Enter into DVFS_PRE_config >>>>>
707 16:30:33.242865 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
708 16:30:33.242931 Exit from DVFS_PRE_config <<<<<
709 16:30:33.243032 Enter into PICG configuration >>>>
710 16:30:33.243125 Exit from PICG configuration <<<<
711 16:30:33.243190 [RX_INPUT] configuration >>>>>
712 16:30:33.243251 [RX_INPUT] configuration <<<<<
713 16:30:33.243316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
714 16:30:33.243377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
715 16:30:33.243476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
716 16:30:33.243543 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
717 16:30:33.243606 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
718 16:30:33.243668 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
719 16:30:33.243729 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
720 16:30:33.243793 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
721 16:30:33.243862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
722 16:30:33.243962 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
723 16:30:33.244045 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
724 16:30:33.244108 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
725 16:30:33.244171 ===================================
726 16:30:33.244232 LPDDR4 DRAM CONFIGURATION
727 16:30:33.244294 ===================================
728 16:30:33.244355 EX_ROW_EN[0] = 0x0
729 16:30:33.244451 EX_ROW_EN[1] = 0x0
730 16:30:33.244519 LP4Y_EN = 0x0
731 16:30:33.244581 WORK_FSP = 0x0
732 16:30:33.244641 WL = 0x2
733 16:30:33.244702 RL = 0x2
734 16:30:33.244763 BL = 0x2
735 16:30:33.244824 RPST = 0x0
736 16:30:33.244884 RD_PRE = 0x0
737 16:30:33.244967 WR_PRE = 0x1
738 16:30:33.245046 WR_PST = 0x0
739 16:30:33.245108 DBI_WR = 0x0
740 16:30:33.245169 DBI_RD = 0x0
741 16:30:33.245231 OTF = 0x1
742 16:30:33.245292 ===================================
743 16:30:33.245353 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
744 16:30:33.245424 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
745 16:30:33.245517 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
746 16:30:33.245581 ===================================
747 16:30:33.245643 LPDDR4 DRAM CONFIGURATION
748 16:30:33.245705 ===================================
749 16:30:33.245766 EX_ROW_EN[0] = 0x10
750 16:30:33.245827 EX_ROW_EN[1] = 0x0
751 16:30:33.245887 LP4Y_EN = 0x0
752 16:30:33.245967 WORK_FSP = 0x0
753 16:30:33.246066 WL = 0x2
754 16:30:33.246169 RL = 0x2
755 16:30:33.246266 BL = 0x2
756 16:30:33.246367 RPST = 0x0
757 16:30:33.246466 RD_PRE = 0x0
758 16:30:33.246561 WR_PRE = 0x1
759 16:30:33.246655 WR_PST = 0x0
760 16:30:33.246750 DBI_WR = 0x0
761 16:30:33.246844 DBI_RD = 0x0
762 16:30:33.246943 OTF = 0x1
763 16:30:33.247043 ===================================
764 16:30:33.247139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
765 16:30:33.247234 nWR fixed to 40
766 16:30:33.247330 [ModeRegInit_LP4] CH0 RK0
767 16:30:33.247424 [ModeRegInit_LP4] CH0 RK1
768 16:30:33.247526 [ModeRegInit_LP4] CH1 RK0
769 16:30:33.247621 [ModeRegInit_LP4] CH1 RK1
770 16:30:33.247728 match AC timing 13
771 16:30:33.248015 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
772 16:30:33.248080 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
773 16:30:33.248139 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
774 16:30:33.248196 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
775 16:30:33.248253 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
776 16:30:33.248309 [EMI DOE] emi_dcm 0
777 16:30:33.248365 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
778 16:30:33.248421 ==
779 16:30:33.248478 Dram Type= 6, Freq= 0, CH_0, rank 0
780 16:30:33.248534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 16:30:33.248590 ==
782 16:30:33.248655 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 16:30:33.248713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 16:30:33.248770 [CA 0] Center 37 (6~68) winsize 63
785 16:30:33.248826 [CA 1] Center 37 (6~68) winsize 63
786 16:30:33.248882 [CA 2] Center 34 (4~65) winsize 62
787 16:30:33.248938 [CA 3] Center 34 (4~65) winsize 62
788 16:30:33.248995 [CA 4] Center 34 (4~64) winsize 61
789 16:30:33.249051 [CA 5] Center 33 (3~64) winsize 62
790 16:30:33.249107
791 16:30:33.249162 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 16:30:33.249224
793 16:30:33.249281 [CATrainingPosCal] consider 1 rank data
794 16:30:33.249337 u2DelayCellTimex100 = 270/100 ps
795 16:30:33.249393 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
796 16:30:33.249448 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
797 16:30:33.249504 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 16:30:33.249559 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 16:30:33.249615 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
800 16:30:33.249670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 16:30:33.249725
802 16:30:33.249781 CA PerBit enable=1, Macro0, CA PI delay=33
803 16:30:33.249836
804 16:30:33.249891 [CBTSetCACLKResult] CA Dly = 33
805 16:30:33.249946 CS Dly: 6 (0~37)
806 16:30:33.250001 ==
807 16:30:33.250056 Dram Type= 6, Freq= 0, CH_0, rank 1
808 16:30:33.250111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
809 16:30:33.250177 ==
810 16:30:33.250236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
811 16:30:33.250291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
812 16:30:33.250348 [CA 0] Center 37 (6~68) winsize 63
813 16:30:33.250403 [CA 1] Center 37 (7~68) winsize 62
814 16:30:33.250459 [CA 2] Center 34 (4~65) winsize 62
815 16:30:33.250514 [CA 3] Center 34 (4~65) winsize 62
816 16:30:33.250569 [CA 4] Center 33 (3~64) winsize 62
817 16:30:33.250625 [CA 5] Center 33 (3~64) winsize 62
818 16:30:33.250680
819 16:30:33.250735 [CmdBusTrainingLP45] Vref(ca) range 1: 34
820 16:30:33.250791
821 16:30:33.250845 [CATrainingPosCal] consider 2 rank data
822 16:30:33.250901 u2DelayCellTimex100 = 270/100 ps
823 16:30:33.250957 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
824 16:30:33.251013 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
825 16:30:33.251068 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
826 16:30:33.251124 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
827 16:30:33.251179 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
828 16:30:33.251235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
829 16:30:33.251291
830 16:30:33.251346 CA PerBit enable=1, Macro0, CA PI delay=33
831 16:30:33.251402
832 16:30:33.251457 [CBTSetCACLKResult] CA Dly = 33
833 16:30:33.251513 CS Dly: 6 (0~38)
834 16:30:33.251568
835 16:30:33.251623 ----->DramcWriteLeveling(PI) begin...
836 16:30:33.251680 ==
837 16:30:33.251735 Dram Type= 6, Freq= 0, CH_0, rank 0
838 16:30:33.251791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
839 16:30:33.251847 ==
840 16:30:33.251902 Write leveling (Byte 0): 34 => 34
841 16:30:33.251958 Write leveling (Byte 1): 32 => 32
842 16:30:33.252012 DramcWriteLeveling(PI) end<-----
843 16:30:33.252068
844 16:30:33.252123 ==
845 16:30:33.252178 Dram Type= 6, Freq= 0, CH_0, rank 0
846 16:30:33.252234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
847 16:30:33.252290 ==
848 16:30:33.252345 [Gating] SW mode calibration
849 16:30:33.252401 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
850 16:30:33.252457 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
851 16:30:33.252513 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 16:30:33.252570 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
853 16:30:33.252625 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 16:30:33.252693 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 16:30:33.252748 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 16:30:33.252802 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:30:33.252856 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:30:33.252910 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:30:33.252964 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:30:33.253033 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:30:33.253102 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:30:33.253157 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:30:33.253216 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:30:33.253277 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:30:33.253332 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:30:33.253386 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:30:33.253485 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 16:30:33.253540 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 16:30:33.253595 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
870 16:30:33.253650 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 16:30:33.253705 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 16:30:33.253794 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 16:30:33.253849 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:30:33.253908 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:30:33.253965 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 16:30:33.254055 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 16:30:33.254167 0 9 8 | B1->B0 | 2322 2c2c | 1 0 | (0 0) (0 0)
878 16:30:33.254269 0 9 12 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
879 16:30:33.254354 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 16:30:33.254637 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 16:30:33.254732 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:30:33.254822 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 16:30:33.254908 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 16:30:33.254999 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 16:30:33.255120 0 10 8 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 0)
886 16:30:33.255220 0 10 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
887 16:30:33.255296 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 16:30:33.255386 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 16:30:33.255472 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:30:33.255548 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:30:33.255605 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 16:30:33.255675 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
893 16:30:33.255763 0 11 8 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
894 16:30:33.255849 0 11 12 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
895 16:30:33.255934 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 16:30:33.256019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 16:30:33.256104 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:30:33.256189 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:30:33.256274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 16:30:33.256362 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 16:30:33.256447 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 16:30:33.256532 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 16:30:33.256617 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 16:30:33.256701 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 16:30:33.256786 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:30:33.256870 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:30:33.256955 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:30:33.257045 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:30:33.257133 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:30:33.257218 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:30:33.257306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:30:33.257395 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:30:33.257516 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:30:33.257600 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 16:30:33.257685 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 16:30:33.257769 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 16:30:33.257853 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
918 16:30:33.257937 Total UI for P1: 0, mck2ui 16
919 16:30:33.258022 best dqsien dly found for B0: ( 0, 14, 6)
920 16:30:33.258107 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 16:30:33.258227 Total UI for P1: 0, mck2ui 16
922 16:30:33.258313 best dqsien dly found for B1: ( 0, 14, 8)
923 16:30:33.258404 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
924 16:30:33.258496 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
925 16:30:33.258556
926 16:30:33.258617 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
927 16:30:33.258674 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
928 16:30:33.258728 [Gating] SW calibration Done
929 16:30:33.258786 ==
930 16:30:33.258849 Dram Type= 6, Freq= 0, CH_0, rank 0
931 16:30:33.258934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
932 16:30:33.259018 ==
933 16:30:33.259102 RX Vref Scan: 0
934 16:30:33.259186
935 16:30:33.259269 RX Vref 0 -> 0, step: 1
936 16:30:33.259352
937 16:30:33.259436 RX Delay -130 -> 252, step: 16
938 16:30:33.259506 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
939 16:30:33.259593 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
940 16:30:33.259678 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
941 16:30:33.259763 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
942 16:30:33.259847 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
943 16:30:33.259931 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
944 16:30:33.260015 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
945 16:30:33.260087 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
946 16:30:33.260142 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
947 16:30:33.260197 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
948 16:30:33.260252 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
949 16:30:33.260306 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
950 16:30:33.260361 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
951 16:30:33.260445 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
952 16:30:33.260499 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
953 16:30:33.260561 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
954 16:30:33.260616 ==
955 16:30:33.260671 Dram Type= 6, Freq= 0, CH_0, rank 0
956 16:30:33.260725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 16:30:33.260780 ==
958 16:30:33.260834 DQS Delay:
959 16:30:33.260887 DQS0 = 0, DQS1 = 0
960 16:30:33.260941 DQM Delay:
961 16:30:33.260995 DQM0 = 85, DQM1 = 71
962 16:30:33.261056 DQ Delay:
963 16:30:33.261111 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
964 16:30:33.261165 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
965 16:30:33.261220 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
966 16:30:33.261274 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
967 16:30:33.261328
968 16:30:33.261381
969 16:30:33.261434 ==
970 16:30:33.261488 Dram Type= 6, Freq= 0, CH_0, rank 0
971 16:30:33.261543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 16:30:33.261611 ==
973 16:30:33.261736
974 16:30:33.261820
975 16:30:33.261904 TX Vref Scan disable
976 16:30:33.261987 == TX Byte 0 ==
977 16:30:33.262089 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
978 16:30:33.262183 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
979 16:30:33.262256 == TX Byte 1 ==
980 16:30:33.262311 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 16:30:33.262366 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 16:30:33.262421 ==
983 16:30:33.262475 Dram Type= 6, Freq= 0, CH_0, rank 0
984 16:30:33.262530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
985 16:30:33.262585 ==
986 16:30:33.262646 TX Vref=22, minBit 3, minWin=27, winSum=444
987 16:30:33.262897 TX Vref=24, minBit 3, minWin=27, winSum=444
988 16:30:33.262965 TX Vref=26, minBit 4, minWin=27, winSum=448
989 16:30:33.263021 TX Vref=28, minBit 8, minWin=27, winSum=450
990 16:30:33.263094 TX Vref=30, minBit 10, minWin=27, winSum=451
991 16:30:33.263162 TX Vref=32, minBit 4, minWin=27, winSum=445
992 16:30:33.263218 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 30
993 16:30:33.263273
994 16:30:33.263327 Final TX Range 1 Vref 30
995 16:30:33.263382
996 16:30:33.263436 ==
997 16:30:33.263491 Dram Type= 6, Freq= 0, CH_0, rank 0
998 16:30:33.263553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
999 16:30:33.263674 ==
1000 16:30:33.263758
1001 16:30:33.263816
1002 16:30:33.263871 TX Vref Scan disable
1003 16:30:33.263926 == TX Byte 0 ==
1004 16:30:33.263980 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1005 16:30:33.264034 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1006 16:30:33.264092 == TX Byte 1 ==
1007 16:30:33.264209 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1008 16:30:33.264331 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1009 16:30:33.264415
1010 16:30:33.264505 [DATLAT]
1011 16:30:33.264593 Freq=800, CH0 RK0
1012 16:30:33.264689
1013 16:30:33.264775 DATLAT Default: 0xa
1014 16:30:33.264859 0, 0xFFFF, sum = 0
1015 16:30:33.264922 1, 0xFFFF, sum = 0
1016 16:30:33.264978 2, 0xFFFF, sum = 0
1017 16:30:33.265034 3, 0xFFFF, sum = 0
1018 16:30:33.265112 4, 0xFFFF, sum = 0
1019 16:30:33.265198 5, 0xFFFF, sum = 0
1020 16:30:33.265287 6, 0xFFFF, sum = 0
1021 16:30:33.265372 7, 0xFFFF, sum = 0
1022 16:30:33.265459 8, 0xFFFF, sum = 0
1023 16:30:33.265544 9, 0x0, sum = 1
1024 16:30:33.265630 10, 0x0, sum = 2
1025 16:30:33.265723 11, 0x0, sum = 3
1026 16:30:33.265820 12, 0x0, sum = 4
1027 16:30:33.265917 best_step = 10
1028 16:30:33.266001
1029 16:30:33.266084 ==
1030 16:30:33.266195 Dram Type= 6, Freq= 0, CH_0, rank 0
1031 16:30:33.266297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1032 16:30:33.266381 ==
1033 16:30:33.266471 RX Vref Scan: 1
1034 16:30:33.266555
1035 16:30:33.266638 Set Vref Range= 32 -> 127
1036 16:30:33.266720
1037 16:30:33.266808 RX Vref 32 -> 127, step: 1
1038 16:30:33.266867
1039 16:30:33.266921 RX Delay -111 -> 252, step: 8
1040 16:30:33.266975
1041 16:30:33.267028 Set Vref, RX VrefLevel [Byte0]: 32
1042 16:30:33.267082 [Byte1]: 32
1043 16:30:33.267136
1044 16:30:33.267189 Set Vref, RX VrefLevel [Byte0]: 33
1045 16:30:33.267243 [Byte1]: 33
1046 16:30:33.267329
1047 16:30:33.267417 Set Vref, RX VrefLevel [Byte0]: 34
1048 16:30:33.267501 [Byte1]: 34
1049 16:30:33.267587
1050 16:30:33.267660 Set Vref, RX VrefLevel [Byte0]: 35
1051 16:30:33.267715 [Byte1]: 35
1052 16:30:33.267770
1053 16:30:33.267823 Set Vref, RX VrefLevel [Byte0]: 36
1054 16:30:33.267876 [Byte1]: 36
1055 16:30:33.267930
1056 16:30:33.267983 Set Vref, RX VrefLevel [Byte0]: 37
1057 16:30:33.268047 [Byte1]: 37
1058 16:30:33.268134
1059 16:30:33.268217 Set Vref, RX VrefLevel [Byte0]: 38
1060 16:30:33.268300 [Byte1]: 38
1061 16:30:33.268382
1062 16:30:33.268469 Set Vref, RX VrefLevel [Byte0]: 39
1063 16:30:33.268568 [Byte1]: 39
1064 16:30:33.268652
1065 16:30:33.268735 Set Vref, RX VrefLevel [Byte0]: 40
1066 16:30:33.268819 [Byte1]: 40
1067 16:30:33.268928
1068 16:30:33.269014 Set Vref, RX VrefLevel [Byte0]: 41
1069 16:30:33.269098 [Byte1]: 41
1070 16:30:33.269180
1071 16:30:33.269262 Set Vref, RX VrefLevel [Byte0]: 42
1072 16:30:33.269345 [Byte1]: 42
1073 16:30:33.269427
1074 16:30:33.269510 Set Vref, RX VrefLevel [Byte0]: 43
1075 16:30:33.269593 [Byte1]: 43
1076 16:30:33.269675
1077 16:30:33.269757 Set Vref, RX VrefLevel [Byte0]: 44
1078 16:30:33.269840 [Byte1]: 44
1079 16:30:33.269922
1080 16:30:33.270004 Set Vref, RX VrefLevel [Byte0]: 45
1081 16:30:33.270087 [Byte1]: 45
1082 16:30:33.270175
1083 16:30:33.270264 Set Vref, RX VrefLevel [Byte0]: 46
1084 16:30:33.270319 [Byte1]: 46
1085 16:30:33.270372
1086 16:30:33.270426 Set Vref, RX VrefLevel [Byte0]: 47
1087 16:30:33.270479 [Byte1]: 47
1088 16:30:33.270533
1089 16:30:33.270586 Set Vref, RX VrefLevel [Byte0]: 48
1090 16:30:33.270639 [Byte1]: 48
1091 16:30:33.270693
1092 16:30:33.270746 Set Vref, RX VrefLevel [Byte0]: 49
1093 16:30:33.270799 [Byte1]: 49
1094 16:30:33.270852
1095 16:30:33.270905 Set Vref, RX VrefLevel [Byte0]: 50
1096 16:30:33.270959 [Byte1]: 50
1097 16:30:33.271012
1098 16:30:33.271065 Set Vref, RX VrefLevel [Byte0]: 51
1099 16:30:33.271118 [Byte1]: 51
1100 16:30:33.271172
1101 16:30:33.271225 Set Vref, RX VrefLevel [Byte0]: 52
1102 16:30:33.271278 [Byte1]: 52
1103 16:30:33.271331
1104 16:30:33.271385 Set Vref, RX VrefLevel [Byte0]: 53
1105 16:30:33.271438 [Byte1]: 53
1106 16:30:33.271492
1107 16:30:33.271544 Set Vref, RX VrefLevel [Byte0]: 54
1108 16:30:33.271598 [Byte1]: 54
1109 16:30:33.271652
1110 16:30:33.271705 Set Vref, RX VrefLevel [Byte0]: 55
1111 16:30:33.271758 [Byte1]: 55
1112 16:30:33.271812
1113 16:30:33.271865 Set Vref, RX VrefLevel [Byte0]: 56
1114 16:30:33.271918 [Byte1]: 56
1115 16:30:33.271971
1116 16:30:33.272024 Set Vref, RX VrefLevel [Byte0]: 57
1117 16:30:33.272077 [Byte1]: 57
1118 16:30:33.272130
1119 16:30:33.272184 Set Vref, RX VrefLevel [Byte0]: 58
1120 16:30:33.272237 [Byte1]: 58
1121 16:30:33.272291
1122 16:30:33.272343 Set Vref, RX VrefLevel [Byte0]: 59
1123 16:30:33.272396 [Byte1]: 59
1124 16:30:33.272450
1125 16:30:33.272503 Set Vref, RX VrefLevel [Byte0]: 60
1126 16:30:33.272556 [Byte1]: 60
1127 16:30:33.272609
1128 16:30:33.272662 Set Vref, RX VrefLevel [Byte0]: 61
1129 16:30:33.272715 [Byte1]: 61
1130 16:30:33.272768
1131 16:30:33.272849 Set Vref, RX VrefLevel [Byte0]: 62
1132 16:30:33.272902 [Byte1]: 62
1133 16:30:33.272955
1134 16:30:33.273008 Set Vref, RX VrefLevel [Byte0]: 63
1135 16:30:33.273061 [Byte1]: 63
1136 16:30:33.273115
1137 16:30:33.273167 Set Vref, RX VrefLevel [Byte0]: 64
1138 16:30:33.273221 [Byte1]: 64
1139 16:30:33.273274
1140 16:30:33.273327 Set Vref, RX VrefLevel [Byte0]: 65
1141 16:30:33.273380 [Byte1]: 65
1142 16:30:33.273433
1143 16:30:33.273486 Set Vref, RX VrefLevel [Byte0]: 66
1144 16:30:33.273539 [Byte1]: 66
1145 16:30:33.273592
1146 16:30:33.273645 Set Vref, RX VrefLevel [Byte0]: 67
1147 16:30:33.273697 [Byte1]: 67
1148 16:30:33.273750
1149 16:30:33.273803 Set Vref, RX VrefLevel [Byte0]: 68
1150 16:30:33.273856 [Byte1]: 68
1151 16:30:33.273910
1152 16:30:33.273962 Set Vref, RX VrefLevel [Byte0]: 69
1153 16:30:33.274016 [Byte1]: 69
1154 16:30:33.274070
1155 16:30:33.274337 Set Vref, RX VrefLevel [Byte0]: 70
1156 16:30:33.274433 [Byte1]: 70
1157 16:30:33.274488
1158 16:30:33.274542 Set Vref, RX VrefLevel [Byte0]: 71
1159 16:30:33.274642 [Byte1]: 71
1160 16:30:33.274710
1161 16:30:33.274763 Set Vref, RX VrefLevel [Byte0]: 72
1162 16:30:33.274816 [Byte1]: 72
1163 16:30:33.274870
1164 16:30:33.274924 Set Vref, RX VrefLevel [Byte0]: 73
1165 16:30:33.274977 [Byte1]: 73
1166 16:30:33.275031
1167 16:30:33.275084 Set Vref, RX VrefLevel [Byte0]: 74
1168 16:30:33.275137 [Byte1]: 74
1169 16:30:33.275190
1170 16:30:33.275243 Set Vref, RX VrefLevel [Byte0]: 75
1171 16:30:33.275310 [Byte1]: 75
1172 16:30:33.275379
1173 16:30:33.275432 Set Vref, RX VrefLevel [Byte0]: 76
1174 16:30:33.275485 [Byte1]: 76
1175 16:30:33.275538
1176 16:30:33.275592 Set Vref, RX VrefLevel [Byte0]: 77
1177 16:30:33.275645 [Byte1]: 77
1178 16:30:33.275699
1179 16:30:33.275752 Set Vref, RX VrefLevel [Byte0]: 78
1180 16:30:33.275805 [Byte1]: 78
1181 16:30:33.275859
1182 16:30:33.275912 Set Vref, RX VrefLevel [Byte0]: 79
1183 16:30:33.275965 [Byte1]: 79
1184 16:30:33.276018
1185 16:30:33.276071 Final RX Vref Byte 0 = 63 to rank0
1186 16:30:33.276125 Final RX Vref Byte 1 = 51 to rank0
1187 16:30:33.276178 Final RX Vref Byte 0 = 63 to rank1
1188 16:30:33.276231 Final RX Vref Byte 1 = 51 to rank1==
1189 16:30:33.276285 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 16:30:33.276339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 16:30:33.276393 ==
1192 16:30:33.276446 DQS Delay:
1193 16:30:33.276500 DQS0 = 0, DQS1 = 0
1194 16:30:33.276554 DQM Delay:
1195 16:30:33.276607 DQM0 = 87, DQM1 = 76
1196 16:30:33.276661 DQ Delay:
1197 16:30:33.276715 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1198 16:30:33.276768 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1199 16:30:33.276822 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1200 16:30:33.276875 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1201 16:30:33.276928
1202 16:30:33.276981
1203 16:30:33.277034 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1204 16:30:33.277089 CH0 RK0: MR19=606, MR18=4729
1205 16:30:33.277171 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1206 16:30:33.277226
1207 16:30:33.277279 ----->DramcWriteLeveling(PI) begin...
1208 16:30:33.277334 ==
1209 16:30:33.277387 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 16:30:33.277441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 16:30:33.277495 ==
1212 16:30:33.277548 Write leveling (Byte 0): 32 => 32
1213 16:30:33.277602 Write leveling (Byte 1): 30 => 30
1214 16:30:33.277656 DramcWriteLeveling(PI) end<-----
1215 16:30:33.277710
1216 16:30:33.277762 ==
1217 16:30:33.277814 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 16:30:33.277867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 16:30:33.277921 ==
1220 16:30:33.277974 [Gating] SW mode calibration
1221 16:30:33.278027 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 16:30:33.278081 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 16:30:33.278135 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 16:30:33.278218 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 16:30:33.278286 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1226 16:30:33.278340 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:30:33.278394 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:30:33.278447 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:30:33.278500 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:30:33.278554 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:30:33.278607 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:30:33.278661 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 16:30:33.278714 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 16:30:33.278767 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 16:30:33.278821 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 16:30:33.278904 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 16:30:33.278957 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 16:30:33.279011 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 16:30:33.279064 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 16:30:33.279117 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1241 16:30:33.279170 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1242 16:30:33.279239 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 16:30:33.279308 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 16:30:33.279361 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 16:30:33.279414 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 16:30:33.279468 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 16:30:33.279521 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 16:30:33.279575 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 16:30:33.279628 0 9 8 | B1->B0 | 2322 2c2c | 1 1 | (1 1) (0 0)
1250 16:30:33.279681 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 16:30:33.279735 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 16:30:33.279788 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 16:30:33.279841 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 16:30:33.279895 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 16:30:33.279948 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 16:30:33.280002 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
1257 16:30:33.280055 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (1 0)
1258 16:30:33.280108 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
1259 16:30:33.280162 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 16:30:33.280215 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 16:30:33.280269 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 16:30:33.280322 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 16:30:33.280376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 16:30:33.280429 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 16:30:33.280671 0 11 8 | B1->B0 | 2f2f 3939 | 0 1 | (0 0) (0 0)
1266 16:30:33.280733 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 16:30:33.280787 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 16:30:33.280841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 16:30:33.280895 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 16:30:33.280948 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 16:30:33.281002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 16:30:33.281055 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 16:30:33.281108 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 16:30:33.281161 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1275 16:30:33.281231 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 16:30:33.281298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 16:30:33.281352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 16:30:33.281405 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 16:30:33.281459 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 16:30:33.281512 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 16:30:33.281566 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 16:30:33.281620 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 16:30:33.281674 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 16:30:33.281727 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 16:30:33.281780 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 16:30:33.281834 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 16:30:33.281887 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 16:30:33.281940 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 16:30:33.281994 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1290 16:30:33.282047 Total UI for P1: 0, mck2ui 16
1291 16:30:33.282117 best dqsien dly found for B0: ( 0, 14, 6)
1292 16:30:33.282183 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1293 16:30:33.282252 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1294 16:30:33.282306 Total UI for P1: 0, mck2ui 16
1295 16:30:33.282360 best dqsien dly found for B1: ( 0, 14, 10)
1296 16:30:33.282414 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1297 16:30:33.282468 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1298 16:30:33.282521
1299 16:30:33.282574 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1300 16:30:33.282628 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1301 16:30:33.282681 [Gating] SW calibration Done
1302 16:30:33.282735 ==
1303 16:30:33.282788 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 16:30:33.282842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 16:30:33.282896 ==
1306 16:30:33.282949 RX Vref Scan: 0
1307 16:30:33.283002
1308 16:30:33.283056 RX Vref 0 -> 0, step: 1
1309 16:30:33.283108
1310 16:30:33.283161 RX Delay -130 -> 252, step: 16
1311 16:30:33.283214 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1312 16:30:33.283268 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1313 16:30:33.283322 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1314 16:30:33.283376 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1315 16:30:33.283429 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1316 16:30:33.283483 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1317 16:30:33.283537 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1318 16:30:33.283590 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1319 16:30:33.283643 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1320 16:30:33.283697 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1321 16:30:33.283749 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1322 16:30:33.283802 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1323 16:30:33.283856 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1324 16:30:33.283909 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1325 16:30:33.283962 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1326 16:30:33.284015 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1327 16:30:33.284069 ==
1328 16:30:33.284122 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 16:30:33.284175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 16:30:33.284229 ==
1331 16:30:33.284282 DQS Delay:
1332 16:30:33.284335 DQS0 = 0, DQS1 = 0
1333 16:30:33.284388 DQM Delay:
1334 16:30:33.284441 DQM0 = 85, DQM1 = 77
1335 16:30:33.284495 DQ Delay:
1336 16:30:33.284547 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1337 16:30:33.284630 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1338 16:30:33.284683 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1339 16:30:33.284736 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1340 16:30:33.284790
1341 16:30:33.284843
1342 16:30:33.284896 ==
1343 16:30:33.284948 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 16:30:33.285002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 16:30:33.285056 ==
1346 16:30:33.285109
1347 16:30:33.285161
1348 16:30:33.285250 TX Vref Scan disable
1349 16:30:33.285303 == TX Byte 0 ==
1350 16:30:33.285357 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1351 16:30:33.285411 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1352 16:30:33.285464 == TX Byte 1 ==
1353 16:30:33.285518 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1354 16:30:33.285571 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1355 16:30:33.285624 ==
1356 16:30:33.285677 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 16:30:33.285731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 16:30:33.285785 ==
1359 16:30:33.285838 TX Vref=22, minBit 5, minWin=27, winSum=446
1360 16:30:33.285891 TX Vref=24, minBit 11, minWin=27, winSum=446
1361 16:30:33.285945 TX Vref=26, minBit 9, minWin=27, winSum=449
1362 16:30:33.285998 TX Vref=28, minBit 9, minWin=27, winSum=449
1363 16:30:33.286051 TX Vref=30, minBit 9, minWin=27, winSum=445
1364 16:30:33.286104 TX Vref=32, minBit 8, minWin=27, winSum=445
1365 16:30:33.286158 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 26
1366 16:30:33.286257
1367 16:30:33.286310 Final TX Range 1 Vref 26
1368 16:30:33.286365
1369 16:30:33.286417 ==
1370 16:30:33.286470 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 16:30:33.286524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 16:30:33.286577 ==
1373 16:30:33.286629
1374 16:30:33.286682
1375 16:30:33.286734 TX Vref Scan disable
1376 16:30:33.286786 == TX Byte 0 ==
1377 16:30:33.286839 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1378 16:30:33.286893 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1379 16:30:33.286946 == TX Byte 1 ==
1380 16:30:33.286999 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1381 16:30:33.287053 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1382 16:30:33.287106
1383 16:30:33.287353 [DATLAT]
1384 16:30:33.287412 Freq=800, CH0 RK1
1385 16:30:33.287466
1386 16:30:33.287519 DATLAT Default: 0xa
1387 16:30:33.287572 0, 0xFFFF, sum = 0
1388 16:30:33.287627 1, 0xFFFF, sum = 0
1389 16:30:33.287681 2, 0xFFFF, sum = 0
1390 16:30:33.287734 3, 0xFFFF, sum = 0
1391 16:30:33.287788 4, 0xFFFF, sum = 0
1392 16:30:33.287865 5, 0xFFFF, sum = 0
1393 16:30:33.287932 6, 0xFFFF, sum = 0
1394 16:30:33.287986 7, 0xFFFF, sum = 0
1395 16:30:33.288055 8, 0xFFFF, sum = 0
1396 16:30:33.288123 9, 0x0, sum = 1
1397 16:30:33.288176 10, 0x0, sum = 2
1398 16:30:33.288230 11, 0x0, sum = 3
1399 16:30:33.288283 12, 0x0, sum = 4
1400 16:30:33.288336 best_step = 10
1401 16:30:33.288389
1402 16:30:33.288442 ==
1403 16:30:33.288494 Dram Type= 6, Freq= 0, CH_0, rank 1
1404 16:30:33.288549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 16:30:33.288636 ==
1406 16:30:33.288688 RX Vref Scan: 0
1407 16:30:33.288741
1408 16:30:33.288793 RX Vref 0 -> 0, step: 1
1409 16:30:33.288846
1410 16:30:33.288898 RX Delay -111 -> 252, step: 8
1411 16:30:33.288952 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1412 16:30:33.289005 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1413 16:30:33.289059 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1414 16:30:33.289112 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1415 16:30:33.289165 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1416 16:30:33.289217 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1417 16:30:33.289271 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1418 16:30:33.289323 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1419 16:30:33.289377 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1420 16:30:33.289429 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1421 16:30:33.289481 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1422 16:30:33.289534 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1423 16:30:33.289588 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1424 16:30:33.289641 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1425 16:30:33.289693 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1426 16:30:33.289746 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1427 16:30:33.289799 ==
1428 16:30:33.289852 Dram Type= 6, Freq= 0, CH_0, rank 1
1429 16:30:33.289904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 16:30:33.289958 ==
1431 16:30:33.290010 DQS Delay:
1432 16:30:33.290062 DQS0 = 0, DQS1 = 0
1433 16:30:33.290115 DQM Delay:
1434 16:30:33.290175 DQM0 = 84, DQM1 = 76
1435 16:30:33.290269 DQ Delay:
1436 16:30:33.290323 DQ0 =80, DQ1 =92, DQ2 =76, DQ3 =80
1437 16:30:33.290376 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1438 16:30:33.290429 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
1439 16:30:33.290482 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1440 16:30:33.290535
1441 16:30:33.290587
1442 16:30:33.290672 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1443 16:30:33.290761 CH0 RK1: MR19=606, MR18=3C03
1444 16:30:33.290845 CH0_RK1: MR19=0x606, MR18=0x3C03, DQSOSC=394, MR23=63, INC=95, DEC=63
1445 16:30:33.290928 [RxdqsGatingPostProcess] freq 800
1446 16:30:33.291016 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1447 16:30:33.291082 Pre-setting of DQS Precalculation
1448 16:30:33.291137 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1449 16:30:33.291191 ==
1450 16:30:33.291244 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 16:30:33.291297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 16:30:33.291351 ==
1453 16:30:33.291403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 16:30:33.291457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 16:30:33.291530 [CA 0] Center 36 (6~67) winsize 62
1456 16:30:33.291602 [CA 1] Center 36 (6~67) winsize 62
1457 16:30:33.291657 [CA 2] Center 34 (4~65) winsize 62
1458 16:30:33.291711 [CA 3] Center 34 (3~65) winsize 63
1459 16:30:33.291764 [CA 4] Center 34 (4~65) winsize 62
1460 16:30:33.291818 [CA 5] Center 34 (3~65) winsize 63
1461 16:30:33.291871
1462 16:30:33.291933 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1463 16:30:33.292014
1464 16:30:33.292070 [CATrainingPosCal] consider 1 rank data
1465 16:30:33.292128 u2DelayCellTimex100 = 270/100 ps
1466 16:30:33.292184 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 16:30:33.292238 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1468 16:30:33.292291 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 16:30:33.292365 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1470 16:30:33.292448 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 16:30:33.292532 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1472 16:30:33.292691
1473 16:30:33.292789 CA PerBit enable=1, Macro0, CA PI delay=34
1474 16:30:33.292842
1475 16:30:33.292895 [CBTSetCACLKResult] CA Dly = 34
1476 16:30:33.292948 CS Dly: 4 (0~35)
1477 16:30:33.293002 ==
1478 16:30:33.293055 Dram Type= 6, Freq= 0, CH_1, rank 1
1479 16:30:33.293108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1480 16:30:33.293162 ==
1481 16:30:33.293216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1482 16:30:33.293279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1483 16:30:33.293334 [CA 0] Center 37 (7~67) winsize 61
1484 16:30:33.293387 [CA 1] Center 37 (6~68) winsize 63
1485 16:30:33.293440 [CA 2] Center 34 (4~65) winsize 62
1486 16:30:33.293493 [CA 3] Center 34 (3~65) winsize 63
1487 16:30:33.293546 [CA 4] Center 34 (4~65) winsize 62
1488 16:30:33.293599 [CA 5] Center 34 (3~65) winsize 63
1489 16:30:33.293652
1490 16:30:33.293704 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1491 16:30:33.293757
1492 16:30:33.293809 [CATrainingPosCal] consider 2 rank data
1493 16:30:33.293861 u2DelayCellTimex100 = 270/100 ps
1494 16:30:33.293914 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1495 16:30:33.293967 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1496 16:30:33.294020 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 16:30:33.294072 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1498 16:30:33.294125 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1499 16:30:33.294224 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1500 16:30:33.294279
1501 16:30:33.294332 CA PerBit enable=1, Macro0, CA PI delay=34
1502 16:30:33.294386
1503 16:30:33.294438 [CBTSetCACLKResult] CA Dly = 34
1504 16:30:33.294491 CS Dly: 5 (0~38)
1505 16:30:33.294544
1506 16:30:33.294597 ----->DramcWriteLeveling(PI) begin...
1507 16:30:33.294651 ==
1508 16:30:33.294705 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 16:30:33.294758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 16:30:33.294811 ==
1511 16:30:33.294864 Write leveling (Byte 0): 27 => 27
1512 16:30:33.294923 Write leveling (Byte 1): 30 => 30
1513 16:30:33.294977 DramcWriteLeveling(PI) end<-----
1514 16:30:33.295030
1515 16:30:33.295083 ==
1516 16:30:33.295135 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 16:30:33.295381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 16:30:33.295442 ==
1519 16:30:33.295497 [Gating] SW mode calibration
1520 16:30:33.295559 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1521 16:30:33.295625 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1522 16:30:33.295708 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1523 16:30:33.295765 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1524 16:30:33.295819 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:30:33.295872 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:30:33.295926 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:30:33.295979 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:30:33.296033 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:30:33.296085 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 16:30:33.296139 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 16:30:33.296192 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 16:30:33.296286 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 16:30:33.296370 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 16:30:33.296458 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 16:30:33.296543 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 16:30:33.296630 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 16:30:33.296716 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 16:30:33.296773 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1539 16:30:33.296831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1540 16:30:33.296914 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 16:30:33.296997 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 16:30:33.297080 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 16:30:33.297166 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 16:30:33.297253 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 16:30:33.297336 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 16:30:33.297419 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 16:30:33.297501 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 16:30:33.297593 0 9 8 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
1549 16:30:33.297666 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 16:30:33.297722 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 16:30:33.297776 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 16:30:33.297861 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 16:30:33.297944 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 16:30:33.298030 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 16:30:33.298113 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
1556 16:30:33.298214 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1557 16:30:33.298302 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 16:30:33.298389 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 16:30:33.298476 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 16:30:33.298560 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 16:30:33.298654 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 16:30:33.298739 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 16:30:33.298829 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1564 16:30:33.298932 0 11 8 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
1565 16:30:33.299035 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 16:30:33.299136 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 16:30:33.299237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 16:30:33.299335 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 16:30:33.299437 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 16:30:33.299522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 16:30:33.299617 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 16:30:33.299736 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 16:30:33.299824 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 16:30:33.299908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 16:30:33.299989 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 16:30:33.300047 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 16:30:33.300102 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 16:30:33.300169 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 16:30:33.300224 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 16:30:33.300278 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 16:30:33.300335 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 16:30:33.300389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 16:30:33.300443 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 16:30:33.300504 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 16:30:33.300559 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 16:30:33.300613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1587 16:30:33.300667 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 16:30:33.300720 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1589 16:30:33.300773 Total UI for P1: 0, mck2ui 16
1590 16:30:33.300827 best dqsien dly found for B0: ( 0, 14, 6)
1591 16:30:33.300880 Total UI for P1: 0, mck2ui 16
1592 16:30:33.300934 best dqsien dly found for B1: ( 0, 14, 6)
1593 16:30:33.300987 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1594 16:30:33.301041 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1595 16:30:33.301094
1596 16:30:33.301146 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1597 16:30:33.301199 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1598 16:30:33.301253 [Gating] SW calibration Done
1599 16:30:33.301306 ==
1600 16:30:33.301359 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 16:30:33.301412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 16:30:33.301466 ==
1603 16:30:33.301518 RX Vref Scan: 0
1604 16:30:33.301571
1605 16:30:33.301624 RX Vref 0 -> 0, step: 1
1606 16:30:33.301676
1607 16:30:33.301932 RX Delay -130 -> 252, step: 16
1608 16:30:33.302024 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1609 16:30:33.302128 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1610 16:30:33.302223 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1611 16:30:33.302280 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1612 16:30:33.302334 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1613 16:30:33.302387 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1614 16:30:33.302440 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1615 16:30:33.302493 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1616 16:30:33.302547 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1617 16:30:33.302600 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1618 16:30:33.302653 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1619 16:30:33.302706 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1620 16:30:33.302763 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1621 16:30:33.302817 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1622 16:30:33.302870 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1623 16:30:33.302923 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1624 16:30:33.302976 ==
1625 16:30:33.303030 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 16:30:33.303084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 16:30:33.303136 ==
1628 16:30:33.303189 DQS Delay:
1629 16:30:33.303241 DQS0 = 0, DQS1 = 0
1630 16:30:33.303294 DQM Delay:
1631 16:30:33.303346 DQM0 = 89, DQM1 = 79
1632 16:30:33.303399 DQ Delay:
1633 16:30:33.303452 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1634 16:30:33.303506 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1635 16:30:33.303558 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1636 16:30:33.303610 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1637 16:30:33.303663
1638 16:30:33.303750
1639 16:30:33.303808 ==
1640 16:30:33.303861 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 16:30:33.303915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 16:30:33.303968 ==
1643 16:30:33.304021
1644 16:30:33.304073
1645 16:30:33.304126 TX Vref Scan disable
1646 16:30:33.304179 == TX Byte 0 ==
1647 16:30:33.304232 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1648 16:30:33.304285 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1649 16:30:33.304339 == TX Byte 1 ==
1650 16:30:33.304391 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1651 16:30:33.304470 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1652 16:30:33.304556 ==
1653 16:30:33.304640 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 16:30:33.304727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 16:30:33.304809 ==
1656 16:30:33.304896 TX Vref=22, minBit 10, minWin=26, winSum=441
1657 16:30:33.304963 TX Vref=24, minBit 8, minWin=27, winSum=449
1658 16:30:33.305018 TX Vref=26, minBit 9, minWin=27, winSum=450
1659 16:30:33.305104 TX Vref=28, minBit 9, minWin=27, winSum=453
1660 16:30:33.305187 TX Vref=30, minBit 9, minWin=27, winSum=452
1661 16:30:33.305272 TX Vref=32, minBit 8, minWin=27, winSum=448
1662 16:30:33.305376 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 28
1663 16:30:33.305510
1664 16:30:33.305593 Final TX Range 1 Vref 28
1665 16:30:33.305678
1666 16:30:33.305760 ==
1667 16:30:33.305882 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 16:30:33.305967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 16:30:33.306051 ==
1670 16:30:33.306133
1671 16:30:33.306238
1672 16:30:33.306293 TX Vref Scan disable
1673 16:30:33.306347 == TX Byte 0 ==
1674 16:30:33.306403 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1675 16:30:33.306457 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1676 16:30:33.306511 == TX Byte 1 ==
1677 16:30:33.306564 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1678 16:30:33.306617 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1679 16:30:33.306670
1680 16:30:33.306723 [DATLAT]
1681 16:30:33.306774 Freq=800, CH1 RK0
1682 16:30:33.306828
1683 16:30:33.306880 DATLAT Default: 0xa
1684 16:30:33.306934 0, 0xFFFF, sum = 0
1685 16:30:33.306988 1, 0xFFFF, sum = 0
1686 16:30:33.307041 2, 0xFFFF, sum = 0
1687 16:30:33.307095 3, 0xFFFF, sum = 0
1688 16:30:33.307149 4, 0xFFFF, sum = 0
1689 16:30:33.307206 5, 0xFFFF, sum = 0
1690 16:30:33.307260 6, 0xFFFF, sum = 0
1691 16:30:33.307314 7, 0xFFFF, sum = 0
1692 16:30:33.307369 8, 0xFFFF, sum = 0
1693 16:30:33.307423 9, 0x0, sum = 1
1694 16:30:33.307477 10, 0x0, sum = 2
1695 16:30:33.307531 11, 0x0, sum = 3
1696 16:30:33.307592 12, 0x0, sum = 4
1697 16:30:33.307676 best_step = 10
1698 16:30:33.307759
1699 16:30:33.307844 ==
1700 16:30:33.307931 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 16:30:33.308018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 16:30:33.308102 ==
1703 16:30:33.308184 RX Vref Scan: 1
1704 16:30:33.308267
1705 16:30:33.308352 Set Vref Range= 32 -> 127
1706 16:30:33.308438
1707 16:30:33.308525 RX Vref 32 -> 127, step: 1
1708 16:30:33.308606
1709 16:30:33.308689 RX Delay -95 -> 252, step: 8
1710 16:30:33.308770
1711 16:30:33.308864 Set Vref, RX VrefLevel [Byte0]: 32
1712 16:30:33.308954 [Byte1]: 32
1713 16:30:33.309045
1714 16:30:33.309129 Set Vref, RX VrefLevel [Byte0]: 33
1715 16:30:33.309213 [Byte1]: 33
1716 16:30:33.309301
1717 16:30:33.309393 Set Vref, RX VrefLevel [Byte0]: 34
1718 16:30:33.309476 [Byte1]: 34
1719 16:30:33.309566
1720 16:30:33.309651 Set Vref, RX VrefLevel [Byte0]: 35
1721 16:30:33.309738 [Byte1]: 35
1722 16:30:33.309821
1723 16:30:33.309904 Set Vref, RX VrefLevel [Byte0]: 36
1724 16:30:33.309987 [Byte1]: 36
1725 16:30:33.310068
1726 16:30:33.310157 Set Vref, RX VrefLevel [Byte0]: 37
1727 16:30:33.310287 [Byte1]: 37
1728 16:30:33.310369
1729 16:30:33.310451 Set Vref, RX VrefLevel [Byte0]: 38
1730 16:30:33.310539 [Byte1]: 38
1731 16:30:33.310628
1732 16:30:33.310711 Set Vref, RX VrefLevel [Byte0]: 39
1733 16:30:33.310793 [Byte1]: 39
1734 16:30:33.310875
1735 16:30:33.310957 Set Vref, RX VrefLevel [Byte0]: 40
1736 16:30:33.311039 [Byte1]: 40
1737 16:30:33.311123
1738 16:30:33.311210 Set Vref, RX VrefLevel [Byte0]: 41
1739 16:30:33.311293 [Byte1]: 41
1740 16:30:33.311376
1741 16:30:33.311458 Set Vref, RX VrefLevel [Byte0]: 42
1742 16:30:33.311546 [Byte1]: 42
1743 16:30:33.311629
1744 16:30:33.311684 Set Vref, RX VrefLevel [Byte0]: 43
1745 16:30:33.311738 [Byte1]: 43
1746 16:30:33.311790
1747 16:30:33.311850 Set Vref, RX VrefLevel [Byte0]: 44
1748 16:30:33.311933 [Byte1]: 44
1749 16:30:33.312015
1750 16:30:33.312104 Set Vref, RX VrefLevel [Byte0]: 45
1751 16:30:33.312190 [Byte1]: 45
1752 16:30:33.312272
1753 16:30:33.312354 Set Vref, RX VrefLevel [Byte0]: 46
1754 16:30:33.312437 [Byte1]: 46
1755 16:30:33.312523
1756 16:30:33.312598 Set Vref, RX VrefLevel [Byte0]: 47
1757 16:30:33.312652 [Byte1]: 47
1758 16:30:33.312720
1759 16:30:33.312837 Set Vref, RX VrefLevel [Byte0]: 48
1760 16:30:33.312920 [Byte1]: 48
1761 16:30:33.313007
1762 16:30:33.313295 Set Vref, RX VrefLevel [Byte0]: 49
1763 16:30:33.313388 [Byte1]: 49
1764 16:30:33.313476
1765 16:30:33.313559 Set Vref, RX VrefLevel [Byte0]: 50
1766 16:30:33.313642 [Byte1]: 50
1767 16:30:33.313724
1768 16:30:33.313806 Set Vref, RX VrefLevel [Byte0]: 51
1769 16:30:33.313892 [Byte1]: 51
1770 16:30:33.313978
1771 16:30:33.314067 Set Vref, RX VrefLevel [Byte0]: 52
1772 16:30:33.314150 [Byte1]: 52
1773 16:30:33.314283
1774 16:30:33.314345 Set Vref, RX VrefLevel [Byte0]: 53
1775 16:30:33.314400 [Byte1]: 53
1776 16:30:33.314454
1777 16:30:33.314507 Set Vref, RX VrefLevel [Byte0]: 54
1778 16:30:33.314560 [Byte1]: 54
1779 16:30:33.314613
1780 16:30:33.314666 Set Vref, RX VrefLevel [Byte0]: 55
1781 16:30:33.314728 [Byte1]: 55
1782 16:30:33.314810
1783 16:30:33.314896 Set Vref, RX VrefLevel [Byte0]: 56
1784 16:30:33.314988 [Byte1]: 56
1785 16:30:33.315070
1786 16:30:33.315152 Set Vref, RX VrefLevel [Byte0]: 57
1787 16:30:33.315239 [Byte1]: 57
1788 16:30:33.315324
1789 16:30:33.315406 Set Vref, RX VrefLevel [Byte0]: 58
1790 16:30:33.315488 [Byte1]: 58
1791 16:30:33.315573
1792 16:30:33.315659 Set Vref, RX VrefLevel [Byte0]: 59
1793 16:30:33.315742 [Byte1]: 59
1794 16:30:33.315823
1795 16:30:33.315910 Set Vref, RX VrefLevel [Byte0]: 60
1796 16:30:33.315984 [Byte1]: 60
1797 16:30:33.316039
1798 16:30:33.316091 Set Vref, RX VrefLevel [Byte0]: 61
1799 16:30:33.316144 [Byte1]: 61
1800 16:30:33.316198
1801 16:30:33.316251 Set Vref, RX VrefLevel [Byte0]: 62
1802 16:30:33.316304 [Byte1]: 62
1803 16:30:33.316356
1804 16:30:33.316427 Set Vref, RX VrefLevel [Byte0]: 63
1805 16:30:33.316514 [Byte1]: 63
1806 16:30:33.316596
1807 16:30:33.316681 Set Vref, RX VrefLevel [Byte0]: 64
1808 16:30:33.316765 [Byte1]: 64
1809 16:30:33.316821
1810 16:30:33.316875 Set Vref, RX VrefLevel [Byte0]: 65
1811 16:30:33.316928 [Byte1]: 65
1812 16:30:33.316981
1813 16:30:33.317033 Set Vref, RX VrefLevel [Byte0]: 66
1814 16:30:33.317086 [Byte1]: 66
1815 16:30:33.317139
1816 16:30:33.317209 Set Vref, RX VrefLevel [Byte0]: 67
1817 16:30:33.317295 [Byte1]: 67
1818 16:30:33.317377
1819 16:30:33.317459 Set Vref, RX VrefLevel [Byte0]: 68
1820 16:30:33.317546 [Byte1]: 68
1821 16:30:33.317606
1822 16:30:33.317659 Set Vref, RX VrefLevel [Byte0]: 69
1823 16:30:33.317713 [Byte1]: 69
1824 16:30:33.317774
1825 16:30:33.317860 Set Vref, RX VrefLevel [Byte0]: 70
1826 16:30:33.317942 [Byte1]: 70
1827 16:30:33.318026
1828 16:30:33.318126 Set Vref, RX VrefLevel [Byte0]: 71
1829 16:30:33.318237 [Byte1]: 71
1830 16:30:33.318320
1831 16:30:33.318403 Set Vref, RX VrefLevel [Byte0]: 72
1832 16:30:33.318486 [Byte1]: 72
1833 16:30:33.318586
1834 16:30:33.318662 Final RX Vref Byte 0 = 56 to rank0
1835 16:30:33.318733 Final RX Vref Byte 1 = 63 to rank0
1836 16:30:33.318802 Final RX Vref Byte 0 = 56 to rank1
1837 16:30:33.318855 Final RX Vref Byte 1 = 63 to rank1==
1838 16:30:33.318910 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 16:30:33.318966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 16:30:33.319020 ==
1841 16:30:33.319076 DQS Delay:
1842 16:30:33.319130 DQS0 = 0, DQS1 = 0
1843 16:30:33.319190 DQM Delay:
1844 16:30:33.319244 DQM0 = 86, DQM1 = 79
1845 16:30:33.319324 DQ Delay:
1846 16:30:33.319407 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1847 16:30:33.319489 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1848 16:30:33.319571 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1849 16:30:33.319654 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1850 16:30:33.319735
1851 16:30:33.319816
1852 16:30:33.319900 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1853 16:30:33.319983 CH1 RK0: MR19=606, MR18=311D
1854 16:30:33.320066 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1855 16:30:33.320148
1856 16:30:33.320232 ----->DramcWriteLeveling(PI) begin...
1857 16:30:33.320315 ==
1858 16:30:33.320399 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 16:30:33.320486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 16:30:33.320575 ==
1861 16:30:33.320658 Write leveling (Byte 0): 29 => 29
1862 16:30:33.320747 Write leveling (Byte 1): 30 => 30
1863 16:30:33.320888 DramcWriteLeveling(PI) end<-----
1864 16:30:33.320961
1865 16:30:33.321016 ==
1866 16:30:33.321070 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 16:30:33.321126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 16:30:33.321180 ==
1869 16:30:33.321233 [Gating] SW mode calibration
1870 16:30:33.321287 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 16:30:33.321341 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 16:30:33.321395 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1873 16:30:33.321449 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1874 16:30:33.321503 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1875 16:30:33.321556 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 16:30:33.321609 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 16:30:33.321668 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 16:30:33.321722 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 16:30:33.321775 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 16:30:33.321827 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 16:30:33.321881 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:30:33.321933 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:30:33.321986 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:30:33.322039 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:30:33.322092 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:30:33.322144 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:30:33.322237 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 16:30:33.322291 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 16:30:33.322346 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 16:30:33.322400 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1891 16:30:33.322453 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 16:30:33.322506 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 16:30:33.322753 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 16:30:33.322813 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 16:30:33.322867 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 16:30:33.322924 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 16:30:33.322978 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1898 16:30:33.323032 0 9 8 | B1->B0 | 3232 2828 | 1 0 | (1 1) (0 0)
1899 16:30:33.323111 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 16:30:33.323194 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 16:30:33.323278 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 16:30:33.323363 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 16:30:33.323447 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 16:30:33.323506 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 16:30:33.323560 0 10 4 | B1->B0 | 3131 3434 | 1 0 | (1 0) (0 1)
1906 16:30:33.323613 0 10 8 | B1->B0 | 2727 2727 | 0 0 | (0 0) (1 0)
1907 16:30:33.323667 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 16:30:33.323723 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 16:30:33.323781 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 16:30:33.323876 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 16:30:33.323960 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 16:30:33.324050 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 16:30:33.324135 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1914 16:30:33.324228 0 11 8 | B1->B0 | 4141 3838 | 0 0 | (0 0) (0 0)
1915 16:30:33.324320 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1916 16:30:33.324406 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 16:30:33.324497 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 16:30:33.324587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 16:30:33.324671 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 16:30:33.324759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 16:30:33.324852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1922 16:30:33.324941 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1923 16:30:33.325031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 16:30:33.325121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 16:30:33.325224 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 16:30:33.325317 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 16:30:33.325419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 16:30:33.325513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 16:30:33.325597 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 16:30:33.325681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 16:30:33.325764 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 16:30:33.325847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 16:30:33.325931 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 16:30:33.326038 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 16:30:33.326123 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 16:30:33.326230 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 16:30:33.326314 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1938 16:30:33.326396 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 16:30:33.326479 Total UI for P1: 0, mck2ui 16
1940 16:30:33.326562 best dqsien dly found for B0: ( 0, 14, 6)
1941 16:30:33.326644 Total UI for P1: 0, mck2ui 16
1942 16:30:33.326727 best dqsien dly found for B1: ( 0, 14, 4)
1943 16:30:33.326810 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1944 16:30:33.326893 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1945 16:30:33.326975
1946 16:30:33.327058 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1947 16:30:33.327141 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1948 16:30:33.327223 [Gating] SW calibration Done
1949 16:30:33.327304 ==
1950 16:30:33.327387 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 16:30:33.327469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 16:30:33.327551 ==
1953 16:30:33.327639 RX Vref Scan: 0
1954 16:30:33.327731
1955 16:30:33.327814 RX Vref 0 -> 0, step: 1
1956 16:30:33.327895
1957 16:30:33.327977 RX Delay -130 -> 252, step: 16
1958 16:30:33.328060 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1959 16:30:33.328142 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1960 16:30:33.328225 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1961 16:30:33.328307 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1962 16:30:33.328421 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1963 16:30:33.328562 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1964 16:30:33.328696 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1965 16:30:33.328832 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1966 16:30:33.328941 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1967 16:30:33.329041 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1968 16:30:33.329125 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1969 16:30:33.329211 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1970 16:30:33.329295 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1971 16:30:33.329378 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1972 16:30:33.329461 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1973 16:30:33.329543 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1974 16:30:33.329629 ==
1975 16:30:33.329714 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 16:30:33.329798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 16:30:33.329880 ==
1978 16:30:33.329962 DQS Delay:
1979 16:30:33.330044 DQS0 = 0, DQS1 = 0
1980 16:30:33.330149 DQM Delay:
1981 16:30:33.330266 DQM0 = 88, DQM1 = 80
1982 16:30:33.330351 DQ Delay:
1983 16:30:33.330433 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1984 16:30:33.582067 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1985 16:30:33.582234 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1986 16:30:33.582306 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1987 16:30:33.582372
1988 16:30:33.582434
1989 16:30:33.582494 ==
1990 16:30:33.582554 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 16:30:33.582613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 16:30:33.582686 ==
1993 16:30:33.582748
1994 16:30:33.582809
1995 16:30:33.582870 TX Vref Scan disable
1996 16:30:33.582933 == TX Byte 0 ==
1997 16:30:33.582995 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1998 16:30:33.583273 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1999 16:30:33.583374 == TX Byte 1 ==
2000 16:30:33.583498 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 16:30:33.583623 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 16:30:33.583743 ==
2003 16:30:33.583865 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 16:30:33.583988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 16:30:33.584111 ==
2006 16:30:33.584234 TX Vref=22, minBit 8, minWin=27, winSum=445
2007 16:30:33.584342 TX Vref=24, minBit 8, minWin=27, winSum=449
2008 16:30:33.584442 TX Vref=26, minBit 9, minWin=27, winSum=451
2009 16:30:33.584538 TX Vref=28, minBit 8, minWin=27, winSum=451
2010 16:30:33.584633 TX Vref=30, minBit 8, minWin=27, winSum=452
2011 16:30:33.584729 TX Vref=32, minBit 8, minWin=27, winSum=452
2012 16:30:33.584825 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
2013 16:30:33.584919
2014 16:30:33.585013 Final TX Range 1 Vref 30
2015 16:30:33.585108
2016 16:30:33.585201 ==
2017 16:30:33.585296 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 16:30:33.585391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 16:30:33.585485 ==
2020 16:30:33.585579
2021 16:30:33.585672
2022 16:30:33.585765 TX Vref Scan disable
2023 16:30:33.585859 == TX Byte 0 ==
2024 16:30:33.585954 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2025 16:30:33.586049 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2026 16:30:33.586143 == TX Byte 1 ==
2027 16:30:33.586222 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2028 16:30:33.586286 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2029 16:30:33.586347
2030 16:30:33.586408 [DATLAT]
2031 16:30:33.586469 Freq=800, CH1 RK1
2032 16:30:33.586530
2033 16:30:33.586590 DATLAT Default: 0xa
2034 16:30:33.586650 0, 0xFFFF, sum = 0
2035 16:30:33.586712 1, 0xFFFF, sum = 0
2036 16:30:33.586774 2, 0xFFFF, sum = 0
2037 16:30:33.586835 3, 0xFFFF, sum = 0
2038 16:30:33.586896 4, 0xFFFF, sum = 0
2039 16:30:33.586957 5, 0xFFFF, sum = 0
2040 16:30:33.587019 6, 0xFFFF, sum = 0
2041 16:30:33.587080 7, 0xFFFF, sum = 0
2042 16:30:33.587141 8, 0xFFFF, sum = 0
2043 16:30:33.587203 9, 0x0, sum = 1
2044 16:30:33.587264 10, 0x0, sum = 2
2045 16:30:33.587326 11, 0x0, sum = 3
2046 16:30:33.587387 12, 0x0, sum = 4
2047 16:30:33.587448 best_step = 10
2048 16:30:33.587509
2049 16:30:33.587587 ==
2050 16:30:33.587648 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 16:30:33.587710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 16:30:33.587772 ==
2053 16:30:33.587832 RX Vref Scan: 0
2054 16:30:33.587893
2055 16:30:33.587954 RX Vref 0 -> 0, step: 1
2056 16:30:33.588014
2057 16:30:33.588075 RX Delay -95 -> 252, step: 8
2058 16:30:33.588137 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2059 16:30:33.588198 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2060 16:30:33.588260 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2061 16:30:33.588322 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2062 16:30:33.588384 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2063 16:30:33.588445 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2064 16:30:33.588506 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2065 16:30:33.588568 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2066 16:30:33.588655 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2067 16:30:33.588729 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2068 16:30:33.588798 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2069 16:30:33.588860 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2070 16:30:33.588921 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2071 16:30:33.588983 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2072 16:30:33.589045 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2073 16:30:33.589107 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2074 16:30:33.589168 ==
2075 16:30:33.589229 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 16:30:33.589291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 16:30:33.589353 ==
2078 16:30:33.589414 DQS Delay:
2079 16:30:33.589475 DQS0 = 0, DQS1 = 0
2080 16:30:33.589536 DQM Delay:
2081 16:30:33.589596 DQM0 = 87, DQM1 = 78
2082 16:30:33.589658 DQ Delay:
2083 16:30:33.589719 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2084 16:30:33.589780 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2085 16:30:33.589841 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2086 16:30:33.589902 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2087 16:30:33.589963
2088 16:30:33.590024
2089 16:30:33.590084 [DQSOSCAuto] RK1, (LSB)MR18= 0x1911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2090 16:30:33.590146 CH1 RK1: MR19=606, MR18=1911
2091 16:30:33.590220 CH1_RK1: MR19=0x606, MR18=0x1911, DQSOSC=403, MR23=63, INC=90, DEC=60
2092 16:30:33.590283 [RxdqsGatingPostProcess] freq 800
2093 16:30:33.590344 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 16:30:33.590406 Pre-setting of DQS Precalculation
2095 16:30:33.590467 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 16:30:33.590530 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 16:30:33.590593 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 16:30:33.590655
2099 16:30:33.590723
2100 16:30:33.590785 [Calibration Summary] 1600 Mbps
2101 16:30:33.590846 CH 0, Rank 0
2102 16:30:33.590908 SW Impedance : PASS
2103 16:30:33.590970 DUTY Scan : NO K
2104 16:30:33.591032 ZQ Calibration : PASS
2105 16:30:33.591092 Jitter Meter : NO K
2106 16:30:33.591154 CBT Training : PASS
2107 16:30:33.591215 Write leveling : PASS
2108 16:30:33.591277 RX DQS gating : PASS
2109 16:30:33.591338 RX DQ/DQS(RDDQC) : PASS
2110 16:30:33.591400 TX DQ/DQS : PASS
2111 16:30:33.591461 RX DATLAT : PASS
2112 16:30:33.591523 RX DQ/DQS(Engine): PASS
2113 16:30:33.591584 TX OE : NO K
2114 16:30:33.591645 All Pass.
2115 16:30:33.591706
2116 16:30:33.591767 CH 0, Rank 1
2117 16:30:33.591829 SW Impedance : PASS
2118 16:30:33.591893 DUTY Scan : NO K
2119 16:30:33.591970 ZQ Calibration : PASS
2120 16:30:33.592034 Jitter Meter : NO K
2121 16:30:33.592095 CBT Training : PASS
2122 16:30:33.592157 Write leveling : PASS
2123 16:30:33.592218 RX DQS gating : PASS
2124 16:30:33.592288 RX DQ/DQS(RDDQC) : PASS
2125 16:30:33.592350 TX DQ/DQS : PASS
2126 16:30:33.592412 RX DATLAT : PASS
2127 16:30:33.592473 RX DQ/DQS(Engine): PASS
2128 16:30:33.592534 TX OE : NO K
2129 16:30:33.592595 All Pass.
2130 16:30:33.592656
2131 16:30:33.592717 CH 1, Rank 0
2132 16:30:33.592778 SW Impedance : PASS
2133 16:30:33.592839 DUTY Scan : NO K
2134 16:30:33.592900 ZQ Calibration : PASS
2135 16:30:33.592961 Jitter Meter : NO K
2136 16:30:33.593023 CBT Training : PASS
2137 16:30:33.593083 Write leveling : PASS
2138 16:30:33.593144 RX DQS gating : PASS
2139 16:30:33.593204 RX DQ/DQS(RDDQC) : PASS
2140 16:30:33.593265 TX DQ/DQS : PASS
2141 16:30:33.593326 RX DATLAT : PASS
2142 16:30:33.593387 RX DQ/DQS(Engine): PASS
2143 16:30:33.593448 TX OE : NO K
2144 16:30:33.593718 All Pass.
2145 16:30:33.593828
2146 16:30:33.593950 CH 1, Rank 1
2147 16:30:33.594070 SW Impedance : PASS
2148 16:30:33.594177 DUTY Scan : NO K
2149 16:30:33.594277 ZQ Calibration : PASS
2150 16:30:33.594373 Jitter Meter : NO K
2151 16:30:33.594468 CBT Training : PASS
2152 16:30:33.594562 Write leveling : PASS
2153 16:30:33.594657 RX DQS gating : PASS
2154 16:30:33.594751 RX DQ/DQS(RDDQC) : PASS
2155 16:30:33.594845 TX DQ/DQS : PASS
2156 16:30:33.594941 RX DATLAT : PASS
2157 16:30:33.595035 RX DQ/DQS(Engine): PASS
2158 16:30:33.595129 TX OE : NO K
2159 16:30:33.595213 All Pass.
2160 16:30:33.595276
2161 16:30:33.595338 DramC Write-DBI off
2162 16:30:33.595399 PER_BANK_REFRESH: Hybrid Mode
2163 16:30:33.595461 TX_TRACKING: ON
2164 16:30:33.595522 [GetDramInforAfterCalByMRR] Vendor 6.
2165 16:30:33.595584 [GetDramInforAfterCalByMRR] Revision 606.
2166 16:30:33.595645 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 16:30:33.595707 MR0 0x3b3b
2168 16:30:33.595768 MR8 0x5151
2169 16:30:33.595829 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 16:30:33.595890
2171 16:30:33.595951 MR0 0x3b3b
2172 16:30:33.596012 MR8 0x5151
2173 16:30:33.596072 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 16:30:33.596134
2175 16:30:33.596195 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 16:30:33.596257 [FAST_K] Save calibration result to emmc
2177 16:30:33.596318 [FAST_K] Save calibration result to emmc
2178 16:30:33.596379 dram_init: config_dvfs: 1
2179 16:30:33.596441 dramc_set_vcore_voltage set vcore to 662500
2180 16:30:33.596502 Read voltage for 1200, 2
2181 16:30:33.596564 Vio18 = 0
2182 16:30:33.596625 Vcore = 662500
2183 16:30:33.596686 Vdram = 0
2184 16:30:33.596747 Vddq = 0
2185 16:30:33.596808 Vmddr = 0
2186 16:30:33.596868 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 16:30:33.596930 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 16:30:33.596992 MEM_TYPE=3, freq_sel=15
2189 16:30:33.597052 sv_algorithm_assistance_LP4_1600
2190 16:30:33.597114 ============ PULL DRAM RESETB DOWN ============
2191 16:30:33.597175 ========== PULL DRAM RESETB DOWN end =========
2192 16:30:33.597237 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 16:30:33.597298 ===================================
2194 16:30:33.597360 LPDDR4 DRAM CONFIGURATION
2195 16:30:33.597421 ===================================
2196 16:30:33.597482 EX_ROW_EN[0] = 0x0
2197 16:30:33.597543 EX_ROW_EN[1] = 0x0
2198 16:30:33.597604 LP4Y_EN = 0x0
2199 16:30:33.597665 WORK_FSP = 0x0
2200 16:30:33.597726 WL = 0x4
2201 16:30:33.597786 RL = 0x4
2202 16:30:33.597847 BL = 0x2
2203 16:30:33.597909 RPST = 0x0
2204 16:30:33.597969 RD_PRE = 0x0
2205 16:30:33.598031 WR_PRE = 0x1
2206 16:30:33.598091 WR_PST = 0x0
2207 16:30:33.598151 DBI_WR = 0x0
2208 16:30:33.598223 DBI_RD = 0x0
2209 16:30:33.598285 OTF = 0x1
2210 16:30:33.598346 ===================================
2211 16:30:33.598409 ===================================
2212 16:30:33.598470 ANA top config
2213 16:30:33.598531 ===================================
2214 16:30:33.598593 DLL_ASYNC_EN = 0
2215 16:30:33.598655 ALL_SLAVE_EN = 0
2216 16:30:33.598716 NEW_RANK_MODE = 1
2217 16:30:33.598779 DLL_IDLE_MODE = 1
2218 16:30:33.598840 LP45_APHY_COMB_EN = 1
2219 16:30:33.598902 TX_ODT_DIS = 1
2220 16:30:33.598964 NEW_8X_MODE = 1
2221 16:30:33.599025 ===================================
2222 16:30:33.599087 ===================================
2223 16:30:33.599149 data_rate = 2400
2224 16:30:33.599211 CKR = 1
2225 16:30:33.599272 DQ_P2S_RATIO = 8
2226 16:30:33.599333 ===================================
2227 16:30:33.599394 CA_P2S_RATIO = 8
2228 16:30:33.599456 DQ_CA_OPEN = 0
2229 16:30:33.599518 DQ_SEMI_OPEN = 0
2230 16:30:33.599579 CA_SEMI_OPEN = 0
2231 16:30:33.599639 CA_FULL_RATE = 0
2232 16:30:33.599700 DQ_CKDIV4_EN = 0
2233 16:30:33.599761 CA_CKDIV4_EN = 0
2234 16:30:33.599823 CA_PREDIV_EN = 0
2235 16:30:33.599883 PH8_DLY = 17
2236 16:30:33.599945 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 16:30:33.600006 DQ_AAMCK_DIV = 4
2238 16:30:33.600067 CA_AAMCK_DIV = 4
2239 16:30:33.600128 CA_ADMCK_DIV = 4
2240 16:30:33.600189 DQ_TRACK_CA_EN = 0
2241 16:30:33.600251 CA_PICK = 1200
2242 16:30:33.600312 CA_MCKIO = 1200
2243 16:30:33.600374 MCKIO_SEMI = 0
2244 16:30:33.600435 PLL_FREQ = 2366
2245 16:30:33.600496 DQ_UI_PI_RATIO = 32
2246 16:30:33.600558 CA_UI_PI_RATIO = 0
2247 16:30:33.600619 ===================================
2248 16:30:33.600679 ===================================
2249 16:30:33.600741 memory_type:LPDDR4
2250 16:30:33.600802 GP_NUM : 10
2251 16:30:33.600863 SRAM_EN : 1
2252 16:30:33.600924 MD32_EN : 0
2253 16:30:33.600985 ===================================
2254 16:30:33.601046 [ANA_INIT] >>>>>>>>>>>>>>
2255 16:30:33.601107 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 16:30:33.601169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 16:30:33.601230 ===================================
2258 16:30:33.601292 data_rate = 2400,PCW = 0X5b00
2259 16:30:33.601380 ===================================
2260 16:30:33.601446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 16:30:33.601525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 16:30:33.601646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 16:30:33.601748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 16:30:33.601846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 16:30:33.601942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 16:30:33.602038 [ANA_INIT] flow start
2267 16:30:33.602134 [ANA_INIT] PLL >>>>>>>>
2268 16:30:33.602221 [ANA_INIT] PLL <<<<<<<<
2269 16:30:33.602285 [ANA_INIT] MIDPI >>>>>>>>
2270 16:30:33.602347 [ANA_INIT] MIDPI <<<<<<<<
2271 16:30:33.602409 [ANA_INIT] DLL >>>>>>>>
2272 16:30:33.602471 [ANA_INIT] DLL <<<<<<<<
2273 16:30:33.602531 [ANA_INIT] flow end
2274 16:30:33.602593 ============ LP4 DIFF to SE enter ============
2275 16:30:33.602655 ============ LP4 DIFF to SE exit ============
2276 16:30:33.602717 [ANA_INIT] <<<<<<<<<<<<<
2277 16:30:33.602779 [Flow] Enable top DCM control >>>>>
2278 16:30:33.602840 [Flow] Enable top DCM control <<<<<
2279 16:30:33.603099 Enable DLL master slave shuffle
2280 16:30:33.603169 ==============================================================
2281 16:30:33.603295 Gating Mode config
2282 16:30:33.603420 ==============================================================
2283 16:30:33.603544 Config description:
2284 16:30:33.603664 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 16:30:33.603773 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 16:30:33.603858 SELPH_MODE 0: By rank 1: By Phase
2287 16:30:33.603922 ==============================================================
2288 16:30:33.603986 GAT_TRACK_EN = 1
2289 16:30:33.604048 RX_GATING_MODE = 2
2290 16:30:33.604110 RX_GATING_TRACK_MODE = 2
2291 16:30:33.604180 SELPH_MODE = 1
2292 16:30:33.604276 PICG_EARLY_EN = 1
2293 16:30:33.604372 VALID_LAT_VALUE = 1
2294 16:30:33.604468 ==============================================================
2295 16:30:33.604564 Enter into Gating configuration >>>>
2296 16:30:33.604659 Exit from Gating configuration <<<<
2297 16:30:33.604755 Enter into DVFS_PRE_config >>>>>
2298 16:30:33.604852 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 16:30:33.604949 Exit from DVFS_PRE_config <<<<<
2300 16:30:33.605045 Enter into PICG configuration >>>>
2301 16:30:33.605146 Exit from PICG configuration <<<<
2302 16:30:33.605211 [RX_INPUT] configuration >>>>>
2303 16:30:33.605274 [RX_INPUT] configuration <<<<<
2304 16:30:33.605336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 16:30:33.605398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 16:30:33.605461 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 16:30:33.605523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 16:30:33.605585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 16:30:33.605669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 16:30:33.605734 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 16:30:33.605797 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 16:30:33.605886 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 16:30:33.605952 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 16:30:33.606014 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 16:30:33.606076 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 16:30:33.606139 ===================================
2317 16:30:33.606209 LPDDR4 DRAM CONFIGURATION
2318 16:30:33.606273 ===================================
2319 16:30:33.606335 EX_ROW_EN[0] = 0x0
2320 16:30:33.606397 EX_ROW_EN[1] = 0x0
2321 16:30:33.606459 LP4Y_EN = 0x0
2322 16:30:33.606520 WORK_FSP = 0x0
2323 16:30:33.606581 WL = 0x4
2324 16:30:33.606643 RL = 0x4
2325 16:30:33.606704 BL = 0x2
2326 16:30:33.606765 RPST = 0x0
2327 16:30:33.606826 RD_PRE = 0x0
2328 16:30:33.606888 WR_PRE = 0x1
2329 16:30:33.606948 WR_PST = 0x0
2330 16:30:33.607010 DBI_WR = 0x0
2331 16:30:33.607071 DBI_RD = 0x0
2332 16:30:33.607160 OTF = 0x1
2333 16:30:33.607264 ===================================
2334 16:30:33.607331 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 16:30:33.607394 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 16:30:33.607457 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 16:30:33.607520 ===================================
2338 16:30:33.607582 LPDDR4 DRAM CONFIGURATION
2339 16:30:33.607644 ===================================
2340 16:30:33.607706 EX_ROW_EN[0] = 0x10
2341 16:30:33.607767 EX_ROW_EN[1] = 0x0
2342 16:30:33.607829 LP4Y_EN = 0x0
2343 16:30:33.607891 WORK_FSP = 0x0
2344 16:30:33.607952 WL = 0x4
2345 16:30:33.608014 RL = 0x4
2346 16:30:33.608076 BL = 0x2
2347 16:30:33.608137 RPST = 0x0
2348 16:30:33.608199 RD_PRE = 0x0
2349 16:30:33.608260 WR_PRE = 0x1
2350 16:30:33.608321 WR_PST = 0x0
2351 16:30:33.608382 DBI_WR = 0x0
2352 16:30:33.608443 DBI_RD = 0x0
2353 16:30:33.608504 OTF = 0x1
2354 16:30:33.608566 ===================================
2355 16:30:33.608629 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 16:30:33.608691 ==
2357 16:30:33.608753 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 16:30:33.608815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 16:30:33.608878 ==
2360 16:30:33.608939 [Duty_Offset_Calibration]
2361 16:30:33.609000 B0:1 B1:-1 CA:0
2362 16:30:33.609062
2363 16:30:33.609123 [DutyScan_Calibration_Flow] k_type=0
2364 16:30:33.609184
2365 16:30:33.609244 ==CLK 0==
2366 16:30:33.609305 Final CLK duty delay cell = 0
2367 16:30:33.609366 [0] MAX Duty = 5094%(X100), DQS PI = 16
2368 16:30:33.609427 [0] MIN Duty = 4875%(X100), DQS PI = 8
2369 16:30:33.609488 [0] AVG Duty = 4984%(X100)
2370 16:30:33.609549
2371 16:30:33.609609 CH0 CLK Duty spec in!! Max-Min= 219%
2372 16:30:33.609671 [DutyScan_Calibration_Flow] ====Done====
2373 16:30:33.609731
2374 16:30:33.609791 [DutyScan_Calibration_Flow] k_type=1
2375 16:30:33.609851
2376 16:30:33.609912 ==DQS 0 ==
2377 16:30:33.609973 Final DQS duty delay cell = -4
2378 16:30:33.610035 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2379 16:30:33.610095 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2380 16:30:33.610156 [-4] AVG Duty = 4968%(X100)
2381 16:30:33.610223
2382 16:30:33.610284 ==DQS 1 ==
2383 16:30:33.610344 Final DQS duty delay cell = 0
2384 16:30:33.610405 [0] MAX Duty = 5124%(X100), DQS PI = 4
2385 16:30:33.610466 [0] MIN Duty = 5000%(X100), DQS PI = 22
2386 16:30:33.610527 [0] AVG Duty = 5062%(X100)
2387 16:30:33.610587
2388 16:30:33.610647 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2389 16:30:33.610708
2390 16:30:33.610768 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2391 16:30:33.610829 [DutyScan_Calibration_Flow] ====Done====
2392 16:30:33.610889
2393 16:30:33.610949 [DutyScan_Calibration_Flow] k_type=3
2394 16:30:33.611010
2395 16:30:33.611071 ==DQM 0 ==
2396 16:30:33.611131 Final DQM duty delay cell = 0
2397 16:30:33.611193 [0] MAX Duty = 5031%(X100), DQS PI = 14
2398 16:30:33.611254 [0] MIN Duty = 4875%(X100), DQS PI = 8
2399 16:30:33.611315 [0] AVG Duty = 4953%(X100)
2400 16:30:33.611375
2401 16:30:33.611436 ==DQM 1 ==
2402 16:30:33.611497 Final DQM duty delay cell = 4
2403 16:30:33.611759 [4] MAX Duty = 5187%(X100), DQS PI = 32
2404 16:30:33.611830 [4] MIN Duty = 4969%(X100), DQS PI = 26
2405 16:30:33.611893 [4] AVG Duty = 5078%(X100)
2406 16:30:33.611955
2407 16:30:33.612016 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2408 16:30:33.612077
2409 16:30:33.612151 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2410 16:30:33.612213 [DutyScan_Calibration_Flow] ====Done====
2411 16:30:33.612275
2412 16:30:33.612343 [DutyScan_Calibration_Flow] k_type=2
2413 16:30:33.612406
2414 16:30:33.612467 ==DQ 0 ==
2415 16:30:33.612528 Final DQ duty delay cell = -4
2416 16:30:33.612590 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2417 16:30:33.612651 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2418 16:30:33.612725 [-4] AVG Duty = 4953%(X100)
2419 16:30:33.612780
2420 16:30:33.612835 ==DQ 1 ==
2421 16:30:33.612891 Final DQ duty delay cell = -4
2422 16:30:33.612947 [-4] MAX Duty = 4969%(X100), DQS PI = 54
2423 16:30:33.613003 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2424 16:30:33.613059 [-4] AVG Duty = 4922%(X100)
2425 16:30:33.613114
2426 16:30:33.613170 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2427 16:30:33.613226
2428 16:30:33.613281 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2429 16:30:33.613336 [DutyScan_Calibration_Flow] ====Done====
2430 16:30:33.613391 ==
2431 16:30:33.613446 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 16:30:33.613503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 16:30:33.613559 ==
2434 16:30:33.613614 [Duty_Offset_Calibration]
2435 16:30:33.613670 B0:-1 B1:1 CA:1
2436 16:30:33.613725
2437 16:30:33.613780 [DutyScan_Calibration_Flow] k_type=0
2438 16:30:33.613835
2439 16:30:33.613890 ==CLK 0==
2440 16:30:33.613945 Final CLK duty delay cell = 0
2441 16:30:33.614030 [0] MAX Duty = 5156%(X100), DQS PI = 4
2442 16:30:33.614117 [0] MIN Duty = 5000%(X100), DQS PI = 28
2443 16:30:33.614202 [0] AVG Duty = 5078%(X100)
2444 16:30:33.614261
2445 16:30:33.614316 CH1 CLK Duty spec in!! Max-Min= 156%
2446 16:30:33.614374 [DutyScan_Calibration_Flow] ====Done====
2447 16:30:33.614430
2448 16:30:33.614486 [DutyScan_Calibration_Flow] k_type=1
2449 16:30:33.614542
2450 16:30:33.614597 ==DQS 0 ==
2451 16:30:33.614653 Final DQS duty delay cell = 0
2452 16:30:33.614709 [0] MAX Duty = 5125%(X100), DQS PI = 18
2453 16:30:33.614765 [0] MIN Duty = 4875%(X100), DQS PI = 38
2454 16:30:33.614820 [0] AVG Duty = 5000%(X100)
2455 16:30:33.614876
2456 16:30:33.614932 ==DQS 1 ==
2457 16:30:33.614987 Final DQS duty delay cell = 0
2458 16:30:33.615043 [0] MAX Duty = 5062%(X100), DQS PI = 0
2459 16:30:33.615098 [0] MIN Duty = 4969%(X100), DQS PI = 26
2460 16:30:33.615168 [0] AVG Duty = 5015%(X100)
2461 16:30:33.615232
2462 16:30:33.615289 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2463 16:30:33.615345
2464 16:30:33.615405 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2465 16:30:33.615462 [DutyScan_Calibration_Flow] ====Done====
2466 16:30:33.615518
2467 16:30:33.615573 [DutyScan_Calibration_Flow] k_type=3
2468 16:30:33.615629
2469 16:30:33.615684 ==DQM 0 ==
2470 16:30:33.615740 Final DQM duty delay cell = -4
2471 16:30:33.615795 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2472 16:30:33.615851 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2473 16:30:33.615906 [-4] AVG Duty = 4953%(X100)
2474 16:30:33.615962
2475 16:30:33.616017 ==DQM 1 ==
2476 16:30:33.616072 Final DQM duty delay cell = 0
2477 16:30:33.616128 [0] MAX Duty = 5187%(X100), DQS PI = 36
2478 16:30:33.616183 [0] MIN Duty = 4969%(X100), DQS PI = 0
2479 16:30:33.616247 [0] AVG Duty = 5078%(X100)
2480 16:30:33.616312
2481 16:30:33.616369 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2482 16:30:33.616424
2483 16:30:33.616503 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2484 16:30:33.616560 [DutyScan_Calibration_Flow] ====Done====
2485 16:30:33.616617
2486 16:30:33.616672 [DutyScan_Calibration_Flow] k_type=2
2487 16:30:33.616728
2488 16:30:33.616783 ==DQ 0 ==
2489 16:30:33.616841 Final DQ duty delay cell = 0
2490 16:30:33.616897 [0] MAX Duty = 5156%(X100), DQS PI = 60
2491 16:30:33.616954 [0] MIN Duty = 4907%(X100), DQS PI = 38
2492 16:30:33.617009 [0] AVG Duty = 5031%(X100)
2493 16:30:33.617065
2494 16:30:33.617120 ==DQ 1 ==
2495 16:30:33.617176 Final DQ duty delay cell = 0
2496 16:30:33.617236 [0] MAX Duty = 5124%(X100), DQS PI = 42
2497 16:30:33.617292 [0] MIN Duty = 4969%(X100), DQS PI = 0
2498 16:30:33.617348 [0] AVG Duty = 5046%(X100)
2499 16:30:33.617404
2500 16:30:33.617458 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2501 16:30:33.617514
2502 16:30:33.617569 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2503 16:30:33.617624 [DutyScan_Calibration_Flow] ====Done====
2504 16:30:33.617679 nWR fixed to 30
2505 16:30:33.617746 [ModeRegInit_LP4] CH0 RK0
2506 16:30:33.617798 [ModeRegInit_LP4] CH0 RK1
2507 16:30:33.617851 [ModeRegInit_LP4] CH1 RK0
2508 16:30:33.617904 [ModeRegInit_LP4] CH1 RK1
2509 16:30:33.617956 match AC timing 7
2510 16:30:33.618009 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 16:30:33.618063 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 16:30:33.618116 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 16:30:33.618195 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 16:30:33.618264 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 16:30:33.618370 ==
2516 16:30:33.618426 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 16:30:33.618480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 16:30:33.618533 ==
2519 16:30:33.618591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 16:30:33.618645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2521 16:30:33.618698 [CA 0] Center 39 (9~70) winsize 62
2522 16:30:33.618751 [CA 1] Center 39 (9~70) winsize 62
2523 16:30:33.618804 [CA 2] Center 35 (5~66) winsize 62
2524 16:30:33.618857 [CA 3] Center 35 (5~66) winsize 62
2525 16:30:33.618910 [CA 4] Center 33 (4~63) winsize 60
2526 16:30:33.618962 [CA 5] Center 33 (3~63) winsize 61
2527 16:30:33.619015
2528 16:30:33.619067 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2529 16:30:33.619122
2530 16:30:33.619174 [CATrainingPosCal] consider 1 rank data
2531 16:30:33.619228 u2DelayCellTimex100 = 270/100 ps
2532 16:30:33.619281 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 16:30:33.619334 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2534 16:30:33.619387 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 16:30:33.619440 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 16:30:33.619493 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2537 16:30:33.619546 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2538 16:30:33.619599
2539 16:30:33.619652 CA PerBit enable=1, Macro0, CA PI delay=33
2540 16:30:33.619705
2541 16:30:33.619758 [CBTSetCACLKResult] CA Dly = 33
2542 16:30:33.619811 CS Dly: 8 (0~39)
2543 16:30:33.619864 ==
2544 16:30:33.619917 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 16:30:33.619970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 16:30:33.620023 ==
2547 16:30:33.620076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 16:30:33.620130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 16:30:33.620386 [CA 0] Center 39 (8~70) winsize 63
2550 16:30:33.620481 [CA 1] Center 39 (9~70) winsize 62
2551 16:30:33.620587 [CA 2] Center 35 (5~66) winsize 62
2552 16:30:33.620693 [CA 3] Center 34 (4~65) winsize 62
2553 16:30:33.620799 [CA 4] Center 33 (3~64) winsize 62
2554 16:30:33.620905 [CA 5] Center 33 (3~63) winsize 61
2555 16:30:33.621009
2556 16:30:33.621114 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 16:30:33.621218
2558 16:30:33.621320 [CATrainingPosCal] consider 2 rank data
2559 16:30:33.621407 u2DelayCellTimex100 = 270/100 ps
2560 16:30:33.621491 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 16:30:33.621574 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2562 16:30:33.621656 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 16:30:33.621739 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2564 16:30:33.621821 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2565 16:30:33.621904 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2566 16:30:33.621985
2567 16:30:33.622067 CA PerBit enable=1, Macro0, CA PI delay=33
2568 16:30:33.622149
2569 16:30:33.622272 [CBTSetCACLKResult] CA Dly = 33
2570 16:30:33.622354 CS Dly: 9 (0~41)
2571 16:30:33.622436
2572 16:30:33.622519 ----->DramcWriteLeveling(PI) begin...
2573 16:30:33.622602 ==
2574 16:30:33.622684 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 16:30:33.622767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 16:30:33.622850 ==
2577 16:30:33.622932 Write leveling (Byte 0): 33 => 33
2578 16:30:33.623015 Write leveling (Byte 1): 28 => 28
2579 16:30:33.623097 DramcWriteLeveling(PI) end<-----
2580 16:30:33.623178
2581 16:30:33.623259 ==
2582 16:30:33.623348 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 16:30:33.623417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 16:30:33.623478 ==
2585 16:30:33.623545 [Gating] SW mode calibration
2586 16:30:33.623608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 16:30:33.623690 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 16:30:33.623777 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2589 16:30:33.623874 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2590 16:30:33.623962 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 16:30:33.624049 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 16:30:33.624132 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 16:30:33.624222 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 16:30:33.624311 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2595 16:30:33.624401 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
2596 16:30:33.624487 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2597 16:30:33.624572 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 16:30:33.624655 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 16:30:33.624738 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 16:30:33.624821 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 16:30:33.624904 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 16:30:33.624987 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 16:30:33.625069 1 0 28 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
2604 16:30:33.625152 1 1 0 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2605 16:30:33.625237 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2606 16:30:33.625322 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 16:30:33.625407 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 16:30:33.625493 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 16:30:33.625576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 16:30:33.625663 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 16:30:33.625746 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 16:30:33.625829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 16:30:33.625912 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 16:30:33.625995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 16:30:33.626077 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 16:30:33.626165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 16:30:33.626282 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 16:30:33.626365 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 16:30:33.626448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 16:30:33.626531 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 16:30:33.626614 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 16:30:33.626699 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 16:30:33.626797 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 16:30:33.626867 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 16:30:33.626921 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 16:30:33.626975 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 16:30:33.627029 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 16:30:33.627082 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2629 16:30:33.627136 Total UI for P1: 0, mck2ui 16
2630 16:30:33.627190 best dqsien dly found for B0: ( 1, 3, 28)
2631 16:30:33.627244 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 16:30:33.627302 Total UI for P1: 0, mck2ui 16
2633 16:30:33.627357 best dqsien dly found for B1: ( 1, 4, 0)
2634 16:30:33.627411 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2635 16:30:33.627465 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2636 16:30:33.627522
2637 16:30:33.627575 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2638 16:30:33.627629 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2639 16:30:33.627682 [Gating] SW calibration Done
2640 16:30:33.627736 ==
2641 16:30:33.627790 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 16:30:33.627844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 16:30:33.627898 ==
2644 16:30:33.627950 RX Vref Scan: 0
2645 16:30:33.628003
2646 16:30:33.628056 RX Vref 0 -> 0, step: 1
2647 16:30:33.628109
2648 16:30:33.628162 RX Delay -40 -> 252, step: 8
2649 16:30:33.628215 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2650 16:30:33.628268 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2651 16:30:33.628322 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2652 16:30:33.628375 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2653 16:30:33.628427 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2654 16:30:33.628679 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2655 16:30:33.628775 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2656 16:30:33.628879 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2657 16:30:33.628985 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2658 16:30:33.629090 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2659 16:30:33.629186 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2660 16:30:33.629277 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2661 16:30:33.629361 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2662 16:30:33.629445 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2663 16:30:33.629527 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2664 16:30:33.629610 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2665 16:30:33.629692 ==
2666 16:30:33.629775 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 16:30:33.629858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 16:30:33.629941 ==
2669 16:30:33.630023 DQS Delay:
2670 16:30:33.630105 DQS0 = 0, DQS1 = 0
2671 16:30:33.630231 DQM Delay:
2672 16:30:33.630315 DQM0 = 119, DQM1 = 107
2673 16:30:33.630397 DQ Delay:
2674 16:30:33.630483 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2675 16:30:33.630566 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2676 16:30:33.630649 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2677 16:30:33.630732 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2678 16:30:33.630814
2679 16:30:33.630895
2680 16:30:33.630978 ==
2681 16:30:33.631061 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 16:30:33.631144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 16:30:33.631226 ==
2684 16:30:33.631308
2685 16:30:33.631389
2686 16:30:33.631471 TX Vref Scan disable
2687 16:30:33.631552 == TX Byte 0 ==
2688 16:30:33.631635 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2689 16:30:33.631718 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2690 16:30:33.631801 == TX Byte 1 ==
2691 16:30:33.631883 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2692 16:30:33.631966 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2693 16:30:33.632048 ==
2694 16:30:33.632136 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 16:30:33.632221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 16:30:33.632324 ==
2697 16:30:33.632420 TX Vref=22, minBit 13, minWin=25, winSum=416
2698 16:30:33.632513 TX Vref=24, minBit 1, minWin=26, winSum=425
2699 16:30:33.632609 TX Vref=26, minBit 1, minWin=26, winSum=428
2700 16:30:33.632699 TX Vref=28, minBit 13, minWin=25, winSum=435
2701 16:30:33.632791 TX Vref=30, minBit 10, minWin=26, winSum=435
2702 16:30:33.632881 TX Vref=32, minBit 4, minWin=26, winSum=430
2703 16:30:33.632985 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
2704 16:30:33.633075
2705 16:30:33.633164 Final TX Range 1 Vref 30
2706 16:30:33.633248
2707 16:30:33.633330 ==
2708 16:30:33.633417 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 16:30:33.633500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 16:30:33.633587 ==
2711 16:30:33.633676
2712 16:30:33.633763
2713 16:30:33.633850 TX Vref Scan disable
2714 16:30:33.633933 == TX Byte 0 ==
2715 16:30:33.634020 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2716 16:30:33.634106 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2717 16:30:33.634270 == TX Byte 1 ==
2718 16:30:33.634357 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2719 16:30:33.634440 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2720 16:30:33.634522
2721 16:30:33.634611 [DATLAT]
2722 16:30:33.634696 Freq=1200, CH0 RK0
2723 16:30:33.634782
2724 16:30:33.634866 DATLAT Default: 0xd
2725 16:30:33.634949 0, 0xFFFF, sum = 0
2726 16:30:33.635034 1, 0xFFFF, sum = 0
2727 16:30:33.635118 2, 0xFFFF, sum = 0
2728 16:30:33.635201 3, 0xFFFF, sum = 0
2729 16:30:33.635285 4, 0xFFFF, sum = 0
2730 16:30:33.635369 5, 0xFFFF, sum = 0
2731 16:30:33.635453 6, 0xFFFF, sum = 0
2732 16:30:33.635537 7, 0xFFFF, sum = 0
2733 16:30:33.635620 8, 0xFFFF, sum = 0
2734 16:30:33.635704 9, 0xFFFF, sum = 0
2735 16:30:33.635788 10, 0xFFFF, sum = 0
2736 16:30:33.635872 11, 0xFFFF, sum = 0
2737 16:30:33.635956 12, 0x0, sum = 1
2738 16:30:33.636039 13, 0x0, sum = 2
2739 16:30:33.636123 14, 0x0, sum = 3
2740 16:30:33.636207 15, 0x0, sum = 4
2741 16:30:33.636291 best_step = 13
2742 16:30:33.636372
2743 16:30:33.636453 ==
2744 16:30:33.636536 Dram Type= 6, Freq= 0, CH_0, rank 0
2745 16:30:33.636619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2746 16:30:33.636702 ==
2747 16:30:33.636789 RX Vref Scan: 1
2748 16:30:33.636875
2749 16:30:33.636960 Set Vref Range= 32 -> 127
2750 16:30:33.637045
2751 16:30:33.637128 RX Vref 32 -> 127, step: 1
2752 16:30:33.637210
2753 16:30:33.637292 RX Delay -21 -> 252, step: 4
2754 16:30:33.637374
2755 16:30:33.637456 Set Vref, RX VrefLevel [Byte0]: 32
2756 16:30:33.637538 [Byte1]: 32
2757 16:30:33.637620
2758 16:30:33.637702 Set Vref, RX VrefLevel [Byte0]: 33
2759 16:30:33.637785 [Byte1]: 33
2760 16:30:33.637866
2761 16:30:33.637949 Set Vref, RX VrefLevel [Byte0]: 34
2762 16:30:33.638031 [Byte1]: 34
2763 16:30:33.638113
2764 16:30:33.638220 Set Vref, RX VrefLevel [Byte0]: 35
2765 16:30:33.638288 [Byte1]: 35
2766 16:30:33.638343
2767 16:30:33.638396 Set Vref, RX VrefLevel [Byte0]: 36
2768 16:30:33.638450 [Byte1]: 36
2769 16:30:33.638504
2770 16:30:33.638556 Set Vref, RX VrefLevel [Byte0]: 37
2771 16:30:33.638609 [Byte1]: 37
2772 16:30:33.638661
2773 16:30:33.638714 Set Vref, RX VrefLevel [Byte0]: 38
2774 16:30:33.638768 [Byte1]: 38
2775 16:30:33.638821
2776 16:30:33.638874 Set Vref, RX VrefLevel [Byte0]: 39
2777 16:30:33.638927 [Byte1]: 39
2778 16:30:33.638980
2779 16:30:33.639032 Set Vref, RX VrefLevel [Byte0]: 40
2780 16:30:33.639085 [Byte1]: 40
2781 16:30:33.639138
2782 16:30:33.639191 Set Vref, RX VrefLevel [Byte0]: 41
2783 16:30:33.639244 [Byte1]: 41
2784 16:30:33.639297
2785 16:30:33.639349 Set Vref, RX VrefLevel [Byte0]: 42
2786 16:30:33.639402 [Byte1]: 42
2787 16:30:33.639455
2788 16:30:33.639508 Set Vref, RX VrefLevel [Byte0]: 43
2789 16:30:33.639561 [Byte1]: 43
2790 16:30:33.639613
2791 16:30:33.639666 Set Vref, RX VrefLevel [Byte0]: 44
2792 16:30:33.639719 [Byte1]: 44
2793 16:30:33.639772
2794 16:30:33.639836 Set Vref, RX VrefLevel [Byte0]: 45
2795 16:30:33.639916 [Byte1]: 45
2796 16:30:33.639999
2797 16:30:33.640082 Set Vref, RX VrefLevel [Byte0]: 46
2798 16:30:33.640164 [Byte1]: 46
2799 16:30:33.640226
2800 16:30:33.640280 Set Vref, RX VrefLevel [Byte0]: 47
2801 16:30:33.640334 [Byte1]: 47
2802 16:30:33.640388
2803 16:30:33.640440 Set Vref, RX VrefLevel [Byte0]: 48
2804 16:30:33.640494 [Byte1]: 48
2805 16:30:33.640547
2806 16:30:33.640599 Set Vref, RX VrefLevel [Byte0]: 49
2807 16:30:33.640653 [Byte1]: 49
2808 16:30:33.640707
2809 16:30:33.640771 Set Vref, RX VrefLevel [Byte0]: 50
2810 16:30:33.640829 [Byte1]: 50
2811 16:30:33.640883
2812 16:30:33.640935 Set Vref, RX VrefLevel [Byte0]: 51
2813 16:30:33.641209 [Byte1]: 51
2814 16:30:33.641270
2815 16:30:33.641324 Set Vref, RX VrefLevel [Byte0]: 52
2816 16:30:33.641378 [Byte1]: 52
2817 16:30:33.641432
2818 16:30:33.641485 Set Vref, RX VrefLevel [Byte0]: 53
2819 16:30:33.641538 [Byte1]: 53
2820 16:30:33.641591
2821 16:30:33.641644 Set Vref, RX VrefLevel [Byte0]: 54
2822 16:30:33.641697 [Byte1]: 54
2823 16:30:33.641750
2824 16:30:33.641802 Set Vref, RX VrefLevel [Byte0]: 55
2825 16:30:33.641880 [Byte1]: 55
2826 16:30:33.642051
2827 16:30:33.642135 Set Vref, RX VrefLevel [Byte0]: 56
2828 16:30:33.642223 [Byte1]: 56
2829 16:30:33.642332
2830 16:30:33.642389 Set Vref, RX VrefLevel [Byte0]: 57
2831 16:30:33.642445 [Byte1]: 57
2832 16:30:33.642500
2833 16:30:33.642559 Set Vref, RX VrefLevel [Byte0]: 58
2834 16:30:33.642614 [Byte1]: 58
2835 16:30:33.642669
2836 16:30:33.642736 Set Vref, RX VrefLevel [Byte0]: 59
2837 16:30:33.642789 [Byte1]: 59
2838 16:30:33.642841
2839 16:30:33.642908 Set Vref, RX VrefLevel [Byte0]: 60
2840 16:30:33.642978 [Byte1]: 60
2841 16:30:33.643031
2842 16:30:33.643084 Set Vref, RX VrefLevel [Byte0]: 61
2843 16:30:33.643136 [Byte1]: 61
2844 16:30:33.643189
2845 16:30:33.643242 Set Vref, RX VrefLevel [Byte0]: 62
2846 16:30:33.643295 [Byte1]: 62
2847 16:30:33.643348
2848 16:30:33.643401 Set Vref, RX VrefLevel [Byte0]: 63
2849 16:30:33.643454 [Byte1]: 63
2850 16:30:33.643508
2851 16:30:33.643561 Set Vref, RX VrefLevel [Byte0]: 64
2852 16:30:33.643615 [Byte1]: 64
2853 16:30:33.643668
2854 16:30:33.643720 Set Vref, RX VrefLevel [Byte0]: 65
2855 16:30:33.643773 [Byte1]: 65
2856 16:30:33.643826
2857 16:30:33.643878 Set Vref, RX VrefLevel [Byte0]: 66
2858 16:30:33.643930 [Byte1]: 66
2859 16:30:33.643983
2860 16:30:33.644036 Set Vref, RX VrefLevel [Byte0]: 67
2861 16:30:33.644088 [Byte1]: 67
2862 16:30:33.644140
2863 16:30:33.644193 Set Vref, RX VrefLevel [Byte0]: 68
2864 16:30:33.644245 [Byte1]: 68
2865 16:30:33.644299
2866 16:30:33.644350 Set Vref, RX VrefLevel [Byte0]: 69
2867 16:30:33.644404 [Byte1]: 69
2868 16:30:33.644457
2869 16:30:33.644509 Set Vref, RX VrefLevel [Byte0]: 70
2870 16:30:33.644562 [Byte1]: 70
2871 16:30:33.644614
2872 16:30:33.644667 Set Vref, RX VrefLevel [Byte0]: 71
2873 16:30:33.644720 [Byte1]: 71
2874 16:30:33.644772
2875 16:30:33.644824 Set Vref, RX VrefLevel [Byte0]: 72
2876 16:30:33.644877 [Byte1]: 72
2877 16:30:33.644933
2878 16:30:33.645048 Set Vref, RX VrefLevel [Byte0]: 73
2879 16:30:33.645131 [Byte1]: 73
2880 16:30:33.645222
2881 16:30:33.645280 Set Vref, RX VrefLevel [Byte0]: 74
2882 16:30:33.645334 [Byte1]: 74
2883 16:30:33.645388
2884 16:30:33.645474 Set Vref, RX VrefLevel [Byte0]: 75
2885 16:30:33.645527 [Byte1]: 75
2886 16:30:33.645580
2887 16:30:33.645632 Set Vref, RX VrefLevel [Byte0]: 76
2888 16:30:33.645685 [Byte1]: 76
2889 16:30:33.645738
2890 16:30:33.645790 Set Vref, RX VrefLevel [Byte0]: 77
2891 16:30:33.645843 [Byte1]: 77
2892 16:30:33.645896
2893 16:30:33.645949 Final RX Vref Byte 0 = 60 to rank0
2894 16:30:33.646003 Final RX Vref Byte 1 = 49 to rank0
2895 16:30:33.646056 Final RX Vref Byte 0 = 60 to rank1
2896 16:30:33.646109 Final RX Vref Byte 1 = 49 to rank1==
2897 16:30:33.646168 Dram Type= 6, Freq= 0, CH_0, rank 0
2898 16:30:33.646255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 16:30:33.646309 ==
2900 16:30:33.646362 DQS Delay:
2901 16:30:33.646414 DQS0 = 0, DQS1 = 0
2902 16:30:33.646468 DQM Delay:
2903 16:30:33.646521 DQM0 = 118, DQM1 = 106
2904 16:30:33.646574 DQ Delay:
2905 16:30:33.646626 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =116
2906 16:30:33.646680 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2907 16:30:33.646734 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =100
2908 16:30:33.646786 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2909 16:30:33.646839
2910 16:30:33.646892
2911 16:30:33.646945 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2912 16:30:33.646999 CH0 RK0: MR19=403, MR18=11FD
2913 16:30:33.647052 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2914 16:30:33.647106
2915 16:30:33.647159 ----->DramcWriteLeveling(PI) begin...
2916 16:30:33.647213 ==
2917 16:30:33.647288 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 16:30:33.647344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 16:30:33.647398 ==
2920 16:30:33.647468 Write leveling (Byte 0): 32 => 32
2921 16:30:33.647523 Write leveling (Byte 1): 32 => 32
2922 16:30:33.647577 DramcWriteLeveling(PI) end<-----
2923 16:30:33.647650
2924 16:30:33.647741 ==
2925 16:30:33.647797 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 16:30:33.647852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 16:30:33.647945 ==
2928 16:30:33.648028 [Gating] SW mode calibration
2929 16:30:33.648114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2930 16:30:33.648199 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2931 16:30:33.648282 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2932 16:30:33.648367 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2933 16:30:33.648450 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 16:30:33.648534 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 16:30:33.648617 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 16:30:33.648700 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 16:30:33.648793 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2938 16:30:33.648877 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
2939 16:30:33.648970 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2940 16:30:33.649064 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 16:30:33.649155 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 16:30:33.649252 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 16:30:33.649310 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 16:30:33.649364 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 16:30:33.649438 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 16:30:33.649493 1 0 28 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
2947 16:30:33.649547 1 1 0 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
2948 16:30:33.649603 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 16:30:33.649857 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 16:30:33.649949 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 16:30:33.650033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 16:30:33.650117 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 16:30:33.650217 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2954 16:30:33.650296 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2955 16:30:33.650351 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 16:30:33.650404 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 16:30:33.650458 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 16:30:33.650512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 16:30:33.650565 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 16:30:33.650619 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 16:30:33.650673 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 16:30:33.650726 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 16:30:33.650779 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 16:30:33.650833 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 16:30:33.650887 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 16:30:33.650941 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 16:30:33.650994 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 16:30:33.651048 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 16:30:33.651101 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2970 16:30:33.651154 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2971 16:30:33.651217 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2972 16:30:33.651279 Total UI for P1: 0, mck2ui 16
2973 16:30:33.651334 best dqsien dly found for B0: ( 1, 3, 26)
2974 16:30:33.651387 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 16:30:33.651440 Total UI for P1: 0, mck2ui 16
2976 16:30:33.651495 best dqsien dly found for B1: ( 1, 3, 30)
2977 16:30:33.651548 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2978 16:30:33.651602 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2979 16:30:33.651655
2980 16:30:33.651708 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2981 16:30:33.651761 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2982 16:30:33.651823 [Gating] SW calibration Done
2983 16:30:33.651877 ==
2984 16:30:33.651939 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 16:30:33.652003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 16:30:33.652085 ==
2987 16:30:33.652167 RX Vref Scan: 0
2988 16:30:33.652255
2989 16:30:33.652346 RX Vref 0 -> 0, step: 1
2990 16:30:33.652433
2991 16:30:33.652515 RX Delay -40 -> 252, step: 8
2992 16:30:33.652598 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2993 16:30:33.652681 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2994 16:30:33.652764 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2995 16:30:33.652846 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2996 16:30:33.652929 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2997 16:30:33.653011 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2998 16:30:33.653094 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2999 16:30:33.653176 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3000 16:30:33.653258 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3001 16:30:33.653341 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3002 16:30:33.872543 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3003 16:30:33.873028 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3004 16:30:33.873364 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3005 16:30:33.873675 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3006 16:30:33.874029 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3007 16:30:33.874473 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3008 16:30:33.874778 ==
3009 16:30:33.875066 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 16:30:33.875351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 16:30:33.875634 ==
3012 16:30:33.875912 DQS Delay:
3013 16:30:33.876184 DQS0 = 0, DQS1 = 0
3014 16:30:33.876461 DQM Delay:
3015 16:30:33.876736 DQM0 = 117, DQM1 = 108
3016 16:30:33.877010 DQ Delay:
3017 16:30:33.877282 DQ0 =115, DQ1 =123, DQ2 =111, DQ3 =115
3018 16:30:33.877556 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3019 16:30:33.877829 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3020 16:30:33.878236 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
3021 16:30:33.878649
3022 16:30:33.878936
3023 16:30:33.879211 ==
3024 16:30:33.879485 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 16:30:33.879760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 16:30:33.880083 ==
3027 16:30:33.880376
3028 16:30:33.880647
3029 16:30:33.880915 TX Vref Scan disable
3030 16:30:33.881325 == TX Byte 0 ==
3031 16:30:33.881641 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3032 16:30:33.881930 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3033 16:30:33.882355 == TX Byte 1 ==
3034 16:30:33.882641 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3035 16:30:33.882919 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3036 16:30:33.883196 ==
3037 16:30:33.883468 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 16:30:33.883746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 16:30:33.884063 ==
3040 16:30:33.884519 TX Vref=22, minBit 5, minWin=25, winSum=420
3041 16:30:33.884822 TX Vref=24, minBit 4, minWin=26, winSum=426
3042 16:30:33.885104 TX Vref=26, minBit 2, minWin=26, winSum=428
3043 16:30:33.885382 TX Vref=28, minBit 1, minWin=27, winSum=433
3044 16:30:33.885657 TX Vref=30, minBit 13, minWin=26, winSum=434
3045 16:30:33.885933 TX Vref=32, minBit 10, minWin=26, winSum=430
3046 16:30:33.886245 [TxChooseVref] Worse bit 1, Min win 27, Win sum 433, Final Vref 28
3047 16:30:33.886529
3048 16:30:33.886803 Final TX Range 1 Vref 28
3049 16:30:33.887079
3050 16:30:33.887352 ==
3051 16:30:33.887628 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 16:30:33.887900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 16:30:33.888281 ==
3054 16:30:33.888606
3055 16:30:33.888920
3056 16:30:33.889204 TX Vref Scan disable
3057 16:30:33.889481 == TX Byte 0 ==
3058 16:30:33.889754 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3059 16:30:33.890030 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3060 16:30:33.890348 == TX Byte 1 ==
3061 16:30:33.890628 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3062 16:30:33.890903 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3063 16:30:33.891214
3064 16:30:33.891532 [DATLAT]
3065 16:30:33.891828 Freq=1200, CH0 RK1
3066 16:30:33.892112
3067 16:30:33.892397 DATLAT Default: 0xd
3068 16:30:33.892675 0, 0xFFFF, sum = 0
3069 16:30:33.892954 1, 0xFFFF, sum = 0
3070 16:30:33.893630 2, 0xFFFF, sum = 0
3071 16:30:33.894259 3, 0xFFFF, sum = 0
3072 16:30:33.894860 4, 0xFFFF, sum = 0
3073 16:30:33.895315 5, 0xFFFF, sum = 0
3074 16:30:33.895754 6, 0xFFFF, sum = 0
3075 16:30:33.896185 7, 0xFFFF, sum = 0
3076 16:30:33.896613 8, 0xFFFF, sum = 0
3077 16:30:33.897040 9, 0xFFFF, sum = 0
3078 16:30:33.897469 10, 0xFFFF, sum = 0
3079 16:30:33.897856 11, 0xFFFF, sum = 0
3080 16:30:33.898159 12, 0x0, sum = 1
3081 16:30:33.898493 13, 0x0, sum = 2
3082 16:30:33.898795 14, 0x0, sum = 3
3083 16:30:33.899097 15, 0x0, sum = 4
3084 16:30:33.899401 best_step = 13
3085 16:30:33.899696
3086 16:30:33.899993 ==
3087 16:30:33.900292 Dram Type= 6, Freq= 0, CH_0, rank 1
3088 16:30:33.900591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 16:30:33.900888 ==
3090 16:30:33.901185 RX Vref Scan: 0
3091 16:30:33.901480
3092 16:30:33.901778 RX Vref 0 -> 0, step: 1
3093 16:30:33.902075
3094 16:30:33.902400 RX Delay -21 -> 252, step: 4
3095 16:30:33.902722 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3096 16:30:33.902950 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3097 16:30:33.903177 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3098 16:30:33.903404 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3099 16:30:33.903630 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3100 16:30:33.903855 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3101 16:30:33.904081 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3102 16:30:33.904308 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3103 16:30:33.904534 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3104 16:30:33.904760 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3105 16:30:33.904986 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3106 16:30:33.905212 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3107 16:30:33.905438 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3108 16:30:33.905665 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3109 16:30:33.905902 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3110 16:30:33.906132 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3111 16:30:33.906319 ==
3112 16:30:33.906472 Dram Type= 6, Freq= 0, CH_0, rank 1
3113 16:30:33.906623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 16:30:33.906771 ==
3115 16:30:33.906919 DQS Delay:
3116 16:30:33.907068 DQS0 = 0, DQS1 = 0
3117 16:30:33.907216 DQM Delay:
3118 16:30:33.907362 DQM0 = 116, DQM1 = 107
3119 16:30:33.907509 DQ Delay:
3120 16:30:33.907657 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3121 16:30:33.907797 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3122 16:30:33.907913 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3123 16:30:33.908030 DQ12 =112, DQ13 =116, DQ14 =118, DQ15 =116
3124 16:30:33.908148
3125 16:30:33.908264
3126 16:30:33.908381 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3127 16:30:33.908531 CH0 RK1: MR19=403, MR18=DE8
3128 16:30:33.908653 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3129 16:30:33.908773 [RxdqsGatingPostProcess] freq 1200
3130 16:30:33.908892 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3131 16:30:33.909011 best DQS0 dly(2T, 0.5T) = (0, 11)
3132 16:30:33.909149 best DQS1 dly(2T, 0.5T) = (0, 12)
3133 16:30:33.909269 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3134 16:30:33.909388 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3135 16:30:33.909506 best DQS0 dly(2T, 0.5T) = (0, 11)
3136 16:30:33.909624 best DQS1 dly(2T, 0.5T) = (0, 11)
3137 16:30:33.909742 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3138 16:30:33.909860 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3139 16:30:33.909977 Pre-setting of DQS Precalculation
3140 16:30:33.910100 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3141 16:30:33.910262 ==
3142 16:30:33.910450 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 16:30:33.910645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 16:30:33.910774 ==
3145 16:30:33.910892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 16:30:33.911012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3147 16:30:33.911132 [CA 0] Center 37 (7~67) winsize 61
3148 16:30:33.911251 [CA 1] Center 38 (8~68) winsize 61
3149 16:30:33.911370 [CA 2] Center 34 (4~64) winsize 61
3150 16:30:33.911488 [CA 3] Center 34 (4~64) winsize 61
3151 16:30:33.911605 [CA 4] Center 34 (4~64) winsize 61
3152 16:30:33.911723 [CA 5] Center 33 (3~64) winsize 62
3153 16:30:33.911840
3154 16:30:33.911957 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3155 16:30:33.912074
3156 16:30:33.912191 [CATrainingPosCal] consider 1 rank data
3157 16:30:33.912308 u2DelayCellTimex100 = 270/100 ps
3158 16:30:33.912427 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3159 16:30:33.912544 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3160 16:30:33.912662 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 16:30:33.912781 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 16:30:33.912879 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 16:30:33.912976 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3164 16:30:33.913073
3165 16:30:33.913171 CA PerBit enable=1, Macro0, CA PI delay=33
3166 16:30:33.913268
3167 16:30:33.913365 [CBTSetCACLKResult] CA Dly = 33
3168 16:30:33.913463 CS Dly: 5 (0~36)
3169 16:30:33.913561 ==
3170 16:30:33.913659 Dram Type= 6, Freq= 0, CH_1, rank 1
3171 16:30:33.913756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 16:30:33.913855 ==
3173 16:30:33.913953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3174 16:30:33.914051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3175 16:30:33.914150 [CA 0] Center 37 (7~68) winsize 62
3176 16:30:33.914312 [CA 1] Center 38 (8~68) winsize 61
3177 16:30:33.914444 [CA 2] Center 34 (4~65) winsize 62
3178 16:30:33.914550 [CA 3] Center 33 (3~64) winsize 62
3179 16:30:33.914648 [CA 4] Center 34 (4~65) winsize 62
3180 16:30:33.914747 [CA 5] Center 33 (3~64) winsize 62
3181 16:30:33.914846
3182 16:30:33.914944 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3183 16:30:33.915043
3184 16:30:33.915140 [CATrainingPosCal] consider 2 rank data
3185 16:30:33.915238 u2DelayCellTimex100 = 270/100 ps
3186 16:30:33.915337 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3187 16:30:33.915436 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3188 16:30:33.915534 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 16:30:33.915632 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3190 16:30:33.915731 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3191 16:30:33.915828 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3192 16:30:33.915926
3193 16:30:33.916024 CA PerBit enable=1, Macro0, CA PI delay=33
3194 16:30:33.916122
3195 16:30:33.916219 [CBTSetCACLKResult] CA Dly = 33
3196 16:30:33.916319 CS Dly: 7 (0~41)
3197 16:30:33.916440
3198 16:30:33.916540 ----->DramcWriteLeveling(PI) begin...
3199 16:30:33.916641 ==
3200 16:30:33.916975 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 16:30:33.917086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 16:30:33.917187 ==
3203 16:30:33.917286 Write leveling (Byte 0): 24 => 24
3204 16:30:33.917385 Write leveling (Byte 1): 30 => 30
3205 16:30:33.917483 DramcWriteLeveling(PI) end<-----
3206 16:30:33.917581
3207 16:30:33.917678 ==
3208 16:30:33.917779 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 16:30:33.917863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 16:30:33.917949 ==
3211 16:30:33.918033 [Gating] SW mode calibration
3212 16:30:33.918118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3213 16:30:33.918221 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3214 16:30:33.918308 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3215 16:30:33.918402 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 16:30:33.918487 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 16:30:33.918571 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 16:30:33.918655 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 16:30:33.918740 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3220 16:30:33.918824 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3221 16:30:33.918908 0 15 28 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (1 0)
3222 16:30:33.918991 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 16:30:33.919075 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 16:30:33.919159 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 16:30:33.919243 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 16:30:33.919326 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 16:30:33.919409 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 16:30:33.919493 1 0 24 | B1->B0 | 2525 3939 | 0 1 | (0 0) (1 1)
3229 16:30:33.919576 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3230 16:30:33.919659 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3231 16:30:33.919743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 16:30:33.919827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 16:30:33.919911 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 16:30:33.919995 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 16:30:33.920079 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 16:30:33.920190 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3237 16:30:33.920279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3238 16:30:33.920364 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 16:30:33.920448 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 16:30:33.920533 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 16:30:33.920617 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 16:30:33.920701 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 16:30:33.920787 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 16:30:33.920871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 16:30:33.920954 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 16:30:33.921038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 16:30:33.921123 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 16:30:33.921207 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 16:30:33.921292 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 16:30:33.921376 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 16:30:33.921460 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 16:30:33.921545 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3253 16:30:33.921629 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3254 16:30:33.921714 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 16:30:33.921799 Total UI for P1: 0, mck2ui 16
3256 16:30:33.921884 best dqsien dly found for B0: ( 1, 3, 26)
3257 16:30:33.921968 Total UI for P1: 0, mck2ui 16
3258 16:30:33.922053 best dqsien dly found for B1: ( 1, 3, 28)
3259 16:30:33.922138 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3260 16:30:33.922275 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3261 16:30:33.922415
3262 16:30:33.922508 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3263 16:30:33.922594 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3264 16:30:33.922693 [Gating] SW calibration Done
3265 16:30:33.922767 ==
3266 16:30:33.922842 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 16:30:33.922918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 16:30:33.922993 ==
3269 16:30:33.923066 RX Vref Scan: 0
3270 16:30:33.923144
3271 16:30:33.923218 RX Vref 0 -> 0, step: 1
3272 16:30:33.923293
3273 16:30:33.923366 RX Delay -40 -> 252, step: 8
3274 16:30:33.923440 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3275 16:30:33.923514 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3276 16:30:33.923588 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3277 16:30:33.923712 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3278 16:30:33.923819 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3279 16:30:33.923897 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3280 16:30:33.923972 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3281 16:30:33.924046 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3282 16:30:33.924121 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3283 16:30:33.924196 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3284 16:30:33.924270 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3285 16:30:33.924350 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3286 16:30:33.924439 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3287 16:30:33.924515 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3288 16:30:33.924590 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3289 16:30:33.924663 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3290 16:30:33.924738 ==
3291 16:30:33.924812 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 16:30:33.924886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 16:30:33.924960 ==
3294 16:30:33.925034 DQS Delay:
3295 16:30:33.925108 DQS0 = 0, DQS1 = 0
3296 16:30:33.925183 DQM Delay:
3297 16:30:33.925256 DQM0 = 119, DQM1 = 110
3298 16:30:33.925330 DQ Delay:
3299 16:30:33.925404 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =119
3300 16:30:33.925478 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3301 16:30:33.925771 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3302 16:30:33.925954 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3303 16:30:33.926131
3304 16:30:33.926324
3305 16:30:33.926449 ==
3306 16:30:33.926530 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 16:30:33.926608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 16:30:33.926684 ==
3309 16:30:33.926759
3310 16:30:33.926833
3311 16:30:33.926906 TX Vref Scan disable
3312 16:30:33.926980 == TX Byte 0 ==
3313 16:30:33.927055 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3314 16:30:33.927130 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3315 16:30:33.927204 == TX Byte 1 ==
3316 16:30:33.927277 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3317 16:30:33.927351 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3318 16:30:33.927425 ==
3319 16:30:33.927499 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 16:30:33.927573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 16:30:33.927669 ==
3322 16:30:33.927757 TX Vref=22, minBit 1, minWin=25, winSum=411
3323 16:30:33.927824 TX Vref=24, minBit 10, minWin=25, winSum=420
3324 16:30:33.927891 TX Vref=26, minBit 0, minWin=26, winSum=425
3325 16:30:33.927957 TX Vref=28, minBit 11, minWin=25, winSum=427
3326 16:30:33.928023 TX Vref=30, minBit 1, minWin=26, winSum=428
3327 16:30:33.928090 TX Vref=32, minBit 9, minWin=25, winSum=421
3328 16:30:33.928155 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3329 16:30:33.928221
3330 16:30:33.928287 Final TX Range 1 Vref 30
3331 16:30:33.928354
3332 16:30:33.928441 ==
3333 16:30:33.928510 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 16:30:33.928577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 16:30:33.928644 ==
3336 16:30:33.928710
3337 16:30:33.928775
3338 16:30:33.928841 TX Vref Scan disable
3339 16:30:33.928907 == TX Byte 0 ==
3340 16:30:33.928972 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3341 16:30:33.929053 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3342 16:30:33.929122 == TX Byte 1 ==
3343 16:30:33.929189 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3344 16:30:33.929255 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3345 16:30:33.929320
3346 16:30:33.929385 [DATLAT]
3347 16:30:33.929451 Freq=1200, CH1 RK0
3348 16:30:33.929517
3349 16:30:33.929581 DATLAT Default: 0xd
3350 16:30:33.929647 0, 0xFFFF, sum = 0
3351 16:30:33.929715 1, 0xFFFF, sum = 0
3352 16:30:33.929782 2, 0xFFFF, sum = 0
3353 16:30:33.929848 3, 0xFFFF, sum = 0
3354 16:30:33.929914 4, 0xFFFF, sum = 0
3355 16:30:33.929980 5, 0xFFFF, sum = 0
3356 16:30:33.930047 6, 0xFFFF, sum = 0
3357 16:30:33.930113 7, 0xFFFF, sum = 0
3358 16:30:33.930191 8, 0xFFFF, sum = 0
3359 16:30:33.930261 9, 0xFFFF, sum = 0
3360 16:30:33.930328 10, 0xFFFF, sum = 0
3361 16:30:33.930420 11, 0xFFFF, sum = 0
3362 16:30:33.930490 12, 0x0, sum = 1
3363 16:30:33.930557 13, 0x0, sum = 2
3364 16:30:33.930633 14, 0x0, sum = 3
3365 16:30:33.930703 15, 0x0, sum = 4
3366 16:30:33.930769 best_step = 13
3367 16:30:33.930833
3368 16:30:33.930897 ==
3369 16:30:33.930963 Dram Type= 6, Freq= 0, CH_1, rank 0
3370 16:30:33.931028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3371 16:30:33.931094 ==
3372 16:30:33.931159 RX Vref Scan: 1
3373 16:30:33.931223
3374 16:30:33.931288 Set Vref Range= 32 -> 127
3375 16:30:33.931353
3376 16:30:33.931417 RX Vref 32 -> 127, step: 1
3377 16:30:33.931483
3378 16:30:33.931548 RX Delay -21 -> 252, step: 4
3379 16:30:33.931612
3380 16:30:33.931677 Set Vref, RX VrefLevel [Byte0]: 32
3381 16:30:33.931742 [Byte1]: 32
3382 16:30:33.931807
3383 16:30:33.931871 Set Vref, RX VrefLevel [Byte0]: 33
3384 16:30:33.931936 [Byte1]: 33
3385 16:30:33.932000
3386 16:30:33.932065 Set Vref, RX VrefLevel [Byte0]: 34
3387 16:30:33.932130 [Byte1]: 34
3388 16:30:33.932196
3389 16:30:33.932260 Set Vref, RX VrefLevel [Byte0]: 35
3390 16:30:33.932340 [Byte1]: 35
3391 16:30:33.932455
3392 16:30:33.932526 Set Vref, RX VrefLevel [Byte0]: 36
3393 16:30:33.932593 [Byte1]: 36
3394 16:30:33.932659
3395 16:30:33.932735 Set Vref, RX VrefLevel [Byte0]: 37
3396 16:30:33.932794 [Byte1]: 37
3397 16:30:33.932853
3398 16:30:33.932911 Set Vref, RX VrefLevel [Byte0]: 38
3399 16:30:33.932969 [Byte1]: 38
3400 16:30:33.933028
3401 16:30:33.933085 Set Vref, RX VrefLevel [Byte0]: 39
3402 16:30:33.933144 [Byte1]: 39
3403 16:30:33.933202
3404 16:30:33.933261 Set Vref, RX VrefLevel [Byte0]: 40
3405 16:30:33.933321 [Byte1]: 40
3406 16:30:33.933380
3407 16:30:33.933437 Set Vref, RX VrefLevel [Byte0]: 41
3408 16:30:33.933496 [Byte1]: 41
3409 16:30:33.933554
3410 16:30:33.933615 Set Vref, RX VrefLevel [Byte0]: 42
3411 16:30:33.933674 [Byte1]: 42
3412 16:30:33.933731
3413 16:30:33.933789 Set Vref, RX VrefLevel [Byte0]: 43
3414 16:30:33.933847 [Byte1]: 43
3415 16:30:33.933906
3416 16:30:33.933993 Set Vref, RX VrefLevel [Byte0]: 44
3417 16:30:33.934087 [Byte1]: 44
3418 16:30:33.934189
3419 16:30:33.934254 Set Vref, RX VrefLevel [Byte0]: 45
3420 16:30:33.934313 [Byte1]: 45
3421 16:30:33.934383
3422 16:30:33.934444 Set Vref, RX VrefLevel [Byte0]: 46
3423 16:30:33.934503 [Byte1]: 46
3424 16:30:33.934562
3425 16:30:33.934620 Set Vref, RX VrefLevel [Byte0]: 47
3426 16:30:33.934679 [Byte1]: 47
3427 16:30:33.934737
3428 16:30:33.934796 Set Vref, RX VrefLevel [Byte0]: 48
3429 16:30:33.934854 [Byte1]: 48
3430 16:30:33.934913
3431 16:30:33.934971 Set Vref, RX VrefLevel [Byte0]: 49
3432 16:30:33.935029 [Byte1]: 49
3433 16:30:33.935087
3434 16:30:33.935145 Set Vref, RX VrefLevel [Byte0]: 50
3435 16:30:33.935203 [Byte1]: 50
3436 16:30:33.935262
3437 16:30:33.935320 Set Vref, RX VrefLevel [Byte0]: 51
3438 16:30:33.935379 [Byte1]: 51
3439 16:30:33.935437
3440 16:30:33.935495 Set Vref, RX VrefLevel [Byte0]: 52
3441 16:30:33.935554 [Byte1]: 52
3442 16:30:33.935612
3443 16:30:33.935670 Set Vref, RX VrefLevel [Byte0]: 53
3444 16:30:33.935728 [Byte1]: 53
3445 16:30:33.935787
3446 16:30:33.935845 Set Vref, RX VrefLevel [Byte0]: 54
3447 16:30:33.935904 [Byte1]: 54
3448 16:30:33.935962
3449 16:30:33.936020 Set Vref, RX VrefLevel [Byte0]: 55
3450 16:30:33.936078 [Byte1]: 55
3451 16:30:33.936136
3452 16:30:33.936194 Set Vref, RX VrefLevel [Byte0]: 56
3453 16:30:33.936252 [Byte1]: 56
3454 16:30:33.936310
3455 16:30:33.936368 Set Vref, RX VrefLevel [Byte0]: 57
3456 16:30:33.936427 [Byte1]: 57
3457 16:30:33.936484
3458 16:30:33.936542 Set Vref, RX VrefLevel [Byte0]: 58
3459 16:30:33.936601 [Byte1]: 58
3460 16:30:33.936659
3461 16:30:33.936717 Set Vref, RX VrefLevel [Byte0]: 59
3462 16:30:33.936775 [Byte1]: 59
3463 16:30:33.936833
3464 16:30:33.936891 Set Vref, RX VrefLevel [Byte0]: 60
3465 16:30:33.936950 [Byte1]: 60
3466 16:30:33.937030
3467 16:30:33.937091 Set Vref, RX VrefLevel [Byte0]: 61
3468 16:30:33.937150 [Byte1]: 61
3469 16:30:33.937208
3470 16:30:33.937466 Set Vref, RX VrefLevel [Byte0]: 62
3471 16:30:33.937545 [Byte1]: 62
3472 16:30:33.937608
3473 16:30:33.937667 Set Vref, RX VrefLevel [Byte0]: 63
3474 16:30:33.937738 [Byte1]: 63
3475 16:30:33.937791
3476 16:30:33.937845 Set Vref, RX VrefLevel [Byte0]: 64
3477 16:30:33.937898 [Byte1]: 64
3478 16:30:33.937951
3479 16:30:33.938004 Set Vref, RX VrefLevel [Byte0]: 65
3480 16:30:33.938057 [Byte1]: 65
3481 16:30:33.938110
3482 16:30:33.938172 Set Vref, RX VrefLevel [Byte0]: 66
3483 16:30:33.938228 [Byte1]: 66
3484 16:30:33.938281
3485 16:30:33.938334 Set Vref, RX VrefLevel [Byte0]: 67
3486 16:30:33.938387 [Byte1]: 67
3487 16:30:33.938441
3488 16:30:33.938494 Set Vref, RX VrefLevel [Byte0]: 68
3489 16:30:33.938548 [Byte1]: 68
3490 16:30:33.938601
3491 16:30:33.938654 Set Vref, RX VrefLevel [Byte0]: 69
3492 16:30:33.938708 [Byte1]: 69
3493 16:30:33.938761
3494 16:30:33.938814 Final RX Vref Byte 0 = 52 to rank0
3495 16:30:33.938867 Final RX Vref Byte 1 = 57 to rank0
3496 16:30:33.938921 Final RX Vref Byte 0 = 52 to rank1
3497 16:30:33.938974 Final RX Vref Byte 1 = 57 to rank1==
3498 16:30:33.939028 Dram Type= 6, Freq= 0, CH_1, rank 0
3499 16:30:33.939081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 16:30:33.939135 ==
3501 16:30:33.939188 DQS Delay:
3502 16:30:33.939241 DQS0 = 0, DQS1 = 0
3503 16:30:33.939294 DQM Delay:
3504 16:30:33.939348 DQM0 = 117, DQM1 = 112
3505 16:30:33.939401 DQ Delay:
3506 16:30:33.939454 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =112
3507 16:30:33.939506 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =114
3508 16:30:33.939559 DQ8 =98, DQ9 =104, DQ10 =116, DQ11 =102
3509 16:30:33.939612 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =120
3510 16:30:33.939666
3511 16:30:33.939718
3512 16:30:33.939771 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3513 16:30:33.939826 CH1 RK0: MR19=403, MR18=1F5
3514 16:30:33.939880 CH1_RK0: MR19=0x403, MR18=0x1F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3515 16:30:33.939934
3516 16:30:33.939986 ----->DramcWriteLeveling(PI) begin...
3517 16:30:33.940041 ==
3518 16:30:33.940094 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 16:30:33.940147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 16:30:33.940201 ==
3521 16:30:33.940254 Write leveling (Byte 0): 22 => 22
3522 16:30:33.940308 Write leveling (Byte 1): 29 => 29
3523 16:30:33.940379 DramcWriteLeveling(PI) end<-----
3524 16:30:33.940434
3525 16:30:33.940488 ==
3526 16:30:33.940541 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 16:30:33.940594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 16:30:33.940648 ==
3529 16:30:33.940701 [Gating] SW mode calibration
3530 16:30:33.940756 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3531 16:30:33.940810 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3532 16:30:33.940864 0 15 0 | B1->B0 | 3333 3232 | 0 1 | (0 0) (0 0)
3533 16:30:33.940918 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 16:30:33.940971 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3535 16:30:33.941025 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 16:30:33.941090 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 16:30:33.941145 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3538 16:30:33.941199 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3539 16:30:33.941252 0 15 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 1)
3540 16:30:33.941305 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 16:30:33.941359 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 16:30:33.941413 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3543 16:30:33.941466 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 16:30:33.941520 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 16:30:33.941573 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3546 16:30:33.941627 1 0 24 | B1->B0 | 2f2f 2525 | 1 0 | (0 0) (0 0)
3547 16:30:33.941680 1 0 28 | B1->B0 | 4343 4343 | 0 1 | (0 0) (0 0)
3548 16:30:33.941734 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 16:30:33.941787 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 16:30:33.941840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 16:30:33.941893 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 16:30:33.941947 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 16:30:33.942000 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 16:30:33.942053 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3555 16:30:33.942107 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3556 16:30:33.942165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 16:30:33.942220 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 16:30:33.942274 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 16:30:33.942327 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 16:30:33.942380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 16:30:33.942433 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 16:30:33.942486 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 16:30:33.942541 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 16:30:33.942595 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 16:30:33.942648 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 16:30:33.942702 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 16:30:33.942769 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 16:30:33.942821 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 16:30:33.942872 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 16:30:33.942924 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3571 16:30:33.942976 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3572 16:30:33.943028 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3573 16:30:33.943080 Total UI for P1: 0, mck2ui 16
3574 16:30:33.943133 best dqsien dly found for B0: ( 1, 3, 28)
3575 16:30:33.943185 Total UI for P1: 0, mck2ui 16
3576 16:30:33.943238 best dqsien dly found for B1: ( 1, 3, 26)
3577 16:30:33.943291 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3578 16:30:33.943560 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3579 16:30:33.943619
3580 16:30:33.943672 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3581 16:30:33.943724 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3582 16:30:33.943777 [Gating] SW calibration Done
3583 16:30:33.943829 ==
3584 16:30:33.943883 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 16:30:33.943935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 16:30:33.943988 ==
3587 16:30:33.944040 RX Vref Scan: 0
3588 16:30:33.944092
3589 16:30:33.944162 RX Vref 0 -> 0, step: 1
3590 16:30:33.944215
3591 16:30:33.944268 RX Delay -40 -> 252, step: 8
3592 16:30:33.944320 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3593 16:30:33.944373 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3594 16:30:33.944425 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3595 16:30:33.944477 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3596 16:30:33.944530 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3597 16:30:33.944583 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3598 16:30:33.944635 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3599 16:30:33.944687 iDelay=208, Bit 7, Center 119 (48 ~ 191) 144
3600 16:30:33.944740 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3601 16:30:33.944793 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3602 16:30:33.944845 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3603 16:30:33.944897 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3604 16:30:33.944949 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3605 16:30:33.945001 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3606 16:30:33.945052 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3607 16:30:33.945104 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3608 16:30:33.945156 ==
3609 16:30:33.945208 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 16:30:33.945260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 16:30:33.945312 ==
3612 16:30:33.945364 DQS Delay:
3613 16:30:33.945416 DQS0 = 0, DQS1 = 0
3614 16:30:33.945468 DQM Delay:
3615 16:30:33.945520 DQM0 = 118, DQM1 = 110
3616 16:30:33.945572 DQ Delay:
3617 16:30:33.945624 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3618 16:30:33.945677 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3619 16:30:33.945729 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3620 16:30:33.945781 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3621 16:30:33.945833
3622 16:30:33.945885
3623 16:30:33.945935 ==
3624 16:30:33.945987 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 16:30:33.946039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 16:30:33.946092 ==
3627 16:30:33.946143
3628 16:30:33.946274
3629 16:30:33.946326 TX Vref Scan disable
3630 16:30:33.946379 == TX Byte 0 ==
3631 16:30:33.946432 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3632 16:30:33.946484 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3633 16:30:33.946537 == TX Byte 1 ==
3634 16:30:33.946588 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3635 16:30:33.946641 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3636 16:30:33.946693 ==
3637 16:30:33.946746 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 16:30:33.946798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 16:30:33.946851 ==
3640 16:30:33.946902 TX Vref=22, minBit 11, minWin=25, winSum=424
3641 16:30:33.946955 TX Vref=24, minBit 9, minWin=25, winSum=427
3642 16:30:33.947008 TX Vref=26, minBit 3, minWin=26, winSum=431
3643 16:30:33.947060 TX Vref=28, minBit 1, minWin=27, winSum=436
3644 16:30:33.947112 TX Vref=30, minBit 0, minWin=27, winSum=436
3645 16:30:33.947164 TX Vref=32, minBit 0, minWin=26, winSum=432
3646 16:30:33.947216 [TxChooseVref] Worse bit 1, Min win 27, Win sum 436, Final Vref 28
3647 16:30:33.947281
3648 16:30:33.947336 Final TX Range 1 Vref 28
3649 16:30:33.947389
3650 16:30:33.947441 ==
3651 16:30:33.947494 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 16:30:33.947546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 16:30:33.947598 ==
3654 16:30:33.947650
3655 16:30:33.947702
3656 16:30:33.947753 TX Vref Scan disable
3657 16:30:33.947805 == TX Byte 0 ==
3658 16:30:33.947858 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3659 16:30:33.947910 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3660 16:30:33.947963 == TX Byte 1 ==
3661 16:30:33.948015 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3662 16:30:33.948068 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3663 16:30:33.948120
3664 16:30:33.948172 [DATLAT]
3665 16:30:33.948223 Freq=1200, CH1 RK1
3666 16:30:33.948276
3667 16:30:33.948327 DATLAT Default: 0xd
3668 16:30:33.948379 0, 0xFFFF, sum = 0
3669 16:30:33.948433 1, 0xFFFF, sum = 0
3670 16:30:33.948486 2, 0xFFFF, sum = 0
3671 16:30:33.948539 3, 0xFFFF, sum = 0
3672 16:30:33.948592 4, 0xFFFF, sum = 0
3673 16:30:33.948645 5, 0xFFFF, sum = 0
3674 16:30:33.948697 6, 0xFFFF, sum = 0
3675 16:30:33.948750 7, 0xFFFF, sum = 0
3676 16:30:33.948803 8, 0xFFFF, sum = 0
3677 16:30:33.948855 9, 0xFFFF, sum = 0
3678 16:30:33.948908 10, 0xFFFF, sum = 0
3679 16:30:33.948961 11, 0xFFFF, sum = 0
3680 16:30:33.949014 12, 0x0, sum = 1
3681 16:30:33.949066 13, 0x0, sum = 2
3682 16:30:33.949119 14, 0x0, sum = 3
3683 16:30:33.949172 15, 0x0, sum = 4
3684 16:30:33.949226 best_step = 13
3685 16:30:33.949278
3686 16:30:33.949330 ==
3687 16:30:33.949382 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 16:30:33.949434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 16:30:33.949490 ==
3690 16:30:33.949549 RX Vref Scan: 0
3691 16:30:33.949601
3692 16:30:33.949653 RX Vref 0 -> 0, step: 1
3693 16:30:33.949704
3694 16:30:33.949756 RX Delay -21 -> 252, step: 4
3695 16:30:33.949807 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3696 16:30:33.949859 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3697 16:30:33.949911 iDelay=199, Bit 2, Center 108 (47 ~ 170) 124
3698 16:30:33.949963 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3699 16:30:33.950015 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3700 16:30:33.950067 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3701 16:30:33.950118 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3702 16:30:33.950203 iDelay=199, Bit 7, Center 118 (55 ~ 182) 128
3703 16:30:33.950299 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3704 16:30:33.950352 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3705 16:30:33.950404 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3706 16:30:33.950456 iDelay=199, Bit 11, Center 102 (39 ~ 166) 128
3707 16:30:33.950516 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3708 16:30:33.950581 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3709 16:30:33.950660 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3710 16:30:33.950793 iDelay=199, Bit 15, Center 122 (55 ~ 190) 136
3711 16:30:33.950875 ==
3712 16:30:33.950963 Dram Type= 6, Freq= 0, CH_1, rank 1
3713 16:30:33.951050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3714 16:30:33.951130 ==
3715 16:30:33.951228 DQS Delay:
3716 16:30:33.951280 DQS0 = 0, DQS1 = 0
3717 16:30:33.951333 DQM Delay:
3718 16:30:33.951386 DQM0 = 118, DQM1 = 112
3719 16:30:33.951438 DQ Delay:
3720 16:30:33.951491 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3721 16:30:33.951744 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =118
3722 16:30:33.951806 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =102
3723 16:30:33.951860 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3724 16:30:33.951914
3725 16:30:33.951967
3726 16:30:33.952019 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1ec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3727 16:30:33.952073 CH1 RK1: MR19=303, MR18=F1EC
3728 16:30:33.952125 CH1_RK1: MR19=0x303, MR18=0xF1EC, DQSOSC=416, MR23=63, INC=37, DEC=25
3729 16:30:33.952178 [RxdqsGatingPostProcess] freq 1200
3730 16:30:33.952231 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3731 16:30:33.952283 best DQS0 dly(2T, 0.5T) = (0, 11)
3732 16:30:33.952335 best DQS1 dly(2T, 0.5T) = (0, 11)
3733 16:30:33.952388 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3734 16:30:33.952439 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3735 16:30:33.952492 best DQS0 dly(2T, 0.5T) = (0, 11)
3736 16:30:33.952543 best DQS1 dly(2T, 0.5T) = (0, 11)
3737 16:30:33.952595 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3738 16:30:33.952647 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3739 16:30:33.952699 Pre-setting of DQS Precalculation
3740 16:30:33.952751 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3741 16:30:33.952804 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3742 16:30:33.952857 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3743 16:30:33.952909
3744 16:30:33.952961
3745 16:30:33.953012 [Calibration Summary] 2400 Mbps
3746 16:30:33.953064 CH 0, Rank 0
3747 16:30:33.953116 SW Impedance : PASS
3748 16:30:33.953168 DUTY Scan : NO K
3749 16:30:33.953220 ZQ Calibration : PASS
3750 16:30:33.953272 Jitter Meter : NO K
3751 16:30:33.953325 CBT Training : PASS
3752 16:30:33.953376 Write leveling : PASS
3753 16:30:33.953428 RX DQS gating : PASS
3754 16:30:33.953480 RX DQ/DQS(RDDQC) : PASS
3755 16:30:33.953531 TX DQ/DQS : PASS
3756 16:30:33.953584 RX DATLAT : PASS
3757 16:30:33.953636 RX DQ/DQS(Engine): PASS
3758 16:30:33.953687 TX OE : NO K
3759 16:30:33.953740 All Pass.
3760 16:30:33.953812
3761 16:30:33.953866 CH 0, Rank 1
3762 16:30:33.953918 SW Impedance : PASS
3763 16:30:33.953972 DUTY Scan : NO K
3764 16:30:33.954024 ZQ Calibration : PASS
3765 16:30:33.954076 Jitter Meter : NO K
3766 16:30:33.954138 CBT Training : PASS
3767 16:30:33.954240 Write leveling : PASS
3768 16:30:33.954294 RX DQS gating : PASS
3769 16:30:33.954347 RX DQ/DQS(RDDQC) : PASS
3770 16:30:33.954399 TX DQ/DQS : PASS
3771 16:30:33.954451 RX DATLAT : PASS
3772 16:30:33.954503 RX DQ/DQS(Engine): PASS
3773 16:30:33.954555 TX OE : NO K
3774 16:30:33.954607 All Pass.
3775 16:30:33.954659
3776 16:30:33.954710 CH 1, Rank 0
3777 16:30:33.954762 SW Impedance : PASS
3778 16:30:33.954814 DUTY Scan : NO K
3779 16:30:33.954866 ZQ Calibration : PASS
3780 16:30:33.954918 Jitter Meter : NO K
3781 16:30:33.954970 CBT Training : PASS
3782 16:30:33.955021 Write leveling : PASS
3783 16:30:33.955073 RX DQS gating : PASS
3784 16:30:33.955124 RX DQ/DQS(RDDQC) : PASS
3785 16:30:33.955176 TX DQ/DQS : PASS
3786 16:30:33.955228 RX DATLAT : PASS
3787 16:30:33.955280 RX DQ/DQS(Engine): PASS
3788 16:30:33.955332 TX OE : NO K
3789 16:30:33.955384 All Pass.
3790 16:30:33.955436
3791 16:30:33.955488 CH 1, Rank 1
3792 16:30:33.955540 SW Impedance : PASS
3793 16:30:33.955592 DUTY Scan : NO K
3794 16:30:33.955644 ZQ Calibration : PASS
3795 16:30:33.955696 Jitter Meter : NO K
3796 16:30:33.955747 CBT Training : PASS
3797 16:30:33.955799 Write leveling : PASS
3798 16:30:33.955851 RX DQS gating : PASS
3799 16:30:33.955903 RX DQ/DQS(RDDQC) : PASS
3800 16:30:33.955954 TX DQ/DQS : PASS
3801 16:30:33.956006 RX DATLAT : PASS
3802 16:30:33.956058 RX DQ/DQS(Engine): PASS
3803 16:30:33.956109 TX OE : NO K
3804 16:30:33.956161 All Pass.
3805 16:30:33.956213
3806 16:30:33.956264 DramC Write-DBI off
3807 16:30:33.956317 PER_BANK_REFRESH: Hybrid Mode
3808 16:30:33.956370 TX_TRACKING: ON
3809 16:30:33.956422 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3810 16:30:33.956475 [FAST_K] Save calibration result to emmc
3811 16:30:33.956527 dramc_set_vcore_voltage set vcore to 650000
3812 16:30:33.956580 Read voltage for 600, 5
3813 16:30:33.956631 Vio18 = 0
3814 16:30:33.956683 Vcore = 650000
3815 16:30:33.956734 Vdram = 0
3816 16:30:33.956786 Vddq = 0
3817 16:30:33.956837 Vmddr = 0
3818 16:30:33.956889 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3819 16:30:33.956942 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3820 16:30:33.957013 MEM_TYPE=3, freq_sel=19
3821 16:30:33.957067 sv_algorithm_assistance_LP4_1600
3822 16:30:33.957120 ============ PULL DRAM RESETB DOWN ============
3823 16:30:33.957172 ========== PULL DRAM RESETB DOWN end =========
3824 16:30:33.957225 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3825 16:30:33.957277 ===================================
3826 16:30:33.957329 LPDDR4 DRAM CONFIGURATION
3827 16:30:33.957382 ===================================
3828 16:30:33.957435 EX_ROW_EN[0] = 0x0
3829 16:30:33.957487 EX_ROW_EN[1] = 0x0
3830 16:30:33.957538 LP4Y_EN = 0x0
3831 16:30:33.957591 WORK_FSP = 0x0
3832 16:30:33.957643 WL = 0x2
3833 16:30:33.957694 RL = 0x2
3834 16:30:33.957746 BL = 0x2
3835 16:30:33.957798 RPST = 0x0
3836 16:30:33.957850 RD_PRE = 0x0
3837 16:30:33.957902 WR_PRE = 0x1
3838 16:30:33.957954 WR_PST = 0x0
3839 16:30:33.958005 DBI_WR = 0x0
3840 16:30:33.958057 DBI_RD = 0x0
3841 16:30:33.958109 OTF = 0x1
3842 16:30:33.958168 ===================================
3843 16:30:33.958260 ===================================
3844 16:30:33.958312 ANA top config
3845 16:30:33.958364 ===================================
3846 16:30:33.958416 DLL_ASYNC_EN = 0
3847 16:30:33.958467 ALL_SLAVE_EN = 1
3848 16:30:33.958520 NEW_RANK_MODE = 1
3849 16:30:33.958572 DLL_IDLE_MODE = 1
3850 16:30:33.958624 LP45_APHY_COMB_EN = 1
3851 16:30:33.958676 TX_ODT_DIS = 1
3852 16:30:33.958728 NEW_8X_MODE = 1
3853 16:30:33.958781 ===================================
3854 16:30:33.958834 ===================================
3855 16:30:33.958886 data_rate = 1200
3856 16:30:33.958937 CKR = 1
3857 16:30:33.958990 DQ_P2S_RATIO = 8
3858 16:30:33.959041 ===================================
3859 16:30:33.959093 CA_P2S_RATIO = 8
3860 16:30:33.959145 DQ_CA_OPEN = 0
3861 16:30:33.959197 DQ_SEMI_OPEN = 0
3862 16:30:33.959249 CA_SEMI_OPEN = 0
3863 16:30:33.959301 CA_FULL_RATE = 0
3864 16:30:33.959545 DQ_CKDIV4_EN = 1
3865 16:30:33.959603 CA_CKDIV4_EN = 1
3866 16:30:33.959656 CA_PREDIV_EN = 0
3867 16:30:33.959709 PH8_DLY = 0
3868 16:30:33.959761 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3869 16:30:33.959813 DQ_AAMCK_DIV = 4
3870 16:30:33.959866 CA_AAMCK_DIV = 4
3871 16:30:33.959918 CA_ADMCK_DIV = 4
3872 16:30:33.959970 DQ_TRACK_CA_EN = 0
3873 16:30:33.960034 CA_PICK = 600
3874 16:30:33.960088 CA_MCKIO = 600
3875 16:30:33.960141 MCKIO_SEMI = 0
3876 16:30:33.960194 PLL_FREQ = 2288
3877 16:30:33.960246 DQ_UI_PI_RATIO = 32
3878 16:30:33.960319 CA_UI_PI_RATIO = 0
3879 16:30:33.960376 ===================================
3880 16:30:33.960435 ===================================
3881 16:30:33.960488 memory_type:LPDDR4
3882 16:30:33.960542 GP_NUM : 10
3883 16:30:33.960594 SRAM_EN : 1
3884 16:30:33.960646 MD32_EN : 0
3885 16:30:33.960717 ===================================
3886 16:30:33.960773 [ANA_INIT] >>>>>>>>>>>>>>
3887 16:30:33.960826 <<<<<< [CONFIGURE PHASE]: ANA_TX
3888 16:30:33.960880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3889 16:30:33.960934 ===================================
3890 16:30:33.960986 data_rate = 1200,PCW = 0X5800
3891 16:30:33.961039 ===================================
3892 16:30:33.961092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3893 16:30:33.961145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3894 16:30:33.961198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3895 16:30:33.961251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3896 16:30:33.961303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3897 16:30:33.961356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3898 16:30:33.961409 [ANA_INIT] flow start
3899 16:30:33.961461 [ANA_INIT] PLL >>>>>>>>
3900 16:30:33.961513 [ANA_INIT] PLL <<<<<<<<
3901 16:30:33.961565 [ANA_INIT] MIDPI >>>>>>>>
3902 16:30:33.961617 [ANA_INIT] MIDPI <<<<<<<<
3903 16:30:33.961669 [ANA_INIT] DLL >>>>>>>>
3904 16:30:33.961720 [ANA_INIT] flow end
3905 16:30:33.961772 ============ LP4 DIFF to SE enter ============
3906 16:30:33.961825 ============ LP4 DIFF to SE exit ============
3907 16:30:33.961877 [ANA_INIT] <<<<<<<<<<<<<
3908 16:30:33.961929 [Flow] Enable top DCM control >>>>>
3909 16:30:33.961981 [Flow] Enable top DCM control <<<<<
3910 16:30:33.962035 Enable DLL master slave shuffle
3911 16:30:33.962127 ==============================================================
3912 16:30:33.962263 Gating Mode config
3913 16:30:33.962320 ==============================================================
3914 16:30:33.962375 Config description:
3915 16:30:33.962428 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3916 16:30:33.962483 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3917 16:30:33.962536 SELPH_MODE 0: By rank 1: By Phase
3918 16:30:33.962589 ==============================================================
3919 16:30:33.962642 GAT_TRACK_EN = 1
3920 16:30:33.962695 RX_GATING_MODE = 2
3921 16:30:33.962748 RX_GATING_TRACK_MODE = 2
3922 16:30:33.962800 SELPH_MODE = 1
3923 16:30:33.962852 PICG_EARLY_EN = 1
3924 16:30:33.962906 VALID_LAT_VALUE = 1
3925 16:30:33.962958 ==============================================================
3926 16:30:33.963011 Enter into Gating configuration >>>>
3927 16:30:33.963063 Exit from Gating configuration <<<<
3928 16:30:33.963115 Enter into DVFS_PRE_config >>>>>
3929 16:30:33.963167 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3930 16:30:33.963221 Exit from DVFS_PRE_config <<<<<
3931 16:30:33.963273 Enter into PICG configuration >>>>
3932 16:30:33.963325 Exit from PICG configuration <<<<
3933 16:30:33.963377 [RX_INPUT] configuration >>>>>
3934 16:30:33.963429 [RX_INPUT] configuration <<<<<
3935 16:30:33.963481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3936 16:30:33.963533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3937 16:30:33.963585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3938 16:30:33.963638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3939 16:30:33.963690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3940 16:30:33.963742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3941 16:30:33.963808 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3942 16:30:33.963864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3943 16:30:33.963931 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3944 16:30:33.966821 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3945 16:30:33.970692 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3946 16:30:33.976989 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 16:30:33.980239 ===================================
3948 16:30:33.980320 LPDDR4 DRAM CONFIGURATION
3949 16:30:33.983640 ===================================
3950 16:30:33.987069 EX_ROW_EN[0] = 0x0
3951 16:30:33.990091 EX_ROW_EN[1] = 0x0
3952 16:30:33.990215 LP4Y_EN = 0x0
3953 16:30:33.993725 WORK_FSP = 0x0
3954 16:30:33.993806 WL = 0x2
3955 16:30:33.996743 RL = 0x2
3956 16:30:33.996824 BL = 0x2
3957 16:30:33.999975 RPST = 0x0
3958 16:30:34.000056 RD_PRE = 0x0
3959 16:30:34.003167 WR_PRE = 0x1
3960 16:30:34.003249 WR_PST = 0x0
3961 16:30:34.006980 DBI_WR = 0x0
3962 16:30:34.007114 DBI_RD = 0x0
3963 16:30:34.009892 OTF = 0x1
3964 16:30:34.012838 ===================================
3965 16:30:34.016793 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3966 16:30:34.019926 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3967 16:30:34.026155 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3968 16:30:34.029942 ===================================
3969 16:30:34.030102 LPDDR4 DRAM CONFIGURATION
3970 16:30:34.032834 ===================================
3971 16:30:34.036089 EX_ROW_EN[0] = 0x10
3972 16:30:34.039381 EX_ROW_EN[1] = 0x0
3973 16:30:34.039532 LP4Y_EN = 0x0
3974 16:30:34.042755 WORK_FSP = 0x0
3975 16:30:34.042927 WL = 0x2
3976 16:30:34.046074 RL = 0x2
3977 16:30:34.046306 BL = 0x2
3978 16:30:34.049368 RPST = 0x0
3979 16:30:34.049567 RD_PRE = 0x0
3980 16:30:34.052649 WR_PRE = 0x1
3981 16:30:34.053087 WR_PST = 0x0
3982 16:30:34.055988 DBI_WR = 0x0
3983 16:30:34.056406 DBI_RD = 0x0
3984 16:30:34.059625 OTF = 0x1
3985 16:30:34.063034 ===================================
3986 16:30:34.069292 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3987 16:30:34.072993 nWR fixed to 30
3988 16:30:34.076150 [ModeRegInit_LP4] CH0 RK0
3989 16:30:34.076565 [ModeRegInit_LP4] CH0 RK1
3990 16:30:34.079202 [ModeRegInit_LP4] CH1 RK0
3991 16:30:34.082902 [ModeRegInit_LP4] CH1 RK1
3992 16:30:34.083320 match AC timing 17
3993 16:30:34.089377 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3994 16:30:34.092754 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3995 16:30:34.095783 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3996 16:30:34.102453 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3997 16:30:34.105645 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3998 16:30:34.106066 ==
3999 16:30:34.108915 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 16:30:34.304857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 16:30:34.305014 ==
4002 16:30:34.305097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4003 16:30:34.305174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4004 16:30:34.305248 [CA 0] Center 36 (6~66) winsize 61
4005 16:30:34.305321 [CA 1] Center 36 (6~66) winsize 61
4006 16:30:34.305390 [CA 2] Center 34 (4~65) winsize 62
4007 16:30:34.305459 [CA 3] Center 34 (4~65) winsize 62
4008 16:30:34.305527 [CA 4] Center 33 (3~64) winsize 62
4009 16:30:34.305595 [CA 5] Center 33 (3~64) winsize 62
4010 16:30:34.305663
4011 16:30:34.305730 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4012 16:30:34.305797
4013 16:30:34.305863 [CATrainingPosCal] consider 1 rank data
4014 16:30:34.305931 u2DelayCellTimex100 = 270/100 ps
4015 16:30:34.305998 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4016 16:30:34.306065 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4017 16:30:34.306132 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4018 16:30:34.306212 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4019 16:30:34.306280 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4020 16:30:34.306346 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4021 16:30:34.306413
4022 16:30:34.306478 CA PerBit enable=1, Macro0, CA PI delay=33
4023 16:30:34.306545
4024 16:30:34.306611 [CBTSetCACLKResult] CA Dly = 33
4025 16:30:34.306691 CS Dly: 6 (0~37)
4026 16:30:34.306763 ==
4027 16:30:34.306835 Dram Type= 6, Freq= 0, CH_0, rank 1
4028 16:30:34.306908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 16:30:34.306981 ==
4030 16:30:34.307053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4031 16:30:34.307126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4032 16:30:34.307199 [CA 0] Center 36 (6~66) winsize 61
4033 16:30:34.307271 [CA 1] Center 36 (6~66) winsize 61
4034 16:30:34.307343 [CA 2] Center 33 (3~64) winsize 62
4035 16:30:34.307416 [CA 3] Center 33 (3~64) winsize 62
4036 16:30:34.307488 [CA 4] Center 33 (2~64) winsize 63
4037 16:30:34.307560 [CA 5] Center 33 (2~64) winsize 63
4038 16:30:34.307632
4039 16:30:34.307703 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4040 16:30:34.307775
4041 16:30:34.307847 [CATrainingPosCal] consider 2 rank data
4042 16:30:34.307918 u2DelayCellTimex100 = 270/100 ps
4043 16:30:34.308006 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4044 16:30:34.308088 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4045 16:30:34.308171 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4046 16:30:34.308260 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4047 16:30:34.308333 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4048 16:30:34.308406 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4049 16:30:34.308478
4050 16:30:34.308589 CA PerBit enable=1, Macro0, CA PI delay=33
4051 16:30:34.308672
4052 16:30:34.308746 [CBTSetCACLKResult] CA Dly = 33
4053 16:30:34.308820 CS Dly: 6 (0~37)
4054 16:30:34.308892
4055 16:30:34.308965 ----->DramcWriteLeveling(PI) begin...
4056 16:30:34.309039 ==
4057 16:30:34.309112 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 16:30:34.309185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 16:30:34.309258 ==
4060 16:30:34.309331 Write leveling (Byte 0): 32 => 32
4061 16:30:34.309403 Write leveling (Byte 1): 29 => 29
4062 16:30:34.309477 DramcWriteLeveling(PI) end<-----
4063 16:30:34.309548
4064 16:30:34.309620 ==
4065 16:30:34.309691 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 16:30:34.309764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 16:30:34.309837 ==
4068 16:30:34.309909 [Gating] SW mode calibration
4069 16:30:34.309982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4070 16:30:34.310075 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4071 16:30:34.313309 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4072 16:30:34.316494 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4073 16:30:34.323100 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4074 16:30:34.326316 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
4075 16:30:34.329254 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (1 0)
4076 16:30:34.336232 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 16:30:34.339430 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 16:30:34.342737 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 16:30:34.349827 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 16:30:34.353350 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 16:30:34.356578 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 16:30:34.362988 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4083 16:30:34.365978 0 10 16 | B1->B0 | 3737 3f3f | 0 0 | (1 1) (0 0)
4084 16:30:34.369791 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 16:30:34.376119 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 16:30:34.379435 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 16:30:34.382424 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 16:30:34.389387 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 16:30:34.392469 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 16:30:34.395750 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 16:30:34.402434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4092 16:30:34.405529 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 16:30:34.408727 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 16:30:34.415360 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 16:30:34.418553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 16:30:34.422157 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 16:30:34.428600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 16:30:34.431743 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 16:30:34.438200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 16:30:34.441518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 16:30:34.444944 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 16:30:34.451239 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 16:30:34.454883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 16:30:34.458080 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 16:30:34.464419 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 16:30:34.467947 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4107 16:30:34.471080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4108 16:30:34.477528 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 16:30:34.477968 Total UI for P1: 0, mck2ui 16
4110 16:30:34.484521 best dqsien dly found for B0: ( 0, 13, 14)
4111 16:30:34.484950 Total UI for P1: 0, mck2ui 16
4112 16:30:34.487530 best dqsien dly found for B1: ( 0, 13, 18)
4113 16:30:34.494116 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4114 16:30:34.497354 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4115 16:30:34.497959
4116 16:30:34.500273 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4117 16:30:34.503963 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4118 16:30:34.506931 [Gating] SW calibration Done
4119 16:30:34.507366 ==
4120 16:30:34.510575 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 16:30:34.513660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 16:30:34.514090 ==
4123 16:30:34.516942 RX Vref Scan: 0
4124 16:30:34.517371
4125 16:30:34.517709 RX Vref 0 -> 0, step: 1
4126 16:30:34.520145
4127 16:30:34.520568 RX Delay -230 -> 252, step: 16
4128 16:30:34.527304 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4129 16:30:34.530488 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4130 16:30:34.533666 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4131 16:30:34.536706 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4132 16:30:34.540175 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4133 16:30:34.546759 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4134 16:30:34.549909 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4135 16:30:34.553125 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4136 16:30:34.556936 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4137 16:30:34.563276 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4138 16:30:34.566601 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4139 16:30:34.569820 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4140 16:30:34.573149 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4141 16:30:34.579597 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4142 16:30:34.583398 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4143 16:30:34.586639 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4144 16:30:34.587068 ==
4145 16:30:34.589825 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 16:30:34.596141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 16:30:34.596572 ==
4148 16:30:34.596915 DQS Delay:
4149 16:30:34.597253 DQS0 = 0, DQS1 = 0
4150 16:30:34.599903 DQM Delay:
4151 16:30:34.600369 DQM0 = 42, DQM1 = 33
4152 16:30:34.602965 DQ Delay:
4153 16:30:34.606386 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4154 16:30:34.606812 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4155 16:30:34.609439 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4156 16:30:34.616121 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4157 16:30:34.616545
4158 16:30:34.616881
4159 16:30:34.617193 ==
4160 16:30:34.619388 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 16:30:34.622390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 16:30:34.622821 ==
4163 16:30:34.623157
4164 16:30:34.623469
4165 16:30:34.626345 TX Vref Scan disable
4166 16:30:34.626770 == TX Byte 0 ==
4167 16:30:34.632734 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4168 16:30:34.635907 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4169 16:30:34.636349 == TX Byte 1 ==
4170 16:30:34.642242 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4171 16:30:34.645375 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4172 16:30:34.646010 ==
4173 16:30:34.649029 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 16:30:34.652098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 16:30:34.652726 ==
4176 16:30:34.655703
4177 16:30:34.656278
4178 16:30:34.656765 TX Vref Scan disable
4179 16:30:34.659317 == TX Byte 0 ==
4180 16:30:34.662492 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4181 16:30:34.669373 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4182 16:30:34.669766 == TX Byte 1 ==
4183 16:30:34.672228 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4184 16:30:34.678705 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4185 16:30:34.678931
4186 16:30:34.679107 [DATLAT]
4187 16:30:34.679272 Freq=600, CH0 RK0
4188 16:30:34.679434
4189 16:30:34.681820 DATLAT Default: 0x9
4190 16:30:34.685107 0, 0xFFFF, sum = 0
4191 16:30:34.685366 1, 0xFFFF, sum = 0
4192 16:30:34.688326 2, 0xFFFF, sum = 0
4193 16:30:34.688561 3, 0xFFFF, sum = 0
4194 16:30:34.691932 4, 0xFFFF, sum = 0
4195 16:30:34.692171 5, 0xFFFF, sum = 0
4196 16:30:34.695405 6, 0xFFFF, sum = 0
4197 16:30:34.695718 7, 0xFFFF, sum = 0
4198 16:30:34.698614 8, 0x0, sum = 1
4199 16:30:34.698848 9, 0x0, sum = 2
4200 16:30:34.701591 10, 0x0, sum = 3
4201 16:30:34.701825 11, 0x0, sum = 4
4202 16:30:34.702120 best_step = 9
4203 16:30:34.702340
4204 16:30:34.704767 ==
4205 16:30:34.708571 Dram Type= 6, Freq= 0, CH_0, rank 0
4206 16:30:34.711875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 16:30:34.712105 ==
4208 16:30:34.712295 RX Vref Scan: 1
4209 16:30:34.712465
4210 16:30:34.715132 RX Vref 0 -> 0, step: 1
4211 16:30:34.715359
4212 16:30:34.718306 RX Delay -179 -> 252, step: 8
4213 16:30:34.718675
4214 16:30:34.721407 Set Vref, RX VrefLevel [Byte0]: 60
4215 16:30:34.724817 [Byte1]: 49
4216 16:30:34.725109
4217 16:30:34.728224 Final RX Vref Byte 0 = 60 to rank0
4218 16:30:34.731409 Final RX Vref Byte 1 = 49 to rank0
4219 16:30:34.734483 Final RX Vref Byte 0 = 60 to rank1
4220 16:30:34.737647 Final RX Vref Byte 1 = 49 to rank1==
4221 16:30:34.740891 Dram Type= 6, Freq= 0, CH_0, rank 0
4222 16:30:34.747896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 16:30:34.748203 ==
4224 16:30:34.748496 DQS Delay:
4225 16:30:34.748770 DQS0 = 0, DQS1 = 0
4226 16:30:34.751241 DQM Delay:
4227 16:30:34.751542 DQM0 = 43, DQM1 = 32
4228 16:30:34.754310 DQ Delay:
4229 16:30:34.757589 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4230 16:30:34.760871 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4231 16:30:34.764413 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4232 16:30:34.767621 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4233 16:30:34.767901
4234 16:30:34.768122
4235 16:30:34.774242 [DQSOSCAuto] RK0, (LSB)MR18= 0x623a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4236 16:30:34.777368 CH0 RK0: MR19=808, MR18=623A
4237 16:30:34.784003 CH0_RK0: MR19=0x808, MR18=0x623A, DQSOSC=391, MR23=63, INC=171, DEC=114
4238 16:30:34.784367
4239 16:30:34.787647 ----->DramcWriteLeveling(PI) begin...
4240 16:30:34.788094 ==
4241 16:30:34.790726 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 16:30:34.793813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 16:30:34.794386 ==
4244 16:30:34.797232 Write leveling (Byte 0): 32 => 32
4245 16:30:34.800576 Write leveling (Byte 1): 28 => 28
4246 16:30:34.804406 DramcWriteLeveling(PI) end<-----
4247 16:30:34.804846
4248 16:30:34.805187 ==
4249 16:30:34.807684 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 16:30:34.810674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 16:30:34.811114 ==
4252 16:30:34.813892 [Gating] SW mode calibration
4253 16:30:34.820574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4254 16:30:34.827383 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4255 16:30:34.830433 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4256 16:30:34.836995 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4257 16:30:34.840038 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4258 16:30:34.843749 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4259 16:30:34.850068 0 9 16 | B1->B0 | 2929 2727 | 0 0 | (0 0) (1 0)
4260 16:30:34.853415 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 16:30:34.856656 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 16:30:34.863569 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 16:30:34.866727 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 16:30:34.869762 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 16:30:34.876727 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 16:30:34.879815 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4267 16:30:34.883231 0 10 16 | B1->B0 | 3939 3e3e | 0 1 | (0 0) (0 0)
4268 16:30:34.890112 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 16:30:34.893177 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 16:30:34.896399 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 16:30:34.903300 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 16:30:34.905899 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 16:30:34.909508 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 16:30:34.915643 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4275 16:30:34.919399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 16:30:34.922302 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 16:30:34.928822 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 16:30:34.932519 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 16:30:34.935786 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 16:30:34.942213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 16:30:34.945309 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 16:30:34.948290 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 16:30:34.955423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 16:30:34.958586 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 16:30:34.961784 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 16:30:34.968327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 16:30:34.971976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 16:30:34.975149 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 16:30:34.981500 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 16:30:34.985112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4291 16:30:34.988128 Total UI for P1: 0, mck2ui 16
4292 16:30:34.991293 best dqsien dly found for B0: ( 0, 13, 10)
4293 16:30:34.995146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 16:30:34.998202 Total UI for P1: 0, mck2ui 16
4295 16:30:35.001426 best dqsien dly found for B1: ( 0, 13, 12)
4296 16:30:35.004684 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4297 16:30:35.007927 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4298 16:30:35.008028
4299 16:30:35.014986 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4300 16:30:35.018028 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4301 16:30:35.021406 [Gating] SW calibration Done
4302 16:30:35.021496 ==
4303 16:30:35.024350 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 16:30:35.027904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 16:30:35.028008 ==
4306 16:30:35.028100 RX Vref Scan: 0
4307 16:30:35.028189
4308 16:30:35.031052 RX Vref 0 -> 0, step: 1
4309 16:30:35.031152
4310 16:30:35.034321 RX Delay -230 -> 252, step: 16
4311 16:30:35.037858 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4312 16:30:35.044259 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4313 16:30:35.047505 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4314 16:30:35.050655 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4315 16:30:35.053892 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4316 16:30:35.057279 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4317 16:30:35.063890 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4318 16:30:35.067216 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4319 16:30:35.070494 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4320 16:30:35.073771 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4321 16:30:35.080732 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4322 16:30:35.083856 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4323 16:30:35.087129 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4324 16:30:35.090344 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4325 16:30:35.096905 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4326 16:30:35.100664 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4327 16:30:35.100769 ==
4328 16:30:35.104015 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 16:30:35.107040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 16:30:35.107144 ==
4331 16:30:35.110351 DQS Delay:
4332 16:30:35.110431 DQS0 = 0, DQS1 = 0
4333 16:30:35.110495 DQM Delay:
4334 16:30:35.113501 DQM0 = 42, DQM1 = 34
4335 16:30:35.113592 DQ Delay:
4336 16:30:35.116699 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4337 16:30:35.120532 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4338 16:30:35.123696 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4339 16:30:35.126803 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4340 16:30:35.126893
4341 16:30:35.126986
4342 16:30:35.127081 ==
4343 16:30:35.129935 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 16:30:35.136724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 16:30:35.136836 ==
4346 16:30:35.136929
4347 16:30:35.137030
4348 16:30:35.137119 TX Vref Scan disable
4349 16:30:35.140765 == TX Byte 0 ==
4350 16:30:35.143871 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4351 16:30:35.150773 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4352 16:30:35.150897 == TX Byte 1 ==
4353 16:30:35.154035 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4354 16:30:35.160656 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4355 16:30:35.160769 ==
4356 16:30:35.163419 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 16:30:35.166708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 16:30:35.166810 ==
4359 16:30:35.166876
4360 16:30:35.166936
4361 16:30:35.170036 TX Vref Scan disable
4362 16:30:35.173783 == TX Byte 0 ==
4363 16:30:35.176610 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4364 16:30:35.179874 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4365 16:30:35.183293 == TX Byte 1 ==
4366 16:30:35.186925 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4367 16:30:35.190298 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4368 16:30:35.190373
4369 16:30:35.193485 [DATLAT]
4370 16:30:35.193587 Freq=600, CH0 RK1
4371 16:30:35.193678
4372 16:30:35.196740 DATLAT Default: 0x9
4373 16:30:35.196845 0, 0xFFFF, sum = 0
4374 16:30:35.199904 1, 0xFFFF, sum = 0
4375 16:30:35.200007 2, 0xFFFF, sum = 0
4376 16:30:35.202911 3, 0xFFFF, sum = 0
4377 16:30:35.203024 4, 0xFFFF, sum = 0
4378 16:30:35.206373 5, 0xFFFF, sum = 0
4379 16:30:35.206455 6, 0xFFFF, sum = 0
4380 16:30:35.209987 7, 0xFFFF, sum = 0
4381 16:30:35.210095 8, 0x0, sum = 1
4382 16:30:35.213311 9, 0x0, sum = 2
4383 16:30:35.213387 10, 0x0, sum = 3
4384 16:30:35.216387 11, 0x0, sum = 4
4385 16:30:35.216494 best_step = 9
4386 16:30:35.216585
4387 16:30:35.216676 ==
4388 16:30:35.219765 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 16:30:35.222844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 16:30:35.226007 ==
4391 16:30:35.226110 RX Vref Scan: 0
4392 16:30:35.226237
4393 16:30:35.229301 RX Vref 0 -> 0, step: 1
4394 16:30:35.229380
4395 16:30:35.232941 RX Delay -195 -> 252, step: 8
4396 16:30:35.235830 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4397 16:30:35.239147 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4398 16:30:35.246276 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4399 16:30:35.249432 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4400 16:30:35.252511 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4401 16:30:35.255825 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4402 16:30:35.262188 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4403 16:30:35.265977 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4404 16:30:35.268891 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4405 16:30:35.272051 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4406 16:30:35.279032 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4407 16:30:35.282221 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4408 16:30:35.285470 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4409 16:30:35.288824 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4410 16:30:35.295513 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4411 16:30:35.298514 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4412 16:30:35.298590 ==
4413 16:30:35.302153 Dram Type= 6, Freq= 0, CH_0, rank 1
4414 16:30:35.304965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 16:30:35.305054 ==
4416 16:30:35.308393 DQS Delay:
4417 16:30:35.308494 DQS0 = 0, DQS1 = 0
4418 16:30:35.308584 DQM Delay:
4419 16:30:35.312029 DQM0 = 41, DQM1 = 37
4420 16:30:35.312131 DQ Delay:
4421 16:30:35.314999 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4422 16:30:35.318664 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4423 16:30:35.321833 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4424 16:30:35.325016 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4425 16:30:35.325129
4426 16:30:35.325220
4427 16:30:35.335147 [DQSOSCAuto] RK1, (LSB)MR18= 0x6215, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4428 16:30:35.335265 CH0 RK1: MR19=808, MR18=6215
4429 16:30:35.341984 CH0_RK1: MR19=0x808, MR18=0x6215, DQSOSC=391, MR23=63, INC=171, DEC=114
4430 16:30:35.345090 [RxdqsGatingPostProcess] freq 600
4431 16:30:35.351474 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4432 16:30:35.354715 Pre-setting of DQS Precalculation
4433 16:30:35.357828 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4434 16:30:35.357931 ==
4435 16:30:35.361729 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 16:30:35.368211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 16:30:35.368317 ==
4438 16:30:35.371145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 16:30:35.378199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4440 16:30:35.381457 [CA 0] Center 35 (5~66) winsize 62
4441 16:30:35.384502 [CA 1] Center 35 (5~66) winsize 62
4442 16:30:35.387627 [CA 2] Center 34 (4~65) winsize 62
4443 16:30:35.390776 [CA 3] Center 33 (3~64) winsize 62
4444 16:30:35.394005 [CA 4] Center 34 (4~64) winsize 61
4445 16:30:35.397860 [CA 5] Center 33 (3~64) winsize 62
4446 16:30:35.397966
4447 16:30:35.400843 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4448 16:30:35.400942
4449 16:30:35.404378 [CATrainingPosCal] consider 1 rank data
4450 16:30:35.407331 u2DelayCellTimex100 = 270/100 ps
4451 16:30:35.410818 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4452 16:30:35.417573 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4453 16:30:35.420755 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 16:30:35.423773 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4455 16:30:35.427465 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4456 16:30:35.430812 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 16:30:35.430915
4458 16:30:35.433704 CA PerBit enable=1, Macro0, CA PI delay=33
4459 16:30:35.433810
4460 16:30:35.437517 [CBTSetCACLKResult] CA Dly = 33
4461 16:30:35.440641 CS Dly: 4 (0~35)
4462 16:30:35.440785 ==
4463 16:30:35.443754 Dram Type= 6, Freq= 0, CH_1, rank 1
4464 16:30:35.447044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 16:30:35.447156 ==
4466 16:30:35.453916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4467 16:30:35.457218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4468 16:30:35.461808 [CA 0] Center 35 (5~66) winsize 62
4469 16:30:35.464954 [CA 1] Center 36 (6~66) winsize 61
4470 16:30:35.468155 [CA 2] Center 34 (4~65) winsize 62
4471 16:30:35.471503 [CA 3] Center 34 (3~65) winsize 63
4472 16:30:35.474637 [CA 4] Center 34 (4~65) winsize 62
4473 16:30:35.477842 [CA 5] Center 34 (3~65) winsize 63
4474 16:30:35.478080
4475 16:30:35.481706 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4476 16:30:35.482099
4477 16:30:35.485000 [CATrainingPosCal] consider 2 rank data
4478 16:30:35.488181 u2DelayCellTimex100 = 270/100 ps
4479 16:30:35.491315 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4480 16:30:35.497795 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4481 16:30:35.500785 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4482 16:30:35.504640 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4483 16:30:35.507634 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4484 16:30:35.510907 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4485 16:30:35.511588
4486 16:30:35.514598 CA PerBit enable=1, Macro0, CA PI delay=33
4487 16:30:35.515104
4488 16:30:35.517875 [CBTSetCACLKResult] CA Dly = 33
4489 16:30:35.520906 CS Dly: 4 (0~36)
4490 16:30:35.521455
4491 16:30:35.524671 ----->DramcWriteLeveling(PI) begin...
4492 16:30:35.525096 ==
4493 16:30:35.527677 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 16:30:35.530654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 16:30:35.531192 ==
4496 16:30:35.534036 Write leveling (Byte 0): 29 => 29
4497 16:30:35.537469 Write leveling (Byte 1): 32 => 32
4498 16:30:35.541039 DramcWriteLeveling(PI) end<-----
4499 16:30:35.541652
4500 16:30:35.542264 ==
4501 16:30:35.544015 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 16:30:35.547521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 16:30:35.548078 ==
4504 16:30:35.550891 [Gating] SW mode calibration
4505 16:30:35.557274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4506 16:30:35.563829 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4507 16:30:35.567637 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4508 16:30:35.570670 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4509 16:30:35.577061 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4510 16:30:35.580148 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
4511 16:30:35.583810 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4512 16:30:35.590238 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 16:30:35.593429 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 16:30:35.597337 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 16:30:35.603765 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 16:30:35.606922 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 16:30:35.609876 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 16:30:35.616793 0 10 12 | B1->B0 | 2a2a 3d3d | 0 0 | (0 0) (0 0)
4519 16:30:35.619947 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4520 16:30:35.623218 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 16:30:35.629754 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 16:30:35.633172 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 16:30:35.636266 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 16:30:35.643086 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 16:30:35.646431 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4526 16:30:35.649766 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4527 16:30:35.656491 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4528 16:30:35.659813 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 16:30:35.662948 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 16:30:35.669778 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 16:30:35.672521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 16:30:35.675805 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 16:30:35.682623 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 16:30:35.686431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 16:30:35.689443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 16:30:35.695796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 16:30:35.699144 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 16:30:35.702803 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 16:30:35.709303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 16:30:35.712314 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 16:30:35.716085 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 16:30:35.722154 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4543 16:30:35.725899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 16:30:35.729170 Total UI for P1: 0, mck2ui 16
4545 16:30:35.732230 best dqsien dly found for B0: ( 0, 13, 12)
4546 16:30:35.735289 Total UI for P1: 0, mck2ui 16
4547 16:30:35.739228 best dqsien dly found for B1: ( 0, 13, 14)
4548 16:30:35.742279 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4549 16:30:35.745657 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4550 16:30:35.746130
4551 16:30:35.748704 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4552 16:30:35.751917 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4553 16:30:35.755443 [Gating] SW calibration Done
4554 16:30:35.755927 ==
4555 16:30:35.758264 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 16:30:35.765046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 16:30:35.765481 ==
4558 16:30:35.765814 RX Vref Scan: 0
4559 16:30:35.766123
4560 16:30:35.768047 RX Vref 0 -> 0, step: 1
4561 16:30:35.768619
4562 16:30:35.772135 RX Delay -230 -> 252, step: 16
4563 16:30:35.775271 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4564 16:30:35.778316 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4565 16:30:35.781939 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4566 16:30:35.788474 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4567 16:30:35.791463 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4568 16:30:35.794842 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4569 16:30:35.798249 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4570 16:30:35.804826 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4571 16:30:35.808095 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4572 16:30:35.811244 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4573 16:30:35.815091 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4574 16:30:35.821224 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4575 16:30:35.824406 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4576 16:30:35.827496 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4577 16:30:35.830709 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4578 16:30:35.837655 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4579 16:30:35.838260 ==
4580 16:30:35.840663 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 16:30:35.843908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 16:30:35.844374 ==
4583 16:30:35.844704 DQS Delay:
4584 16:30:35.847184 DQS0 = 0, DQS1 = 0
4585 16:30:35.847693 DQM Delay:
4586 16:30:35.851089 DQM0 = 46, DQM1 = 37
4587 16:30:35.851503 DQ Delay:
4588 16:30:35.854271 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4589 16:30:35.857430 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4590 16:30:35.860393 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4591 16:30:35.864160 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4592 16:30:35.864851
4593 16:30:35.865430
4594 16:30:35.865941 ==
4595 16:30:35.867060 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 16:30:35.870292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 16:30:35.873745 ==
4598 16:30:35.874143
4599 16:30:35.874563
4600 16:30:35.874865 TX Vref Scan disable
4601 16:30:35.877197 == TX Byte 0 ==
4602 16:30:35.880604 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4603 16:30:35.886831 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4604 16:30:35.887248 == TX Byte 1 ==
4605 16:30:35.889960 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4606 16:30:35.896272 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4607 16:30:35.896763 ==
4608 16:30:35.899889 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 16:30:35.903140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 16:30:35.903608 ==
4611 16:30:35.904047
4612 16:30:35.904469
4613 16:30:35.906444 TX Vref Scan disable
4614 16:30:35.909894 == TX Byte 0 ==
4615 16:30:35.912811 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4616 16:30:35.916863 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4617 16:30:35.919676 == TX Byte 1 ==
4618 16:30:35.922932 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4619 16:30:35.926063 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4620 16:30:35.926541
4621 16:30:35.929860 [DATLAT]
4622 16:30:35.930444 Freq=600, CH1 RK0
4623 16:30:35.930811
4624 16:30:35.932875 DATLAT Default: 0x9
4625 16:30:35.933298 0, 0xFFFF, sum = 0
4626 16:30:35.936174 1, 0xFFFF, sum = 0
4627 16:30:35.936606 2, 0xFFFF, sum = 0
4628 16:30:35.940040 3, 0xFFFF, sum = 0
4629 16:30:35.940473 4, 0xFFFF, sum = 0
4630 16:30:35.943074 5, 0xFFFF, sum = 0
4631 16:30:35.943504 6, 0xFFFF, sum = 0
4632 16:30:35.946303 7, 0xFFFF, sum = 0
4633 16:30:35.946815 8, 0x0, sum = 1
4634 16:30:35.949611 9, 0x0, sum = 2
4635 16:30:35.950042 10, 0x0, sum = 3
4636 16:30:35.952709 11, 0x0, sum = 4
4637 16:30:35.953142 best_step = 9
4638 16:30:35.953480
4639 16:30:35.953795 ==
4640 16:30:35.955782 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 16:30:35.959134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 16:30:35.962359 ==
4643 16:30:35.962783 RX Vref Scan: 1
4644 16:30:35.963125
4645 16:30:35.966247 RX Vref 0 -> 0, step: 1
4646 16:30:35.966672
4647 16:30:35.969163 RX Delay -195 -> 252, step: 8
4648 16:30:35.969598
4649 16:30:35.972309 Set Vref, RX VrefLevel [Byte0]: 52
4650 16:30:35.975533 [Byte1]: 57
4651 16:30:35.975958
4652 16:30:35.979468 Final RX Vref Byte 0 = 52 to rank0
4653 16:30:35.982365 Final RX Vref Byte 1 = 57 to rank0
4654 16:30:35.985931 Final RX Vref Byte 0 = 52 to rank1
4655 16:30:35.988935 Final RX Vref Byte 1 = 57 to rank1==
4656 16:30:35.992400 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 16:30:35.995226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 16:30:35.995697 ==
4659 16:30:35.998955 DQS Delay:
4660 16:30:35.999380 DQS0 = 0, DQS1 = 0
4661 16:30:35.999712 DQM Delay:
4662 16:30:36.002243 DQM0 = 47, DQM1 = 37
4663 16:30:36.002663 DQ Delay:
4664 16:30:36.005597 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4665 16:30:36.008412 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4666 16:30:36.011633 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4667 16:30:36.015391 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4668 16:30:36.015882
4669 16:30:36.016249
4670 16:30:36.024679 [DQSOSCAuto] RK0, (LSB)MR18= 0x5237, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4671 16:30:36.028479 CH1 RK0: MR19=808, MR18=5237
4672 16:30:36.031632 CH1_RK0: MR19=0x808, MR18=0x5237, DQSOSC=394, MR23=63, INC=168, DEC=112
4673 16:30:36.034710
4674 16:30:36.038022 ----->DramcWriteLeveling(PI) begin...
4675 16:30:36.038552 ==
4676 16:30:36.041122 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 16:30:36.045069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 16:30:36.045495 ==
4679 16:30:36.048154 Write leveling (Byte 0): 30 => 30
4680 16:30:36.051394 Write leveling (Byte 1): 30 => 30
4681 16:30:36.054745 DramcWriteLeveling(PI) end<-----
4682 16:30:36.055167
4683 16:30:36.055605 ==
4684 16:30:36.058027 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 16:30:36.061086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 16:30:36.061589 ==
4687 16:30:36.064185 [Gating] SW mode calibration
4688 16:30:36.070884 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4689 16:30:36.077387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4690 16:30:36.080686 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4691 16:30:36.083968 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4692 16:30:36.090196 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4693 16:30:36.093533 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
4694 16:30:36.097059 0 9 16 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 0)
4695 16:30:36.103262 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 16:30:36.106867 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 16:30:36.109960 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 16:30:36.116836 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 16:30:36.119856 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4700 16:30:36.123621 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 16:30:36.129976 0 10 12 | B1->B0 | 3434 2626 | 0 0 | (1 1) (0 0)
4702 16:30:36.133113 0 10 16 | B1->B0 | 4444 4242 | 0 0 | (0 0) (0 0)
4703 16:30:36.136182 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 16:30:36.143215 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 16:30:36.146526 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 16:30:36.149461 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 16:30:36.156123 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 16:30:36.159334 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 16:30:36.163112 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4710 16:30:36.169613 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 16:30:36.172878 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 16:30:36.176065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 16:30:36.183173 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 16:30:36.186275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 16:30:36.189412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 16:30:36.196181 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 16:30:36.199462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 16:30:36.202786 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 16:30:36.208986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 16:30:36.212401 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 16:30:36.215713 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 16:30:36.222392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 16:30:36.225752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 16:30:36.229243 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 16:30:36.235771 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 16:30:36.238810 Total UI for P1: 0, mck2ui 16
4727 16:30:36.241998 best dqsien dly found for B0: ( 0, 13, 10)
4728 16:30:36.245536 Total UI for P1: 0, mck2ui 16
4729 16:30:36.248784 best dqsien dly found for B1: ( 0, 13, 10)
4730 16:30:36.252036 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4731 16:30:36.255134 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4732 16:30:36.255571
4733 16:30:36.258908 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4734 16:30:36.262053 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4735 16:30:36.265317 [Gating] SW calibration Done
4736 16:30:36.265750 ==
4737 16:30:36.268572 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 16:30:36.271796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 16:30:36.272233 ==
4740 16:30:36.275043 RX Vref Scan: 0
4741 16:30:36.275476
4742 16:30:36.278016 RX Vref 0 -> 0, step: 1
4743 16:30:36.278528
4744 16:30:36.281445 RX Delay -230 -> 252, step: 16
4745 16:30:36.284503 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4746 16:30:36.288400 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4747 16:30:36.291176 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4748 16:30:36.297876 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4749 16:30:36.301494 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4750 16:30:36.304606 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4751 16:30:36.307951 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4752 16:30:36.311249 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4753 16:30:36.317813 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4754 16:30:36.321107 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4755 16:30:36.324157 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4756 16:30:36.327864 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4757 16:30:36.334757 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4758 16:30:36.337487 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4759 16:30:36.340674 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4760 16:30:36.343992 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4761 16:30:36.347632 ==
4762 16:30:36.348053 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 16:30:36.354073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 16:30:36.354569 ==
4765 16:30:36.354909 DQS Delay:
4766 16:30:36.357221 DQS0 = 0, DQS1 = 0
4767 16:30:36.357657 DQM Delay:
4768 16:30:36.360847 DQM0 = 43, DQM1 = 39
4769 16:30:36.361463 DQ Delay:
4770 16:30:36.364156 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4771 16:30:36.367402 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4772 16:30:36.370438 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4773 16:30:36.373977 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4774 16:30:36.374644
4775 16:30:36.375008
4776 16:30:36.375330 ==
4777 16:30:36.377118 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 16:30:36.380452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 16:30:36.380910 ==
4780 16:30:36.381246
4781 16:30:36.381556
4782 16:30:36.384134 TX Vref Scan disable
4783 16:30:36.387429 == TX Byte 0 ==
4784 16:30:36.390425 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4785 16:30:36.393565 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4786 16:30:36.397429 == TX Byte 1 ==
4787 16:30:36.400566 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4788 16:30:36.403645 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4789 16:30:36.404070 ==
4790 16:30:36.407127 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 16:30:36.413611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 16:30:36.414037 ==
4793 16:30:36.414411
4794 16:30:36.414726
4795 16:30:36.415082 TX Vref Scan disable
4796 16:30:36.417957 == TX Byte 0 ==
4797 16:30:36.421207 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4798 16:30:36.427372 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4799 16:30:36.427797 == TX Byte 1 ==
4800 16:30:36.430944 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4801 16:30:36.437662 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4802 16:30:36.438093
4803 16:30:36.438466 [DATLAT]
4804 16:30:36.438944 Freq=600, CH1 RK1
4805 16:30:36.439280
4806 16:30:36.440734 DATLAT Default: 0x9
4807 16:30:36.444306 0, 0xFFFF, sum = 0
4808 16:30:36.444750 1, 0xFFFF, sum = 0
4809 16:30:36.447290 2, 0xFFFF, sum = 0
4810 16:30:36.447718 3, 0xFFFF, sum = 0
4811 16:30:36.450753 4, 0xFFFF, sum = 0
4812 16:30:36.451241 5, 0xFFFF, sum = 0
4813 16:30:36.454078 6, 0xFFFF, sum = 0
4814 16:30:36.454557 7, 0xFFFF, sum = 0
4815 16:30:36.457627 8, 0x0, sum = 1
4816 16:30:36.458251 9, 0x0, sum = 2
4817 16:30:36.460420 10, 0x0, sum = 3
4818 16:30:36.461005 11, 0x0, sum = 4
4819 16:30:36.461466 best_step = 9
4820 16:30:36.461904
4821 16:30:36.463502 ==
4822 16:30:36.467091 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 16:30:36.470043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 16:30:36.470580 ==
4825 16:30:36.470924 RX Vref Scan: 0
4826 16:30:36.471244
4827 16:30:36.473299 RX Vref 0 -> 0, step: 1
4828 16:30:36.473735
4829 16:30:36.477012 RX Delay -179 -> 252, step: 8
4830 16:30:36.483498 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4831 16:30:36.486732 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4832 16:30:36.490028 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4833 16:30:36.493102 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4834 16:30:36.500287 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4835 16:30:36.503286 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4836 16:30:36.506417 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4837 16:30:36.509860 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4838 16:30:36.512582 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4839 16:30:36.519595 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4840 16:30:36.523098 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4841 16:30:36.525893 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4842 16:30:36.529211 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4843 16:30:36.535716 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4844 16:30:36.539082 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4845 16:30:36.542252 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4846 16:30:36.542644 ==
4847 16:30:36.545555 Dram Type= 6, Freq= 0, CH_1, rank 1
4848 16:30:36.552341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4849 16:30:36.552782 ==
4850 16:30:36.553129 DQS Delay:
4851 16:30:36.555522 DQS0 = 0, DQS1 = 0
4852 16:30:36.555946 DQM Delay:
4853 16:30:36.556287 DQM0 = 45, DQM1 = 36
4854 16:30:36.558451 DQ Delay:
4855 16:30:36.562331 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4856 16:30:36.565404 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4857 16:30:36.569003 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4858 16:30:36.572567 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4859 16:30:36.573007
4860 16:30:36.573454
4861 16:30:36.578762 [DQSOSCAuto] RK1, (LSB)MR18= 0x3025, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4862 16:30:36.582243 CH1 RK1: MR19=808, MR18=3025
4863 16:30:36.588231 CH1_RK1: MR19=0x808, MR18=0x3025, DQSOSC=400, MR23=63, INC=163, DEC=109
4864 16:30:36.591981 [RxdqsGatingPostProcess] freq 600
4865 16:30:36.595288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4866 16:30:36.598468 Pre-setting of DQS Precalculation
4867 16:30:36.605411 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4868 16:30:36.611796 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4869 16:30:36.618537 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4870 16:30:36.619011
4871 16:30:36.619449
4872 16:30:36.621665 [Calibration Summary] 1200 Mbps
4873 16:30:36.622104 CH 0, Rank 0
4874 16:30:36.624995 SW Impedance : PASS
4875 16:30:36.628458 DUTY Scan : NO K
4876 16:30:36.628917 ZQ Calibration : PASS
4877 16:30:36.631745 Jitter Meter : NO K
4878 16:30:36.634835 CBT Training : PASS
4879 16:30:36.635273 Write leveling : PASS
4880 16:30:36.638036 RX DQS gating : PASS
4881 16:30:36.641773 RX DQ/DQS(RDDQC) : PASS
4882 16:30:36.642243 TX DQ/DQS : PASS
4883 16:30:36.644566 RX DATLAT : PASS
4884 16:30:36.648238 RX DQ/DQS(Engine): PASS
4885 16:30:36.648662 TX OE : NO K
4886 16:30:36.651442 All Pass.
4887 16:30:36.651883
4888 16:30:36.652325 CH 0, Rank 1
4889 16:30:36.654660 SW Impedance : PASS
4890 16:30:36.655103 DUTY Scan : NO K
4891 16:30:36.657885 ZQ Calibration : PASS
4892 16:30:36.661097 Jitter Meter : NO K
4893 16:30:36.661591 CBT Training : PASS
4894 16:30:36.664245 Write leveling : PASS
4895 16:30:36.667843 RX DQS gating : PASS
4896 16:30:36.668266 RX DQ/DQS(RDDQC) : PASS
4897 16:30:36.671041 TX DQ/DQS : PASS
4898 16:30:36.674124 RX DATLAT : PASS
4899 16:30:36.674581 RX DQ/DQS(Engine): PASS
4900 16:30:36.677248 TX OE : NO K
4901 16:30:36.677672 All Pass.
4902 16:30:36.678004
4903 16:30:36.680606 CH 1, Rank 0
4904 16:30:36.681024 SW Impedance : PASS
4905 16:30:36.684324 DUTY Scan : NO K
4906 16:30:36.687289 ZQ Calibration : PASS
4907 16:30:36.687914 Jitter Meter : NO K
4908 16:30:36.690659 CBT Training : PASS
4909 16:30:36.693928 Write leveling : PASS
4910 16:30:36.694394 RX DQS gating : PASS
4911 16:30:36.697099 RX DQ/DQS(RDDQC) : PASS
4912 16:30:36.697513 TX DQ/DQS : PASS
4913 16:30:36.700631 RX DATLAT : PASS
4914 16:30:36.703912 RX DQ/DQS(Engine): PASS
4915 16:30:36.704338 TX OE : NO K
4916 16:30:36.707462 All Pass.
4917 16:30:36.707911
4918 16:30:36.708351 CH 1, Rank 1
4919 16:30:36.710688 SW Impedance : PASS
4920 16:30:36.711103 DUTY Scan : NO K
4921 16:30:36.713911 ZQ Calibration : PASS
4922 16:30:36.717156 Jitter Meter : NO K
4923 16:30:36.717571 CBT Training : PASS
4924 16:30:36.720680 Write leveling : PASS
4925 16:30:36.723815 RX DQS gating : PASS
4926 16:30:36.724233 RX DQ/DQS(RDDQC) : PASS
4927 16:30:36.727441 TX DQ/DQS : PASS
4928 16:30:36.730410 RX DATLAT : PASS
4929 16:30:36.730875 RX DQ/DQS(Engine): PASS
4930 16:30:36.733668 TX OE : NO K
4931 16:30:36.734114 All Pass.
4932 16:30:36.734597
4933 16:30:36.736858 DramC Write-DBI off
4934 16:30:36.739967 PER_BANK_REFRESH: Hybrid Mode
4935 16:30:36.740428 TX_TRACKING: ON
4936 16:30:36.750325 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4937 16:30:36.753310 [FAST_K] Save calibration result to emmc
4938 16:30:36.757036 dramc_set_vcore_voltage set vcore to 662500
4939 16:30:36.760143 Read voltage for 933, 3
4940 16:30:36.760749 Vio18 = 0
4941 16:30:36.761247 Vcore = 662500
4942 16:30:36.763477 Vdram = 0
4943 16:30:36.764054 Vddq = 0
4944 16:30:36.764693 Vmddr = 0
4945 16:30:36.769843 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4946 16:30:36.773494 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4947 16:30:36.776747 MEM_TYPE=3, freq_sel=17
4948 16:30:36.779922 sv_algorithm_assistance_LP4_1600
4949 16:30:36.783098 ============ PULL DRAM RESETB DOWN ============
4950 16:30:36.789480 ========== PULL DRAM RESETB DOWN end =========
4951 16:30:36.793175 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4952 16:30:36.796460 ===================================
4953 16:30:36.799515 LPDDR4 DRAM CONFIGURATION
4954 16:30:36.803268 ===================================
4955 16:30:36.803723 EX_ROW_EN[0] = 0x0
4956 16:30:36.806061 EX_ROW_EN[1] = 0x0
4957 16:30:36.806512 LP4Y_EN = 0x0
4958 16:30:36.809862 WORK_FSP = 0x0
4959 16:30:36.810332 WL = 0x3
4960 16:30:36.812705 RL = 0x3
4961 16:30:36.813191 BL = 0x2
4962 16:30:36.815818 RPST = 0x0
4963 16:30:36.816235 RD_PRE = 0x0
4964 16:30:36.819635 WR_PRE = 0x1
4965 16:30:36.820050 WR_PST = 0x0
4966 16:30:36.822477 DBI_WR = 0x0
4967 16:30:36.825966 DBI_RD = 0x0
4968 16:30:36.826507 OTF = 0x1
4969 16:30:36.829508 ===================================
4970 16:30:36.832578 ===================================
4971 16:30:36.832996 ANA top config
4972 16:30:36.835745 ===================================
4973 16:30:36.839685 DLL_ASYNC_EN = 0
4974 16:30:36.842847 ALL_SLAVE_EN = 1
4975 16:30:36.845980 NEW_RANK_MODE = 1
4976 16:30:36.849255 DLL_IDLE_MODE = 1
4977 16:30:36.849673 LP45_APHY_COMB_EN = 1
4978 16:30:36.853072 TX_ODT_DIS = 1
4979 16:30:36.856330 NEW_8X_MODE = 1
4980 16:30:36.859220 ===================================
4981 16:30:36.862292 ===================================
4982 16:30:36.865559 data_rate = 1866
4983 16:30:36.869331 CKR = 1
4984 16:30:36.869745 DQ_P2S_RATIO = 8
4985 16:30:36.872621 ===================================
4986 16:30:36.875731 CA_P2S_RATIO = 8
4987 16:30:36.879193 DQ_CA_OPEN = 0
4988 16:30:36.882195 DQ_SEMI_OPEN = 0
4989 16:30:36.885357 CA_SEMI_OPEN = 0
4990 16:30:36.888619 CA_FULL_RATE = 0
4991 16:30:36.889110 DQ_CKDIV4_EN = 1
4992 16:30:36.892505 CA_CKDIV4_EN = 1
4993 16:30:36.895417 CA_PREDIV_EN = 0
4994 16:30:36.898678 PH8_DLY = 0
4995 16:30:36.901943 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4996 16:30:36.905635 DQ_AAMCK_DIV = 4
4997 16:30:36.906049 CA_AAMCK_DIV = 4
4998 16:30:36.908777 CA_ADMCK_DIV = 4
4999 16:30:36.911899 DQ_TRACK_CA_EN = 0
5000 16:30:36.915094 CA_PICK = 933
5001 16:30:36.918293 CA_MCKIO = 933
5002 16:30:36.921754 MCKIO_SEMI = 0
5003 16:30:36.925340 PLL_FREQ = 3732
5004 16:30:36.928321 DQ_UI_PI_RATIO = 32
5005 16:30:36.928740 CA_UI_PI_RATIO = 0
5006 16:30:36.931725 ===================================
5007 16:30:36.934863 ===================================
5008 16:30:36.938448 memory_type:LPDDR4
5009 16:30:36.941726 GP_NUM : 10
5010 16:30:36.942355 SRAM_EN : 1
5011 16:30:36.944712 MD32_EN : 0
5012 16:30:36.948157 ===================================
5013 16:30:36.951600 [ANA_INIT] >>>>>>>>>>>>>>
5014 16:30:36.955167 <<<<<< [CONFIGURE PHASE]: ANA_TX
5015 16:30:36.958282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5016 16:30:36.961599 ===================================
5017 16:30:36.962058 data_rate = 1866,PCW = 0X8f00
5018 16:30:36.964619 ===================================
5019 16:30:36.967838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5020 16:30:36.974332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5021 16:30:36.981497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5022 16:30:36.984829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5023 16:30:36.987633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5024 16:30:36.991823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5025 16:30:36.994677 [ANA_INIT] flow start
5026 16:30:36.997825 [ANA_INIT] PLL >>>>>>>>
5027 16:30:36.998306 [ANA_INIT] PLL <<<<<<<<
5028 16:30:37.000859 [ANA_INIT] MIDPI >>>>>>>>
5029 16:30:37.004556 [ANA_INIT] MIDPI <<<<<<<<
5030 16:30:37.004977 [ANA_INIT] DLL >>>>>>>>
5031 16:30:37.007760 [ANA_INIT] flow end
5032 16:30:37.010892 ============ LP4 DIFF to SE enter ============
5033 16:30:37.013941 ============ LP4 DIFF to SE exit ============
5034 16:30:37.017220 [ANA_INIT] <<<<<<<<<<<<<
5035 16:30:37.020464 [Flow] Enable top DCM control >>>>>
5036 16:30:37.024201 [Flow] Enable top DCM control <<<<<
5037 16:30:37.027333 Enable DLL master slave shuffle
5038 16:30:37.033637 ==============================================================
5039 16:30:37.034066 Gating Mode config
5040 16:30:37.040645 ==============================================================
5041 16:30:37.043901 Config description:
5042 16:30:37.050133 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5043 16:30:37.059972 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5044 16:30:37.063244 SELPH_MODE 0: By rank 1: By Phase
5045 16:30:37.069479 ==============================================================
5046 16:30:37.073278 GAT_TRACK_EN = 1
5047 16:30:37.073699 RX_GATING_MODE = 2
5048 16:30:37.076620 RX_GATING_TRACK_MODE = 2
5049 16:30:37.079782 SELPH_MODE = 1
5050 16:30:37.083363 PICG_EARLY_EN = 1
5051 16:30:37.086626 VALID_LAT_VALUE = 1
5052 16:30:37.093193 ==============================================================
5053 16:30:37.096393 Enter into Gating configuration >>>>
5054 16:30:37.099742 Exit from Gating configuration <<<<
5055 16:30:37.102846 Enter into DVFS_PRE_config >>>>>
5056 16:30:37.113357 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5057 16:30:37.116496 Exit from DVFS_PRE_config <<<<<
5058 16:30:37.119706 Enter into PICG configuration >>>>
5059 16:30:37.122861 Exit from PICG configuration <<<<
5060 16:30:37.126153 [RX_INPUT] configuration >>>>>
5061 16:30:37.129891 [RX_INPUT] configuration <<<<<
5062 16:30:37.132941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5063 16:30:37.139524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5064 16:30:37.145847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5065 16:30:37.152281 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5066 16:30:37.156039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5067 16:30:37.162472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5068 16:30:37.169110 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5069 16:30:37.172165 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5070 16:30:37.175715 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5071 16:30:37.178874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5072 16:30:37.182364 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5073 16:30:37.188757 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5074 16:30:37.192164 ===================================
5075 16:30:37.195288 LPDDR4 DRAM CONFIGURATION
5076 16:30:37.198886 ===================================
5077 16:30:37.199309 EX_ROW_EN[0] = 0x0
5078 16:30:37.202336 EX_ROW_EN[1] = 0x0
5079 16:30:37.202791 LP4Y_EN = 0x0
5080 16:30:37.205450 WORK_FSP = 0x0
5081 16:30:37.205869 WL = 0x3
5082 16:30:37.208640 RL = 0x3
5083 16:30:37.209190 BL = 0x2
5084 16:30:37.212178 RPST = 0x0
5085 16:30:37.212637 RD_PRE = 0x0
5086 16:30:37.215078 WR_PRE = 0x1
5087 16:30:37.215517 WR_PST = 0x0
5088 16:30:37.218795 DBI_WR = 0x0
5089 16:30:37.221572 DBI_RD = 0x0
5090 16:30:37.222131 OTF = 0x1
5091 16:30:37.224980 ===================================
5092 16:30:37.228678 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5093 16:30:37.235158 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5094 16:30:37.238251 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5095 16:30:37.241336 ===================================
5096 16:30:37.244597 LPDDR4 DRAM CONFIGURATION
5097 16:30:37.248327 ===================================
5098 16:30:37.248751 EX_ROW_EN[0] = 0x10
5099 16:30:37.251618 EX_ROW_EN[1] = 0x0
5100 16:30:37.252058 LP4Y_EN = 0x0
5101 16:30:37.254679 WORK_FSP = 0x0
5102 16:30:37.255114 WL = 0x3
5103 16:30:37.257799 RL = 0x3
5104 16:30:37.258256 BL = 0x2
5105 16:30:37.261225 RPST = 0x0
5106 16:30:37.265124 RD_PRE = 0x0
5107 16:30:37.265543 WR_PRE = 0x1
5108 16:30:37.268290 WR_PST = 0x0
5109 16:30:37.268720 DBI_WR = 0x0
5110 16:30:37.271445 DBI_RD = 0x0
5111 16:30:37.271914 OTF = 0x1
5112 16:30:37.274682 ===================================
5113 16:30:37.280947 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5114 16:30:37.284712 nWR fixed to 30
5115 16:30:37.288450 [ModeRegInit_LP4] CH0 RK0
5116 16:30:37.288939 [ModeRegInit_LP4] CH0 RK1
5117 16:30:37.291427 [ModeRegInit_LP4] CH1 RK0
5118 16:30:37.294740 [ModeRegInit_LP4] CH1 RK1
5119 16:30:37.295197 match AC timing 9
5120 16:30:37.301487 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5121 16:30:37.304378 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5122 16:30:37.307878 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5123 16:30:37.314724 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5124 16:30:37.317504 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5125 16:30:37.317922 ==
5126 16:30:37.321062 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 16:30:37.324342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 16:30:37.324767 ==
5129 16:30:37.331293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5130 16:30:37.337209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5131 16:30:37.340981 [CA 0] Center 37 (7~68) winsize 62
5132 16:30:37.344061 [CA 1] Center 37 (7~68) winsize 62
5133 16:30:37.347338 [CA 2] Center 34 (4~65) winsize 62
5134 16:30:37.351202 [CA 3] Center 34 (4~65) winsize 62
5135 16:30:37.354276 [CA 4] Center 33 (3~64) winsize 62
5136 16:30:37.357556 [CA 5] Center 33 (3~63) winsize 61
5137 16:30:37.357980
5138 16:30:37.360685 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5139 16:30:37.361110
5140 16:30:37.364069 [CATrainingPosCal] consider 1 rank data
5141 16:30:37.367038 u2DelayCellTimex100 = 270/100 ps
5142 16:30:37.370320 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5143 16:30:37.373624 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5144 16:30:37.377493 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5145 16:30:37.380608 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5146 16:30:37.387365 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5147 16:30:37.390519 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5148 16:30:37.390949
5149 16:30:37.393529 CA PerBit enable=1, Macro0, CA PI delay=33
5150 16:30:37.394101
5151 16:30:37.397105 [CBTSetCACLKResult] CA Dly = 33
5152 16:30:37.397530 CS Dly: 7 (0~38)
5153 16:30:37.397866 ==
5154 16:30:37.400372 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 16:30:37.406684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 16:30:37.407116 ==
5157 16:30:37.410410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5158 16:30:37.416391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5159 16:30:37.419668 [CA 0] Center 37 (7~68) winsize 62
5160 16:30:37.423347 [CA 1] Center 37 (7~68) winsize 62
5161 16:30:37.426647 [CA 2] Center 34 (4~65) winsize 62
5162 16:30:37.429923 [CA 3] Center 34 (4~65) winsize 62
5163 16:30:37.433001 [CA 4] Center 33 (3~64) winsize 62
5164 16:30:37.436157 [CA 5] Center 33 (3~63) winsize 61
5165 16:30:37.436580
5166 16:30:37.439780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5167 16:30:37.440202
5168 16:30:37.443230 [CATrainingPosCal] consider 2 rank data
5169 16:30:37.446259 u2DelayCellTimex100 = 270/100 ps
5170 16:30:37.449353 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5171 16:30:37.455899 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5172 16:30:37.459321 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5173 16:30:37.462319 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5174 16:30:37.465828 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5175 16:30:37.468933 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5176 16:30:37.469381
5177 16:30:37.472555 CA PerBit enable=1, Macro0, CA PI delay=33
5178 16:30:37.472974
5179 16:30:37.475673 [CBTSetCACLKResult] CA Dly = 33
5180 16:30:37.479062 CS Dly: 7 (0~39)
5181 16:30:37.479478
5182 16:30:37.482315 ----->DramcWriteLeveling(PI) begin...
5183 16:30:37.482755 ==
5184 16:30:37.485725 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 16:30:37.488994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 16:30:37.489431 ==
5187 16:30:37.492154 Write leveling (Byte 0): 34 => 34
5188 16:30:37.495935 Write leveling (Byte 1): 28 => 28
5189 16:30:37.498906 DramcWriteLeveling(PI) end<-----
5190 16:30:37.499328
5191 16:30:37.499657 ==
5192 16:30:37.502225 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 16:30:37.505407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 16:30:37.505828 ==
5195 16:30:37.508826 [Gating] SW mode calibration
5196 16:30:37.515326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5197 16:30:37.522122 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5198 16:30:37.524998 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5199 16:30:37.531513 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5200 16:30:37.535065 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 16:30:37.538197 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 16:30:37.544622 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 16:30:37.548327 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5204 16:30:37.551489 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 16:30:37.558068 0 14 28 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
5206 16:30:37.561663 0 15 0 | B1->B0 | 3030 2727 | 1 0 | (1 0) (0 0)
5207 16:30:37.564581 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5208 16:30:37.568133 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 16:30:37.574678 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 16:30:37.577834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 16:30:37.581686 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 16:30:37.587888 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 16:30:37.590668 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5214 16:30:37.593910 1 0 0 | B1->B0 | 2f2f 4242 | 1 0 | (0 0) (0 0)
5215 16:30:37.600810 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5216 16:30:37.603724 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 16:30:37.607127 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 16:30:37.614108 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 16:30:37.617400 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 16:30:37.621198 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 16:30:37.627378 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 16:30:37.630759 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5223 16:30:37.634091 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5224 16:30:37.640707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 16:30:37.643877 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 16:30:37.647703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 16:30:37.654051 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 16:30:37.657170 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 16:30:37.660442 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 16:30:37.667584 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 16:30:37.670610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 16:30:37.673427 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 16:30:37.680157 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 16:30:37.683582 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 16:30:37.687139 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 16:30:37.693450 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5237 16:30:37.696560 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5238 16:30:37.700210 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5239 16:30:37.703425 Total UI for P1: 0, mck2ui 16
5240 16:30:37.706545 best dqsien dly found for B0: ( 1, 2, 26)
5241 16:30:37.713430 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5242 16:30:37.716535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 16:30:37.719693 Total UI for P1: 0, mck2ui 16
5244 16:30:37.723543 best dqsien dly found for B1: ( 1, 3, 2)
5245 16:30:37.726670 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5246 16:30:37.729732 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5247 16:30:37.730224
5248 16:30:37.733377 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5249 16:30:37.736480 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5250 16:30:37.739655 [Gating] SW calibration Done
5251 16:30:37.740087 ==
5252 16:30:37.742815 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 16:30:37.749824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 16:30:37.750403 ==
5255 16:30:37.750841 RX Vref Scan: 0
5256 16:30:37.751252
5257 16:30:37.752736 RX Vref 0 -> 0, step: 1
5258 16:30:37.753170
5259 16:30:37.756180 RX Delay -80 -> 252, step: 8
5260 16:30:37.759299 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5261 16:30:37.763017 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5262 16:30:37.766216 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5263 16:30:37.769377 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5264 16:30:37.776167 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5265 16:30:37.779272 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5266 16:30:37.782331 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5267 16:30:37.785507 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5268 16:30:37.789317 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5269 16:30:37.795359 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5270 16:30:37.799060 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5271 16:30:37.802157 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5272 16:30:37.805424 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5273 16:30:37.808998 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5274 16:30:37.811771 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5275 16:30:37.818631 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5276 16:30:37.819055 ==
5277 16:30:37.822142 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 16:30:37.825288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 16:30:37.825723 ==
5280 16:30:37.826061 DQS Delay:
5281 16:30:37.828463 DQS0 = 0, DQS1 = 0
5282 16:30:37.828885 DQM Delay:
5283 16:30:37.831730 DQM0 = 96, DQM1 = 87
5284 16:30:37.832149 DQ Delay:
5285 16:30:37.834989 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5286 16:30:37.838484 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5287 16:30:37.841575 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5288 16:30:37.844915 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5289 16:30:37.845345
5290 16:30:37.845707
5291 16:30:37.846020 ==
5292 16:30:37.848611 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 16:30:37.854894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 16:30:37.855376 ==
5295 16:30:37.855932
5296 16:30:37.856468
5297 16:30:37.857174 TX Vref Scan disable
5298 16:30:37.858323 == TX Byte 0 ==
5299 16:30:37.861856 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5300 16:30:37.868151 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5301 16:30:37.868720 == TX Byte 1 ==
5302 16:30:37.871376 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5303 16:30:37.877693 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5304 16:30:37.878298 ==
5305 16:30:37.881476 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 16:30:37.884504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 16:30:37.884952 ==
5308 16:30:37.885391
5309 16:30:37.885807
5310 16:30:37.887775 TX Vref Scan disable
5311 16:30:37.890858 == TX Byte 0 ==
5312 16:30:37.894700 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5313 16:30:37.897672 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5314 16:30:37.900984 == TX Byte 1 ==
5315 16:30:37.904191 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5316 16:30:37.907691 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5317 16:30:37.908170
5318 16:30:37.908504 [DATLAT]
5319 16:30:37.911191 Freq=933, CH0 RK0
5320 16:30:37.911636
5321 16:30:37.914266 DATLAT Default: 0xd
5322 16:30:37.914704 0, 0xFFFF, sum = 0
5323 16:30:37.917804 1, 0xFFFF, sum = 0
5324 16:30:37.918288 2, 0xFFFF, sum = 0
5325 16:30:37.920544 3, 0xFFFF, sum = 0
5326 16:30:37.920987 4, 0xFFFF, sum = 0
5327 16:30:37.924099 5, 0xFFFF, sum = 0
5328 16:30:37.924615 6, 0xFFFF, sum = 0
5329 16:30:37.927233 7, 0xFFFF, sum = 0
5330 16:30:37.927672 8, 0xFFFF, sum = 0
5331 16:30:37.930815 9, 0xFFFF, sum = 0
5332 16:30:37.931262 10, 0x0, sum = 1
5333 16:30:37.934051 11, 0x0, sum = 2
5334 16:30:37.934615 12, 0x0, sum = 3
5335 16:30:37.937116 13, 0x0, sum = 4
5336 16:30:37.937560 best_step = 11
5337 16:30:37.938127
5338 16:30:37.938521 ==
5339 16:30:37.940970 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 16:30:37.944170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 16:30:37.947355 ==
5342 16:30:37.947779 RX Vref Scan: 1
5343 16:30:37.948119
5344 16:30:37.950805 RX Vref 0 -> 0, step: 1
5345 16:30:37.951452
5346 16:30:37.954136 RX Delay -61 -> 252, step: 4
5347 16:30:37.954750
5348 16:30:37.957458 Set Vref, RX VrefLevel [Byte0]: 60
5349 16:30:37.957963 [Byte1]: 49
5350 16:30:37.962779
5351 16:30:37.963411 Final RX Vref Byte 0 = 60 to rank0
5352 16:30:37.965554 Final RX Vref Byte 1 = 49 to rank0
5353 16:30:37.969032 Final RX Vref Byte 0 = 60 to rank1
5354 16:30:37.971980 Final RX Vref Byte 1 = 49 to rank1==
5355 16:30:37.975258 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 16:30:37.982461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 16:30:37.982978 ==
5358 16:30:37.983424 DQS Delay:
5359 16:30:37.985447 DQS0 = 0, DQS1 = 0
5360 16:30:37.986011 DQM Delay:
5361 16:30:37.986570 DQM0 = 97, DQM1 = 85
5362 16:30:37.988608 DQ Delay:
5363 16:30:37.992290 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5364 16:30:37.995376 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5365 16:30:37.998476 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5366 16:30:38.002245 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =92
5367 16:30:38.002793
5368 16:30:38.003208
5369 16:30:38.008444 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5370 16:30:38.011779 CH0 RK0: MR19=505, MR18=280F
5371 16:30:38.017888 CH0_RK0: MR19=0x505, MR18=0x280F, DQSOSC=409, MR23=63, INC=64, DEC=43
5372 16:30:38.017975
5373 16:30:38.021015 ----->DramcWriteLeveling(PI) begin...
5374 16:30:38.021093 ==
5375 16:30:38.024229 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 16:30:38.028066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 16:30:38.028172 ==
5378 16:30:38.030869 Write leveling (Byte 0): 33 => 33
5379 16:30:38.034516 Write leveling (Byte 1): 33 => 33
5380 16:30:38.037965 DramcWriteLeveling(PI) end<-----
5381 16:30:38.038068
5382 16:30:38.038175 ==
5383 16:30:38.041351 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 16:30:38.044441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 16:30:38.047490 ==
5386 16:30:38.047592 [Gating] SW mode calibration
5387 16:30:38.057429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5388 16:30:38.061231 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5389 16:30:38.064415 0 14 0 | B1->B0 | 2d2c 3030 | 1 1 | (1 1) (1 1)
5390 16:30:38.070814 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 16:30:38.074427 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 16:30:38.077304 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 16:30:38.084292 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 16:30:38.087313 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 16:30:38.090419 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 16:30:38.097522 0 14 28 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
5397 16:30:38.100827 0 15 0 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
5398 16:30:38.103662 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5399 16:30:38.110671 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 16:30:38.113986 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 16:30:38.117013 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 16:30:38.123474 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 16:30:38.126568 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 16:30:38.130390 0 15 28 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
5405 16:30:38.136582 1 0 0 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (1 1)
5406 16:30:38.140167 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 16:30:38.143302 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 16:30:38.149598 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 16:30:38.153283 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 16:30:38.156265 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 16:30:38.163109 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 16:30:38.165952 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5413 16:30:38.169604 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 16:30:38.176457 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 16:30:38.179574 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 16:30:38.183106 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 16:30:38.189838 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 16:30:38.192885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 16:30:38.195995 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 16:30:38.202598 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 16:30:38.206171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 16:30:38.209483 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 16:30:38.215805 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 16:30:38.219675 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 16:30:38.222722 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 16:30:38.229185 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 16:30:38.232408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5428 16:30:38.235695 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5429 16:30:38.242348 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5430 16:30:38.242432 Total UI for P1: 0, mck2ui 16
5431 16:30:38.249041 best dqsien dly found for B0: ( 1, 2, 26)
5432 16:30:38.252377 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 16:30:38.255480 Total UI for P1: 0, mck2ui 16
5434 16:30:38.258650 best dqsien dly found for B1: ( 1, 2, 30)
5435 16:30:38.261966 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5436 16:30:38.265163 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5437 16:30:38.265246
5438 16:30:38.268879 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5439 16:30:38.271942 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5440 16:30:38.275603 [Gating] SW calibration Done
5441 16:30:38.275710 ==
5442 16:30:38.278598 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 16:30:38.285263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 16:30:38.285346 ==
5445 16:30:38.285410 RX Vref Scan: 0
5446 16:30:38.285471
5447 16:30:38.288868 RX Vref 0 -> 0, step: 1
5448 16:30:38.288972
5449 16:30:38.292014 RX Delay -80 -> 252, step: 8
5450 16:30:38.295124 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5451 16:30:38.298507 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5452 16:30:38.301670 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5453 16:30:38.304872 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5454 16:30:38.312218 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5455 16:30:38.315464 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5456 16:30:38.318644 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5457 16:30:38.321795 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5458 16:30:38.325449 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5459 16:30:38.328635 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5460 16:30:38.335052 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5461 16:30:38.338827 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5462 16:30:38.342111 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5463 16:30:38.345252 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5464 16:30:38.348348 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5465 16:30:38.355122 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5466 16:30:38.355559 ==
5467 16:30:38.358354 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 16:30:38.361998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 16:30:38.362590 ==
5470 16:30:38.363007 DQS Delay:
5471 16:30:38.365079 DQS0 = 0, DQS1 = 0
5472 16:30:38.365503 DQM Delay:
5473 16:30:38.368341 DQM0 = 97, DQM1 = 87
5474 16:30:38.368763 DQ Delay:
5475 16:30:38.371437 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5476 16:30:38.375212 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5477 16:30:38.378274 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5478 16:30:38.381274 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5479 16:30:38.381843
5480 16:30:38.382349
5481 16:30:38.382805 ==
5482 16:30:38.384503 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 16:30:38.388261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 16:30:38.391230 ==
5485 16:30:38.391655
5486 16:30:38.391987
5487 16:30:38.392299 TX Vref Scan disable
5488 16:30:38.394927 == TX Byte 0 ==
5489 16:30:38.398075 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5490 16:30:38.401060 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5491 16:30:38.404789 == TX Byte 1 ==
5492 16:30:38.407653 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5493 16:30:38.411424 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5494 16:30:38.414517 ==
5495 16:30:38.417591 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 16:30:38.420801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 16:30:38.421220 ==
5498 16:30:38.421546
5499 16:30:38.421850
5500 16:30:38.424538 TX Vref Scan disable
5501 16:30:38.424954 == TX Byte 0 ==
5502 16:30:38.430908 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5503 16:30:38.433978 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5504 16:30:38.434439 == TX Byte 1 ==
5505 16:30:38.441231 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5506 16:30:38.444648 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5507 16:30:38.445065
5508 16:30:38.445389 [DATLAT]
5509 16:30:38.447249 Freq=933, CH0 RK1
5510 16:30:38.447662
5511 16:30:38.447992 DATLAT Default: 0xb
5512 16:30:38.451156 0, 0xFFFF, sum = 0
5513 16:30:38.451578 1, 0xFFFF, sum = 0
5514 16:30:38.453834 2, 0xFFFF, sum = 0
5515 16:30:38.453916 3, 0xFFFF, sum = 0
5516 16:30:38.456942 4, 0xFFFF, sum = 0
5517 16:30:38.460130 5, 0xFFFF, sum = 0
5518 16:30:38.460212 6, 0xFFFF, sum = 0
5519 16:30:38.463996 7, 0xFFFF, sum = 0
5520 16:30:38.464092 8, 0xFFFF, sum = 0
5521 16:30:38.467023 9, 0xFFFF, sum = 0
5522 16:30:38.467144 10, 0x0, sum = 1
5523 16:30:38.470037 11, 0x0, sum = 2
5524 16:30:38.470146 12, 0x0, sum = 3
5525 16:30:38.470281 13, 0x0, sum = 4
5526 16:30:38.473975 best_step = 11
5527 16:30:38.474061
5528 16:30:38.474128 ==
5529 16:30:38.477556 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 16:30:38.480196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 16:30:38.480368 ==
5532 16:30:38.483216 RX Vref Scan: 0
5533 16:30:38.483371
5534 16:30:38.486954 RX Vref 0 -> 0, step: 1
5535 16:30:38.487131
5536 16:30:38.487213 RX Delay -61 -> 252, step: 4
5537 16:30:38.494400 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5538 16:30:38.497889 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5539 16:30:38.500915 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5540 16:30:38.504121 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5541 16:30:38.507222 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5542 16:30:38.514213 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5543 16:30:38.517281 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5544 16:30:38.520914 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5545 16:30:38.523685 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5546 16:30:38.526972 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5547 16:30:38.533936 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5548 16:30:38.537271 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5549 16:30:38.540231 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5550 16:30:38.543405 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5551 16:30:38.547027 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5552 16:30:38.553601 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5553 16:30:38.553692 ==
5554 16:30:38.556659 Dram Type= 6, Freq= 0, CH_0, rank 1
5555 16:30:38.559892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 16:30:38.559975 ==
5557 16:30:38.560041 DQS Delay:
5558 16:30:38.562930 DQS0 = 0, DQS1 = 0
5559 16:30:38.563012 DQM Delay:
5560 16:30:38.566670 DQM0 = 95, DQM1 = 86
5561 16:30:38.566778 DQ Delay:
5562 16:30:38.569848 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5563 16:30:38.572663 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5564 16:30:38.576442 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5565 16:30:38.579531 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5566 16:30:38.579613
5567 16:30:38.579679
5568 16:30:38.589304 [DQSOSCAuto] RK1, (LSB)MR18= 0x24f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5569 16:30:38.592518 CH0 RK1: MR19=504, MR18=24F5
5570 16:30:38.595834 CH0_RK1: MR19=0x504, MR18=0x24F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5571 16:30:38.599489 [RxdqsGatingPostProcess] freq 933
5572 16:30:38.606061 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5573 16:30:38.609111 best DQS0 dly(2T, 0.5T) = (0, 10)
5574 16:30:38.612391 best DQS1 dly(2T, 0.5T) = (0, 11)
5575 16:30:38.615819 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5576 16:30:38.619091 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5577 16:30:38.622333 best DQS0 dly(2T, 0.5T) = (0, 10)
5578 16:30:38.625441 best DQS1 dly(2T, 0.5T) = (0, 10)
5579 16:30:38.629021 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5580 16:30:38.632470 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5581 16:30:38.635529 Pre-setting of DQS Precalculation
5582 16:30:38.639112 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5583 16:30:38.639417 ==
5584 16:30:38.642625 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 16:30:38.645752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 16:30:38.646303 ==
5587 16:30:38.652121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 16:30:38.658841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5589 16:30:38.662146 [CA 0] Center 36 (6~67) winsize 62
5590 16:30:38.665248 [CA 1] Center 36 (6~67) winsize 62
5591 16:30:38.668412 [CA 2] Center 34 (4~64) winsize 61
5592 16:30:38.672110 [CA 3] Center 33 (3~64) winsize 62
5593 16:30:38.675076 [CA 4] Center 34 (4~64) winsize 61
5594 16:30:38.678655 [CA 5] Center 33 (3~64) winsize 62
5595 16:30:38.679271
5596 16:30:38.681576 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5597 16:30:38.682002
5598 16:30:38.684903 [CATrainingPosCal] consider 1 rank data
5599 16:30:38.688258 u2DelayCellTimex100 = 270/100 ps
5600 16:30:38.692144 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5601 16:30:38.695337 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5602 16:30:38.698338 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5603 16:30:38.704714 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5604 16:30:38.708237 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5605 16:30:38.711345 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5606 16:30:38.711974
5607 16:30:38.714436 CA PerBit enable=1, Macro0, CA PI delay=33
5608 16:30:38.715073
5609 16:30:38.717683 [CBTSetCACLKResult] CA Dly = 33
5610 16:30:38.718265 CS Dly: 5 (0~36)
5611 16:30:38.718611 ==
5612 16:30:38.721028 Dram Type= 6, Freq= 0, CH_1, rank 1
5613 16:30:38.728102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 16:30:38.728400 ==
5615 16:30:38.731034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5616 16:30:38.737302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5617 16:30:38.741298 [CA 0] Center 36 (6~67) winsize 62
5618 16:30:38.744201 [CA 1] Center 37 (7~67) winsize 61
5619 16:30:38.747218 [CA 2] Center 34 (4~65) winsize 62
5620 16:30:38.751131 [CA 3] Center 33 (3~64) winsize 62
5621 16:30:38.754322 [CA 4] Center 34 (3~65) winsize 63
5622 16:30:38.757234 [CA 5] Center 33 (3~64) winsize 62
5623 16:30:38.757366
5624 16:30:38.760882 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5625 16:30:38.760974
5626 16:30:38.763714 [CATrainingPosCal] consider 2 rank data
5627 16:30:38.767117 u2DelayCellTimex100 = 270/100 ps
5628 16:30:38.770376 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5629 16:30:38.777316 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5630 16:30:38.780228 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5631 16:30:38.784099 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5632 16:30:38.787080 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5633 16:30:38.790705 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5634 16:30:38.791175
5635 16:30:38.793919 CA PerBit enable=1, Macro0, CA PI delay=33
5636 16:30:38.794382
5637 16:30:38.797149 [CBTSetCACLKResult] CA Dly = 33
5638 16:30:38.800455 CS Dly: 6 (0~39)
5639 16:30:38.800905
5640 16:30:38.803977 ----->DramcWriteLeveling(PI) begin...
5641 16:30:38.804401 ==
5642 16:30:38.807089 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 16:30:38.810273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 16:30:38.810690 ==
5645 16:30:38.813176 Write leveling (Byte 0): 25 => 25
5646 16:30:38.816891 Write leveling (Byte 1): 27 => 27
5647 16:30:38.820156 DramcWriteLeveling(PI) end<-----
5648 16:30:38.820571
5649 16:30:38.820900 ==
5650 16:30:38.823210 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 16:30:38.826638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 16:30:38.827053 ==
5653 16:30:38.829852 [Gating] SW mode calibration
5654 16:30:38.836463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5655 16:30:38.843154 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5656 16:30:38.846903 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5657 16:30:38.850032 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 16:30:38.856631 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 16:30:38.860029 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 16:30:38.863428 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 16:30:38.869896 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5662 16:30:38.872943 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 1)
5663 16:30:38.876283 0 14 28 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
5664 16:30:38.883280 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5665 16:30:38.886469 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 16:30:38.889445 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 16:30:38.895875 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 16:30:38.899462 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 16:30:38.903039 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 16:30:38.909302 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5671 16:30:38.912482 0 15 28 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (0 0)
5672 16:30:38.916010 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 16:30:38.922489 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 16:30:38.925773 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 16:30:38.928745 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 16:30:38.935801 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 16:30:38.939035 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 16:30:38.942276 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5679 16:30:38.948527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5680 16:30:38.951785 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 16:30:38.955663 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 16:30:38.962083 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 16:30:38.965279 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 16:30:38.968520 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 16:30:38.974896 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 16:30:38.978664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 16:30:38.981740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 16:30:38.988423 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 16:30:38.991470 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 16:30:38.994766 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 16:30:39.001566 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 16:30:39.004890 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 16:30:39.008007 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5694 16:30:39.014807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5695 16:30:39.017801 Total UI for P1: 0, mck2ui 16
5696 16:30:39.021162 best dqsien dly found for B0: ( 1, 2, 20)
5697 16:30:39.024779 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 16:30:39.028001 Total UI for P1: 0, mck2ui 16
5699 16:30:39.031149 best dqsien dly found for B1: ( 1, 2, 24)
5700 16:30:39.034149 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5701 16:30:39.037466 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5702 16:30:39.037904
5703 16:30:39.041181 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5704 16:30:39.047583 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5705 16:30:39.048094 [Gating] SW calibration Done
5706 16:30:39.048464 ==
5707 16:30:39.050880 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 16:30:39.057512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 16:30:39.057838 ==
5710 16:30:39.058211 RX Vref Scan: 0
5711 16:30:39.058465
5712 16:30:39.060693 RX Vref 0 -> 0, step: 1
5713 16:30:39.060927
5714 16:30:39.064337 RX Delay -80 -> 252, step: 8
5715 16:30:39.067233 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5716 16:30:39.070351 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5717 16:30:39.073939 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5718 16:30:39.077089 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5719 16:30:39.083352 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5720 16:30:39.087060 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5721 16:30:39.090148 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5722 16:30:39.093924 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5723 16:30:39.096742 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5724 16:30:39.103669 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5725 16:30:39.106944 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5726 16:30:39.110027 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5727 16:30:39.113245 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5728 16:30:39.116522 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5729 16:30:39.123681 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5730 16:30:39.126676 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5731 16:30:39.126787 ==
5732 16:30:39.129754 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 16:30:39.132854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 16:30:39.132936 ==
5735 16:30:39.136651 DQS Delay:
5736 16:30:39.136727 DQS0 = 0, DQS1 = 0
5737 16:30:39.136790 DQM Delay:
5738 16:30:39.139473 DQM0 = 102, DQM1 = 90
5739 16:30:39.139556 DQ Delay:
5740 16:30:39.142844 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5741 16:30:39.146126 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5742 16:30:39.149749 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5743 16:30:39.152940 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5744 16:30:39.153036
5745 16:30:39.153124
5746 16:30:39.153202 ==
5747 16:30:39.156258 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 16:30:39.162480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 16:30:39.162569 ==
5750 16:30:39.162654
5751 16:30:39.162733
5752 16:30:39.162809 TX Vref Scan disable
5753 16:30:39.166293 == TX Byte 0 ==
5754 16:30:39.169903 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5755 16:30:39.176367 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5756 16:30:39.176457 == TX Byte 1 ==
5757 16:30:39.179533 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5758 16:30:39.186335 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5759 16:30:39.186427 ==
5760 16:30:39.189461 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 16:30:39.192628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 16:30:39.192712 ==
5763 16:30:39.192777
5764 16:30:39.192837
5765 16:30:39.196366 TX Vref Scan disable
5766 16:30:39.196449 == TX Byte 0 ==
5767 16:30:39.202754 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5768 16:30:39.206391 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5769 16:30:39.206477 == TX Byte 1 ==
5770 16:30:39.212805 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5771 16:30:39.216042 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5772 16:30:39.216129
5773 16:30:39.216214 [DATLAT]
5774 16:30:39.219138 Freq=933, CH1 RK0
5775 16:30:39.219223
5776 16:30:39.219308 DATLAT Default: 0xd
5777 16:30:39.222368 0, 0xFFFF, sum = 0
5778 16:30:39.226120 1, 0xFFFF, sum = 0
5779 16:30:39.226240 2, 0xFFFF, sum = 0
5780 16:30:39.229345 3, 0xFFFF, sum = 0
5781 16:30:39.229436 4, 0xFFFF, sum = 0
5782 16:30:39.232430 5, 0xFFFF, sum = 0
5783 16:30:39.232515 6, 0xFFFF, sum = 0
5784 16:30:39.235631 7, 0xFFFF, sum = 0
5785 16:30:39.235728 8, 0xFFFF, sum = 0
5786 16:30:39.238873 9, 0xFFFF, sum = 0
5787 16:30:39.238970 10, 0x0, sum = 1
5788 16:30:39.242661 11, 0x0, sum = 2
5789 16:30:39.242796 12, 0x0, sum = 3
5790 16:30:39.245775 13, 0x0, sum = 4
5791 16:30:39.245859 best_step = 11
5792 16:30:39.245924
5793 16:30:39.245992 ==
5794 16:30:39.248704 Dram Type= 6, Freq= 0, CH_1, rank 0
5795 16:30:39.252109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 16:30:39.252187 ==
5797 16:30:39.255514 RX Vref Scan: 1
5798 16:30:39.255602
5799 16:30:39.258908 RX Vref 0 -> 0, step: 1
5800 16:30:39.258986
5801 16:30:39.259049 RX Delay -61 -> 252, step: 4
5802 16:30:39.259138
5803 16:30:39.261962 Set Vref, RX VrefLevel [Byte0]: 52
5804 16:30:39.265302 [Byte1]: 57
5805 16:30:39.270396
5806 16:30:39.270475 Final RX Vref Byte 0 = 52 to rank0
5807 16:30:39.273411 Final RX Vref Byte 1 = 57 to rank0
5808 16:30:39.277130 Final RX Vref Byte 0 = 52 to rank1
5809 16:30:39.280252 Final RX Vref Byte 1 = 57 to rank1==
5810 16:30:39.283628 Dram Type= 6, Freq= 0, CH_1, rank 0
5811 16:30:39.289936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 16:30:39.290047 ==
5813 16:30:39.290142 DQS Delay:
5814 16:30:39.292919 DQS0 = 0, DQS1 = 0
5815 16:30:39.292992 DQM Delay:
5816 16:30:39.293061 DQM0 = 100, DQM1 = 94
5817 16:30:39.296664 DQ Delay:
5818 16:30:39.299902 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5819 16:30:39.302933 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5820 16:30:39.306201 DQ8 =84, DQ9 =86, DQ10 =92, DQ11 =86
5821 16:30:39.309429 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5822 16:30:39.309504
5823 16:30:39.309566
5824 16:30:39.319439 [DQSOSCAuto] RK0, (LSB)MR18= 0x1808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5825 16:30:39.319546 CH1 RK0: MR19=505, MR18=1808
5826 16:30:39.325832 CH1_RK0: MR19=0x505, MR18=0x1808, DQSOSC=414, MR23=63, INC=63, DEC=42
5827 16:30:39.325912
5828 16:30:39.329100 ----->DramcWriteLeveling(PI) begin...
5829 16:30:39.329193 ==
5830 16:30:39.332448 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 16:30:39.339035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 16:30:39.339154 ==
5833 16:30:39.342185 Write leveling (Byte 0): 26 => 26
5834 16:30:39.345450 Write leveling (Byte 1): 31 => 31
5835 16:30:39.345531 DramcWriteLeveling(PI) end<-----
5836 16:30:39.345595
5837 16:30:39.348709 ==
5838 16:30:39.351836 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 16:30:39.355582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 16:30:39.355674 ==
5841 16:30:39.358473 [Gating] SW mode calibration
5842 16:30:39.365271 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5843 16:30:39.368571 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5844 16:30:39.375409 0 14 0 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5845 16:30:39.378446 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 16:30:39.384722 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 16:30:39.387872 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 16:30:39.391074 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 16:30:39.398082 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 16:30:39.401036 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 16:30:39.404559 0 14 28 | B1->B0 | 2d2d 2f2f | 1 1 | (1 0) (1 1)
5852 16:30:39.411337 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5853 16:30:39.414559 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 16:30:39.417869 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 16:30:39.424214 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 16:30:39.428195 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 16:30:39.431335 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 16:30:39.438028 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5859 16:30:39.441219 0 15 28 | B1->B0 | 3e3e 2c2c | 0 1 | (0 0) (0 0)
5860 16:30:39.444269 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 16:30:39.450779 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 16:30:39.453779 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 16:30:39.457737 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 16:30:39.461129 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 16:30:39.467633 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 16:30:39.470760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 16:30:39.474276 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5868 16:30:39.480761 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 16:30:39.484166 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 16:30:39.487575 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 16:30:39.493987 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 16:30:39.497829 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 16:30:39.500964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 16:30:39.507287 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 16:30:39.510546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 16:30:39.514123 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 16:30:39.520733 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 16:30:39.524241 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 16:30:39.527347 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 16:30:39.533970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 16:30:39.537096 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 16:30:39.540183 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 16:30:39.547216 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5884 16:30:39.550152 Total UI for P1: 0, mck2ui 16
5885 16:30:39.553382 best dqsien dly found for B1: ( 1, 2, 26)
5886 16:30:39.556485 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 16:30:39.559992 Total UI for P1: 0, mck2ui 16
5888 16:30:39.563121 best dqsien dly found for B0: ( 1, 2, 28)
5889 16:30:39.566963 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5890 16:30:39.569819 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5891 16:30:39.570325
5892 16:30:39.573119 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5893 16:30:39.579669 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5894 16:30:39.580104 [Gating] SW calibration Done
5895 16:30:39.580460 ==
5896 16:30:39.583537 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 16:30:39.589485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 16:30:39.589907 ==
5899 16:30:39.590275 RX Vref Scan: 0
5900 16:30:39.590589
5901 16:30:39.592987 RX Vref 0 -> 0, step: 1
5902 16:30:39.593404
5903 16:30:39.596534 RX Delay -80 -> 252, step: 8
5904 16:30:39.599710 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5905 16:30:39.602698 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5906 16:30:39.606397 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5907 16:30:39.609677 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5908 16:30:39.616289 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5909 16:30:39.619404 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5910 16:30:39.622463 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5911 16:30:39.625706 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5912 16:30:39.629430 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5913 16:30:39.635743 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5914 16:30:39.639091 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5915 16:30:39.642297 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5916 16:30:39.645444 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5917 16:30:39.648684 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5918 16:30:39.655448 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5919 16:30:39.658740 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5920 16:30:39.659212 ==
5921 16:30:39.662597 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 16:30:39.665550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 16:30:39.665999 ==
5924 16:30:39.666397 DQS Delay:
5925 16:30:39.668675 DQS0 = 0, DQS1 = 0
5926 16:30:39.669098 DQM Delay:
5927 16:30:39.671906 DQM0 = 99, DQM1 = 91
5928 16:30:39.672292 DQ Delay:
5929 16:30:39.675596 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5930 16:30:39.678802 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5931 16:30:39.682102 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5932 16:30:39.685187 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5933 16:30:39.685641
5934 16:30:39.685972
5935 16:30:39.686347 ==
5936 16:30:39.688446 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 16:30:39.695405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 16:30:39.695822 ==
5939 16:30:39.696151
5940 16:30:39.696529
5941 16:30:39.696827 TX Vref Scan disable
5942 16:30:39.698739 == TX Byte 0 ==
5943 16:30:39.701889 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5944 16:30:39.709041 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5945 16:30:39.709461 == TX Byte 1 ==
5946 16:30:39.712267 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5947 16:30:39.718647 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5948 16:30:39.719072 ==
5949 16:30:39.722226 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 16:30:39.725349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 16:30:39.725770 ==
5952 16:30:39.726096
5953 16:30:39.726582
5954 16:30:39.728409 TX Vref Scan disable
5955 16:30:39.728826 == TX Byte 0 ==
5956 16:30:39.735005 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5957 16:30:39.738241 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5958 16:30:39.741292 == TX Byte 1 ==
5959 16:30:39.745211 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5960 16:30:39.748507 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5961 16:30:39.748953
5962 16:30:39.749299 [DATLAT]
5963 16:30:39.751733 Freq=933, CH1 RK1
5964 16:30:39.752151
5965 16:30:39.754767 DATLAT Default: 0xb
5966 16:30:39.755224 0, 0xFFFF, sum = 0
5967 16:30:39.757889 1, 0xFFFF, sum = 0
5968 16:30:39.758558 2, 0xFFFF, sum = 0
5969 16:30:39.761558 3, 0xFFFF, sum = 0
5970 16:30:39.762028 4, 0xFFFF, sum = 0
5971 16:30:39.764751 5, 0xFFFF, sum = 0
5972 16:30:39.765179 6, 0xFFFF, sum = 0
5973 16:30:39.768385 7, 0xFFFF, sum = 0
5974 16:30:39.768911 8, 0xFFFF, sum = 0
5975 16:30:39.771503 9, 0xFFFF, sum = 0
5976 16:30:39.771931 10, 0x0, sum = 1
5977 16:30:39.774678 11, 0x0, sum = 2
5978 16:30:39.775106 12, 0x0, sum = 3
5979 16:30:39.777754 13, 0x0, sum = 4
5980 16:30:39.778195 best_step = 11
5981 16:30:39.778535
5982 16:30:39.778846 ==
5983 16:30:39.781534 Dram Type= 6, Freq= 0, CH_1, rank 1
5984 16:30:39.784744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5985 16:30:39.785168 ==
5986 16:30:39.788056 RX Vref Scan: 0
5987 16:30:39.788480
5988 16:30:39.791266 RX Vref 0 -> 0, step: 1
5989 16:30:39.791567
5990 16:30:39.791803 RX Delay -61 -> 252, step: 4
5991 16:30:39.798801 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5992 16:30:39.801998 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
5993 16:30:39.805749 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5994 16:30:39.808952 iDelay=207, Bit 3, Center 100 (15 ~ 186) 172
5995 16:30:39.812147 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5996 16:30:39.818967 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
5997 16:30:39.822489 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5998 16:30:39.825203 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5999 16:30:39.828740 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6000 16:30:39.832051 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6001 16:30:39.835164 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6002 16:30:39.842141 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6003 16:30:39.845301 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6004 16:30:39.848477 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6005 16:30:39.851773 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6006 16:30:39.858787 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6007 16:30:39.859264 ==
6008 16:30:39.861786 Dram Type= 6, Freq= 0, CH_1, rank 1
6009 16:30:39.865500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6010 16:30:39.866076 ==
6011 16:30:39.866601 DQS Delay:
6012 16:30:39.868660 DQS0 = 0, DQS1 = 0
6013 16:30:39.869081 DQM Delay:
6014 16:30:39.871751 DQM0 = 101, DQM1 = 93
6015 16:30:39.872176 DQ Delay:
6016 16:30:39.875027 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =100
6017 16:30:39.878303 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
6018 16:30:39.881818 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
6019 16:30:39.884930 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
6020 16:30:39.885354
6021 16:30:39.885688
6022 16:30:39.895163 [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6023 16:30:39.895653 CH1 RK1: MR19=505, MR18=600
6024 16:30:39.901479 CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40
6025 16:30:39.904876 [RxdqsGatingPostProcess] freq 933
6026 16:30:39.911303 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6027 16:30:39.914993 best DQS0 dly(2T, 0.5T) = (0, 10)
6028 16:30:39.918311 best DQS1 dly(2T, 0.5T) = (0, 10)
6029 16:30:39.921349 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6030 16:30:39.924822 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6031 16:30:39.927885 best DQS0 dly(2T, 0.5T) = (0, 10)
6032 16:30:39.928356 best DQS1 dly(2T, 0.5T) = (0, 10)
6033 16:30:39.931290 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6034 16:30:39.934521 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6035 16:30:39.938267 Pre-setting of DQS Precalculation
6036 16:30:39.944721 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6037 16:30:39.950928 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6038 16:30:39.957889 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6039 16:30:39.958491
6040 16:30:39.958965
6041 16:30:39.960884 [Calibration Summary] 1866 Mbps
6042 16:30:39.964383 CH 0, Rank 0
6043 16:30:39.964808 SW Impedance : PASS
6044 16:30:39.967391 DUTY Scan : NO K
6045 16:30:39.970679 ZQ Calibration : PASS
6046 16:30:39.971131 Jitter Meter : NO K
6047 16:30:39.974221 CBT Training : PASS
6048 16:30:39.977500 Write leveling : PASS
6049 16:30:39.977924 RX DQS gating : PASS
6050 16:30:39.980560 RX DQ/DQS(RDDQC) : PASS
6051 16:30:39.980985 TX DQ/DQS : PASS
6052 16:30:39.984317 RX DATLAT : PASS
6053 16:30:39.987250 RX DQ/DQS(Engine): PASS
6054 16:30:39.987694 TX OE : NO K
6055 16:30:39.990479 All Pass.
6056 16:30:39.990899
6057 16:30:39.991281 CH 0, Rank 1
6058 16:30:39.993644 SW Impedance : PASS
6059 16:30:39.994084 DUTY Scan : NO K
6060 16:30:39.997529 ZQ Calibration : PASS
6061 16:30:40.000950 Jitter Meter : NO K
6062 16:30:40.001375 CBT Training : PASS
6063 16:30:40.003899 Write leveling : PASS
6064 16:30:40.007152 RX DQS gating : PASS
6065 16:30:40.007578 RX DQ/DQS(RDDQC) : PASS
6066 16:30:40.010442 TX DQ/DQS : PASS
6067 16:30:40.013663 RX DATLAT : PASS
6068 16:30:40.014302 RX DQ/DQS(Engine): PASS
6069 16:30:40.017312 TX OE : NO K
6070 16:30:40.017986 All Pass.
6071 16:30:40.018630
6072 16:30:40.020621 CH 1, Rank 0
6073 16:30:40.021042 SW Impedance : PASS
6074 16:30:40.023909 DUTY Scan : NO K
6075 16:30:40.027104 ZQ Calibration : PASS
6076 16:30:40.027549 Jitter Meter : NO K
6077 16:30:40.030266 CBT Training : PASS
6078 16:30:40.033397 Write leveling : PASS
6079 16:30:40.033984 RX DQS gating : PASS
6080 16:30:40.037073 RX DQ/DQS(RDDQC) : PASS
6081 16:30:40.040320 TX DQ/DQS : PASS
6082 16:30:40.040745 RX DATLAT : PASS
6083 16:30:40.043753 RX DQ/DQS(Engine): PASS
6084 16:30:40.046747 TX OE : NO K
6085 16:30:40.047172 All Pass.
6086 16:30:40.047625
6087 16:30:40.048003 CH 1, Rank 1
6088 16:30:40.050022 SW Impedance : PASS
6089 16:30:40.053727 DUTY Scan : NO K
6090 16:30:40.054152 ZQ Calibration : PASS
6091 16:30:40.056673 Jitter Meter : NO K
6092 16:30:40.057095 CBT Training : PASS
6093 16:30:40.060148 Write leveling : PASS
6094 16:30:40.063113 RX DQS gating : PASS
6095 16:30:40.063684 RX DQ/DQS(RDDQC) : PASS
6096 16:30:40.066606 TX DQ/DQS : PASS
6097 16:30:40.069712 RX DATLAT : PASS
6098 16:30:40.070268 RX DQ/DQS(Engine): PASS
6099 16:30:40.073500 TX OE : NO K
6100 16:30:40.074077 All Pass.
6101 16:30:40.074518
6102 16:30:40.076498 DramC Write-DBI off
6103 16:30:40.079750 PER_BANK_REFRESH: Hybrid Mode
6104 16:30:40.080201 TX_TRACKING: ON
6105 16:30:40.089926 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6106 16:30:40.092662 [FAST_K] Save calibration result to emmc
6107 16:30:40.096354 dramc_set_vcore_voltage set vcore to 650000
6108 16:30:40.099552 Read voltage for 400, 6
6109 16:30:40.100018 Vio18 = 0
6110 16:30:40.100349 Vcore = 650000
6111 16:30:40.102668 Vdram = 0
6112 16:30:40.103349 Vddq = 0
6113 16:30:40.103962 Vmddr = 0
6114 16:30:40.109714 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6115 16:30:40.115837 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6116 16:30:40.116476 MEM_TYPE=3, freq_sel=20
6117 16:30:40.119421 sv_algorithm_assistance_LP4_800
6118 16:30:40.123121 ============ PULL DRAM RESETB DOWN ============
6119 16:30:40.129340 ========== PULL DRAM RESETB DOWN end =========
6120 16:30:40.132564 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6121 16:30:40.136543 ===================================
6122 16:30:40.139318 LPDDR4 DRAM CONFIGURATION
6123 16:30:40.142252 ===================================
6124 16:30:40.142858 EX_ROW_EN[0] = 0x0
6125 16:30:40.145465 EX_ROW_EN[1] = 0x0
6126 16:30:40.146047 LP4Y_EN = 0x0
6127 16:30:40.149434 WORK_FSP = 0x0
6128 16:30:40.149857 WL = 0x2
6129 16:30:40.152683 RL = 0x2
6130 16:30:40.153271 BL = 0x2
6131 16:30:40.155318 RPST = 0x0
6132 16:30:40.159244 RD_PRE = 0x0
6133 16:30:40.159671 WR_PRE = 0x1
6134 16:30:40.162096 WR_PST = 0x0
6135 16:30:40.162568 DBI_WR = 0x0
6136 16:30:40.165693 DBI_RD = 0x0
6137 16:30:40.166138 OTF = 0x1
6138 16:30:40.168781 ===================================
6139 16:30:40.172381 ===================================
6140 16:30:40.175308 ANA top config
6141 16:30:40.179080 ===================================
6142 16:30:40.179524 DLL_ASYNC_EN = 0
6143 16:30:40.182084 ALL_SLAVE_EN = 1
6144 16:30:40.185311 NEW_RANK_MODE = 1
6145 16:30:40.189112 DLL_IDLE_MODE = 1
6146 16:30:40.189538 LP45_APHY_COMB_EN = 1
6147 16:30:40.192291 TX_ODT_DIS = 1
6148 16:30:40.195223 NEW_8X_MODE = 1
6149 16:30:40.198578 ===================================
6150 16:30:40.202102 ===================================
6151 16:30:40.205442 data_rate = 800
6152 16:30:40.208378 CKR = 1
6153 16:30:40.212098 DQ_P2S_RATIO = 4
6154 16:30:40.215093 ===================================
6155 16:30:40.215526 CA_P2S_RATIO = 4
6156 16:30:40.218219 DQ_CA_OPEN = 0
6157 16:30:40.221557 DQ_SEMI_OPEN = 1
6158 16:30:40.225564 CA_SEMI_OPEN = 1
6159 16:30:40.228830 CA_FULL_RATE = 0
6160 16:30:40.231808 DQ_CKDIV4_EN = 0
6161 16:30:40.232425 CA_CKDIV4_EN = 1
6162 16:30:40.235071 CA_PREDIV_EN = 0
6163 16:30:40.238407 PH8_DLY = 0
6164 16:30:40.241734 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6165 16:30:40.244638 DQ_AAMCK_DIV = 0
6166 16:30:40.247783 CA_AAMCK_DIV = 0
6167 16:30:40.248341 CA_ADMCK_DIV = 4
6168 16:30:40.251698 DQ_TRACK_CA_EN = 0
6169 16:30:40.255184 CA_PICK = 800
6170 16:30:40.258233 CA_MCKIO = 400
6171 16:30:40.261548 MCKIO_SEMI = 400
6172 16:30:40.264672 PLL_FREQ = 3016
6173 16:30:40.267840 DQ_UI_PI_RATIO = 32
6174 16:30:40.270780 CA_UI_PI_RATIO = 32
6175 16:30:40.274632 ===================================
6176 16:30:40.277551 ===================================
6177 16:30:40.278326 memory_type:LPDDR4
6178 16:30:40.280780 GP_NUM : 10
6179 16:30:40.284131 SRAM_EN : 1
6180 16:30:40.284708 MD32_EN : 0
6181 16:30:40.287753 ===================================
6182 16:30:40.291016 [ANA_INIT] >>>>>>>>>>>>>>
6183 16:30:40.294101 <<<<<< [CONFIGURE PHASE]: ANA_TX
6184 16:30:40.297363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6185 16:30:40.300709 ===================================
6186 16:30:40.303905 data_rate = 800,PCW = 0X7400
6187 16:30:40.306997 ===================================
6188 16:30:40.310890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6189 16:30:40.313695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6190 16:30:40.327042 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6191 16:30:40.330290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6192 16:30:40.333417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6193 16:30:40.336962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6194 16:30:40.340487 [ANA_INIT] flow start
6195 16:30:40.343858 [ANA_INIT] PLL >>>>>>>>
6196 16:30:40.344275 [ANA_INIT] PLL <<<<<<<<
6197 16:30:40.346905 [ANA_INIT] MIDPI >>>>>>>>
6198 16:30:40.350004 [ANA_INIT] MIDPI <<<<<<<<
6199 16:30:40.350464 [ANA_INIT] DLL >>>>>>>>
6200 16:30:40.353295 [ANA_INIT] flow end
6201 16:30:40.356923 ============ LP4 DIFF to SE enter ============
6202 16:30:40.363322 ============ LP4 DIFF to SE exit ============
6203 16:30:40.363751 [ANA_INIT] <<<<<<<<<<<<<
6204 16:30:40.366512 [Flow] Enable top DCM control >>>>>
6205 16:30:40.369792 [Flow] Enable top DCM control <<<<<
6206 16:30:40.373358 Enable DLL master slave shuffle
6207 16:30:40.379735 ==============================================================
6208 16:30:40.380164 Gating Mode config
6209 16:30:40.386152 ==============================================================
6210 16:30:40.389570 Config description:
6211 16:30:40.399127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6212 16:30:40.406075 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6213 16:30:40.409445 SELPH_MODE 0: By rank 1: By Phase
6214 16:30:40.415716 ==============================================================
6215 16:30:40.419036 GAT_TRACK_EN = 0
6216 16:30:40.422565 RX_GATING_MODE = 2
6217 16:30:40.423054 RX_GATING_TRACK_MODE = 2
6218 16:30:40.425670 SELPH_MODE = 1
6219 16:30:40.429032 PICG_EARLY_EN = 1
6220 16:30:40.432093 VALID_LAT_VALUE = 1
6221 16:30:40.439379 ==============================================================
6222 16:30:40.442671 Enter into Gating configuration >>>>
6223 16:30:40.445786 Exit from Gating configuration <<<<
6224 16:30:40.448897 Enter into DVFS_PRE_config >>>>>
6225 16:30:40.458937 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6226 16:30:40.461866 Exit from DVFS_PRE_config <<<<<
6227 16:30:40.465289 Enter into PICG configuration >>>>
6228 16:30:40.468893 Exit from PICG configuration <<<<
6229 16:30:40.472017 [RX_INPUT] configuration >>>>>
6230 16:30:40.475390 [RX_INPUT] configuration <<<<<
6231 16:30:40.478277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6232 16:30:40.485408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6233 16:30:40.491673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6234 16:30:40.498189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6235 16:30:40.504793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6236 16:30:40.507790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6237 16:30:40.515048 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6238 16:30:40.518235 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6239 16:30:40.521136 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6240 16:30:40.524268 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6241 16:30:40.531254 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6242 16:30:40.534348 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6243 16:30:40.537412 ===================================
6244 16:30:40.541348 LPDDR4 DRAM CONFIGURATION
6245 16:30:40.544354 ===================================
6246 16:30:40.544935 EX_ROW_EN[0] = 0x0
6247 16:30:40.547624 EX_ROW_EN[1] = 0x0
6248 16:30:40.548235 LP4Y_EN = 0x0
6249 16:30:40.550825 WORK_FSP = 0x0
6250 16:30:40.553896 WL = 0x2
6251 16:30:40.554576 RL = 0x2
6252 16:30:40.557141 BL = 0x2
6253 16:30:40.557745 RPST = 0x0
6254 16:30:40.560909 RD_PRE = 0x0
6255 16:30:40.561493 WR_PRE = 0x1
6256 16:30:40.563733 WR_PST = 0x0
6257 16:30:40.564408 DBI_WR = 0x0
6258 16:30:40.567169 DBI_RD = 0x0
6259 16:30:40.567787 OTF = 0x1
6260 16:30:40.570490 ===================================
6261 16:30:40.573741 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6262 16:30:40.580347 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6263 16:30:40.583407 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6264 16:30:40.587257 ===================================
6265 16:30:40.590448 LPDDR4 DRAM CONFIGURATION
6266 16:30:40.593569 ===================================
6267 16:30:40.593990 EX_ROW_EN[0] = 0x10
6268 16:30:40.596797 EX_ROW_EN[1] = 0x0
6269 16:30:40.599989 LP4Y_EN = 0x0
6270 16:30:40.600472 WORK_FSP = 0x0
6271 16:30:40.603139 WL = 0x2
6272 16:30:40.603558 RL = 0x2
6273 16:30:40.606257 BL = 0x2
6274 16:30:40.606678 RPST = 0x0
6275 16:30:40.609926 RD_PRE = 0x0
6276 16:30:40.610400 WR_PRE = 0x1
6277 16:30:40.612923 WR_PST = 0x0
6278 16:30:40.613339 DBI_WR = 0x0
6279 16:30:40.616511 DBI_RD = 0x0
6280 16:30:40.616935 OTF = 0x1
6281 16:30:40.619743 ===================================
6282 16:30:40.626201 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6283 16:30:40.631039 nWR fixed to 30
6284 16:30:40.634318 [ModeRegInit_LP4] CH0 RK0
6285 16:30:40.634745 [ModeRegInit_LP4] CH0 RK1
6286 16:30:40.637454 [ModeRegInit_LP4] CH1 RK0
6287 16:30:40.640582 [ModeRegInit_LP4] CH1 RK1
6288 16:30:40.641006 match AC timing 19
6289 16:30:40.647476 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6290 16:30:40.650690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6291 16:30:40.653762 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6292 16:30:40.660640 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6293 16:30:40.663818 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6294 16:30:40.664297 ==
6295 16:30:40.667064 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 16:30:40.670105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 16:30:40.670601 ==
6298 16:30:40.677108 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6299 16:30:40.683797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6300 16:30:40.686854 [CA 0] Center 36 (8~64) winsize 57
6301 16:30:40.690211 [CA 1] Center 36 (8~64) winsize 57
6302 16:30:40.693358 [CA 2] Center 36 (8~64) winsize 57
6303 16:30:40.697043 [CA 3] Center 36 (8~64) winsize 57
6304 16:30:40.700158 [CA 4] Center 36 (8~64) winsize 57
6305 16:30:40.703601 [CA 5] Center 36 (8~64) winsize 57
6306 16:30:40.704030
6307 16:30:40.706934 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6308 16:30:40.707463
6309 16:30:40.709974 [CATrainingPosCal] consider 1 rank data
6310 16:30:40.713202 u2DelayCellTimex100 = 270/100 ps
6311 16:30:40.716411 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 16:30:40.720119 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 16:30:40.723388 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 16:30:40.726645 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 16:30:40.729907 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 16:30:40.732889 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 16:30:40.733328
6318 16:30:40.740040 CA PerBit enable=1, Macro0, CA PI delay=36
6319 16:30:40.740560
6320 16:30:40.740908 [CBTSetCACLKResult] CA Dly = 36
6321 16:30:40.742928 CS Dly: 1 (0~32)
6322 16:30:40.743287 ==
6323 16:30:40.746292 Dram Type= 6, Freq= 0, CH_0, rank 1
6324 16:30:40.749477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 16:30:40.749901 ==
6326 16:30:40.756482 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6327 16:30:40.762677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6328 16:30:40.765966 [CA 0] Center 36 (8~64) winsize 57
6329 16:30:40.769157 [CA 1] Center 36 (8~64) winsize 57
6330 16:30:40.772357 [CA 2] Center 36 (8~64) winsize 57
6331 16:30:40.775997 [CA 3] Center 36 (8~64) winsize 57
6332 16:30:40.779214 [CA 4] Center 36 (8~64) winsize 57
6333 16:30:40.779652 [CA 5] Center 36 (8~64) winsize 57
6334 16:30:40.780088
6335 16:30:40.785755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6336 16:30:40.786336
6337 16:30:40.789321 [CATrainingPosCal] consider 2 rank data
6338 16:30:40.792581 u2DelayCellTimex100 = 270/100 ps
6339 16:30:40.795981 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 16:30:40.799112 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 16:30:40.802492 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 16:30:40.805482 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 16:30:40.808876 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 16:30:40.812141 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 16:30:40.812579
6346 16:30:40.815504 CA PerBit enable=1, Macro0, CA PI delay=36
6347 16:30:40.815945
6348 16:30:40.818675 [CBTSetCACLKResult] CA Dly = 36
6349 16:30:40.822568 CS Dly: 1 (0~32)
6350 16:30:40.823124
6351 16:30:40.825774 ----->DramcWriteLeveling(PI) begin...
6352 16:30:40.826308 ==
6353 16:30:40.828702 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 16:30:40.831946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 16:30:40.832377 ==
6356 16:30:40.835097 Write leveling (Byte 0): 40 => 8
6357 16:30:40.838744 Write leveling (Byte 1): 32 => 0
6358 16:30:40.841792 DramcWriteLeveling(PI) end<-----
6359 16:30:40.842381
6360 16:30:40.842740 ==
6361 16:30:40.845002 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 16:30:40.848655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 16:30:40.849080 ==
6364 16:30:40.851710 [Gating] SW mode calibration
6365 16:30:40.858149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6366 16:30:40.865003 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6367 16:30:40.868135 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6368 16:30:40.874339 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6369 16:30:40.877598 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6370 16:30:40.881063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 16:30:40.887516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 16:30:40.890894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 16:30:40.894073 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 16:30:40.900906 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 16:30:40.903902 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 16:30:40.907776 Total UI for P1: 0, mck2ui 16
6377 16:30:40.910969 best dqsien dly found for B0: ( 0, 14, 24)
6378 16:30:40.914145 Total UI for P1: 0, mck2ui 16
6379 16:30:40.917243 best dqsien dly found for B1: ( 0, 14, 24)
6380 16:30:40.921009 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6381 16:30:40.923953 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6382 16:30:40.924504
6383 16:30:40.927345 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6384 16:30:40.933834 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6385 16:30:40.934297 [Gating] SW calibration Done
6386 16:30:40.934638 ==
6387 16:30:40.937339 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 16:30:40.943508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 16:30:40.943935 ==
6390 16:30:40.944269 RX Vref Scan: 0
6391 16:30:40.944583
6392 16:30:40.946598 RX Vref 0 -> 0, step: 1
6393 16:30:40.947041
6394 16:30:40.950367 RX Delay -410 -> 252, step: 16
6395 16:30:40.953633 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6396 16:30:40.956535 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6397 16:30:40.963529 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6398 16:30:40.966660 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6399 16:30:40.969677 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6400 16:30:40.973006 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6401 16:30:40.980148 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6402 16:30:40.983281 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6403 16:30:40.986228 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6404 16:30:40.989532 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6405 16:30:40.996654 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6406 16:30:40.999956 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6407 16:30:41.002730 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6408 16:30:41.009740 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6409 16:30:41.012986 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6410 16:30:41.016044 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6411 16:30:41.016465 ==
6412 16:30:41.019489 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 16:30:41.025781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 16:30:41.026271 ==
6415 16:30:41.026642 DQS Delay:
6416 16:30:41.027109 DQS0 = 43, DQS1 = 59
6417 16:30:41.028956 DQM Delay:
6418 16:30:41.029375 DQM0 = 10, DQM1 = 11
6419 16:30:41.032077 DQ Delay:
6420 16:30:41.035380 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6421 16:30:41.036107 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6422 16:30:41.038801 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6423 16:30:41.042691 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6424 16:30:41.043123
6425 16:30:41.045885
6426 16:30:41.046385 ==
6427 16:30:41.048863 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 16:30:41.052216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 16:30:41.052674 ==
6430 16:30:41.053014
6431 16:30:41.053330
6432 16:30:41.055531 TX Vref Scan disable
6433 16:30:41.055954 == TX Byte 0 ==
6434 16:30:41.058447 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 16:30:41.065186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 16:30:41.065624 == TX Byte 1 ==
6437 16:30:41.068564 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6438 16:30:41.075309 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6439 16:30:41.075802 ==
6440 16:30:41.078425 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 16:30:41.081698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 16:30:41.082132 ==
6443 16:30:41.082588
6444 16:30:41.082996
6445 16:30:41.084910 TX Vref Scan disable
6446 16:30:41.085344 == TX Byte 0 ==
6447 16:30:41.091637 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6448 16:30:41.094841 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6449 16:30:41.095278 == TX Byte 1 ==
6450 16:30:41.101408 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6451 16:30:41.104523 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6452 16:30:41.104956
6453 16:30:41.105395 [DATLAT]
6454 16:30:41.108255 Freq=400, CH0 RK0
6455 16:30:41.108690
6456 16:30:41.109124 DATLAT Default: 0xf
6457 16:30:41.111330 0, 0xFFFF, sum = 0
6458 16:30:41.111771 1, 0xFFFF, sum = 0
6459 16:30:41.114594 2, 0xFFFF, sum = 0
6460 16:30:41.115029 3, 0xFFFF, sum = 0
6461 16:30:41.118304 4, 0xFFFF, sum = 0
6462 16:30:41.118777 5, 0xFFFF, sum = 0
6463 16:30:41.121312 6, 0xFFFF, sum = 0
6464 16:30:41.121750 7, 0xFFFF, sum = 0
6465 16:30:41.124495 8, 0xFFFF, sum = 0
6466 16:30:41.127593 9, 0xFFFF, sum = 0
6467 16:30:41.128032 10, 0xFFFF, sum = 0
6468 16:30:41.130940 11, 0xFFFF, sum = 0
6469 16:30:41.131425 12, 0xFFFF, sum = 0
6470 16:30:41.134331 13, 0x0, sum = 1
6471 16:30:41.134771 14, 0x0, sum = 2
6472 16:30:41.138192 15, 0x0, sum = 3
6473 16:30:41.138640 16, 0x0, sum = 4
6474 16:30:41.139077 best_step = 14
6475 16:30:41.141272
6476 16:30:41.141747 ==
6477 16:30:41.144061 Dram Type= 6, Freq= 0, CH_0, rank 0
6478 16:30:41.147575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 16:30:41.148012 ==
6480 16:30:41.148468 RX Vref Scan: 1
6481 16:30:41.148879
6482 16:30:41.150584 RX Vref 0 -> 0, step: 1
6483 16:30:41.151057
6484 16:30:41.154139 RX Delay -359 -> 252, step: 8
6485 16:30:41.154703
6486 16:30:41.157695 Set Vref, RX VrefLevel [Byte0]: 60
6487 16:30:41.160701 [Byte1]: 49
6488 16:30:41.165028
6489 16:30:41.165461 Final RX Vref Byte 0 = 60 to rank0
6490 16:30:41.168463 Final RX Vref Byte 1 = 49 to rank0
6491 16:30:41.171494 Final RX Vref Byte 0 = 60 to rank1
6492 16:30:41.174859 Final RX Vref Byte 1 = 49 to rank1==
6493 16:30:41.178309 Dram Type= 6, Freq= 0, CH_0, rank 0
6494 16:30:41.184831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 16:30:41.185270 ==
6496 16:30:41.185705 DQS Delay:
6497 16:30:41.187910 DQS0 = 48, DQS1 = 60
6498 16:30:41.188342 DQM Delay:
6499 16:30:41.188776 DQM0 = 11, DQM1 = 12
6500 16:30:41.191115 DQ Delay:
6501 16:30:41.194275 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6502 16:30:41.197940 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6503 16:30:41.198421 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6504 16:30:41.204530 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6505 16:30:41.205053
6506 16:30:41.205491
6507 16:30:41.211688 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6508 16:30:41.214665 CH0 RK0: MR19=C0C, MR18=BF82
6509 16:30:41.221036 CH0_RK0: MR19=0xC0C, MR18=0xBF82, DQSOSC=386, MR23=63, INC=396, DEC=264
6510 16:30:41.221473 ==
6511 16:30:41.224130 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 16:30:41.227322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 16:30:41.227762 ==
6514 16:30:41.231057 [Gating] SW mode calibration
6515 16:30:41.237643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6516 16:30:41.243828 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6517 16:30:41.247628 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6518 16:30:41.250541 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6519 16:30:41.257391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6520 16:30:41.260640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 16:30:41.263854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 16:30:41.270283 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 16:30:41.273851 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 16:30:41.277150 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 16:30:41.283593 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 16:30:41.286632 Total UI for P1: 0, mck2ui 16
6527 16:30:41.290627 best dqsien dly found for B0: ( 0, 14, 24)
6528 16:30:41.293585 Total UI for P1: 0, mck2ui 16
6529 16:30:41.297117 best dqsien dly found for B1: ( 0, 14, 24)
6530 16:30:41.299963 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6531 16:30:41.303033 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6532 16:30:41.303511
6533 16:30:41.306298 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6534 16:30:41.310243 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6535 16:30:41.313340 [Gating] SW calibration Done
6536 16:30:41.313750 ==
6537 16:30:41.316355 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 16:30:41.319710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 16:30:41.320252 ==
6540 16:30:41.323365 RX Vref Scan: 0
6541 16:30:41.323788
6542 16:30:41.326484 RX Vref 0 -> 0, step: 1
6543 16:30:41.327052
6544 16:30:41.327567 RX Delay -410 -> 252, step: 16
6545 16:30:41.333139 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6546 16:30:41.336332 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6547 16:30:41.339947 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6548 16:30:41.346025 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6549 16:30:41.349943 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6550 16:30:41.352961 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6551 16:30:41.356060 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6552 16:30:41.362654 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6553 16:30:41.366153 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6554 16:30:41.369348 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6555 16:30:41.372407 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6556 16:30:41.379157 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6557 16:30:41.382664 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6558 16:30:41.385706 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6559 16:30:41.389469 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6560 16:30:41.395476 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6561 16:30:41.395906 ==
6562 16:30:41.398700 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 16:30:41.402576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 16:30:41.403002 ==
6565 16:30:41.405811 DQS Delay:
6566 16:30:41.406284 DQS0 = 43, DQS1 = 59
6567 16:30:41.406634 DQM Delay:
6568 16:30:41.408971 DQM0 = 9, DQM1 = 16
6569 16:30:41.409394 DQ Delay:
6570 16:30:41.412044 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6571 16:30:41.415328 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6572 16:30:41.418469 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6573 16:30:41.422008 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6574 16:30:41.422462
6575 16:30:41.422800
6576 16:30:41.423112 ==
6577 16:30:41.425257 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 16:30:41.428442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 16:30:41.428953 ==
6580 16:30:41.432048
6581 16:30:41.432489
6582 16:30:41.432820 TX Vref Scan disable
6583 16:30:41.435242 == TX Byte 0 ==
6584 16:30:41.438285 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6585 16:30:41.441575 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6586 16:30:41.445460 == TX Byte 1 ==
6587 16:30:41.448290 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6588 16:30:41.451873 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6589 16:30:41.452315 ==
6590 16:30:41.455041 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 16:30:41.458452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 16:30:41.461434 ==
6593 16:30:41.461971
6594 16:30:41.462537
6595 16:30:41.462984 TX Vref Scan disable
6596 16:30:41.465076 == TX Byte 0 ==
6597 16:30:41.468172 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6598 16:30:41.472119 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6599 16:30:41.475209 == TX Byte 1 ==
6600 16:30:41.478308 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6601 16:30:41.481719 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6602 16:30:41.482221
6603 16:30:41.482596 [DATLAT]
6604 16:30:41.484551 Freq=400, CH0 RK1
6605 16:30:41.485083
6606 16:30:41.488297 DATLAT Default: 0xe
6607 16:30:41.488848 0, 0xFFFF, sum = 0
6608 16:30:41.491366 1, 0xFFFF, sum = 0
6609 16:30:41.491786 2, 0xFFFF, sum = 0
6610 16:30:41.494699 3, 0xFFFF, sum = 0
6611 16:30:41.495157 4, 0xFFFF, sum = 0
6612 16:30:41.497667 5, 0xFFFF, sum = 0
6613 16:30:41.498115 6, 0xFFFF, sum = 0
6614 16:30:41.501649 7, 0xFFFF, sum = 0
6615 16:30:41.502080 8, 0xFFFF, sum = 0
6616 16:30:41.504370 9, 0xFFFF, sum = 0
6617 16:30:41.504829 10, 0xFFFF, sum = 0
6618 16:30:41.507889 11, 0xFFFF, sum = 0
6619 16:30:41.508319 12, 0xFFFF, sum = 0
6620 16:30:41.510952 13, 0x0, sum = 1
6621 16:30:41.511384 14, 0x0, sum = 2
6622 16:30:41.514110 15, 0x0, sum = 3
6623 16:30:41.514640 16, 0x0, sum = 4
6624 16:30:41.517490 best_step = 14
6625 16:30:41.517913
6626 16:30:41.518291 ==
6627 16:30:41.521317 Dram Type= 6, Freq= 0, CH_0, rank 1
6628 16:30:41.524479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 16:30:41.524995 ==
6630 16:30:41.527486 RX Vref Scan: 0
6631 16:30:41.527913
6632 16:30:41.530522 RX Vref 0 -> 0, step: 1
6633 16:30:41.530960
6634 16:30:41.531302 RX Delay -359 -> 252, step: 8
6635 16:30:41.539425 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6636 16:30:41.542623 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6637 16:30:41.545649 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6638 16:30:41.552132 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6639 16:30:41.555699 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6640 16:30:41.558655 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6641 16:30:41.562475 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6642 16:30:41.568885 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6643 16:30:41.572043 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6644 16:30:41.575190 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6645 16:30:41.578542 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6646 16:30:41.585456 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6647 16:30:41.588345 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6648 16:30:41.592187 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6649 16:30:41.595223 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6650 16:30:41.601416 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6651 16:30:41.601838 ==
6652 16:30:41.604871 Dram Type= 6, Freq= 0, CH_0, rank 1
6653 16:30:41.608457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 16:30:41.608848 ==
6655 16:30:41.609172 DQS Delay:
6656 16:30:41.611433 DQS0 = 44, DQS1 = 60
6657 16:30:41.611921 DQM Delay:
6658 16:30:41.615104 DQM0 = 7, DQM1 = 14
6659 16:30:41.615521 DQ Delay:
6660 16:30:41.618119 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =4
6661 16:30:41.621299 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6662 16:30:41.624414 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6663 16:30:41.628290 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6664 16:30:41.628707
6665 16:30:41.629089
6666 16:30:41.634676 [DQSOSCAuto] RK1, (LSB)MR18= 0xb541, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6667 16:30:41.638222 CH0 RK1: MR19=C0C, MR18=B541
6668 16:30:41.644666 CH0_RK1: MR19=0xC0C, MR18=0xB541, DQSOSC=387, MR23=63, INC=394, DEC=262
6669 16:30:41.647725 [RxdqsGatingPostProcess] freq 400
6670 16:30:41.654712 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6671 16:30:41.658139 best DQS0 dly(2T, 0.5T) = (0, 10)
6672 16:30:41.661163 best DQS1 dly(2T, 0.5T) = (0, 10)
6673 16:30:41.664136 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6674 16:30:41.668104 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6675 16:30:41.668522 best DQS0 dly(2T, 0.5T) = (0, 10)
6676 16:30:41.671385 best DQS1 dly(2T, 0.5T) = (0, 10)
6677 16:30:41.674229 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6678 16:30:41.677633 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6679 16:30:41.680583 Pre-setting of DQS Precalculation
6680 16:30:41.687298 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6681 16:30:41.687723 ==
6682 16:30:41.691104 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 16:30:41.694281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 16:30:41.694708 ==
6685 16:30:41.701134 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6686 16:30:41.707445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6687 16:30:41.710848 [CA 0] Center 36 (8~64) winsize 57
6688 16:30:41.714066 [CA 1] Center 36 (8~64) winsize 57
6689 16:30:41.714546 [CA 2] Center 36 (8~64) winsize 57
6690 16:30:41.716900 [CA 3] Center 36 (8~64) winsize 57
6691 16:30:41.720555 [CA 4] Center 36 (8~64) winsize 57
6692 16:30:41.723583 [CA 5] Center 36 (8~64) winsize 57
6693 16:30:41.724100
6694 16:30:41.727149 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6695 16:30:41.730438
6696 16:30:41.733585 [CATrainingPosCal] consider 1 rank data
6697 16:30:41.737236 u2DelayCellTimex100 = 270/100 ps
6698 16:30:41.740383 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 16:30:41.743489 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 16:30:41.746510 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 16:30:41.749729 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 16:30:41.753440 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 16:30:41.756734 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 16:30:41.757151
6705 16:30:41.759861 CA PerBit enable=1, Macro0, CA PI delay=36
6706 16:30:41.760286
6707 16:30:41.763222 [CBTSetCACLKResult] CA Dly = 36
6708 16:30:41.766601 CS Dly: 1 (0~32)
6709 16:30:41.767030 ==
6710 16:30:41.770040 Dram Type= 6, Freq= 0, CH_1, rank 1
6711 16:30:41.773353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 16:30:41.773786 ==
6713 16:30:41.779292 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6714 16:30:41.786239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6715 16:30:41.789543 [CA 0] Center 36 (8~64) winsize 57
6716 16:30:41.789996 [CA 1] Center 36 (8~64) winsize 57
6717 16:30:41.793213 [CA 2] Center 36 (8~64) winsize 57
6718 16:30:41.795904 [CA 3] Center 36 (8~64) winsize 57
6719 16:30:41.799533 [CA 4] Center 36 (8~64) winsize 57
6720 16:30:41.802566 [CA 5] Center 36 (8~64) winsize 57
6721 16:30:41.803037
6722 16:30:41.806309 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6723 16:30:41.806756
6724 16:30:41.812845 [CATrainingPosCal] consider 2 rank data
6725 16:30:41.813356 u2DelayCellTimex100 = 270/100 ps
6726 16:30:41.819077 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 16:30:41.822659 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 16:30:41.825967 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 16:30:41.829007 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 16:30:41.832651 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 16:30:41.835704 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 16:30:41.836241
6733 16:30:41.838688 CA PerBit enable=1, Macro0, CA PI delay=36
6734 16:30:41.839167
6735 16:30:41.842449 [CBTSetCACLKResult] CA Dly = 36
6736 16:30:41.845694 CS Dly: 1 (0~32)
6737 16:30:41.846281
6738 16:30:41.848766 ----->DramcWriteLeveling(PI) begin...
6739 16:30:41.849452 ==
6740 16:30:41.852617 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 16:30:41.855720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 16:30:41.856211 ==
6743 16:30:41.858867 Write leveling (Byte 0): 40 => 8
6744 16:30:41.862287 Write leveling (Byte 1): 32 => 0
6745 16:30:41.865358 DramcWriteLeveling(PI) end<-----
6746 16:30:41.866028
6747 16:30:41.866864 ==
6748 16:30:41.868524 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 16:30:41.871679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 16:30:41.872200 ==
6751 16:30:41.875337 [Gating] SW mode calibration
6752 16:30:41.881537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6753 16:30:41.888384 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6754 16:30:41.891687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6755 16:30:41.895317 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6756 16:30:41.902116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6757 16:30:41.905031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 16:30:41.908359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 16:30:41.914584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 16:30:41.918435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 16:30:41.921601 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 16:30:41.928253 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 16:30:41.930996 Total UI for P1: 0, mck2ui 16
6764 16:30:41.934732 best dqsien dly found for B0: ( 0, 14, 24)
6765 16:30:41.937660 Total UI for P1: 0, mck2ui 16
6766 16:30:41.941285 best dqsien dly found for B1: ( 0, 14, 24)
6767 16:30:41.944146 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6768 16:30:41.948042 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6769 16:30:41.948493
6770 16:30:41.951123 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6771 16:30:41.954822 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6772 16:30:41.957442 [Gating] SW calibration Done
6773 16:30:41.957859 ==
6774 16:30:41.960709 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 16:30:41.964062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 16:30:41.964483 ==
6777 16:30:41.967283 RX Vref Scan: 0
6778 16:30:41.967723
6779 16:30:41.970494 RX Vref 0 -> 0, step: 1
6780 16:30:41.970910
6781 16:30:41.971240 RX Delay -410 -> 252, step: 16
6782 16:30:41.977679 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6783 16:30:41.980840 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6784 16:30:41.984460 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6785 16:30:41.987807 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6786 16:30:41.993970 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6787 16:30:41.997657 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6788 16:30:42.000693 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6789 16:30:42.007797 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6790 16:30:42.010659 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6791 16:30:42.014080 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6792 16:30:42.017119 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6793 16:30:42.023772 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6794 16:30:42.027582 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6795 16:30:42.030616 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6796 16:30:42.033593 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6797 16:30:42.040135 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6798 16:30:42.040556 ==
6799 16:30:42.043402 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 16:30:42.047110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 16:30:42.047535 ==
6802 16:30:42.047863 DQS Delay:
6803 16:30:42.050060 DQS0 = 43, DQS1 = 51
6804 16:30:42.050520 DQM Delay:
6805 16:30:42.053716 DQM0 = 12, DQM1 = 14
6806 16:30:42.054135 DQ Delay:
6807 16:30:42.056962 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6808 16:30:42.060046 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6809 16:30:42.063873 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6810 16:30:42.067156 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6811 16:30:42.067576
6812 16:30:42.067906
6813 16:30:42.068214 ==
6814 16:30:42.070227 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 16:30:42.073201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 16:30:42.073621 ==
6817 16:30:42.073958
6818 16:30:42.074316
6819 16:30:42.076561 TX Vref Scan disable
6820 16:30:42.080076 == TX Byte 0 ==
6821 16:30:42.083314 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 16:30:42.086370 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 16:30:42.089888 == TX Byte 1 ==
6824 16:30:42.093363 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6825 16:30:42.096499 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6826 16:30:42.096927 ==
6827 16:30:42.099663 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 16:30:42.102727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 16:30:42.106435 ==
6830 16:30:42.106850
6831 16:30:42.107176
6832 16:30:42.107477 TX Vref Scan disable
6833 16:30:42.109723 == TX Byte 0 ==
6834 16:30:42.112742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6835 16:30:42.116465 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6836 16:30:42.119860 == TX Byte 1 ==
6837 16:30:42.122924 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6838 16:30:42.125985 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6839 16:30:42.126489
6840 16:30:42.129335 [DATLAT]
6841 16:30:42.129749 Freq=400, CH1 RK0
6842 16:30:42.130077
6843 16:30:42.132499 DATLAT Default: 0xf
6844 16:30:42.132913 0, 0xFFFF, sum = 0
6845 16:30:42.136031 1, 0xFFFF, sum = 0
6846 16:30:42.136473 2, 0xFFFF, sum = 0
6847 16:30:42.139455 3, 0xFFFF, sum = 0
6848 16:30:42.139876 4, 0xFFFF, sum = 0
6849 16:30:42.143049 5, 0xFFFF, sum = 0
6850 16:30:42.143467 6, 0xFFFF, sum = 0
6851 16:30:42.145980 7, 0xFFFF, sum = 0
6852 16:30:42.146476 8, 0xFFFF, sum = 0
6853 16:30:42.149735 9, 0xFFFF, sum = 0
6854 16:30:42.150158 10, 0xFFFF, sum = 0
6855 16:30:42.153042 11, 0xFFFF, sum = 0
6856 16:30:42.156010 12, 0xFFFF, sum = 0
6857 16:30:42.156607 13, 0x0, sum = 1
6858 16:30:42.156981 14, 0x0, sum = 2
6859 16:30:42.159392 15, 0x0, sum = 3
6860 16:30:42.159810 16, 0x0, sum = 4
6861 16:30:42.162927 best_step = 14
6862 16:30:42.163342
6863 16:30:42.163673 ==
6864 16:30:42.166004 Dram Type= 6, Freq= 0, CH_1, rank 0
6865 16:30:42.169144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 16:30:42.169650 ==
6867 16:30:42.172659 RX Vref Scan: 1
6868 16:30:42.173073
6869 16:30:42.173405 RX Vref 0 -> 0, step: 1
6870 16:30:42.175668
6871 16:30:42.176085 RX Delay -343 -> 252, step: 8
6872 16:30:42.176412
6873 16:30:42.179042 Set Vref, RX VrefLevel [Byte0]: 52
6874 16:30:42.182137 [Byte1]: 57
6875 16:30:42.187717
6876 16:30:42.188129 Final RX Vref Byte 0 = 52 to rank0
6877 16:30:42.191126 Final RX Vref Byte 1 = 57 to rank0
6878 16:30:42.194077 Final RX Vref Byte 0 = 52 to rank1
6879 16:30:42.197519 Final RX Vref Byte 1 = 57 to rank1==
6880 16:30:42.200525 Dram Type= 6, Freq= 0, CH_1, rank 0
6881 16:30:42.207395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 16:30:42.207824 ==
6883 16:30:42.208175 DQS Delay:
6884 16:30:42.210367 DQS0 = 44, DQS1 = 56
6885 16:30:42.210943 DQM Delay:
6886 16:30:42.211419 DQM0 = 7, DQM1 = 12
6887 16:30:42.214037 DQ Delay:
6888 16:30:42.217272 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6889 16:30:42.217761 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6890 16:30:42.220182 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6891 16:30:42.224090 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6892 16:30:42.224509
6893 16:30:42.224840
6894 16:30:42.233951 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6895 16:30:42.237101 CH1 RK0: MR19=C0C, MR18=9A71
6896 16:30:42.243949 CH1_RK0: MR19=0xC0C, MR18=0x9A71, DQSOSC=390, MR23=63, INC=388, DEC=258
6897 16:30:42.244367 ==
6898 16:30:42.247016 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 16:30:42.250350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 16:30:42.250807 ==
6901 16:30:42.253311 [Gating] SW mode calibration
6902 16:30:42.260163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6903 16:30:42.266715 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6904 16:30:42.270214 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6905 16:30:42.273172 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6906 16:30:42.280251 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6907 16:30:42.283473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 16:30:42.286763 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 16:30:42.292979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 16:30:42.296473 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 16:30:42.300177 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 16:30:42.306135 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 16:30:42.306647 Total UI for P1: 0, mck2ui 16
6914 16:30:42.313043 best dqsien dly found for B0: ( 0, 14, 24)
6915 16:30:42.313485 Total UI for P1: 0, mck2ui 16
6916 16:30:42.319189 best dqsien dly found for B1: ( 0, 14, 24)
6917 16:30:42.322929 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6918 16:30:42.326123 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6919 16:30:42.326606
6920 16:30:42.329204 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6921 16:30:42.332497 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6922 16:30:42.335693 [Gating] SW calibration Done
6923 16:30:42.336112 ==
6924 16:30:42.338837 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 16:30:42.342588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 16:30:42.343003 ==
6927 16:30:42.345838 RX Vref Scan: 0
6928 16:30:42.346288
6929 16:30:42.348989 RX Vref 0 -> 0, step: 1
6930 16:30:42.349421
6931 16:30:42.349754 RX Delay -410 -> 252, step: 16
6932 16:30:42.355586 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6933 16:30:42.358562 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6934 16:30:42.362323 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6935 16:30:42.368511 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6936 16:30:42.371681 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6937 16:30:42.375394 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6938 16:30:42.378664 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6939 16:30:42.385102 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6940 16:30:42.388064 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6941 16:30:42.391675 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6942 16:30:42.394984 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6943 16:30:42.401426 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6944 16:30:42.404971 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6945 16:30:42.408098 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6946 16:30:42.414598 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6947 16:30:42.418096 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6948 16:30:42.418586 ==
6949 16:30:42.421299 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 16:30:42.424502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 16:30:42.424927 ==
6952 16:30:42.427625 DQS Delay:
6953 16:30:42.428047 DQS0 = 43, DQS1 = 59
6954 16:30:42.428380 DQM Delay:
6955 16:30:42.431377 DQM0 = 12, DQM1 = 22
6956 16:30:42.431841 DQ Delay:
6957 16:30:42.434540 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6958 16:30:42.437597 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6959 16:30:42.440953 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6960 16:30:42.444100 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6961 16:30:42.444523
6962 16:30:42.444853
6963 16:30:42.445162 ==
6964 16:30:42.448097 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 16:30:42.454221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 16:30:42.454725 ==
6967 16:30:42.455062
6968 16:30:42.455371
6969 16:30:42.455668 TX Vref Scan disable
6970 16:30:42.457284 == TX Byte 0 ==
6971 16:30:42.460905 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6972 16:30:42.463839 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6973 16:30:42.467423 == TX Byte 1 ==
6974 16:30:42.470285 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6975 16:30:42.473982 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6976 16:30:42.474504 ==
6977 16:30:42.477334 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 16:30:42.483833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 16:30:42.484253 ==
6980 16:30:42.484684
6981 16:30:42.485100
6982 16:30:42.485402 TX Vref Scan disable
6983 16:30:42.486737 == TX Byte 0 ==
6984 16:30:42.490524 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6985 16:30:42.493541 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6986 16:30:42.496978 == TX Byte 1 ==
6987 16:30:42.500460 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6988 16:30:42.503588 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6989 16:30:42.504007
6990 16:30:42.506973 [DATLAT]
6991 16:30:42.507386 Freq=400, CH1 RK1
6992 16:30:42.507716
6993 16:30:42.510589 DATLAT Default: 0xe
6994 16:30:42.511008 0, 0xFFFF, sum = 0
6995 16:30:42.513571 1, 0xFFFF, sum = 0
6996 16:30:42.514001 2, 0xFFFF, sum = 0
6997 16:30:42.516566 3, 0xFFFF, sum = 0
6998 16:30:42.517054 4, 0xFFFF, sum = 0
6999 16:30:42.519996 5, 0xFFFF, sum = 0
7000 16:30:42.520478 6, 0xFFFF, sum = 0
7001 16:30:42.523016 7, 0xFFFF, sum = 0
7002 16:30:42.527040 8, 0xFFFF, sum = 0
7003 16:30:42.527462 9, 0xFFFF, sum = 0
7004 16:30:42.529939 10, 0xFFFF, sum = 0
7005 16:30:42.530416 11, 0xFFFF, sum = 0
7006 16:30:42.532896 12, 0xFFFF, sum = 0
7007 16:30:42.533396 13, 0x0, sum = 1
7008 16:30:42.536677 14, 0x0, sum = 2
7009 16:30:42.537113 15, 0x0, sum = 3
7010 16:30:42.539835 16, 0x0, sum = 4
7011 16:30:42.540267 best_step = 14
7012 16:30:42.540599
7013 16:30:42.540910 ==
7014 16:30:42.543106 Dram Type= 6, Freq= 0, CH_1, rank 1
7015 16:30:42.546493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7016 16:30:42.546920 ==
7017 16:30:42.549432 RX Vref Scan: 0
7018 16:30:42.549856
7019 16:30:42.553277 RX Vref 0 -> 0, step: 1
7020 16:30:42.553699
7021 16:30:42.554035 RX Delay -359 -> 252, step: 8
7022 16:30:42.562187 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7023 16:30:42.565345 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7024 16:30:42.568650 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7025 16:30:42.575369 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7026 16:30:42.578210 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7027 16:30:42.582089 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7028 16:30:42.585159 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7029 16:30:42.591485 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7030 16:30:42.594727 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7031 16:30:42.598018 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7032 16:30:42.601475 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7033 16:30:42.607996 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7034 16:30:42.611092 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7035 16:30:42.614663 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7036 16:30:42.618217 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7037 16:30:42.624363 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7038 16:30:42.624783 ==
7039 16:30:42.627976 Dram Type= 6, Freq= 0, CH_1, rank 1
7040 16:30:42.631289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7041 16:30:42.631740 ==
7042 16:30:42.632070 DQS Delay:
7043 16:30:42.634349 DQS0 = 44, DQS1 = 60
7044 16:30:42.634762 DQM Delay:
7045 16:30:42.638260 DQM0 = 7, DQM1 = 14
7046 16:30:42.638784 DQ Delay:
7047 16:30:42.641217 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
7048 16:30:42.644417 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7049 16:30:42.647514 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7050 16:30:42.651408 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7051 16:30:42.651847
7052 16:30:42.652282
7053 16:30:42.657606 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7054 16:30:42.660970 CH1 RK1: MR19=C0C, MR18=6A59
7055 16:30:42.667565 CH1_RK1: MR19=0xC0C, MR18=0x6A59, DQSOSC=396, MR23=63, INC=376, DEC=251
7056 16:30:42.670614 [RxdqsGatingPostProcess] freq 400
7057 16:30:42.677241 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7058 16:30:42.680826 best DQS0 dly(2T, 0.5T) = (0, 10)
7059 16:30:42.683710 best DQS1 dly(2T, 0.5T) = (0, 10)
7060 16:30:42.687285 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7061 16:30:42.690645 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7062 16:30:42.691064 best DQS0 dly(2T, 0.5T) = (0, 10)
7063 16:30:42.693881 best DQS1 dly(2T, 0.5T) = (0, 10)
7064 16:30:42.697002 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7065 16:30:42.700679 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7066 16:30:42.703750 Pre-setting of DQS Precalculation
7067 16:30:42.709838 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7068 16:30:42.717294 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7069 16:30:42.723455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7070 16:30:42.723905
7071 16:30:42.724451
7072 16:30:42.726418 [Calibration Summary] 800 Mbps
7073 16:30:42.730084 CH 0, Rank 0
7074 16:30:42.730566 SW Impedance : PASS
7075 16:30:42.733169 DUTY Scan : NO K
7076 16:30:42.736377 ZQ Calibration : PASS
7077 16:30:42.736956 Jitter Meter : NO K
7078 16:30:42.739590 CBT Training : PASS
7079 16:30:42.740185 Write leveling : PASS
7080 16:30:42.743432 RX DQS gating : PASS
7081 16:30:42.746515 RX DQ/DQS(RDDQC) : PASS
7082 16:30:42.746945 TX DQ/DQS : PASS
7083 16:30:42.749507 RX DATLAT : PASS
7084 16:30:42.752715 RX DQ/DQS(Engine): PASS
7085 16:30:42.753174 TX OE : NO K
7086 16:30:42.756032 All Pass.
7087 16:30:42.756472
7088 16:30:42.756912 CH 0, Rank 1
7089 16:30:42.759159 SW Impedance : PASS
7090 16:30:42.759597 DUTY Scan : NO K
7091 16:30:42.762924 ZQ Calibration : PASS
7092 16:30:42.766285 Jitter Meter : NO K
7093 16:30:42.766710 CBT Training : PASS
7094 16:30:42.769470 Write leveling : NO K
7095 16:30:42.772728 RX DQS gating : PASS
7096 16:30:42.773152 RX DQ/DQS(RDDQC) : PASS
7097 16:30:42.775744 TX DQ/DQS : PASS
7098 16:30:42.779278 RX DATLAT : PASS
7099 16:30:42.779703 RX DQ/DQS(Engine): PASS
7100 16:30:42.782326 TX OE : NO K
7101 16:30:42.782754 All Pass.
7102 16:30:42.783088
7103 16:30:42.785996 CH 1, Rank 0
7104 16:30:42.786465 SW Impedance : PASS
7105 16:30:42.788916 DUTY Scan : NO K
7106 16:30:42.792731 ZQ Calibration : PASS
7107 16:30:42.793253 Jitter Meter : NO K
7108 16:30:42.795731 CBT Training : PASS
7109 16:30:42.798942 Write leveling : PASS
7110 16:30:42.799366 RX DQS gating : PASS
7111 16:30:42.802035 RX DQ/DQS(RDDQC) : PASS
7112 16:30:42.805320 TX DQ/DQS : PASS
7113 16:30:42.805886 RX DATLAT : PASS
7114 16:30:42.808978 RX DQ/DQS(Engine): PASS
7115 16:30:42.812223 TX OE : NO K
7116 16:30:42.812648 All Pass.
7117 16:30:42.812985
7118 16:30:42.813294 CH 1, Rank 1
7119 16:30:42.815426 SW Impedance : PASS
7120 16:30:42.818360 DUTY Scan : NO K
7121 16:30:42.818788 ZQ Calibration : PASS
7122 16:30:42.822040 Jitter Meter : NO K
7123 16:30:42.825363 CBT Training : PASS
7124 16:30:42.825786 Write leveling : NO K
7125 16:30:42.828677 RX DQS gating : PASS
7126 16:30:42.829090 RX DQ/DQS(RDDQC) : PASS
7127 16:30:42.832007 TX DQ/DQS : PASS
7128 16:30:42.835122 RX DATLAT : PASS
7129 16:30:42.835561 RX DQ/DQS(Engine): PASS
7130 16:30:42.838236 TX OE : NO K
7131 16:30:42.838693 All Pass.
7132 16:30:42.839027
7133 16:30:42.841814 DramC Write-DBI off
7134 16:30:42.845009 PER_BANK_REFRESH: Hybrid Mode
7135 16:30:42.845531 TX_TRACKING: ON
7136 16:30:42.855117 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7137 16:30:42.858107 [FAST_K] Save calibration result to emmc
7138 16:30:42.861914 dramc_set_vcore_voltage set vcore to 725000
7139 16:30:42.864989 Read voltage for 1600, 0
7140 16:30:42.865534 Vio18 = 0
7141 16:30:42.868136 Vcore = 725000
7142 16:30:42.868736 Vdram = 0
7143 16:30:42.869276 Vddq = 0
7144 16:30:42.869734 Vmddr = 0
7145 16:30:42.874634 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7146 16:30:42.881016 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7147 16:30:42.881433 MEM_TYPE=3, freq_sel=13
7148 16:30:42.884555 sv_algorithm_assistance_LP4_3733
7149 16:30:42.887811 ============ PULL DRAM RESETB DOWN ============
7150 16:30:42.894435 ========== PULL DRAM RESETB DOWN end =========
7151 16:30:42.898305 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7152 16:30:42.901297 ===================================
7153 16:30:42.904143 LPDDR4 DRAM CONFIGURATION
7154 16:30:42.907362 ===================================
7155 16:30:42.907785 EX_ROW_EN[0] = 0x0
7156 16:30:42.911282 EX_ROW_EN[1] = 0x0
7157 16:30:42.914281 LP4Y_EN = 0x0
7158 16:30:42.914714 WORK_FSP = 0x1
7159 16:30:42.917376 WL = 0x5
7160 16:30:42.917810 RL = 0x5
7161 16:30:42.920561 BL = 0x2
7162 16:30:42.920983 RPST = 0x0
7163 16:30:42.924475 RD_PRE = 0x0
7164 16:30:42.924952 WR_PRE = 0x1
7165 16:30:42.927655 WR_PST = 0x1
7166 16:30:42.928078 DBI_WR = 0x0
7167 16:30:42.930724 DBI_RD = 0x0
7168 16:30:42.931145 OTF = 0x1
7169 16:30:42.933794 ===================================
7170 16:30:42.936999 ===================================
7171 16:30:42.940539 ANA top config
7172 16:30:42.943919 ===================================
7173 16:30:42.944372 DLL_ASYNC_EN = 0
7174 16:30:42.946962 ALL_SLAVE_EN = 0
7175 16:30:42.950287 NEW_RANK_MODE = 1
7176 16:30:42.953711 DLL_IDLE_MODE = 1
7177 16:30:42.956967 LP45_APHY_COMB_EN = 1
7178 16:30:42.957403 TX_ODT_DIS = 0
7179 16:30:42.960361 NEW_8X_MODE = 1
7180 16:30:42.964057 ===================================
7181 16:30:42.967209 ===================================
7182 16:30:42.970353 data_rate = 3200
7183 16:30:42.973530 CKR = 1
7184 16:30:42.976763 DQ_P2S_RATIO = 8
7185 16:30:42.980037 ===================================
7186 16:30:42.983322 CA_P2S_RATIO = 8
7187 16:30:42.983760 DQ_CA_OPEN = 0
7188 16:30:42.986948 DQ_SEMI_OPEN = 0
7189 16:30:42.989859 CA_SEMI_OPEN = 0
7190 16:30:42.992945 CA_FULL_RATE = 0
7191 16:30:42.996782 DQ_CKDIV4_EN = 0
7192 16:30:42.999846 CA_CKDIV4_EN = 0
7193 16:30:43.000282 CA_PREDIV_EN = 0
7194 16:30:43.002977 PH8_DLY = 12
7195 16:30:43.006336 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7196 16:30:43.010069 DQ_AAMCK_DIV = 4
7197 16:30:43.012951 CA_AAMCK_DIV = 4
7198 16:30:43.016671 CA_ADMCK_DIV = 4
7199 16:30:43.017097 DQ_TRACK_CA_EN = 0
7200 16:30:43.019728 CA_PICK = 1600
7201 16:30:43.022907 CA_MCKIO = 1600
7202 16:30:43.026038 MCKIO_SEMI = 0
7203 16:30:43.029382 PLL_FREQ = 3068
7204 16:30:43.033081 DQ_UI_PI_RATIO = 32
7205 16:30:43.036258 CA_UI_PI_RATIO = 0
7206 16:30:43.039417 ===================================
7207 16:30:43.043057 ===================================
7208 16:30:43.043631 memory_type:LPDDR4
7209 16:30:43.046218 GP_NUM : 10
7210 16:30:43.049268 SRAM_EN : 1
7211 16:30:43.049646 MD32_EN : 0
7212 16:30:43.052860 ===================================
7213 16:30:43.055838 [ANA_INIT] >>>>>>>>>>>>>>
7214 16:30:43.059417 <<<<<< [CONFIGURE PHASE]: ANA_TX
7215 16:30:43.062416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7216 16:30:43.066049 ===================================
7217 16:30:43.069438 data_rate = 3200,PCW = 0X7600
7218 16:30:43.072785 ===================================
7219 16:30:43.075778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7220 16:30:43.079184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7221 16:30:43.085559 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7222 16:30:43.092323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7223 16:30:43.095459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7224 16:30:43.098772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7225 16:30:43.099269 [ANA_INIT] flow start
7226 16:30:43.102306 [ANA_INIT] PLL >>>>>>>>
7227 16:30:43.105498 [ANA_INIT] PLL <<<<<<<<
7228 16:30:43.105911 [ANA_INIT] MIDPI >>>>>>>>
7229 16:30:43.108608 [ANA_INIT] MIDPI <<<<<<<<
7230 16:30:43.111754 [ANA_INIT] DLL >>>>>>>>
7231 16:30:43.112308 [ANA_INIT] DLL <<<<<<<<
7232 16:30:43.115742 [ANA_INIT] flow end
7233 16:30:43.118582 ============ LP4 DIFF to SE enter ============
7234 16:30:43.125086 ============ LP4 DIFF to SE exit ============
7235 16:30:43.125573 [ANA_INIT] <<<<<<<<<<<<<
7236 16:30:43.128579 [Flow] Enable top DCM control >>>>>
7237 16:30:43.131892 [Flow] Enable top DCM control <<<<<
7238 16:30:43.135115 Enable DLL master slave shuffle
7239 16:30:43.141635 ==============================================================
7240 16:30:43.142151 Gating Mode config
7241 16:30:43.148257 ==============================================================
7242 16:30:43.151615 Config description:
7243 16:30:43.158079 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7244 16:30:43.164734 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7245 16:30:43.171443 SELPH_MODE 0: By rank 1: By Phase
7246 16:30:43.177885 ==============================================================
7247 16:30:43.181666 GAT_TRACK_EN = 1
7248 16:30:43.182098 RX_GATING_MODE = 2
7249 16:30:43.184480 RX_GATING_TRACK_MODE = 2
7250 16:30:43.187991 SELPH_MODE = 1
7251 16:30:43.191426 PICG_EARLY_EN = 1
7252 16:30:43.194596 VALID_LAT_VALUE = 1
7253 16:30:43.201030 ==============================================================
7254 16:30:43.204758 Enter into Gating configuration >>>>
7255 16:30:43.207778 Exit from Gating configuration <<<<
7256 16:30:43.211136 Enter into DVFS_PRE_config >>>>>
7257 16:30:43.221143 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7258 16:30:43.224183 Exit from DVFS_PRE_config <<<<<
7259 16:30:43.227492 Enter into PICG configuration >>>>
7260 16:30:43.231249 Exit from PICG configuration <<<<
7261 16:30:43.234089 [RX_INPUT] configuration >>>>>
7262 16:30:43.237760 [RX_INPUT] configuration <<<<<
7263 16:30:43.240895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7264 16:30:43.247321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7265 16:30:43.254319 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7266 16:30:43.260741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7267 16:30:43.263891 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7268 16:30:43.270404 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7269 16:30:43.273354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7270 16:30:43.280229 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7271 16:30:43.283465 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7272 16:30:43.287275 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7273 16:30:43.289791 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7274 16:30:43.296725 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7275 16:30:43.300279 ===================================
7276 16:30:43.303530 LPDDR4 DRAM CONFIGURATION
7277 16:30:43.306850 ===================================
7278 16:30:43.307080 EX_ROW_EN[0] = 0x0
7279 16:30:43.309871 EX_ROW_EN[1] = 0x0
7280 16:30:43.310103 LP4Y_EN = 0x0
7281 16:30:43.313028 WORK_FSP = 0x1
7282 16:30:43.313256 WL = 0x5
7283 16:30:43.316335 RL = 0x5
7284 16:30:43.316643 BL = 0x2
7285 16:30:43.319767 RPST = 0x0
7286 16:30:43.319997 RD_PRE = 0x0
7287 16:30:43.323142 WR_PRE = 0x1
7288 16:30:43.323369 WR_PST = 0x1
7289 16:30:43.326366 DBI_WR = 0x0
7290 16:30:43.329557 DBI_RD = 0x0
7291 16:30:43.329786 OTF = 0x1
7292 16:30:43.333390 ===================================
7293 16:30:43.336611 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7294 16:30:43.339654 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7295 16:30:43.346390 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7296 16:30:43.349666 ===================================
7297 16:30:43.352753 LPDDR4 DRAM CONFIGURATION
7298 16:30:43.356391 ===================================
7299 16:30:43.356818 EX_ROW_EN[0] = 0x10
7300 16:30:43.359526 EX_ROW_EN[1] = 0x0
7301 16:30:43.359951 LP4Y_EN = 0x0
7302 16:30:43.362647 WORK_FSP = 0x1
7303 16:30:43.363154 WL = 0x5
7304 16:30:43.365919 RL = 0x5
7305 16:30:43.366395 BL = 0x2
7306 16:30:43.369762 RPST = 0x0
7307 16:30:43.370442 RD_PRE = 0x0
7308 16:30:43.373066 WR_PRE = 0x1
7309 16:30:43.373518 WR_PST = 0x1
7310 16:30:43.375921 DBI_WR = 0x0
7311 16:30:43.379064 DBI_RD = 0x0
7312 16:30:43.379635 OTF = 0x1
7313 16:30:43.382732 ===================================
7314 16:30:43.389353 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7315 16:30:43.389780 ==
7316 16:30:43.392711 Dram Type= 6, Freq= 0, CH_0, rank 0
7317 16:30:43.395998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7318 16:30:43.396413 ==
7319 16:30:43.399302 [Duty_Offset_Calibration]
7320 16:30:43.399725 B0:1 B1:-1 CA:0
7321 16:30:43.402442
7322 16:30:43.405805 [DutyScan_Calibration_Flow] k_type=0
7323 16:30:43.413938
7324 16:30:43.414488 ==CLK 0==
7325 16:30:43.417653 Final CLK duty delay cell = 0
7326 16:30:43.420415 [0] MAX Duty = 5125%(X100), DQS PI = 20
7327 16:30:43.423718 [0] MIN Duty = 4907%(X100), DQS PI = 6
7328 16:30:43.427438 [0] AVG Duty = 5016%(X100)
7329 16:30:43.428007
7330 16:30:43.430599 CH0 CLK Duty spec in!! Max-Min= 218%
7331 16:30:43.433747 [DutyScan_Calibration_Flow] ====Done====
7332 16:30:43.434337
7333 16:30:43.437027 [DutyScan_Calibration_Flow] k_type=1
7334 16:30:43.453101
7335 16:30:43.453620 ==DQS 0 ==
7336 16:30:43.456245 Final DQS duty delay cell = -4
7337 16:30:43.459445 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7338 16:30:43.463172 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7339 16:30:43.466121 [-4] AVG Duty = 4922%(X100)
7340 16:30:43.466588
7341 16:30:43.466924 ==DQS 1 ==
7342 16:30:43.469499 Final DQS duty delay cell = 0
7343 16:30:43.472591 [0] MAX Duty = 5156%(X100), DQS PI = 2
7344 16:30:43.476534 [0] MIN Duty = 5000%(X100), DQS PI = 20
7345 16:30:43.479819 [0] AVG Duty = 5078%(X100)
7346 16:30:43.480243
7347 16:30:43.482919 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7348 16:30:43.483343
7349 16:30:43.486223 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7350 16:30:43.489765 [DutyScan_Calibration_Flow] ====Done====
7351 16:30:43.490224
7352 16:30:43.492537 [DutyScan_Calibration_Flow] k_type=3
7353 16:30:43.510360
7354 16:30:43.511140 ==DQM 0 ==
7355 16:30:43.514305 Final DQM duty delay cell = 0
7356 16:30:43.517446 [0] MAX Duty = 5093%(X100), DQS PI = 18
7357 16:30:43.520607 [0] MIN Duty = 4875%(X100), DQS PI = 10
7358 16:30:43.523862 [0] AVG Duty = 4984%(X100)
7359 16:30:43.524288
7360 16:30:43.524619 ==DQM 1 ==
7361 16:30:43.527157 Final DQM duty delay cell = 0
7362 16:30:43.530767 [0] MAX Duty = 5000%(X100), DQS PI = 8
7363 16:30:43.533667 [0] MIN Duty = 4782%(X100), DQS PI = 20
7364 16:30:43.536874 [0] AVG Duty = 4891%(X100)
7365 16:30:43.537293
7366 16:30:43.540345 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7367 16:30:43.540820
7368 16:30:43.543750 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7369 16:30:43.546888 [DutyScan_Calibration_Flow] ====Done====
7370 16:30:43.547332
7371 16:30:43.549704 [DutyScan_Calibration_Flow] k_type=2
7372 16:30:43.566590
7373 16:30:43.566683 ==DQ 0 ==
7374 16:30:43.569658 Final DQ duty delay cell = -4
7375 16:30:43.573223 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7376 16:30:43.576442 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7377 16:30:43.580139 [-4] AVG Duty = 4953%(X100)
7378 16:30:43.580233
7379 16:30:43.580307 ==DQ 1 ==
7380 16:30:43.583341 Final DQ duty delay cell = 0
7381 16:30:43.586735 [0] MAX Duty = 5125%(X100), DQS PI = 4
7382 16:30:43.590059 [0] MIN Duty = 5000%(X100), DQS PI = 36
7383 16:30:43.593130 [0] AVG Duty = 5062%(X100)
7384 16:30:43.593615
7385 16:30:43.596448 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7386 16:30:43.596868
7387 16:30:43.599983 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7388 16:30:43.602842 [DutyScan_Calibration_Flow] ====Done====
7389 16:30:43.603260 ==
7390 16:30:43.606125 Dram Type= 6, Freq= 0, CH_1, rank 0
7391 16:30:43.609786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7392 16:30:43.610262 ==
7393 16:30:43.613002 [Duty_Offset_Calibration]
7394 16:30:43.613419 B0:-1 B1:1 CA:2
7395 16:30:43.616169
7396 16:30:43.616583 [DutyScan_Calibration_Flow] k_type=0
7397 16:30:43.627950
7398 16:30:43.628406 ==CLK 0==
7399 16:30:43.631070 Final CLK duty delay cell = 0
7400 16:30:43.634122 [0] MAX Duty = 5187%(X100), DQS PI = 24
7401 16:30:43.637371 [0] MIN Duty = 4969%(X100), DQS PI = 62
7402 16:30:43.640602 [0] AVG Duty = 5078%(X100)
7403 16:30:43.641253
7404 16:30:43.643864 CH1 CLK Duty spec in!! Max-Min= 218%
7405 16:30:43.647668 [DutyScan_Calibration_Flow] ====Done====
7406 16:30:43.648103
7407 16:30:43.650633 [DutyScan_Calibration_Flow] k_type=1
7408 16:30:43.667555
7409 16:30:43.668060 ==DQS 0 ==
7410 16:30:43.670743 Final DQS duty delay cell = 0
7411 16:30:43.673497 [0] MAX Duty = 5124%(X100), DQS PI = 18
7412 16:30:43.677075 [0] MIN Duty = 4907%(X100), DQS PI = 10
7413 16:30:43.680839 [0] AVG Duty = 5015%(X100)
7414 16:30:43.681309
7415 16:30:43.681707 ==DQS 1 ==
7416 16:30:43.683913 Final DQS duty delay cell = 0
7417 16:30:43.687034 [0] MAX Duty = 5093%(X100), DQS PI = 26
7418 16:30:43.690229 [0] MIN Duty = 4969%(X100), DQS PI = 54
7419 16:30:43.693983 [0] AVG Duty = 5031%(X100)
7420 16:30:43.694561
7421 16:30:43.696959 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7422 16:30:43.697399
7423 16:30:43.700463 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7424 16:30:43.703496 [DutyScan_Calibration_Flow] ====Done====
7425 16:30:43.704041
7426 16:30:43.706985 [DutyScan_Calibration_Flow] k_type=3
7427 16:30:43.724333
7428 16:30:43.724899 ==DQM 0 ==
7429 16:30:43.727505 Final DQM duty delay cell = 0
7430 16:30:43.730671 [0] MAX Duty = 5218%(X100), DQS PI = 18
7431 16:30:43.733908 [0] MIN Duty = 5031%(X100), DQS PI = 8
7432 16:30:43.737211 [0] AVG Duty = 5124%(X100)
7433 16:30:43.737638
7434 16:30:43.737974 ==DQM 1 ==
7435 16:30:43.740822 Final DQM duty delay cell = 0
7436 16:30:43.743430 [0] MAX Duty = 5125%(X100), DQS PI = 2
7437 16:30:43.747222 [0] MIN Duty = 4969%(X100), DQS PI = 28
7438 16:30:43.750471 [0] AVG Duty = 5047%(X100)
7439 16:30:43.750895
7440 16:30:43.753610 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7441 16:30:43.754035
7442 16:30:43.756842 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7443 16:30:43.760398 [DutyScan_Calibration_Flow] ====Done====
7444 16:30:43.760821
7445 16:30:43.763241 [DutyScan_Calibration_Flow] k_type=2
7446 16:30:43.781027
7447 16:30:43.781485 ==DQ 0 ==
7448 16:30:43.784541 Final DQ duty delay cell = 0
7449 16:30:43.787589 [0] MAX Duty = 5156%(X100), DQS PI = 30
7450 16:30:43.790730 [0] MIN Duty = 4906%(X100), DQS PI = 10
7451 16:30:43.793906 [0] AVG Duty = 5031%(X100)
7452 16:30:43.794380
7453 16:30:43.794815 ==DQ 1 ==
7454 16:30:43.797530 Final DQ duty delay cell = 0
7455 16:30:43.800673 [0] MAX Duty = 5125%(X100), DQS PI = 8
7456 16:30:43.803815 [0] MIN Duty = 4938%(X100), DQS PI = 60
7457 16:30:43.807120 [0] AVG Duty = 5031%(X100)
7458 16:30:43.807623
7459 16:30:43.810220 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7460 16:30:43.810655
7461 16:30:43.813986 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7462 16:30:43.816953 [DutyScan_Calibration_Flow] ====Done====
7463 16:30:43.820034 nWR fixed to 30
7464 16:30:43.823257 [ModeRegInit_LP4] CH0 RK0
7465 16:30:43.823707 [ModeRegInit_LP4] CH0 RK1
7466 16:30:43.826998 [ModeRegInit_LP4] CH1 RK0
7467 16:30:43.830348 [ModeRegInit_LP4] CH1 RK1
7468 16:30:43.830785 match AC timing 5
7469 16:30:43.836470 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7470 16:30:43.839775 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7471 16:30:43.843397 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7472 16:30:43.849869 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7473 16:30:43.853121 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7474 16:30:43.853543 [MiockJmeterHQA]
7475 16:30:43.856212
7476 16:30:43.856635 [DramcMiockJmeter] u1RxGatingPI = 0
7477 16:30:43.859539 0 : 4365, 4140
7478 16:30:43.859990 4 : 4253, 4026
7479 16:30:43.863356 8 : 4366, 4139
7480 16:30:43.863788 12 : 4253, 4027
7481 16:30:43.866466 16 : 4257, 4032
7482 16:30:43.866928 20 : 4365, 4140
7483 16:30:43.869476 24 : 4250, 4027
7484 16:30:43.869915 28 : 4364, 4137
7485 16:30:43.870553 32 : 4250, 4026
7486 16:30:43.872934 36 : 4250, 4027
7487 16:30:43.873372 40 : 4252, 4029
7488 16:30:43.876262 44 : 4252, 4027
7489 16:30:43.876701 48 : 4363, 4140
7490 16:30:43.879612 52 : 4361, 4137
7491 16:30:43.880060 56 : 4252, 4029
7492 16:30:43.882555 60 : 4252, 4029
7493 16:30:43.882998 64 : 4361, 4137
7494 16:30:43.883576 68 : 4250, 4027
7495 16:30:43.886269 72 : 4363, 4140
7496 16:30:43.886708 76 : 4255, 4029
7497 16:30:43.889446 80 : 4250, 4026
7498 16:30:43.889883 84 : 4250, 4026
7499 16:30:43.892556 88 : 4253, 4029
7500 16:30:43.892992 92 : 4361, 520
7501 16:30:43.893435 96 : 4253, 0
7502 16:30:43.895822 100 : 4252, 0
7503 16:30:43.896279 104 : 4361, 0
7504 16:30:43.899600 108 : 4360, 0
7505 16:30:43.900026 112 : 4250, 0
7506 16:30:43.900365 116 : 4360, 0
7507 16:30:43.902252 120 : 4250, 0
7508 16:30:43.902699 124 : 4253, 0
7509 16:30:43.905969 128 : 4250, 0
7510 16:30:43.906455 132 : 4255, 0
7511 16:30:43.906926 136 : 4253, 0
7512 16:30:43.909281 140 : 4250, 0
7513 16:30:43.909816 144 : 4250, 0
7514 16:30:43.912349 148 : 4252, 0
7515 16:30:43.912789 152 : 4360, 0
7516 16:30:43.913226 156 : 4253, 0
7517 16:30:43.916288 160 : 4250, 0
7518 16:30:43.916860 164 : 4255, 0
7519 16:30:43.919120 168 : 4361, 0
7520 16:30:43.919559 172 : 4252, 0
7521 16:30:43.920001 176 : 4250, 0
7522 16:30:43.922159 180 : 4250, 0
7523 16:30:43.922758 184 : 4250, 0
7524 16:30:43.923259 188 : 4252, 0
7525 16:30:43.925399 192 : 4250, 0
7526 16:30:43.925858 196 : 4250, 0
7527 16:30:43.928512 200 : 4254, 0
7528 16:30:43.929048 204 : 4360, 0
7529 16:30:43.929455 208 : 4360, 0
7530 16:30:43.932116 212 : 4249, 0
7531 16:30:43.932585 216 : 4250, 0
7532 16:30:43.935463 220 : 4361, 0
7533 16:30:43.935966 224 : 4249, 58
7534 16:30:43.938757 228 : 4250, 2646
7535 16:30:43.939188 232 : 4250, 4027
7536 16:30:43.939546 236 : 4250, 4027
7537 16:30:43.941672 240 : 4363, 4140
7538 16:30:43.942228 244 : 4361, 4137
7539 16:30:43.945353 248 : 4250, 4027
7540 16:30:43.945789 252 : 4250, 4027
7541 16:30:43.948807 256 : 4252, 4029
7542 16:30:43.949246 260 : 4250, 4026
7543 16:30:43.951933 264 : 4250, 4027
7544 16:30:43.952372 268 : 4252, 4030
7545 16:30:43.954881 272 : 4250, 4027
7546 16:30:43.955399 276 : 4363, 4140
7547 16:30:43.958392 280 : 4250, 4027
7548 16:30:43.958987 284 : 4250, 4027
7549 16:30:43.961844 288 : 4250, 4027
7550 16:30:43.962422 292 : 4363, 4140
7551 16:30:43.965306 296 : 4361, 4137
7552 16:30:43.965726 300 : 4247, 4024
7553 16:30:43.966065 304 : 4363, 4140
7554 16:30:43.968314 308 : 4252, 4029
7555 16:30:43.968764 312 : 4250, 4026
7556 16:30:43.971473 316 : 4250, 4026
7557 16:30:43.971895 320 : 4249, 4027
7558 16:30:43.974746 324 : 4252, 4029
7559 16:30:43.975266 328 : 4250, 4026
7560 16:30:43.978545 332 : 4250, 4026
7561 16:30:43.979022 336 : 4252, 3974
7562 16:30:43.981290 340 : 4250, 2265
7563 16:30:43.981657 344 : 4361, 60
7564 16:30:43.982036
7565 16:30:43.984409 MIOCK jitter meter ch=0
7566 16:30:43.984848
7567 16:30:43.988043 1T = (344-92) = 252 dly cells
7568 16:30:43.991304 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7569 16:30:43.994334 ==
7570 16:30:43.997672 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 16:30:44.001403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 16:30:44.001819 ==
7573 16:30:44.004450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7574 16:30:44.011068 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7575 16:30:44.014489 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7576 16:30:44.020754 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7577 16:30:44.029574 [CA 0] Center 43 (12~74) winsize 63
7578 16:30:44.032675 [CA 1] Center 42 (12~73) winsize 62
7579 16:30:44.035843 [CA 2] Center 38 (9~68) winsize 60
7580 16:30:44.039065 [CA 3] Center 38 (9~68) winsize 60
7581 16:30:44.042265 [CA 4] Center 36 (7~66) winsize 60
7582 16:30:44.046068 [CA 5] Center 35 (6~65) winsize 60
7583 16:30:44.046561
7584 16:30:44.048996 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7585 16:30:44.049426
7586 16:30:44.052724 [CATrainingPosCal] consider 1 rank data
7587 16:30:44.055969 u2DelayCellTimex100 = 258/100 ps
7588 16:30:44.062407 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7589 16:30:44.065632 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7590 16:30:44.068965 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7591 16:30:44.072563 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7592 16:30:44.075634 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7593 16:30:44.078784 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7594 16:30:44.079202
7595 16:30:44.082059 CA PerBit enable=1, Macro0, CA PI delay=35
7596 16:30:44.082523
7597 16:30:44.085883 [CBTSetCACLKResult] CA Dly = 35
7598 16:30:44.088727 CS Dly: 12 (0~43)
7599 16:30:44.092452 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7600 16:30:44.095160 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7601 16:30:44.095584 ==
7602 16:30:44.099014 Dram Type= 6, Freq= 0, CH_0, rank 1
7603 16:30:44.105370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 16:30:44.105810 ==
7605 16:30:44.108631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7606 16:30:44.115591 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7607 16:30:44.118803 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7608 16:30:44.125081 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7609 16:30:44.135882 [CA 0] Center 42 (12~73) winsize 62
7610 16:30:44.136318 [CA 1] Center 43 (13~73) winsize 61
7611 16:30:44.139152 [CA 2] Center 37 (8~67) winsize 60
7612 16:30:44.142479 [CA 3] Center 37 (7~67) winsize 61
7613 16:30:44.145665 [CA 4] Center 35 (6~65) winsize 60
7614 16:30:44.149371 [CA 5] Center 35 (5~66) winsize 62
7615 16:30:44.149817
7616 16:30:44.152352 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7617 16:30:44.152769
7618 16:30:44.159330 [CATrainingPosCal] consider 2 rank data
7619 16:30:44.159750 u2DelayCellTimex100 = 258/100 ps
7620 16:30:44.165831 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7621 16:30:44.168963 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7622 16:30:44.172003 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7623 16:30:44.175700 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7624 16:30:44.178733 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7625 16:30:44.182121 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7626 16:30:44.182586
7627 16:30:44.185671 CA PerBit enable=1, Macro0, CA PI delay=35
7628 16:30:44.186220
7629 16:30:44.189270 [CBTSetCACLKResult] CA Dly = 35
7630 16:30:44.192116 CS Dly: 12 (0~44)
7631 16:30:44.195163 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7632 16:30:44.198333 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7633 16:30:44.198752
7634 16:30:44.202325 ----->DramcWriteLeveling(PI) begin...
7635 16:30:44.202750 ==
7636 16:30:44.205151 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 16:30:44.212072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 16:30:44.212507 ==
7639 16:30:44.215167 Write leveling (Byte 0): 34 => 34
7640 16:30:44.218897 Write leveling (Byte 1): 26 => 26
7641 16:30:44.222220 DramcWriteLeveling(PI) end<-----
7642 16:30:44.222655
7643 16:30:44.223087 ==
7644 16:30:44.225224 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 16:30:44.228551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 16:30:44.228983 ==
7647 16:30:44.231533 [Gating] SW mode calibration
7648 16:30:44.238511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7649 16:30:44.244888 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7650 16:30:44.248277 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 16:30:44.251446 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 16:30:44.258246 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 16:30:44.261276 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7654 16:30:44.264482 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7655 16:30:44.270814 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7656 16:30:44.273916 1 4 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7657 16:30:44.277551 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 16:30:44.284016 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 16:30:44.287223 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 16:30:44.290790 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 16:30:44.297145 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7662 16:30:44.300168 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7663 16:30:44.303864 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7664 16:30:44.310074 1 5 24 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7665 16:30:44.313896 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 16:30:44.316888 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 16:30:44.323662 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 16:30:44.326569 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7669 16:30:44.330025 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7670 16:30:44.336856 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7671 16:30:44.340069 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7672 16:30:44.343201 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7673 16:30:44.349710 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 16:30:44.353527 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 16:30:44.356646 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 16:30:44.363384 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7677 16:30:44.366509 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7678 16:30:44.369625 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7679 16:30:44.376109 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7680 16:30:44.379612 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 16:30:44.383139 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 16:30:44.389509 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 16:30:44.393267 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 16:30:44.396442 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 16:30:44.403135 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 16:30:44.406471 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 16:30:44.409334 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 16:30:44.416367 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 16:30:44.419619 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 16:30:44.422727 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 16:30:44.429169 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 16:30:44.432273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 16:30:44.435710 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7694 16:30:44.439199 Total UI for P1: 0, mck2ui 16
7695 16:30:44.442423 best dqsien dly found for B0: ( 1, 9, 10)
7696 16:30:44.448768 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7697 16:30:44.452489 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7698 16:30:44.455852 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 16:30:44.459100 Total UI for P1: 0, mck2ui 16
7700 16:30:44.462219 best dqsien dly found for B1: ( 1, 9, 20)
7701 16:30:44.465283 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7702 16:30:44.468611 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7703 16:30:44.469011
7704 16:30:44.475531 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7705 16:30:44.478627 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7706 16:30:44.481868 [Gating] SW calibration Done
7707 16:30:44.482319 ==
7708 16:30:44.485501 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 16:30:44.488704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 16:30:44.489195 ==
7711 16:30:44.489567 RX Vref Scan: 0
7712 16:30:44.489878
7713 16:30:44.491815 RX Vref 0 -> 0, step: 1
7714 16:30:44.492270
7715 16:30:44.495066 RX Delay 0 -> 252, step: 8
7716 16:30:44.498298 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7717 16:30:44.501588 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7718 16:30:44.505272 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7719 16:30:44.511669 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7720 16:30:44.514818 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7721 16:30:44.518066 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7722 16:30:44.521384 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7723 16:30:44.524962 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7724 16:30:44.531653 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7725 16:30:44.534652 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7726 16:30:44.537781 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7727 16:30:44.541147 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7728 16:30:44.548253 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7729 16:30:44.551333 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7730 16:30:44.554437 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7731 16:30:44.557861 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7732 16:30:44.558305 ==
7733 16:30:44.561350 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 16:30:44.567702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 16:30:44.568123 ==
7736 16:30:44.568501 DQS Delay:
7737 16:30:44.568846 DQS0 = 0, DQS1 = 0
7738 16:30:44.571145 DQM Delay:
7739 16:30:44.571772 DQM0 = 136, DQM1 = 126
7740 16:30:44.574247 DQ Delay:
7741 16:30:44.577602 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7742 16:30:44.581214 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7743 16:30:44.584446 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7744 16:30:44.587668 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7745 16:30:44.588118
7746 16:30:44.588451
7747 16:30:44.588755 ==
7748 16:30:44.590405 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 16:30:44.597615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 16:30:44.598034 ==
7751 16:30:44.598417
7752 16:30:44.598725
7753 16:30:44.599015 TX Vref Scan disable
7754 16:30:44.600721 == TX Byte 0 ==
7755 16:30:44.603900 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7756 16:30:44.610507 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7757 16:30:44.610923 == TX Byte 1 ==
7758 16:30:44.613721 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7759 16:30:44.620533 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7760 16:30:44.621055 ==
7761 16:30:44.623868 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 16:30:44.626770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 16:30:44.627192 ==
7764 16:30:44.640043
7765 16:30:44.643270 TX Vref early break, caculate TX vref
7766 16:30:44.646357 TX Vref=16, minBit 8, minWin=22, winSum=371
7767 16:30:44.650270 TX Vref=18, minBit 1, minWin=23, winSum=378
7768 16:30:44.653354 TX Vref=20, minBit 6, minWin=23, winSum=391
7769 16:30:44.656523 TX Vref=22, minBit 3, minWin=24, winSum=400
7770 16:30:44.659515 TX Vref=24, minBit 5, minWin=24, winSum=407
7771 16:30:44.666637 TX Vref=26, minBit 1, minWin=25, winSum=415
7772 16:30:44.669732 TX Vref=28, minBit 0, minWin=25, winSum=418
7773 16:30:44.672788 TX Vref=30, minBit 4, minWin=24, winSum=407
7774 16:30:44.676307 TX Vref=32, minBit 5, minWin=24, winSum=404
7775 16:30:44.679354 TX Vref=34, minBit 4, minWin=23, winSum=391
7776 16:30:44.686136 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7777 16:30:44.686601
7778 16:30:44.689167 Final TX Range 0 Vref 28
7779 16:30:44.689677
7780 16:30:44.690016 ==
7781 16:30:44.692645 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 16:30:44.695595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 16:30:44.696031 ==
7784 16:30:44.696358
7785 16:30:44.698982
7786 16:30:44.699393 TX Vref Scan disable
7787 16:30:44.705536 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7788 16:30:44.705951 == TX Byte 0 ==
7789 16:30:44.708786 u2DelayCellOfst[0]=15 cells (4 PI)
7790 16:30:44.713055 u2DelayCellOfst[1]=18 cells (5 PI)
7791 16:30:44.715903 u2DelayCellOfst[2]=15 cells (4 PI)
7792 16:30:44.719329 u2DelayCellOfst[3]=15 cells (4 PI)
7793 16:30:44.722327 u2DelayCellOfst[4]=11 cells (3 PI)
7794 16:30:44.725637 u2DelayCellOfst[5]=0 cells (0 PI)
7795 16:30:44.728836 u2DelayCellOfst[6]=18 cells (5 PI)
7796 16:30:44.732380 u2DelayCellOfst[7]=22 cells (6 PI)
7797 16:30:44.735430 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7798 16:30:44.738623 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7799 16:30:44.741763 == TX Byte 1 ==
7800 16:30:44.744932 u2DelayCellOfst[8]=0 cells (0 PI)
7801 16:30:44.748235 u2DelayCellOfst[9]=3 cells (1 PI)
7802 16:30:44.751526 u2DelayCellOfst[10]=7 cells (2 PI)
7803 16:30:44.754846 u2DelayCellOfst[11]=3 cells (1 PI)
7804 16:30:44.758009 u2DelayCellOfst[12]=15 cells (4 PI)
7805 16:30:44.762002 u2DelayCellOfst[13]=15 cells (4 PI)
7806 16:30:44.765009 u2DelayCellOfst[14]=15 cells (4 PI)
7807 16:30:44.768107 u2DelayCellOfst[15]=11 cells (3 PI)
7808 16:30:44.771441 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7809 16:30:44.774602 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7810 16:30:44.777798 DramC Write-DBI on
7811 16:30:44.778289 ==
7812 16:30:44.781586 Dram Type= 6, Freq= 0, CH_0, rank 0
7813 16:30:44.784586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7814 16:30:44.785194 ==
7815 16:30:44.785604
7816 16:30:44.785924
7817 16:30:44.787699 TX Vref Scan disable
7818 16:30:44.791023 == TX Byte 0 ==
7819 16:30:44.794761 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7820 16:30:44.795188 == TX Byte 1 ==
7821 16:30:44.801192 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7822 16:30:44.801872 DramC Write-DBI off
7823 16:30:44.802396
7824 16:30:44.802731 [DATLAT]
7825 16:30:44.804297 Freq=1600, CH0 RK0
7826 16:30:44.804717
7827 16:30:44.807798 DATLAT Default: 0xf
7828 16:30:44.808401 0, 0xFFFF, sum = 0
7829 16:30:44.810506 1, 0xFFFF, sum = 0
7830 16:30:44.811060 2, 0xFFFF, sum = 0
7831 16:30:44.814281 3, 0xFFFF, sum = 0
7832 16:30:44.814804 4, 0xFFFF, sum = 0
7833 16:30:44.817165 5, 0xFFFF, sum = 0
7834 16:30:44.817586 6, 0xFFFF, sum = 0
7835 16:30:44.820819 7, 0xFFFF, sum = 0
7836 16:30:44.821245 8, 0xFFFF, sum = 0
7837 16:30:44.824018 9, 0xFFFF, sum = 0
7838 16:30:44.824465 10, 0xFFFF, sum = 0
7839 16:30:44.827887 11, 0xFFFF, sum = 0
7840 16:30:44.828483 12, 0xFFFF, sum = 0
7841 16:30:44.830958 13, 0xFFFF, sum = 0
7842 16:30:44.831567 14, 0x0, sum = 1
7843 16:30:44.834112 15, 0x0, sum = 2
7844 16:30:44.834600 16, 0x0, sum = 3
7845 16:30:44.837159 17, 0x0, sum = 4
7846 16:30:44.837670 best_step = 15
7847 16:30:44.838010
7848 16:30:44.838366 ==
7849 16:30:44.840898 Dram Type= 6, Freq= 0, CH_0, rank 0
7850 16:30:44.847098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7851 16:30:44.847651 ==
7852 16:30:44.848154 RX Vref Scan: 1
7853 16:30:44.848625
7854 16:30:44.850306 Set Vref Range= 24 -> 127
7855 16:30:44.850815
7856 16:30:44.854069 RX Vref 24 -> 127, step: 1
7857 16:30:44.854550
7858 16:30:44.857242 RX Delay 19 -> 252, step: 4
7859 16:30:44.857663
7860 16:30:44.860478 Set Vref, RX VrefLevel [Byte0]: 24
7861 16:30:44.863708 [Byte1]: 24
7862 16:30:44.864127
7863 16:30:44.867151 Set Vref, RX VrefLevel [Byte0]: 25
7864 16:30:44.870139 [Byte1]: 25
7865 16:30:44.870598
7866 16:30:44.873229 Set Vref, RX VrefLevel [Byte0]: 26
7867 16:30:44.877207 [Byte1]: 26
7868 16:30:44.877727
7869 16:30:44.880336 Set Vref, RX VrefLevel [Byte0]: 27
7870 16:30:44.883504 [Byte1]: 27
7871 16:30:44.887178
7872 16:30:44.887603 Set Vref, RX VrefLevel [Byte0]: 28
7873 16:30:44.890933 [Byte1]: 28
7874 16:30:44.894762
7875 16:30:44.895182 Set Vref, RX VrefLevel [Byte0]: 29
7876 16:30:44.898102 [Byte1]: 29
7877 16:30:44.902581
7878 16:30:44.903265 Set Vref, RX VrefLevel [Byte0]: 30
7879 16:30:44.906025 [Byte1]: 30
7880 16:30:44.910311
7881 16:30:44.910749 Set Vref, RX VrefLevel [Byte0]: 31
7882 16:30:44.913513 [Byte1]: 31
7883 16:30:44.917884
7884 16:30:44.918338 Set Vref, RX VrefLevel [Byte0]: 32
7885 16:30:44.920724 [Byte1]: 32
7886 16:30:44.925319
7887 16:30:44.925738 Set Vref, RX VrefLevel [Byte0]: 33
7888 16:30:44.928843 [Byte1]: 33
7889 16:30:44.933040
7890 16:30:44.933627 Set Vref, RX VrefLevel [Byte0]: 34
7891 16:30:44.936298 [Byte1]: 34
7892 16:30:44.940524
7893 16:30:44.940953 Set Vref, RX VrefLevel [Byte0]: 35
7894 16:30:44.943791 [Byte1]: 35
7895 16:30:44.948243
7896 16:30:44.948658 Set Vref, RX VrefLevel [Byte0]: 36
7897 16:30:44.951313 [Byte1]: 36
7898 16:30:44.955955
7899 16:30:44.956373 Set Vref, RX VrefLevel [Byte0]: 37
7900 16:30:44.959062 [Byte1]: 37
7901 16:30:44.963066
7902 16:30:44.963535 Set Vref, RX VrefLevel [Byte0]: 38
7903 16:30:44.966717 [Byte1]: 38
7904 16:30:44.971129
7905 16:30:44.971735 Set Vref, RX VrefLevel [Byte0]: 39
7906 16:30:44.973839 [Byte1]: 39
7907 16:30:44.978604
7908 16:30:44.979241 Set Vref, RX VrefLevel [Byte0]: 40
7909 16:30:44.981479 [Byte1]: 40
7910 16:30:44.986123
7911 16:30:44.986652 Set Vref, RX VrefLevel [Byte0]: 41
7912 16:30:44.989307 [Byte1]: 41
7913 16:30:44.993504
7914 16:30:44.993944 Set Vref, RX VrefLevel [Byte0]: 42
7915 16:30:44.996845 [Byte1]: 42
7916 16:30:45.001069
7917 16:30:45.001623 Set Vref, RX VrefLevel [Byte0]: 43
7918 16:30:45.004317 [Byte1]: 43
7919 16:30:45.008554
7920 16:30:45.008974 Set Vref, RX VrefLevel [Byte0]: 44
7921 16:30:45.012174 [Byte1]: 44
7922 16:30:45.016255
7923 16:30:45.016779 Set Vref, RX VrefLevel [Byte0]: 45
7924 16:30:45.019890 [Byte1]: 45
7925 16:30:45.023768
7926 16:30:45.024190 Set Vref, RX VrefLevel [Byte0]: 46
7927 16:30:45.026853 [Byte1]: 46
7928 16:30:45.031846
7929 16:30:45.032357 Set Vref, RX VrefLevel [Byte0]: 47
7930 16:30:45.034630 [Byte1]: 47
7931 16:30:45.038861
7932 16:30:45.039400 Set Vref, RX VrefLevel [Byte0]: 48
7933 16:30:45.042297 [Byte1]: 48
7934 16:30:45.046640
7935 16:30:45.047227 Set Vref, RX VrefLevel [Byte0]: 49
7936 16:30:45.049890 [Byte1]: 49
7937 16:30:45.053813
7938 16:30:45.054308 Set Vref, RX VrefLevel [Byte0]: 50
7939 16:30:45.057666 [Byte1]: 50
7940 16:30:45.061485
7941 16:30:45.061927 Set Vref, RX VrefLevel [Byte0]: 51
7942 16:30:45.064652 [Byte1]: 51
7943 16:30:45.069041
7944 16:30:45.069464 Set Vref, RX VrefLevel [Byte0]: 52
7945 16:30:45.072442 [Byte1]: 52
7946 16:30:45.076652
7947 16:30:45.077076 Set Vref, RX VrefLevel [Byte0]: 53
7948 16:30:45.080232 [Byte1]: 53
7949 16:30:45.084244
7950 16:30:45.084705 Set Vref, RX VrefLevel [Byte0]: 54
7951 16:30:45.087645 [Byte1]: 54
7952 16:30:45.091706
7953 16:30:45.092129 Set Vref, RX VrefLevel [Byte0]: 55
7954 16:30:45.095005 [Byte1]: 55
7955 16:30:45.099278
7956 16:30:45.099736 Set Vref, RX VrefLevel [Byte0]: 56
7957 16:30:45.103128 [Byte1]: 56
7958 16:30:45.106774
7959 16:30:45.107199 Set Vref, RX VrefLevel [Byte0]: 57
7960 16:30:45.110147 [Byte1]: 57
7961 16:30:45.114708
7962 16:30:45.115131 Set Vref, RX VrefLevel [Byte0]: 58
7963 16:30:45.117714 [Byte1]: 58
7964 16:30:45.121993
7965 16:30:45.125173 Set Vref, RX VrefLevel [Byte0]: 59
7966 16:30:45.128504 [Byte1]: 59
7967 16:30:45.128927
7968 16:30:45.132151 Set Vref, RX VrefLevel [Byte0]: 60
7969 16:30:45.135332 [Byte1]: 60
7970 16:30:45.135825
7971 16:30:45.138522 Set Vref, RX VrefLevel [Byte0]: 61
7972 16:30:45.142034 [Byte1]: 61
7973 16:30:45.142523
7974 16:30:45.144994 Set Vref, RX VrefLevel [Byte0]: 62
7975 16:30:45.148129 [Byte1]: 62
7976 16:30:45.152410
7977 16:30:45.152837 Set Vref, RX VrefLevel [Byte0]: 63
7978 16:30:45.156217 [Byte1]: 63
7979 16:30:45.160018
7980 16:30:45.160560 Set Vref, RX VrefLevel [Byte0]: 64
7981 16:30:45.163391 [Byte1]: 64
7982 16:30:45.167397
7983 16:30:45.167886 Set Vref, RX VrefLevel [Byte0]: 65
7984 16:30:45.171196 [Byte1]: 65
7985 16:30:45.175461
7986 16:30:45.175882 Set Vref, RX VrefLevel [Byte0]: 66
7987 16:30:45.178655 [Byte1]: 66
7988 16:30:45.182523
7989 16:30:45.182968 Set Vref, RX VrefLevel [Byte0]: 67
7990 16:30:45.185848 [Byte1]: 67
7991 16:30:45.190452
7992 16:30:45.190873 Set Vref, RX VrefLevel [Byte0]: 68
7993 16:30:45.193553 [Byte1]: 68
7994 16:30:45.198101
7995 16:30:45.198674 Set Vref, RX VrefLevel [Byte0]: 69
7996 16:30:45.201306 [Byte1]: 69
7997 16:30:45.205305
7998 16:30:45.205728 Set Vref, RX VrefLevel [Byte0]: 70
7999 16:30:45.208971 [Byte1]: 70
8000 16:30:45.212823
8001 16:30:45.213372 Set Vref, RX VrefLevel [Byte0]: 71
8002 16:30:45.216864 [Byte1]: 71
8003 16:30:45.220735
8004 16:30:45.221155 Set Vref, RX VrefLevel [Byte0]: 72
8005 16:30:45.223798 [Byte1]: 72
8006 16:30:45.227958
8007 16:30:45.228379 Set Vref, RX VrefLevel [Byte0]: 73
8008 16:30:45.231749 [Byte1]: 73
8009 16:30:45.235759
8010 16:30:45.236178 Set Vref, RX VrefLevel [Byte0]: 74
8011 16:30:45.239014 [Byte1]: 74
8012 16:30:45.243323
8013 16:30:45.243772 Set Vref, RX VrefLevel [Byte0]: 75
8014 16:30:45.246314 [Byte1]: 75
8015 16:30:45.250616
8016 16:30:45.251051 Set Vref, RX VrefLevel [Byte0]: 76
8017 16:30:45.254139 [Byte1]: 76
8018 16:30:45.258573
8019 16:30:45.259197 Set Vref, RX VrefLevel [Byte0]: 77
8020 16:30:45.261673 [Byte1]: 77
8021 16:30:45.265956
8022 16:30:45.266599 Set Vref, RX VrefLevel [Byte0]: 78
8023 16:30:45.269321 [Byte1]: 78
8024 16:30:45.273519
8025 16:30:45.274126 Final RX Vref Byte 0 = 65 to rank0
8026 16:30:45.276785 Final RX Vref Byte 1 = 60 to rank0
8027 16:30:45.280503 Final RX Vref Byte 0 = 65 to rank1
8028 16:30:45.283616 Final RX Vref Byte 1 = 60 to rank1==
8029 16:30:45.286896 Dram Type= 6, Freq= 0, CH_0, rank 0
8030 16:30:45.293548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 16:30:45.294225 ==
8032 16:30:45.294685 DQS Delay:
8033 16:30:45.296682 DQS0 = 0, DQS1 = 0
8034 16:30:45.297275 DQM Delay:
8035 16:30:45.299739 DQM0 = 133, DQM1 = 122
8036 16:30:45.300380 DQ Delay:
8037 16:30:45.303009 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8038 16:30:45.306369 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8039 16:30:45.309946 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118
8040 16:30:45.313285 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8041 16:30:45.313703
8042 16:30:45.314028
8043 16:30:45.314390
8044 16:30:45.316264 [DramC_TX_OE_Calibration] TA2
8045 16:30:45.319284 Original DQ_B0 (3 6) =30, OEN = 27
8046 16:30:45.322586 Original DQ_B1 (3 6) =30, OEN = 27
8047 16:30:45.326255 24, 0x0, End_B0=24 End_B1=24
8048 16:30:45.329298 25, 0x0, End_B0=25 End_B1=25
8049 16:30:45.329827 26, 0x0, End_B0=26 End_B1=26
8050 16:30:45.332319 27, 0x0, End_B0=27 End_B1=27
8051 16:30:45.336027 28, 0x0, End_B0=28 End_B1=28
8052 16:30:45.339392 29, 0x0, End_B0=29 End_B1=29
8053 16:30:45.342427 30, 0x0, End_B0=30 End_B1=30
8054 16:30:45.342849 31, 0x4141, End_B0=30 End_B1=30
8055 16:30:45.345714 Byte0 end_step=30 best_step=27
8056 16:30:45.349345 Byte1 end_step=30 best_step=27
8057 16:30:45.352527 Byte0 TX OE(2T, 0.5T) = (3, 3)
8058 16:30:45.355608 Byte1 TX OE(2T, 0.5T) = (3, 3)
8059 16:30:45.356183
8060 16:30:45.356683
8061 16:30:45.362278 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8062 16:30:45.365302 CH0 RK0: MR19=303, MR18=2415
8063 16:30:45.371769 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8064 16:30:45.372192
8065 16:30:45.375341 ----->DramcWriteLeveling(PI) begin...
8066 16:30:45.375764 ==
8067 16:30:45.378959 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 16:30:45.382110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 16:30:45.385317 ==
8070 16:30:45.385735 Write leveling (Byte 0): 36 => 36
8071 16:30:45.388417 Write leveling (Byte 1): 27 => 27
8072 16:30:45.392190 DramcWriteLeveling(PI) end<-----
8073 16:30:45.392609
8074 16:30:45.392937 ==
8075 16:30:45.395307 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 16:30:45.401443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 16:30:45.401865 ==
8078 16:30:45.405492 [Gating] SW mode calibration
8079 16:30:45.411945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8080 16:30:45.415128 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8081 16:30:45.421530 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 16:30:45.425063 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 16:30:45.428370 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 16:30:45.435008 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8085 16:30:45.438196 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8086 16:30:45.441563 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8087 16:30:45.448220 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 16:30:45.451278 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 16:30:45.454403 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 16:30:45.461518 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8091 16:30:45.464644 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8092 16:30:45.467561 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8093 16:30:45.474047 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
8094 16:30:45.477290 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
8095 16:30:45.481213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 16:30:45.487821 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 16:30:45.491048 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 16:30:45.494112 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 16:30:45.501024 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 16:30:45.504303 1 6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8101 16:30:45.507406 1 6 16 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
8102 16:30:45.513756 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8103 16:30:45.516968 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 16:30:45.520299 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 16:30:45.527378 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 16:30:45.530553 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 16:30:45.533687 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 16:30:45.539963 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8109 16:30:45.543557 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8110 16:30:45.546942 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8111 16:30:45.553404 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 16:30:45.556424 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 16:30:45.559721 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 16:30:45.566753 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 16:30:45.569887 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 16:30:45.572769 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 16:30:45.579491 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 16:30:45.582671 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 16:30:45.585904 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 16:30:45.593034 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 16:30:45.596043 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 16:30:45.599336 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 16:30:45.606240 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8124 16:30:45.609435 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8125 16:30:45.612619 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8126 16:30:45.615874 Total UI for P1: 0, mck2ui 16
8127 16:30:45.619756 best dqsien dly found for B0: ( 1, 9, 10)
8128 16:30:45.626326 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 16:30:45.629857 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 16:30:45.632766 Total UI for P1: 0, mck2ui 16
8131 16:30:45.635993 best dqsien dly found for B1: ( 1, 9, 18)
8132 16:30:45.639112 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8133 16:30:45.642156 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8134 16:30:45.642615
8135 16:30:45.645361 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8136 16:30:45.649252 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8137 16:30:45.652527 [Gating] SW calibration Done
8138 16:30:45.653103 ==
8139 16:30:45.655647 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 16:30:45.661959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 16:30:45.662656 ==
8142 16:30:45.663204 RX Vref Scan: 0
8143 16:30:45.663684
8144 16:30:45.665471 RX Vref 0 -> 0, step: 1
8145 16:30:45.665914
8146 16:30:45.668792 RX Delay 0 -> 252, step: 8
8147 16:30:45.671791 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8148 16:30:45.675345 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8149 16:30:45.678657 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8150 16:30:45.681997 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8151 16:30:45.688283 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8152 16:30:45.691619 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8153 16:30:45.695027 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8154 16:30:45.698075 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8155 16:30:45.701441 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8156 16:30:45.708372 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8157 16:30:45.711561 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8158 16:30:45.714850 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8159 16:30:45.718034 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8160 16:30:45.724354 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8161 16:30:45.728631 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8162 16:30:45.731637 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8163 16:30:45.732160 ==
8164 16:30:45.734221 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 16:30:45.738101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 16:30:45.738565 ==
8167 16:30:45.741516 DQS Delay:
8168 16:30:45.742030 DQS0 = 0, DQS1 = 0
8169 16:30:45.744245 DQM Delay:
8170 16:30:45.744661 DQM0 = 132, DQM1 = 128
8171 16:30:45.747324 DQ Delay:
8172 16:30:45.751181 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8173 16:30:45.754380 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8174 16:30:45.757562 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8175 16:30:45.760837 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8176 16:30:45.761279
8177 16:30:45.761607
8178 16:30:45.761911 ==
8179 16:30:45.764584 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 16:30:45.767713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 16:30:45.768132 ==
8182 16:30:45.768461
8183 16:30:45.770628
8184 16:30:45.771040 TX Vref Scan disable
8185 16:30:45.774122 == TX Byte 0 ==
8186 16:30:45.777298 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8187 16:30:45.780389 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8188 16:30:45.783709 == TX Byte 1 ==
8189 16:30:45.787418 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8190 16:30:45.790488 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8191 16:30:45.790915 ==
8192 16:30:45.793463 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 16:30:45.800573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 16:30:45.800998 ==
8195 16:30:45.812802
8196 16:30:45.816080 TX Vref early break, caculate TX vref
8197 16:30:45.819764 TX Vref=16, minBit 1, minWin=22, winSum=373
8198 16:30:45.822850 TX Vref=18, minBit 0, minWin=23, winSum=386
8199 16:30:45.826617 TX Vref=20, minBit 1, minWin=23, winSum=390
8200 16:30:45.829223 TX Vref=22, minBit 2, minWin=24, winSum=401
8201 16:30:45.832392 TX Vref=24, minBit 1, minWin=24, winSum=408
8202 16:30:45.839338 TX Vref=26, minBit 4, minWin=24, winSum=411
8203 16:30:45.842493 TX Vref=28, minBit 0, minWin=24, winSum=407
8204 16:30:45.846255 TX Vref=30, minBit 0, minWin=24, winSum=399
8205 16:30:45.849218 TX Vref=32, minBit 0, minWin=23, winSum=392
8206 16:30:45.852536 TX Vref=34, minBit 4, minWin=23, winSum=386
8207 16:30:45.859636 [TxChooseVref] Worse bit 4, Min win 24, Win sum 411, Final Vref 26
8208 16:30:45.860064
8209 16:30:45.862701 Final TX Range 0 Vref 26
8210 16:30:45.863157
8211 16:30:45.863515 ==
8212 16:30:45.866031 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 16:30:45.869198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 16:30:45.869623 ==
8215 16:30:45.869976
8216 16:30:45.870449
8217 16:30:45.872206 TX Vref Scan disable
8218 16:30:45.879065 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8219 16:30:45.879511 == TX Byte 0 ==
8220 16:30:45.882347 u2DelayCellOfst[0]=11 cells (3 PI)
8221 16:30:45.885453 u2DelayCellOfst[1]=15 cells (4 PI)
8222 16:30:45.888538 u2DelayCellOfst[2]=11 cells (3 PI)
8223 16:30:45.892248 u2DelayCellOfst[3]=11 cells (3 PI)
8224 16:30:45.895543 u2DelayCellOfst[4]=7 cells (2 PI)
8225 16:30:45.898674 u2DelayCellOfst[5]=0 cells (0 PI)
8226 16:30:45.901699 u2DelayCellOfst[6]=15 cells (4 PI)
8227 16:30:45.905364 u2DelayCellOfst[7]=15 cells (4 PI)
8228 16:30:45.908413 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8229 16:30:45.911586 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8230 16:30:45.914831 == TX Byte 1 ==
8231 16:30:45.917961 u2DelayCellOfst[8]=0 cells (0 PI)
8232 16:30:45.921545 u2DelayCellOfst[9]=0 cells (0 PI)
8233 16:30:45.924508 u2DelayCellOfst[10]=7 cells (2 PI)
8234 16:30:45.928175 u2DelayCellOfst[11]=3 cells (1 PI)
8235 16:30:45.931342 u2DelayCellOfst[12]=11 cells (3 PI)
8236 16:30:45.931859 u2DelayCellOfst[13]=11 cells (3 PI)
8237 16:30:45.934394 u2DelayCellOfst[14]=15 cells (4 PI)
8238 16:30:45.938268 u2DelayCellOfst[15]=11 cells (3 PI)
8239 16:30:45.944328 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8240 16:30:45.948223 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8241 16:30:45.948668 DramC Write-DBI on
8242 16:30:45.951320 ==
8243 16:30:45.954284 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 16:30:45.958016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 16:30:45.958660 ==
8246 16:30:45.959151
8247 16:30:45.959650
8248 16:30:45.961181 TX Vref Scan disable
8249 16:30:45.961737 == TX Byte 0 ==
8250 16:30:45.967751 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8251 16:30:45.968348 == TX Byte 1 ==
8252 16:30:45.970948 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8253 16:30:45.974190 DramC Write-DBI off
8254 16:30:45.974739
8255 16:30:45.975253 [DATLAT]
8256 16:30:45.977822 Freq=1600, CH0 RK1
8257 16:30:45.978454
8258 16:30:45.978972 DATLAT Default: 0xf
8259 16:30:45.980869 0, 0xFFFF, sum = 0
8260 16:30:45.981383 1, 0xFFFF, sum = 0
8261 16:30:45.984227 2, 0xFFFF, sum = 0
8262 16:30:45.984818 3, 0xFFFF, sum = 0
8263 16:30:45.988065 4, 0xFFFF, sum = 0
8264 16:30:45.988581 5, 0xFFFF, sum = 0
8265 16:30:45.991249 6, 0xFFFF, sum = 0
8266 16:30:45.994570 7, 0xFFFF, sum = 0
8267 16:30:45.994989 8, 0xFFFF, sum = 0
8268 16:30:45.997542 9, 0xFFFF, sum = 0
8269 16:30:45.997964 10, 0xFFFF, sum = 0
8270 16:30:46.000740 11, 0xFFFF, sum = 0
8271 16:30:46.001317 12, 0xFFFF, sum = 0
8272 16:30:46.004117 13, 0xFFFF, sum = 0
8273 16:30:46.004555 14, 0x0, sum = 1
8274 16:30:46.007621 15, 0x0, sum = 2
8275 16:30:46.008070 16, 0x0, sum = 3
8276 16:30:46.011082 17, 0x0, sum = 4
8277 16:30:46.011527 best_step = 15
8278 16:30:46.011861
8279 16:30:46.012170 ==
8280 16:30:46.014390 Dram Type= 6, Freq= 0, CH_0, rank 1
8281 16:30:46.017426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 16:30:46.020917 ==
8283 16:30:46.021570 RX Vref Scan: 0
8284 16:30:46.022069
8285 16:30:46.023812 RX Vref 0 -> 0, step: 1
8286 16:30:46.024244
8287 16:30:46.024716 RX Delay 11 -> 252, step: 4
8288 16:30:46.031150 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8289 16:30:46.035151 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8290 16:30:46.038147 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8291 16:30:46.041153 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8292 16:30:46.044609 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8293 16:30:46.051358 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8294 16:30:46.054600 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8295 16:30:46.057884 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8296 16:30:46.061226 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8297 16:30:46.064512 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8298 16:30:46.071105 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8299 16:30:46.074222 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8300 16:30:46.077441 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8301 16:30:46.080645 iDelay=195, Bit 13, Center 130 (79 ~ 182) 104
8302 16:30:46.087607 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8303 16:30:46.090696 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8304 16:30:46.091119 ==
8305 16:30:46.093895 Dram Type= 6, Freq= 0, CH_0, rank 1
8306 16:30:46.097169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 16:30:46.097591 ==
8308 16:30:46.100890 DQS Delay:
8309 16:30:46.101438 DQS0 = 0, DQS1 = 0
8310 16:30:46.101908 DQM Delay:
8311 16:30:46.104305 DQM0 = 130, DQM1 = 125
8312 16:30:46.104866 DQ Delay:
8313 16:30:46.107419 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8314 16:30:46.110451 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8315 16:30:46.116788 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8316 16:30:46.120840 DQ12 =130, DQ13 =130, DQ14 =136, DQ15 =132
8317 16:30:46.121258
8318 16:30:46.121583
8319 16:30:46.121888
8320 16:30:46.123838 [DramC_TX_OE_Calibration] TA2
8321 16:30:46.127397 Original DQ_B0 (3 6) =30, OEN = 27
8322 16:30:46.130185 Original DQ_B1 (3 6) =30, OEN = 27
8323 16:30:46.130782 24, 0x0, End_B0=24 End_B1=24
8324 16:30:46.133873 25, 0x0, End_B0=25 End_B1=25
8325 16:30:46.136904 26, 0x0, End_B0=26 End_B1=26
8326 16:30:46.139933 27, 0x0, End_B0=27 End_B1=27
8327 16:30:46.140360 28, 0x0, End_B0=28 End_B1=28
8328 16:30:46.144097 29, 0x0, End_B0=29 End_B1=29
8329 16:30:46.147095 30, 0x0, End_B0=30 End_B1=30
8330 16:30:46.150122 31, 0x4141, End_B0=30 End_B1=30
8331 16:30:46.153229 Byte0 end_step=30 best_step=27
8332 16:30:46.157004 Byte1 end_step=30 best_step=27
8333 16:30:46.157531 Byte0 TX OE(2T, 0.5T) = (3, 3)
8334 16:30:46.159922 Byte1 TX OE(2T, 0.5T) = (3, 3)
8335 16:30:46.160357
8336 16:30:46.160878
8337 16:30:46.169570 [DQSOSCAuto] RK1, (LSB)MR18= 0x2003, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8338 16:30:46.172968 CH0 RK1: MR19=303, MR18=2003
8339 16:30:46.179836 CH0_RK1: MR19=0x303, MR18=0x2003, DQSOSC=393, MR23=63, INC=23, DEC=15
8340 16:30:46.180426 [RxdqsGatingPostProcess] freq 1600
8341 16:30:46.186193 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8342 16:30:46.189216 best DQS0 dly(2T, 0.5T) = (1, 1)
8343 16:30:46.193326 best DQS1 dly(2T, 0.5T) = (1, 1)
8344 16:30:46.196502 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8345 16:30:46.199659 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8346 16:30:46.202683 best DQS0 dly(2T, 0.5T) = (1, 1)
8347 16:30:46.205766 best DQS1 dly(2T, 0.5T) = (1, 1)
8348 16:30:46.209154 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8349 16:30:46.212835 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8350 16:30:46.216061 Pre-setting of DQS Precalculation
8351 16:30:46.219169 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8352 16:30:46.219586 ==
8353 16:30:46.222290 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 16:30:46.226047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 16:30:46.226622 ==
8356 16:30:46.232406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8357 16:30:46.235546 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8358 16:30:46.242468 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8359 16:30:46.245430 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8360 16:30:46.255662 [CA 0] Center 42 (13~71) winsize 59
8361 16:30:46.259005 [CA 1] Center 42 (13~72) winsize 60
8362 16:30:46.262055 [CA 2] Center 37 (8~66) winsize 59
8363 16:30:46.265772 [CA 3] Center 36 (7~65) winsize 59
8364 16:30:46.268504 [CA 4] Center 36 (7~66) winsize 60
8365 16:30:46.272253 [CA 5] Center 36 (6~66) winsize 61
8366 16:30:46.272548
8367 16:30:46.275557 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8368 16:30:46.275908
8369 16:30:46.279120 [CATrainingPosCal] consider 1 rank data
8370 16:30:46.281841 u2DelayCellTimex100 = 258/100 ps
8371 16:30:46.288592 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8372 16:30:46.291781 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8373 16:30:46.295663 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8374 16:30:46.298943 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8375 16:30:46.302090 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8376 16:30:46.305061 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8377 16:30:46.305358
8378 16:30:46.308403 CA PerBit enable=1, Macro0, CA PI delay=36
8379 16:30:46.308805
8380 16:30:46.311611 [CBTSetCACLKResult] CA Dly = 36
8381 16:30:46.314865 CS Dly: 9 (0~40)
8382 16:30:46.318662 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8383 16:30:46.321668 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8384 16:30:46.322084 ==
8385 16:30:46.325144 Dram Type= 6, Freq= 0, CH_1, rank 1
8386 16:30:46.331314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 16:30:46.331736 ==
8388 16:30:46.334682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8389 16:30:46.341551 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8390 16:30:46.344874 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8391 16:30:46.351331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8392 16:30:46.358637 [CA 0] Center 42 (12~72) winsize 61
8393 16:30:46.361781 [CA 1] Center 42 (13~72) winsize 60
8394 16:30:46.365285 [CA 2] Center 37 (8~67) winsize 60
8395 16:30:46.368794 [CA 3] Center 36 (7~66) winsize 60
8396 16:30:46.372096 [CA 4] Center 37 (8~67) winsize 60
8397 16:30:46.375146 [CA 5] Center 37 (7~67) winsize 61
8398 16:30:46.375566
8399 16:30:46.378471 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8400 16:30:46.378894
8401 16:30:46.385021 [CATrainingPosCal] consider 2 rank data
8402 16:30:46.385460 u2DelayCellTimex100 = 258/100 ps
8403 16:30:46.391455 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8404 16:30:46.394818 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8405 16:30:46.398210 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8406 16:30:46.401396 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8407 16:30:46.404643 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8408 16:30:46.408183 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8409 16:30:46.408730
8410 16:30:46.411436 CA PerBit enable=1, Macro0, CA PI delay=36
8411 16:30:46.411911
8412 16:30:46.414554 [CBTSetCACLKResult] CA Dly = 36
8413 16:30:46.417900 CS Dly: 11 (0~44)
8414 16:30:46.421155 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8415 16:30:46.424897 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8416 16:30:46.425314
8417 16:30:46.428235 ----->DramcWriteLeveling(PI) begin...
8418 16:30:46.431184 ==
8419 16:30:46.431606 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 16:30:46.437545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 16:30:46.438094 ==
8422 16:30:46.441204 Write leveling (Byte 0): 23 => 23
8423 16:30:46.444482 Write leveling (Byte 1): 26 => 26
8424 16:30:46.447661 DramcWriteLeveling(PI) end<-----
8425 16:30:46.448090
8426 16:30:46.448419 ==
8427 16:30:46.450933 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 16:30:46.454214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 16:30:46.454642 ==
8430 16:30:46.457417 [Gating] SW mode calibration
8431 16:30:46.463978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8432 16:30:46.470452 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8433 16:30:46.474265 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 16:30:46.477435 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 16:30:46.484270 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 16:30:46.487052 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8437 16:30:46.490126 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 16:30:46.496838 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 16:30:46.500404 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 16:30:46.503851 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 16:30:46.510143 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 16:30:46.513374 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 16:30:46.516588 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8444 16:30:46.523082 1 5 12 | B1->B0 | 2727 2424 | 0 0 | (0 1) (1 0)
8445 16:30:46.526131 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8446 16:30:46.529654 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 16:30:46.536413 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 16:30:46.539771 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 16:30:46.542917 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 16:30:46.549319 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 16:30:46.552589 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 16:30:46.556380 1 6 12 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
8453 16:30:46.562646 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 16:30:46.566271 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 16:30:46.569283 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 16:30:46.575617 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 16:30:46.579483 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 16:30:46.582778 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 16:30:46.589021 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8460 16:30:46.592282 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8461 16:30:46.595796 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8462 16:30:46.602453 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 16:30:46.605674 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 16:30:46.608975 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 16:30:46.615467 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 16:30:46.618708 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 16:30:46.621720 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 16:30:46.628736 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 16:30:46.631658 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 16:30:46.635535 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 16:30:46.641828 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 16:30:46.645299 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 16:30:46.648235 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 16:30:46.654859 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 16:30:46.658098 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8476 16:30:46.661288 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8477 16:30:46.668232 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 16:30:46.668830 Total UI for P1: 0, mck2ui 16
8479 16:30:46.674593 best dqsien dly found for B0: ( 1, 9, 10)
8480 16:30:46.675034 Total UI for P1: 0, mck2ui 16
8481 16:30:46.681634 best dqsien dly found for B1: ( 1, 9, 12)
8482 16:30:46.684752 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8483 16:30:46.687980 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8484 16:30:46.688433
8485 16:30:46.691221 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8486 16:30:46.694380 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8487 16:30:46.698202 [Gating] SW calibration Done
8488 16:30:46.698636 ==
8489 16:30:46.701220 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 16:30:46.704148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 16:30:46.704571 ==
8492 16:30:46.707610 RX Vref Scan: 0
8493 16:30:46.708031
8494 16:30:46.710766 RX Vref 0 -> 0, step: 1
8495 16:30:46.711223
8496 16:30:46.711797 RX Delay 0 -> 252, step: 8
8497 16:30:46.717296 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8498 16:30:46.721021 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8499 16:30:46.724264 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8500 16:30:46.727436 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8501 16:30:46.730960 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8502 16:30:46.737260 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8503 16:30:46.740472 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8504 16:30:46.743908 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8505 16:30:46.746810 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8506 16:30:46.750348 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8507 16:30:46.757477 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8508 16:30:46.760305 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8509 16:30:46.763869 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8510 16:30:46.767074 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8511 16:30:46.770308 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8512 16:30:46.776830 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8513 16:30:46.777453 ==
8514 16:30:46.779907 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 16:30:46.783751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 16:30:46.784216 ==
8517 16:30:46.784613 DQS Delay:
8518 16:30:46.786856 DQS0 = 0, DQS1 = 0
8519 16:30:46.787308 DQM Delay:
8520 16:30:46.790082 DQM0 = 137, DQM1 = 128
8521 16:30:46.790554 DQ Delay:
8522 16:30:46.793232 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8523 16:30:46.796459 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8524 16:30:46.799695 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8525 16:30:46.806868 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8526 16:30:46.807321
8527 16:30:46.807661
8528 16:30:46.807971 ==
8529 16:30:46.809845 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 16:30:46.812915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 16:30:46.813336 ==
8532 16:30:46.813666
8533 16:30:46.813978
8534 16:30:46.816198 TX Vref Scan disable
8535 16:30:46.816687 == TX Byte 0 ==
8536 16:30:46.823269 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8537 16:30:46.826364 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8538 16:30:46.826785 == TX Byte 1 ==
8539 16:30:46.832858 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8540 16:30:46.836015 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8541 16:30:46.836537 ==
8542 16:30:46.839216 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 16:30:46.843215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 16:30:46.843637 ==
8545 16:30:46.856731
8546 16:30:46.860061 TX Vref early break, caculate TX vref
8547 16:30:46.863366 TX Vref=16, minBit 5, minWin=21, winSum=370
8548 16:30:46.866247 TX Vref=18, minBit 0, minWin=22, winSum=384
8549 16:30:46.869760 TX Vref=20, minBit 0, minWin=23, winSum=395
8550 16:30:46.873149 TX Vref=22, minBit 0, minWin=23, winSum=404
8551 16:30:46.876210 TX Vref=24, minBit 0, minWin=24, winSum=413
8552 16:30:46.883206 TX Vref=26, minBit 0, minWin=25, winSum=420
8553 16:30:46.886106 TX Vref=28, minBit 5, minWin=24, winSum=416
8554 16:30:46.889503 TX Vref=30, minBit 0, minWin=25, winSum=412
8555 16:30:46.892789 TX Vref=32, minBit 0, minWin=23, winSum=401
8556 16:30:46.896138 TX Vref=34, minBit 0, minWin=23, winSum=394
8557 16:30:46.902646 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8558 16:30:46.903120
8559 16:30:46.905876 Final TX Range 0 Vref 26
8560 16:30:46.906526
8561 16:30:46.907095 ==
8562 16:30:46.909753 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 16:30:46.912869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 16:30:46.913324 ==
8565 16:30:46.913855
8566 16:30:46.914385
8567 16:30:46.916024 TX Vref Scan disable
8568 16:30:46.922490 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8569 16:30:46.923116 == TX Byte 0 ==
8570 16:30:46.926053 u2DelayCellOfst[0]=22 cells (6 PI)
8571 16:30:46.929419 u2DelayCellOfst[1]=15 cells (4 PI)
8572 16:30:46.932555 u2DelayCellOfst[2]=0 cells (0 PI)
8573 16:30:46.935769 u2DelayCellOfst[3]=7 cells (2 PI)
8574 16:30:46.938858 u2DelayCellOfst[4]=11 cells (3 PI)
8575 16:30:46.942077 u2DelayCellOfst[5]=22 cells (6 PI)
8576 16:30:46.946027 u2DelayCellOfst[6]=22 cells (6 PI)
8577 16:30:46.949066 u2DelayCellOfst[7]=7 cells (2 PI)
8578 16:30:46.952341 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8579 16:30:46.955525 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8580 16:30:46.958729 == TX Byte 1 ==
8581 16:30:46.961939 u2DelayCellOfst[8]=0 cells (0 PI)
8582 16:30:46.962410 u2DelayCellOfst[9]=3 cells (1 PI)
8583 16:30:46.965765 u2DelayCellOfst[10]=11 cells (3 PI)
8584 16:30:46.968740 u2DelayCellOfst[11]=3 cells (1 PI)
8585 16:30:46.972125 u2DelayCellOfst[12]=15 cells (4 PI)
8586 16:30:46.975706 u2DelayCellOfst[13]=18 cells (5 PI)
8587 16:30:46.979032 u2DelayCellOfst[14]=18 cells (5 PI)
8588 16:30:46.982383 u2DelayCellOfst[15]=18 cells (5 PI)
8589 16:30:46.989060 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8590 16:30:46.991795 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8591 16:30:46.992217 DramC Write-DBI on
8592 16:30:46.992547 ==
8593 16:30:46.995071 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 16:30:47.001896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 16:30:47.002450 ==
8596 16:30:47.002791
8597 16:30:47.003103
8598 16:30:47.003400 TX Vref Scan disable
8599 16:30:47.006027 == TX Byte 0 ==
8600 16:30:47.009317 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8601 16:30:47.012612 == TX Byte 1 ==
8602 16:30:47.015589 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8603 16:30:47.019363 DramC Write-DBI off
8604 16:30:47.019779
8605 16:30:47.020111 [DATLAT]
8606 16:30:47.020480 Freq=1600, CH1 RK0
8607 16:30:47.020803
8608 16:30:47.022544 DATLAT Default: 0xf
8609 16:30:47.025671 0, 0xFFFF, sum = 0
8610 16:30:47.026098 1, 0xFFFF, sum = 0
8611 16:30:47.029207 2, 0xFFFF, sum = 0
8612 16:30:47.029717 3, 0xFFFF, sum = 0
8613 16:30:47.032618 4, 0xFFFF, sum = 0
8614 16:30:47.033042 5, 0xFFFF, sum = 0
8615 16:30:47.035842 6, 0xFFFF, sum = 0
8616 16:30:47.036538 7, 0xFFFF, sum = 0
8617 16:30:47.038994 8, 0xFFFF, sum = 0
8618 16:30:47.039417 9, 0xFFFF, sum = 0
8619 16:30:47.042273 10, 0xFFFF, sum = 0
8620 16:30:47.042700 11, 0xFFFF, sum = 0
8621 16:30:47.045600 12, 0xFFFF, sum = 0
8622 16:30:47.046146 13, 0xFFFF, sum = 0
8623 16:30:47.048740 14, 0x0, sum = 1
8624 16:30:47.049343 15, 0x0, sum = 2
8625 16:30:47.051901 16, 0x0, sum = 3
8626 16:30:47.052495 17, 0x0, sum = 4
8627 16:30:47.055075 best_step = 15
8628 16:30:47.055499
8629 16:30:47.055835 ==
8630 16:30:47.058650 Dram Type= 6, Freq= 0, CH_1, rank 0
8631 16:30:47.062002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8632 16:30:47.062541 ==
8633 16:30:47.065354 RX Vref Scan: 1
8634 16:30:47.065925
8635 16:30:47.066516 Set Vref Range= 24 -> 127
8636 16:30:47.066981
8637 16:30:47.068388 RX Vref 24 -> 127, step: 1
8638 16:30:47.068950
8639 16:30:47.071604 RX Delay 11 -> 252, step: 4
8640 16:30:47.072120
8641 16:30:47.075288 Set Vref, RX VrefLevel [Byte0]: 24
8642 16:30:47.078451 [Byte1]: 24
8643 16:30:47.078923
8644 16:30:47.081509 Set Vref, RX VrefLevel [Byte0]: 25
8645 16:30:47.084643 [Byte1]: 25
8646 16:30:47.088588
8647 16:30:47.089218 Set Vref, RX VrefLevel [Byte0]: 26
8648 16:30:47.091623 [Byte1]: 26
8649 16:30:47.096254
8650 16:30:47.096896 Set Vref, RX VrefLevel [Byte0]: 27
8651 16:30:47.099677 [Byte1]: 27
8652 16:30:47.103682
8653 16:30:47.104218 Set Vref, RX VrefLevel [Byte0]: 28
8654 16:30:47.107307 [Byte1]: 28
8655 16:30:47.111295
8656 16:30:47.111713 Set Vref, RX VrefLevel [Byte0]: 29
8657 16:30:47.114814 [Byte1]: 29
8658 16:30:47.118956
8659 16:30:47.119374 Set Vref, RX VrefLevel [Byte0]: 30
8660 16:30:47.122533 [Byte1]: 30
8661 16:30:47.127009
8662 16:30:47.127664 Set Vref, RX VrefLevel [Byte0]: 31
8663 16:30:47.129786 [Byte1]: 31
8664 16:30:47.134445
8665 16:30:47.135110 Set Vref, RX VrefLevel [Byte0]: 32
8666 16:30:47.137579 [Byte1]: 32
8667 16:30:47.141920
8668 16:30:47.142583 Set Vref, RX VrefLevel [Byte0]: 33
8669 16:30:47.145205 [Byte1]: 33
8670 16:30:47.149648
8671 16:30:47.150224 Set Vref, RX VrefLevel [Byte0]: 34
8672 16:30:47.152729 [Byte1]: 34
8673 16:30:47.157303
8674 16:30:47.157950 Set Vref, RX VrefLevel [Byte0]: 35
8675 16:30:47.160237 [Byte1]: 35
8676 16:30:47.164906
8677 16:30:47.165212 Set Vref, RX VrefLevel [Byte0]: 36
8678 16:30:47.168015 [Byte1]: 36
8679 16:30:47.172438
8680 16:30:47.172620 Set Vref, RX VrefLevel [Byte0]: 37
8681 16:30:47.175680 [Byte1]: 37
8682 16:30:47.180134
8683 16:30:47.180309 Set Vref, RX VrefLevel [Byte0]: 38
8684 16:30:47.182719 [Byte1]: 38
8685 16:30:47.187073
8686 16:30:47.187197 Set Vref, RX VrefLevel [Byte0]: 39
8687 16:30:47.190934 [Byte1]: 39
8688 16:30:47.194769
8689 16:30:47.194908 Set Vref, RX VrefLevel [Byte0]: 40
8690 16:30:47.198301 [Byte1]: 40
8691 16:30:47.202935
8692 16:30:47.203028 Set Vref, RX VrefLevel [Byte0]: 41
8693 16:30:47.206053 [Byte1]: 41
8694 16:30:47.210322
8695 16:30:47.210442 Set Vref, RX VrefLevel [Byte0]: 42
8696 16:30:47.213450 [Byte1]: 42
8697 16:30:47.217780
8698 16:30:47.217906 Set Vref, RX VrefLevel [Byte0]: 43
8699 16:30:47.221430 [Byte1]: 43
8700 16:30:47.225268
8701 16:30:47.225353 Set Vref, RX VrefLevel [Byte0]: 44
8702 16:30:47.228456 [Byte1]: 44
8703 16:30:47.232830
8704 16:30:47.232947 Set Vref, RX VrefLevel [Byte0]: 45
8705 16:30:47.236484 [Byte1]: 45
8706 16:30:47.240784
8707 16:30:47.240914 Set Vref, RX VrefLevel [Byte0]: 46
8708 16:30:47.243803 [Byte1]: 46
8709 16:30:47.248076
8710 16:30:47.248166 Set Vref, RX VrefLevel [Byte0]: 47
8711 16:30:47.251561 [Byte1]: 47
8712 16:30:47.256071
8713 16:30:47.256171 Set Vref, RX VrefLevel [Byte0]: 48
8714 16:30:47.258798 [Byte1]: 48
8715 16:30:47.263137
8716 16:30:47.263235 Set Vref, RX VrefLevel [Byte0]: 49
8717 16:30:47.266925 [Byte1]: 49
8718 16:30:47.270815
8719 16:30:47.270929 Set Vref, RX VrefLevel [Byte0]: 50
8720 16:30:47.274813 [Byte1]: 50
8721 16:30:47.278585
8722 16:30:47.278701 Set Vref, RX VrefLevel [Byte0]: 51
8723 16:30:47.281795 [Byte1]: 51
8724 16:30:47.286098
8725 16:30:47.286244 Set Vref, RX VrefLevel [Byte0]: 52
8726 16:30:47.289557 [Byte1]: 52
8727 16:30:47.293827
8728 16:30:47.293953 Set Vref, RX VrefLevel [Byte0]: 53
8729 16:30:47.297157 [Byte1]: 53
8730 16:30:47.301492
8731 16:30:47.301621 Set Vref, RX VrefLevel [Byte0]: 54
8732 16:30:47.304490 [Byte1]: 54
8733 16:30:47.309160
8734 16:30:47.309251 Set Vref, RX VrefLevel [Byte0]: 55
8735 16:30:47.312405 [Byte1]: 55
8736 16:30:47.316800
8737 16:30:47.316902 Set Vref, RX VrefLevel [Byte0]: 56
8738 16:30:47.319871 [Byte1]: 56
8739 16:30:47.324569
8740 16:30:47.324665 Set Vref, RX VrefLevel [Byte0]: 57
8741 16:30:47.327769 [Byte1]: 57
8742 16:30:47.332152
8743 16:30:47.332238 Set Vref, RX VrefLevel [Byte0]: 58
8744 16:30:47.335193 [Byte1]: 58
8745 16:30:47.339524
8746 16:30:47.339623 Set Vref, RX VrefLevel [Byte0]: 59
8747 16:30:47.342654 [Byte1]: 59
8748 16:30:47.347092
8749 16:30:47.347204 Set Vref, RX VrefLevel [Byte0]: 60
8750 16:30:47.350183 [Byte1]: 60
8751 16:30:47.354465
8752 16:30:47.354585 Set Vref, RX VrefLevel [Byte0]: 61
8753 16:30:47.357991 [Byte1]: 61
8754 16:30:47.362382
8755 16:30:47.362483 Set Vref, RX VrefLevel [Byte0]: 62
8756 16:30:47.365434 [Byte1]: 62
8757 16:30:47.369978
8758 16:30:47.370106 Set Vref, RX VrefLevel [Byte0]: 63
8759 16:30:47.373156 [Byte1]: 63
8760 16:30:47.377781
8761 16:30:47.377941 Set Vref, RX VrefLevel [Byte0]: 64
8762 16:30:47.380989 [Byte1]: 64
8763 16:30:47.384897
8764 16:30:47.385007 Set Vref, RX VrefLevel [Byte0]: 65
8765 16:30:47.388771 [Byte1]: 65
8766 16:30:47.392636
8767 16:30:47.392731 Set Vref, RX VrefLevel [Byte0]: 66
8768 16:30:47.395842 [Byte1]: 66
8769 16:30:47.400453
8770 16:30:47.400548 Set Vref, RX VrefLevel [Byte0]: 67
8771 16:30:47.403588 [Byte1]: 67
8772 16:30:47.407813
8773 16:30:47.407897 Set Vref, RX VrefLevel [Byte0]: 68
8774 16:30:47.411042 [Byte1]: 68
8775 16:30:47.415628
8776 16:30:47.415717 Set Vref, RX VrefLevel [Byte0]: 69
8777 16:30:47.418741 [Byte1]: 69
8778 16:30:47.423063
8779 16:30:47.423144 Set Vref, RX VrefLevel [Byte0]: 70
8780 16:30:47.426716 [Byte1]: 70
8781 16:30:47.431048
8782 16:30:47.431173 Set Vref, RX VrefLevel [Byte0]: 71
8783 16:30:47.434047 [Byte1]: 71
8784 16:30:47.438709
8785 16:30:47.438817 Set Vref, RX VrefLevel [Byte0]: 72
8786 16:30:47.441725 [Byte1]: 72
8787 16:30:47.446087
8788 16:30:47.446227 Set Vref, RX VrefLevel [Byte0]: 73
8789 16:30:47.449284 [Byte1]: 73
8790 16:30:47.453753
8791 16:30:47.453868 Set Vref, RX VrefLevel [Byte0]: 74
8792 16:30:47.457008 [Byte1]: 74
8793 16:30:47.461376
8794 16:30:47.461484 Set Vref, RX VrefLevel [Byte0]: 75
8795 16:30:47.464388 [Byte1]: 75
8796 16:30:47.469016
8797 16:30:47.469113 Final RX Vref Byte 0 = 52 to rank0
8798 16:30:47.472086 Final RX Vref Byte 1 = 59 to rank0
8799 16:30:47.475359 Final RX Vref Byte 0 = 52 to rank1
8800 16:30:47.479027 Final RX Vref Byte 1 = 59 to rank1==
8801 16:30:47.482220 Dram Type= 6, Freq= 0, CH_1, rank 0
8802 16:30:47.488804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 16:30:47.488904 ==
8804 16:30:47.488969 DQS Delay:
8805 16:30:47.491642 DQS0 = 0, DQS1 = 0
8806 16:30:47.491725 DQM Delay:
8807 16:30:47.491790 DQM0 = 133, DQM1 = 127
8808 16:30:47.494962 DQ Delay:
8809 16:30:47.498399 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8810 16:30:47.501745 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8811 16:30:47.504770 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8812 16:30:47.508556 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8813 16:30:47.508692
8814 16:30:47.508785
8815 16:30:47.508873
8816 16:30:47.511549 [DramC_TX_OE_Calibration] TA2
8817 16:30:47.514964 Original DQ_B0 (3 6) =30, OEN = 27
8818 16:30:47.518072 Original DQ_B1 (3 6) =30, OEN = 27
8819 16:30:47.521291 24, 0x0, End_B0=24 End_B1=24
8820 16:30:47.525017 25, 0x0, End_B0=25 End_B1=25
8821 16:30:47.525101 26, 0x0, End_B0=26 End_B1=26
8822 16:30:47.528196 27, 0x0, End_B0=27 End_B1=27
8823 16:30:47.531327 28, 0x0, End_B0=28 End_B1=28
8824 16:30:47.534911 29, 0x0, End_B0=29 End_B1=29
8825 16:30:47.534999 30, 0x0, End_B0=30 End_B1=30
8826 16:30:47.537846 31, 0x4141, End_B0=30 End_B1=30
8827 16:30:47.541732 Byte0 end_step=30 best_step=27
8828 16:30:47.544905 Byte1 end_step=30 best_step=27
8829 16:30:47.548017 Byte0 TX OE(2T, 0.5T) = (3, 3)
8830 16:30:47.551004 Byte1 TX OE(2T, 0.5T) = (3, 3)
8831 16:30:47.551109
8832 16:30:47.551178
8833 16:30:47.557608 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8834 16:30:47.560793 CH1 RK0: MR19=303, MR18=1B11
8835 16:30:47.567650 CH1_RK0: MR19=0x303, MR18=0x1B11, DQSOSC=396, MR23=63, INC=23, DEC=15
8836 16:30:47.567763
8837 16:30:47.571008 ----->DramcWriteLeveling(PI) begin...
8838 16:30:47.571114 ==
8839 16:30:47.574246 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 16:30:47.577319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 16:30:47.577434 ==
8842 16:30:47.580485 Write leveling (Byte 0): 24 => 24
8843 16:30:47.583695 Write leveling (Byte 1): 27 => 27
8844 16:30:47.587620 DramcWriteLeveling(PI) end<-----
8845 16:30:47.587733
8846 16:30:47.587828 ==
8847 16:30:47.590825 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 16:30:47.596789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 16:30:47.596899 ==
8850 16:30:47.596993 [Gating] SW mode calibration
8851 16:30:47.606747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8852 16:30:47.609953 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8853 16:30:47.616818 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 16:30:47.619947 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 16:30:47.623146 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8856 16:30:47.630249 1 4 12 | B1->B0 | 3333 2322 | 1 1 | (1 1) (0 0)
8857 16:30:47.633224 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 16:30:47.636460 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 16:30:47.643126 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 16:30:47.646228 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8861 16:30:47.649971 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8862 16:30:47.656216 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8863 16:30:47.659751 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8864 16:30:47.663025 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8865 16:30:47.669400 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 16:30:47.673132 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 16:30:47.676251 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 16:30:47.682637 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 16:30:47.685937 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8870 16:30:47.689118 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8871 16:30:47.695999 1 6 8 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
8872 16:30:47.699093 1 6 12 | B1->B0 | 4545 2626 | 0 0 | (1 1) (0 0)
8873 16:30:47.702598 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8874 16:30:47.708914 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 16:30:47.712593 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 16:30:47.715587 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 16:30:47.722060 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 16:30:47.725314 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 16:30:47.728941 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8880 16:30:47.735307 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8881 16:30:47.738652 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8882 16:30:47.741833 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 16:30:47.748360 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 16:30:47.751446 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 16:30:47.755179 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 16:30:47.761454 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 16:30:47.764747 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 16:30:47.768522 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 16:30:47.774916 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 16:30:47.777929 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 16:30:47.781160 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 16:30:47.788061 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 16:30:47.791408 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 16:30:47.794501 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 16:30:47.800972 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8896 16:30:47.804478 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8897 16:30:47.808034 Total UI for P1: 0, mck2ui 16
8898 16:30:47.811099 best dqsien dly found for B1: ( 1, 9, 8)
8899 16:30:47.814464 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 16:30:47.817589 Total UI for P1: 0, mck2ui 16
8901 16:30:47.820859 best dqsien dly found for B0: ( 1, 9, 12)
8902 16:30:47.824673 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8903 16:30:47.827875 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8904 16:30:47.827990
8905 16:30:47.834087 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8906 16:30:47.837414 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8907 16:30:47.837491 [Gating] SW calibration Done
8908 16:30:47.841164 ==
8909 16:30:47.844430 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 16:30:47.847279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 16:30:47.847385 ==
8912 16:30:47.847477 RX Vref Scan: 0
8913 16:30:47.847570
8914 16:30:47.850352 RX Vref 0 -> 0, step: 1
8915 16:30:47.850432
8916 16:30:47.854140 RX Delay 0 -> 252, step: 8
8917 16:30:47.857093 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8918 16:30:47.860794 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8919 16:30:47.864019 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8920 16:30:47.870381 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8921 16:30:47.873417 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8922 16:30:47.877135 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8923 16:30:47.880049 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8924 16:30:47.886782 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8925 16:30:47.889893 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8926 16:30:47.893842 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8927 16:30:47.896981 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8928 16:30:47.900222 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8929 16:30:47.906639 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8930 16:30:47.909723 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8931 16:30:47.913076 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8932 16:30:47.916631 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8933 16:30:47.916779 ==
8934 16:30:47.920120 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 16:30:47.926367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 16:30:47.926450 ==
8937 16:30:47.926533 DQS Delay:
8938 16:30:47.929795 DQS0 = 0, DQS1 = 0
8939 16:30:47.929896 DQM Delay:
8940 16:30:47.929994 DQM0 = 136, DQM1 = 129
8941 16:30:47.932922 DQ Delay:
8942 16:30:47.936204 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8943 16:30:47.940124 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8944 16:30:47.943227 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8945 16:30:47.946346 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8946 16:30:47.946478
8947 16:30:47.946595
8948 16:30:47.946734 ==
8949 16:30:47.949770 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 16:30:47.956261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 16:30:47.956377 ==
8952 16:30:47.956491
8953 16:30:47.956624
8954 16:30:47.956778 TX Vref Scan disable
8955 16:30:47.959701 == TX Byte 0 ==
8956 16:30:47.962839 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8957 16:30:47.969608 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8958 16:30:47.969778 == TX Byte 1 ==
8959 16:30:47.972669 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8960 16:30:47.979875 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8961 16:30:47.980100 ==
8962 16:30:47.982949 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 16:30:47.986222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 16:30:47.986527 ==
8965 16:30:47.998877
8966 16:30:48.002113 TX Vref early break, caculate TX vref
8967 16:30:48.005434 TX Vref=16, minBit 5, minWin=22, winSum=381
8968 16:30:48.008751 TX Vref=18, minBit 1, minWin=23, winSum=394
8969 16:30:48.011892 TX Vref=20, minBit 1, minWin=24, winSum=404
8970 16:30:48.015093 TX Vref=22, minBit 1, minWin=24, winSum=409
8971 16:30:48.018242 TX Vref=24, minBit 5, minWin=25, winSum=423
8972 16:30:48.025428 TX Vref=26, minBit 0, minWin=25, winSum=422
8973 16:30:48.028092 TX Vref=28, minBit 0, minWin=25, winSum=425
8974 16:30:48.031729 TX Vref=30, minBit 0, minWin=24, winSum=418
8975 16:30:48.034974 TX Vref=32, minBit 0, minWin=24, winSum=411
8976 16:30:48.038201 TX Vref=34, minBit 0, minWin=23, winSum=400
8977 16:30:48.045136 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8978 16:30:48.045790
8979 16:30:48.048055 Final TX Range 0 Vref 28
8980 16:30:48.048565
8981 16:30:48.048926 ==
8982 16:30:48.051245 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 16:30:48.055092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 16:30:48.055644 ==
8985 16:30:48.056111
8986 16:30:48.056505
8987 16:30:48.057933 TX Vref Scan disable
8988 16:30:48.064801 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8989 16:30:48.065218 == TX Byte 0 ==
8990 16:30:48.068011 u2DelayCellOfst[0]=18 cells (5 PI)
8991 16:30:48.071230 u2DelayCellOfst[1]=11 cells (3 PI)
8992 16:30:48.074533 u2DelayCellOfst[2]=0 cells (0 PI)
8993 16:30:48.077922 u2DelayCellOfst[3]=7 cells (2 PI)
8994 16:30:48.081148 u2DelayCellOfst[4]=7 cells (2 PI)
8995 16:30:48.084422 u2DelayCellOfst[5]=22 cells (6 PI)
8996 16:30:48.087548 u2DelayCellOfst[6]=22 cells (6 PI)
8997 16:30:48.090858 u2DelayCellOfst[7]=7 cells (2 PI)
8998 16:30:48.094266 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8999 16:30:48.097842 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9000 16:30:48.100582 == TX Byte 1 ==
9001 16:30:48.104387 u2DelayCellOfst[8]=0 cells (0 PI)
9002 16:30:48.107388 u2DelayCellOfst[9]=3 cells (1 PI)
9003 16:30:48.107813 u2DelayCellOfst[10]=15 cells (4 PI)
9004 16:30:48.110716 u2DelayCellOfst[11]=7 cells (2 PI)
9005 16:30:48.113819 u2DelayCellOfst[12]=18 cells (5 PI)
9006 16:30:48.117425 u2DelayCellOfst[13]=18 cells (5 PI)
9007 16:30:48.120690 u2DelayCellOfst[14]=18 cells (5 PI)
9008 16:30:48.123980 u2DelayCellOfst[15]=18 cells (5 PI)
9009 16:30:48.130588 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9010 16:30:48.133897 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9011 16:30:48.134398 DramC Write-DBI on
9012 16:30:48.134725 ==
9013 16:30:48.137545 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 16:30:48.143983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 16:30:48.144570 ==
9016 16:30:48.144912
9017 16:30:48.145239
9018 16:30:48.147397 TX Vref Scan disable
9019 16:30:48.147906 == TX Byte 0 ==
9020 16:30:48.153615 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9021 16:30:48.154032 == TX Byte 1 ==
9022 16:30:48.156716 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9023 16:30:48.159995 DramC Write-DBI off
9024 16:30:48.160470
9025 16:30:48.160940 [DATLAT]
9026 16:30:48.163594 Freq=1600, CH1 RK1
9027 16:30:48.164114
9028 16:30:48.164577 DATLAT Default: 0xf
9029 16:30:48.166643 0, 0xFFFF, sum = 0
9030 16:30:48.167079 1, 0xFFFF, sum = 0
9031 16:30:48.170054 2, 0xFFFF, sum = 0
9032 16:30:48.170527 3, 0xFFFF, sum = 0
9033 16:30:48.173079 4, 0xFFFF, sum = 0
9034 16:30:48.173644 5, 0xFFFF, sum = 0
9035 16:30:48.176490 6, 0xFFFF, sum = 0
9036 16:30:48.176910 7, 0xFFFF, sum = 0
9037 16:30:48.180215 8, 0xFFFF, sum = 0
9038 16:30:48.183551 9, 0xFFFF, sum = 0
9039 16:30:48.184180 10, 0xFFFF, sum = 0
9040 16:30:48.186634 11, 0xFFFF, sum = 0
9041 16:30:48.187061 12, 0xFFFF, sum = 0
9042 16:30:48.189590 13, 0xFFFF, sum = 0
9043 16:30:48.190212 14, 0x0, sum = 1
9044 16:30:48.193162 15, 0x0, sum = 2
9045 16:30:48.193725 16, 0x0, sum = 3
9046 16:30:48.196707 17, 0x0, sum = 4
9047 16:30:48.197258 best_step = 15
9048 16:30:48.197599
9049 16:30:48.197909 ==
9050 16:30:48.199380 Dram Type= 6, Freq= 0, CH_1, rank 1
9051 16:30:48.203016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9052 16:30:48.206248 ==
9053 16:30:48.206678 RX Vref Scan: 0
9054 16:30:48.207026
9055 16:30:48.209720 RX Vref 0 -> 0, step: 1
9056 16:30:48.210134
9057 16:30:48.210520 RX Delay 11 -> 252, step: 4
9058 16:30:48.216908 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9059 16:30:48.220319 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9060 16:30:48.223572 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9061 16:30:48.226889 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9062 16:30:48.230233 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9063 16:30:48.237140 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9064 16:30:48.239995 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9065 16:30:48.243136 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9066 16:30:48.246688 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9067 16:30:48.253079 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9068 16:30:48.256803 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9069 16:30:48.260096 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9070 16:30:48.263220 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9071 16:30:48.266312 iDelay=203, Bit 13, Center 132 (79 ~ 186) 108
9072 16:30:48.273178 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9073 16:30:48.276415 iDelay=203, Bit 15, Center 136 (79 ~ 194) 116
9074 16:30:48.276833 ==
9075 16:30:48.279400 Dram Type= 6, Freq= 0, CH_1, rank 1
9076 16:30:48.283163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9077 16:30:48.283648 ==
9078 16:30:48.286460 DQS Delay:
9079 16:30:48.287146 DQS0 = 0, DQS1 = 0
9080 16:30:48.287754 DQM Delay:
9081 16:30:48.289792 DQM0 = 133, DQM1 = 126
9082 16:30:48.290290 DQ Delay:
9083 16:30:48.292965 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9084 16:30:48.296134 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9085 16:30:48.302634 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9086 16:30:48.305852 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
9087 16:30:48.306314
9088 16:30:48.306810
9089 16:30:48.307141
9090 16:30:48.309068 [DramC_TX_OE_Calibration] TA2
9091 16:30:48.312872 Original DQ_B0 (3 6) =30, OEN = 27
9092 16:30:48.315786 Original DQ_B1 (3 6) =30, OEN = 27
9093 16:30:48.316202 24, 0x0, End_B0=24 End_B1=24
9094 16:30:48.319370 25, 0x0, End_B0=25 End_B1=25
9095 16:30:48.322702 26, 0x0, End_B0=26 End_B1=26
9096 16:30:48.325943 27, 0x0, End_B0=27 End_B1=27
9097 16:30:48.326686 28, 0x0, End_B0=28 End_B1=28
9098 16:30:48.329501 29, 0x0, End_B0=29 End_B1=29
9099 16:30:48.332308 30, 0x0, End_B0=30 End_B1=30
9100 16:30:48.335511 31, 0x4141, End_B0=30 End_B1=30
9101 16:30:48.339202 Byte0 end_step=30 best_step=27
9102 16:30:48.342403 Byte1 end_step=30 best_step=27
9103 16:30:48.342949 Byte0 TX OE(2T, 0.5T) = (3, 3)
9104 16:30:48.345565 Byte1 TX OE(2T, 0.5T) = (3, 3)
9105 16:30:48.346151
9106 16:30:48.346582
9107 16:30:48.355253 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9108 16:30:48.358363 CH1 RK1: MR19=303, MR18=D09
9109 16:30:48.361884 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9110 16:30:48.364998 [RxdqsGatingPostProcess] freq 1600
9111 16:30:48.371550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9112 16:30:48.375515 best DQS0 dly(2T, 0.5T) = (1, 1)
9113 16:30:48.378514 best DQS1 dly(2T, 0.5T) = (1, 1)
9114 16:30:48.381830 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9115 16:30:48.384952 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9116 16:30:48.388801 best DQS0 dly(2T, 0.5T) = (1, 1)
9117 16:30:48.391879 best DQS1 dly(2T, 0.5T) = (1, 1)
9118 16:30:48.392353 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9119 16:30:48.395010 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9120 16:30:48.398133 Pre-setting of DQS Precalculation
9121 16:30:48.405239 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9122 16:30:48.411488 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9123 16:30:48.417874 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9124 16:30:48.418330
9125 16:30:48.418667
9126 16:30:48.421231 [Calibration Summary] 3200 Mbps
9127 16:30:48.424934 CH 0, Rank 0
9128 16:30:48.425347 SW Impedance : PASS
9129 16:30:48.428157 DUTY Scan : NO K
9130 16:30:48.431419 ZQ Calibration : PASS
9131 16:30:48.431835 Jitter Meter : NO K
9132 16:30:48.434554 CBT Training : PASS
9133 16:30:48.438189 Write leveling : PASS
9134 16:30:48.438724 RX DQS gating : PASS
9135 16:30:48.441565 RX DQ/DQS(RDDQC) : PASS
9136 16:30:48.441982 TX DQ/DQS : PASS
9137 16:30:48.444418 RX DATLAT : PASS
9138 16:30:48.447761 RX DQ/DQS(Engine): PASS
9139 16:30:48.448178 TX OE : PASS
9140 16:30:48.450984 All Pass.
9141 16:30:48.451634
9142 16:30:48.452006 CH 0, Rank 1
9143 16:30:48.454601 SW Impedance : PASS
9144 16:30:48.455222 DUTY Scan : NO K
9145 16:30:48.457944 ZQ Calibration : PASS
9146 16:30:48.460871 Jitter Meter : NO K
9147 16:30:48.461325 CBT Training : PASS
9148 16:30:48.464520 Write leveling : PASS
9149 16:30:48.467722 RX DQS gating : PASS
9150 16:30:48.468139 RX DQ/DQS(RDDQC) : PASS
9151 16:30:48.470839 TX DQ/DQS : PASS
9152 16:30:48.474191 RX DATLAT : PASS
9153 16:30:48.474699 RX DQ/DQS(Engine): PASS
9154 16:30:48.477590 TX OE : PASS
9155 16:30:48.478008 All Pass.
9156 16:30:48.478391
9157 16:30:48.480529 CH 1, Rank 0
9158 16:30:48.480965 SW Impedance : PASS
9159 16:30:48.483879 DUTY Scan : NO K
9160 16:30:48.487644 ZQ Calibration : PASS
9161 16:30:48.488066 Jitter Meter : NO K
9162 16:30:48.490781 CBT Training : PASS
9163 16:30:48.493772 Write leveling : PASS
9164 16:30:48.494383 RX DQS gating : PASS
9165 16:30:48.497036 RX DQ/DQS(RDDQC) : PASS
9166 16:30:48.500838 TX DQ/DQS : PASS
9167 16:30:48.501288 RX DATLAT : PASS
9168 16:30:48.503590 RX DQ/DQS(Engine): PASS
9169 16:30:48.507359 TX OE : PASS
9170 16:30:48.507780 All Pass.
9171 16:30:48.508111
9172 16:30:48.508413 CH 1, Rank 1
9173 16:30:48.510559 SW Impedance : PASS
9174 16:30:48.513621 DUTY Scan : NO K
9175 16:30:48.514219 ZQ Calibration : PASS
9176 16:30:48.516832 Jitter Meter : NO K
9177 16:30:48.520435 CBT Training : PASS
9178 16:30:48.520991 Write leveling : PASS
9179 16:30:48.523831 RX DQS gating : PASS
9180 16:30:48.526835 RX DQ/DQS(RDDQC) : PASS
9181 16:30:48.527249 TX DQ/DQS : PASS
9182 16:30:48.530141 RX DATLAT : PASS
9183 16:30:48.530602 RX DQ/DQS(Engine): PASS
9184 16:30:48.533275 TX OE : PASS
9185 16:30:48.533694 All Pass.
9186 16:30:48.534019
9187 16:30:48.536462 DramC Write-DBI on
9188 16:30:48.540259 PER_BANK_REFRESH: Hybrid Mode
9189 16:30:48.540730 TX_TRACKING: ON
9190 16:30:48.549924 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9191 16:30:48.556290 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9192 16:30:48.566143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9193 16:30:48.569654 [FAST_K] Save calibration result to emmc
9194 16:30:48.573011 sync common calibartion params.
9195 16:30:48.573569 sync cbt_mode0:1, 1:1
9196 16:30:48.576106 dram_init: ddr_geometry: 2
9197 16:30:48.579388 dram_init: ddr_geometry: 2
9198 16:30:48.579802 dram_init: ddr_geometry: 2
9199 16:30:48.583005 0:dram_rank_size:100000000
9200 16:30:48.585850 1:dram_rank_size:100000000
9201 16:30:48.592799 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9202 16:30:48.593274 DFS_SHUFFLE_HW_MODE: ON
9203 16:30:48.595775 dramc_set_vcore_voltage set vcore to 725000
9204 16:30:48.599002 Read voltage for 1600, 0
9205 16:30:48.599469 Vio18 = 0
9206 16:30:48.602667 Vcore = 725000
9207 16:30:48.603126 Vdram = 0
9208 16:30:48.603458 Vddq = 0
9209 16:30:48.605658 Vmddr = 0
9210 16:30:48.606218 switch to 3200 Mbps bootup
9211 16:30:48.608841 [DramcRunTimeConfig]
9212 16:30:48.609398 PHYPLL
9213 16:30:48.612259 DPM_CONTROL_AFTERK: ON
9214 16:30:48.612672 PER_BANK_REFRESH: ON
9215 16:30:48.615300 REFRESH_OVERHEAD_REDUCTION: ON
9216 16:30:48.619109 CMD_PICG_NEW_MODE: OFF
9217 16:30:48.619527 XRTWTW_NEW_MODE: ON
9218 16:30:48.621942 XRTRTR_NEW_MODE: ON
9219 16:30:48.622467 TX_TRACKING: ON
9220 16:30:48.625145 RDSEL_TRACKING: OFF
9221 16:30:48.628322 DQS Precalculation for DVFS: ON
9222 16:30:48.628833 RX_TRACKING: OFF
9223 16:30:48.632194 HW_GATING DBG: ON
9224 16:30:48.632684 ZQCS_ENABLE_LP4: ON
9225 16:30:48.635326 RX_PICG_NEW_MODE: ON
9226 16:30:48.635740 TX_PICG_NEW_MODE: ON
9227 16:30:48.638606 ENABLE_RX_DCM_DPHY: ON
9228 16:30:48.641622 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9229 16:30:48.644980 DUMMY_READ_FOR_TRACKING: OFF
9230 16:30:48.648585 !!! SPM_CONTROL_AFTERK: OFF
9231 16:30:48.649033 !!! SPM could not control APHY
9232 16:30:48.651447 IMPEDANCE_TRACKING: ON
9233 16:30:48.652037 TEMP_SENSOR: ON
9234 16:30:48.654851 HW_SAVE_FOR_SR: OFF
9235 16:30:48.658031 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9236 16:30:48.662007 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9237 16:30:48.665138 Read ODT Tracking: ON
9238 16:30:48.665553 Refresh Rate DeBounce: ON
9239 16:30:48.668256 DFS_NO_QUEUE_FLUSH: ON
9240 16:30:48.671797 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9241 16:30:48.675091 ENABLE_DFS_RUNTIME_MRW: OFF
9242 16:30:48.675504 DDR_RESERVE_NEW_MODE: ON
9243 16:30:48.677937 MR_CBT_SWITCH_FREQ: ON
9244 16:30:48.681544 =========================
9245 16:30:48.699684 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9246 16:30:48.702346 dram_init: ddr_geometry: 2
9247 16:30:48.721116 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9248 16:30:48.724317 dram_init: dram init end (result: 0)
9249 16:30:48.731226 DRAM-K: Full calibration passed in 24589 msecs
9250 16:30:48.733758 MRC: failed to locate region type 0.
9251 16:30:48.734206 DRAM rank0 size:0x100000000,
9252 16:30:48.737765 DRAM rank1 size=0x100000000
9253 16:30:48.747258 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9254 16:30:48.753966 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9255 16:30:48.760358 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9256 16:30:48.771067 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9257 16:30:48.771631 DRAM rank0 size:0x100000000,
9258 16:30:48.773785 DRAM rank1 size=0x100000000
9259 16:30:48.774221 CBMEM:
9260 16:30:48.776885 IMD: root @ 0xfffff000 254 entries.
9261 16:30:48.780042 IMD: root @ 0xffffec00 62 entries.
9262 16:30:48.783554 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9263 16:30:48.789958 WARNING: RO_VPD is uninitialized or empty.
9264 16:30:48.793589 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9265 16:30:48.801142 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9266 16:30:48.813633 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9267 16:30:48.824865 BS: romstage times (exec / console): total (unknown) / 24084 ms
9268 16:30:48.825302
9269 16:30:48.825634
9270 16:30:48.835204 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9271 16:30:48.838448 ARM64: Exception handlers installed.
9272 16:30:48.841521 ARM64: Testing exception
9273 16:30:48.844857 ARM64: Done test exception
9274 16:30:48.845296 Enumerating buses...
9275 16:30:48.847978 Show all devs... Before device enumeration.
9276 16:30:48.851074 Root Device: enabled 1
9277 16:30:48.854257 CPU_CLUSTER: 0: enabled 1
9278 16:30:48.854770 CPU: 00: enabled 1
9279 16:30:48.857590 Compare with tree...
9280 16:30:48.861354 Root Device: enabled 1
9281 16:30:48.861783 CPU_CLUSTER: 0: enabled 1
9282 16:30:48.864198 CPU: 00: enabled 1
9283 16:30:48.864722 Root Device scanning...
9284 16:30:48.867511 scan_static_bus for Root Device
9285 16:30:48.871624 CPU_CLUSTER: 0 enabled
9286 16:30:48.874535 scan_static_bus for Root Device done
9287 16:30:48.877718 scan_bus: bus Root Device finished in 8 msecs
9288 16:30:48.878242 done
9289 16:30:48.884041 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9290 16:30:48.887710 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9291 16:30:48.894107 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9292 16:30:48.900459 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9293 16:30:48.900973 Allocating resources...
9294 16:30:48.904318 Reading resources...
9295 16:30:48.907250 Root Device read_resources bus 0 link: 0
9296 16:30:48.910849 DRAM rank0 size:0x100000000,
9297 16:30:48.911474 DRAM rank1 size=0x100000000
9298 16:30:48.917465 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9299 16:30:48.917888 CPU: 00 missing read_resources
9300 16:30:48.923971 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9301 16:30:48.927217 Root Device read_resources bus 0 link: 0 done
9302 16:30:48.930233 Done reading resources.
9303 16:30:48.933528 Show resources in subtree (Root Device)...After reading.
9304 16:30:48.936666 Root Device child on link 0 CPU_CLUSTER: 0
9305 16:30:48.940416 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 16:30:48.949781 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 16:30:48.950316 CPU: 00
9308 16:30:48.957079 Root Device assign_resources, bus 0 link: 0
9309 16:30:48.960101 CPU_CLUSTER: 0 missing set_resources
9310 16:30:48.963168 Root Device assign_resources, bus 0 link: 0 done
9311 16:30:48.966240 Done setting resources.
9312 16:30:48.969766 Show resources in subtree (Root Device)...After assigning values.
9313 16:30:48.976172 Root Device child on link 0 CPU_CLUSTER: 0
9314 16:30:48.980001 CPU_CLUSTER: 0 child on link 0 CPU: 00
9315 16:30:48.986255 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9316 16:30:48.989496 CPU: 00
9317 16:30:48.989958 Done allocating resources.
9318 16:30:48.995720 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9319 16:30:48.999132 Enabling resources...
9320 16:30:48.999686 done.
9321 16:30:49.002623 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9322 16:30:49.005925 Initializing devices...
9323 16:30:49.006474 Root Device init
9324 16:30:49.009075 init hardware done!
9325 16:30:49.012221 0x00000018: ctrlr->caps
9326 16:30:49.012770 52.000 MHz: ctrlr->f_max
9327 16:30:49.016026 0.400 MHz: ctrlr->f_min
9328 16:30:49.019118 0x40ff8080: ctrlr->voltages
9329 16:30:49.019565 sclk: 390625
9330 16:30:49.019903 Bus Width = 1
9331 16:30:49.022648 sclk: 390625
9332 16:30:49.023135 Bus Width = 1
9333 16:30:49.025682 Early init status = 3
9334 16:30:49.029004 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9335 16:30:49.032453 in-header: 03 fc 00 00 01 00 00 00
9336 16:30:49.035994 in-data: 00
9337 16:30:49.038939 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9338 16:30:49.043935 in-header: 03 fd 00 00 00 00 00 00
9339 16:30:49.047533 in-data:
9340 16:30:49.050623 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9341 16:30:49.054629 in-header: 03 fc 00 00 01 00 00 00
9342 16:30:49.057865 in-data: 00
9343 16:30:49.061753 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9344 16:30:49.067058 in-header: 03 fd 00 00 00 00 00 00
9345 16:30:49.070114 in-data:
9346 16:30:49.073757 [SSUSB] Setting up USB HOST controller...
9347 16:30:49.077400 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9348 16:30:49.080545 [SSUSB] phy power-on done.
9349 16:30:49.083755 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9350 16:30:49.089843 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9351 16:30:49.093188 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9352 16:30:49.099936 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9353 16:30:49.106404 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9354 16:30:49.113449 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9355 16:30:49.119797 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9356 16:30:49.126713 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9357 16:30:49.129878 SPM: binary array size = 0x9dc
9358 16:30:49.133206 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9359 16:30:49.139672 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9360 16:30:49.146048 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9361 16:30:49.152949 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9362 16:30:49.155780 configure_display: Starting display init
9363 16:30:49.190029 anx7625_power_on_init: Init interface.
9364 16:30:49.193885 anx7625_disable_pd_protocol: Disabled PD feature.
9365 16:30:49.197114 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9366 16:30:49.224533 anx7625_start_dp_work: Secure OCM version=00
9367 16:30:49.228165 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9368 16:30:49.242613 sp_tx_get_edid_block: EDID Block = 1
9369 16:30:49.345455 Extracted contents:
9370 16:30:49.348658 header: 00 ff ff ff ff ff ff 00
9371 16:30:49.352379 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9372 16:30:49.356000 version: 01 04
9373 16:30:49.358637 basic params: 95 1f 11 78 0a
9374 16:30:49.361792 chroma info: 76 90 94 55 54 90 27 21 50 54
9375 16:30:49.365275 established: 00 00 00
9376 16:30:49.372237 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9377 16:30:49.378486 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9378 16:30:49.382131 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 16:30:49.388129 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9380 16:30:49.394681 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9381 16:30:49.398256 extensions: 00
9382 16:30:49.398682 checksum: fb
9383 16:30:49.399109
9384 16:30:49.401947 Manufacturer: IVO Model 57d Serial Number 0
9385 16:30:49.405209 Made week 0 of 2020
9386 16:30:49.408376 EDID version: 1.4
9387 16:30:49.408850 Digital display
9388 16:30:49.411367 6 bits per primary color channel
9389 16:30:49.411833 DisplayPort interface
9390 16:30:49.414538 Maximum image size: 31 cm x 17 cm
9391 16:30:49.418396 Gamma: 220%
9392 16:30:49.418895 Check DPMS levels
9393 16:30:49.421659 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9394 16:30:49.427965 First detailed timing is preferred timing
9395 16:30:49.428478 Established timings supported:
9396 16:30:49.431139 Standard timings supported:
9397 16:30:49.434872 Detailed timings
9398 16:30:49.438220 Hex of detail: 383680a07038204018303c0035ae10000019
9399 16:30:49.444364 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9400 16:30:49.447564 0780 0798 07c8 0820 hborder 0
9401 16:30:49.450706 0438 043b 0447 0458 vborder 0
9402 16:30:49.454495 -hsync -vsync
9403 16:30:49.455177 Did detailed timing
9404 16:30:49.460930 Hex of detail: 000000000000000000000000000000000000
9405 16:30:49.464564 Manufacturer-specified data, tag 0
9406 16:30:49.467577 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9407 16:30:49.470956 ASCII string: InfoVision
9408 16:30:49.473803 Hex of detail: 000000fe00523134304e574635205248200a
9409 16:30:49.477627 ASCII string: R140NWF5 RH
9410 16:30:49.478302 Checksum
9411 16:30:49.480828 Checksum: 0xfb (valid)
9412 16:30:49.483861 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9413 16:30:49.487699 DSI data_rate: 832800000 bps
9414 16:30:49.494149 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9415 16:30:49.497080 anx7625_parse_edid: pixelclock(138800).
9416 16:30:49.500681 hactive(1920), hsync(48), hfp(24), hbp(88)
9417 16:30:49.503865 vactive(1080), vsync(12), vfp(3), vbp(17)
9418 16:30:49.507392 anx7625_dsi_config: config dsi.
9419 16:30:49.514149 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9420 16:30:49.527519 anx7625_dsi_config: success to config DSI
9421 16:30:49.530831 anx7625_dp_start: MIPI phy setup OK.
9422 16:30:49.534229 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9423 16:30:49.537306 mtk_ddp_mode_set invalid vrefresh 60
9424 16:30:49.540468 main_disp_path_setup
9425 16:30:49.540885 ovl_layer_smi_id_en
9426 16:30:49.543619 ovl_layer_smi_id_en
9427 16:30:49.544075 ccorr_config
9428 16:30:49.544582 aal_config
9429 16:30:49.547014 gamma_config
9430 16:30:49.547426 postmask_config
9431 16:30:49.550804 dither_config
9432 16:30:49.553992 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9433 16:30:49.560403 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9434 16:30:49.563684 Root Device init finished in 553 msecs
9435 16:30:49.566728 CPU_CLUSTER: 0 init
9436 16:30:49.573550 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9437 16:30:49.579839 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9438 16:30:49.580256 APU_MBOX 0x190000b0 = 0x10001
9439 16:30:49.583233 APU_MBOX 0x190001b0 = 0x10001
9440 16:30:49.586372 APU_MBOX 0x190005b0 = 0x10001
9441 16:30:49.589539 APU_MBOX 0x190006b0 = 0x10001
9442 16:30:49.596637 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9443 16:30:49.606531 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9444 16:30:49.619325 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9445 16:30:49.625294 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9446 16:30:49.637031 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9447 16:30:49.646569 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9448 16:30:49.649629 CPU_CLUSTER: 0 init finished in 81 msecs
9449 16:30:49.652789 Devices initialized
9450 16:30:49.656119 Show all devs... After init.
9451 16:30:49.656559 Root Device: enabled 1
9452 16:30:49.659334 CPU_CLUSTER: 0: enabled 1
9453 16:30:49.663206 CPU: 00: enabled 1
9454 16:30:49.666274 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9455 16:30:49.669838 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9456 16:30:49.672940 ELOG: NV offset 0x57f000 size 0x1000
9457 16:30:49.679417 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9458 16:30:49.685819 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9459 16:30:49.689481 ELOG: Event(17) added with size 13 at 2024-06-17 16:30:49 UTC
9460 16:30:49.693056 out: cmd=0x121: 03 db 21 01 00 00 00 00
9461 16:30:49.697407 in-header: 03 8b 00 00 2c 00 00 00
9462 16:30:49.710424 in-data: b3 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9463 16:30:49.717016 ELOG: Event(A1) added with size 10 at 2024-06-17 16:30:49 UTC
9464 16:30:49.724081 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9465 16:30:49.729892 ELOG: Event(A0) added with size 9 at 2024-06-17 16:30:49 UTC
9466 16:30:49.733630 elog_add_boot_reason: Logged dev mode boot
9467 16:30:49.736885 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9468 16:30:49.740482 Finalize devices...
9469 16:30:49.740910 Devices finalized
9470 16:30:49.746789 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9471 16:30:49.749887 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9472 16:30:49.753205 in-header: 03 07 00 00 08 00 00 00
9473 16:30:49.756493 in-data: aa e4 47 04 13 02 00 00
9474 16:30:49.759767 Chrome EC: UHEPI supported
9475 16:30:49.766698 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9476 16:30:49.769838 in-header: 03 a9 00 00 08 00 00 00
9477 16:30:49.773031 in-data: 84 60 60 08 00 00 00 00
9478 16:30:49.776210 ELOG: Event(91) added with size 10 at 2024-06-17 16:30:49 UTC
9479 16:30:49.783101 Chrome EC: clear events_b mask to 0x0000000020004000
9480 16:30:49.789545 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9481 16:30:49.793233 in-header: 03 fd 00 00 00 00 00 00
9482 16:30:49.793697 in-data:
9483 16:30:49.799768 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9484 16:30:49.802749 Writing coreboot table at 0xffe64000
9485 16:30:49.806305 0. 000000000010a000-0000000000113fff: RAMSTAGE
9486 16:30:49.809409 1. 0000000040000000-00000000400fffff: RAM
9487 16:30:49.816240 2. 0000000040100000-000000004032afff: RAMSTAGE
9488 16:30:49.819755 3. 000000004032b000-00000000545fffff: RAM
9489 16:30:49.822661 4. 0000000054600000-000000005465ffff: BL31
9490 16:30:49.825948 5. 0000000054660000-00000000ffe63fff: RAM
9491 16:30:49.832302 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9492 16:30:49.835889 7. 0000000100000000-000000023fffffff: RAM
9493 16:30:49.839159 Passing 5 GPIOs to payload:
9494 16:30:49.842310 NAME | PORT | POLARITY | VALUE
9495 16:30:49.845380 EC in RW | 0x000000aa | low | undefined
9496 16:30:49.852036 EC interrupt | 0x00000005 | low | undefined
9497 16:30:49.855360 TPM interrupt | 0x000000ab | high | undefined
9498 16:30:49.861974 SD card detect | 0x00000011 | high | undefined
9499 16:30:49.865840 speaker enable | 0x00000093 | high | undefined
9500 16:30:49.868917 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9501 16:30:49.872286 in-header: 03 f9 00 00 02 00 00 00
9502 16:30:49.875369 in-data: 02 00
9503 16:30:49.875796 ADC[4]: Raw value=903400 ID=7
9504 16:30:49.878569 ADC[3]: Raw value=213282 ID=1
9505 16:30:49.881808 RAM Code: 0x71
9506 16:30:49.885493 ADC[6]: Raw value=74667 ID=0
9507 16:30:49.885924 ADC[5]: Raw value=214021 ID=1
9508 16:30:49.888644 SKU Code: 0x1
9509 16:30:49.891735 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b353
9510 16:30:49.895096 coreboot table: 964 bytes.
9511 16:30:49.898300 IMD ROOT 0. 0xfffff000 0x00001000
9512 16:30:49.902062 IMD SMALL 1. 0xffffe000 0x00001000
9513 16:30:49.905134 RO MCACHE 2. 0xffffc000 0x00001104
9514 16:30:49.908598 CONSOLE 3. 0xfff7c000 0x00080000
9515 16:30:49.911857 FMAP 4. 0xfff7b000 0x00000452
9516 16:30:49.914984 TIME STAMP 5. 0xfff7a000 0x00000910
9517 16:30:49.918254 VBOOT WORK 6. 0xfff66000 0x00014000
9518 16:30:49.921834 RAMOOPS 7. 0xffe66000 0x00100000
9519 16:30:49.924946 COREBOOT 8. 0xffe64000 0x00002000
9520 16:30:49.928434 IMD small region:
9521 16:30:49.931613 IMD ROOT 0. 0xffffec00 0x00000400
9522 16:30:49.934845 VPD 1. 0xffffeb80 0x0000006c
9523 16:30:49.937672 MMC STATUS 2. 0xffffeb60 0x00000004
9524 16:30:49.941214 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9525 16:30:49.948103 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9526 16:30:49.988592 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9527 16:30:49.992397 Checking segment from ROM address 0x40100000
9528 16:30:49.998607 Checking segment from ROM address 0x4010001c
9529 16:30:50.001673 Loading segment from ROM address 0x40100000
9530 16:30:50.002100 code (compression=0)
9531 16:30:50.012028 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9532 16:30:50.018457 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9533 16:30:50.018882 it's not compressed!
9534 16:30:50.025015 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9535 16:30:50.031511 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9536 16:30:50.049255 Loading segment from ROM address 0x4010001c
9537 16:30:50.049842 Entry Point 0x80000000
9538 16:30:50.052330 Loaded segments
9539 16:30:50.055853 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9540 16:30:50.061958 Jumping to boot code at 0x80000000(0xffe64000)
9541 16:30:50.068759 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9542 16:30:50.075349 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9543 16:30:50.083391 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9544 16:30:50.086655 Checking segment from ROM address 0x40100000
9545 16:30:50.089781 Checking segment from ROM address 0x4010001c
9546 16:30:50.096770 Loading segment from ROM address 0x40100000
9547 16:30:50.096867 code (compression=1)
9548 16:30:50.102992 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9549 16:30:50.113151 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9550 16:30:50.113267 using LZMA
9551 16:30:50.121780 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9552 16:30:50.128406 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9553 16:30:50.131751 Loading segment from ROM address 0x4010001c
9554 16:30:50.131846 Entry Point 0x54601000
9555 16:30:50.134729 Loaded segments
9556 16:30:50.138114 NOTICE: MT8192 bl31_setup
9557 16:30:50.145380 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9558 16:30:50.148637 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9559 16:30:50.151848 WARNING: region 0:
9560 16:30:50.155729 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9561 16:30:50.155815 WARNING: region 1:
9562 16:30:50.161792 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9563 16:30:50.164816 WARNING: region 2:
9564 16:30:50.168249 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9565 16:30:50.171767 WARNING: region 3:
9566 16:30:50.174878 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9567 16:30:50.178440 WARNING: region 4:
9568 16:30:50.184991 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9569 16:30:50.185114 WARNING: region 5:
9570 16:30:50.188008 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9571 16:30:50.191724 WARNING: region 6:
9572 16:30:50.194945 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9573 16:30:50.198012 WARNING: region 7:
9574 16:30:50.201294 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9575 16:30:50.207826 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9576 16:30:50.211456 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9577 16:30:50.217896 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9578 16:30:50.221161 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9579 16:30:50.224261 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9580 16:30:50.231026 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9581 16:30:50.234412 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9582 16:30:50.237515 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9583 16:30:50.244245 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9584 16:30:50.247753 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9585 16:30:50.254559 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9586 16:30:50.257681 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9587 16:30:50.260885 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9588 16:30:50.267928 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9589 16:30:50.270976 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9590 16:30:50.274135 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9591 16:30:50.280913 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9592 16:30:50.283963 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9593 16:30:50.290678 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9594 16:30:50.293715 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9595 16:30:50.297171 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9596 16:30:50.304055 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9597 16:30:50.307263 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9598 16:30:50.313682 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9599 16:30:50.316843 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9600 16:30:50.320276 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9601 16:30:50.327197 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9602 16:30:50.330590 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9603 16:30:50.336918 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9604 16:30:50.339907 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9605 16:30:50.346529 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9606 16:30:50.350061 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9607 16:30:50.353299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9608 16:30:50.356503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9609 16:30:50.363428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9610 16:30:50.366607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9611 16:30:50.369903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9612 16:30:50.373040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9613 16:30:50.379937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9614 16:30:50.383010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9615 16:30:50.386423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9616 16:30:50.389648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9617 16:30:50.396545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9618 16:30:50.399586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9619 16:30:50.402640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9620 16:30:50.409088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9621 16:30:50.412863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9622 16:30:50.416178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9623 16:30:50.419341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9624 16:30:50.425850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9625 16:30:50.429100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9626 16:30:50.435939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9627 16:30:50.439197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9628 16:30:50.445585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9629 16:30:50.449101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9630 16:30:50.455437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9631 16:30:50.458661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9632 16:30:50.462097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9633 16:30:50.468960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9634 16:30:50.472239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9635 16:30:50.479154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9636 16:30:50.482125 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9637 16:30:50.488543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9638 16:30:50.492059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9639 16:30:50.498447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9640 16:30:50.501993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9641 16:30:50.505373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9642 16:30:50.511970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9643 16:30:50.515012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9644 16:30:50.521985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9645 16:30:50.525180 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9646 16:30:50.531453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9647 16:30:50.534754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9648 16:30:50.541210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9649 16:30:50.545010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9650 16:30:50.548025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9651 16:30:50.555112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9652 16:30:50.558309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9653 16:30:50.564769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9654 16:30:50.567834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9655 16:30:50.574982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9656 16:30:50.578274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9657 16:30:50.584556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9658 16:30:50.587784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9659 16:30:50.591120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9660 16:30:50.597970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9661 16:30:50.600768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9662 16:30:50.607710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9663 16:30:50.611017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9664 16:30:50.617398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9665 16:30:50.620950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9666 16:30:50.627812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9667 16:30:50.630657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9668 16:30:50.634349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9669 16:30:50.640844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9670 16:30:50.644105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9671 16:30:50.650482 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9672 16:30:50.654331 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9673 16:30:50.657355 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9674 16:30:50.660711 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9675 16:30:50.666951 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9676 16:30:50.670500 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9677 16:30:50.677071 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9678 16:30:50.680238 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9679 16:30:50.683813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9680 16:30:50.690047 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9681 16:30:50.693904 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9682 16:30:50.700302 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9683 16:30:50.703340 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9684 16:30:50.706925 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9685 16:30:50.713595 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9686 16:30:50.716850 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9687 16:30:50.723291 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9688 16:30:50.726722 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9689 16:30:50.729694 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9690 16:30:50.736333 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9691 16:30:50.739743 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9692 16:30:50.743288 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9693 16:30:50.749664 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9694 16:30:50.752921 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9695 16:30:50.756121 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9696 16:30:50.759978 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9697 16:30:50.766216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9698 16:30:50.769761 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9699 16:30:50.772830 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9700 16:30:50.779649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9701 16:30:50.782893 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9702 16:30:50.789602 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9703 16:30:50.792518 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9704 16:30:50.796051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9705 16:30:50.802471 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9706 16:30:50.805919 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9707 16:30:50.812155 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9708 16:30:50.815701 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9709 16:30:50.819247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9710 16:30:50.825726 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9711 16:30:50.829010 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9712 16:30:50.835296 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9713 16:30:50.838510 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9714 16:30:50.842319 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9715 16:30:50.848917 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9716 16:30:50.852327 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9717 16:30:50.858662 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9718 16:30:50.861843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9719 16:30:50.865017 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9720 16:30:50.872066 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9721 16:30:50.875241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9722 16:30:50.881944 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9723 16:30:50.885131 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9724 16:30:50.888542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9725 16:30:50.894733 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9726 16:30:50.897953 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9727 16:30:50.904845 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9728 16:30:50.907940 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9729 16:30:50.911476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9730 16:30:50.918081 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9731 16:30:50.921419 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9732 16:30:50.927804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9733 16:30:50.931513 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9734 16:30:50.934751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9735 16:30:50.941051 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9736 16:30:50.944365 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9737 16:30:50.951208 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9738 16:30:50.954310 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9739 16:30:50.957988 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9740 16:30:50.964490 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9741 16:30:50.967836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9742 16:30:50.974039 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9743 16:30:50.977299 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9744 16:30:50.981194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9745 16:30:50.987672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9746 16:30:50.990782 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9747 16:30:50.993910 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9748 16:30:51.000352 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9749 16:30:51.004195 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9750 16:30:51.010269 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9751 16:30:51.013559 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9752 16:30:51.020319 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9753 16:30:51.023647 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9754 16:30:51.027269 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9755 16:30:51.033555 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9756 16:30:51.037102 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9757 16:30:51.043812 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9758 16:30:51.046883 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9759 16:30:51.050063 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9760 16:30:51.057142 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9761 16:30:51.060357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9762 16:30:51.066322 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9763 16:30:51.069826 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9764 16:30:51.073042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9765 16:30:51.079919 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9766 16:30:51.083009 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9767 16:30:51.090018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9768 16:30:51.092983 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9769 16:30:51.096436 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9770 16:30:51.103006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9771 16:30:51.106139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9772 16:30:51.112945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9773 16:30:51.116267 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9774 16:30:51.122482 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9775 16:30:51.125737 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9776 16:30:51.132167 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9777 16:30:51.136018 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9778 16:30:51.139077 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9779 16:30:51.145988 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9780 16:30:51.148705 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9781 16:30:51.155769 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9782 16:30:51.159003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9783 16:30:51.162060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9784 16:30:51.168629 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9785 16:30:51.172259 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9786 16:30:51.178705 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9787 16:30:51.181939 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9788 16:30:51.188897 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9789 16:30:51.191555 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9790 16:30:51.195379 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9791 16:30:51.201672 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9792 16:30:51.204964 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9793 16:30:51.211562 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9794 16:30:51.215273 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9795 16:30:51.221557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9796 16:30:51.224807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9797 16:30:51.227920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9798 16:30:51.234932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9799 16:30:51.237916 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9800 16:30:51.244495 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9801 16:30:51.247800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9802 16:30:51.254680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9803 16:30:51.257689 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9804 16:30:51.260623 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9805 16:30:51.267610 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9806 16:30:51.270595 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9807 16:30:51.274415 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9808 16:30:51.277044 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9809 16:30:51.283818 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9810 16:30:51.287293 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9811 16:30:51.290299 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9812 16:30:51.297364 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9813 16:30:51.300706 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9814 16:30:51.303808 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9815 16:30:51.310307 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9816 16:30:51.313777 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9817 16:30:51.320191 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9818 16:30:51.323794 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9819 16:30:51.326908 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9820 16:30:51.333527 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9821 16:30:51.336879 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9822 16:30:51.343588 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9823 16:30:51.346607 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9824 16:30:51.350107 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9825 16:30:51.356561 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9826 16:30:51.360349 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9827 16:30:51.363341 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9828 16:30:51.370169 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9829 16:30:51.373423 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9830 16:30:51.377017 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9831 16:30:51.383241 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9832 16:30:51.386442 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9833 16:30:51.390144 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9834 16:30:51.396543 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9835 16:30:51.399476 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9836 16:30:51.405935 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9837 16:30:51.409785 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9838 16:30:51.413056 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9839 16:30:51.419825 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9840 16:30:51.422826 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9841 16:30:51.429496 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9842 16:30:51.432595 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9843 16:30:51.435749 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9844 16:30:51.439510 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9845 16:30:51.445787 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9846 16:30:51.449457 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9847 16:30:51.452440 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9848 16:30:51.455999 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9849 16:30:51.462225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9850 16:30:51.465614 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9851 16:30:51.468686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9852 16:30:51.472327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9853 16:30:51.478818 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9854 16:30:51.482685 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9855 16:30:51.485586 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9856 16:30:51.488776 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9857 16:30:51.495646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9858 16:30:51.498957 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9859 16:30:51.505260 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9860 16:30:51.508431 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9861 16:30:51.515319 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9862 16:30:51.518500 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9863 16:30:51.525385 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9864 16:30:51.528516 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9865 16:30:51.531809 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9866 16:30:51.538310 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9867 16:30:51.541835 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9868 16:30:51.548089 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9869 16:30:51.551315 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9870 16:30:51.554980 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9871 16:30:51.561305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9872 16:30:51.564476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9873 16:30:51.571355 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9874 16:30:51.574386 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9875 16:30:51.577603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9876 16:30:51.584670 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9877 16:30:51.587663 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9878 16:30:51.594391 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9879 16:30:51.597537 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9880 16:30:51.601279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9881 16:30:51.607636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9882 16:30:51.611355 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9883 16:30:51.617640 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9884 16:30:51.620825 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9885 16:30:51.627722 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9886 16:30:51.630841 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9887 16:30:51.637314 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9888 16:30:51.640922 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9889 16:30:51.643930 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9890 16:30:51.650821 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9891 16:30:51.654022 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9892 16:30:51.660260 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9893 16:30:51.664006 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9894 16:30:51.666870 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9895 16:30:51.673826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9896 16:30:51.676813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9897 16:30:51.683539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9898 16:30:51.686842 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9899 16:30:51.690020 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9900 16:30:51.696960 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9901 16:30:51.700073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9902 16:30:51.706899 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9903 16:30:51.710089 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9904 16:30:51.713393 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9905 16:30:51.719635 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9906 16:30:51.723018 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9907 16:30:51.729923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9908 16:30:51.733129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9909 16:30:51.739290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9910 16:30:51.742989 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9911 16:30:51.749991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9912 16:30:51.752550 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9913 16:30:51.756283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9914 16:30:51.762571 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9915 16:30:51.765791 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9916 16:30:51.772593 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9917 16:30:51.775578 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9918 16:30:51.778975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9919 16:30:51.785763 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9920 16:30:51.789238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9921 16:30:51.795675 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9922 16:30:51.798789 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9923 16:30:51.802582 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9924 16:30:51.808763 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9925 16:30:51.812376 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9926 16:30:51.818760 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9927 16:30:51.822028 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9928 16:30:51.825728 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9929 16:30:51.832388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9930 16:30:51.835688 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9931 16:30:51.841902 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9932 16:30:51.845818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9933 16:30:51.852088 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9934 16:30:51.855703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9935 16:30:51.862066 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9936 16:30:51.865072 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9937 16:30:51.868895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9938 16:30:51.875287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9939 16:30:51.878831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9940 16:30:51.885330 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9941 16:30:51.888449 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9942 16:30:51.895324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9943 16:30:51.898543 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9944 16:30:51.901710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9945 16:30:51.908174 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9946 16:30:51.911984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9947 16:30:51.918119 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9948 16:30:51.921811 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9949 16:30:51.927925 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9950 16:30:51.931232 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9951 16:30:51.938106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9952 16:30:51.941067 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9953 16:30:51.944611 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9954 16:30:51.951183 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9955 16:30:51.954780 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9956 16:30:51.960994 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9957 16:30:51.964924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9958 16:30:51.971022 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9959 16:30:51.974245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9960 16:30:51.980634 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9961 16:30:51.984104 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9962 16:30:51.987785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9963 16:30:51.993985 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9964 16:30:51.997535 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9965 16:30:52.004035 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9966 16:30:52.007689 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9967 16:30:52.013933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9968 16:30:52.017206 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9969 16:30:52.024164 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9970 16:30:52.027281 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9971 16:30:52.030609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9972 16:30:52.037243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9973 16:30:52.040403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9974 16:30:52.046717 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9975 16:30:52.050470 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9976 16:30:52.056788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9977 16:30:52.059903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9978 16:30:52.063365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9979 16:30:52.070379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9980 16:30:52.073594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9981 16:30:52.080388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9982 16:30:52.083664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9983 16:30:52.090074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9984 16:30:52.093318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9985 16:30:52.100007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9986 16:30:52.103329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9987 16:30:52.109639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9988 16:30:52.113179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9989 16:30:52.119629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9990 16:30:52.122792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9991 16:30:52.129862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9992 16:30:52.132896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9993 16:30:52.139657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9994 16:30:52.142583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9995 16:30:52.149308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9996 16:30:52.153097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9997 16:30:52.159571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9998 16:30:52.162803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9999 16:30:52.169163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10000 16:30:52.172547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10001 16:30:52.179133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10002 16:30:52.182693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10003 16:30:52.189176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10004 16:30:52.192335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10005 16:30:52.198796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10006 16:30:52.202063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10007 16:30:52.208914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10008 16:30:52.212083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10009 16:30:52.218715 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10010 16:30:52.218799 INFO: [APUAPC] vio 0
10011 16:30:52.225186 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10012 16:30:52.228441 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10013 16:30:52.232293 INFO: [APUAPC] D0_APC_0: 0x400510
10014 16:30:52.235360 INFO: [APUAPC] D0_APC_1: 0x0
10015 16:30:52.238413 INFO: [APUAPC] D0_APC_2: 0x1540
10016 16:30:52.241668 INFO: [APUAPC] D0_APC_3: 0x0
10017 16:30:52.244841 INFO: [APUAPC] D1_APC_0: 0xffffffff
10018 16:30:52.248639 INFO: [APUAPC] D1_APC_1: 0xffffffff
10019 16:30:52.251592 INFO: [APUAPC] D1_APC_2: 0x3fffff
10020 16:30:52.255075 INFO: [APUAPC] D1_APC_3: 0x0
10021 16:30:52.258307 INFO: [APUAPC] D2_APC_0: 0xffffffff
10022 16:30:52.261458 INFO: [APUAPC] D2_APC_1: 0xffffffff
10023 16:30:52.265295 INFO: [APUAPC] D2_APC_2: 0x3fffff
10024 16:30:52.268427 INFO: [APUAPC] D2_APC_3: 0x0
10025 16:30:52.271308 INFO: [APUAPC] D3_APC_0: 0xffffffff
10026 16:30:52.274595 INFO: [APUAPC] D3_APC_1: 0xffffffff
10027 16:30:52.278147 INFO: [APUAPC] D3_APC_2: 0x3fffff
10028 16:30:52.281328 INFO: [APUAPC] D3_APC_3: 0x0
10029 16:30:52.284898 INFO: [APUAPC] D4_APC_0: 0xffffffff
10030 16:30:52.287775 INFO: [APUAPC] D4_APC_1: 0xffffffff
10031 16:30:52.291118 INFO: [APUAPC] D4_APC_2: 0x3fffff
10032 16:30:52.294582 INFO: [APUAPC] D4_APC_3: 0x0
10033 16:30:52.297684 INFO: [APUAPC] D5_APC_0: 0xffffffff
10034 16:30:52.300824 INFO: [APUAPC] D5_APC_1: 0xffffffff
10035 16:30:52.304726 INFO: [APUAPC] D5_APC_2: 0x3fffff
10036 16:30:52.304809 INFO: [APUAPC] D5_APC_3: 0x0
10037 16:30:52.311236 INFO: [APUAPC] D6_APC_0: 0xffffffff
10038 16:30:52.314495 INFO: [APUAPC] D6_APC_1: 0xffffffff
10039 16:30:52.317482 INFO: [APUAPC] D6_APC_2: 0x3fffff
10040 16:30:52.317581 INFO: [APUAPC] D6_APC_3: 0x0
10041 16:30:52.320732 INFO: [APUAPC] D7_APC_0: 0xffffffff
10042 16:30:52.327395 INFO: [APUAPC] D7_APC_1: 0xffffffff
10043 16:30:52.330660 INFO: [APUAPC] D7_APC_2: 0x3fffff
10044 16:30:52.330736 INFO: [APUAPC] D7_APC_3: 0x0
10045 16:30:52.334036 INFO: [APUAPC] D8_APC_0: 0xffffffff
10046 16:30:52.337267 INFO: [APUAPC] D8_APC_1: 0xffffffff
10047 16:30:52.340827 INFO: [APUAPC] D8_APC_2: 0x3fffff
10048 16:30:52.344395 INFO: [APUAPC] D8_APC_3: 0x0
10049 16:30:52.347761 INFO: [APUAPC] D9_APC_0: 0xffffffff
10050 16:30:52.350937 INFO: [APUAPC] D9_APC_1: 0xffffffff
10051 16:30:52.354130 INFO: [APUAPC] D9_APC_2: 0x3fffff
10052 16:30:52.357415 INFO: [APUAPC] D9_APC_3: 0x0
10053 16:30:52.360431 INFO: [APUAPC] D10_APC_0: 0xffffffff
10054 16:30:52.364068 INFO: [APUAPC] D10_APC_1: 0xffffffff
10055 16:30:52.367367 INFO: [APUAPC] D10_APC_2: 0x3fffff
10056 16:30:52.370970 INFO: [APUAPC] D10_APC_3: 0x0
10057 16:30:52.373682 INFO: [APUAPC] D11_APC_0: 0xffffffff
10058 16:30:52.376899 INFO: [APUAPC] D11_APC_1: 0xffffffff
10059 16:30:52.380736 INFO: [APUAPC] D11_APC_2: 0x3fffff
10060 16:30:52.383819 INFO: [APUAPC] D11_APC_3: 0x0
10061 16:30:52.387070 INFO: [APUAPC] D12_APC_0: 0xffffffff
10062 16:30:52.390142 INFO: [APUAPC] D12_APC_1: 0xffffffff
10063 16:30:52.396864 INFO: [APUAPC] D12_APC_2: 0x3fffff
10064 16:30:52.396955 INFO: [APUAPC] D12_APC_3: 0x0
10065 16:30:52.400282 INFO: [APUAPC] D13_APC_0: 0xffffffff
10066 16:30:52.406927 INFO: [APUAPC] D13_APC_1: 0xffffffff
10067 16:30:52.409981 INFO: [APUAPC] D13_APC_2: 0x3fffff
10068 16:30:52.410091 INFO: [APUAPC] D13_APC_3: 0x0
10069 16:30:52.417098 INFO: [APUAPC] D14_APC_0: 0xffffffff
10070 16:30:52.420256 INFO: [APUAPC] D14_APC_1: 0xffffffff
10071 16:30:52.423394 INFO: [APUAPC] D14_APC_2: 0x3fffff
10072 16:30:52.426593 INFO: [APUAPC] D14_APC_3: 0x0
10073 16:30:52.429882 INFO: [APUAPC] D15_APC_0: 0xffffffff
10074 16:30:52.433071 INFO: [APUAPC] D15_APC_1: 0xffffffff
10075 16:30:52.436255 INFO: [APUAPC] D15_APC_2: 0x3fffff
10076 16:30:52.440004 INFO: [APUAPC] D15_APC_3: 0x0
10077 16:30:52.440088 INFO: [APUAPC] APC_CON: 0x4
10078 16:30:52.442825 INFO: [NOCDAPC] D0_APC_0: 0x0
10079 16:30:52.446089 INFO: [NOCDAPC] D0_APC_1: 0x0
10080 16:30:52.449849 INFO: [NOCDAPC] D1_APC_0: 0x0
10081 16:30:52.453064 INFO: [NOCDAPC] D1_APC_1: 0xfff
10082 16:30:52.456124 INFO: [NOCDAPC] D2_APC_0: 0x0
10083 16:30:52.459793 INFO: [NOCDAPC] D2_APC_1: 0xfff
10084 16:30:52.462929 INFO: [NOCDAPC] D3_APC_0: 0x0
10085 16:30:52.466154 INFO: [NOCDAPC] D3_APC_1: 0xfff
10086 16:30:52.469896 INFO: [NOCDAPC] D4_APC_0: 0x0
10087 16:30:52.469979 INFO: [NOCDAPC] D4_APC_1: 0xfff
10088 16:30:52.472786 INFO: [NOCDAPC] D5_APC_0: 0x0
10089 16:30:52.476113 INFO: [NOCDAPC] D5_APC_1: 0xfff
10090 16:30:52.479261 INFO: [NOCDAPC] D6_APC_0: 0x0
10091 16:30:52.482468 INFO: [NOCDAPC] D6_APC_1: 0xfff
10092 16:30:52.486309 INFO: [NOCDAPC] D7_APC_0: 0x0
10093 16:30:52.489547 INFO: [NOCDAPC] D7_APC_1: 0xfff
10094 16:30:52.492803 INFO: [NOCDAPC] D8_APC_0: 0x0
10095 16:30:52.496055 INFO: [NOCDAPC] D8_APC_1: 0xfff
10096 16:30:52.499087 INFO: [NOCDAPC] D9_APC_0: 0x0
10097 16:30:52.502336 INFO: [NOCDAPC] D9_APC_1: 0xfff
10098 16:30:52.506060 INFO: [NOCDAPC] D10_APC_0: 0x0
10099 16:30:52.506144 INFO: [NOCDAPC] D10_APC_1: 0xfff
10100 16:30:52.508967 INFO: [NOCDAPC] D11_APC_0: 0x0
10101 16:30:52.512402 INFO: [NOCDAPC] D11_APC_1: 0xfff
10102 16:30:52.515745 INFO: [NOCDAPC] D12_APC_0: 0x0
10103 16:30:52.519243 INFO: [NOCDAPC] D12_APC_1: 0xfff
10104 16:30:52.522360 INFO: [NOCDAPC] D13_APC_0: 0x0
10105 16:30:52.525640 INFO: [NOCDAPC] D13_APC_1: 0xfff
10106 16:30:52.528885 INFO: [NOCDAPC] D14_APC_0: 0x0
10107 16:30:52.532611 INFO: [NOCDAPC] D14_APC_1: 0xfff
10108 16:30:52.535933 INFO: [NOCDAPC] D15_APC_0: 0x0
10109 16:30:52.539227 INFO: [NOCDAPC] D15_APC_1: 0xfff
10110 16:30:52.542136 INFO: [NOCDAPC] APC_CON: 0x4
10111 16:30:52.545515 INFO: [APUAPC] set_apusys_apc done
10112 16:30:52.548758 INFO: [DEVAPC] devapc_init done
10113 16:30:52.552451 INFO: GICv3 without legacy support detected.
10114 16:30:52.555364 INFO: ARM GICv3 driver initialized in EL3
10115 16:30:52.558822 INFO: Maximum SPI INTID supported: 639
10116 16:30:52.562667 INFO: BL31: Initializing runtime services
10117 16:30:52.568453 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10118 16:30:52.572112 INFO: SPM: enable CPC mode
10119 16:30:52.578303 INFO: mcdi ready for mcusys-off-idle and system suspend
10120 16:30:52.582047 INFO: BL31: Preparing for EL3 exit to normal world
10121 16:30:52.585070 INFO: Entry point address = 0x80000000
10122 16:30:52.588740 INFO: SPSR = 0x8
10123 16:30:52.593397
10124 16:30:52.593481
10125 16:30:52.593547
10126 16:30:52.596444 Starting depthcharge on Spherion...
10127 16:30:52.596528
10128 16:30:52.596595 Wipe memory regions:
10129 16:30:52.596656
10130 16:30:52.597255 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10131 16:30:52.597360 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10132 16:30:52.597451 Setting prompt string to ['asurada:']
10133 16:30:52.597550 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10134 16:30:52.600304 [0x00000040000000, 0x00000054600000)
10135 16:30:52.722548
10136 16:30:52.722705 [0x00000054660000, 0x00000080000000)
10137 16:30:52.982874
10138 16:30:52.983028 [0x000000821a7280, 0x000000ffe64000)
10139 16:30:53.727637
10140 16:30:53.727790 [0x00000100000000, 0x00000240000000)
10141 16:30:55.616953
10142 16:30:55.620666 Initializing XHCI USB controller at 0x11200000.
10143 16:30:56.658263
10144 16:30:56.661342 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10145 16:30:56.661434
10146 16:30:56.661499
10147 16:30:56.661781 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10149 16:30:56.762167 asurada: tftpboot 192.168.201.1 14396117/tftp-deploy-7cy_9ryj/kernel/image.itb 14396117/tftp-deploy-7cy_9ryj/kernel/cmdline
10150 16:30:56.762374 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10151 16:30:56.762458 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10152 16:30:56.767166 tftpboot 192.168.201.1 14396117/tftp-deploy-7cy_9ryj/kernel/image.itp-deploy-7cy_9ryj/kernel/cmdline
10153 16:30:56.767252
10154 16:30:56.767317 Waiting for link
10155 16:30:56.925339
10156 16:30:56.925487 R8152: Initializing
10157 16:30:56.925555
10158 16:30:56.928602 Version 6 (ocp_data = 5c30)
10159 16:30:56.928684
10160 16:30:56.931656 R8152: Done initializing
10161 16:30:56.931738
10162 16:30:56.931803 Adding net device
10163 16:30:58.837982
10164 16:30:58.838156 done.
10165 16:30:58.838249
10166 16:30:58.838311 MAC: 00:e0:4c:68:02:81
10167 16:30:58.838369
10168 16:30:58.841218 Sending DHCP discover... done.
10169 16:30:58.841306
10170 16:30:58.844804 Waiting for reply... done.
10171 16:30:58.844895
10172 16:30:58.847610 Sending DHCP request... done.
10173 16:30:58.847693
10174 16:30:58.855840 Waiting for reply... done.
10175 16:30:58.855930
10176 16:30:58.855996 My ip is 192.168.201.14
10177 16:30:58.856056
10178 16:30:58.859024 The DHCP server ip is 192.168.201.1
10179 16:30:58.859107
10180 16:30:58.865600 TFTP server IP predefined by user: 192.168.201.1
10181 16:30:58.865685
10182 16:30:58.872418 Bootfile predefined by user: 14396117/tftp-deploy-7cy_9ryj/kernel/image.itb
10183 16:30:58.872501
10184 16:30:58.875583 Sending tftp read request... done.
10185 16:30:58.875667
10186 16:30:58.879496 Waiting for the transfer...
10187 16:30:58.879578
10188 16:30:59.445495 00000000 ################################################################
10189 16:30:59.445647
10190 16:30:59.991144 00080000 ################################################################
10191 16:30:59.991307
10192 16:31:00.559199 00100000 ################################################################
10193 16:31:00.559354
10194 16:31:01.106988 00180000 ################################################################
10195 16:31:01.107155
10196 16:31:01.654526 00200000 ################################################################
10197 16:31:01.654702
10198 16:31:02.285790 00280000 ################################################################
10199 16:31:02.285943
10200 16:31:02.835890 00300000 ################################################################
10201 16:31:02.836038
10202 16:31:03.397256 00380000 ################################################################
10203 16:31:03.397423
10204 16:31:03.968383 00400000 ################################################################
10205 16:31:03.968550
10206 16:31:04.548209 00480000 ################################################################
10207 16:31:04.548355
10208 16:31:05.115997 00500000 ################################################################
10209 16:31:05.116216
10210 16:31:05.653979 00580000 ################################################################
10211 16:31:05.654145
10212 16:31:06.269037 00600000 ################################################################
10213 16:31:06.269273
10214 16:31:06.811456 00680000 ################################################################
10215 16:31:06.811620
10216 16:31:07.376168 00700000 ################################################################
10217 16:31:07.376322
10218 16:31:07.935090 00780000 ################################################################
10219 16:31:07.935243
10220 16:31:08.478544 00800000 ################################################################
10221 16:31:08.478681
10222 16:31:09.031644 00880000 ################################################################
10223 16:31:09.031835
10224 16:31:09.566934 00900000 ################################################################
10225 16:31:09.567096
10226 16:31:10.115511 00980000 ################################################################
10227 16:31:10.115652
10228 16:31:10.665571 00a00000 ################################################################
10229 16:31:10.665723
10230 16:31:11.197561 00a80000 ################################################################
10231 16:31:11.197762
10232 16:31:11.748177 00b00000 ################################################################
10233 16:31:11.748350
10234 16:31:12.303367 00b80000 ################################################################
10235 16:31:12.303519
10236 16:31:12.856677 00c00000 ################################################################
10237 16:31:12.856851
10238 16:31:13.404643 00c80000 ################################################################
10239 16:31:13.404827
10240 16:31:13.948813 00d00000 ################################################################
10241 16:31:13.949007
10242 16:31:14.487581 00d80000 ################################################################
10243 16:31:14.487734
10244 16:31:15.100362 00e00000 ################################################################
10245 16:31:15.100556
10246 16:31:15.708841 00e80000 ################################################################
10247 16:31:15.709006
10248 16:31:16.255691 00f00000 ################################################################
10249 16:31:16.255894
10250 16:31:16.795573 00f80000 ################################################################
10251 16:31:16.795743
10252 16:31:17.355710 01000000 ################################################################
10253 16:31:17.355882
10254 16:31:17.905588 01080000 ################################################################
10255 16:31:17.905739
10256 16:31:18.468034 01100000 ################################################################
10257 16:31:18.468270
10258 16:31:19.007494 01180000 ################################################################
10259 16:31:19.007665
10260 16:31:19.554685 01200000 ################################################################
10261 16:31:19.554848
10262 16:31:20.183925 01280000 ################################################################
10263 16:31:20.184081
10264 16:31:20.713122 01300000 ################################################################
10265 16:31:20.713316
10266 16:31:21.334621 01380000 ################################################################
10267 16:31:21.334811
10268 16:31:21.963322 01400000 ################################################################
10269 16:31:21.963506
10270 16:31:22.502142 01480000 ################################################################
10271 16:31:22.502304
10272 16:31:23.040505 01500000 ################################################################
10273 16:31:23.040692
10274 16:31:23.568366 01580000 ################################################################
10275 16:31:23.568554
10276 16:31:24.103701 01600000 ################################################################
10277 16:31:24.103845
10278 16:31:24.675465 01680000 ################################################################
10279 16:31:24.675612
10280 16:31:25.241606 01700000 ################################################################
10281 16:31:25.241786
10282 16:31:25.810537 01780000 ################################################################
10283 16:31:25.810713
10284 16:31:26.444529 01800000 ################################################################
10285 16:31:26.444715
10286 16:31:26.982845 01880000 ################################################################
10287 16:31:26.983015
10288 16:31:27.525879 01900000 ################################################################
10289 16:31:27.526054
10290 16:31:28.082720 01980000 ################################################################
10291 16:31:28.082874
10292 16:31:28.618496 01a00000 ################################################################
10293 16:31:28.618675
10294 16:31:29.163723 01a80000 ################################################################
10295 16:31:29.163879
10296 16:31:29.717551 01b00000 ################################################################
10297 16:31:29.717706
10298 16:31:30.269781 01b80000 ################################################################
10299 16:31:30.269964
10300 16:31:30.818100 01c00000 ################################################################
10301 16:31:30.818272
10302 16:31:31.403028 01c80000 ################################################################
10303 16:31:31.403212
10304 16:31:31.926344 01d00000 ################################################################
10305 16:31:31.926506
10306 16:31:32.534550 01d80000 ################################################################
10307 16:31:32.534724
10308 16:31:33.013360 01e00000 ########################################################## done.
10309 16:31:33.013511
10310 16:31:33.017169 The bootfile was 31926082 bytes long.
10311 16:31:33.017289
10312 16:31:33.020206 Sending tftp read request... done.
10313 16:31:33.020324
10314 16:31:33.023653 Waiting for the transfer...
10315 16:31:33.023783
10316 16:31:33.023881 00000000 # done.
10317 16:31:33.023977
10318 16:31:33.033720 Command line loaded dynamically from TFTP file: 14396117/tftp-deploy-7cy_9ryj/kernel/cmdline
10319 16:31:33.033885
10320 16:31:33.056609 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10321 16:31:33.056790
10322 16:31:33.056926 Loading FIT.
10323 16:31:33.057046
10324 16:31:33.059328 Image ramdisk-1 has 18748034 bytes.
10325 16:31:33.059438
10326 16:31:33.063219 Image fdt-1 has 47258 bytes.
10327 16:31:33.063329
10328 16:31:33.066008 Image kernel-1 has 13128753 bytes.
10329 16:31:33.066119
10330 16:31:33.072881 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10331 16:31:33.073000
10332 16:31:33.092898 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10333 16:31:33.093047
10334 16:31:33.096135 Choosing best match conf-1 for compat google,spherion-rev2.
10335 16:31:33.101071
10336 16:31:33.105045 Connected to device vid:did:rid of 1ae0:0028:00
10337 16:31:33.112370
10338 16:31:33.115594 tpm_get_response: command 0x17b, return code 0x0
10339 16:31:33.115690
10340 16:31:33.122424 ec_init: CrosEC protocol v3 supported (256, 248)
10341 16:31:33.122521
10342 16:31:33.125741 tpm_cleanup: add release locality here.
10343 16:31:33.125824
10344 16:31:33.129026 Shutting down all USB controllers.
10345 16:31:33.129118
10346 16:31:33.132211 Removing current net device
10347 16:31:33.132291
10348 16:31:33.135271 Exiting depthcharge with code 4 at timestamp: 69950057
10349 16:31:33.135388
10350 16:31:33.142430 LZMA decompressing kernel-1 to 0x821a6718
10351 16:31:33.142576
10352 16:31:33.145009 LZMA decompressing kernel-1 to 0x40000000
10353 16:31:34.760938
10354 16:31:34.761099 jumping to kernel
10355 16:31:34.761591 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10356 16:31:34.761693 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10357 16:31:34.761777 Setting prompt string to ['Linux version [0-9]']
10358 16:31:34.761847 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10359 16:31:34.761916 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10360 16:31:34.843375
10361 16:31:34.846382 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10362 16:31:34.850106 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10363 16:31:34.850271 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10364 16:31:34.850356 Setting prompt string to []
10365 16:31:34.850480 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10366 16:31:34.850588 Using line separator: #'\n'#
10367 16:31:34.850684 No login prompt set.
10368 16:31:34.850781 Parsing kernel messages
10369 16:31:34.850893 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10370 16:31:34.851085 [login-action] Waiting for messages, (timeout 00:03:45)
10371 16:31:34.851190 Waiting using forced prompt support (timeout 00:01:52)
10372 16:31:34.869402 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10373 16:31:34.872703 [ 0.000000] random: crng init done
10374 16:31:34.879580 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10375 16:31:34.882827 [ 0.000000] efi: UEFI not found.
10376 16:31:34.889033 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10377 16:31:34.898983 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10378 16:31:34.905684 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10379 16:31:34.915641 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10380 16:31:34.922427 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10381 16:31:34.928856 [ 0.000000] printk: bootconsole [mtk8250] enabled
10382 16:31:34.935040 [ 0.000000] NUMA: No NUMA configuration found
10383 16:31:34.941612 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10384 16:31:34.948182 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10385 16:31:34.948283 [ 0.000000] Zone ranges:
10386 16:31:34.955119 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10387 16:31:34.958038 [ 0.000000] DMA32 empty
10388 16:31:34.964815 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10389 16:31:34.967867 [ 0.000000] Movable zone start for each node
10390 16:31:34.971595 [ 0.000000] Early memory node ranges
10391 16:31:34.977985 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10392 16:31:34.984427 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10393 16:31:34.990886 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10394 16:31:34.997608 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10395 16:31:35.004450 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10396 16:31:35.011001 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10397 16:31:35.068024 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10398 16:31:35.074457 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10399 16:31:35.080816 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10400 16:31:35.084641 [ 0.000000] psci: probing for conduit method from DT.
10401 16:31:35.090704 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10402 16:31:35.094117 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10403 16:31:35.100603 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10404 16:31:35.104107 [ 0.000000] psci: SMC Calling Convention v1.2
10405 16:31:35.110745 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10406 16:31:35.113460 [ 0.000000] Detected VIPT I-cache on CPU0
10407 16:31:35.120136 [ 0.000000] CPU features: detected: GIC system register CPU interface
10408 16:31:35.126786 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10409 16:31:35.133584 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10410 16:31:35.140078 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10411 16:31:35.150112 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10412 16:31:35.156647 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10413 16:31:35.159951 [ 0.000000] alternatives: applying boot alternatives
10414 16:31:35.166665 [ 0.000000] Fallback order for Node 0: 0
10415 16:31:35.173130 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10416 16:31:35.176354 [ 0.000000] Policy zone: Normal
10417 16:31:35.199430 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10418 16:31:35.209678 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10419 16:31:35.221336 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10420 16:31:35.231146 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10421 16:31:35.237576 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10422 16:31:35.241277 <6>[ 0.000000] software IO TLB: area num 8.
10423 16:31:35.297614 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10424 16:31:35.446982 <6>[ 0.000000] Memory: 7945748K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407020K reserved, 32768K cma-reserved)
10425 16:31:35.453588 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10426 16:31:35.460155 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10427 16:31:35.463379 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10428 16:31:35.469734 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10429 16:31:35.476838 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10430 16:31:35.480000 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10431 16:31:35.490127 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10432 16:31:35.496214 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10433 16:31:35.503236 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10434 16:31:35.509582 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10435 16:31:35.512970 <6>[ 0.000000] GICv3: 608 SPIs implemented
10436 16:31:35.516164 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10437 16:31:35.522757 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10438 16:31:35.526236 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10439 16:31:35.532807 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10440 16:31:35.545858 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10441 16:31:35.558740 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10442 16:31:35.565288 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10443 16:31:35.573677 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10444 16:31:35.587195 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10445 16:31:35.593577 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10446 16:31:35.600143 <6>[ 0.009182] Console: colour dummy device 80x25
10447 16:31:35.609808 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10448 16:31:35.617106 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10449 16:31:35.619689 <6>[ 0.029251] LSM: Security Framework initializing
10450 16:31:35.626812 <6>[ 0.034190] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10451 16:31:35.635955 <6>[ 0.042003] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 16:31:35.645971 <6>[ 0.051434] cblist_init_generic: Setting adjustable number of callback queues.
10453 16:31:35.652528 <6>[ 0.058878] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 16:31:35.659527 <6>[ 0.065217] cblist_init_generic: Setting adjustable number of callback queues.
10455 16:31:35.665989 <6>[ 0.072643] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 16:31:35.669276 <6>[ 0.079044] rcu: Hierarchical SRCU implementation.
10457 16:31:35.675633 <6>[ 0.084058] rcu: Max phase no-delay instances is 1000.
10458 16:31:35.682524 <6>[ 0.091129] EFI services will not be available.
10459 16:31:35.685569 <6>[ 0.096117] smp: Bringing up secondary CPUs ...
10460 16:31:35.694403 <6>[ 0.101170] Detected VIPT I-cache on CPU1
10461 16:31:35.701401 <6>[ 0.101242] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10462 16:31:35.707819 <6>[ 0.101274] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10463 16:31:35.711028 <6>[ 0.101611] Detected VIPT I-cache on CPU2
10464 16:31:35.720746 <6>[ 0.101664] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10465 16:31:35.727365 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10466 16:31:35.730746 <6>[ 0.101943] Detected VIPT I-cache on CPU3
10467 16:31:35.737241 <6>[ 0.101991] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10468 16:31:35.743991 <6>[ 0.102005] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10469 16:31:35.750645 <6>[ 0.102313] CPU features: detected: Spectre-v4
10470 16:31:35.754037 <6>[ 0.102319] CPU features: detected: Spectre-BHB
10471 16:31:35.757342 <6>[ 0.102324] Detected PIPT I-cache on CPU4
10472 16:31:35.763436 <6>[ 0.102382] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10473 16:31:35.770534 <6>[ 0.102399] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10474 16:31:35.777123 <6>[ 0.102693] Detected PIPT I-cache on CPU5
10475 16:31:35.783539 <6>[ 0.102756] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10476 16:31:35.789861 <6>[ 0.102772] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10477 16:31:35.793395 <6>[ 0.103054] Detected PIPT I-cache on CPU6
10478 16:31:35.800198 <6>[ 0.103119] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10479 16:31:35.809959 <6>[ 0.103135] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10480 16:31:35.813260 <6>[ 0.103430] Detected PIPT I-cache on CPU7
10481 16:31:35.819710 <6>[ 0.103494] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10482 16:31:35.826080 <6>[ 0.103510] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10483 16:31:35.829433 <6>[ 0.103557] smp: Brought up 1 node, 8 CPUs
10484 16:31:35.836098 <6>[ 0.244904] SMP: Total of 8 processors activated.
10485 16:31:35.842851 <6>[ 0.249825] CPU features: detected: 32-bit EL0 Support
10486 16:31:35.849447 <6>[ 0.255189] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10487 16:31:35.855898 <6>[ 0.263990] CPU features: detected: Common not Private translations
10488 16:31:35.862624 <6>[ 0.270465] CPU features: detected: CRC32 instructions
10489 16:31:35.869052 <6>[ 0.275817] CPU features: detected: RCpc load-acquire (LDAPR)
10490 16:31:35.872534 <6>[ 0.281777] CPU features: detected: LSE atomic instructions
10491 16:31:35.879087 <6>[ 0.287559] CPU features: detected: Privileged Access Never
10492 16:31:35.885468 <6>[ 0.293338] CPU features: detected: RAS Extension Support
10493 16:31:35.892449 <6>[ 0.298947] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10494 16:31:35.895711 <6>[ 0.306167] CPU: All CPU(s) started at EL2
10495 16:31:35.901997 <6>[ 0.310510] alternatives: applying system-wide alternatives
10496 16:31:35.912115 <6>[ 0.321296] devtmpfs: initialized
10497 16:31:35.927812 <6>[ 0.330150] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10498 16:31:35.934237 <6>[ 0.340114] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10499 16:31:35.940840 <6>[ 0.348136] pinctrl core: initialized pinctrl subsystem
10500 16:31:35.944564 <6>[ 0.354827] DMI not present or invalid.
10501 16:31:35.950657 <6>[ 0.359240] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10502 16:31:35.960715 <6>[ 0.366105] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10503 16:31:35.967283 <6>[ 0.373693] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10504 16:31:35.977125 <6>[ 0.381918] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10505 16:31:35.980594 <6>[ 0.390160] audit: initializing netlink subsys (disabled)
10506 16:31:35.990150 <5>[ 0.395853] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10507 16:31:35.996686 <6>[ 0.396574] thermal_sys: Registered thermal governor 'step_wise'
10508 16:31:36.003838 <6>[ 0.403819] thermal_sys: Registered thermal governor 'power_allocator'
10509 16:31:36.006922 <6>[ 0.410074] cpuidle: using governor menu
10510 16:31:36.013472 <6>[ 0.421032] NET: Registered PF_QIPCRTR protocol family
10511 16:31:36.019868 <6>[ 0.426516] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10512 16:31:36.026434 <6>[ 0.433620] ASID allocator initialised with 32768 entries
10513 16:31:36.029725 <6>[ 0.440218] Serial: AMBA PL011 UART driver
10514 16:31:36.040032 <4>[ 0.449077] Trying to register duplicate clock ID: 134
10515 16:31:36.098271 <6>[ 0.510636] KASLR enabled
10516 16:31:36.112907 <6>[ 0.518360] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10517 16:31:36.119595 <6>[ 0.525372] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10518 16:31:36.126012 <6>[ 0.531861] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10519 16:31:36.132498 <6>[ 0.538865] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10520 16:31:36.138843 <6>[ 0.545352] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10521 16:31:36.145507 <6>[ 0.552358] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10522 16:31:36.151830 <6>[ 0.558845] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10523 16:31:36.158436 <6>[ 0.565850] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10524 16:31:36.161663 <6>[ 0.573389] ACPI: Interpreter disabled.
10525 16:31:36.170850 <6>[ 0.579819] iommu: Default domain type: Translated
10526 16:31:36.177057 <6>[ 0.584932] iommu: DMA domain TLB invalidation policy: strict mode
10527 16:31:36.180470 <5>[ 0.591590] SCSI subsystem initialized
10528 16:31:36.186951 <6>[ 0.595757] usbcore: registered new interface driver usbfs
10529 16:31:36.193498 <6>[ 0.601490] usbcore: registered new interface driver hub
10530 16:31:36.196705 <6>[ 0.607041] usbcore: registered new device driver usb
10531 16:31:36.204357 <6>[ 0.613138] pps_core: LinuxPPS API ver. 1 registered
10532 16:31:36.213742 <6>[ 0.618331] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10533 16:31:36.217547 <6>[ 0.627679] PTP clock support registered
10534 16:31:36.220890 <6>[ 0.631921] EDAC MC: Ver: 3.0.0
10535 16:31:36.227930 <6>[ 0.637057] FPGA manager framework
10536 16:31:36.234496 <6>[ 0.640743] Advanced Linux Sound Architecture Driver Initialized.
10537 16:31:36.238077 <6>[ 0.647514] vgaarb: loaded
10538 16:31:36.244752 <6>[ 0.650675] clocksource: Switched to clocksource arch_sys_counter
10539 16:31:36.247952 <5>[ 0.657112] VFS: Disk quotas dquot_6.6.0
10540 16:31:36.254621 <6>[ 0.661300] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10541 16:31:36.257732 <6>[ 0.668490] pnp: PnP ACPI: disabled
10542 16:31:36.266126 <6>[ 0.675224] NET: Registered PF_INET protocol family
10543 16:31:36.275934 <6>[ 0.680819] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10544 16:31:36.287707 <6>[ 0.693164] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10545 16:31:36.297520 <6>[ 0.701978] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10546 16:31:36.303959 <6>[ 0.709952] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10547 16:31:36.310953 <6>[ 0.718653] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10548 16:31:36.322509 <6>[ 0.728407] TCP: Hash tables configured (established 65536 bind 65536)
10549 16:31:36.329165 <6>[ 0.735272] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10550 16:31:36.335622 <6>[ 0.742469] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 16:31:36.342129 <6>[ 0.750170] NET: Registered PF_UNIX/PF_LOCAL protocol family
10552 16:31:36.349328 <6>[ 0.756322] RPC: Registered named UNIX socket transport module.
10553 16:31:36.352699 <6>[ 0.762471] RPC: Registered udp transport module.
10554 16:31:36.358960 <6>[ 0.767404] RPC: Registered tcp transport module.
10555 16:31:36.365947 <6>[ 0.772334] RPC: Registered tcp NFSv4.1 backchannel transport module.
10556 16:31:36.369217 <6>[ 0.779003] PCI: CLS 0 bytes, default 64
10557 16:31:36.371694 <6>[ 0.783334] Unpacking initramfs...
10558 16:31:36.397248 <6>[ 0.802790] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10559 16:31:36.406865 <6>[ 0.811437] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10560 16:31:36.410129 <6>[ 0.820270] kvm [1]: IPA Size Limit: 40 bits
10561 16:31:36.417342 <6>[ 0.824798] kvm [1]: GICv3: no GICV resource entry
10562 16:31:36.420516 <6>[ 0.829820] kvm [1]: disabling GICv2 emulation
10563 16:31:36.427092 <6>[ 0.834510] kvm [1]: GIC system register CPU interface enabled
10564 16:31:36.430315 <6>[ 0.840670] kvm [1]: vgic interrupt IRQ18
10565 16:31:36.436800 <6>[ 0.845026] kvm [1]: VHE mode initialized successfully
10566 16:31:36.443256 <5>[ 0.851454] Initialise system trusted keyrings
10567 16:31:36.449706 <6>[ 0.856235] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10568 16:31:36.457012 <6>[ 0.866170] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10569 16:31:36.463607 <5>[ 0.872562] NFS: Registering the id_resolver key type
10570 16:31:36.467199 <5>[ 0.877866] Key type id_resolver registered
10571 16:31:36.473259 <5>[ 0.882282] Key type id_legacy registered
10572 16:31:36.479956 <6>[ 0.886560] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10573 16:31:36.486580 <6>[ 0.893481] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10574 16:31:36.492979 <6>[ 0.901202] 9p: Installing v9fs 9p2000 file system support
10575 16:31:36.530309 <5>[ 0.939181] Key type asymmetric registered
10576 16:31:36.533471 <5>[ 0.943512] Asymmetric key parser 'x509' registered
10577 16:31:36.543445 <6>[ 0.948661] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10578 16:31:36.546613 <6>[ 0.956277] io scheduler mq-deadline registered
10579 16:31:36.549833 <6>[ 0.961060] io scheduler kyber registered
10580 16:31:36.568702 <6>[ 0.978011] EINJ: ACPI disabled.
10581 16:31:36.601826 <4>[ 1.004082] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 16:31:36.611526 <4>[ 1.014713] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 16:31:36.626645 <6>[ 1.035786] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10584 16:31:36.634417 <6>[ 1.043842] printk: console [ttyS0] disabled
10585 16:31:36.662366 <6>[ 1.068469] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10586 16:31:36.669511 <6>[ 1.077944] printk: console [ttyS0] enabled
10587 16:31:36.672881 <6>[ 1.077944] printk: console [ttyS0] enabled
10588 16:31:36.679189 <6>[ 1.086839] printk: bootconsole [mtk8250] disabled
10589 16:31:36.682443 <6>[ 1.086839] printk: bootconsole [mtk8250] disabled
10590 16:31:36.689357 <6>[ 1.098084] SuperH (H)SCI(F) driver initialized
10591 16:31:36.692465 <6>[ 1.103368] msm_serial: driver initialized
10592 16:31:36.706851 <6>[ 1.112402] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10593 16:31:36.716619 <6>[ 1.120949] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10594 16:31:36.722906 <6>[ 1.129498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10595 16:31:36.733039 <6>[ 1.138125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10596 16:31:36.742727 <6>[ 1.146836] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10597 16:31:36.749172 <6>[ 1.155550] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10598 16:31:36.759554 <6>[ 1.164091] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10599 16:31:36.766028 <6>[ 1.172887] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10600 16:31:36.775833 <6>[ 1.181432] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10601 16:31:36.788238 <6>[ 1.197022] loop: module loaded
10602 16:31:36.794100 <6>[ 1.203105] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10603 16:31:36.817130 <4>[ 1.226463] mtk-pmic-keys: Failed to locate of_node [id: -1]
10604 16:31:36.823977 <6>[ 1.233340] megasas: 07.719.03.00-rc1
10605 16:31:36.833587 <6>[ 1.242968] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10606 16:31:36.840917 <6>[ 1.250048] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10607 16:31:36.857417 <6>[ 1.266602] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10608 16:31:36.918094 <6>[ 1.320561] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10609 16:31:37.159660 <6>[ 1.569119] Freeing initrd memory: 18308K
10610 16:31:37.171465 <6>[ 1.580554] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10611 16:31:37.182042 <6>[ 1.591357] tun: Universal TUN/TAP device driver, 1.6
10612 16:31:37.185622 <6>[ 1.597409] thunder_xcv, ver 1.0
10613 16:31:37.188900 <6>[ 1.600913] thunder_bgx, ver 1.0
10614 16:31:37.192285 <6>[ 1.604408] nicpf, ver 1.0
10615 16:31:37.202780 <6>[ 1.608416] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10616 16:31:37.206060 <6>[ 1.615891] hns3: Copyright (c) 2017 Huawei Corporation.
10617 16:31:37.212802 <6>[ 1.621477] hclge is initializing
10618 16:31:37.216093 <6>[ 1.625052] e1000: Intel(R) PRO/1000 Network Driver
10619 16:31:37.222738 <6>[ 1.630181] e1000: Copyright (c) 1999-2006 Intel Corporation.
10620 16:31:37.225904 <6>[ 1.636194] e1000e: Intel(R) PRO/1000 Network Driver
10621 16:31:37.232324 <6>[ 1.641410] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10622 16:31:37.239159 <6>[ 1.647596] igb: Intel(R) Gigabit Ethernet Network Driver
10623 16:31:37.245393 <6>[ 1.653246] igb: Copyright (c) 2007-2014 Intel Corporation.
10624 16:31:37.252396 <6>[ 1.659081] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10625 16:31:37.258910 <6>[ 1.665599] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10626 16:31:37.262069 <6>[ 1.672058] sky2: driver version 1.30
10627 16:31:37.268902 <6>[ 1.676991] usbcore: registered new device driver r8152-cfgselector
10628 16:31:37.275487 <6>[ 1.683525] usbcore: registered new interface driver r8152
10629 16:31:37.281892 <6>[ 1.689354] VFIO - User Level meta-driver version: 0.3
10630 16:31:37.288552 <6>[ 1.697570] usbcore: registered new interface driver usb-storage
10631 16:31:37.295169 <6>[ 1.704017] usbcore: registered new device driver onboard-usb-hub
10632 16:31:37.304003 <6>[ 1.713185] mt6397-rtc mt6359-rtc: registered as rtc0
10633 16:31:37.313818 <6>[ 1.718653] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:31:37 UTC (1718641897)
10634 16:31:37.317127 <6>[ 1.728214] i2c_dev: i2c /dev entries driver
10635 16:31:37.330888 <4>[ 1.740134] cpu cpu0: supply cpu not found, using dummy regulator
10636 16:31:37.337484 <4>[ 1.746579] cpu cpu1: supply cpu not found, using dummy regulator
10637 16:31:37.344544 <4>[ 1.752981] cpu cpu2: supply cpu not found, using dummy regulator
10638 16:31:37.350609 <4>[ 1.759378] cpu cpu3: supply cpu not found, using dummy regulator
10639 16:31:37.357236 <4>[ 1.765773] cpu cpu4: supply cpu not found, using dummy regulator
10640 16:31:37.364295 <4>[ 1.772171] cpu cpu5: supply cpu not found, using dummy regulator
10641 16:31:37.370636 <4>[ 1.778585] cpu cpu6: supply cpu not found, using dummy regulator
10642 16:31:37.377331 <4>[ 1.784983] cpu cpu7: supply cpu not found, using dummy regulator
10643 16:31:37.396746 <6>[ 1.805610] cpu cpu0: EM: created perf domain
10644 16:31:37.399810 <6>[ 1.810537] cpu cpu4: EM: created perf domain
10645 16:31:37.406888 <6>[ 1.816134] sdhci: Secure Digital Host Controller Interface driver
10646 16:31:37.413445 <6>[ 1.822568] sdhci: Copyright(c) Pierre Ossman
10647 16:31:37.420245 <6>[ 1.827528] Synopsys Designware Multimedia Card Interface Driver
10648 16:31:37.426961 <6>[ 1.834155] sdhci-pltfm: SDHCI platform and OF driver helper
10649 16:31:37.430338 <6>[ 1.834172] mmc0: CQHCI version 5.10
10650 16:31:37.436808 <6>[ 1.844321] ledtrig-cpu: registered to indicate activity on CPUs
10651 16:31:37.443350 <6>[ 1.851297] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10652 16:31:37.449875 <6>[ 1.858343] usbcore: registered new interface driver usbhid
10653 16:31:37.453068 <6>[ 1.864165] usbhid: USB HID core driver
10654 16:31:37.460069 <6>[ 1.868369] spi_master spi0: will run message pump with realtime priority
10655 16:31:37.508137 <6>[ 1.910997] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10656 16:31:37.527034 <6>[ 1.926013] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10657 16:31:37.530260 <6>[ 1.932942] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10658 16:31:37.537564 <6>[ 1.946682] cros-ec-spi spi0.0: Chrome EC device registered
10659 16:31:37.544554 <6>[ 1.952751] mmc0: Command Queue Engine enabled
10660 16:31:37.551074 <6>[ 1.957539] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10661 16:31:37.554361 <6>[ 1.965078] mmcblk0: mmc0:0001 DA4128 116 GiB
10662 16:31:37.564802 <6>[ 1.973899] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10663 16:31:37.571975 <6>[ 1.980982] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10664 16:31:37.578481 <6>[ 1.986892] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10665 16:31:37.585196 <6>[ 1.993102] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10666 16:31:37.594780 <6>[ 1.993804] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10667 16:31:37.602030 <6>[ 2.010437] NET: Registered PF_PACKET protocol family
10668 16:31:37.605211 <6>[ 2.015831] 9pnet: Installing 9P2000 support
10669 16:31:37.611645 <5>[ 2.020399] Key type dns_resolver registered
10670 16:31:37.615134 <6>[ 2.025408] registered taskstats version 1
10671 16:31:37.621611 <5>[ 2.029790] Loading compiled-in X.509 certificates
10672 16:31:37.651846 <4>[ 2.054364] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10673 16:31:37.661752 <4>[ 2.065132] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10674 16:31:37.678254 <6>[ 2.087530] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10675 16:31:37.685218 <6>[ 2.094337] xhci-mtk 11200000.usb: xHCI Host Controller
10676 16:31:37.691780 <6>[ 2.099873] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10677 16:31:37.702086 <6>[ 2.107739] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10678 16:31:37.708653 <6>[ 2.117171] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10679 16:31:37.715062 <6>[ 2.123262] xhci-mtk 11200000.usb: xHCI Host Controller
10680 16:31:37.721811 <6>[ 2.128753] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10681 16:31:37.728092 <6>[ 2.136533] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10682 16:31:37.734951 <6>[ 2.144412] hub 1-0:1.0: USB hub found
10683 16:31:37.738717 <6>[ 2.148459] hub 1-0:1.0: 1 port detected
10684 16:31:37.748447 <6>[ 2.152783] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10685 16:31:37.751542 <6>[ 2.161496] hub 2-0:1.0: USB hub found
10686 16:31:37.754897 <6>[ 2.165538] hub 2-0:1.0: 1 port detected
10687 16:31:37.763534 <6>[ 2.172616] mtk-msdc 11f70000.mmc: Got CD GPIO
10688 16:31:37.776663 <6>[ 2.182527] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10689 16:31:37.786876 <6>[ 2.190919] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10690 16:31:37.793545 <6>[ 2.199262] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10691 16:31:37.802912 <6>[ 2.207603] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10692 16:31:37.810196 <6>[ 2.215941] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10693 16:31:37.819466 <6>[ 2.224280] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10694 16:31:37.826077 <6>[ 2.232618] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10695 16:31:37.835831 <6>[ 2.240955] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10696 16:31:37.842726 <6>[ 2.249294] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10697 16:31:37.852440 <6>[ 2.257634] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10698 16:31:37.859493 <6>[ 2.265974] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10699 16:31:37.869264 <6>[ 2.274319] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10700 16:31:37.875954 <6>[ 2.282657] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10701 16:31:37.885650 <6>[ 2.290995] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10702 16:31:37.892713 <6>[ 2.299332] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10703 16:31:37.899364 <6>[ 2.308033] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10704 16:31:37.905721 <6>[ 2.315192] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10705 16:31:37.912877 <6>[ 2.321963] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10706 16:31:37.922679 <6>[ 2.328767] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10707 16:31:37.929280 <6>[ 2.335699] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10708 16:31:37.935693 <6>[ 2.342572] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10709 16:31:37.945658 <6>[ 2.351711] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10710 16:31:37.955592 <6>[ 2.360831] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10711 16:31:37.965575 <6>[ 2.370125] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10712 16:31:37.975544 <6>[ 2.379591] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10713 16:31:37.985407 <6>[ 2.389059] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10714 16:31:37.991922 <6>[ 2.398179] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10715 16:31:38.002265 <6>[ 2.407644] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10716 16:31:38.011633 <6>[ 2.416766] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10717 16:31:38.021916 <6>[ 2.426061] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10718 16:31:38.031670 <6>[ 2.436221] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10719 16:31:38.041683 <6>[ 2.447588] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10720 16:31:38.049375 <6>[ 2.458900] Trying to probe devices needed for running init ...
10721 16:31:38.060002 <3>[ 2.466196] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10722 16:31:38.168660 <6>[ 2.574977] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10723 16:31:38.323334 <6>[ 2.732862] hub 1-1:1.0: USB hub found
10724 16:31:38.326688 <6>[ 2.737378] hub 1-1:1.0: 4 ports detected
10725 16:31:38.338620 <6>[ 2.748193] hub 1-1:1.0: USB hub found
10726 16:31:38.341781 <6>[ 2.752548] hub 1-1:1.0: 4 ports detected
10727 16:31:38.448804 <6>[ 2.855153] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10728 16:31:38.475052 <6>[ 2.884736] hub 2-1:1.0: USB hub found
10729 16:31:38.478772 <6>[ 2.889231] hub 2-1:1.0: 3 ports detected
10730 16:31:38.489621 <6>[ 2.898840] hub 2-1:1.0: USB hub found
10731 16:31:38.492760 <6>[ 2.903236] hub 2-1:1.0: 3 ports detected
10732 16:31:38.660955 <6>[ 3.066967] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10733 16:31:38.792928 <6>[ 3.202304] hub 1-1.4:1.0: USB hub found
10734 16:31:38.796024 <6>[ 3.206915] hub 1-1.4:1.0: 2 ports detected
10735 16:31:38.808549 <6>[ 3.217751] hub 1-1.4:1.0: USB hub found
10736 16:31:38.811724 <6>[ 3.222269] hub 1-1.4:1.0: 2 ports detected
10737 16:31:38.872670 <6>[ 3.279053] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10738 16:31:38.981082 <6>[ 3.387395] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10739 16:31:39.013670 <4>[ 3.419516] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10740 16:31:39.023325 <4>[ 3.428616] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10741 16:31:39.058929 <6>[ 3.468090] r8152 2-1.3:1.0 eth0: v1.12.13
10742 16:31:39.112782 <6>[ 3.518715] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10743 16:31:39.304585 <6>[ 3.711009] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10744 16:31:40.664569 <6>[ 5.074518] r8152 2-1.3:1.0 eth0: carrier on
10745 16:31:43.544902 <5>[ 5.098794] Sending DHCP requests .., OK
10746 16:31:43.551854 <6>[ 7.959196] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10747 16:31:43.554566 <6>[ 7.967578] IP-Config: Complete:
10748 16:31:43.568448 <6>[ 7.971081] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10749 16:31:43.574770 <6>[ 7.981796] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10750 16:31:43.581423 <6>[ 7.990413] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10751 16:31:43.587922 <6>[ 7.990422] nameserver0=192.168.201.1
10752 16:31:43.591124 <6>[ 8.002583] clk: Disabling unused clocks
10753 16:31:43.595095 <6>[ 8.008185] ALSA device list:
10754 16:31:43.601519 <6>[ 8.011452] No soundcards found.
10755 16:31:43.609335 <6>[ 8.019193] Freeing unused kernel memory: 8512K
10756 16:31:43.612463 <6>[ 8.024101] Run /init as init process
10757 16:31:43.622034 Loading, please wait...
10758 16:31:43.647819 Starting systemd-udevd version 252.22-1~deb12u1
10759 16:31:43.946956 <6>[ 8.353455] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10760 16:31:43.963891 <6>[ 8.370619] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10761 16:31:43.970943 <6>[ 8.371530] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10762 16:31:43.977577 <6>[ 8.375435] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10763 16:31:43.986969 <6>[ 8.375450] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10764 16:31:43.996985 <4>[ 8.375720] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10765 16:31:44.003439 <6>[ 8.376488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10766 16:31:44.010377 <6>[ 8.376494] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10767 16:31:44.020195 <6>[ 8.376876] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10768 16:31:44.026678 <6>[ 8.376898] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10769 16:31:44.036544 <6>[ 8.376908] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10770 16:31:44.043154 <6>[ 8.376923] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10771 16:31:44.049626 <6>[ 8.386384] remoteproc remoteproc0: scp is available
10772 16:31:44.059455 <6>[ 8.395536] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10773 16:31:44.062746 <6>[ 8.401795] remoteproc remoteproc0: powering up scp
10774 16:31:44.072420 <6>[ 8.411290] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10775 16:31:44.082385 <6>[ 8.421615] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10776 16:31:44.085613 <6>[ 8.428246] mc: Linux media interface: v0.10
10777 16:31:44.092470 <6>[ 8.434971] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10778 16:31:44.098746 <4>[ 8.436930] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10779 16:31:44.105577 <4>[ 8.447472] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10780 16:31:44.112163 <3>[ 8.451015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 16:31:44.122152 <3>[ 8.528794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 16:31:44.128905 <6>[ 8.529847] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10783 16:31:44.138731 <3>[ 8.536979] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 16:31:44.148521 <6>[ 8.541179] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10785 16:31:44.158281 <6>[ 8.541561] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10786 16:31:44.165098 <6>[ 8.552089] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10787 16:31:44.171516 <3>[ 8.552747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 16:31:44.178435 <6>[ 8.562885] pci_bus 0000:00: root bus resource [bus 00-ff]
10789 16:31:44.185017 <3>[ 8.571963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 16:31:44.191544 <6>[ 8.578889] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10791 16:31:44.201244 <3>[ 8.587165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 16:31:44.212175 <6>[ 8.592849] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10793 16:31:44.218309 <3>[ 8.600867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 16:31:44.228179 <3>[ 8.600871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 16:31:44.235921 <3>[ 8.600915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 16:31:44.242551 <6>[ 8.608192] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10797 16:31:44.251883 <6>[ 8.610264] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10798 16:31:44.258545 <4>[ 8.610939] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10799 16:31:44.264947 <4>[ 8.610939] Fallback method does not support PEC.
10800 16:31:44.272048 <3>[ 8.616182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 16:31:44.278391 <6>[ 8.626041] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10802 16:31:44.284911 <6>[ 8.626891] videodev: Linux video capture interface: v2.00
10803 16:31:44.294659 <3>[ 8.628116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10804 16:31:44.301770 <3>[ 8.634106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 16:31:44.308443 <6>[ 8.642250] pci 0000:00:00.0: supports D1 D2
10806 16:31:44.314774 <3>[ 8.650291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 16:31:44.324841 <3>[ 8.651354] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10808 16:31:44.331335 <6>[ 8.654249] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10809 16:31:44.341353 <6>[ 8.654255] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10810 16:31:44.344465 <6>[ 8.654257] remoteproc remoteproc0: remote processor scp is now up
10811 16:31:44.354173 <6>[ 8.656541] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10812 16:31:44.357593 <6>[ 8.657446] Bluetooth: Core ver 2.22
10813 16:31:44.364023 <6>[ 8.657563] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10814 16:31:44.371206 <6>[ 8.657705] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10815 16:31:44.377505 <6>[ 8.657735] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10816 16:31:44.387138 <6>[ 8.657759] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10817 16:31:44.393770 <6>[ 8.657775] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10818 16:31:44.397188 <6>[ 8.657885] pci 0000:01:00.0: supports D1 D2
10819 16:31:44.403538 <6>[ 8.657887] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10820 16:31:44.413507 <3>[ 8.665914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 16:31:44.420448 <6>[ 8.679553] NET: Registered PF_BLUETOOTH protocol family
10822 16:31:44.427009 <6>[ 8.681031] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10823 16:31:44.433684 <6>[ 8.682800] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10824 16:31:44.443230 <6>[ 8.682831] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10825 16:31:44.450031 <6>[ 8.682834] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10826 16:31:44.456476 <6>[ 8.682842] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10827 16:31:44.466253 <6>[ 8.682855] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10828 16:31:44.473427 <6>[ 8.682868] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10829 16:31:44.479910 <6>[ 8.682879] pci 0000:00:00.0: PCI bridge to [bus 01]
10830 16:31:44.486278 <6>[ 8.682884] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10831 16:31:44.492627 <6>[ 8.683031] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10832 16:31:44.499918 <6>[ 8.683550] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10833 16:31:44.509384 <6>[ 8.683718] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10834 16:31:44.512682 <6>[ 8.684091] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10835 16:31:44.522893 <3>[ 8.687573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 16:31:44.529207 <6>[ 8.695050] Bluetooth: HCI device and connection manager initialized
10837 16:31:44.535617 <3>[ 8.700784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 16:31:44.545915 <3>[ 8.700790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 16:31:44.552114 <3>[ 8.700794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 16:31:44.562016 <3>[ 8.700840] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 16:31:44.568533 <6>[ 8.703425] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10842 16:31:44.575033 <5>[ 8.704243] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10843 16:31:44.588594 <6>[ 8.705533] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10844 16:31:44.595041 <6>[ 8.705754] usbcore: registered new interface driver uvcvideo
10845 16:31:44.598218 <6>[ 8.709618] Bluetooth: HCI socket layer initialized
10846 16:31:44.605465 <5>[ 8.719625] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10847 16:31:44.611826 <6>[ 8.722207] Bluetooth: L2CAP socket layer initialized
10848 16:31:44.618033 <6>[ 8.730923] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10849 16:31:44.624686 <5>[ 8.731000] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10850 16:31:44.634702 <4>[ 8.731097] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10851 16:31:44.641523 <6>[ 8.731107] cfg80211: failed to load regulatory.db
10852 16:31:44.644839 <6>[ 8.739065] Bluetooth: SCO socket layer initialized
10853 16:31:44.651248 <6>[ 8.835374] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10854 16:31:44.657845 <6>[ 8.889338] usbcore: registered new interface driver btusb
10855 16:31:44.667943 <4>[ 8.890224] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10856 16:31:44.674067 <3>[ 8.890241] Bluetooth: hci0: Failed to load firmware file (-2)
10857 16:31:44.681076 <3>[ 8.890248] Bluetooth: hci0: Failed to set up firmware (-2)
10858 16:31:44.690899 <4>[ 8.890254] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10859 16:31:44.697395 <6>[ 8.894298] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10860 16:31:44.721049 <6>[ 9.130901] mt7921e 0000:01:00.0: ASIC revision: 79610010
10861 16:31:44.824543 <6>[ 9.230927] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10862 16:31:44.827750 <6>[ 9.230927]
10863 16:31:44.830929 Begin: Loading essential drivers ... done.
10864 16:31:44.834246 Begin: Running /scripts/init-premount ... done.
10865 16:31:44.840733 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10866 16:31:44.850394 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10867 16:31:44.853570 Device /sys/class/net/eth0 found
10868 16:31:44.853678 done.
10869 16:31:44.867453 Begin: Waiting up to 180 secs for any network device to become available ... done.
10870 16:31:44.920856 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10871 16:31:44.927284 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10872 16:31:44.934311 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10873 16:31:44.940944 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10874 16:31:44.947687 host : mt8192-asurada-spherion-r0-cbg-9
10875 16:31:44.953902 domain : lava-rack
10876 16:31:44.957119 rootserver: 192.168.201.1 rootpath:
10877 16:31:44.957243 filename :
10878 16:31:45.070755 done.
10879 16:31:45.077317 Begin: Running /scripts/nfs-bottom ... done.
10880 16:31:45.091561 Begin: Running /scripts/init-bottom ... <6>[ 9.498112] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10881 16:31:45.091725 done.
10882 16:31:46.437988 <6>[ 10.848052] NET: Registered PF_INET6 protocol family
10883 16:31:46.445869 <6>[ 10.855737] Segment Routing with IPv6
10884 16:31:46.449038 <6>[ 10.859741] In-situ OAM (IOAM) with IPv6
10885 16:31:46.627331 <30>[ 11.011105] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10886 16:31:46.634149 <30>[ 11.044232] systemd[1]: Detected architecture arm64.
10887 16:31:46.642709
10888 16:31:46.646447 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10889 16:31:46.646562
10890 16:31:46.671199 <30>[ 11.081171] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10891 16:31:47.781572 <30>[ 12.188408] systemd[1]: Queued start job for default target graphical.target.
10892 16:31:47.817571 <30>[ 12.224190] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10893 16:31:47.823969 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10894 16:31:47.845994 <30>[ 12.252808] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10895 16:31:47.855317 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10896 16:31:47.873981 <30>[ 12.280739] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10897 16:31:47.883680 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10898 16:31:47.901120 <30>[ 12.308324] systemd[1]: Created slice user.slice - User and Session Slice.
10899 16:31:47.907558 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10900 16:31:47.932353 <30>[ 12.335845] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10901 16:31:47.942031 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10902 16:31:47.963786 <30>[ 12.367245] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10903 16:31:47.969690 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10904 16:31:47.998215 <30>[ 12.395547] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10905 16:31:48.008037 <30>[ 12.415451] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10906 16:31:48.014622 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10907 16:31:48.032193 <30>[ 12.439369] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10908 16:31:48.041800 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10909 16:31:48.060464 <30>[ 12.467432] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10910 16:31:48.070422 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10911 16:31:48.085143 <30>[ 12.495493] systemd[1]: Reached target paths.target - Path Units.
10912 16:31:48.095425 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10913 16:31:48.112231 <30>[ 12.519442] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10914 16:31:48.118868 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10915 16:31:48.132803 <30>[ 12.542961] systemd[1]: Reached target slices.target - Slice Units.
10916 16:31:48.142465 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10917 16:31:48.156912 <30>[ 12.567479] systemd[1]: Reached target swap.target - Swaps.
10918 16:31:48.163550 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10919 16:31:48.184468 <30>[ 12.591474] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10920 16:31:48.194238 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10921 16:31:48.212821 <30>[ 12.619947] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10922 16:31:48.223144 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10923 16:31:48.243524 <30>[ 12.650403] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10924 16:31:48.253039 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10925 16:31:48.269587 <30>[ 12.676447] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10926 16:31:48.279476 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10927 16:31:48.296521 <30>[ 12.703606] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10928 16:31:48.302918 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10929 16:31:48.321165 <30>[ 12.728559] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10930 16:31:48.331176 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10931 16:31:48.350670 <30>[ 12.758002] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10932 16:31:48.360460 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10933 16:31:48.376228 <30>[ 12.783446] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10934 16:31:48.386135 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10935 16:31:48.440029 <30>[ 12.847167] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10936 16:31:48.446631 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10937 16:31:48.468749 <30>[ 12.875684] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10938 16:31:48.475373 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10939 16:31:48.500934 <30>[ 12.907859] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10940 16:31:48.507306 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10941 16:31:48.534613 <30>[ 12.935294] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10942 16:31:48.588742 <30>[ 12.995657] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10943 16:31:48.598358 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10944 16:31:48.625669 <30>[ 13.032455] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10945 16:31:48.632071 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10946 16:31:48.660802 <30>[ 13.067668] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10947 16:31:48.667157 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10948 16:31:48.697902 <30>[ 13.105027] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10949 16:31:48.704247 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10950 16:31:48.713939 <6>[ 13.120889] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10951 16:31:48.752743 <30>[ 13.159742] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10952 16:31:48.762024 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10953 16:31:48.782823 <30>[ 13.189872] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10954 16:31:48.789535 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10955 16:31:48.812687 <30>[ 13.219895] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10956 16:31:48.819108 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10957 16:31:48.841785 <6>[ 13.251936] fuse: init (API version 7.37)
10958 16:31:48.880561 <30>[ 13.287762] systemd[1]: Starting systemd-journald.service - Journal Service...
10959 16:31:48.886990 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10960 16:31:48.922058 <30>[ 13.329398] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10961 16:31:48.928526 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10962 16:31:48.955319 <30>[ 13.359049] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10963 16:31:48.961897 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10964 16:31:48.984595 <30>[ 13.392108] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10965 16:31:48.995241 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10966 16:31:49.019691 <30>[ 13.427132] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10967 16:31:49.030058 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10968 16:31:49.053127 <30>[ 13.460545] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10969 16:31:49.059666 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10970 16:31:49.080802 <30>[ 13.487757] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10971 16:31:49.087294 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10972 16:31:49.102347 <3>[ 13.509714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 16:31:49.112658 <30>[ 13.519244] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10974 16:31:49.119316 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10975 16:31:49.131924 <3>[ 13.539053] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 16:31:49.141450 <30>[ 13.548750] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10977 16:31:49.151875 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10978 16:31:49.169354 <30>[ 13.575862] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10979 16:31:49.175625 <30>[ 13.583815] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10980 16:31:49.185346 <3>[ 13.584582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 16:31:49.195363 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10982 16:31:49.212454 <30>[ 13.619789] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10983 16:31:49.219414 <3>[ 13.623042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 16:31:49.229270 <30>[ 13.627478] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10985 16:31:49.235811 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10986 16:31:49.250352 <3>[ 13.657726] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 16:31:49.261733 <30>[ 13.668653] systemd[1]: modprobe@drm.service: Deactivated successfully.
10988 16:31:49.268132 <30>[ 13.676487] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10989 16:31:49.285069 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 13.690842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 16:31:49.285264 ule drm.
10991 16:31:49.305647 <30>[ 13.712094] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10992 16:31:49.311948 <30>[ 13.720290] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10993 16:31:49.321656 <3>[ 13.723225] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 16:31:49.331282 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10995 16:31:49.345716 <30>[ 13.756004] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10996 16:31:49.355660 <3>[ 13.761897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 16:31:49.362798 <30>[ 13.763445] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10998 16:31:49.372468 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10999 16:31:49.388639 <3>[ 13.796077] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 16:31:49.398972 <30>[ 13.806093] systemd[1]: modprobe@loop.service: Deactivated successfully.
11001 16:31:49.405480 <30>[ 13.813540] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11002 16:31:49.412299 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11003 16:31:49.422574 <3>[ 13.829083] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 16:31:49.432631 <30>[ 13.840210] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11005 16:31:49.439679 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11006 16:31:49.456130 <3>[ 13.863215] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 16:31:49.473297 <4>[ 13.872027] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11008 16:31:49.482956 <30>[ 13.872763] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11009 16:31:49.493304 <3>[ 13.881967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 16:31:49.500375 <3>[ 13.887669] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11011 16:31:49.506633 <3>[ 13.905935] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 16:31:49.516883 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11013 16:31:49.537249 <30>[ 13.944096] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11014 16:31:49.547357 <3>[ 13.952327] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 16:31:49.553755 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11016 16:31:49.573247 <30>[ 13.979680] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
11017 16:31:49.579717 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11018 16:31:49.601236 <30>[ 14.008287] systemd[1]: Reached target network-pre.target - Preparation for Network.
11019 16:31:49.610859 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11020 16:31:49.656318 <30>[ 14.063445] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
11021 16:31:49.665805 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11022 16:31:49.688435 <30>[ 14.096041] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
11023 16:31:49.698086 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11024 16:31:49.723187 <30>[ 14.127200] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
11025 16:31:49.740406 <30>[ 14.140886] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
11026 16:31:49.768357 <30>[ 14.175804] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11027 16:31:49.774795 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11028 16:31:49.802347 <30>[ 14.206402] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11029 16:31:49.817082 <30>[ 14.224311] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11030 16:31:49.823495 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11031 16:31:49.884740 <30>[ 14.292057] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11032 16:31:49.891279 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11033 16:31:49.923347 <30>[ 14.330431] systemd[1]: Started systemd-journald.service - Journal Service.
11034 16:31:49.929718 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11035 16:31:49.958209 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11036 16:31:49.980316 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11037 16:31:50.001074 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11038 16:31:50.021148 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11039 16:31:50.041438 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11040 16:31:50.089176 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11041 16:31:50.111587 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11042 16:31:50.158532 <46>[ 14.566025] systemd-journald[314]: Received client request to flush runtime journal.
11043 16:31:50.926727 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11044 16:31:50.943891 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11045 16:31:50.960039 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11046 16:31:51.296759 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11047 16:31:51.590742 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11048 16:31:51.613984 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11049 16:31:51.790534 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11050 16:31:51.844916 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11051 16:31:51.924577 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11052 16:31:52.234675 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11053 16:31:52.249600 <6>[ 16.660241] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11054 16:31:52.276758 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11055 16:31:52.345889 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11056 16:31:52.424646 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11057 16:31:52.446583 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11058 16:31:52.464920 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11059 16:31:52.494198 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11060 16:31:52.510296 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11061 16:31:52.572559 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11062 16:31:52.608626 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11063 16:31:52.632317 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11064 16:31:52.649112 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11065 16:31:52.694495 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11066 16:31:52.759608 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11067 16:31:52.780630 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11068 16:31:52.804615 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11069 16:31:52.827598 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11070 16:31:52.857120 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11071 16:31:52.878885 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11072 16:31:52.896341 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11073 16:31:52.919841 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11074 16:31:52.939475 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11075 16:31:52.955991 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11076 16:31:52.974087 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11077 16:31:52.991690 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11078 16:31:53.012904 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11079 16:31:53.061580 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11080 16:31:53.096313 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11081 16:31:53.201426 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11082 16:31:53.223317 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11083 16:31:53.263020 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11084 16:31:53.313752 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11085 16:31:53.360743 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11086 16:31:53.380841 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11087 16:31:53.407069 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11088 16:31:53.528957 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11089 16:31:53.551331 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11090 16:31:53.571345 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11091 16:31:53.588194 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11092 16:31:53.641666 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11093 16:31:53.685054 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11094 16:31:53.768546
11095 16:31:53.771847 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11096 16:31:53.771939
11097 16:31:53.774538 debian-bookworm-arm64 login: root (automatic login)
11098 16:31:53.774621
11099 16:31:54.070808 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11100 16:31:54.070963
11101 16:31:54.077454 The programs included with the Debian GNU/Linux system are free software;
11102 16:31:54.084063 the exact distribution terms for each program are described in the
11103 16:31:54.087337 individual files in /usr/share/doc/*/copyright.
11104 16:31:54.087442
11105 16:31:54.093936 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11106 16:31:54.097306 permitted by applicable law.
11107 16:31:55.125089 Matched prompt #10: / #
11109 16:31:55.125392 Setting prompt string to ['/ #']
11110 16:31:55.125490 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11112 16:31:55.125688 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11113 16:31:55.125791 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11114 16:31:55.125864 Setting prompt string to ['/ #']
11115 16:31:55.125928 Forcing a shell prompt, looking for ['/ #']
11117 16:31:55.176126 / #
11118 16:31:55.176268 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11119 16:31:55.176346 Waiting using forced prompt support (timeout 00:02:30)
11120 16:31:55.181084
11121 16:31:55.181362 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11122 16:31:55.181456 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11124 16:31:55.281862 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3'
11125 16:31:55.287747 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396117/extract-nfsrootfs-kre4iqk3'
11127 16:31:55.388347 / # export NFS_SERVER_IP='192.168.201.1'
11128 16:31:55.393818 export NFS_SERVER_IP='192.168.201.1'
11129 16:31:55.394125 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11130 16:31:55.394239 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11131 16:31:55.394333 end: 2 depthcharge-action (duration 00:01:36) [common]
11132 16:31:55.394428 start: 3 lava-test-retry (timeout 00:07:42) [common]
11133 16:31:55.394518 start: 3.1 lava-test-shell (timeout 00:07:42) [common]
11134 16:31:55.394601 Using namespace: common
11136 16:31:55.494970 / # #
11137 16:31:55.495147 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11138 16:31:55.499881 #
11139 16:31:55.500155 Using /lava-14396117
11141 16:31:55.600457 / # export SHELL=/bin/bash
11142 16:31:55.605310 export SHELL=/bin/bash
11144 16:31:55.705825 / # . /lava-14396117/environment
11145 16:31:55.710773 . /lava-14396117/environment
11147 16:31:55.817592 / # /lava-14396117/bin/lava-test-runner /lava-14396117/0
11148 16:31:55.817790 Test shell timeout: 10s (minimum of the action and connection timeout)
11149 16:31:55.822569 /lava-14396117/bin/lava-test-runner /lava-14396117/0
11150 16:31:56.106385 + export TESTRUN_ID=0_timesync-off
11151 16:31:56.109438 + TESTRUN_ID=0_timesync-off
11152 16:31:56.112214 + cd /lava-14396117/0/tests/0_timesync-off
11153 16:31:56.115592 ++ cat uuid
11154 16:31:56.123083 + UUID=14396117_1.6.2.3.1
11155 16:31:56.123171 + set +x
11156 16:31:56.129794 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14396117_1.6.2.3.1>
11157 16:31:56.130092 Received signal: <STARTRUN> 0_timesync-off 14396117_1.6.2.3.1
11158 16:31:56.130200 Starting test lava.0_timesync-off (14396117_1.6.2.3.1)
11159 16:31:56.130293 Skipping test definition patterns.
11160 16:31:56.132696 + systemctl stop systemd-timesyncd
11161 16:31:56.206339 + set +x
11162 16:31:56.209186 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14396117_1.6.2.3.1>
11163 16:31:56.209481 Received signal: <ENDRUN> 0_timesync-off 14396117_1.6.2.3.1
11164 16:31:56.209602 Ending use of test pattern.
11165 16:31:56.209674 Ending test lava.0_timesync-off (14396117_1.6.2.3.1), duration 0.08
11167 16:31:56.306119 + export TESTRUN_ID=1_kselftest-arm64
11168 16:31:56.306276 + TESTRUN_ID=1_kselftest-arm64
11169 16:31:56.312788 + cd /lava-14396117/0/tests/1_kselftest-arm64
11170 16:31:56.312875 ++ cat uuid
11171 16:31:56.320982 + UUID=14396117_1.6.2.3.5
11172 16:31:56.321071 + set +x
11173 16:31:56.327684 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14396117_1.6.2.3.5>
11174 16:31:56.327951 Received signal: <STARTRUN> 1_kselftest-arm64 14396117_1.6.2.3.5
11175 16:31:56.328032 Starting test lava.1_kselftest-arm64 (14396117_1.6.2.3.5)
11176 16:31:56.328117 Skipping test definition patterns.
11177 16:31:56.330946 + cd ./automated/linux/kselftest/
11178 16:31:56.360189 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11179 16:31:56.414336 INFO: install_deps skipped
11180 16:31:56.961885 --2024-06-17 16:31:57-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11181 16:31:56.982294 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11182 16:31:57.110583 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11183 16:31:57.238995 HTTP request sent, awaiting response... 200 OK
11184 16:31:57.242777 Length: 1650228 (1.6M) [application/octet-stream]
11185 16:31:57.245998 Saving to: 'kselftest_armhf.tar.gz'
11186 16:31:57.246123
11187 16:31:57.246241
11188 16:31:57.496386 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11189 16:31:57.753043 kselftest_armhf.tar 2%[ ] 47.81K 186KB/s
11190 16:31:58.058043 kselftest_armhf.tar 13%[=> ] 214.67K 418KB/s
11191 16:31:58.190119 kselftest_armhf.tar 51%[=========> ] 836.85K 1023KB/s
11192 16:31:58.196745 kselftest_armhf.tar 100%[===================>] 1.57M 1.66MB/s in 1.0s
11193 16:31:58.196837
11194 16:31:58.342283 2024-06-17 16:31:58 (1.66 MB/s) - 'kselftest_armhf.tar.gz' saved [1650228/1650228]
11195 16:31:58.342462
11196 16:32:03.152068 skiplist:
11197 16:32:03.155622 ========================================
11198 16:32:03.158361 ========================================
11199 16:32:03.214001 arm64:tags_test
11200 16:32:03.216909 arm64:run_tags_test.sh
11201 16:32:03.217060 arm64:fake_sigreturn_bad_magic
11202 16:32:03.220251 arm64:fake_sigreturn_bad_size
11203 16:32:03.223740 arm64:fake_sigreturn_bad_size_for_magic0
11204 16:32:03.227031 arm64:fake_sigreturn_duplicated_fpsimd
11205 16:32:03.230301 arm64:fake_sigreturn_misaligned_sp
11206 16:32:03.233435 arm64:fake_sigreturn_missing_fpsimd
11207 16:32:03.236675 arm64:fake_sigreturn_sme_change_vl
11208 16:32:03.240263 arm64:fake_sigreturn_sve_change_vl
11209 16:32:03.243788 arm64:mangle_pstate_invalid_compat_toggle
11210 16:32:03.246420 arm64:mangle_pstate_invalid_daif_bits
11211 16:32:03.249846 arm64:mangle_pstate_invalid_mode_el1h
11212 16:32:03.253236 arm64:mangle_pstate_invalid_mode_el1t
11213 16:32:03.256464 arm64:mangle_pstate_invalid_mode_el2h
11214 16:32:03.259809 arm64:mangle_pstate_invalid_mode_el2t
11215 16:32:03.266797 arm64:mangle_pstate_invalid_mode_el3h
11216 16:32:03.269802 arm64:mangle_pstate_invalid_mode_el3t
11217 16:32:03.269887 arm64:sme_trap_no_sm
11218 16:32:03.273283 arm64:sme_trap_non_streaming
11219 16:32:03.273368 arm64:sme_trap_za
11220 16:32:03.276689 arm64:sme_vl
11221 16:32:03.276774 arm64:ssve_regs
11222 16:32:03.279555 arm64:sve_regs
11223 16:32:03.279640 arm64:sve_vl
11224 16:32:03.279707 arm64:za_no_regs
11225 16:32:03.282961 arm64:za_regs
11226 16:32:03.283046 arm64:pac
11227 16:32:03.286254 arm64:fp-stress
11228 16:32:03.286339 arm64:sve-ptrace
11229 16:32:03.289621 arm64:sve-probe-vls
11230 16:32:03.289706 arm64:vec-syscfg
11231 16:32:03.293122 arm64:za-fork
11232 16:32:03.293206 arm64:za-ptrace
11233 16:32:03.296208 arm64:check_buffer_fill
11234 16:32:03.296307 arm64:check_child_memory
11235 16:32:03.299517 arm64:check_gcr_el1_cswitch
11236 16:32:03.302959 arm64:check_ksm_options
11237 16:32:03.303044 arm64:check_mmap_options
11238 16:32:03.305682 arm64:check_prctl
11239 16:32:03.309147 arm64:check_tags_inclusion
11240 16:32:03.309232 arm64:check_user_mem
11241 16:32:03.312325 arm64:btitest
11242 16:32:03.312411 arm64:nobtitest
11243 16:32:03.312503 arm64:hwcap
11244 16:32:03.315567 arm64:ptrace
11245 16:32:03.315652 arm64:syscall-abi
11246 16:32:03.319410 arm64:tpidr2
11247 16:32:03.322437 ============== Tests to run ===============
11248 16:32:03.322524 arm64:tags_test
11249 16:32:03.326190 arm64:run_tags_test.sh
11250 16:32:03.328891 arm64:fake_sigreturn_bad_magic
11251 16:32:03.332404 arm64:fake_sigreturn_bad_size
11252 16:32:03.335658 arm64:fake_sigreturn_bad_size_for_magic0
11253 16:32:03.338899 arm64:fake_sigreturn_duplicated_fpsimd
11254 16:32:03.342105 arm64:fake_sigreturn_misaligned_sp
11255 16:32:03.345393 arm64:fake_sigreturn_missing_fpsimd
11256 16:32:03.348962 arm64:fake_sigreturn_sme_change_vl
11257 16:32:03.352436 arm64:fake_sigreturn_sve_change_vl
11258 16:32:03.355819 arm64:mangle_pstate_invalid_compat_toggle
11259 16:32:03.359141 arm64:mangle_pstate_invalid_daif_bits
11260 16:32:03.362007 arm64:mangle_pstate_invalid_mode_el1h
11261 16:32:03.365201 arm64:mangle_pstate_invalid_mode_el1t
11262 16:32:03.368781 arm64:mangle_pstate_invalid_mode_el2h
11263 16:32:03.372226 arm64:mangle_pstate_invalid_mode_el2t
11264 16:32:03.374973 arm64:mangle_pstate_invalid_mode_el3h
11265 16:32:03.378517 arm64:mangle_pstate_invalid_mode_el3t
11266 16:32:03.378603 arm64:sme_trap_no_sm
11267 16:32:03.381890 arm64:sme_trap_non_streaming
11268 16:32:03.385327 arm64:sme_trap_za
11269 16:32:03.385411 arm64:sme_vl
11270 16:32:03.388792 arm64:ssve_regs
11271 16:32:03.388877 arm64:sve_regs
11272 16:32:03.388943 arm64:sve_vl
11273 16:32:03.391554 arm64:za_no_regs
11274 16:32:03.391635 arm64:za_regs
11275 16:32:03.391700 arm64:pac
11276 16:32:03.394991 arm64:fp-stress
11277 16:32:03.395065 arm64:sve-ptrace
11278 16:32:03.398501 arm64:sve-probe-vls
11279 16:32:03.398572 arm64:vec-syscfg
11280 16:32:03.401756 arm64:za-fork
11281 16:32:03.401826 arm64:za-ptrace
11282 16:32:03.404842 arm64:check_buffer_fill
11283 16:32:03.408079 arm64:check_child_memory
11284 16:32:03.408158 arm64:check_gcr_el1_cswitch
11285 16:32:03.411547 arm64:check_ksm_options
11286 16:32:03.414882 arm64:check_mmap_options
11287 16:32:03.414963 arm64:check_prctl
11288 16:32:03.418252 arm64:check_tags_inclusion
11289 16:32:03.421494 arm64:check_user_mem
11290 16:32:03.421583 arm64:btitest
11291 16:32:03.421647 arm64:nobtitest
11292 16:32:03.424848 arm64:hwcap
11293 16:32:03.424921 arm64:ptrace
11294 16:32:03.427992 arm64:syscall-abi
11295 16:32:03.428090 arm64:tpidr2
11296 16:32:03.431259 ===========End Tests to run ===============
11297 16:32:03.434425 shardfile-arm64 pass
11298 16:32:03.666751 <12>[ 28.079259] kselftest: Running tests in arm64
11299 16:32:03.676750 TAP version 13
11300 16:32:03.691987 1..48
11301 16:32:03.711501 # selftests: arm64: tags_test
11302 16:32:04.169043 ok 1 selftests: arm64: tags_test
11303 16:32:04.190372 # selftests: arm64: run_tags_test.sh
11304 16:32:04.253743 # --------------------
11305 16:32:04.257081 # running tags test
11306 16:32:04.257176 # --------------------
11307 16:32:04.259795 # [PASS]
11308 16:32:04.263249 ok 2 selftests: arm64: run_tags_test.sh
11309 16:32:04.276452 # selftests: arm64: fake_sigreturn_bad_magic
11310 16:32:04.345852 # Registered handlers for all signals.
11311 16:32:04.346010 # Detected MINSTKSIGSZ:4720
11312 16:32:04.349186 # Testcase initialized.
11313 16:32:04.352221 # uc context validated.
11314 16:32:04.355926 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11315 16:32:04.359101 # Handled SIG_COPYCTX
11316 16:32:04.359213 # Available space:3568
11317 16:32:04.365622 # Using badly built context - ERR: BAD MAGIC !
11318 16:32:04.371859 # SIG_OK -- SP:0xFFFFFE580B10 si_addr@:0xfffffe580b10 si_code:2 token@:0xfffffe57f8b0 offset:-4704
11319 16:32:04.375162 # ==>> completed. PASS(1)
11320 16:32:04.382175 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11321 16:32:04.388452 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFE57F8B0
11322 16:32:04.395294 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11323 16:32:04.398756 # selftests: arm64: fake_sigreturn_bad_size
11324 16:32:04.435743 # Registered handlers for all signals.
11325 16:32:04.435885 # Detected MINSTKSIGSZ:4720
11326 16:32:04.439182 # Testcase initialized.
11327 16:32:04.442525 # uc context validated.
11328 16:32:04.445806 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11329 16:32:04.449339 # Handled SIG_COPYCTX
11330 16:32:04.449449 # Available space:3568
11331 16:32:04.452211 # uc context validated.
11332 16:32:04.458929 # Using badly built context - ERR: Bad size for esr_context
11333 16:32:04.465376 # SIG_OK -- SP:0xFFFFF24EF820 si_addr@:0xfffff24ef820 si_code:2 token@:0xfffff24ee5c0 offset:-4704
11334 16:32:04.469273 # ==>> completed. PASS(1)
11335 16:32:04.475504 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11336 16:32:04.482309 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF24EE5C0
11337 16:32:04.485636 ok 4 selftests: arm64: fake_sigreturn_bad_size
11338 16:32:04.491676 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11339 16:32:04.521158 # Registered handlers for all signals.
11340 16:32:04.521294 # Detected MINSTKSIGSZ:4720
11341 16:32:04.524486 # Testcase initialized.
11342 16:32:04.528009 # uc context validated.
11343 16:32:04.531177 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11344 16:32:04.534300 # Handled SIG_COPYCTX
11345 16:32:04.534411 # Available space:3568
11346 16:32:04.540521 # Using badly built context - ERR: Bad size for terminator
11347 16:32:04.550634 # SIG_OK -- SP:0xFFFFF32A4400 si_addr@:0xfffff32a4400 si_code:2 token@:0xfffff32a31a0 offset:-4704
11348 16:32:04.550724 # ==>> completed. PASS(1)
11349 16:32:04.560817 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11350 16:32:04.567682 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF32A31A0
11351 16:32:04.570770 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11352 16:32:04.576907 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11353 16:32:04.613244 # Registered handlers for all signals.
11354 16:32:04.613375 # Detected MINSTKSIGSZ:4720
11355 16:32:04.616477 # Testcase initialized.
11356 16:32:04.620387 # uc context validated.
11357 16:32:04.623667 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11358 16:32:04.626812 # Handled SIG_COPYCTX
11359 16:32:04.626921 # Available space:3568
11360 16:32:04.632967 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11361 16:32:04.642986 # SIG_OK -- SP:0xFFFFFF0754B0 si_addr@:0xffffff0754b0 si_code:2 token@:0xffffff074250 offset:-4704
11362 16:32:04.643106 # ==>> completed. PASS(1)
11363 16:32:04.653245 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11364 16:32:04.659574 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFF074250
11365 16:32:04.662932 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11366 16:32:04.666470 # selftests: arm64: fake_sigreturn_misaligned_sp
11367 16:32:04.694707 # Registered handlers for all signals.
11368 16:32:04.694824 # Detected MINSTKSIGSZ:4720
11369 16:32:04.697979 # Testcase initialized.
11370 16:32:04.701211 # uc context validated.
11371 16:32:04.704662 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11372 16:32:04.708181 # Handled SIG_COPYCTX
11373 16:32:04.714993 # SIG_OK -- SP:0xFFFFC553F523 si_addr@:0xffffc553f523 si_code:2 token@:0xffffc553f523 offset:0
11374 16:32:04.717822 # ==>> completed. PASS(1)
11375 16:32:04.724455 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11376 16:32:04.730953 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC553F523
11377 16:32:04.737701 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11378 16:32:04.741177 # selftests: arm64: fake_sigreturn_missing_fpsimd
11379 16:32:04.776082 # Registered handlers for all signals.
11380 16:32:04.776193 # Detected MINSTKSIGSZ:4720
11381 16:32:04.778829 # Testcase initialized.
11382 16:32:04.782322 # uc context validated.
11383 16:32:04.785762 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11384 16:32:04.789127 # Handled SIG_COPYCTX
11385 16:32:04.791883 # Mangling template header. Spare space:4096
11386 16:32:04.795183 # Using badly built context - ERR: Missing FPSIMD
11387 16:32:04.805147 # SIG_OK -- SP:0xFFFFF403AF20 si_addr@:0xfffff403af20 si_code:2 token@:0xfffff4039cc0 offset:-4704
11388 16:32:04.808946 # ==>> completed. PASS(1)
11389 16:32:04.814958 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11390 16:32:04.821800 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF4039CC0
11391 16:32:04.825135 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11392 16:32:04.831778 # selftests: arm64: fake_sigreturn_sme_change_vl
11393 16:32:04.848915 # Registered handlers for all signals.
11394 16:32:04.849037 # Detected MINSTKSIGSZ:4720
11395 16:32:04.852502 # ==>> completed. SKIP.
11396 16:32:04.858425 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11397 16:32:04.861664 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11398 16:32:04.869579 # selftests: arm64: fake_sigreturn_sve_change_vl
11399 16:32:04.928219 # Registered handlers for all signals.
11400 16:32:04.928387 # Detected MINSTKSIGSZ:4720
11401 16:32:04.931563 # ==>> completed. SKIP.
11402 16:32:04.938034 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11403 16:32:04.941346 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11404 16:32:04.949259 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11405 16:32:05.010092 # Registered handlers for all signals.
11406 16:32:05.010270 # Detected MINSTKSIGSZ:4720
11407 16:32:05.013886 # Testcase initialized.
11408 16:32:05.016970 # uc context validated.
11409 16:32:05.017073 # Handled SIG_TRIG
11410 16:32:05.027211 # SIG_OK -- SP:0xFFFFFB9198E0 si_addr@:0xfffffb9198e0 si_code:2 token@:(nil) offset:-281474902366432
11411 16:32:05.030324 # ==>> completed. PASS(1)
11412 16:32:05.037076 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11413 16:32:05.043783 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11414 16:32:05.046484 # selftests: arm64: mangle_pstate_invalid_daif_bits
11415 16:32:05.104549 # Registered handlers for all signals.
11416 16:32:05.104697 # Detected MINSTKSIGSZ:4720
11417 16:32:05.107844 # Testcase initialized.
11418 16:32:05.111257 # uc context validated.
11419 16:32:05.111335 # Handled SIG_TRIG
11420 16:32:05.121415 # SIG_OK -- SP:0xFFFFE009B8F0 si_addr@:0xffffe009b8f0 si_code:2 token@:(nil) offset:-281474440476912
11421 16:32:05.124463 # ==>> completed. PASS(1)
11422 16:32:05.130830 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11423 16:32:05.134030 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11424 16:32:05.140734 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11425 16:32:05.181618 # Registered handlers for all signals.
11426 16:32:05.181723 # Detected MINSTKSIGSZ:4720
11427 16:32:05.184950 # Testcase initialized.
11428 16:32:05.188783 # uc context validated.
11429 16:32:05.188873 # Handled SIG_TRIG
11430 16:32:05.198073 # SIG_OK -- SP:0xFFFFFA2DFFE0 si_addr@:0xfffffa2dffe0 si_code:2 token@:(nil) offset:-281474879061984
11431 16:32:05.201571 # ==>> completed. PASS(1)
11432 16:32:05.208359 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11433 16:32:05.211752 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11434 16:32:05.217813 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11435 16:32:05.265167 # Registered handlers for all signals.
11436 16:32:05.265277 # Detected MINSTKSIGSZ:4720
11437 16:32:05.268284 # Testcase initialized.
11438 16:32:05.271920 # uc context validated.
11439 16:32:05.272002 # Handled SIG_TRIG
11440 16:32:05.281977 # SIG_OK -- SP:0xFFFFEE1B2590 si_addr@:0xffffee1b2590 si_code:2 token@:(nil) offset:-281474676499856
11441 16:32:05.285282 # ==>> completed. PASS(1)
11442 16:32:05.291307 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11443 16:32:05.294547 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11444 16:32:05.301319 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11445 16:32:05.353768 # Registered handlers for all signals.
11446 16:32:05.353880 # Detected MINSTKSIGSZ:4720
11447 16:32:05.357259 # Testcase initialized.
11448 16:32:05.360598 # uc context validated.
11449 16:32:05.360682 # Handled SIG_TRIG
11450 16:32:05.370048 # SIG_OK -- SP:0xFFFFC6EF61C0 si_addr@:0xffffc6ef61c0 si_code:2 token@:(nil) offset:-281474019320256
11451 16:32:05.373590 # ==>> completed. PASS(1)
11452 16:32:05.379854 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11453 16:32:05.383091 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11454 16:32:05.389844 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11455 16:32:05.446252 # Registered handlers for all signals.
11456 16:32:05.446373 # Detected MINSTKSIGSZ:4720
11457 16:32:05.449333 # Testcase initialized.
11458 16:32:05.452687 # uc context validated.
11459 16:32:05.452773 # Handled SIG_TRIG
11460 16:32:05.462625 # SIG_OK -- SP:0xFFFFF2C8E590 si_addr@:0xfffff2c8e590 si_code:2 token@:(nil) offset:-281474754995600
11461 16:32:05.465815 # ==>> completed. PASS(1)
11462 16:32:05.472482 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11463 16:32:05.475933 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11464 16:32:05.482072 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11465 16:32:05.539816 # Registered handlers for all signals.
11466 16:32:05.539962 # Detected MINSTKSIGSZ:4720
11467 16:32:05.543065 # Testcase initialized.
11468 16:32:05.546410 # uc context validated.
11469 16:32:05.546487 # Handled SIG_TRIG
11470 16:32:05.556064 # SIG_OK -- SP:0xFFFFFA2DFBA0 si_addr@:0xfffffa2dfba0 si_code:2 token@:(nil) offset:-281474879060896
11471 16:32:05.559434 # ==>> completed. PASS(1)
11472 16:32:05.566264 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11473 16:32:05.569323 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11474 16:32:05.575508 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11475 16:32:05.632156 # Registered handlers for all signals.
11476 16:32:05.632271 # Detected MINSTKSIGSZ:4720
11477 16:32:05.635413 # Testcase initialized.
11478 16:32:05.638711 # uc context validated.
11479 16:32:05.638823 # Handled SIG_TRIG
11480 16:32:05.648230 # SIG_OK -- SP:0xFFFFCFB582C0 si_addr@:0xffffcfb582c0 si_code:2 token@:(nil) offset:-281474166522560
11481 16:32:05.651621 # ==>> completed. PASS(1)
11482 16:32:05.658537 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11483 16:32:05.661640 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11484 16:32:05.664983 # selftests: arm64: sme_trap_no_sm
11485 16:32:05.705819 # Registered handlers for all signals.
11486 16:32:05.705941 # Detected MINSTKSIGSZ:4720
11487 16:32:05.709025 # ==>> completed. SKIP.
11488 16:32:05.719190 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11489 16:32:05.722656 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11490 16:32:05.729507 # selftests: arm64: sme_trap_non_streaming
11491 16:32:05.790432 # Registered handlers for all signals.
11492 16:32:05.790565 # Detected MINSTKSIGSZ:4720
11493 16:32:05.794249 # ==>> completed. SKIP.
11494 16:32:05.804000 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11495 16:32:05.810521 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11496 16:32:05.813802 # selftests: arm64: sme_trap_za
11497 16:32:05.865266 # Registered handlers for all signals.
11498 16:32:05.865387 # Detected MINSTKSIGSZ:4720
11499 16:32:05.868738 # Testcase initialized.
11500 16:32:05.878634 # SIG_OK -- SP:0xFFFFF2B39E70 si_addr@:0xaaaab1e72510 si_code:1 token@:(nil) offset:-187650105877776
11501 16:32:05.878766 # ==>> completed. PASS(1)
11502 16:32:05.888249 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11503 16:32:05.891646 ok 21 selftests: arm64: sme_trap_za
11504 16:32:05.891731 # selftests: arm64: sme_vl
11505 16:32:05.955880 # Registered handlers for all signals.
11506 16:32:05.956197 # Detected MINSTKSIGSZ:4720
11507 16:32:05.959149 # ==>> completed. SKIP.
11508 16:32:05.965314 # # SME VL :: Check that we get the right SME VL reported
11509 16:32:05.968494 ok 22 selftests: arm64: sme_vl # SKIP
11510 16:32:05.972706 # selftests: arm64: ssve_regs
11511 16:32:06.040713 # Registered handlers for all signals.
11512 16:32:06.040900 # Detected MINSTKSIGSZ:4720
11513 16:32:06.044074 # ==>> completed. SKIP.
11514 16:32:06.050919 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11515 16:32:06.056906 ok 23 selftests: arm64: ssve_regs # SKIP
11516 16:32:06.060957 # selftests: arm64: sve_regs
11517 16:32:06.135379 # Registered handlers for all signals.
11518 16:32:06.135541 # Detected MINSTKSIGSZ:4720
11519 16:32:06.138687 # ==>> completed. SKIP.
11520 16:32:06.145640 # # SVE registers :: Check that we get the right SVE registers reported
11521 16:32:06.148348 ok 24 selftests: arm64: sve_regs # SKIP
11522 16:32:06.155004 # selftests: arm64: sve_vl
11523 16:32:06.229503 # Registered handlers for all signals.
11524 16:32:06.229644 # Detected MINSTKSIGSZ:4720
11525 16:32:06.231978 # ==>> completed. SKIP.
11526 16:32:06.238803 # # SVE VL :: Check that we get the right SVE VL reported
11527 16:32:06.242081 ok 25 selftests: arm64: sve_vl # SKIP
11528 16:32:06.246464 # selftests: arm64: za_no_regs
11529 16:32:06.313148 # Registered handlers for all signals.
11530 16:32:06.313306 # Detected MINSTKSIGSZ:4720
11531 16:32:06.316456 # ==>> completed. SKIP.
11532 16:32:06.323291 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11533 16:32:06.326198 ok 26 selftests: arm64: za_no_regs # SKIP
11534 16:32:06.332320 # selftests: arm64: za_regs
11535 16:32:06.386824 # Registered handlers for all signals.
11536 16:32:06.386972 # Detected MINSTKSIGSZ:4720
11537 16:32:06.390309 # ==>> completed. SKIP.
11538 16:32:06.396965 # # ZA register :: Check that we get the right ZA registers reported
11539 16:32:06.400388 ok 27 selftests: arm64: za_regs # SKIP
11540 16:32:06.407637 # selftests: arm64: pac
11541 16:32:06.461224 # TAP version 13
11542 16:32:06.461400 # 1..7
11543 16:32:06.464864 # # Starting 7 tests from 1 test cases.
11544 16:32:06.467837 # # RUN global.corrupt_pac ...
11545 16:32:06.471574 # # SKIP PAUTH not enabled
11546 16:32:06.474942 # # OK global.corrupt_pac
11547 16:32:06.478317 # ok 1 # SKIP PAUTH not enabled
11548 16:32:06.484479 # # RUN global.pac_instructions_not_nop ...
11549 16:32:06.487865 # # SKIP PAUTH not enabled
11550 16:32:06.491205 # # OK global.pac_instructions_not_nop
11551 16:32:06.494645 # ok 2 # SKIP PAUTH not enabled
11552 16:32:06.501335 # # RUN global.pac_instructions_not_nop_generic ...
11553 16:32:06.504635 # # SKIP Generic PAUTH not enabled
11554 16:32:06.507459 # # OK global.pac_instructions_not_nop_generic
11555 16:32:06.514235 # ok 3 # SKIP Generic PAUTH not enabled
11556 16:32:06.517702 # # RUN global.single_thread_different_keys ...
11557 16:32:06.521017 # # SKIP PAUTH not enabled
11558 16:32:06.527576 # # OK global.single_thread_different_keys
11559 16:32:06.527667 # ok 4 # SKIP PAUTH not enabled
11560 16:32:06.534225 # # RUN global.exec_changed_keys ...
11561 16:32:06.537695 # # SKIP PAUTH not enabled
11562 16:32:06.540385 # # OK global.exec_changed_keys
11563 16:32:06.543991 # ok 5 # SKIP PAUTH not enabled
11564 16:32:06.547048 # # RUN global.context_switch_keep_keys ...
11565 16:32:06.550591 # # SKIP PAUTH not enabled
11566 16:32:06.557121 # # OK global.context_switch_keep_keys
11567 16:32:06.560184 # ok 6 # SKIP PAUTH not enabled
11568 16:32:06.563544 # # RUN global.context_switch_keep_keys_generic ...
11569 16:32:06.566846 # # SKIP Generic PAUTH not enabled
11570 16:32:06.573372 # # OK global.context_switch_keep_keys_generic
11571 16:32:06.576734 # ok 7 # SKIP Generic PAUTH not enabled
11572 16:32:06.579900 # # PASSED: 7 / 7 tests passed.
11573 16:32:06.583592 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11574 16:32:06.586836 ok 28 selftests: arm64: pac
11575 16:32:06.589926 # selftests: arm64: fp-stress
11576 16:32:15.601921 <6>[ 40.018758] vpu: disabling
11577 16:32:15.604995 <6>[ 40.021809] vproc2: disabling
11578 16:32:15.608606 <6>[ 40.025428] vproc1: disabling
11579 16:32:15.611674 <6>[ 40.028706] vaud18: disabling
11580 16:32:15.618231 <6>[ 40.032137] vsram_others: disabling
11581 16:32:15.621877 <6>[ 40.036030] va09: disabling
11582 16:32:15.625127 <6>[ 40.039148] vsram_md: disabling
11583 16:32:15.628675 <6>[ 40.042647] Vgpu: disabling
11584 16:32:16.543029 # TAP version 13
11585 16:32:16.543176 # 1..16
11586 16:32:16.546177 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11587 16:32:16.549457 # # Will run for 10s
11588 16:32:16.549570 # # Started FPSIMD-0-0
11589 16:32:16.552742 # # Started FPSIMD-0-1
11590 16:32:16.556132 # # Started FPSIMD-1-0
11591 16:32:16.556216 # # Started FPSIMD-1-1
11592 16:32:16.559524 # # Started FPSIMD-2-0
11593 16:32:16.562979 # # Started FPSIMD-2-1
11594 16:32:16.563057 # # Started FPSIMD-3-0
11595 16:32:16.566433 # # Started FPSIMD-3-1
11596 16:32:16.566511 # # Started FPSIMD-4-0
11597 16:32:16.569223 # # Started FPSIMD-4-1
11598 16:32:16.572667 # # Started FPSIMD-5-0
11599 16:32:16.572783 # # Started FPSIMD-5-1
11600 16:32:16.575921 # # Started FPSIMD-6-0
11601 16:32:16.579225 # # Started FPSIMD-6-1
11602 16:32:16.579305 # # Started FPSIMD-7-0
11603 16:32:16.582552 # # Started FPSIMD-7-1
11604 16:32:16.585967 # # FPSIMD-1-1: Vector length: 128 bits
11605 16:32:16.589451 # # FPSIMD-1-1: PID: 1177
11606 16:32:16.592693 # # FPSIMD-2-1: Vector length: 128 bits
11607 16:32:16.592805 # # FPSIMD-2-1: PID: 1179
11608 16:32:16.595855 # # FPSIMD-0-0: Vector length: 128 bits
11609 16:32:16.598881 # # FPSIMD-0-0: PID: 1174
11610 16:32:16.602645 # # FPSIMD-0-1: Vector length: 128 bits
11611 16:32:16.605669 # # FPSIMD-0-1: PID: 1175
11612 16:32:16.608702 # # FPSIMD-2-0: Vector length: 128 bits
11613 16:32:16.611895 # # FPSIMD-2-0: PID: 1178
11614 16:32:16.615414 # # FPSIMD-4-0: Vector length: 128 bits
11615 16:32:16.618675 # # FPSIMD-4-0: PID: 1182
11616 16:32:16.621950 # # FPSIMD-1-0: Vector length: 128 bits
11617 16:32:16.622060 # # FPSIMD-1-0: PID: 1176
11618 16:32:16.625475 # # FPSIMD-5-0: Vector length: 128 bits
11619 16:32:16.631810 # # FPSIMD-3-1: Vector length: 128 bits
11620 16:32:16.631916 # # FPSIMD-3-1: PID: 1181
11621 16:32:16.635290 # # FPSIMD-5-0: PID: 1184
11622 16:32:16.638546 # # FPSIMD-5-1: Vector length: 128 bits
11623 16:32:16.641664 # # FPSIMD-5-1: PID: 1185
11624 16:32:16.645557 # # FPSIMD-7-0: Vector length: 128 bits
11625 16:32:16.648286 # # FPSIMD-7-0: PID: 1188
11626 16:32:16.651589 # # FPSIMD-6-0: Vector length: 128 bits
11627 16:32:16.651669 # # FPSIMD-6-0: PID: 1186
11628 16:32:16.655422 # # FPSIMD-4-1: Vector length: 128 bits
11629 16:32:16.658079 # # FPSIMD-4-1: PID: 1183
11630 16:32:16.661418 # # FPSIMD-6-1: Vector length: 128 bits
11631 16:32:16.664805 # # FPSIMD-6-1: PID: 1187
11632 16:32:16.668330 # # FPSIMD-3-0: Vector length: 128 bits
11633 16:32:16.671830 # # FPSIMD-3-0: PID: 1180
11634 16:32:16.675286 # # FPSIMD-7-1: Vector length: 128 bits
11635 16:32:16.675404 # # FPSIMD-7-1: PID: 1189
11636 16:32:16.678036 # # Finishing up...
11637 16:32:16.684740 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1314486, signals=10
11638 16:32:16.691647 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1483207, signals=10
11639 16:32:16.701114 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1342797, signals=10
11640 16:32:16.708056 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1037902, signals=10
11641 16:32:16.714495 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1539864, signals=10
11642 16:32:16.721026 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1087474, signals=10
11643 16:32:16.724097 # ok 1 FPSIMD-0-0
11644 16:32:16.724188 # ok 2 FPSIMD-0-1
11645 16:32:16.727953 # ok 3 FPSIMD-1-0
11646 16:32:16.728042 # ok 4 FPSIMD-1-1
11647 16:32:16.730777 # ok 5 FPSIMD-2-0
11648 16:32:16.730861 # ok 6 FPSIMD-2-1
11649 16:32:16.734211 # ok 7 FPSIMD-3-0
11650 16:32:16.734295 # ok 8 FPSIMD-3-1
11651 16:32:16.737748 # ok 9 FPSIMD-4-0
11652 16:32:16.737833 # ok 10 FPSIMD-4-1
11653 16:32:16.740633 # ok 11 FPSIMD-5-0
11654 16:32:16.740716 # ok 12 FPSIMD-5-1
11655 16:32:16.743834 # ok 13 FPSIMD-6-0
11656 16:32:16.743919 # ok 14 FPSIMD-6-1
11657 16:32:16.747616 # ok 15 FPSIMD-7-0
11658 16:32:16.747700 # ok 16 FPSIMD-7-1
11659 16:32:16.753741 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1178596, signals=10
11660 16:32:16.763653 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1158183, signals=9
11661 16:32:16.770493 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=782876, signals=10
11662 16:32:16.777508 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1232305, signals=10
11663 16:32:16.783416 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=911133, signals=9
11664 16:32:16.790299 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1275502, signals=10
11665 16:32:16.797250 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1051522, signals=10
11666 16:32:16.806549 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1015832, signals=10
11667 16:32:16.813278 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1218502, signals=10
11668 16:32:16.820179 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1536170, signals=9
11669 16:32:16.826560 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11670 16:32:16.826652 ok 29 selftests: arm64: fp-stress
11671 16:32:16.829624 # selftests: arm64: sve-ptrace
11672 16:32:16.833269 # TAP version 13
11673 16:32:16.833352 # 1..4104
11674 16:32:16.836345 # ok 2 # SKIP SVE not available
11675 16:32:16.839790 # # Planned tests != run tests (4104 != 1)
11676 16:32:16.846677 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11677 16:32:16.849346 ok 30 selftests: arm64: sve-ptrace # SKIP
11678 16:32:16.853156 # selftests: arm64: sve-probe-vls
11679 16:32:16.853263 # TAP version 13
11680 16:32:16.853350 # 1..2
11681 16:32:16.856280 # ok 2 # SKIP SVE not available
11682 16:32:16.859450 # # Planned tests != run tests (2 != 1)
11683 16:32:16.866325 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11684 16:32:16.869663 ok 31 selftests: arm64: sve-probe-vls # SKIP
11685 16:32:16.873106 # selftests: arm64: vec-syscfg
11686 16:32:16.873208 # TAP version 13
11687 16:32:16.876483 # 1..20
11688 16:32:16.876585 # ok 1 # SKIP SVE not supported
11689 16:32:16.879287 # ok 2 # SKIP SVE not supported
11690 16:32:16.882775 # ok 3 # SKIP SVE not supported
11691 16:32:16.886317 # ok 4 # SKIP SVE not supported
11692 16:32:16.889132 # ok 5 # SKIP SVE not supported
11693 16:32:16.892346 # ok 6 # SKIP SVE not supported
11694 16:32:16.895635 # ok 7 # SKIP SVE not supported
11695 16:32:16.899024 # ok 8 # SKIP SVE not supported
11696 16:32:16.899102 # ok 9 # SKIP SVE not supported
11697 16:32:16.902466 # ok 10 # SKIP SVE not supported
11698 16:32:16.905867 # ok 11 # SKIP SME not supported
11699 16:32:16.909314 # ok 12 # SKIP SME not supported
11700 16:32:16.912586 # ok 13 # SKIP SME not supported
11701 16:32:16.915836 # ok 14 # SKIP SME not supported
11702 16:32:16.919209 # ok 15 # SKIP SME not supported
11703 16:32:16.922619 # ok 16 # SKIP SME not supported
11704 16:32:16.925362 # ok 17 # SKIP SME not supported
11705 16:32:16.925446 # ok 18 # SKIP SME not supported
11706 16:32:16.928748 # ok 19 # SKIP SME not supported
11707 16:32:16.932121 # ok 20 # SKIP SME not supported
11708 16:32:16.938981 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11709 16:32:16.942089 ok 32 selftests: arm64: vec-syscfg
11710 16:32:16.945165 # selftests: arm64: za-fork
11711 16:32:16.945277 # TAP version 13
11712 16:32:16.945375 # 1..1
11713 16:32:16.949005 # # PID: 1266
11714 16:32:16.949107 # # SME support not present
11715 16:32:16.951906 # ok 0 skipped
11716 16:32:16.955399 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11717 16:32:16.958640 ok 33 selftests: arm64: za-fork
11718 16:32:16.961997 # selftests: arm64: za-ptrace
11719 16:32:16.980611 # TAP version 13
11720 16:32:16.980724 # 1..1
11721 16:32:16.983971 # ok 2 # SKIP SME not available
11722 16:32:16.990752 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11723 16:32:16.993552 ok 34 selftests: arm64: za-ptrace # SKIP
11724 16:32:17.005084 # selftests: arm64: check_buffer_fill
11725 16:32:17.074474 # # SKIP: MTE features unavailable
11726 16:32:17.082015 ok 35 selftests: arm64: check_buffer_fill # SKIP
11727 16:32:17.100121 # selftests: arm64: check_child_memory
11728 16:32:17.161166 # # SKIP: MTE features unavailable
11729 16:32:17.169280 ok 36 selftests: arm64: check_child_memory # SKIP
11730 16:32:17.186003 # selftests: arm64: check_gcr_el1_cswitch
11731 16:32:17.237131 # # SKIP: MTE features unavailable
11732 16:32:17.243437 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11733 16:32:17.259043 # selftests: arm64: check_ksm_options
11734 16:32:17.308598 # # SKIP: MTE features unavailable
11735 16:32:17.316105 ok 38 selftests: arm64: check_ksm_options # SKIP
11736 16:32:17.331972 # selftests: arm64: check_mmap_options
11737 16:32:17.383876 # # SKIP: MTE features unavailable
11738 16:32:17.390986 ok 39 selftests: arm64: check_mmap_options # SKIP
11739 16:32:17.403763 # selftests: arm64: check_prctl
11740 16:32:17.469507 # TAP version 13
11741 16:32:17.469653 # 1..5
11742 16:32:17.472802 # ok 1 check_basic_read
11743 16:32:17.472917 # ok 2 NONE
11744 16:32:17.476115 # ok 3 # SKIP SYNC
11745 16:32:17.476224 # ok 4 # SKIP ASYNC
11746 16:32:17.479595 # ok 5 # SKIP SYNC+ASYNC
11747 16:32:17.482354 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11748 16:32:17.485799 ok 40 selftests: arm64: check_prctl
11749 16:32:17.495905 # selftests: arm64: check_tags_inclusion
11750 16:32:17.551405 # # SKIP: MTE features unavailable
11751 16:32:17.559581 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11752 16:32:17.572604 # selftests: arm64: check_user_mem
11753 16:32:17.637353 # # SKIP: MTE features unavailable
11754 16:32:17.644736 ok 42 selftests: arm64: check_user_mem # SKIP
11755 16:32:17.659410 # selftests: arm64: btitest
11756 16:32:17.721181 # TAP version 13
11757 16:32:17.721328 # 1..18
11758 16:32:17.724416 # # HWCAP_PACA not present
11759 16:32:17.727678 # # HWCAP2_BTI not present
11760 16:32:17.727789 # # Test binary built for BTI
11761 16:32:17.734097 # ok 1 nohint_func/call_using_br_x0 # SKIP
11762 16:32:17.737386 # ok 1 nohint_func/call_using_br_x16 # SKIP
11763 16:32:17.740728 # ok 1 nohint_func/call_using_blr # SKIP
11764 16:32:17.744037 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11765 16:32:17.746817 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11766 16:32:17.753552 # ok 1 bti_none_func/call_using_blr # SKIP
11767 16:32:17.756936 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11768 16:32:17.760333 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11769 16:32:17.763763 # ok 1 bti_c_func/call_using_blr # SKIP
11770 16:32:17.766860 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11771 16:32:17.770427 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11772 16:32:17.773837 # ok 1 bti_j_func/call_using_blr # SKIP
11773 16:32:17.776584 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11774 16:32:17.783479 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11775 16:32:17.786803 # ok 1 bti_jc_func/call_using_blr # SKIP
11776 16:32:17.789972 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11777 16:32:17.793423 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11778 16:32:17.796818 # ok 1 paciasp_func/call_using_blr # SKIP
11779 16:32:17.802986 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11780 16:32:17.806286 # # WARNING - EXPECTED TEST COUNT WRONG
11781 16:32:17.809732 ok 43 selftests: arm64: btitest
11782 16:32:17.813143 # selftests: arm64: nobtitest
11783 16:32:17.813230 # TAP version 13
11784 16:32:17.813297 # 1..18
11785 16:32:17.816524 # # HWCAP_PACA not present
11786 16:32:17.819830 # # HWCAP2_BTI not present
11787 16:32:17.823265 # # Test binary not built for BTI
11788 16:32:17.826711 # ok 1 nohint_func/call_using_br_x0 # SKIP
11789 16:32:17.829419 # ok 1 nohint_func/call_using_br_x16 # SKIP
11790 16:32:17.832701 # ok 1 nohint_func/call_using_blr # SKIP
11791 16:32:17.836418 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11792 16:32:17.842975 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11793 16:32:17.846190 # ok 1 bti_none_func/call_using_blr # SKIP
11794 16:32:17.849413 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11795 16:32:17.852867 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11796 16:32:17.856316 # ok 1 bti_c_func/call_using_blr # SKIP
11797 16:32:17.859156 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11798 16:32:17.862423 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11799 16:32:17.865923 # ok 1 bti_j_func/call_using_blr # SKIP
11800 16:32:17.872539 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11801 16:32:17.875777 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11802 16:32:17.879064 # ok 1 bti_jc_func/call_using_blr # SKIP
11803 16:32:17.882483 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11804 16:32:17.885835 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11805 16:32:17.889138 # ok 1 paciasp_func/call_using_blr # SKIP
11806 16:32:17.895774 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11807 16:32:17.899238 # # WARNING - EXPECTED TEST COUNT WRONG
11808 16:32:17.902605 ok 44 selftests: arm64: nobtitest
11809 16:32:17.905332 # selftests: arm64: hwcap
11810 16:32:17.905419 # TAP version 13
11811 16:32:17.905486 # 1..28
11812 16:32:17.908756 # ok 1 cpuinfo_match_RNG
11813 16:32:17.912005 # # SIGILL reported for RNG
11814 16:32:17.915386 # ok 2 # SKIP sigill_RNG
11815 16:32:17.915503 # ok 3 cpuinfo_match_SME
11816 16:32:17.918706 # ok 4 sigill_SME
11817 16:32:17.918814 # ok 5 cpuinfo_match_SVE
11818 16:32:17.922053 # ok 6 sigill_SVE
11819 16:32:17.925435 # ok 7 cpuinfo_match_SVE 2
11820 16:32:17.925520 # # SIGILL reported for SVE 2
11821 16:32:17.928875 # ok 8 # SKIP sigill_SVE 2
11822 16:32:17.931670 # ok 9 cpuinfo_match_SVE AES
11823 16:32:17.935105 # # SIGILL reported for SVE AES
11824 16:32:17.938377 # ok 10 # SKIP sigill_SVE AES
11825 16:32:17.941628 # ok 11 cpuinfo_match_SVE2 PMULL
11826 16:32:17.941736 # # SIGILL reported for SVE2 PMULL
11827 16:32:17.945464 # ok 12 # SKIP sigill_SVE2 PMULL
11828 16:32:17.948186 # ok 13 cpuinfo_match_SVE2 BITPERM
11829 16:32:17.952122 # # SIGILL reported for SVE2 BITPERM
11830 16:32:17.955241 # ok 14 # SKIP sigill_SVE2 BITPERM
11831 16:32:17.958558 # ok 15 cpuinfo_match_SVE2 SHA3
11832 16:32:17.961329 # # SIGILL reported for SVE2 SHA3
11833 16:32:17.964804 # ok 16 # SKIP sigill_SVE2 SHA3
11834 16:32:17.968091 # ok 17 cpuinfo_match_SVE2 SM4
11835 16:32:17.971492 # # SIGILL reported for SVE2 SM4
11836 16:32:17.975126 # ok 18 # SKIP sigill_SVE2 SM4
11837 16:32:17.975237 # ok 19 cpuinfo_match_SVE2 I8MM
11838 16:32:17.977800 # # SIGILL reported for SVE2 I8MM
11839 16:32:17.981082 # ok 20 # SKIP sigill_SVE2 I8MM
11840 16:32:17.984441 # ok 21 cpuinfo_match_SVE2 F32MM
11841 16:32:17.987796 # # SIGILL reported for SVE2 F32MM
11842 16:32:17.991243 # ok 22 # SKIP sigill_SVE2 F32MM
11843 16:32:17.994692 # ok 23 cpuinfo_match_SVE2 F64MM
11844 16:32:17.998038 # # SIGILL reported for SVE2 F64MM
11845 16:32:18.001336 # ok 24 # SKIP sigill_SVE2 F64MM
11846 16:32:18.004584 # ok 25 cpuinfo_match_SVE2 BF16
11847 16:32:18.004672 # # SIGILL reported for SVE2 BF16
11848 16:32:18.007984 # ok 26 # SKIP sigill_SVE2 BF16
11849 16:32:18.011339 # ok 27 cpuinfo_match_SVE2 EBF16
11850 16:32:18.014672 # ok 28 # SKIP sigill_SVE2 EBF16
11851 16:32:18.020793 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11852 16:32:18.020887 ok 45 selftests: arm64: hwcap
11853 16:32:18.024075 # selftests: arm64: ptrace
11854 16:32:18.027476 # TAP version 13
11855 16:32:18.027563 # 1..7
11856 16:32:18.030882 # # Parent is 1509, child is 1510
11857 16:32:18.030975 # ok 1 read_tpidr_one
11858 16:32:18.034112 # ok 2 write_tpidr_one
11859 16:32:18.037570 # ok 3 verify_tpidr_one
11860 16:32:18.037656 # ok 4 count_tpidrs
11861 16:32:18.040878 # ok 5 tpidr2_write
11862 16:32:18.040963 # ok 6 tpidr2_read
11863 16:32:18.044262 # ok 7 write_tpidr_only
11864 16:32:18.050768 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11865 16:32:18.050865 ok 46 selftests: arm64: ptrace
11866 16:32:18.054146 # selftests: arm64: syscall-abi
11867 16:32:18.078050 # TAP version 13
11868 16:32:18.078227 # 1..2
11869 16:32:18.081415 # ok 1 getpid() FPSIMD
11870 16:32:18.084241 # ok 2 sched_yield() FPSIMD
11871 16:32:18.088138 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11872 16:32:18.091379 ok 47 selftests: arm64: syscall-abi
11873 16:32:18.098169 # selftests: arm64: tpidr2
11874 16:32:18.153310 # TAP version 13
11875 16:32:18.153449 # 1..5
11876 16:32:18.155959 # # PID: 1546
11877 16:32:18.156043 # # SME support not present
11878 16:32:18.159684 # ok 0 skipped, TPIDR2 not supported
11879 16:32:18.163100 # ok 1 skipped, TPIDR2 not supported
11880 16:32:18.165692 # ok 2 skipped, TPIDR2 not supported
11881 16:32:18.168993 # ok 3 skipped, TPIDR2 not supported
11882 16:32:18.172852 # ok 4 skipped, TPIDR2 not supported
11883 16:32:18.179461 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11884 16:32:18.182183 ok 48 selftests: arm64: tpidr2
11885 16:32:19.711355 arm64_tags_test pass
11886 16:32:19.714702 arm64_run_tags_test_sh pass
11887 16:32:19.717986 arm64_fake_sigreturn_bad_magic pass
11888 16:32:19.721344 arm64_fake_sigreturn_bad_size pass
11889 16:32:19.724124 arm64_fake_sigreturn_bad_size_for_magic0 pass
11890 16:32:19.727445 arm64_fake_sigreturn_duplicated_fpsimd pass
11891 16:32:19.730745 arm64_fake_sigreturn_misaligned_sp pass
11892 16:32:19.734108 arm64_fake_sigreturn_missing_fpsimd pass
11893 16:32:19.737166 arm64_fake_sigreturn_sme_change_vl skip
11894 16:32:19.743838 arm64_fake_sigreturn_sve_change_vl skip
11895 16:32:19.747767 arm64_mangle_pstate_invalid_compat_toggle pass
11896 16:32:19.750516 arm64_mangle_pstate_invalid_daif_bits pass
11897 16:32:19.753960 arm64_mangle_pstate_invalid_mode_el1h pass
11898 16:32:19.757444 arm64_mangle_pstate_invalid_mode_el1t pass
11899 16:32:19.760601 arm64_mangle_pstate_invalid_mode_el2h pass
11900 16:32:19.767289 arm64_mangle_pstate_invalid_mode_el2t pass
11901 16:32:19.770789 arm64_mangle_pstate_invalid_mode_el3h pass
11902 16:32:19.773479 arm64_mangle_pstate_invalid_mode_el3t pass
11903 16:32:19.776919 arm64_sme_trap_no_sm skip
11904 16:32:19.780360 arm64_sme_trap_non_streaming skip
11905 16:32:19.780444 arm64_sme_trap_za pass
11906 16:32:19.783724 arm64_sme_vl skip
11907 16:32:19.783802 arm64_ssve_regs skip
11908 16:32:19.787175 arm64_sve_regs skip
11909 16:32:19.787256 arm64_sve_vl skip
11910 16:32:19.790448 arm64_za_no_regs skip
11911 16:32:19.790519 arm64_za_regs skip
11912 16:32:19.793618 arm64_pac_PAUTH_not_enabled skip
11913 16:32:19.796860 arm64_pac_PAUTH_not_enabled_dup2 skip
11914 16:32:19.800293 arm64_pac_Generic_PAUTH_not_enabled skip
11915 16:32:19.803743 arm64_pac_PAUTH_not_enabled_dup3 skip
11916 16:32:19.809789 arm64_pac_PAUTH_not_enabled_dup4 skip
11917 16:32:19.813182 arm64_pac_PAUTH_not_enabled_dup5 skip
11918 16:32:19.816438 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11919 16:32:19.816512 arm64_pac pass
11920 16:32:19.820192 arm64_fp-stress_FPSIMD-0-0 pass
11921 16:32:19.823138 arm64_fp-stress_FPSIMD-0-1 pass
11922 16:32:19.826383 arm64_fp-stress_FPSIMD-1-0 pass
11923 16:32:19.829505 arm64_fp-stress_FPSIMD-1-1 pass
11924 16:32:19.833009 arm64_fp-stress_FPSIMD-2-0 pass
11925 16:32:19.833093 arm64_fp-stress_FPSIMD-2-1 pass
11926 16:32:19.836363 arm64_fp-stress_FPSIMD-3-0 pass
11927 16:32:19.839731 arm64_fp-stress_FPSIMD-3-1 pass
11928 16:32:19.843181 arm64_fp-stress_FPSIMD-4-0 pass
11929 16:32:19.846585 arm64_fp-stress_FPSIMD-4-1 pass
11930 16:32:19.849761 arm64_fp-stress_FPSIMD-5-0 pass
11931 16:32:19.852989 arm64_fp-stress_FPSIMD-5-1 pass
11932 16:32:19.856056 arm64_fp-stress_FPSIMD-6-0 pass
11933 16:32:19.856141 arm64_fp-stress_FPSIMD-6-1 pass
11934 16:32:19.859390 arm64_fp-stress_FPSIMD-7-0 pass
11935 16:32:19.862674 arm64_fp-stress_FPSIMD-7-1 pass
11936 16:32:19.865956 arm64_fp-stress pass
11937 16:32:19.869170 arm64_sve-ptrace_SVE_not_available skip
11938 16:32:19.869244 arm64_sve-ptrace skip
11939 16:32:19.876336 arm64_sve-probe-vls_SVE_not_available skip
11940 16:32:19.876437 arm64_sve-probe-vls skip
11941 16:32:19.879098 arm64_vec-syscfg_SVE_not_supported skip
11942 16:32:19.885909 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11943 16:32:19.889438 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11944 16:32:19.892855 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11945 16:32:19.895676 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11946 16:32:19.899145 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11947 16:32:19.905622 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11948 16:32:19.909115 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11949 16:32:19.912577 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11950 16:32:19.915934 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11951 16:32:19.918713 arm64_vec-syscfg_SME_not_supported skip
11952 16:32:19.922104 arm64_vec-syscfg_SME_not_supported_dup2 skip
11953 16:32:19.928680 arm64_vec-syscfg_SME_not_supported_dup3 skip
11954 16:32:19.931958 arm64_vec-syscfg_SME_not_supported_dup4 skip
11955 16:32:19.935733 arm64_vec-syscfg_SME_not_supported_dup5 skip
11956 16:32:19.938760 arm64_vec-syscfg_SME_not_supported_dup6 skip
11957 16:32:19.945360 arm64_vec-syscfg_SME_not_supported_dup7 skip
11958 16:32:19.948789 arm64_vec-syscfg_SME_not_supported_dup8 skip
11959 16:32:19.952138 arm64_vec-syscfg_SME_not_supported_dup9 skip
11960 16:32:19.955571 arm64_vec-syscfg_SME_not_supported_dup10 skip
11961 16:32:19.958833 arm64_vec-syscfg pass
11962 16:32:19.962091 arm64_za-fork_skipped pass
11963 16:32:19.962176 arm64_za-fork pass
11964 16:32:19.965321 arm64_za-ptrace_SME_not_available skip
11965 16:32:19.968326 arm64_za-ptrace skip
11966 16:32:19.968418 arm64_check_buffer_fill skip
11967 16:32:19.971606 arm64_check_child_memory skip
11968 16:32:19.975299 arm64_check_gcr_el1_cswitch skip
11969 16:32:19.978487 arm64_check_ksm_options skip
11970 16:32:19.981810 arm64_check_mmap_options skip
11971 16:32:19.985220 arm64_check_prctl_check_basic_read pass
11972 16:32:19.988090 arm64_check_prctl_NONE pass
11973 16:32:19.988176 arm64_check_prctl_SYNC skip
11974 16:32:19.991483 arm64_check_prctl_ASYNC skip
11975 16:32:19.994766 arm64_check_prctl_SYNC_ASYNC skip
11976 16:32:19.998262 arm64_check_prctl pass
11977 16:32:20.001665 arm64_check_tags_inclusion skip
11978 16:32:20.001756 arm64_check_user_mem skip
11979 16:32:20.008329 arm64_btitest_nohint_func_call_using_br_x0 skip
11980 16:32:20.011597 arm64_btitest_nohint_func_call_using_br_x16 skip
11981 16:32:20.014962 arm64_btitest_nohint_func_call_using_blr skip
11982 16:32:20.018392 arm64_btitest_bti_none_func_call_using_br_x0 skip
11983 16:32:20.024515 arm64_btitest_bti_none_func_call_using_br_x16 skip
11984 16:32:20.027875 arm64_btitest_bti_none_func_call_using_blr skip
11985 16:32:20.031157 arm64_btitest_bti_c_func_call_using_br_x0 skip
11986 16:32:20.037694 arm64_btitest_bti_c_func_call_using_br_x16 skip
11987 16:32:20.041087 arm64_btitest_bti_c_func_call_using_blr skip
11988 16:32:20.044304 arm64_btitest_bti_j_func_call_using_br_x0 skip
11989 16:32:20.048005 arm64_btitest_bti_j_func_call_using_br_x16 skip
11990 16:32:20.054537 arm64_btitest_bti_j_func_call_using_blr skip
11991 16:32:20.057991 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11992 16:32:20.060687 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11993 16:32:20.064112 arm64_btitest_bti_jc_func_call_using_blr skip
11994 16:32:20.070842 arm64_btitest_paciasp_func_call_using_br_x0 skip
11995 16:32:20.074049 arm64_btitest_paciasp_func_call_using_br_x16 skip
11996 16:32:20.077630 arm64_btitest_paciasp_func_call_using_blr skip
11997 16:32:20.080797 arm64_btitest pass
11998 16:32:20.084074 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11999 16:32:20.090800 arm64_nobtitest_nohint_func_call_using_br_x16 skip
12000 16:32:20.093808 arm64_nobtitest_nohint_func_call_using_blr skip
12001 16:32:20.097151 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
12002 16:32:20.103991 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
12003 16:32:20.107469 arm64_nobtitest_bti_none_func_call_using_blr skip
12004 16:32:20.110225 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
12005 16:32:20.116799 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
12006 16:32:20.120620 arm64_nobtitest_bti_c_func_call_using_blr skip
12007 16:32:20.123432 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
12008 16:32:20.130298 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
12009 16:32:20.133694 arm64_nobtitest_bti_j_func_call_using_blr skip
12010 16:32:20.136990 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
12011 16:32:20.143734 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
12012 16:32:20.146534 arm64_nobtitest_bti_jc_func_call_using_blr skip
12013 16:32:20.149842 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
12014 16:32:20.156848 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
12015 16:32:20.159996 arm64_nobtitest_paciasp_func_call_using_blr skip
12016 16:32:20.163100 arm64_nobtitest pass
12017 16:32:20.166502 arm64_hwcap_cpuinfo_match_RNG pass
12018 16:32:20.166602 arm64_hwcap_sigill_RNG skip
12019 16:32:20.169890 arm64_hwcap_cpuinfo_match_SME pass
12020 16:32:20.173447 arm64_hwcap_sigill_SME pass
12021 16:32:20.176179 arm64_hwcap_cpuinfo_match_SVE pass
12022 16:32:20.179525 arm64_hwcap_sigill_SVE pass
12023 16:32:20.182912 arm64_hwcap_cpuinfo_match_SVE_2 pass
12024 16:32:20.186550 arm64_hwcap_sigill_SVE_2 skip
12025 16:32:20.189363 arm64_hwcap_cpuinfo_match_SVE_AES pass
12026 16:32:20.189452 arm64_hwcap_sigill_SVE_AES skip
12027 16:32:20.196025 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
12028 16:32:20.199369 arm64_hwcap_sigill_SVE2_PMULL skip
12029 16:32:20.202954 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
12030 16:32:20.206023 arm64_hwcap_sigill_SVE2_BITPERM skip
12031 16:32:20.209252 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
12032 16:32:20.212556 arm64_hwcap_sigill_SVE2_SHA3 skip
12033 16:32:20.215895 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
12034 16:32:20.219278 arm64_hwcap_sigill_SVE2_SM4 skip
12035 16:32:20.222596 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
12036 16:32:20.225845 arm64_hwcap_sigill_SVE2_I8MM skip
12037 16:32:20.228909 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
12038 16:32:20.232347 arm64_hwcap_sigill_SVE2_F32MM skip
12039 16:32:20.235727 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
12040 16:32:20.239223 arm64_hwcap_sigill_SVE2_F64MM skip
12041 16:32:20.242464 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12042 16:32:20.245868 arm64_hwcap_sigill_SVE2_BF16 skip
12043 16:32:20.248726 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12044 16:32:20.252177 arm64_hwcap_sigill_SVE2_EBF16 skip
12045 16:32:20.252289 arm64_hwcap pass
12046 16:32:20.255491 arm64_ptrace_read_tpidr_one pass
12047 16:32:20.258695 arm64_ptrace_write_tpidr_one pass
12048 16:32:20.261920 arm64_ptrace_verify_tpidr_one pass
12049 16:32:20.265245 arm64_ptrace_count_tpidrs pass
12050 16:32:20.268595 arm64_ptrace_tpidr2_write pass
12051 16:32:20.272457 arm64_ptrace_tpidr2_read pass
12052 16:32:20.275215 arm64_ptrace_write_tpidr_only pass
12053 16:32:20.275300 arm64_ptrace pass
12054 16:32:20.278550 arm64_syscall-abi_getpid_FPSIMD pass
12055 16:32:20.281955 arm64_syscall-abi_sched_yield_FPSIMD pass
12056 16:32:20.285313 arm64_syscall-abi pass
12057 16:32:20.288770 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12058 16:32:20.294992 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
12059 16:32:20.298466 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
12060 16:32:20.301884 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
12061 16:32:20.308688 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
12062 16:32:20.308793 arm64_tpidr2 pass
12063 16:32:20.314600 + ../../utils/send-to-lava.sh ./output/result.txt
12064 16:32:20.318293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12065 16:32:20.318573 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12067 16:32:20.324956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12068 16:32:20.325222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12070 16:32:20.331076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12071 16:32:20.331335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12073 16:32:20.338184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12074 16:32:20.338453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12076 16:32:20.358532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12077 16:32:20.358813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12079 16:32:20.412551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12080 16:32:20.412886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12082 16:32:20.476353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12083 16:32:20.476669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12085 16:32:20.525581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12086 16:32:20.525897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12088 16:32:20.579968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12089 16:32:20.580279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12091 16:32:20.633146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12092 16:32:20.633471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12094 16:32:20.689735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12095 16:32:20.690089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12097 16:32:20.744421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12098 16:32:20.744733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12100 16:32:20.796398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12101 16:32:20.796733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12103 16:32:20.855649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12104 16:32:20.855960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12106 16:32:20.913411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12107 16:32:20.913753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12109 16:32:20.971285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12110 16:32:20.971596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12112 16:32:21.022523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12113 16:32:21.022839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12115 16:32:21.073720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12116 16:32:21.074031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12118 16:32:21.131319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12119 16:32:21.131634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12121 16:32:21.187239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12122 16:32:21.187586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12124 16:32:21.243594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12125 16:32:21.243927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12127 16:32:21.293475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12128 16:32:21.293791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12130 16:32:21.352993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12131 16:32:21.353308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12133 16:32:21.408738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12134 16:32:21.409074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12136 16:32:21.462771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12137 16:32:21.463124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12139 16:32:21.511935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12140 16:32:21.512286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12142 16:32:21.560700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12143 16:32:21.561016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12145 16:32:21.621819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12146 16:32:21.622154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12148 16:32:21.677103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12150 16:32:21.680329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12151 16:32:21.735351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12152 16:32:21.735714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12154 16:32:21.788209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12155 16:32:21.788530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12157 16:32:21.847352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12158 16:32:21.847663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12160 16:32:21.907503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12161 16:32:21.907845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12163 16:32:21.965678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12164 16:32:21.965986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12166 16:32:22.031361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12167 16:32:22.031668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12169 16:32:22.092276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12170 16:32:22.092583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12172 16:32:22.156679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12173 16:32:22.156999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12175 16:32:22.222805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12176 16:32:22.223142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12178 16:32:22.279625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12179 16:32:22.279942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12181 16:32:22.341235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12182 16:32:22.341560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12184 16:32:22.395135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12185 16:32:22.395439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12187 16:32:22.449191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12189 16:32:22.452408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12190 16:32:22.513731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12191 16:32:22.514045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12193 16:32:22.576668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12194 16:32:22.576976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12196 16:32:22.641087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12198 16:32:22.644084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12199 16:32:22.703079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12200 16:32:22.703392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12202 16:32:22.769710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12203 16:32:22.770060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12205 16:32:22.836486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12206 16:32:22.836842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12208 16:32:22.905363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12209 16:32:22.905690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12211 16:32:22.957584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12213 16:32:22.960619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12214 16:32:23.014652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12215 16:32:23.014974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12217 16:32:23.067665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12218 16:32:23.067980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12220 16:32:23.124230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12221 16:32:23.124573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12223 16:32:23.182982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12224 16:32:23.183289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12226 16:32:23.236258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12227 16:32:23.236569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12229 16:32:23.297464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12230 16:32:23.297775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12232 16:32:23.347476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12233 16:32:23.347810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12235 16:32:23.412029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12236 16:32:23.412351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12238 16:32:23.468926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12239 16:32:23.469237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12241 16:32:23.525773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12242 16:32:23.526117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12244 16:32:23.584801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12245 16:32:23.585145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12247 16:32:23.644164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12248 16:32:23.644507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12250 16:32:23.706262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12251 16:32:23.706577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12253 16:32:23.759905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12254 16:32:23.760276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12256 16:32:23.816747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12257 16:32:23.817069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12259 16:32:23.880088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12260 16:32:23.880422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12262 16:32:23.941984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12263 16:32:23.942333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12265 16:32:24.005477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12266 16:32:24.005797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12268 16:32:24.063363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12269 16:32:24.063695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12271 16:32:24.123619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12272 16:32:24.123933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12274 16:32:24.185288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12275 16:32:24.185607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12277 16:32:24.245553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12278 16:32:24.245892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12280 16:32:24.310630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12281 16:32:24.310965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12283 16:32:24.370597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12284 16:32:24.370909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12286 16:32:24.433538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12287 16:32:24.433888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12289 16:32:24.487784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12290 16:32:24.488127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12292 16:32:24.549692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12293 16:32:24.550008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12295 16:32:24.608573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12296 16:32:24.608921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12298 16:32:24.668888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12299 16:32:24.669230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12301 16:32:24.725897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12302 16:32:24.726254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12304 16:32:24.785766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12305 16:32:24.786111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12307 16:32:24.840149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12308 16:32:24.840470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12310 16:32:24.895722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12311 16:32:24.896041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12313 16:32:24.948294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12314 16:32:24.948654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12316 16:32:25.000805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12318 16:32:25.003626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12319 16:32:25.058945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12320 16:32:25.059312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12322 16:32:25.119722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12323 16:32:25.120068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12325 16:32:25.178450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12326 16:32:25.178766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12328 16:32:25.232768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12329 16:32:25.233110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12331 16:32:25.293984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12332 16:32:25.294333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12334 16:32:25.353803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12335 16:32:25.354137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12337 16:32:25.404974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12339 16:32:25.408377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12340 16:32:25.458329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12341 16:32:25.458681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12343 16:32:25.514531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12344 16:32:25.514870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12346 16:32:25.569168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12347 16:32:25.569488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12349 16:32:25.629531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12350 16:32:25.629853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12352 16:32:25.685760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12353 16:32:25.686089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12355 16:32:25.741142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12356 16:32:25.741532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12358 16:32:25.794397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12359 16:32:25.794717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12361 16:32:25.852584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12362 16:32:25.852901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12364 16:32:25.911569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12365 16:32:25.911897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12367 16:32:25.964807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12368 16:32:25.965153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12370 16:32:26.021783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12371 16:32:26.022100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12373 16:32:26.075909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12374 16:32:26.076233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12376 16:32:26.128483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12377 16:32:26.128802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12379 16:32:26.180694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12380 16:32:26.181039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12382 16:32:26.239366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12383 16:32:26.239729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12385 16:32:26.289978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12386 16:32:26.290356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12388 16:32:26.350262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12389 16:32:26.350607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12391 16:32:26.406403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12392 16:32:26.406723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12394 16:32:26.467955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12395 16:32:26.468301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12397 16:32:26.526787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12398 16:32:26.527141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12400 16:32:26.583704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12401 16:32:26.584024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12403 16:32:26.640377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12404 16:32:26.640728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12406 16:32:26.699260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12407 16:32:26.699610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12409 16:32:26.751814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12410 16:32:26.752159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12412 16:32:26.802453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12413 16:32:26.802799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12415 16:32:26.855699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12416 16:32:26.856033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12418 16:32:26.910311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12419 16:32:26.910632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12421 16:32:26.966927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12422 16:32:26.967273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12424 16:32:27.020263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12425 16:32:27.020617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12427 16:32:27.077074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12428 16:32:27.077422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12430 16:32:27.132599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12431 16:32:27.132917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12433 16:32:27.193613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12434 16:32:27.193934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12436 16:32:27.247742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12437 16:32:27.248058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12439 16:32:27.308861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12440 16:32:27.309185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12442 16:32:27.363860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12443 16:32:27.364177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12445 16:32:27.415190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12446 16:32:27.415520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12448 16:32:27.467071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12449 16:32:27.467398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12451 16:32:27.535135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12452 16:32:27.535500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12454 16:32:27.600151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12455 16:32:27.600492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12457 16:32:27.669620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12458 16:32:27.669959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12460 16:32:27.729688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12461 16:32:27.730043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12463 16:32:27.802475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12464 16:32:27.802909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12466 16:32:27.859438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12467 16:32:27.859848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12469 16:32:27.930882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12470 16:32:27.931250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12472 16:32:27.993661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12473 16:32:27.994025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12475 16:32:28.060154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12476 16:32:28.060591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12478 16:32:28.124044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12479 16:32:28.124379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12481 16:32:28.185022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12482 16:32:28.185362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12484 16:32:28.245166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12485 16:32:28.245533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12487 16:32:28.305668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12488 16:32:28.306027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12490 16:32:28.367694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12491 16:32:28.368057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12493 16:32:28.438064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12494 16:32:28.438415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12496 16:32:28.507313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12497 16:32:28.507666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12499 16:32:28.571403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12500 16:32:28.571779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12502 16:32:28.633057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12503 16:32:28.633404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12505 16:32:28.698025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12506 16:32:28.698392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12508 16:32:28.755766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12510 16:32:28.759331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12511 16:32:28.825800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12512 16:32:28.826159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12514 16:32:28.883727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12516 16:32:28.887003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12517 16:32:28.952876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12518 16:32:28.953219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12520 16:32:29.016140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12522 16:32:29.019420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12523 16:32:29.086402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12524 16:32:29.086761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12526 16:32:29.155077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12527 16:32:29.155398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12529 16:32:29.221122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12530 16:32:29.221457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12532 16:32:29.273144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12533 16:32:29.273464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12535 16:32:29.331620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12536 16:32:29.331936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12538 16:32:29.391164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12539 16:32:29.391483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12541 16:32:29.440728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12542 16:32:29.441056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12544 16:32:29.492281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12545 16:32:29.492633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12547 16:32:29.547386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12548 16:32:29.547715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12550 16:32:29.604189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12552 16:32:29.606698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12553 16:32:29.663448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12555 16:32:29.666563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12556 16:32:29.724248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12557 16:32:29.724577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12559 16:32:29.774859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12560 16:32:29.775209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12562 16:32:29.836387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12563 16:32:29.836757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12565 16:32:29.893405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12566 16:32:29.893749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12568 16:32:29.956217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12569 16:32:29.956577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12571 16:32:30.007362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12572 16:32:30.007730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12574 16:32:30.071005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12575 16:32:30.071343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12577 16:32:30.131264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12578 16:32:30.131584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12580 16:32:30.186194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12581 16:32:30.186509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12583 16:32:30.252694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12584 16:32:30.253035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12586 16:32:30.305681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12587 16:32:30.306030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12589 16:32:30.358499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12590 16:32:30.358819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12592 16:32:30.416207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12593 16:32:30.416556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12595 16:32:30.475639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12596 16:32:30.475983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12598 16:32:30.532246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12599 16:32:30.532413 + set +x
12600 16:32:30.532703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12602 16:32:30.538361 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14396117_1.6.2.3.5>
12603 16:32:30.538674 Received signal: <ENDRUN> 1_kselftest-arm64 14396117_1.6.2.3.5
12604 16:32:30.538783 Ending use of test pattern.
12605 16:32:30.538879 Ending test lava.1_kselftest-arm64 (14396117_1.6.2.3.5), duration 34.21
12607 16:32:30.541758 <LAVA_TEST_RUNNER EXIT>
12608 16:32:30.542045 ok: lava_test_shell seems to have completed
12609 16:32:30.544441 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12610 16:32:30.544653 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12611 16:32:30.544791 end: 3 lava-test-retry (duration 00:00:35) [common]
12612 16:32:30.544920 start: 4 finalize (timeout 00:07:07) [common]
12613 16:32:30.545066 start: 4.1 power-off (timeout 00:00:30) [common]
12614 16:32:30.545376 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
12615 16:32:30.743333 >> Command sent successfully.
12616 16:32:30.746277 Returned 0 in 0 seconds
12617 16:32:30.846738 end: 4.1 power-off (duration 00:00:00) [common]
12619 16:32:30.847224 start: 4.2 read-feedback (timeout 00:07:06) [common]
12620 16:32:30.847548 Listened to connection for namespace 'common' for up to 1s
12621 16:32:31.848464 Finalising connection for namespace 'common'
12622 16:32:31.848677 Disconnecting from shell: Finalise
12623 16:32:31.848788 / #
12624 16:32:31.949123 end: 4.2 read-feedback (duration 00:00:01) [common]
12625 16:32:31.949346 end: 4 finalize (duration 00:00:01) [common]
12626 16:32:31.949499 Cleaning after the job
12627 16:32:31.949634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/ramdisk
12628 16:32:31.952145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/kernel
12629 16:32:31.963153 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/dtb
12630 16:32:31.963436 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/nfsrootfs
12631 16:32:32.022059 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396117/tftp-deploy-7cy_9ryj/modules
12632 16:32:32.027371 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396117
12633 16:32:32.642639 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396117
12634 16:32:32.642903 Job finished correctly