Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 16:36:07.615780 lava-dispatcher, installed at version: 2024.03
2 16:36:07.615990 start: 0 validate
3 16:36:07.616134 Start time: 2024-06-17 16:36:07.616122+00:00 (UTC)
4 16:36:07.616254 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:36:07.616383 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:36:07.876432 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:36:07.876613 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:36:08.140130 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:36:08.140306 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:36:08.396368 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:36:08.396529 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:36:08.653189 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:36:08.653377 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:36:08.918633 validate duration: 1.30
16 16:36:08.918933 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:36:08.919055 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:36:08.919144 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:36:08.919281 Not decompressing ramdisk as can be used compressed.
20 16:36:08.919367 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:36:08.919438 saving as /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/ramdisk/initrd.cpio.gz
22 16:36:08.919516 total size: 5628169 (5 MB)
23 16:36:08.920701 progress 0 % (0 MB)
24 16:36:08.922562 progress 5 % (0 MB)
25 16:36:08.924238 progress 10 % (0 MB)
26 16:36:08.925777 progress 15 % (0 MB)
27 16:36:08.927524 progress 20 % (1 MB)
28 16:36:08.929086 progress 25 % (1 MB)
29 16:36:08.930795 progress 30 % (1 MB)
30 16:36:08.932368 progress 35 % (1 MB)
31 16:36:08.933758 progress 40 % (2 MB)
32 16:36:08.935363 progress 45 % (2 MB)
33 16:36:08.936775 progress 50 % (2 MB)
34 16:36:08.938357 progress 55 % (2 MB)
35 16:36:08.939904 progress 60 % (3 MB)
36 16:36:08.941307 progress 65 % (3 MB)
37 16:36:08.942864 progress 70 % (3 MB)
38 16:36:08.944267 progress 75 % (4 MB)
39 16:36:08.945838 progress 80 % (4 MB)
40 16:36:08.947244 progress 85 % (4 MB)
41 16:36:08.948811 progress 90 % (4 MB)
42 16:36:08.950399 progress 95 % (5 MB)
43 16:36:08.951821 progress 100 % (5 MB)
44 16:36:08.952034 5 MB downloaded in 0.03 s (165.07 MB/s)
45 16:36:08.952188 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:36:08.952436 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:36:08.952523 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:36:08.952614 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:36:08.952785 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:36:08.952856 saving as /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/kernel/Image
52 16:36:08.952918 total size: 54813184 (52 MB)
53 16:36:08.952981 No compression specified
54 16:36:08.954157 progress 0 % (0 MB)
55 16:36:08.968198 progress 5 % (2 MB)
56 16:36:08.982417 progress 10 % (5 MB)
57 16:36:08.997092 progress 15 % (7 MB)
58 16:36:09.012016 progress 20 % (10 MB)
59 16:36:09.026273 progress 25 % (13 MB)
60 16:36:09.040544 progress 30 % (15 MB)
61 16:36:09.054805 progress 35 % (18 MB)
62 16:36:09.068936 progress 40 % (20 MB)
63 16:36:09.082926 progress 45 % (23 MB)
64 16:36:09.097120 progress 50 % (26 MB)
65 16:36:09.111454 progress 55 % (28 MB)
66 16:36:09.126266 progress 60 % (31 MB)
67 16:36:09.141909 progress 65 % (34 MB)
68 16:36:09.157296 progress 70 % (36 MB)
69 16:36:09.171855 progress 75 % (39 MB)
70 16:36:09.186238 progress 80 % (41 MB)
71 16:36:09.200247 progress 85 % (44 MB)
72 16:36:09.214421 progress 90 % (47 MB)
73 16:36:09.228510 progress 95 % (49 MB)
74 16:36:09.243255 progress 100 % (52 MB)
75 16:36:09.243607 52 MB downloaded in 0.29 s (179.83 MB/s)
76 16:36:09.243836 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:36:09.244213 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:36:09.244331 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:36:09.244448 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:36:09.244634 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:36:09.244750 saving as /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/dtb/mt8192-asurada-spherion-r0.dtb
83 16:36:09.244863 total size: 47258 (0 MB)
84 16:36:09.244967 No compression specified
85 16:36:09.246308 progress 69 % (0 MB)
86 16:36:09.246729 progress 100 % (0 MB)
87 16:36:09.246893 0 MB downloaded in 0.00 s (22.23 MB/s)
88 16:36:09.247022 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:36:09.247250 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:36:09.247337 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:36:09.247422 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:36:09.247540 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:36:09.247607 saving as /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/nfsrootfs/full.rootfs.tar
95 16:36:09.247667 total size: 120894716 (115 MB)
96 16:36:09.247730 Using unxz to decompress xz
97 16:36:09.251604 progress 0 % (0 MB)
98 16:36:09.615151 progress 5 % (5 MB)
99 16:36:09.987724 progress 10 % (11 MB)
100 16:36:10.351834 progress 15 % (17 MB)
101 16:36:10.691532 progress 20 % (23 MB)
102 16:36:10.994152 progress 25 % (28 MB)
103 16:36:11.373105 progress 30 % (34 MB)
104 16:36:11.731167 progress 35 % (40 MB)
105 16:36:11.903850 progress 40 % (46 MB)
106 16:36:12.088640 progress 45 % (51 MB)
107 16:36:12.421132 progress 50 % (57 MB)
108 16:36:12.820082 progress 55 % (63 MB)
109 16:36:13.180204 progress 60 % (69 MB)
110 16:36:13.552162 progress 65 % (74 MB)
111 16:36:13.921317 progress 70 % (80 MB)
112 16:36:14.298168 progress 75 % (86 MB)
113 16:36:14.647517 progress 80 % (92 MB)
114 16:36:14.995084 progress 85 % (98 MB)
115 16:36:15.360575 progress 90 % (103 MB)
116 16:36:15.698204 progress 95 % (109 MB)
117 16:36:16.065078 progress 100 % (115 MB)
118 16:36:16.070637 115 MB downloaded in 6.82 s (16.90 MB/s)
119 16:36:16.070941 end: 1.4.1 http-download (duration 00:00:07) [common]
121 16:36:16.071230 end: 1.4 download-retry (duration 00:00:07) [common]
122 16:36:16.071328 start: 1.5 download-retry (timeout 00:09:53) [common]
123 16:36:16.071413 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 16:36:16.071567 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:36:16.071643 saving as /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/modules/modules.tar
126 16:36:16.071706 total size: 8628772 (8 MB)
127 16:36:16.071772 Using unxz to decompress xz
128 16:36:16.076153 progress 0 % (0 MB)
129 16:36:16.098626 progress 5 % (0 MB)
130 16:36:16.124130 progress 10 % (0 MB)
131 16:36:16.148610 progress 15 % (1 MB)
132 16:36:16.173632 progress 20 % (1 MB)
133 16:36:16.200004 progress 25 % (2 MB)
134 16:36:16.225502 progress 30 % (2 MB)
135 16:36:16.252705 progress 35 % (2 MB)
136 16:36:16.277947 progress 40 % (3 MB)
137 16:36:16.303063 progress 45 % (3 MB)
138 16:36:16.329302 progress 50 % (4 MB)
139 16:36:16.354193 progress 55 % (4 MB)
140 16:36:16.379259 progress 60 % (4 MB)
141 16:36:16.406954 progress 65 % (5 MB)
142 16:36:16.431820 progress 70 % (5 MB)
143 16:36:16.455287 progress 75 % (6 MB)
144 16:36:16.478903 progress 80 % (6 MB)
145 16:36:16.506799 progress 85 % (7 MB)
146 16:36:16.535177 progress 90 % (7 MB)
147 16:36:16.560672 progress 95 % (7 MB)
148 16:36:16.585999 progress 100 % (8 MB)
149 16:36:16.591235 8 MB downloaded in 0.52 s (15.84 MB/s)
150 16:36:16.591506 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:36:16.591774 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:36:16.591877 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 16:36:16.591973 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 16:36:20.352376 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr
156 16:36:20.352575 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 16:36:20.352681 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 16:36:20.352855 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_
159 16:36:20.352987 makedir: /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin
160 16:36:20.353088 makedir: /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/tests
161 16:36:20.353196 makedir: /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/results
162 16:36:20.353299 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-add-keys
163 16:36:20.353445 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-add-sources
164 16:36:20.353574 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-background-process-start
165 16:36:20.353700 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-background-process-stop
166 16:36:20.353823 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-common-functions
167 16:36:20.353946 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-echo-ipv4
168 16:36:20.354112 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-install-packages
169 16:36:20.354384 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-installed-packages
170 16:36:20.354522 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-os-build
171 16:36:20.354671 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-probe-channel
172 16:36:20.354796 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-probe-ip
173 16:36:20.354919 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-target-ip
174 16:36:20.355039 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-target-mac
175 16:36:20.355159 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-target-storage
176 16:36:20.355282 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-case
177 16:36:20.355404 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-event
178 16:36:20.355523 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-feedback
179 16:36:20.355654 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-raise
180 16:36:20.355778 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-reference
181 16:36:20.355900 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-runner
182 16:36:20.356022 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-set
183 16:36:20.356157 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-test-shell
184 16:36:20.356283 Updating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-add-keys (debian)
185 16:36:20.356444 Updating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-add-sources (debian)
186 16:36:20.356587 Updating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-install-packages (debian)
187 16:36:20.356732 Updating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-installed-packages (debian)
188 16:36:20.356891 Updating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/bin/lava-os-build (debian)
189 16:36:20.357031 Creating /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/environment
190 16:36:20.357160 LAVA metadata
191 16:36:20.357257 - LAVA_JOB_ID=14396177
192 16:36:20.357349 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:36:20.357487 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 16:36:20.357560 skipped lava-vland-overlay
195 16:36:20.357645 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:36:20.357725 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 16:36:20.357785 skipped lava-multinode-overlay
198 16:36:20.357856 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:36:20.357932 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 16:36:20.358004 Loading test definitions
201 16:36:20.358091 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 16:36:20.358206 Using /lava-14396177 at stage 0
203 16:36:20.358576 uuid=14396177_1.6.2.3.1 testdef=None
204 16:36:20.358679 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:36:20.358764 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 16:36:20.359228 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:36:20.359451 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 16:36:20.360024 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:36:20.360254 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 16:36:20.360779 runner path: /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/0/tests/0_timesync-off test_uuid 14396177_1.6.2.3.1
213 16:36:20.360935 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:36:20.361157 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 16:36:20.361228 Using /lava-14396177 at stage 0
217 16:36:20.361323 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:36:20.361409 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/0/tests/1_kselftest-dt'
219 16:36:22.981689 Running '/usr/bin/git checkout kernelci.org
220 16:36:23.131768 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 16:36:23.132506 uuid=14396177_1.6.2.3.5 testdef=None
222 16:36:23.132672 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 16:36:23.132921 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 16:36:23.133688 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:36:23.133936 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 16:36:23.134998 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:36:23.135264 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 16:36:23.136282 runner path: /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/0/tests/1_kselftest-dt test_uuid 14396177_1.6.2.3.5
232 16:36:23.136374 BOARD='mt8192-asurada-spherion-r0'
233 16:36:23.136437 BRANCH='cip-gitlab'
234 16:36:23.136505 SKIPFILE='/dev/null'
235 16:36:23.136569 SKIP_INSTALL='True'
236 16:36:23.136624 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:36:23.136682 TST_CASENAME=''
238 16:36:23.136736 TST_CMDFILES='dt'
239 16:36:23.136883 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:36:23.137237 Creating lava-test-runner.conf files
242 16:36:23.137305 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396177/lava-overlay-4elymj7_/lava-14396177/0 for stage 0
243 16:36:23.137422 - 0_timesync-off
244 16:36:23.137491 - 1_kselftest-dt
245 16:36:23.137585 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 16:36:23.137670 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 16:36:30.895656 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 16:36:30.895819 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 16:36:30.895937 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:36:30.896057 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 16:36:30.896194 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 16:36:31.064107 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:36:31.064536 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 16:36:31.064721 extracting modules file /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr
255 16:36:31.320286 extracting modules file /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396177/extract-overlay-ramdisk-sqwmep83/ramdisk
256 16:36:31.546649 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:36:31.546799 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 16:36:31.546894 [common] Applying overlay to NFS
259 16:36:31.546965 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396177/compress-overlay-jhvirecf/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr
260 16:36:32.514821 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:36:32.514978 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 16:36:32.515070 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:36:32.515158 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 16:36:32.515241 Building ramdisk /var/lib/lava/dispatcher/tmp/14396177/extract-overlay-ramdisk-sqwmep83/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396177/extract-overlay-ramdisk-sqwmep83/ramdisk
265 16:36:32.863440 >> 130466 blocks
266 16:36:34.906826 rename /var/lib/lava/dispatcher/tmp/14396177/extract-overlay-ramdisk-sqwmep83/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/ramdisk/ramdisk.cpio.gz
267 16:36:34.907262 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 16:36:34.907391 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 16:36:34.907495 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 16:36:34.907602 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/kernel/Image']
271 16:36:49.590332 Returned 0 in 14 seconds
272 16:36:49.690940 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/kernel/image.itb
273 16:36:50.061511 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:36:50.061869 output: Created: Mon Jun 17 17:36:49 2024
275 16:36:50.061940 output: Image 0 (kernel-1)
276 16:36:50.062003 output: Description:
277 16:36:50.062064 output: Created: Mon Jun 17 17:36:49 2024
278 16:36:50.062125 output: Type: Kernel Image
279 16:36:50.062233 output: Compression: lzma compressed
280 16:36:50.062297 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
281 16:36:50.062358 output: Architecture: AArch64
282 16:36:50.062427 output: OS: Linux
283 16:36:50.062487 output: Load Address: 0x00000000
284 16:36:50.062544 output: Entry Point: 0x00000000
285 16:36:50.062597 output: Hash algo: crc32
286 16:36:50.062653 output: Hash value: 106ffd6f
287 16:36:50.062707 output: Image 1 (fdt-1)
288 16:36:50.062760 output: Description: mt8192-asurada-spherion-r0
289 16:36:50.062827 output: Created: Mon Jun 17 17:36:49 2024
290 16:36:50.062915 output: Type: Flat Device Tree
291 16:36:50.063004 output: Compression: uncompressed
292 16:36:50.063084 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 16:36:50.063165 output: Architecture: AArch64
294 16:36:50.063245 output: Hash algo: crc32
295 16:36:50.063327 output: Hash value: 0f8e4d2e
296 16:36:50.063412 output: Image 2 (ramdisk-1)
297 16:36:50.063492 output: Description: unavailable
298 16:36:50.063580 output: Created: Mon Jun 17 17:36:49 2024
299 16:36:50.063662 output: Type: RAMDisk Image
300 16:36:50.063748 output: Compression: Unknown Compression
301 16:36:50.063829 output: Data Size: 18746589 Bytes = 18307.22 KiB = 17.88 MiB
302 16:36:50.063910 output: Architecture: AArch64
303 16:36:50.064011 output: OS: Linux
304 16:36:50.064094 output: Load Address: unavailable
305 16:36:50.064229 output: Entry Point: unavailable
306 16:36:50.064310 output: Hash algo: crc32
307 16:36:50.064395 output: Hash value: 719b427e
308 16:36:50.064475 output: Default Configuration: 'conf-1'
309 16:36:50.064559 output: Configuration 0 (conf-1)
310 16:36:50.064709 output: Description: mt8192-asurada-spherion-r0
311 16:36:50.064793 output: Kernel: kernel-1
312 16:36:50.064881 output: Init Ramdisk: ramdisk-1
313 16:36:50.064961 output: FDT: fdt-1
314 16:36:50.065041 output: Loadables: kernel-1
315 16:36:50.065134 output:
316 16:36:50.065364 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 16:36:50.065465 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 16:36:50.065573 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 16:36:50.065694 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 16:36:50.065807 No LXC device requested
321 16:36:50.065926 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:36:50.066045 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 16:36:50.066154 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:36:50.066305 Checking files for TFTP limit of 4294967296 bytes.
325 16:36:50.066982 end: 1 tftp-deploy (duration 00:00:41) [common]
326 16:36:50.067119 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:36:50.067235 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:36:50.067410 substitutions:
329 16:36:50.067512 - {DTB}: 14396177/tftp-deploy-2f5rhium/dtb/mt8192-asurada-spherion-r0.dtb
330 16:36:50.067603 - {INITRD}: 14396177/tftp-deploy-2f5rhium/ramdisk/ramdisk.cpio.gz
331 16:36:50.067689 - {KERNEL}: 14396177/tftp-deploy-2f5rhium/kernel/Image
332 16:36:50.067774 - {LAVA_MAC}: None
333 16:36:50.067871 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr
334 16:36:50.067932 - {NFS_SERVER_IP}: 192.168.201.1
335 16:36:50.067986 - {PRESEED_CONFIG}: None
336 16:36:50.068038 - {PRESEED_LOCAL}: None
337 16:36:50.068091 - {RAMDISK}: 14396177/tftp-deploy-2f5rhium/ramdisk/ramdisk.cpio.gz
338 16:36:50.068156 - {ROOT_PART}: None
339 16:36:50.068212 - {ROOT}: None
340 16:36:50.068276 - {SERVER_IP}: 192.168.201.1
341 16:36:50.068360 - {TEE}: None
342 16:36:50.068450 Parsed boot commands:
343 16:36:50.068531 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:36:50.068766 Parsed boot commands: tftpboot 192.168.201.1 14396177/tftp-deploy-2f5rhium/kernel/image.itb 14396177/tftp-deploy-2f5rhium/kernel/cmdline
345 16:36:50.068892 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:36:50.069005 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:36:50.069122 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:36:50.069249 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:36:50.069352 Not connected, no need to disconnect.
350 16:36:50.069455 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:36:50.069565 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:36:50.069658 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 16:36:50.073339 Setting prompt string to ['lava-test: # ']
354 16:36:50.073728 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:36:50.073875 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:36:50.074003 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:36:50.074134 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:36:50.074364 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 16:37:04.067128 Returned 0 in 13 seconds
360 16:37:04.167820 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 16:37:04.168187 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 16:37:04.168328 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 16:37:04.168446 Setting prompt string to 'Starting depthcharge on Spherion...'
365 16:37:04.168549 Changing prompt to 'Starting depthcharge on Spherion...'
366 16:37:04.168651 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 16:37:04.169081 [Enter `^Ec?' for help]
368 16:37:04.169174
369 16:37:04.169276
370 16:37:04.169369 F0: 102B 0000
371 16:37:04.169462
372 16:37:04.169555 F3: 1001 0000 [0200]
373 16:37:04.169627
374 16:37:04.169704 F3: 1001 0000
375 16:37:04.169770
376 16:37:04.169866 F7: 102D 0000
377 16:37:04.169930
378 16:37:04.169990 F1: 0000 0000
379 16:37:04.170050
380 16:37:04.170106 V0: 0000 0000 [0001]
381 16:37:04.170178
382 16:37:04.170254 00: 0007 8000
383 16:37:04.170315
384 16:37:04.170370 01: 0000 0000
385 16:37:04.170425
386 16:37:04.170483 BP: 0C00 0209 [0000]
387 16:37:04.170539
388 16:37:04.170596 G0: 1182 0000
389 16:37:04.170652
390 16:37:04.170705 EC: 0000 0021 [4000]
391 16:37:04.170778
392 16:37:04.170833 S7: 0000 0000 [0000]
393 16:37:04.170887
394 16:37:04.170940 CC: 0000 0000 [0001]
395 16:37:04.170997
396 16:37:04.171052 T0: 0000 0040 [010F]
397 16:37:04.171106
398 16:37:04.171159 Jump to BL
399 16:37:04.171213
400 16:37:04.171287
401 16:37:04.171343
402 16:37:04.171396 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 16:37:04.171459 ARM64: Exception handlers installed.
404 16:37:04.171516 ARM64: Testing exception
405 16:37:04.171571 ARM64: Done test exception
406 16:37:04.171624 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 16:37:04.171680 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 16:37:04.171735 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 16:37:04.171806 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 16:37:04.171863 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 16:37:04.171921 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 16:37:04.171978 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 16:37:04.172033 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 16:37:04.172087 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 16:37:04.172142 WDT: Last reset was cold boot
416 16:37:04.172196 SPI1(PAD0) initialized at 2873684 Hz
417 16:37:04.172249 SPI5(PAD0) initialized at 992727 Hz
418 16:37:04.172322 VBOOT: Loading verstage.
419 16:37:04.172377 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 16:37:04.172431 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 16:37:04.172489 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 16:37:04.172546 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 16:37:04.172600 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 16:37:04.172654 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 16:37:04.172709 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 16:37:04.172763
427 16:37:04.172835
428 16:37:04.172891 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 16:37:04.172946 ARM64: Exception handlers installed.
430 16:37:04.173000 ARM64: Testing exception
431 16:37:04.173057 ARM64: Done test exception
432 16:37:04.173111 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 16:37:04.173166 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 16:37:04.173220 Probing TPM: . done!
435 16:37:04.173274 TPM ready after 0 ms
436 16:37:04.173347 Connected to device vid:did:rid of 1ae0:0028:00
437 16:37:04.173403 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 16:37:04.173458 Initialized TPM device CR50 revision 0
439 16:37:04.173512 tlcl_send_startup: Startup return code is 0
440 16:37:04.173569 TPM: setup succeeded
441 16:37:04.173624 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 16:37:04.173680 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 16:37:04.173734 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 16:37:04.173788 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 16:37:04.173855 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 16:37:04.173913 in-header: 03 07 00 00 08 00 00 00
447 16:37:04.173967 in-data: aa e4 47 04 13 02 00 00
448 16:37:04.174021 Chrome EC: UHEPI supported
449 16:37:04.174075 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 16:37:04.174129 in-header: 03 a9 00 00 08 00 00 00
451 16:37:04.174197 in-data: 84 60 60 08 00 00 00 00
452 16:37:04.174254 Phase 1
453 16:37:04.174307 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 16:37:04.174374 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 16:37:04.174432 VB2:vb2_check_recovery() Recovery was requested manually
456 16:37:04.174487 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 16:37:04.174542 Recovery requested (1009000e)
458 16:37:04.174598 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 16:37:04.174653 tlcl_extend: response is 0
460 16:37:04.174707 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 16:37:04.174764 tlcl_extend: response is 0
462 16:37:04.174818 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 16:37:04.174887 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 16:37:04.174945 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 16:37:04.175000
466 16:37:04.175053
467 16:37:04.175107 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 16:37:04.175162 ARM64: Exception handlers installed.
469 16:37:04.175216 ARM64: Testing exception
470 16:37:04.175269 ARM64: Done test exception
471 16:37:04.175324 pmic_efuse_setting: Set efuses in 11 msecs
472 16:37:04.175392 pmwrap_interface_init: Select PMIF_VLD_RDY
473 16:37:04.175452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 16:37:04.175506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 16:37:04.175763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 16:37:04.175826 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 16:37:04.175930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 16:37:04.176017 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 16:37:04.176102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 16:37:04.176187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 16:37:04.176271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 16:37:04.176356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 16:37:04.176444 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 16:37:04.176500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 16:37:04.176555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 16:37:04.176609 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 16:37:04.176663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 16:37:04.176717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 16:37:04.176771 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 16:37:04.176824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 16:37:04.176878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 16:37:04.176963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 16:37:04.177048 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 16:37:04.177140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 16:37:04.177197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 16:37:04.177251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 16:37:04.177341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 16:37:04.177429 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 16:37:04.177520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 16:37:04.177605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 16:37:04.177695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 16:37:04.177783 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 16:37:04.177869 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 16:37:04.177961 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 16:37:04.178020 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 16:37:04.178075 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 16:37:04.178130 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 16:37:04.178205 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 16:37:04.178262 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 16:37:04.178320 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 16:37:04.178376 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 16:37:04.178430 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 16:37:04.178514 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 16:37:04.178599 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 16:37:04.178692 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 16:37:04.178769 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 16:37:04.178826 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 16:37:04.178880 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 16:37:04.178942 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 16:37:04.179016 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 16:37:04.179072 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 16:37:04.179130 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 16:37:04.179186 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 16:37:04.179243 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 16:37:04.179308 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 16:37:04.179383 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 16:37:04.179440 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 16:37:04.179508 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 16:37:04.179566 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 16:37:04.179621 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 16:37:04.179675 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 16:37:04.179733 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
533 16:37:04.179787 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 16:37:04.179841 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 16:37:04.179895 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 16:37:04.179951 [RTC]rtc_get_frequency_meter,154: input=15, output=834
537 16:37:04.180023 [RTC]rtc_get_frequency_meter,154: input=7, output=709
538 16:37:04.180080 [RTC]rtc_get_frequency_meter,154: input=11, output=771
539 16:37:04.180133 [RTC]rtc_get_frequency_meter,154: input=13, output=803
540 16:37:04.180187 [RTC]rtc_get_frequency_meter,154: input=12, output=787
541 16:37:04.180244 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 16:37:04.180300 [RTC]rtc_get_frequency_meter,154: input=13, output=803
543 16:37:04.180354 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 16:37:04.180408 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 16:37:04.180674 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 16:37:04.180811 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 16:37:04.180928 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 16:37:04.181037 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 16:37:04.181140 ADC[4]: Raw value=905988 ID=7
550 16:37:04.181237 ADC[3]: Raw value=213652 ID=1
551 16:37:04.181337 RAM Code: 0x71
552 16:37:04.181438 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 16:37:04.181526 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 16:37:04.181622 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 16:37:04.181740 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 16:37:04.181830 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 16:37:04.181936 in-header: 03 07 00 00 08 00 00 00
558 16:37:04.182024 in-data: aa e4 47 04 13 02 00 00
559 16:37:04.182123 Chrome EC: UHEPI supported
560 16:37:04.182252 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 16:37:04.182351 in-header: 03 a9 00 00 08 00 00 00
562 16:37:04.182437 in-data: 84 60 60 08 00 00 00 00
563 16:37:04.182543 MRC: failed to locate region type 0.
564 16:37:04.182641 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 16:37:04.182761 DRAM-K: Running full calibration
566 16:37:04.182855 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 16:37:04.182950 header.status = 0x0
568 16:37:04.183054 header.version = 0x6 (expected: 0x6)
569 16:37:04.183150 header.size = 0xd00 (expected: 0xd00)
570 16:37:04.183234 header.flags = 0x0
571 16:37:04.183319 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 16:37:04.183412 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 16:37:04.183521 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 16:37:04.183614 dram_init: ddr_geometry: 2
575 16:37:04.183700 [EMI] MDL number = 2
576 16:37:04.183783 [EMI] Get MDL freq = 0
577 16:37:04.183866 dram_init: ddr_type: 0
578 16:37:04.183963 is_discrete_lpddr4: 1
579 16:37:04.184049 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 16:37:04.184139
581 16:37:04.184224
582 16:37:04.184321 [Bian_co] ETT version 0.0.0.1
583 16:37:04.184419 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 16:37:04.184527
585 16:37:04.184616 dramc_set_vcore_voltage set vcore to 650000
586 16:37:04.184711 Read voltage for 800, 4
587 16:37:04.184810 Vio18 = 0
588 16:37:04.184895 Vcore = 650000
589 16:37:04.184977 Vdram = 0
590 16:37:04.185060 Vddq = 0
591 16:37:04.185151 Vmddr = 0
592 16:37:04.185234 dram_init: config_dvfs: 1
593 16:37:04.185334 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 16:37:04.185431 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 16:37:04.185538 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
596 16:37:04.185624 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
597 16:37:04.185709 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 16:37:04.185793 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 16:37:04.185877 MEM_TYPE=3, freq_sel=18
600 16:37:04.185972 sv_algorithm_assistance_LP4_1600
601 16:37:04.186063 ============ PULL DRAM RESETB DOWN ============
602 16:37:04.186150 ========== PULL DRAM RESETB DOWN end =========
603 16:37:04.186228 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 16:37:04.186283 ===================================
605 16:37:04.186336 LPDDR4 DRAM CONFIGURATION
606 16:37:04.186389 ===================================
607 16:37:04.186455 EX_ROW_EN[0] = 0x0
608 16:37:04.186515 EX_ROW_EN[1] = 0x0
609 16:37:04.186570 LP4Y_EN = 0x0
610 16:37:04.186622 WORK_FSP = 0x0
611 16:37:04.186676 WL = 0x2
612 16:37:04.186728 RL = 0x2
613 16:37:04.186780 BL = 0x2
614 16:37:04.186834 RPST = 0x0
615 16:37:04.186887 RD_PRE = 0x0
616 16:37:04.186947 WR_PRE = 0x1
617 16:37:04.187000 WR_PST = 0x0
618 16:37:04.187059 DBI_WR = 0x0
619 16:37:04.187119 DBI_RD = 0x0
620 16:37:04.187173 OTF = 0x1
621 16:37:04.187226 ===================================
622 16:37:04.187285 ===================================
623 16:37:04.187343 ANA top config
624 16:37:04.187428 ===================================
625 16:37:04.187523 DLL_ASYNC_EN = 0
626 16:37:04.187608 ALL_SLAVE_EN = 1
627 16:37:04.187673 NEW_RANK_MODE = 1
628 16:37:04.187730 DLL_IDLE_MODE = 1
629 16:37:04.187784 LP45_APHY_COMB_EN = 1
630 16:37:04.187837 TX_ODT_DIS = 1
631 16:37:04.187891 NEW_8X_MODE = 1
632 16:37:04.187944 ===================================
633 16:37:04.188009 ===================================
634 16:37:04.188072 data_rate = 1600
635 16:37:04.188125 CKR = 1
636 16:37:04.188179 DQ_P2S_RATIO = 8
637 16:37:04.188231 ===================================
638 16:37:04.188284 CA_P2S_RATIO = 8
639 16:37:04.188337 DQ_CA_OPEN = 0
640 16:37:04.188395 DQ_SEMI_OPEN = 0
641 16:37:04.188452 CA_SEMI_OPEN = 0
642 16:37:04.188517 CA_FULL_RATE = 0
643 16:37:04.188576 DQ_CKDIV4_EN = 1
644 16:37:04.188630 CA_CKDIV4_EN = 1
645 16:37:04.188683 CA_PREDIV_EN = 0
646 16:37:04.188736 PH8_DLY = 0
647 16:37:04.188798 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 16:37:04.188851 DQ_AAMCK_DIV = 4
649 16:37:04.188904 CA_AAMCK_DIV = 4
650 16:37:04.188958 CA_ADMCK_DIV = 4
651 16:37:04.189011 DQ_TRACK_CA_EN = 0
652 16:37:04.189063 CA_PICK = 800
653 16:37:04.189117 CA_MCKIO = 800
654 16:37:04.189188 MCKIO_SEMI = 0
655 16:37:04.189242 PLL_FREQ = 3068
656 16:37:04.189295 DQ_UI_PI_RATIO = 32
657 16:37:04.189348 CA_UI_PI_RATIO = 0
658 16:37:04.189413 ===================================
659 16:37:04.189466 ===================================
660 16:37:04.189520 memory_type:LPDDR4
661 16:37:04.189579 GP_NUM : 10
662 16:37:04.189633 SRAM_EN : 1
663 16:37:04.189686 MD32_EN : 0
664 16:37:04.189740 ===================================
665 16:37:04.190019 [ANA_INIT] >>>>>>>>>>>>>>
666 16:37:04.190088 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 16:37:04.190156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 16:37:04.190225 ===================================
669 16:37:04.190280 data_rate = 1600,PCW = 0X7600
670 16:37:04.190333 ===================================
671 16:37:04.190386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 16:37:04.190446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 16:37:04.190507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 16:37:04.190562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 16:37:04.190623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 16:37:04.190676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 16:37:04.190736 [ANA_INIT] flow start
678 16:37:04.190796 [ANA_INIT] PLL >>>>>>>>
679 16:37:04.190849 [ANA_INIT] PLL <<<<<<<<
680 16:37:04.190902 [ANA_INIT] MIDPI >>>>>>>>
681 16:37:04.190954 [ANA_INIT] MIDPI <<<<<<<<
682 16:37:04.191006 [ANA_INIT] DLL >>>>>>>>
683 16:37:04.191064 [ANA_INIT] flow end
684 16:37:04.191126 ============ LP4 DIFF to SE enter ============
685 16:37:04.191183 ============ LP4 DIFF to SE exit ============
686 16:37:04.191242 [ANA_INIT] <<<<<<<<<<<<<
687 16:37:04.191303 [Flow] Enable top DCM control >>>>>
688 16:37:04.191357 [Flow] Enable top DCM control <<<<<
689 16:37:04.191411 Enable DLL master slave shuffle
690 16:37:04.191471 ==============================================================
691 16:37:04.191525 Gating Mode config
692 16:37:04.191589 ==============================================================
693 16:37:04.191651 Config description:
694 16:37:04.191705 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 16:37:04.191760 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 16:37:04.191814 SELPH_MODE 0: By rank 1: By Phase
697 16:37:04.191872 ==============================================================
698 16:37:04.191926 GAT_TRACK_EN = 1
699 16:37:04.191979 RX_GATING_MODE = 2
700 16:37:04.192038 RX_GATING_TRACK_MODE = 2
701 16:37:04.192099 SELPH_MODE = 1
702 16:37:04.192159 PICG_EARLY_EN = 1
703 16:37:04.192211 VALID_LAT_VALUE = 1
704 16:37:04.192265 ==============================================================
705 16:37:04.192324 Enter into Gating configuration >>>>
706 16:37:04.192384 Exit from Gating configuration <<<<
707 16:37:04.192438 Enter into DVFS_PRE_config >>>>>
708 16:37:04.192491 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 16:37:04.192547 Exit from DVFS_PRE_config <<<<<
710 16:37:04.192600 Enter into PICG configuration >>>>
711 16:37:04.192653 Exit from PICG configuration <<<<
712 16:37:04.192706 [RX_INPUT] configuration >>>>>
713 16:37:04.192765 [RX_INPUT] configuration <<<<<
714 16:37:04.192830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 16:37:04.192885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 16:37:04.192938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 16:37:04.192991 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 16:37:04.193051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 16:37:04.193104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 16:37:04.193157 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 16:37:04.193217 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 16:37:04.193270 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 16:37:04.193334 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 16:37:04.193388 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 16:37:04.193441 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 16:37:04.193494 ===================================
727 16:37:04.193547 LPDDR4 DRAM CONFIGURATION
728 16:37:04.193600 ===================================
729 16:37:04.193662 EX_ROW_EN[0] = 0x0
730 16:37:04.193716 EX_ROW_EN[1] = 0x0
731 16:37:04.193775 LP4Y_EN = 0x0
732 16:37:04.193838 WORK_FSP = 0x0
733 16:37:04.193892 WL = 0x2
734 16:37:04.193945 RL = 0x2
735 16:37:04.193997 BL = 0x2
736 16:37:04.194057 RPST = 0x0
737 16:37:04.194110 RD_PRE = 0x0
738 16:37:04.194179 WR_PRE = 0x1
739 16:37:04.194241 WR_PST = 0x0
740 16:37:04.194301 DBI_WR = 0x0
741 16:37:04.194354 DBI_RD = 0x0
742 16:37:04.194407 OTF = 0x1
743 16:37:04.194459 ===================================
744 16:37:04.194519 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 16:37:04.194573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 16:37:04.194626 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 16:37:04.194679 ===================================
748 16:37:04.194732 LPDDR4 DRAM CONFIGURATION
749 16:37:04.194800 ===================================
750 16:37:04.194857 EX_ROW_EN[0] = 0x10
751 16:37:04.194909 EX_ROW_EN[1] = 0x0
752 16:37:04.194962 LP4Y_EN = 0x0
753 16:37:04.195020 WORK_FSP = 0x0
754 16:37:04.195073 WL = 0x2
755 16:37:04.195125 RL = 0x2
756 16:37:04.195177 BL = 0x2
757 16:37:04.195229 RPST = 0x0
758 16:37:04.195282 RD_PRE = 0x0
759 16:37:04.195333 WR_PRE = 0x1
760 16:37:04.195391 WR_PST = 0x0
761 16:37:04.195451 DBI_WR = 0x0
762 16:37:04.195513 DBI_RD = 0x0
763 16:37:04.195573 OTF = 0x1
764 16:37:04.195626 ===================================
765 16:37:04.195679 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 16:37:04.195732 nWR fixed to 40
767 16:37:04.195793 [ModeRegInit_LP4] CH0 RK0
768 16:37:04.195852 [ModeRegInit_LP4] CH0 RK1
769 16:37:04.195910 [ModeRegInit_LP4] CH1 RK0
770 16:37:04.195970 [ModeRegInit_LP4] CH1 RK1
771 16:37:04.196027 match AC timing 13
772 16:37:04.196086 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 16:37:04.196346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 16:37:04.196407 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 16:37:04.196500 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 16:37:04.196585 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 16:37:04.196680 [EMI DOE] emi_dcm 0
778 16:37:04.196747 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 16:37:04.196803 ==
780 16:37:04.196863 Dram Type= 6, Freq= 0, CH_0, rank 0
781 16:37:04.196917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 16:37:04.196971 ==
783 16:37:04.197030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 16:37:04.197093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 16:37:04.197149 [CA 0] Center 37 (7~68) winsize 62
786 16:37:04.197209 [CA 1] Center 37 (6~68) winsize 63
787 16:37:04.197261 [CA 2] Center 34 (4~65) winsize 62
788 16:37:04.197314 [CA 3] Center 34 (4~65) winsize 62
789 16:37:04.197367 [CA 4] Center 33 (3~64) winsize 62
790 16:37:04.197420 [CA 5] Center 33 (3~64) winsize 62
791 16:37:04.197472
792 16:37:04.197525 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 16:37:04.197578
794 16:37:04.197630 [CATrainingPosCal] consider 1 rank data
795 16:37:04.197692 u2DelayCellTimex100 = 270/100 ps
796 16:37:04.197751 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 16:37:04.197805 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 16:37:04.197857 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 16:37:04.197910 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 16:37:04.197962 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 16:37:04.198023 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 16:37:04.198082
803 16:37:04.198142 CA PerBit enable=1, Macro0, CA PI delay=33
804 16:37:04.198210
805 16:37:04.198266 [CBTSetCACLKResult] CA Dly = 33
806 16:37:04.198326 CS Dly: 6 (0~37)
807 16:37:04.198380 ==
808 16:37:04.198433 Dram Type= 6, Freq= 0, CH_0, rank 1
809 16:37:04.198485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 16:37:04.198538 ==
811 16:37:04.198591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 16:37:04.198651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 16:37:04.198706 [CA 0] Center 37 (6~68) winsize 63
814 16:37:04.198758 [CA 1] Center 37 (6~68) winsize 63
815 16:37:04.198812 [CA 2] Center 34 (4~65) winsize 62
816 16:37:04.198873 [CA 3] Center 34 (4~65) winsize 62
817 16:37:04.198926 [CA 4] Center 33 (3~64) winsize 62
818 16:37:04.198978 [CA 5] Center 33 (3~64) winsize 62
819 16:37:04.199031
820 16:37:04.199083 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 16:37:04.199136
822 16:37:04.199196 [CATrainingPosCal] consider 2 rank data
823 16:37:04.199250 u2DelayCellTimex100 = 270/100 ps
824 16:37:04.199311 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 16:37:04.199365 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
826 16:37:04.199417 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 16:37:04.199476 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 16:37:04.199534 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 16:37:04.199593 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 16:37:04.199647
831 16:37:04.199707 CA PerBit enable=1, Macro0, CA PI delay=33
832 16:37:04.199766
833 16:37:04.199819 [CBTSetCACLKResult] CA Dly = 33
834 16:37:04.199871 CS Dly: 6 (0~38)
835 16:37:04.199923
836 16:37:04.199976 ----->DramcWriteLeveling(PI) begin...
837 16:37:04.200040 ==
838 16:37:04.200093 Dram Type= 6, Freq= 0, CH_0, rank 0
839 16:37:04.200154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 16:37:04.200207 ==
841 16:37:04.200260 Write leveling (Byte 0): 31 => 31
842 16:37:04.200320 Write leveling (Byte 1): 29 => 29
843 16:37:04.200373 DramcWriteLeveling(PI) end<-----
844 16:37:04.200426
845 16:37:04.200485 ==
846 16:37:04.200545 Dram Type= 6, Freq= 0, CH_0, rank 0
847 16:37:04.200598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 16:37:04.200658 ==
849 16:37:04.200717 [Gating] SW mode calibration
850 16:37:04.200775 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 16:37:04.200830 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 16:37:04.200890 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 16:37:04.200950 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 16:37:04.201008 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 16:37:04.201062 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 16:37:04.201115 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:37:04.201168 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:37:04.201221 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:37:04.201279 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:37:04.201333 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:37:04.201386 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:37:04.201438 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:37:04.201497 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:37:04.201551 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:37:04.201604 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:37:04.201657 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:37:04.201710 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 16:37:04.201763 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 16:37:04.201816 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 16:37:04.201868 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 16:37:04.201928 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 16:37:04.201984 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 16:37:04.202044 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:37:04.202104 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:37:04.202157 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 16:37:04.202221 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 16:37:04.202274 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 16:37:04.202326 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
879 16:37:04.202379 0 9 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
880 16:37:04.202440 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 16:37:04.202686 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:37:04.202745 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 16:37:04.202805 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 16:37:04.202860 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 16:37:04.202920 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
886 16:37:04.202973 0 10 8 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (0 0)
887 16:37:04.203026 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
888 16:37:04.203079 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 16:37:04.203138 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:37:04.203193 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:37:04.203254 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 16:37:04.203317 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 16:37:04.203371 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 16:37:04.203430 0 11 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
895 16:37:04.203482 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
896 16:37:04.203535 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 16:37:04.203587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:37:04.203640 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:37:04.203701 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 16:37:04.203753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 16:37:04.203806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 16:37:04.203858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 16:37:04.203918 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 16:37:04.203971 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 16:37:04.204023 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:37:04.204075 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:37:04.204128 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:37:04.204181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:37:04.204233 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:37:04.204285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:37:04.204337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:37:04.204394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:37:04.204446 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:37:04.204508 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 16:37:04.204567 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 16:37:04.204621 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 16:37:04.204694 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 16:37:04.204779 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 16:37:04.204865 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 16:37:04.204937 Total UI for P1: 0, mck2ui 16
921 16:37:04.205000 best dqsien dly found for B0: ( 0, 14, 8)
922 16:37:04.205056 Total UI for P1: 0, mck2ui 16
923 16:37:04.205116 best dqsien dly found for B1: ( 0, 14, 10)
924 16:37:04.205170 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
925 16:37:04.205223 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
926 16:37:04.205276
927 16:37:04.205328 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
928 16:37:04.205381 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
929 16:37:04.205434 [Gating] SW calibration Done
930 16:37:04.205494 ==
931 16:37:04.205547 Dram Type= 6, Freq= 0, CH_0, rank 0
932 16:37:04.205605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 16:37:04.205661 ==
934 16:37:04.205720 RX Vref Scan: 0
935 16:37:04.205780
936 16:37:04.205837 RX Vref 0 -> 0, step: 1
937 16:37:04.205891
938 16:37:04.205944 RX Delay -130 -> 252, step: 16
939 16:37:04.206003 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 16:37:04.206057 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
941 16:37:04.206110 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 16:37:04.206171 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
943 16:37:04.206232 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
944 16:37:04.206286 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 16:37:04.206338 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 16:37:04.206391 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
947 16:37:04.206443 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
948 16:37:04.206495 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
949 16:37:04.206547 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 16:37:04.206599 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 16:37:04.206660 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
952 16:37:04.206718 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
953 16:37:04.206772 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 16:37:04.206833 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
955 16:37:04.206886 ==
956 16:37:04.206938 Dram Type= 6, Freq= 0, CH_0, rank 0
957 16:37:04.206991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 16:37:04.207044 ==
959 16:37:04.207096 DQS Delay:
960 16:37:04.207148 DQS0 = 0, DQS1 = 0
961 16:37:04.207200 DQM Delay:
962 16:37:04.207252 DQM0 = 84, DQM1 = 71
963 16:37:04.207305 DQ Delay:
964 16:37:04.207357 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
965 16:37:04.207417 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
966 16:37:04.207470 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
967 16:37:04.207521 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
968 16:37:04.207573
969 16:37:04.207625
970 16:37:04.207677 ==
971 16:37:04.207729 Dram Type= 6, Freq= 0, CH_0, rank 0
972 16:37:04.207788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 16:37:04.207849 ==
974 16:37:04.207907
975 16:37:04.207961
976 16:37:04.208019 TX Vref Scan disable
977 16:37:04.208072 == TX Byte 0 ==
978 16:37:04.208125 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 16:37:04.208178 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 16:37:04.208231 == TX Byte 1 ==
981 16:37:04.208283 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
982 16:37:04.208336 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
983 16:37:04.208388 ==
984 16:37:04.208447 Dram Type= 6, Freq= 0, CH_0, rank 0
985 16:37:04.208501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 16:37:04.208554 ==
987 16:37:04.208606 TX Vref=22, minBit 4, minWin=27, winSum=441
988 16:37:04.208666 TX Vref=24, minBit 5, minWin=27, winSum=444
989 16:37:04.208920 TX Vref=26, minBit 5, minWin=27, winSum=447
990 16:37:04.208981 TX Vref=28, minBit 8, minWin=27, winSum=447
991 16:37:04.209035 TX Vref=30, minBit 4, minWin=27, winSum=445
992 16:37:04.209088 TX Vref=32, minBit 9, minWin=26, winSum=441
993 16:37:04.209141 [TxChooseVref] Worse bit 5, Min win 27, Win sum 447, Final Vref 26
994 16:37:04.209194
995 16:37:04.209247 Final TX Range 1 Vref 26
996 16:37:04.209300
997 16:37:04.209361 ==
998 16:37:04.209414 Dram Type= 6, Freq= 0, CH_0, rank 0
999 16:37:04.209467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 16:37:04.209521 ==
1001 16:37:04.209574
1002 16:37:04.209625
1003 16:37:04.209677 TX Vref Scan disable
1004 16:37:04.209729 == TX Byte 0 ==
1005 16:37:04.209782 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 16:37:04.209834 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 16:37:04.209886 == TX Byte 1 ==
1008 16:37:04.209946 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1009 16:37:04.210005 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1010 16:37:04.210062
1011 16:37:04.210117 [DATLAT]
1012 16:37:04.210189 Freq=800, CH0 RK0
1013 16:37:04.210244
1014 16:37:04.210296 DATLAT Default: 0xa
1015 16:37:04.210349 0, 0xFFFF, sum = 0
1016 16:37:04.210403 1, 0xFFFF, sum = 0
1017 16:37:04.210456 2, 0xFFFF, sum = 0
1018 16:37:04.210510 3, 0xFFFF, sum = 0
1019 16:37:04.210563 4, 0xFFFF, sum = 0
1020 16:37:04.210617 5, 0xFFFF, sum = 0
1021 16:37:04.210670 6, 0xFFFF, sum = 0
1022 16:37:04.210723 7, 0xFFFF, sum = 0
1023 16:37:04.210777 8, 0xFFFF, sum = 0
1024 16:37:04.210830 9, 0x0, sum = 1
1025 16:37:04.210900 10, 0x0, sum = 2
1026 16:37:04.210956 11, 0x0, sum = 3
1027 16:37:04.211011 12, 0x0, sum = 4
1028 16:37:04.211065 best_step = 10
1029 16:37:04.211117
1030 16:37:04.211169 ==
1031 16:37:04.211222 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 16:37:04.211275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 16:37:04.211329 ==
1034 16:37:04.211382 RX Vref Scan: 1
1035 16:37:04.211445
1036 16:37:04.211503 Set Vref Range= 32 -> 127
1037 16:37:04.211557
1038 16:37:04.211610 RX Vref 32 -> 127, step: 1
1039 16:37:04.211662
1040 16:37:04.211714 RX Delay -111 -> 252, step: 8
1041 16:37:04.211767
1042 16:37:04.211819 Set Vref, RX VrefLevel [Byte0]: 32
1043 16:37:04.211871 [Byte1]: 32
1044 16:37:04.211924
1045 16:37:04.211982 Set Vref, RX VrefLevel [Byte0]: 33
1046 16:37:04.212036 [Byte1]: 33
1047 16:37:04.212089
1048 16:37:04.212141 Set Vref, RX VrefLevel [Byte0]: 34
1049 16:37:04.212192 [Byte1]: 34
1050 16:37:04.212245
1051 16:37:04.212295 Set Vref, RX VrefLevel [Byte0]: 35
1052 16:37:04.212347 [Byte1]: 35
1053 16:37:04.212400
1054 16:37:04.212458 Set Vref, RX VrefLevel [Byte0]: 36
1055 16:37:04.212512 [Byte1]: 36
1056 16:37:04.212564
1057 16:37:04.212615 Set Vref, RX VrefLevel [Byte0]: 37
1058 16:37:04.212675 [Byte1]: 37
1059 16:37:04.212732
1060 16:37:04.212785 Set Vref, RX VrefLevel [Byte0]: 38
1061 16:37:04.212837 [Byte1]: 38
1062 16:37:04.212890
1063 16:37:04.212973 Set Vref, RX VrefLevel [Byte0]: 39
1064 16:37:04.213056 [Byte1]: 39
1065 16:37:04.213141
1066 16:37:04.213207 Set Vref, RX VrefLevel [Byte0]: 40
1067 16:37:04.213262 [Byte1]: 40
1068 16:37:04.213315
1069 16:37:04.213367 Set Vref, RX VrefLevel [Byte0]: 41
1070 16:37:04.213419 [Byte1]: 41
1071 16:37:04.213481
1072 16:37:04.213533 Set Vref, RX VrefLevel [Byte0]: 42
1073 16:37:04.213585 [Byte1]: 42
1074 16:37:04.213638
1075 16:37:04.213690 Set Vref, RX VrefLevel [Byte0]: 43
1076 16:37:04.213742 [Byte1]: 43
1077 16:37:04.213794
1078 16:37:04.213846 Set Vref, RX VrefLevel [Byte0]: 44
1079 16:37:04.213898 [Byte1]: 44
1080 16:37:04.213957
1081 16:37:04.214010 Set Vref, RX VrefLevel [Byte0]: 45
1082 16:37:04.214062 [Byte1]: 45
1083 16:37:04.214114
1084 16:37:04.214172 Set Vref, RX VrefLevel [Byte0]: 46
1085 16:37:04.214226 [Byte1]: 46
1086 16:37:04.214278
1087 16:37:04.214330 Set Vref, RX VrefLevel [Byte0]: 47
1088 16:37:04.214381 [Byte1]: 47
1089 16:37:04.214434
1090 16:37:04.214485 Set Vref, RX VrefLevel [Byte0]: 48
1091 16:37:04.214537 [Byte1]: 48
1092 16:37:04.214596
1093 16:37:04.214649 Set Vref, RX VrefLevel [Byte0]: 49
1094 16:37:04.214702 [Byte1]: 49
1095 16:37:04.214754
1096 16:37:04.214806 Set Vref, RX VrefLevel [Byte0]: 50
1097 16:37:04.214858 [Byte1]: 50
1098 16:37:04.214910
1099 16:37:04.214962 Set Vref, RX VrefLevel [Byte0]: 51
1100 16:37:04.215013 [Byte1]: 51
1101 16:37:04.215065
1102 16:37:04.215123 Set Vref, RX VrefLevel [Byte0]: 52
1103 16:37:04.215177 [Byte1]: 52
1104 16:37:04.215229
1105 16:37:04.215280 Set Vref, RX VrefLevel [Byte0]: 53
1106 16:37:04.215332 [Byte1]: 53
1107 16:37:04.215384
1108 16:37:04.215436 Set Vref, RX VrefLevel [Byte0]: 54
1109 16:37:04.215488 [Byte1]: 54
1110 16:37:04.215540
1111 16:37:04.215592 Set Vref, RX VrefLevel [Byte0]: 55
1112 16:37:04.215644 [Byte1]: 55
1113 16:37:04.215703
1114 16:37:04.215755 Set Vref, RX VrefLevel [Byte0]: 56
1115 16:37:04.215808 [Byte1]: 56
1116 16:37:04.215859
1117 16:37:04.215919 Set Vref, RX VrefLevel [Byte0]: 57
1118 16:37:04.215977 [Byte1]: 57
1119 16:37:04.216029
1120 16:37:04.216080 Set Vref, RX VrefLevel [Byte0]: 58
1121 16:37:04.216132 [Byte1]: 58
1122 16:37:04.216190
1123 16:37:04.216243 Set Vref, RX VrefLevel [Byte0]: 59
1124 16:37:04.216295 [Byte1]: 59
1125 16:37:04.216347
1126 16:37:04.216399 Set Vref, RX VrefLevel [Byte0]: 60
1127 16:37:04.216451 [Byte1]: 60
1128 16:37:04.216503
1129 16:37:04.216554 Set Vref, RX VrefLevel [Byte0]: 61
1130 16:37:04.216615 [Byte1]: 61
1131 16:37:04.216672
1132 16:37:04.216724 Set Vref, RX VrefLevel [Byte0]: 62
1133 16:37:04.216783 [Byte1]: 62
1134 16:37:04.216835
1135 16:37:04.216886 Set Vref, RX VrefLevel [Byte0]: 63
1136 16:37:04.216937 [Byte1]: 63
1137 16:37:04.216989
1138 16:37:04.217040 Set Vref, RX VrefLevel [Byte0]: 64
1139 16:37:04.217092 [Byte1]: 64
1140 16:37:04.217143
1141 16:37:04.217195 Set Vref, RX VrefLevel [Byte0]: 65
1142 16:37:04.217247 [Byte1]: 65
1143 16:37:04.217299
1144 16:37:04.217358 Set Vref, RX VrefLevel [Byte0]: 66
1145 16:37:04.217411 [Byte1]: 66
1146 16:37:04.217463
1147 16:37:04.217514 Set Vref, RX VrefLevel [Byte0]: 67
1148 16:37:04.217566 [Byte1]: 67
1149 16:37:04.217618
1150 16:37:04.217669 Set Vref, RX VrefLevel [Byte0]: 68
1151 16:37:04.217721 [Byte1]: 68
1152 16:37:04.217773
1153 16:37:04.217824 Set Vref, RX VrefLevel [Byte0]: 69
1154 16:37:04.217882 [Byte1]: 69
1155 16:37:04.217935
1156 16:37:04.217986 Set Vref, RX VrefLevel [Byte0]: 70
1157 16:37:04.218228 [Byte1]: 70
1158 16:37:04.218289
1159 16:37:04.218342 Set Vref, RX VrefLevel [Byte0]: 71
1160 16:37:04.218403 [Byte1]: 71
1161 16:37:04.218457
1162 16:37:04.218509 Set Vref, RX VrefLevel [Byte0]: 72
1163 16:37:04.218561 [Byte1]: 72
1164 16:37:04.218614
1165 16:37:04.218684 Set Vref, RX VrefLevel [Byte0]: 73
1166 16:37:04.218773 [Byte1]: 73
1167 16:37:04.218829
1168 16:37:04.218881 Set Vref, RX VrefLevel [Byte0]: 74
1169 16:37:04.218933 [Byte1]: 74
1170 16:37:04.218995
1171 16:37:04.219047 Set Vref, RX VrefLevel [Byte0]: 75
1172 16:37:04.219099 [Byte1]: 75
1173 16:37:04.219159
1174 16:37:04.219213 Set Vref, RX VrefLevel [Byte0]: 76
1175 16:37:04.219274 [Byte1]: 76
1176 16:37:04.219328
1177 16:37:04.219381 Set Vref, RX VrefLevel [Byte0]: 77
1178 16:37:04.219432 [Byte1]: 77
1179 16:37:04.219484
1180 16:37:04.219535 Set Vref, RX VrefLevel [Byte0]: 78
1181 16:37:04.219591 [Byte1]: 78
1182 16:37:04.219643
1183 16:37:04.219695 Set Vref, RX VrefLevel [Byte0]: 79
1184 16:37:04.219746 [Byte1]: 79
1185 16:37:04.219806
1186 16:37:04.219858 Set Vref, RX VrefLevel [Byte0]: 80
1187 16:37:04.219910 [Byte1]: 80
1188 16:37:04.219970
1189 16:37:04.220024 Set Vref, RX VrefLevel [Byte0]: 81
1190 16:37:04.220075 [Byte1]: 81
1191 16:37:04.220133
1192 16:37:04.220187 Set Vref, RX VrefLevel [Byte0]: 82
1193 16:37:04.220242 [Byte1]: 82
1194 16:37:04.220299
1195 16:37:04.220353 Final RX Vref Byte 0 = 64 to rank0
1196 16:37:04.220411 Final RX Vref Byte 1 = 58 to rank0
1197 16:37:04.220464 Final RX Vref Byte 0 = 64 to rank1
1198 16:37:04.220516 Final RX Vref Byte 1 = 58 to rank1==
1199 16:37:04.220567 Dram Type= 6, Freq= 0, CH_0, rank 0
1200 16:37:04.220625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 16:37:04.220678 ==
1202 16:37:04.220730 DQS Delay:
1203 16:37:04.220782 DQS0 = 0, DQS1 = 0
1204 16:37:04.220834 DQM Delay:
1205 16:37:04.220893 DQM0 = 87, DQM1 = 75
1206 16:37:04.220946 DQ Delay:
1207 16:37:04.220998 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1208 16:37:04.221050 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1209 16:37:04.221102 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1210 16:37:04.221161 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1211 16:37:04.221220
1212 16:37:04.221271
1213 16:37:04.221330 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1214 16:37:04.221388 CH0 RK0: MR19=606, MR18=4729
1215 16:37:04.221441 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1216 16:37:04.221493
1217 16:37:04.221545 ----->DramcWriteLeveling(PI) begin...
1218 16:37:04.221598 ==
1219 16:37:04.221650 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 16:37:04.221706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 16:37:04.221800 ==
1222 16:37:04.221892 Write leveling (Byte 0): 31 => 31
1223 16:37:04.221981 Write leveling (Byte 1): 30 => 30
1224 16:37:04.222071 DramcWriteLeveling(PI) end<-----
1225 16:37:04.222153
1226 16:37:04.222220 ==
1227 16:37:04.222274 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 16:37:04.222327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 16:37:04.222380 ==
1230 16:37:04.222433 [Gating] SW mode calibration
1231 16:37:04.222485 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1232 16:37:04.222538 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1233 16:37:04.222591 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1234 16:37:04.222643 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1235 16:37:04.222695 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 16:37:04.222747 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1237 16:37:04.222800 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 16:37:04.222852 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 16:37:04.222904 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 16:37:04.222955 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 16:37:04.223007 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 16:37:04.223059 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 16:37:04.223111 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 16:37:04.223163 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 16:37:04.223215 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 16:37:04.223268 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 16:37:04.223320 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 16:37:04.223371 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 16:37:04.223423 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 16:37:04.223475 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1251 16:37:04.223527 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1252 16:37:04.223578 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1253 16:37:04.223630 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 16:37:04.223682 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 16:37:04.223735 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 16:37:04.223786 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 16:37:04.223839 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 16:37:04.223890 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 16:37:04.223943 0 9 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1260 16:37:04.223994 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1261 16:37:04.224046 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 16:37:04.224099 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 16:37:04.224151 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 16:37:04.224202 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 16:37:04.224254 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 16:37:04.224306 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 16:37:04.224358 0 10 8 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (1 0)
1268 16:37:04.224410 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 16:37:04.224462 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 16:37:04.224514 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 16:37:04.224566 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 16:37:04.224812 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 16:37:04.224870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 16:37:04.224924 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1275 16:37:04.224976 0 11 8 | B1->B0 | 2f2f 3939 | 1 1 | (0 0) (1 1)
1276 16:37:04.225028 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1277 16:37:04.225081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 16:37:04.225133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 16:37:04.225185 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 16:37:04.225237 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 16:37:04.225288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 16:37:04.225340 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 16:37:04.225392 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1284 16:37:04.225444 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 16:37:04.225495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 16:37:04.225547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 16:37:04.225599 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 16:37:04.225650 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 16:37:04.225701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 16:37:04.225753 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 16:37:04.225805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 16:37:04.225856 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 16:37:04.225908 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 16:37:04.225960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 16:37:04.226012 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 16:37:04.226063 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 16:37:04.226115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 16:37:04.226191 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 16:37:04.226248 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1300 16:37:04.226300 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1301 16:37:04.226352 Total UI for P1: 0, mck2ui 16
1302 16:37:04.226404 best dqsien dly found for B0: ( 0, 14, 8)
1303 16:37:04.226456 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1304 16:37:04.226508 Total UI for P1: 0, mck2ui 16
1305 16:37:04.226559 best dqsien dly found for B1: ( 0, 14, 12)
1306 16:37:04.226611 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1307 16:37:04.226663 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1308 16:37:04.226714
1309 16:37:04.226765 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1310 16:37:04.226818 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1311 16:37:04.226870 [Gating] SW calibration Done
1312 16:37:04.226931 ==
1313 16:37:04.226986 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 16:37:04.227043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 16:37:04.227097 ==
1316 16:37:04.227149 RX Vref Scan: 0
1317 16:37:04.227201
1318 16:37:04.227253 RX Vref 0 -> 0, step: 1
1319 16:37:04.227305
1320 16:37:04.227356 RX Delay -130 -> 252, step: 16
1321 16:37:04.227408 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1322 16:37:04.227460 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1323 16:37:04.227512 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1324 16:37:04.227564 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1325 16:37:04.227616 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1326 16:37:04.227667 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1327 16:37:04.227720 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1328 16:37:04.227786 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1329 16:37:04.227840 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1330 16:37:04.227892 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1331 16:37:04.227944 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1332 16:37:04.227996 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1333 16:37:04.228047 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1334 16:37:04.228099 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1335 16:37:04.228151 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1336 16:37:04.228211 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1337 16:37:04.228273 ==
1338 16:37:04.228327 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 16:37:04.228379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 16:37:04.228432 ==
1341 16:37:04.228484 DQS Delay:
1342 16:37:04.228535 DQS0 = 0, DQS1 = 0
1343 16:37:04.228586 DQM Delay:
1344 16:37:04.228638 DQM0 = 84, DQM1 = 75
1345 16:37:04.228689 DQ Delay:
1346 16:37:04.228741 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1347 16:37:04.228792 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1348 16:37:04.228843 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1349 16:37:04.228895 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1350 16:37:04.228953
1351 16:37:04.229007
1352 16:37:04.229057 ==
1353 16:37:04.229117 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 16:37:04.229174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 16:37:04.229228 ==
1356 16:37:04.229279
1357 16:37:04.229331
1358 16:37:04.229383 TX Vref Scan disable
1359 16:37:04.229441 == TX Byte 0 ==
1360 16:37:04.229494 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1361 16:37:04.229546 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1362 16:37:04.229598 == TX Byte 1 ==
1363 16:37:04.229649 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1364 16:37:04.229700 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1365 16:37:04.229751 ==
1366 16:37:04.229803 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 16:37:04.229855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 16:37:04.229907 ==
1369 16:37:04.229958 TX Vref=22, minBit 9, minWin=27, winSum=446
1370 16:37:04.230016 TX Vref=24, minBit 9, minWin=27, winSum=449
1371 16:37:04.230077 TX Vref=26, minBit 9, minWin=27, winSum=448
1372 16:37:04.230132 TX Vref=28, minBit 8, minWin=27, winSum=447
1373 16:37:04.230219 TX Vref=30, minBit 8, minWin=27, winSum=445
1374 16:37:04.230302 TX Vref=32, minBit 9, minWin=27, winSum=445
1375 16:37:04.230389 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 24
1376 16:37:04.230452
1377 16:37:04.230506 Final TX Range 1 Vref 24
1378 16:37:04.230558
1379 16:37:04.230610 ==
1380 16:37:04.230661 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 16:37:04.230723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 16:37:04.230776 ==
1383 16:37:04.230834
1384 16:37:04.230889
1385 16:37:04.230943 TX Vref Scan disable
1386 16:37:04.230996 == TX Byte 0 ==
1387 16:37:04.231242 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1388 16:37:04.231308 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1389 16:37:04.231369 == TX Byte 1 ==
1390 16:37:04.231422 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1391 16:37:04.231475 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1392 16:37:04.231526
1393 16:37:04.231578 [DATLAT]
1394 16:37:04.231629 Freq=800, CH0 RK1
1395 16:37:04.231688
1396 16:37:04.231744 DATLAT Default: 0xa
1397 16:37:04.231804 0, 0xFFFF, sum = 0
1398 16:37:04.231857 1, 0xFFFF, sum = 0
1399 16:37:04.231917 2, 0xFFFF, sum = 0
1400 16:37:04.231976 3, 0xFFFF, sum = 0
1401 16:37:04.232030 4, 0xFFFF, sum = 0
1402 16:37:04.232084 5, 0xFFFF, sum = 0
1403 16:37:04.232137 6, 0xFFFF, sum = 0
1404 16:37:04.232189 7, 0xFFFF, sum = 0
1405 16:37:04.232241 8, 0xFFFF, sum = 0
1406 16:37:04.232302 9, 0x0, sum = 1
1407 16:37:04.232355 10, 0x0, sum = 2
1408 16:37:04.232419 11, 0x0, sum = 3
1409 16:37:04.232477 12, 0x0, sum = 4
1410 16:37:04.232535 best_step = 10
1411 16:37:04.232588
1412 16:37:04.232639 ==
1413 16:37:04.232691 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 16:37:04.232750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 16:37:04.232809 ==
1416 16:37:04.232861 RX Vref Scan: 0
1417 16:37:04.232913
1418 16:37:04.232964 RX Vref 0 -> 0, step: 1
1419 16:37:04.233016
1420 16:37:04.233073 RX Delay -111 -> 252, step: 8
1421 16:37:04.233133 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1422 16:37:04.233187 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1423 16:37:04.233241 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1424 16:37:04.233299 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1425 16:37:04.233356 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1426 16:37:04.233408 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1427 16:37:04.233460 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1428 16:37:04.233511 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1429 16:37:04.233572 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1430 16:37:04.233631 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1431 16:37:04.233683 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1432 16:37:04.233734 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1433 16:37:04.233785 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1434 16:37:04.233845 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1435 16:37:04.233899 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1436 16:37:04.233956 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1437 16:37:04.234008 ==
1438 16:37:04.234059 Dram Type= 6, Freq= 0, CH_0, rank 1
1439 16:37:04.234118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 16:37:04.234187 ==
1441 16:37:04.234240 DQS Delay:
1442 16:37:04.234299 DQS0 = 0, DQS1 = 0
1443 16:37:04.234353 DQM Delay:
1444 16:37:04.234405 DQM0 = 85, DQM1 = 76
1445 16:37:04.234456 DQ Delay:
1446 16:37:04.234515 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1447 16:37:04.234574 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1448 16:37:04.234635 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1449 16:37:04.234695 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1450 16:37:04.234747
1451 16:37:04.234798
1452 16:37:04.234857 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d05, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
1453 16:37:04.234911 CH0 RK1: MR19=606, MR18=3D05
1454 16:37:04.234963 CH0_RK1: MR19=0x606, MR18=0x3D05, DQSOSC=394, MR23=63, INC=95, DEC=63
1455 16:37:04.235029 [RxdqsGatingPostProcess] freq 800
1456 16:37:04.235083 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1457 16:37:04.235141 Pre-setting of DQS Precalculation
1458 16:37:04.235199 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1459 16:37:04.235253 ==
1460 16:37:04.235305 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 16:37:04.235357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 16:37:04.235409 ==
1463 16:37:04.235461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 16:37:04.235513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 16:37:04.235573 [CA 0] Center 36 (6~67) winsize 62
1466 16:37:04.235626 [CA 1] Center 37 (6~68) winsize 63
1467 16:37:04.235683 [CA 2] Center 34 (4~65) winsize 62
1468 16:37:04.235741 [CA 3] Center 34 (3~65) winsize 63
1469 16:37:04.235800 [CA 4] Center 34 (4~65) winsize 62
1470 16:37:04.235851 [CA 5] Center 34 (3~65) winsize 63
1471 16:37:04.235909
1472 16:37:04.235963 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1473 16:37:04.236020
1474 16:37:04.236083 [CATrainingPosCal] consider 1 rank data
1475 16:37:04.236135 u2DelayCellTimex100 = 270/100 ps
1476 16:37:04.236187 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 16:37:04.236239 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1478 16:37:04.236303 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1479 16:37:04.236356 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1480 16:37:04.236408 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 16:37:04.236460 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1482 16:37:04.236514
1483 16:37:04.236565 CA PerBit enable=1, Macro0, CA PI delay=34
1484 16:37:04.236616
1485 16:37:04.236668 [CBTSetCACLKResult] CA Dly = 34
1486 16:37:04.236724 CS Dly: 5 (0~36)
1487 16:37:04.236776 ==
1488 16:37:04.236827 Dram Type= 6, Freq= 0, CH_1, rank 1
1489 16:37:04.236890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 16:37:04.236942 ==
1491 16:37:04.236994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1492 16:37:04.237046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1493 16:37:04.237105 [CA 0] Center 36 (6~67) winsize 62
1494 16:37:04.237157 [CA 1] Center 36 (6~67) winsize 62
1495 16:37:04.237208 [CA 2] Center 34 (4~65) winsize 62
1496 16:37:04.237265 [CA 3] Center 34 (3~65) winsize 63
1497 16:37:04.237319 [CA 4] Center 34 (4~65) winsize 62
1498 16:37:04.237370 [CA 5] Center 34 (4~65) winsize 62
1499 16:37:04.237427
1500 16:37:04.237485 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1501 16:37:04.237537
1502 16:37:04.237589 [CATrainingPosCal] consider 2 rank data
1503 16:37:04.237651 u2DelayCellTimex100 = 270/100 ps
1504 16:37:04.237703 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1505 16:37:04.237755 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1506 16:37:04.237813 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1507 16:37:04.237875 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1508 16:37:04.237933 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1509 16:37:04.237985 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1510 16:37:04.238036
1511 16:37:04.238088 CA PerBit enable=1, Macro0, CA PI delay=34
1512 16:37:04.238139
1513 16:37:04.238210 [CBTSetCACLKResult] CA Dly = 34
1514 16:37:04.238272 CS Dly: 6 (0~38)
1515 16:37:04.238327
1516 16:37:04.238387 ----->DramcWriteLeveling(PI) begin...
1517 16:37:04.238443 ==
1518 16:37:04.238517 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 16:37:04.238608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 16:37:04.238893 ==
1521 16:37:04.238959 Write leveling (Byte 0): 26 => 26
1522 16:37:04.239016 Write leveling (Byte 1): 27 => 27
1523 16:37:04.239069 DramcWriteLeveling(PI) end<-----
1524 16:37:04.239122
1525 16:37:04.239184 ==
1526 16:37:04.239239 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 16:37:04.239304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 16:37:04.239364 ==
1529 16:37:04.239417 [Gating] SW mode calibration
1530 16:37:04.239469 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1531 16:37:04.239523 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1532 16:37:04.239574 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1533 16:37:04.239633 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1534 16:37:04.239686 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1535 16:37:04.239738 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 16:37:04.239796 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 16:37:04.239854 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 16:37:04.239913 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 16:37:04.239966 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 16:37:04.240017 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 16:37:04.240071 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 16:37:04.240123 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 16:37:04.240181 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 16:37:04.240233 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 16:37:04.240284 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 16:37:04.240343 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 16:37:04.240395 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 16:37:04.240458 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 16:37:04.240511 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1550 16:37:04.240562 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 16:37:04.240614 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1552 16:37:04.240665 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 16:37:04.240717 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 16:37:04.240768 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 16:37:04.240827 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 16:37:04.240892 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 16:37:04.240945 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1558 16:37:04.241003 0 9 8 | B1->B0 | 3131 3231 | 0 1 | (0 0) (0 0)
1559 16:37:04.241061 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 16:37:04.241114 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 16:37:04.241166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 16:37:04.241217 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 16:37:04.241277 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 16:37:04.241329 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1565 16:37:04.241380 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1566 16:37:04.241438 0 10 8 | B1->B0 | 2c2c 2525 | 0 0 | (1 1) (0 0)
1567 16:37:04.241495 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 16:37:04.241553 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 16:37:04.241612 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 16:37:04.241664 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 16:37:04.241716 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 16:37:04.241774 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 16:37:04.241832 0 11 4 | B1->B0 | 2626 2423 | 1 1 | (0 0) (0 0)
1574 16:37:04.241884 0 11 8 | B1->B0 | 3939 3c3c | 0 0 | (0 0) (0 0)
1575 16:37:04.241936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 16:37:04.241995 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 16:37:04.242050 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 16:37:04.242108 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 16:37:04.242181 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 16:37:04.242241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 16:37:04.242294 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1582 16:37:04.242352 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1583 16:37:04.242404 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 16:37:04.242462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 16:37:04.242515 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 16:37:04.242567 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 16:37:04.242626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 16:37:04.242678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 16:37:04.242736 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 16:37:04.242795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 16:37:04.242847 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 16:37:04.242907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 16:37:04.242958 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 16:37:04.243009 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 16:37:04.243069 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 16:37:04.243128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 16:37:04.243180 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1598 16:37:04.243237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1599 16:37:04.243295 Total UI for P1: 0, mck2ui 16
1600 16:37:04.243349 best dqsien dly found for B0: ( 0, 14, 4)
1601 16:37:04.243401 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1602 16:37:04.243459 Total UI for P1: 0, mck2ui 16
1603 16:37:04.243513 best dqsien dly found for B1: ( 0, 14, 8)
1604 16:37:04.243564 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1605 16:37:04.243622 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1606 16:37:04.243680
1607 16:37:04.243933 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1608 16:37:04.244000 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1609 16:37:04.244053 [Gating] SW calibration Done
1610 16:37:04.244110 ==
1611 16:37:04.244170 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 16:37:04.244223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 16:37:04.244275 ==
1614 16:37:04.244327 RX Vref Scan: 0
1615 16:37:04.244378
1616 16:37:04.244430 RX Vref 0 -> 0, step: 1
1617 16:37:04.244489
1618 16:37:04.244541 RX Delay -130 -> 252, step: 16
1619 16:37:04.244599 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1620 16:37:04.244658 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1621 16:37:04.244710 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1622 16:37:04.244762 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1623 16:37:04.244822 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1624 16:37:04.244877 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1625 16:37:04.244938 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1626 16:37:04.244991 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1627 16:37:04.245054 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1628 16:37:04.245108 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1629 16:37:04.245159 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1630 16:37:04.245210 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1631 16:37:04.245261 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1632 16:37:04.245312 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1633 16:37:04.245370 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1634 16:37:04.245429 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1635 16:37:04.245489 ==
1636 16:37:04.245547 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 16:37:04.245599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 16:37:04.245651 ==
1639 16:37:04.245702 DQS Delay:
1640 16:37:04.245754 DQS0 = 0, DQS1 = 0
1641 16:37:04.245811 DQM Delay:
1642 16:37:04.245864 DQM0 = 89, DQM1 = 79
1643 16:37:04.245915 DQ Delay:
1644 16:37:04.245966 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1645 16:37:04.246024 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1646 16:37:04.246082 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1647 16:37:04.246142 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1648 16:37:04.246206
1649 16:37:04.246260
1650 16:37:04.246311 ==
1651 16:37:04.246397 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 16:37:04.246470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 16:37:04.246537 ==
1654 16:37:04.246591
1655 16:37:04.246642
1656 16:37:04.246693 TX Vref Scan disable
1657 16:37:04.246744 == TX Byte 0 ==
1658 16:37:04.246795 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1659 16:37:04.246855 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1660 16:37:04.246908 == TX Byte 1 ==
1661 16:37:04.246964 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1662 16:37:04.247037 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1663 16:37:04.247121 ==
1664 16:37:04.247207 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 16:37:04.247281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 16:37:04.247346 ==
1667 16:37:04.247399 TX Vref=22, minBit 10, minWin=26, winSum=444
1668 16:37:04.247458 TX Vref=24, minBit 8, minWin=27, winSum=448
1669 16:37:04.247511 TX Vref=26, minBit 9, minWin=27, winSum=448
1670 16:37:04.247569 TX Vref=28, minBit 9, minWin=27, winSum=450
1671 16:37:04.247622 TX Vref=30, minBit 15, minWin=27, winSum=451
1672 16:37:04.247674 TX Vref=32, minBit 8, minWin=27, winSum=445
1673 16:37:04.247726 [TxChooseVref] Worse bit 15, Min win 27, Win sum 451, Final Vref 30
1674 16:37:04.247778
1675 16:37:04.247843 Final TX Range 1 Vref 30
1676 16:37:04.247900
1677 16:37:04.247958 ==
1678 16:37:04.248011 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 16:37:04.248062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 16:37:04.248121 ==
1681 16:37:04.248172
1682 16:37:04.248223
1683 16:37:04.248274 TX Vref Scan disable
1684 16:37:04.248325 == TX Byte 0 ==
1685 16:37:04.248376 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1686 16:37:04.248435 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1687 16:37:04.248487 == TX Byte 1 ==
1688 16:37:04.248538 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1689 16:37:04.248597 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1690 16:37:04.248655
1691 16:37:04.248706 [DATLAT]
1692 16:37:04.248757 Freq=800, CH1 RK0
1693 16:37:04.248809
1694 16:37:04.248860 DATLAT Default: 0xa
1695 16:37:04.248911 0, 0xFFFF, sum = 0
1696 16:37:04.248971 1, 0xFFFF, sum = 0
1697 16:37:04.249024 2, 0xFFFF, sum = 0
1698 16:37:04.249076 3, 0xFFFF, sum = 0
1699 16:37:04.249135 4, 0xFFFF, sum = 0
1700 16:37:04.249193 5, 0xFFFF, sum = 0
1701 16:37:04.249246 6, 0xFFFF, sum = 0
1702 16:37:04.249298 7, 0xFFFF, sum = 0
1703 16:37:04.249350 8, 0xFFFF, sum = 0
1704 16:37:04.249402 9, 0x0, sum = 1
1705 16:37:04.249454 10, 0x0, sum = 2
1706 16:37:04.249512 11, 0x0, sum = 3
1707 16:37:04.249567 12, 0x0, sum = 4
1708 16:37:04.249619 best_step = 10
1709 16:37:04.249671
1710 16:37:04.249729 ==
1711 16:37:04.249781 Dram Type= 6, Freq= 0, CH_1, rank 0
1712 16:37:04.249839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1713 16:37:04.249891 ==
1714 16:37:04.249965 RX Vref Scan: 1
1715 16:37:04.250059
1716 16:37:04.250150 Set Vref Range= 32 -> 127
1717 16:37:04.250216
1718 16:37:04.250281 RX Vref 32 -> 127, step: 1
1719 16:37:04.250333
1720 16:37:04.250385 RX Delay -95 -> 252, step: 8
1721 16:37:04.250436
1722 16:37:04.250487 Set Vref, RX VrefLevel [Byte0]: 32
1723 16:37:04.250539 [Byte1]: 32
1724 16:37:04.250590
1725 16:37:04.250649 Set Vref, RX VrefLevel [Byte0]: 33
1726 16:37:04.250700 [Byte1]: 33
1727 16:37:04.250758
1728 16:37:04.250810 Set Vref, RX VrefLevel [Byte0]: 34
1729 16:37:04.250868 [Byte1]: 34
1730 16:37:04.250920
1731 16:37:04.250971 Set Vref, RX VrefLevel [Byte0]: 35
1732 16:37:04.251023 [Byte1]: 35
1733 16:37:04.251074
1734 16:37:04.251132 Set Vref, RX VrefLevel [Byte0]: 36
1735 16:37:04.251184 [Byte1]: 36
1736 16:37:04.251235
1737 16:37:04.251293 Set Vref, RX VrefLevel [Byte0]: 37
1738 16:37:04.251351 [Byte1]: 37
1739 16:37:04.251403
1740 16:37:04.251453 Set Vref, RX VrefLevel [Byte0]: 38
1741 16:37:04.251504 [Byte1]: 38
1742 16:37:04.251556
1743 16:37:04.251607 Set Vref, RX VrefLevel [Byte0]: 39
1744 16:37:04.251665 [Byte1]: 39
1745 16:37:04.251716
1746 16:37:04.251772 Set Vref, RX VrefLevel [Byte0]: 40
1747 16:37:04.251831 [Byte1]: 40
1748 16:37:04.251882
1749 16:37:04.251933 Set Vref, RX VrefLevel [Byte0]: 41
1750 16:37:04.251985 [Byte1]: 41
1751 16:37:04.252036
1752 16:37:04.252087 Set Vref, RX VrefLevel [Byte0]: 42
1753 16:37:04.252146 [Byte1]: 42
1754 16:37:04.252198
1755 16:37:04.252249 Set Vref, RX VrefLevel [Byte0]: 43
1756 16:37:04.252307 [Byte1]: 43
1757 16:37:04.252364
1758 16:37:04.252416 Set Vref, RX VrefLevel [Byte0]: 44
1759 16:37:04.252468 [Byte1]: 44
1760 16:37:04.252519
1761 16:37:04.252570 Set Vref, RX VrefLevel [Byte0]: 45
1762 16:37:04.252821 [Byte1]: 45
1763 16:37:04.252886
1764 16:37:04.252938 Set Vref, RX VrefLevel [Byte0]: 46
1765 16:37:04.252990 [Byte1]: 46
1766 16:37:04.253042
1767 16:37:04.253094 Set Vref, RX VrefLevel [Byte0]: 47
1768 16:37:04.253152 [Byte1]: 47
1769 16:37:04.253204
1770 16:37:04.253256 Set Vref, RX VrefLevel [Byte0]: 48
1771 16:37:04.253319 [Byte1]: 48
1772 16:37:04.253372
1773 16:37:04.253423 Set Vref, RX VrefLevel [Byte0]: 49
1774 16:37:04.253474 [Byte1]: 49
1775 16:37:04.253526
1776 16:37:04.253577 Set Vref, RX VrefLevel [Byte0]: 50
1777 16:37:04.253628 [Byte1]: 50
1778 16:37:04.253679
1779 16:37:04.253736 Set Vref, RX VrefLevel [Byte0]: 51
1780 16:37:04.253789 [Byte1]: 51
1781 16:37:04.253840
1782 16:37:04.253897 Set Vref, RX VrefLevel [Byte0]: 52
1783 16:37:04.253955 [Byte1]: 52
1784 16:37:04.254006
1785 16:37:04.254057 Set Vref, RX VrefLevel [Byte0]: 53
1786 16:37:04.254108 [Byte1]: 53
1787 16:37:04.254158
1788 16:37:04.254227 Set Vref, RX VrefLevel [Byte0]: 54
1789 16:37:04.254280 [Byte1]: 54
1790 16:37:04.254337
1791 16:37:04.254395 Set Vref, RX VrefLevel [Byte0]: 55
1792 16:37:04.254455 [Byte1]: 55
1793 16:37:04.254518
1794 16:37:04.254570 Set Vref, RX VrefLevel [Byte0]: 56
1795 16:37:04.254621 [Byte1]: 56
1796 16:37:04.254673
1797 16:37:04.254723 Set Vref, RX VrefLevel [Byte0]: 57
1798 16:37:04.254782 [Byte1]: 57
1799 16:37:04.254833
1800 16:37:04.254895 Set Vref, RX VrefLevel [Byte0]: 58
1801 16:37:04.254948 [Byte1]: 58
1802 16:37:04.255006
1803 16:37:04.255057 Set Vref, RX VrefLevel [Byte0]: 59
1804 16:37:04.255107 [Byte1]: 59
1805 16:37:04.255158
1806 16:37:04.255215 Set Vref, RX VrefLevel [Byte0]: 60
1807 16:37:04.255268 [Byte1]: 60
1808 16:37:04.255329
1809 16:37:04.255381 Set Vref, RX VrefLevel [Byte0]: 61
1810 16:37:04.255451 [Byte1]: 61
1811 16:37:04.255542
1812 16:37:04.255640 Set Vref, RX VrefLevel [Byte0]: 62
1813 16:37:04.255721 [Byte1]: 62
1814 16:37:04.255782
1815 16:37:04.255842 Set Vref, RX VrefLevel [Byte0]: 63
1816 16:37:04.255894 [Byte1]: 63
1817 16:37:04.255946
1818 16:37:04.255998 Set Vref, RX VrefLevel [Byte0]: 64
1819 16:37:04.256057 [Byte1]: 64
1820 16:37:04.256109
1821 16:37:04.256168 Set Vref, RX VrefLevel [Byte0]: 65
1822 16:37:04.256220 [Byte1]: 65
1823 16:37:04.256271
1824 16:37:04.256327 Set Vref, RX VrefLevel [Byte0]: 66
1825 16:37:04.256380 [Byte1]: 66
1826 16:37:04.256431
1827 16:37:04.256488 Set Vref, RX VrefLevel [Byte0]: 67
1828 16:37:04.256541 [Byte1]: 67
1829 16:37:04.256592
1830 16:37:04.256654 Set Vref, RX VrefLevel [Byte0]: 68
1831 16:37:04.256708 [Byte1]: 68
1832 16:37:04.256758
1833 16:37:04.256816 Set Vref, RX VrefLevel [Byte0]: 69
1834 16:37:04.256872 [Byte1]: 69
1835 16:37:04.256926
1836 16:37:04.256982 Set Vref, RX VrefLevel [Byte0]: 70
1837 16:37:04.257036 [Byte1]: 70
1838 16:37:04.257093
1839 16:37:04.257151 Set Vref, RX VrefLevel [Byte0]: 71
1840 16:37:04.257202 [Byte1]: 71
1841 16:37:04.257253
1842 16:37:04.257304 Set Vref, RX VrefLevel [Byte0]: 72
1843 16:37:04.257356 [Byte1]: 72
1844 16:37:04.257413
1845 16:37:04.257465 Final RX Vref Byte 0 = 56 to rank0
1846 16:37:04.257518 Final RX Vref Byte 1 = 65 to rank0
1847 16:37:04.257575 Final RX Vref Byte 0 = 56 to rank1
1848 16:37:04.257628 Final RX Vref Byte 1 = 65 to rank1==
1849 16:37:04.257679 Dram Type= 6, Freq= 0, CH_1, rank 0
1850 16:37:04.257730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 16:37:04.257782 ==
1852 16:37:04.257833 DQS Delay:
1853 16:37:04.257891 DQS0 = 0, DQS1 = 0
1854 16:37:04.257949 DQM Delay:
1855 16:37:04.258006 DQM0 = 86, DQM1 = 79
1856 16:37:04.258058 DQ Delay:
1857 16:37:04.258117 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1858 16:37:04.258185 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1859 16:37:04.258268 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1860 16:37:04.258322 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1861 16:37:04.258375
1862 16:37:04.258437
1863 16:37:04.258489 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1864 16:37:04.258542 CH1 RK0: MR19=606, MR18=2C19
1865 16:37:04.258601 CH1_RK0: MR19=0x606, MR18=0x2C19, DQSOSC=398, MR23=63, INC=93, DEC=62
1866 16:37:04.258656
1867 16:37:04.258707 ----->DramcWriteLeveling(PI) begin...
1868 16:37:04.258766 ==
1869 16:37:04.258825 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 16:37:04.258878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 16:37:04.258938 ==
1872 16:37:04.258994 Write leveling (Byte 0): 24 => 24
1873 16:37:04.259052 Write leveling (Byte 1): 29 => 29
1874 16:37:04.259104 DramcWriteLeveling(PI) end<-----
1875 16:37:04.259156
1876 16:37:04.259214 ==
1877 16:37:04.259272 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 16:37:04.259326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 16:37:04.259384 ==
1880 16:37:04.259436 [Gating] SW mode calibration
1881 16:37:04.259488 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1882 16:37:04.259540 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1883 16:37:04.259593 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1884 16:37:04.259652 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1885 16:37:04.259704 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:37:04.259755 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:37:04.259813 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 16:37:04.259866 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 16:37:04.259918 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 16:37:04.259969 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 16:37:04.260027 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 16:37:04.260086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 16:37:04.260142 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 16:37:04.260201 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 16:37:04.260259 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 16:37:04.260317 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 16:37:04.260370 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 16:37:04.260421 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 16:37:04.260674 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1900 16:37:04.260742 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1901 16:37:04.260796 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 16:37:04.260856 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 16:37:04.260908 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 16:37:04.260959 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 16:37:04.261010 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 16:37:04.261062 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 16:37:04.261122 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 16:37:04.261174 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 16:37:04.261226 0 9 8 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 0)
1910 16:37:04.261283 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 16:37:04.261345 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 16:37:04.261403 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 16:37:04.261457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 16:37:04.261509 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 16:37:04.261560 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 16:37:04.261620 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
1917 16:37:04.261711 0 10 8 | B1->B0 | 2b2b 2f2f | 0 1 | (1 0) (1 0)
1918 16:37:04.261774 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 16:37:04.261827 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 16:37:04.261885 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 16:37:04.261938 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 16:37:04.261990 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 16:37:04.262042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 16:37:04.262100 0 11 4 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
1925 16:37:04.262192 0 11 8 | B1->B0 | 3e3e 3434 | 0 0 | (0 0) (1 1)
1926 16:37:04.262249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 16:37:04.262301 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 16:37:04.262353 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 16:37:04.262413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 16:37:04.262465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 16:37:04.262517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 16:37:04.262568 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1933 16:37:04.262620 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1934 16:37:04.262684 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 16:37:04.262743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 16:37:04.262801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 16:37:04.262853 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 16:37:04.262905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 16:37:04.262976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 16:37:04.263068 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 16:37:04.263164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 16:37:04.263242 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 16:37:04.263297 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 16:37:04.263349 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 16:37:04.263402 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 16:37:04.263460 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 16:37:04.263513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 16:37:04.263565 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1949 16:37:04.263623 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1950 16:37:04.263684 Total UI for P1: 0, mck2ui 16
1951 16:37:04.263739 best dqsien dly found for B1: ( 0, 14, 4)
1952 16:37:04.263791 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 16:37:04.263843 Total UI for P1: 0, mck2ui 16
1954 16:37:04.263903 best dqsien dly found for B0: ( 0, 14, 6)
1955 16:37:04.263955 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1956 16:37:04.264007 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1957 16:37:04.264066
1958 16:37:04.264118 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1959 16:37:04.264169 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1960 16:37:04.264220 [Gating] SW calibration Done
1961 16:37:04.264277 ==
1962 16:37:04.264330 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 16:37:04.264382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 16:37:04.264433 ==
1965 16:37:04.264485 RX Vref Scan: 0
1966 16:37:04.264535
1967 16:37:04.264586 RX Vref 0 -> 0, step: 1
1968 16:37:04.264636
1969 16:37:04.264687 RX Delay -130 -> 252, step: 16
1970 16:37:04.264739 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1971 16:37:04.264790 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1972 16:37:04.264849 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1973 16:37:04.264911 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1974 16:37:04.264965 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1975 16:37:04.265016 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1976 16:37:04.265067 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1977 16:37:04.265118 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1978 16:37:04.265169 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1979 16:37:04.265220 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1980 16:37:04.265271 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1981 16:37:04.265328 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1982 16:37:04.265386 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1983 16:37:04.526897 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1984 16:37:04.527031 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1985 16:37:04.527095 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1986 16:37:04.527161 ==
1987 16:37:04.527218 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 16:37:04.527273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 16:37:04.527327 ==
1990 16:37:04.527380 DQS Delay:
1991 16:37:04.527432 DQS0 = 0, DQS1 = 0
1992 16:37:04.527492 DQM Delay:
1993 16:37:04.527544 DQM0 = 87, DQM1 = 80
1994 16:37:04.527596 DQ Delay:
1995 16:37:04.527647 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1996 16:37:04.527934 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1997 16:37:04.528046 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1998 16:37:04.528101 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1999 16:37:04.528172
2000 16:37:04.528263
2001 16:37:04.528315 ==
2002 16:37:04.528366 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 16:37:04.528418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 16:37:04.528477 ==
2005 16:37:04.528528
2006 16:37:04.528579
2007 16:37:04.528651 TX Vref Scan disable
2008 16:37:04.528718 == TX Byte 0 ==
2009 16:37:04.528768 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2010 16:37:04.528825 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2011 16:37:04.528890 == TX Byte 1 ==
2012 16:37:04.528941 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2013 16:37:04.528992 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2014 16:37:04.529043 ==
2015 16:37:04.529093 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 16:37:04.529169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 16:37:04.529259 ==
2018 16:37:04.529324 TX Vref=22, minBit 9, minWin=26, winSum=436
2019 16:37:04.529375 TX Vref=24, minBit 1, minWin=27, winSum=444
2020 16:37:04.529426 TX Vref=26, minBit 1, minWin=27, winSum=444
2021 16:37:04.529477 TX Vref=28, minBit 1, minWin=27, winSum=445
2022 16:37:04.529527 TX Vref=30, minBit 7, minWin=27, winSum=447
2023 16:37:04.529586 TX Vref=32, minBit 0, minWin=27, winSum=446
2024 16:37:04.529643 [TxChooseVref] Worse bit 7, Min win 27, Win sum 447, Final Vref 30
2025 16:37:04.529748
2026 16:37:04.529825 Final TX Range 1 Vref 30
2027 16:37:04.529878
2028 16:37:04.529932 ==
2029 16:37:04.529983 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 16:37:04.530033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 16:37:04.530084 ==
2032 16:37:04.530136
2033 16:37:04.530228
2034 16:37:04.530279 TX Vref Scan disable
2035 16:37:04.530363 == TX Byte 0 ==
2036 16:37:04.530427 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2037 16:37:04.530479 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2038 16:37:04.530562 == TX Byte 1 ==
2039 16:37:04.530626 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2040 16:37:04.530698 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2041 16:37:04.530750
2042 16:37:04.530800 [DATLAT]
2043 16:37:04.530851 Freq=800, CH1 RK1
2044 16:37:04.530909
2045 16:37:04.530960 DATLAT Default: 0xa
2046 16:37:04.531011 0, 0xFFFF, sum = 0
2047 16:37:04.531087 1, 0xFFFF, sum = 0
2048 16:37:04.531179 2, 0xFFFF, sum = 0
2049 16:37:04.531231 3, 0xFFFF, sum = 0
2050 16:37:04.531283 4, 0xFFFF, sum = 0
2051 16:37:04.531335 5, 0xFFFF, sum = 0
2052 16:37:04.531401 6, 0xFFFF, sum = 0
2053 16:37:04.531454 7, 0xFFFF, sum = 0
2054 16:37:04.531504 8, 0xFFFF, sum = 0
2055 16:37:04.531570 9, 0x0, sum = 1
2056 16:37:04.531623 10, 0x0, sum = 2
2057 16:37:04.531674 11, 0x0, sum = 3
2058 16:37:04.531725 12, 0x0, sum = 4
2059 16:37:04.531826 best_step = 10
2060 16:37:04.531968
2061 16:37:04.532060 ==
2062 16:37:04.532112 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 16:37:04.532188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 16:37:04.532291 ==
2065 16:37:04.532343 RX Vref Scan: 0
2066 16:37:04.532485
2067 16:37:04.532597 RX Vref 0 -> 0, step: 1
2068 16:37:04.532651
2069 16:37:04.532703 RX Delay -95 -> 252, step: 8
2070 16:37:04.532764 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2071 16:37:04.532872 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2072 16:37:04.532965 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2073 16:37:04.533060 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2074 16:37:04.533153 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2075 16:37:04.533219 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2076 16:37:04.533275 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2077 16:37:04.533335 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2078 16:37:04.533396 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2079 16:37:04.533449 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2080 16:37:04.533501 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2081 16:37:04.533554 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2082 16:37:04.533608 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2083 16:37:04.533673 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2084 16:37:04.533727 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2085 16:37:04.533792 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2086 16:37:04.533864 ==
2087 16:37:04.533915 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 16:37:04.533966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 16:37:04.534017 ==
2090 16:37:04.534080 DQS Delay:
2091 16:37:04.534131 DQS0 = 0, DQS1 = 0
2092 16:37:04.534220 DQM Delay:
2093 16:37:04.534285 DQM0 = 87, DQM1 = 79
2094 16:37:04.534337 DQ Delay:
2095 16:37:04.534407 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2096 16:37:04.534462 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2097 16:37:04.534515 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =68
2098 16:37:04.534570 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2099 16:37:04.534630
2100 16:37:04.534681
2101 16:37:04.534732 [DQSOSCAuto] RK1, (LSB)MR18= 0x140c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2102 16:37:04.534792 CH1 RK1: MR19=606, MR18=140C
2103 16:37:04.534844 CH1_RK1: MR19=0x606, MR18=0x140C, DQSOSC=404, MR23=63, INC=90, DEC=60
2104 16:37:04.534895 [RxdqsGatingPostProcess] freq 800
2105 16:37:04.534946 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 16:37:04.535010 Pre-setting of DQS Precalculation
2107 16:37:04.535062 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 16:37:04.535120 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 16:37:04.535173 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 16:37:04.535224
2111 16:37:04.535275
2112 16:37:04.535325 [Calibration Summary] 1600 Mbps
2113 16:37:04.535394 CH 0, Rank 0
2114 16:37:04.535465 SW Impedance : PASS
2115 16:37:04.535522 DUTY Scan : NO K
2116 16:37:04.535580 ZQ Calibration : PASS
2117 16:37:04.535632 Jitter Meter : NO K
2118 16:37:04.535683 CBT Training : PASS
2119 16:37:04.535734 Write leveling : PASS
2120 16:37:04.535943 RX DQS gating : PASS
2121 16:37:04.536062 RX DQ/DQS(RDDQC) : PASS
2122 16:37:04.536168 TX DQ/DQS : PASS
2123 16:37:04.536254 RX DATLAT : PASS
2124 16:37:04.536348 RX DQ/DQS(Engine): PASS
2125 16:37:04.536413 TX OE : NO K
2126 16:37:04.536473 All Pass.
2127 16:37:04.536532
2128 16:37:04.536599 CH 0, Rank 1
2129 16:37:04.536654 SW Impedance : PASS
2130 16:37:04.536709 DUTY Scan : NO K
2131 16:37:04.536763 ZQ Calibration : PASS
2132 16:37:04.536820 Jitter Meter : NO K
2133 16:37:04.536872 CBT Training : PASS
2134 16:37:04.536923 Write leveling : PASS
2135 16:37:04.536973 RX DQS gating : PASS
2136 16:37:04.537030 RX DQ/DQS(RDDQC) : PASS
2137 16:37:04.537082 TX DQ/DQS : PASS
2138 16:37:04.537134 RX DATLAT : PASS
2139 16:37:04.537184 RX DQ/DQS(Engine): PASS
2140 16:37:04.537246 TX OE : NO K
2141 16:37:04.537302 All Pass.
2142 16:37:04.537354
2143 16:37:04.537405 CH 1, Rank 0
2144 16:37:04.537662 SW Impedance : PASS
2145 16:37:04.537990 DUTY Scan : NO K
2146 16:37:04.538103 ZQ Calibration : PASS
2147 16:37:04.538340 Jitter Meter : NO K
2148 16:37:04.538486 CBT Training : PASS
2149 16:37:04.538564 Write leveling : PASS
2150 16:37:04.538633 RX DQS gating : PASS
2151 16:37:04.538692 RX DQ/DQS(RDDQC) : PASS
2152 16:37:04.538747 TX DQ/DQS : PASS
2153 16:37:04.538828 RX DATLAT : PASS
2154 16:37:04.538882 RX DQ/DQS(Engine): PASS
2155 16:37:04.538935 TX OE : NO K
2156 16:37:04.538986 All Pass.
2157 16:37:04.539065
2158 16:37:04.539124 CH 1, Rank 1
2159 16:37:04.539177 SW Impedance : PASS
2160 16:37:04.539234 DUTY Scan : NO K
2161 16:37:04.539292 ZQ Calibration : PASS
2162 16:37:04.539344 Jitter Meter : NO K
2163 16:37:04.539395 CBT Training : PASS
2164 16:37:04.539446 Write leveling : PASS
2165 16:37:04.539519 RX DQS gating : PASS
2166 16:37:04.539591 RX DQ/DQS(RDDQC) : PASS
2167 16:37:04.539643 TX DQ/DQS : PASS
2168 16:37:04.539701 RX DATLAT : PASS
2169 16:37:04.539779 RX DQ/DQS(Engine): PASS
2170 16:37:04.539895 TX OE : NO K
2171 16:37:04.540033 All Pass.
2172 16:37:04.540125
2173 16:37:04.540194 DramC Write-DBI off
2174 16:37:04.540257 PER_BANK_REFRESH: Hybrid Mode
2175 16:37:04.540329 TX_TRACKING: ON
2176 16:37:04.540399 [GetDramInforAfterCalByMRR] Vendor 6.
2177 16:37:04.540455 [GetDramInforAfterCalByMRR] Revision 606.
2178 16:37:04.540514 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 16:37:04.540568 MR0 0x3b3b
2180 16:37:04.540620 MR8 0x5151
2181 16:37:04.540671 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 16:37:04.540731
2183 16:37:04.540783 MR0 0x3b3b
2184 16:37:04.540835 MR8 0x5151
2185 16:37:04.540908 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 16:37:04.540961
2187 16:37:04.541020 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 16:37:04.541074 [FAST_K] Save calibration result to emmc
2189 16:37:04.541162 [FAST_K] Save calibration result to emmc
2190 16:37:04.541237 dram_init: config_dvfs: 1
2191 16:37:04.541329 dramc_set_vcore_voltage set vcore to 662500
2192 16:37:04.541413 Read voltage for 1200, 2
2193 16:37:04.541482 Vio18 = 0
2194 16:37:04.541549 Vcore = 662500
2195 16:37:04.541601 Vdram = 0
2196 16:37:04.541654 Vddq = 0
2197 16:37:04.541706 Vmddr = 0
2198 16:37:04.541764 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 16:37:04.541818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 16:37:04.541870 MEM_TYPE=3, freq_sel=15
2201 16:37:04.541922 sv_algorithm_assistance_LP4_1600
2202 16:37:04.541974 ============ PULL DRAM RESETB DOWN ============
2203 16:37:04.542034 ========== PULL DRAM RESETB DOWN end =========
2204 16:37:04.542093 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 16:37:04.542147 ===================================
2206 16:37:04.542220 LPDDR4 DRAM CONFIGURATION
2207 16:37:04.542281 ===================================
2208 16:37:04.542333 EX_ROW_EN[0] = 0x0
2209 16:37:04.542385 EX_ROW_EN[1] = 0x0
2210 16:37:04.542437 LP4Y_EN = 0x0
2211 16:37:04.542497 WORK_FSP = 0x0
2212 16:37:04.542556 WL = 0x4
2213 16:37:04.542609 RL = 0x4
2214 16:37:04.542660 BL = 0x2
2215 16:37:04.542717 RPST = 0x0
2216 16:37:04.542770 RD_PRE = 0x0
2217 16:37:04.542821 WR_PRE = 0x1
2218 16:37:04.542873 WR_PST = 0x0
2219 16:37:04.542924 DBI_WR = 0x0
2220 16:37:04.542982 DBI_RD = 0x0
2221 16:37:04.543034 OTF = 0x1
2222 16:37:04.543086 ===================================
2223 16:37:04.543138 ===================================
2224 16:37:04.543190 ANA top config
2225 16:37:04.543253 ===================================
2226 16:37:04.543306 DLL_ASYNC_EN = 0
2227 16:37:04.543358 ALL_SLAVE_EN = 0
2228 16:37:04.543410 NEW_RANK_MODE = 1
2229 16:37:04.543469 DLL_IDLE_MODE = 1
2230 16:37:04.543532 LP45_APHY_COMB_EN = 1
2231 16:37:04.543590 TX_ODT_DIS = 1
2232 16:37:04.543642 NEW_8X_MODE = 1
2233 16:37:04.543701 ===================================
2234 16:37:04.543754 ===================================
2235 16:37:04.543806 data_rate = 2400
2236 16:37:04.543871 CKR = 1
2237 16:37:04.544062 DQ_P2S_RATIO = 8
2238 16:37:04.544181 ===================================
2239 16:37:04.544367 CA_P2S_RATIO = 8
2240 16:37:04.544478 DQ_CA_OPEN = 0
2241 16:37:04.544539 DQ_SEMI_OPEN = 0
2242 16:37:04.544608 CA_SEMI_OPEN = 0
2243 16:37:04.544666 CA_FULL_RATE = 0
2244 16:37:04.544725 DQ_CKDIV4_EN = 0
2245 16:37:04.544779 CA_CKDIV4_EN = 0
2246 16:37:04.544831 CA_PREDIV_EN = 0
2247 16:37:04.544890 PH8_DLY = 17
2248 16:37:04.544949 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 16:37:04.545007 DQ_AAMCK_DIV = 4
2250 16:37:04.545060 CA_AAMCK_DIV = 4
2251 16:37:04.545112 CA_ADMCK_DIV = 4
2252 16:37:04.545163 DQ_TRACK_CA_EN = 0
2253 16:37:04.545222 CA_PICK = 1200
2254 16:37:04.545280 CA_MCKIO = 1200
2255 16:37:04.545334 MCKIO_SEMI = 0
2256 16:37:04.545391 PLL_FREQ = 2366
2257 16:37:04.545450 DQ_UI_PI_RATIO = 32
2258 16:37:04.545503 CA_UI_PI_RATIO = 0
2259 16:37:04.545555 ===================================
2260 16:37:04.545608 ===================================
2261 16:37:04.545672 memory_type:LPDDR4
2262 16:37:04.545724 GP_NUM : 10
2263 16:37:04.545783 SRAM_EN : 1
2264 16:37:04.545836 MD32_EN : 0
2265 16:37:04.545896 ===================================
2266 16:37:04.545956 [ANA_INIT] >>>>>>>>>>>>>>
2267 16:37:04.546015 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 16:37:04.546069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 16:37:04.546128 ===================================
2270 16:37:04.546207 data_rate = 2400,PCW = 0X5b00
2271 16:37:04.546267 ===================================
2272 16:37:04.546320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 16:37:04.546379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 16:37:04.546438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 16:37:04.546499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 16:37:04.546557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 16:37:04.546616 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 16:37:04.546676 [ANA_INIT] flow start
2279 16:37:04.546736 [ANA_INIT] PLL >>>>>>>>
2280 16:37:04.546788 [ANA_INIT] PLL <<<<<<<<
2281 16:37:04.546845 [ANA_INIT] MIDPI >>>>>>>>
2282 16:37:04.546897 [ANA_INIT] MIDPI <<<<<<<<
2283 16:37:04.547157 [ANA_INIT] DLL >>>>>>>>
2284 16:37:04.547228 [ANA_INIT] DLL <<<<<<<<
2285 16:37:04.547289 [ANA_INIT] flow end
2286 16:37:04.547348 ============ LP4 DIFF to SE enter ============
2287 16:37:04.547408 ============ LP4 DIFF to SE exit ============
2288 16:37:04.547468 [ANA_INIT] <<<<<<<<<<<<<
2289 16:37:04.547521 [Flow] Enable top DCM control >>>>>
2290 16:37:04.547573 [Flow] Enable top DCM control <<<<<
2291 16:37:04.547631 Enable DLL master slave shuffle
2292 16:37:04.547690 ==============================================================
2293 16:37:04.547749 Gating Mode config
2294 16:37:04.547808 ==============================================================
2295 16:37:04.547862 Config description:
2296 16:37:04.547925 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 16:37:04.547981 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 16:37:04.548034 SELPH_MODE 0: By rank 1: By Phase
2299 16:37:04.548093 ==============================================================
2300 16:37:04.548147 GAT_TRACK_EN = 1
2301 16:37:04.548206 RX_GATING_MODE = 2
2302 16:37:04.548264 RX_GATING_TRACK_MODE = 2
2303 16:37:04.548317 SELPH_MODE = 1
2304 16:37:04.548380 PICG_EARLY_EN = 1
2305 16:37:04.548433 VALID_LAT_VALUE = 1
2306 16:37:04.548491 ==============================================================
2307 16:37:04.548552 Enter into Gating configuration >>>>
2308 16:37:04.548604 Exit from Gating configuration <<<<
2309 16:37:04.548664 Enter into DVFS_PRE_config >>>>>
2310 16:37:04.548724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 16:37:04.548779 Exit from DVFS_PRE_config <<<<<
2312 16:37:04.548839 Enter into PICG configuration >>>>
2313 16:37:04.548897 Exit from PICG configuration <<<<
2314 16:37:04.548977 [RX_INPUT] configuration >>>>>
2315 16:37:04.549032 [RX_INPUT] configuration <<<<<
2316 16:37:04.549229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 16:37:04.549353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 16:37:04.549423 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 16:37:04.549501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 16:37:04.549565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 16:37:04.549625 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 16:37:04.549686 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 16:37:04.549746 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 16:37:04.549805 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 16:37:04.549864 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 16:37:04.549924 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 16:37:04.549983 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 16:37:04.550035 ===================================
2329 16:37:04.550100 LPDDR4 DRAM CONFIGURATION
2330 16:37:04.550154 ===================================
2331 16:37:04.550230 EX_ROW_EN[0] = 0x0
2332 16:37:04.550283 EX_ROW_EN[1] = 0x0
2333 16:37:04.550335 LP4Y_EN = 0x0
2334 16:37:04.550394 WORK_FSP = 0x0
2335 16:37:04.550453 WL = 0x4
2336 16:37:04.550506 RL = 0x4
2337 16:37:04.550564 BL = 0x2
2338 16:37:04.550623 RPST = 0x0
2339 16:37:04.550680 RD_PRE = 0x0
2340 16:37:04.550739 WR_PRE = 0x1
2341 16:37:04.550790 WR_PST = 0x0
2342 16:37:04.550850 DBI_WR = 0x0
2343 16:37:04.550908 DBI_RD = 0x0
2344 16:37:04.550968 OTF = 0x1
2345 16:37:04.551027 ===================================
2346 16:37:04.551080 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 16:37:04.551139 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 16:37:04.551198 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 16:37:04.551256 ===================================
2350 16:37:04.551320 LPDDR4 DRAM CONFIGURATION
2351 16:37:04.551380 ===================================
2352 16:37:04.551434 EX_ROW_EN[0] = 0x10
2353 16:37:04.551486 EX_ROW_EN[1] = 0x0
2354 16:37:04.551545 LP4Y_EN = 0x0
2355 16:37:04.551604 WORK_FSP = 0x0
2356 16:37:04.551661 WL = 0x4
2357 16:37:04.551722 RL = 0x4
2358 16:37:04.551777 BL = 0x2
2359 16:37:04.551835 RPST = 0x0
2360 16:37:04.551898 RD_PRE = 0x0
2361 16:37:04.551953 WR_PRE = 0x1
2362 16:37:04.552004 WR_PST = 0x0
2363 16:37:04.552064 DBI_WR = 0x0
2364 16:37:04.552126 DBI_RD = 0x0
2365 16:37:04.552185 OTF = 0x1
2366 16:37:04.552243 ===================================
2367 16:37:04.552296 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 16:37:04.552360 ==
2369 16:37:04.552413 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 16:37:04.552465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 16:37:04.552517 ==
2372 16:37:04.552577 [Duty_Offset_Calibration]
2373 16:37:04.552634 B0:1 B1:-1 CA:0
2374 16:37:04.552687
2375 16:37:04.552738 [DutyScan_Calibration_Flow] k_type=0
2376 16:37:04.552796
2377 16:37:04.552855 ==CLK 0==
2378 16:37:04.552907 Final CLK duty delay cell = 0
2379 16:37:04.552964 [0] MAX Duty = 5094%(X100), DQS PI = 16
2380 16:37:04.553017 [0] MIN Duty = 4875%(X100), DQS PI = 8
2381 16:37:04.553069 [0] AVG Duty = 4984%(X100)
2382 16:37:04.553120
2383 16:37:04.553179 CH0 CLK Duty spec in!! Max-Min= 219%
2384 16:37:04.553231 [DutyScan_Calibration_Flow] ====Done====
2385 16:37:04.553283
2386 16:37:04.553334 [DutyScan_Calibration_Flow] k_type=1
2387 16:37:04.553385
2388 16:37:04.553444 ==DQS 0 ==
2389 16:37:04.553496 Final DQS duty delay cell = -4
2390 16:37:04.553548 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2391 16:37:04.553599 [-4] MIN Duty = 4875%(X100), DQS PI = 46
2392 16:37:04.553651 [-4] AVG Duty = 4968%(X100)
2393 16:37:04.553702
2394 16:37:04.553754 ==DQS 1 ==
2395 16:37:04.553820 Final DQS duty delay cell = -4
2396 16:37:04.553881 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2397 16:37:04.553940 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2398 16:37:04.553993 [-4] AVG Duty = 4938%(X100)
2399 16:37:04.554044
2400 16:37:04.554095 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2401 16:37:04.554146
2402 16:37:04.554422 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2403 16:37:04.554484 [DutyScan_Calibration_Flow] ====Done====
2404 16:37:04.554542
2405 16:37:04.554596 [DutyScan_Calibration_Flow] k_type=3
2406 16:37:04.554657
2407 16:37:04.554715 ==DQM 0 ==
2408 16:37:04.554769 Final DQM duty delay cell = 0
2409 16:37:04.554835 [0] MAX Duty = 5031%(X100), DQS PI = 16
2410 16:37:04.554906 [0] MIN Duty = 4875%(X100), DQS PI = 6
2411 16:37:04.554962 [0] AVG Duty = 4953%(X100)
2412 16:37:04.555020
2413 16:37:04.555079 ==DQM 1 ==
2414 16:37:04.555134 Final DQM duty delay cell = 4
2415 16:37:04.555187 [4] MAX Duty = 5187%(X100), DQS PI = 32
2416 16:37:04.555239 [4] MIN Duty = 5000%(X100), DQS PI = 22
2417 16:37:04.555296 [4] AVG Duty = 5093%(X100)
2418 16:37:04.555356
2419 16:37:04.555408 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2420 16:37:04.555465
2421 16:37:04.555526 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2422 16:37:04.555579 [DutyScan_Calibration_Flow] ====Done====
2423 16:37:04.555630
2424 16:37:04.555682 [DutyScan_Calibration_Flow] k_type=2
2425 16:37:04.555741
2426 16:37:04.555792 ==DQ 0 ==
2427 16:37:04.555851 Final DQ duty delay cell = -4
2428 16:37:04.555910 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2429 16:37:04.555977 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2430 16:37:04.556032 [-4] AVG Duty = 4953%(X100)
2431 16:37:04.556084
2432 16:37:04.556136 ==DQ 1 ==
2433 16:37:04.556195 Final DQ duty delay cell = 0
2434 16:37:04.556248 [0] MAX Duty = 5093%(X100), DQS PI = 2
2435 16:37:04.556307 [0] MIN Duty = 4969%(X100), DQS PI = 40
2436 16:37:04.556365 [0] AVG Duty = 5031%(X100)
2437 16:37:04.556416
2438 16:37:04.556468 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2439 16:37:04.556527
2440 16:37:04.556578 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2441 16:37:04.556630 [DutyScan_Calibration_Flow] ====Done====
2442 16:37:04.556681 ==
2443 16:37:04.556740 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 16:37:04.556793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 16:37:04.556852 ==
2446 16:37:04.556910 [Duty_Offset_Calibration]
2447 16:37:04.556969 B0:-1 B1:1 CA:1
2448 16:37:04.557023
2449 16:37:04.557074 [DutyScan_Calibration_Flow] k_type=0
2450 16:37:04.557126
2451 16:37:04.557183 ==CLK 0==
2452 16:37:04.557242 Final CLK duty delay cell = 0
2453 16:37:04.557295 [0] MAX Duty = 5156%(X100), DQS PI = 22
2454 16:37:04.557353 [0] MIN Duty = 4969%(X100), DQS PI = 60
2455 16:37:04.557405 [0] AVG Duty = 5062%(X100)
2456 16:37:04.557457
2457 16:37:04.557508 CH1 CLK Duty spec in!! Max-Min= 187%
2458 16:37:04.557560 [DutyScan_Calibration_Flow] ====Done====
2459 16:37:04.557612
2460 16:37:04.557670 [DutyScan_Calibration_Flow] k_type=1
2461 16:37:04.557722
2462 16:37:04.557773 ==DQS 0 ==
2463 16:37:04.557831 Final DQS duty delay cell = 0
2464 16:37:04.557884 [0] MAX Duty = 5156%(X100), DQS PI = 48
2465 16:37:04.557966 [0] MIN Duty = 4907%(X100), DQS PI = 8
2466 16:37:04.558070 [0] AVG Duty = 5031%(X100)
2467 16:37:04.558159
2468 16:37:04.558232 ==DQS 1 ==
2469 16:37:04.558293 Final DQS duty delay cell = 0
2470 16:37:04.558354 [0] MAX Duty = 5062%(X100), DQS PI = 12
2471 16:37:04.558408 [0] MIN Duty = 4969%(X100), DQS PI = 56
2472 16:37:04.558477 [0] AVG Duty = 5015%(X100)
2473 16:37:04.558542
2474 16:37:04.558600 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2475 16:37:04.558656
2476 16:37:04.558713 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2477 16:37:04.558773 [DutyScan_Calibration_Flow] ====Done====
2478 16:37:04.558831
2479 16:37:04.558883 [DutyScan_Calibration_Flow] k_type=3
2480 16:37:04.558941
2481 16:37:04.558993 ==DQM 0 ==
2482 16:37:04.559044 Final DQM duty delay cell = -4
2483 16:37:04.559104 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2484 16:37:04.559157 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2485 16:37:04.559214 [-4] AVG Duty = 4937%(X100)
2486 16:37:04.559273
2487 16:37:04.559325 ==DQM 1 ==
2488 16:37:04.559377 Final DQM duty delay cell = 0
2489 16:37:04.559428 [0] MAX Duty = 5125%(X100), DQS PI = 2
2490 16:37:04.559487 [0] MIN Duty = 4969%(X100), DQS PI = 28
2491 16:37:04.559541 [0] AVG Duty = 5047%(X100)
2492 16:37:04.559593
2493 16:37:04.559653 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2494 16:37:04.559705
2495 16:37:04.559768 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2496 16:37:04.559820 [DutyScan_Calibration_Flow] ====Done====
2497 16:37:04.559877
2498 16:37:04.559931 [DutyScan_Calibration_Flow] k_type=2
2499 16:37:04.559982
2500 16:37:04.560039 ==DQ 0 ==
2501 16:37:04.560092 Final DQ duty delay cell = 0
2502 16:37:04.560151 [0] MAX Duty = 5187%(X100), DQS PI = 30
2503 16:37:04.560209 [0] MIN Duty = 4876%(X100), DQS PI = 8
2504 16:37:04.560262 [0] AVG Duty = 5031%(X100)
2505 16:37:04.560320
2506 16:37:04.560382 ==DQ 1 ==
2507 16:37:04.560435 Final DQ duty delay cell = 0
2508 16:37:04.560487 [0] MAX Duty = 5124%(X100), DQS PI = 10
2509 16:37:04.560545 [0] MIN Duty = 4969%(X100), DQS PI = 0
2510 16:37:04.560597 [0] AVG Duty = 5046%(X100)
2511 16:37:04.560656
2512 16:37:04.560708 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2513 16:37:04.560766
2514 16:37:04.560824 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2515 16:37:04.560876 [DutyScan_Calibration_Flow] ====Done====
2516 16:37:04.560928 nWR fixed to 30
2517 16:37:04.560987 [ModeRegInit_LP4] CH0 RK0
2518 16:37:04.561040 [ModeRegInit_LP4] CH0 RK1
2519 16:37:04.561098 [ModeRegInit_LP4] CH1 RK0
2520 16:37:04.561154 [ModeRegInit_LP4] CH1 RK1
2521 16:37:04.561213 match AC timing 7
2522 16:37:04.561265 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 16:37:04.561324 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 16:37:04.561376 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 16:37:04.561434 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 16:37:04.561492 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 16:37:04.561546 ==
2528 16:37:04.561597 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 16:37:04.561656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 16:37:04.561720 ==
2531 16:37:04.561774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 16:37:04.561834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 16:37:04.561887 [CA 0] Center 39 (9~70) winsize 62
2534 16:37:04.561939 [CA 1] Center 39 (9~70) winsize 62
2535 16:37:04.561997 [CA 2] Center 35 (5~66) winsize 62
2536 16:37:04.562049 [CA 3] Center 35 (5~66) winsize 62
2537 16:37:04.562100 [CA 4] Center 34 (4~64) winsize 61
2538 16:37:04.562152 [CA 5] Center 33 (4~63) winsize 60
2539 16:37:04.562244
2540 16:37:04.562326 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2541 16:37:04.562414
2542 16:37:04.562498 [CATrainingPosCal] consider 1 rank data
2543 16:37:04.562561 u2DelayCellTimex100 = 270/100 ps
2544 16:37:04.562620 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2545 16:37:04.562674 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2546 16:37:04.562726 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 16:37:04.562784 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 16:37:04.562837 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2549 16:37:04.562895 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2550 16:37:04.562949
2551 16:37:04.563276 CA PerBit enable=1, Macro0, CA PI delay=33
2552 16:37:04.563393
2553 16:37:04.563464 [CBTSetCACLKResult] CA Dly = 33
2554 16:37:04.563529 CS Dly: 8 (0~39)
2555 16:37:04.563596 ==
2556 16:37:04.563651 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 16:37:04.563704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 16:37:04.563757 ==
2559 16:37:04.563810 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 16:37:04.563863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2561 16:37:04.563923 [CA 0] Center 39 (9~70) winsize 62
2562 16:37:04.563976 [CA 1] Center 40 (10~70) winsize 61
2563 16:37:04.564028 [CA 2] Center 35 (5~66) winsize 62
2564 16:37:04.564086 [CA 3] Center 34 (4~65) winsize 62
2565 16:37:04.564138 [CA 4] Center 33 (3~64) winsize 62
2566 16:37:04.564189 [CA 5] Center 33 (3~63) winsize 61
2567 16:37:04.564241
2568 16:37:04.564292 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2569 16:37:04.564344
2570 16:37:04.564396 [CATrainingPosCal] consider 2 rank data
2571 16:37:04.564448 u2DelayCellTimex100 = 270/100 ps
2572 16:37:04.564500 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 16:37:04.564552 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2574 16:37:04.564611 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 16:37:04.564663 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2576 16:37:04.564721 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2577 16:37:04.564772 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2578 16:37:04.564824
2579 16:37:04.564874 CA PerBit enable=1, Macro0, CA PI delay=33
2580 16:37:04.564925
2581 16:37:04.564976 [CBTSetCACLKResult] CA Dly = 33
2582 16:37:04.565028 CS Dly: 8 (0~40)
2583 16:37:04.565092
2584 16:37:04.565144 ----->DramcWriteLeveling(PI) begin...
2585 16:37:04.565203 ==
2586 16:37:04.565256 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 16:37:04.565308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 16:37:04.565360 ==
2589 16:37:04.565411 Write leveling (Byte 0): 30 => 30
2590 16:37:04.565463 Write leveling (Byte 1): 30 => 30
2591 16:37:04.565523 DramcWriteLeveling(PI) end<-----
2592 16:37:04.565580
2593 16:37:04.565640 ==
2594 16:37:04.565706 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 16:37:04.565758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 16:37:04.565810 ==
2597 16:37:04.565861 [Gating] SW mode calibration
2598 16:37:04.565913 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 16:37:04.565966 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 16:37:04.566026 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2601 16:37:04.566079 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2602 16:37:04.566138 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 16:37:04.566202 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 16:37:04.566255 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 16:37:04.566306 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 16:37:04.566358 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2607 16:37:04.566409 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2608 16:37:04.566461 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
2609 16:37:04.566513 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2610 16:37:04.566564 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 16:37:04.566616 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 16:37:04.566667 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 16:37:04.566718 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 16:37:04.566779 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 16:37:04.566837 1 0 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
2616 16:37:04.566890 1 1 0 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
2617 16:37:04.566941 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2618 16:37:04.566992 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 16:37:04.567044 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 16:37:04.567096 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 16:37:04.567147 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 16:37:04.567205 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2623 16:37:04.567257 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2624 16:37:04.567309 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2625 16:37:04.567360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 16:37:04.567417 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 16:37:04.567469 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 16:37:04.567521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 16:37:04.567578 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 16:37:04.567629 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 16:37:04.567680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 16:37:04.567732 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 16:37:04.567790 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 16:37:04.567842 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 16:37:04.567894 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 16:37:04.567952 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 16:37:04.568010 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 16:37:04.568069 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 16:37:04.568124 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2640 16:37:04.568176 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 16:37:04.568232 Total UI for P1: 0, mck2ui 16
2642 16:37:04.568288 best dqsien dly found for B0: ( 1, 3, 28)
2643 16:37:04.568354 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2644 16:37:04.568415 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2645 16:37:04.568469 Total UI for P1: 0, mck2ui 16
2646 16:37:04.568540 best dqsien dly found for B1: ( 1, 4, 2)
2647 16:37:04.568597 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2648 16:37:04.568653 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2649 16:37:04.568709
2650 16:37:04.568770 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2651 16:37:04.568852 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2652 16:37:04.568909 [Gating] SW calibration Done
2653 16:37:04.568967 ==
2654 16:37:04.569021 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 16:37:04.569275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 16:37:04.569338 ==
2657 16:37:04.569391 RX Vref Scan: 0
2658 16:37:04.569443
2659 16:37:04.569495 RX Vref 0 -> 0, step: 1
2660 16:37:04.569547
2661 16:37:04.569599 RX Delay -40 -> 252, step: 8
2662 16:37:04.569658 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2663 16:37:04.569711 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2664 16:37:04.569770 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2665 16:37:04.569822 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2666 16:37:04.569882 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2667 16:37:04.569934 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2668 16:37:04.569997 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2669 16:37:04.570052 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2670 16:37:04.570123 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2671 16:37:04.570215 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2672 16:37:04.570310 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2673 16:37:04.570539 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2674 16:37:04.570643 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2675 16:37:04.570747 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2676 16:37:04.570831 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2677 16:37:04.570896 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2678 16:37:04.570957 ==
2679 16:37:04.571011 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 16:37:04.571063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 16:37:04.571134 ==
2682 16:37:04.571205 DQS Delay:
2683 16:37:04.571259 DQS0 = 0, DQS1 = 0
2684 16:37:04.571310 DQM Delay:
2685 16:37:04.571363 DQM0 = 119, DQM1 = 106
2686 16:37:04.571430 DQ Delay:
2687 16:37:04.571484 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2688 16:37:04.571535 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2689 16:37:04.571587 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2690 16:37:04.571643 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2691 16:37:04.571695
2692 16:37:04.571746
2693 16:37:04.571811 ==
2694 16:37:04.571864 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 16:37:04.571916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 16:37:04.571968 ==
2697 16:37:04.572033
2698 16:37:04.572085
2699 16:37:04.572136 TX Vref Scan disable
2700 16:37:04.572203 == TX Byte 0 ==
2701 16:37:04.572257 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2702 16:37:04.572309 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2703 16:37:04.572369 == TX Byte 1 ==
2704 16:37:04.572422 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2705 16:37:04.572474 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2706 16:37:04.572526 ==
2707 16:37:04.572584 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 16:37:04.572637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 16:37:04.572689 ==
2710 16:37:04.572740 TX Vref=22, minBit 1, minWin=25, winSum=416
2711 16:37:04.572803 TX Vref=24, minBit 13, minWin=25, winSum=420
2712 16:37:04.572855 TX Vref=26, minBit 0, minWin=26, winSum=424
2713 16:37:04.572908 TX Vref=28, minBit 13, minWin=25, winSum=427
2714 16:37:04.572976 TX Vref=30, minBit 4, minWin=26, winSum=428
2715 16:37:04.573031 TX Vref=32, minBit 0, minWin=26, winSum=429
2716 16:37:04.573089 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 32
2717 16:37:04.573143
2718 16:37:04.573194 Final TX Range 1 Vref 32
2719 16:37:04.573246
2720 16:37:04.573297 ==
2721 16:37:04.573360 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 16:37:04.573416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 16:37:04.573470 ==
2724 16:37:04.573526
2725 16:37:04.573591
2726 16:37:04.573644 TX Vref Scan disable
2727 16:37:04.573695 == TX Byte 0 ==
2728 16:37:04.573746 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2729 16:37:04.573804 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2730 16:37:04.573863 == TX Byte 1 ==
2731 16:37:04.573922 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2732 16:37:04.573974 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2733 16:37:04.574025
2734 16:37:04.574081 [DATLAT]
2735 16:37:04.574134 Freq=1200, CH0 RK0
2736 16:37:04.574203
2737 16:37:04.574256 DATLAT Default: 0xd
2738 16:37:04.574307 0, 0xFFFF, sum = 0
2739 16:37:04.574367 1, 0xFFFF, sum = 0
2740 16:37:04.574440 2, 0xFFFF, sum = 0
2741 16:37:04.574498 3, 0xFFFF, sum = 0
2742 16:37:04.574552 4, 0xFFFF, sum = 0
2743 16:37:04.574611 5, 0xFFFF, sum = 0
2744 16:37:04.574665 6, 0xFFFF, sum = 0
2745 16:37:04.574717 7, 0xFFFF, sum = 0
2746 16:37:04.574770 8, 0xFFFF, sum = 0
2747 16:37:04.574829 9, 0xFFFF, sum = 0
2748 16:37:04.574882 10, 0xFFFF, sum = 0
2749 16:37:04.574934 11, 0xFFFF, sum = 0
2750 16:37:04.574987 12, 0x0, sum = 1
2751 16:37:04.575067 13, 0x0, sum = 2
2752 16:37:04.575127 14, 0x0, sum = 3
2753 16:37:04.575180 15, 0x0, sum = 4
2754 16:37:04.575233 best_step = 13
2755 16:37:04.575291
2756 16:37:04.575343 ==
2757 16:37:04.575395 Dram Type= 6, Freq= 0, CH_0, rank 0
2758 16:37:04.575447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2759 16:37:04.575499 ==
2760 16:37:04.575572 RX Vref Scan: 1
2761 16:37:04.575629
2762 16:37:04.575690 Set Vref Range= 32 -> 127
2763 16:37:04.575744
2764 16:37:04.575796 RX Vref 32 -> 127, step: 1
2765 16:37:04.575847
2766 16:37:04.575906 RX Delay -21 -> 252, step: 4
2767 16:37:04.575958
2768 16:37:04.576010 Set Vref, RX VrefLevel [Byte0]: 32
2769 16:37:04.576075 [Byte1]: 32
2770 16:37:04.576134
2771 16:37:04.576185 Set Vref, RX VrefLevel [Byte0]: 33
2772 16:37:04.576236 [Byte1]: 33
2773 16:37:04.576300
2774 16:37:04.576357 Set Vref, RX VrefLevel [Byte0]: 34
2775 16:37:04.576416 [Byte1]: 34
2776 16:37:04.576488
2777 16:37:04.576549 Set Vref, RX VrefLevel [Byte0]: 35
2778 16:37:04.576614 [Byte1]: 35
2779 16:37:04.576670
2780 16:37:04.576723 Set Vref, RX VrefLevel [Byte0]: 36
2781 16:37:04.576779 [Byte1]: 36
2782 16:37:04.576838
2783 16:37:04.576897 Set Vref, RX VrefLevel [Byte0]: 37
2784 16:37:04.576949 [Byte1]: 37
2785 16:37:04.577001
2786 16:37:04.577081 Set Vref, RX VrefLevel [Byte0]: 38
2787 16:37:04.577138 [Byte1]: 38
2788 16:37:04.577190
2789 16:37:04.577259 Set Vref, RX VrefLevel [Byte0]: 39
2790 16:37:04.577320 [Byte1]: 39
2791 16:37:04.577379
2792 16:37:04.577431 Set Vref, RX VrefLevel [Byte0]: 40
2793 16:37:04.577511 [Byte1]: 40
2794 16:37:04.577571
2795 16:37:04.577631 Set Vref, RX VrefLevel [Byte0]: 41
2796 16:37:04.577685 [Byte1]: 41
2797 16:37:04.577736
2798 16:37:04.577787 Set Vref, RX VrefLevel [Byte0]: 42
2799 16:37:04.577857 [Byte1]: 42
2800 16:37:04.577919
2801 16:37:04.577987 Set Vref, RX VrefLevel [Byte0]: 43
2802 16:37:04.578051 [Byte1]: 43
2803 16:37:04.578136
2804 16:37:04.578217 Set Vref, RX VrefLevel [Byte0]: 44
2805 16:37:04.578281 [Byte1]: 44
2806 16:37:04.578334
2807 16:37:04.578386 Set Vref, RX VrefLevel [Byte0]: 45
2808 16:37:04.578449 [Byte1]: 45
2809 16:37:04.578504
2810 16:37:04.578565 Set Vref, RX VrefLevel [Byte0]: 46
2811 16:37:04.578621 [Byte1]: 46
2812 16:37:04.578679
2813 16:37:04.578921 Set Vref, RX VrefLevel [Byte0]: 47
2814 16:37:04.579062 [Byte1]: 47
2815 16:37:04.579174
2816 16:37:04.579276 Set Vref, RX VrefLevel [Byte0]: 48
2817 16:37:04.579367 [Byte1]: 48
2818 16:37:04.579453
2819 16:37:04.579516 Set Vref, RX VrefLevel [Byte0]: 49
2820 16:37:04.579573 [Byte1]: 49
2821 16:37:04.579628
2822 16:37:04.579685 Set Vref, RX VrefLevel [Byte0]: 50
2823 16:37:04.579750 [Byte1]: 50
2824 16:37:04.579807
2825 16:37:04.579863 Set Vref, RX VrefLevel [Byte0]: 51
2826 16:37:04.579917 [Byte1]: 51
2827 16:37:04.579998
2828 16:37:04.580054 Set Vref, RX VrefLevel [Byte0]: 52
2829 16:37:04.580116 [Byte1]: 52
2830 16:37:04.580188
2831 16:37:04.580245 Set Vref, RX VrefLevel [Byte0]: 53
2832 16:37:04.580304 [Byte1]: 53
2833 16:37:04.580401
2834 16:37:04.580486 Set Vref, RX VrefLevel [Byte0]: 54
2835 16:37:04.580569 [Byte1]: 54
2836 16:37:04.580677
2837 16:37:04.580763 Set Vref, RX VrefLevel [Byte0]: 55
2838 16:37:04.580845 [Byte1]: 55
2839 16:37:04.580933
2840 16:37:04.581023 Set Vref, RX VrefLevel [Byte0]: 56
2841 16:37:04.581114 [Byte1]: 56
2842 16:37:04.581198
2843 16:37:04.581280 Set Vref, RX VrefLevel [Byte0]: 57
2844 16:37:04.581362 [Byte1]: 57
2845 16:37:04.581432
2846 16:37:04.581508 Set Vref, RX VrefLevel [Byte0]: 58
2847 16:37:04.581592 [Byte1]: 58
2848 16:37:04.581673
2849 16:37:04.581755 Set Vref, RX VrefLevel [Byte0]: 59
2850 16:37:04.581837 [Byte1]: 59
2851 16:37:04.581920
2852 16:37:04.582007 Set Vref, RX VrefLevel [Byte0]: 60
2853 16:37:04.582091 [Byte1]: 60
2854 16:37:04.582190
2855 16:37:04.582274 Set Vref, RX VrefLevel [Byte0]: 61
2856 16:37:04.582356 [Byte1]: 61
2857 16:37:04.582434
2858 16:37:04.582492 Set Vref, RX VrefLevel [Byte0]: 62
2859 16:37:04.582547 [Byte1]: 62
2860 16:37:04.582599
2861 16:37:04.582651 Set Vref, RX VrefLevel [Byte0]: 63
2862 16:37:04.582703 [Byte1]: 63
2863 16:37:04.582756
2864 16:37:04.582808 Set Vref, RX VrefLevel [Byte0]: 64
2865 16:37:04.582894 [Byte1]: 64
2866 16:37:04.582981
2867 16:37:04.583065 Set Vref, RX VrefLevel [Byte0]: 65
2868 16:37:04.583146 [Byte1]: 65
2869 16:37:04.583227
2870 16:37:04.583308 Set Vref, RX VrefLevel [Byte0]: 66
2871 16:37:04.583364 [Byte1]: 66
2872 16:37:04.583416
2873 16:37:04.583478 Set Vref, RX VrefLevel [Byte0]: 67
2874 16:37:04.583565 [Byte1]: 67
2875 16:37:04.583649
2876 16:37:04.583730 Set Vref, RX VrefLevel [Byte0]: 68
2877 16:37:04.583812 [Byte1]: 68
2878 16:37:04.583895
2879 16:37:04.583988 Set Vref, RX VrefLevel [Byte0]: 69
2880 16:37:04.584076 [Byte1]: 69
2881 16:37:04.584159
2882 16:37:04.584241 Set Vref, RX VrefLevel [Byte0]: 70
2883 16:37:04.584323 [Byte1]: 70
2884 16:37:04.584404
2885 16:37:04.584495 Set Vref, RX VrefLevel [Byte0]: 71
2886 16:37:04.584582 [Byte1]: 71
2887 16:37:04.584664
2888 16:37:04.584745 Set Vref, RX VrefLevel [Byte0]: 72
2889 16:37:04.584827 [Byte1]: 72
2890 16:37:04.584907
2891 16:37:04.584991 Set Vref, RX VrefLevel [Byte0]: 73
2892 16:37:04.585078 [Byte1]: 73
2893 16:37:04.585166
2894 16:37:04.585248 Set Vref, RX VrefLevel [Byte0]: 74
2895 16:37:04.585331 [Byte1]: 74
2896 16:37:04.585411
2897 16:37:04.585493 Set Vref, RX VrefLevel [Byte0]: 75
2898 16:37:04.585576 [Byte1]: 75
2899 16:37:04.585641
2900 16:37:04.585727 Set Vref, RX VrefLevel [Byte0]: 76
2901 16:37:04.585810 [Byte1]: 76
2902 16:37:04.585891
2903 16:37:04.585972 Set Vref, RX VrefLevel [Byte0]: 77
2904 16:37:04.586055 [Byte1]: 77
2905 16:37:04.586145
2906 16:37:04.586240 Final RX Vref Byte 0 = 56 to rank0
2907 16:37:04.586323 Final RX Vref Byte 1 = 50 to rank0
2908 16:37:04.586405 Final RX Vref Byte 0 = 56 to rank1
2909 16:37:04.586488 Final RX Vref Byte 1 = 50 to rank1==
2910 16:37:04.586563 Dram Type= 6, Freq= 0, CH_0, rank 0
2911 16:37:04.586622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 16:37:04.586676 ==
2913 16:37:04.586728 DQS Delay:
2914 16:37:04.586781 DQS0 = 0, DQS1 = 0
2915 16:37:04.586834 DQM Delay:
2916 16:37:04.586886 DQM0 = 118, DQM1 = 107
2917 16:37:04.586938 DQ Delay:
2918 16:37:04.586990 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2919 16:37:04.587054 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =124
2920 16:37:04.587139 DQ8 =98, DQ9 =92, DQ10 =108, DQ11 =100
2921 16:37:04.587221 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2922 16:37:04.587307
2923 16:37:04.587369
2924 16:37:04.587422 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2925 16:37:04.587477 CH0 RK0: MR19=403, MR18=EFA
2926 16:37:04.587539 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2927 16:37:04.587595
2928 16:37:04.587647 ----->DramcWriteLeveling(PI) begin...
2929 16:37:04.587701 ==
2930 16:37:04.587766 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 16:37:04.587821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 16:37:04.587874 ==
2933 16:37:04.587926 Write leveling (Byte 0): 33 => 33
2934 16:37:04.588014 Write leveling (Byte 1): 30 => 30
2935 16:37:04.588098 DramcWriteLeveling(PI) end<-----
2936 16:37:04.588180
2937 16:37:04.588260 ==
2938 16:37:04.588362 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 16:37:04.588454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 16:37:04.588541 ==
2941 16:37:04.588644 [Gating] SW mode calibration
2942 16:37:04.588728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2943 16:37:04.588818 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2944 16:37:04.588909 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2945 16:37:04.589001 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2946 16:37:04.589087 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 16:37:04.589186 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 16:37:04.589260 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 16:37:04.589336 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 16:37:04.589421 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2951 16:37:04.589503 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2952 16:37:04.589585 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2953 16:37:04.589670 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 16:37:04.589761 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 16:37:04.590052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 16:37:04.590140 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 16:37:04.590219 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 16:37:04.590276 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 16:37:04.590330 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2960 16:37:04.590383 1 1 0 | B1->B0 | 3232 4545 | 1 0 | (1 1) (0 0)
2961 16:37:04.590435 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 16:37:04.590487 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 16:37:04.590540 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 16:37:04.590592 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 16:37:04.590653 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 16:37:04.590710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 16:37:04.590764 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2968 16:37:04.590817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2969 16:37:04.590869 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 16:37:04.590921 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 16:37:04.590987 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 16:37:04.591043 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 16:37:04.591096 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 16:37:04.591185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 16:37:04.591268 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 16:37:04.591350 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 16:37:04.591439 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 16:37:04.591529 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 16:37:04.591613 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 16:37:04.591695 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 16:37:04.591777 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 16:37:04.591865 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2983 16:37:04.591955 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2984 16:37:04.592038 Total UI for P1: 0, mck2ui 16
2985 16:37:04.592121 best dqsien dly found for B0: ( 1, 3, 24)
2986 16:37:04.592203 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2987 16:37:04.592292 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 16:37:04.592379 Total UI for P1: 0, mck2ui 16
2989 16:37:04.592467 best dqsien dly found for B1: ( 1, 3, 30)
2990 16:37:04.592550 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2991 16:37:04.592632 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2992 16:37:04.592713
2993 16:37:04.592803 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2994 16:37:04.592890 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2995 16:37:04.592974 [Gating] SW calibration Done
2996 16:37:04.593056 ==
2997 16:37:04.593142 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 16:37:04.593226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 16:37:04.593308 ==
3000 16:37:04.593389 RX Vref Scan: 0
3001 16:37:04.593469
3002 16:37:04.593557 RX Vref 0 -> 0, step: 1
3003 16:37:04.593640
3004 16:37:04.593721 RX Delay -40 -> 252, step: 8
3005 16:37:04.593803 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3006 16:37:04.593885 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3007 16:37:04.593968 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3008 16:37:04.901799 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3009 16:37:04.901932 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3010 16:37:04.901998 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3011 16:37:04.902057 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3012 16:37:04.902114 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3013 16:37:04.902196 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3014 16:37:04.902269 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3015 16:37:04.902394 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3016 16:37:04.902523 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3017 16:37:04.902597 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3018 16:37:04.902652 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3019 16:37:04.902706 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3020 16:37:04.902794 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3021 16:37:04.902848 ==
3022 16:37:04.902902 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 16:37:04.902954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 16:37:04.903007 ==
3025 16:37:04.903060 DQS Delay:
3026 16:37:04.903111 DQS0 = 0, DQS1 = 0
3027 16:37:04.903163 DQM Delay:
3028 16:37:04.903214 DQM0 = 117, DQM1 = 108
3029 16:37:04.903265 DQ Delay:
3030 16:37:04.903317 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3031 16:37:04.903368 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3032 16:37:04.903419 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3033 16:37:04.903478 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3034 16:37:04.903535
3035 16:37:04.903588
3036 16:37:04.903638 ==
3037 16:37:04.903690 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 16:37:04.903741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 16:37:04.903792 ==
3040 16:37:04.903843
3041 16:37:04.903894
3042 16:37:04.903945 TX Vref Scan disable
3043 16:37:04.903996 == TX Byte 0 ==
3044 16:37:04.904053 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3045 16:37:04.904108 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3046 16:37:04.904161 == TX Byte 1 ==
3047 16:37:04.904212 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3048 16:37:04.904263 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3049 16:37:04.904314 ==
3050 16:37:04.904366 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 16:37:04.904417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 16:37:04.904468 ==
3053 16:37:04.904553 TX Vref=22, minBit 2, minWin=26, winSum=420
3054 16:37:04.904635 TX Vref=24, minBit 0, minWin=26, winSum=421
3055 16:37:04.904716 TX Vref=26, minBit 12, minWin=25, winSum=424
3056 16:37:04.904797 TX Vref=28, minBit 12, minWin=25, winSum=428
3057 16:37:04.904878 TX Vref=30, minBit 10, minWin=25, winSum=428
3058 16:37:04.904965 TX Vref=32, minBit 12, minWin=25, winSum=425
3059 16:37:04.905048 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 24
3060 16:37:04.905131
3061 16:37:04.905211 Final TX Range 1 Vref 24
3062 16:37:04.905290
3063 16:37:04.905369 ==
3064 16:37:04.905449 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 16:37:04.905530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 16:37:04.905609 ==
3067 16:37:04.905688
3068 16:37:04.905774
3069 16:37:04.906075 TX Vref Scan disable
3070 16:37:04.906214 == TX Byte 0 ==
3071 16:37:04.906323 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3072 16:37:04.906429 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3073 16:37:04.906531 == TX Byte 1 ==
3074 16:37:04.906621 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3075 16:37:04.906710 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3076 16:37:04.906791
3077 16:37:04.906871 [DATLAT]
3078 16:37:04.906951 Freq=1200, CH0 RK1
3079 16:37:04.907031
3080 16:37:04.907110 DATLAT Default: 0xd
3081 16:37:04.907190 0, 0xFFFF, sum = 0
3082 16:37:04.907272 1, 0xFFFF, sum = 0
3083 16:37:04.907347 2, 0xFFFF, sum = 0
3084 16:37:04.907400 3, 0xFFFF, sum = 0
3085 16:37:04.907458 4, 0xFFFF, sum = 0
3086 16:37:04.907510 5, 0xFFFF, sum = 0
3087 16:37:04.907562 6, 0xFFFF, sum = 0
3088 16:37:04.907613 7, 0xFFFF, sum = 0
3089 16:37:04.907665 8, 0xFFFF, sum = 0
3090 16:37:04.907717 9, 0xFFFF, sum = 0
3091 16:37:04.907769 10, 0xFFFF, sum = 0
3092 16:37:04.907821 11, 0xFFFF, sum = 0
3093 16:37:04.907872 12, 0x0, sum = 1
3094 16:37:04.907925 13, 0x0, sum = 2
3095 16:37:04.907976 14, 0x0, sum = 3
3096 16:37:04.908037 15, 0x0, sum = 4
3097 16:37:04.908090 best_step = 13
3098 16:37:04.908143
3099 16:37:04.908194 ==
3100 16:37:04.908245 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 16:37:04.908297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 16:37:04.908349 ==
3103 16:37:04.908400 RX Vref Scan: 0
3104 16:37:04.908451
3105 16:37:04.908502 RX Vref 0 -> 0, step: 1
3106 16:37:04.908553
3107 16:37:04.908603 RX Delay -21 -> 252, step: 4
3108 16:37:04.908654 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3109 16:37:04.908707 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3110 16:37:04.908758 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3111 16:37:04.908810 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3112 16:37:04.908861 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3113 16:37:04.908913 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3114 16:37:04.908964 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3115 16:37:04.909016 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3116 16:37:04.909067 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3117 16:37:04.909119 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3118 16:37:04.909170 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3119 16:37:04.909222 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3120 16:37:04.909286 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3121 16:37:04.909339 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3122 16:37:04.909391 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3123 16:37:04.909443 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3124 16:37:04.909494 ==
3125 16:37:04.909546 Dram Type= 6, Freq= 0, CH_0, rank 1
3126 16:37:04.909598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 16:37:04.909665 ==
3128 16:37:04.909723 DQS Delay:
3129 16:37:04.909815 DQS0 = 0, DQS1 = 0
3130 16:37:04.909901 DQM Delay:
3131 16:37:04.909986 DQM0 = 116, DQM1 = 107
3132 16:37:04.910071 DQ Delay:
3133 16:37:04.910157 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3134 16:37:04.910225 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3135 16:37:04.910281 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3136 16:37:04.910336 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3137 16:37:04.910392
3138 16:37:04.910446
3139 16:37:04.910511 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3140 16:37:04.910570 CH0 RK1: MR19=403, MR18=DE8
3141 16:37:04.910627 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3142 16:37:04.910683 [RxdqsGatingPostProcess] freq 1200
3143 16:37:04.910739 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3144 16:37:04.910794 best DQS0 dly(2T, 0.5T) = (0, 11)
3145 16:37:04.910849 best DQS1 dly(2T, 0.5T) = (0, 12)
3146 16:37:04.910905 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3147 16:37:04.910960 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3148 16:37:04.911015 best DQS0 dly(2T, 0.5T) = (0, 11)
3149 16:37:04.911070 best DQS1 dly(2T, 0.5T) = (0, 11)
3150 16:37:04.911126 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3151 16:37:04.911181 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3152 16:37:04.911236 Pre-setting of DQS Precalculation
3153 16:37:04.911295 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3154 16:37:04.911356 ==
3155 16:37:04.911413 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 16:37:04.911469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 16:37:04.911524 ==
3158 16:37:04.911579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 16:37:04.911634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3160 16:37:04.911690 [CA 0] Center 37 (7~67) winsize 61
3161 16:37:04.911744 [CA 1] Center 38 (8~68) winsize 61
3162 16:37:04.911800 [CA 2] Center 34 (4~64) winsize 61
3163 16:37:04.911864 [CA 3] Center 33 (3~64) winsize 62
3164 16:37:04.911921 [CA 4] Center 34 (4~64) winsize 61
3165 16:37:04.911976 [CA 5] Center 33 (3~64) winsize 62
3166 16:37:04.912031
3167 16:37:04.912085 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3168 16:37:04.912140
3169 16:37:04.912194 [CATrainingPosCal] consider 1 rank data
3170 16:37:04.912249 u2DelayCellTimex100 = 270/100 ps
3171 16:37:04.912304 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3172 16:37:04.912359 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3173 16:37:04.912414 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 16:37:04.912468 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3175 16:37:04.912523 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 16:37:04.912578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3177 16:37:04.912633
3178 16:37:04.912687 CA PerBit enable=1, Macro0, CA PI delay=33
3179 16:37:04.912742
3180 16:37:04.912796 [CBTSetCACLKResult] CA Dly = 33
3181 16:37:04.912852 CS Dly: 5 (0~36)
3182 16:37:04.912907 ==
3183 16:37:04.912962 Dram Type= 6, Freq= 0, CH_1, rank 1
3184 16:37:04.913017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 16:37:04.913073 ==
3186 16:37:04.913127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3187 16:37:04.913182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3188 16:37:04.913238 [CA 0] Center 37 (7~68) winsize 62
3189 16:37:04.913305 [CA 1] Center 38 (8~68) winsize 61
3190 16:37:04.913363 [CA 2] Center 34 (4~65) winsize 62
3191 16:37:04.913418 [CA 3] Center 33 (3~64) winsize 62
3192 16:37:04.913474 [CA 4] Center 34 (3~65) winsize 63
3193 16:37:04.913528 [CA 5] Center 33 (3~64) winsize 62
3194 16:37:04.913583
3195 16:37:04.913637 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3196 16:37:04.913692
3197 16:37:04.913747 [CATrainingPosCal] consider 2 rank data
3198 16:37:04.913801 u2DelayCellTimex100 = 270/100 ps
3199 16:37:04.913856 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3200 16:37:04.914112 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3201 16:37:04.914184 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3202 16:37:04.914243 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3203 16:37:04.914298 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3204 16:37:04.914354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3205 16:37:04.914408
3206 16:37:04.914463 CA PerBit enable=1, Macro0, CA PI delay=33
3207 16:37:04.914518
3208 16:37:04.914572 [CBTSetCACLKResult] CA Dly = 33
3209 16:37:04.914627 CS Dly: 7 (0~40)
3210 16:37:04.914681
3211 16:37:04.914736 ----->DramcWriteLeveling(PI) begin...
3212 16:37:04.914801 ==
3213 16:37:04.914859 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 16:37:04.914916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 16:37:04.914972 ==
3216 16:37:04.915026 Write leveling (Byte 0): 24 => 24
3217 16:37:04.915082 Write leveling (Byte 1): 28 => 28
3218 16:37:04.915137 DramcWriteLeveling(PI) end<-----
3219 16:37:04.915191
3220 16:37:04.915245 ==
3221 16:37:04.915299 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 16:37:04.915354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 16:37:04.915410 ==
3224 16:37:04.915464 [Gating] SW mode calibration
3225 16:37:04.915519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3226 16:37:04.915575 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3227 16:37:04.915630 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3228 16:37:04.915685 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 16:37:04.915741 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 16:37:04.915796 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 16:37:04.915851 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 16:37:04.915907 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3233 16:37:04.915961 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3234 16:37:04.916017 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3235 16:37:04.916072 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 16:37:04.916128 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 16:37:04.916183 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 16:37:04.916238 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 16:37:04.916293 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 16:37:04.916348 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3241 16:37:04.916402 1 0 24 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0)
3242 16:37:04.916457 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3243 16:37:04.916512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 16:37:04.916567 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 16:37:04.916621 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 16:37:04.916692 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 16:37:04.916748 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 16:37:04.916803 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 16:37:04.916858 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3250 16:37:04.916914 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3251 16:37:04.916969 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 16:37:04.917024 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 16:37:04.917078 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 16:37:04.917133 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 16:37:04.917187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 16:37:04.917242 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 16:37:04.917296 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 16:37:04.917351 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 16:37:04.917406 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 16:37:04.917460 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 16:37:04.917515 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 16:37:04.917569 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 16:37:04.917624 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 16:37:04.917679 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 16:37:04.917733 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3266 16:37:04.917787 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3267 16:37:04.917843 Total UI for P1: 0, mck2ui 16
3268 16:37:04.917898 best dqsien dly found for B0: ( 1, 3, 24)
3269 16:37:04.917953 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 16:37:04.918008 Total UI for P1: 0, mck2ui 16
3271 16:37:04.918063 best dqsien dly found for B1: ( 1, 3, 26)
3272 16:37:04.918118 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3273 16:37:04.918183 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3274 16:37:04.918245
3275 16:37:04.918301 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3276 16:37:04.918363 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3277 16:37:04.918430 [Gating] SW calibration Done
3278 16:37:04.918485 ==
3279 16:37:04.918541 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 16:37:04.918597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 16:37:04.918653 ==
3282 16:37:04.918707 RX Vref Scan: 0
3283 16:37:04.918762
3284 16:37:04.918817 RX Vref 0 -> 0, step: 1
3285 16:37:04.918873
3286 16:37:04.918928 RX Delay -40 -> 252, step: 8
3287 16:37:04.918983 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3288 16:37:04.919047 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3289 16:37:04.919105 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3290 16:37:04.919161 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3291 16:37:04.919215 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3292 16:37:04.919271 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3293 16:37:04.919326 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3294 16:37:04.919381 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3295 16:37:04.919438 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3296 16:37:04.919493 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3297 16:37:04.919548 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3298 16:37:04.919603 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3299 16:37:04.919658 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3300 16:37:04.919713 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3301 16:37:04.919964 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3302 16:37:04.920027 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3303 16:37:04.920084 ==
3304 16:37:04.920140 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 16:37:04.920196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 16:37:04.920256 ==
3307 16:37:04.920316 DQS Delay:
3308 16:37:04.920373 DQS0 = 0, DQS1 = 0
3309 16:37:04.920440 DQM Delay:
3310 16:37:04.920536 DQM0 = 117, DQM1 = 109
3311 16:37:04.920596 DQ Delay:
3312 16:37:04.920652 DQ0 =119, DQ1 =111, DQ2 =111, DQ3 =115
3313 16:37:04.920707 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3314 16:37:04.920763 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3315 16:37:04.920818 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3316 16:37:04.920879
3317 16:37:04.920941
3318 16:37:04.920996 ==
3319 16:37:04.921051 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 16:37:04.921107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 16:37:04.921163 ==
3322 16:37:04.921217
3323 16:37:04.921272
3324 16:37:04.921327 TX Vref Scan disable
3325 16:37:04.921382 == TX Byte 0 ==
3326 16:37:04.921437 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3327 16:37:04.921508 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3328 16:37:04.921566 == TX Byte 1 ==
3329 16:37:04.921621 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3330 16:37:04.921676 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3331 16:37:04.921731 ==
3332 16:37:04.921786 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 16:37:04.921841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 16:37:04.921908 ==
3335 16:37:04.921998 TX Vref=22, minBit 9, minWin=25, winSum=418
3336 16:37:04.922085 TX Vref=24, minBit 9, minWin=25, winSum=423
3337 16:37:04.922180 TX Vref=26, minBit 3, minWin=26, winSum=432
3338 16:37:04.922240 TX Vref=28, minBit 9, minWin=26, winSum=437
3339 16:37:04.922305 TX Vref=30, minBit 10, minWin=25, winSum=431
3340 16:37:04.922364 TX Vref=32, minBit 11, minWin=25, winSum=429
3341 16:37:04.922420 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 28
3342 16:37:04.922487
3343 16:37:04.922546 Final TX Range 1 Vref 28
3344 16:37:04.922602
3345 16:37:04.922657 ==
3346 16:37:04.922712 Dram Type= 6, Freq= 0, CH_1, rank 0
3347 16:37:04.922767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3348 16:37:04.922823 ==
3349 16:37:04.922877
3350 16:37:04.922931
3351 16:37:04.922986 TX Vref Scan disable
3352 16:37:04.923045 == TX Byte 0 ==
3353 16:37:04.923105 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3354 16:37:04.923162 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3355 16:37:04.923217 == TX Byte 1 ==
3356 16:37:04.923271 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3357 16:37:04.923326 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3358 16:37:04.923381
3359 16:37:04.923436 [DATLAT]
3360 16:37:04.923490 Freq=1200, CH1 RK0
3361 16:37:04.923545
3362 16:37:04.923608 DATLAT Default: 0xd
3363 16:37:04.923667 0, 0xFFFF, sum = 0
3364 16:37:04.923723 1, 0xFFFF, sum = 0
3365 16:37:04.923779 2, 0xFFFF, sum = 0
3366 16:37:04.923834 3, 0xFFFF, sum = 0
3367 16:37:04.923890 4, 0xFFFF, sum = 0
3368 16:37:04.923945 5, 0xFFFF, sum = 0
3369 16:37:04.924001 6, 0xFFFF, sum = 0
3370 16:37:04.924056 7, 0xFFFF, sum = 0
3371 16:37:04.924122 8, 0xFFFF, sum = 0
3372 16:37:04.924179 9, 0xFFFF, sum = 0
3373 16:37:04.924235 10, 0xFFFF, sum = 0
3374 16:37:04.924291 11, 0xFFFF, sum = 0
3375 16:37:04.924347 12, 0x0, sum = 1
3376 16:37:04.924403 13, 0x0, sum = 2
3377 16:37:04.924459 14, 0x0, sum = 3
3378 16:37:04.924514 15, 0x0, sum = 4
3379 16:37:04.924579 best_step = 13
3380 16:37:04.924636
3381 16:37:04.924691 ==
3382 16:37:04.924746 Dram Type= 6, Freq= 0, CH_1, rank 0
3383 16:37:04.924800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3384 16:37:04.924855 ==
3385 16:37:04.924909 RX Vref Scan: 1
3386 16:37:04.924964
3387 16:37:04.925021 Set Vref Range= 32 -> 127
3388 16:37:04.925075
3389 16:37:04.925129 RX Vref 32 -> 127, step: 1
3390 16:37:04.925183
3391 16:37:04.925238 RX Delay -21 -> 252, step: 4
3392 16:37:04.925292
3393 16:37:04.925346 Set Vref, RX VrefLevel [Byte0]: 32
3394 16:37:04.925412 [Byte1]: 32
3395 16:37:04.925469
3396 16:37:04.925523 Set Vref, RX VrefLevel [Byte0]: 33
3397 16:37:04.925578 [Byte1]: 33
3398 16:37:04.925632
3399 16:37:04.925686 Set Vref, RX VrefLevel [Byte0]: 34
3400 16:37:04.925741 [Byte1]: 34
3401 16:37:04.925795
3402 16:37:04.925849 Set Vref, RX VrefLevel [Byte0]: 35
3403 16:37:04.925904 [Byte1]: 35
3404 16:37:04.925994
3405 16:37:04.926081 Set Vref, RX VrefLevel [Byte0]: 36
3406 16:37:04.926174 [Byte1]: 36
3407 16:37:04.926234
3408 16:37:04.926288 Set Vref, RX VrefLevel [Byte0]: 37
3409 16:37:04.926343 [Byte1]: 37
3410 16:37:04.926398
3411 16:37:04.926452 Set Vref, RX VrefLevel [Byte0]: 38
3412 16:37:04.926516 [Byte1]: 38
3413 16:37:04.926572
3414 16:37:04.926628 Set Vref, RX VrefLevel [Byte0]: 39
3415 16:37:04.926682 [Byte1]: 39
3416 16:37:04.926736
3417 16:37:04.926790 Set Vref, RX VrefLevel [Byte0]: 40
3418 16:37:04.926844 [Byte1]: 40
3419 16:37:04.926899
3420 16:37:04.926953 Set Vref, RX VrefLevel [Byte0]: 41
3421 16:37:04.927007 [Byte1]: 41
3422 16:37:04.927071
3423 16:37:04.927128 Set Vref, RX VrefLevel [Byte0]: 42
3424 16:37:04.927192 [Byte1]: 42
3425 16:37:04.927248
3426 16:37:04.927303 Set Vref, RX VrefLevel [Byte0]: 43
3427 16:37:04.927357 [Byte1]: 43
3428 16:37:04.927411
3429 16:37:04.927465 Set Vref, RX VrefLevel [Byte0]: 44
3430 16:37:04.927519 [Byte1]: 44
3431 16:37:04.927576
3432 16:37:04.927639 Set Vref, RX VrefLevel [Byte0]: 45
3433 16:37:04.927698 [Byte1]: 45
3434 16:37:04.927754
3435 16:37:04.927809 Set Vref, RX VrefLevel [Byte0]: 46
3436 16:37:04.927863 [Byte1]: 46
3437 16:37:04.927918
3438 16:37:04.927972 Set Vref, RX VrefLevel [Byte0]: 47
3439 16:37:04.928027 [Byte1]: 47
3440 16:37:04.928081
3441 16:37:04.928135 Set Vref, RX VrefLevel [Byte0]: 48
3442 16:37:04.928189 [Byte1]: 48
3443 16:37:04.928244
3444 16:37:04.928301 Set Vref, RX VrefLevel [Byte0]: 49
3445 16:37:04.928362 [Byte1]: 49
3446 16:37:04.928417
3447 16:37:04.928471 Set Vref, RX VrefLevel [Byte0]: 50
3448 16:37:04.928526 [Byte1]: 50
3449 16:37:04.928580
3450 16:37:04.928648 Set Vref, RX VrefLevel [Byte0]: 51
3451 16:37:04.928700 [Byte1]: 51
3452 16:37:04.928752
3453 16:37:04.928803 Set Vref, RX VrefLevel [Byte0]: 52
3454 16:37:04.928855 [Byte1]: 52
3455 16:37:04.928907
3456 16:37:04.928958 Set Vref, RX VrefLevel [Byte0]: 53
3457 16:37:04.929011 [Byte1]: 53
3458 16:37:04.929062
3459 16:37:04.929114 Set Vref, RX VrefLevel [Byte0]: 54
3460 16:37:04.929166 [Byte1]: 54
3461 16:37:04.929217
3462 16:37:04.929269 Set Vref, RX VrefLevel [Byte0]: 55
3463 16:37:04.929329 [Byte1]: 55
3464 16:37:04.929382
3465 16:37:04.929434 Set Vref, RX VrefLevel [Byte0]: 56
3466 16:37:04.929486 [Byte1]: 56
3467 16:37:04.929538
3468 16:37:04.929789 Set Vref, RX VrefLevel [Byte0]: 57
3469 16:37:04.929849 [Byte1]: 57
3470 16:37:04.929944
3471 16:37:04.930029 Set Vref, RX VrefLevel [Byte0]: 58
3472 16:37:04.930111 [Byte1]: 58
3473 16:37:04.930209
3474 16:37:04.930262 Set Vref, RX VrefLevel [Byte0]: 59
3475 16:37:04.930314 [Byte1]: 59
3476 16:37:04.930365
3477 16:37:04.930425 Set Vref, RX VrefLevel [Byte0]: 60
3478 16:37:04.930478 [Byte1]: 60
3479 16:37:04.930529
3480 16:37:04.930617 Set Vref, RX VrefLevel [Byte0]: 61
3481 16:37:04.930670 [Byte1]: 61
3482 16:37:04.930723
3483 16:37:04.930774 Set Vref, RX VrefLevel [Byte0]: 62
3484 16:37:04.930825 [Byte1]: 62
3485 16:37:04.930887
3486 16:37:04.930952 Set Vref, RX VrefLevel [Byte0]: 63
3487 16:37:04.931008 [Byte1]: 63
3488 16:37:04.931066
3489 16:37:04.931119 Set Vref, RX VrefLevel [Byte0]: 64
3490 16:37:04.931171 [Byte1]: 64
3491 16:37:04.931221
3492 16:37:04.931288 Set Vref, RX VrefLevel [Byte0]: 65
3493 16:37:04.931349 [Byte1]: 65
3494 16:37:04.931420
3495 16:37:04.931474 Set Vref, RX VrefLevel [Byte0]: 66
3496 16:37:04.931527 [Byte1]: 66
3497 16:37:04.931577
3498 16:37:04.931650 Set Vref, RX VrefLevel [Byte0]: 67
3499 16:37:04.931732 [Byte1]: 67
3500 16:37:04.931815
3501 16:37:04.931917 Final RX Vref Byte 0 = 50 to rank0
3502 16:37:04.932008 Final RX Vref Byte 1 = 59 to rank0
3503 16:37:04.932089 Final RX Vref Byte 0 = 50 to rank1
3504 16:37:04.932177 Final RX Vref Byte 1 = 59 to rank1==
3505 16:37:04.932258 Dram Type= 6, Freq= 0, CH_1, rank 0
3506 16:37:04.932341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 16:37:04.932421 ==
3508 16:37:04.932502 DQS Delay:
3509 16:37:04.932584 DQS0 = 0, DQS1 = 0
3510 16:37:04.932670 DQM Delay:
3511 16:37:04.932755 DQM0 = 115, DQM1 = 111
3512 16:37:04.932834 DQ Delay:
3513 16:37:04.932914 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3514 16:37:04.932995 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3515 16:37:04.933075 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =100
3516 16:37:04.933155 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3517 16:37:04.933234
3518 16:37:04.933313
3519 16:37:04.933394 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3520 16:37:04.933466 CH1 RK0: MR19=403, MR18=2F5
3521 16:37:04.933526 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3522 16:37:04.933581
3523 16:37:04.933637 ----->DramcWriteLeveling(PI) begin...
3524 16:37:04.933690 ==
3525 16:37:04.933741 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 16:37:04.933793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 16:37:04.933845 ==
3528 16:37:04.933895 Write leveling (Byte 0): 25 => 25
3529 16:37:04.933946 Write leveling (Byte 1): 28 => 28
3530 16:37:04.934023 DramcWriteLeveling(PI) end<-----
3531 16:37:04.934128
3532 16:37:04.934221 ==
3533 16:37:04.934274 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 16:37:04.934326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 16:37:04.934377 ==
3536 16:37:04.934428 [Gating] SW mode calibration
3537 16:37:04.934479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3538 16:37:04.934532 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3539 16:37:04.934609 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3540 16:37:04.934672 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 16:37:04.934729 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 16:37:04.934781 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 16:37:04.934833 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 16:37:04.934884 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3545 16:37:04.934935 0 15 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
3546 16:37:04.934986 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
3547 16:37:04.935043 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 16:37:04.935107 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 16:37:04.935186 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 16:37:04.935287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 16:37:04.935382 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 16:37:04.935462 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 16:37:04.935555 1 0 24 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
3554 16:37:04.935644 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3555 16:37:04.935725 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 16:37:04.935806 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 16:37:04.935886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 16:37:04.935967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 16:37:04.936053 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 16:37:04.936142 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 16:37:04.936230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3562 16:37:04.936312 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3563 16:37:04.936392 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 16:37:04.936482 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 16:37:04.936572 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 16:37:04.936659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 16:37:04.936740 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 16:37:04.936820 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 16:37:04.936901 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 16:37:04.936987 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 16:37:04.937075 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 16:37:04.937157 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 16:37:04.937237 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 16:37:04.937317 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 16:37:04.937398 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 16:37:04.937470 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 16:37:04.937534 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3578 16:37:04.937590 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3579 16:37:04.937643 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3580 16:37:04.937893 Total UI for P1: 0, mck2ui 16
3581 16:37:04.937989 best dqsien dly found for B0: ( 1, 3, 26)
3582 16:37:04.938073 Total UI for P1: 0, mck2ui 16
3583 16:37:04.938154 best dqsien dly found for B1: ( 1, 3, 26)
3584 16:37:04.938248 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3585 16:37:04.938300 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3586 16:37:04.938352
3587 16:37:04.938403 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3588 16:37:04.938462 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3589 16:37:04.938515 [Gating] SW calibration Done
3590 16:37:04.938567 ==
3591 16:37:04.938619 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 16:37:04.938711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 16:37:04.938767 ==
3594 16:37:04.938820 RX Vref Scan: 0
3595 16:37:04.938870
3596 16:37:04.938938 RX Vref 0 -> 0, step: 1
3597 16:37:04.939028
3598 16:37:04.939112 RX Delay -40 -> 252, step: 8
3599 16:37:04.939194 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3600 16:37:04.939281 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3601 16:37:04.939368 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3602 16:37:04.939458 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3603 16:37:04.939546 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3604 16:37:04.939628 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3605 16:37:04.939710 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3606 16:37:04.939798 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3607 16:37:04.939882 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3608 16:37:04.939940 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3609 16:37:04.939993 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3610 16:37:04.940045 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3611 16:37:04.940109 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3612 16:37:04.940178 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3613 16:37:04.940269 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3614 16:37:04.940351 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3615 16:37:04.940431 ==
3616 16:37:04.940514 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 16:37:04.940602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 16:37:04.940697 ==
3619 16:37:04.940784 DQS Delay:
3620 16:37:04.940873 DQS0 = 0, DQS1 = 0
3621 16:37:04.940953 DQM Delay:
3622 16:37:04.941049 DQM0 = 116, DQM1 = 110
3623 16:37:04.941137 DQ Delay:
3624 16:37:04.941222 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3625 16:37:04.941302 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3626 16:37:04.941382 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3627 16:37:04.941462 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3628 16:37:04.941542
3629 16:37:04.941630
3630 16:37:04.941713 ==
3631 16:37:04.941794 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 16:37:04.941874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 16:37:04.941954 ==
3634 16:37:04.942050
3635 16:37:04.942133
3636 16:37:04.942229 TX Vref Scan disable
3637 16:37:04.942282 == TX Byte 0 ==
3638 16:37:04.942334 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3639 16:37:04.942386 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3640 16:37:04.942438 == TX Byte 1 ==
3641 16:37:04.942492 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3642 16:37:04.942554 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3643 16:37:04.942615 ==
3644 16:37:04.942670 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 16:37:04.942724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 16:37:04.942777 ==
3647 16:37:04.942829 TX Vref=22, minBit 8, minWin=25, winSum=421
3648 16:37:04.942880 TX Vref=24, minBit 11, minWin=25, winSum=426
3649 16:37:04.942936 TX Vref=26, minBit 3, minWin=26, winSum=427
3650 16:37:04.943002 TX Vref=28, minBit 8, minWin=26, winSum=432
3651 16:37:04.943091 TX Vref=30, minBit 8, minWin=26, winSum=433
3652 16:37:04.943176 TX Vref=32, minBit 8, minWin=26, winSum=432
3653 16:37:04.943257 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3654 16:37:04.943338
3655 16:37:04.943417 Final TX Range 1 Vref 30
3656 16:37:04.943508
3657 16:37:04.943595 ==
3658 16:37:04.943680 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 16:37:04.943760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 16:37:04.943840 ==
3661 16:37:04.943919
3662 16:37:04.944015
3663 16:37:04.944101 TX Vref Scan disable
3664 16:37:04.944185 == TX Byte 0 ==
3665 16:37:04.944265 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3666 16:37:04.944346 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3667 16:37:04.944427 == TX Byte 1 ==
3668 16:37:04.944514 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3669 16:37:04.944602 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3670 16:37:04.944684
3671 16:37:04.944763 [DATLAT]
3672 16:37:04.944842 Freq=1200, CH1 RK1
3673 16:37:04.944926
3674 16:37:04.945011 DATLAT Default: 0xd
3675 16:37:04.945094 0, 0xFFFF, sum = 0
3676 16:37:04.945177 1, 0xFFFF, sum = 0
3677 16:37:04.945258 2, 0xFFFF, sum = 0
3678 16:37:04.945340 3, 0xFFFF, sum = 0
3679 16:37:04.945420 4, 0xFFFF, sum = 0
3680 16:37:04.945483 5, 0xFFFF, sum = 0
3681 16:37:04.945539 6, 0xFFFF, sum = 0
3682 16:37:04.945593 7, 0xFFFF, sum = 0
3683 16:37:04.945645 8, 0xFFFF, sum = 0
3684 16:37:04.945697 9, 0xFFFF, sum = 0
3685 16:37:04.945749 10, 0xFFFF, sum = 0
3686 16:37:04.945802 11, 0xFFFF, sum = 0
3687 16:37:04.945853 12, 0x0, sum = 1
3688 16:37:04.945941 13, 0x0, sum = 2
3689 16:37:04.946028 14, 0x0, sum = 3
3690 16:37:04.946112 15, 0x0, sum = 4
3691 16:37:04.946194 best_step = 13
3692 16:37:04.946247
3693 16:37:04.946298 ==
3694 16:37:04.946349 Dram Type= 6, Freq= 0, CH_1, rank 1
3695 16:37:04.946400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3696 16:37:04.946464 ==
3697 16:37:04.946531 RX Vref Scan: 0
3698 16:37:04.946587
3699 16:37:04.946640 RX Vref 0 -> 0, step: 1
3700 16:37:04.946691
3701 16:37:04.946742 RX Delay -21 -> 252, step: 4
3702 16:37:04.946793 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3703 16:37:04.946845 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3704 16:37:04.946896 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3705 16:37:04.946958 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3706 16:37:04.947012 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3707 16:37:04.947067 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3708 16:37:04.947120 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3709 16:37:04.947171 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3710 16:37:04.947222 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3711 16:37:04.947274 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3712 16:37:04.947324 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3713 16:37:04.947375 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3714 16:37:04.947430 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3715 16:37:04.947486 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3716 16:37:04.947538 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3717 16:37:04.947606 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3718 16:37:04.947688 ==
3719 16:37:04.947967 Dram Type= 6, Freq= 0, CH_1, rank 1
3720 16:37:04.948061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3721 16:37:04.948144 ==
3722 16:37:04.948224 DQS Delay:
3723 16:37:04.948304 DQS0 = 0, DQS1 = 0
3724 16:37:04.948388 DQM Delay:
3725 16:37:04.948472 DQM0 = 116, DQM1 = 111
3726 16:37:04.948557 DQ Delay:
3727 16:37:04.948637 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3728 16:37:04.948718 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3729 16:37:04.948797 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =100
3730 16:37:04.948884 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3731 16:37:04.948968
3732 16:37:04.949051
3733 16:37:04.949132 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3734 16:37:04.949213 CH1 RK1: MR19=303, MR18=F3ED
3735 16:37:04.949294 CH1_RK1: MR19=0x303, MR18=0xF3ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3736 16:37:04.949377 [RxdqsGatingPostProcess] freq 1200
3737 16:37:04.949448 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3738 16:37:04.949507 best DQS0 dly(2T, 0.5T) = (0, 11)
3739 16:37:04.949560 best DQS1 dly(2T, 0.5T) = (0, 11)
3740 16:37:04.949612 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3741 16:37:04.949664 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3742 16:37:04.949714 best DQS0 dly(2T, 0.5T) = (0, 11)
3743 16:37:04.949778 best DQS1 dly(2T, 0.5T) = (0, 11)
3744 16:37:04.949862 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3745 16:37:04.949949 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3746 16:37:04.950033 Pre-setting of DQS Precalculation
3747 16:37:04.950114 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3748 16:37:04.950231 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3749 16:37:04.950303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3750 16:37:04.950383
3751 16:37:04.950471
3752 16:37:04.950552 [Calibration Summary] 2400 Mbps
3753 16:37:04.950632 CH 0, Rank 0
3754 16:37:04.950713 SW Impedance : PASS
3755 16:37:04.950770 DUTY Scan : NO K
3756 16:37:04.950837 ZQ Calibration : PASS
3757 16:37:04.950921 Jitter Meter : NO K
3758 16:37:04.951005 CBT Training : PASS
3759 16:37:04.951085 Write leveling : PASS
3760 16:37:04.951164 RX DQS gating : PASS
3761 16:37:04.951243 RX DQ/DQS(RDDQC) : PASS
3762 16:37:04.951305 TX DQ/DQS : PASS
3763 16:37:04.951398 RX DATLAT : PASS
3764 16:37:04.951478 RX DQ/DQS(Engine): PASS
3765 16:37:04.951558 TX OE : NO K
3766 16:37:04.951638 All Pass.
3767 16:37:04.951723
3768 16:37:04.951808 CH 0, Rank 1
3769 16:37:04.951895 SW Impedance : PASS
3770 16:37:04.951977 DUTY Scan : NO K
3771 16:37:04.952057 ZQ Calibration : PASS
3772 16:37:04.952136 Jitter Meter : NO K
3773 16:37:04.952228 CBT Training : PASS
3774 16:37:04.952325 Write leveling : PASS
3775 16:37:04.952408 RX DQS gating : PASS
3776 16:37:04.952487 RX DQ/DQS(RDDQC) : PASS
3777 16:37:04.952567 TX DQ/DQS : PASS
3778 16:37:04.952647 RX DATLAT : PASS
3779 16:37:04.952733 RX DQ/DQS(Engine): PASS
3780 16:37:04.952824 TX OE : NO K
3781 16:37:04.952910 All Pass.
3782 16:37:04.952994
3783 16:37:04.953073 CH 1, Rank 0
3784 16:37:04.953156 SW Impedance : PASS
3785 16:37:04.953234 DUTY Scan : NO K
3786 16:37:04.953293 ZQ Calibration : PASS
3787 16:37:04.953346 Jitter Meter : NO K
3788 16:37:04.953396 CBT Training : PASS
3789 16:37:04.953447 Write leveling : PASS
3790 16:37:04.953498 RX DQS gating : PASS
3791 16:37:04.953561 RX DQ/DQS(RDDQC) : PASS
3792 16:37:04.953650 TX DQ/DQS : PASS
3793 16:37:04.953735 RX DATLAT : PASS
3794 16:37:04.953828 RX DQ/DQS(Engine): PASS
3795 16:37:04.953915 TX OE : NO K
3796 16:37:04.953996 All Pass.
3797 16:37:04.954075
3798 16:37:04.954185 CH 1, Rank 1
3799 16:37:04.954287 SW Impedance : PASS
3800 16:37:04.954374 DUTY Scan : NO K
3801 16:37:04.954459 ZQ Calibration : PASS
3802 16:37:04.954534 Jitter Meter : NO K
3803 16:37:04.954619 CBT Training : PASS
3804 16:37:04.954705 Write leveling : PASS
3805 16:37:04.954792 RX DQS gating : PASS
3806 16:37:04.954881 RX DQ/DQS(RDDQC) : PASS
3807 16:37:04.954965 TX DQ/DQS : PASS
3808 16:37:04.955056 RX DATLAT : PASS
3809 16:37:04.955143 RX DQ/DQS(Engine): PASS
3810 16:37:04.955228 TX OE : NO K
3811 16:37:04.955315 All Pass.
3812 16:37:04.955380
3813 16:37:04.955435 DramC Write-DBI off
3814 16:37:04.955489 PER_BANK_REFRESH: Hybrid Mode
3815 16:37:04.955540 TX_TRACKING: ON
3816 16:37:04.955592 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3817 16:37:04.955682 [FAST_K] Save calibration result to emmc
3818 16:37:04.955771 dramc_set_vcore_voltage set vcore to 650000
3819 16:37:04.955855 Read voltage for 600, 5
3820 16:37:04.955935 Vio18 = 0
3821 16:37:04.956014 Vcore = 650000
3822 16:37:04.956101 Vdram = 0
3823 16:37:04.956191 Vddq = 0
3824 16:37:04.956284 Vmddr = 0
3825 16:37:04.956364 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3826 16:37:04.956448 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3827 16:37:04.956538 MEM_TYPE=3, freq_sel=19
3828 16:37:04.956623 sv_algorithm_assistance_LP4_1600
3829 16:37:04.956711 ============ PULL DRAM RESETB DOWN ============
3830 16:37:04.956794 ========== PULL DRAM RESETB DOWN end =========
3831 16:37:04.956874 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3832 16:37:04.956955 ===================================
3833 16:37:04.957035 LPDDR4 DRAM CONFIGURATION
3834 16:37:04.957114 ===================================
3835 16:37:04.957187 EX_ROW_EN[0] = 0x0
3836 16:37:04.957272 EX_ROW_EN[1] = 0x0
3837 16:37:04.957356 LP4Y_EN = 0x0
3838 16:37:04.957435 WORK_FSP = 0x0
3839 16:37:04.957514 WL = 0x2
3840 16:37:04.957593 RL = 0x2
3841 16:37:04.957672 BL = 0x2
3842 16:37:04.957757 RPST = 0x0
3843 16:37:04.957840 RD_PRE = 0x0
3844 16:37:04.957925 WR_PRE = 0x1
3845 16:37:04.958004 WR_PST = 0x0
3846 16:37:04.958091 DBI_WR = 0x0
3847 16:37:04.958222 DBI_RD = 0x0
3848 16:37:04.958278 OTF = 0x1
3849 16:37:04.958331 ===================================
3850 16:37:04.958393 ===================================
3851 16:37:04.958447 ANA top config
3852 16:37:04.958498 ===================================
3853 16:37:04.958550 DLL_ASYNC_EN = 0
3854 16:37:04.958611 ALL_SLAVE_EN = 1
3855 16:37:04.958663 NEW_RANK_MODE = 1
3856 16:37:04.958715 DLL_IDLE_MODE = 1
3857 16:37:04.958775 LP45_APHY_COMB_EN = 1
3858 16:37:04.958832 TX_ODT_DIS = 1
3859 16:37:04.958886 NEW_8X_MODE = 1
3860 16:37:04.958939 ===================================
3861 16:37:04.958991 ===================================
3862 16:37:04.959043 data_rate = 1200
3863 16:37:04.959094 CKR = 1
3864 16:37:04.959145 DQ_P2S_RATIO = 8
3865 16:37:04.959407 ===================================
3866 16:37:04.959494 CA_P2S_RATIO = 8
3867 16:37:04.959575 DQ_CA_OPEN = 0
3868 16:37:04.959663 DQ_SEMI_OPEN = 0
3869 16:37:04.959746 CA_SEMI_OPEN = 0
3870 16:37:04.959826 CA_FULL_RATE = 0
3871 16:37:04.959913 DQ_CKDIV4_EN = 1
3872 16:37:04.959994 CA_CKDIV4_EN = 1
3873 16:37:04.960074 CA_PREDIV_EN = 0
3874 16:37:04.960154 PH8_DLY = 0
3875 16:37:04.960234 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3876 16:37:04.960319 DQ_AAMCK_DIV = 4
3877 16:37:04.960406 CA_AAMCK_DIV = 4
3878 16:37:04.960488 CA_ADMCK_DIV = 4
3879 16:37:04.960568 DQ_TRACK_CA_EN = 0
3880 16:37:04.960647 CA_PICK = 600
3881 16:37:04.960732 CA_MCKIO = 600
3882 16:37:04.960814 MCKIO_SEMI = 0
3883 16:37:04.960896 PLL_FREQ = 2288
3884 16:37:04.960981 DQ_UI_PI_RATIO = 32
3885 16:37:04.961061 CA_UI_PI_RATIO = 0
3886 16:37:04.961141 ===================================
3887 16:37:04.961218 ===================================
3888 16:37:04.961273 memory_type:LPDDR4
3889 16:37:04.961336 GP_NUM : 10
3890 16:37:04.961390 SRAM_EN : 1
3891 16:37:04.961442 MD32_EN : 0
3892 16:37:04.961493 ===================================
3893 16:37:04.961545 [ANA_INIT] >>>>>>>>>>>>>>
3894 16:37:04.961596 <<<<<< [CONFIGURE PHASE]: ANA_TX
3895 16:37:04.961648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3896 16:37:04.961699 ===================================
3897 16:37:04.961751 data_rate = 1200,PCW = 0X5800
3898 16:37:04.961825 ===================================
3899 16:37:04.961907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3900 16:37:04.961989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 16:37:04.962070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3902 16:37:04.962151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3903 16:37:04.962275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3904 16:37:04.962358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3905 16:37:04.962438 [ANA_INIT] flow start
3906 16:37:04.962517 [ANA_INIT] PLL >>>>>>>>
3907 16:37:04.962597 [ANA_INIT] PLL <<<<<<<<
3908 16:37:04.962676 [ANA_INIT] MIDPI >>>>>>>>
3909 16:37:04.962759 [ANA_INIT] MIDPI <<<<<<<<
3910 16:37:04.962818 [ANA_INIT] DLL >>>>>>>>
3911 16:37:04.962879 [ANA_INIT] flow end
3912 16:37:04.962964 ============ LP4 DIFF to SE enter ============
3913 16:37:04.963045 ============ LP4 DIFF to SE exit ============
3914 16:37:04.963128 [ANA_INIT] <<<<<<<<<<<<<
3915 16:37:04.963209 [Flow] Enable top DCM control >>>>>
3916 16:37:04.963288 [Flow] Enable top DCM control <<<<<
3917 16:37:04.963376 Enable DLL master slave shuffle
3918 16:37:04.963462 ==============================================================
3919 16:37:04.963523 Gating Mode config
3920 16:37:04.963575 ==============================================================
3921 16:37:04.963626 Config description:
3922 16:37:04.963678 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3923 16:37:04.963731 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3924 16:37:04.963783 SELPH_MODE 0: By rank 1: By Phase
3925 16:37:04.963834 ==============================================================
3926 16:37:04.963887 GAT_TRACK_EN = 1
3927 16:37:04.963941 RX_GATING_MODE = 2
3928 16:37:04.964054 RX_GATING_TRACK_MODE = 2
3929 16:37:04.964110 SELPH_MODE = 1
3930 16:37:04.964163 PICG_EARLY_EN = 1
3931 16:37:04.964214 VALID_LAT_VALUE = 1
3932 16:37:04.964265 ==============================================================
3933 16:37:04.964316 Enter into Gating configuration >>>>
3934 16:37:04.964368 Exit from Gating configuration <<<<
3935 16:37:04.964419 Enter into DVFS_PRE_config >>>>>
3936 16:37:04.964470 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3937 16:37:04.964522 Exit from DVFS_PRE_config <<<<<
3938 16:37:04.964573 Enter into PICG configuration >>>>
3939 16:37:04.964666 Exit from PICG configuration <<<<
3940 16:37:04.964752 [RX_INPUT] configuration >>>>>
3941 16:37:04.964832 [RX_INPUT] configuration <<<<<
3942 16:37:04.964913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3943 16:37:04.964994 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3944 16:37:04.965075 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3945 16:37:04.965157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3946 16:37:04.965238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3947 16:37:04.965321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3948 16:37:04.965381 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3949 16:37:04.965449 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3950 16:37:04.965504 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3951 16:37:04.967462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3952 16:37:04.973879 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3953 16:37:04.977358 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 16:37:04.980808 ===================================
3955 16:37:04.984227 LPDDR4 DRAM CONFIGURATION
3956 16:37:04.987599 ===================================
3957 16:37:04.987678 EX_ROW_EN[0] = 0x0
3958 16:37:04.990433 EX_ROW_EN[1] = 0x0
3959 16:37:04.990512 LP4Y_EN = 0x0
3960 16:37:04.993857 WORK_FSP = 0x0
3961 16:37:04.993947 WL = 0x2
3962 16:37:04.996640 RL = 0x2
3963 16:37:05.000185 BL = 0x2
3964 16:37:05.000265 RPST = 0x0
3965 16:37:05.003630 RD_PRE = 0x0
3966 16:37:05.003710 WR_PRE = 0x1
3967 16:37:05.007108 WR_PST = 0x0
3968 16:37:05.007188 DBI_WR = 0x0
3969 16:37:05.010425 DBI_RD = 0x0
3970 16:37:05.010533 OTF = 0x1
3971 16:37:05.013530 ===================================
3972 16:37:05.016624 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3973 16:37:05.023406 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3974 16:37:05.026693 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3975 16:37:05.030063 ===================================
3976 16:37:05.032921 LPDDR4 DRAM CONFIGURATION
3977 16:37:05.036434 ===================================
3978 16:37:05.036531 EX_ROW_EN[0] = 0x10
3979 16:37:05.040093 EX_ROW_EN[1] = 0x0
3980 16:37:05.040197 LP4Y_EN = 0x0
3981 16:37:05.042881 WORK_FSP = 0x0
3982 16:37:05.042969 WL = 0x2
3983 16:37:05.046218 RL = 0x2
3984 16:37:05.049508 BL = 0x2
3985 16:37:05.049613 RPST = 0x0
3986 16:37:05.052786 RD_PRE = 0x0
3987 16:37:05.052865 WR_PRE = 0x1
3988 16:37:05.056216 WR_PST = 0x0
3989 16:37:05.056287 DBI_WR = 0x0
3990 16:37:05.059598 DBI_RD = 0x0
3991 16:37:05.059667 OTF = 0x1
3992 16:37:05.063108 ===================================
3993 16:37:05.069285 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3994 16:37:05.073477 nWR fixed to 30
3995 16:37:05.077075 [ModeRegInit_LP4] CH0 RK0
3996 16:37:05.077154 [ModeRegInit_LP4] CH0 RK1
3997 16:37:05.080548 [ModeRegInit_LP4] CH1 RK0
3998 16:37:05.083283 [ModeRegInit_LP4] CH1 RK1
3999 16:37:05.083363 match AC timing 17
4000 16:37:05.089973 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4001 16:37:05.093540 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4002 16:37:05.096406 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4003 16:37:05.179190 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4004 16:37:05.179321 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4005 16:37:05.179387 ==
4006 16:37:05.179453 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 16:37:05.179542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 16:37:05.179628 ==
4009 16:37:05.179712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 16:37:05.179806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4011 16:37:05.179889 [CA 0] Center 36 (6~66) winsize 61
4012 16:37:05.179979 [CA 1] Center 36 (6~66) winsize 61
4013 16:37:05.180101 [CA 2] Center 34 (4~65) winsize 62
4014 16:37:05.180184 [CA 3] Center 34 (4~65) winsize 62
4015 16:37:05.180274 [CA 4] Center 33 (3~64) winsize 62
4016 16:37:05.180357 [CA 5] Center 33 (3~64) winsize 62
4017 16:37:05.180438
4018 16:37:05.180518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4019 16:37:05.180599
4020 16:37:05.180679 [CATrainingPosCal] consider 1 rank data
4021 16:37:05.180764 u2DelayCellTimex100 = 270/100 ps
4022 16:37:05.180853 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 16:37:05.180935 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4024 16:37:05.181015 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 16:37:05.181096 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4026 16:37:05.181176 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 16:37:05.181256 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 16:37:05.181332
4029 16:37:05.182235 CA PerBit enable=1, Macro0, CA PI delay=33
4030 16:37:05.182331
4031 16:37:05.185006 [CBTSetCACLKResult] CA Dly = 33
4032 16:37:05.185100 CS Dly: 6 (0~37)
4033 16:37:05.188492 ==
4034 16:37:05.191747 Dram Type= 6, Freq= 0, CH_0, rank 1
4035 16:37:05.195314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 16:37:05.195414 ==
4037 16:37:05.198691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4038 16:37:05.205088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4039 16:37:05.209253 [CA 0] Center 36 (6~66) winsize 61
4040 16:37:05.211904 [CA 1] Center 36 (6~66) winsize 61
4041 16:37:05.215355 [CA 2] Center 34 (4~64) winsize 61
4042 16:37:05.218913 [CA 3] Center 34 (4~64) winsize 61
4043 16:37:05.222301 [CA 4] Center 33 (2~64) winsize 63
4044 16:37:05.225654 [CA 5] Center 33 (2~64) winsize 63
4045 16:37:05.225762
4046 16:37:05.229003 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4047 16:37:05.229101
4048 16:37:05.232413 [CATrainingPosCal] consider 2 rank data
4049 16:37:05.235071 u2DelayCellTimex100 = 270/100 ps
4050 16:37:05.238606 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4051 16:37:05.245317 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4052 16:37:05.248440 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4053 16:37:05.251730 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4054 16:37:05.254837 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4055 16:37:05.258058 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4056 16:37:05.258157
4057 16:37:05.261436 CA PerBit enable=1, Macro0, CA PI delay=33
4058 16:37:05.261511
4059 16:37:05.265190 [CBTSetCACLKResult] CA Dly = 33
4060 16:37:05.268245 CS Dly: 6 (0~37)
4061 16:37:05.268318
4062 16:37:05.271376 ----->DramcWriteLeveling(PI) begin...
4063 16:37:05.271465 ==
4064 16:37:05.274765 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 16:37:05.277989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 16:37:05.278087 ==
4067 16:37:05.281404 Write leveling (Byte 0): 33 => 33
4068 16:37:05.284680 Write leveling (Byte 1): 30 => 30
4069 16:37:05.288068 DramcWriteLeveling(PI) end<-----
4070 16:37:05.288170
4071 16:37:05.288261 ==
4072 16:37:05.291483 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 16:37:05.294951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 16:37:05.295051 ==
4075 16:37:05.297693 [Gating] SW mode calibration
4076 16:37:05.305004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4077 16:37:05.311378 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4078 16:37:05.314228 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 16:37:05.317674 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 16:37:05.324157 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4081 16:37:05.327562 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4082 16:37:05.331015 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4083 16:37:05.337876 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 16:37:05.340588 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 16:37:05.344051 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 16:37:05.350488 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 16:37:05.353900 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 16:37:05.357172 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 16:37:05.363549 0 10 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4090 16:37:05.366948 0 10 16 | B1->B0 | 3434 3c3c | 0 1 | (1 1) (0 0)
4091 16:37:05.370427 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 16:37:05.377039 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 16:37:05.380202 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 16:37:05.383345 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 16:37:05.389848 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 16:37:05.393507 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 16:37:05.396415 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 16:37:05.403389 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4099 16:37:05.406846 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 16:37:05.410299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 16:37:05.416581 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 16:37:05.419943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 16:37:05.422905 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 16:37:05.429810 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 16:37:05.433231 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 16:37:05.435899 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 16:37:05.442614 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 16:37:05.446471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 16:37:05.449271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 16:37:05.456269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 16:37:05.459662 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 16:37:05.462470 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 16:37:05.469104 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4114 16:37:05.472438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 16:37:05.475689 Total UI for P1: 0, mck2ui 16
4116 16:37:05.479094 best dqsien dly found for B0: ( 0, 13, 12)
4117 16:37:05.482560 Total UI for P1: 0, mck2ui 16
4118 16:37:05.485987 best dqsien dly found for B1: ( 0, 13, 12)
4119 16:37:05.488733 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4120 16:37:05.492174 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4121 16:37:05.492269
4122 16:37:05.495603 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4123 16:37:05.502134 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4124 16:37:05.502239 [Gating] SW calibration Done
4125 16:37:05.502302 ==
4126 16:37:05.505779 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 16:37:05.512104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 16:37:05.512185 ==
4129 16:37:05.512248 RX Vref Scan: 0
4130 16:37:05.512307
4131 16:37:05.515773 RX Vref 0 -> 0, step: 1
4132 16:37:05.515853
4133 16:37:05.518984 RX Delay -230 -> 252, step: 16
4134 16:37:05.522374 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4135 16:37:05.525081 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4136 16:37:05.532160 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4137 16:37:05.535110 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4138 16:37:05.538464 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4139 16:37:05.541945 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4140 16:37:05.545507 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4141 16:37:05.552119 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4142 16:37:05.555209 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4143 16:37:05.558585 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4144 16:37:05.561378 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4145 16:37:05.568156 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4146 16:37:05.571616 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4147 16:37:05.574997 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4148 16:37:05.578017 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4149 16:37:05.584492 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4150 16:37:05.584575 ==
4151 16:37:05.587845 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 16:37:05.591386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 16:37:05.591470 ==
4154 16:37:05.591545 DQS Delay:
4155 16:37:05.594855 DQS0 = 0, DQS1 = 0
4156 16:37:05.594935 DQM Delay:
4157 16:37:05.598297 DQM0 = 42, DQM1 = 28
4158 16:37:05.598393 DQ Delay:
4159 16:37:05.601217 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4160 16:37:05.604557 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4161 16:37:05.607977 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4162 16:37:05.610836 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4163 16:37:05.610916
4164 16:37:05.610983
4165 16:37:05.611068 ==
4166 16:37:05.614280 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 16:37:05.617783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 16:37:05.621139 ==
4169 16:37:05.621240
4170 16:37:05.621332
4171 16:37:05.621460 TX Vref Scan disable
4172 16:37:05.624528 == TX Byte 0 ==
4173 16:37:05.627654 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4174 16:37:05.634180 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4175 16:37:05.634275 == TX Byte 1 ==
4176 16:37:05.637683 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4177 16:37:05.643853 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4178 16:37:05.643936 ==
4179 16:37:05.647302 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 16:37:05.650890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 16:37:05.650970 ==
4182 16:37:05.651034
4183 16:37:05.651092
4184 16:37:05.654153 TX Vref Scan disable
4185 16:37:05.657439 == TX Byte 0 ==
4186 16:37:05.660292 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4187 16:37:05.663615 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4188 16:37:05.667136 == TX Byte 1 ==
4189 16:37:05.670646 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4190 16:37:05.673569 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4191 16:37:05.673649
4192 16:37:05.676913 [DATLAT]
4193 16:37:05.677017 Freq=600, CH0 RK0
4194 16:37:05.677111
4195 16:37:05.680380 DATLAT Default: 0x9
4196 16:37:05.680485 0, 0xFFFF, sum = 0
4197 16:37:05.683687 1, 0xFFFF, sum = 0
4198 16:37:05.683800 2, 0xFFFF, sum = 0
4199 16:37:05.687246 3, 0xFFFF, sum = 0
4200 16:37:05.687327 4, 0xFFFF, sum = 0
4201 16:37:05.690427 5, 0xFFFF, sum = 0
4202 16:37:05.690541 6, 0xFFFF, sum = 0
4203 16:37:05.693533 7, 0xFFFF, sum = 0
4204 16:37:05.693641 8, 0x0, sum = 1
4205 16:37:05.696904 9, 0x0, sum = 2
4206 16:37:05.696986 10, 0x0, sum = 3
4207 16:37:05.700319 11, 0x0, sum = 4
4208 16:37:05.700401 best_step = 9
4209 16:37:05.700463
4210 16:37:05.700522 ==
4211 16:37:05.703647 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 16:37:05.706489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 16:37:05.706597 ==
4214 16:37:05.709975 RX Vref Scan: 1
4215 16:37:05.710074
4216 16:37:05.713433 RX Vref 0 -> 0, step: 1
4217 16:37:05.713533
4218 16:37:05.713624 RX Delay -195 -> 252, step: 8
4219 16:37:05.716235
4220 16:37:05.716330 Set Vref, RX VrefLevel [Byte0]: 56
4221 16:37:05.719650 [Byte1]: 50
4222 16:37:05.724508
4223 16:37:05.724615 Final RX Vref Byte 0 = 56 to rank0
4224 16:37:05.727893 Final RX Vref Byte 1 = 50 to rank0
4225 16:37:05.731470 Final RX Vref Byte 0 = 56 to rank1
4226 16:37:05.734467 Final RX Vref Byte 1 = 50 to rank1==
4227 16:37:05.737696 Dram Type= 6, Freq= 0, CH_0, rank 0
4228 16:37:05.744343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 16:37:05.744449 ==
4230 16:37:05.744540 DQS Delay:
4231 16:37:05.747652 DQS0 = 0, DQS1 = 0
4232 16:37:05.747764 DQM Delay:
4233 16:37:05.747857 DQM0 = 45, DQM1 = 32
4234 16:37:05.750864 DQ Delay:
4235 16:37:05.754401 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =40
4236 16:37:05.757502 DQ4 =44, DQ5 =36, DQ6 =56, DQ7 =52
4237 16:37:05.760976 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4238 16:37:05.764413 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4239 16:37:05.764515
4240 16:37:05.764604
4241 16:37:05.770808 [DQSOSCAuto] RK0, (LSB)MR18= 0x673f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4242 16:37:05.774028 CH0 RK0: MR19=808, MR18=673F
4243 16:37:05.780978 CH0_RK0: MR19=0x808, MR18=0x673F, DQSOSC=390, MR23=63, INC=172, DEC=114
4244 16:37:05.781089
4245 16:37:05.783824 ----->DramcWriteLeveling(PI) begin...
4246 16:37:05.783926 ==
4247 16:37:05.787486 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 16:37:05.790804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 16:37:05.790880 ==
4250 16:37:05.793758 Write leveling (Byte 0): 35 => 35
4251 16:37:05.797103 Write leveling (Byte 1): 29 => 29
4252 16:37:05.800501 DramcWriteLeveling(PI) end<-----
4253 16:37:05.800582
4254 16:37:05.800645 ==
4255 16:37:05.803925 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 16:37:05.810292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 16:37:05.810373 ==
4258 16:37:05.810437 [Gating] SW mode calibration
4259 16:37:05.820042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4260 16:37:05.823436 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4261 16:37:05.826704 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 16:37:05.833165 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 16:37:05.836619 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 16:37:05.843330 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4265 16:37:05.846195 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
4266 16:37:05.849613 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 16:37:05.856585 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 16:37:05.859276 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 16:37:05.862648 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 16:37:05.866151 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 16:37:05.872420 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 16:37:05.876174 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4273 16:37:05.879285 0 10 16 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
4274 16:37:05.886243 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 16:37:05.889272 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 16:37:05.896303 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 16:37:05.898928 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 16:37:05.902322 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 16:37:05.909421 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 16:37:05.912449 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4281 16:37:05.915773 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 16:37:05.921893 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 16:37:05.925482 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 16:37:05.929067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 16:37:05.935201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 16:37:05.938652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 16:37:05.942140 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 16:37:05.945555 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 16:37:05.951716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 16:37:05.955419 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 16:37:05.958736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 16:37:05.964817 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 16:37:05.968226 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 16:37:05.971672 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 16:37:05.978557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 16:37:05.981993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4297 16:37:05.984657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 16:37:05.987989 Total UI for P1: 0, mck2ui 16
4299 16:37:05.991298 best dqsien dly found for B0: ( 0, 13, 12)
4300 16:37:05.994536 Total UI for P1: 0, mck2ui 16
4301 16:37:05.997763 best dqsien dly found for B1: ( 0, 13, 12)
4302 16:37:06.004626 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4303 16:37:06.007898 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4304 16:37:06.008007
4305 16:37:06.011449 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4306 16:37:06.014429 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4307 16:37:06.017821 [Gating] SW calibration Done
4308 16:37:06.017900 ==
4309 16:37:06.021136 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 16:37:06.024321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 16:37:06.024400 ==
4312 16:37:06.027817 RX Vref Scan: 0
4313 16:37:06.027896
4314 16:37:06.028005 RX Vref 0 -> 0, step: 1
4315 16:37:06.028065
4316 16:37:06.031148 RX Delay -230 -> 252, step: 16
4317 16:37:06.034439 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4318 16:37:06.040657 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4319 16:37:06.044172 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4320 16:37:06.047751 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4321 16:37:06.050436 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4322 16:37:06.057473 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4323 16:37:06.060943 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4324 16:37:06.063632 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4325 16:37:06.067061 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4326 16:37:06.074005 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4327 16:37:06.077329 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4328 16:37:06.080856 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4329 16:37:06.083612 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4330 16:37:06.090061 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4331 16:37:06.093463 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4332 16:37:06.096877 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4333 16:37:06.096952 ==
4334 16:37:06.100284 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 16:37:06.103596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 16:37:06.103676 ==
4337 16:37:06.107264 DQS Delay:
4338 16:37:06.107375 DQS0 = 0, DQS1 = 0
4339 16:37:06.110385 DQM Delay:
4340 16:37:06.110465 DQM0 = 43, DQM1 = 37
4341 16:37:06.110528 DQ Delay:
4342 16:37:06.113505 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4343 16:37:06.116648 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4344 16:37:06.120195 DQ8 =33, DQ9 =17, DQ10 =41, DQ11 =33
4345 16:37:06.123499 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4346 16:37:06.123602
4347 16:37:06.127161
4348 16:37:06.127239 ==
4349 16:37:06.129774 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 16:37:06.133150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 16:37:06.133234 ==
4352 16:37:06.133297
4353 16:37:06.133359
4354 16:37:06.136487 TX Vref Scan disable
4355 16:37:06.136558 == TX Byte 0 ==
4356 16:37:06.143027 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4357 16:37:06.146564 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4358 16:37:06.146654 == TX Byte 1 ==
4359 16:37:06.153522 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4360 16:37:06.156397 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4361 16:37:06.156472 ==
4362 16:37:06.159784 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 16:37:06.163111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 16:37:06.163196 ==
4365 16:37:06.163260
4366 16:37:06.163323
4367 16:37:06.166570 TX Vref Scan disable
4368 16:37:06.170029 == TX Byte 0 ==
4369 16:37:06.173027 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4370 16:37:06.176332 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4371 16:37:06.179636 == TX Byte 1 ==
4372 16:37:06.182945 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4373 16:37:06.189907 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4374 16:37:06.189988
4375 16:37:06.190052 [DATLAT]
4376 16:37:06.190110 Freq=600, CH0 RK1
4377 16:37:06.190194
4378 16:37:06.192669 DATLAT Default: 0x9
4379 16:37:06.192751 0, 0xFFFF, sum = 0
4380 16:37:06.196186 1, 0xFFFF, sum = 0
4381 16:37:06.196266 2, 0xFFFF, sum = 0
4382 16:37:06.199611 3, 0xFFFF, sum = 0
4383 16:37:06.203129 4, 0xFFFF, sum = 0
4384 16:37:06.203209 5, 0xFFFF, sum = 0
4385 16:37:06.205940 6, 0xFFFF, sum = 0
4386 16:37:06.206047 7, 0xFFFF, sum = 0
4387 16:37:06.209226 8, 0x0, sum = 1
4388 16:37:06.209298 9, 0x0, sum = 2
4389 16:37:06.209362 10, 0x0, sum = 3
4390 16:37:06.212804 11, 0x0, sum = 4
4391 16:37:06.212887 best_step = 9
4392 16:37:06.212950
4393 16:37:06.213008 ==
4394 16:37:06.216225 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 16:37:06.222322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 16:37:06.222401 ==
4397 16:37:06.222464 RX Vref Scan: 0
4398 16:37:06.222523
4399 16:37:06.225816 RX Vref 0 -> 0, step: 1
4400 16:37:06.225895
4401 16:37:06.229154 RX Delay -195 -> 252, step: 8
4402 16:37:06.235567 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4403 16:37:06.238751 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4404 16:37:06.241850 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4405 16:37:06.245837 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4406 16:37:06.249107 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4407 16:37:06.255230 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4408 16:37:06.258641 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4409 16:37:06.262100 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4410 16:37:06.265425 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4411 16:37:06.271747 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4412 16:37:06.275245 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4413 16:37:06.278568 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4414 16:37:06.281332 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4415 16:37:06.288141 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4416 16:37:06.291487 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4417 16:37:06.295091 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4418 16:37:06.295164 ==
4419 16:37:06.297742 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 16:37:06.304639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 16:37:06.304720 ==
4422 16:37:06.304782 DQS Delay:
4423 16:37:06.304841 DQS0 = 0, DQS1 = 0
4424 16:37:06.308068 DQM Delay:
4425 16:37:06.308150 DQM0 = 41, DQM1 = 36
4426 16:37:06.310963 DQ Delay:
4427 16:37:06.314473 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4428 16:37:06.317654 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4429 16:37:06.321144 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4430 16:37:06.324503 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4431 16:37:06.324589
4432 16:37:06.324650
4433 16:37:06.330774 [DQSOSCAuto] RK1, (LSB)MR18= 0x6114, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4434 16:37:06.334139 CH0 RK1: MR19=808, MR18=6114
4435 16:37:06.341184 CH0_RK1: MR19=0x808, MR18=0x6114, DQSOSC=391, MR23=63, INC=171, DEC=114
4436 16:37:06.344440 [RxdqsGatingPostProcess] freq 600
4437 16:37:06.347605 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4438 16:37:06.350992 Pre-setting of DQS Precalculation
4439 16:37:06.357145 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4440 16:37:06.357224 ==
4441 16:37:06.360376 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 16:37:06.363749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 16:37:06.363832 ==
4444 16:37:06.370434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 16:37:06.377430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4446 16:37:06.380209 [CA 0] Center 35 (5~66) winsize 62
4447 16:37:06.383663 [CA 1] Center 35 (5~66) winsize 62
4448 16:37:06.387157 [CA 2] Center 34 (4~65) winsize 62
4449 16:37:06.390510 [CA 3] Center 33 (3~64) winsize 62
4450 16:37:06.393980 [CA 4] Center 34 (4~65) winsize 62
4451 16:37:06.396746 [CA 5] Center 33 (3~64) winsize 62
4452 16:37:06.396823
4453 16:37:06.400212 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4454 16:37:06.400311
4455 16:37:06.403619 [CATrainingPosCal] consider 1 rank data
4456 16:37:06.406997 u2DelayCellTimex100 = 270/100 ps
4457 16:37:06.410446 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 16:37:06.413761 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 16:37:06.416534 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 16:37:06.419905 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 16:37:06.423372 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 16:37:06.426594 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 16:37:06.426777
4464 16:37:06.433043 CA PerBit enable=1, Macro0, CA PI delay=33
4465 16:37:06.433179
4466 16:37:06.436439 [CBTSetCACLKResult] CA Dly = 33
4467 16:37:06.436545 CS Dly: 5 (0~36)
4468 16:37:06.436612 ==
4469 16:37:06.440102 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 16:37:06.443013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 16:37:06.443122 ==
4472 16:37:06.449953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4473 16:37:06.456507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4474 16:37:06.459977 [CA 0] Center 35 (5~66) winsize 62
4475 16:37:06.462682 [CA 1] Center 36 (6~66) winsize 61
4476 16:37:06.465923 [CA 2] Center 34 (4~65) winsize 62
4477 16:37:06.469278 [CA 3] Center 34 (4~65) winsize 62
4478 16:37:06.472649 [CA 4] Center 34 (4~65) winsize 62
4479 16:37:06.476079 [CA 5] Center 34 (3~65) winsize 63
4480 16:37:06.476166
4481 16:37:06.479749 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4482 16:37:06.479844
4483 16:37:06.482908 [CATrainingPosCal] consider 2 rank data
4484 16:37:06.486334 u2DelayCellTimex100 = 270/100 ps
4485 16:37:06.489040 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4486 16:37:06.492341 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4487 16:37:06.495902 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4488 16:37:06.499314 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4489 16:37:06.506136 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4490 16:37:06.508938 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4491 16:37:06.509026
4492 16:37:06.512424 CA PerBit enable=1, Macro0, CA PI delay=33
4493 16:37:06.512509
4494 16:37:06.515969 [CBTSetCACLKResult] CA Dly = 33
4495 16:37:06.516053 CS Dly: 4 (0~35)
4496 16:37:06.516117
4497 16:37:06.518813 ----->DramcWriteLeveling(PI) begin...
4498 16:37:06.518898 ==
4499 16:37:06.522285 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 16:37:06.528659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 16:37:06.528752 ==
4502 16:37:06.531947 Write leveling (Byte 0): 30 => 30
4503 16:37:06.535480 Write leveling (Byte 1): 28 => 28
4504 16:37:06.538956 DramcWriteLeveling(PI) end<-----
4505 16:37:06.539044
4506 16:37:06.539108 ==
4507 16:37:06.541776 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 16:37:06.545311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 16:37:06.545397 ==
4510 16:37:06.548546 [Gating] SW mode calibration
4511 16:37:06.555522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4512 16:37:06.558806 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4513 16:37:06.565233 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 16:37:06.568601 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 16:37:06.572049 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 16:37:06.578113 0 9 12 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 1)
4517 16:37:06.581646 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 16:37:06.585156 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 16:37:06.591501 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 16:37:06.594724 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 16:37:06.598483 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 16:37:06.604530 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 16:37:06.608205 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 16:37:06.611625 0 10 12 | B1->B0 | 3232 3737 | 0 0 | (1 1) (0 0)
4525 16:37:06.617904 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 16:37:06.621315 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 16:37:06.624628 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 16:37:06.631367 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 16:37:06.634754 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 16:37:06.638152 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 16:37:06.644479 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 16:37:06.647965 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4533 16:37:06.650858 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 16:37:06.657688 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 16:37:06.661177 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 16:37:06.664461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 16:37:06.670622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 16:37:06.673980 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 16:37:06.677518 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 16:37:06.684296 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 16:37:06.687002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 16:37:06.690464 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 16:37:06.697250 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 16:37:06.700610 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 16:37:06.704117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 16:37:06.710014 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 16:37:06.713780 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 16:37:06.716935 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4549 16:37:06.723318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 16:37:06.726902 Total UI for P1: 0, mck2ui 16
4551 16:37:06.730071 best dqsien dly found for B0: ( 0, 13, 12)
4552 16:37:06.733269 Total UI for P1: 0, mck2ui 16
4553 16:37:06.736763 best dqsien dly found for B1: ( 0, 13, 14)
4554 16:37:06.739442 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4555 16:37:06.743100 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4556 16:37:06.743180
4557 16:37:06.746439 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4558 16:37:06.749809 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4559 16:37:06.753138 [Gating] SW calibration Done
4560 16:37:06.753219 ==
4561 16:37:06.755922 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 16:37:06.759377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 16:37:06.762746 ==
4564 16:37:06.762834 RX Vref Scan: 0
4565 16:37:06.762897
4566 16:37:06.766099 RX Vref 0 -> 0, step: 1
4567 16:37:06.766205
4568 16:37:06.769475 RX Delay -230 -> 252, step: 16
4569 16:37:06.772959 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4570 16:37:06.776508 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4571 16:37:06.779401 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4572 16:37:06.782823 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4573 16:37:06.789175 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4574 16:37:06.794685 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4575 16:37:06.796018 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4576 16:37:06.799559 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4577 16:37:06.806048 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4578 16:37:06.808810 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4579 16:37:06.812461 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4580 16:37:06.815886 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4581 16:37:06.822086 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4582 16:37:06.825585 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4583 16:37:06.829112 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4584 16:37:06.832429 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4585 16:37:06.835572 ==
4586 16:37:06.835649 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 16:37:06.842196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 16:37:06.842307 ==
4589 16:37:06.842427 DQS Delay:
4590 16:37:06.845281 DQS0 = 0, DQS1 = 0
4591 16:37:06.845362 DQM Delay:
4592 16:37:06.848663 DQM0 = 46, DQM1 = 35
4593 16:37:06.848743 DQ Delay:
4594 16:37:06.851850 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4595 16:37:06.855287 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4596 16:37:06.858047 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4597 16:37:06.861538 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4598 16:37:06.861615
4599 16:37:06.861688
4600 16:37:06.861750 ==
4601 16:37:06.864929 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 16:37:06.868287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 16:37:06.868363 ==
4604 16:37:06.868425
4605 16:37:06.868483
4606 16:37:06.871323 TX Vref Scan disable
4607 16:37:06.874692 == TX Byte 0 ==
4608 16:37:06.878281 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4609 16:37:06.881204 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4610 16:37:06.884483 == TX Byte 1 ==
4611 16:37:06.887888 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4612 16:37:06.891327 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4613 16:37:06.891407 ==
4614 16:37:06.894123 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 16:37:06.901155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 16:37:06.901305 ==
4617 16:37:06.901447
4618 16:37:06.901579
4619 16:37:06.901693 TX Vref Scan disable
4620 16:37:06.905272 == TX Byte 0 ==
4621 16:37:06.908731 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4622 16:37:06.915165 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4623 16:37:06.915273 == TX Byte 1 ==
4624 16:37:06.918806 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4625 16:37:06.925440 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4626 16:37:06.925524
4627 16:37:06.925588 [DATLAT]
4628 16:37:06.925647 Freq=600, CH1 RK0
4629 16:37:06.925721
4630 16:37:06.929028 DATLAT Default: 0x9
4631 16:37:06.929094 0, 0xFFFF, sum = 0
4632 16:37:06.931865 1, 0xFFFF, sum = 0
4633 16:37:06.935408 2, 0xFFFF, sum = 0
4634 16:37:06.935490 3, 0xFFFF, sum = 0
4635 16:37:06.938987 4, 0xFFFF, sum = 0
4636 16:37:06.939068 5, 0xFFFF, sum = 0
4637 16:37:06.942294 6, 0xFFFF, sum = 0
4638 16:37:06.942378 7, 0xFFFF, sum = 0
4639 16:37:06.945084 8, 0x0, sum = 1
4640 16:37:06.945168 9, 0x0, sum = 2
4641 16:37:06.948622 10, 0x0, sum = 3
4642 16:37:06.948715 11, 0x0, sum = 4
4643 16:37:06.948781 best_step = 9
4644 16:37:06.948841
4645 16:37:06.951825 ==
4646 16:37:06.955009 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 16:37:06.958480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 16:37:06.958562 ==
4649 16:37:06.958627 RX Vref Scan: 1
4650 16:37:06.958687
4651 16:37:06.961529 RX Vref 0 -> 0, step: 1
4652 16:37:06.961611
4653 16:37:06.964812 RX Delay -195 -> 252, step: 8
4654 16:37:06.964910
4655 16:37:06.968032 Set Vref, RX VrefLevel [Byte0]: 50
4656 16:37:06.971492 [Byte1]: 59
4657 16:37:06.971583
4658 16:37:06.974456 Final RX Vref Byte 0 = 50 to rank0
4659 16:37:06.977860 Final RX Vref Byte 1 = 59 to rank0
4660 16:37:06.981454 Final RX Vref Byte 0 = 50 to rank1
4661 16:37:06.984398 Final RX Vref Byte 1 = 59 to rank1==
4662 16:37:06.987969 Dram Type= 6, Freq= 0, CH_1, rank 0
4663 16:37:06.994834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 16:37:06.994917 ==
4665 16:37:06.994983 DQS Delay:
4666 16:37:06.995044 DQS0 = 0, DQS1 = 0
4667 16:37:06.997627 DQM Delay:
4668 16:37:06.997735 DQM0 = 47, DQM1 = 38
4669 16:37:07.001246 DQ Delay:
4670 16:37:07.004557 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4671 16:37:07.007545 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4672 16:37:07.011142 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4673 16:37:07.014095 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4674 16:37:07.014207
4675 16:37:07.014273
4676 16:37:07.021139 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4677 16:37:07.023929 CH1 RK0: MR19=808, MR18=4B30
4678 16:37:07.030739 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4679 16:37:07.030822
4680 16:37:07.034370 ----->DramcWriteLeveling(PI) begin...
4681 16:37:07.034463 ==
4682 16:37:07.037184 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 16:37:07.040724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 16:37:07.040835 ==
4685 16:37:07.044258 Write leveling (Byte 0): 30 => 30
4686 16:37:07.047063 Write leveling (Byte 1): 30 => 30
4687 16:37:07.050617 DramcWriteLeveling(PI) end<-----
4688 16:37:07.050700
4689 16:37:07.050764 ==
4690 16:37:07.054103 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 16:37:07.057047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 16:37:07.060260 ==
4693 16:37:07.060342 [Gating] SW mode calibration
4694 16:37:07.069868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4695 16:37:07.073326 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4696 16:37:07.076633 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 16:37:07.083576 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 16:37:07.086365 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 16:37:07.089757 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (1 0) (0 0)
4700 16:37:07.096018 0 9 16 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
4701 16:37:07.099417 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 16:37:07.102906 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 16:37:07.109143 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 16:37:07.112746 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 16:37:07.116251 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 16:37:07.122632 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 16:37:07.126013 0 10 12 | B1->B0 | 3333 2929 | 1 1 | (0 0) (0 0)
4708 16:37:07.132389 0 10 16 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
4709 16:37:07.135774 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 16:37:07.139292 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 16:37:07.145521 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 16:37:07.148906 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 16:37:07.152229 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 16:37:07.158537 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 16:37:07.161972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 16:37:07.165261 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4717 16:37:07.171868 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 16:37:07.175483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 16:37:07.178945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 16:37:07.185035 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 16:37:07.188194 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 16:37:07.191436 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 16:37:07.198047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 16:37:07.201371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 16:37:07.204884 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 16:37:07.211205 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 16:37:07.214525 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 16:37:07.218051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 16:37:07.224368 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 16:37:07.227880 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 16:37:07.231108 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4732 16:37:07.234472 Total UI for P1: 0, mck2ui 16
4733 16:37:07.237917 best dqsien dly found for B1: ( 0, 13, 10)
4734 16:37:07.244541 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 16:37:07.244623 Total UI for P1: 0, mck2ui 16
4736 16:37:07.247322 best dqsien dly found for B0: ( 0, 13, 14)
4737 16:37:07.254110 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4738 16:37:07.257485 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4739 16:37:07.257567
4740 16:37:07.260955 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4741 16:37:07.263696 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4742 16:37:07.267132 [Gating] SW calibration Done
4743 16:37:07.267213 ==
4744 16:37:07.270346 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 16:37:07.274004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 16:37:07.274085 ==
4747 16:37:07.276925 RX Vref Scan: 0
4748 16:37:07.277005
4749 16:37:07.277068 RX Vref 0 -> 0, step: 1
4750 16:37:07.277127
4751 16:37:07.280193 RX Delay -230 -> 252, step: 16
4752 16:37:07.286776 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4753 16:37:07.290266 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4754 16:37:07.294037 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4755 16:37:07.296652 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4756 16:37:07.300015 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4757 16:37:07.306692 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4758 16:37:07.309945 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4759 16:37:07.313681 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4760 16:37:07.316963 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4761 16:37:07.323732 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4762 16:37:07.326604 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4763 16:37:07.330157 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4764 16:37:07.333620 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4765 16:37:07.339948 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4766 16:37:07.343567 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4767 16:37:07.346911 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4768 16:37:07.347024 ==
4769 16:37:07.350176 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 16:37:07.353562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 16:37:07.356358 ==
4772 16:37:07.356463 DQS Delay:
4773 16:37:07.356563 DQS0 = 0, DQS1 = 0
4774 16:37:07.359556 DQM Delay:
4775 16:37:07.359665 DQM0 = 44, DQM1 = 37
4776 16:37:07.363002 DQ Delay:
4777 16:37:07.366537 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4778 16:37:07.366619 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4779 16:37:07.369327 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4780 16:37:07.372747 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4781 16:37:07.376231
4782 16:37:07.376318
4783 16:37:07.376383 ==
4784 16:37:07.379765 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 16:37:07.382489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 16:37:07.382572 ==
4787 16:37:07.382659
4788 16:37:07.382736
4789 16:37:07.386027 TX Vref Scan disable
4790 16:37:07.386136 == TX Byte 0 ==
4791 16:37:07.392359 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4792 16:37:07.395938 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4793 16:37:07.396022 == TX Byte 1 ==
4794 16:37:07.402363 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4795 16:37:07.405771 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4796 16:37:07.405880 ==
4797 16:37:07.409429 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 16:37:07.412183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 16:37:07.412266 ==
4800 16:37:07.412331
4801 16:37:07.415734
4802 16:37:07.415816 TX Vref Scan disable
4803 16:37:07.419032 == TX Byte 0 ==
4804 16:37:07.422398 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4805 16:37:07.428780 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4806 16:37:07.428886 == TX Byte 1 ==
4807 16:37:07.432047 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4808 16:37:07.438910 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4809 16:37:07.439001
4810 16:37:07.439066 [DATLAT]
4811 16:37:07.439127 Freq=600, CH1 RK1
4812 16:37:07.439186
4813 16:37:07.442245 DATLAT Default: 0x9
4814 16:37:07.445061 0, 0xFFFF, sum = 0
4815 16:37:07.445143 1, 0xFFFF, sum = 0
4816 16:37:07.448498 2, 0xFFFF, sum = 0
4817 16:37:07.448595 3, 0xFFFF, sum = 0
4818 16:37:07.451719 4, 0xFFFF, sum = 0
4819 16:37:07.451827 5, 0xFFFF, sum = 0
4820 16:37:07.455150 6, 0xFFFF, sum = 0
4821 16:37:07.455232 7, 0xFFFF, sum = 0
4822 16:37:07.459071 8, 0x0, sum = 1
4823 16:37:07.459154 9, 0x0, sum = 2
4824 16:37:07.459218 10, 0x0, sum = 3
4825 16:37:07.461695 11, 0x0, sum = 4
4826 16:37:07.461804 best_step = 9
4827 16:37:07.461895
4828 16:37:07.464970 ==
4829 16:37:07.465094 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 16:37:07.471875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 16:37:07.471995 ==
4832 16:37:07.472060 RX Vref Scan: 0
4833 16:37:07.472121
4834 16:37:07.475202 RX Vref 0 -> 0, step: 1
4835 16:37:07.475283
4836 16:37:07.478632 RX Delay -195 -> 252, step: 8
4837 16:37:07.485293 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4838 16:37:07.488073 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4839 16:37:07.491580 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4840 16:37:07.495195 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4841 16:37:07.497904 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4842 16:37:07.614068 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4843 16:37:07.614463 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4844 16:37:07.614571 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4845 16:37:07.614647 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4846 16:37:07.614758 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4847 16:37:07.614830 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4848 16:37:07.614903 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4849 16:37:07.614959 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4850 16:37:07.615014 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4851 16:37:07.615069 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4852 16:37:07.615123 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4853 16:37:07.615178 ==
4854 16:37:07.615233 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 16:37:07.615287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 16:37:07.615341 ==
4857 16:37:07.615394 DQS Delay:
4858 16:37:07.615448 DQS0 = 0, DQS1 = 0
4859 16:37:07.615502 DQM Delay:
4860 16:37:07.615556 DQM0 = 45, DQM1 = 37
4861 16:37:07.615609 DQ Delay:
4862 16:37:07.615662 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4863 16:37:07.615716 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4864 16:37:07.615769 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4865 16:37:07.615822 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4866 16:37:07.615876
4867 16:37:07.615929
4868 16:37:07.615982 [DQSOSCAuto] RK1, (LSB)MR18= 0x281d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4869 16:37:07.616041 CH1 RK1: MR19=808, MR18=281D
4870 16:37:07.616095 CH1_RK1: MR19=0x808, MR18=0x281D, DQSOSC=402, MR23=63, INC=162, DEC=108
4871 16:37:07.616150 [RxdqsGatingPostProcess] freq 600
4872 16:37:07.616204 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4873 16:37:07.616258 Pre-setting of DQS Precalculation
4874 16:37:07.616311 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4875 16:37:07.616364 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4876 16:37:07.620433 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4877 16:37:07.620560
4878 16:37:07.620625
4879 16:37:07.623216 [Calibration Summary] 1200 Mbps
4880 16:37:07.623298 CH 0, Rank 0
4881 16:37:07.626698 SW Impedance : PASS
4882 16:37:07.630098 DUTY Scan : NO K
4883 16:37:07.630228 ZQ Calibration : PASS
4884 16:37:07.633572 Jitter Meter : NO K
4885 16:37:07.636451 CBT Training : PASS
4886 16:37:07.636535 Write leveling : PASS
4887 16:37:07.639978 RX DQS gating : PASS
4888 16:37:07.643430 RX DQ/DQS(RDDQC) : PASS
4889 16:37:07.643516 TX DQ/DQS : PASS
4890 16:37:07.646929 RX DATLAT : PASS
4891 16:37:07.647015 RX DQ/DQS(Engine): PASS
4892 16:37:07.649605 TX OE : NO K
4893 16:37:07.649690 All Pass.
4894 16:37:07.649754
4895 16:37:07.653042 CH 0, Rank 1
4896 16:37:07.656297 SW Impedance : PASS
4897 16:37:07.656378 DUTY Scan : NO K
4898 16:37:07.660073 ZQ Calibration : PASS
4899 16:37:07.660154 Jitter Meter : NO K
4900 16:37:07.663243 CBT Training : PASS
4901 16:37:07.666550 Write leveling : PASS
4902 16:37:07.666649 RX DQS gating : PASS
4903 16:37:07.669963 RX DQ/DQS(RDDQC) : PASS
4904 16:37:07.673231 TX DQ/DQS : PASS
4905 16:37:07.673314 RX DATLAT : PASS
4906 16:37:07.675997 RX DQ/DQS(Engine): PASS
4907 16:37:07.679661 TX OE : NO K
4908 16:37:07.679736 All Pass.
4909 16:37:07.679797
4910 16:37:07.679859 CH 1, Rank 0
4911 16:37:07.683190 SW Impedance : PASS
4912 16:37:07.686055 DUTY Scan : NO K
4913 16:37:07.686190 ZQ Calibration : PASS
4914 16:37:07.689610 Jitter Meter : NO K
4915 16:37:07.693131 CBT Training : PASS
4916 16:37:07.693248 Write leveling : PASS
4917 16:37:07.695984 RX DQS gating : PASS
4918 16:37:07.699803 RX DQ/DQS(RDDQC) : PASS
4919 16:37:07.699927 TX DQ/DQS : PASS
4920 16:37:07.702613 RX DATLAT : PASS
4921 16:37:07.706008 RX DQ/DQS(Engine): PASS
4922 16:37:07.706126 TX OE : NO K
4923 16:37:07.706244 All Pass.
4924 16:37:07.709374
4925 16:37:07.709462 CH 1, Rank 1
4926 16:37:07.712838 SW Impedance : PASS
4927 16:37:07.712920 DUTY Scan : NO K
4928 16:37:07.716326 ZQ Calibration : PASS
4929 16:37:07.719215 Jitter Meter : NO K
4930 16:37:07.719296 CBT Training : PASS
4931 16:37:07.722550 Write leveling : PASS
4932 16:37:07.722632 RX DQS gating : PASS
4933 16:37:07.725976 RX DQ/DQS(RDDQC) : PASS
4934 16:37:07.729588 TX DQ/DQS : PASS
4935 16:37:07.729665 RX DATLAT : PASS
4936 16:37:07.732152 RX DQ/DQS(Engine): PASS
4937 16:37:07.735524 TX OE : NO K
4938 16:37:07.735606 All Pass.
4939 16:37:07.735669
4940 16:37:07.739067 DramC Write-DBI off
4941 16:37:07.739139 PER_BANK_REFRESH: Hybrid Mode
4942 16:37:07.742532 TX_TRACKING: ON
4943 16:37:07.752266 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4944 16:37:07.755635 [FAST_K] Save calibration result to emmc
4945 16:37:07.759076 dramc_set_vcore_voltage set vcore to 662500
4946 16:37:07.759157 Read voltage for 933, 3
4947 16:37:07.761932 Vio18 = 0
4948 16:37:07.762038 Vcore = 662500
4949 16:37:07.762128 Vdram = 0
4950 16:37:07.765257 Vddq = 0
4951 16:37:07.765338 Vmddr = 0
4952 16:37:07.772262 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4953 16:37:07.775674 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4954 16:37:07.778903 MEM_TYPE=3, freq_sel=17
4955 16:37:07.782063 sv_algorithm_assistance_LP4_1600
4956 16:37:07.785283 ============ PULL DRAM RESETB DOWN ============
4957 16:37:07.788798 ========== PULL DRAM RESETB DOWN end =========
4958 16:37:07.795286 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 16:37:07.798594 ===================================
4960 16:37:07.798678 LPDDR4 DRAM CONFIGURATION
4961 16:37:07.801832 ===================================
4962 16:37:07.805171 EX_ROW_EN[0] = 0x0
4963 16:37:07.808663 EX_ROW_EN[1] = 0x0
4964 16:37:07.808744 LP4Y_EN = 0x0
4965 16:37:07.811545 WORK_FSP = 0x0
4966 16:37:07.811625 WL = 0x3
4967 16:37:07.815092 RL = 0x3
4968 16:37:07.815172 BL = 0x2
4969 16:37:07.818551 RPST = 0x0
4970 16:37:07.818632 RD_PRE = 0x0
4971 16:37:07.821318 WR_PRE = 0x1
4972 16:37:07.821398 WR_PST = 0x0
4973 16:37:07.824820 DBI_WR = 0x0
4974 16:37:07.824900 DBI_RD = 0x0
4975 16:37:07.828169 OTF = 0x1
4976 16:37:07.831565 ===================================
4977 16:37:07.834428 ===================================
4978 16:37:07.834527 ANA top config
4979 16:37:07.837911 ===================================
4980 16:37:07.841227 DLL_ASYNC_EN = 0
4981 16:37:07.844691 ALL_SLAVE_EN = 1
4982 16:37:07.848133 NEW_RANK_MODE = 1
4983 16:37:07.848264 DLL_IDLE_MODE = 1
4984 16:37:07.850938 LP45_APHY_COMB_EN = 1
4985 16:37:07.854418 TX_ODT_DIS = 1
4986 16:37:07.857946 NEW_8X_MODE = 1
4987 16:37:07.861448 ===================================
4988 16:37:07.864279 ===================================
4989 16:37:07.867703 data_rate = 1866
4990 16:37:07.867785 CKR = 1
4991 16:37:07.871240 DQ_P2S_RATIO = 8
4992 16:37:07.874448 ===================================
4993 16:37:07.877919 CA_P2S_RATIO = 8
4994 16:37:07.880879 DQ_CA_OPEN = 0
4995 16:37:07.884178 DQ_SEMI_OPEN = 0
4996 16:37:07.887644 CA_SEMI_OPEN = 0
4997 16:37:07.890366 CA_FULL_RATE = 0
4998 16:37:07.890487 DQ_CKDIV4_EN = 1
4999 16:37:07.894203 CA_CKDIV4_EN = 1
5000 16:37:07.897009 CA_PREDIV_EN = 0
5001 16:37:07.900147 PH8_DLY = 0
5002 16:37:07.903941 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5003 16:37:07.906990 DQ_AAMCK_DIV = 4
5004 16:37:07.907074 CA_AAMCK_DIV = 4
5005 16:37:07.910343 CA_ADMCK_DIV = 4
5006 16:37:07.913734 DQ_TRACK_CA_EN = 0
5007 16:37:07.917221 CA_PICK = 933
5008 16:37:07.920120 CA_MCKIO = 933
5009 16:37:07.923562 MCKIO_SEMI = 0
5010 16:37:07.926548 PLL_FREQ = 3732
5011 16:37:07.926643 DQ_UI_PI_RATIO = 32
5012 16:37:07.930073 CA_UI_PI_RATIO = 0
5013 16:37:07.933502 ===================================
5014 16:37:07.936415 ===================================
5015 16:37:07.939905 memory_type:LPDDR4
5016 16:37:07.943477 GP_NUM : 10
5017 16:37:07.943572 SRAM_EN : 1
5018 16:37:07.946330 MD32_EN : 0
5019 16:37:07.949730 ===================================
5020 16:37:07.953173 [ANA_INIT] >>>>>>>>>>>>>>
5021 16:37:07.953257 <<<<<< [CONFIGURE PHASE]: ANA_TX
5022 16:37:07.960090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5023 16:37:07.963483 ===================================
5024 16:37:07.963566 data_rate = 1866,PCW = 0X8f00
5025 16:37:07.966392 ===================================
5026 16:37:07.969854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5027 16:37:07.976495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 16:37:07.982607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 16:37:07.986064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5030 16:37:07.989453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5031 16:37:07.992992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5032 16:37:07.996105 [ANA_INIT] flow start
5033 16:37:07.999240 [ANA_INIT] PLL >>>>>>>>
5034 16:37:07.999335 [ANA_INIT] PLL <<<<<<<<
5035 16:37:08.002773 [ANA_INIT] MIDPI >>>>>>>>
5036 16:37:08.005663 [ANA_INIT] MIDPI <<<<<<<<
5037 16:37:08.005764 [ANA_INIT] DLL >>>>>>>>
5038 16:37:08.009112 [ANA_INIT] flow end
5039 16:37:08.012474 ============ LP4 DIFF to SE enter ============
5040 16:37:08.015720 ============ LP4 DIFF to SE exit ============
5041 16:37:08.019442 [ANA_INIT] <<<<<<<<<<<<<
5042 16:37:08.022605 [Flow] Enable top DCM control >>>>>
5043 16:37:08.025912 [Flow] Enable top DCM control <<<<<
5044 16:37:08.029062 Enable DLL master slave shuffle
5045 16:37:08.035566 ==============================================================
5046 16:37:08.035831 Gating Mode config
5047 16:37:08.042287 ==============================================================
5048 16:37:08.044981 Config description:
5049 16:37:08.052092 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5050 16:37:08.058131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5051 16:37:08.065148 SELPH_MODE 0: By rank 1: By Phase
5052 16:37:08.071283 ==============================================================
5053 16:37:08.074788 GAT_TRACK_EN = 1
5054 16:37:08.074924 RX_GATING_MODE = 2
5055 16:37:08.078130 RX_GATING_TRACK_MODE = 2
5056 16:37:08.081517 SELPH_MODE = 1
5057 16:37:08.084981 PICG_EARLY_EN = 1
5058 16:37:08.088400 VALID_LAT_VALUE = 1
5059 16:37:08.094776 ==============================================================
5060 16:37:08.098198 Enter into Gating configuration >>>>
5061 16:37:08.101616 Exit from Gating configuration <<<<
5062 16:37:08.104930 Enter into DVFS_PRE_config >>>>>
5063 16:37:08.114833 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5064 16:37:08.117799 Exit from DVFS_PRE_config <<<<<
5065 16:37:08.121327 Enter into PICG configuration >>>>
5066 16:37:08.124798 Exit from PICG configuration <<<<
5067 16:37:08.128297 [RX_INPUT] configuration >>>>>
5068 16:37:08.131151 [RX_INPUT] configuration <<<<<
5069 16:37:08.134639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5070 16:37:08.141086 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5071 16:37:08.147821 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 16:37:08.154754 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 16:37:08.157420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 16:37:08.164223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 16:37:08.167716 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5076 16:37:08.174681 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5077 16:37:08.177150 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5078 16:37:08.180850 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5079 16:37:08.184437 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5080 16:37:08.190709 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 16:37:08.194282 ===================================
5082 16:37:08.196911 LPDDR4 DRAM CONFIGURATION
5083 16:37:08.200333 ===================================
5084 16:37:08.200769 EX_ROW_EN[0] = 0x0
5085 16:37:08.203850 EX_ROW_EN[1] = 0x0
5086 16:37:08.204387 LP4Y_EN = 0x0
5087 16:37:08.207433 WORK_FSP = 0x0
5088 16:37:08.207910 WL = 0x3
5089 16:37:08.210879 RL = 0x3
5090 16:37:08.211460 BL = 0x2
5091 16:37:08.213548 RPST = 0x0
5092 16:37:08.214142 RD_PRE = 0x0
5093 16:37:08.217368 WR_PRE = 0x1
5094 16:37:08.220087 WR_PST = 0x0
5095 16:37:08.220506 DBI_WR = 0x0
5096 16:37:08.223447 DBI_RD = 0x0
5097 16:37:08.223924 OTF = 0x1
5098 16:37:08.226959 ===================================
5099 16:37:08.230211 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5100 16:37:08.233504 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5101 16:37:08.240277 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 16:37:08.243008 ===================================
5103 16:37:08.246482 LPDDR4 DRAM CONFIGURATION
5104 16:37:08.250011 ===================================
5105 16:37:08.250573 EX_ROW_EN[0] = 0x10
5106 16:37:08.253217 EX_ROW_EN[1] = 0x0
5107 16:37:08.253638 LP4Y_EN = 0x0
5108 16:37:08.256524 WORK_FSP = 0x0
5109 16:37:08.257189 WL = 0x3
5110 16:37:08.259661 RL = 0x3
5111 16:37:08.260271 BL = 0x2
5112 16:37:08.262954 RPST = 0x0
5113 16:37:08.263453 RD_PRE = 0x0
5114 16:37:08.266908 WR_PRE = 0x1
5115 16:37:08.269955 WR_PST = 0x0
5116 16:37:08.270557 DBI_WR = 0x0
5117 16:37:08.273102 DBI_RD = 0x0
5118 16:37:08.273614 OTF = 0x1
5119 16:37:08.276387 ===================================
5120 16:37:08.282912 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5121 16:37:08.286794 nWR fixed to 30
5122 16:37:08.290328 [ModeRegInit_LP4] CH0 RK0
5123 16:37:08.290761 [ModeRegInit_LP4] CH0 RK1
5124 16:37:08.293044 [ModeRegInit_LP4] CH1 RK0
5125 16:37:08.296491 [ModeRegInit_LP4] CH1 RK1
5126 16:37:08.297054 match AC timing 9
5127 16:37:08.303121 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5128 16:37:08.306809 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5129 16:37:08.309463 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5130 16:37:08.316336 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5131 16:37:08.319798 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5132 16:37:08.320229 ==
5133 16:37:08.322597 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 16:37:08.326058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 16:37:08.329660 ==
5136 16:37:08.332368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 16:37:08.339317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5138 16:37:08.342759 [CA 0] Center 37 (7~68) winsize 62
5139 16:37:08.346151 [CA 1] Center 37 (7~68) winsize 62
5140 16:37:08.348911 [CA 2] Center 34 (4~65) winsize 62
5141 16:37:08.352407 [CA 3] Center 35 (5~65) winsize 61
5142 16:37:08.355871 [CA 4] Center 34 (4~64) winsize 61
5143 16:37:08.358807 [CA 5] Center 33 (4~63) winsize 60
5144 16:37:08.359264
5145 16:37:08.362318 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5146 16:37:08.362781
5147 16:37:08.365633 [CATrainingPosCal] consider 1 rank data
5148 16:37:08.368851 u2DelayCellTimex100 = 270/100 ps
5149 16:37:08.372230 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 16:37:08.375454 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5151 16:37:08.378782 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5152 16:37:08.385143 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5153 16:37:08.388288 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5154 16:37:08.391534 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5155 16:37:08.392083
5156 16:37:08.394697 CA PerBit enable=1, Macro0, CA PI delay=33
5157 16:37:08.395078
5158 16:37:08.398102 [CBTSetCACLKResult] CA Dly = 33
5159 16:37:08.398584 CS Dly: 7 (0~38)
5160 16:37:08.401770 ==
5161 16:37:08.402422 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 16:37:08.408513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 16:37:08.409149 ==
5164 16:37:08.411353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5165 16:37:08.418323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5166 16:37:08.421667 [CA 0] Center 37 (7~68) winsize 62
5167 16:37:08.425039 [CA 1] Center 37 (7~68) winsize 62
5168 16:37:08.428661 [CA 2] Center 34 (4~65) winsize 62
5169 16:37:08.431911 [CA 3] Center 34 (4~65) winsize 62
5170 16:37:08.434733 [CA 4] Center 33 (3~64) winsize 62
5171 16:37:08.438289 [CA 5] Center 32 (2~63) winsize 62
5172 16:37:08.438955
5173 16:37:08.441733 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5174 16:37:08.442354
5175 16:37:08.444803 [CATrainingPosCal] consider 2 rank data
5176 16:37:08.448229 u2DelayCellTimex100 = 270/100 ps
5177 16:37:08.451685 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 16:37:08.457843 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 16:37:08.461241 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5180 16:37:08.464846 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5181 16:37:08.467763 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5182 16:37:08.471178 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5183 16:37:08.471414
5184 16:37:08.474684 CA PerBit enable=1, Macro0, CA PI delay=33
5185 16:37:08.474924
5186 16:37:08.477178 [CBTSetCACLKResult] CA Dly = 33
5187 16:37:08.480459 CS Dly: 7 (0~39)
5188 16:37:08.480567
5189 16:37:08.484378 ----->DramcWriteLeveling(PI) begin...
5190 16:37:08.484473 ==
5191 16:37:08.487071 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 16:37:08.490392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 16:37:08.490477 ==
5194 16:37:08.493894 Write leveling (Byte 0): 32 => 32
5195 16:37:08.497467 Write leveling (Byte 1): 29 => 29
5196 16:37:08.500758 DramcWriteLeveling(PI) end<-----
5197 16:37:08.500862
5198 16:37:08.500952 ==
5199 16:37:08.503907 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 16:37:08.507276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 16:37:08.507358 ==
5202 16:37:08.510539 [Gating] SW mode calibration
5203 16:37:08.516973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5204 16:37:08.523805 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5205 16:37:08.527151 0 14 0 | B1->B0 | 2322 3232 | 1 0 | (0 0) (1 1)
5206 16:37:08.530393 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5207 16:37:08.536625 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 16:37:08.540042 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 16:37:08.543414 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 16:37:08.550278 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 16:37:08.553492 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 16:37:08.557065 0 14 28 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5213 16:37:08.563199 0 15 0 | B1->B0 | 3232 2c2c | 0 0 | (1 0) (0 0)
5214 16:37:08.566663 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 16:37:08.570071 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 16:37:08.576366 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 16:37:08.579912 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 16:37:08.582659 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 16:37:08.589441 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 16:37:08.592613 0 15 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
5221 16:37:08.599322 1 0 0 | B1->B0 | 3030 4545 | 0 0 | (1 1) (0 0)
5222 16:37:08.602773 1 0 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5223 16:37:08.605672 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 16:37:08.612694 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 16:37:08.615930 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 16:37:08.619167 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 16:37:08.625626 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 16:37:08.628770 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5229 16:37:08.632409 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5230 16:37:08.635788 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5231 16:37:08.642005 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 16:37:08.645540 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 16:37:08.648929 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 16:37:08.655065 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 16:37:08.659138 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 16:37:08.661750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 16:37:08.668592 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 16:37:08.672081 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 16:37:08.678432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 16:37:08.681897 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 16:37:08.685414 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 16:37:08.688194 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 16:37:08.694856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 16:37:08.698289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5245 16:37:08.701492 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5246 16:37:08.704626 Total UI for P1: 0, mck2ui 16
5247 16:37:08.708116 best dqsien dly found for B0: ( 1, 2, 28)
5248 16:37:08.715069 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5249 16:37:08.718530 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 16:37:08.721317 Total UI for P1: 0, mck2ui 16
5251 16:37:08.724774 best dqsien dly found for B1: ( 1, 3, 2)
5252 16:37:08.728183 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5253 16:37:08.731499 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5254 16:37:08.731587
5255 16:37:08.734756 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5256 16:37:08.741251 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5257 16:37:08.741369 [Gating] SW calibration Done
5258 16:37:08.741463 ==
5259 16:37:08.744280 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 16:37:08.750951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 16:37:08.751047 ==
5262 16:37:08.751114 RX Vref Scan: 0
5263 16:37:08.751174
5264 16:37:08.754201 RX Vref 0 -> 0, step: 1
5265 16:37:08.754295
5266 16:37:08.757567 RX Delay -80 -> 252, step: 8
5267 16:37:08.761226 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5268 16:37:08.764464 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5269 16:37:08.767911 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5270 16:37:08.770731 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5271 16:37:08.777132 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5272 16:37:08.780751 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5273 16:37:08.784071 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5274 16:37:08.787571 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5275 16:37:08.790423 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5276 16:37:08.793998 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5277 16:37:08.801002 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5278 16:37:08.804190 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5279 16:37:08.807033 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5280 16:37:08.810463 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5281 16:37:08.816747 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5282 16:37:08.820126 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5283 16:37:08.820207 ==
5284 16:37:08.823474 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 16:37:08.827130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 16:37:08.827209 ==
5287 16:37:08.827272 DQS Delay:
5288 16:37:08.829919 DQS0 = 0, DQS1 = 0
5289 16:37:08.829998 DQM Delay:
5290 16:37:08.833557 DQM0 = 96, DQM1 = 86
5291 16:37:08.833636 DQ Delay:
5292 16:37:08.837106 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5293 16:37:08.839947 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5294 16:37:08.843269 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5295 16:37:08.846581 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5296 16:37:08.846687
5297 16:37:08.846777
5298 16:37:08.846863 ==
5299 16:37:08.849980 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 16:37:08.856508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 16:37:08.856591 ==
5302 16:37:08.856660
5303 16:37:08.856718
5304 16:37:08.856773 TX Vref Scan disable
5305 16:37:08.859696 == TX Byte 0 ==
5306 16:37:08.862881 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5307 16:37:08.869523 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5308 16:37:08.869629 == TX Byte 1 ==
5309 16:37:08.873037 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5310 16:37:08.879420 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5311 16:37:08.879556 ==
5312 16:37:08.882927 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 16:37:08.886406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 16:37:08.886515 ==
5315 16:37:08.886611
5316 16:37:08.886707
5317 16:37:08.889134 TX Vref Scan disable
5318 16:37:08.892677 == TX Byte 0 ==
5319 16:37:08.896317 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5320 16:37:08.899056 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5321 16:37:08.902760 == TX Byte 1 ==
5322 16:37:08.905503 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5323 16:37:08.909108 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5324 16:37:08.909273
5325 16:37:08.909408 [DATLAT]
5326 16:37:08.912536 Freq=933, CH0 RK0
5327 16:37:08.912618
5328 16:37:08.915423 DATLAT Default: 0xd
5329 16:37:08.915503 0, 0xFFFF, sum = 0
5330 16:37:08.918711 1, 0xFFFF, sum = 0
5331 16:37:08.918794 2, 0xFFFF, sum = 0
5332 16:37:08.922042 3, 0xFFFF, sum = 0
5333 16:37:08.922154 4, 0xFFFF, sum = 0
5334 16:37:08.925392 5, 0xFFFF, sum = 0
5335 16:37:08.925474 6, 0xFFFF, sum = 0
5336 16:37:08.928730 7, 0xFFFF, sum = 0
5337 16:37:08.928812 8, 0xFFFF, sum = 0
5338 16:37:08.932279 9, 0xFFFF, sum = 0
5339 16:37:08.932362 10, 0x0, sum = 1
5340 16:37:08.935881 11, 0x0, sum = 2
5341 16:37:08.935962 12, 0x0, sum = 3
5342 16:37:08.939168 13, 0x0, sum = 4
5343 16:37:08.939249 best_step = 11
5344 16:37:08.939313
5345 16:37:08.939372 ==
5346 16:37:08.942027 Dram Type= 6, Freq= 0, CH_0, rank 0
5347 16:37:08.945439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 16:37:08.948892 ==
5349 16:37:08.948975 RX Vref Scan: 1
5350 16:37:08.949040
5351 16:37:08.952362 RX Vref 0 -> 0, step: 1
5352 16:37:08.952436
5353 16:37:08.955620 RX Delay -61 -> 252, step: 4
5354 16:37:08.955690
5355 16:37:08.958973 Set Vref, RX VrefLevel [Byte0]: 56
5356 16:37:08.961607 [Byte1]: 50
5357 16:37:08.961705
5358 16:37:08.964871 Final RX Vref Byte 0 = 56 to rank0
5359 16:37:08.968754 Final RX Vref Byte 1 = 50 to rank0
5360 16:37:08.971778 Final RX Vref Byte 0 = 56 to rank1
5361 16:37:08.975048 Final RX Vref Byte 1 = 50 to rank1==
5362 16:37:08.978434 Dram Type= 6, Freq= 0, CH_0, rank 0
5363 16:37:08.981958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 16:37:08.982071 ==
5365 16:37:08.984720 DQS Delay:
5366 16:37:08.984831 DQS0 = 0, DQS1 = 0
5367 16:37:08.984927 DQM Delay:
5368 16:37:08.988305 DQM0 = 97, DQM1 = 85
5369 16:37:08.988415 DQ Delay:
5370 16:37:08.991212 DQ0 =96, DQ1 =100, DQ2 =94, DQ3 =94
5371 16:37:08.994658 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5372 16:37:08.998126 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5373 16:37:09.001639 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =90
5374 16:37:09.001744
5375 16:37:09.001840
5376 16:37:09.011221 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5377 16:37:09.014577 CH0 RK0: MR19=505, MR18=2C13
5378 16:37:09.020971 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5379 16:37:09.021075
5380 16:37:09.024264 ----->DramcWriteLeveling(PI) begin...
5381 16:37:09.024366 ==
5382 16:37:09.027522 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 16:37:09.030658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 16:37:09.030759 ==
5385 16:37:09.034484 Write leveling (Byte 0): 35 => 35
5386 16:37:09.037845 Write leveling (Byte 1): 33 => 33
5387 16:37:09.040566 DramcWriteLeveling(PI) end<-----
5388 16:37:09.040643
5389 16:37:09.040708 ==
5390 16:37:09.044051 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 16:37:09.047517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 16:37:09.047591 ==
5393 16:37:09.050458 [Gating] SW mode calibration
5394 16:37:09.057306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5395 16:37:09.064251 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5396 16:37:09.066955 0 14 0 | B1->B0 | 2828 3030 | 0 1 | (0 0) (0 0)
5397 16:37:09.070342 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 16:37:09.077085 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 16:37:09.080356 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 16:37:09.083667 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 16:37:09.090596 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 16:37:09.093439 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 16:37:09.097082 0 14 28 | B1->B0 | 3333 2a2a | 0 0 | (0 1) (0 0)
5404 16:37:09.103497 0 15 0 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (0 0)
5405 16:37:09.106949 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 16:37:09.110359 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 16:37:09.116673 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 16:37:09.119942 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 16:37:09.123432 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 16:37:09.129729 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 16:37:09.133239 0 15 28 | B1->B0 | 2424 3332 | 0 1 | (0 0) (0 0)
5412 16:37:09.136499 1 0 0 | B1->B0 | 4242 4545 | 0 0 | (1 1) (0 0)
5413 16:37:09.142860 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 16:37:09.146094 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 16:37:09.149436 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 16:37:09.156359 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 16:37:09.159959 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 16:37:09.162689 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 16:37:09.169601 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5420 16:37:09.172928 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5421 16:37:09.176118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 16:37:09.182706 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 16:37:09.186208 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 16:37:09.189562 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 16:37:09.196084 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 16:37:09.198924 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 16:37:09.202460 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 16:37:09.209316 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 16:37:09.212021 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 16:37:09.215412 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 16:37:09.222359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 16:37:09.225072 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 16:37:09.228463 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 16:37:09.235415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 16:37:09.238978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5436 16:37:09.241887 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5437 16:37:09.245231 Total UI for P1: 0, mck2ui 16
5438 16:37:09.248481 best dqsien dly found for B0: ( 1, 2, 28)
5439 16:37:09.255144 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 16:37:09.255228 Total UI for P1: 0, mck2ui 16
5441 16:37:09.261958 best dqsien dly found for B1: ( 1, 3, 0)
5442 16:37:09.265493 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5443 16:37:09.268162 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5444 16:37:09.268245
5445 16:37:09.271739 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5446 16:37:09.274535 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5447 16:37:09.278034 [Gating] SW calibration Done
5448 16:37:09.278116 ==
5449 16:37:09.281373 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 16:37:09.284689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 16:37:09.284782 ==
5452 16:37:09.288072 RX Vref Scan: 0
5453 16:37:09.288159
5454 16:37:09.288224 RX Vref 0 -> 0, step: 1
5455 16:37:09.291546
5456 16:37:09.291620 RX Delay -80 -> 252, step: 8
5457 16:37:09.297897 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5458 16:37:09.301066 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5459 16:37:09.304402 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5460 16:37:09.307840 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5461 16:37:09.311451 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5462 16:37:09.314301 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5463 16:37:09.321381 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5464 16:37:09.324171 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5465 16:37:09.327661 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5466 16:37:09.330853 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5467 16:37:09.334371 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5468 16:37:09.340422 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5469 16:37:09.343947 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5470 16:37:09.347537 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5471 16:37:09.350431 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5472 16:37:09.353809 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5473 16:37:09.353890 ==
5474 16:37:09.357138 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 16:37:09.364031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 16:37:09.364114 ==
5477 16:37:09.364178 DQS Delay:
5478 16:37:09.366727 DQS0 = 0, DQS1 = 0
5479 16:37:09.366808 DQM Delay:
5480 16:37:09.370190 DQM0 = 97, DQM1 = 87
5481 16:37:09.370284 DQ Delay:
5482 16:37:09.373595 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5483 16:37:09.377284 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5484 16:37:09.379983 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5485 16:37:09.383472 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5486 16:37:09.383553
5487 16:37:09.383616
5488 16:37:09.383674 ==
5489 16:37:09.387031 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 16:37:09.390394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 16:37:09.390475 ==
5492 16:37:09.390540
5493 16:37:09.390599
5494 16:37:09.393492 TX Vref Scan disable
5495 16:37:09.396408 == TX Byte 0 ==
5496 16:37:09.399920 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5497 16:37:09.403356 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5498 16:37:09.406047 == TX Byte 1 ==
5499 16:37:09.409410 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5500 16:37:09.413461 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5501 16:37:09.413542 ==
5502 16:37:09.416264 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 16:37:09.422650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 16:37:09.422731 ==
5505 16:37:09.422795
5506 16:37:09.422853
5507 16:37:09.422910 TX Vref Scan disable
5508 16:37:09.426791 == TX Byte 0 ==
5509 16:37:09.430322 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5510 16:37:09.436882 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5511 16:37:09.436964 == TX Byte 1 ==
5512 16:37:09.439844 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5513 16:37:09.446795 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5514 16:37:09.446878
5515 16:37:09.446941 [DATLAT]
5516 16:37:09.447000 Freq=933, CH0 RK1
5517 16:37:09.449589
5518 16:37:09.449669 DATLAT Default: 0xb
5519 16:37:09.453230 0, 0xFFFF, sum = 0
5520 16:37:09.453312 1, 0xFFFF, sum = 0
5521 16:37:09.456760 2, 0xFFFF, sum = 0
5522 16:37:09.456842 3, 0xFFFF, sum = 0
5523 16:37:09.459564 4, 0xFFFF, sum = 0
5524 16:37:09.459646 5, 0xFFFF, sum = 0
5525 16:37:09.462864 6, 0xFFFF, sum = 0
5526 16:37:09.462947 7, 0xFFFF, sum = 0
5527 16:37:09.466323 8, 0xFFFF, sum = 0
5528 16:37:09.466406 9, 0xFFFF, sum = 0
5529 16:37:09.469607 10, 0x0, sum = 1
5530 16:37:09.469689 11, 0x0, sum = 2
5531 16:37:09.473212 12, 0x0, sum = 3
5532 16:37:09.473294 13, 0x0, sum = 4
5533 16:37:09.475933 best_step = 11
5534 16:37:09.476017
5535 16:37:09.476082 ==
5536 16:37:09.479413 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 16:37:09.483025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 16:37:09.483121 ==
5539 16:37:09.485995 RX Vref Scan: 0
5540 16:37:09.486077
5541 16:37:09.486177 RX Vref 0 -> 0, step: 1
5542 16:37:09.486271
5543 16:37:09.489339 RX Delay -69 -> 252, step: 4
5544 16:37:09.496087 iDelay=203, Bit 0, Center 92 (3 ~ 182) 180
5545 16:37:09.499326 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5546 16:37:09.502592 iDelay=203, Bit 2, Center 92 (3 ~ 182) 180
5547 16:37:09.506108 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5548 16:37:09.508941 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5549 16:37:09.512522 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5550 16:37:09.519150 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5551 16:37:09.522526 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5552 16:37:09.525874 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5553 16:37:09.528609 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5554 16:37:09.531983 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5555 16:37:09.538873 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5556 16:37:09.541721 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5557 16:37:09.545252 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5558 16:37:09.548906 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5559 16:37:09.551846 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5560 16:37:09.555412 ==
5561 16:37:09.558147 Dram Type= 6, Freq= 0, CH_0, rank 1
5562 16:37:09.561852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 16:37:09.561954 ==
5564 16:37:09.562046 DQS Delay:
5565 16:37:09.565342 DQS0 = 0, DQS1 = 0
5566 16:37:09.565439 DQM Delay:
5567 16:37:09.568050 DQM0 = 96, DQM1 = 86
5568 16:37:09.568149 DQ Delay:
5569 16:37:09.571416 DQ0 =92, DQ1 =98, DQ2 =92, DQ3 =94
5570 16:37:09.574892 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5571 16:37:09.578243 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5572 16:37:09.581696 DQ12 =94, DQ13 =94, DQ14 =94, DQ15 =94
5573 16:37:09.581778
5574 16:37:09.581843
5575 16:37:09.588171 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5576 16:37:09.591028 CH0 RK1: MR19=504, MR18=25F6
5577 16:37:09.597922 CH0_RK1: MR19=0x504, MR18=0x25F6, DQSOSC=410, MR23=63, INC=64, DEC=42
5578 16:37:09.601431 [RxdqsGatingPostProcess] freq 933
5579 16:37:09.607692 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5580 16:37:09.611265 best DQS0 dly(2T, 0.5T) = (0, 10)
5581 16:37:09.614027 best DQS1 dly(2T, 0.5T) = (0, 11)
5582 16:37:09.617493 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5583 16:37:09.621178 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5584 16:37:09.621286 best DQS0 dly(2T, 0.5T) = (0, 10)
5585 16:37:09.624552 best DQS1 dly(2T, 0.5T) = (0, 11)
5586 16:37:09.627283 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5587 16:37:09.631199 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5588 16:37:09.633875 Pre-setting of DQS Precalculation
5589 16:37:09.640963 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5590 16:37:09.641080 ==
5591 16:37:09.644450 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 16:37:09.647126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 16:37:09.647234 ==
5594 16:37:09.654181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 16:37:09.660910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5596 16:37:09.664292 [CA 0] Center 36 (6~67) winsize 62
5597 16:37:09.667280 [CA 1] Center 36 (6~67) winsize 62
5598 16:37:09.670563 [CA 2] Center 34 (4~64) winsize 61
5599 16:37:09.673945 [CA 3] Center 33 (3~64) winsize 62
5600 16:37:09.676953 [CA 4] Center 34 (4~65) winsize 62
5601 16:37:09.680333 [CA 5] Center 33 (3~64) winsize 62
5602 16:37:09.680436
5603 16:37:09.683632 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5604 16:37:09.683741
5605 16:37:09.686731 [CATrainingPosCal] consider 1 rank data
5606 16:37:09.690453 u2DelayCellTimex100 = 270/100 ps
5607 16:37:09.693272 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 16:37:09.696769 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5609 16:37:09.700192 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5610 16:37:09.703715 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5611 16:37:09.706616 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5612 16:37:09.710290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5613 16:37:09.710398
5614 16:37:09.716424 CA PerBit enable=1, Macro0, CA PI delay=33
5615 16:37:09.716541
5616 16:37:09.719959 [CBTSetCACLKResult] CA Dly = 33
5617 16:37:09.720072 CS Dly: 5 (0~36)
5618 16:37:09.720181 ==
5619 16:37:09.722826 Dram Type= 6, Freq= 0, CH_1, rank 1
5620 16:37:09.726437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 16:37:09.726542 ==
5622 16:37:09.732637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5623 16:37:09.739545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5624 16:37:09.743070 [CA 0] Center 36 (6~67) winsize 62
5625 16:37:09.746183 [CA 1] Center 36 (6~67) winsize 62
5626 16:37:09.749737 [CA 2] Center 34 (3~65) winsize 63
5627 16:37:09.752449 [CA 3] Center 33 (3~64) winsize 62
5628 16:37:09.756284 [CA 4] Center 34 (3~65) winsize 63
5629 16:37:09.759237 [CA 5] Center 33 (3~64) winsize 62
5630 16:37:09.759347
5631 16:37:09.762676 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5632 16:37:09.762786
5633 16:37:09.765532 [CATrainingPosCal] consider 2 rank data
5634 16:37:09.769150 u2DelayCellTimex100 = 270/100 ps
5635 16:37:09.772768 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5636 16:37:09.775717 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5637 16:37:09.779179 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5638 16:37:09.781999 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5639 16:37:09.788968 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5640 16:37:09.792310 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5641 16:37:09.792417
5642 16:37:09.795749 CA PerBit enable=1, Macro0, CA PI delay=33
5643 16:37:09.795856
5644 16:37:09.798976 [CBTSetCACLKResult] CA Dly = 33
5645 16:37:09.799080 CS Dly: 6 (0~39)
5646 16:37:09.799172
5647 16:37:09.802387 ----->DramcWriteLeveling(PI) begin...
5648 16:37:09.802497 ==
5649 16:37:09.805809 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 16:37:09.812189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 16:37:09.812300 ==
5652 16:37:09.815736 Write leveling (Byte 0): 23 => 23
5653 16:37:09.818480 Write leveling (Byte 1): 31 => 31
5654 16:37:09.818591 DramcWriteLeveling(PI) end<-----
5655 16:37:09.818685
5656 16:37:09.822072 ==
5657 16:37:09.825662 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 16:37:09.828395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 16:37:09.828497 ==
5660 16:37:09.831934 [Gating] SW mode calibration
5661 16:37:09.839021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5662 16:37:09.841784 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5663 16:37:09.848730 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5664 16:37:09.852081 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 16:37:09.854855 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 16:37:09.861410 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 16:37:09.864893 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 16:37:09.868577 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5669 16:37:09.874920 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 0)
5670 16:37:09.878381 0 14 28 | B1->B0 | 2f2f 2b2b | 1 1 | (1 0) (1 0)
5671 16:37:09.881200 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 16:37:09.888095 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 16:37:09.890970 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 16:37:09.894442 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 16:37:09.900809 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 16:37:09.904707 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 16:37:09.907784 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5678 16:37:09.914665 0 15 28 | B1->B0 | 3232 3b3b | 0 0 | (1 1) (1 1)
5679 16:37:09.917449 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5680 16:37:09.920980 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 16:37:09.927425 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 16:37:09.931023 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 16:37:09.933931 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 16:37:09.941040 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 16:37:09.943898 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5686 16:37:09.947446 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5687 16:37:09.953700 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5688 16:37:09.957181 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 16:37:09.960630 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 16:37:09.967490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 16:37:09.970268 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 16:37:09.973888 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 16:37:09.980198 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 16:37:09.983452 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 16:37:09.986760 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 16:37:09.993768 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 16:37:09.996687 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 16:37:10.000192 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 16:37:10.007161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 16:37:10.009834 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 16:37:10.013096 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5702 16:37:10.019778 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5703 16:37:10.023212 Total UI for P1: 0, mck2ui 16
5704 16:37:10.026467 best dqsien dly found for B0: ( 1, 2, 24)
5705 16:37:10.030003 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 16:37:10.033422 Total UI for P1: 0, mck2ui 16
5707 16:37:10.036405 best dqsien dly found for B1: ( 1, 2, 26)
5708 16:37:10.039935 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5709 16:37:10.042713 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5710 16:37:10.042884
5711 16:37:10.046358 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5712 16:37:10.049698 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5713 16:37:10.053152 [Gating] SW calibration Done
5714 16:37:10.053306 ==
5715 16:37:10.055891 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 16:37:10.063127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 16:37:10.063303 ==
5718 16:37:10.063404 RX Vref Scan: 0
5719 16:37:10.063498
5720 16:37:10.065878 RX Vref 0 -> 0, step: 1
5721 16:37:10.065977
5722 16:37:10.069138 RX Delay -80 -> 252, step: 8
5723 16:37:10.072380 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5724 16:37:10.075830 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5725 16:37:10.079263 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5726 16:37:10.082655 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5727 16:37:10.089015 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5728 16:37:10.092439 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5729 16:37:10.096428 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5730 16:37:10.099200 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5731 16:37:10.102033 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5732 16:37:10.105609 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5733 16:37:10.112055 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5734 16:37:10.115673 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5735 16:37:10.118556 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5736 16:37:10.121898 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5737 16:37:10.128781 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5738 16:37:10.132121 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5739 16:37:10.132225 ==
5740 16:37:10.135324 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 16:37:10.138675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 16:37:10.138784 ==
5743 16:37:10.138878 DQS Delay:
5744 16:37:10.141602 DQS0 = 0, DQS1 = 0
5745 16:37:10.141703 DQM Delay:
5746 16:37:10.145129 DQM0 = 101, DQM1 = 90
5747 16:37:10.145238 DQ Delay:
5748 16:37:10.148727 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5749 16:37:10.151423 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5750 16:37:10.154999 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5751 16:37:10.158651 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =103
5752 16:37:10.158755
5753 16:37:10.158847
5754 16:37:10.158942 ==
5755 16:37:10.161473 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 16:37:10.168427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 16:37:10.168538 ==
5758 16:37:10.168632
5759 16:37:10.168723
5760 16:37:10.168819 TX Vref Scan disable
5761 16:37:10.172028 == TX Byte 0 ==
5762 16:37:10.175445 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5763 16:37:10.181551 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5764 16:37:10.181660 == TX Byte 1 ==
5765 16:37:10.184992 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5766 16:37:10.191645 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5767 16:37:10.191753 ==
5768 16:37:10.195099 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 16:37:10.197918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 16:37:10.198022 ==
5771 16:37:10.198114
5772 16:37:10.198221
5773 16:37:10.201467 TX Vref Scan disable
5774 16:37:10.205045 == TX Byte 0 ==
5775 16:37:10.207936 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5776 16:37:10.211472 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5777 16:37:10.214314 == TX Byte 1 ==
5778 16:37:10.217816 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5779 16:37:10.221401 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5780 16:37:10.221504
5781 16:37:10.221601 [DATLAT]
5782 16:37:10.224227 Freq=933, CH1 RK0
5783 16:37:10.224326
5784 16:37:10.227637 DATLAT Default: 0xd
5785 16:37:10.227737 0, 0xFFFF, sum = 0
5786 16:37:10.231126 1, 0xFFFF, sum = 0
5787 16:37:10.231228 2, 0xFFFF, sum = 0
5788 16:37:10.234508 3, 0xFFFF, sum = 0
5789 16:37:10.234614 4, 0xFFFF, sum = 0
5790 16:37:10.238036 5, 0xFFFF, sum = 0
5791 16:37:10.238141 6, 0xFFFF, sum = 0
5792 16:37:10.241336 7, 0xFFFF, sum = 0
5793 16:37:10.241439 8, 0xFFFF, sum = 0
5794 16:37:10.244536 9, 0xFFFF, sum = 0
5795 16:37:10.244639 10, 0x0, sum = 1
5796 16:37:10.247855 11, 0x0, sum = 2
5797 16:37:10.247961 12, 0x0, sum = 3
5798 16:37:10.250638 13, 0x0, sum = 4
5799 16:37:10.250739 best_step = 11
5800 16:37:10.250829
5801 16:37:10.250918 ==
5802 16:37:10.254244 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 16:37:10.257721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 16:37:10.261313 ==
5805 16:37:10.261405 RX Vref Scan: 1
5806 16:37:10.261485
5807 16:37:10.264026 RX Vref 0 -> 0, step: 1
5808 16:37:10.264108
5809 16:37:10.267475 RX Delay -61 -> 252, step: 4
5810 16:37:10.267557
5811 16:37:10.271087 Set Vref, RX VrefLevel [Byte0]: 50
5812 16:37:10.273872 [Byte1]: 59
5813 16:37:10.273954
5814 16:37:10.277413 Final RX Vref Byte 0 = 50 to rank0
5815 16:37:10.280381 Final RX Vref Byte 1 = 59 to rank0
5816 16:37:10.283791 Final RX Vref Byte 0 = 50 to rank1
5817 16:37:10.287311 Final RX Vref Byte 1 = 59 to rank1==
5818 16:37:10.290739 Dram Type= 6, Freq= 0, CH_1, rank 0
5819 16:37:10.293501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 16:37:10.293583 ==
5821 16:37:10.296902 DQS Delay:
5822 16:37:10.296984 DQS0 = 0, DQS1 = 0
5823 16:37:10.297048 DQM Delay:
5824 16:37:10.300174 DQM0 = 100, DQM1 = 93
5825 16:37:10.300256 DQ Delay:
5826 16:37:10.303521 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5827 16:37:10.307114 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =96
5828 16:37:10.310037 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =86
5829 16:37:10.313619 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5830 16:37:10.313730
5831 16:37:10.317032
5832 16:37:10.323597 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5833 16:37:10.327067 CH1 RK0: MR19=505, MR18=1E0D
5834 16:37:10.333296 CH1_RK0: MR19=0x505, MR18=0x1E0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5835 16:37:10.333381
5836 16:37:10.337004 ----->DramcWriteLeveling(PI) begin...
5837 16:37:10.337088 ==
5838 16:37:10.339829 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 16:37:10.343302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 16:37:10.343420 ==
5841 16:37:10.346216 Write leveling (Byte 0): 24 => 24
5842 16:37:10.349641 Write leveling (Byte 1): 27 => 27
5843 16:37:10.352970 DramcWriteLeveling(PI) end<-----
5844 16:37:10.353051
5845 16:37:10.353114 ==
5846 16:37:10.356410 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 16:37:10.359561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 16:37:10.359644 ==
5849 16:37:10.362913 [Gating] SW mode calibration
5850 16:37:10.369740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5851 16:37:10.376172 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5852 16:37:10.379808 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 16:37:10.386124 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 16:37:10.389624 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 16:37:10.392373 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 16:37:10.399363 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 16:37:10.402192 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5858 16:37:10.405558 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5859 16:37:10.412271 0 14 28 | B1->B0 | 2c2c 2f2f | 0 0 | (1 1) (0 0)
5860 16:37:10.415895 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5861 16:37:10.418624 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 16:37:10.425657 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 16:37:10.429219 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 16:37:10.432023 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 16:37:10.439039 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5866 16:37:10.442363 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5867 16:37:10.445161 0 15 28 | B1->B0 | 3a3a 3131 | 1 1 | (0 0) (0 0)
5868 16:37:10.452112 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 16:37:10.455564 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 16:37:10.458477 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 16:37:10.465412 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 16:37:10.468656 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 16:37:10.471728 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 16:37:10.478025 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5875 16:37:10.481589 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5876 16:37:10.484542 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 16:37:10.491765 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 16:37:10.495396 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 16:37:10.498046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 16:37:10.501465 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 16:37:10.507993 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 16:37:10.511321 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 16:37:10.514662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 16:37:10.521394 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 16:37:10.524676 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 16:37:10.527673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 16:37:10.534896 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 16:37:10.537758 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 16:37:10.541335 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 16:37:10.547464 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5891 16:37:10.551010 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5892 16:37:10.554494 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 16:37:10.557427 Total UI for P1: 0, mck2ui 16
5894 16:37:10.560834 best dqsien dly found for B0: ( 1, 2, 28)
5895 16:37:10.564319 Total UI for P1: 0, mck2ui 16
5896 16:37:10.567307 best dqsien dly found for B1: ( 1, 2, 26)
5897 16:37:10.570816 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5898 16:37:10.577549 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5899 16:37:10.577652
5900 16:37:10.580839 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5901 16:37:10.584150 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5902 16:37:10.587523 [Gating] SW calibration Done
5903 16:37:10.587624 ==
5904 16:37:10.590430 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 16:37:10.594006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 16:37:10.594107 ==
5907 16:37:10.594207 RX Vref Scan: 0
5908 16:37:10.597720
5909 16:37:10.597812 RX Vref 0 -> 0, step: 1
5910 16:37:10.597901
5911 16:37:10.600606 RX Delay -80 -> 252, step: 8
5912 16:37:10.603924 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5913 16:37:10.606844 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5914 16:37:10.613534 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5915 16:37:10.616903 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5916 16:37:10.620509 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5917 16:37:10.623844 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5918 16:37:10.626438 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5919 16:37:10.629798 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5920 16:37:10.636475 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5921 16:37:10.639923 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5922 16:37:10.643464 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5923 16:37:10.647062 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5924 16:37:10.649860 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5925 16:37:10.656828 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5926 16:37:10.659507 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5927 16:37:10.663110 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5928 16:37:10.663210 ==
5929 16:37:10.666683 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 16:37:10.669378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 16:37:10.669475 ==
5932 16:37:10.672975 DQS Delay:
5933 16:37:10.673073 DQS0 = 0, DQS1 = 0
5934 16:37:10.676379 DQM Delay:
5935 16:37:10.676482 DQM0 = 100, DQM1 = 91
5936 16:37:10.676573 DQ Delay:
5937 16:37:10.679788 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5938 16:37:10.683270 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =95
5939 16:37:10.686060 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5940 16:37:10.689545 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5941 16:37:10.692712
5942 16:37:10.692818
5943 16:37:10.692910 ==
5944 16:37:10.696276 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 16:37:10.699844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 16:37:10.699948 ==
5947 16:37:10.700042
5948 16:37:10.700140
5949 16:37:10.702611 TX Vref Scan disable
5950 16:37:10.702715 == TX Byte 0 ==
5951 16:37:10.709694 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5952 16:37:10.716994 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5953 16:37:10.717113 == TX Byte 1 ==
5954 16:37:10.719333 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5955 16:37:10.722533 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5956 16:37:10.722637 ==
5957 16:37:10.725757 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 16:37:10.729097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 16:37:10.729203 ==
5960 16:37:10.729296
5961 16:37:10.729387
5962 16:37:10.732504 TX Vref Scan disable
5963 16:37:10.735857 == TX Byte 0 ==
5964 16:37:10.739302 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5965 16:37:10.742544 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5966 16:37:10.745886 == TX Byte 1 ==
5967 16:37:10.748851 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5968 16:37:10.752284 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5969 16:37:10.752385
5970 16:37:10.755649 [DATLAT]
5971 16:37:10.755752 Freq=933, CH1 RK1
5972 16:37:10.755854
5973 16:37:10.758462 DATLAT Default: 0xb
5974 16:37:10.758570 0, 0xFFFF, sum = 0
5975 16:37:10.761919 1, 0xFFFF, sum = 0
5976 16:37:10.762031 2, 0xFFFF, sum = 0
5977 16:37:10.765380 3, 0xFFFF, sum = 0
5978 16:37:10.765492 4, 0xFFFF, sum = 0
5979 16:37:10.768866 5, 0xFFFF, sum = 0
5980 16:37:10.772202 6, 0xFFFF, sum = 0
5981 16:37:10.772305 7, 0xFFFF, sum = 0
5982 16:37:10.775553 8, 0xFFFF, sum = 0
5983 16:37:10.775656 9, 0xFFFF, sum = 0
5984 16:37:10.778382 10, 0x0, sum = 1
5985 16:37:10.778496 11, 0x0, sum = 2
5986 16:37:10.781808 12, 0x0, sum = 3
5987 16:37:10.781912 13, 0x0, sum = 4
5988 16:37:10.782005 best_step = 11
5989 16:37:10.782093
5990 16:37:10.785129 ==
5991 16:37:10.788596 Dram Type= 6, Freq= 0, CH_1, rank 1
5992 16:37:10.791438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5993 16:37:10.791543 ==
5994 16:37:10.791636 RX Vref Scan: 0
5995 16:37:10.791724
5996 16:37:10.794864 RX Vref 0 -> 0, step: 1
5997 16:37:10.794968
5998 16:37:10.798233 RX Delay -61 -> 252, step: 4
5999 16:37:10.804882 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6000 16:37:10.808215 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6001 16:37:10.811703 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6002 16:37:10.814535 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
6003 16:37:10.818096 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6004 16:37:10.821565 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6005 16:37:10.827630 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6006 16:37:10.831560 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6007 16:37:10.834184 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6008 16:37:10.837532 iDelay=207, Bit 9, Center 86 (-1 ~ 174) 176
6009 16:37:10.840890 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6010 16:37:10.844206 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6011 16:37:10.850942 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6012 16:37:10.854402 iDelay=207, Bit 13, Center 104 (15 ~ 194) 180
6013 16:37:10.857249 iDelay=207, Bit 14, Center 104 (15 ~ 194) 180
6014 16:37:10.860560 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6015 16:37:10.863904 ==
6016 16:37:10.864009 Dram Type= 6, Freq= 0, CH_1, rank 1
6017 16:37:10.870807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6018 16:37:10.870909 ==
6019 16:37:10.870999 DQS Delay:
6020 16:37:10.874107 DQS0 = 0, DQS1 = 0
6021 16:37:10.874231 DQM Delay:
6022 16:37:10.877443 DQM0 = 100, DQM1 = 95
6023 16:37:10.877542 DQ Delay:
6024 16:37:10.880332 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =96
6025 16:37:10.883719 DQ4 =98, DQ5 =110, DQ6 =116, DQ7 =98
6026 16:37:10.887089 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
6027 16:37:10.890452 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =104
6028 16:37:10.890529
6029 16:37:10.890592
6030 16:37:10.896884 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6031 16:37:10.900352 CH1 RK1: MR19=505, MR18=701
6032 16:37:10.906783 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
6033 16:37:10.910012 [RxdqsGatingPostProcess] freq 933
6034 16:37:10.916695 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6035 16:37:10.920237 best DQS0 dly(2T, 0.5T) = (0, 10)
6036 16:37:10.923631 best DQS1 dly(2T, 0.5T) = (0, 10)
6037 16:37:10.926441 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6038 16:37:10.929802 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6039 16:37:10.929908 best DQS0 dly(2T, 0.5T) = (0, 10)
6040 16:37:10.933209 best DQS1 dly(2T, 0.5T) = (0, 10)
6041 16:37:10.936857 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6042 16:37:10.940272 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6043 16:37:10.943558 Pre-setting of DQS Precalculation
6044 16:37:10.949949 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6045 16:37:10.956402 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6046 16:37:10.963195 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6047 16:37:10.963327
6048 16:37:10.963430
6049 16:37:10.966063 [Calibration Summary] 1866 Mbps
6050 16:37:10.966182 CH 0, Rank 0
6051 16:37:10.969394 SW Impedance : PASS
6052 16:37:10.972752 DUTY Scan : NO K
6053 16:37:10.972859 ZQ Calibration : PASS
6054 16:37:10.976262 Jitter Meter : NO K
6055 16:37:10.979734 CBT Training : PASS
6056 16:37:10.979853 Write leveling : PASS
6057 16:37:10.983237 RX DQS gating : PASS
6058 16:37:10.985934 RX DQ/DQS(RDDQC) : PASS
6059 16:37:10.986048 TX DQ/DQS : PASS
6060 16:37:10.989410 RX DATLAT : PASS
6061 16:37:10.992710 RX DQ/DQS(Engine): PASS
6062 16:37:10.992820 TX OE : NO K
6063 16:37:10.995982 All Pass.
6064 16:37:10.996093
6065 16:37:10.996188 CH 0, Rank 1
6066 16:37:10.999535 SW Impedance : PASS
6067 16:37:10.999640 DUTY Scan : NO K
6068 16:37:11.002995 ZQ Calibration : PASS
6069 16:37:11.006458 Jitter Meter : NO K
6070 16:37:11.006573 CBT Training : PASS
6071 16:37:11.009252 Write leveling : PASS
6072 16:37:11.012546 RX DQS gating : PASS
6073 16:37:11.012702 RX DQ/DQS(RDDQC) : PASS
6074 16:37:11.016019 TX DQ/DQS : PASS
6075 16:37:11.019402 RX DATLAT : PASS
6076 16:37:11.019581 RX DQ/DQS(Engine): PASS
6077 16:37:11.022730 TX OE : NO K
6078 16:37:11.022894 All Pass.
6079 16:37:11.022995
6080 16:37:11.025581 CH 1, Rank 0
6081 16:37:11.025707 SW Impedance : PASS
6082 16:37:11.029148 DUTY Scan : NO K
6083 16:37:11.029302 ZQ Calibration : PASS
6084 16:37:11.032486 Jitter Meter : NO K
6085 16:37:11.035907 CBT Training : PASS
6086 16:37:11.036087 Write leveling : PASS
6087 16:37:11.038663 RX DQS gating : PASS
6088 16:37:11.042183 RX DQ/DQS(RDDQC) : PASS
6089 16:37:11.042334 TX DQ/DQS : PASS
6090 16:37:11.045547 RX DATLAT : PASS
6091 16:37:11.048982 RX DQ/DQS(Engine): PASS
6092 16:37:11.049133 TX OE : NO K
6093 16:37:11.052383 All Pass.
6094 16:37:11.052533
6095 16:37:11.052634 CH 1, Rank 1
6096 16:37:11.055656 SW Impedance : PASS
6097 16:37:11.055797 DUTY Scan : NO K
6098 16:37:11.058894 ZQ Calibration : PASS
6099 16:37:11.062305 Jitter Meter : NO K
6100 16:37:11.062496 CBT Training : PASS
6101 16:37:11.065539 Write leveling : PASS
6102 16:37:11.068431 RX DQS gating : PASS
6103 16:37:11.068598 RX DQ/DQS(RDDQC) : PASS
6104 16:37:11.071803 TX DQ/DQS : PASS
6105 16:37:11.075036 RX DATLAT : PASS
6106 16:37:11.075159 RX DQ/DQS(Engine): PASS
6107 16:37:11.078540 TX OE : NO K
6108 16:37:11.078666 All Pass.
6109 16:37:11.078766
6110 16:37:11.081968 DramC Write-DBI off
6111 16:37:11.084898 PER_BANK_REFRESH: Hybrid Mode
6112 16:37:11.085004 TX_TRACKING: ON
6113 16:37:11.094569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6114 16:37:11.098481 [FAST_K] Save calibration result to emmc
6115 16:37:11.101126 dramc_set_vcore_voltage set vcore to 650000
6116 16:37:11.104607 Read voltage for 400, 6
6117 16:37:11.104726 Vio18 = 0
6118 16:37:11.104823 Vcore = 650000
6119 16:37:11.107966 Vdram = 0
6120 16:37:11.108086 Vddq = 0
6121 16:37:11.108185 Vmddr = 0
6122 16:37:11.115075 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6123 16:37:11.117719 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6124 16:37:11.121161 MEM_TYPE=3, freq_sel=20
6125 16:37:11.124638 sv_algorithm_assistance_LP4_800
6126 16:37:11.128111 ============ PULL DRAM RESETB DOWN ============
6127 16:37:11.130889 ========== PULL DRAM RESETB DOWN end =========
6128 16:37:11.137864 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6129 16:37:11.141423 ===================================
6130 16:37:11.144136 LPDDR4 DRAM CONFIGURATION
6131 16:37:11.147611 ===================================
6132 16:37:11.147717 EX_ROW_EN[0] = 0x0
6133 16:37:11.151125 EX_ROW_EN[1] = 0x0
6134 16:37:11.151226 LP4Y_EN = 0x0
6135 16:37:11.153907 WORK_FSP = 0x0
6136 16:37:11.154026 WL = 0x2
6137 16:37:11.157327 RL = 0x2
6138 16:37:11.157433 BL = 0x2
6139 16:37:11.160816 RPST = 0x0
6140 16:37:11.160914 RD_PRE = 0x0
6141 16:37:11.164146 WR_PRE = 0x1
6142 16:37:11.164250 WR_PST = 0x0
6143 16:37:11.167334 DBI_WR = 0x0
6144 16:37:11.170710 DBI_RD = 0x0
6145 16:37:11.170838 OTF = 0x1
6146 16:37:11.174000 ===================================
6147 16:37:11.177240 ===================================
6148 16:37:11.177337 ANA top config
6149 16:37:11.180710 ===================================
6150 16:37:11.184230 DLL_ASYNC_EN = 0
6151 16:37:11.187000 ALL_SLAVE_EN = 1
6152 16:37:11.190384 NEW_RANK_MODE = 1
6153 16:37:11.194024 DLL_IDLE_MODE = 1
6154 16:37:11.194146 LP45_APHY_COMB_EN = 1
6155 16:37:11.196978 TX_ODT_DIS = 1
6156 16:37:11.200353 NEW_8X_MODE = 1
6157 16:37:11.203716 ===================================
6158 16:37:11.206966 ===================================
6159 16:37:11.210549 data_rate = 800
6160 16:37:11.213610 CKR = 1
6161 16:37:11.217057 DQ_P2S_RATIO = 4
6162 16:37:11.220407 ===================================
6163 16:37:11.220541 CA_P2S_RATIO = 4
6164 16:37:11.223105 DQ_CA_OPEN = 0
6165 16:37:11.226456 DQ_SEMI_OPEN = 1
6166 16:37:11.230001 CA_SEMI_OPEN = 1
6167 16:37:11.233440 CA_FULL_RATE = 0
6168 16:37:11.236879 DQ_CKDIV4_EN = 0
6169 16:37:11.237007 CA_CKDIV4_EN = 1
6170 16:37:11.239471 CA_PREDIV_EN = 0
6171 16:37:11.242932 PH8_DLY = 0
6172 16:37:11.246432 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6173 16:37:11.249986 DQ_AAMCK_DIV = 0
6174 16:37:11.252650 CA_AAMCK_DIV = 0
6175 16:37:11.252779 CA_ADMCK_DIV = 4
6176 16:37:11.256041 DQ_TRACK_CA_EN = 0
6177 16:37:11.259278 CA_PICK = 800
6178 16:37:11.262568 CA_MCKIO = 400
6179 16:37:11.265962 MCKIO_SEMI = 400
6180 16:37:11.269286 PLL_FREQ = 3016
6181 16:37:11.272490 DQ_UI_PI_RATIO = 32
6182 16:37:11.275960 CA_UI_PI_RATIO = 32
6183 16:37:11.279260 ===================================
6184 16:37:11.282536 ===================================
6185 16:37:11.282625 memory_type:LPDDR4
6186 16:37:11.285842 GP_NUM : 10
6187 16:37:11.288845 SRAM_EN : 1
6188 16:37:11.288962 MD32_EN : 0
6189 16:37:11.292589 ===================================
6190 16:37:11.295383 [ANA_INIT] >>>>>>>>>>>>>>
6191 16:37:11.298861 <<<<<< [CONFIGURE PHASE]: ANA_TX
6192 16:37:11.302207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6193 16:37:11.305628 ===================================
6194 16:37:11.309165 data_rate = 800,PCW = 0X7400
6195 16:37:11.311854 ===================================
6196 16:37:11.315814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6197 16:37:11.318665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6198 16:37:11.331986 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6199 16:37:11.335348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6200 16:37:11.338702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6201 16:37:11.342099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6202 16:37:11.344883 [ANA_INIT] flow start
6203 16:37:11.348192 [ANA_INIT] PLL >>>>>>>>
6204 16:37:11.348294 [ANA_INIT] PLL <<<<<<<<
6205 16:37:11.351640 [ANA_INIT] MIDPI >>>>>>>>
6206 16:37:11.354986 [ANA_INIT] MIDPI <<<<<<<<
6207 16:37:11.355069 [ANA_INIT] DLL >>>>>>>>
6208 16:37:11.358478 [ANA_INIT] flow end
6209 16:37:11.361322 ============ LP4 DIFF to SE enter ============
6210 16:37:11.367843 ============ LP4 DIFF to SE exit ============
6211 16:37:11.367936 [ANA_INIT] <<<<<<<<<<<<<
6212 16:37:11.371253 [Flow] Enable top DCM control >>>>>
6213 16:37:11.374628 [Flow] Enable top DCM control <<<<<
6214 16:37:11.378111 Enable DLL master slave shuffle
6215 16:37:11.384910 ==============================================================
6216 16:37:11.385003 Gating Mode config
6217 16:37:11.391001 ==============================================================
6218 16:37:11.394389 Config description:
6219 16:37:11.404481 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6220 16:37:11.410622 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6221 16:37:11.413844 SELPH_MODE 0: By rank 1: By Phase
6222 16:37:11.420572 ==============================================================
6223 16:37:11.423870 GAT_TRACK_EN = 0
6224 16:37:11.427017 RX_GATING_MODE = 2
6225 16:37:11.427102 RX_GATING_TRACK_MODE = 2
6226 16:37:11.430417 SELPH_MODE = 1
6227 16:37:11.434290 PICG_EARLY_EN = 1
6228 16:37:11.437104 VALID_LAT_VALUE = 1
6229 16:37:11.443588 ==============================================================
6230 16:37:11.446989 Enter into Gating configuration >>>>
6231 16:37:11.450442 Exit from Gating configuration <<<<
6232 16:37:11.453913 Enter into DVFS_PRE_config >>>>>
6233 16:37:11.463353 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6234 16:37:11.466857 Exit from DVFS_PRE_config <<<<<
6235 16:37:11.470085 Enter into PICG configuration >>>>
6236 16:37:11.473536 Exit from PICG configuration <<<<
6237 16:37:11.476928 [RX_INPUT] configuration >>>>>
6238 16:37:11.480312 [RX_INPUT] configuration <<<<<
6239 16:37:11.483797 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6240 16:37:11.489962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6241 16:37:11.496902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 16:37:11.503117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 16:37:11.509591 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6244 16:37:11.512808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6245 16:37:11.519449 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6246 16:37:11.522739 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6247 16:37:11.526088 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6248 16:37:11.529346 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6249 16:37:11.536067 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6250 16:37:11.539205 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 16:37:11.542981 ===================================
6252 16:37:11.546379 LPDDR4 DRAM CONFIGURATION
6253 16:37:11.549726 ===================================
6254 16:37:11.549844 EX_ROW_EN[0] = 0x0
6255 16:37:11.552327 EX_ROW_EN[1] = 0x0
6256 16:37:11.552415 LP4Y_EN = 0x0
6257 16:37:11.555628 WORK_FSP = 0x0
6258 16:37:11.555706 WL = 0x2
6259 16:37:11.559099 RL = 0x2
6260 16:37:11.559180 BL = 0x2
6261 16:37:11.562298 RPST = 0x0
6262 16:37:11.565829 RD_PRE = 0x0
6263 16:37:11.565912 WR_PRE = 0x1
6264 16:37:11.569252 WR_PST = 0x0
6265 16:37:11.569329 DBI_WR = 0x0
6266 16:37:11.572532 DBI_RD = 0x0
6267 16:37:11.572612 OTF = 0x1
6268 16:37:11.575883 ===================================
6269 16:37:11.578665 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6270 16:37:11.585457 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6271 16:37:11.588950 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6272 16:37:11.591742 ===================================
6273 16:37:11.595044 LPDDR4 DRAM CONFIGURATION
6274 16:37:11.598454 ===================================
6275 16:37:11.598546 EX_ROW_EN[0] = 0x10
6276 16:37:11.601743 EX_ROW_EN[1] = 0x0
6277 16:37:11.601827 LP4Y_EN = 0x0
6278 16:37:11.605189 WORK_FSP = 0x0
6279 16:37:11.608497 WL = 0x2
6280 16:37:11.608580 RL = 0x2
6281 16:37:11.611827 BL = 0x2
6282 16:37:11.611925 RPST = 0x0
6283 16:37:11.615112 RD_PRE = 0x0
6284 16:37:11.615196 WR_PRE = 0x1
6285 16:37:11.618657 WR_PST = 0x0
6286 16:37:11.618741 DBI_WR = 0x0
6287 16:37:11.621762 DBI_RD = 0x0
6288 16:37:11.621846 OTF = 0x1
6289 16:37:11.624869 ===================================
6290 16:37:11.631630 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6291 16:37:11.635785 nWR fixed to 30
6292 16:37:11.639280 [ModeRegInit_LP4] CH0 RK0
6293 16:37:11.639367 [ModeRegInit_LP4] CH0 RK1
6294 16:37:11.642036 [ModeRegInit_LP4] CH1 RK0
6295 16:37:11.645473 [ModeRegInit_LP4] CH1 RK1
6296 16:37:11.645559 match AC timing 19
6297 16:37:11.652485 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6298 16:37:11.655763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6299 16:37:11.659143 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6300 16:37:11.665319 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6301 16:37:11.668638 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6302 16:37:11.668757 ==
6303 16:37:11.672044 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 16:37:11.675260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 16:37:11.675368 ==
6306 16:37:11.682053 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 16:37:11.688299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6308 16:37:11.691567 [CA 0] Center 36 (8~64) winsize 57
6309 16:37:11.695318 [CA 1] Center 36 (8~64) winsize 57
6310 16:37:11.698582 [CA 2] Center 36 (8~64) winsize 57
6311 16:37:11.701998 [CA 3] Center 36 (8~64) winsize 57
6312 16:37:11.704731 [CA 4] Center 36 (8~64) winsize 57
6313 16:37:11.708240 [CA 5] Center 36 (8~64) winsize 57
6314 16:37:11.708324
6315 16:37:11.711583 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6316 16:37:11.711667
6317 16:37:11.715176 [CATrainingPosCal] consider 1 rank data
6318 16:37:11.717900 u2DelayCellTimex100 = 270/100 ps
6319 16:37:11.721258 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 16:37:11.724718 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 16:37:11.728237 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 16:37:11.731509 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 16:37:11.734867 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 16:37:11.737991 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 16:37:11.738102
6326 16:37:11.741841 CA PerBit enable=1, Macro0, CA PI delay=36
6327 16:37:11.741923
6328 16:37:11.744559 [CBTSetCACLKResult] CA Dly = 36
6329 16:37:11.747992 CS Dly: 1 (0~32)
6330 16:37:11.748121 ==
6331 16:37:11.751447 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 16:37:11.754568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 16:37:11.754677 ==
6334 16:37:11.761252 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6335 16:37:11.768098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6336 16:37:11.770827 [CA 0] Center 36 (8~64) winsize 57
6337 16:37:11.774279 [CA 1] Center 36 (8~64) winsize 57
6338 16:37:11.777696 [CA 2] Center 36 (8~64) winsize 57
6339 16:37:11.777777 [CA 3] Center 36 (8~64) winsize 57
6340 16:37:11.780997 [CA 4] Center 36 (8~64) winsize 57
6341 16:37:11.784165 [CA 5] Center 36 (8~64) winsize 57
6342 16:37:11.784254
6343 16:37:11.791109 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6344 16:37:11.791194
6345 16:37:11.794503 [CATrainingPosCal] consider 2 rank data
6346 16:37:11.797210 u2DelayCellTimex100 = 270/100 ps
6347 16:37:11.800509 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 16:37:11.803959 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 16:37:11.807383 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 16:37:11.810780 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 16:37:11.814177 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 16:37:11.816929 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 16:37:11.817011
6354 16:37:11.820428 CA PerBit enable=1, Macro0, CA PI delay=36
6355 16:37:11.820509
6356 16:37:11.823623 [CBTSetCACLKResult] CA Dly = 36
6357 16:37:11.826974 CS Dly: 1 (0~32)
6358 16:37:11.827054
6359 16:37:11.830318 ----->DramcWriteLeveling(PI) begin...
6360 16:37:11.830400 ==
6361 16:37:11.833751 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 16:37:11.837236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 16:37:11.837329 ==
6364 16:37:11.840630 Write leveling (Byte 0): 40 => 8
6365 16:37:11.843437 Write leveling (Byte 1): 32 => 0
6366 16:37:11.846746 DramcWriteLeveling(PI) end<-----
6367 16:37:11.846819
6368 16:37:11.846879 ==
6369 16:37:11.849934 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 16:37:11.853238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 16:37:11.853323 ==
6372 16:37:11.856564 [Gating] SW mode calibration
6373 16:37:11.863176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6374 16:37:11.870239 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6375 16:37:11.873579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6376 16:37:11.879651 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6377 16:37:11.883007 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 16:37:11.886643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6379 16:37:11.893240 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 16:37:11.896081 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 16:37:11.899402 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 16:37:11.905971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6383 16:37:11.909354 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 16:37:11.912750 Total UI for P1: 0, mck2ui 16
6385 16:37:11.916120 best dqsien dly found for B0: ( 0, 14, 24)
6386 16:37:11.919616 Total UI for P1: 0, mck2ui 16
6387 16:37:11.922457 best dqsien dly found for B1: ( 0, 14, 24)
6388 16:37:11.926003 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6389 16:37:11.929213 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6390 16:37:11.929295
6391 16:37:11.932652 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6392 16:37:11.936041 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6393 16:37:11.938935 [Gating] SW calibration Done
6394 16:37:11.939019 ==
6395 16:37:11.942400 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 16:37:11.945789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 16:37:11.949046 ==
6398 16:37:11.949127 RX Vref Scan: 0
6399 16:37:11.949190
6400 16:37:11.952567 RX Vref 0 -> 0, step: 1
6401 16:37:11.952646
6402 16:37:11.955932 RX Delay -410 -> 252, step: 16
6403 16:37:11.959095 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6404 16:37:11.962200 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6405 16:37:11.965456 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6406 16:37:11.972107 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6407 16:37:11.975489 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6408 16:37:11.978629 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6409 16:37:11.985222 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6410 16:37:11.988742 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6411 16:37:11.991976 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6412 16:37:11.995312 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6413 16:37:12.001476 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6414 16:37:12.004861 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6415 16:37:12.008343 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6416 16:37:12.011508 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6417 16:37:12.018279 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6418 16:37:12.021095 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6419 16:37:12.021252 ==
6420 16:37:12.024549 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 16:37:12.028070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 16:37:12.028175 ==
6423 16:37:12.031333 DQS Delay:
6424 16:37:12.031441 DQS0 = 43, DQS1 = 59
6425 16:37:12.034820 DQM Delay:
6426 16:37:12.034968 DQM0 = 9, DQM1 = 11
6427 16:37:12.035070 DQ Delay:
6428 16:37:12.037440 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6429 16:37:12.040794 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6430 16:37:12.044342 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6431 16:37:12.047723 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6432 16:37:12.047802
6433 16:37:12.047863
6434 16:37:12.047921 ==
6435 16:37:12.051196 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 16:37:12.058022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 16:37:12.058133 ==
6438 16:37:12.058219
6439 16:37:12.058286
6440 16:37:12.058350 TX Vref Scan disable
6441 16:37:12.060669 == TX Byte 0 ==
6442 16:37:12.064024 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6443 16:37:12.067334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6444 16:37:12.070579 == TX Byte 1 ==
6445 16:37:12.074275 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6446 16:37:12.077367 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6447 16:37:12.080867 ==
6448 16:37:12.084188 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 16:37:12.087340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 16:37:12.087424 ==
6451 16:37:12.087488
6452 16:37:12.087547
6453 16:37:12.090624 TX Vref Scan disable
6454 16:37:12.090724 == TX Byte 0 ==
6455 16:37:12.093918 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6456 16:37:12.100804 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6457 16:37:12.100918 == TX Byte 1 ==
6458 16:37:12.103957 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6459 16:37:12.110669 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6460 16:37:12.110763
6461 16:37:12.110841 [DATLAT]
6462 16:37:12.110932 Freq=400, CH0 RK0
6463 16:37:12.111019
6464 16:37:12.114038 DATLAT Default: 0xf
6465 16:37:12.117393 0, 0xFFFF, sum = 0
6466 16:37:12.117490 1, 0xFFFF, sum = 0
6467 16:37:12.120792 2, 0xFFFF, sum = 0
6468 16:37:12.120877 3, 0xFFFF, sum = 0
6469 16:37:12.123616 4, 0xFFFF, sum = 0
6470 16:37:12.123692 5, 0xFFFF, sum = 0
6471 16:37:12.127014 6, 0xFFFF, sum = 0
6472 16:37:12.127098 7, 0xFFFF, sum = 0
6473 16:37:12.130414 8, 0xFFFF, sum = 0
6474 16:37:12.130508 9, 0xFFFF, sum = 0
6475 16:37:12.133881 10, 0xFFFF, sum = 0
6476 16:37:12.133997 11, 0xFFFF, sum = 0
6477 16:37:12.136600 12, 0xFFFF, sum = 0
6478 16:37:12.136683 13, 0x0, sum = 1
6479 16:37:12.139966 14, 0x0, sum = 2
6480 16:37:12.140050 15, 0x0, sum = 3
6481 16:37:12.143406 16, 0x0, sum = 4
6482 16:37:12.143517 best_step = 14
6483 16:37:12.143607
6484 16:37:12.143692 ==
6485 16:37:12.146797 Dram Type= 6, Freq= 0, CH_0, rank 0
6486 16:37:12.153613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 16:37:12.153720 ==
6488 16:37:12.153819 RX Vref Scan: 1
6489 16:37:12.153916
6490 16:37:12.156444 RX Vref 0 -> 0, step: 1
6491 16:37:12.156546
6492 16:37:12.159892 RX Delay -359 -> 252, step: 8
6493 16:37:12.159966
6494 16:37:12.163367 Set Vref, RX VrefLevel [Byte0]: 56
6495 16:37:12.166629 [Byte1]: 50
6496 16:37:12.166702
6497 16:37:12.170099 Final RX Vref Byte 0 = 56 to rank0
6498 16:37:12.172935 Final RX Vref Byte 1 = 50 to rank0
6499 16:37:12.176328 Final RX Vref Byte 0 = 56 to rank1
6500 16:37:12.179593 Final RX Vref Byte 1 = 50 to rank1==
6501 16:37:12.182876 Dram Type= 6, Freq= 0, CH_0, rank 0
6502 16:37:12.189738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 16:37:12.189821 ==
6504 16:37:12.189885 DQS Delay:
6505 16:37:12.193090 DQS0 = 48, DQS1 = 60
6506 16:37:12.193164 DQM Delay:
6507 16:37:12.193224 DQM0 = 11, DQM1 = 12
6508 16:37:12.196286 DQ Delay:
6509 16:37:12.199350 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6510 16:37:12.202507 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6511 16:37:12.202583 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6512 16:37:12.205823 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6513 16:37:12.209162
6514 16:37:12.209261
6515 16:37:12.215986 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6516 16:37:12.219395 CH0 RK0: MR19=C0C, MR18=BE81
6517 16:37:12.225399 CH0_RK0: MR19=0xC0C, MR18=0xBE81, DQSOSC=386, MR23=63, INC=396, DEC=264
6518 16:37:12.225482 ==
6519 16:37:12.228938 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 16:37:12.232380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 16:37:12.232490 ==
6522 16:37:12.235210 [Gating] SW mode calibration
6523 16:37:12.241973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6524 16:37:12.248550 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6525 16:37:12.252063 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6526 16:37:12.255447 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6527 16:37:12.261505 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 16:37:12.264940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6529 16:37:12.268309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 16:37:12.275009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 16:37:12.278433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 16:37:12.281732 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6533 16:37:12.288327 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 16:37:12.291108 Total UI for P1: 0, mck2ui 16
6535 16:37:12.294925 best dqsien dly found for B0: ( 0, 14, 24)
6536 16:37:12.297950 Total UI for P1: 0, mck2ui 16
6537 16:37:12.301116 best dqsien dly found for B1: ( 0, 14, 24)
6538 16:37:12.304473 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6539 16:37:12.307940 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6540 16:37:12.308017
6541 16:37:12.311071 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6542 16:37:12.314787 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6543 16:37:12.317899 [Gating] SW calibration Done
6544 16:37:12.318001 ==
6545 16:37:12.321009 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 16:37:12.324145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 16:37:12.324244 ==
6548 16:37:12.327405 RX Vref Scan: 0
6549 16:37:12.327505
6550 16:37:12.330829 RX Vref 0 -> 0, step: 1
6551 16:37:12.330902
6552 16:37:12.330962 RX Delay -410 -> 252, step: 16
6553 16:37:12.337648 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6554 16:37:12.341073 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6555 16:37:12.344657 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6556 16:37:12.350755 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6557 16:37:12.354154 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6558 16:37:12.357611 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6559 16:37:12.361044 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6560 16:37:12.367224 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6561 16:37:12.370735 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6562 16:37:12.374152 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6563 16:37:12.377487 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6564 16:37:12.383709 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6565 16:37:12.387041 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6566 16:37:12.390574 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6567 16:37:12.393983 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6568 16:37:12.400769 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6569 16:37:12.400883 ==
6570 16:37:12.403562 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 16:37:12.407320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 16:37:12.407429 ==
6573 16:37:12.407525 DQS Delay:
6574 16:37:12.410401 DQS0 = 43, DQS1 = 59
6575 16:37:12.410482 DQM Delay:
6576 16:37:12.413703 DQM0 = 10, DQM1 = 16
6577 16:37:12.413785 DQ Delay:
6578 16:37:12.416996 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6579 16:37:12.420196 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6580 16:37:12.423821 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6581 16:37:12.426816 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6582 16:37:12.426897
6583 16:37:12.426959
6584 16:37:12.427017 ==
6585 16:37:12.430099 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 16:37:12.433347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 16:37:12.433427 ==
6588 16:37:12.433491
6589 16:37:12.436537
6590 16:37:12.436617 TX Vref Scan disable
6591 16:37:12.440392 == TX Byte 0 ==
6592 16:37:12.443152 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6593 16:37:12.446633 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6594 16:37:12.450030 == TX Byte 1 ==
6595 16:37:12.453371 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6596 16:37:12.456730 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6597 16:37:12.456856 ==
6598 16:37:12.460101 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 16:37:12.462887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 16:37:12.466315 ==
6601 16:37:12.466394
6602 16:37:12.466456
6603 16:37:12.466514 TX Vref Scan disable
6604 16:37:12.469614 == TX Byte 0 ==
6605 16:37:12.472920 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6606 16:37:12.476338 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6607 16:37:12.479665 == TX Byte 1 ==
6608 16:37:12.483066 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6609 16:37:12.486600 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6610 16:37:12.486766
6611 16:37:12.486841 [DATLAT]
6612 16:37:12.490000 Freq=400, CH0 RK1
6613 16:37:12.490115
6614 16:37:12.492780 DATLAT Default: 0xe
6615 16:37:12.492891 0, 0xFFFF, sum = 0
6616 16:37:12.496176 1, 0xFFFF, sum = 0
6617 16:37:12.496283 2, 0xFFFF, sum = 0
6618 16:37:12.499419 3, 0xFFFF, sum = 0
6619 16:37:12.499555 4, 0xFFFF, sum = 0
6620 16:37:12.502897 5, 0xFFFF, sum = 0
6621 16:37:12.503010 6, 0xFFFF, sum = 0
6622 16:37:12.506115 7, 0xFFFF, sum = 0
6623 16:37:12.506246 8, 0xFFFF, sum = 0
6624 16:37:12.509606 9, 0xFFFF, sum = 0
6625 16:37:12.509692 10, 0xFFFF, sum = 0
6626 16:37:12.512337 11, 0xFFFF, sum = 0
6627 16:37:12.515759 12, 0xFFFF, sum = 0
6628 16:37:12.515842 13, 0x0, sum = 1
6629 16:37:12.515907 14, 0x0, sum = 2
6630 16:37:12.518900 15, 0x0, sum = 3
6631 16:37:12.518981 16, 0x0, sum = 4
6632 16:37:12.522583 best_step = 14
6633 16:37:12.522662
6634 16:37:12.522726 ==
6635 16:37:12.525730 Dram Type= 6, Freq= 0, CH_0, rank 1
6636 16:37:12.528979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 16:37:12.529056 ==
6638 16:37:12.532369 RX Vref Scan: 0
6639 16:37:12.532443
6640 16:37:12.532503 RX Vref 0 -> 0, step: 1
6641 16:37:12.532592
6642 16:37:12.535684 RX Delay -359 -> 252, step: 8
6643 16:37:12.543687 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6644 16:37:12.547052 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6645 16:37:12.550587 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6646 16:37:12.557453 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6647 16:37:12.560822 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6648 16:37:12.563614 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6649 16:37:12.567004 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6650 16:37:12.573763 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6651 16:37:12.576603 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6652 16:37:12.580174 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6653 16:37:12.583434 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6654 16:37:12.590131 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6655 16:37:12.593498 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6656 16:37:12.596922 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6657 16:37:12.600229 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6658 16:37:12.606299 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6659 16:37:12.606395 ==
6660 16:37:12.609733 Dram Type= 6, Freq= 0, CH_0, rank 1
6661 16:37:12.613058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 16:37:12.613167 ==
6663 16:37:12.616504 DQS Delay:
6664 16:37:12.616609 DQS0 = 44, DQS1 = 60
6665 16:37:12.616706 DQM Delay:
6666 16:37:12.619399 DQM0 = 7, DQM1 = 13
6667 16:37:12.619520 DQ Delay:
6668 16:37:12.622687 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6669 16:37:12.626043 DQ4 =4, DQ5 =0, DQ6 =16, DQ7 =16
6670 16:37:12.629338 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6671 16:37:12.632468 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6672 16:37:12.632611
6673 16:37:12.632708
6674 16:37:12.642995 [DQSOSCAuto] RK1, (LSB)MR18= 0xad3a, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6675 16:37:12.643138 CH0 RK1: MR19=C0C, MR18=AD3A
6676 16:37:12.649477 CH0_RK1: MR19=0xC0C, MR18=0xAD3A, DQSOSC=388, MR23=63, INC=392, DEC=261
6677 16:37:12.652479 [RxdqsGatingPostProcess] freq 400
6678 16:37:12.658829 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6679 16:37:12.662032 best DQS0 dly(2T, 0.5T) = (0, 10)
6680 16:37:12.666028 best DQS1 dly(2T, 0.5T) = (0, 10)
6681 16:37:12.669293 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6682 16:37:12.672032 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6683 16:37:12.675530 best DQS0 dly(2T, 0.5T) = (0, 10)
6684 16:37:12.675632 best DQS1 dly(2T, 0.5T) = (0, 10)
6685 16:37:12.678827 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6686 16:37:12.682365 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6687 16:37:12.685810 Pre-setting of DQS Precalculation
6688 16:37:12.691955 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6689 16:37:12.692052 ==
6690 16:37:12.695387 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 16:37:12.698879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 16:37:12.698961 ==
6693 16:37:12.705608 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 16:37:12.711829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6695 16:37:12.715181 [CA 0] Center 36 (8~64) winsize 57
6696 16:37:12.718487 [CA 1] Center 36 (8~64) winsize 57
6697 16:37:12.721913 [CA 2] Center 36 (8~64) winsize 57
6698 16:37:12.722020 [CA 3] Center 36 (8~64) winsize 57
6699 16:37:12.725393 [CA 4] Center 36 (8~64) winsize 57
6700 16:37:12.728111 [CA 5] Center 36 (8~64) winsize 57
6701 16:37:12.728211
6702 16:37:12.735377 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6703 16:37:12.735468
6704 16:37:12.738089 [CATrainingPosCal] consider 1 rank data
6705 16:37:12.741398 u2DelayCellTimex100 = 270/100 ps
6706 16:37:12.744702 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 16:37:12.747844 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 16:37:12.751042 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 16:37:12.754915 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 16:37:12.758110 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 16:37:12.761385 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 16:37:12.761468
6713 16:37:12.764670 CA PerBit enable=1, Macro0, CA PI delay=36
6714 16:37:12.764762
6715 16:37:12.768007 [CBTSetCACLKResult] CA Dly = 36
6716 16:37:12.771352 CS Dly: 1 (0~32)
6717 16:37:12.771433 ==
6718 16:37:12.774529 Dram Type= 6, Freq= 0, CH_1, rank 1
6719 16:37:12.777666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 16:37:12.777748 ==
6721 16:37:12.784358 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6722 16:37:12.791060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6723 16:37:12.794432 [CA 0] Center 36 (8~64) winsize 57
6724 16:37:12.797778 [CA 1] Center 36 (8~64) winsize 57
6725 16:37:12.797859 [CA 2] Center 36 (8~64) winsize 57
6726 16:37:12.800575 [CA 3] Center 36 (8~64) winsize 57
6727 16:37:12.803983 [CA 4] Center 36 (8~64) winsize 57
6728 16:37:12.807339 [CA 5] Center 36 (8~64) winsize 57
6729 16:37:12.807429
6730 16:37:12.810664 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6731 16:37:12.814035
6732 16:37:12.817539 [CATrainingPosCal] consider 2 rank data
6733 16:37:12.817669 u2DelayCellTimex100 = 270/100 ps
6734 16:37:12.823791 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 16:37:12.827368 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 16:37:12.830588 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 16:37:12.833932 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 16:37:12.837401 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 16:37:12.840219 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 16:37:12.840294
6741 16:37:12.843621 CA PerBit enable=1, Macro0, CA PI delay=36
6742 16:37:12.843693
6743 16:37:12.846855 [CBTSetCACLKResult] CA Dly = 36
6744 16:37:12.850340 CS Dly: 1 (0~32)
6745 16:37:12.850420
6746 16:37:12.853807 ----->DramcWriteLeveling(PI) begin...
6747 16:37:12.853888 ==
6748 16:37:12.857064 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 16:37:12.860096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 16:37:12.860177 ==
6751 16:37:12.863363 Write leveling (Byte 0): 40 => 8
6752 16:37:12.866484 Write leveling (Byte 1): 40 => 8
6753 16:37:12.870386 DramcWriteLeveling(PI) end<-----
6754 16:37:12.870466
6755 16:37:12.870529 ==
6756 16:37:12.873184 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 16:37:12.876558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 16:37:12.876638 ==
6759 16:37:12.879953 [Gating] SW mode calibration
6760 16:37:12.886058 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6761 16:37:12.893159 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6762 16:37:12.896451 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6763 16:37:12.899682 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6764 16:37:12.905841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 16:37:12.909356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6766 16:37:12.913155 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 16:37:12.919884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 16:37:12.923120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 16:37:12.925909 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6770 16:37:12.932740 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 16:37:12.936178 Total UI for P1: 0, mck2ui 16
6772 16:37:12.939605 best dqsien dly found for B0: ( 0, 14, 24)
6773 16:37:12.943005 Total UI for P1: 0, mck2ui 16
6774 16:37:12.945751 best dqsien dly found for B1: ( 0, 14, 24)
6775 16:37:12.949079 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6776 16:37:12.952358 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6777 16:37:12.952437
6778 16:37:12.955761 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6779 16:37:12.959149 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6780 16:37:12.962363 [Gating] SW calibration Done
6781 16:37:12.962450 ==
6782 16:37:12.965752 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 16:37:12.969080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 16:37:12.969160 ==
6785 16:37:12.972468 RX Vref Scan: 0
6786 16:37:12.972572
6787 16:37:12.975798 RX Vref 0 -> 0, step: 1
6788 16:37:12.975904
6789 16:37:12.975995 RX Delay -410 -> 252, step: 16
6790 16:37:12.982281 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6791 16:37:12.985531 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6792 16:37:12.989069 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6793 16:37:12.995588 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6794 16:37:12.998857 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6795 16:37:13.002575 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6796 16:37:13.005751 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6797 16:37:13.012422 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6798 16:37:13.015775 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6799 16:37:13.018498 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6800 16:37:13.022397 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6801 16:37:13.028655 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6802 16:37:13.032042 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6803 16:37:13.035452 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6804 16:37:13.038681 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6805 16:37:13.044946 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6806 16:37:13.045027 ==
6807 16:37:13.048252 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 16:37:13.051797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 16:37:13.051877 ==
6810 16:37:13.055152 DQS Delay:
6811 16:37:13.055231 DQS0 = 43, DQS1 = 51
6812 16:37:13.055294 DQM Delay:
6813 16:37:13.057790 DQM0 = 12, DQM1 = 14
6814 16:37:13.057869 DQ Delay:
6815 16:37:13.061332 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6816 16:37:13.064722 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6817 16:37:13.068134 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6818 16:37:13.071337 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6819 16:37:13.071417
6820 16:37:13.071480
6821 16:37:13.071537 ==
6822 16:37:13.074672 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 16:37:13.078196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 16:37:13.078277 ==
6825 16:37:13.080987
6826 16:37:13.081066
6827 16:37:13.081127 TX Vref Scan disable
6828 16:37:13.084127 == TX Byte 0 ==
6829 16:37:13.087488 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 16:37:13.090923 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 16:37:13.094310 == TX Byte 1 ==
6832 16:37:13.097769 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 16:37:13.101006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 16:37:13.101086 ==
6835 16:37:13.104314 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 16:37:13.110753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 16:37:13.110835 ==
6838 16:37:13.110897
6839 16:37:13.110955
6840 16:37:13.111010 TX Vref Scan disable
6841 16:37:13.114102 == TX Byte 0 ==
6842 16:37:13.117299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6843 16:37:13.120618 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6844 16:37:13.124082 == TX Byte 1 ==
6845 16:37:13.127430 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6846 16:37:13.130707 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6847 16:37:13.130801
6848 16:37:13.134122 [DATLAT]
6849 16:37:13.134233 Freq=400, CH1 RK0
6850 16:37:13.134308
6851 16:37:13.137599 DATLAT Default: 0xf
6852 16:37:13.137698 0, 0xFFFF, sum = 0
6853 16:37:13.140338 1, 0xFFFF, sum = 0
6854 16:37:13.140458 2, 0xFFFF, sum = 0
6855 16:37:13.143870 3, 0xFFFF, sum = 0
6856 16:37:13.143951 4, 0xFFFF, sum = 0
6857 16:37:13.147511 5, 0xFFFF, sum = 0
6858 16:37:13.147920 6, 0xFFFF, sum = 0
6859 16:37:13.150772 7, 0xFFFF, sum = 0
6860 16:37:13.151360 8, 0xFFFF, sum = 0
6861 16:37:13.154103 9, 0xFFFF, sum = 0
6862 16:37:13.154658 10, 0xFFFF, sum = 0
6863 16:37:13.157511 11, 0xFFFF, sum = 0
6864 16:37:13.160806 12, 0xFFFF, sum = 0
6865 16:37:13.161229 13, 0x0, sum = 1
6866 16:37:13.164074 14, 0x0, sum = 2
6867 16:37:13.164656 15, 0x0, sum = 3
6868 16:37:13.165024 16, 0x0, sum = 4
6869 16:37:13.167600 best_step = 14
6870 16:37:13.168004
6871 16:37:13.168365 ==
6872 16:37:13.170358 Dram Type= 6, Freq= 0, CH_1, rank 0
6873 16:37:13.173649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 16:37:13.174124 ==
6875 16:37:13.177487 RX Vref Scan: 1
6876 16:37:13.177943
6877 16:37:13.180280 RX Vref 0 -> 0, step: 1
6878 16:37:13.180736
6879 16:37:13.181287 RX Delay -343 -> 252, step: 8
6880 16:37:13.181650
6881 16:37:13.183758 Set Vref, RX VrefLevel [Byte0]: 50
6882 16:37:13.187160 [Byte1]: 59
6883 16:37:13.192620
6884 16:37:13.193044 Final RX Vref Byte 0 = 50 to rank0
6885 16:37:13.195836 Final RX Vref Byte 1 = 59 to rank0
6886 16:37:13.198895 Final RX Vref Byte 0 = 50 to rank1
6887 16:37:13.202286 Final RX Vref Byte 1 = 59 to rank1==
6888 16:37:13.205780 Dram Type= 6, Freq= 0, CH_1, rank 0
6889 16:37:13.212425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 16:37:13.212868 ==
6891 16:37:13.213199 DQS Delay:
6892 16:37:13.215658 DQS0 = 44, DQS1 = 56
6893 16:37:13.216071 DQM Delay:
6894 16:37:13.216432 DQM0 = 7, DQM1 = 12
6895 16:37:13.219151 DQ Delay:
6896 16:37:13.222415 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6897 16:37:13.222828 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6898 16:37:13.225727 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6899 16:37:13.228925 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6900 16:37:13.229334
6901 16:37:13.232316
6902 16:37:13.238282 [DQSOSCAuto] RK0, (LSB)MR18= 0x966c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6903 16:37:13.241798 CH1 RK0: MR19=C0C, MR18=966C
6904 16:37:13.248824 CH1_RK0: MR19=0xC0C, MR18=0x966C, DQSOSC=391, MR23=63, INC=386, DEC=257
6905 16:37:13.249279 ==
6906 16:37:13.252144 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 16:37:13.255533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 16:37:13.255978 ==
6909 16:37:13.258270 [Gating] SW mode calibration
6910 16:37:13.265104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6911 16:37:13.271907 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6912 16:37:13.275107 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6913 16:37:13.278237 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6914 16:37:13.285073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 16:37:13.287936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6916 16:37:13.291151 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 16:37:13.297935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 16:37:13.301265 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 16:37:13.304622 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6920 16:37:13.311313 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 16:37:13.311723 Total UI for P1: 0, mck2ui 16
6922 16:37:13.317836 best dqsien dly found for B0: ( 0, 14, 24)
6923 16:37:13.318329 Total UI for P1: 0, mck2ui 16
6924 16:37:13.321017 best dqsien dly found for B1: ( 0, 14, 24)
6925 16:37:13.327756 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6926 16:37:13.331245 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6927 16:37:13.331693
6928 16:37:13.334295 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6929 16:37:13.337330 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6930 16:37:13.340738 [Gating] SW calibration Done
6931 16:37:13.341306 ==
6932 16:37:13.344289 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 16:37:13.347727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 16:37:13.348182 ==
6935 16:37:13.350405 RX Vref Scan: 0
6936 16:37:13.350814
6937 16:37:13.351152 RX Vref 0 -> 0, step: 1
6938 16:37:13.351471
6939 16:37:13.353780 RX Delay -410 -> 252, step: 16
6940 16:37:13.360432 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6941 16:37:13.363821 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6942 16:37:13.367109 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6943 16:37:13.370593 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6944 16:37:13.377147 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6945 16:37:13.379871 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6946 16:37:13.383293 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6947 16:37:13.386981 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6948 16:37:13.393151 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6949 16:37:13.396535 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6950 16:37:13.400013 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6951 16:37:13.406532 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6952 16:37:13.409853 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6953 16:37:13.413236 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6954 16:37:13.416315 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6955 16:37:13.422999 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6956 16:37:13.423411 ==
6957 16:37:13.426729 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 16:37:13.429628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 16:37:13.430124 ==
6960 16:37:13.430627 DQS Delay:
6961 16:37:13.432785 DQS0 = 51, DQS1 = 59
6962 16:37:13.433387 DQM Delay:
6963 16:37:13.436381 DQM0 = 20, DQM1 = 22
6964 16:37:13.436950 DQ Delay:
6965 16:37:13.439666 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6966 16:37:13.443055 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6967 16:37:13.446429 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6968 16:37:13.449684 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6969 16:37:13.450254
6970 16:37:13.450595
6971 16:37:13.450902 ==
6972 16:37:13.452948 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 16:37:13.456431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 16:37:13.459757 ==
6975 16:37:13.460206
6976 16:37:13.460661
6977 16:37:13.461133 TX Vref Scan disable
6978 16:37:13.462426 == TX Byte 0 ==
6979 16:37:13.466510 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6980 16:37:13.468980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6981 16:37:13.472493 == TX Byte 1 ==
6982 16:37:13.476013 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6983 16:37:13.479383 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6984 16:37:13.479827 ==
6985 16:37:13.482877 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 16:37:13.489120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 16:37:13.489550 ==
6988 16:37:13.489920
6989 16:37:13.490294
6990 16:37:13.490633 TX Vref Scan disable
6991 16:37:13.492283 == TX Byte 0 ==
6992 16:37:13.495657 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6993 16:37:13.498993 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6994 16:37:13.502448 == TX Byte 1 ==
6995 16:37:13.505699 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6996 16:37:13.509058 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6997 16:37:13.509461
6998 16:37:13.512484 [DATLAT]
6999 16:37:13.512919 Freq=400, CH1 RK1
7000 16:37:13.513267
7001 16:37:13.515129 DATLAT Default: 0xe
7002 16:37:13.515506 0, 0xFFFF, sum = 0
7003 16:37:13.518656 1, 0xFFFF, sum = 0
7004 16:37:13.519121 2, 0xFFFF, sum = 0
7005 16:37:13.522055 3, 0xFFFF, sum = 0
7006 16:37:13.522723 4, 0xFFFF, sum = 0
7007 16:37:13.525036 5, 0xFFFF, sum = 0
7008 16:37:13.525477 6, 0xFFFF, sum = 0
7009 16:37:13.528759 7, 0xFFFF, sum = 0
7010 16:37:13.529400 8, 0xFFFF, sum = 0
7011 16:37:13.531873 9, 0xFFFF, sum = 0
7012 16:37:13.535001 10, 0xFFFF, sum = 0
7013 16:37:13.535449 11, 0xFFFF, sum = 0
7014 16:37:13.538150 12, 0xFFFF, sum = 0
7015 16:37:13.538813 13, 0x0, sum = 1
7016 16:37:13.541444 14, 0x0, sum = 2
7017 16:37:13.541934 15, 0x0, sum = 3
7018 16:37:13.542425 16, 0x0, sum = 4
7019 16:37:13.544955 best_step = 14
7020 16:37:13.545505
7021 16:37:13.546043 ==
7022 16:37:13.548347 Dram Type= 6, Freq= 0, CH_1, rank 1
7023 16:37:13.551495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7024 16:37:13.551959 ==
7025 16:37:13.554789 RX Vref Scan: 0
7026 16:37:13.555394
7027 16:37:13.558298 RX Vref 0 -> 0, step: 1
7028 16:37:13.558808
7029 16:37:13.559147 RX Delay -359 -> 252, step: 8
7030 16:37:13.567186 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7031 16:37:13.570463 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7032 16:37:13.573702 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7033 16:37:13.580562 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7034 16:37:13.583757 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7035 16:37:13.587108 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7036 16:37:13.590571 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7037 16:37:13.596500 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7038 16:37:13.599923 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7039 16:37:13.603708 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7040 16:37:13.606483 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7041 16:37:13.613304 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7042 16:37:13.616744 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7043 16:37:13.619557 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7044 16:37:13.622988 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7045 16:37:13.629730 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7046 16:37:13.630152 ==
7047 16:37:13.632777 Dram Type= 6, Freq= 0, CH_1, rank 1
7048 16:37:13.636468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7049 16:37:13.636925 ==
7050 16:37:13.637464 DQS Delay:
7051 16:37:13.639575 DQS0 = 44, DQS1 = 60
7052 16:37:13.640075 DQM Delay:
7053 16:37:13.642961 DQM0 = 8, DQM1 = 14
7054 16:37:13.643392 DQ Delay:
7055 16:37:13.645944 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7056 16:37:13.649525 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7057 16:37:13.652986 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7058 16:37:13.655728 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7059 16:37:13.656209
7060 16:37:13.656566
7061 16:37:13.662374 [DQSOSCAuto] RK1, (LSB)MR18= 0x6857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7062 16:37:13.665722 CH1 RK1: MR19=C0C, MR18=6857
7063 16:37:13.672492 CH1_RK1: MR19=0xC0C, MR18=0x6857, DQSOSC=396, MR23=63, INC=376, DEC=251
7064 16:37:13.675857 [RxdqsGatingPostProcess] freq 400
7065 16:37:13.682473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7066 16:37:13.685624 best DQS0 dly(2T, 0.5T) = (0, 10)
7067 16:37:13.688894 best DQS1 dly(2T, 0.5T) = (0, 10)
7068 16:37:13.692198 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7069 16:37:13.695499 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7070 16:37:13.698889 best DQS0 dly(2T, 0.5T) = (0, 10)
7071 16:37:13.699301 best DQS1 dly(2T, 0.5T) = (0, 10)
7072 16:37:13.702240 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7073 16:37:13.705648 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7074 16:37:13.708392 Pre-setting of DQS Precalculation
7075 16:37:13.715329 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7076 16:37:13.721990 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7077 16:37:13.728245 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7078 16:37:13.728840
7079 16:37:13.729301
7080 16:37:13.731593 [Calibration Summary] 800 Mbps
7081 16:37:13.734814 CH 0, Rank 0
7082 16:37:13.735300 SW Impedance : PASS
7083 16:37:13.738093 DUTY Scan : NO K
7084 16:37:13.741366 ZQ Calibration : PASS
7085 16:37:13.741854 Jitter Meter : NO K
7086 16:37:13.744568 CBT Training : PASS
7087 16:37:13.745014 Write leveling : PASS
7088 16:37:13.748006 RX DQS gating : PASS
7089 16:37:13.751439 RX DQ/DQS(RDDQC) : PASS
7090 16:37:13.751901 TX DQ/DQS : PASS
7091 16:37:13.754712 RX DATLAT : PASS
7092 16:37:13.758106 RX DQ/DQS(Engine): PASS
7093 16:37:13.758675 TX OE : NO K
7094 16:37:13.761424 All Pass.
7095 16:37:13.762199
7096 16:37:13.762652 CH 0, Rank 1
7097 16:37:13.764762 SW Impedance : PASS
7098 16:37:13.765366 DUTY Scan : NO K
7099 16:37:13.768090 ZQ Calibration : PASS
7100 16:37:13.771601 Jitter Meter : NO K
7101 16:37:13.772008 CBT Training : PASS
7102 16:37:13.774314 Write leveling : NO K
7103 16:37:13.777804 RX DQS gating : PASS
7104 16:37:13.778490 RX DQ/DQS(RDDQC) : PASS
7105 16:37:13.781135 TX DQ/DQS : PASS
7106 16:37:13.784443 RX DATLAT : PASS
7107 16:37:13.784961 RX DQ/DQS(Engine): PASS
7108 16:37:13.787941 TX OE : NO K
7109 16:37:13.788408 All Pass.
7110 16:37:13.788829
7111 16:37:13.790579 CH 1, Rank 0
7112 16:37:13.790988 SW Impedance : PASS
7113 16:37:13.794628 DUTY Scan : NO K
7114 16:37:13.797589 ZQ Calibration : PASS
7115 16:37:13.798081 Jitter Meter : NO K
7116 16:37:13.800840 CBT Training : PASS
7117 16:37:13.804457 Write leveling : PASS
7118 16:37:13.805003 RX DQS gating : PASS
7119 16:37:13.807824 RX DQ/DQS(RDDQC) : PASS
7120 16:37:13.811157 TX DQ/DQS : PASS
7121 16:37:13.811614 RX DATLAT : PASS
7122 16:37:13.814604 RX DQ/DQS(Engine): PASS
7123 16:37:13.815220 TX OE : NO K
7124 16:37:13.817689 All Pass.
7125 16:37:13.818515
7126 16:37:13.819228 CH 1, Rank 1
7127 16:37:13.820455 SW Impedance : PASS
7128 16:37:13.821015 DUTY Scan : NO K
7129 16:37:13.823798 ZQ Calibration : PASS
7130 16:37:13.827150 Jitter Meter : NO K
7131 16:37:13.827445 CBT Training : PASS
7132 16:37:13.830563 Write leveling : NO K
7133 16:37:13.833971 RX DQS gating : PASS
7134 16:37:13.834294 RX DQ/DQS(RDDQC) : PASS
7135 16:37:13.837359 TX DQ/DQS : PASS
7136 16:37:13.839925 RX DATLAT : PASS
7137 16:37:13.840219 RX DQ/DQS(Engine): PASS
7138 16:37:13.843266 TX OE : NO K
7139 16:37:13.843560 All Pass.
7140 16:37:13.843788
7141 16:37:13.846572 DramC Write-DBI off
7142 16:37:13.850002 PER_BANK_REFRESH: Hybrid Mode
7143 16:37:13.850333 TX_TRACKING: ON
7144 16:37:13.859804 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7145 16:37:13.863139 [FAST_K] Save calibration result to emmc
7146 16:37:13.866599 dramc_set_vcore_voltage set vcore to 725000
7147 16:37:13.870007 Read voltage for 1600, 0
7148 16:37:13.870374 Vio18 = 0
7149 16:37:13.873377 Vcore = 725000
7150 16:37:13.873769 Vdram = 0
7151 16:37:13.874139 Vddq = 0
7152 16:37:13.874595 Vmddr = 0
7153 16:37:13.879592 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7154 16:37:13.886394 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7155 16:37:13.886797 MEM_TYPE=3, freq_sel=13
7156 16:37:13.889683 sv_algorithm_assistance_LP4_3733
7157 16:37:13.892466 ============ PULL DRAM RESETB DOWN ============
7158 16:37:13.899303 ========== PULL DRAM RESETB DOWN end =========
7159 16:37:13.902561 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7160 16:37:13.905718 ===================================
7161 16:37:13.909038 LPDDR4 DRAM CONFIGURATION
7162 16:37:13.912318 ===================================
7163 16:37:13.912676 EX_ROW_EN[0] = 0x0
7164 16:37:13.915743 EX_ROW_EN[1] = 0x0
7165 16:37:13.919275 LP4Y_EN = 0x0
7166 16:37:13.919566 WORK_FSP = 0x1
7167 16:37:13.922530 WL = 0x5
7168 16:37:13.922817 RL = 0x5
7169 16:37:13.925948 BL = 0x2
7170 16:37:13.926370 RPST = 0x0
7171 16:37:13.929317 RD_PRE = 0x0
7172 16:37:13.929639 WR_PRE = 0x1
7173 16:37:13.932651 WR_PST = 0x1
7174 16:37:13.932969 DBI_WR = 0x0
7175 16:37:13.935895 DBI_RD = 0x0
7176 16:37:13.936003 OTF = 0x1
7177 16:37:13.938607 ===================================
7178 16:37:13.942086 ===================================
7179 16:37:13.945502 ANA top config
7180 16:37:13.948753 ===================================
7181 16:37:13.948832 DLL_ASYNC_EN = 0
7182 16:37:13.952260 ALL_SLAVE_EN = 0
7183 16:37:13.955478 NEW_RANK_MODE = 1
7184 16:37:13.958834 DLL_IDLE_MODE = 1
7185 16:37:13.962093 LP45_APHY_COMB_EN = 1
7186 16:37:13.962225 TX_ODT_DIS = 0
7187 16:37:13.965315 NEW_8X_MODE = 1
7188 16:37:13.968689 ===================================
7189 16:37:13.972115 ===================================
7190 16:37:13.975549 data_rate = 3200
7191 16:37:13.978817 CKR = 1
7192 16:37:13.981520 DQ_P2S_RATIO = 8
7193 16:37:13.984851 ===================================
7194 16:37:13.988216 CA_P2S_RATIO = 8
7195 16:37:13.988348 DQ_CA_OPEN = 0
7196 16:37:13.991523 DQ_SEMI_OPEN = 0
7197 16:37:13.994978 CA_SEMI_OPEN = 0
7198 16:37:13.998303 CA_FULL_RATE = 0
7199 16:37:14.001657 DQ_CKDIV4_EN = 0
7200 16:37:14.005209 CA_CKDIV4_EN = 0
7201 16:37:14.005356 CA_PREDIV_EN = 0
7202 16:37:14.008418 PH8_DLY = 12
7203 16:37:14.011531 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7204 16:37:14.014942 DQ_AAMCK_DIV = 4
7205 16:37:14.018204 CA_AAMCK_DIV = 4
7206 16:37:14.021639 CA_ADMCK_DIV = 4
7207 16:37:14.021889 DQ_TRACK_CA_EN = 0
7208 16:37:14.024917 CA_PICK = 1600
7209 16:37:14.028365 CA_MCKIO = 1600
7210 16:37:14.031060 MCKIO_SEMI = 0
7211 16:37:14.034596 PLL_FREQ = 3068
7212 16:37:14.038089 DQ_UI_PI_RATIO = 32
7213 16:37:14.041420 CA_UI_PI_RATIO = 0
7214 16:37:14.044800 ===================================
7215 16:37:14.048138 ===================================
7216 16:37:14.048569 memory_type:LPDDR4
7217 16:37:14.050864 GP_NUM : 10
7218 16:37:14.054393 SRAM_EN : 1
7219 16:37:14.054876 MD32_EN : 0
7220 16:37:14.057542 ===================================
7221 16:37:14.060892 [ANA_INIT] >>>>>>>>>>>>>>
7222 16:37:14.064261 <<<<<< [CONFIGURE PHASE]: ANA_TX
7223 16:37:14.067821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7224 16:37:14.070896 ===================================
7225 16:37:14.074002 data_rate = 3200,PCW = 0X7600
7226 16:37:14.077393 ===================================
7227 16:37:14.080764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7228 16:37:14.087468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7229 16:37:14.090846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7230 16:37:14.098046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7231 16:37:14.100814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7232 16:37:14.104364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7233 16:37:14.104889 [ANA_INIT] flow start
7234 16:37:14.106992 [ANA_INIT] PLL >>>>>>>>
7235 16:37:14.110294 [ANA_INIT] PLL <<<<<<<<
7236 16:37:14.110725 [ANA_INIT] MIDPI >>>>>>>>
7237 16:37:14.113577 [ANA_INIT] MIDPI <<<<<<<<
7238 16:37:14.117014 [ANA_INIT] DLL >>>>>>>>
7239 16:37:14.117446 [ANA_INIT] DLL <<<<<<<<
7240 16:37:14.120297 [ANA_INIT] flow end
7241 16:37:14.123590 ============ LP4 DIFF to SE enter ============
7242 16:37:14.130593 ============ LP4 DIFF to SE exit ============
7243 16:37:14.131029 [ANA_INIT] <<<<<<<<<<<<<
7244 16:37:14.133862 [Flow] Enable top DCM control >>>>>
7245 16:37:14.137310 [Flow] Enable top DCM control <<<<<
7246 16:37:14.140105 Enable DLL master slave shuffle
7247 16:37:14.146917 ==============================================================
7248 16:37:14.147334 Gating Mode config
7249 16:37:14.153588 ==============================================================
7250 16:37:14.156959 Config description:
7251 16:37:14.163430 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7252 16:37:14.170477 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7253 16:37:14.177110 SELPH_MODE 0: By rank 1: By Phase
7254 16:37:14.183669 ==============================================================
7255 16:37:14.184114 GAT_TRACK_EN = 1
7256 16:37:14.187008 RX_GATING_MODE = 2
7257 16:37:14.190119 RX_GATING_TRACK_MODE = 2
7258 16:37:14.193371 SELPH_MODE = 1
7259 16:37:14.196812 PICG_EARLY_EN = 1
7260 16:37:14.199687 VALID_LAT_VALUE = 1
7261 16:37:14.206364 ==============================================================
7262 16:37:14.209803 Enter into Gating configuration >>>>
7263 16:37:14.212486 Exit from Gating configuration <<<<
7264 16:37:14.215911 Enter into DVFS_PRE_config >>>>>
7265 16:37:14.225635 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7266 16:37:14.229009 Exit from DVFS_PRE_config <<<<<
7267 16:37:14.232290 Enter into PICG configuration >>>>
7268 16:37:14.235620 Exit from PICG configuration <<<<
7269 16:37:14.239560 [RX_INPUT] configuration >>>>>
7270 16:37:14.242781 [RX_INPUT] configuration <<<<<
7271 16:37:14.246053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7272 16:37:14.252434 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7273 16:37:14.259193 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 16:37:14.266029 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 16:37:14.269032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7276 16:37:14.275349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7277 16:37:14.282054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7278 16:37:14.285105 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7279 16:37:14.288564 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7280 16:37:14.291598 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7281 16:37:14.298743 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7282 16:37:14.302078 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 16:37:14.305648 ===================================
7284 16:37:14.308096 LPDDR4 DRAM CONFIGURATION
7285 16:37:14.311427 ===================================
7286 16:37:14.311858 EX_ROW_EN[0] = 0x0
7287 16:37:14.314837 EX_ROW_EN[1] = 0x0
7288 16:37:14.315400 LP4Y_EN = 0x0
7289 16:37:14.318223 WORK_FSP = 0x1
7290 16:37:14.318643 WL = 0x5
7291 16:37:14.321711 RL = 0x5
7292 16:37:14.322125 BL = 0x2
7293 16:37:14.324612 RPST = 0x0
7294 16:37:14.325023 RD_PRE = 0x0
7295 16:37:14.327981 WR_PRE = 0x1
7296 16:37:14.331327 WR_PST = 0x1
7297 16:37:14.331747 DBI_WR = 0x0
7298 16:37:14.334763 DBI_RD = 0x0
7299 16:37:14.335339 OTF = 0x1
7300 16:37:14.338092 ===================================
7301 16:37:14.341388 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7302 16:37:14.348066 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7303 16:37:14.351543 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7304 16:37:14.354293 ===================================
7305 16:37:14.357660 LPDDR4 DRAM CONFIGURATION
7306 16:37:14.360921 ===================================
7307 16:37:14.361338 EX_ROW_EN[0] = 0x10
7308 16:37:14.364518 EX_ROW_EN[1] = 0x0
7309 16:37:14.364852 LP4Y_EN = 0x0
7310 16:37:14.367665 WORK_FSP = 0x1
7311 16:37:14.367961 WL = 0x5
7312 16:37:14.370940 RL = 0x5
7313 16:37:14.371164 BL = 0x2
7314 16:37:14.374118 RPST = 0x0
7315 16:37:14.377670 RD_PRE = 0x0
7316 16:37:14.377850 WR_PRE = 0x1
7317 16:37:14.380845 WR_PST = 0x1
7318 16:37:14.381025 DBI_WR = 0x0
7319 16:37:14.384141 DBI_RD = 0x0
7320 16:37:14.384319 OTF = 0x1
7321 16:37:14.387486 ===================================
7322 16:37:14.393675 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7323 16:37:14.393756 ==
7324 16:37:14.397000 Dram Type= 6, Freq= 0, CH_0, rank 0
7325 16:37:14.400211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 16:37:14.400291 ==
7327 16:37:14.403415 [Duty_Offset_Calibration]
7328 16:37:14.406764 B0:1 B1:-1 CA:0
7329 16:37:14.406844
7330 16:37:14.409983 [DutyScan_Calibration_Flow] k_type=0
7331 16:37:14.419094
7332 16:37:14.419175 ==CLK 0==
7333 16:37:14.421789 Final CLK duty delay cell = 0
7334 16:37:14.425210 [0] MAX Duty = 5125%(X100), DQS PI = 20
7335 16:37:14.428519 [0] MIN Duty = 4907%(X100), DQS PI = 6
7336 16:37:14.428600 [0] AVG Duty = 5016%(X100)
7337 16:37:14.431788
7338 16:37:14.435171 CH0 CLK Duty spec in!! Max-Min= 218%
7339 16:37:14.438503 [DutyScan_Calibration_Flow] ====Done====
7340 16:37:14.438583
7341 16:37:14.442087 [DutyScan_Calibration_Flow] k_type=1
7342 16:37:14.457574
7343 16:37:14.457654 ==DQS 0 ==
7344 16:37:14.460879 Final DQS duty delay cell = -4
7345 16:37:14.464294 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7346 16:37:14.467642 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7347 16:37:14.471028 [-4] AVG Duty = 4906%(X100)
7348 16:37:14.471108
7349 16:37:14.471203 ==DQS 1 ==
7350 16:37:14.474443 Final DQS duty delay cell = 0
7351 16:37:14.477596 [0] MAX Duty = 5156%(X100), DQS PI = 2
7352 16:37:14.481061 [0] MIN Duty = 5031%(X100), DQS PI = 16
7353 16:37:14.484351 [0] AVG Duty = 5093%(X100)
7354 16:37:14.484432
7355 16:37:14.487826 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7356 16:37:14.487906
7357 16:37:14.491039 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7358 16:37:14.494471 [DutyScan_Calibration_Flow] ====Done====
7359 16:37:14.494551
7360 16:37:14.497207 [DutyScan_Calibration_Flow] k_type=3
7361 16:37:14.517488
7362 16:37:14.517596 ==DQM 0 ==
7363 16:37:14.518433 Final DQM duty delay cell = 0
7364 16:37:14.522116 [0] MAX Duty = 5124%(X100), DQS PI = 24
7365 16:37:14.525349 [0] MIN Duty = 4875%(X100), DQS PI = 10
7366 16:37:14.528993 [0] AVG Duty = 4999%(X100)
7367 16:37:14.529078
7368 16:37:14.529155 ==DQM 1 ==
7369 16:37:14.531676 Final DQM duty delay cell = 0
7370 16:37:14.535039 [0] MAX Duty = 5000%(X100), DQS PI = 4
7371 16:37:14.538520 [0] MIN Duty = 4813%(X100), DQS PI = 18
7372 16:37:14.542057 [0] AVG Duty = 4906%(X100)
7373 16:37:14.542143
7374 16:37:14.544843 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7375 16:37:14.544936
7376 16:37:14.548366 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7377 16:37:14.551649 [DutyScan_Calibration_Flow] ====Done====
7378 16:37:14.551749
7379 16:37:14.554999 [DutyScan_Calibration_Flow] k_type=2
7380 16:37:14.571367
7381 16:37:14.571540 ==DQ 0 ==
7382 16:37:14.575082 Final DQ duty delay cell = -4
7383 16:37:14.578371 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7384 16:37:14.581642 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7385 16:37:14.584822 [-4] AVG Duty = 4953%(X100)
7386 16:37:14.584905
7387 16:37:14.584968 ==DQ 1 ==
7388 16:37:14.588110 Final DQ duty delay cell = 0
7389 16:37:14.591025 [0] MAX Duty = 5125%(X100), DQS PI = 48
7390 16:37:14.594305 [0] MIN Duty = 4969%(X100), DQS PI = 38
7391 16:37:14.597782 [0] AVG Duty = 5047%(X100)
7392 16:37:14.597862
7393 16:37:14.601262 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7394 16:37:14.601343
7395 16:37:14.604673 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7396 16:37:14.607504 [DutyScan_Calibration_Flow] ====Done====
7397 16:37:14.607601 ==
7398 16:37:14.610868 Dram Type= 6, Freq= 0, CH_1, rank 0
7399 16:37:14.614304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7400 16:37:14.614385 ==
7401 16:37:14.617803 [Duty_Offset_Calibration]
7402 16:37:14.617883 B0:-1 B1:1 CA:2
7403 16:37:14.621219
7404 16:37:14.625169 [DutyScan_Calibration_Flow] k_type=0
7405 16:37:14.634189
7406 16:37:14.634271 ==CLK 0==
7407 16:37:14.635528 Final CLK duty delay cell = 0
7408 16:37:14.646423 [0] MAX Duty = 5187%(X100), DQS PI = 22
7409 16:37:14.646544 [0] MIN Duty = 4969%(X100), DQS PI = 0
7410 16:37:14.646615 [0] AVG Duty = 5078%(X100)
7411 16:37:14.646967
7412 16:37:14.648596 CH1 CLK Duty spec in!! Max-Min= 218%
7413 16:37:14.652097 [DutyScan_Calibration_Flow] ====Done====
7414 16:37:14.652177
7415 16:37:14.655497 [DutyScan_Calibration_Flow] k_type=1
7416 16:37:14.671746
7417 16:37:14.671833 ==DQS 0 ==
7418 16:37:14.675070 Final DQS duty delay cell = 0
7419 16:37:14.678915 [0] MAX Duty = 5124%(X100), DQS PI = 18
7420 16:37:14.682169 [0] MIN Duty = 4907%(X100), DQS PI = 10
7421 16:37:14.684870 [0] AVG Duty = 5015%(X100)
7422 16:37:14.684951
7423 16:37:14.685013 ==DQS 1 ==
7424 16:37:14.688519 Final DQS duty delay cell = 0
7425 16:37:14.691662 [0] MAX Duty = 5093%(X100), DQS PI = 26
7426 16:37:14.695411 [0] MIN Duty = 4938%(X100), DQS PI = 58
7427 16:37:14.698066 [0] AVG Duty = 5015%(X100)
7428 16:37:14.698179
7429 16:37:14.701547 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7430 16:37:14.701620
7431 16:37:14.704759 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7432 16:37:14.708234 [DutyScan_Calibration_Flow] ====Done====
7433 16:37:14.708342
7434 16:37:14.711504 [DutyScan_Calibration_Flow] k_type=3
7435 16:37:14.728329
7436 16:37:14.728445 ==DQM 0 ==
7437 16:37:14.731610 Final DQM duty delay cell = -4
7438 16:37:14.734955 [-4] MAX Duty = 5031%(X100), DQS PI = 18
7439 16:37:14.737730 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7440 16:37:14.740950 [-4] AVG Duty = 4906%(X100)
7441 16:37:14.741057
7442 16:37:14.741123 ==DQM 1 ==
7443 16:37:14.744255 Final DQM duty delay cell = 0
7444 16:37:14.747575 [0] MAX Duty = 5156%(X100), DQS PI = 2
7445 16:37:14.750956 [0] MIN Duty = 4938%(X100), DQS PI = 34
7446 16:37:14.754541 [0] AVG Duty = 5047%(X100)
7447 16:37:14.754650
7448 16:37:14.759090 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7449 16:37:14.759188
7450 16:37:14.761174 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7451 16:37:14.764630 [DutyScan_Calibration_Flow] ====Done====
7452 16:37:14.764780
7453 16:37:14.767282 [DutyScan_Calibration_Flow] k_type=2
7454 16:37:14.785166
7455 16:37:14.785356 ==DQ 0 ==
7456 16:37:14.788590 Final DQ duty delay cell = 0
7457 16:37:14.792029 [0] MAX Duty = 5187%(X100), DQS PI = 32
7458 16:37:14.795154 [0] MIN Duty = 4906%(X100), DQS PI = 8
7459 16:37:14.795266 [0] AVG Duty = 5046%(X100)
7460 16:37:14.798416
7461 16:37:14.798496 ==DQ 1 ==
7462 16:37:14.801661 Final DQ duty delay cell = 0
7463 16:37:14.804644 [0] MAX Duty = 5156%(X100), DQS PI = 10
7464 16:37:14.807989 [0] MIN Duty = 4969%(X100), DQS PI = 54
7465 16:37:14.808090 [0] AVG Duty = 5062%(X100)
7466 16:37:14.811513
7467 16:37:14.814959 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7468 16:37:14.815053
7469 16:37:14.817837 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7470 16:37:14.821114 [DutyScan_Calibration_Flow] ====Done====
7471 16:37:14.824189 nWR fixed to 30
7472 16:37:14.827450 [ModeRegInit_LP4] CH0 RK0
7473 16:37:14.827550 [ModeRegInit_LP4] CH0 RK1
7474 16:37:14.830903 [ModeRegInit_LP4] CH1 RK0
7475 16:37:14.834347 [ModeRegInit_LP4] CH1 RK1
7476 16:37:14.834432 match AC timing 5
7477 16:37:14.840962 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7478 16:37:14.844398 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7479 16:37:14.847699 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7480 16:37:14.854258 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7481 16:37:14.857730 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7482 16:37:14.857828 [MiockJmeterHQA]
7483 16:37:14.857917
7484 16:37:14.860464 [DramcMiockJmeter] u1RxGatingPI = 0
7485 16:37:14.864012 0 : 4252, 4027
7486 16:37:14.864091 4 : 4363, 4137
7487 16:37:14.867488 8 : 4363, 4137
7488 16:37:14.867596 12 : 4363, 4138
7489 16:37:14.870476 16 : 4366, 4140
7490 16:37:14.870577 20 : 4252, 4027
7491 16:37:14.870679 24 : 4252, 4027
7492 16:37:14.873995 28 : 4253, 4026
7493 16:37:14.874094 32 : 4252, 4027
7494 16:37:14.877503 36 : 4365, 4140
7495 16:37:14.877604 40 : 4363, 4138
7496 16:37:14.880191 44 : 4255, 4029
7497 16:37:14.880297 48 : 4255, 4029
7498 16:37:14.884074 52 : 4363, 4138
7499 16:37:14.884183 56 : 4253, 4026
7500 16:37:14.884279 60 : 4366, 4140
7501 16:37:14.886812 64 : 4252, 4030
7502 16:37:14.886918 68 : 4250, 4027
7503 16:37:14.890682 72 : 4250, 4027
7504 16:37:14.890757 76 : 4250, 4026
7505 16:37:14.894136 80 : 4255, 4029
7506 16:37:14.894252 84 : 4250, 4027
7507 16:37:14.896904 88 : 4363, 4139
7508 16:37:14.897011 92 : 4363, 852
7509 16:37:14.897102 96 : 4252, 0
7510 16:37:14.900203 100 : 4252, 0
7511 16:37:14.900300 104 : 4253, 0
7512 16:37:14.903646 108 : 4360, 0
7513 16:37:14.903749 112 : 4250, 0
7514 16:37:14.903847 116 : 4250, 0
7515 16:37:14.906798 120 : 4250, 0
7516 16:37:14.906870 124 : 4255, 0
7517 16:37:14.906933 128 : 4361, 0
7518 16:37:14.910495 132 : 4361, 0
7519 16:37:14.910602 136 : 4250, 0
7520 16:37:14.913590 140 : 4250, 0
7521 16:37:14.913698 144 : 4360, 0
7522 16:37:14.913801 148 : 4250, 0
7523 16:37:14.916892 152 : 4250, 0
7524 16:37:14.916990 156 : 4250, 0
7525 16:37:14.920166 160 : 4360, 0
7526 16:37:14.920280 164 : 4250, 0
7527 16:37:14.920373 168 : 4250, 0
7528 16:37:14.923618 172 : 4250, 0
7529 16:37:14.923699 176 : 4250, 0
7530 16:37:14.927121 180 : 4361, 0
7531 16:37:14.927197 184 : 4361, 0
7532 16:37:14.927260 188 : 4250, 0
7533 16:37:14.929881 192 : 4250, 0
7534 16:37:14.929996 196 : 4360, 0
7535 16:37:14.933231 200 : 4250, 0
7536 16:37:14.933330 204 : 4250, 0
7537 16:37:14.933421 208 : 4250, 0
7538 16:37:14.936445 212 : 4250, 0
7539 16:37:14.936547 216 : 4250, 0
7540 16:37:14.936638 220 : 4250, 0
7541 16:37:14.939932 224 : 4250, 64
7542 16:37:14.940046 228 : 4249, 3381
7543 16:37:14.943402 232 : 4252, 4029
7544 16:37:14.943477 236 : 4253, 4029
7545 16:37:14.946833 240 : 4253, 4029
7546 16:37:14.946903 244 : 4250, 4027
7547 16:37:14.950095 248 : 4249, 4027
7548 16:37:14.950234 252 : 4253, 4029
7549 16:37:14.953462 256 : 4363, 4139
7550 16:37:14.953533 260 : 4250, 4026
7551 16:37:14.956190 264 : 4250, 4026
7552 16:37:14.956286 268 : 4250, 4027
7553 16:37:14.959434 272 : 4363, 4140
7554 16:37:14.959519 276 : 4360, 4138
7555 16:37:14.962826 280 : 4250, 4026
7556 16:37:14.962905 284 : 4361, 4137
7557 16:37:14.962964 288 : 4253, 4029
7558 16:37:14.966082 292 : 4250, 4027
7559 16:37:14.966201 296 : 4250, 4027
7560 16:37:14.969575 300 : 4250, 4027
7561 16:37:14.969663 304 : 4253, 4029
7562 16:37:14.972961 308 : 4363, 4139
7563 16:37:14.973057 312 : 4250, 4027
7564 16:37:14.976356 316 : 4250, 4026
7565 16:37:14.976452 320 : 4250, 4027
7566 16:37:14.979146 324 : 4363, 4139
7567 16:37:14.979214 328 : 4360, 4138
7568 16:37:14.982457 332 : 4250, 4026
7569 16:37:14.982548 336 : 4361, 4043
7570 16:37:14.985827 340 : 4253, 2366
7571 16:37:14.985901 344 : 4252, 56
7572 16:37:14.985962
7573 16:37:14.989254 MIOCK jitter meter ch=0
7574 16:37:14.989339
7575 16:37:14.992660 1T = (344-92) = 252 dly cells
7576 16:37:14.996091 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7577 16:37:14.996206 ==
7578 16:37:14.999512 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 16:37:15.005764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 16:37:15.005861 ==
7581 16:37:15.009222 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7582 16:37:15.016041 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7583 16:37:15.019142 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7584 16:37:15.025438 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7585 16:37:15.033435 [CA 0] Center 43 (13~74) winsize 62
7586 16:37:15.036620 [CA 1] Center 43 (13~73) winsize 61
7587 16:37:15.040022 [CA 2] Center 38 (9~68) winsize 60
7588 16:37:15.043932 [CA 3] Center 38 (9~68) winsize 60
7589 16:37:15.046630 [CA 4] Center 36 (7~66) winsize 60
7590 16:37:15.049912 [CA 5] Center 35 (6~65) winsize 60
7591 16:37:15.050022
7592 16:37:15.053245 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7593 16:37:15.053350
7594 16:37:15.056664 [CATrainingPosCal] consider 1 rank data
7595 16:37:15.059859 u2DelayCellTimex100 = 258/100 ps
7596 16:37:15.066622 CA0 delay=43 (13~74),Diff = 8 PI (30 cell)
7597 16:37:15.069925 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7598 16:37:15.073277 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7599 16:37:15.076717 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7600 16:37:15.079577 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7601 16:37:15.083019 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7602 16:37:15.083187
7603 16:37:15.086476 CA PerBit enable=1, Macro0, CA PI delay=35
7604 16:37:15.086585
7605 16:37:15.089293 [CBTSetCACLKResult] CA Dly = 35
7606 16:37:15.092615 CS Dly: 12 (0~43)
7607 16:37:15.096137 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7608 16:37:15.099576 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7609 16:37:15.099668 ==
7610 16:37:15.102944 Dram Type= 6, Freq= 0, CH_0, rank 1
7611 16:37:15.109051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 16:37:15.109160 ==
7613 16:37:15.112282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7614 16:37:15.119257 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7615 16:37:15.122038 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7616 16:37:15.128507 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7617 16:37:15.137179 [CA 0] Center 43 (13~74) winsize 62
7618 16:37:15.140448 [CA 1] Center 44 (14~74) winsize 61
7619 16:37:15.143540 [CA 2] Center 39 (9~69) winsize 61
7620 16:37:15.147041 [CA 3] Center 38 (9~68) winsize 60
7621 16:37:15.150132 [CA 4] Center 36 (7~66) winsize 60
7622 16:37:15.153638 [CA 5] Center 36 (7~66) winsize 60
7623 16:37:15.153785
7624 16:37:15.156908 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7625 16:37:15.157070
7626 16:37:15.163170 [CATrainingPosCal] consider 2 rank data
7627 16:37:15.163303 u2DelayCellTimex100 = 258/100 ps
7628 16:37:15.169887 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7629 16:37:15.173370 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7630 16:37:15.176692 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7631 16:37:15.180194 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7632 16:37:15.183695 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7633 16:37:15.186582 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7634 16:37:15.186905
7635 16:37:15.189939 CA PerBit enable=1, Macro0, CA PI delay=36
7636 16:37:15.190369
7637 16:37:15.193207 [CBTSetCACLKResult] CA Dly = 36
7638 16:37:15.196592 CS Dly: 12 (0~43)
7639 16:37:15.199844 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7640 16:37:15.203287 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7641 16:37:15.203790
7642 16:37:15.206548 ----->DramcWriteLeveling(PI) begin...
7643 16:37:15.207020 ==
7644 16:37:15.209900 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 16:37:15.216588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 16:37:15.217150 ==
7647 16:37:15.219243 Write leveling (Byte 0): 35 => 35
7648 16:37:15.222739 Write leveling (Byte 1): 27 => 27
7649 16:37:15.226229 DramcWriteLeveling(PI) end<-----
7650 16:37:15.226701
7651 16:37:15.227044 ==
7652 16:37:15.229564 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 16:37:15.233169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 16:37:15.233585 ==
7655 16:37:15.236620 [Gating] SW mode calibration
7656 16:37:15.242772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7657 16:37:15.249626 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7658 16:37:15.252850 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 16:37:15.255890 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 16:37:15.262610 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 16:37:15.265931 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7662 16:37:15.269379 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7663 16:37:15.275373 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7664 16:37:15.278959 1 4 24 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
7665 16:37:15.282393 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 16:37:15.288602 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7667 16:37:15.291912 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7668 16:37:15.295502 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7669 16:37:15.302402 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7670 16:37:15.305039 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7671 16:37:15.308592 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7672 16:37:15.315244 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7673 16:37:15.318436 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 16:37:15.321857 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 16:37:15.328491 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 16:37:15.331574 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7677 16:37:15.335029 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7678 16:37:15.341239 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7679 16:37:15.344694 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7680 16:37:15.348330 1 6 24 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
7681 16:37:15.354655 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 16:37:15.357830 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 16:37:15.361180 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 16:37:15.368023 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 16:37:15.371455 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7686 16:37:15.374574 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7687 16:37:15.380883 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7688 16:37:15.384491 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7689 16:37:15.387968 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 16:37:15.394199 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 16:37:15.397596 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 16:37:15.400987 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 16:37:15.407790 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 16:37:15.410489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 16:37:15.414471 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 16:37:15.417205 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 16:37:15.423865 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 16:37:15.427314 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 16:37:15.434215 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 16:37:15.436840 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7701 16:37:15.440465 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7702 16:37:15.447196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7703 16:37:15.450598 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 16:37:15.453518 Total UI for P1: 0, mck2ui 16
7705 16:37:15.457007 best dqsien dly found for B0: ( 1, 9, 12)
7706 16:37:15.460284 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7707 16:37:15.463598 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7708 16:37:15.467041 Total UI for P1: 0, mck2ui 16
7709 16:37:15.470228 best dqsien dly found for B1: ( 1, 9, 22)
7710 16:37:15.473385 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7711 16:37:15.480406 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7712 16:37:15.480830
7713 16:37:15.483772 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7714 16:37:15.487013 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7715 16:37:15.490035 [Gating] SW calibration Done
7716 16:37:15.490537 ==
7717 16:37:15.493239 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 16:37:15.496398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 16:37:15.496824 ==
7720 16:37:15.499730 RX Vref Scan: 0
7721 16:37:15.500155
7722 16:37:15.500584 RX Vref 0 -> 0, step: 1
7723 16:37:15.500996
7724 16:37:15.503133 RX Delay 0 -> 252, step: 8
7725 16:37:15.506515 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7726 16:37:15.509437 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7727 16:37:15.516169 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7728 16:37:15.519659 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7729 16:37:15.522424 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7730 16:37:15.525826 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7731 16:37:15.532222 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7732 16:37:15.535645 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7733 16:37:15.539109 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7734 16:37:15.542518 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7735 16:37:15.545288 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7736 16:37:15.552112 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7737 16:37:15.555541 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7738 16:37:15.559090 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7739 16:37:15.562620 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7740 16:37:15.568436 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7741 16:37:15.568517 ==
7742 16:37:15.571683 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 16:37:15.575221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 16:37:15.575328 ==
7745 16:37:15.575455 DQS Delay:
7746 16:37:15.578569 DQS0 = 0, DQS1 = 0
7747 16:37:15.578646 DQM Delay:
7748 16:37:15.581781 DQM0 = 133, DQM1 = 126
7749 16:37:15.581853 DQ Delay:
7750 16:37:15.584684 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7751 16:37:15.587982 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7752 16:37:15.591318 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7753 16:37:15.594666 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7754 16:37:15.594747
7755 16:37:15.598136
7756 16:37:15.598239 ==
7757 16:37:15.601224 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 16:37:15.604469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 16:37:15.604550 ==
7760 16:37:15.604614
7761 16:37:15.604686
7762 16:37:15.607751 TX Vref Scan disable
7763 16:37:15.607832 == TX Byte 0 ==
7764 16:37:15.614423 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7765 16:37:15.617747 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7766 16:37:15.617856 == TX Byte 1 ==
7767 16:37:15.624533 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7768 16:37:15.627977 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7769 16:37:15.628058 ==
7770 16:37:15.630823 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 16:37:15.634596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 16:37:15.634676 ==
7773 16:37:15.648265
7774 16:37:15.651796 TX Vref early break, caculate TX vref
7775 16:37:15.654986 TX Vref=16, minBit 4, minWin=22, winSum=369
7776 16:37:15.658481 TX Vref=18, minBit 4, minWin=22, winSum=379
7777 16:37:15.661758 TX Vref=20, minBit 1, minWin=23, winSum=391
7778 16:37:15.665238 TX Vref=22, minBit 3, minWin=24, winSum=402
7779 16:37:15.668430 TX Vref=24, minBit 1, minWin=24, winSum=403
7780 16:37:15.675157 TX Vref=26, minBit 0, minWin=25, winSum=412
7781 16:37:15.678487 TX Vref=28, minBit 4, minWin=24, winSum=416
7782 16:37:15.681181 TX Vref=30, minBit 0, minWin=25, winSum=411
7783 16:37:15.684575 TX Vref=32, minBit 7, minWin=23, winSum=399
7784 16:37:15.687892 TX Vref=34, minBit 4, minWin=23, winSum=386
7785 16:37:15.694803 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 26
7786 16:37:15.694906
7787 16:37:15.698273 Final TX Range 0 Vref 26
7788 16:37:15.698382
7789 16:37:15.698471 ==
7790 16:37:15.701426 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 16:37:15.704846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 16:37:15.704933 ==
7793 16:37:15.704997
7794 16:37:15.705070
7795 16:37:15.708087 TX Vref Scan disable
7796 16:37:15.714636 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7797 16:37:15.714716 == TX Byte 0 ==
7798 16:37:15.717881 u2DelayCellOfst[0]=15 cells (4 PI)
7799 16:37:15.721324 u2DelayCellOfst[1]=18 cells (5 PI)
7800 16:37:15.724094 u2DelayCellOfst[2]=15 cells (4 PI)
7801 16:37:15.727704 u2DelayCellOfst[3]=18 cells (5 PI)
7802 16:37:15.730986 u2DelayCellOfst[4]=7 cells (2 PI)
7803 16:37:15.734285 u2DelayCellOfst[5]=0 cells (0 PI)
7804 16:37:15.737608 u2DelayCellOfst[6]=22 cells (6 PI)
7805 16:37:15.740798 u2DelayCellOfst[7]=22 cells (6 PI)
7806 16:37:15.744030 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7807 16:37:15.747442 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7808 16:37:15.750786 == TX Byte 1 ==
7809 16:37:15.754273 u2DelayCellOfst[8]=0 cells (0 PI)
7810 16:37:15.756987 u2DelayCellOfst[9]=3 cells (1 PI)
7811 16:37:15.760361 u2DelayCellOfst[10]=7 cells (2 PI)
7812 16:37:15.760442 u2DelayCellOfst[11]=3 cells (1 PI)
7813 16:37:15.763685 u2DelayCellOfst[12]=15 cells (4 PI)
7814 16:37:15.767175 u2DelayCellOfst[13]=15 cells (4 PI)
7815 16:37:15.770535 u2DelayCellOfst[14]=15 cells (4 PI)
7816 16:37:15.773846 u2DelayCellOfst[15]=15 cells (4 PI)
7817 16:37:15.780008 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7818 16:37:15.783449 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7819 16:37:15.783530 DramC Write-DBI on
7820 16:37:15.786942 ==
7821 16:37:15.790199 Dram Type= 6, Freq= 0, CH_0, rank 0
7822 16:37:15.793435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7823 16:37:15.793516 ==
7824 16:37:15.793579
7825 16:37:15.793638
7826 16:37:15.796731 TX Vref Scan disable
7827 16:37:15.796812 == TX Byte 0 ==
7828 16:37:15.803411 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7829 16:37:15.803492 == TX Byte 1 ==
7830 16:37:15.806882 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7831 16:37:15.809571 DramC Write-DBI off
7832 16:37:15.809651
7833 16:37:15.809716 [DATLAT]
7834 16:37:15.812946 Freq=1600, CH0 RK0
7835 16:37:15.813026
7836 16:37:15.813089 DATLAT Default: 0xf
7837 16:37:15.816273 0, 0xFFFF, sum = 0
7838 16:37:15.816356 1, 0xFFFF, sum = 0
7839 16:37:15.819626 2, 0xFFFF, sum = 0
7840 16:37:15.819707 3, 0xFFFF, sum = 0
7841 16:37:15.822887 4, 0xFFFF, sum = 0
7842 16:37:15.826207 5, 0xFFFF, sum = 0
7843 16:37:15.826289 6, 0xFFFF, sum = 0
7844 16:37:15.829593 7, 0xFFFF, sum = 0
7845 16:37:15.829676 8, 0xFFFF, sum = 0
7846 16:37:15.832937 9, 0xFFFF, sum = 0
7847 16:37:15.833019 10, 0xFFFF, sum = 0
7848 16:37:15.836381 11, 0xFFFF, sum = 0
7849 16:37:15.836462 12, 0xFFFF, sum = 0
7850 16:37:15.839186 13, 0xFFFF, sum = 0
7851 16:37:15.839267 14, 0x0, sum = 1
7852 16:37:15.842479 15, 0x0, sum = 2
7853 16:37:15.842561 16, 0x0, sum = 3
7854 16:37:15.846056 17, 0x0, sum = 4
7855 16:37:15.846137 best_step = 15
7856 16:37:15.846240
7857 16:37:15.846300 ==
7858 16:37:15.849047 Dram Type= 6, Freq= 0, CH_0, rank 0
7859 16:37:15.855846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7860 16:37:15.855927 ==
7861 16:37:15.855990 RX Vref Scan: 1
7862 16:37:15.856049
7863 16:37:15.859306 Set Vref Range= 24 -> 127
7864 16:37:15.859387
7865 16:37:15.862929 RX Vref 24 -> 127, step: 1
7866 16:37:15.863137
7867 16:37:15.863244 RX Delay 11 -> 252, step: 4
7868 16:37:15.863304
7869 16:37:15.865556 Set Vref, RX VrefLevel [Byte0]: 24
7870 16:37:15.868847 [Byte1]: 24
7871 16:37:15.873034
7872 16:37:15.873114 Set Vref, RX VrefLevel [Byte0]: 25
7873 16:37:15.876310 [Byte1]: 25
7874 16:37:15.881048
7875 16:37:15.881144 Set Vref, RX VrefLevel [Byte0]: 26
7876 16:37:15.883854 [Byte1]: 26
7877 16:37:15.888211
7878 16:37:15.888291 Set Vref, RX VrefLevel [Byte0]: 27
7879 16:37:15.891631 [Byte1]: 27
7880 16:37:15.896348
7881 16:37:15.896428 Set Vref, RX VrefLevel [Byte0]: 28
7882 16:37:15.898984 [Byte1]: 28
7883 16:37:15.903775
7884 16:37:15.903879 Set Vref, RX VrefLevel [Byte0]: 29
7885 16:37:15.907161 [Byte1]: 29
7886 16:37:15.911265
7887 16:37:15.911371 Set Vref, RX VrefLevel [Byte0]: 30
7888 16:37:15.914731 [Byte1]: 30
7889 16:37:15.918814
7890 16:37:15.918898 Set Vref, RX VrefLevel [Byte0]: 31
7891 16:37:15.922158 [Byte1]: 31
7892 16:37:15.926194
7893 16:37:15.926285 Set Vref, RX VrefLevel [Byte0]: 32
7894 16:37:15.929632 [Byte1]: 32
7895 16:37:15.934411
7896 16:37:15.934496 Set Vref, RX VrefLevel [Byte0]: 33
7897 16:37:15.937213 [Byte1]: 33
7898 16:37:15.941981
7899 16:37:15.942054 Set Vref, RX VrefLevel [Byte0]: 34
7900 16:37:15.944699 [Byte1]: 34
7901 16:37:15.949323
7902 16:37:15.949425 Set Vref, RX VrefLevel [Byte0]: 35
7903 16:37:15.952694 [Byte1]: 35
7904 16:37:15.956780
7905 16:37:15.956849 Set Vref, RX VrefLevel [Byte0]: 36
7906 16:37:15.960010 [Byte1]: 36
7907 16:37:15.964898
7908 16:37:15.964966 Set Vref, RX VrefLevel [Byte0]: 37
7909 16:37:15.967576 [Byte1]: 37
7910 16:37:15.972079
7911 16:37:15.972159 Set Vref, RX VrefLevel [Byte0]: 38
7912 16:37:15.975348 [Byte1]: 38
7913 16:37:15.979391
7914 16:37:15.979470 Set Vref, RX VrefLevel [Byte0]: 39
7915 16:37:15.982878 [Byte1]: 39
7916 16:37:15.987052
7917 16:37:15.987131 Set Vref, RX VrefLevel [Byte0]: 40
7918 16:37:15.990499 [Byte1]: 40
7919 16:37:15.994744
7920 16:37:15.994824 Set Vref, RX VrefLevel [Byte0]: 41
7921 16:37:15.998352 [Byte1]: 41
7922 16:37:16.002431
7923 16:37:16.002511 Set Vref, RX VrefLevel [Byte0]: 42
7924 16:37:16.005715 [Byte1]: 42
7925 16:37:16.010321
7926 16:37:16.010401 Set Vref, RX VrefLevel [Byte0]: 43
7927 16:37:16.013412 [Byte1]: 43
7928 16:37:16.017593
7929 16:37:16.017674 Set Vref, RX VrefLevel [Byte0]: 44
7930 16:37:16.021453 [Byte1]: 44
7931 16:37:16.025449
7932 16:37:16.025531 Set Vref, RX VrefLevel [Byte0]: 45
7933 16:37:16.028824 [Byte1]: 45
7934 16:37:16.033311
7935 16:37:16.033390 Set Vref, RX VrefLevel [Byte0]: 46
7936 16:37:16.036566 [Byte1]: 46
7937 16:37:16.040676
7938 16:37:16.040774 Set Vref, RX VrefLevel [Byte0]: 47
7939 16:37:16.044056 [Byte1]: 47
7940 16:37:16.048230
7941 16:37:16.048309 Set Vref, RX VrefLevel [Byte0]: 48
7942 16:37:16.051748 [Byte1]: 48
7943 16:37:16.055957
7944 16:37:16.056032 Set Vref, RX VrefLevel [Byte0]: 49
7945 16:37:16.059133 [Byte1]: 49
7946 16:37:16.063790
7947 16:37:16.063860 Set Vref, RX VrefLevel [Byte0]: 50
7948 16:37:16.067141 [Byte1]: 50
7949 16:37:16.071441
7950 16:37:16.071515 Set Vref, RX VrefLevel [Byte0]: 51
7951 16:37:16.074102 [Byte1]: 51
7952 16:37:16.078608
7953 16:37:16.078680 Set Vref, RX VrefLevel [Byte0]: 52
7954 16:37:16.082141 [Byte1]: 52
7955 16:37:16.086179
7956 16:37:16.086262 Set Vref, RX VrefLevel [Byte0]: 53
7957 16:37:16.089746 [Byte1]: 53
7958 16:37:16.093746
7959 16:37:16.093824 Set Vref, RX VrefLevel [Byte0]: 54
7960 16:37:16.097172 [Byte1]: 54
7961 16:37:16.101958
7962 16:37:16.102036 Set Vref, RX VrefLevel [Byte0]: 55
7963 16:37:16.104721 [Byte1]: 55
7964 16:37:16.109477
7965 16:37:16.109561 Set Vref, RX VrefLevel [Byte0]: 56
7966 16:37:16.112155 [Byte1]: 56
7967 16:37:16.116505
7968 16:37:16.116585 Set Vref, RX VrefLevel [Byte0]: 57
7969 16:37:16.119763 [Byte1]: 57
7970 16:37:16.124483
7971 16:37:16.124573 Set Vref, RX VrefLevel [Byte0]: 58
7972 16:37:16.127877 [Byte1]: 58
7973 16:37:16.131832
7974 16:37:16.131916 Set Vref, RX VrefLevel [Byte0]: 59
7975 16:37:16.135180 [Byte1]: 59
7976 16:37:16.139895
7977 16:37:16.139980 Set Vref, RX VrefLevel [Byte0]: 60
7978 16:37:16.143133 [Byte1]: 60
7979 16:37:16.147221
7980 16:37:16.147293 Set Vref, RX VrefLevel [Byte0]: 61
7981 16:37:16.150424 [Byte1]: 61
7982 16:37:16.154603
7983 16:37:16.154680 Set Vref, RX VrefLevel [Byte0]: 62
7984 16:37:16.157939 [Byte1]: 62
7985 16:37:16.162740
7986 16:37:16.162826 Set Vref, RX VrefLevel [Byte0]: 63
7987 16:37:16.165380 [Byte1]: 63
7988 16:37:16.170153
7989 16:37:16.170256 Set Vref, RX VrefLevel [Byte0]: 64
7990 16:37:16.173824 [Byte1]: 64
7991 16:37:16.177724
7992 16:37:16.177897 Set Vref, RX VrefLevel [Byte0]: 65
7993 16:37:16.181090 [Byte1]: 65
7994 16:37:16.185092
7995 16:37:16.185173 Set Vref, RX VrefLevel [Byte0]: 66
7996 16:37:16.188564 [Byte1]: 66
7997 16:37:16.193187
7998 16:37:16.193267 Set Vref, RX VrefLevel [Byte0]: 67
7999 16:37:16.195941 [Byte1]: 67
8000 16:37:16.200807
8001 16:37:16.200889 Set Vref, RX VrefLevel [Byte0]: 68
8002 16:37:16.204033 [Byte1]: 68
8003 16:37:16.208118
8004 16:37:16.208199 Set Vref, RX VrefLevel [Byte0]: 69
8005 16:37:16.211432 [Byte1]: 69
8006 16:37:16.215687
8007 16:37:16.215766 Set Vref, RX VrefLevel [Byte0]: 70
8008 16:37:16.218901 [Byte1]: 70
8009 16:37:16.223612
8010 16:37:16.223693 Set Vref, RX VrefLevel [Byte0]: 71
8011 16:37:16.227026 [Byte1]: 71
8012 16:37:16.231042
8013 16:37:16.231124 Set Vref, RX VrefLevel [Byte0]: 72
8014 16:37:16.234325 [Byte1]: 72
8015 16:37:16.238360
8016 16:37:16.238441 Set Vref, RX VrefLevel [Byte0]: 73
8017 16:37:16.241648 [Byte1]: 73
8018 16:37:16.246394
8019 16:37:16.246474 Set Vref, RX VrefLevel [Byte0]: 74
8020 16:37:16.249587 [Byte1]: 74
8021 16:37:16.253726
8022 16:37:16.253808 Set Vref, RX VrefLevel [Byte0]: 75
8023 16:37:16.257078 [Byte1]: 75
8024 16:37:16.261651
8025 16:37:16.261731 Set Vref, RX VrefLevel [Byte0]: 76
8026 16:37:16.264976 [Byte1]: 76
8027 16:37:16.268938
8028 16:37:16.269018 Set Vref, RX VrefLevel [Byte0]: 77
8029 16:37:16.272304 [Byte1]: 77
8030 16:37:16.276494
8031 16:37:16.276573 Set Vref, RX VrefLevel [Byte0]: 78
8032 16:37:16.279926 [Byte1]: 78
8033 16:37:16.284081
8034 16:37:16.284163 Set Vref, RX VrefLevel [Byte0]: 79
8035 16:37:16.287488 [Byte1]: 79
8036 16:37:16.292026
8037 16:37:16.292106 Set Vref, RX VrefLevel [Byte0]: 80
8038 16:37:16.295296 [Byte1]: 80
8039 16:37:16.299470
8040 16:37:16.299549 Final RX Vref Byte 0 = 62 to rank0
8041 16:37:16.302988 Final RX Vref Byte 1 = 57 to rank0
8042 16:37:16.305822 Final RX Vref Byte 0 = 62 to rank1
8043 16:37:16.309118 Final RX Vref Byte 1 = 57 to rank1==
8044 16:37:16.312493 Dram Type= 6, Freq= 0, CH_0, rank 0
8045 16:37:16.318848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 16:37:16.318925 ==
8047 16:37:16.318987 DQS Delay:
8048 16:37:16.322293 DQS0 = 0, DQS1 = 0
8049 16:37:16.322376 DQM Delay:
8050 16:37:16.325429 DQM0 = 132, DQM1 = 123
8051 16:37:16.325519 DQ Delay:
8052 16:37:16.328823 DQ0 =130, DQ1 =132, DQ2 =130, DQ3 =132
8053 16:37:16.332181 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8054 16:37:16.335466 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118
8055 16:37:16.339405 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8056 16:37:16.339489
8057 16:37:16.339554
8058 16:37:16.339627
8059 16:37:16.342042 [DramC_TX_OE_Calibration] TA2
8060 16:37:16.345431 Original DQ_B0 (3 6) =30, OEN = 27
8061 16:37:16.348765 Original DQ_B1 (3 6) =30, OEN = 27
8062 16:37:16.352124 24, 0x0, End_B0=24 End_B1=24
8063 16:37:16.355877 25, 0x0, End_B0=25 End_B1=25
8064 16:37:16.355983 26, 0x0, End_B0=26 End_B1=26
8065 16:37:16.358472 27, 0x0, End_B0=27 End_B1=27
8066 16:37:16.361942 28, 0x0, End_B0=28 End_B1=28
8067 16:37:16.365345 29, 0x0, End_B0=29 End_B1=29
8068 16:37:16.365460 30, 0x0, End_B0=30 End_B1=30
8069 16:37:16.368721 31, 0x4141, End_B0=30 End_B1=30
8070 16:37:16.372084 Byte0 end_step=30 best_step=27
8071 16:37:16.375324 Byte1 end_step=30 best_step=27
8072 16:37:16.378764 Byte0 TX OE(2T, 0.5T) = (3, 3)
8073 16:37:16.381454 Byte1 TX OE(2T, 0.5T) = (3, 3)
8074 16:37:16.381553
8075 16:37:16.381623
8076 16:37:16.388167 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8077 16:37:16.391400 CH0 RK0: MR19=303, MR18=1F10
8078 16:37:16.398121 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8079 16:37:16.398266
8080 16:37:16.401646 ----->DramcWriteLeveling(PI) begin...
8081 16:37:16.401720 ==
8082 16:37:16.404956 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 16:37:16.408337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 16:37:16.408408 ==
8085 16:37:16.411133 Write leveling (Byte 0): 34 => 34
8086 16:37:16.414668 Write leveling (Byte 1): 27 => 27
8087 16:37:16.418270 DramcWriteLeveling(PI) end<-----
8088 16:37:16.418356
8089 16:37:16.418420 ==
8090 16:37:16.421031 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 16:37:16.427717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 16:37:16.427798 ==
8093 16:37:16.427861 [Gating] SW mode calibration
8094 16:37:16.437703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8095 16:37:16.441093 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8096 16:37:16.444440 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 16:37:16.450903 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 16:37:16.454035 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 16:37:16.460573 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8100 16:37:16.464429 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8101 16:37:16.467663 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
8102 16:37:16.473562 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8103 16:37:16.477513 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 16:37:16.480680 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 16:37:16.486927 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 16:37:16.490424 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 16:37:16.493679 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8108 16:37:16.499872 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8109 16:37:16.503313 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8110 16:37:16.506939 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8111 16:37:16.513062 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 16:37:16.516494 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 16:37:16.519927 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 16:37:16.525993 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 16:37:16.529598 1 6 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8116 16:37:16.532845 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8117 16:37:16.539532 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
8118 16:37:16.542367 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 16:37:16.545942 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 16:37:16.552466 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 16:37:16.555774 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 16:37:16.559267 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8123 16:37:16.565839 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8124 16:37:16.569084 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8125 16:37:16.572653 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8126 16:37:16.578981 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 16:37:16.582027 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 16:37:16.585848 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 16:37:16.592028 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 16:37:16.595392 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 16:37:16.598529 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 16:37:16.605240 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 16:37:16.608504 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 16:37:16.612087 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 16:37:16.618180 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 16:37:16.621606 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 16:37:16.625092 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 16:37:16.631343 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 16:37:16.634677 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8140 16:37:16.638077 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8141 16:37:16.641284 Total UI for P1: 0, mck2ui 16
8142 16:37:16.644689 best dqsien dly found for B0: ( 1, 9, 12)
8143 16:37:16.651516 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8144 16:37:16.654927 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 16:37:16.658449 Total UI for P1: 0, mck2ui 16
8146 16:37:16.661234 best dqsien dly found for B1: ( 1, 9, 20)
8147 16:37:16.664597 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8148 16:37:16.668083 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8149 16:37:16.668167
8150 16:37:16.670901 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8151 16:37:16.674273 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8152 16:37:16.677475 [Gating] SW calibration Done
8153 16:37:16.677567 ==
8154 16:37:16.680649 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 16:37:16.687343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 16:37:16.687449 ==
8157 16:37:16.687541 RX Vref Scan: 0
8158 16:37:16.687636
8159 16:37:16.690645 RX Vref 0 -> 0, step: 1
8160 16:37:16.690717
8161 16:37:16.693890 RX Delay 0 -> 252, step: 8
8162 16:37:16.697045 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8163 16:37:16.700712 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8164 16:37:16.703808 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8165 16:37:16.710338 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8166 16:37:16.714094 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8167 16:37:16.716623 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8168 16:37:16.720068 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8169 16:37:16.723538 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8170 16:37:16.730317 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8171 16:37:16.733681 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8172 16:37:16.737071 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8173 16:37:16.740423 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8174 16:37:16.743693 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8175 16:37:16.750258 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8176 16:37:16.753019 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8177 16:37:16.756387 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8178 16:37:16.756461 ==
8179 16:37:16.759851 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 16:37:16.763447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 16:37:16.766845 ==
8182 16:37:16.766927 DQS Delay:
8183 16:37:16.766992 DQS0 = 0, DQS1 = 0
8184 16:37:16.770195 DQM Delay:
8185 16:37:16.770277 DQM0 = 132, DQM1 = 129
8186 16:37:16.772890 DQ Delay:
8187 16:37:16.776257 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8188 16:37:16.779688 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8189 16:37:16.783115 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8190 16:37:16.786295 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8191 16:37:16.786377
8192 16:37:16.786441
8193 16:37:16.786500 ==
8194 16:37:16.789694 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 16:37:16.793019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 16:37:16.793130 ==
8197 16:37:16.796271
8198 16:37:16.796352
8199 16:37:16.796422 TX Vref Scan disable
8200 16:37:16.799640 == TX Byte 0 ==
8201 16:37:16.803112 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8202 16:37:16.805838 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8203 16:37:16.809619 == TX Byte 1 ==
8204 16:37:16.812959 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8205 16:37:16.816180 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8206 16:37:16.816283 ==
8207 16:37:16.819399 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 16:37:16.825529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 16:37:16.825633 ==
8210 16:37:16.838170
8211 16:37:16.841627 TX Vref early break, caculate TX vref
8212 16:37:16.845061 TX Vref=16, minBit 1, minWin=22, winSum=375
8213 16:37:16.848334 TX Vref=18, minBit 1, minWin=22, winSum=385
8214 16:37:16.851676 TX Vref=20, minBit 1, minWin=23, winSum=388
8215 16:37:16.855116 TX Vref=22, minBit 1, minWin=23, winSum=397
8216 16:37:16.858009 TX Vref=24, minBit 1, minWin=24, winSum=408
8217 16:37:16.865054 TX Vref=26, minBit 1, minWin=24, winSum=412
8218 16:37:16.868507 TX Vref=28, minBit 4, minWin=24, winSum=406
8219 16:37:16.871331 TX Vref=30, minBit 0, minWin=24, winSum=403
8220 16:37:16.874776 TX Vref=32, minBit 7, minWin=23, winSum=393
8221 16:37:16.878271 TX Vref=34, minBit 1, minWin=22, winSum=381
8222 16:37:16.884954 [TxChooseVref] Worse bit 1, Min win 24, Win sum 412, Final Vref 26
8223 16:37:16.885058
8224 16:37:16.888345 Final TX Range 0 Vref 26
8225 16:37:16.888451
8226 16:37:16.888545 ==
8227 16:37:16.891083 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 16:37:16.894961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 16:37:16.895041 ==
8230 16:37:16.895114
8231 16:37:16.895173
8232 16:37:16.898278 TX Vref Scan disable
8233 16:37:16.904341 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8234 16:37:16.904492 == TX Byte 0 ==
8235 16:37:16.907662 u2DelayCellOfst[0]=11 cells (3 PI)
8236 16:37:16.911071 u2DelayCellOfst[1]=15 cells (4 PI)
8237 16:37:16.914340 u2DelayCellOfst[2]=11 cells (3 PI)
8238 16:37:16.917495 u2DelayCellOfst[3]=15 cells (4 PI)
8239 16:37:16.920911 u2DelayCellOfst[4]=7 cells (2 PI)
8240 16:37:16.924168 u2DelayCellOfst[5]=0 cells (0 PI)
8241 16:37:16.927647 u2DelayCellOfst[6]=15 cells (4 PI)
8242 16:37:16.931071 u2DelayCellOfst[7]=18 cells (5 PI)
8243 16:37:16.934120 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8244 16:37:16.937850 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8245 16:37:16.941086 == TX Byte 1 ==
8246 16:37:16.944522 u2DelayCellOfst[8]=0 cells (0 PI)
8247 16:37:16.947305 u2DelayCellOfst[9]=3 cells (1 PI)
8248 16:37:16.947382 u2DelayCellOfst[10]=7 cells (2 PI)
8249 16:37:16.950834 u2DelayCellOfst[11]=3 cells (1 PI)
8250 16:37:16.954082 u2DelayCellOfst[12]=11 cells (3 PI)
8251 16:37:16.957456 u2DelayCellOfst[13]=11 cells (3 PI)
8252 16:37:16.960912 u2DelayCellOfst[14]=18 cells (5 PI)
8253 16:37:16.964249 u2DelayCellOfst[15]=11 cells (3 PI)
8254 16:37:16.970578 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8255 16:37:16.974120 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8256 16:37:16.974247 DramC Write-DBI on
8257 16:37:16.974316 ==
8258 16:37:16.976914 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 16:37:16.983858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 16:37:16.983969 ==
8261 16:37:16.984067
8262 16:37:16.984158
8263 16:37:16.984246 TX Vref Scan disable
8264 16:37:16.987943 == TX Byte 0 ==
8265 16:37:16.991358 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8266 16:37:16.994707 == TX Byte 1 ==
8267 16:37:16.998126 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8268 16:37:17.001388 DramC Write-DBI off
8269 16:37:17.001503
8270 16:37:17.001597 [DATLAT]
8271 16:37:17.001685 Freq=1600, CH0 RK1
8272 16:37:17.001789
8273 16:37:17.004565 DATLAT Default: 0xf
8274 16:37:17.004678 0, 0xFFFF, sum = 0
8275 16:37:17.007657 1, 0xFFFF, sum = 0
8276 16:37:17.011112 2, 0xFFFF, sum = 0
8277 16:37:17.011223 3, 0xFFFF, sum = 0
8278 16:37:17.014017 4, 0xFFFF, sum = 0
8279 16:37:17.014126 5, 0xFFFF, sum = 0
8280 16:37:17.017417 6, 0xFFFF, sum = 0
8281 16:37:17.017536 7, 0xFFFF, sum = 0
8282 16:37:17.020885 8, 0xFFFF, sum = 0
8283 16:37:17.020967 9, 0xFFFF, sum = 0
8284 16:37:17.024099 10, 0xFFFF, sum = 0
8285 16:37:17.024209 11, 0xFFFF, sum = 0
8286 16:37:17.027273 12, 0xFFFF, sum = 0
8287 16:37:17.027356 13, 0xFFFF, sum = 0
8288 16:37:17.030607 14, 0x0, sum = 1
8289 16:37:17.030689 15, 0x0, sum = 2
8290 16:37:17.033965 16, 0x0, sum = 3
8291 16:37:17.034046 17, 0x0, sum = 4
8292 16:37:17.037433 best_step = 15
8293 16:37:17.037512
8294 16:37:17.037576 ==
8295 16:37:17.040809 Dram Type= 6, Freq= 0, CH_0, rank 1
8296 16:37:17.043963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 16:37:17.044049 ==
8298 16:37:17.047121 RX Vref Scan: 0
8299 16:37:17.047201
8300 16:37:17.047265 RX Vref 0 -> 0, step: 1
8301 16:37:17.047324
8302 16:37:17.050068 RX Delay 11 -> 252, step: 4
8303 16:37:17.056890 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8304 16:37:17.060155 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8305 16:37:17.063446 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8306 16:37:17.066909 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8307 16:37:17.073539 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8308 16:37:17.076323 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8309 16:37:17.079862 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8310 16:37:17.083281 iDelay=195, Bit 7, Center 140 (91 ~ 190) 100
8311 16:37:17.086634 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8312 16:37:17.092838 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8313 16:37:17.096220 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8314 16:37:17.099573 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8315 16:37:17.103109 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8316 16:37:17.106320 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8317 16:37:17.112911 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8318 16:37:17.116154 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8319 16:37:17.116236 ==
8320 16:37:17.119455 Dram Type= 6, Freq= 0, CH_0, rank 1
8321 16:37:17.122354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 16:37:17.122437 ==
8323 16:37:17.125934 DQS Delay:
8324 16:37:17.126016 DQS0 = 0, DQS1 = 0
8325 16:37:17.129450 DQM Delay:
8326 16:37:17.129532 DQM0 = 130, DQM1 = 125
8327 16:37:17.129598 DQ Delay:
8328 16:37:17.132738 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8329 16:37:17.139187 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8330 16:37:17.142528 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8331 16:37:17.145990 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8332 16:37:17.146070
8333 16:37:17.146134
8334 16:37:17.146237
8335 16:37:17.148609 [DramC_TX_OE_Calibration] TA2
8336 16:37:17.152557 Original DQ_B0 (3 6) =30, OEN = 27
8337 16:37:17.155206 Original DQ_B1 (3 6) =30, OEN = 27
8338 16:37:17.155295 24, 0x0, End_B0=24 End_B1=24
8339 16:37:17.158507 25, 0x0, End_B0=25 End_B1=25
8340 16:37:17.161958 26, 0x0, End_B0=26 End_B1=26
8341 16:37:17.165113 27, 0x0, End_B0=27 End_B1=27
8342 16:37:17.168884 28, 0x0, End_B0=28 End_B1=28
8343 16:37:17.168966 29, 0x0, End_B0=29 End_B1=29
8344 16:37:17.171990 30, 0x0, End_B0=30 End_B1=30
8345 16:37:17.175347 31, 0x4141, End_B0=30 End_B1=30
8346 16:37:17.178840 Byte0 end_step=30 best_step=27
8347 16:37:17.182277 Byte1 end_step=30 best_step=27
8348 16:37:17.185041 Byte0 TX OE(2T, 0.5T) = (3, 3)
8349 16:37:17.185126 Byte1 TX OE(2T, 0.5T) = (3, 3)
8350 16:37:17.185194
8351 16:37:17.188382
8352 16:37:17.195317 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8353 16:37:17.198614 CH0 RK1: MR19=303, MR18=1D00
8354 16:37:17.204856 CH0_RK1: MR19=0x303, MR18=0x1D00, DQSOSC=395, MR23=63, INC=23, DEC=15
8355 16:37:17.208169 [RxdqsGatingPostProcess] freq 1600
8356 16:37:17.211568 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8357 16:37:17.215017 best DQS0 dly(2T, 0.5T) = (1, 1)
8358 16:37:17.217689 best DQS1 dly(2T, 0.5T) = (1, 1)
8359 16:37:17.221089 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8360 16:37:17.224350 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8361 16:37:17.228260 best DQS0 dly(2T, 0.5T) = (1, 1)
8362 16:37:17.231534 best DQS1 dly(2T, 0.5T) = (1, 1)
8363 16:37:17.234337 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8364 16:37:17.237650 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8365 16:37:17.240980 Pre-setting of DQS Precalculation
8366 16:37:17.244856 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8367 16:37:17.244938 ==
8368 16:37:17.248029 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 16:37:17.251412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 16:37:17.251494 ==
8371 16:37:17.257631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 16:37:17.261065 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 16:37:17.267451 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 16:37:17.270893 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 16:37:17.281440 [CA 0] Center 42 (13~71) winsize 59
8376 16:37:17.284739 [CA 1] Center 41 (12~71) winsize 60
8377 16:37:17.287574 [CA 2] Center 37 (8~66) winsize 59
8378 16:37:17.290895 [CA 3] Center 36 (7~65) winsize 59
8379 16:37:17.294478 [CA 4] Center 37 (7~67) winsize 61
8380 16:37:17.297175 [CA 5] Center 36 (7~66) winsize 60
8381 16:37:17.297285
8382 16:37:17.300704 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8383 16:37:17.300786
8384 16:37:17.307413 [CATrainingPosCal] consider 1 rank data
8385 16:37:17.307503 u2DelayCellTimex100 = 258/100 ps
8386 16:37:17.314313 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8387 16:37:17.317086 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8388 16:37:17.320530 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8389 16:37:17.324043 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8390 16:37:17.327313 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8391 16:37:17.330710 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8392 16:37:17.330792
8393 16:37:17.334085 CA PerBit enable=1, Macro0, CA PI delay=36
8394 16:37:17.334191
8395 16:37:17.337299 [CBTSetCACLKResult] CA Dly = 36
8396 16:37:17.340666 CS Dly: 9 (0~40)
8397 16:37:17.343401 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 16:37:17.346792 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 16:37:17.346877 ==
8400 16:37:17.350229 Dram Type= 6, Freq= 0, CH_1, rank 1
8401 16:37:17.356949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 16:37:17.357062 ==
8403 16:37:17.360036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8404 16:37:17.366627 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8405 16:37:17.370076 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8406 16:37:17.376367 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8407 16:37:17.383927 [CA 0] Center 42 (12~72) winsize 61
8408 16:37:17.387969 [CA 1] Center 42 (13~72) winsize 60
8409 16:37:17.390617 [CA 2] Center 37 (8~67) winsize 60
8410 16:37:17.394076 [CA 3] Center 36 (7~66) winsize 60
8411 16:37:17.397519 [CA 4] Center 37 (8~67) winsize 60
8412 16:37:17.401004 [CA 5] Center 37 (8~67) winsize 60
8413 16:37:17.401082
8414 16:37:17.404507 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8415 16:37:17.404589
8416 16:37:17.410622 [CATrainingPosCal] consider 2 rank data
8417 16:37:17.410701 u2DelayCellTimex100 = 258/100 ps
8418 16:37:17.417467 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8419 16:37:17.420224 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8420 16:37:17.423677 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8421 16:37:17.427130 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8422 16:37:17.430449 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8423 16:37:17.433690 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8424 16:37:17.433769
8425 16:37:17.437105 CA PerBit enable=1, Macro0, CA PI delay=36
8426 16:37:17.437232
8427 16:37:17.439875 [CBTSetCACLKResult] CA Dly = 36
8428 16:37:17.443286 CS Dly: 11 (0~44)
8429 16:37:17.446450 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8430 16:37:17.449836 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8431 16:37:17.449940
8432 16:37:17.453258 ----->DramcWriteLeveling(PI) begin...
8433 16:37:17.453346 ==
8434 16:37:17.456691 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 16:37:17.463414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 16:37:17.463505 ==
8437 16:37:17.466750 Write leveling (Byte 0): 25 => 25
8438 16:37:17.469893 Write leveling (Byte 1): 28 => 28
8439 16:37:17.472951 DramcWriteLeveling(PI) end<-----
8440 16:37:17.473034
8441 16:37:17.473102 ==
8442 16:37:17.476235 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 16:37:17.479677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 16:37:17.479759 ==
8445 16:37:17.483013 [Gating] SW mode calibration
8446 16:37:17.489386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8447 16:37:17.496090 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8448 16:37:17.499212 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 16:37:17.503040 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 16:37:17.509078 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 16:37:17.512396 1 4 12 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
8452 16:37:17.515767 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 16:37:17.522707 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 16:37:17.525521 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 16:37:17.528918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 16:37:17.535295 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 16:37:17.538622 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 16:37:17.542073 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8459 16:37:17.548844 1 5 12 | B1->B0 | 3333 2727 | 0 0 | (0 1) (1 0)
8460 16:37:17.551626 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 16:37:17.555431 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 16:37:17.561890 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 16:37:17.565196 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 16:37:17.568096 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 16:37:17.574813 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 16:37:17.578141 1 6 8 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
8467 16:37:17.581463 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8468 16:37:17.588287 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 16:37:17.591693 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 16:37:17.594426 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 16:37:17.601055 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 16:37:17.604297 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 16:37:17.608081 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 16:37:17.614499 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 16:37:17.617853 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8476 16:37:17.621300 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8477 16:37:17.628092 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 16:37:17.631513 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 16:37:17.634292 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 16:37:17.641035 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 16:37:17.644443 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 16:37:17.647126 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 16:37:17.653948 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 16:37:17.657288 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 16:37:17.660649 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 16:37:17.667375 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 16:37:17.670834 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 16:37:17.673563 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 16:37:17.680390 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 16:37:17.683715 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8491 16:37:17.687185 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8492 16:37:17.693813 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 16:37:17.693895 Total UI for P1: 0, mck2ui 16
8494 16:37:17.700071 best dqsien dly found for B0: ( 1, 9, 10)
8495 16:37:17.700152 Total UI for P1: 0, mck2ui 16
8496 16:37:17.707008 best dqsien dly found for B1: ( 1, 9, 12)
8497 16:37:17.710355 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8498 16:37:17.713431 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8499 16:37:17.713513
8500 16:37:17.716687 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8501 16:37:17.720111 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8502 16:37:17.723223 [Gating] SW calibration Done
8503 16:37:17.723309 ==
8504 16:37:17.726400 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 16:37:17.729789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 16:37:17.729890 ==
8507 16:37:17.733206 RX Vref Scan: 0
8508 16:37:17.733288
8509 16:37:17.733353 RX Vref 0 -> 0, step: 1
8510 16:37:17.735924
8511 16:37:17.736006 RX Delay 0 -> 252, step: 8
8512 16:37:17.742688 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8513 16:37:17.745882 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8514 16:37:17.749375 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8515 16:37:17.752792 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8516 16:37:17.756126 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8517 16:37:17.762933 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8518 16:37:17.766180 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8519 16:37:17.769423 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8520 16:37:17.772147 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8521 16:37:17.775587 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8522 16:37:17.782456 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8523 16:37:17.785863 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8524 16:37:17.789243 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8525 16:37:17.791962 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8526 16:37:17.798932 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8527 16:37:17.802271 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8528 16:37:17.802354 ==
8529 16:37:17.805136 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 16:37:17.808971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 16:37:17.809055 ==
8532 16:37:17.811590 DQS Delay:
8533 16:37:17.811672 DQS0 = 0, DQS1 = 0
8534 16:37:17.811737 DQM Delay:
8535 16:37:17.815285 DQM0 = 138, DQM1 = 130
8536 16:37:17.815367 DQ Delay:
8537 16:37:17.818284 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8538 16:37:17.821852 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8539 16:37:17.824942 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8540 16:37:17.831861 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8541 16:37:17.831947
8542 16:37:17.832012
8543 16:37:17.832073 ==
8544 16:37:17.834975 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 16:37:17.838296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 16:37:17.838379 ==
8547 16:37:17.838444
8548 16:37:17.838503
8549 16:37:17.841791 TX Vref Scan disable
8550 16:37:17.841864 == TX Byte 0 ==
8551 16:37:17.847955 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8552 16:37:17.851303 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8553 16:37:17.854786 == TX Byte 1 ==
8554 16:37:17.858252 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8555 16:37:17.861601 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8556 16:37:17.861690 ==
8557 16:37:17.864414 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 16:37:17.867881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 16:37:17.867961 ==
8560 16:37:17.882299
8561 16:37:17.885550 TX Vref early break, caculate TX vref
8562 16:37:17.888300 TX Vref=16, minBit 5, minWin=22, winSum=376
8563 16:37:17.891816 TX Vref=18, minBit 0, minWin=23, winSum=389
8564 16:37:17.895176 TX Vref=20, minBit 5, minWin=23, winSum=395
8565 16:37:17.898539 TX Vref=22, minBit 0, minWin=25, winSum=412
8566 16:37:17.904819 TX Vref=24, minBit 0, minWin=25, winSum=419
8567 16:37:17.908349 TX Vref=26, minBit 13, minWin=25, winSum=422
8568 16:37:17.911604 TX Vref=28, minBit 5, minWin=25, winSum=422
8569 16:37:17.915128 TX Vref=30, minBit 5, minWin=25, winSum=419
8570 16:37:17.918324 TX Vref=32, minBit 0, minWin=24, winSum=405
8571 16:37:17.920931 TX Vref=34, minBit 0, minWin=23, winSum=396
8572 16:37:17.927756 [TxChooseVref] Worse bit 13, Min win 25, Win sum 422, Final Vref 26
8573 16:37:17.927863
8574 16:37:17.931405 Final TX Range 0 Vref 26
8575 16:37:17.931485
8576 16:37:17.931554 ==
8577 16:37:17.934441 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 16:37:17.938019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 16:37:17.938127 ==
8580 16:37:17.941034
8581 16:37:17.941134
8582 16:37:17.941223 TX Vref Scan disable
8583 16:37:17.947897 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8584 16:37:17.947982 == TX Byte 0 ==
8585 16:37:17.950586 u2DelayCellOfst[0]=18 cells (5 PI)
8586 16:37:17.953946 u2DelayCellOfst[1]=11 cells (3 PI)
8587 16:37:17.957792 u2DelayCellOfst[2]=0 cells (0 PI)
8588 16:37:17.960535 u2DelayCellOfst[3]=7 cells (2 PI)
8589 16:37:17.964037 u2DelayCellOfst[4]=7 cells (2 PI)
8590 16:37:17.967468 u2DelayCellOfst[5]=22 cells (6 PI)
8591 16:37:17.970903 u2DelayCellOfst[6]=18 cells (5 PI)
8592 16:37:17.973624 u2DelayCellOfst[7]=3 cells (1 PI)
8593 16:37:17.977235 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8594 16:37:17.981067 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8595 16:37:17.983696 == TX Byte 1 ==
8596 16:37:17.987024 u2DelayCellOfst[8]=0 cells (0 PI)
8597 16:37:17.990344 u2DelayCellOfst[9]=7 cells (2 PI)
8598 16:37:17.993400 u2DelayCellOfst[10]=11 cells (3 PI)
8599 16:37:17.997233 u2DelayCellOfst[11]=7 cells (2 PI)
8600 16:37:18.000680 u2DelayCellOfst[12]=15 cells (4 PI)
8601 16:37:18.003413 u2DelayCellOfst[13]=18 cells (5 PI)
8602 16:37:18.003495 u2DelayCellOfst[14]=18 cells (5 PI)
8603 16:37:18.006682 u2DelayCellOfst[15]=18 cells (5 PI)
8604 16:37:18.013414 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8605 16:37:18.016861 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8606 16:37:18.020245 DramC Write-DBI on
8607 16:37:18.020327 ==
8608 16:37:18.023414 Dram Type= 6, Freq= 0, CH_1, rank 0
8609 16:37:18.026828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8610 16:37:18.026912 ==
8611 16:37:18.026977
8612 16:37:18.027037
8613 16:37:18.030151 TX Vref Scan disable
8614 16:37:18.030242 == TX Byte 0 ==
8615 16:37:18.036219 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8616 16:37:18.036301 == TX Byte 1 ==
8617 16:37:18.042716 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8618 16:37:18.042814 DramC Write-DBI off
8619 16:37:18.042887
8620 16:37:18.042953 [DATLAT]
8621 16:37:18.046070 Freq=1600, CH1 RK0
8622 16:37:18.046153
8623 16:37:18.046239 DATLAT Default: 0xf
8624 16:37:18.049634 0, 0xFFFF, sum = 0
8625 16:37:18.052900 1, 0xFFFF, sum = 0
8626 16:37:18.052982 2, 0xFFFF, sum = 0
8627 16:37:18.055978 3, 0xFFFF, sum = 0
8628 16:37:18.056074 4, 0xFFFF, sum = 0
8629 16:37:18.059563 5, 0xFFFF, sum = 0
8630 16:37:18.059688 6, 0xFFFF, sum = 0
8631 16:37:18.062556 7, 0xFFFF, sum = 0
8632 16:37:18.062675 8, 0xFFFF, sum = 0
8633 16:37:18.066063 9, 0xFFFF, sum = 0
8634 16:37:18.066176 10, 0xFFFF, sum = 0
8635 16:37:18.069123 11, 0xFFFF, sum = 0
8636 16:37:18.069237 12, 0xFFFF, sum = 0
8637 16:37:18.072359 13, 0xFFFF, sum = 0
8638 16:37:18.072460 14, 0x0, sum = 1
8639 16:37:18.075786 15, 0x0, sum = 2
8640 16:37:18.075902 16, 0x0, sum = 3
8641 16:37:18.079111 17, 0x0, sum = 4
8642 16:37:18.079225 best_step = 15
8643 16:37:18.079312
8644 16:37:18.079396 ==
8645 16:37:18.082403 Dram Type= 6, Freq= 0, CH_1, rank 0
8646 16:37:18.089347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8647 16:37:18.089426 ==
8648 16:37:18.089488 RX Vref Scan: 1
8649 16:37:18.089547
8650 16:37:18.092029 Set Vref Range= 24 -> 127
8651 16:37:18.092139
8652 16:37:18.095932 RX Vref 24 -> 127, step: 1
8653 16:37:18.096012
8654 16:37:18.099050 RX Delay 19 -> 252, step: 4
8655 16:37:18.099130
8656 16:37:18.102027 Set Vref, RX VrefLevel [Byte0]: 24
8657 16:37:18.105752 [Byte1]: 24
8658 16:37:18.105833
8659 16:37:18.108905 Set Vref, RX VrefLevel [Byte0]: 25
8660 16:37:18.111732 [Byte1]: 25
8661 16:37:18.111813
8662 16:37:18.115061 Set Vref, RX VrefLevel [Byte0]: 26
8663 16:37:18.118593 [Byte1]: 26
8664 16:37:18.122081
8665 16:37:18.122209 Set Vref, RX VrefLevel [Byte0]: 27
8666 16:37:18.124916 [Byte1]: 27
8667 16:37:18.129422
8668 16:37:18.129503 Set Vref, RX VrefLevel [Byte0]: 28
8669 16:37:18.135588 [Byte1]: 28
8670 16:37:18.135669
8671 16:37:18.138994 Set Vref, RX VrefLevel [Byte0]: 29
8672 16:37:18.142343 [Byte1]: 29
8673 16:37:18.142426
8674 16:37:18.145817 Set Vref, RX VrefLevel [Byte0]: 30
8675 16:37:18.148569 [Byte1]: 30
8676 16:37:18.148651
8677 16:37:18.151996 Set Vref, RX VrefLevel [Byte0]: 31
8678 16:37:18.155360 [Byte1]: 31
8679 16:37:18.159395
8680 16:37:18.159509 Set Vref, RX VrefLevel [Byte0]: 32
8681 16:37:18.162696 [Byte1]: 32
8682 16:37:18.167336
8683 16:37:18.167419 Set Vref, RX VrefLevel [Byte0]: 33
8684 16:37:18.170463 [Byte1]: 33
8685 16:37:18.174874
8686 16:37:18.174957 Set Vref, RX VrefLevel [Byte0]: 34
8687 16:37:18.177947 [Byte1]: 34
8688 16:37:18.182416
8689 16:37:18.182497 Set Vref, RX VrefLevel [Byte0]: 35
8690 16:37:18.185721 [Byte1]: 35
8691 16:37:18.189845
8692 16:37:18.189949 Set Vref, RX VrefLevel [Byte0]: 36
8693 16:37:18.193209 [Byte1]: 36
8694 16:37:18.197169
8695 16:37:18.197286 Set Vref, RX VrefLevel [Byte0]: 37
8696 16:37:18.200602 [Byte1]: 37
8697 16:37:18.204822
8698 16:37:18.204903 Set Vref, RX VrefLevel [Byte0]: 38
8699 16:37:18.208026 [Byte1]: 38
8700 16:37:18.212668
8701 16:37:18.212750 Set Vref, RX VrefLevel [Byte0]: 39
8702 16:37:18.215875 [Byte1]: 39
8703 16:37:18.219827
8704 16:37:18.219940 Set Vref, RX VrefLevel [Byte0]: 40
8705 16:37:18.223208 [Byte1]: 40
8706 16:37:18.227418
8707 16:37:18.227513 Set Vref, RX VrefLevel [Byte0]: 41
8708 16:37:18.230848 [Byte1]: 41
8709 16:37:18.235483
8710 16:37:18.235564 Set Vref, RX VrefLevel [Byte0]: 42
8711 16:37:18.238878 [Byte1]: 42
8712 16:37:18.243070
8713 16:37:18.243185 Set Vref, RX VrefLevel [Byte0]: 43
8714 16:37:18.246418 [Byte1]: 43
8715 16:37:18.250484
8716 16:37:18.250594 Set Vref, RX VrefLevel [Byte0]: 44
8717 16:37:18.253917 [Byte1]: 44
8718 16:37:18.257931
8719 16:37:18.258033 Set Vref, RX VrefLevel [Byte0]: 45
8720 16:37:18.261155 [Byte1]: 45
8721 16:37:18.265258
8722 16:37:18.265365 Set Vref, RX VrefLevel [Byte0]: 46
8723 16:37:18.268510 [Byte1]: 46
8724 16:37:18.273269
8725 16:37:18.273353 Set Vref, RX VrefLevel [Byte0]: 47
8726 16:37:18.276630 [Byte1]: 47
8727 16:37:18.280769
8728 16:37:18.280871 Set Vref, RX VrefLevel [Byte0]: 48
8729 16:37:18.284066 [Byte1]: 48
8730 16:37:18.288373
8731 16:37:18.288474 Set Vref, RX VrefLevel [Byte0]: 49
8732 16:37:18.291593 [Byte1]: 49
8733 16:37:18.296088
8734 16:37:18.296161 Set Vref, RX VrefLevel [Byte0]: 50
8735 16:37:18.299397 [Byte1]: 50
8736 16:37:18.303420
8737 16:37:18.303502 Set Vref, RX VrefLevel [Byte0]: 51
8738 16:37:18.306880 [Byte1]: 51
8739 16:37:18.310863
8740 16:37:18.310971 Set Vref, RX VrefLevel [Byte0]: 52
8741 16:37:18.314187 [Byte1]: 52
8742 16:37:18.318309
8743 16:37:18.318392 Set Vref, RX VrefLevel [Byte0]: 53
8744 16:37:18.321675 [Byte1]: 53
8745 16:37:18.326188
8746 16:37:18.326296 Set Vref, RX VrefLevel [Byte0]: 54
8747 16:37:18.329724 [Byte1]: 54
8748 16:37:18.333861
8749 16:37:18.333969 Set Vref, RX VrefLevel [Byte0]: 55
8750 16:37:18.337116 [Byte1]: 55
8751 16:37:18.341226
8752 16:37:18.341335 Set Vref, RX VrefLevel [Byte0]: 56
8753 16:37:18.344691 [Byte1]: 56
8754 16:37:18.348662
8755 16:37:18.348742 Set Vref, RX VrefLevel [Byte0]: 57
8756 16:37:18.352164 [Byte1]: 57
8757 16:37:18.356407
8758 16:37:18.356503 Set Vref, RX VrefLevel [Byte0]: 58
8759 16:37:18.359863 [Byte1]: 58
8760 16:37:18.363756
8761 16:37:18.363837 Set Vref, RX VrefLevel [Byte0]: 59
8762 16:37:18.366966 [Byte1]: 59
8763 16:37:18.371688
8764 16:37:18.371800 Set Vref, RX VrefLevel [Byte0]: 60
8765 16:37:18.374932 [Byte1]: 60
8766 16:37:18.379041
8767 16:37:18.379138 Set Vref, RX VrefLevel [Byte0]: 61
8768 16:37:18.382448 [Byte1]: 61
8769 16:37:18.386879
8770 16:37:18.386960 Set Vref, RX VrefLevel [Byte0]: 62
8771 16:37:18.390285 [Byte1]: 62
8772 16:37:18.394240
8773 16:37:18.394319 Set Vref, RX VrefLevel [Byte0]: 63
8774 16:37:18.397471 [Byte1]: 63
8775 16:37:18.401833
8776 16:37:18.401912 Set Vref, RX VrefLevel [Byte0]: 64
8777 16:37:18.404868 [Byte1]: 64
8778 16:37:18.409361
8779 16:37:18.409489 Set Vref, RX VrefLevel [Byte0]: 65
8780 16:37:18.412593 [Byte1]: 65
8781 16:37:18.417205
8782 16:37:18.417309 Set Vref, RX VrefLevel [Byte0]: 66
8783 16:37:18.420664 [Byte1]: 66
8784 16:37:18.424800
8785 16:37:18.424878 Set Vref, RX VrefLevel [Byte0]: 67
8786 16:37:18.428102 [Byte1]: 67
8787 16:37:18.432050
8788 16:37:18.432128 Set Vref, RX VrefLevel [Byte0]: 68
8789 16:37:18.435273 [Byte1]: 68
8790 16:37:18.439979
8791 16:37:18.440058 Set Vref, RX VrefLevel [Byte0]: 69
8792 16:37:18.443428 [Byte1]: 69
8793 16:37:18.447586
8794 16:37:18.447665 Set Vref, RX VrefLevel [Byte0]: 70
8795 16:37:18.451011 [Byte1]: 70
8796 16:37:18.455174
8797 16:37:18.455253 Set Vref, RX VrefLevel [Byte0]: 71
8798 16:37:18.457903 [Byte1]: 71
8799 16:37:18.462694
8800 16:37:18.462785 Set Vref, RX VrefLevel [Byte0]: 72
8801 16:37:18.466015 [Byte1]: 72
8802 16:37:18.470141
8803 16:37:18.470261 Set Vref, RX VrefLevel [Byte0]: 73
8804 16:37:18.473551 [Byte1]: 73
8805 16:37:18.477559
8806 16:37:18.477642 Set Vref, RX VrefLevel [Byte0]: 74
8807 16:37:18.481057 [Byte1]: 74
8808 16:37:18.485225
8809 16:37:18.485306 Final RX Vref Byte 0 = 54 to rank0
8810 16:37:18.488603 Final RX Vref Byte 1 = 58 to rank0
8811 16:37:18.492034 Final RX Vref Byte 0 = 54 to rank1
8812 16:37:18.494749 Final RX Vref Byte 1 = 58 to rank1==
8813 16:37:18.498316 Dram Type= 6, Freq= 0, CH_1, rank 0
8814 16:37:18.504575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 16:37:18.504686 ==
8816 16:37:18.504790 DQS Delay:
8817 16:37:18.507906 DQS0 = 0, DQS1 = 0
8818 16:37:18.508012 DQM Delay:
8819 16:37:18.511612 DQM0 = 135, DQM1 = 129
8820 16:37:18.511716 DQ Delay:
8821 16:37:18.514375 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8822 16:37:18.517912 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8823 16:37:18.520998 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =118
8824 16:37:18.524850 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
8825 16:37:18.524929
8826 16:37:18.524990
8827 16:37:18.525048
8828 16:37:18.528058 [DramC_TX_OE_Calibration] TA2
8829 16:37:18.531371 Original DQ_B0 (3 6) =30, OEN = 27
8830 16:37:18.534441 Original DQ_B1 (3 6) =30, OEN = 27
8831 16:37:18.537902 24, 0x0, End_B0=24 End_B1=24
8832 16:37:18.541115 25, 0x0, End_B0=25 End_B1=25
8833 16:37:18.541269 26, 0x0, End_B0=26 End_B1=26
8834 16:37:18.544233 27, 0x0, End_B0=27 End_B1=27
8835 16:37:18.547301 28, 0x0, End_B0=28 End_B1=28
8836 16:37:18.550838 29, 0x0, End_B0=29 End_B1=29
8837 16:37:18.554084 30, 0x0, End_B0=30 End_B1=30
8838 16:37:18.554198 31, 0x4545, End_B0=30 End_B1=30
8839 16:37:18.557581 Byte0 end_step=30 best_step=27
8840 16:37:18.560337 Byte1 end_step=30 best_step=27
8841 16:37:18.563727 Byte0 TX OE(2T, 0.5T) = (3, 3)
8842 16:37:18.567173 Byte1 TX OE(2T, 0.5T) = (3, 3)
8843 16:37:18.567245
8844 16:37:18.567307
8845 16:37:18.573991 [DQSOSCAuto] RK0, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8846 16:37:18.576731 CH1 RK0: MR19=303, MR18=160C
8847 16:37:18.583351 CH1_RK0: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8848 16:37:18.583438
8849 16:37:18.586838 ----->DramcWriteLeveling(PI) begin...
8850 16:37:18.586938 ==
8851 16:37:18.590156 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 16:37:18.593066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 16:37:18.596489 ==
8854 16:37:18.596589 Write leveling (Byte 0): 23 => 23
8855 16:37:18.600011 Write leveling (Byte 1): 27 => 27
8856 16:37:18.603432 DramcWriteLeveling(PI) end<-----
8857 16:37:18.603513
8858 16:37:18.603575 ==
8859 16:37:18.606875 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 16:37:18.613370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 16:37:18.613455 ==
8862 16:37:18.616744 [Gating] SW mode calibration
8863 16:37:18.622797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8864 16:37:18.626728 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8865 16:37:18.633077 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 16:37:18.636157 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 16:37:18.639429 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 16:37:18.646011 1 4 12 | B1->B0 | 3434 2322 | 1 1 | (1 1) (0 0)
8869 16:37:18.649422 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 16:37:18.652701 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 16:37:18.659195 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 16:37:18.662261 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 16:37:18.665948 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 16:37:18.672733 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8875 16:37:18.675462 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8876 16:37:18.678733 1 5 12 | B1->B0 | 2626 3434 | 0 1 | (1 0) (1 0)
8877 16:37:18.685432 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8878 16:37:18.688784 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 16:37:18.692105 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 16:37:18.698945 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 16:37:18.702275 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 16:37:18.705134 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8883 16:37:18.712004 1 6 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8884 16:37:18.715458 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8885 16:37:18.718685 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 16:37:18.725250 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 16:37:18.728566 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 16:37:18.732056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 16:37:18.738723 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 16:37:18.741900 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 16:37:18.745136 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8892 16:37:18.751782 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8893 16:37:18.754897 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 16:37:18.758297 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 16:37:18.764895 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 16:37:18.768167 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 16:37:18.771510 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 16:37:18.778067 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 16:37:18.781433 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 16:37:18.784764 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 16:37:18.791469 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 16:37:18.794958 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 16:37:18.798348 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 16:37:18.804472 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 16:37:18.807906 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 16:37:18.811455 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 16:37:18.817669 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8908 16:37:18.821066 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8909 16:37:18.824247 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8910 16:37:18.827493 Total UI for P1: 0, mck2ui 16
8911 16:37:18.831423 best dqsien dly found for B0: ( 1, 9, 12)
8912 16:37:18.834355 Total UI for P1: 0, mck2ui 16
8913 16:37:18.837802 best dqsien dly found for B1: ( 1, 9, 10)
8914 16:37:18.841223 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8915 16:37:18.844587 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8916 16:37:18.844701
8917 16:37:18.847465 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8918 16:37:18.854183 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8919 16:37:18.854277 [Gating] SW calibration Done
8920 16:37:18.857344 ==
8921 16:37:18.860497 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 16:37:18.863925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 16:37:18.863999 ==
8924 16:37:18.864061 RX Vref Scan: 0
8925 16:37:18.864118
8926 16:37:18.867077 RX Vref 0 -> 0, step: 1
8927 16:37:18.867157
8928 16:37:18.870282 RX Delay 0 -> 252, step: 8
8929 16:37:18.873743 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8930 16:37:18.877070 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8931 16:37:18.880319 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8932 16:37:18.887001 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8933 16:37:18.890429 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8934 16:37:18.893613 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8935 16:37:18.897014 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8936 16:37:18.899856 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8937 16:37:18.906692 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8938 16:37:18.910022 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8939 16:37:18.913368 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8940 16:37:18.916880 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8941 16:37:18.923087 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8942 16:37:18.926545 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8943 16:37:18.929193 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8944 16:37:18.932492 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8945 16:37:18.932595 ==
8946 16:37:18.935839 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 16:37:18.942626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 16:37:18.942706 ==
8949 16:37:18.942771 DQS Delay:
8950 16:37:18.946071 DQS0 = 0, DQS1 = 0
8951 16:37:18.946146 DQM Delay:
8952 16:37:18.949522 DQM0 = 136, DQM1 = 129
8953 16:37:18.949603 DQ Delay:
8954 16:37:18.952948 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8955 16:37:18.956459 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8956 16:37:18.959158 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8957 16:37:18.962593 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8958 16:37:18.962674
8959 16:37:18.962737
8960 16:37:18.962796 ==
8961 16:37:18.965714 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 16:37:18.972377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 16:37:18.972469 ==
8964 16:37:18.972535
8965 16:37:18.972602
8966 16:37:18.972659 TX Vref Scan disable
8967 16:37:18.976163 == TX Byte 0 ==
8968 16:37:18.979354 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8969 16:37:18.985865 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8970 16:37:18.985977 == TX Byte 1 ==
8971 16:37:18.988991 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8972 16:37:18.995262 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8973 16:37:18.995354 ==
8974 16:37:18.999204 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 16:37:19.001841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 16:37:19.001951 ==
8977 16:37:19.015049
8978 16:37:19.018381 TX Vref early break, caculate TX vref
8979 16:37:19.021246 TX Vref=16, minBit 0, minWin=22, winSum=383
8980 16:37:19.024719 TX Vref=18, minBit 0, minWin=22, winSum=389
8981 16:37:19.028198 TX Vref=20, minBit 1, minWin=23, winSum=401
8982 16:37:19.031493 TX Vref=22, minBit 6, minWin=23, winSum=407
8983 16:37:19.034900 TX Vref=24, minBit 0, minWin=25, winSum=417
8984 16:37:19.040821 TX Vref=26, minBit 0, minWin=25, winSum=420
8985 16:37:19.044318 TX Vref=28, minBit 0, minWin=24, winSum=416
8986 16:37:19.047722 TX Vref=30, minBit 0, minWin=23, winSum=414
8987 16:37:19.051051 TX Vref=32, minBit 0, minWin=23, winSum=403
8988 16:37:19.054364 TX Vref=34, minBit 0, minWin=22, winSum=395
8989 16:37:19.061341 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8990 16:37:19.061437
8991 16:37:19.064011 Final TX Range 0 Vref 26
8992 16:37:19.064095
8993 16:37:19.064159 ==
8994 16:37:19.067326 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 16:37:19.070549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 16:37:19.070660 ==
8997 16:37:19.070754
8998 16:37:19.070848
8999 16:37:19.073935 TX Vref Scan disable
9000 16:37:19.080879 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9001 16:37:19.080974 == TX Byte 0 ==
9002 16:37:19.083999 u2DelayCellOfst[0]=18 cells (5 PI)
9003 16:37:19.086998 u2DelayCellOfst[1]=11 cells (3 PI)
9004 16:37:19.090455 u2DelayCellOfst[2]=0 cells (0 PI)
9005 16:37:19.093867 u2DelayCellOfst[3]=3 cells (1 PI)
9006 16:37:19.097151 u2DelayCellOfst[4]=7 cells (2 PI)
9007 16:37:19.100336 u2DelayCellOfst[5]=18 cells (5 PI)
9008 16:37:19.103443 u2DelayCellOfst[6]=18 cells (5 PI)
9009 16:37:19.107186 u2DelayCellOfst[7]=3 cells (1 PI)
9010 16:37:19.110187 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9011 16:37:19.113905 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9012 16:37:19.116623 == TX Byte 1 ==
9013 16:37:19.120079 u2DelayCellOfst[8]=0 cells (0 PI)
9014 16:37:19.123430 u2DelayCellOfst[9]=7 cells (2 PI)
9015 16:37:19.126864 u2DelayCellOfst[10]=11 cells (3 PI)
9016 16:37:19.126946 u2DelayCellOfst[11]=7 cells (2 PI)
9017 16:37:19.130266 u2DelayCellOfst[12]=18 cells (5 PI)
9018 16:37:19.133568 u2DelayCellOfst[13]=18 cells (5 PI)
9019 16:37:19.136247 u2DelayCellOfst[14]=18 cells (5 PI)
9020 16:37:19.139679 u2DelayCellOfst[15]=18 cells (5 PI)
9021 16:37:19.146247 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9022 16:37:19.149639 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9023 16:37:19.149748 DramC Write-DBI on
9024 16:37:19.153050 ==
9025 16:37:19.156438 Dram Type= 6, Freq= 0, CH_1, rank 1
9026 16:37:19.159900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9027 16:37:19.160017 ==
9028 16:37:19.160115
9029 16:37:19.160203
9030 16:37:19.162656 TX Vref Scan disable
9031 16:37:19.162754 == TX Byte 0 ==
9032 16:37:19.169515 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9033 16:37:19.169598 == TX Byte 1 ==
9034 16:37:19.172981 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9035 16:37:19.175650 DramC Write-DBI off
9036 16:37:19.175722
9037 16:37:19.175783 [DATLAT]
9038 16:37:19.178974 Freq=1600, CH1 RK1
9039 16:37:19.179057
9040 16:37:19.179121 DATLAT Default: 0xf
9041 16:37:19.182721 0, 0xFFFF, sum = 0
9042 16:37:19.182805 1, 0xFFFF, sum = 0
9043 16:37:19.186013 2, 0xFFFF, sum = 0
9044 16:37:19.189300 3, 0xFFFF, sum = 0
9045 16:37:19.189415 4, 0xFFFF, sum = 0
9046 16:37:19.192460 5, 0xFFFF, sum = 0
9047 16:37:19.192547 6, 0xFFFF, sum = 0
9048 16:37:19.195621 7, 0xFFFF, sum = 0
9049 16:37:19.195704 8, 0xFFFF, sum = 0
9050 16:37:19.198948 9, 0xFFFF, sum = 0
9051 16:37:19.199058 10, 0xFFFF, sum = 0
9052 16:37:19.202066 11, 0xFFFF, sum = 0
9053 16:37:19.202149 12, 0xFFFF, sum = 0
9054 16:37:19.205465 13, 0xFFFF, sum = 0
9055 16:37:19.205548 14, 0x0, sum = 1
9056 16:37:19.208891 15, 0x0, sum = 2
9057 16:37:19.208974 16, 0x0, sum = 3
9058 16:37:19.212125 17, 0x0, sum = 4
9059 16:37:19.212244 best_step = 15
9060 16:37:19.212350
9061 16:37:19.212449 ==
9062 16:37:19.215417 Dram Type= 6, Freq= 0, CH_1, rank 1
9063 16:37:19.221919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9064 16:37:19.222028 ==
9065 16:37:19.222122 RX Vref Scan: 0
9066 16:37:19.222209
9067 16:37:19.225473 RX Vref 0 -> 0, step: 1
9068 16:37:19.225556
9069 16:37:19.228709 RX Delay 11 -> 252, step: 4
9070 16:37:19.232154 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9071 16:37:19.235675 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9072 16:37:19.238440 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9073 16:37:19.245188 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9074 16:37:19.248436 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9075 16:37:19.251885 iDelay=199, Bit 5, Center 146 (95 ~ 198) 104
9076 16:37:19.255282 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9077 16:37:19.258658 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9078 16:37:19.264900 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9079 16:37:19.268275 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9080 16:37:19.271837 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9081 16:37:19.274598 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9082 16:37:19.281393 iDelay=199, Bit 12, Center 138 (83 ~ 194) 112
9083 16:37:19.284775 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9084 16:37:19.288040 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9085 16:37:19.291408 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9086 16:37:19.291521 ==
9087 16:37:19.294825 Dram Type= 6, Freq= 0, CH_1, rank 1
9088 16:37:19.300855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9089 16:37:19.300965 ==
9090 16:37:19.301058 DQS Delay:
9091 16:37:19.304057 DQS0 = 0, DQS1 = 0
9092 16:37:19.304164 DQM Delay:
9093 16:37:19.304256 DQM0 = 134, DQM1 = 127
9094 16:37:19.307322 DQ Delay:
9095 16:37:19.310721 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9096 16:37:19.314173 DQ4 =134, DQ5 =146, DQ6 =144, DQ7 =130
9097 16:37:19.317452 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9098 16:37:19.320656 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138
9099 16:37:19.320765
9100 16:37:19.320865
9101 16:37:19.320963
9102 16:37:19.324151 [DramC_TX_OE_Calibration] TA2
9103 16:37:19.327447 Original DQ_B0 (3 6) =30, OEN = 27
9104 16:37:19.330865 Original DQ_B1 (3 6) =30, OEN = 27
9105 16:37:19.334036 24, 0x0, End_B0=24 End_B1=24
9106 16:37:19.336997 25, 0x0, End_B0=25 End_B1=25
9107 16:37:19.337106 26, 0x0, End_B0=26 End_B1=26
9108 16:37:19.340775 27, 0x0, End_B0=27 End_B1=27
9109 16:37:19.344037 28, 0x0, End_B0=28 End_B1=28
9110 16:37:19.347416 29, 0x0, End_B0=29 End_B1=29
9111 16:37:19.347544 30, 0x0, End_B0=30 End_B1=30
9112 16:37:19.350865 31, 0x4141, End_B0=30 End_B1=30
9113 16:37:19.353952 Byte0 end_step=30 best_step=27
9114 16:37:19.356766 Byte1 end_step=30 best_step=27
9115 16:37:19.360167 Byte0 TX OE(2T, 0.5T) = (3, 3)
9116 16:37:19.363497 Byte1 TX OE(2T, 0.5T) = (3, 3)
9117 16:37:19.363666
9118 16:37:19.363804
9119 16:37:19.370502 [DQSOSCAuto] RK1, (LSB)MR18= 0xe09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
9120 16:37:19.373425 CH1 RK1: MR19=303, MR18=E09
9121 16:37:19.380423 CH1_RK1: MR19=0x303, MR18=0xE09, DQSOSC=402, MR23=63, INC=22, DEC=15
9122 16:37:19.383179 [RxdqsGatingPostProcess] freq 1600
9123 16:37:19.390069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9124 16:37:19.390336 best DQS0 dly(2T, 0.5T) = (1, 1)
9125 16:37:19.393104 best DQS1 dly(2T, 0.5T) = (1, 1)
9126 16:37:19.396350 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9127 16:37:19.399710 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9128 16:37:19.403273 best DQS0 dly(2T, 0.5T) = (1, 1)
9129 16:37:19.406607 best DQS1 dly(2T, 0.5T) = (1, 1)
9130 16:37:19.409944 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9131 16:37:19.413277 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9132 16:37:19.416574 Pre-setting of DQS Precalculation
9133 16:37:19.419861 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9134 16:37:19.429857 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9135 16:37:19.436004 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9136 16:37:19.436094
9137 16:37:19.436158
9138 16:37:19.439329 [Calibration Summary] 3200 Mbps
9139 16:37:19.439411 CH 0, Rank 0
9140 16:37:19.442638 SW Impedance : PASS
9141 16:37:19.442753 DUTY Scan : NO K
9142 16:37:19.445932 ZQ Calibration : PASS
9143 16:37:19.449223 Jitter Meter : NO K
9144 16:37:19.449331 CBT Training : PASS
9145 16:37:19.452284 Write leveling : PASS
9146 16:37:19.455916 RX DQS gating : PASS
9147 16:37:19.456000 RX DQ/DQS(RDDQC) : PASS
9148 16:37:19.459186 TX DQ/DQS : PASS
9149 16:37:19.462215 RX DATLAT : PASS
9150 16:37:19.462298 RX DQ/DQS(Engine): PASS
9151 16:37:19.465575 TX OE : PASS
9152 16:37:19.465658 All Pass.
9153 16:37:19.465722
9154 16:37:19.469065 CH 0, Rank 1
9155 16:37:19.469146 SW Impedance : PASS
9156 16:37:19.472356 DUTY Scan : NO K
9157 16:37:19.475233 ZQ Calibration : PASS
9158 16:37:19.475316 Jitter Meter : NO K
9159 16:37:19.478576 CBT Training : PASS
9160 16:37:19.481967 Write leveling : PASS
9161 16:37:19.482076 RX DQS gating : PASS
9162 16:37:19.485362 RX DQ/DQS(RDDQC) : PASS
9163 16:37:19.488737 TX DQ/DQS : PASS
9164 16:37:19.488821 RX DATLAT : PASS
9165 16:37:19.492293 RX DQ/DQS(Engine): PASS
9166 16:37:19.492375 TX OE : PASS
9167 16:37:19.495901 All Pass.
9168 16:37:19.496011
9169 16:37:19.496115 CH 1, Rank 0
9170 16:37:19.498952 SW Impedance : PASS
9171 16:37:19.499026 DUTY Scan : NO K
9172 16:37:19.502102 ZQ Calibration : PASS
9173 16:37:19.505587 Jitter Meter : NO K
9174 16:37:19.505681 CBT Training : PASS
9175 16:37:19.508452 Write leveling : PASS
9176 16:37:19.511730 RX DQS gating : PASS
9177 16:37:19.511845 RX DQ/DQS(RDDQC) : PASS
9178 16:37:19.515232 TX DQ/DQS : PASS
9179 16:37:19.518575 RX DATLAT : PASS
9180 16:37:19.518679 RX DQ/DQS(Engine): PASS
9181 16:37:19.521940 TX OE : PASS
9182 16:37:19.522041 All Pass.
9183 16:37:19.522130
9184 16:37:19.525111 CH 1, Rank 1
9185 16:37:19.525220 SW Impedance : PASS
9186 16:37:19.528486 DUTY Scan : NO K
9187 16:37:19.531717 ZQ Calibration : PASS
9188 16:37:19.531821 Jitter Meter : NO K
9189 16:37:19.535242 CBT Training : PASS
9190 16:37:19.538697 Write leveling : PASS
9191 16:37:19.538799 RX DQS gating : PASS
9192 16:37:19.541467 RX DQ/DQS(RDDQC) : PASS
9193 16:37:19.544813 TX DQ/DQS : PASS
9194 16:37:19.544918 RX DATLAT : PASS
9195 16:37:19.548209 RX DQ/DQS(Engine): PASS
9196 16:37:19.551522 TX OE : PASS
9197 16:37:19.551599 All Pass.
9198 16:37:19.551661
9199 16:37:19.551738 DramC Write-DBI on
9200 16:37:19.554816 PER_BANK_REFRESH: Hybrid Mode
9201 16:37:19.558017 TX_TRACKING: ON
9202 16:37:19.564666 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9203 16:37:19.574645 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9204 16:37:19.580878 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9205 16:37:19.584371 [FAST_K] Save calibration result to emmc
9206 16:37:19.587870 sync common calibartion params.
9207 16:37:19.591427 sync cbt_mode0:1, 1:1
9208 16:37:19.591508 dram_init: ddr_geometry: 2
9209 16:37:19.594677 dram_init: ddr_geometry: 2
9210 16:37:19.597781 dram_init: ddr_geometry: 2
9211 16:37:19.597863 0:dram_rank_size:100000000
9212 16:37:19.601204 1:dram_rank_size:100000000
9213 16:37:19.607553 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9214 16:37:19.610967 DFS_SHUFFLE_HW_MODE: ON
9215 16:37:19.614084 dramc_set_vcore_voltage set vcore to 725000
9216 16:37:19.614214 Read voltage for 1600, 0
9217 16:37:19.617518 Vio18 = 0
9218 16:37:19.617632 Vcore = 725000
9219 16:37:19.617700 Vdram = 0
9220 16:37:19.620775 Vddq = 0
9221 16:37:19.620901 Vmddr = 0
9222 16:37:19.624227 switch to 3200 Mbps bootup
9223 16:37:19.624320 [DramcRunTimeConfig]
9224 16:37:19.627084 PHYPLL
9225 16:37:19.627167 DPM_CONTROL_AFTERK: ON
9226 16:37:19.630411 PER_BANK_REFRESH: ON
9227 16:37:19.633803 REFRESH_OVERHEAD_REDUCTION: ON
9228 16:37:19.633885 CMD_PICG_NEW_MODE: OFF
9229 16:37:19.637037 XRTWTW_NEW_MODE: ON
9230 16:37:19.637119 XRTRTR_NEW_MODE: ON
9231 16:37:19.640456 TX_TRACKING: ON
9232 16:37:19.640539 RDSEL_TRACKING: OFF
9233 16:37:19.643877 DQS Precalculation for DVFS: ON
9234 16:37:19.647199 RX_TRACKING: OFF
9235 16:37:19.647275 HW_GATING DBG: ON
9236 16:37:19.649917 ZQCS_ENABLE_LP4: ON
9237 16:37:19.650016 RX_PICG_NEW_MODE: ON
9238 16:37:19.653802 TX_PICG_NEW_MODE: ON
9239 16:37:19.653909 ENABLE_RX_DCM_DPHY: ON
9240 16:37:19.656528 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9241 16:37:19.659923 DUMMY_READ_FOR_TRACKING: OFF
9242 16:37:19.663329 !!! SPM_CONTROL_AFTERK: OFF
9243 16:37:19.666722 !!! SPM could not control APHY
9244 16:37:19.666810 IMPEDANCE_TRACKING: ON
9245 16:37:19.670286 TEMP_SENSOR: ON
9246 16:37:19.670394 HW_SAVE_FOR_SR: OFF
9247 16:37:19.672973 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9248 16:37:19.676521 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9249 16:37:19.680120 Read ODT Tracking: ON
9250 16:37:19.683113 Refresh Rate DeBounce: ON
9251 16:37:19.683280 DFS_NO_QUEUE_FLUSH: ON
9252 16:37:19.686590 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9253 16:37:19.690021 ENABLE_DFS_RUNTIME_MRW: OFF
9254 16:37:19.692791 DDR_RESERVE_NEW_MODE: ON
9255 16:37:19.692945 MR_CBT_SWITCH_FREQ: ON
9256 16:37:19.696081 =========================
9257 16:37:19.715966 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9258 16:37:19.719269 dram_init: ddr_geometry: 2
9259 16:37:19.737700 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9260 16:37:19.741194 dram_init: dram init end (result: 0)
9261 16:37:19.747078 DRAM-K: Full calibration passed in 24623 msecs
9262 16:37:19.750424 MRC: failed to locate region type 0.
9263 16:37:19.750898 DRAM rank0 size:0x100000000,
9264 16:37:19.754007 DRAM rank1 size=0x100000000
9265 16:37:19.763958 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9266 16:37:19.770639 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9267 16:37:19.776975 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9268 16:37:19.787087 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9269 16:37:19.787566 DRAM rank0 size:0x100000000,
9270 16:37:19.790189 DRAM rank1 size=0x100000000
9271 16:37:19.790685 CBMEM:
9272 16:37:19.793193 IMD: root @ 0xfffff000 254 entries.
9273 16:37:19.796784 IMD: root @ 0xffffec00 62 entries.
9274 16:37:19.799715 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9275 16:37:19.806545 WARNING: RO_VPD is uninitialized or empty.
9276 16:37:19.809826 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9277 16:37:19.817481 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9278 16:37:19.830240 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9279 16:37:19.841371 BS: romstage times (exec / console): total (unknown) / 24119 ms
9280 16:37:19.841933
9281 16:37:19.842396
9282 16:37:19.851335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9283 16:37:19.855263 ARM64: Exception handlers installed.
9284 16:37:19.857865 ARM64: Testing exception
9285 16:37:19.861553 ARM64: Done test exception
9286 16:37:19.862150 Enumerating buses...
9287 16:37:19.864774 Show all devs... Before device enumeration.
9288 16:37:19.868170 Root Device: enabled 1
9289 16:37:19.871526 CPU_CLUSTER: 0: enabled 1
9290 16:37:19.871948 CPU: 00: enabled 1
9291 16:37:19.874672 Compare with tree...
9292 16:37:19.875124 Root Device: enabled 1
9293 16:37:19.878107 CPU_CLUSTER: 0: enabled 1
9294 16:37:19.880865 CPU: 00: enabled 1
9295 16:37:19.881391 Root Device scanning...
9296 16:37:19.884246 scan_static_bus for Root Device
9297 16:37:19.887583 CPU_CLUSTER: 0 enabled
9298 16:37:19.891261 scan_static_bus for Root Device done
9299 16:37:19.894679 scan_bus: bus Root Device finished in 8 msecs
9300 16:37:19.895091 done
9301 16:37:19.900760 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9302 16:37:19.904596 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9303 16:37:19.910399 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9304 16:37:19.917295 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9305 16:37:19.917725 Allocating resources...
9306 16:37:19.920679 Reading resources...
9307 16:37:19.924209 Root Device read_resources bus 0 link: 0
9308 16:37:19.927057 DRAM rank0 size:0x100000000,
9309 16:37:19.927469 DRAM rank1 size=0x100000000
9310 16:37:19.933923 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9311 16:37:19.934463 CPU: 00 missing read_resources
9312 16:37:19.940246 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9313 16:37:19.943460 Root Device read_resources bus 0 link: 0 done
9314 16:37:19.946715 Done reading resources.
9315 16:37:19.950077 Show resources in subtree (Root Device)...After reading.
9316 16:37:19.953660 Root Device child on link 0 CPU_CLUSTER: 0
9317 16:37:19.957068 CPU_CLUSTER: 0 child on link 0 CPU: 00
9318 16:37:19.966707 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9319 16:37:19.967150 CPU: 00
9320 16:37:19.973448 Root Device assign_resources, bus 0 link: 0
9321 16:37:19.976659 CPU_CLUSTER: 0 missing set_resources
9322 16:37:19.979887 Root Device assign_resources, bus 0 link: 0 done
9323 16:37:19.983348 Done setting resources.
9324 16:37:19.986727 Show resources in subtree (Root Device)...After assigning values.
9325 16:37:19.990236 Root Device child on link 0 CPU_CLUSTER: 0
9326 16:37:19.996451 CPU_CLUSTER: 0 child on link 0 CPU: 00
9327 16:37:20.003184 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9328 16:37:20.003649 CPU: 00
9329 16:37:20.006393 Done allocating resources.
9330 16:37:20.013397 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9331 16:37:20.013840 Enabling resources...
9332 16:37:20.016284 done.
9333 16:37:20.019515 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9334 16:37:20.022931 Initializing devices...
9335 16:37:20.023500 Root Device init
9336 16:37:20.026400 init hardware done!
9337 16:37:20.026970 0x00000018: ctrlr->caps
9338 16:37:20.029793 52.000 MHz: ctrlr->f_max
9339 16:37:20.032421 0.400 MHz: ctrlr->f_min
9340 16:37:20.035938 0x40ff8080: ctrlr->voltages
9341 16:37:20.036507 sclk: 390625
9342 16:37:20.037001 Bus Width = 1
9343 16:37:20.039384 sclk: 390625
9344 16:37:20.039904 Bus Width = 1
9345 16:37:20.042785 Early init status = 3
9346 16:37:20.045480 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9347 16:37:20.049273 in-header: 03 fc 00 00 01 00 00 00
9348 16:37:20.052484 in-data: 00
9349 16:37:20.055858 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9350 16:37:20.061119 in-header: 03 fd 00 00 00 00 00 00
9351 16:37:20.063797 in-data:
9352 16:37:20.067133 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9353 16:37:20.071700 in-header: 03 fc 00 00 01 00 00 00
9354 16:37:20.074872 in-data: 00
9355 16:37:20.078145 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9356 16:37:20.083580 in-header: 03 fd 00 00 00 00 00 00
9357 16:37:20.086724 in-data:
9358 16:37:20.090062 [SSUSB] Setting up USB HOST controller...
9359 16:37:20.093677 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9360 16:37:20.096909 [SSUSB] phy power-on done.
9361 16:37:20.100387 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9362 16:37:20.106707 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9363 16:37:20.110019 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9364 16:37:20.116640 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9365 16:37:20.122967 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9366 16:37:20.130112 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9367 16:37:20.136161 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9368 16:37:20.142918 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9369 16:37:20.146456 SPM: binary array size = 0x9dc
9370 16:37:20.149896 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9371 16:37:20.156036 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9372 16:37:20.162685 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9373 16:37:20.169541 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9374 16:37:20.172981 configure_display: Starting display init
9375 16:37:20.207348 anx7625_power_on_init: Init interface.
9376 16:37:20.209959 anx7625_disable_pd_protocol: Disabled PD feature.
9377 16:37:20.213282 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9378 16:37:20.241341 anx7625_start_dp_work: Secure OCM version=00
9379 16:37:20.244490 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9380 16:37:20.259417 sp_tx_get_edid_block: EDID Block = 1
9381 16:37:20.362261 Extracted contents:
9382 16:37:20.365494 header: 00 ff ff ff ff ff ff 00
9383 16:37:20.369053 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9384 16:37:20.371639 version: 01 04
9385 16:37:20.375036 basic params: 95 1f 11 78 0a
9386 16:37:20.378250 chroma info: 76 90 94 55 54 90 27 21 50 54
9387 16:37:20.381475 established: 00 00 00
9388 16:37:20.388064 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9389 16:37:20.394578 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9390 16:37:20.397953 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 16:37:20.404858 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9392 16:37:20.411489 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9393 16:37:20.414425 extensions: 00
9394 16:37:20.414929 checksum: fb
9395 16:37:20.415321
9396 16:37:20.421270 Manufacturer: IVO Model 57d Serial Number 0
9397 16:37:20.421811 Made week 0 of 2020
9398 16:37:20.424671 EDID version: 1.4
9399 16:37:20.425162 Digital display
9400 16:37:20.428169 6 bits per primary color channel
9401 16:37:20.428704 DisplayPort interface
9402 16:37:20.431617 Maximum image size: 31 cm x 17 cm
9403 16:37:20.434956 Gamma: 220%
9404 16:37:20.435472 Check DPMS levels
9405 16:37:20.437745 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9406 16:37:20.444546 First detailed timing is preferred timing
9407 16:37:20.445234 Established timings supported:
9408 16:37:20.448001 Standard timings supported:
9409 16:37:20.451340 Detailed timings
9410 16:37:20.454693 Hex of detail: 383680a07038204018303c0035ae10000019
9411 16:37:20.461172 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9412 16:37:20.464163 0780 0798 07c8 0820 hborder 0
9413 16:37:20.467651 0438 043b 0447 0458 vborder 0
9414 16:37:20.470807 -hsync -vsync
9415 16:37:20.471357 Did detailed timing
9416 16:37:20.477504 Hex of detail: 000000000000000000000000000000000000
9417 16:37:20.480837 Manufacturer-specified data, tag 0
9418 16:37:20.484081 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9419 16:37:20.487398 ASCII string: InfoVision
9420 16:37:20.490529 Hex of detail: 000000fe00523134304e574635205248200a
9421 16:37:20.494429 ASCII string: R140NWF5 RH
9422 16:37:20.495055 Checksum
9423 16:37:20.497499 Checksum: 0xfb (valid)
9424 16:37:20.500596 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9425 16:37:20.503923 DSI data_rate: 832800000 bps
9426 16:37:20.510509 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9427 16:37:20.514091 anx7625_parse_edid: pixelclock(138800).
9428 16:37:20.517351 hactive(1920), hsync(48), hfp(24), hbp(88)
9429 16:37:20.520795 vactive(1080), vsync(12), vfp(3), vbp(17)
9430 16:37:20.523922 anx7625_dsi_config: config dsi.
9431 16:37:20.530736 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9432 16:37:20.544180 anx7625_dsi_config: success to config DSI
9433 16:37:20.547382 anx7625_dp_start: MIPI phy setup OK.
9434 16:37:20.550878 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9435 16:37:20.554291 mtk_ddp_mode_set invalid vrefresh 60
9436 16:37:20.556949 main_disp_path_setup
9437 16:37:20.557378 ovl_layer_smi_id_en
9438 16:37:20.560445 ovl_layer_smi_id_en
9439 16:37:20.561078 ccorr_config
9440 16:37:20.561503 aal_config
9441 16:37:20.563840 gamma_config
9442 16:37:20.564339 postmask_config
9443 16:37:20.566904 dither_config
9444 16:37:20.570237 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9445 16:37:20.577460 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9446 16:37:20.580251 Root Device init finished in 553 msecs
9447 16:37:20.584267 CPU_CLUSTER: 0 init
9448 16:37:20.590401 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9449 16:37:20.593656 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9450 16:37:20.596884 APU_MBOX 0x190000b0 = 0x10001
9451 16:37:20.600259 APU_MBOX 0x190001b0 = 0x10001
9452 16:37:20.603295 APU_MBOX 0x190005b0 = 0x10001
9453 16:37:20.607298 APU_MBOX 0x190006b0 = 0x10001
9454 16:37:20.610274 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9455 16:37:20.623024 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9456 16:37:20.635435 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9457 16:37:20.642156 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9458 16:37:20.653662 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9459 16:37:20.663272 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9460 16:37:20.665898 CPU_CLUSTER: 0 init finished in 81 msecs
9461 16:37:20.669342 Devices initialized
9462 16:37:20.672697 Show all devs... After init.
9463 16:37:20.673113 Root Device: enabled 1
9464 16:37:20.676168 CPU_CLUSTER: 0: enabled 1
9465 16:37:20.679430 CPU: 00: enabled 1
9466 16:37:20.682731 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9467 16:37:20.685651 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9468 16:37:20.689353 ELOG: NV offset 0x57f000 size 0x1000
9469 16:37:20.695989 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9470 16:37:20.702750 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9471 16:37:20.705502 ELOG: Event(17) added with size 13 at 2024-06-17 16:37:20 UTC
9472 16:37:20.712354 out: cmd=0x121: 03 db 21 01 00 00 00 00
9473 16:37:20.715729 in-header: 03 2c 00 00 2c 00 00 00
9474 16:37:20.728444 in-data: 10 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9475 16:37:20.731871 ELOG: Event(A1) added with size 10 at 2024-06-17 16:37:20 UTC
9476 16:37:20.742084 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9477 16:37:20.744820 ELOG: Event(A0) added with size 9 at 2024-06-17 16:37:20 UTC
9478 16:37:20.748277 elog_add_boot_reason: Logged dev mode boot
9479 16:37:20.755003 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9480 16:37:20.755504 Finalize devices...
9481 16:37:20.758443 Devices finalized
9482 16:37:20.761941 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9483 16:37:20.765358 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9484 16:37:20.768893 in-header: 03 07 00 00 08 00 00 00
9485 16:37:20.771468 in-data: aa e4 47 04 13 02 00 00
9486 16:37:20.774909 Chrome EC: UHEPI supported
9487 16:37:20.781596 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9488 16:37:20.785089 in-header: 03 a9 00 00 08 00 00 00
9489 16:37:20.788565 in-data: 84 60 60 08 00 00 00 00
9490 16:37:20.795038 ELOG: Event(91) added with size 10 at 2024-06-17 16:37:20 UTC
9491 16:37:20.798222 Chrome EC: clear events_b mask to 0x0000000020004000
9492 16:37:20.804680 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9493 16:37:20.808145 in-header: 03 fd 00 00 00 00 00 00
9494 16:37:20.811346 in-data:
9495 16:37:20.814814 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9496 16:37:20.818218 Writing coreboot table at 0xffe64000
9497 16:37:20.824980 0. 000000000010a000-0000000000113fff: RAMSTAGE
9498 16:37:20.828102 1. 0000000040000000-00000000400fffff: RAM
9499 16:37:20.831218 2. 0000000040100000-000000004032afff: RAMSTAGE
9500 16:37:20.834873 3. 000000004032b000-00000000545fffff: RAM
9501 16:37:20.837995 4. 0000000054600000-000000005465ffff: BL31
9502 16:37:20.844480 5. 0000000054660000-00000000ffe63fff: RAM
9503 16:37:20.847821 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9504 16:37:20.851326 7. 0000000100000000-000000023fffffff: RAM
9505 16:37:20.854627 Passing 5 GPIOs to payload:
9506 16:37:20.857944 NAME | PORT | POLARITY | VALUE
9507 16:37:20.864702 EC in RW | 0x000000aa | low | undefined
9508 16:37:20.867560 EC interrupt | 0x00000005 | low | undefined
9509 16:37:20.874237 TPM interrupt | 0x000000ab | high | undefined
9510 16:37:20.877734 SD card detect | 0x00000011 | high | undefined
9511 16:37:20.880916 speaker enable | 0x00000093 | high | undefined
9512 16:37:20.887710 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9513 16:37:20.890561 in-header: 03 f9 00 00 02 00 00 00
9514 16:37:20.891011 in-data: 02 00
9515 16:37:20.893839 ADC[4]: Raw value=903400 ID=7
9516 16:37:20.897195 ADC[3]: Raw value=213282 ID=1
9517 16:37:20.897767 RAM Code: 0x71
9518 16:37:20.900713 ADC[6]: Raw value=75406 ID=0
9519 16:37:20.903934 ADC[5]: Raw value=212912 ID=1
9520 16:37:20.904576 SKU Code: 0x1
9521 16:37:20.910501 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9fa9
9522 16:37:20.913654 coreboot table: 964 bytes.
9523 16:37:20.917256 IMD ROOT 0. 0xfffff000 0x00001000
9524 16:37:20.920540 IMD SMALL 1. 0xffffe000 0x00001000
9525 16:37:20.923795 RO MCACHE 2. 0xffffc000 0x00001104
9526 16:37:20.927074 CONSOLE 3. 0xfff7c000 0x00080000
9527 16:37:20.930395 FMAP 4. 0xfff7b000 0x00000452
9528 16:37:20.933758 TIME STAMP 5. 0xfff7a000 0x00000910
9529 16:37:20.937050 VBOOT WORK 6. 0xfff66000 0x00014000
9530 16:37:20.940142 RAMOOPS 7. 0xffe66000 0x00100000
9531 16:37:20.943435 COREBOOT 8. 0xffe64000 0x00002000
9532 16:37:20.943867 IMD small region:
9533 16:37:20.946669 IMD ROOT 0. 0xffffec00 0x00000400
9534 16:37:20.950016 VPD 1. 0xffffeb80 0x0000006c
9535 16:37:20.953510 MMC STATUS 2. 0xffffeb60 0x00000004
9536 16:37:20.959791 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9537 16:37:20.966910 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9538 16:37:21.006319 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9539 16:37:21.009726 Checking segment from ROM address 0x40100000
9540 16:37:21.013123 Checking segment from ROM address 0x4010001c
9541 16:37:21.019508 Loading segment from ROM address 0x40100000
9542 16:37:21.019825 code (compression=0)
9543 16:37:21.029659 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9544 16:37:21.036368 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9545 16:37:21.036786 it's not compressed!
9546 16:37:21.042391 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9547 16:37:21.048996 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9548 16:37:21.067101 Loading segment from ROM address 0x4010001c
9549 16:37:21.067511 Entry Point 0x80000000
9550 16:37:21.070398 Loaded segments
9551 16:37:21.073735 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9552 16:37:21.079870 Jumping to boot code at 0x80000000(0xffe64000)
9553 16:37:21.086839 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9554 16:37:21.093394 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9555 16:37:21.100981 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9556 16:37:21.104393 Checking segment from ROM address 0x40100000
9557 16:37:21.107809 Checking segment from ROM address 0x4010001c
9558 16:37:21.114622 Loading segment from ROM address 0x40100000
9559 16:37:21.115035 code (compression=1)
9560 16:37:21.120852 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9561 16:37:21.130982 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9562 16:37:21.131374 using LZMA
9563 16:37:21.139482 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9564 16:37:21.146225 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9565 16:37:21.149466 Loading segment from ROM address 0x4010001c
9566 16:37:21.152916 Entry Point 0x54601000
9567 16:37:21.153305 Loaded segments
9568 16:37:21.156179 NOTICE: MT8192 bl31_setup
9569 16:37:21.163435 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9570 16:37:21.166678 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9571 16:37:21.169937 WARNING: region 0:
9572 16:37:21.173113 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9573 16:37:21.173496 WARNING: region 1:
9574 16:37:21.179890 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9575 16:37:21.183337 WARNING: region 2:
9576 16:37:21.186144 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9577 16:37:21.189503 WARNING: region 3:
9578 16:37:21.193186 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9579 16:37:21.196086 WARNING: region 4:
9580 16:37:21.202895 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9581 16:37:21.203229 WARNING: region 5:
9582 16:37:21.206015 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9583 16:37:21.209368 WARNING: region 6:
9584 16:37:21.213238 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 16:37:21.215973 WARNING: region 7:
9586 16:37:21.219396 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9587 16:37:21.226236 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9588 16:37:21.229480 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9589 16:37:21.235658 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9590 16:37:21.238936 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9591 16:37:21.242239 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9592 16:37:21.248819 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9593 16:37:21.252148 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9594 16:37:21.255540 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9595 16:37:21.262147 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9596 16:37:21.265632 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9597 16:37:21.272293 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9598 16:37:21.275884 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9599 16:37:21.279152 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9600 16:37:21.285634 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9601 16:37:21.289063 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9602 16:37:21.292439 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9603 16:37:21.298559 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9604 16:37:21.301871 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9605 16:37:21.308563 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9606 16:37:21.312103 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9607 16:37:21.315432 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9608 16:37:21.322071 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9609 16:37:21.324782 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9610 16:37:21.331800 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9611 16:37:21.335248 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9612 16:37:21.338467 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9613 16:37:21.345154 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9614 16:37:21.347932 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9615 16:37:21.354643 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9616 16:37:21.357797 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9617 16:37:21.364911 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9618 16:37:21.367769 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9619 16:37:21.371193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9620 16:37:21.374533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9621 16:37:21.381325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9622 16:37:21.384521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9623 16:37:21.387700 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9624 16:37:21.390973 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9625 16:37:21.397579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9626 16:37:21.400894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9627 16:37:21.404045 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9628 16:37:21.407391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9629 16:37:21.414282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9630 16:37:21.417820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9631 16:37:21.420433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9632 16:37:21.427690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9633 16:37:21.430956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9634 16:37:21.433922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9635 16:37:21.440603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9636 16:37:21.443789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9637 16:37:21.447049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9638 16:37:21.453691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9639 16:37:21.457087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9640 16:37:21.463924 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9641 16:37:21.467146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9642 16:37:21.473615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9643 16:37:21.476965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9644 16:37:21.480286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9645 16:37:21.487196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9646 16:37:21.490445 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9647 16:37:21.496909 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9648 16:37:21.500161 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9649 16:37:21.506930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9650 16:37:21.510448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9651 16:37:21.516806 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9652 16:37:21.520389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9653 16:37:21.523707 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9654 16:37:21.529820 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9655 16:37:21.533124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9656 16:37:21.539768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9657 16:37:21.543191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9658 16:37:21.549771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9659 16:37:21.553191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9660 16:37:21.559189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9661 16:37:21.562689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9662 16:37:21.569324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9663 16:37:21.572735 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9664 16:37:21.576168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9665 16:37:21.582720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9666 16:37:21.586031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9667 16:37:21.592738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9668 16:37:21.596156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9669 16:37:21.602795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9670 16:37:21.605871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9671 16:37:21.612398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9672 16:37:21.615785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9673 16:37:21.619156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9674 16:37:21.625912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9675 16:37:21.628786 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9676 16:37:21.635424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9677 16:37:21.638693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9678 16:37:21.645491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9679 16:37:21.648913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9680 16:37:21.655705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9681 16:37:21.658896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9682 16:37:21.662193 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9683 16:37:21.668375 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9684 16:37:21.671966 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9685 16:37:21.675433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9686 16:37:21.678860 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9687 16:37:21.684820 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9688 16:37:21.688216 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9689 16:37:21.694835 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9690 16:37:21.698654 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9691 16:37:21.701287 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9692 16:37:21.708475 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9693 16:37:21.711319 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9694 16:37:21.718390 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9695 16:37:21.721439 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9696 16:37:21.724830 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9697 16:37:21.731369 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9698 16:37:21.734889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9699 16:37:21.741019 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9700 16:37:21.744264 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9701 16:37:21.750853 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9702 16:37:21.754288 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9703 16:37:21.757551 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9704 16:37:21.760891 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9705 16:37:21.767592 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9706 16:37:21.770985 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9707 16:37:21.773670 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9708 16:37:21.777043 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9709 16:37:21.783930 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9710 16:37:21.787428 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9711 16:37:21.790720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9712 16:37:21.796743 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9713 16:37:21.800048 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9714 16:37:21.807081 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9715 16:37:21.810013 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9716 16:37:21.813742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9717 16:37:21.820342 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9718 16:37:21.823547 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9719 16:37:21.830447 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9720 16:37:21.833901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9721 16:37:21.836582 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9722 16:37:21.843460 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9723 16:37:21.846675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9724 16:37:21.853844 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9725 16:37:21.856450 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9726 16:37:21.859806 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9727 16:37:21.866493 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9728 16:37:21.869821 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9729 16:37:21.876650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9730 16:37:21.880122 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9731 16:37:21.883515 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9732 16:37:21.889607 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9733 16:37:21.893079 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9734 16:37:21.899886 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9735 16:37:21.903277 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9736 16:37:21.906591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9737 16:37:21.912692 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9738 16:37:21.915973 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9739 16:37:21.919776 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9740 16:37:21.926135 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9741 16:37:21.929674 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9742 16:37:21.936155 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9743 16:37:21.939231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9744 16:37:21.945907 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9745 16:37:21.949499 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9746 16:37:21.952894 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9747 16:37:21.958920 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9748 16:37:21.962396 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9749 16:37:21.965894 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9750 16:37:21.972398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9751 16:37:21.975771 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9752 16:37:21.982526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9753 16:37:21.985312 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9754 16:37:21.988706 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9755 16:37:21.995597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9756 16:37:21.998864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9757 16:37:22.005629 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9758 16:37:22.009040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9759 16:37:22.012252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9760 16:37:22.018610 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9761 16:37:22.021947 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9762 16:37:22.028378 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9763 16:37:22.032284 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9764 16:37:22.034826 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9765 16:37:22.041637 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9766 16:37:22.044985 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9767 16:37:22.051619 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9768 16:37:22.054842 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9769 16:37:22.058614 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9770 16:37:22.064641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9771 16:37:22.067982 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9772 16:37:22.074682 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9773 16:37:22.077996 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9774 16:37:22.081311 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9775 16:37:22.088053 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9776 16:37:22.091402 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9777 16:37:22.098279 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9778 16:37:22.101783 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9779 16:37:22.107841 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9780 16:37:22.111330 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9781 16:37:22.114641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9782 16:37:22.120757 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9783 16:37:22.124185 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9784 16:37:22.130902 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9785 16:37:22.134174 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9786 16:37:22.140705 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9787 16:37:22.144422 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9788 16:37:22.147785 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9789 16:37:22.153852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9790 16:37:22.157345 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9791 16:37:22.164066 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9792 16:37:22.167255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9793 16:37:22.174079 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9794 16:37:22.177137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9795 16:37:22.180521 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9796 16:37:22.186852 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9797 16:37:22.190302 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9798 16:37:22.197144 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9799 16:37:22.200588 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9800 16:37:22.206799 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9801 16:37:22.210234 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9802 16:37:22.213527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9803 16:37:22.220203 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9804 16:37:22.223031 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9805 16:37:22.229822 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9806 16:37:22.233141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9807 16:37:22.240104 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9808 16:37:22.243406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9809 16:37:22.246604 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9810 16:37:22.252922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9811 16:37:22.256281 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9812 16:37:22.262490 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9813 16:37:22.265796 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9814 16:37:22.272695 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9815 16:37:22.276118 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9816 16:37:22.278821 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9817 16:37:22.282108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9818 16:37:22.289155 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9819 16:37:22.292293 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9820 16:37:22.295468 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9821 16:37:22.301767 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9822 16:37:22.305127 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9823 16:37:22.308438 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9824 16:37:22.315216 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9825 16:37:22.318579 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9826 16:37:22.322020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9827 16:37:22.327994 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9828 16:37:22.331328 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9829 16:37:22.337919 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9830 16:37:22.341415 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9831 16:37:22.344764 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9832 16:37:22.351521 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9833 16:37:22.354233 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9834 16:37:22.361365 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9835 16:37:22.364447 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9836 16:37:22.367910 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9837 16:37:22.374180 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9838 16:37:22.377538 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9839 16:37:22.380884 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9840 16:37:22.387471 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9841 16:37:22.390991 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9842 16:37:22.394252 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9843 16:37:22.400957 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9844 16:37:22.404223 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9845 16:37:22.407498 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9846 16:37:22.413802 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9847 16:37:22.417725 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9848 16:37:22.423918 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9849 16:37:22.427336 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9850 16:37:22.430652 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9851 16:37:22.436874 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9852 16:37:22.440191 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9853 16:37:22.447116 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9854 16:37:22.450443 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9855 16:37:22.453825 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9856 16:37:22.460095 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9857 16:37:22.463387 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9858 16:37:22.466690 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9859 16:37:22.469789 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9860 16:37:22.472899 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9861 16:37:22.479772 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9862 16:37:22.483260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9863 16:37:22.486574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9864 16:37:22.492692 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9865 16:37:22.496061 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9866 16:37:22.499199 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9867 16:37:22.502579 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9868 16:37:22.509399 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9869 16:37:22.512527 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9870 16:37:22.519417 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9871 16:37:22.522471 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9872 16:37:22.525729 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9873 16:37:22.532735 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9874 16:37:22.536142 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9875 16:37:22.542177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9876 16:37:22.545487 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9877 16:37:22.548931 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9878 16:37:22.555684 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9879 16:37:22.558898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9880 16:37:22.565389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9881 16:37:22.568806 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9882 16:37:22.575447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9883 16:37:22.578629 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9884 16:37:22.581917 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9885 16:37:22.588795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9886 16:37:22.591466 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9887 16:37:22.598399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9888 16:37:22.601579 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9889 16:37:22.608239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9890 16:37:22.611652 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9891 16:37:22.614967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9892 16:37:22.621544 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9893 16:37:22.624991 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9894 16:37:22.631055 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9895 16:37:22.634536 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9896 16:37:22.637747 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9897 16:37:22.644849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9898 16:37:22.648132 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9899 16:37:22.654826 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9900 16:37:22.657459 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9901 16:37:22.660702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9902 16:37:22.667579 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9903 16:37:22.671003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9904 16:37:22.677618 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9905 16:37:22.680436 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9906 16:37:22.687572 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9907 16:37:22.690913 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9908 16:37:22.694239 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9909 16:37:22.700526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9910 16:37:22.704083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9911 16:37:22.710633 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9912 16:37:22.714020 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9913 16:37:22.719991 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9914 16:37:22.723428 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9915 16:37:22.726902 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9916 16:37:22.733651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9917 16:37:22.736907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9918 16:37:22.743601 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9919 16:37:22.746487 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9920 16:37:22.753100 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9921 16:37:22.756826 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9922 16:37:22.759661 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9923 16:37:22.766507 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9924 16:37:22.770070 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9925 16:37:22.773310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9926 16:37:22.780154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9927 16:37:22.782972 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9928 16:37:22.789883 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9929 16:37:22.793178 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9930 16:37:22.799597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9931 16:37:22.802985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9932 16:37:22.806117 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9933 16:37:22.813087 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9934 16:37:22.816440 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9935 16:37:22.822708 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9936 16:37:22.825971 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9937 16:37:22.832941 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9938 16:37:22.835694 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9939 16:37:22.839069 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9940 16:37:22.845845 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9941 16:37:22.849349 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9942 16:37:22.856149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9943 16:37:22.858951 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9944 16:37:22.862868 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9945 16:37:22.869507 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9946 16:37:22.872321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9947 16:37:22.878888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9948 16:37:22.882047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9949 16:37:22.888961 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9950 16:37:22.892409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9951 16:37:22.898644 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9952 16:37:22.901973 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9953 16:37:22.905668 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9954 16:37:22.912138 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9955 16:37:22.915586 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9956 16:37:22.922336 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9957 16:37:22.925020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9958 16:37:22.931691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9959 16:37:22.935156 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9960 16:37:22.941838 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9961 16:37:22.945180 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9962 16:37:22.948381 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9963 16:37:22.954714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9964 16:37:22.958022 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9965 16:37:22.964900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9966 16:37:22.968343 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9967 16:37:22.974908 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9968 16:37:22.978384 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9969 16:37:22.984889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9970 16:37:22.988130 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9971 16:37:22.994377 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9972 16:37:22.997768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9973 16:37:23.001113 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9974 16:37:23.007922 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9975 16:37:23.011174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9976 16:37:23.017729 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9977 16:37:23.021041 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9978 16:37:23.027688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9979 16:37:23.031092 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9980 16:37:23.033762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9981 16:37:23.040496 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9982 16:37:23.044010 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9983 16:37:23.050734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9984 16:37:23.054006 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9985 16:37:23.060035 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9986 16:37:23.063532 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9987 16:37:23.070300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9988 16:37:23.073182 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9989 16:37:23.077016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9990 16:37:23.083483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9991 16:37:23.086814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9992 16:37:23.093032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9993 16:37:23.096540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9994 16:37:23.103447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9995 16:37:23.106368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9996 16:37:23.113196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9997 16:37:23.116590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9998 16:37:23.123138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9999 16:37:23.126449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10000 16:37:23.132978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10001 16:37:23.136245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10002 16:37:23.142903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10003 16:37:23.146123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10004 16:37:23.152884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10005 16:37:23.155567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10006 16:37:23.162198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10007 16:37:23.165628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10008 16:37:23.172400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10009 16:37:23.175942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10010 16:37:23.182116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10011 16:37:23.185462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10012 16:37:23.192284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10013 16:37:23.195513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10014 16:37:23.202346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10015 16:37:23.205100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10016 16:37:23.211848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10017 16:37:23.215321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10018 16:37:23.222073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10019 16:37:23.225365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10020 16:37:23.231763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10021 16:37:23.235188 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10022 16:37:23.238315 INFO: [APUAPC] vio 0
10023 16:37:23.241616 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10024 16:37:23.248285 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10025 16:37:23.251578 INFO: [APUAPC] D0_APC_0: 0x400510
10026 16:37:23.251659 INFO: [APUAPC] D0_APC_1: 0x0
10027 16:37:23.254968 INFO: [APUAPC] D0_APC_2: 0x1540
10028 16:37:23.258106 INFO: [APUAPC] D0_APC_3: 0x0
10029 16:37:23.261619 INFO: [APUAPC] D1_APC_0: 0xffffffff
10030 16:37:23.264645 INFO: [APUAPC] D1_APC_1: 0xffffffff
10031 16:37:23.268089 INFO: [APUAPC] D1_APC_2: 0x3fffff
10032 16:37:23.271467 INFO: [APUAPC] D1_APC_3: 0x0
10033 16:37:23.274877 INFO: [APUAPC] D2_APC_0: 0xffffffff
10034 16:37:23.278350 INFO: [APUAPC] D2_APC_1: 0xffffffff
10035 16:37:23.281034 INFO: [APUAPC] D2_APC_2: 0x3fffff
10036 16:37:23.284544 INFO: [APUAPC] D2_APC_3: 0x0
10037 16:37:23.287847 INFO: [APUAPC] D3_APC_0: 0xffffffff
10038 16:37:23.291341 INFO: [APUAPC] D3_APC_1: 0xffffffff
10039 16:37:23.294544 INFO: [APUAPC] D3_APC_2: 0x3fffff
10040 16:37:23.297932 INFO: [APUAPC] D3_APC_3: 0x0
10041 16:37:23.301109 INFO: [APUAPC] D4_APC_0: 0xffffffff
10042 16:37:23.304084 INFO: [APUAPC] D4_APC_1: 0xffffffff
10043 16:37:23.308017 INFO: [APUAPC] D4_APC_2: 0x3fffff
10044 16:37:23.311448 INFO: [APUAPC] D4_APC_3: 0x0
10045 16:37:23.314087 INFO: [APUAPC] D5_APC_0: 0xffffffff
10046 16:37:23.317424 INFO: [APUAPC] D5_APC_1: 0xffffffff
10047 16:37:23.320787 INFO: [APUAPC] D5_APC_2: 0x3fffff
10048 16:37:23.324343 INFO: [APUAPC] D5_APC_3: 0x0
10049 16:37:23.327617 INFO: [APUAPC] D6_APC_0: 0xffffffff
10050 16:37:23.330960 INFO: [APUAPC] D6_APC_1: 0xffffffff
10051 16:37:23.334208 INFO: [APUAPC] D6_APC_2: 0x3fffff
10052 16:37:23.337357 INFO: [APUAPC] D6_APC_3: 0x0
10053 16:37:23.340420 INFO: [APUAPC] D7_APC_0: 0xffffffff
10054 16:37:23.344392 INFO: [APUAPC] D7_APC_1: 0xffffffff
10055 16:37:23.347529 INFO: [APUAPC] D7_APC_2: 0x3fffff
10056 16:37:23.350947 INFO: [APUAPC] D7_APC_3: 0x0
10057 16:37:23.354253 INFO: [APUAPC] D8_APC_0: 0xffffffff
10058 16:37:23.357537 INFO: [APUAPC] D8_APC_1: 0xffffffff
10059 16:37:23.360679 INFO: [APUAPC] D8_APC_2: 0x3fffff
10060 16:37:23.363928 INFO: [APUAPC] D8_APC_3: 0x0
10061 16:37:23.367066 INFO: [APUAPC] D9_APC_0: 0xffffffff
10062 16:37:23.370732 INFO: [APUAPC] D9_APC_1: 0xffffffff
10063 16:37:23.373447 INFO: [APUAPC] D9_APC_2: 0x3fffff
10064 16:37:23.376891 INFO: [APUAPC] D9_APC_3: 0x0
10065 16:37:23.380227 INFO: [APUAPC] D10_APC_0: 0xffffffff
10066 16:37:23.383651 INFO: [APUAPC] D10_APC_1: 0xffffffff
10067 16:37:23.387105 INFO: [APUAPC] D10_APC_2: 0x3fffff
10068 16:37:23.390500 INFO: [APUAPC] D10_APC_3: 0x0
10069 16:37:23.393255 INFO: [APUAPC] D11_APC_0: 0xffffffff
10070 16:37:23.396678 INFO: [APUAPC] D11_APC_1: 0xffffffff
10071 16:37:23.400185 INFO: [APUAPC] D11_APC_2: 0x3fffff
10072 16:37:23.403610 INFO: [APUAPC] D11_APC_3: 0x0
10073 16:37:23.406909 INFO: [APUAPC] D12_APC_0: 0xffffffff
10074 16:37:23.410273 INFO: [APUAPC] D12_APC_1: 0xffffffff
10075 16:37:23.413502 INFO: [APUAPC] D12_APC_2: 0x3fffff
10076 16:37:23.416656 INFO: [APUAPC] D12_APC_3: 0x0
10077 16:37:23.419978 INFO: [APUAPC] D13_APC_0: 0xffffffff
10078 16:37:23.423352 INFO: [APUAPC] D13_APC_1: 0xffffffff
10079 16:37:23.426806 INFO: [APUAPC] D13_APC_2: 0x3fffff
10080 16:37:23.430282 INFO: [APUAPC] D13_APC_3: 0x0
10081 16:37:23.432895 INFO: [APUAPC] D14_APC_0: 0xffffffff
10082 16:37:23.436363 INFO: [APUAPC] D14_APC_1: 0xffffffff
10083 16:37:23.439816 INFO: [APUAPC] D14_APC_2: 0x3fffff
10084 16:37:23.443073 INFO: [APUAPC] D14_APC_3: 0x0
10085 16:37:23.446329 INFO: [APUAPC] D15_APC_0: 0xffffffff
10086 16:37:23.449471 INFO: [APUAPC] D15_APC_1: 0xffffffff
10087 16:37:23.453162 INFO: [APUAPC] D15_APC_2: 0x3fffff
10088 16:37:23.456320 INFO: [APUAPC] D15_APC_3: 0x0
10089 16:37:23.459634 INFO: [APUAPC] APC_CON: 0x4
10090 16:37:23.463048 INFO: [NOCDAPC] D0_APC_0: 0x0
10091 16:37:23.465829 INFO: [NOCDAPC] D0_APC_1: 0x0
10092 16:37:23.465939 INFO: [NOCDAPC] D1_APC_0: 0x0
10093 16:37:23.469116 INFO: [NOCDAPC] D1_APC_1: 0xfff
10094 16:37:23.472391 INFO: [NOCDAPC] D2_APC_0: 0x0
10095 16:37:23.475677 INFO: [NOCDAPC] D2_APC_1: 0xfff
10096 16:37:23.479407 INFO: [NOCDAPC] D3_APC_0: 0x0
10097 16:37:23.482635 INFO: [NOCDAPC] D3_APC_1: 0xfff
10098 16:37:23.486141 INFO: [NOCDAPC] D4_APC_0: 0x0
10099 16:37:23.488899 INFO: [NOCDAPC] D4_APC_1: 0xfff
10100 16:37:23.492310 INFO: [NOCDAPC] D5_APC_0: 0x0
10101 16:37:23.495802 INFO: [NOCDAPC] D5_APC_1: 0xfff
10102 16:37:23.499146 INFO: [NOCDAPC] D6_APC_0: 0x0
10103 16:37:23.501918 INFO: [NOCDAPC] D6_APC_1: 0xfff
10104 16:37:23.502023 INFO: [NOCDAPC] D7_APC_0: 0x0
10105 16:37:23.505361 INFO: [NOCDAPC] D7_APC_1: 0xfff
10106 16:37:23.508899 INFO: [NOCDAPC] D8_APC_0: 0x0
10107 16:37:23.512172 INFO: [NOCDAPC] D8_APC_1: 0xfff
10108 16:37:23.515690 INFO: [NOCDAPC] D9_APC_0: 0x0
10109 16:37:23.519129 INFO: [NOCDAPC] D9_APC_1: 0xfff
10110 16:37:23.521764 INFO: [NOCDAPC] D10_APC_0: 0x0
10111 16:37:23.525683 INFO: [NOCDAPC] D10_APC_1: 0xfff
10112 16:37:23.528903 INFO: [NOCDAPC] D11_APC_0: 0x0
10113 16:37:23.532224 INFO: [NOCDAPC] D11_APC_1: 0xfff
10114 16:37:23.535720 INFO: [NOCDAPC] D12_APC_0: 0x0
10115 16:37:23.538334 INFO: [NOCDAPC] D12_APC_1: 0xfff
10116 16:37:23.541760 INFO: [NOCDAPC] D13_APC_0: 0x0
10117 16:37:23.545198 INFO: [NOCDAPC] D13_APC_1: 0xfff
10118 16:37:23.545275 INFO: [NOCDAPC] D14_APC_0: 0x0
10119 16:37:23.548490 INFO: [NOCDAPC] D14_APC_1: 0xfff
10120 16:37:23.551913 INFO: [NOCDAPC] D15_APC_0: 0x0
10121 16:37:23.555253 INFO: [NOCDAPC] D15_APC_1: 0xfff
10122 16:37:23.558357 INFO: [NOCDAPC] APC_CON: 0x4
10123 16:37:23.561514 INFO: [APUAPC] set_apusys_apc done
10124 16:37:23.564606 INFO: [DEVAPC] devapc_init done
10125 16:37:23.568494 INFO: GICv3 without legacy support detected.
10126 16:37:23.575027 INFO: ARM GICv3 driver initialized in EL3
10127 16:37:23.578472 INFO: Maximum SPI INTID supported: 639
10128 16:37:23.581725 INFO: BL31: Initializing runtime services
10129 16:37:23.588218 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10130 16:37:23.591183 INFO: SPM: enable CPC mode
10131 16:37:23.594610 INFO: mcdi ready for mcusys-off-idle and system suspend
10132 16:37:23.601550 INFO: BL31: Preparing for EL3 exit to normal world
10133 16:37:23.604291 INFO: Entry point address = 0x80000000
10134 16:37:23.604396 INFO: SPSR = 0x8
10135 16:37:23.611267
10136 16:37:23.611345
10137 16:37:23.611425
10138 16:37:23.614095 Starting depthcharge on Spherion...
10139 16:37:23.614223
10140 16:37:23.614351 Wipe memory regions:
10141 16:37:23.614463
10142 16:37:23.615210 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10143 16:37:23.615348 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10144 16:37:23.615445 Setting prompt string to ['asurada:']
10145 16:37:23.615545 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10146 16:37:23.617529 [0x00000040000000, 0x00000054600000)
10147 16:37:23.740044
10148 16:37:23.740219 [0x00000054660000, 0x00000080000000)
10149 16:37:24.001009
10150 16:37:24.001140 [0x000000821a7280, 0x000000ffe64000)
10151 16:37:24.745918
10152 16:37:24.746083 [0x00000100000000, 0x00000240000000)
10153 16:37:26.635582
10154 16:37:26.638976 Initializing XHCI USB controller at 0x11200000.
10155 16:37:27.678635
10156 16:37:27.681491 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10157 16:37:27.681575
10158 16:37:27.681644
10159 16:37:27.681932 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10161 16:37:27.782215 asurada: tftpboot 192.168.201.1 14396177/tftp-deploy-2f5rhium/kernel/image.itb 14396177/tftp-deploy-2f5rhium/kernel/cmdline
10162 16:37:27.782364 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10163 16:37:27.782444 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10164 16:37:27.786351 tftpboot 192.168.201.1 14396177/tftp-deploy-2f5rhium/kernel/image.ittp-deploy-2f5rhium/kernel/cmdline
10165 16:37:27.786433
10166 16:37:27.786497 Waiting for link
10167 16:37:27.944535
10168 16:37:27.944704 R8152: Initializing
10169 16:37:27.944805
10170 16:37:27.947957 Version 6 (ocp_data = 5c30)
10171 16:37:27.948056
10172 16:37:27.951343 R8152: Done initializing
10173 16:37:27.951417
10174 16:37:27.951477 Adding net device
10175 16:37:29.857307
10176 16:37:29.857497 done.
10177 16:37:29.857603
10178 16:37:29.857697 MAC: 00:e0:4c:68:02:81
10179 16:37:29.857783
10180 16:37:29.860758 Sending DHCP discover... done.
10181 16:37:29.860861
10182 16:37:29.864208 Waiting for reply... done.
10183 16:37:29.864304
10184 16:37:29.867077 Sending DHCP request... done.
10185 16:37:29.867160
10186 16:37:29.872402 Waiting for reply... done.
10187 16:37:29.872482
10188 16:37:29.872544 My ip is 192.168.201.14
10189 16:37:29.872603
10190 16:37:29.875089 The DHCP server ip is 192.168.201.1
10191 16:37:29.875170
10192 16:37:29.882149 TFTP server IP predefined by user: 192.168.201.1
10193 16:37:29.882266
10194 16:37:29.888378 Bootfile predefined by user: 14396177/tftp-deploy-2f5rhium/kernel/image.itb
10195 16:37:29.888460
10196 16:37:29.891801 Sending tftp read request... done.
10197 16:37:29.891880
10198 16:37:29.895819 Waiting for the transfer...
10199 16:37:29.895892
10200 16:37:30.438731 00000000 ################################################################
10201 16:37:30.438874
10202 16:37:30.987523 00080000 ################################################################
10203 16:37:30.987653
10204 16:37:31.546112 00100000 ################################################################
10205 16:37:31.546298
10206 16:37:32.084437 00180000 ################################################################
10207 16:37:32.084578
10208 16:37:32.638298 00200000 ################################################################
10209 16:37:32.638713
10210 16:37:33.200651 00280000 ################################################################
10211 16:37:33.200784
10212 16:37:33.765999 00300000 ################################################################
10213 16:37:33.766171
10214 16:37:34.359369 00380000 ################################################################
10215 16:37:34.359531
10216 16:37:34.931303 00400000 ################################################################
10217 16:37:34.931437
10218 16:37:35.521719 00480000 ################################################################
10219 16:37:35.521859
10220 16:37:36.080667 00500000 ################################################################
10221 16:37:36.080796
10222 16:37:36.658791 00580000 ################################################################
10223 16:37:36.659274
10224 16:37:37.227016 00600000 ################################################################
10225 16:37:37.227503
10226 16:37:37.823099 00680000 ################################################################
10227 16:37:37.823512
10228 16:37:38.397014 00700000 ################################################################
10229 16:37:38.397222
10230 16:37:38.953873 00780000 ################################################################
10231 16:37:38.954042
10232 16:37:39.499053 00800000 ################################################################
10233 16:37:39.499190
10234 16:37:40.050029 00880000 ################################################################
10235 16:37:40.050192
10236 16:37:40.644322 00900000 ################################################################
10237 16:37:40.644461
10238 16:37:41.233587 00980000 ################################################################
10239 16:37:41.233720
10240 16:37:41.843762 00a00000 ################################################################
10241 16:37:41.844239
10242 16:37:42.464870 00a80000 ################################################################
10243 16:37:42.465028
10244 16:37:43.019804 00b00000 ################################################################
10245 16:37:43.019960
10246 16:37:43.612830 00b80000 ################################################################
10247 16:37:43.613406
10248 16:37:44.209472 00c00000 ################################################################
10249 16:37:44.209637
10250 16:37:44.758059 00c80000 ################################################################
10251 16:37:44.758214
10252 16:37:45.350435 00d00000 ################################################################
10253 16:37:45.350597
10254 16:37:45.950276 00d80000 ################################################################
10255 16:37:45.950410
10256 16:37:46.518833 00e00000 ################################################################
10257 16:37:46.519460
10258 16:37:47.095007 00e80000 ################################################################
10259 16:37:47.095169
10260 16:37:47.641343 00f00000 ################################################################
10261 16:37:47.641508
10262 16:37:48.180429 00f80000 ################################################################
10263 16:37:48.180608
10264 16:37:48.769485 01000000 ################################################################
10265 16:37:48.769943
10266 16:37:49.357554 01080000 ################################################################
10267 16:37:49.357693
10268 16:37:49.935151 01100000 ################################################################
10269 16:37:49.935681
10270 16:37:50.529024 01180000 ################################################################
10271 16:37:50.529193
10272 16:37:51.086109 01200000 ################################################################
10273 16:37:51.086298
10274 16:37:51.646283 01280000 ################################################################
10275 16:37:51.646453
10276 16:37:52.189930 01300000 ################################################################
10277 16:37:52.190097
10278 16:37:52.726996 01380000 ################################################################
10279 16:37:52.727164
10280 16:37:53.315987 01400000 ################################################################
10281 16:37:53.316132
10282 16:37:53.885319 01480000 ################################################################
10283 16:37:53.885454
10284 16:37:54.499543 01500000 ################################################################
10285 16:37:54.500038
10286 16:37:55.120837 01580000 ################################################################
10287 16:37:55.121032
10288 16:37:55.709800 01600000 ################################################################
10289 16:37:55.710488
10290 16:37:56.340181 01680000 ################################################################
10291 16:37:56.340828
10292 16:37:56.933223 01700000 ################################################################
10293 16:37:56.933782
10294 16:37:57.556977 01780000 ################################################################
10295 16:37:57.557501
10296 16:37:58.203642 01800000 ################################################################
10297 16:37:58.204347
10298 16:37:58.827668 01880000 ################################################################
10299 16:37:58.827820
10300 16:37:59.364483 01900000 ################################################################
10301 16:37:59.364630
10302 16:37:59.971833 01980000 ################################################################
10303 16:37:59.972399
10304 16:38:00.609621 01a00000 ################################################################
10305 16:38:00.610142
10306 16:38:01.218332 01a80000 ################################################################
10307 16:38:01.218479
10308 16:38:01.840450 01b00000 ################################################################
10309 16:38:01.840601
10310 16:38:02.438225 01b80000 ################################################################
10311 16:38:02.438366
10312 16:38:03.048377 01c00000 ################################################################
10313 16:38:03.048526
10314 16:38:03.656706 01c80000 ################################################################
10315 16:38:03.657226
10316 16:38:04.286619 01d00000 ################################################################
10317 16:38:04.287153
10318 16:38:04.891036 01d80000 ################################################################
10319 16:38:04.891179
10320 16:38:05.402523 01e00000 ########################################################## done.
10321 16:38:05.402663
10322 16:38:05.405642 The bootfile was 31924638 bytes long.
10323 16:38:05.405745
10324 16:38:05.408917 Sending tftp read request... done.
10325 16:38:05.409015
10326 16:38:05.409104 Waiting for the transfer...
10327 16:38:05.412122
10328 16:38:05.412219 00000000 # done.
10329 16:38:05.412310
10330 16:38:05.419038 Command line loaded dynamically from TFTP file: 14396177/tftp-deploy-2f5rhium/kernel/cmdline
10331 16:38:05.419143
10332 16:38:05.442329 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10333 16:38:05.442450
10334 16:38:05.442543 Loading FIT.
10335 16:38:05.445667
10336 16:38:05.445768 Image ramdisk-1 has 18746589 bytes.
10337 16:38:05.445858
10338 16:38:05.448884 Image fdt-1 has 47258 bytes.
10339 16:38:05.448985
10340 16:38:05.452123 Image kernel-1 has 13128753 bytes.
10341 16:38:05.452224
10342 16:38:05.461574 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10343 16:38:05.461662
10344 16:38:05.478168 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10345 16:38:05.478349
10346 16:38:05.485177 Choosing best match conf-1 for compat google,spherion-rev2.
10347 16:38:05.488753
10348 16:38:05.492711 Connected to device vid:did:rid of 1ae0:0028:00
10349 16:38:05.499983
10350 16:38:05.503172 tpm_get_response: command 0x17b, return code 0x0
10351 16:38:05.503379
10352 16:38:05.506774 ec_init: CrosEC protocol v3 supported (256, 248)
10353 16:38:05.512324
10354 16:38:05.515316 tpm_cleanup: add release locality here.
10355 16:38:05.515715
10356 16:38:05.516109 Shutting down all USB controllers.
10357 16:38:05.518434
10358 16:38:05.518527 Removing current net device
10359 16:38:05.518660
10360 16:38:05.524955 Exiting depthcharge with code 4 at timestamp: 71356649
10361 16:38:05.525036
10362 16:38:05.528117 LZMA decompressing kernel-1 to 0x821a6718
10363 16:38:05.528198
10364 16:38:05.531253 LZMA decompressing kernel-1 to 0x40000000
10365 16:38:07.148654
10366 16:38:07.148812 jumping to kernel
10367 16:38:07.149288 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10368 16:38:07.149414 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10369 16:38:07.149501 Setting prompt string to ['Linux version [0-9]']
10370 16:38:07.149579 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10371 16:38:07.149658 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10372 16:38:07.231119
10373 16:38:07.234199 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10374 16:38:07.237791 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10375 16:38:07.238347 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10376 16:38:07.238947 Setting prompt string to []
10377 16:38:07.239556 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10378 16:38:07.240105 Using line separator: #'\n'#
10379 16:38:07.240605 No login prompt set.
10380 16:38:07.241144 Parsing kernel messages
10381 16:38:07.241638 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10382 16:38:07.242489 [login-action] Waiting for messages, (timeout 00:03:43)
10383 16:38:07.242979 Waiting using forced prompt support (timeout 00:01:51)
10384 16:38:07.256962 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10385 16:38:07.260177 [ 0.000000] random: crng init done
10386 16:38:07.267037 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10387 16:38:07.270297 [ 0.000000] efi: UEFI not found.
10388 16:38:07.276883 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10389 16:38:07.286201 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10390 16:38:07.296221 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10391 16:38:07.302905 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10392 16:38:07.309209 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10393 16:38:07.316168 [ 0.000000] printk: bootconsole [mtk8250] enabled
10394 16:38:07.322661 [ 0.000000] NUMA: No NUMA configuration found
10395 16:38:07.329129 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10396 16:38:07.335502 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10397 16:38:07.335586 [ 0.000000] Zone ranges:
10398 16:38:07.342004 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10399 16:38:07.345831 [ 0.000000] DMA32 empty
10400 16:38:07.351995 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10401 16:38:07.355877 [ 0.000000] Movable zone start for each node
10402 16:38:07.359092 [ 0.000000] Early memory node ranges
10403 16:38:07.365610 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10404 16:38:07.372182 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10405 16:38:07.378890 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10406 16:38:07.385283 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10407 16:38:07.391984 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10408 16:38:07.398353 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10409 16:38:07.455755 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10410 16:38:07.461785 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10411 16:38:07.468727 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10412 16:38:07.471846 [ 0.000000] psci: probing for conduit method from DT.
10413 16:38:07.478341 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10414 16:38:07.482229 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10415 16:38:07.488607 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10416 16:38:07.491802 [ 0.000000] psci: SMC Calling Convention v1.2
10417 16:38:07.498128 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10418 16:38:07.501413 [ 0.000000] Detected VIPT I-cache on CPU0
10419 16:38:07.508025 [ 0.000000] CPU features: detected: GIC system register CPU interface
10420 16:38:07.514123 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10421 16:38:07.520948 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10422 16:38:07.527373 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10423 16:38:07.537120 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10424 16:38:07.543695 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10425 16:38:07.546571 [ 0.000000] alternatives: applying boot alternatives
10426 16:38:07.553864 [ 0.000000] Fallback order for Node 0: 0
10427 16:38:07.560695 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10428 16:38:07.563946 [ 0.000000] Policy zone: Normal
10429 16:38:07.587312 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10430 16:38:07.597003 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10431 16:38:07.608759 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10432 16:38:07.618195 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10433 16:38:07.625130 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10434 16:38:07.628449 <6>[ 0.000000] software IO TLB: area num 8.
10435 16:38:07.684575 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10436 16:38:07.834796 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10437 16:38:07.841371 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10438 16:38:07.847981 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10439 16:38:07.851123 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10440 16:38:07.857633 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10441 16:38:07.864792 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10442 16:38:07.867970 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10443 16:38:07.877418 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10444 16:38:07.884394 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10445 16:38:07.890814 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10446 16:38:07.897289 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10447 16:38:07.900446 <6>[ 0.000000] GICv3: 608 SPIs implemented
10448 16:38:07.903956 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10449 16:38:07.910613 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10450 16:38:07.913888 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10451 16:38:07.920335 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10452 16:38:07.933185 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10453 16:38:07.946143 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10454 16:38:07.952777 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10455 16:38:07.961106 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10456 16:38:07.974197 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10457 16:38:07.980528 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10458 16:38:07.987576 <6>[ 0.009182] Console: colour dummy device 80x25
10459 16:38:07.997272 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10460 16:38:08.003803 <6>[ 0.024400] pid_max: default: 32768 minimum: 301
10461 16:38:08.007519 <6>[ 0.029301] LSM: Security Framework initializing
10462 16:38:08.013635 <6>[ 0.034241] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 16:38:08.023672 <6>[ 0.042103] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10464 16:38:08.033763 <6>[ 0.051572] cblist_init_generic: Setting adjustable number of callback queues.
10465 16:38:08.040034 <6>[ 0.059015] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 16:38:08.046720 <6>[ 0.065355] cblist_init_generic: Setting adjustable number of callback queues.
10467 16:38:08.053398 <6>[ 0.072782] cblist_init_generic: Setting shift to 3 and lim to 1.
10468 16:38:08.056543 <6>[ 0.079183] rcu: Hierarchical SRCU implementation.
10469 16:38:08.062981 <6>[ 0.084198] rcu: Max phase no-delay instances is 1000.
10470 16:38:08.070141 <6>[ 0.091232] EFI services will not be available.
10471 16:38:08.072831 <6>[ 0.096217] smp: Bringing up secondary CPUs ...
10472 16:38:08.081805 <6>[ 0.101269] Detected VIPT I-cache on CPU1
10473 16:38:08.088306 <6>[ 0.101342] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10474 16:38:08.095438 <6>[ 0.101375] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10475 16:38:08.098559 <6>[ 0.101713] Detected VIPT I-cache on CPU2
10476 16:38:08.105109 <6>[ 0.101767] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10477 16:38:08.115257 <6>[ 0.101787] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10478 16:38:08.118425 <6>[ 0.102043] Detected VIPT I-cache on CPU3
10479 16:38:08.124820 <6>[ 0.102090] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10480 16:38:08.131267 <6>[ 0.102104] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10481 16:38:08.135086 <6>[ 0.102408] CPU features: detected: Spectre-v4
10482 16:38:08.141458 <6>[ 0.102414] CPU features: detected: Spectre-BHB
10483 16:38:08.144586 <6>[ 0.102419] Detected PIPT I-cache on CPU4
10484 16:38:08.151311 <6>[ 0.102478] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10485 16:38:08.157833 <6>[ 0.102494] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10486 16:38:08.164374 <6>[ 0.102788] Detected PIPT I-cache on CPU5
10487 16:38:08.170985 <6>[ 0.102851] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10488 16:38:08.177948 <6>[ 0.102868] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10489 16:38:08.181216 <6>[ 0.103150] Detected PIPT I-cache on CPU6
10490 16:38:08.187649 <6>[ 0.103214] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10491 16:38:08.197337 <6>[ 0.103230] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10492 16:38:08.200515 <6>[ 0.103527] Detected PIPT I-cache on CPU7
10493 16:38:08.207379 <6>[ 0.103586] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10494 16:38:08.214010 <6>[ 0.103601] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10495 16:38:08.217028 <6>[ 0.103647] smp: Brought up 1 node, 8 CPUs
10496 16:38:08.223484 <6>[ 0.245006] SMP: Total of 8 processors activated.
10497 16:38:08.230595 <6>[ 0.249958] CPU features: detected: 32-bit EL0 Support
10498 16:38:08.236968 <6>[ 0.255321] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10499 16:38:08.243443 <6>[ 0.264121] CPU features: detected: Common not Private translations
10500 16:38:08.249847 <6>[ 0.270637] CPU features: detected: CRC32 instructions
10501 16:38:08.256898 <6>[ 0.275989] CPU features: detected: RCpc load-acquire (LDAPR)
10502 16:38:08.259834 <6>[ 0.281949] CPU features: detected: LSE atomic instructions
10503 16:38:08.266197 <6>[ 0.287730] CPU features: detected: Privileged Access Never
10504 16:38:08.273205 <6>[ 0.293510] CPU features: detected: RAS Extension Support
10505 16:38:08.279629 <6>[ 0.299119] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10506 16:38:08.282928 <6>[ 0.306338] CPU: All CPU(s) started at EL2
10507 16:38:08.289530 <6>[ 0.310655] alternatives: applying system-wide alternatives
10508 16:38:08.299668 <6>[ 0.321473] devtmpfs: initialized
10509 16:38:08.315126 <6>[ 0.330337] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10510 16:38:08.322177 <6>[ 0.340298] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10511 16:38:08.328436 <6>[ 0.348342] pinctrl core: initialized pinctrl subsystem
10512 16:38:08.332105 <6>[ 0.355018] DMI not present or invalid.
10513 16:38:08.338660 <6>[ 0.359432] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10514 16:38:08.348453 <6>[ 0.366285] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10515 16:38:08.354954 <6>[ 0.373870] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10516 16:38:08.364695 <6>[ 0.382089] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10517 16:38:08.368395 <6>[ 0.390330] audit: initializing netlink subsys (disabled)
10518 16:38:08.378215 <5>[ 0.396025] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10519 16:38:08.384875 <6>[ 0.396747] thermal_sys: Registered thermal governor 'step_wise'
10520 16:38:08.391255 <6>[ 0.403993] thermal_sys: Registered thermal governor 'power_allocator'
10521 16:38:08.394296 <6>[ 0.410249] cpuidle: using governor menu
10522 16:38:08.401107 <6>[ 0.421208] NET: Registered PF_QIPCRTR protocol family
10523 16:38:08.407672 <6>[ 0.426696] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10524 16:38:08.414196 <6>[ 0.433799] ASID allocator initialised with 32768 entries
10525 16:38:08.417271 <6>[ 0.440383] Serial: AMBA PL011 UART driver
10526 16:38:08.428287 <4>[ 0.449285] Trying to register duplicate clock ID: 134
10527 16:38:08.486355 <6>[ 0.510972] KASLR enabled
10528 16:38:08.500472 <6>[ 0.518692] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10529 16:38:08.507106 <6>[ 0.525705] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10530 16:38:08.513979 <6>[ 0.532196] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10531 16:38:08.520617 <6>[ 0.539199] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10532 16:38:08.526883 <6>[ 0.545685] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10533 16:38:08.533343 <6>[ 0.552689] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10534 16:38:08.539910 <6>[ 0.559175] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10535 16:38:08.546778 <6>[ 0.566178] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10536 16:38:08.549591 <6>[ 0.573597] ACPI: Interpreter disabled.
10537 16:38:08.558512 <6>[ 0.580030] iommu: Default domain type: Translated
10538 16:38:08.565525 <6>[ 0.585142] iommu: DMA domain TLB invalidation policy: strict mode
10539 16:38:08.568748 <5>[ 0.591801] SCSI subsystem initialized
10540 16:38:08.575307 <6>[ 0.595965] usbcore: registered new interface driver usbfs
10541 16:38:08.581928 <6>[ 0.601696] usbcore: registered new interface driver hub
10542 16:38:08.584850 <6>[ 0.607248] usbcore: registered new device driver usb
10543 16:38:08.591812 <6>[ 0.613348] pps_core: LinuxPPS API ver. 1 registered
10544 16:38:08.602225 <6>[ 0.618542] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10545 16:38:08.605482 <6>[ 0.627888] PTP clock support registered
10546 16:38:08.608598 <6>[ 0.632130] EDAC MC: Ver: 3.0.0
10547 16:38:08.616076 <6>[ 0.637275] FPGA manager framework
10548 16:38:08.622450 <6>[ 0.640960] Advanced Linux Sound Architecture Driver Initialized.
10549 16:38:08.625705 <6>[ 0.647731] vgaarb: loaded
10550 16:38:08.632106 <6>[ 0.650886] clocksource: Switched to clocksource arch_sys_counter
10551 16:38:08.635310 <5>[ 0.657321] VFS: Disk quotas dquot_6.6.0
10552 16:38:08.641817 <6>[ 0.661507] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10553 16:38:08.645159 <6>[ 0.668694] pnp: PnP ACPI: disabled
10554 16:38:08.653704 <6>[ 0.675395] NET: Registered PF_INET protocol family
10555 16:38:08.663759 <6>[ 0.680987] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10556 16:38:08.674982 <6>[ 0.693330] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10557 16:38:08.684758 <6>[ 0.702145] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10558 16:38:08.691909 <6>[ 0.710116] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10559 16:38:08.701449 <6>[ 0.718817] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10560 16:38:08.708546 <6>[ 0.728575] TCP: Hash tables configured (established 65536 bind 65536)
10561 16:38:08.714967 <6>[ 0.735441] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10562 16:38:08.724751 <6>[ 0.742641] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10563 16:38:08.731504 <6>[ 0.750342] NET: Registered PF_UNIX/PF_LOCAL protocol family
10564 16:38:08.738103 <6>[ 0.756495] RPC: Registered named UNIX socket transport module.
10565 16:38:08.741476 <6>[ 0.762649] RPC: Registered udp transport module.
10566 16:38:08.747873 <6>[ 0.767581] RPC: Registered tcp transport module.
10567 16:38:08.754192 <6>[ 0.772513] RPC: Registered tcp NFSv4.1 backchannel transport module.
10568 16:38:08.757456 <6>[ 0.779178] PCI: CLS 0 bytes, default 64
10569 16:38:08.760529 <6>[ 0.783520] Unpacking initramfs...
10570 16:38:08.784783 <6>[ 0.803006] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10571 16:38:08.794385 <6>[ 0.811655] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10572 16:38:08.798140 <6>[ 0.820496] kvm [1]: IPA Size Limit: 40 bits
10573 16:38:08.804768 <6>[ 0.825023] kvm [1]: GICv3: no GICV resource entry
10574 16:38:08.808155 <6>[ 0.830044] kvm [1]: disabling GICv2 emulation
10575 16:38:08.814633 <6>[ 0.834735] kvm [1]: GIC system register CPU interface enabled
10576 16:38:08.817969 <6>[ 0.840892] kvm [1]: vgic interrupt IRQ18
10577 16:38:08.823961 <6>[ 0.845244] kvm [1]: VHE mode initialized successfully
10578 16:38:08.830881 <5>[ 0.851710] Initialise system trusted keyrings
10579 16:38:08.837164 <6>[ 0.856541] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10580 16:38:08.845272 <6>[ 0.866513] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10581 16:38:08.851746 <5>[ 0.872923] NFS: Registering the id_resolver key type
10582 16:38:08.854981 <5>[ 0.878232] Key type id_resolver registered
10583 16:38:08.861350 <5>[ 0.882649] Key type id_legacy registered
10584 16:38:08.868301 <6>[ 0.886929] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10585 16:38:08.874847 <6>[ 0.893851] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10586 16:38:08.881365 <6>[ 0.901563] 9p: Installing v9fs 9p2000 file system support
10587 16:38:08.918500 <5>[ 0.939838] Key type asymmetric registered
10588 16:38:08.921797 <5>[ 0.944168] Asymmetric key parser 'x509' registered
10589 16:38:08.932100 <6>[ 0.949318] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10590 16:38:08.935089 <6>[ 0.956938] io scheduler mq-deadline registered
10591 16:38:08.938410 <6>[ 0.961729] io scheduler kyber registered
10592 16:38:08.957416 <6>[ 0.978748] EINJ: ACPI disabled.
10593 16:38:08.990343 <4>[ 1.005137] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 16:38:08.999903 <4>[ 1.015777] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 16:38:09.015136 <6>[ 1.036803] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10596 16:38:09.023385 <6>[ 1.044725] printk: console [ttyS0] disabled
10597 16:38:09.051187 <6>[ 1.069360] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10598 16:38:09.057619 <6>[ 1.078832] printk: console [ttyS0] enabled
10599 16:38:09.061048 <6>[ 1.078832] printk: console [ttyS0] enabled
10600 16:38:09.067894 <6>[ 1.087728] printk: bootconsole [mtk8250] disabled
10601 16:38:09.070972 <6>[ 1.087728] printk: bootconsole [mtk8250] disabled
10602 16:38:09.078065 <6>[ 1.098775] SuperH (H)SCI(F) driver initialized
10603 16:38:09.081346 <6>[ 1.104032] msm_serial: driver initialized
10604 16:38:09.094931 <6>[ 1.112917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10605 16:38:09.104561 <6>[ 1.121462] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10606 16:38:09.111209 <6>[ 1.130005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10607 16:38:09.121162 <6>[ 1.138637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10608 16:38:09.131268 <6>[ 1.147349] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10609 16:38:09.137799 <6>[ 1.156063] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10610 16:38:09.147848 <6>[ 1.164608] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10611 16:38:09.154317 <6>[ 1.173402] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10612 16:38:09.164155 <6>[ 1.181942] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10613 16:38:09.176109 <6>[ 1.197501] loop: module loaded
10614 16:38:09.182308 <6>[ 1.203401] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10615 16:38:09.205059 <4>[ 1.226537] mtk-pmic-keys: Failed to locate of_node [id: -1]
10616 16:38:09.211637 <6>[ 1.233362] megasas: 07.719.03.00-rc1
10617 16:38:09.221181 <6>[ 1.242991] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10618 16:38:09.228351 <6>[ 1.250271] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10619 16:38:09.245015 <6>[ 1.266847] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10620 16:38:09.305806 <6>[ 1.320623] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10621 16:38:09.554820 <6>[ 1.576969] Freeing initrd memory: 18304K
10622 16:38:09.566980 <6>[ 1.588536] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10623 16:38:09.577676 <6>[ 1.599412] tun: Universal TUN/TAP device driver, 1.6
10624 16:38:09.580964 <6>[ 1.605465] thunder_xcv, ver 1.0
10625 16:38:09.584100 <6>[ 1.608973] thunder_bgx, ver 1.0
10626 16:38:09.587676 <6>[ 1.612467] nicpf, ver 1.0
10627 16:38:09.597919 <6>[ 1.616477] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10628 16:38:09.601057 <6>[ 1.623952] hns3: Copyright (c) 2017 Huawei Corporation.
10629 16:38:09.607807 <6>[ 1.629536] hclge is initializing
10630 16:38:09.610926 <6>[ 1.633116] e1000: Intel(R) PRO/1000 Network Driver
10631 16:38:09.618070 <6>[ 1.638245] e1000: Copyright (c) 1999-2006 Intel Corporation.
10632 16:38:09.621290 <6>[ 1.644257] e1000e: Intel(R) PRO/1000 Network Driver
10633 16:38:09.627883 <6>[ 1.649472] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10634 16:38:09.634417 <6>[ 1.655659] igb: Intel(R) Gigabit Ethernet Network Driver
10635 16:38:09.641311 <6>[ 1.661308] igb: Copyright (c) 2007-2014 Intel Corporation.
10636 16:38:09.647618 <6>[ 1.667144] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10637 16:38:09.654120 <6>[ 1.673661] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10638 16:38:09.657339 <6>[ 1.680119] sky2: driver version 1.30
10639 16:38:09.664397 <6>[ 1.685047] usbcore: registered new device driver r8152-cfgselector
10640 16:38:09.670785 <6>[ 1.691581] usbcore: registered new interface driver r8152
10641 16:38:09.677266 <6>[ 1.697399] VFIO - User Level meta-driver version: 0.3
10642 16:38:09.684051 <6>[ 1.705620] usbcore: registered new interface driver usb-storage
10643 16:38:09.690404 <6>[ 1.712067] usbcore: registered new device driver onboard-usb-hub
10644 16:38:09.699132 <6>[ 1.721199] mt6397-rtc mt6359-rtc: registered as rtc0
10645 16:38:09.709330 <6>[ 1.726667] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:38:09 UTC (1718642289)
10646 16:38:09.712608 <6>[ 1.736228] i2c_dev: i2c /dev entries driver
10647 16:38:09.726205 <4>[ 1.748189] cpu cpu0: supply cpu not found, using dummy regulator
10648 16:38:09.733327 <4>[ 1.754629] cpu cpu1: supply cpu not found, using dummy regulator
10649 16:38:09.739917 <4>[ 1.761034] cpu cpu2: supply cpu not found, using dummy regulator
10650 16:38:09.746135 <4>[ 1.767435] cpu cpu3: supply cpu not found, using dummy regulator
10651 16:38:09.752586 <4>[ 1.773833] cpu cpu4: supply cpu not found, using dummy regulator
10652 16:38:09.759595 <4>[ 1.780228] cpu cpu5: supply cpu not found, using dummy regulator
10653 16:38:09.766075 <4>[ 1.786643] cpu cpu6: supply cpu not found, using dummy regulator
10654 16:38:09.772683 <4>[ 1.793041] cpu cpu7: supply cpu not found, using dummy regulator
10655 16:38:09.791800 <6>[ 1.813679] cpu cpu0: EM: created perf domain
10656 16:38:09.794938 <6>[ 1.818623] cpu cpu4: EM: created perf domain
10657 16:38:09.802705 <6>[ 1.824215] sdhci: Secure Digital Host Controller Interface driver
10658 16:38:09.809111 <6>[ 1.830648] sdhci: Copyright(c) Pierre Ossman
10659 16:38:09.815517 <6>[ 1.835602] Synopsys Designware Multimedia Card Interface Driver
10660 16:38:09.822503 <6>[ 1.842237] sdhci-pltfm: SDHCI platform and OF driver helper
10661 16:38:09.825634 <6>[ 1.842271] mmc0: CQHCI version 5.10
10662 16:38:09.832223 <6>[ 1.852593] ledtrig-cpu: registered to indicate activity on CPUs
10663 16:38:09.839230 <6>[ 1.859688] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10664 16:38:09.845667 <6>[ 1.866744] usbcore: registered new interface driver usbhid
10665 16:38:09.849053 <6>[ 1.872575] usbhid: USB HID core driver
10666 16:38:09.855446 <6>[ 1.876766] spi_master spi0: will run message pump with realtime priority
10667 16:38:09.903827 <6>[ 1.919260] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10668 16:38:09.922825 <6>[ 1.934775] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10669 16:38:09.926458 <6>[ 1.944816] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10670 16:38:09.934827 <6>[ 1.956213] cros-ec-spi spi0.0: Chrome EC device registered
10671 16:38:09.941316 <6>[ 1.962217] mmc0: Command Queue Engine enabled
10672 16:38:09.947783 <6>[ 1.966954] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10673 16:38:09.951127 <6>[ 1.974406] mmcblk0: mmc0:0001 DA4128 116 GiB
10674 16:38:09.961979 <6>[ 1.980821] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10675 16:38:09.968966 <6>[ 1.985862] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10676 16:38:09.975488 <6>[ 1.991078] NET: Registered PF_PACKET protocol family
10677 16:38:09.978761 <6>[ 1.996982] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10678 16:38:09.985352 <6>[ 2.001431] 9pnet: Installing 9P2000 support
10679 16:38:09.989045 <6>[ 2.007228] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10680 16:38:09.995470 <5>[ 2.011136] Key type dns_resolver registered
10681 16:38:10.001803 <6>[ 2.016868] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10682 16:38:10.005402 <6>[ 2.021311] registered taskstats version 1
10683 16:38:10.008835 <5>[ 2.031743] Loading compiled-in X.509 certificates
10684 16:38:10.039570 <4>[ 2.054472] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 16:38:10.049242 <4>[ 2.065195] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10686 16:38:10.063463 <6>[ 2.085279] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10687 16:38:10.070433 <6>[ 2.092127] xhci-mtk 11200000.usb: xHCI Host Controller
10688 16:38:10.076851 <6>[ 2.097735] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10689 16:38:10.087376 <6>[ 2.105593] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10690 16:38:10.093973 <6>[ 2.115018] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10691 16:38:10.100456 <6>[ 2.121229] xhci-mtk 11200000.usb: xHCI Host Controller
10692 16:38:10.107057 <6>[ 2.126731] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10693 16:38:10.113720 <6>[ 2.134387] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10694 16:38:10.120497 <6>[ 2.142165] hub 1-0:1.0: USB hub found
10695 16:38:10.123516 <6>[ 2.146186] hub 1-0:1.0: 1 port detected
10696 16:38:10.133679 <6>[ 2.150460] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10697 16:38:10.136958 <6>[ 2.159167] hub 2-0:1.0: USB hub found
10698 16:38:10.139842 <6>[ 2.163187] hub 2-0:1.0: 1 port detected
10699 16:38:10.148377 <6>[ 2.170090] mtk-msdc 11f70000.mmc: Got CD GPIO
10700 16:38:10.163232 <6>[ 2.181663] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10701 16:38:10.172888 <6>[ 2.190031] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10702 16:38:10.180034 <6>[ 2.198370] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10703 16:38:10.189788 <6>[ 2.206713] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10704 16:38:10.196139 <6>[ 2.215051] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10705 16:38:10.205975 <6>[ 2.223389] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10706 16:38:10.212558 <6>[ 2.231728] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10707 16:38:10.222806 <6>[ 2.240066] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10708 16:38:10.229476 <6>[ 2.248404] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10709 16:38:10.239327 <6>[ 2.256742] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10710 16:38:10.245523 <6>[ 2.265080] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10711 16:38:10.255676 <6>[ 2.273424] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10712 16:38:10.262077 <6>[ 2.281762] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10713 16:38:10.272551 <6>[ 2.290099] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10714 16:38:10.279040 <6>[ 2.298437] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10715 16:38:10.285544 <6>[ 2.307154] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10716 16:38:10.292624 <6>[ 2.314297] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10717 16:38:10.299207 <6>[ 2.321104] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10718 16:38:10.309461 <6>[ 2.327868] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10719 16:38:10.316115 <6>[ 2.334789] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10720 16:38:10.322697 <6>[ 2.341678] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10721 16:38:10.332129 <6>[ 2.350816] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10722 16:38:10.342186 <6>[ 2.359940] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10723 16:38:10.352497 <6>[ 2.369234] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10724 16:38:10.362277 <6>[ 2.378702] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10725 16:38:10.371713 <6>[ 2.388169] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10726 16:38:10.378444 <6>[ 2.397289] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10727 16:38:10.388248 <6>[ 2.406755] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10728 16:38:10.398465 <6>[ 2.415873] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10729 16:38:10.408312 <6>[ 2.425172] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10730 16:38:10.418104 <6>[ 2.435332] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10731 16:38:10.428594 <6>[ 2.447117] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10732 16:38:10.436240 <6>[ 2.458062] Trying to probe devices needed for running init ...
10733 16:38:10.446706 <3>[ 2.465295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10734 16:38:10.552760 <6>[ 2.571194] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10735 16:38:10.707132 <6>[ 2.729235] hub 1-1:1.0: USB hub found
10736 16:38:10.710330 <6>[ 2.733765] hub 1-1:1.0: 4 ports detected
10737 16:38:10.722132 <6>[ 2.744202] hub 1-1:1.0: USB hub found
10738 16:38:10.725795 <6>[ 2.748502] hub 1-1:1.0: 4 ports detected
10739 16:38:10.832652 <6>[ 2.851375] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10740 16:38:10.858858 <6>[ 2.880936] hub 2-1:1.0: USB hub found
10741 16:38:10.862132 <6>[ 2.885435] hub 2-1:1.0: 3 ports detected
10742 16:38:10.873756 <6>[ 2.895822] hub 2-1:1.0: USB hub found
10743 16:38:10.876918 <6>[ 2.900212] hub 2-1:1.0: 3 ports detected
10744 16:38:11.044251 <6>[ 3.063224] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10745 16:38:11.177026 <6>[ 3.199180] hub 1-1.4:1.0: USB hub found
10746 16:38:11.180311 <6>[ 3.203806] hub 1-1.4:1.0: 2 ports detected
10747 16:38:11.192030 <6>[ 3.214062] hub 1-1.4:1.0: USB hub found
10748 16:38:11.195249 <6>[ 3.218577] hub 1-1.4:1.0: 2 ports detected
10749 16:38:11.264457 <6>[ 3.283289] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10750 16:38:11.372844 <6>[ 3.391751] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10751 16:38:11.408129 <4>[ 3.426872] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10752 16:38:11.417939 <4>[ 3.436065] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10753 16:38:11.454536 <6>[ 3.476523] r8152 2-1.3:1.0 eth0: v1.12.13
10754 16:38:11.504147 <6>[ 3.523135] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10755 16:38:11.700479 <6>[ 3.719044] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10756 16:38:13.049908 <6>[ 5.071810] r8152 2-1.3:1.0 eth0: carrier on
10757 16:38:15.944358 <5>[ 5.103015] Sending DHCP requests .., OK
10758 16:38:15.951243 <6>[ 7.971288] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10759 16:38:15.954401 <6>[ 7.979594] IP-Config: Complete:
10760 16:38:15.967527 <6>[ 7.983124] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10761 16:38:15.973998 <6>[ 7.993836] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10762 16:38:15.984012 <6>[ 8.002456] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10763 16:38:15.987324 <6>[ 8.002466] nameserver0=192.168.201.1
10764 16:38:15.990691 <6>[ 8.014636] clk: Disabling unused clocks
10765 16:38:15.994550 <6>[ 8.020170] ALSA device list:
10766 16:38:16.000955 <6>[ 8.023468] No soundcards found.
10767 16:38:16.008449 <6>[ 8.031124] Freeing unused kernel memory: 8512K
10768 16:38:16.012186 <6>[ 8.036030] Run /init as init process
10769 16:38:16.020901 Loading, please wait...
10770 16:38:16.049551 Starting systemd-udevd version 252.22-1~deb12u1
10771 16:38:16.298603 <6>[ 8.317703] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10772 16:38:16.312788 <6>[ 8.332070] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10773 16:38:16.319125 <6>[ 8.335696] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10774 16:38:16.329551 <6>[ 8.342020] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10775 16:38:16.336024 <6>[ 8.347714] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10776 16:38:16.345576 <4>[ 8.348029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10777 16:38:16.355586 <6>[ 8.358319] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10778 16:38:16.362491 <6>[ 8.364946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10779 16:38:16.368940 <6>[ 8.367923] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10780 16:38:16.375470 <6>[ 8.374145] remoteproc remoteproc0: scp is available
10781 16:38:16.381841 <3>[ 8.375646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 16:38:16.391715 <3>[ 8.375918] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 16:38:16.398575 <3>[ 8.375924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 16:38:16.408298 <3>[ 8.375977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 16:38:16.414870 <3>[ 8.375980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 16:38:16.425273 <3>[ 8.375983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 16:38:16.431903 <3>[ 8.375987] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 16:38:16.439016 <3>[ 8.375992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 16:38:16.448864 <3>[ 8.376013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 16:38:16.455150 <3>[ 8.376036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 16:38:16.465184 <3>[ 8.376039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 16:38:16.471863 <3>[ 8.376042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 16:38:16.481753 <3>[ 8.376063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 16:38:16.488866 <3>[ 8.376066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 16:38:16.495235 <3>[ 8.376068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 16:38:16.505496 <3>[ 8.376071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 16:38:16.512143 <3>[ 8.376073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 16:38:16.521928 <3>[ 8.376092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 16:38:16.528332 <6>[ 8.382013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10800 16:38:16.538221 <6>[ 8.395234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10801 16:38:16.541467 <6>[ 8.395368] mc: Linux media interface: v0.10
10802 16:38:16.547967 <6>[ 8.397569] remoteproc remoteproc0: powering up scp
10803 16:38:16.555061 <6>[ 8.400978] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10804 16:38:16.561550 <6>[ 8.402764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10805 16:38:16.571640 <6>[ 8.410827] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10806 16:38:16.574652 <6>[ 8.410854] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10807 16:38:16.584550 <4>[ 8.425461] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10808 16:38:16.590929 <4>[ 8.425461] Fallback method does not support PEC.
10809 16:38:16.598009 <6>[ 8.427233] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10810 16:38:16.604449 <4>[ 8.428692] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10811 16:38:16.610974 <4>[ 8.436470] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10812 16:38:16.620722 <6>[ 8.443246] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10813 16:38:16.627613 <6>[ 8.452564] videodev: Linux video capture interface: v2.00
10814 16:38:16.637449 <3>[ 8.464901] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 16:38:16.647432 <6>[ 8.487312] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10816 16:38:16.653823 <6>[ 8.492342] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10817 16:38:16.660798 <6>[ 8.500462] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10818 16:38:16.667376 <6>[ 8.508287] pci_bus 0000:00: root bus resource [bus 00-ff]
10819 16:38:16.677156 <3>[ 8.516114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10820 16:38:16.683299 <6>[ 8.536638] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10821 16:38:16.693289 <6>[ 8.536683] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10822 16:38:16.696877 <6>[ 8.536690] remoteproc remoteproc0: remote processor scp is now up
10823 16:38:16.706387 <6>[ 8.540678] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10824 16:38:16.712971 <6>[ 8.571909] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10825 16:38:16.722963 <6>[ 8.574426] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10826 16:38:16.732812 <6>[ 8.605618] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10827 16:38:16.739670 <6>[ 8.617389] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10828 16:38:16.743088 <6>[ 8.633084] Bluetooth: Core ver 2.22
10829 16:38:16.749346 <6>[ 8.639812] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10830 16:38:16.755922 <6>[ 8.648979] NET: Registered PF_BLUETOOTH protocol family
10831 16:38:16.762979 <6>[ 8.649016] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10832 16:38:16.772719 <6>[ 8.650054] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10833 16:38:16.782534 <6>[ 8.652726] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10834 16:38:16.789318 <6>[ 8.653045] usbcore: registered new interface driver uvcvideo
10835 16:38:16.795501 <6>[ 8.654719] pci 0000:00:00.0: supports D1 D2
10836 16:38:16.802517 <6>[ 8.663429] Bluetooth: HCI device and connection manager initialized
10837 16:38:16.805579 <6>[ 8.663449] Bluetooth: HCI socket layer initialized
10838 16:38:16.812261 <6>[ 8.673513] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10839 16:38:16.819099 <6>[ 8.680375] Bluetooth: L2CAP socket layer initialized
10840 16:38:16.825376 <6>[ 8.690480] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10841 16:38:16.832015 <6>[ 8.695148] Bluetooth: SCO socket layer initialized
10842 16:38:16.838723 <6>[ 8.696358] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10843 16:38:16.845034 <6>[ 8.704065] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10844 16:38:16.848746 <6>[ 8.742834] usbcore: registered new interface driver btusb
10845 16:38:16.861554 <4>[ 8.743986] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10846 16:38:16.865346 <3>[ 8.743993] Bluetooth: hci0: Failed to load firmware file (-2)
10847 16:38:16.871896 <3>[ 8.743995] Bluetooth: hci0: Failed to set up firmware (-2)
10848 16:38:16.881700 <4>[ 8.743998] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10849 16:38:16.891471 <6>[ 8.752291] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10850 16:38:16.897830 <6>[ 8.917932] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10851 16:38:16.904737 <6>[ 8.925420] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10852 16:38:16.911047 <6>[ 8.932996] pci 0000:01:00.0: supports D1 D2
10853 16:38:16.918054 <6>[ 8.937515] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10854 16:38:16.935609 <6>[ 8.955126] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10855 16:38:16.942341 <6>[ 8.962038] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10856 16:38:16.949299 <6>[ 8.970120] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10857 16:38:16.958742 <6>[ 8.978119] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10858 16:38:16.965495 <6>[ 8.986122] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10859 16:38:16.975714 <6>[ 8.994123] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10860 16:38:16.978962 <6>[ 9.002124] pci 0000:00:00.0: PCI bridge to [bus 01]
10861 16:38:16.988772 <6>[ 9.007341] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10862 16:38:16.995314 <6>[ 9.015468] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10863 16:38:17.001672 <6>[ 9.022296] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10864 16:38:17.008334 <6>[ 9.029035] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10865 16:38:17.023827 <5>[ 9.042947] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10866 16:38:17.055228 <5>[ 9.074255] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10867 16:38:17.061488 <5>[ 9.081676] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10868 16:38:17.071386 <4>[ 9.090114] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10869 16:38:17.077848 <6>[ 9.099021] cfg80211: failed to load regulatory.db
10870 16:38:17.126212 <6>[ 9.145313] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10871 16:38:17.132579 <6>[ 9.152839] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10872 16:38:17.157089 <6>[ 9.179529] mt7921e 0000:01:00.0: ASIC revision: 79610010
10873 16:38:17.260320 <6>[ 9.279564] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10874 16:38:17.263377 <6>[ 9.279564]
10875 16:38:17.277589 Begin: Loading essential drivers ... done.
10876 16:38:17.280707 Begin: Running /scripts/init-premount ... done.
10877 16:38:17.287747 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10878 16:38:17.297178 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10879 16:38:17.300338 Device /sys/class/net/eth0 found
10880 16:38:17.300416 done.
10881 16:38:17.306922 Begin: Waiting up to 180 secs for any network device to become available ... done.
10882 16:38:17.364854 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10883 16:38:17.371350 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10884 16:38:17.377698 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10885 16:38:17.384499 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10886 16:38:17.390920 host : mt8192-asurada-spherion-r0-cbg-9
10887 16:38:17.397668 domain : lava-rack
10888 16:38:17.400789 rootserver: 192.168.201.1 rootpath:
10889 16:38:17.404011 filename :
10890 16:38:17.516073 done.
10891 16:38:17.526012 <6>[ 9.545635] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10892 16:38:17.532853 Begin: Running /scripts/nfs-bottom ... done.
10893 16:38:17.551843 Begin: Running /scripts/init-bottom ... done.
10894 16:38:18.907323 <6>[ 10.930078] NET: Registered PF_INET6 protocol family
10895 16:38:18.914440 <6>[ 10.937588] Segment Routing with IPv6
10896 16:38:18.917666 <6>[ 10.941562] In-situ OAM (IOAM) with IPv6
10897 16:38:19.094677 <30>[ 11.091203] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10898 16:38:19.101717 <30>[ 11.124366] systemd[1]: Detected architecture arm64.
10899 16:38:19.110680
10900 16:38:19.113981 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10901 16:38:19.114073
10902 16:38:19.138063 <30>[ 11.160810] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10903 16:38:20.227633 <30>[ 12.247346] systemd[1]: Queued start job for default target graphical.target.
10904 16:38:20.268589 <30>[ 12.287906] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10905 16:38:20.274421 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10906 16:38:20.297194 <30>[ 12.316778] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10907 16:38:20.306970 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10908 16:38:20.325206 <30>[ 12.344709] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10909 16:38:20.334755 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10910 16:38:20.352474 <30>[ 12.372381] systemd[1]: Created slice user.slice - User and Session Slice.
10911 16:38:20.359605 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10912 16:38:20.379090 <30>[ 12.395529] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10913 16:38:20.388831 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10914 16:38:20.407054 <30>[ 12.423412] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10915 16:38:20.413298 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10916 16:38:20.442173 <30>[ 12.451744] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10917 16:38:20.452325 <30>[ 12.471647] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10918 16:38:20.458930 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10919 16:38:20.476340 <30>[ 12.495593] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10920 16:38:20.486018 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10921 16:38:20.503895 <30>[ 12.523700] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10922 16:38:20.513915 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10923 16:38:20.528692 <30>[ 12.551728] systemd[1]: Reached target paths.target - Path Units.
10924 16:38:20.535784 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10925 16:38:20.556037 <30>[ 12.575654] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10926 16:38:20.562615 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10927 16:38:20.575748 <30>[ 12.599171] systemd[1]: Reached target slices.target - Slice Units.
10928 16:38:20.586133 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10929 16:38:20.600339 <30>[ 12.623711] systemd[1]: Reached target swap.target - Swaps.
10930 16:38:20.607370 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10931 16:38:20.628076 <30>[ 12.647661] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10932 16:38:20.637546 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10933 16:38:20.656049 <30>[ 12.675655] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10934 16:38:20.665852 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10935 16:38:20.686768 <30>[ 12.706618] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10936 16:38:20.696460 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10937 16:38:20.712913 <30>[ 12.732608] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10938 16:38:20.722561 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10939 16:38:20.739761 <30>[ 12.759810] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10940 16:38:20.746532 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10941 16:38:20.764827 <30>[ 12.784669] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10942 16:38:20.774857 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10943 16:38:20.794052 <30>[ 12.814198] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10944 16:38:20.804353 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10945 16:38:20.819948 <30>[ 12.839663] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10946 16:38:20.829779 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10947 16:38:20.871617 <30>[ 12.891234] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10948 16:38:20.878095 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10949 16:38:20.899898 <30>[ 12.919903] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10950 16:38:20.906976 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10951 16:38:20.955490 <30>[ 12.975437] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10952 16:38:20.962010 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10953 16:38:20.990646 <30>[ 13.003839] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10954 16:38:21.005810 <30>[ 13.025841] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10955 16:38:21.016141 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10956 16:38:21.064011 <30>[ 13.083992] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10957 16:38:21.070555 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10958 16:38:21.097456 <30>[ 13.117090] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10959 16:38:21.104036 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10960 16:38:21.131898 <30>[ 13.151441] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10961 16:38:21.144733 Starting [0;1;39mmodprobe@drm.service<6>[ 13.162841] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10962 16:38:21.147950 [0m - Load Kernel Module drm...
10963 16:38:21.173240 <30>[ 13.192906] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10964 16:38:21.182958 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10965 16:38:21.224171 <30>[ 13.244019] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10966 16:38:21.230828 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10967 16:38:21.257281 <30>[ 13.277038] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10968 16:38:21.263792 Starting [0;1;39mmodpr<6>[ 13.287827] fuse: init (API version 7.37)
10969 16:38:21.270360 obe@loop.ser…e[0m - Load Kernel Module loop...
10970 16:38:21.297112 <30>[ 13.317036] systemd[1]: Starting systemd-journald.service - Journal Service...
10971 16:38:21.303680 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10972 16:38:21.356672 <30>[ 13.376360] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10973 16:38:21.363429 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10974 16:38:21.390562 <30>[ 13.406950] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10975 16:38:21.396915 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10976 16:38:21.421681 <30>[ 13.441250] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10977 16:38:21.431795 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10978 16:38:21.441762 <3>[ 13.461358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 16:38:21.472761 <3>[ 13.492359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 16:38:21.482608 <30>[ 13.495793] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10981 16:38:21.489129 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10982 16:38:21.513606 <30>[ 13.533380] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10983 16:38:21.520527 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10984 16:38:21.531048 <3>[ 13.549359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 16:38:21.544301 <30>[ 13.564097] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10986 16:38:21.554231 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10987 16:38:21.568999 <3>[ 13.588986] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 16:38:21.579197 <30>[ 13.598758] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10989 16:38:21.585605 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10990 16:38:21.600679 <3>[ 13.620674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 16:38:21.611069 <30>[ 13.631199] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10992 16:38:21.621616 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10993 16:38:21.631474 <3>[ 13.650841] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 16:38:21.641710 <30>[ 13.661672] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10995 16:38:21.651427 <30>[ 13.670004] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10996 16:38:21.665453 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 13.684641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 16:38:21.668701 le configfs.
10998 16:38:21.685115 <30>[ 13.704660] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10999 16:38:21.691692 <30>[ 13.712431] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11000 16:38:21.702053 <3>[ 13.716441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 16:38:21.708460 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11002 16:38:21.729265 <30>[ 13.748949] systemd[1]: modprobe@drm.service: Deactivated successfully.
11003 16:38:21.735733 <3>[ 13.749949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 16:38:21.745842 <30>[ 13.756816] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11005 16:38:21.752409 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11006 16:38:21.766141 <3>[ 13.785857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 16:38:21.777261 <30>[ 13.797146] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11008 16:38:21.788238 <30>[ 13.805688] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11009 16:38:21.798425 [[0;32m OK [<3>[ 13.815493] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 16:38:21.805016 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11011 16:38:21.821640 <30>[ 13.840833] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11012 16:38:21.828133 <30>[ 13.848773] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11013 16:38:21.837900 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11014 16:38:21.856511 <30>[ 13.876301] systemd[1]: Started systemd-journald.service - Journal Service.
11015 16:38:21.862982 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11016 16:38:21.889215 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11017 16:38:21.909441 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11018 16:38:21.946754 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel c<4>[ 13.959166] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11019 16:38:21.956179 <3>[ 13.975491] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11020 16:38:21.956275 ommand line.
11021 16:38:21.982298 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11022 16:38:22.001515 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11023 16:38:22.025905 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11024 16:38:22.079857 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11025 16:38:22.108248 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11026 16:38:22.132398 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11027 16:38:22.155462 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11028 16:38:22.180160 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11029 16:38:22.208603 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11030 16:38:22.215636 <46>[ 14.235945] systemd-journald[313]: Received client request to flush runtime journal.
11031 16:38:22.249725 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11032 16:38:22.268854 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11033 16:38:22.288836 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11034 16:38:22.309391 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11035 16:38:23.010220 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11036 16:38:23.072555 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11037 16:38:23.671008 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11038 16:38:23.727288 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11039 16:38:23.743532 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11040 16:38:23.759187 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11041 16:38:23.812437 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11042 16:38:23.839271 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11043 16:38:24.084658 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11044 16:38:24.146330 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11045 16:38:24.215983 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11046 16:38:24.516578 <6>[ 16.539800] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11047 16:38:24.526173 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11048 16:38:24.576652 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11049 16:38:24.598443 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11050 16:38:24.693511 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11051 16:38:24.711633 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11052 16:38:24.767667 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11053 16:38:24.793453 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11054 16:38:24.813972 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11055 16:38:24.833776 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11056 16:38:24.864431 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11057 16:38:24.924031 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11058 16:38:24.969237 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11059 16:38:24.987680 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11060 16:38:25.077979 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11061 16:38:25.096032 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11062 16:38:25.115053 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11063 16:38:25.130999 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11064 16:38:25.154744 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11065 16:38:25.174492 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11066 16:38:25.191364 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11067 16:38:25.210718 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11068 16:38:25.230126 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11069 16:38:25.246339 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11070 16:38:25.263933 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11071 16:38:25.281120 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11072 16:38:25.297397 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11073 16:38:25.351802 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11074 16:38:25.385187 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11075 16:38:25.497027 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11076 16:38:25.523893 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11077 16:38:25.658549 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11078 16:38:25.699622 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11079 16:38:25.724774 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11080 16:38:25.770204 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11081 16:38:25.791348 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11082 16:38:25.824962 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11083 16:38:25.847067 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11084 16:38:25.864808 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11085 16:38:25.883650 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11086 16:38:25.931001 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11087 16:38:25.978712 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11088 16:38:26.065823
11089 16:38:26.068919 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11090 16:38:26.069017
11091 16:38:26.072244 debian-bookworm-arm64 login: root (automatic login)
11092 16:38:26.072323
11093 16:38:26.384197 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11094 16:38:26.384332
11095 16:38:26.390690 The programs included with the Debian GNU/Linux system are free software;
11096 16:38:26.396969 the exact distribution terms for each program are described in the
11097 16:38:26.400218 individual files in /usr/share/doc/*/copyright.
11098 16:38:26.400325
11099 16:38:26.406792 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11100 16:38:26.410340 permitted by applicable law.
11101 16:38:27.462293 Matched prompt #10: / #
11103 16:38:27.462569 Setting prompt string to ['/ #']
11104 16:38:27.462693 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11106 16:38:27.462886 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11107 16:38:27.462973 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11108 16:38:27.463041 Setting prompt string to ['/ #']
11109 16:38:27.463099 Forcing a shell prompt, looking for ['/ #']
11111 16:38:27.513311 / #
11112 16:38:27.513446 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11113 16:38:27.513519 Waiting using forced prompt support (timeout 00:02:30)
11114 16:38:27.518462
11115 16:38:27.518736 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11116 16:38:27.518832 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11118 16:38:27.619172 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr'
11119 16:38:27.624837 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396177/extract-nfsrootfs-704_ncfr'
11121 16:38:27.725459 / # export NFS_SERVER_IP='192.168.201.1'
11122 16:38:27.730317 export NFS_SERVER_IP='192.168.201.1'
11123 16:38:27.730600 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11124 16:38:27.730734 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11125 16:38:27.730826 end: 2 depthcharge-action (duration 00:01:38) [common]
11126 16:38:27.730913 start: 3 lava-test-retry (timeout 00:07:41) [common]
11127 16:38:27.731000 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11128 16:38:27.731076 Using namespace: common
11130 16:38:27.831394 / # #
11131 16:38:27.831589 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11132 16:38:27.836245 #
11133 16:38:27.836554 Using /lava-14396177
11135 16:38:27.936913 / # export SHELL=/bin/bash
11136 16:38:27.941803 export SHELL=/bin/bash
11138 16:38:28.042279 / # . /lava-14396177/environment
11139 16:38:28.047294 . /lava-14396177/environment
11141 16:38:28.153540 / # /lava-14396177/bin/lava-test-runner /lava-14396177/0
11142 16:38:28.153709 Test shell timeout: 10s (minimum of the action and connection timeout)
11143 16:38:28.158708 /lava-14396177/bin/lava-test-runner /lava-14396177/0
11144 16:38:28.434754 + export TESTRUN_ID=0_timesync-off
11145 16:38:28.437873 + TESTRUN_ID=0_timesync-off
11146 16:38:28.441040 + cd /lava-14396177/0/tests/0_timesync-off
11147 16:38:28.444324 ++ cat uuid
11148 16:38:28.450783 + UUID=14396177_1.6.2.3.1
11149 16:38:28.450866 + set +x
11150 16:38:28.456952 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14396177_1.6.2.3.1>
11151 16:38:28.457216 Received signal: <STARTRUN> 0_timesync-off 14396177_1.6.2.3.1
11152 16:38:28.457289 Starting test lava.0_timesync-off (14396177_1.6.2.3.1)
11153 16:38:28.457414 Skipping test definition patterns.
11154 16:38:28.460211 + systemctl stop systemd-timesyncd
11155 16:38:28.536965 + set +x
11156 16:38:28.540274 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14396177_1.6.2.3.1>
11157 16:38:28.540538 Received signal: <ENDRUN> 0_timesync-off 14396177_1.6.2.3.1
11158 16:38:28.540644 Ending use of test pattern.
11159 16:38:28.540720 Ending test lava.0_timesync-off (14396177_1.6.2.3.1), duration 0.08
11161 16:38:28.620584 + export TESTRUN_ID=1_kselftest-dt
11162 16:38:28.623731 + TESTRUN_ID=1_kselftest-dt
11163 16:38:28.626974 + cd /lava-14396177/0/tests/1_kselftest-dt
11164 16:38:28.630140 ++ cat uuid
11165 16:38:28.635543 + UUID=14396177_1.6.2.3.5
11166 16:38:28.635637 + set +x
11167 16:38:28.642040 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14396177_1.6.2.3.5>
11168 16:38:28.642296 Received signal: <STARTRUN> 1_kselftest-dt 14396177_1.6.2.3.5
11169 16:38:28.642367 Starting test lava.1_kselftest-dt (14396177_1.6.2.3.5)
11170 16:38:28.642450 Skipping test definition patterns.
11171 16:38:28.645917 + cd ./automated/linux/kselftest/
11172 16:38:28.672162 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11173 16:38:28.717674 INFO: install_deps skipped
11174 16:38:29.236354 --2024-06-17 16:38:29-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11175 16:38:29.242709 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11176 16:38:29.367403 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11177 16:38:29.498820 HTTP request sent, awaiting response... 200 OK
11178 16:38:29.502342 Length: 1650228 (1.6M) [application/octet-stream]
11179 16:38:29.505464 Saving to: 'kselftest_armhf.tar.gz'
11180 16:38:29.505544
11181 16:38:29.505606
11182 16:38:29.762781 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11183 16:38:30.025619 kselftest_armhf.tar 2%[ ] 47.81K 179KB/s
11184 16:38:30.315356 kselftest_armhf.tar 13%[=> ] 217.50K 407KB/s
11185 16:38:30.450250 kselftest_armhf.tar 37%[======> ] 597.88K 723KB/s
11186 16:38:30.456644 kselftest_armhf.tar 100%[===================>] 1.57M 1.63MB/s in 1.0s
11187 16:38:30.456744
11188 16:38:30.601754 2024-06-17 16:38:30 (1.63 MB/s) - 'kselftest_armhf.tar.gz' saved [1650228/1650228]
11189 16:38:30.601892
11190 16:38:35.473052 skiplist:
11191 16:38:35.476172 ========================================
11192 16:38:35.479441 ========================================
11193 16:38:35.553267 ============== Tests to run ===============
11194 16:38:35.559834 ===========End Tests to run ===============
11195 16:38:35.565756 shardfile-dt fail
11196 16:38:35.589431 ./kselftest.sh: 131: cannot open /lava-14396177/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11197 16:38:35.592688 + ../../utils/send-to-lava.sh ./output/result.txt
11198 16:38:35.670910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11199 16:38:35.671041 + set +x
11200 16:38:35.671285 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11202 16:38:35.677407 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14396177_1.6.2.3.5>
11203 16:38:35.677664 Received signal: <ENDRUN> 1_kselftest-dt 14396177_1.6.2.3.5
11204 16:38:35.677736 Ending use of test pattern.
11205 16:38:35.677797 Ending test lava.1_kselftest-dt (14396177_1.6.2.3.5), duration 7.04
11207 16:38:35.678011 ok: lava_test_shell seems to have completed
11208 16:38:35.678099 shardfile-dt: fail
11209 16:38:35.678224 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11210 16:38:35.678318 end: 3 lava-test-retry (duration 00:00:08) [common]
11211 16:38:35.678404 start: 4 finalize (timeout 00:07:33) [common]
11212 16:38:35.678491 start: 4.1 power-off (timeout 00:00:30) [common]
11213 16:38:35.678636 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11214 16:38:35.881896 >> Command sent successfully.
11215 16:38:35.884221 Returned 0 in 0 seconds
11216 16:38:35.984608 end: 4.1 power-off (duration 00:00:00) [common]
11218 16:38:35.984969 start: 4.2 read-feedback (timeout 00:07:33) [common]
11220 16:38:35.985539 Listened to connection for namespace 'common' for up to 1s
11221 16:38:36.986238 Finalising connection for namespace 'common'
11222 16:38:36.986435 Disconnecting from shell: Finalise
11223 16:38:36.986534 / #
11224 16:38:37.086881 end: 4.2 read-feedback (duration 00:00:01) [common]
11225 16:38:37.087068 end: 4 finalize (duration 00:00:01) [common]
11226 16:38:37.087241 Cleaning after the job
11227 16:38:37.087430 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/ramdisk
11228 16:38:37.090042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/kernel
11229 16:38:37.101059 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/dtb
11230 16:38:37.101274 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/nfsrootfs
11231 16:38:37.163875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396177/tftp-deploy-2f5rhium/modules
11232 16:38:37.169338 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396177
11233 16:38:37.835974 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396177
11234 16:38:37.836153 Job finished correctly