Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 16:32:03.065312 lava-dispatcher, installed at version: 2024.03
2 16:32:03.065577 start: 0 validate
3 16:32:03.065703 Start time: 2024-06-17 16:32:03.065696+00:00 (UTC)
4 16:32:03.065857 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:32:03.066043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:32:03.349580 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:32:03.349800 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:32:03.612577 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:32:03.612820 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:32:03.875379 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:32:03.875577 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:32:04.138970 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:32:04.139145 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:32:04.402771 validate duration: 1.34
16 16:32:04.403057 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:32:04.403166 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:32:04.403286 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:32:04.403457 Not decompressing ramdisk as can be used compressed.
20 16:32:04.403556 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:32:04.403632 saving as /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/ramdisk/initrd.cpio.gz
22 16:32:04.403697 total size: 5628169 (5 MB)
23 16:32:04.404650 progress 0 % (0 MB)
24 16:32:04.406384 progress 5 % (0 MB)
25 16:32:04.408033 progress 10 % (0 MB)
26 16:32:04.409567 progress 15 % (0 MB)
27 16:32:04.411202 progress 20 % (1 MB)
28 16:32:04.412711 progress 25 % (1 MB)
29 16:32:04.414370 progress 30 % (1 MB)
30 16:32:04.415996 progress 35 % (1 MB)
31 16:32:04.417412 progress 40 % (2 MB)
32 16:32:04.418989 progress 45 % (2 MB)
33 16:32:04.420465 progress 50 % (2 MB)
34 16:32:04.422058 progress 55 % (2 MB)
35 16:32:04.423716 progress 60 % (3 MB)
36 16:32:04.425211 progress 65 % (3 MB)
37 16:32:04.426913 progress 70 % (3 MB)
38 16:32:04.428375 progress 75 % (4 MB)
39 16:32:04.430064 progress 80 % (4 MB)
40 16:32:04.431528 progress 85 % (4 MB)
41 16:32:04.433194 progress 90 % (4 MB)
42 16:32:04.434856 progress 95 % (5 MB)
43 16:32:04.436328 progress 100 % (5 MB)
44 16:32:04.436550 5 MB downloaded in 0.03 s (163.42 MB/s)
45 16:32:04.436706 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:32:04.436939 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:32:04.437021 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:32:04.437103 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:32:04.437272 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:32:04.437370 saving as /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/kernel/Image
52 16:32:04.437461 total size: 54813184 (52 MB)
53 16:32:04.437559 No compression specified
54 16:32:04.439041 progress 0 % (0 MB)
55 16:32:04.453654 progress 5 % (2 MB)
56 16:32:04.468409 progress 10 % (5 MB)
57 16:32:04.482782 progress 15 % (7 MB)
58 16:32:04.497213 progress 20 % (10 MB)
59 16:32:04.512189 progress 25 % (13 MB)
60 16:32:04.526782 progress 30 % (15 MB)
61 16:32:04.541396 progress 35 % (18 MB)
62 16:32:04.555771 progress 40 % (20 MB)
63 16:32:04.570473 progress 45 % (23 MB)
64 16:32:04.585394 progress 50 % (26 MB)
65 16:32:04.600075 progress 55 % (28 MB)
66 16:32:04.614391 progress 60 % (31 MB)
67 16:32:04.629090 progress 65 % (34 MB)
68 16:32:04.643537 progress 70 % (36 MB)
69 16:32:04.657894 progress 75 % (39 MB)
70 16:32:04.672792 progress 80 % (41 MB)
71 16:32:04.687387 progress 85 % (44 MB)
72 16:32:04.701684 progress 90 % (47 MB)
73 16:32:04.715990 progress 95 % (49 MB)
74 16:32:04.730197 progress 100 % (52 MB)
75 16:32:04.730452 52 MB downloaded in 0.29 s (178.41 MB/s)
76 16:32:04.730609 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:32:04.730825 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:32:04.730911 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:32:04.730989 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:32:04.731122 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:32:04.731189 saving as /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/dtb/mt8192-asurada-spherion-r0.dtb
83 16:32:04.731243 total size: 47258 (0 MB)
84 16:32:04.731304 No compression specified
85 16:32:04.732424 progress 69 % (0 MB)
86 16:32:04.732698 progress 100 % (0 MB)
87 16:32:04.732852 0 MB downloaded in 0.00 s (28.06 MB/s)
88 16:32:04.732965 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:32:04.733173 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:32:04.733256 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:32:04.733332 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:32:04.733441 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:32:04.733502 saving as /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/nfsrootfs/full.rootfs.tar
95 16:32:04.733573 total size: 120894716 (115 MB)
96 16:32:04.733656 Using unxz to decompress xz
97 16:32:04.734809 progress 0 % (0 MB)
98 16:32:05.088758 progress 5 % (5 MB)
99 16:32:05.446904 progress 10 % (11 MB)
100 16:32:05.807553 progress 15 % (17 MB)
101 16:32:06.156067 progress 20 % (23 MB)
102 16:32:06.476689 progress 25 % (28 MB)
103 16:32:06.860384 progress 30 % (34 MB)
104 16:32:07.220782 progress 35 % (40 MB)
105 16:32:07.395523 progress 40 % (46 MB)
106 16:32:07.581946 progress 45 % (51 MB)
107 16:32:07.905460 progress 50 % (57 MB)
108 16:32:08.290948 progress 55 % (63 MB)
109 16:32:08.643923 progress 60 % (69 MB)
110 16:32:08.999461 progress 65 % (74 MB)
111 16:32:09.348067 progress 70 % (80 MB)
112 16:32:09.711757 progress 75 % (86 MB)
113 16:32:10.050173 progress 80 % (92 MB)
114 16:32:10.401905 progress 85 % (98 MB)
115 16:32:10.742202 progress 90 % (103 MB)
116 16:32:11.064717 progress 95 % (109 MB)
117 16:32:11.437213 progress 100 % (115 MB)
118 16:32:11.442850 115 MB downloaded in 6.71 s (17.18 MB/s)
119 16:32:11.443018 end: 1.4.1 http-download (duration 00:00:07) [common]
121 16:32:11.443249 end: 1.4 download-retry (duration 00:00:07) [common]
122 16:32:11.443341 start: 1.5 download-retry (timeout 00:09:53) [common]
123 16:32:11.443419 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 16:32:11.443556 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:32:11.443624 saving as /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/modules/modules.tar
126 16:32:11.443681 total size: 8628772 (8 MB)
127 16:32:11.443738 Using unxz to decompress xz
128 16:32:11.444968 progress 0 % (0 MB)
129 16:32:11.466130 progress 5 % (0 MB)
130 16:32:11.490435 progress 10 % (0 MB)
131 16:32:11.514388 progress 15 % (1 MB)
132 16:32:11.538703 progress 20 % (1 MB)
133 16:32:11.563642 progress 25 % (2 MB)
134 16:32:11.587673 progress 30 % (2 MB)
135 16:32:11.614203 progress 35 % (2 MB)
136 16:32:11.638862 progress 40 % (3 MB)
137 16:32:11.664311 progress 45 % (3 MB)
138 16:32:11.690574 progress 50 % (4 MB)
139 16:32:11.717104 progress 55 % (4 MB)
140 16:32:11.743467 progress 60 % (4 MB)
141 16:32:11.773179 progress 65 % (5 MB)
142 16:32:11.800138 progress 70 % (5 MB)
143 16:32:11.824817 progress 75 % (6 MB)
144 16:32:11.848748 progress 80 % (6 MB)
145 16:32:11.876276 progress 85 % (7 MB)
146 16:32:11.905950 progress 90 % (7 MB)
147 16:32:11.933245 progress 95 % (7 MB)
148 16:32:11.959381 progress 100 % (8 MB)
149 16:32:11.964856 8 MB downloaded in 0.52 s (15.79 MB/s)
150 16:32:11.965023 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:32:11.965241 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:32:11.965322 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 16:32:11.965402 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 16:32:15.660626 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h
156 16:32:15.660786 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 16:32:15.660875 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 16:32:15.661040 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b
159 16:32:15.661160 makedir: /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin
160 16:32:15.661253 makedir: /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/tests
161 16:32:15.661343 makedir: /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/results
162 16:32:15.661426 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-add-keys
163 16:32:15.661687 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-add-sources
164 16:32:15.661813 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-background-process-start
165 16:32:15.661934 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-background-process-stop
166 16:32:15.662060 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-common-functions
167 16:32:15.662178 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-echo-ipv4
168 16:32:15.662294 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-install-packages
169 16:32:15.662410 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-installed-packages
170 16:32:15.662530 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-os-build
171 16:32:15.662643 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-probe-channel
172 16:32:15.662758 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-probe-ip
173 16:32:15.662872 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-target-ip
174 16:32:15.662985 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-target-mac
175 16:32:15.663098 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-target-storage
176 16:32:15.663214 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-case
177 16:32:15.663328 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-event
178 16:32:15.663440 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-feedback
179 16:32:15.663552 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-raise
180 16:32:15.663663 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-reference
181 16:32:15.663775 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-runner
182 16:32:15.663887 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-set
183 16:32:15.663999 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-test-shell
184 16:32:15.664115 Updating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-add-keys (debian)
185 16:32:15.664254 Updating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-add-sources (debian)
186 16:32:15.664380 Updating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-install-packages (debian)
187 16:32:15.664506 Updating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-installed-packages (debian)
188 16:32:15.664631 Updating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/bin/lava-os-build (debian)
189 16:32:15.664740 Creating /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/environment
190 16:32:15.664826 LAVA metadata
191 16:32:15.664892 - LAVA_JOB_ID=14396140
192 16:32:15.664947 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:32:15.665040 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 16:32:15.665111 skipped lava-vland-overlay
195 16:32:15.665181 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:32:15.665253 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 16:32:15.665307 skipped lava-multinode-overlay
198 16:32:15.665371 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:32:15.665442 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 16:32:15.665503 Loading test definitions
201 16:32:15.665584 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 16:32:15.665643 Using /lava-14396140 at stage 0
203 16:32:15.665914 uuid=14396140_1.6.2.3.1 testdef=None
204 16:32:15.665994 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:32:15.666069 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 16:32:15.666467 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:32:15.666666 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 16:32:15.667182 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:32:15.667397 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 16:32:15.667894 runner path: /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/0/tests/0_timesync-off test_uuid 14396140_1.6.2.3.1
213 16:32:15.668039 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:32:15.668243 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 16:32:15.668311 Using /lava-14396140 at stage 0
217 16:32:15.668398 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:32:15.668472 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/0/tests/1_kselftest-rtc'
219 16:32:17.702651 Running '/usr/bin/git checkout kernelci.org
220 16:32:17.864560 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 16:32:17.864905 uuid=14396140_1.6.2.3.5 testdef=None
222 16:32:17.865007 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 16:32:17.865199 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 16:32:17.865892 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:32:17.866109 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 16:32:17.867025 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:32:17.867274 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 16:32:17.868179 runner path: /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/0/tests/1_kselftest-rtc test_uuid 14396140_1.6.2.3.5
232 16:32:17.868284 BOARD='mt8192-asurada-spherion-r0'
233 16:32:17.868367 BRANCH='cip-gitlab'
234 16:32:17.868445 SKIPFILE='/dev/null'
235 16:32:17.868527 SKIP_INSTALL='True'
236 16:32:17.868581 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:32:17.868632 TST_CASENAME=''
238 16:32:17.868682 TST_CMDFILES='rtc'
239 16:32:17.868812 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:32:17.868991 Creating lava-test-runner.conf files
242 16:32:17.869045 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396140/lava-overlay-ui8zq43b/lava-14396140/0 for stage 0
243 16:32:17.869126 - 0_timesync-off
244 16:32:17.869184 - 1_kselftest-rtc
245 16:32:17.869269 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 16:32:17.869343 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 16:32:25.169305 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 16:32:25.169475 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 16:32:25.169604 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:32:25.169705 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 16:32:25.169827 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 16:32:25.346877 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:32:25.347042 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 16:32:25.347161 extracting modules file /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h
255 16:32:25.625260 extracting modules file /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396140/extract-overlay-ramdisk-7c4girhw/ramdisk
256 16:32:25.873809 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 16:32:25.873947 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 16:32:25.874034 [common] Applying overlay to NFS
259 16:32:25.874096 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396140/compress-overlay-p0miglya/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h
260 16:32:26.767413 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:32:26.767550 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 16:32:26.767640 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:32:26.767727 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 16:32:26.767802 Building ramdisk /var/lib/lava/dispatcher/tmp/14396140/extract-overlay-ramdisk-7c4girhw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396140/extract-overlay-ramdisk-7c4girhw/ramdisk
265 16:32:27.117768 >> 130466 blocks
266 16:32:29.260208 rename /var/lib/lava/dispatcher/tmp/14396140/extract-overlay-ramdisk-7c4girhw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/ramdisk/ramdisk.cpio.gz
267 16:32:29.260373 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 16:32:29.260460 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 16:32:29.260539 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 16:32:29.260616 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/kernel/Image']
271 16:32:43.882294 Returned 0 in 14 seconds
272 16:32:43.982771 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/kernel/image.itb
273 16:32:44.395098 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:32:44.395223 output: Created: Mon Jun 17 17:32:44 2024
275 16:32:44.395293 output: Image 0 (kernel-1)
276 16:32:44.395353 output: Description:
277 16:32:44.395407 output: Created: Mon Jun 17 17:32:44 2024
278 16:32:44.395462 output: Type: Kernel Image
279 16:32:44.395514 output: Compression: lzma compressed
280 16:32:44.395571 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
281 16:32:44.395623 output: Architecture: AArch64
282 16:32:44.395675 output: OS: Linux
283 16:32:44.395726 output: Load Address: 0x00000000
284 16:32:44.395778 output: Entry Point: 0x00000000
285 16:32:44.395836 output: Hash algo: crc32
286 16:32:44.395922 output: Hash value: 106ffd6f
287 16:32:44.396008 output: Image 1 (fdt-1)
288 16:32:44.396091 output: Description: mt8192-asurada-spherion-r0
289 16:32:44.396178 output: Created: Mon Jun 17 17:32:44 2024
290 16:32:44.396236 output: Type: Flat Device Tree
291 16:32:44.396289 output: Compression: uncompressed
292 16:32:44.396344 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 16:32:44.396402 output: Architecture: AArch64
294 16:32:44.396457 output: Hash algo: crc32
295 16:32:44.396510 output: Hash value: 0f8e4d2e
296 16:32:44.396559 output: Image 2 (ramdisk-1)
297 16:32:44.396609 output: Description: unavailable
298 16:32:44.396657 output: Created: Mon Jun 17 17:32:44 2024
299 16:32:44.396706 output: Type: RAMDisk Image
300 16:32:44.396755 output: Compression: uncompressed
301 16:32:44.396803 output: Data Size: 18745857 Bytes = 18306.50 KiB = 17.88 MiB
302 16:32:44.396851 output: Architecture: AArch64
303 16:32:44.396898 output: OS: Linux
304 16:32:44.396960 output: Load Address: unavailable
305 16:32:44.397010 output: Entry Point: unavailable
306 16:32:44.397060 output: Hash algo: crc32
307 16:32:44.397109 output: Hash value: 9f54b267
308 16:32:44.397157 output: Default Configuration: 'conf-1'
309 16:32:44.397205 output: Configuration 0 (conf-1)
310 16:32:44.397257 output: Description: mt8192-asurada-spherion-r0
311 16:32:44.397340 output: Kernel: kernel-1
312 16:32:44.397417 output: Init Ramdisk: ramdisk-1
313 16:32:44.397496 output: FDT: fdt-1
314 16:32:44.397582 output: Loadables: kernel-1
315 16:32:44.397634 output:
316 16:32:44.397771 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 16:32:44.397863 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 16:32:44.397953 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 16:32:44.398039 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 16:32:44.398107 No LXC device requested
321 16:32:44.398176 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:32:44.398254 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 16:32:44.398323 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:32:44.398386 Checking files for TFTP limit of 4294967296 bytes.
325 16:32:44.398843 end: 1 tftp-deploy (duration 00:00:40) [common]
326 16:32:44.398943 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:32:44.399029 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:32:44.399145 substitutions:
329 16:32:44.399207 - {DTB}: 14396140/tftp-deploy-98og2484/dtb/mt8192-asurada-spherion-r0.dtb
330 16:32:44.399296 - {INITRD}: 14396140/tftp-deploy-98og2484/ramdisk/ramdisk.cpio.gz
331 16:32:44.399380 - {KERNEL}: 14396140/tftp-deploy-98og2484/kernel/Image
332 16:32:44.399455 - {LAVA_MAC}: None
333 16:32:44.399509 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h
334 16:32:44.399561 - {NFS_SERVER_IP}: 192.168.201.1
335 16:32:44.399612 - {PRESEED_CONFIG}: None
336 16:32:44.399670 - {PRESEED_LOCAL}: None
337 16:32:44.399721 - {RAMDISK}: 14396140/tftp-deploy-98og2484/ramdisk/ramdisk.cpio.gz
338 16:32:44.399771 - {ROOT_PART}: None
339 16:32:44.399842 - {ROOT}: None
340 16:32:44.399895 - {SERVER_IP}: 192.168.201.1
341 16:32:44.399944 - {TEE}: None
342 16:32:44.399994 Parsed boot commands:
343 16:32:44.400042 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:32:44.400194 Parsed boot commands: tftpboot 192.168.201.1 14396140/tftp-deploy-98og2484/kernel/image.itb 14396140/tftp-deploy-98og2484/kernel/cmdline
345 16:32:44.400279 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:32:44.400359 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:32:44.400440 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:32:44.400519 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:32:44.400580 Not connected, no need to disconnect.
350 16:32:44.400647 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:32:44.400724 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:32:44.400787 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 16:32:44.404413 Setting prompt string to ['lava-test: # ']
354 16:32:44.404744 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:32:44.404864 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:32:44.404997 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:32:44.405101 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:32:44.405283 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 16:32:53.550664 >> Command sent successfully.
360 16:32:53.553787 Returned 0 in 9 seconds
361 16:32:53.654140 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 16:32:53.654411 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 16:32:53.654505 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 16:32:53.654591 Setting prompt string to 'Starting depthcharge on Spherion...'
366 16:32:53.654654 Changing prompt to 'Starting depthcharge on Spherion...'
367 16:32:53.654750 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 16:32:53.655163 [Enter `^Ec?' for help]
369 16:32:55.023128
370 16:32:55.023288
371 16:32:55.023415 F0: 102B 0000
372 16:32:55.023540
373 16:32:55.023671 F3: 1001 0000 [0200]
374 16:32:55.023777
375 16:32:55.026792 F3: 1001 0000
376 16:32:55.026889
377 16:32:55.026963 F7: 102D 0000
378 16:32:55.027017
379 16:32:55.027067 F1: 0000 0000
380 16:32:55.027128
381 16:32:55.030561 V0: 0000 0000 [0001]
382 16:32:55.030649
383 16:32:55.030737 00: 0007 8000
384 16:32:55.030837
385 16:32:55.034304 01: 0000 0000
386 16:32:55.034368
387 16:32:55.034436 BP: 0C00 0209 [0000]
388 16:32:55.034488
389 16:32:55.037965 G0: 1182 0000
390 16:32:55.038026
391 16:32:55.038078 EC: 0000 0021 [4000]
392 16:32:55.038129
393 16:32:55.041663 S7: 0000 0000 [0000]
394 16:32:55.041748
395 16:32:55.041825 CC: 0000 0000 [0001]
396 16:32:55.041903
397 16:32:55.044592 T0: 0000 0040 [010F]
398 16:32:55.044658
399 16:32:55.044709 Jump to BL
400 16:32:55.044758
401 16:32:55.070372
402 16:32:55.070477
403 16:32:55.077323 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 16:32:55.081467 ARM64: Exception handlers installed.
405 16:32:55.084932 ARM64: Testing exception
406 16:32:55.085047 ARM64: Done test exception
407 16:32:55.092498 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 16:32:55.103664 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 16:32:55.111430 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 16:32:55.122164 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 16:32:55.129461 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 16:32:55.135987 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 16:32:55.146047 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 16:32:55.152784 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 16:32:55.172891 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 16:32:55.175689 WDT: Last reset was cold boot
417 16:32:55.179310 SPI1(PAD0) initialized at 2873684 Hz
418 16:32:55.182787 SPI5(PAD0) initialized at 992727 Hz
419 16:32:55.185722 VBOOT: Loading verstage.
420 16:32:55.193037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 16:32:55.195795 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 16:32:55.199260 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 16:32:55.202827 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 16:32:55.210146 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 16:32:55.216737 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 16:32:55.227744 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 16:32:55.227858
428 16:32:55.227937
429 16:32:55.237257 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 16:32:55.240975 ARM64: Exception handlers installed.
431 16:32:55.244693 ARM64: Testing exception
432 16:32:55.244775 ARM64: Done test exception
433 16:32:55.251330 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 16:32:55.254344 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 16:32:55.268698 Probing TPM: . done!
436 16:32:55.268782 TPM ready after 0 ms
437 16:32:55.274971 Connected to device vid:did:rid of 1ae0:0028:00
438 16:32:55.285487 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 16:32:55.322286 Initialized TPM device CR50 revision 0
440 16:32:55.333870 tlcl_send_startup: Startup return code is 0
441 16:32:55.333959 TPM: setup succeeded
442 16:32:55.345340 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 16:32:55.354361 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 16:32:55.364624 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 16:32:55.373909 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 16:32:55.376798 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 16:32:55.380290 in-header: 03 07 00 00 08 00 00 00
448 16:32:55.383290 in-data: aa e4 47 04 13 02 00 00
449 16:32:55.386579 Chrome EC: UHEPI supported
450 16:32:55.393903 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 16:32:55.396795 in-header: 03 a9 00 00 08 00 00 00
452 16:32:55.400064 in-data: 84 60 60 08 00 00 00 00
453 16:32:55.400139 Phase 1
454 16:32:55.406767 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 16:32:55.410488 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 16:32:55.416959 VB2:vb2_check_recovery() Recovery was requested manually
457 16:32:55.423988 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 16:32:55.424064 Recovery requested (1009000e)
459 16:32:55.432750 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 16:32:55.437823 tlcl_extend: response is 0
461 16:32:55.448774 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 16:32:55.452023 tlcl_extend: response is 0
463 16:32:55.457765 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 16:32:55.478818 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 16:32:55.485340 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 16:32:55.485427
467 16:32:55.485487
468 16:32:55.495345 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 16:32:55.498873 ARM64: Exception handlers installed.
470 16:32:55.501774 ARM64: Testing exception
471 16:32:55.501881 ARM64: Done test exception
472 16:32:55.524091 pmic_efuse_setting: Set efuses in 11 msecs
473 16:32:55.527759 pmwrap_interface_init: Select PMIF_VLD_RDY
474 16:32:55.534327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 16:32:55.537996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 16:32:55.544488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 16:32:55.547496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 16:32:55.554664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 16:32:55.557899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 16:32:55.561364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 16:32:55.567368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 16:32:55.571008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 16:32:55.577456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 16:32:55.581101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 16:32:55.584625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 16:32:55.591275 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 16:32:55.597768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 16:32:55.601323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 16:32:55.607813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 16:32:55.614431 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 16:32:55.618000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 16:32:55.625794 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 16:32:55.629140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 16:32:55.636192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 16:32:55.643390 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 16:32:55.647014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 16:32:55.654233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 16:32:55.657107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 16:32:55.663942 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 16:32:55.667415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 16:32:55.674070 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 16:32:55.677480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 16:32:55.683965 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 16:32:55.687376 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 16:32:55.694051 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 16:32:55.697682 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 16:32:55.704334 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 16:32:55.707196 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 16:32:55.714411 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 16:32:55.717401 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 16:32:55.724580 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 16:32:55.728212 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 16:32:55.731781 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 16:32:55.735131 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 16:32:55.741964 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 16:32:55.744660 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 16:32:55.748119 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 16:32:55.754884 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 16:32:55.758615 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 16:32:55.761531 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 16:32:55.768392 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 16:32:55.772186 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 16:32:55.775084 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 16:32:55.778099 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 16:32:55.788303 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 16:32:55.795262 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 16:32:55.801799 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 16:32:55.808338 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 16:32:55.818118 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 16:32:55.821890 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 16:32:55.824701 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 16:32:55.831391 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 16:32:55.838105 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x9
534 16:32:55.841945 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 16:32:55.848403 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 16:32:55.851960 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 16:32:55.861275 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 16:32:55.870857 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 16:32:55.880668 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 16:32:55.890331 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 16:32:55.899485 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 16:32:55.908736 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 16:32:55.918937 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 16:32:55.921683 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 16:32:55.928792 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 16:32:55.932201 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 16:32:55.935785 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 16:32:55.942365 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 16:32:55.945377 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 16:32:55.949056 ADC[4]: Raw value=905465 ID=7
551 16:32:55.949127 ADC[3]: Raw value=213441 ID=1
552 16:32:55.952654 RAM Code: 0x71
553 16:32:55.955609 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 16:32:55.962645 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 16:32:55.969463 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 16:32:55.975642 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 16:32:55.979330 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 16:32:55.982283 in-header: 03 07 00 00 08 00 00 00
559 16:32:55.985961 in-data: aa e4 47 04 13 02 00 00
560 16:32:55.988863 Chrome EC: UHEPI supported
561 16:32:55.995645 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 16:32:55.999272 in-header: 03 a9 00 00 08 00 00 00
563 16:32:56.002740 in-data: 84 60 60 08 00 00 00 00
564 16:32:56.005624 MRC: failed to locate region type 0.
565 16:32:56.012567 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 16:32:56.015630 DRAM-K: Running full calibration
567 16:32:56.022070 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 16:32:56.022146 header.status = 0x0
569 16:32:56.025489 header.version = 0x6 (expected: 0x6)
570 16:32:56.029057 header.size = 0xd00 (expected: 0xd00)
571 16:32:56.032506 header.flags = 0x0
572 16:32:56.038694 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 16:32:56.055446 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 16:32:56.062206 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 16:32:56.065846 dram_init: ddr_geometry: 2
576 16:32:56.065925 [EMI] MDL number = 2
577 16:32:56.069317 [EMI] Get MDL freq = 0
578 16:32:56.072328 dram_init: ddr_type: 0
579 16:32:56.072401 is_discrete_lpddr4: 1
580 16:32:56.075918 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 16:32:56.075997
582 16:32:56.076058
583 16:32:56.079374 [Bian_co] ETT version 0.0.0.1
584 16:32:56.085619 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 16:32:56.085692
586 16:32:56.089266 dramc_set_vcore_voltage set vcore to 650000
587 16:32:56.089340 Read voltage for 800, 4
588 16:32:56.092238 Vio18 = 0
589 16:32:56.092308 Vcore = 650000
590 16:32:56.092366 Vdram = 0
591 16:32:56.096064 Vddq = 0
592 16:32:56.096135 Vmddr = 0
593 16:32:56.099116 dram_init: config_dvfs: 1
594 16:32:56.102098 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 16:32:56.108697 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 16:32:56.112393 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 16:32:56.115481 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 16:32:56.118901 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 16:32:56.122268 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 16:32:56.125587 MEM_TYPE=3, freq_sel=18
601 16:32:56.129264 sv_algorithm_assistance_LP4_1600
602 16:32:56.132695 ============ PULL DRAM RESETB DOWN ============
603 16:32:56.135423 ========== PULL DRAM RESETB DOWN end =========
604 16:32:56.141987 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 16:32:56.145511 ===================================
606 16:32:56.149012 LPDDR4 DRAM CONFIGURATION
607 16:32:56.152459 ===================================
608 16:32:56.152534 EX_ROW_EN[0] = 0x0
609 16:32:56.155774 EX_ROW_EN[1] = 0x0
610 16:32:56.155847 LP4Y_EN = 0x0
611 16:32:56.159038 WORK_FSP = 0x0
612 16:32:56.159115 WL = 0x2
613 16:32:56.162212 RL = 0x2
614 16:32:56.162285 BL = 0x2
615 16:32:56.165538 RPST = 0x0
616 16:32:56.165621 RD_PRE = 0x0
617 16:32:56.169264 WR_PRE = 0x1
618 16:32:56.169365 WR_PST = 0x0
619 16:32:56.172265 DBI_WR = 0x0
620 16:32:56.172344 DBI_RD = 0x0
621 16:32:56.175841 OTF = 0x1
622 16:32:56.179394 ===================================
623 16:32:56.182416 ===================================
624 16:32:56.182496 ANA top config
625 16:32:56.186018 ===================================
626 16:32:56.188836 DLL_ASYNC_EN = 0
627 16:32:56.192147 ALL_SLAVE_EN = 1
628 16:32:56.195535 NEW_RANK_MODE = 1
629 16:32:56.195622 DLL_IDLE_MODE = 1
630 16:32:56.199168 LP45_APHY_COMB_EN = 1
631 16:32:56.202785 TX_ODT_DIS = 1
632 16:32:56.205909 NEW_8X_MODE = 1
633 16:32:56.208888 ===================================
634 16:32:56.212631 ===================================
635 16:32:56.215577 data_rate = 1600
636 16:32:56.215674 CKR = 1
637 16:32:56.219219 DQ_P2S_RATIO = 8
638 16:32:56.222798 ===================================
639 16:32:56.225805 CA_P2S_RATIO = 8
640 16:32:56.229314 DQ_CA_OPEN = 0
641 16:32:56.232728 DQ_SEMI_OPEN = 0
642 16:32:56.232803 CA_SEMI_OPEN = 0
643 16:32:56.236020 CA_FULL_RATE = 0
644 16:32:56.238952 DQ_CKDIV4_EN = 1
645 16:32:56.242461 CA_CKDIV4_EN = 1
646 16:32:56.246079 CA_PREDIV_EN = 0
647 16:32:56.249128 PH8_DLY = 0
648 16:32:56.249207 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 16:32:56.252980 DQ_AAMCK_DIV = 4
650 16:32:56.255927 CA_AAMCK_DIV = 4
651 16:32:56.259512 CA_ADMCK_DIV = 4
652 16:32:56.262972 DQ_TRACK_CA_EN = 0
653 16:32:56.265745 CA_PICK = 800
654 16:32:56.265854 CA_MCKIO = 800
655 16:32:56.269374 MCKIO_SEMI = 0
656 16:32:56.272652 PLL_FREQ = 3068
657 16:32:56.276023 DQ_UI_PI_RATIO = 32
658 16:32:56.279246 CA_UI_PI_RATIO = 0
659 16:32:56.282817 ===================================
660 16:32:56.286390 ===================================
661 16:32:56.286468 memory_type:LPDDR4
662 16:32:56.290118 GP_NUM : 10
663 16:32:56.293956 SRAM_EN : 1
664 16:32:56.294033 MD32_EN : 0
665 16:32:56.297506 ===================================
666 16:32:56.301536 [ANA_INIT] >>>>>>>>>>>>>>
667 16:32:56.301624 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 16:32:56.305589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 16:32:56.309085 ===================================
670 16:32:56.313515 data_rate = 1600,PCW = 0X7600
671 16:32:56.317330 ===================================
672 16:32:56.317411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 16:32:56.324103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 16:32:56.330688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 16:32:56.333764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 16:32:56.337447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 16:32:56.340814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 16:32:56.343557 [ANA_INIT] flow start
679 16:32:56.343638 [ANA_INIT] PLL >>>>>>>>
680 16:32:56.347225 [ANA_INIT] PLL <<<<<<<<
681 16:32:56.350540 [ANA_INIT] MIDPI >>>>>>>>
682 16:32:56.354307 [ANA_INIT] MIDPI <<<<<<<<
683 16:32:56.354408 [ANA_INIT] DLL >>>>>>>>
684 16:32:56.357240 [ANA_INIT] flow end
685 16:32:56.360907 ============ LP4 DIFF to SE enter ============
686 16:32:56.363779 ============ LP4 DIFF to SE exit ============
687 16:32:56.367371 [ANA_INIT] <<<<<<<<<<<<<
688 16:32:56.370913 [Flow] Enable top DCM control >>>>>
689 16:32:56.373792 [Flow] Enable top DCM control <<<<<
690 16:32:56.377519 Enable DLL master slave shuffle
691 16:32:56.383916 ==============================================================
692 16:32:56.383992 Gating Mode config
693 16:32:56.390615 ==============================================================
694 16:32:56.390690 Config description:
695 16:32:56.400944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 16:32:56.407473 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 16:32:56.414381 SELPH_MODE 0: By rank 1: By Phase
698 16:32:56.417065 ==============================================================
699 16:32:56.420419 GAT_TRACK_EN = 1
700 16:32:56.423937 RX_GATING_MODE = 2
701 16:32:56.427468 RX_GATING_TRACK_MODE = 2
702 16:32:56.430484 SELPH_MODE = 1
703 16:32:56.434249 PICG_EARLY_EN = 1
704 16:32:56.437107 VALID_LAT_VALUE = 1
705 16:32:56.440617 ==============================================================
706 16:32:56.444429 Enter into Gating configuration >>>>
707 16:32:56.447259 Exit from Gating configuration <<<<
708 16:32:56.450625 Enter into DVFS_PRE_config >>>>>
709 16:32:56.460972 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 16:32:56.463973 Exit from DVFS_PRE_config <<<<<
711 16:32:56.467604 Enter into PICG configuration >>>>
712 16:32:56.470662 Exit from PICG configuration <<<<
713 16:32:56.474319 [RX_INPUT] configuration >>>>>
714 16:32:56.477945 [RX_INPUT] configuration <<<<<
715 16:32:56.483946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 16:32:56.487880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 16:32:56.494517 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 16:32:56.501012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 16:32:56.507950 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 16:32:56.514687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 16:32:56.517709 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 16:32:56.521334 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 16:32:56.524862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 16:32:56.527632 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 16:32:56.534609 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 16:32:56.537756 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 16:32:56.541323 ===================================
728 16:32:56.544847 LPDDR4 DRAM CONFIGURATION
729 16:32:56.547831 ===================================
730 16:32:56.547909 EX_ROW_EN[0] = 0x0
731 16:32:56.551537 EX_ROW_EN[1] = 0x0
732 16:32:56.551617 LP4Y_EN = 0x0
733 16:32:56.554408 WORK_FSP = 0x0
734 16:32:56.554486 WL = 0x2
735 16:32:56.557785 RL = 0x2
736 16:32:56.557873 BL = 0x2
737 16:32:56.561148 RPST = 0x0
738 16:32:56.561225 RD_PRE = 0x0
739 16:32:56.564687 WR_PRE = 0x1
740 16:32:56.567522 WR_PST = 0x0
741 16:32:56.567600 DBI_WR = 0x0
742 16:32:56.571148 DBI_RD = 0x0
743 16:32:56.571226 OTF = 0x1
744 16:32:56.574089 ===================================
745 16:32:56.577604 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 16:32:56.581255 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 16:32:56.587798 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 16:32:56.591476 ===================================
749 16:32:56.591554 LPDDR4 DRAM CONFIGURATION
750 16:32:56.594548 ===================================
751 16:32:56.597503 EX_ROW_EN[0] = 0x10
752 16:32:56.601123 EX_ROW_EN[1] = 0x0
753 16:32:56.601200 LP4Y_EN = 0x0
754 16:32:56.604797 WORK_FSP = 0x0
755 16:32:56.604875 WL = 0x2
756 16:32:56.607698 RL = 0x2
757 16:32:56.607775 BL = 0x2
758 16:32:56.611460 RPST = 0x0
759 16:32:56.611538 RD_PRE = 0x0
760 16:32:56.614912 WR_PRE = 0x1
761 16:32:56.614989 WR_PST = 0x0
762 16:32:56.617661 DBI_WR = 0x0
763 16:32:56.617738 DBI_RD = 0x0
764 16:32:56.621106 OTF = 0x1
765 16:32:56.624917 ===================================
766 16:32:56.631133 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 16:32:56.634586 nWR fixed to 40
768 16:32:56.634664 [ModeRegInit_LP4] CH0 RK0
769 16:32:56.638194 [ModeRegInit_LP4] CH0 RK1
770 16:32:56.641779 [ModeRegInit_LP4] CH1 RK0
771 16:32:56.644683 [ModeRegInit_LP4] CH1 RK1
772 16:32:56.644761 match AC timing 13
773 16:32:56.648144 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 16:32:56.651295 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 16:32:56.658149 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 16:32:56.661581 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 16:32:56.667936 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 16:32:56.668042 [EMI DOE] emi_dcm 0
779 16:32:56.674909 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 16:32:56.675013 ==
781 16:32:56.678728 Dram Type= 6, Freq= 0, CH_0, rank 0
782 16:32:56.681487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 16:32:56.681608 ==
784 16:32:56.685098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 16:32:56.691689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 16:32:56.701307 [CA 0] Center 36 (6~67) winsize 62
787 16:32:56.704959 [CA 1] Center 36 (6~67) winsize 62
788 16:32:56.707960 [CA 2] Center 34 (4~65) winsize 62
789 16:32:56.711710 [CA 3] Center 34 (4~64) winsize 61
790 16:32:56.714697 [CA 4] Center 33 (3~64) winsize 62
791 16:32:56.718287 [CA 5] Center 32 (3~62) winsize 60
792 16:32:56.718363
793 16:32:56.721945 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 16:32:56.722037
795 16:32:56.724920 [CATrainingPosCal] consider 1 rank data
796 16:32:56.728617 u2DelayCellTimex100 = 270/100 ps
797 16:32:56.732015 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 16:32:56.735238 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 16:32:56.738698 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 16:32:56.745029 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 16:32:56.748512 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 16:32:56.751926 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 16:32:56.752021
804 16:32:56.755532 CA PerBit enable=1, Macro0, CA PI delay=32
805 16:32:56.755632
806 16:32:56.758339 [CBTSetCACLKResult] CA Dly = 32
807 16:32:56.758430 CS Dly: 5 (0~36)
808 16:32:56.758518 ==
809 16:32:56.761726 Dram Type= 6, Freq= 0, CH_0, rank 1
810 16:32:56.768208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 16:32:56.768312 ==
812 16:32:56.771684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 16:32:56.778831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 16:32:56.788112 [CA 0] Center 36 (6~67) winsize 62
815 16:32:56.791052 [CA 1] Center 36 (6~67) winsize 62
816 16:32:56.794638 [CA 2] Center 34 (4~65) winsize 62
817 16:32:56.797619 [CA 3] Center 34 (3~65) winsize 63
818 16:32:56.801089 [CA 4] Center 32 (2~63) winsize 62
819 16:32:56.804092 [CA 5] Center 32 (2~63) winsize 62
820 16:32:56.804196
821 16:32:56.807802 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 16:32:56.807895
823 16:32:56.811583 [CATrainingPosCal] consider 2 rank data
824 16:32:56.814469 u2DelayCellTimex100 = 270/100 ps
825 16:32:56.817924 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 16:32:56.820871 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 16:32:56.827661 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 16:32:56.831252 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 16:32:56.834853 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 16:32:56.837701 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 16:32:56.837772
832 16:32:56.841440 CA PerBit enable=1, Macro0, CA PI delay=32
833 16:32:56.841535
834 16:32:56.844429 [CBTSetCACLKResult] CA Dly = 32
835 16:32:56.844523 CS Dly: 5 (0~36)
836 16:32:56.844606
837 16:32:56.848018 ----->DramcWriteLeveling(PI) begin...
838 16:32:56.851648 ==
839 16:32:56.851745 Dram Type= 6, Freq= 0, CH_0, rank 0
840 16:32:56.857939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 16:32:56.858033 ==
842 16:32:56.861487 Write leveling (Byte 0): 31 => 31
843 16:32:56.861587 Write leveling (Byte 1): 27 => 27
844 16:32:56.865079 DramcWriteLeveling(PI) end<-----
845 16:32:56.865177
846 16:32:56.865269 ==
847 16:32:56.868689 Dram Type= 6, Freq= 0, CH_0, rank 0
848 16:32:56.875639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 16:32:56.875736 ==
850 16:32:56.875826 [Gating] SW mode calibration
851 16:32:56.885796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 16:32:56.889135 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 16:32:56.891944 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 16:32:56.898517 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 16:32:56.902371 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 16:32:56.905275 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:32:56.912141 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:32:56.915205 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:32:56.918807 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:32:56.925381 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:32:56.928922 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:32:56.931842 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:32:56.938565 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:32:56.942191 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:32:56.945040 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:32:56.952005 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:32:56.955605 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 16:32:56.958540 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 16:32:56.965057 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 16:32:56.968682 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
871 16:32:56.972254 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 16:32:56.978415 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 16:32:56.982092 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:32:56.985571 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:32:56.988797 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 16:32:56.995347 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 16:32:56.998710 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 16:32:57.002006 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 16:32:57.008785 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
880 16:32:57.012390 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 16:32:57.015445 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:32:57.022592 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 16:32:57.025519 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 16:32:57.029079 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 16:32:57.035702 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 16:32:57.039522 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
887 16:32:57.042497 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
888 16:32:57.049043 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
889 16:32:57.052091 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:32:57.055686 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:32:57.059213 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 16:32:57.065751 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 16:32:57.069385 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 16:32:57.072332 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
895 16:32:57.078933 0 11 8 | B1->B0 | 2b2b 4040 | 0 0 | (1 1) (0 0)
896 16:32:57.082478 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 16:32:57.085987 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:32:57.092545 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:32:57.095959 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 16:32:57.098813 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 16:32:57.105434 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 16:32:57.108820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 16:32:57.112804 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 16:32:57.118821 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 16:32:57.122623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:32:57.125917 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:32:57.132434 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:32:57.136069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:32:57.139104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:32:57.142625 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:32:57.148997 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:32:57.152541 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:32:57.156187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:32:57.162749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 16:32:57.165666 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 16:32:57.169163 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 16:32:57.176251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 16:32:57.179228 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 16:32:57.182730 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 16:32:57.185624 Total UI for P1: 0, mck2ui 16
921 16:32:57.189410 best dqsien dly found for B0: ( 0, 14, 4)
922 16:32:57.195874 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 16:32:57.195990 Total UI for P1: 0, mck2ui 16
924 16:32:57.202610 best dqsien dly found for B1: ( 0, 14, 8)
925 16:32:57.206209 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 16:32:57.209131 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 16:32:57.209212
928 16:32:57.212602 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 16:32:57.215868 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 16:32:57.219397 [Gating] SW calibration Done
931 16:32:57.219496 ==
932 16:32:57.222880 Dram Type= 6, Freq= 0, CH_0, rank 0
933 16:32:57.225742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 16:32:57.225821 ==
935 16:32:57.229445 RX Vref Scan: 0
936 16:32:57.229554
937 16:32:57.229630 RX Vref 0 -> 0, step: 1
938 16:32:57.229686
939 16:32:57.232330 RX Delay -130 -> 252, step: 16
940 16:32:57.235632 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 16:32:57.239267 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 16:32:57.245734 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 16:32:57.249682 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 16:32:57.252472 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 16:32:57.256027 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 16:32:57.259789 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 16:32:57.266214 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 16:32:57.269125 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 16:32:57.272880 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 16:32:57.276305 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 16:32:57.279294 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 16:32:57.286271 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 16:32:57.289097 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 16:32:57.292799 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 16:32:57.295672 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 16:32:57.295755 ==
957 16:32:57.299245 Dram Type= 6, Freq= 0, CH_0, rank 0
958 16:32:57.306250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 16:32:57.306328 ==
960 16:32:57.306390 DQS Delay:
961 16:32:57.309110 DQS0 = 0, DQS1 = 0
962 16:32:57.309205 DQM Delay:
963 16:32:57.309290 DQM0 = 89, DQM1 = 80
964 16:32:57.312849 DQ Delay:
965 16:32:57.315756 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 16:32:57.319337 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 16:32:57.322860 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
968 16:32:57.325649 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 16:32:57.325746
970 16:32:57.325840
971 16:32:57.325924 ==
972 16:32:57.329592 Dram Type= 6, Freq= 0, CH_0, rank 0
973 16:32:57.332945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 16:32:57.333025 ==
975 16:32:57.333087
976 16:32:57.333142
977 16:32:57.336233 TX Vref Scan disable
978 16:32:57.336313 == TX Byte 0 ==
979 16:32:57.343016 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 16:32:57.345835 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 16:32:57.345916 == TX Byte 1 ==
982 16:32:57.352535 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
983 16:32:57.356178 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
984 16:32:57.356289 ==
985 16:32:57.359665 Dram Type= 6, Freq= 0, CH_0, rank 0
986 16:32:57.362555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 16:32:57.362670 ==
988 16:32:57.377136 TX Vref=22, minBit 7, minWin=27, winSum=449
989 16:32:57.380786 TX Vref=24, minBit 8, minWin=27, winSum=451
990 16:32:57.383662 TX Vref=26, minBit 9, minWin=27, winSum=456
991 16:32:57.387396 TX Vref=28, minBit 0, minWin=28, winSum=458
992 16:32:57.390395 TX Vref=30, minBit 8, minWin=28, winSum=458
993 16:32:57.394086 TX Vref=32, minBit 8, minWin=28, winSum=460
994 16:32:57.400520 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 32
995 16:32:57.400604
996 16:32:57.404091 Final TX Range 1 Vref 32
997 16:32:57.404171
998 16:32:57.404232 ==
999 16:32:57.407557 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 16:32:57.411200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 16:32:57.411280 ==
1002 16:32:57.411341
1003 16:32:57.411398
1004 16:32:57.414198 TX Vref Scan disable
1005 16:32:57.417236 == TX Byte 0 ==
1006 16:32:57.420749 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 16:32:57.423741 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 16:32:57.427329 == TX Byte 1 ==
1009 16:32:57.431024 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1010 16:32:57.433957 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1011 16:32:57.434035
1012 16:32:57.437529 [DATLAT]
1013 16:32:57.437620 Freq=800, CH0 RK0
1014 16:32:57.437683
1015 16:32:57.440869 DATLAT Default: 0xa
1016 16:32:57.440961 0, 0xFFFF, sum = 0
1017 16:32:57.444078 1, 0xFFFF, sum = 0
1018 16:32:57.444146 2, 0xFFFF, sum = 0
1019 16:32:57.447478 3, 0xFFFF, sum = 0
1020 16:32:57.447599 4, 0xFFFF, sum = 0
1021 16:32:57.450957 5, 0xFFFF, sum = 0
1022 16:32:57.451064 6, 0xFFFF, sum = 0
1023 16:32:57.454211 7, 0xFFFF, sum = 0
1024 16:32:57.454309 8, 0xFFFF, sum = 0
1025 16:32:57.457418 9, 0x0, sum = 1
1026 16:32:57.457501 10, 0x0, sum = 2
1027 16:32:57.460724 11, 0x0, sum = 3
1028 16:32:57.460837 12, 0x0, sum = 4
1029 16:32:57.464346 best_step = 10
1030 16:32:57.464451
1031 16:32:57.464539 ==
1032 16:32:57.467978 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 16:32:57.470775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 16:32:57.470855 ==
1035 16:32:57.474507 RX Vref Scan: 1
1036 16:32:57.474586
1037 16:32:57.474647 Set Vref Range= 32 -> 127
1038 16:32:57.474704
1039 16:32:57.477374 RX Vref 32 -> 127, step: 1
1040 16:32:57.477464
1041 16:32:57.481019 RX Delay -95 -> 252, step: 8
1042 16:32:57.481091
1043 16:32:57.484549 Set Vref, RX VrefLevel [Byte0]: 32
1044 16:32:57.488159 [Byte1]: 32
1045 16:32:57.488238
1046 16:32:57.491046 Set Vref, RX VrefLevel [Byte0]: 33
1047 16:32:57.494701 [Byte1]: 33
1048 16:32:57.494781
1049 16:32:57.497770 Set Vref, RX VrefLevel [Byte0]: 34
1050 16:32:57.501344 [Byte1]: 34
1051 16:32:57.504858
1052 16:32:57.504967 Set Vref, RX VrefLevel [Byte0]: 35
1053 16:32:57.508018 [Byte1]: 35
1054 16:32:57.512317
1055 16:32:57.512415 Set Vref, RX VrefLevel [Byte0]: 36
1056 16:32:57.515712 [Byte1]: 36
1057 16:32:57.520140
1058 16:32:57.520234 Set Vref, RX VrefLevel [Byte0]: 37
1059 16:32:57.523805 [Byte1]: 37
1060 16:32:57.527575
1061 16:32:57.527648 Set Vref, RX VrefLevel [Byte0]: 38
1062 16:32:57.531331 [Byte1]: 38
1063 16:32:57.535689
1064 16:32:57.535767 Set Vref, RX VrefLevel [Byte0]: 39
1065 16:32:57.538676 [Byte1]: 39
1066 16:32:57.543137
1067 16:32:57.543215 Set Vref, RX VrefLevel [Byte0]: 40
1068 16:32:57.546663 [Byte1]: 40
1069 16:32:57.551011
1070 16:32:57.551089 Set Vref, RX VrefLevel [Byte0]: 41
1071 16:32:57.553804 [Byte1]: 41
1072 16:32:57.558043
1073 16:32:57.558121 Set Vref, RX VrefLevel [Byte0]: 42
1074 16:32:57.561529 [Byte1]: 42
1075 16:32:57.566210
1076 16:32:57.566289 Set Vref, RX VrefLevel [Byte0]: 43
1077 16:32:57.569429 [Byte1]: 43
1078 16:32:57.573207
1079 16:32:57.573306 Set Vref, RX VrefLevel [Byte0]: 44
1080 16:32:57.576995 [Byte1]: 44
1081 16:32:57.580671
1082 16:32:57.580779 Set Vref, RX VrefLevel [Byte0]: 45
1083 16:32:57.584087 [Byte1]: 45
1084 16:32:57.588823
1085 16:32:57.588926 Set Vref, RX VrefLevel [Byte0]: 46
1086 16:32:57.592046 [Byte1]: 46
1087 16:32:57.596510
1088 16:32:57.596613 Set Vref, RX VrefLevel [Byte0]: 47
1089 16:32:57.599205 [Byte1]: 47
1090 16:32:57.604181
1091 16:32:57.604288 Set Vref, RX VrefLevel [Byte0]: 48
1092 16:32:57.606966 [Byte1]: 48
1093 16:32:57.611308
1094 16:32:57.611394 Set Vref, RX VrefLevel [Byte0]: 49
1095 16:32:57.614816 [Byte1]: 49
1096 16:32:57.619241
1097 16:32:57.619338 Set Vref, RX VrefLevel [Byte0]: 50
1098 16:32:57.622593 [Byte1]: 50
1099 16:32:57.626530
1100 16:32:57.626615 Set Vref, RX VrefLevel [Byte0]: 51
1101 16:32:57.630246 [Byte1]: 51
1102 16:32:57.633802
1103 16:32:57.633876 Set Vref, RX VrefLevel [Byte0]: 52
1104 16:32:57.637575 [Byte1]: 52
1105 16:32:57.642081
1106 16:32:57.642177 Set Vref, RX VrefLevel [Byte0]: 53
1107 16:32:57.644951 [Byte1]: 53
1108 16:32:57.649320
1109 16:32:57.649416 Set Vref, RX VrefLevel [Byte0]: 54
1110 16:32:57.653053 [Byte1]: 54
1111 16:32:57.656710
1112 16:32:57.656796 Set Vref, RX VrefLevel [Byte0]: 55
1113 16:32:57.660223 [Byte1]: 55
1114 16:32:57.664767
1115 16:32:57.664839 Set Vref, RX VrefLevel [Byte0]: 56
1116 16:32:57.667520 [Byte1]: 56
1117 16:32:57.672566
1118 16:32:57.672654 Set Vref, RX VrefLevel [Byte0]: 57
1119 16:32:57.675420 [Byte1]: 57
1120 16:32:57.679751
1121 16:32:57.679830 Set Vref, RX VrefLevel [Byte0]: 58
1122 16:32:57.683328 [Byte1]: 58
1123 16:32:57.687348
1124 16:32:57.687426 Set Vref, RX VrefLevel [Byte0]: 59
1125 16:32:57.690659 [Byte1]: 59
1126 16:32:57.694818
1127 16:32:57.694912 Set Vref, RX VrefLevel [Byte0]: 60
1128 16:32:57.698502 [Byte1]: 60
1129 16:32:57.702393
1130 16:32:57.702498 Set Vref, RX VrefLevel [Byte0]: 61
1131 16:32:57.705859 [Byte1]: 61
1132 16:32:57.709907
1133 16:32:57.710003 Set Vref, RX VrefLevel [Byte0]: 62
1134 16:32:57.713168 [Byte1]: 62
1135 16:32:57.717954
1136 16:32:57.718073 Set Vref, RX VrefLevel [Byte0]: 63
1137 16:32:57.721374 [Byte1]: 63
1138 16:32:57.725530
1139 16:32:57.725639 Set Vref, RX VrefLevel [Byte0]: 64
1140 16:32:57.728916 [Byte1]: 64
1141 16:32:57.733089
1142 16:32:57.733183 Set Vref, RX VrefLevel [Byte0]: 65
1143 16:32:57.736176 [Byte1]: 65
1144 16:32:57.740617
1145 16:32:57.740688 Set Vref, RX VrefLevel [Byte0]: 66
1146 16:32:57.743663 [Byte1]: 66
1147 16:32:57.748250
1148 16:32:57.748344 Set Vref, RX VrefLevel [Byte0]: 67
1149 16:32:57.751141 [Byte1]: 67
1150 16:32:57.755539
1151 16:32:57.755636 Set Vref, RX VrefLevel [Byte0]: 68
1152 16:32:57.759178 [Byte1]: 68
1153 16:32:57.763655
1154 16:32:57.763752 Set Vref, RX VrefLevel [Byte0]: 69
1155 16:32:57.766704 [Byte1]: 69
1156 16:32:57.771182
1157 16:32:57.771283 Set Vref, RX VrefLevel [Byte0]: 70
1158 16:32:57.774130 [Byte1]: 70
1159 16:32:57.778236
1160 16:32:57.778335 Set Vref, RX VrefLevel [Byte0]: 71
1161 16:32:57.781943 [Byte1]: 71
1162 16:32:57.786414
1163 16:32:57.786529 Set Vref, RX VrefLevel [Byte0]: 72
1164 16:32:57.789235 [Byte1]: 72
1165 16:32:57.794189
1166 16:32:57.794293 Set Vref, RX VrefLevel [Byte0]: 73
1167 16:32:57.796939 [Byte1]: 73
1168 16:32:57.801596
1169 16:32:57.801676 Set Vref, RX VrefLevel [Byte0]: 74
1170 16:32:57.805032 [Byte1]: 74
1171 16:32:57.809253
1172 16:32:57.809332 Set Vref, RX VrefLevel [Byte0]: 75
1173 16:32:57.812141 [Byte1]: 75
1174 16:32:57.816399
1175 16:32:57.816494 Set Vref, RX VrefLevel [Byte0]: 76
1176 16:32:57.819870 [Byte1]: 76
1177 16:32:57.824141
1178 16:32:57.824220 Set Vref, RX VrefLevel [Byte0]: 77
1179 16:32:57.827753 [Byte1]: 77
1180 16:32:57.832100
1181 16:32:57.832180 Set Vref, RX VrefLevel [Byte0]: 78
1182 16:32:57.834942 [Byte1]: 78
1183 16:32:57.839667
1184 16:32:57.839746 Set Vref, RX VrefLevel [Byte0]: 79
1185 16:32:57.842358 [Byte1]: 79
1186 16:32:57.847089
1187 16:32:57.847168 Final RX Vref Byte 0 = 50 to rank0
1188 16:32:57.850645 Final RX Vref Byte 1 = 60 to rank0
1189 16:32:57.853494 Final RX Vref Byte 0 = 50 to rank1
1190 16:32:57.857258 Final RX Vref Byte 1 = 60 to rank1==
1191 16:32:57.860246 Dram Type= 6, Freq= 0, CH_0, rank 0
1192 16:32:57.866990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 16:32:57.867074 ==
1194 16:32:57.867135 DQS Delay:
1195 16:32:57.867191 DQS0 = 0, DQS1 = 0
1196 16:32:57.870671 DQM Delay:
1197 16:32:57.870749 DQM0 = 91, DQM1 = 84
1198 16:32:57.873680 DQ Delay:
1199 16:32:57.877265 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1200 16:32:57.877344 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1201 16:32:57.880218 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1202 16:32:57.883656 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1203 16:32:57.886990
1204 16:32:57.887068
1205 16:32:57.894016 [DQSOSCAuto] RK0, (LSB)MR18= 0x5148, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
1206 16:32:57.896969 CH0 RK0: MR19=606, MR18=5148
1207 16:32:57.903623 CH0_RK0: MR19=0x606, MR18=0x5148, DQSOSC=389, MR23=63, INC=97, DEC=65
1208 16:32:57.903728
1209 16:32:57.907267 ----->DramcWriteLeveling(PI) begin...
1210 16:32:57.907371 ==
1211 16:32:57.910737 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 16:32:57.914277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 16:32:57.914358 ==
1214 16:32:57.917645 Write leveling (Byte 0): 33 => 33
1215 16:32:57.920439 Write leveling (Byte 1): 31 => 31
1216 16:32:57.923796 DramcWriteLeveling(PI) end<-----
1217 16:32:57.923907
1218 16:32:57.923995 ==
1219 16:32:57.927280 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 16:32:57.930215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 16:32:57.930289 ==
1222 16:32:57.933734 [Gating] SW mode calibration
1223 16:32:57.977876 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1224 16:32:57.978229 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1225 16:32:57.978339 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1226 16:32:57.978444 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1227 16:32:57.978552 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1228 16:32:57.978642 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:32:57.978729 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:32:57.978813 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:32:57.978902 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:32:58.018186 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 16:32:58.018532 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 16:32:58.018660 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 16:32:58.018750 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 16:32:58.018846 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 16:32:58.018936 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 16:32:58.019041 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 16:32:58.019147 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 16:32:58.019232 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 16:32:58.021879 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 16:32:58.025532 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1243 16:32:58.029133 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1244 16:32:58.035389 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 16:32:58.038841 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 16:32:58.042317 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 16:32:58.045767 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 16:32:58.052256 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 16:32:58.055772 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 16:32:58.058719 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 16:32:58.065189 0 9 8 | B1->B0 | 3232 2929 | 0 0 | (0 0) (0 0)
1252 16:32:58.068707 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 16:32:58.072182 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 16:32:58.079049 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 16:32:58.082177 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 16:32:58.085126 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 16:32:58.091908 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 16:32:58.095558 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1259 16:32:58.099206 0 10 8 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
1260 16:32:58.105404 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 16:32:58.108977 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 16:32:58.111951 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 16:32:58.119006 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 16:32:58.122564 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 16:32:58.125298 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 16:32:58.132473 0 11 4 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
1267 16:32:58.135385 0 11 8 | B1->B0 | 3a3a 4040 | 0 1 | (1 1) (0 0)
1268 16:32:58.138963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 16:32:58.141896 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 16:32:58.149003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 16:32:58.152536 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 16:32:58.155396 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 16:32:58.161996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 16:32:58.165535 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 16:32:58.168970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 16:32:58.175701 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 16:32:58.178554 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 16:32:58.182070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 16:32:58.188954 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 16:32:58.192000 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 16:32:58.195694 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 16:32:58.202435 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 16:32:58.205293 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 16:32:58.208870 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 16:32:58.215260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 16:32:58.218854 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 16:32:58.222324 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 16:32:58.228607 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 16:32:58.232152 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 16:32:58.235021 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 16:32:58.242257 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1292 16:32:58.242340 Total UI for P1: 0, mck2ui 16
1293 16:32:58.245757 best dqsien dly found for B1: ( 0, 14, 6)
1294 16:32:58.252350 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1295 16:32:58.255198 Total UI for P1: 0, mck2ui 16
1296 16:32:58.258876 best dqsien dly found for B0: ( 0, 14, 8)
1297 16:32:58.261854 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1298 16:32:58.265484 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1299 16:32:58.265585
1300 16:32:58.268624 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1301 16:32:58.272153 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1302 16:32:58.275786 [Gating] SW calibration Done
1303 16:32:58.275885 ==
1304 16:32:58.278703 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 16:32:58.282503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 16:32:58.282573 ==
1307 16:32:58.285520 RX Vref Scan: 0
1308 16:32:58.285594
1309 16:32:58.285653 RX Vref 0 -> 0, step: 1
1310 16:32:58.285707
1311 16:32:58.288438 RX Delay -130 -> 252, step: 16
1312 16:32:58.292074 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1313 16:32:58.299051 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1314 16:32:58.301730 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1315 16:32:58.305336 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1316 16:32:58.309003 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1317 16:32:58.311999 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1318 16:32:58.318531 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1319 16:32:58.322098 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1320 16:32:58.325745 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1321 16:32:58.328775 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1322 16:32:58.332226 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1323 16:32:58.339296 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1324 16:32:58.342071 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1325 16:32:58.345589 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1326 16:32:58.349264 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1327 16:32:58.352173 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1328 16:32:58.355182 ==
1329 16:32:58.358950 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 16:32:58.362511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 16:32:58.362597 ==
1332 16:32:58.362675 DQS Delay:
1333 16:32:58.365408 DQS0 = 0, DQS1 = 0
1334 16:32:58.365530 DQM Delay:
1335 16:32:58.369035 DQM0 = 92, DQM1 = 85
1336 16:32:58.369147 DQ Delay:
1337 16:32:58.371996 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1338 16:32:58.375807 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1339 16:32:58.378790 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1340 16:32:58.382232 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1341 16:32:58.382313
1342 16:32:58.382408
1343 16:32:58.382498 ==
1344 16:32:58.385254 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 16:32:58.388963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 16:32:58.389038 ==
1347 16:32:58.389116
1348 16:32:58.389226
1349 16:32:58.391941 TX Vref Scan disable
1350 16:32:58.395664 == TX Byte 0 ==
1351 16:32:58.398638 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1352 16:32:58.402449 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1353 16:32:58.405357 == TX Byte 1 ==
1354 16:32:58.408843 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1355 16:32:58.412269 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1356 16:32:58.412341 ==
1357 16:32:58.415474 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 16:32:58.419279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 16:32:58.419360 ==
1360 16:32:58.433532 TX Vref=22, minBit 8, minWin=27, winSum=448
1361 16:32:58.437185 TX Vref=24, minBit 1, minWin=28, winSum=453
1362 16:32:58.440010 TX Vref=26, minBit 1, minWin=28, winSum=455
1363 16:32:58.443639 TX Vref=28, minBit 2, minWin=28, winSum=455
1364 16:32:58.446985 TX Vref=30, minBit 8, minWin=27, winSum=455
1365 16:32:58.450517 TX Vref=32, minBit 10, minWin=27, winSum=450
1366 16:32:58.457060 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 26
1367 16:32:58.457155
1368 16:32:58.460805 Final TX Range 1 Vref 26
1369 16:32:58.460924
1370 16:32:58.461012 ==
1371 16:32:58.463786 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 16:32:58.467360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 16:32:58.467445 ==
1374 16:32:58.467506
1375 16:32:58.467562
1376 16:32:58.470216 TX Vref Scan disable
1377 16:32:58.473978 == TX Byte 0 ==
1378 16:32:58.477022 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1379 16:32:58.480719 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1380 16:32:58.483666 == TX Byte 1 ==
1381 16:32:58.487271 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1382 16:32:58.490131 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1383 16:32:58.490208
1384 16:32:58.493828 [DATLAT]
1385 16:32:58.493906 Freq=800, CH0 RK1
1386 16:32:58.493965
1387 16:32:58.496608 DATLAT Default: 0xa
1388 16:32:58.496682 0, 0xFFFF, sum = 0
1389 16:32:58.500279 1, 0xFFFF, sum = 0
1390 16:32:58.500355 2, 0xFFFF, sum = 0
1391 16:32:58.503901 3, 0xFFFF, sum = 0
1392 16:32:58.503996 4, 0xFFFF, sum = 0
1393 16:32:58.506832 5, 0xFFFF, sum = 0
1394 16:32:58.506914 6, 0xFFFF, sum = 0
1395 16:32:58.510564 7, 0xFFFF, sum = 0
1396 16:32:58.510658 8, 0xFFFF, sum = 0
1397 16:32:58.513495 9, 0x0, sum = 1
1398 16:32:58.513607 10, 0x0, sum = 2
1399 16:32:58.517188 11, 0x0, sum = 3
1400 16:32:58.517285 12, 0x0, sum = 4
1401 16:32:58.519994 best_step = 10
1402 16:32:58.520062
1403 16:32:58.520118 ==
1404 16:32:58.523647 Dram Type= 6, Freq= 0, CH_0, rank 1
1405 16:32:58.527102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 16:32:58.527186 ==
1407 16:32:58.530597 RX Vref Scan: 0
1408 16:32:58.530673
1409 16:32:58.530733 RX Vref 0 -> 0, step: 1
1410 16:32:58.530788
1411 16:32:58.533977 RX Delay -79 -> 252, step: 8
1412 16:32:58.540783 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1413 16:32:58.543539 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1414 16:32:58.546900 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1415 16:32:58.550393 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1416 16:32:58.553789 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1417 16:32:58.559956 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1418 16:32:58.563568 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1419 16:32:58.567034 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1420 16:32:58.570616 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1421 16:32:58.573480 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1422 16:32:58.580650 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1423 16:32:58.583442 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1424 16:32:58.587039 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1425 16:32:58.589965 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1426 16:32:58.593542 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1427 16:32:58.600255 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1428 16:32:58.600362 ==
1429 16:32:58.603787 Dram Type= 6, Freq= 0, CH_0, rank 1
1430 16:32:58.606724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 16:32:58.606796 ==
1432 16:32:58.606871 DQS Delay:
1433 16:32:58.610359 DQS0 = 0, DQS1 = 0
1434 16:32:58.610433 DQM Delay:
1435 16:32:58.613815 DQM0 = 92, DQM1 = 82
1436 16:32:58.613889 DQ Delay:
1437 16:32:58.616717 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1438 16:32:58.620378 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1439 16:32:58.623363 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1440 16:32:58.627102 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1441 16:32:58.627181
1442 16:32:58.627241
1443 16:32:58.633806 [DQSOSCAuto] RK1, (LSB)MR18= 0x4818, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1444 16:32:58.636860 CH0 RK1: MR19=606, MR18=4818
1445 16:32:58.643362 CH0_RK1: MR19=0x606, MR18=0x4818, DQSOSC=391, MR23=63, INC=96, DEC=64
1446 16:32:58.646924 [RxdqsGatingPostProcess] freq 800
1447 16:32:58.653500 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1448 16:32:58.653594 Pre-setting of DQS Precalculation
1449 16:32:58.660208 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1450 16:32:58.660292 ==
1451 16:32:58.663580 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 16:32:58.666785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 16:32:58.666908 ==
1454 16:32:58.673489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1455 16:32:58.680335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1456 16:32:58.688405 [CA 0] Center 36 (6~67) winsize 62
1457 16:32:58.691844 [CA 1] Center 36 (6~67) winsize 62
1458 16:32:58.695385 [CA 2] Center 34 (4~65) winsize 62
1459 16:32:58.698319 [CA 3] Center 34 (4~65) winsize 62
1460 16:32:58.701766 [CA 4] Center 34 (4~65) winsize 62
1461 16:32:58.704912 [CA 5] Center 34 (4~64) winsize 61
1462 16:32:58.704992
1463 16:32:58.708734 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1464 16:32:58.708812
1465 16:32:58.711718 [CATrainingPosCal] consider 1 rank data
1466 16:32:58.715519 u2DelayCellTimex100 = 270/100 ps
1467 16:32:58.718539 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1468 16:32:58.721484 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1469 16:32:58.728689 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 16:32:58.731873 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 16:32:58.734787 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 16:32:58.738446 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1473 16:32:58.738529
1474 16:32:58.741415 CA PerBit enable=1, Macro0, CA PI delay=34
1475 16:32:58.741511
1476 16:32:58.744969 [CBTSetCACLKResult] CA Dly = 34
1477 16:32:58.745039 CS Dly: 6 (0~37)
1478 16:32:58.745096 ==
1479 16:32:58.748699 Dram Type= 6, Freq= 0, CH_1, rank 1
1480 16:32:58.754746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1481 16:32:58.754830 ==
1482 16:32:58.758453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1483 16:32:58.764831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1484 16:32:58.774796 [CA 0] Center 37 (6~68) winsize 63
1485 16:32:58.777986 [CA 1] Center 37 (6~68) winsize 63
1486 16:32:58.781258 [CA 2] Center 35 (4~66) winsize 63
1487 16:32:58.784520 [CA 3] Center 34 (4~65) winsize 62
1488 16:32:58.788171 [CA 4] Center 35 (5~65) winsize 61
1489 16:32:58.791418 [CA 5] Center 34 (4~65) winsize 62
1490 16:32:58.791498
1491 16:32:58.794463 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1492 16:32:58.794542
1493 16:32:58.798197 [CATrainingPosCal] consider 2 rank data
1494 16:32:58.801234 u2DelayCellTimex100 = 270/100 ps
1495 16:32:58.804885 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1496 16:32:58.807999 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1497 16:32:58.811275 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 16:32:58.817833 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1499 16:32:58.821182 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1500 16:32:58.824631 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1501 16:32:58.824729
1502 16:32:58.828151 CA PerBit enable=1, Macro0, CA PI delay=34
1503 16:32:58.828231
1504 16:32:58.831215 [CBTSetCACLKResult] CA Dly = 34
1505 16:32:58.831294 CS Dly: 6 (0~38)
1506 16:32:58.831371
1507 16:32:58.834906 ----->DramcWriteLeveling(PI) begin...
1508 16:32:58.834986 ==
1509 16:32:58.837864 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 16:32:58.844576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1511 16:32:58.844675 ==
1512 16:32:58.848196 Write leveling (Byte 0): 28 => 28
1513 16:32:58.851253 Write leveling (Byte 1): 26 => 26
1514 16:32:58.851356 DramcWriteLeveling(PI) end<-----
1515 16:32:58.854859
1516 16:32:58.854947 ==
1517 16:32:58.857779 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 16:32:58.861354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 16:32:58.861451 ==
1520 16:32:58.865070 [Gating] SW mode calibration
1521 16:32:58.871177 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1522 16:32:58.874919 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1523 16:32:58.881385 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1524 16:32:58.884920 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1525 16:32:58.887810 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1526 16:32:58.894837 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:32:58.898246 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:32:58.901669 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:32:58.908035 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 16:32:58.911554 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 16:32:58.915000 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 16:32:58.918419 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 16:32:58.925176 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 16:32:58.927994 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 16:32:58.931548 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 16:32:58.938194 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 16:32:58.941617 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 16:32:58.944979 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 16:32:58.951551 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1540 16:32:58.955311 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1541 16:32:58.958203 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1542 16:32:58.964718 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 16:32:58.968543 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 16:32:58.971501 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 16:32:58.978237 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 16:32:58.981933 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 16:32:58.984765 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 16:32:58.991950 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1549 16:32:58.994823 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1550 16:32:58.998528 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 16:32:59.005046 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 16:32:59.008377 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 16:32:59.011718 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 16:32:59.018454 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 16:32:59.021923 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1556 16:32:59.024661 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
1557 16:32:59.028169 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1558 16:32:59.035178 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 16:32:59.038229 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 16:32:59.041735 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 16:32:59.048165 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 16:32:59.051757 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 16:32:59.055480 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 16:32:59.061600 0 11 4 | B1->B0 | 2525 3333 | 0 0 | (1 1) (0 0)
1565 16:32:59.064887 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1566 16:32:59.068529 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 16:32:59.075645 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 16:32:59.078657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 16:32:59.081525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 16:32:59.088179 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 16:32:59.091813 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 16:32:59.095461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1573 16:32:59.098363 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 16:32:59.104966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 16:32:59.108724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 16:32:59.111632 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 16:32:59.118362 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 16:32:59.121884 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 16:32:59.125317 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 16:32:59.131451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 16:32:59.135245 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 16:32:59.138526 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 16:32:59.145580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 16:32:59.148428 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 16:32:59.151884 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 16:32:59.158584 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 16:32:59.162190 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 16:32:59.165063 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1589 16:32:59.171651 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1590 16:32:59.171764 Total UI for P1: 0, mck2ui 16
1591 16:32:59.175089 best dqsien dly found for B0: ( 0, 14, 4)
1592 16:32:59.178593 Total UI for P1: 0, mck2ui 16
1593 16:32:59.181864 best dqsien dly found for B1: ( 0, 14, 4)
1594 16:32:59.185085 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1595 16:32:59.191681 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1596 16:32:59.191772
1597 16:32:59.195313 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1598 16:32:59.198959 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1599 16:32:59.201918 [Gating] SW calibration Done
1600 16:32:59.201988 ==
1601 16:32:59.205671 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 16:32:59.208691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 16:32:59.208763 ==
1604 16:32:59.208822 RX Vref Scan: 0
1605 16:32:59.208895
1606 16:32:59.212383 RX Vref 0 -> 0, step: 1
1607 16:32:59.212464
1608 16:32:59.215356 RX Delay -130 -> 252, step: 16
1609 16:32:59.218884 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1610 16:32:59.221862 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1611 16:32:59.229101 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1612 16:32:59.232005 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1613 16:32:59.235772 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1614 16:32:59.238761 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1615 16:32:59.241983 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1616 16:32:59.245410 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1617 16:32:59.252305 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1618 16:32:59.255640 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1619 16:32:59.258729 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1620 16:32:59.262436 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1621 16:32:59.265584 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1622 16:32:59.272284 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1623 16:32:59.275858 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1624 16:32:59.278835 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1625 16:32:59.278942 ==
1626 16:32:59.282555 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 16:32:59.285362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 16:32:59.285465 ==
1629 16:32:59.289031 DQS Delay:
1630 16:32:59.289132 DQS0 = 0, DQS1 = 0
1631 16:32:59.292328 DQM Delay:
1632 16:32:59.292401 DQM0 = 94, DQM1 = 91
1633 16:32:59.292461 DQ Delay:
1634 16:32:59.295693 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1635 16:32:59.299048 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1636 16:32:59.302438 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1637 16:32:59.308765 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1638 16:32:59.308847
1639 16:32:59.308906
1640 16:32:59.308961 ==
1641 16:32:59.312689 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 16:32:59.315615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 16:32:59.315709 ==
1644 16:32:59.315793
1645 16:32:59.315875
1646 16:32:59.319242 TX Vref Scan disable
1647 16:32:59.319336 == TX Byte 0 ==
1648 16:32:59.325849 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1649 16:32:59.329486 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1650 16:32:59.329596 == TX Byte 1 ==
1651 16:32:59.336155 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1652 16:32:59.339238 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1653 16:32:59.339332 ==
1654 16:32:59.342197 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 16:32:59.345853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 16:32:59.345924 ==
1657 16:32:59.359619 TX Vref=22, minBit 0, minWin=26, winSum=433
1658 16:32:59.363344 TX Vref=24, minBit 1, minWin=26, winSum=436
1659 16:32:59.366338 TX Vref=26, minBit 2, minWin=27, winSum=447
1660 16:32:59.369738 TX Vref=28, minBit 3, minWin=26, winSum=445
1661 16:32:59.373124 TX Vref=30, minBit 2, minWin=26, winSum=449
1662 16:32:59.376570 TX Vref=32, minBit 1, minWin=27, winSum=445
1663 16:32:59.383324 [TxChooseVref] Worse bit 2, Min win 27, Win sum 447, Final Vref 26
1664 16:32:59.383400
1665 16:32:59.386916 Final TX Range 1 Vref 26
1666 16:32:59.386989
1667 16:32:59.387046 ==
1668 16:32:59.390236 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 16:32:59.393124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 16:32:59.393228 ==
1671 16:32:59.393327
1672 16:32:59.393386
1673 16:32:59.396748 TX Vref Scan disable
1674 16:32:59.400318 == TX Byte 0 ==
1675 16:32:59.403163 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1676 16:32:59.406717 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1677 16:32:59.410241 == TX Byte 1 ==
1678 16:32:59.413681 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1679 16:32:59.417027 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1680 16:32:59.417138
1681 16:32:59.420347 [DATLAT]
1682 16:32:59.420450 Freq=800, CH1 RK0
1683 16:32:59.420537
1684 16:32:59.423292 DATLAT Default: 0xa
1685 16:32:59.423387 0, 0xFFFF, sum = 0
1686 16:32:59.427074 1, 0xFFFF, sum = 0
1687 16:32:59.427178 2, 0xFFFF, sum = 0
1688 16:32:59.430040 3, 0xFFFF, sum = 0
1689 16:32:59.430168 4, 0xFFFF, sum = 0
1690 16:32:59.433690 5, 0xFFFF, sum = 0
1691 16:32:59.433767 6, 0xFFFF, sum = 0
1692 16:32:59.436490 7, 0xFFFF, sum = 0
1693 16:32:59.436603 8, 0xFFFF, sum = 0
1694 16:32:59.440179 9, 0x0, sum = 1
1695 16:32:59.440283 10, 0x0, sum = 2
1696 16:32:59.443183 11, 0x0, sum = 3
1697 16:32:59.443284 12, 0x0, sum = 4
1698 16:32:59.447007 best_step = 10
1699 16:32:59.447083
1700 16:32:59.447144 ==
1701 16:32:59.450065 Dram Type= 6, Freq= 0, CH_1, rank 0
1702 16:32:59.453645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1703 16:32:59.453746 ==
1704 16:32:59.453836 RX Vref Scan: 1
1705 16:32:59.456461
1706 16:32:59.456562 Set Vref Range= 32 -> 127
1707 16:32:59.456675
1708 16:32:59.460184 RX Vref 32 -> 127, step: 1
1709 16:32:59.460288
1710 16:32:59.463179 RX Delay -79 -> 252, step: 8
1711 16:32:59.463286
1712 16:32:59.466772 Set Vref, RX VrefLevel [Byte0]: 32
1713 16:32:59.469851 [Byte1]: 32
1714 16:32:59.469929
1715 16:32:59.473421 Set Vref, RX VrefLevel [Byte0]: 33
1716 16:32:59.477039 [Byte1]: 33
1717 16:32:59.477139
1718 16:32:59.479957 Set Vref, RX VrefLevel [Byte0]: 34
1719 16:32:59.483654 [Byte1]: 34
1720 16:32:59.487527
1721 16:32:59.487606 Set Vref, RX VrefLevel [Byte0]: 35
1722 16:32:59.490432 [Byte1]: 35
1723 16:32:59.494675
1724 16:32:59.494779 Set Vref, RX VrefLevel [Byte0]: 36
1725 16:32:59.498136 [Byte1]: 36
1726 16:32:59.502156
1727 16:32:59.502235 Set Vref, RX VrefLevel [Byte0]: 37
1728 16:32:59.505948 [Byte1]: 37
1729 16:32:59.509808
1730 16:32:59.509887 Set Vref, RX VrefLevel [Byte0]: 38
1731 16:32:59.513077 [Byte1]: 38
1732 16:32:59.517257
1733 16:32:59.517360 Set Vref, RX VrefLevel [Byte0]: 39
1734 16:32:59.520779 [Byte1]: 39
1735 16:32:59.524932
1736 16:32:59.525013 Set Vref, RX VrefLevel [Byte0]: 40
1737 16:32:59.528417 [Byte1]: 40
1738 16:32:59.532409
1739 16:32:59.532488 Set Vref, RX VrefLevel [Byte0]: 41
1740 16:32:59.535757 [Byte1]: 41
1741 16:32:59.540244
1742 16:32:59.540324 Set Vref, RX VrefLevel [Byte0]: 42
1743 16:32:59.543795 [Byte1]: 42
1744 16:32:59.547516
1745 16:32:59.547594 Set Vref, RX VrefLevel [Byte0]: 43
1746 16:32:59.551329 [Byte1]: 43
1747 16:32:59.554936
1748 16:32:59.555007 Set Vref, RX VrefLevel [Byte0]: 44
1749 16:32:59.558597 [Byte1]: 44
1750 16:32:59.562744
1751 16:32:59.562818 Set Vref, RX VrefLevel [Byte0]: 45
1752 16:32:59.566223 [Byte1]: 45
1753 16:32:59.570607
1754 16:32:59.570691 Set Vref, RX VrefLevel [Byte0]: 46
1755 16:32:59.573541 [Byte1]: 46
1756 16:32:59.577838
1757 16:32:59.577919 Set Vref, RX VrefLevel [Byte0]: 47
1758 16:32:59.581445 [Byte1]: 47
1759 16:32:59.585800
1760 16:32:59.585880 Set Vref, RX VrefLevel [Byte0]: 48
1761 16:32:59.588717 [Byte1]: 48
1762 16:32:59.593345
1763 16:32:59.593425 Set Vref, RX VrefLevel [Byte0]: 49
1764 16:32:59.596264 [Byte1]: 49
1765 16:32:59.600627
1766 16:32:59.600706 Set Vref, RX VrefLevel [Byte0]: 50
1767 16:32:59.603529 [Byte1]: 50
1768 16:32:59.607863
1769 16:32:59.607942 Set Vref, RX VrefLevel [Byte0]: 51
1770 16:32:59.611148 [Byte1]: 51
1771 16:32:59.615357
1772 16:32:59.615436 Set Vref, RX VrefLevel [Byte0]: 52
1773 16:32:59.618678 [Byte1]: 52
1774 16:32:59.623384
1775 16:32:59.623493 Set Vref, RX VrefLevel [Byte0]: 53
1776 16:32:59.626628 [Byte1]: 53
1777 16:32:59.630561
1778 16:32:59.630641 Set Vref, RX VrefLevel [Byte0]: 54
1779 16:32:59.634106 [Byte1]: 54
1780 16:32:59.637957
1781 16:32:59.638038 Set Vref, RX VrefLevel [Byte0]: 55
1782 16:32:59.641683 [Byte1]: 55
1783 16:32:59.645814
1784 16:32:59.645892 Set Vref, RX VrefLevel [Byte0]: 56
1785 16:32:59.648986 [Byte1]: 56
1786 16:32:59.653065
1787 16:32:59.653144 Set Vref, RX VrefLevel [Byte0]: 57
1788 16:32:59.656523 [Byte1]: 57
1789 16:32:59.660962
1790 16:32:59.661041 Set Vref, RX VrefLevel [Byte0]: 58
1791 16:32:59.663844 [Byte1]: 58
1792 16:32:59.668133
1793 16:32:59.668213 Set Vref, RX VrefLevel [Byte0]: 59
1794 16:32:59.671633 [Byte1]: 59
1795 16:32:59.675654
1796 16:32:59.675728 Set Vref, RX VrefLevel [Byte0]: 60
1797 16:32:59.679349 [Byte1]: 60
1798 16:32:59.683604
1799 16:32:59.683704 Set Vref, RX VrefLevel [Byte0]: 61
1800 16:32:59.686501 [Byte1]: 61
1801 16:32:59.690913
1802 16:32:59.691009 Set Vref, RX VrefLevel [Byte0]: 62
1803 16:32:59.694524 [Byte1]: 62
1804 16:32:59.698274
1805 16:32:59.698343 Set Vref, RX VrefLevel [Byte0]: 63
1806 16:32:59.702030 [Byte1]: 63
1807 16:32:59.706588
1808 16:32:59.706660 Set Vref, RX VrefLevel [Byte0]: 64
1809 16:32:59.709659 [Byte1]: 64
1810 16:32:59.713443
1811 16:32:59.713557 Set Vref, RX VrefLevel [Byte0]: 65
1812 16:32:59.716970 [Byte1]: 65
1813 16:32:59.721462
1814 16:32:59.721564 Set Vref, RX VrefLevel [Byte0]: 66
1815 16:32:59.724354 [Byte1]: 66
1816 16:32:59.728806
1817 16:32:59.728906 Set Vref, RX VrefLevel [Byte0]: 67
1818 16:32:59.732392 [Byte1]: 67
1819 16:32:59.736457
1820 16:32:59.736555 Set Vref, RX VrefLevel [Byte0]: 68
1821 16:32:59.739211 [Byte1]: 68
1822 16:32:59.743484
1823 16:32:59.743558 Set Vref, RX VrefLevel [Byte0]: 69
1824 16:32:59.747021 [Byte1]: 69
1825 16:32:59.751268
1826 16:32:59.751339 Set Vref, RX VrefLevel [Byte0]: 70
1827 16:32:59.754891 [Byte1]: 70
1828 16:32:59.759100
1829 16:32:59.759197 Set Vref, RX VrefLevel [Byte0]: 71
1830 16:32:59.762559 [Byte1]: 71
1831 16:32:59.766792
1832 16:32:59.766888 Set Vref, RX VrefLevel [Byte0]: 72
1833 16:32:59.769496 [Byte1]: 72
1834 16:32:59.773796
1835 16:32:59.773898 Set Vref, RX VrefLevel [Byte0]: 73
1836 16:32:59.777387 [Byte1]: 73
1837 16:32:59.781536
1838 16:32:59.781615 Set Vref, RX VrefLevel [Byte0]: 74
1839 16:32:59.784927 [Byte1]: 74
1840 16:32:59.789381
1841 16:32:59.789475 Final RX Vref Byte 0 = 57 to rank0
1842 16:32:59.792397 Final RX Vref Byte 1 = 59 to rank0
1843 16:32:59.796076 Final RX Vref Byte 0 = 57 to rank1
1844 16:32:59.798927 Final RX Vref Byte 1 = 59 to rank1==
1845 16:32:59.802623 Dram Type= 6, Freq= 0, CH_1, rank 0
1846 16:32:59.809433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 16:32:59.809558 ==
1848 16:32:59.809651 DQS Delay:
1849 16:32:59.809735 DQS0 = 0, DQS1 = 0
1850 16:32:59.812422 DQM Delay:
1851 16:32:59.812501 DQM0 = 95, DQM1 = 89
1852 16:32:59.816028 DQ Delay:
1853 16:32:59.818972 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1854 16:32:59.822727 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1855 16:32:59.825586 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1856 16:32:59.829362 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1857 16:32:59.829460
1858 16:32:59.829555
1859 16:32:59.835818 [DQSOSCAuto] RK0, (LSB)MR18= 0x314d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1860 16:32:59.838697 CH1 RK0: MR19=606, MR18=314D
1861 16:32:59.845994 CH1_RK0: MR19=0x606, MR18=0x314D, DQSOSC=390, MR23=63, INC=97, DEC=64
1862 16:32:59.846073
1863 16:32:59.848892 ----->DramcWriteLeveling(PI) begin...
1864 16:32:59.848983 ==
1865 16:32:59.852534 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 16:32:59.855512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 16:32:59.855609 ==
1868 16:32:59.858913 Write leveling (Byte 0): 28 => 28
1869 16:32:59.862312 Write leveling (Byte 1): 30 => 30
1870 16:32:59.865718 DramcWriteLeveling(PI) end<-----
1871 16:32:59.865792
1872 16:32:59.865854 ==
1873 16:32:59.869097 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 16:32:59.872587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 16:32:59.872686 ==
1876 16:32:59.876123 [Gating] SW mode calibration
1877 16:32:59.882421 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1878 16:32:59.889206 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1879 16:32:59.892700 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1880 16:32:59.896137 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1881 16:32:59.902975 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:32:59.905891 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:32:59.909460 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:32:59.916203 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:32:59.919079 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:32:59.922827 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:32:59.926422 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 16:32:59.932924 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 16:32:59.936490 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 16:32:59.939547 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 16:32:59.946082 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 16:32:59.949688 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 16:32:59.952991 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 16:32:59.959571 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 16:32:59.962581 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 16:32:59.966208 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1897 16:32:59.972702 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 16:32:59.976020 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 16:32:59.979346 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 16:32:59.986523 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 16:32:59.989333 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 16:32:59.992891 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 16:32:59.999210 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 16:33:00.002431 0 9 4 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
1905 16:33:00.007464 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 16:33:00.012972 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 16:33:00.016169 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 16:33:00.019625 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 16:33:00.026169 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 16:33:00.029083 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 16:33:00.032646 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
1912 16:33:00.039428 0 10 4 | B1->B0 | 2525 3030 | 0 1 | (1 0) (1 0)
1913 16:33:00.042383 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 16:33:00.046032 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 16:33:00.048958 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 16:33:00.056205 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 16:33:00.059121 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 16:33:00.062597 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 16:33:00.069130 0 11 0 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
1920 16:33:00.072787 0 11 4 | B1->B0 | 4040 2e2e | 0 0 | (0 0) (0 0)
1921 16:33:00.075807 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1922 16:33:00.083152 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 16:33:00.085889 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 16:33:00.089045 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 16:33:00.096013 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 16:33:00.099635 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 16:33:00.102701 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 16:33:00.109272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1929 16:33:00.112727 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1930 16:33:00.116082 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 16:33:00.122828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 16:33:00.126347 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 16:33:00.129275 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 16:33:00.132498 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 16:33:00.139454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 16:33:00.143000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 16:33:00.146099 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 16:33:00.152806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 16:33:00.156383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 16:33:00.159362 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 16:33:00.166341 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 16:33:00.169153 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 16:33:00.172796 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 16:33:00.179461 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1945 16:33:00.179535 Total UI for P1: 0, mck2ui 16
1946 16:33:00.186027 best dqsien dly found for B0: ( 0, 14, 2)
1947 16:33:00.189646 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 16:33:00.192608 Total UI for P1: 0, mck2ui 16
1949 16:33:00.196204 best dqsien dly found for B1: ( 0, 14, 4)
1950 16:33:00.199343 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1951 16:33:00.202678 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1952 16:33:00.202776
1953 16:33:00.205956 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1954 16:33:00.209683 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1955 16:33:00.212644 [Gating] SW calibration Done
1956 16:33:00.212719 ==
1957 16:33:00.216346 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 16:33:00.219248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 16:33:00.219321 ==
1960 16:33:00.222770 RX Vref Scan: 0
1961 16:33:00.222841
1962 16:33:00.226617 RX Vref 0 -> 0, step: 1
1963 16:33:00.226689
1964 16:33:00.226745 RX Delay -130 -> 252, step: 16
1965 16:33:00.232620 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1966 16:33:00.236229 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1967 16:33:00.239733 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1968 16:33:00.243031 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1969 16:33:00.246355 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1970 16:33:00.253003 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1971 16:33:00.256372 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1972 16:33:00.259497 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1973 16:33:00.263358 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1974 16:33:00.266464 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1975 16:33:00.269829 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1976 16:33:00.276228 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1977 16:33:00.279784 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1978 16:33:00.283450 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1979 16:33:00.286411 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1980 16:33:00.290324 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1981 16:33:00.293208 ==
1982 16:33:00.296203 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 16:33:00.299901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 16:33:00.299998 ==
1985 16:33:00.300086 DQS Delay:
1986 16:33:00.303518 DQS0 = 0, DQS1 = 0
1987 16:33:00.303615 DQM Delay:
1988 16:33:00.306347 DQM0 = 92, DQM1 = 89
1989 16:33:00.306419 DQ Delay:
1990 16:33:00.309719 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1991 16:33:00.313101 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1992 16:33:00.316426 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1993 16:33:00.319660 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1994 16:33:00.319753
1995 16:33:00.319840
1996 16:33:00.319918 ==
1997 16:33:00.323327 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 16:33:00.326333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 16:33:00.326412 ==
2000 16:33:00.326498
2001 16:33:00.326579
2002 16:33:00.329866 TX Vref Scan disable
2003 16:33:00.333567 == TX Byte 0 ==
2004 16:33:00.336608 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2005 16:33:00.339578 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2006 16:33:00.343207 == TX Byte 1 ==
2007 16:33:00.346243 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2008 16:33:00.349679 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2009 16:33:00.349751 ==
2010 16:33:00.352786 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 16:33:00.359810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 16:33:00.359892 ==
2013 16:33:00.371352 TX Vref=22, minBit 0, minWin=27, winSum=439
2014 16:33:00.374717 TX Vref=24, minBit 0, minWin=27, winSum=446
2015 16:33:00.378050 TX Vref=26, minBit 2, minWin=27, winSum=450
2016 16:33:00.381301 TX Vref=28, minBit 2, minWin=27, winSum=451
2017 16:33:00.384516 TX Vref=30, minBit 2, minWin=27, winSum=450
2018 16:33:00.388070 TX Vref=32, minBit 2, minWin=27, winSum=449
2019 16:33:00.394710 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
2020 16:33:00.394794
2021 16:33:00.398276 Final TX Range 1 Vref 28
2022 16:33:00.398348
2023 16:33:00.398408 ==
2024 16:33:00.401221 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 16:33:00.404908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 16:33:00.404989 ==
2027 16:33:00.405051
2028 16:33:00.405107
2029 16:33:00.408517 TX Vref Scan disable
2030 16:33:00.411440 == TX Byte 0 ==
2031 16:33:00.415142 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2032 16:33:00.418122 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2033 16:33:00.421644 == TX Byte 1 ==
2034 16:33:00.425079 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2035 16:33:00.428405 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2036 16:33:00.428486
2037 16:33:00.431723 [DATLAT]
2038 16:33:00.431801 Freq=800, CH1 RK1
2039 16:33:00.431863
2040 16:33:00.435147 DATLAT Default: 0xa
2041 16:33:00.435226 0, 0xFFFF, sum = 0
2042 16:33:00.438483 1, 0xFFFF, sum = 0
2043 16:33:00.438590 2, 0xFFFF, sum = 0
2044 16:33:00.442046 3, 0xFFFF, sum = 0
2045 16:33:00.442154 4, 0xFFFF, sum = 0
2046 16:33:00.444969 5, 0xFFFF, sum = 0
2047 16:33:00.445070 6, 0xFFFF, sum = 0
2048 16:33:00.448055 7, 0xFFFF, sum = 0
2049 16:33:00.448129 8, 0xFFFF, sum = 0
2050 16:33:00.451755 9, 0x0, sum = 1
2051 16:33:00.451834 10, 0x0, sum = 2
2052 16:33:00.455470 11, 0x0, sum = 3
2053 16:33:00.455551 12, 0x0, sum = 4
2054 16:33:00.458508 best_step = 10
2055 16:33:00.458587
2056 16:33:00.458648 ==
2057 16:33:00.462010 Dram Type= 6, Freq= 0, CH_1, rank 1
2058 16:33:00.465014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2059 16:33:00.465122 ==
2060 16:33:00.468692 RX Vref Scan: 0
2061 16:33:00.468764
2062 16:33:00.468827 RX Vref 0 -> 0, step: 1
2063 16:33:00.468884
2064 16:33:00.471537 RX Delay -63 -> 252, step: 8
2065 16:33:00.475369 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2066 16:33:00.482010 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2067 16:33:00.484925 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2068 16:33:00.488645 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2069 16:33:00.492066 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2070 16:33:00.495547 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2071 16:33:00.498881 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2072 16:33:00.505233 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2073 16:33:00.508577 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2074 16:33:00.511584 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2075 16:33:00.514912 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2076 16:33:00.518568 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2077 16:33:00.525244 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2078 16:33:00.528909 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2079 16:33:00.531877 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2080 16:33:00.535287 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2081 16:33:00.535366 ==
2082 16:33:00.538687 Dram Type= 6, Freq= 0, CH_1, rank 1
2083 16:33:00.541634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2084 16:33:00.544989 ==
2085 16:33:00.545068 DQS Delay:
2086 16:33:00.545128 DQS0 = 0, DQS1 = 0
2087 16:33:00.548687 DQM Delay:
2088 16:33:00.548765 DQM0 = 97, DQM1 = 91
2089 16:33:00.552222 DQ Delay:
2090 16:33:00.552300 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2091 16:33:00.555134 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2092 16:33:00.558720 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2093 16:33:00.561706 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2094 16:33:00.565306
2095 16:33:00.565384
2096 16:33:00.571863 [DQSOSCAuto] RK1, (LSB)MR18= 0x4710, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2097 16:33:00.574911 CH1 RK1: MR19=606, MR18=4710
2098 16:33:00.581599 CH1_RK1: MR19=0x606, MR18=0x4710, DQSOSC=392, MR23=63, INC=96, DEC=64
2099 16:33:00.585364 [RxdqsGatingPostProcess] freq 800
2100 16:33:00.588240 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2101 16:33:00.591950 Pre-setting of DQS Precalculation
2102 16:33:00.598670 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2103 16:33:00.605372 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2104 16:33:00.611825 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2105 16:33:00.611920
2106 16:33:00.611980
2107 16:33:00.615427 [Calibration Summary] 1600 Mbps
2108 16:33:00.615507 CH 0, Rank 0
2109 16:33:00.618364 SW Impedance : PASS
2110 16:33:00.621931 DUTY Scan : NO K
2111 16:33:00.622010 ZQ Calibration : PASS
2112 16:33:00.624948 Jitter Meter : NO K
2113 16:33:00.625043 CBT Training : PASS
2114 16:33:00.628347 Write leveling : PASS
2115 16:33:00.631662 RX DQS gating : PASS
2116 16:33:00.631740 RX DQ/DQS(RDDQC) : PASS
2117 16:33:00.634993 TX DQ/DQS : PASS
2118 16:33:00.638311 RX DATLAT : PASS
2119 16:33:00.638390 RX DQ/DQS(Engine): PASS
2120 16:33:00.641738 TX OE : NO K
2121 16:33:00.641816 All Pass.
2122 16:33:00.641876
2123 16:33:00.645072 CH 0, Rank 1
2124 16:33:00.645151 SW Impedance : PASS
2125 16:33:00.648493 DUTY Scan : NO K
2126 16:33:00.652268 ZQ Calibration : PASS
2127 16:33:00.652347 Jitter Meter : NO K
2128 16:33:00.655114 CBT Training : PASS
2129 16:33:00.658581 Write leveling : PASS
2130 16:33:00.658660 RX DQS gating : PASS
2131 16:33:00.661981 RX DQ/DQS(RDDQC) : PASS
2132 16:33:00.665395 TX DQ/DQS : PASS
2133 16:33:00.665502 RX DATLAT : PASS
2134 16:33:00.668769 RX DQ/DQS(Engine): PASS
2135 16:33:00.668846 TX OE : NO K
2136 16:33:00.672266 All Pass.
2137 16:33:00.672367
2138 16:33:00.672455 CH 1, Rank 0
2139 16:33:00.675143 SW Impedance : PASS
2140 16:33:00.675221 DUTY Scan : NO K
2141 16:33:00.678209 ZQ Calibration : PASS
2142 16:33:00.681980 Jitter Meter : NO K
2143 16:33:00.682071 CBT Training : PASS
2144 16:33:00.684934 Write leveling : PASS
2145 16:33:00.688549 RX DQS gating : PASS
2146 16:33:00.688656 RX DQ/DQS(RDDQC) : PASS
2147 16:33:00.691570 TX DQ/DQS : PASS
2148 16:33:00.695278 RX DATLAT : PASS
2149 16:33:00.695354 RX DQ/DQS(Engine): PASS
2150 16:33:00.698781 TX OE : NO K
2151 16:33:00.698859 All Pass.
2152 16:33:00.698917
2153 16:33:00.701781 CH 1, Rank 1
2154 16:33:00.701874 SW Impedance : PASS
2155 16:33:00.705491 DUTY Scan : NO K
2156 16:33:00.708282 ZQ Calibration : PASS
2157 16:33:00.708359 Jitter Meter : NO K
2158 16:33:00.711797 CBT Training : PASS
2159 16:33:00.711878 Write leveling : PASS
2160 16:33:00.715490 RX DQS gating : PASS
2161 16:33:00.718555 RX DQ/DQS(RDDQC) : PASS
2162 16:33:00.718633 TX DQ/DQS : PASS
2163 16:33:00.722120 RX DATLAT : PASS
2164 16:33:00.725020 RX DQ/DQS(Engine): PASS
2165 16:33:00.725106 TX OE : NO K
2166 16:33:00.728641 All Pass.
2167 16:33:00.728708
2168 16:33:00.728765 DramC Write-DBI off
2169 16:33:00.732235 PER_BANK_REFRESH: Hybrid Mode
2170 16:33:00.732325 TX_TRACKING: ON
2171 16:33:00.735154 [GetDramInforAfterCalByMRR] Vendor 6.
2172 16:33:00.742290 [GetDramInforAfterCalByMRR] Revision 606.
2173 16:33:00.745084 [GetDramInforAfterCalByMRR] Revision 2 0.
2174 16:33:00.745156 MR0 0x3b3b
2175 16:33:00.745217 MR8 0x5151
2176 16:33:00.748602 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 16:33:00.748689
2178 16:33:00.752142 MR0 0x3b3b
2179 16:33:00.752224 MR8 0x5151
2180 16:33:00.755081 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2181 16:33:00.755149
2182 16:33:00.765186 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2183 16:33:00.768580 [FAST_K] Save calibration result to emmc
2184 16:33:00.771881 [FAST_K] Save calibration result to emmc
2185 16:33:00.775203 dram_init: config_dvfs: 1
2186 16:33:00.778657 dramc_set_vcore_voltage set vcore to 662500
2187 16:33:00.781839 Read voltage for 1200, 2
2188 16:33:00.781911 Vio18 = 0
2189 16:33:00.781972 Vcore = 662500
2190 16:33:00.784978 Vdram = 0
2191 16:33:00.785048 Vddq = 0
2192 16:33:00.785104 Vmddr = 0
2193 16:33:00.791643 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2194 16:33:00.795310 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2195 16:33:00.798894 MEM_TYPE=3, freq_sel=15
2196 16:33:00.801930 sv_algorithm_assistance_LP4_1600
2197 16:33:00.805697 ============ PULL DRAM RESETB DOWN ============
2198 16:33:00.808739 ========== PULL DRAM RESETB DOWN end =========
2199 16:33:00.815177 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2200 16:33:00.818792 ===================================
2201 16:33:00.818867 LPDDR4 DRAM CONFIGURATION
2202 16:33:00.821809 ===================================
2203 16:33:00.825450 EX_ROW_EN[0] = 0x0
2204 16:33:00.828421 EX_ROW_EN[1] = 0x0
2205 16:33:00.828518 LP4Y_EN = 0x0
2206 16:33:00.832206 WORK_FSP = 0x0
2207 16:33:00.832280 WL = 0x4
2208 16:33:00.835102 RL = 0x4
2209 16:33:00.835172 BL = 0x2
2210 16:33:00.838846 RPST = 0x0
2211 16:33:00.838916 RD_PRE = 0x0
2212 16:33:00.841823 WR_PRE = 0x1
2213 16:33:00.841893 WR_PST = 0x0
2214 16:33:00.845575 DBI_WR = 0x0
2215 16:33:00.845664 DBI_RD = 0x0
2216 16:33:00.848647 OTF = 0x1
2217 16:33:00.852106 ===================================
2218 16:33:00.855004 ===================================
2219 16:33:00.855082 ANA top config
2220 16:33:00.858476 ===================================
2221 16:33:00.862118 DLL_ASYNC_EN = 0
2222 16:33:00.865107 ALL_SLAVE_EN = 0
2223 16:33:00.868569 NEW_RANK_MODE = 1
2224 16:33:00.868732 DLL_IDLE_MODE = 1
2225 16:33:00.872087 LP45_APHY_COMB_EN = 1
2226 16:33:00.874788 TX_ODT_DIS = 1
2227 16:33:00.878527 NEW_8X_MODE = 1
2228 16:33:00.881916 ===================================
2229 16:33:00.884828 ===================================
2230 16:33:00.884923 data_rate = 2400
2231 16:33:00.888499 CKR = 1
2232 16:33:00.891990 DQ_P2S_RATIO = 8
2233 16:33:00.895431 ===================================
2234 16:33:00.898127 CA_P2S_RATIO = 8
2235 16:33:00.901710 DQ_CA_OPEN = 0
2236 16:33:00.904827 DQ_SEMI_OPEN = 0
2237 16:33:00.904930 CA_SEMI_OPEN = 0
2238 16:33:00.908104 CA_FULL_RATE = 0
2239 16:33:00.911516 DQ_CKDIV4_EN = 0
2240 16:33:00.915167 CA_CKDIV4_EN = 0
2241 16:33:00.918055 CA_PREDIV_EN = 0
2242 16:33:00.921522 PH8_DLY = 17
2243 16:33:00.921623 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2244 16:33:00.925349 DQ_AAMCK_DIV = 4
2245 16:33:00.928327 CA_AAMCK_DIV = 4
2246 16:33:00.932002 CA_ADMCK_DIV = 4
2247 16:33:00.934813 DQ_TRACK_CA_EN = 0
2248 16:33:00.938570 CA_PICK = 1200
2249 16:33:00.941454 CA_MCKIO = 1200
2250 16:33:00.941544 MCKIO_SEMI = 0
2251 16:33:00.945084 PLL_FREQ = 2366
2252 16:33:00.948629 DQ_UI_PI_RATIO = 32
2253 16:33:00.952353 CA_UI_PI_RATIO = 0
2254 16:33:00.955438 ===================================
2255 16:33:00.958971 ===================================
2256 16:33:00.961741 memory_type:LPDDR4
2257 16:33:00.961820 GP_NUM : 10
2258 16:33:00.965330 SRAM_EN : 1
2259 16:33:00.965408 MD32_EN : 0
2260 16:33:00.968370 ===================================
2261 16:33:00.971961 [ANA_INIT] >>>>>>>>>>>>>>
2262 16:33:00.975586 <<<<<< [CONFIGURE PHASE]: ANA_TX
2263 16:33:00.978444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2264 16:33:00.981965 ===================================
2265 16:33:00.985544 data_rate = 2400,PCW = 0X5b00
2266 16:33:00.988437 ===================================
2267 16:33:00.992086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2268 16:33:00.995047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 16:33:01.002333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 16:33:01.005306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2271 16:33:01.012364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2272 16:33:01.015206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2273 16:33:01.015288 [ANA_INIT] flow start
2274 16:33:01.018653 [ANA_INIT] PLL >>>>>>>>
2275 16:33:01.022158 [ANA_INIT] PLL <<<<<<<<
2276 16:33:01.022227 [ANA_INIT] MIDPI >>>>>>>>
2277 16:33:01.025378 [ANA_INIT] MIDPI <<<<<<<<
2278 16:33:01.028443 [ANA_INIT] DLL >>>>>>>>
2279 16:33:01.028510 [ANA_INIT] DLL <<<<<<<<
2280 16:33:01.031813 [ANA_INIT] flow end
2281 16:33:01.035254 ============ LP4 DIFF to SE enter ============
2282 16:33:01.038871 ============ LP4 DIFF to SE exit ============
2283 16:33:01.041832 [ANA_INIT] <<<<<<<<<<<<<
2284 16:33:01.045495 [Flow] Enable top DCM control >>>>>
2285 16:33:01.048417 [Flow] Enable top DCM control <<<<<
2286 16:33:01.052104 Enable DLL master slave shuffle
2287 16:33:01.058871 ==============================================================
2288 16:33:01.058973 Gating Mode config
2289 16:33:01.065426 ==============================================================
2290 16:33:01.065527 Config description:
2291 16:33:01.075580 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2292 16:33:01.081828 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2293 16:33:01.088499 SELPH_MODE 0: By rank 1: By Phase
2294 16:33:01.092172 ==============================================================
2295 16:33:01.095720 GAT_TRACK_EN = 1
2296 16:33:01.098518 RX_GATING_MODE = 2
2297 16:33:01.102257 RX_GATING_TRACK_MODE = 2
2298 16:33:01.105796 SELPH_MODE = 1
2299 16:33:01.108784 PICG_EARLY_EN = 1
2300 16:33:01.112410 VALID_LAT_VALUE = 1
2301 16:33:01.115904 ==============================================================
2302 16:33:01.118846 Enter into Gating configuration >>>>
2303 16:33:01.122468 Exit from Gating configuration <<<<
2304 16:33:01.125458 Enter into DVFS_PRE_config >>>>>
2305 16:33:01.139024 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2306 16:33:01.139141 Exit from DVFS_PRE_config <<<<<
2307 16:33:01.142330 Enter into PICG configuration >>>>
2308 16:33:01.145684 Exit from PICG configuration <<<<
2309 16:33:01.148840 [RX_INPUT] configuration >>>>>
2310 16:33:01.152571 [RX_INPUT] configuration <<<<<
2311 16:33:01.159104 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2312 16:33:01.162103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2313 16:33:01.169402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 16:33:01.175941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 16:33:01.182351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 16:33:01.188726 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 16:33:01.192327 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2318 16:33:01.195666 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2319 16:33:01.199219 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2320 16:33:01.205533 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2321 16:33:01.208737 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2322 16:33:01.212362 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 16:33:01.215510 ===================================
2324 16:33:01.219062 LPDDR4 DRAM CONFIGURATION
2325 16:33:01.222711 ===================================
2326 16:33:01.222783 EX_ROW_EN[0] = 0x0
2327 16:33:01.225610 EX_ROW_EN[1] = 0x0
2328 16:33:01.225675 LP4Y_EN = 0x0
2329 16:33:01.229359 WORK_FSP = 0x0
2330 16:33:01.229422 WL = 0x4
2331 16:33:01.232197 RL = 0x4
2332 16:33:01.235797 BL = 0x2
2333 16:33:01.235863 RPST = 0x0
2334 16:33:01.239523 RD_PRE = 0x0
2335 16:33:01.239590 WR_PRE = 0x1
2336 16:33:01.242431 WR_PST = 0x0
2337 16:33:01.242497 DBI_WR = 0x0
2338 16:33:01.245463 DBI_RD = 0x0
2339 16:33:01.245531 OTF = 0x1
2340 16:33:01.249062 ===================================
2341 16:33:01.252056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2342 16:33:01.259319 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2343 16:33:01.262031 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2344 16:33:01.265326 ===================================
2345 16:33:01.269185 LPDDR4 DRAM CONFIGURATION
2346 16:33:01.272578 ===================================
2347 16:33:01.272657 EX_ROW_EN[0] = 0x10
2348 16:33:01.275900 EX_ROW_EN[1] = 0x0
2349 16:33:01.275968 LP4Y_EN = 0x0
2350 16:33:01.279050 WORK_FSP = 0x0
2351 16:33:01.279116 WL = 0x4
2352 16:33:01.282245 RL = 0x4
2353 16:33:01.282316 BL = 0x2
2354 16:33:01.285613 RPST = 0x0
2355 16:33:01.285685 RD_PRE = 0x0
2356 16:33:01.289216 WR_PRE = 0x1
2357 16:33:01.289283 WR_PST = 0x0
2358 16:33:01.292687 DBI_WR = 0x0
2359 16:33:01.292755 DBI_RD = 0x0
2360 16:33:01.295511 OTF = 0x1
2361 16:33:01.299013 ===================================
2362 16:33:01.306009 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2363 16:33:01.306087 ==
2364 16:33:01.308743 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 16:33:01.312396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 16:33:01.312470 ==
2367 16:33:01.315881 [Duty_Offset_Calibration]
2368 16:33:01.315953 B0:2 B1:1 CA:1
2369 16:33:01.316009
2370 16:33:01.318804 [DutyScan_Calibration_Flow] k_type=0
2371 16:33:01.330176
2372 16:33:01.330257 ==CLK 0==
2373 16:33:01.333040 Final CLK duty delay cell = 0
2374 16:33:01.336751 [0] MAX Duty = 5218%(X100), DQS PI = 24
2375 16:33:01.339812 [0] MIN Duty = 4844%(X100), DQS PI = 48
2376 16:33:01.339880 [0] AVG Duty = 5031%(X100)
2377 16:33:01.342805
2378 16:33:01.346503 CH0 CLK Duty spec in!! Max-Min= 374%
2379 16:33:01.350172 [DutyScan_Calibration_Flow] ====Done====
2380 16:33:01.350253
2381 16:33:01.353147 [DutyScan_Calibration_Flow] k_type=1
2382 16:33:01.367956
2383 16:33:01.368036 ==DQS 0 ==
2384 16:33:01.371583 Final DQS duty delay cell = -4
2385 16:33:01.375070 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2386 16:33:01.378625 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2387 16:33:01.381605 [-4] AVG Duty = 4937%(X100)
2388 16:33:01.381682
2389 16:33:01.381742 ==DQS 1 ==
2390 16:33:01.385019 Final DQS duty delay cell = 0
2391 16:33:01.388554 [0] MAX Duty = 5156%(X100), DQS PI = 0
2392 16:33:01.391460 [0] MIN Duty = 5000%(X100), DQS PI = 32
2393 16:33:01.394841 [0] AVG Duty = 5078%(X100)
2394 16:33:01.394924
2395 16:33:01.398055 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2396 16:33:01.398148
2397 16:33:01.401371 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2398 16:33:01.404948 [DutyScan_Calibration_Flow] ====Done====
2399 16:33:01.405016
2400 16:33:01.408367 [DutyScan_Calibration_Flow] k_type=3
2401 16:33:01.425329
2402 16:33:01.425442 ==DQM 0 ==
2403 16:33:01.428681 Final DQM duty delay cell = 0
2404 16:33:01.432056 [0] MAX Duty = 5156%(X100), DQS PI = 30
2405 16:33:01.434812 [0] MIN Duty = 4906%(X100), DQS PI = 52
2406 16:33:01.438337 [0] AVG Duty = 5031%(X100)
2407 16:33:01.438438
2408 16:33:01.438525 ==DQM 1 ==
2409 16:33:01.442022 Final DQM duty delay cell = 0
2410 16:33:01.444874 [0] MAX Duty = 5093%(X100), DQS PI = 0
2411 16:33:01.448439 [0] MIN Duty = 5031%(X100), DQS PI = 14
2412 16:33:01.448516 [0] AVG Duty = 5062%(X100)
2413 16:33:01.452157
2414 16:33:01.455179 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2415 16:33:01.455267
2416 16:33:01.458744 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2417 16:33:01.461503 [DutyScan_Calibration_Flow] ====Done====
2418 16:33:01.461585
2419 16:33:01.465205 [DutyScan_Calibration_Flow] k_type=2
2420 16:33:01.481545
2421 16:33:01.481647 ==DQ 0 ==
2422 16:33:01.485082 Final DQ duty delay cell = 0
2423 16:33:01.488086 [0] MAX Duty = 5031%(X100), DQS PI = 26
2424 16:33:01.491700 [0] MIN Duty = 4844%(X100), DQS PI = 62
2425 16:33:01.491795 [0] AVG Duty = 4937%(X100)
2426 16:33:01.491879
2427 16:33:01.494854 ==DQ 1 ==
2428 16:33:01.497870 Final DQ duty delay cell = 0
2429 16:33:01.501563 [0] MAX Duty = 5093%(X100), DQS PI = 24
2430 16:33:01.505287 [0] MIN Duty = 4938%(X100), DQS PI = 36
2431 16:33:01.505361 [0] AVG Duty = 5015%(X100)
2432 16:33:01.505419
2433 16:33:01.507997 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2434 16:33:01.508097
2435 16:33:01.511435 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2436 16:33:01.518544 [DutyScan_Calibration_Flow] ====Done====
2437 16:33:01.518636 ==
2438 16:33:01.521402 Dram Type= 6, Freq= 0, CH_1, rank 0
2439 16:33:01.524902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 16:33:01.524982 ==
2441 16:33:01.528447 [Duty_Offset_Calibration]
2442 16:33:01.528533 B0:1 B1:0 CA:0
2443 16:33:01.528619
2444 16:33:01.531766 [DutyScan_Calibration_Flow] k_type=0
2445 16:33:01.540902
2446 16:33:01.540985 ==CLK 0==
2447 16:33:01.543970 Final CLK duty delay cell = -4
2448 16:33:01.547621 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2449 16:33:01.550559 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2450 16:33:01.554094 [-4] AVG Duty = 4953%(X100)
2451 16:33:01.554166
2452 16:33:01.557203 CH1 CLK Duty spec in!! Max-Min= 93%
2453 16:33:01.561009 [DutyScan_Calibration_Flow] ====Done====
2454 16:33:01.561082
2455 16:33:01.563745 [DutyScan_Calibration_Flow] k_type=1
2456 16:33:01.580613
2457 16:33:01.580703 ==DQS 0 ==
2458 16:33:01.583631 Final DQS duty delay cell = 0
2459 16:33:01.587105 [0] MAX Duty = 5062%(X100), DQS PI = 24
2460 16:33:01.590701 [0] MIN Duty = 4844%(X100), DQS PI = 0
2461 16:33:01.590773 [0] AVG Duty = 4953%(X100)
2462 16:33:01.593685
2463 16:33:01.593756 ==DQS 1 ==
2464 16:33:01.597338 Final DQS duty delay cell = 0
2465 16:33:01.600286 [0] MAX Duty = 5187%(X100), DQS PI = 18
2466 16:33:01.603955 [0] MIN Duty = 4969%(X100), DQS PI = 10
2467 16:33:01.604028 [0] AVG Duty = 5078%(X100)
2468 16:33:01.606868
2469 16:33:01.610458 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2470 16:33:01.610528
2471 16:33:01.613503 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2472 16:33:01.617236 [DutyScan_Calibration_Flow] ====Done====
2473 16:33:01.617334
2474 16:33:01.620039 [DutyScan_Calibration_Flow] k_type=3
2475 16:33:01.636856
2476 16:33:01.636961 ==DQM 0 ==
2477 16:33:01.640459 Final DQM duty delay cell = 0
2478 16:33:01.643970 [0] MAX Duty = 5156%(X100), DQS PI = 8
2479 16:33:01.646734 [0] MIN Duty = 5000%(X100), DQS PI = 62
2480 16:33:01.646813 [0] AVG Duty = 5078%(X100)
2481 16:33:01.650485
2482 16:33:01.650567 ==DQM 1 ==
2483 16:33:01.653417 Final DQM duty delay cell = 0
2484 16:33:01.656976 [0] MAX Duty = 5031%(X100), DQS PI = 16
2485 16:33:01.660404 [0] MIN Duty = 4875%(X100), DQS PI = 36
2486 16:33:01.660503 [0] AVG Duty = 4953%(X100)
2487 16:33:01.663726
2488 16:33:01.666977 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2489 16:33:01.667050
2490 16:33:01.670303 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2491 16:33:01.673830 [DutyScan_Calibration_Flow] ====Done====
2492 16:33:01.673900
2493 16:33:01.676921 [DutyScan_Calibration_Flow] k_type=2
2494 16:33:01.692519
2495 16:33:01.692612 ==DQ 0 ==
2496 16:33:01.695956 Final DQ duty delay cell = -4
2497 16:33:01.699405 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2498 16:33:01.702375 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2499 16:33:01.706005 [-4] AVG Duty = 4984%(X100)
2500 16:33:01.706098
2501 16:33:01.706185 ==DQ 1 ==
2502 16:33:01.709055 Final DQ duty delay cell = 0
2503 16:33:01.712699 [0] MAX Duty = 5125%(X100), DQS PI = 20
2504 16:33:01.716283 [0] MIN Duty = 4969%(X100), DQS PI = 32
2505 16:33:01.716352 [0] AVG Duty = 5047%(X100)
2506 16:33:01.719461
2507 16:33:01.722423 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2508 16:33:01.722527
2509 16:33:01.726059 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2510 16:33:01.729665 [DutyScan_Calibration_Flow] ====Done====
2511 16:33:01.732553 nWR fixed to 30
2512 16:33:01.732624 [ModeRegInit_LP4] CH0 RK0
2513 16:33:01.736179 [ModeRegInit_LP4] CH0 RK1
2514 16:33:01.739803 [ModeRegInit_LP4] CH1 RK0
2515 16:33:01.742745 [ModeRegInit_LP4] CH1 RK1
2516 16:33:01.742813 match AC timing 7
2517 16:33:01.746476 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2518 16:33:01.749415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2519 16:33:01.756535 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2520 16:33:01.759431 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2521 16:33:01.766053 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2522 16:33:01.766129 ==
2523 16:33:01.769631 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 16:33:01.773081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 16:33:01.773190 ==
2526 16:33:01.779716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 16:33:01.782703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2528 16:33:01.793345 [CA 0] Center 38 (8~69) winsize 62
2529 16:33:01.796044 [CA 1] Center 39 (8~70) winsize 63
2530 16:33:01.799287 [CA 2] Center 35 (4~66) winsize 63
2531 16:33:01.802588 [CA 3] Center 34 (4~65) winsize 62
2532 16:33:01.806703 [CA 4] Center 33 (3~64) winsize 62
2533 16:33:01.809840 [CA 5] Center 32 (3~62) winsize 60
2534 16:33:01.809938
2535 16:33:01.813207 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2536 16:33:01.813285
2537 16:33:01.816632 [CATrainingPosCal] consider 1 rank data
2538 16:33:01.819668 u2DelayCellTimex100 = 270/100 ps
2539 16:33:01.823405 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2540 16:33:01.826364 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2541 16:33:01.832923 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2542 16:33:01.836552 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2543 16:33:01.840019 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2544 16:33:01.842927 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2545 16:33:01.843011
2546 16:33:01.846788 CA PerBit enable=1, Macro0, CA PI delay=32
2547 16:33:01.846865
2548 16:33:01.849809 [CBTSetCACLKResult] CA Dly = 32
2549 16:33:01.849908 CS Dly: 6 (0~37)
2550 16:33:01.850000 ==
2551 16:33:01.853504 Dram Type= 6, Freq= 0, CH_0, rank 1
2552 16:33:01.859935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 16:33:01.860020 ==
2554 16:33:01.862831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2555 16:33:01.869829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2556 16:33:01.878572 [CA 0] Center 38 (8~69) winsize 62
2557 16:33:01.882193 [CA 1] Center 38 (8~69) winsize 62
2558 16:33:01.885221 [CA 2] Center 35 (4~66) winsize 63
2559 16:33:01.888808 [CA 3] Center 34 (4~65) winsize 62
2560 16:33:01.891742 [CA 4] Center 33 (3~64) winsize 62
2561 16:33:01.895471 [CA 5] Center 32 (3~62) winsize 60
2562 16:33:01.895581
2563 16:33:01.899086 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2564 16:33:01.899186
2565 16:33:01.902024 [CATrainingPosCal] consider 2 rank data
2566 16:33:01.905483 u2DelayCellTimex100 = 270/100 ps
2567 16:33:01.908465 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2568 16:33:01.912011 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2569 16:33:01.918966 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2570 16:33:01.922315 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2571 16:33:01.925703 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2572 16:33:01.928822 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2573 16:33:01.928930
2574 16:33:01.931994 CA PerBit enable=1, Macro0, CA PI delay=32
2575 16:33:01.932094
2576 16:33:01.935346 [CBTSetCACLKResult] CA Dly = 32
2577 16:33:01.935423 CS Dly: 6 (0~38)
2578 16:33:01.935484
2579 16:33:01.938522 ----->DramcWriteLeveling(PI) begin...
2580 16:33:01.941809 ==
2581 16:33:01.941883 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 16:33:01.948486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 16:33:01.948564 ==
2584 16:33:01.951989 Write leveling (Byte 0): 32 => 32
2585 16:33:01.955169 Write leveling (Byte 1): 30 => 30
2586 16:33:01.958929 DramcWriteLeveling(PI) end<-----
2587 16:33:01.959031
2588 16:33:01.959114 ==
2589 16:33:01.961864 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 16:33:01.965458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 16:33:01.965575 ==
2592 16:33:01.968930 [Gating] SW mode calibration
2593 16:33:01.975491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2594 16:33:01.978474 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2595 16:33:01.985615 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2596 16:33:01.988511 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2597 16:33:01.992357 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 16:33:01.998898 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 16:33:02.001842 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 16:33:02.005489 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 16:33:02.012032 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2602 16:33:02.015803 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2603 16:33:02.018907 1 0 0 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
2604 16:33:02.025683 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 16:33:02.028689 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 16:33:02.032332 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 16:33:02.039163 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 16:33:02.042076 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 16:33:02.045630 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2610 16:33:02.048909 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2611 16:33:02.055783 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2612 16:33:02.059080 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 16:33:02.062537 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 16:33:02.069079 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 16:33:02.072351 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 16:33:02.075564 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 16:33:02.082275 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 16:33:02.085963 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2619 16:33:02.088919 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2620 16:33:02.095439 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 16:33:02.099123 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 16:33:02.102064 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 16:33:02.108684 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 16:33:02.112350 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 16:33:02.115285 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 16:33:02.122503 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 16:33:02.125575 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 16:33:02.128699 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 16:33:02.135865 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 16:33:02.138779 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 16:33:02.142310 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 16:33:02.148890 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 16:33:02.151836 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 16:33:02.155546 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2635 16:33:02.161908 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2636 16:33:02.162017 Total UI for P1: 0, mck2ui 16
2637 16:33:02.165434 best dqsien dly found for B0: ( 1, 3, 28)
2638 16:33:02.172064 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 16:33:02.175669 Total UI for P1: 0, mck2ui 16
2640 16:33:02.178638 best dqsien dly found for B1: ( 1, 4, 0)
2641 16:33:02.182016 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2642 16:33:02.185472 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2643 16:33:02.185587
2644 16:33:02.188914 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2645 16:33:02.192217 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2646 16:33:02.195379 [Gating] SW calibration Done
2647 16:33:02.195457 ==
2648 16:33:02.198449 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 16:33:02.201716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 16:33:02.201796 ==
2651 16:33:02.205071 RX Vref Scan: 0
2652 16:33:02.205149
2653 16:33:02.205210 RX Vref 0 -> 0, step: 1
2654 16:33:02.205266
2655 16:33:02.208369 RX Delay -40 -> 252, step: 8
2656 16:33:02.212287 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2657 16:33:02.218776 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2658 16:33:02.222039 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2659 16:33:02.225674 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2660 16:33:02.228596 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2661 16:33:02.232400 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2662 16:33:02.238508 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2663 16:33:02.242260 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2664 16:33:02.245144 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2665 16:33:02.248722 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2666 16:33:02.251818 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2667 16:33:02.258521 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2668 16:33:02.262132 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2669 16:33:02.265664 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2670 16:33:02.269070 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2671 16:33:02.271924 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2672 16:33:02.275618 ==
2673 16:33:02.275699 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 16:33:02.282038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 16:33:02.282120 ==
2676 16:33:02.282199 DQS Delay:
2677 16:33:02.285725 DQS0 = 0, DQS1 = 0
2678 16:33:02.285797 DQM Delay:
2679 16:33:02.288676 DQM0 = 121, DQM1 = 113
2680 16:33:02.288748 DQ Delay:
2681 16:33:02.292391 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2682 16:33:02.295503 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2683 16:33:02.299181 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2684 16:33:02.302126 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2685 16:33:02.302201
2686 16:33:02.302293
2687 16:33:02.302386 ==
2688 16:33:02.305619 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 16:33:02.309049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 16:33:02.312359 ==
2691 16:33:02.312454
2692 16:33:02.312539
2693 16:33:02.312621 TX Vref Scan disable
2694 16:33:02.315427 == TX Byte 0 ==
2695 16:33:02.319162 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2696 16:33:02.322473 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2697 16:33:02.325801 == TX Byte 1 ==
2698 16:33:02.329294 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2699 16:33:02.332420 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2700 16:33:02.332514 ==
2701 16:33:02.335671 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 16:33:02.342321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 16:33:02.342420 ==
2704 16:33:02.353052 TX Vref=22, minBit 12, minWin=24, winSum=405
2705 16:33:02.356697 TX Vref=24, minBit 1, minWin=25, winSum=412
2706 16:33:02.359862 TX Vref=26, minBit 7, minWin=25, winSum=415
2707 16:33:02.363716 TX Vref=28, minBit 11, minWin=25, winSum=421
2708 16:33:02.366538 TX Vref=30, minBit 10, minWin=25, winSum=423
2709 16:33:02.373031 TX Vref=32, minBit 10, minWin=25, winSum=421
2710 16:33:02.376774 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 30
2711 16:33:02.376858
2712 16:33:02.380387 Final TX Range 1 Vref 30
2713 16:33:02.380462
2714 16:33:02.380556 ==
2715 16:33:02.383353 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 16:33:02.386778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 16:33:02.389646 ==
2718 16:33:02.389725
2719 16:33:02.389786
2720 16:33:02.389842 TX Vref Scan disable
2721 16:33:02.393424 == TX Byte 0 ==
2722 16:33:02.396499 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2723 16:33:02.400254 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2724 16:33:02.403752 == TX Byte 1 ==
2725 16:33:02.406860 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2726 16:33:02.409772 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2727 16:33:02.413513
2728 16:33:02.413613 [DATLAT]
2729 16:33:02.413676 Freq=1200, CH0 RK0
2730 16:33:02.413732
2731 16:33:02.417193 DATLAT Default: 0xd
2732 16:33:02.417272 0, 0xFFFF, sum = 0
2733 16:33:02.420172 1, 0xFFFF, sum = 0
2734 16:33:02.420260 2, 0xFFFF, sum = 0
2735 16:33:02.423846 3, 0xFFFF, sum = 0
2736 16:33:02.423954 4, 0xFFFF, sum = 0
2737 16:33:02.426671 5, 0xFFFF, sum = 0
2738 16:33:02.426779 6, 0xFFFF, sum = 0
2739 16:33:02.430143 7, 0xFFFF, sum = 0
2740 16:33:02.430219 8, 0xFFFF, sum = 0
2741 16:33:02.433694 9, 0xFFFF, sum = 0
2742 16:33:02.436531 10, 0xFFFF, sum = 0
2743 16:33:02.436605 11, 0xFFFF, sum = 0
2744 16:33:02.440197 12, 0x0, sum = 1
2745 16:33:02.440268 13, 0x0, sum = 2
2746 16:33:02.443554 14, 0x0, sum = 3
2747 16:33:02.443628 15, 0x0, sum = 4
2748 16:33:02.443716 best_step = 13
2749 16:33:02.443771
2750 16:33:02.446928 ==
2751 16:33:02.447028 Dram Type= 6, Freq= 0, CH_0, rank 0
2752 16:33:02.453353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2753 16:33:02.453435 ==
2754 16:33:02.453496 RX Vref Scan: 1
2755 16:33:02.453562
2756 16:33:02.456758 Set Vref Range= 32 -> 127
2757 16:33:02.456849
2758 16:33:02.460275 RX Vref 32 -> 127, step: 1
2759 16:33:02.460346
2760 16:33:02.463453 RX Delay -13 -> 252, step: 4
2761 16:33:02.463527
2762 16:33:02.466901 Set Vref, RX VrefLevel [Byte0]: 32
2763 16:33:02.469991 [Byte1]: 32
2764 16:33:02.470064
2765 16:33:02.473697 Set Vref, RX VrefLevel [Byte0]: 33
2766 16:33:02.477339 [Byte1]: 33
2767 16:33:02.477413
2768 16:33:02.480213 Set Vref, RX VrefLevel [Byte0]: 34
2769 16:33:02.483800 [Byte1]: 34
2770 16:33:02.487349
2771 16:33:02.487430 Set Vref, RX VrefLevel [Byte0]: 35
2772 16:33:02.490883 [Byte1]: 35
2773 16:33:02.495383
2774 16:33:02.495461 Set Vref, RX VrefLevel [Byte0]: 36
2775 16:33:02.499201 [Byte1]: 36
2776 16:33:02.503720
2777 16:33:02.503798 Set Vref, RX VrefLevel [Byte0]: 37
2778 16:33:02.506693 [Byte1]: 37
2779 16:33:02.511130
2780 16:33:02.511208 Set Vref, RX VrefLevel [Byte0]: 38
2781 16:33:02.514937 [Byte1]: 38
2782 16:33:02.519344
2783 16:33:02.519418 Set Vref, RX VrefLevel [Byte0]: 39
2784 16:33:02.522401 [Byte1]: 39
2785 16:33:02.526955
2786 16:33:02.527059 Set Vref, RX VrefLevel [Byte0]: 40
2787 16:33:02.530757 [Byte1]: 40
2788 16:33:02.535004
2789 16:33:02.535087 Set Vref, RX VrefLevel [Byte0]: 41
2790 16:33:02.538686 [Byte1]: 41
2791 16:33:02.543077
2792 16:33:02.543183 Set Vref, RX VrefLevel [Byte0]: 42
2793 16:33:02.545887 [Byte1]: 42
2794 16:33:02.550929
2795 16:33:02.550999 Set Vref, RX VrefLevel [Byte0]: 43
2796 16:33:02.553884 [Byte1]: 43
2797 16:33:02.558715
2798 16:33:02.558813 Set Vref, RX VrefLevel [Byte0]: 44
2799 16:33:02.562239 [Byte1]: 44
2800 16:33:02.566660
2801 16:33:02.566737 Set Vref, RX VrefLevel [Byte0]: 45
2802 16:33:02.570250 [Byte1]: 45
2803 16:33:02.574363
2804 16:33:02.574449 Set Vref, RX VrefLevel [Byte0]: 46
2805 16:33:02.577635 [Byte1]: 46
2806 16:33:02.582094
2807 16:33:02.582205 Set Vref, RX VrefLevel [Byte0]: 47
2808 16:33:02.585297 [Byte1]: 47
2809 16:33:02.590279
2810 16:33:02.590358 Set Vref, RX VrefLevel [Byte0]: 48
2811 16:33:02.593165 [Byte1]: 48
2812 16:33:02.597901
2813 16:33:02.598003 Set Vref, RX VrefLevel [Byte0]: 49
2814 16:33:02.601406 [Byte1]: 49
2815 16:33:02.605907
2816 16:33:02.605984 Set Vref, RX VrefLevel [Byte0]: 50
2817 16:33:02.609619 [Byte1]: 50
2818 16:33:02.614021
2819 16:33:02.614091 Set Vref, RX VrefLevel [Byte0]: 51
2820 16:33:02.616967 [Byte1]: 51
2821 16:33:02.622140
2822 16:33:02.622218 Set Vref, RX VrefLevel [Byte0]: 52
2823 16:33:02.625115 [Byte1]: 52
2824 16:33:02.629410
2825 16:33:02.629515 Set Vref, RX VrefLevel [Byte0]: 53
2826 16:33:02.633337 [Byte1]: 53
2827 16:33:02.637583
2828 16:33:02.637658 Set Vref, RX VrefLevel [Byte0]: 54
2829 16:33:02.641122 [Byte1]: 54
2830 16:33:02.645351
2831 16:33:02.645431 Set Vref, RX VrefLevel [Byte0]: 55
2832 16:33:02.649023 [Byte1]: 55
2833 16:33:02.653345
2834 16:33:02.653424 Set Vref, RX VrefLevel [Byte0]: 56
2835 16:33:02.656393 [Byte1]: 56
2836 16:33:02.661471
2837 16:33:02.661583 Set Vref, RX VrefLevel [Byte0]: 57
2838 16:33:02.664242 [Byte1]: 57
2839 16:33:02.669064
2840 16:33:02.669144 Set Vref, RX VrefLevel [Byte0]: 58
2841 16:33:02.672624 [Byte1]: 58
2842 16:33:02.677091
2843 16:33:02.677171 Set Vref, RX VrefLevel [Byte0]: 59
2844 16:33:02.680042 [Byte1]: 59
2845 16:33:02.685004
2846 16:33:02.685108 Set Vref, RX VrefLevel [Byte0]: 60
2847 16:33:02.688465 [Byte1]: 60
2848 16:33:02.692718
2849 16:33:02.692797 Set Vref, RX VrefLevel [Byte0]: 61
2850 16:33:02.696425 [Byte1]: 61
2851 16:33:02.700543
2852 16:33:02.700621 Set Vref, RX VrefLevel [Byte0]: 62
2853 16:33:02.703949 [Byte1]: 62
2854 16:33:02.708805
2855 16:33:02.708885 Set Vref, RX VrefLevel [Byte0]: 63
2856 16:33:02.711607 [Byte1]: 63
2857 16:33:02.716478
2858 16:33:02.716558 Set Vref, RX VrefLevel [Byte0]: 64
2859 16:33:02.720145 [Byte1]: 64
2860 16:33:02.724002
2861 16:33:02.724104 Set Vref, RX VrefLevel [Byte0]: 65
2862 16:33:02.727715 [Byte1]: 65
2863 16:33:02.732312
2864 16:33:02.732390 Set Vref, RX VrefLevel [Byte0]: 66
2865 16:33:02.735371 [Byte1]: 66
2866 16:33:02.739956
2867 16:33:02.740034 Set Vref, RX VrefLevel [Byte0]: 67
2868 16:33:02.743561 [Byte1]: 67
2869 16:33:02.748078
2870 16:33:02.748157 Set Vref, RX VrefLevel [Byte0]: 68
2871 16:33:02.751780 [Byte1]: 68
2872 16:33:02.755867
2873 16:33:02.755947 Set Vref, RX VrefLevel [Byte0]: 69
2874 16:33:02.759424 [Byte1]: 69
2875 16:33:02.763706
2876 16:33:02.763790 Final RX Vref Byte 0 = 57 to rank0
2877 16:33:02.767298 Final RX Vref Byte 1 = 50 to rank0
2878 16:33:02.770221 Final RX Vref Byte 0 = 57 to rank1
2879 16:33:02.773776 Final RX Vref Byte 1 = 50 to rank1==
2880 16:33:02.777207 Dram Type= 6, Freq= 0, CH_0, rank 0
2881 16:33:02.783781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 16:33:02.783891 ==
2883 16:33:02.783983 DQS Delay:
2884 16:33:02.784067 DQS0 = 0, DQS1 = 0
2885 16:33:02.787431 DQM Delay:
2886 16:33:02.787543 DQM0 = 120, DQM1 = 112
2887 16:33:02.790452 DQ Delay:
2888 16:33:02.794113 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2889 16:33:02.797064 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2890 16:33:02.800697 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2891 16:33:02.803729 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2892 16:33:02.803810
2893 16:33:02.803875
2894 16:33:02.810416 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2895 16:33:02.814013 CH0 RK0: MR19=404, MR18=1812
2896 16:33:02.820786 CH0_RK0: MR19=0x404, MR18=0x1812, DQSOSC=400, MR23=63, INC=40, DEC=27
2897 16:33:02.820871
2898 16:33:02.824433 ----->DramcWriteLeveling(PI) begin...
2899 16:33:02.824516 ==
2900 16:33:02.827704 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 16:33:02.831121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 16:33:02.831204 ==
2903 16:33:02.834778 Write leveling (Byte 0): 33 => 33
2904 16:33:02.837805 Write leveling (Byte 1): 30 => 30
2905 16:33:02.840863 DramcWriteLeveling(PI) end<-----
2906 16:33:02.840944
2907 16:33:02.841023 ==
2908 16:33:02.844473 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 16:33:02.848167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 16:33:02.848251 ==
2911 16:33:02.851006 [Gating] SW mode calibration
2912 16:33:02.857841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2913 16:33:02.864496 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2914 16:33:02.868012 0 15 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
2915 16:33:02.874784 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 16:33:02.877751 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 16:33:02.881278 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 16:33:02.887581 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 16:33:02.891145 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 16:33:02.894188 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 16:33:02.900739 0 15 28 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
2922 16:33:02.904420 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 16:33:02.908177 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 16:33:02.911295 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 16:33:02.917846 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 16:33:02.921455 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 16:33:02.924503 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 16:33:02.931177 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 16:33:02.934780 1 0 28 | B1->B0 | 3838 3d3d | 1 0 | (0 0) (0 0)
2930 16:33:02.937646 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 16:33:02.944605 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 16:33:02.947769 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 16:33:02.951193 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 16:33:02.957681 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 16:33:02.961438 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 16:33:02.964313 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 16:33:02.970872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2938 16:33:02.974317 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 16:33:02.978031 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 16:33:02.981776 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 16:33:02.988461 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 16:33:02.991276 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 16:33:02.994617 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 16:33:03.001404 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 16:33:03.004332 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 16:33:03.008018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 16:33:03.014799 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 16:33:03.017895 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 16:33:03.021536 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 16:33:03.027842 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 16:33:03.031593 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 16:33:03.034475 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 16:33:03.041203 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 16:33:03.044836 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 16:33:03.048419 Total UI for P1: 0, mck2ui 16
2956 16:33:03.051378 best dqsien dly found for B0: ( 1, 3, 30)
2957 16:33:03.054945 Total UI for P1: 0, mck2ui 16
2958 16:33:03.058099 best dqsien dly found for B1: ( 1, 3, 30)
2959 16:33:03.061692 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2960 16:33:03.065014 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2961 16:33:03.065097
2962 16:33:03.068155 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2963 16:33:03.071381 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2964 16:33:03.074537 [Gating] SW calibration Done
2965 16:33:03.074708 ==
2966 16:33:03.077814 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 16:33:03.081354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 16:33:03.081473 ==
2969 16:33:03.084643 RX Vref Scan: 0
2970 16:33:03.084748
2971 16:33:03.088024 RX Vref 0 -> 0, step: 1
2972 16:33:03.088129
2973 16:33:03.088228 RX Delay -40 -> 252, step: 8
2974 16:33:03.094880 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2975 16:33:03.097828 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2976 16:33:03.101512 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2977 16:33:03.104988 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2978 16:33:03.108488 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2979 16:33:03.114610 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2980 16:33:03.118029 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2981 16:33:03.121226 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2982 16:33:03.124900 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2983 16:33:03.127782 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2984 16:33:03.131400 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2985 16:33:03.138065 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2986 16:33:03.141752 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2987 16:33:03.144766 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2988 16:33:03.148482 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2989 16:33:03.155239 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2990 16:33:03.155376 ==
2991 16:33:03.158107 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 16:33:03.161720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 16:33:03.161802 ==
2994 16:33:03.161869 DQS Delay:
2995 16:33:03.164725 DQS0 = 0, DQS1 = 0
2996 16:33:03.164830 DQM Delay:
2997 16:33:03.168358 DQM0 = 122, DQM1 = 112
2998 16:33:03.168464 DQ Delay:
2999 16:33:03.171871 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
3000 16:33:03.174696 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
3001 16:33:03.178347 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3002 16:33:03.181796 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
3003 16:33:03.181917
3004 16:33:03.182012
3005 16:33:03.185244 ==
3006 16:33:03.185324 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 16:33:03.191307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 16:33:03.191391 ==
3009 16:33:03.191453
3010 16:33:03.191510
3011 16:33:03.191582 TX Vref Scan disable
3012 16:33:03.195085 == TX Byte 0 ==
3013 16:33:03.198811 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3014 16:33:03.201974 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3015 16:33:03.205480 == TX Byte 1 ==
3016 16:33:03.208677 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3017 16:33:03.212003 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3018 16:33:03.215719 ==
3019 16:33:03.218552 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 16:33:03.222031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 16:33:03.222137 ==
3022 16:33:03.233325 TX Vref=22, minBit 3, minWin=25, winSum=416
3023 16:33:03.236863 TX Vref=24, minBit 3, minWin=25, winSum=420
3024 16:33:03.239760 TX Vref=26, minBit 3, minWin=25, winSum=425
3025 16:33:03.243252 TX Vref=28, minBit 1, minWin=26, winSum=430
3026 16:33:03.246915 TX Vref=30, minBit 1, minWin=26, winSum=429
3027 16:33:03.253566 TX Vref=32, minBit 0, minWin=26, winSum=425
3028 16:33:03.256604 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3029 16:33:03.256693
3030 16:33:03.260223 Final TX Range 1 Vref 28
3031 16:33:03.260302
3032 16:33:03.260366 ==
3033 16:33:03.263045 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 16:33:03.266697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 16:33:03.266777 ==
3036 16:33:03.269672
3037 16:33:03.269750
3038 16:33:03.269811 TX Vref Scan disable
3039 16:33:03.273441 == TX Byte 0 ==
3040 16:33:03.276364 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3041 16:33:03.279495 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3042 16:33:03.283301 == TX Byte 1 ==
3043 16:33:03.286298 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3044 16:33:03.290107 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3045 16:33:03.293041
3046 16:33:03.293111 [DATLAT]
3047 16:33:03.293169 Freq=1200, CH0 RK1
3048 16:33:03.293224
3049 16:33:03.296663 DATLAT Default: 0xd
3050 16:33:03.296743 0, 0xFFFF, sum = 0
3051 16:33:03.299605 1, 0xFFFF, sum = 0
3052 16:33:03.299686 2, 0xFFFF, sum = 0
3053 16:33:03.303154 3, 0xFFFF, sum = 0
3054 16:33:03.306732 4, 0xFFFF, sum = 0
3055 16:33:03.306813 5, 0xFFFF, sum = 0
3056 16:33:03.309570 6, 0xFFFF, sum = 0
3057 16:33:03.309649 7, 0xFFFF, sum = 0
3058 16:33:03.313128 8, 0xFFFF, sum = 0
3059 16:33:03.313208 9, 0xFFFF, sum = 0
3060 16:33:03.316601 10, 0xFFFF, sum = 0
3061 16:33:03.316682 11, 0xFFFF, sum = 0
3062 16:33:03.319899 12, 0x0, sum = 1
3063 16:33:03.319979 13, 0x0, sum = 2
3064 16:33:03.323085 14, 0x0, sum = 3
3065 16:33:03.323160 15, 0x0, sum = 4
3066 16:33:03.323220 best_step = 13
3067 16:33:03.326351
3068 16:33:03.326433 ==
3069 16:33:03.329710 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 16:33:03.332902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 16:33:03.333001 ==
3072 16:33:03.333066 RX Vref Scan: 0
3073 16:33:03.333130
3074 16:33:03.336083 RX Vref 0 -> 0, step: 1
3075 16:33:03.336182
3076 16:33:03.339747 RX Delay -13 -> 252, step: 4
3077 16:33:03.342879 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3078 16:33:03.349498 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3079 16:33:03.352743 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3080 16:33:03.356109 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3081 16:33:03.359592 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3082 16:33:03.362523 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3083 16:33:03.369626 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3084 16:33:03.372477 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3085 16:33:03.376185 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3086 16:33:03.379208 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3087 16:33:03.382908 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3088 16:33:03.389454 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3089 16:33:03.392476 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3090 16:33:03.395473 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3091 16:33:03.399240 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3092 16:33:03.406057 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3093 16:33:03.406138 ==
3094 16:33:03.408875 Dram Type= 6, Freq= 0, CH_0, rank 1
3095 16:33:03.412586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 16:33:03.412659 ==
3097 16:33:03.412726 DQS Delay:
3098 16:33:03.415436 DQS0 = 0, DQS1 = 0
3099 16:33:03.415514 DQM Delay:
3100 16:33:03.419102 DQM0 = 120, DQM1 = 110
3101 16:33:03.419209 DQ Delay:
3102 16:33:03.422044 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3103 16:33:03.425666 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3104 16:33:03.428918 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =102
3105 16:33:03.432574 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
3106 16:33:03.432677
3107 16:33:03.432782
3108 16:33:03.442355 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3109 16:33:03.446032 CH0 RK1: MR19=403, MR18=DEE
3110 16:33:03.448949 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3111 16:33:03.451973 [RxdqsGatingPostProcess] freq 1200
3112 16:33:03.459133 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3113 16:33:03.462480 best DQS0 dly(2T, 0.5T) = (0, 11)
3114 16:33:03.465239 best DQS1 dly(2T, 0.5T) = (0, 12)
3115 16:33:03.468503 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3116 16:33:03.472327 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3117 16:33:03.475673 best DQS0 dly(2T, 0.5T) = (0, 11)
3118 16:33:03.478802 best DQS1 dly(2T, 0.5T) = (0, 11)
3119 16:33:03.481717 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3120 16:33:03.485134 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3121 16:33:03.488575 Pre-setting of DQS Precalculation
3122 16:33:03.491796 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3123 16:33:03.491904 ==
3124 16:33:03.495159 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 16:33:03.498258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 16:33:03.498371 ==
3127 16:33:03.505551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3128 16:33:03.512026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3129 16:33:03.519272 [CA 0] Center 37 (7~68) winsize 62
3130 16:33:03.523087 [CA 1] Center 37 (7~68) winsize 62
3131 16:33:03.526098 [CA 2] Center 35 (5~65) winsize 61
3132 16:33:03.529587 [CA 3] Center 34 (4~65) winsize 62
3133 16:33:03.532550 [CA 4] Center 34 (5~64) winsize 60
3134 16:33:03.536175 [CA 5] Center 33 (3~63) winsize 61
3135 16:33:03.536286
3136 16:33:03.539008 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3137 16:33:03.539127
3138 16:33:03.542655 [CATrainingPosCal] consider 1 rank data
3139 16:33:03.545566 u2DelayCellTimex100 = 270/100 ps
3140 16:33:03.549094 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3141 16:33:03.556099 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3142 16:33:03.559151 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3143 16:33:03.562180 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3144 16:33:03.565754 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3145 16:33:03.569398 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3146 16:33:03.569508
3147 16:33:03.572319 CA PerBit enable=1, Macro0, CA PI delay=33
3148 16:33:03.572432
3149 16:33:03.576036 [CBTSetCACLKResult] CA Dly = 33
3150 16:33:03.576142 CS Dly: 7 (0~38)
3151 16:33:03.578888 ==
3152 16:33:03.582510 Dram Type= 6, Freq= 0, CH_1, rank 1
3153 16:33:03.586094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 16:33:03.586208 ==
3155 16:33:03.588916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3156 16:33:03.595400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3157 16:33:03.604979 [CA 0] Center 37 (7~68) winsize 62
3158 16:33:03.608779 [CA 1] Center 38 (7~69) winsize 63
3159 16:33:03.611928 [CA 2] Center 35 (5~65) winsize 61
3160 16:33:03.614847 [CA 3] Center 35 (5~65) winsize 61
3161 16:33:03.618181 [CA 4] Center 34 (4~65) winsize 62
3162 16:33:03.621502 [CA 5] Center 33 (3~64) winsize 62
3163 16:33:03.621627
3164 16:33:03.624893 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3165 16:33:03.625030
3166 16:33:03.628221 [CATrainingPosCal] consider 2 rank data
3167 16:33:03.631344 u2DelayCellTimex100 = 270/100 ps
3168 16:33:03.634607 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3169 16:33:03.641918 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3170 16:33:03.644732 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3171 16:33:03.648443 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3172 16:33:03.651337 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3173 16:33:03.654887 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3174 16:33:03.655001
3175 16:33:03.657682 CA PerBit enable=1, Macro0, CA PI delay=33
3176 16:33:03.657792
3177 16:33:03.661178 [CBTSetCACLKResult] CA Dly = 33
3178 16:33:03.664951 CS Dly: 8 (0~41)
3179 16:33:03.665054
3180 16:33:03.667868 ----->DramcWriteLeveling(PI) begin...
3181 16:33:03.667974 ==
3182 16:33:03.671528 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 16:33:03.674408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 16:33:03.674520 ==
3185 16:33:03.678204 Write leveling (Byte 0): 25 => 25
3186 16:33:03.681053 Write leveling (Byte 1): 28 => 28
3187 16:33:03.684662 DramcWriteLeveling(PI) end<-----
3188 16:33:03.684777
3189 16:33:03.684870 ==
3190 16:33:03.687668 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 16:33:03.691287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 16:33:03.691369 ==
3193 16:33:03.694850 [Gating] SW mode calibration
3194 16:33:03.701222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3195 16:33:03.707773 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3196 16:33:03.711574 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 16:33:03.714533 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 16:33:03.721832 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 16:33:03.724708 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 16:33:03.728261 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 16:33:03.734917 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 16:33:03.737731 0 15 24 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
3203 16:33:03.740903 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3204 16:33:03.744671 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 16:33:03.751431 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 16:33:03.754403 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 16:33:03.757925 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 16:33:03.764196 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 16:33:03.767415 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 16:33:03.770749 1 0 24 | B1->B0 | 3333 3f3f | 1 0 | (0 0) (1 1)
3211 16:33:03.777913 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 16:33:03.780817 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 16:33:03.784442 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 16:33:03.790998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 16:33:03.794592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 16:33:03.797543 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 16:33:03.804074 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 16:33:03.807795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3219 16:33:03.810899 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3220 16:33:03.817598 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 16:33:03.820712 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 16:33:03.824396 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 16:33:03.831075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 16:33:03.834079 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 16:33:03.837649 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 16:33:03.843760 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 16:33:03.847430 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 16:33:03.850573 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 16:33:03.857376 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 16:33:03.860934 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 16:33:03.863723 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 16:33:03.870924 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 16:33:03.873581 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3234 16:33:03.876892 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3235 16:33:03.883907 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3236 16:33:03.884010 Total UI for P1: 0, mck2ui 16
3237 16:33:03.886944 best dqsien dly found for B0: ( 1, 3, 22)
3238 16:33:03.893704 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 16:33:03.897511 Total UI for P1: 0, mck2ui 16
3240 16:33:03.900629 best dqsien dly found for B1: ( 1, 3, 26)
3241 16:33:03.903549 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3242 16:33:03.907070 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3243 16:33:03.907141
3244 16:33:03.910425 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3245 16:33:03.914048 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3246 16:33:03.917241 [Gating] SW calibration Done
3247 16:33:03.917337 ==
3248 16:33:03.920633 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 16:33:03.923690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 16:33:03.923787 ==
3251 16:33:03.927341 RX Vref Scan: 0
3252 16:33:03.927432
3253 16:33:03.930314 RX Vref 0 -> 0, step: 1
3254 16:33:03.930406
3255 16:33:03.930491 RX Delay -40 -> 252, step: 8
3256 16:33:03.936865 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3257 16:33:03.940377 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3258 16:33:03.943422 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3259 16:33:03.947076 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3260 16:33:03.949906 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3261 16:33:03.956588 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3262 16:33:03.960379 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3263 16:33:03.963385 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3264 16:33:03.967184 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3265 16:33:03.970194 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3266 16:33:03.976832 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3267 16:33:03.980433 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3268 16:33:03.983383 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3269 16:33:03.986795 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3270 16:33:03.990428 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3271 16:33:03.997108 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3272 16:33:03.997213 ==
3273 16:33:04.000501 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 16:33:04.003425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 16:33:04.003503 ==
3276 16:33:04.003604 DQS Delay:
3277 16:33:04.007116 DQS0 = 0, DQS1 = 0
3278 16:33:04.007191 DQM Delay:
3279 16:33:04.010082 DQM0 = 119, DQM1 = 116
3280 16:33:04.010182 DQ Delay:
3281 16:33:04.013493 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3282 16:33:04.016905 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3283 16:33:04.019824 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3284 16:33:04.023343 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3285 16:33:04.023420
3286 16:33:04.026671
3287 16:33:04.026754 ==
3288 16:33:04.029913 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 16:33:04.033765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 16:33:04.033844 ==
3291 16:33:04.033920
3292 16:33:04.034016
3293 16:33:04.037091 TX Vref Scan disable
3294 16:33:04.037186 == TX Byte 0 ==
3295 16:33:04.040273 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3296 16:33:04.047014 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3297 16:33:04.047104 == TX Byte 1 ==
3298 16:33:04.053564 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3299 16:33:04.057030 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3300 16:33:04.057109 ==
3301 16:33:04.060151 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 16:33:04.063215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 16:33:04.063294 ==
3304 16:33:04.075760 TX Vref=22, minBit 1, minWin=24, winSum=411
3305 16:33:04.078765 TX Vref=24, minBit 10, minWin=25, winSum=420
3306 16:33:04.081976 TX Vref=26, minBit 9, minWin=25, winSum=421
3307 16:33:04.085824 TX Vref=28, minBit 1, minWin=26, winSum=430
3308 16:33:04.088816 TX Vref=30, minBit 9, minWin=25, winSum=428
3309 16:33:04.095797 TX Vref=32, minBit 9, minWin=25, winSum=426
3310 16:33:04.098828 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3311 16:33:04.098909
3312 16:33:04.101819 Final TX Range 1 Vref 28
3313 16:33:04.101902
3314 16:33:04.101964 ==
3315 16:33:04.105408 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 16:33:04.108407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 16:33:04.112101 ==
3318 16:33:04.112201
3319 16:33:04.112287
3320 16:33:04.112371 TX Vref Scan disable
3321 16:33:04.115791 == TX Byte 0 ==
3322 16:33:04.118958 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3323 16:33:04.122343 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3324 16:33:04.125279 == TX Byte 1 ==
3325 16:33:04.128354 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3326 16:33:04.134916 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3327 16:33:04.134998
3328 16:33:04.135059 [DATLAT]
3329 16:33:04.135115 Freq=1200, CH1 RK0
3330 16:33:04.135174
3331 16:33:04.138560 DATLAT Default: 0xd
3332 16:33:04.138666 0, 0xFFFF, sum = 0
3333 16:33:04.142182 1, 0xFFFF, sum = 0
3334 16:33:04.145199 2, 0xFFFF, sum = 0
3335 16:33:04.145268 3, 0xFFFF, sum = 0
3336 16:33:04.148166 4, 0xFFFF, sum = 0
3337 16:33:04.148257 5, 0xFFFF, sum = 0
3338 16:33:04.151662 6, 0xFFFF, sum = 0
3339 16:33:04.151732 7, 0xFFFF, sum = 0
3340 16:33:04.155313 8, 0xFFFF, sum = 0
3341 16:33:04.155386 9, 0xFFFF, sum = 0
3342 16:33:04.158601 10, 0xFFFF, sum = 0
3343 16:33:04.158669 11, 0xFFFF, sum = 0
3344 16:33:04.161943 12, 0x0, sum = 1
3345 16:33:04.162010 13, 0x0, sum = 2
3346 16:33:04.165167 14, 0x0, sum = 3
3347 16:33:04.165229 15, 0x0, sum = 4
3348 16:33:04.168434 best_step = 13
3349 16:33:04.168537
3350 16:33:04.168633 ==
3351 16:33:04.171732 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 16:33:04.174994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 16:33:04.175071 ==
3354 16:33:04.175132 RX Vref Scan: 1
3355 16:33:04.175193
3356 16:33:04.178274 Set Vref Range= 32 -> 127
3357 16:33:04.178362
3358 16:33:04.182010 RX Vref 32 -> 127, step: 1
3359 16:33:04.182077
3360 16:33:04.184846 RX Delay -5 -> 252, step: 4
3361 16:33:04.184946
3362 16:33:04.188466 Set Vref, RX VrefLevel [Byte0]: 32
3363 16:33:04.191747 [Byte1]: 32
3364 16:33:04.191848
3365 16:33:04.195042 Set Vref, RX VrefLevel [Byte0]: 33
3366 16:33:04.198426 [Byte1]: 33
3367 16:33:04.201412
3368 16:33:04.201508 Set Vref, RX VrefLevel [Byte0]: 34
3369 16:33:04.205113 [Byte1]: 34
3370 16:33:04.209627
3371 16:33:04.209722 Set Vref, RX VrefLevel [Byte0]: 35
3372 16:33:04.213123 [Byte1]: 35
3373 16:33:04.217376
3374 16:33:04.217473 Set Vref, RX VrefLevel [Byte0]: 36
3375 16:33:04.220276 [Byte1]: 36
3376 16:33:04.225128
3377 16:33:04.225207 Set Vref, RX VrefLevel [Byte0]: 37
3378 16:33:04.228202 [Byte1]: 37
3379 16:33:04.233241
3380 16:33:04.233344 Set Vref, RX VrefLevel [Byte0]: 38
3381 16:33:04.236112 [Byte1]: 38
3382 16:33:04.241285
3383 16:33:04.241389 Set Vref, RX VrefLevel [Byte0]: 39
3384 16:33:04.244224 [Byte1]: 39
3385 16:33:04.248722
3386 16:33:04.248793 Set Vref, RX VrefLevel [Byte0]: 40
3387 16:33:04.252479 [Byte1]: 40
3388 16:33:04.256205
3389 16:33:04.256307 Set Vref, RX VrefLevel [Byte0]: 41
3390 16:33:04.259954 [Byte1]: 41
3391 16:33:04.264457
3392 16:33:04.264553 Set Vref, RX VrefLevel [Byte0]: 42
3393 16:33:04.267447 [Byte1]: 42
3394 16:33:04.272598
3395 16:33:04.272671 Set Vref, RX VrefLevel [Byte0]: 43
3396 16:33:04.275384 [Byte1]: 43
3397 16:33:04.280300
3398 16:33:04.280413 Set Vref, RX VrefLevel [Byte0]: 44
3399 16:33:04.283272 [Byte1]: 44
3400 16:33:04.288268
3401 16:33:04.288340 Set Vref, RX VrefLevel [Byte0]: 45
3402 16:33:04.291084 [Byte1]: 45
3403 16:33:04.295998
3404 16:33:04.296076 Set Vref, RX VrefLevel [Byte0]: 46
3405 16:33:04.299381 [Byte1]: 46
3406 16:33:04.304029
3407 16:33:04.304106 Set Vref, RX VrefLevel [Byte0]: 47
3408 16:33:04.306690 [Byte1]: 47
3409 16:33:04.311703
3410 16:33:04.311782 Set Vref, RX VrefLevel [Byte0]: 48
3411 16:33:04.314826 [Byte1]: 48
3412 16:33:04.319564
3413 16:33:04.319671 Set Vref, RX VrefLevel [Byte0]: 49
3414 16:33:04.322418 [Byte1]: 49
3415 16:33:04.326972
3416 16:33:04.327072 Set Vref, RX VrefLevel [Byte0]: 50
3417 16:33:04.330744 [Byte1]: 50
3418 16:33:04.334708
3419 16:33:04.334809 Set Vref, RX VrefLevel [Byte0]: 51
3420 16:33:04.338659 [Byte1]: 51
3421 16:33:04.342615
3422 16:33:04.342697 Set Vref, RX VrefLevel [Byte0]: 52
3423 16:33:04.346267 [Byte1]: 52
3424 16:33:04.350646
3425 16:33:04.350742 Set Vref, RX VrefLevel [Byte0]: 53
3426 16:33:04.354369 [Byte1]: 53
3427 16:33:04.358707
3428 16:33:04.358784 Set Vref, RX VrefLevel [Byte0]: 54
3429 16:33:04.361720 [Byte1]: 54
3430 16:33:04.366224
3431 16:33:04.366301 Set Vref, RX VrefLevel [Byte0]: 55
3432 16:33:04.370022 [Byte1]: 55
3433 16:33:04.374565
3434 16:33:04.374642 Set Vref, RX VrefLevel [Byte0]: 56
3435 16:33:04.377423 [Byte1]: 56
3436 16:33:04.382470
3437 16:33:04.382548 Set Vref, RX VrefLevel [Byte0]: 57
3438 16:33:04.385174 [Byte1]: 57
3439 16:33:04.390234
3440 16:33:04.390310 Set Vref, RX VrefLevel [Byte0]: 58
3441 16:33:04.393694 [Byte1]: 58
3442 16:33:04.398166
3443 16:33:04.398266 Set Vref, RX VrefLevel [Byte0]: 59
3444 16:33:04.401135 [Byte1]: 59
3445 16:33:04.405478
3446 16:33:04.405581 Set Vref, RX VrefLevel [Byte0]: 60
3447 16:33:04.409280 [Byte1]: 60
3448 16:33:04.413790
3449 16:33:04.413898 Set Vref, RX VrefLevel [Byte0]: 61
3450 16:33:04.416844 [Byte1]: 61
3451 16:33:04.421225
3452 16:33:04.421320 Set Vref, RX VrefLevel [Byte0]: 62
3453 16:33:04.424876 [Byte1]: 62
3454 16:33:04.429137
3455 16:33:04.429232 Set Vref, RX VrefLevel [Byte0]: 63
3456 16:33:04.432161 [Byte1]: 63
3457 16:33:04.436831
3458 16:33:04.436926 Set Vref, RX VrefLevel [Byte0]: 64
3459 16:33:04.440679 [Byte1]: 64
3460 16:33:04.445087
3461 16:33:04.445178 Set Vref, RX VrefLevel [Byte0]: 65
3462 16:33:04.448322 [Byte1]: 65
3463 16:33:04.452878
3464 16:33:04.452970 Set Vref, RX VrefLevel [Byte0]: 66
3465 16:33:04.456182 [Byte1]: 66
3466 16:33:04.460550
3467 16:33:04.460646 Final RX Vref Byte 0 = 54 to rank0
3468 16:33:04.464070 Final RX Vref Byte 1 = 50 to rank0
3469 16:33:04.467491 Final RX Vref Byte 0 = 54 to rank1
3470 16:33:04.470452 Final RX Vref Byte 1 = 50 to rank1==
3471 16:33:04.474187 Dram Type= 6, Freq= 0, CH_1, rank 0
3472 16:33:04.480895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 16:33:04.481004 ==
3474 16:33:04.481092 DQS Delay:
3475 16:33:04.481152 DQS0 = 0, DQS1 = 0
3476 16:33:04.483972 DQM Delay:
3477 16:33:04.484050 DQM0 = 120, DQM1 = 116
3478 16:33:04.486871 DQ Delay:
3479 16:33:04.490499 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3480 16:33:04.494060 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3481 16:33:04.496826 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3482 16:33:04.500313 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3483 16:33:04.500390
3484 16:33:04.500450
3485 16:33:04.510264 [DQSOSCAuto] RK0, (LSB)MR18= 0x113, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3486 16:33:04.510345 CH1 RK0: MR19=404, MR18=113
3487 16:33:04.517369 CH1_RK0: MR19=0x404, MR18=0x113, DQSOSC=402, MR23=63, INC=40, DEC=27
3488 16:33:04.517447
3489 16:33:04.520236 ----->DramcWriteLeveling(PI) begin...
3490 16:33:04.520352 ==
3491 16:33:04.523843 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 16:33:04.526788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 16:33:04.530356 ==
3494 16:33:04.533379 Write leveling (Byte 0): 27 => 27
3495 16:33:04.533481 Write leveling (Byte 1): 29 => 29
3496 16:33:04.537105 DramcWriteLeveling(PI) end<-----
3497 16:33:04.537181
3498 16:33:04.537240 ==
3499 16:33:04.540106 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 16:33:04.546679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 16:33:04.546786 ==
3502 16:33:04.550271 [Gating] SW mode calibration
3503 16:33:04.556874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3504 16:33:04.559895 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3505 16:33:04.566660 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 16:33:04.569886 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 16:33:04.573219 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 16:33:04.579793 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 16:33:04.583633 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 16:33:04.586685 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3511 16:33:04.593197 0 15 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 1)
3512 16:33:04.596823 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3513 16:33:04.599868 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 16:33:04.603174 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 16:33:04.609928 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 16:33:04.613543 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 16:33:04.617042 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 16:33:04.623350 1 0 20 | B1->B0 | 2b2a 2323 | 1 0 | (1 1) (0 0)
3519 16:33:04.626365 1 0 24 | B1->B0 | 4444 2d2d | 0 0 | (1 1) (0 0)
3520 16:33:04.630086 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3521 16:33:04.636760 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 16:33:04.639809 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 16:33:04.642821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 16:33:04.649360 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 16:33:04.653018 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 16:33:04.656645 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3527 16:33:04.663306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3528 16:33:04.666068 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3529 16:33:04.669701 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3530 16:33:04.676146 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 16:33:04.679867 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 16:33:04.682801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 16:33:04.689704 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 16:33:04.692552 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 16:33:04.696169 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 16:33:04.702520 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 16:33:04.706032 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 16:33:04.709303 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 16:33:04.715847 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 16:33:04.719624 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 16:33:04.722875 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 16:33:04.729654 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3543 16:33:04.732576 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3544 16:33:04.736156 Total UI for P1: 0, mck2ui 16
3545 16:33:04.739940 best dqsien dly found for B1: ( 1, 3, 20)
3546 16:33:04.742985 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3547 16:33:04.746349 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 16:33:04.749344 Total UI for P1: 0, mck2ui 16
3549 16:33:04.752989 best dqsien dly found for B0: ( 1, 3, 28)
3550 16:33:04.755867 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3551 16:33:04.762724 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3552 16:33:04.762807
3553 16:33:04.766234 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3554 16:33:04.769312 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3555 16:33:04.773013 [Gating] SW calibration Done
3556 16:33:04.773087 ==
3557 16:33:04.776004 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 16:33:04.779128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 16:33:04.779209 ==
3560 16:33:04.779273 RX Vref Scan: 0
3561 16:33:04.782746
3562 16:33:04.782847 RX Vref 0 -> 0, step: 1
3563 16:33:04.782925
3564 16:33:04.785749 RX Delay -40 -> 252, step: 8
3565 16:33:04.789410 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3566 16:33:04.792292 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3567 16:33:04.798844 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3568 16:33:04.802385 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3569 16:33:04.806070 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3570 16:33:04.809034 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3571 16:33:04.812758 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3572 16:33:04.819331 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3573 16:33:04.822247 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3574 16:33:04.825901 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3575 16:33:04.828701 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3576 16:33:04.832309 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3577 16:33:04.838770 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3578 16:33:04.842344 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3579 16:33:04.845665 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3580 16:33:04.849070 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3581 16:33:04.849146 ==
3582 16:33:04.852456 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 16:33:04.858878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 16:33:04.858999 ==
3585 16:33:04.859070 DQS Delay:
3586 16:33:04.862091 DQS0 = 0, DQS1 = 0
3587 16:33:04.862180 DQM Delay:
3588 16:33:04.865199 DQM0 = 121, DQM1 = 118
3589 16:33:04.865302 DQ Delay:
3590 16:33:04.868856 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3591 16:33:04.872182 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3592 16:33:04.875538 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3593 16:33:04.878463 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3594 16:33:04.878571
3595 16:33:04.878662
3596 16:33:04.878745 ==
3597 16:33:04.882161 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 16:33:04.888741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 16:33:04.888822 ==
3600 16:33:04.888886
3601 16:33:04.888943
3602 16:33:04.888997 TX Vref Scan disable
3603 16:33:04.891802 == TX Byte 0 ==
3604 16:33:04.895367 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3605 16:33:04.902170 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3606 16:33:04.902249 == TX Byte 1 ==
3607 16:33:04.905043 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3608 16:33:04.911744 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3609 16:33:04.911830 ==
3610 16:33:04.915483 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 16:33:04.918585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 16:33:04.918667 ==
3613 16:33:04.930324 TX Vref=22, minBit 1, minWin=25, winSum=416
3614 16:33:04.933444 TX Vref=24, minBit 1, minWin=25, winSum=423
3615 16:33:04.936486 TX Vref=26, minBit 10, minWin=25, winSum=426
3616 16:33:04.940176 TX Vref=28, minBit 2, minWin=26, winSum=429
3617 16:33:04.943872 TX Vref=30, minBit 4, minWin=26, winSum=433
3618 16:33:04.946785 TX Vref=32, minBit 11, minWin=25, winSum=431
3619 16:33:04.953351 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 30
3620 16:33:04.953474
3621 16:33:04.956317 Final TX Range 1 Vref 30
3622 16:33:04.956417
3623 16:33:04.956485 ==
3624 16:33:04.960028 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 16:33:04.963916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 16:33:04.964050 ==
3627 16:33:04.964138
3628 16:33:04.966772
3629 16:33:04.966876 TX Vref Scan disable
3630 16:33:04.969689 == TX Byte 0 ==
3631 16:33:04.973391 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3632 16:33:04.976974 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3633 16:33:04.979841 == TX Byte 1 ==
3634 16:33:04.983355 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3635 16:33:04.986698 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3636 16:33:04.986783
3637 16:33:04.989853 [DATLAT]
3638 16:33:04.989956 Freq=1200, CH1 RK1
3639 16:33:04.990044
3640 16:33:04.993068 DATLAT Default: 0xd
3641 16:33:04.993146 0, 0xFFFF, sum = 0
3642 16:33:04.996324 1, 0xFFFF, sum = 0
3643 16:33:04.996435 2, 0xFFFF, sum = 0
3644 16:33:04.999697 3, 0xFFFF, sum = 0
3645 16:33:04.999783 4, 0xFFFF, sum = 0
3646 16:33:05.003509 5, 0xFFFF, sum = 0
3647 16:33:05.003589 6, 0xFFFF, sum = 0
3648 16:33:05.006871 7, 0xFFFF, sum = 0
3649 16:33:05.006965 8, 0xFFFF, sum = 0
3650 16:33:05.010240 9, 0xFFFF, sum = 0
3651 16:33:05.012993 10, 0xFFFF, sum = 0
3652 16:33:05.013074 11, 0xFFFF, sum = 0
3653 16:33:05.016571 12, 0x0, sum = 1
3654 16:33:05.016652 13, 0x0, sum = 2
3655 16:33:05.019530 14, 0x0, sum = 3
3656 16:33:05.019611 15, 0x0, sum = 4
3657 16:33:05.019674 best_step = 13
3658 16:33:05.019756
3659 16:33:05.023205 ==
3660 16:33:05.026176 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 16:33:05.029915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 16:33:05.029989 ==
3663 16:33:05.030051 RX Vref Scan: 0
3664 16:33:05.030106
3665 16:33:05.032930 RX Vref 0 -> 0, step: 1
3666 16:33:05.033022
3667 16:33:05.036498 RX Delay -5 -> 252, step: 4
3668 16:33:05.040176 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3669 16:33:05.043041 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3670 16:33:05.049655 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3671 16:33:05.053414 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3672 16:33:05.056201 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3673 16:33:05.060014 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3674 16:33:05.062965 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3675 16:33:05.069236 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3676 16:33:05.072640 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3677 16:33:05.076270 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3678 16:33:05.079179 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3679 16:33:05.085872 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3680 16:33:05.089504 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3681 16:33:05.092638 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3682 16:33:05.096314 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3683 16:33:05.099276 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3684 16:33:05.102798 ==
3685 16:33:05.102906 Dram Type= 6, Freq= 0, CH_1, rank 1
3686 16:33:05.109223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3687 16:33:05.109316 ==
3688 16:33:05.109377 DQS Delay:
3689 16:33:05.112673 DQS0 = 0, DQS1 = 0
3690 16:33:05.112752 DQM Delay:
3691 16:33:05.116062 DQM0 = 120, DQM1 = 117
3692 16:33:05.116166 DQ Delay:
3693 16:33:05.119449 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3694 16:33:05.122655 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3695 16:33:05.125586 DQ8 =106, DQ9 =106, DQ10 =118, DQ11 =110
3696 16:33:05.129286 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3697 16:33:05.129388
3698 16:33:05.129482
3699 16:33:05.138930 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3700 16:33:05.142558 CH1 RK1: MR19=403, MR18=14F1
3701 16:33:05.146157 CH1_RK1: MR19=0x403, MR18=0x14F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3702 16:33:05.149270 [RxdqsGatingPostProcess] freq 1200
3703 16:33:05.155949 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3704 16:33:05.158658 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 16:33:05.162341 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 16:33:05.165488 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 16:33:05.169217 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 16:33:05.172256 best DQS0 dly(2T, 0.5T) = (0, 11)
3709 16:33:05.175878 best DQS1 dly(2T, 0.5T) = (0, 11)
3710 16:33:05.178709 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3711 16:33:05.182191 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3712 16:33:05.182277 Pre-setting of DQS Precalculation
3713 16:33:05.189184 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3714 16:33:05.195766 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3715 16:33:05.202425 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3716 16:33:05.202543
3717 16:33:05.202646
3718 16:33:05.205356 [Calibration Summary] 2400 Mbps
3719 16:33:05.208994 CH 0, Rank 0
3720 16:33:05.209093 SW Impedance : PASS
3721 16:33:05.211979 DUTY Scan : NO K
3722 16:33:05.215797 ZQ Calibration : PASS
3723 16:33:05.215877 Jitter Meter : NO K
3724 16:33:05.218584 CBT Training : PASS
3725 16:33:05.222427 Write leveling : PASS
3726 16:33:05.222512 RX DQS gating : PASS
3727 16:33:05.225255 RX DQ/DQS(RDDQC) : PASS
3728 16:33:05.225354 TX DQ/DQS : PASS
3729 16:33:05.228772 RX DATLAT : PASS
3730 16:33:05.232115 RX DQ/DQS(Engine): PASS
3731 16:33:05.232188 TX OE : NO K
3732 16:33:05.235420 All Pass.
3733 16:33:05.235502
3734 16:33:05.235569 CH 0, Rank 1
3735 16:33:05.238694 SW Impedance : PASS
3736 16:33:05.238784 DUTY Scan : NO K
3737 16:33:05.242394 ZQ Calibration : PASS
3738 16:33:05.245970 Jitter Meter : NO K
3739 16:33:05.246071 CBT Training : PASS
3740 16:33:05.248885 Write leveling : PASS
3741 16:33:05.252408 RX DQS gating : PASS
3742 16:33:05.252506 RX DQ/DQS(RDDQC) : PASS
3743 16:33:05.255432 TX DQ/DQS : PASS
3744 16:33:05.259076 RX DATLAT : PASS
3745 16:33:05.259147 RX DQ/DQS(Engine): PASS
3746 16:33:05.261906 TX OE : NO K
3747 16:33:05.262004 All Pass.
3748 16:33:05.262087
3749 16:33:05.265533 CH 1, Rank 0
3750 16:33:05.265617 SW Impedance : PASS
3751 16:33:05.268961 DUTY Scan : NO K
3752 16:33:05.271948 ZQ Calibration : PASS
3753 16:33:05.272024 Jitter Meter : NO K
3754 16:33:05.275638 CBT Training : PASS
3755 16:33:05.275711 Write leveling : PASS
3756 16:33:05.278485 RX DQS gating : PASS
3757 16:33:05.282168 RX DQ/DQS(RDDQC) : PASS
3758 16:33:05.282316 TX DQ/DQS : PASS
3759 16:33:05.285163 RX DATLAT : PASS
3760 16:33:05.288784 RX DQ/DQS(Engine): PASS
3761 16:33:05.288923 TX OE : NO K
3762 16:33:05.292295 All Pass.
3763 16:33:05.292431
3764 16:33:05.292558 CH 1, Rank 1
3765 16:33:05.295089 SW Impedance : PASS
3766 16:33:05.295168 DUTY Scan : NO K
3767 16:33:05.298805 ZQ Calibration : PASS
3768 16:33:05.301767 Jitter Meter : NO K
3769 16:33:05.301846 CBT Training : PASS
3770 16:33:05.305563 Write leveling : PASS
3771 16:33:05.308499 RX DQS gating : PASS
3772 16:33:05.308602 RX DQ/DQS(RDDQC) : PASS
3773 16:33:05.312221 TX DQ/DQS : PASS
3774 16:33:05.315448 RX DATLAT : PASS
3775 16:33:05.315527 RX DQ/DQS(Engine): PASS
3776 16:33:05.318409 TX OE : NO K
3777 16:33:05.318521 All Pass.
3778 16:33:05.318601
3779 16:33:05.322088 DramC Write-DBI off
3780 16:33:05.325025 PER_BANK_REFRESH: Hybrid Mode
3781 16:33:05.325123 TX_TRACKING: ON
3782 16:33:05.334900 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3783 16:33:05.338551 [FAST_K] Save calibration result to emmc
3784 16:33:05.342214 dramc_set_vcore_voltage set vcore to 650000
3785 16:33:05.345566 Read voltage for 600, 5
3786 16:33:05.345663 Vio18 = 0
3787 16:33:05.345736 Vcore = 650000
3788 16:33:05.348362 Vdram = 0
3789 16:33:05.348455 Vddq = 0
3790 16:33:05.348539 Vmddr = 0
3791 16:33:05.354803 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3792 16:33:05.358445 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3793 16:33:05.361855 MEM_TYPE=3, freq_sel=19
3794 16:33:05.364810 sv_algorithm_assistance_LP4_1600
3795 16:33:05.368554 ============ PULL DRAM RESETB DOWN ============
3796 16:33:05.371519 ========== PULL DRAM RESETB DOWN end =========
3797 16:33:05.378414 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3798 16:33:05.381762 ===================================
3799 16:33:05.381851 LPDDR4 DRAM CONFIGURATION
3800 16:33:05.384767 ===================================
3801 16:33:05.388474 EX_ROW_EN[0] = 0x0
3802 16:33:05.392200 EX_ROW_EN[1] = 0x0
3803 16:33:05.392300 LP4Y_EN = 0x0
3804 16:33:05.395074 WORK_FSP = 0x0
3805 16:33:05.395168 WL = 0x2
3806 16:33:05.398688 RL = 0x2
3807 16:33:05.398760 BL = 0x2
3808 16:33:05.402086 RPST = 0x0
3809 16:33:05.402203 RD_PRE = 0x0
3810 16:33:05.405047 WR_PRE = 0x1
3811 16:33:05.405159 WR_PST = 0x0
3812 16:33:05.408801 DBI_WR = 0x0
3813 16:33:05.408915 DBI_RD = 0x0
3814 16:33:05.411790 OTF = 0x1
3815 16:33:05.415511 ===================================
3816 16:33:05.418537 ===================================
3817 16:33:05.418652 ANA top config
3818 16:33:05.422066 ===================================
3819 16:33:05.424954 DLL_ASYNC_EN = 0
3820 16:33:05.428685 ALL_SLAVE_EN = 1
3821 16:33:05.428819 NEW_RANK_MODE = 1
3822 16:33:05.431455 DLL_IDLE_MODE = 1
3823 16:33:05.435118 LP45_APHY_COMB_EN = 1
3824 16:33:05.438685 TX_ODT_DIS = 1
3825 16:33:05.441528 NEW_8X_MODE = 1
3826 16:33:05.445280 ===================================
3827 16:33:05.445437 ===================================
3828 16:33:05.448329 data_rate = 1200
3829 16:33:05.451856 CKR = 1
3830 16:33:05.454747 DQ_P2S_RATIO = 8
3831 16:33:05.458282 ===================================
3832 16:33:05.461571 CA_P2S_RATIO = 8
3833 16:33:05.464969 DQ_CA_OPEN = 0
3834 16:33:05.468452 DQ_SEMI_OPEN = 0
3835 16:33:05.468602 CA_SEMI_OPEN = 0
3836 16:33:05.472034 CA_FULL_RATE = 0
3837 16:33:05.475335 DQ_CKDIV4_EN = 1
3838 16:33:05.478090 CA_CKDIV4_EN = 1
3839 16:33:05.481682 CA_PREDIV_EN = 0
3840 16:33:05.481788 PH8_DLY = 0
3841 16:33:05.485267 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3842 16:33:05.488000 DQ_AAMCK_DIV = 4
3843 16:33:05.491361 CA_AAMCK_DIV = 4
3844 16:33:05.495323 CA_ADMCK_DIV = 4
3845 16:33:05.498070 DQ_TRACK_CA_EN = 0
3846 16:33:05.501881 CA_PICK = 600
3847 16:33:05.501964 CA_MCKIO = 600
3848 16:33:05.504743 MCKIO_SEMI = 0
3849 16:33:05.508117 PLL_FREQ = 2288
3850 16:33:05.511790 DQ_UI_PI_RATIO = 32
3851 16:33:05.514687 CA_UI_PI_RATIO = 0
3852 16:33:05.518361 ===================================
3853 16:33:05.521453 ===================================
3854 16:33:05.524448 memory_type:LPDDR4
3855 16:33:05.524595 GP_NUM : 10
3856 16:33:05.528080 SRAM_EN : 1
3857 16:33:05.528183 MD32_EN : 0
3858 16:33:05.531590 ===================================
3859 16:33:05.534622 [ANA_INIT] >>>>>>>>>>>>>>
3860 16:33:05.538171 <<<<<< [CONFIGURE PHASE]: ANA_TX
3861 16:33:05.541116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3862 16:33:05.544758 ===================================
3863 16:33:05.547640 data_rate = 1200,PCW = 0X5800
3864 16:33:05.551318 ===================================
3865 16:33:05.554264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3866 16:33:05.561023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3867 16:33:05.564557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 16:33:05.571062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3869 16:33:05.574670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3870 16:33:05.577673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3871 16:33:05.577774 [ANA_INIT] flow start
3872 16:33:05.581297 [ANA_INIT] PLL >>>>>>>>
3873 16:33:05.584662 [ANA_INIT] PLL <<<<<<<<
3874 16:33:05.584740 [ANA_INIT] MIDPI >>>>>>>>
3875 16:33:05.587472 [ANA_INIT] MIDPI <<<<<<<<
3876 16:33:05.590808 [ANA_INIT] DLL >>>>>>>>
3877 16:33:05.590893 [ANA_INIT] flow end
3878 16:33:05.598087 ============ LP4 DIFF to SE enter ============
3879 16:33:05.600979 ============ LP4 DIFF to SE exit ============
3880 16:33:05.601056 [ANA_INIT] <<<<<<<<<<<<<
3881 16:33:05.604448 [Flow] Enable top DCM control >>>>>
3882 16:33:05.607615 [Flow] Enable top DCM control <<<<<
3883 16:33:05.611207 Enable DLL master slave shuffle
3884 16:33:05.617617 ==============================================================
3885 16:33:05.621318 Gating Mode config
3886 16:33:05.624247 ==============================================================
3887 16:33:05.627203 Config description:
3888 16:33:05.637399 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3889 16:33:05.644307 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3890 16:33:05.647843 SELPH_MODE 0: By rank 1: By Phase
3891 16:33:05.653637 ==============================================================
3892 16:33:05.657397 GAT_TRACK_EN = 1
3893 16:33:05.660975 RX_GATING_MODE = 2
3894 16:33:05.663947 RX_GATING_TRACK_MODE = 2
3895 16:33:05.667610 SELPH_MODE = 1
3896 16:33:05.667710 PICG_EARLY_EN = 1
3897 16:33:05.670365 VALID_LAT_VALUE = 1
3898 16:33:05.677047 ==============================================================
3899 16:33:05.680720 Enter into Gating configuration >>>>
3900 16:33:05.683650 Exit from Gating configuration <<<<
3901 16:33:05.687350 Enter into DVFS_PRE_config >>>>>
3902 16:33:05.697318 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3903 16:33:05.700074 Exit from DVFS_PRE_config <<<<<
3904 16:33:05.703678 Enter into PICG configuration >>>>
3905 16:33:05.707320 Exit from PICG configuration <<<<
3906 16:33:05.710057 [RX_INPUT] configuration >>>>>
3907 16:33:05.713542 [RX_INPUT] configuration <<<<<
3908 16:33:05.716987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3909 16:33:05.723323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3910 16:33:05.730074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3911 16:33:05.736681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3912 16:33:05.743273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 16:33:05.746787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 16:33:05.753130 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3915 16:33:05.756562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3916 16:33:05.760017 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3917 16:33:05.763660 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3918 16:33:05.770320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3919 16:33:05.773353 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 16:33:05.776230 ===================================
3921 16:33:05.779714 LPDDR4 DRAM CONFIGURATION
3922 16:33:05.783351 ===================================
3923 16:33:05.783433 EX_ROW_EN[0] = 0x0
3924 16:33:05.786693 EX_ROW_EN[1] = 0x0
3925 16:33:05.786804 LP4Y_EN = 0x0
3926 16:33:05.789610 WORK_FSP = 0x0
3927 16:33:05.789690 WL = 0x2
3928 16:33:05.793347 RL = 0x2
3929 16:33:05.793461 BL = 0x2
3930 16:33:05.796346 RPST = 0x0
3931 16:33:05.800073 RD_PRE = 0x0
3932 16:33:05.800173 WR_PRE = 0x1
3933 16:33:05.803015 WR_PST = 0x0
3934 16:33:05.803104 DBI_WR = 0x0
3935 16:33:05.806513 DBI_RD = 0x0
3936 16:33:05.806610 OTF = 0x1
3937 16:33:05.810047 ===================================
3938 16:33:05.812779 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3939 16:33:05.819403 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3940 16:33:05.822748 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3941 16:33:05.826329 ===================================
3942 16:33:05.830055 LPDDR4 DRAM CONFIGURATION
3943 16:33:05.832858 ===================================
3944 16:33:05.832962 EX_ROW_EN[0] = 0x10
3945 16:33:05.836310 EX_ROW_EN[1] = 0x0
3946 16:33:05.836415 LP4Y_EN = 0x0
3947 16:33:05.839814 WORK_FSP = 0x0
3948 16:33:05.839918 WL = 0x2
3949 16:33:05.842963 RL = 0x2
3950 16:33:05.843067 BL = 0x2
3951 16:33:05.846552 RPST = 0x0
3952 16:33:05.846653 RD_PRE = 0x0
3953 16:33:05.849502 WR_PRE = 0x1
3954 16:33:05.849599 WR_PST = 0x0
3955 16:33:05.853258 DBI_WR = 0x0
3956 16:33:05.853332 DBI_RD = 0x0
3957 16:33:05.856094 OTF = 0x1
3958 16:33:05.859783 ===================================
3959 16:33:05.866177 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3960 16:33:05.869720 nWR fixed to 30
3961 16:33:05.872467 [ModeRegInit_LP4] CH0 RK0
3962 16:33:05.872572 [ModeRegInit_LP4] CH0 RK1
3963 16:33:05.875900 [ModeRegInit_LP4] CH1 RK0
3964 16:33:05.879604 [ModeRegInit_LP4] CH1 RK1
3965 16:33:05.879714 match AC timing 17
3966 16:33:05.886387 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3967 16:33:05.889185 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3968 16:33:05.892540 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3969 16:33:05.899175 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3970 16:33:05.902773 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3971 16:33:05.902876 ==
3972 16:33:05.905646 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 16:33:05.909327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 16:33:05.909429 ==
3975 16:33:05.915777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3976 16:33:05.922301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3977 16:33:05.925694 [CA 0] Center 35 (5~66) winsize 62
3978 16:33:05.929175 [CA 1] Center 35 (5~66) winsize 62
3979 16:33:05.932536 [CA 2] Center 33 (3~64) winsize 62
3980 16:33:05.936092 [CA 3] Center 33 (2~64) winsize 63
3981 16:33:05.939343 [CA 4] Center 33 (2~64) winsize 63
3982 16:33:05.942766 [CA 5] Center 32 (2~63) winsize 62
3983 16:33:05.942869
3984 16:33:05.945487 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3985 16:33:05.945598
3986 16:33:05.948849 [CATrainingPosCal] consider 1 rank data
3987 16:33:05.952217 u2DelayCellTimex100 = 270/100 ps
3988 16:33:05.955841 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3989 16:33:05.959479 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3990 16:33:05.962347 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3991 16:33:05.966080 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3992 16:33:05.969059 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3993 16:33:05.975465 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3994 16:33:05.975548
3995 16:33:05.979133 CA PerBit enable=1, Macro0, CA PI delay=32
3996 16:33:05.979239
3997 16:33:05.982608 [CBTSetCACLKResult] CA Dly = 32
3998 16:33:05.982717 CS Dly: 4 (0~35)
3999 16:33:05.982806 ==
4000 16:33:05.985949 Dram Type= 6, Freq= 0, CH_0, rank 1
4001 16:33:05.989071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 16:33:05.991992 ==
4003 16:33:05.995542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4004 16:33:06.002602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4005 16:33:06.005629 [CA 0] Center 35 (5~66) winsize 62
4006 16:33:06.009308 [CA 1] Center 35 (5~66) winsize 62
4007 16:33:06.012273 [CA 2] Center 34 (3~65) winsize 63
4008 16:33:06.015301 [CA 3] Center 33 (3~64) winsize 62
4009 16:33:06.019025 [CA 4] Center 32 (2~63) winsize 62
4010 16:33:06.021995 [CA 5] Center 32 (1~63) winsize 63
4011 16:33:06.022078
4012 16:33:06.025619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4013 16:33:06.025714
4014 16:33:06.028570 [CATrainingPosCal] consider 2 rank data
4015 16:33:06.032141 u2DelayCellTimex100 = 270/100 ps
4016 16:33:06.035844 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4017 16:33:06.038723 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4018 16:33:06.042144 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4019 16:33:06.045536 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4020 16:33:06.051959 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4021 16:33:06.055439 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4022 16:33:06.055544
4023 16:33:06.058887 CA PerBit enable=1, Macro0, CA PI delay=32
4024 16:33:06.058989
4025 16:33:06.062294 [CBTSetCACLKResult] CA Dly = 32
4026 16:33:06.062399 CS Dly: 4 (0~35)
4027 16:33:06.062489
4028 16:33:06.065661 ----->DramcWriteLeveling(PI) begin...
4029 16:33:06.065766 ==
4030 16:33:06.068573 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 16:33:06.075233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 16:33:06.075343 ==
4033 16:33:06.078866 Write leveling (Byte 0): 33 => 33
4034 16:33:06.078968 Write leveling (Byte 1): 30 => 30
4035 16:33:06.081916 DramcWriteLeveling(PI) end<-----
4036 16:33:06.082021
4037 16:33:06.085540 ==
4038 16:33:06.085649 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 16:33:06.091954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 16:33:06.092061 ==
4041 16:33:06.095299 [Gating] SW mode calibration
4042 16:33:06.102341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4043 16:33:06.105635 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4044 16:33:06.112233 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 16:33:06.115055 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 16:33:06.118844 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 16:33:06.125461 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
4048 16:33:06.128473 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4049 16:33:06.132090 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 16:33:06.138332 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 16:33:06.141882 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 16:33:06.145559 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 16:33:06.152052 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 16:33:06.155682 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 16:33:06.158413 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
4056 16:33:06.162116 0 10 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
4057 16:33:06.168695 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 16:33:06.172174 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 16:33:06.175401 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 16:33:06.181905 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 16:33:06.185014 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 16:33:06.188560 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 16:33:06.195053 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4064 16:33:06.198691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 16:33:06.201555 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 16:33:06.208459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 16:33:06.211840 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 16:33:06.215127 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 16:33:06.221678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 16:33:06.224610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 16:33:06.228354 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 16:33:06.235096 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 16:33:06.237957 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 16:33:06.241610 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 16:33:06.247841 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 16:33:06.251568 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 16:33:06.255316 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 16:33:06.261668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 16:33:06.265033 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4080 16:33:06.267871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 16:33:06.271430 Total UI for P1: 0, mck2ui 16
4082 16:33:06.275111 best dqsien dly found for B0: ( 0, 13, 12)
4083 16:33:06.277982 Total UI for P1: 0, mck2ui 16
4084 16:33:06.281724 best dqsien dly found for B1: ( 0, 13, 14)
4085 16:33:06.284555 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4086 16:33:06.288074 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4087 16:33:06.288179
4088 16:33:06.294286 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4089 16:33:06.297626 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4090 16:33:06.297728 [Gating] SW calibration Done
4091 16:33:06.301062 ==
4092 16:33:06.304475 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 16:33:06.307616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 16:33:06.307721 ==
4095 16:33:06.307810 RX Vref Scan: 0
4096 16:33:06.307894
4097 16:33:06.310825 RX Vref 0 -> 0, step: 1
4098 16:33:06.310923
4099 16:33:06.314106 RX Delay -230 -> 252, step: 16
4100 16:33:06.317633 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4101 16:33:06.321002 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4102 16:33:06.327800 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4103 16:33:06.331453 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4104 16:33:06.334372 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4105 16:33:06.337966 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4106 16:33:06.340851 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4107 16:33:06.348060 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4108 16:33:06.350984 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4109 16:33:06.354547 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4110 16:33:06.357956 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4111 16:33:06.364535 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4112 16:33:06.367505 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4113 16:33:06.371219 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4114 16:33:06.373959 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4115 16:33:06.381186 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4116 16:33:06.381300 ==
4117 16:33:06.384256 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 16:33:06.387935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 16:33:06.388008 ==
4120 16:33:06.388067 DQS Delay:
4121 16:33:06.390768 DQS0 = 0, DQS1 = 0
4122 16:33:06.390847 DQM Delay:
4123 16:33:06.394476 DQM0 = 50, DQM1 = 45
4124 16:33:06.394554 DQ Delay:
4125 16:33:06.397342 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4126 16:33:06.401021 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4127 16:33:06.403948 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4128 16:33:06.407662 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4129 16:33:06.407741
4130 16:33:06.407816
4131 16:33:06.407875 ==
4132 16:33:06.410564 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 16:33:06.414097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 16:33:06.414199 ==
4135 16:33:06.414262
4136 16:33:06.414318
4137 16:33:06.417592 TX Vref Scan disable
4138 16:33:06.421066 == TX Byte 0 ==
4139 16:33:06.424422 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4140 16:33:06.427646 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4141 16:33:06.430922 == TX Byte 1 ==
4142 16:33:06.434263 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4143 16:33:06.437538 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4144 16:33:06.437655 ==
4145 16:33:06.440927 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 16:33:06.447764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 16:33:06.447852 ==
4148 16:33:06.447915
4149 16:33:06.447971
4150 16:33:06.448024 TX Vref Scan disable
4151 16:33:06.452038 == TX Byte 0 ==
4152 16:33:06.454867 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4153 16:33:06.461412 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4154 16:33:06.461514 == TX Byte 1 ==
4155 16:33:06.464972 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4156 16:33:06.471531 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4157 16:33:06.471609
4158 16:33:06.471670 [DATLAT]
4159 16:33:06.471726 Freq=600, CH0 RK0
4160 16:33:06.471782
4161 16:33:06.475248 DATLAT Default: 0x9
4162 16:33:06.475326 0, 0xFFFF, sum = 0
4163 16:33:06.478251 1, 0xFFFF, sum = 0
4164 16:33:06.481228 2, 0xFFFF, sum = 0
4165 16:33:06.481343 3, 0xFFFF, sum = 0
4166 16:33:06.484724 4, 0xFFFF, sum = 0
4167 16:33:06.484816 5, 0xFFFF, sum = 0
4168 16:33:06.487674 6, 0xFFFF, sum = 0
4169 16:33:06.487753 7, 0xFFFF, sum = 0
4170 16:33:06.491441 8, 0x0, sum = 1
4171 16:33:06.491521 9, 0x0, sum = 2
4172 16:33:06.494471 10, 0x0, sum = 3
4173 16:33:06.494550 11, 0x0, sum = 4
4174 16:33:06.494612 best_step = 9
4175 16:33:06.494694
4176 16:33:06.498170 ==
4177 16:33:06.500945 Dram Type= 6, Freq= 0, CH_0, rank 0
4178 16:33:06.504693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 16:33:06.504771 ==
4180 16:33:06.504832 RX Vref Scan: 1
4181 16:33:06.504888
4182 16:33:06.508199 RX Vref 0 -> 0, step: 1
4183 16:33:06.508277
4184 16:33:06.511163 RX Delay -163 -> 252, step: 8
4185 16:33:06.511242
4186 16:33:06.514808 Set Vref, RX VrefLevel [Byte0]: 57
4187 16:33:06.517674 [Byte1]: 50
4188 16:33:06.517753
4189 16:33:06.521239 Final RX Vref Byte 0 = 57 to rank0
4190 16:33:06.524063 Final RX Vref Byte 1 = 50 to rank0
4191 16:33:06.527816 Final RX Vref Byte 0 = 57 to rank1
4192 16:33:06.530782 Final RX Vref Byte 1 = 50 to rank1==
4193 16:33:06.534406 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 16:33:06.537318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 16:33:06.541013 ==
4196 16:33:06.541122 DQS Delay:
4197 16:33:06.541219 DQS0 = 0, DQS1 = 0
4198 16:33:06.543783 DQM Delay:
4199 16:33:06.543876 DQM0 = 52, DQM1 = 46
4200 16:33:06.547766 DQ Delay:
4201 16:33:06.547848 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =48
4202 16:33:06.550840 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4203 16:33:06.554085 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4204 16:33:06.557381 DQ12 =52, DQ13 =56, DQ14 =56, DQ15 =52
4205 16:33:06.557484
4206 16:33:06.560732
4207 16:33:06.567519 [DQSOSCAuto] RK0, (LSB)MR18= 0x7265, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4208 16:33:06.570393 CH0 RK0: MR19=808, MR18=7265
4209 16:33:06.577334 CH0_RK0: MR19=0x808, MR18=0x7265, DQSOSC=388, MR23=63, INC=174, DEC=116
4210 16:33:06.577437
4211 16:33:06.581036 ----->DramcWriteLeveling(PI) begin...
4212 16:33:06.581135 ==
4213 16:33:06.583930 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 16:33:06.587421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 16:33:06.587514 ==
4216 16:33:06.590306 Write leveling (Byte 0): 35 => 35
4217 16:33:06.593998 Write leveling (Byte 1): 30 => 30
4218 16:33:06.596956 DramcWriteLeveling(PI) end<-----
4219 16:33:06.597055
4220 16:33:06.597141 ==
4221 16:33:06.600606 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 16:33:06.604231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 16:33:06.604322 ==
4224 16:33:06.607308 [Gating] SW mode calibration
4225 16:33:06.613784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4226 16:33:06.620538 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4227 16:33:06.623534 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 16:33:06.627299 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 16:33:06.633934 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 16:33:06.636835 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4231 16:33:06.640471 0 9 16 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (1 1)
4232 16:33:06.647392 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 16:33:06.650291 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 16:33:06.653975 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 16:33:06.660211 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 16:33:06.663563 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 16:33:06.666828 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 16:33:06.673687 0 10 12 | B1->B0 | 2727 2928 | 0 1 | (0 0) (0 0)
4239 16:33:06.676663 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4240 16:33:06.679964 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 16:33:06.686662 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 16:33:06.690158 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 16:33:06.693584 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 16:33:06.699853 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 16:33:06.703584 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 16:33:06.706556 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 16:33:06.713185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 16:33:06.716939 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 16:33:06.720239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:33:06.726748 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 16:33:06.730340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 16:33:06.733121 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 16:33:06.736818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 16:33:06.743544 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 16:33:06.746489 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 16:33:06.750076 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 16:33:06.756868 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 16:33:06.759818 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 16:33:06.762871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 16:33:06.769507 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 16:33:06.773242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 16:33:06.776106 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4263 16:33:06.782961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 16:33:06.786368 Total UI for P1: 0, mck2ui 16
4265 16:33:06.789675 best dqsien dly found for B0: ( 0, 13, 12)
4266 16:33:06.793035 Total UI for P1: 0, mck2ui 16
4267 16:33:06.796184 best dqsien dly found for B1: ( 0, 13, 12)
4268 16:33:06.799277 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4269 16:33:06.802499 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4270 16:33:06.802569
4271 16:33:06.806253 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4272 16:33:06.809426 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4273 16:33:06.812654 [Gating] SW calibration Done
4274 16:33:06.812758 ==
4275 16:33:06.816008 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 16:33:06.819409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 16:33:06.819513 ==
4278 16:33:06.822812 RX Vref Scan: 0
4279 16:33:06.822916
4280 16:33:06.825664 RX Vref 0 -> 0, step: 1
4281 16:33:06.825735
4282 16:33:06.825792 RX Delay -230 -> 252, step: 16
4283 16:33:06.833041 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4284 16:33:06.835860 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4285 16:33:06.839501 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4286 16:33:06.842458 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4287 16:33:06.849020 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4288 16:33:06.852757 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4289 16:33:06.855784 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4290 16:33:06.859315 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4291 16:33:06.862792 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4292 16:33:06.869223 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4293 16:33:06.872845 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4294 16:33:06.875861 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4295 16:33:06.879447 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4296 16:33:06.885844 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4297 16:33:06.889494 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4298 16:33:06.892350 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4299 16:33:06.892450 ==
4300 16:33:06.895870 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 16:33:06.898859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 16:33:06.902309 ==
4303 16:33:06.902381 DQS Delay:
4304 16:33:06.902480 DQS0 = 0, DQS1 = 0
4305 16:33:06.905896 DQM Delay:
4306 16:33:06.905986 DQM0 = 52, DQM1 = 43
4307 16:33:06.908821 DQ Delay:
4308 16:33:06.908919 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4309 16:33:06.912383 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4310 16:33:06.915692 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4311 16:33:06.919062 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4312 16:33:06.919141
4313 16:33:06.922413
4314 16:33:06.922506 ==
4315 16:33:06.925695 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 16:33:06.928961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 16:33:06.929037 ==
4318 16:33:06.929095
4319 16:33:06.929148
4320 16:33:06.932226 TX Vref Scan disable
4321 16:33:06.932323 == TX Byte 0 ==
4322 16:33:06.939429 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4323 16:33:06.942657 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4324 16:33:06.942730 == TX Byte 1 ==
4325 16:33:06.949354 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4326 16:33:06.952790 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4327 16:33:06.952865 ==
4328 16:33:06.955813 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 16:33:06.958860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 16:33:06.958946 ==
4331 16:33:06.959037
4332 16:33:06.959114
4333 16:33:06.962519 TX Vref Scan disable
4334 16:33:06.965541 == TX Byte 0 ==
4335 16:33:06.969213 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4336 16:33:06.972153 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4337 16:33:06.975560 == TX Byte 1 ==
4338 16:33:06.979318 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4339 16:33:06.982203 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4340 16:33:06.982282
4341 16:33:06.985861 [DATLAT]
4342 16:33:06.985941 Freq=600, CH0 RK1
4343 16:33:06.986004
4344 16:33:06.988877 DATLAT Default: 0x9
4345 16:33:06.988954 0, 0xFFFF, sum = 0
4346 16:33:06.992519 1, 0xFFFF, sum = 0
4347 16:33:06.992591 2, 0xFFFF, sum = 0
4348 16:33:06.995401 3, 0xFFFF, sum = 0
4349 16:33:06.995495 4, 0xFFFF, sum = 0
4350 16:33:06.998924 5, 0xFFFF, sum = 0
4351 16:33:06.999033 6, 0xFFFF, sum = 0
4352 16:33:07.001920 7, 0xFFFF, sum = 0
4353 16:33:07.001994 8, 0x0, sum = 1
4354 16:33:07.005605 9, 0x0, sum = 2
4355 16:33:07.005695 10, 0x0, sum = 3
4356 16:33:07.009205 11, 0x0, sum = 4
4357 16:33:07.009310 best_step = 9
4358 16:33:07.009405
4359 16:33:07.009488 ==
4360 16:33:07.012090 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 16:33:07.018541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 16:33:07.018620 ==
4363 16:33:07.018696 RX Vref Scan: 0
4364 16:33:07.018762
4365 16:33:07.022063 RX Vref 0 -> 0, step: 1
4366 16:33:07.022158
4367 16:33:07.024906 RX Delay -163 -> 252, step: 8
4368 16:33:07.028616 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4369 16:33:07.035237 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4370 16:33:07.038169 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4371 16:33:07.041627 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4372 16:33:07.045071 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4373 16:33:07.048591 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4374 16:33:07.054727 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4375 16:33:07.058177 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4376 16:33:07.061438 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4377 16:33:07.064924 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4378 16:33:07.068179 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4379 16:33:07.075184 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4380 16:33:07.078754 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4381 16:33:07.081534 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4382 16:33:07.085065 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4383 16:33:07.088475 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4384 16:33:07.091419 ==
4385 16:33:07.091493 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 16:33:07.098066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 16:33:07.098139 ==
4388 16:33:07.098198 DQS Delay:
4389 16:33:07.101630 DQS0 = 0, DQS1 = 0
4390 16:33:07.101707 DQM Delay:
4391 16:33:07.105193 DQM0 = 53, DQM1 = 46
4392 16:33:07.105261 DQ Delay:
4393 16:33:07.108071 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4394 16:33:07.111748 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4395 16:33:07.114739 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4396 16:33:07.118335 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4397 16:33:07.118440
4398 16:33:07.118508
4399 16:33:07.124849 [DQSOSCAuto] RK1, (LSB)MR18= 0x6728, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4400 16:33:07.128429 CH0 RK1: MR19=808, MR18=6728
4401 16:33:07.135234 CH0_RK1: MR19=0x808, MR18=0x6728, DQSOSC=390, MR23=63, INC=172, DEC=114
4402 16:33:07.138103 [RxdqsGatingPostProcess] freq 600
4403 16:33:07.141766 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4404 16:33:07.144646 Pre-setting of DQS Precalculation
4405 16:33:07.151795 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4406 16:33:07.151917 ==
4407 16:33:07.154745 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 16:33:07.158234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 16:33:07.158386 ==
4410 16:33:07.164707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 16:33:07.171872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4412 16:33:07.174618 [CA 0] Center 36 (5~67) winsize 63
4413 16:33:07.177968 [CA 1] Center 36 (5~67) winsize 63
4414 16:33:07.181385 [CA 2] Center 34 (4~65) winsize 62
4415 16:33:07.184717 [CA 3] Center 34 (4~65) winsize 62
4416 16:33:07.188254 [CA 4] Center 34 (4~65) winsize 62
4417 16:33:07.191496 [CA 5] Center 33 (3~64) winsize 62
4418 16:33:07.191590
4419 16:33:07.194951 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4420 16:33:07.195046
4421 16:33:07.198437 [CATrainingPosCal] consider 1 rank data
4422 16:33:07.201285 u2DelayCellTimex100 = 270/100 ps
4423 16:33:07.204835 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4424 16:33:07.208140 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4425 16:33:07.211160 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 16:33:07.214773 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4427 16:33:07.218298 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 16:33:07.221127 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 16:33:07.221247
4430 16:33:07.224867 CA PerBit enable=1, Macro0, CA PI delay=33
4431 16:33:07.227886
4432 16:33:07.227990 [CBTSetCACLKResult] CA Dly = 33
4433 16:33:07.230942 CS Dly: 6 (0~37)
4434 16:33:07.231054 ==
4435 16:33:07.234595 Dram Type= 6, Freq= 0, CH_1, rank 1
4436 16:33:07.238217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 16:33:07.238323 ==
4438 16:33:07.244272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 16:33:07.250933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4440 16:33:07.254554 [CA 0] Center 36 (5~67) winsize 63
4441 16:33:07.258276 [CA 1] Center 36 (5~67) winsize 63
4442 16:33:07.261006 [CA 2] Center 34 (4~65) winsize 62
4443 16:33:07.264448 [CA 3] Center 34 (4~65) winsize 62
4444 16:33:07.268149 [CA 4] Center 34 (4~65) winsize 62
4445 16:33:07.270928 [CA 5] Center 34 (3~65) winsize 63
4446 16:33:07.271031
4447 16:33:07.274654 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4448 16:33:07.274758
4449 16:33:07.277684 [CATrainingPosCal] consider 2 rank data
4450 16:33:07.281304 u2DelayCellTimex100 = 270/100 ps
4451 16:33:07.284175 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4452 16:33:07.287677 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4453 16:33:07.291309 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 16:33:07.294032 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4455 16:33:07.297458 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 16:33:07.300810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 16:33:07.300912
4458 16:33:07.307772 CA PerBit enable=1, Macro0, CA PI delay=33
4459 16:33:07.307852
4460 16:33:07.311077 [CBTSetCACLKResult] CA Dly = 33
4461 16:33:07.311155 CS Dly: 6 (0~37)
4462 16:33:07.311216
4463 16:33:07.314367 ----->DramcWriteLeveling(PI) begin...
4464 16:33:07.314446 ==
4465 16:33:07.317672 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 16:33:07.320995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 16:33:07.321075 ==
4468 16:33:07.324477 Write leveling (Byte 0): 31 => 31
4469 16:33:07.327442 Write leveling (Byte 1): 32 => 32
4470 16:33:07.331243 DramcWriteLeveling(PI) end<-----
4471 16:33:07.331321
4472 16:33:07.331382 ==
4473 16:33:07.334285 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 16:33:07.340702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 16:33:07.340786 ==
4476 16:33:07.340847 [Gating] SW mode calibration
4477 16:33:07.350986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4478 16:33:07.354628 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4479 16:33:07.357517 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 16:33:07.364152 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 16:33:07.367643 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 16:33:07.371129 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (0 1) (1 1)
4483 16:33:07.377295 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 16:33:07.380989 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 16:33:07.383962 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 16:33:07.390956 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 16:33:07.394508 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 16:33:07.397435 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 16:33:07.404464 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 16:33:07.407305 0 10 12 | B1->B0 | 3939 3737 | 0 0 | (0 0) (0 0)
4491 16:33:07.410880 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 16:33:07.417164 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 16:33:07.420590 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 16:33:07.424153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 16:33:07.430333 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 16:33:07.434244 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 16:33:07.437625 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 16:33:07.443879 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4499 16:33:07.447394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 16:33:07.450332 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:33:07.456981 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:33:07.460535 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 16:33:07.464301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 16:33:07.467214 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 16:33:07.473896 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 16:33:07.477531 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 16:33:07.480379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 16:33:07.487304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 16:33:07.490210 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 16:33:07.493859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 16:33:07.500634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 16:33:07.503564 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 16:33:07.507258 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 16:33:07.513922 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4515 16:33:07.516713 Total UI for P1: 0, mck2ui 16
4516 16:33:07.520429 best dqsien dly found for B1: ( 0, 13, 10)
4517 16:33:07.523481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 16:33:07.526585 Total UI for P1: 0, mck2ui 16
4519 16:33:07.530041 best dqsien dly found for B0: ( 0, 13, 12)
4520 16:33:07.533664 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4521 16:33:07.536535 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4522 16:33:07.536612
4523 16:33:07.540086 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4524 16:33:07.543301 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4525 16:33:07.546426 [Gating] SW calibration Done
4526 16:33:07.546502 ==
4527 16:33:07.550187 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 16:33:07.556506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 16:33:07.556585 ==
4530 16:33:07.556646 RX Vref Scan: 0
4531 16:33:07.556719
4532 16:33:07.559794 RX Vref 0 -> 0, step: 1
4533 16:33:07.559876
4534 16:33:07.563364 RX Delay -230 -> 252, step: 16
4535 16:33:07.566272 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4536 16:33:07.569865 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4537 16:33:07.573422 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4538 16:33:07.580163 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4539 16:33:07.583083 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4540 16:33:07.586564 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4541 16:33:07.589954 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4542 16:33:07.596703 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4543 16:33:07.599402 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4544 16:33:07.603416 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4545 16:33:07.606651 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4546 16:33:07.609502 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4547 16:33:07.616680 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4548 16:33:07.619558 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4549 16:33:07.623219 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4550 16:33:07.626159 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4551 16:33:07.629825 ==
4552 16:33:07.632763 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 16:33:07.636517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 16:33:07.636596 ==
4555 16:33:07.636657 DQS Delay:
4556 16:33:07.639518 DQS0 = 0, DQS1 = 0
4557 16:33:07.639598 DQM Delay:
4558 16:33:07.643169 DQM0 = 49, DQM1 = 46
4559 16:33:07.643249 DQ Delay:
4560 16:33:07.646081 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4561 16:33:07.649797 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4562 16:33:07.652708 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4563 16:33:07.656158 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4564 16:33:07.656237
4565 16:33:07.656298
4566 16:33:07.656354 ==
4567 16:33:07.659719 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 16:33:07.663081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 16:33:07.663165 ==
4570 16:33:07.663227
4571 16:33:07.663282
4572 16:33:07.666460 TX Vref Scan disable
4573 16:33:07.669188 == TX Byte 0 ==
4574 16:33:07.673018 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4575 16:33:07.675790 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4576 16:33:07.679179 == TX Byte 1 ==
4577 16:33:07.682796 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4578 16:33:07.686448 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4579 16:33:07.686528 ==
4580 16:33:07.689406 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 16:33:07.693124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 16:33:07.695993 ==
4583 16:33:07.696098
4584 16:33:07.696195
4585 16:33:07.696286 TX Vref Scan disable
4586 16:33:07.700311 == TX Byte 0 ==
4587 16:33:07.703843 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4588 16:33:07.706728 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4589 16:33:07.710329 == TX Byte 1 ==
4590 16:33:07.713784 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4591 16:33:07.716616 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4592 16:33:07.720063
4593 16:33:07.720150 [DATLAT]
4594 16:33:07.720212 Freq=600, CH1 RK0
4595 16:33:07.720269
4596 16:33:07.723408 DATLAT Default: 0x9
4597 16:33:07.723515 0, 0xFFFF, sum = 0
4598 16:33:07.726727 1, 0xFFFF, sum = 0
4599 16:33:07.726853 2, 0xFFFF, sum = 0
4600 16:33:07.729852 3, 0xFFFF, sum = 0
4601 16:33:07.729955 4, 0xFFFF, sum = 0
4602 16:33:07.733521 5, 0xFFFF, sum = 0
4603 16:33:07.736525 6, 0xFFFF, sum = 0
4604 16:33:07.736675 7, 0xFFFF, sum = 0
4605 16:33:07.736767 8, 0x0, sum = 1
4606 16:33:07.739962 9, 0x0, sum = 2
4607 16:33:07.740093 10, 0x0, sum = 3
4608 16:33:07.743526 11, 0x0, sum = 4
4609 16:33:07.743671 best_step = 9
4610 16:33:07.743767
4611 16:33:07.743855 ==
4612 16:33:07.746495 Dram Type= 6, Freq= 0, CH_1, rank 0
4613 16:33:07.753308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 16:33:07.753437 ==
4615 16:33:07.753529 RX Vref Scan: 1
4616 16:33:07.753603
4617 16:33:07.756293 RX Vref 0 -> 0, step: 1
4618 16:33:07.756371
4619 16:33:07.760224 RX Delay -163 -> 252, step: 8
4620 16:33:07.760303
4621 16:33:07.763050 Set Vref, RX VrefLevel [Byte0]: 54
4622 16:33:07.766797 [Byte1]: 50
4623 16:33:07.766875
4624 16:33:07.769901 Final RX Vref Byte 0 = 54 to rank0
4625 16:33:07.773462 Final RX Vref Byte 1 = 50 to rank0
4626 16:33:07.776852 Final RX Vref Byte 0 = 54 to rank1
4627 16:33:07.779912 Final RX Vref Byte 1 = 50 to rank1==
4628 16:33:07.783645 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 16:33:07.786291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 16:33:07.786393 ==
4631 16:33:07.790168 DQS Delay:
4632 16:33:07.790257 DQS0 = 0, DQS1 = 0
4633 16:33:07.790320 DQM Delay:
4634 16:33:07.792991 DQM0 = 47, DQM1 = 45
4635 16:33:07.793101 DQ Delay:
4636 16:33:07.796606 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4637 16:33:07.799666 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4638 16:33:07.802747 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4639 16:33:07.806476 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4640 16:33:07.806570
4641 16:33:07.806633
4642 16:33:07.815934 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4643 16:33:07.819582 CH1 RK0: MR19=808, MR18=4B70
4644 16:33:07.823189 CH1_RK0: MR19=0x808, MR18=0x4B70, DQSOSC=388, MR23=63, INC=174, DEC=116
4645 16:33:07.823294
4646 16:33:07.826234 ----->DramcWriteLeveling(PI) begin...
4647 16:33:07.829759 ==
4648 16:33:07.832715 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 16:33:07.836250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 16:33:07.836336 ==
4651 16:33:07.839750 Write leveling (Byte 0): 29 => 29
4652 16:33:07.843220 Write leveling (Byte 1): 30 => 30
4653 16:33:07.846632 DramcWriteLeveling(PI) end<-----
4654 16:33:07.846730
4655 16:33:07.846792 ==
4656 16:33:07.849531 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 16:33:07.853332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 16:33:07.853442 ==
4659 16:33:07.856462 [Gating] SW mode calibration
4660 16:33:07.863226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4661 16:33:07.866189 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4662 16:33:07.872912 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 16:33:07.876495 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 16:33:07.879494 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4665 16:33:07.886710 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4666 16:33:07.889682 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 16:33:07.893267 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 16:33:07.899593 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 16:33:07.902874 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 16:33:07.906329 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 16:33:07.912631 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 16:33:07.916243 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4673 16:33:07.919724 0 10 12 | B1->B0 | 3838 3434 | 0 1 | (0 0) (0 0)
4674 16:33:07.926299 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 16:33:07.929365 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 16:33:07.932885 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 16:33:07.939394 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 16:33:07.942916 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 16:33:07.946590 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 16:33:07.952758 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 16:33:07.956118 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4682 16:33:07.959287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 16:33:07.966269 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 16:33:07.970381 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:33:07.972376 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 16:33:07.979077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 16:33:07.982625 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 16:33:07.986169 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 16:33:07.992829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 16:33:07.995792 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 16:33:07.999423 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 16:33:08.002439 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 16:33:08.009061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 16:33:08.012607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 16:33:08.016062 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 16:33:08.022515 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 16:33:08.025358 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4698 16:33:08.029007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 16:33:08.032450 Total UI for P1: 0, mck2ui 16
4700 16:33:08.035989 best dqsien dly found for B0: ( 0, 13, 12)
4701 16:33:08.038880 Total UI for P1: 0, mck2ui 16
4702 16:33:08.042353 best dqsien dly found for B1: ( 0, 13, 12)
4703 16:33:08.045321 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4704 16:33:08.052132 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4705 16:33:08.052248
4706 16:33:08.055845 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4707 16:33:08.058849 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4708 16:33:08.062473 [Gating] SW calibration Done
4709 16:33:08.062598 ==
4710 16:33:08.065397 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 16:33:08.068822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 16:33:08.068963 ==
4713 16:33:08.069058 RX Vref Scan: 0
4714 16:33:08.072420
4715 16:33:08.072535 RX Vref 0 -> 0, step: 1
4716 16:33:08.072599
4717 16:33:08.075304 RX Delay -230 -> 252, step: 16
4718 16:33:08.078690 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4719 16:33:08.085489 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4720 16:33:08.089116 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4721 16:33:08.091959 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4722 16:33:08.095752 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4723 16:33:08.098859 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4724 16:33:08.105475 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4725 16:33:08.109101 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4726 16:33:08.111992 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4727 16:33:08.115762 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4728 16:33:08.119087 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4729 16:33:08.125366 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4730 16:33:08.128857 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4731 16:33:08.132421 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4732 16:33:08.135443 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4733 16:33:08.142056 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4734 16:33:08.142136 ==
4735 16:33:08.145539 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 16:33:08.149096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 16:33:08.149175 ==
4738 16:33:08.149235 DQS Delay:
4739 16:33:08.151950 DQS0 = 0, DQS1 = 0
4740 16:33:08.152030 DQM Delay:
4741 16:33:08.155567 DQM0 = 51, DQM1 = 49
4742 16:33:08.155645 DQ Delay:
4743 16:33:08.158630 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4744 16:33:08.162332 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4745 16:33:08.165800 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4746 16:33:08.168830 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4747 16:33:08.168908
4748 16:33:08.168969
4749 16:33:08.169026 ==
4750 16:33:08.171847 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 16:33:08.175636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 16:33:08.178609 ==
4753 16:33:08.178687
4754 16:33:08.178766
4755 16:33:08.178825 TX Vref Scan disable
4756 16:33:08.182246 == TX Byte 0 ==
4757 16:33:08.184977 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4758 16:33:08.188530 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4759 16:33:08.191986 == TX Byte 1 ==
4760 16:33:08.195497 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4761 16:33:08.198325 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4762 16:33:08.202006 ==
4763 16:33:08.202104 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 16:33:08.208583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 16:33:08.208658 ==
4766 16:33:08.208717
4767 16:33:08.208771
4768 16:33:08.211582 TX Vref Scan disable
4769 16:33:08.211651 == TX Byte 0 ==
4770 16:33:08.218307 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4771 16:33:08.222058 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4772 16:33:08.222132 == TX Byte 1 ==
4773 16:33:08.228698 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4774 16:33:08.231631 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4775 16:33:08.231711
4776 16:33:08.231771 [DATLAT]
4777 16:33:08.235194 Freq=600, CH1 RK1
4778 16:33:08.235332
4779 16:33:08.235438 DATLAT Default: 0x9
4780 16:33:08.238751 0, 0xFFFF, sum = 0
4781 16:33:08.238831 1, 0xFFFF, sum = 0
4782 16:33:08.241506 2, 0xFFFF, sum = 0
4783 16:33:08.241596 3, 0xFFFF, sum = 0
4784 16:33:08.244779 4, 0xFFFF, sum = 0
4785 16:33:08.244858 5, 0xFFFF, sum = 0
4786 16:33:08.248125 6, 0xFFFF, sum = 0
4787 16:33:08.248205 7, 0xFFFF, sum = 0
4788 16:33:08.251540 8, 0x0, sum = 1
4789 16:33:08.251620 9, 0x0, sum = 2
4790 16:33:08.255066 10, 0x0, sum = 3
4791 16:33:08.255146 11, 0x0, sum = 4
4792 16:33:08.258543 best_step = 9
4793 16:33:08.258621
4794 16:33:08.258682 ==
4795 16:33:08.261450 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 16:33:08.265160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 16:33:08.265239 ==
4798 16:33:08.268176 RX Vref Scan: 0
4799 16:33:08.268253
4800 16:33:08.268314 RX Vref 0 -> 0, step: 1
4801 16:33:08.268371
4802 16:33:08.271818 RX Delay -163 -> 252, step: 8
4803 16:33:08.278572 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4804 16:33:08.281679 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4805 16:33:08.285365 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4806 16:33:08.288285 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4807 16:33:08.292188 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4808 16:33:08.298170 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4809 16:33:08.301775 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4810 16:33:08.305276 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4811 16:33:08.308550 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4812 16:33:08.315369 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4813 16:33:08.318337 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4814 16:33:08.322004 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4815 16:33:08.324980 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4816 16:33:08.328676 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4817 16:33:08.334757 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4818 16:33:08.338377 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4819 16:33:08.338457 ==
4820 16:33:08.341348 Dram Type= 6, Freq= 0, CH_1, rank 1
4821 16:33:08.345024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4822 16:33:08.345104 ==
4823 16:33:08.347947 DQS Delay:
4824 16:33:08.348027 DQS0 = 0, DQS1 = 0
4825 16:33:08.348088 DQM Delay:
4826 16:33:08.351461 DQM0 = 48, DQM1 = 44
4827 16:33:08.351540 DQ Delay:
4828 16:33:08.354940 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4829 16:33:08.358372 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =48
4830 16:33:08.361192 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4831 16:33:08.364594 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4832 16:33:08.364674
4833 16:33:08.364736
4834 16:33:08.374612 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4835 16:33:08.378171 CH1 RK1: MR19=808, MR18=6D23
4836 16:33:08.381201 CH1_RK1: MR19=0x808, MR18=0x6D23, DQSOSC=389, MR23=63, INC=173, DEC=115
4837 16:33:08.384899 [RxdqsGatingPostProcess] freq 600
4838 16:33:08.391415 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4839 16:33:08.395044 Pre-setting of DQS Precalculation
4840 16:33:08.397828 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4841 16:33:08.404588 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4842 16:33:08.414720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4843 16:33:08.414802
4844 16:33:08.414862
4845 16:33:08.418193 [Calibration Summary] 1200 Mbps
4846 16:33:08.418288 CH 0, Rank 0
4847 16:33:08.421463 SW Impedance : PASS
4848 16:33:08.421564 DUTY Scan : NO K
4849 16:33:08.424773 ZQ Calibration : PASS
4850 16:33:08.428213 Jitter Meter : NO K
4851 16:33:08.428294 CBT Training : PASS
4852 16:33:08.431115 Write leveling : PASS
4853 16:33:08.431197 RX DQS gating : PASS
4854 16:33:08.434866 RX DQ/DQS(RDDQC) : PASS
4855 16:33:08.437818 TX DQ/DQS : PASS
4856 16:33:08.437900 RX DATLAT : PASS
4857 16:33:08.441502 RX DQ/DQS(Engine): PASS
4858 16:33:08.444436 TX OE : NO K
4859 16:33:08.444541 All Pass.
4860 16:33:08.444617
4861 16:33:08.444690 CH 0, Rank 1
4862 16:33:08.448154 SW Impedance : PASS
4863 16:33:08.451078 DUTY Scan : NO K
4864 16:33:08.451211 ZQ Calibration : PASS
4865 16:33:08.454848 Jitter Meter : NO K
4866 16:33:08.457730 CBT Training : PASS
4867 16:33:08.457816 Write leveling : PASS
4868 16:33:08.461364 RX DQS gating : PASS
4869 16:33:08.464186 RX DQ/DQS(RDDQC) : PASS
4870 16:33:08.464346 TX DQ/DQS : PASS
4871 16:33:08.467993 RX DATLAT : PASS
4872 16:33:08.470864 RX DQ/DQS(Engine): PASS
4873 16:33:08.470948 TX OE : NO K
4874 16:33:08.471009 All Pass.
4875 16:33:08.474533
4876 16:33:08.474611 CH 1, Rank 0
4877 16:33:08.478104 SW Impedance : PASS
4878 16:33:08.478187 DUTY Scan : NO K
4879 16:33:08.480867 ZQ Calibration : PASS
4880 16:33:08.480965 Jitter Meter : NO K
4881 16:33:08.484208 CBT Training : PASS
4882 16:33:08.487601 Write leveling : PASS
4883 16:33:08.487686 RX DQS gating : PASS
4884 16:33:08.491091 RX DQ/DQS(RDDQC) : PASS
4885 16:33:08.494883 TX DQ/DQS : PASS
4886 16:33:08.494974 RX DATLAT : PASS
4887 16:33:08.497938 RX DQ/DQS(Engine): PASS
4888 16:33:08.501686 TX OE : NO K
4889 16:33:08.501773 All Pass.
4890 16:33:08.501834
4891 16:33:08.501891 CH 1, Rank 1
4892 16:33:08.504596 SW Impedance : PASS
4893 16:33:08.508315 DUTY Scan : NO K
4894 16:33:08.508429 ZQ Calibration : PASS
4895 16:33:08.511239 Jitter Meter : NO K
4896 16:33:08.514919 CBT Training : PASS
4897 16:33:08.515016 Write leveling : PASS
4898 16:33:08.517781 RX DQS gating : PASS
4899 16:33:08.521379 RX DQ/DQS(RDDQC) : PASS
4900 16:33:08.521479 TX DQ/DQS : PASS
4901 16:33:08.524191 RX DATLAT : PASS
4902 16:33:08.524274 RX DQ/DQS(Engine): PASS
4903 16:33:08.527911 TX OE : NO K
4904 16:33:08.528009 All Pass.
4905 16:33:08.528101
4906 16:33:08.531368 DramC Write-DBI off
4907 16:33:08.534104 PER_BANK_REFRESH: Hybrid Mode
4908 16:33:08.534216 TX_TRACKING: ON
4909 16:33:08.544069 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4910 16:33:08.547865 [FAST_K] Save calibration result to emmc
4911 16:33:08.550754 dramc_set_vcore_voltage set vcore to 662500
4912 16:33:08.554405 Read voltage for 933, 3
4913 16:33:08.554487 Vio18 = 0
4914 16:33:08.557383 Vcore = 662500
4915 16:33:08.557477 Vdram = 0
4916 16:33:08.557538 Vddq = 0
4917 16:33:08.557616 Vmddr = 0
4918 16:33:08.564038 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4919 16:33:08.570689 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4920 16:33:08.570786 MEM_TYPE=3, freq_sel=17
4921 16:33:08.573697 sv_algorithm_assistance_LP4_1600
4922 16:33:08.577398 ============ PULL DRAM RESETB DOWN ============
4923 16:33:08.584066 ========== PULL DRAM RESETB DOWN end =========
4924 16:33:08.587065 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4925 16:33:08.590801 ===================================
4926 16:33:08.593699 LPDDR4 DRAM CONFIGURATION
4927 16:33:08.596963 ===================================
4928 16:33:08.597066 EX_ROW_EN[0] = 0x0
4929 16:33:08.600518 EX_ROW_EN[1] = 0x0
4930 16:33:08.600597 LP4Y_EN = 0x0
4931 16:33:08.603989 WORK_FSP = 0x0
4932 16:33:08.604067 WL = 0x3
4933 16:33:08.607416 RL = 0x3
4934 16:33:08.610281 BL = 0x2
4935 16:33:08.610359 RPST = 0x0
4936 16:33:08.613707 RD_PRE = 0x0
4937 16:33:08.613785 WR_PRE = 0x1
4938 16:33:08.617062 WR_PST = 0x0
4939 16:33:08.617166 DBI_WR = 0x0
4940 16:33:08.620724 DBI_RD = 0x0
4941 16:33:08.620830 OTF = 0x1
4942 16:33:08.623814 ===================================
4943 16:33:08.627498 ===================================
4944 16:33:08.627576 ANA top config
4945 16:33:08.630361 ===================================
4946 16:33:08.633603 DLL_ASYNC_EN = 0
4947 16:33:08.637311 ALL_SLAVE_EN = 1
4948 16:33:08.640386 NEW_RANK_MODE = 1
4949 16:33:08.643913 DLL_IDLE_MODE = 1
4950 16:33:08.644014 LP45_APHY_COMB_EN = 1
4951 16:33:08.647512 TX_ODT_DIS = 1
4952 16:33:08.650371 NEW_8X_MODE = 1
4953 16:33:08.653956 ===================================
4954 16:33:08.656894 ===================================
4955 16:33:08.660529 data_rate = 1866
4956 16:33:08.663433 CKR = 1
4957 16:33:08.663513 DQ_P2S_RATIO = 8
4958 16:33:08.667189 ===================================
4959 16:33:08.670842 CA_P2S_RATIO = 8
4960 16:33:08.673787 DQ_CA_OPEN = 0
4961 16:33:08.677589 DQ_SEMI_OPEN = 0
4962 16:33:08.680600 CA_SEMI_OPEN = 0
4963 16:33:08.683572 CA_FULL_RATE = 0
4964 16:33:08.683667 DQ_CKDIV4_EN = 1
4965 16:33:08.687264 CA_CKDIV4_EN = 1
4966 16:33:08.690293 CA_PREDIV_EN = 0
4967 16:33:08.693866 PH8_DLY = 0
4968 16:33:08.696877 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4969 16:33:08.700578 DQ_AAMCK_DIV = 4
4970 16:33:08.700655 CA_AAMCK_DIV = 4
4971 16:33:08.703465 CA_ADMCK_DIV = 4
4972 16:33:08.707036 DQ_TRACK_CA_EN = 0
4973 16:33:08.710703 CA_PICK = 933
4974 16:33:08.713726 CA_MCKIO = 933
4975 16:33:08.716994 MCKIO_SEMI = 0
4976 16:33:08.720533 PLL_FREQ = 3732
4977 16:33:08.720637 DQ_UI_PI_RATIO = 32
4978 16:33:08.723484 CA_UI_PI_RATIO = 0
4979 16:33:08.726896 ===================================
4980 16:33:08.730386 ===================================
4981 16:33:08.733225 memory_type:LPDDR4
4982 16:33:08.736798 GP_NUM : 10
4983 16:33:08.736944 SRAM_EN : 1
4984 16:33:08.740347 MD32_EN : 0
4985 16:33:08.743222 ===================================
4986 16:33:08.743306 [ANA_INIT] >>>>>>>>>>>>>>
4987 16:33:08.746687 <<<<<< [CONFIGURE PHASE]: ANA_TX
4988 16:33:08.750394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4989 16:33:08.753425 ===================================
4990 16:33:08.756902 data_rate = 1866,PCW = 0X8f00
4991 16:33:08.759906 ===================================
4992 16:33:08.763488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4993 16:33:08.770231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4994 16:33:08.776938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 16:33:08.779890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4996 16:33:08.783584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4997 16:33:08.786586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4998 16:33:08.790324 [ANA_INIT] flow start
4999 16:33:08.790404 [ANA_INIT] PLL >>>>>>>>
5000 16:33:08.793411 [ANA_INIT] PLL <<<<<<<<
5001 16:33:08.796399 [ANA_INIT] MIDPI >>>>>>>>
5002 16:33:08.796477 [ANA_INIT] MIDPI <<<<<<<<
5003 16:33:08.800100 [ANA_INIT] DLL >>>>>>>>
5004 16:33:08.803035 [ANA_INIT] flow end
5005 16:33:08.806708 ============ LP4 DIFF to SE enter ============
5006 16:33:08.810424 ============ LP4 DIFF to SE exit ============
5007 16:33:08.813429 [ANA_INIT] <<<<<<<<<<<<<
5008 16:33:08.816361 [Flow] Enable top DCM control >>>>>
5009 16:33:08.819977 [Flow] Enable top DCM control <<<<<
5010 16:33:08.823559 Enable DLL master slave shuffle
5011 16:33:08.826505 ==============================================================
5012 16:33:08.830110 Gating Mode config
5013 16:33:08.836363 ==============================================================
5014 16:33:08.836447 Config description:
5015 16:33:08.846396 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5016 16:33:08.853407 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5017 16:33:08.856729 SELPH_MODE 0: By rank 1: By Phase
5018 16:33:08.862922 ==============================================================
5019 16:33:08.866313 GAT_TRACK_EN = 1
5020 16:33:08.869736 RX_GATING_MODE = 2
5021 16:33:08.873045 RX_GATING_TRACK_MODE = 2
5022 16:33:08.876532 SELPH_MODE = 1
5023 16:33:08.879591 PICG_EARLY_EN = 1
5024 16:33:08.883293 VALID_LAT_VALUE = 1
5025 16:33:08.886199 ==============================================================
5026 16:33:08.889726 Enter into Gating configuration >>>>
5027 16:33:08.893467 Exit from Gating configuration <<<<
5028 16:33:08.896476 Enter into DVFS_PRE_config >>>>>
5029 16:33:08.906307 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5030 16:33:08.909826 Exit from DVFS_PRE_config <<<<<
5031 16:33:08.912812 Enter into PICG configuration >>>>
5032 16:33:08.916630 Exit from PICG configuration <<<<
5033 16:33:08.919553 [RX_INPUT] configuration >>>>>
5034 16:33:08.923262 [RX_INPUT] configuration <<<<<
5035 16:33:08.929275 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5036 16:33:08.933017 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5037 16:33:08.939408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 16:33:08.946640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 16:33:08.952953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 16:33:08.959242 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 16:33:08.962889 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5042 16:33:08.966479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5043 16:33:08.969161 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5044 16:33:08.976045 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5045 16:33:08.979723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5046 16:33:08.982584 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 16:33:08.985954 ===================================
5048 16:33:08.989516 LPDDR4 DRAM CONFIGURATION
5049 16:33:08.993024 ===================================
5050 16:33:08.993144 EX_ROW_EN[0] = 0x0
5051 16:33:08.995883 EX_ROW_EN[1] = 0x0
5052 16:33:08.999677 LP4Y_EN = 0x0
5053 16:33:08.999749 WORK_FSP = 0x0
5054 16:33:09.002536 WL = 0x3
5055 16:33:09.002605 RL = 0x3
5056 16:33:09.006282 BL = 0x2
5057 16:33:09.006353 RPST = 0x0
5058 16:33:09.009235 RD_PRE = 0x0
5059 16:33:09.009296 WR_PRE = 0x1
5060 16:33:09.012901 WR_PST = 0x0
5061 16:33:09.012962 DBI_WR = 0x0
5062 16:33:09.015847 DBI_RD = 0x0
5063 16:33:09.015967 OTF = 0x1
5064 16:33:09.019477 ===================================
5065 16:33:09.022467 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5066 16:33:09.029183 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5067 16:33:09.032890 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 16:33:09.035948 ===================================
5069 16:33:09.038978 LPDDR4 DRAM CONFIGURATION
5070 16:33:09.042609 ===================================
5071 16:33:09.042687 EX_ROW_EN[0] = 0x10
5072 16:33:09.045537 EX_ROW_EN[1] = 0x0
5073 16:33:09.045637 LP4Y_EN = 0x0
5074 16:33:09.049201 WORK_FSP = 0x0
5075 16:33:09.049278 WL = 0x3
5076 16:33:09.052888 RL = 0x3
5077 16:33:09.055884 BL = 0x2
5078 16:33:09.055976 RPST = 0x0
5079 16:33:09.059414 RD_PRE = 0x0
5080 16:33:09.059491 WR_PRE = 0x1
5081 16:33:09.062278 WR_PST = 0x0
5082 16:33:09.062356 DBI_WR = 0x0
5083 16:33:09.065725 DBI_RD = 0x0
5084 16:33:09.065803 OTF = 0x1
5085 16:33:09.069205 ===================================
5086 16:33:09.075528 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5087 16:33:09.079619 nWR fixed to 30
5088 16:33:09.082519 [ModeRegInit_LP4] CH0 RK0
5089 16:33:09.082596 [ModeRegInit_LP4] CH0 RK1
5090 16:33:09.086202 [ModeRegInit_LP4] CH1 RK0
5091 16:33:09.089767 [ModeRegInit_LP4] CH1 RK1
5092 16:33:09.089864 match AC timing 9
5093 16:33:09.096059 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5094 16:33:09.099353 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5095 16:33:09.102846 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5096 16:33:09.109302 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5097 16:33:09.112972 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5098 16:33:09.113066 ==
5099 16:33:09.115882 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 16:33:09.119409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 16:33:09.119505 ==
5102 16:33:09.125989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 16:33:09.132692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5104 16:33:09.136342 [CA 0] Center 37 (6~68) winsize 63
5105 16:33:09.139311 [CA 1] Center 37 (6~68) winsize 63
5106 16:33:09.143074 [CA 2] Center 34 (4~65) winsize 62
5107 16:33:09.145838 [CA 3] Center 34 (3~65) winsize 63
5108 16:33:09.149449 [CA 4] Center 33 (3~63) winsize 61
5109 16:33:09.152348 [CA 5] Center 32 (2~62) winsize 61
5110 16:33:09.152431
5111 16:33:09.156010 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5112 16:33:09.156090
5113 16:33:09.159019 [CATrainingPosCal] consider 1 rank data
5114 16:33:09.162790 u2DelayCellTimex100 = 270/100 ps
5115 16:33:09.165751 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5116 16:33:09.169426 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5117 16:33:09.172281 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5118 16:33:09.175879 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5119 16:33:09.179465 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5120 16:33:09.182937 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5121 16:33:09.185625
5122 16:33:09.188897 CA PerBit enable=1, Macro0, CA PI delay=32
5123 16:33:09.188974
5124 16:33:09.192468 [CBTSetCACLKResult] CA Dly = 32
5125 16:33:09.192551 CS Dly: 5 (0~36)
5126 16:33:09.192613 ==
5127 16:33:09.195954 Dram Type= 6, Freq= 0, CH_0, rank 1
5128 16:33:09.199326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 16:33:09.199413 ==
5130 16:33:09.205586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5131 16:33:09.212424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5132 16:33:09.215874 [CA 0] Center 37 (7~68) winsize 62
5133 16:33:09.219494 [CA 1] Center 37 (7~68) winsize 62
5134 16:33:09.222465 [CA 2] Center 34 (4~65) winsize 62
5135 16:33:09.226052 [CA 3] Center 34 (4~65) winsize 62
5136 16:33:09.228870 [CA 4] Center 32 (2~63) winsize 62
5137 16:33:09.232598 [CA 5] Center 32 (2~62) winsize 61
5138 16:33:09.232665
5139 16:33:09.235528 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5140 16:33:09.235593
5141 16:33:09.239239 [CATrainingPosCal] consider 2 rank data
5142 16:33:09.242246 u2DelayCellTimex100 = 270/100 ps
5143 16:33:09.245800 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5144 16:33:09.248867 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5145 16:33:09.252497 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5146 16:33:09.255423 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5147 16:33:09.261996 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5148 16:33:09.265829 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5149 16:33:09.265908
5150 16:33:09.268842 CA PerBit enable=1, Macro0, CA PI delay=32
5151 16:33:09.268928
5152 16:33:09.271837 [CBTSetCACLKResult] CA Dly = 32
5153 16:33:09.271899 CS Dly: 5 (0~37)
5154 16:33:09.271953
5155 16:33:09.275587 ----->DramcWriteLeveling(PI) begin...
5156 16:33:09.275672 ==
5157 16:33:09.279123 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 16:33:09.285659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 16:33:09.285756 ==
5160 16:33:09.288581 Write leveling (Byte 0): 34 => 34
5161 16:33:09.288659 Write leveling (Byte 1): 30 => 30
5162 16:33:09.292098 DramcWriteLeveling(PI) end<-----
5163 16:33:09.292177
5164 16:33:09.295812 ==
5165 16:33:09.295891 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 16:33:09.302223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 16:33:09.302317 ==
5168 16:33:09.305740 [Gating] SW mode calibration
5169 16:33:09.312403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5170 16:33:09.315187 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5171 16:33:09.321756 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5172 16:33:09.325118 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 16:33:09.328504 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 16:33:09.335545 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 16:33:09.338542 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 16:33:09.341504 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 16:33:09.348280 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5178 16:33:09.351626 0 14 28 | B1->B0 | 3333 2828 | 1 0 | (1 1) (0 0)
5179 16:33:09.355145 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5180 16:33:09.361762 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 16:33:09.364894 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 16:33:09.368334 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 16:33:09.374965 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 16:33:09.377863 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 16:33:09.381693 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5186 16:33:09.388217 0 15 28 | B1->B0 | 2525 3a39 | 0 1 | (0 0) (0 0)
5187 16:33:09.391276 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5188 16:33:09.394969 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 16:33:09.401246 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 16:33:09.404958 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 16:33:09.407969 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 16:33:09.414458 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 16:33:09.417928 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 16:33:09.421455 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5195 16:33:09.427679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 16:33:09.431110 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 16:33:09.434583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:33:09.440683 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 16:33:09.444078 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 16:33:09.447567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 16:33:09.454307 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 16:33:09.457300 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 16:33:09.461165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 16:33:09.464088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 16:33:09.470938 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 16:33:09.473879 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 16:33:09.477384 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 16:33:09.483963 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 16:33:09.487718 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5210 16:33:09.490719 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5211 16:33:09.497379 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 16:33:09.500872 Total UI for P1: 0, mck2ui 16
5213 16:33:09.503696 best dqsien dly found for B0: ( 1, 2, 26)
5214 16:33:09.507517 Total UI for P1: 0, mck2ui 16
5215 16:33:09.510579 best dqsien dly found for B1: ( 1, 2, 30)
5216 16:33:09.513467 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5217 16:33:09.517049 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5218 16:33:09.517160
5219 16:33:09.520136 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5220 16:33:09.523867 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5221 16:33:09.526879 [Gating] SW calibration Done
5222 16:33:09.526954 ==
5223 16:33:09.530513 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 16:33:09.533465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 16:33:09.533542 ==
5226 16:33:09.537041 RX Vref Scan: 0
5227 16:33:09.537110
5228 16:33:09.537183 RX Vref 0 -> 0, step: 1
5229 16:33:09.540566
5230 16:33:09.540636 RX Delay -80 -> 252, step: 8
5231 16:33:09.547027 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5232 16:33:09.549905 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5233 16:33:09.553444 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5234 16:33:09.556750 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5235 16:33:09.560161 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5236 16:33:09.563697 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5237 16:33:09.570355 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5238 16:33:09.573399 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5239 16:33:09.577136 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5240 16:33:09.580021 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5241 16:33:09.583629 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5242 16:33:09.586662 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5243 16:33:09.593391 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5244 16:33:09.597035 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5245 16:33:09.599961 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5246 16:33:09.603802 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5247 16:33:09.603875 ==
5248 16:33:09.606899 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 16:33:09.610558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 16:33:09.613354 ==
5251 16:33:09.613423 DQS Delay:
5252 16:33:09.613516 DQS0 = 0, DQS1 = 0
5253 16:33:09.616930 DQM Delay:
5254 16:33:09.617005 DQM0 = 104, DQM1 = 95
5255 16:33:09.620435 DQ Delay:
5256 16:33:09.623447 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5257 16:33:09.627041 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5258 16:33:09.630103 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5259 16:33:09.633923 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5260 16:33:09.634000
5261 16:33:09.634060
5262 16:33:09.634115 ==
5263 16:33:09.636734 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 16:33:09.639815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 16:33:09.639882 ==
5266 16:33:09.639936
5267 16:33:09.639988
5268 16:33:09.643472 TX Vref Scan disable
5269 16:33:09.643550 == TX Byte 0 ==
5270 16:33:09.650413 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5271 16:33:09.653377 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5272 16:33:09.653479 == TX Byte 1 ==
5273 16:33:09.660035 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5274 16:33:09.663651 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5275 16:33:09.663730 ==
5276 16:33:09.666465 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 16:33:09.670081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 16:33:09.670158 ==
5279 16:33:09.673493
5280 16:33:09.673599
5281 16:33:09.673694 TX Vref Scan disable
5282 16:33:09.676371 == TX Byte 0 ==
5283 16:33:09.680129 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5284 16:33:09.683052 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5285 16:33:09.686826 == TX Byte 1 ==
5286 16:33:09.690378 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5287 16:33:09.693388 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5288 16:33:09.696512
5289 16:33:09.696587 [DATLAT]
5290 16:33:09.696646 Freq=933, CH0 RK0
5291 16:33:09.696702
5292 16:33:09.700259 DATLAT Default: 0xd
5293 16:33:09.700336 0, 0xFFFF, sum = 0
5294 16:33:09.709571 1, 0xFFFF, sum = 0
5295 16:33:09.709710 2, 0xFFFF, sum = 0
5296 16:33:09.709793 3, 0xFFFF, sum = 0
5297 16:33:09.709865 4, 0xFFFF, sum = 0
5298 16:33:09.710118 5, 0xFFFF, sum = 0
5299 16:33:09.713376 6, 0xFFFF, sum = 0
5300 16:33:09.713446 7, 0xFFFF, sum = 0
5301 16:33:09.716348 8, 0xFFFF, sum = 0
5302 16:33:09.716430 9, 0xFFFF, sum = 0
5303 16:33:09.719827 10, 0x0, sum = 1
5304 16:33:09.719916 11, 0x0, sum = 2
5305 16:33:09.719992 12, 0x0, sum = 3
5306 16:33:09.723356 13, 0x0, sum = 4
5307 16:33:09.723429 best_step = 11
5308 16:33:09.723503
5309 16:33:09.726817 ==
5310 16:33:09.726890 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 16:33:09.733140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 16:33:09.733219 ==
5313 16:33:09.733298 RX Vref Scan: 1
5314 16:33:09.733387
5315 16:33:09.736751 RX Vref 0 -> 0, step: 1
5316 16:33:09.736826
5317 16:33:09.739769 RX Delay -45 -> 252, step: 4
5318 16:33:09.739845
5319 16:33:09.743445 Set Vref, RX VrefLevel [Byte0]: 57
5320 16:33:09.746448 [Byte1]: 50
5321 16:33:09.746524
5322 16:33:09.749416 Final RX Vref Byte 0 = 57 to rank0
5323 16:33:09.753036 Final RX Vref Byte 1 = 50 to rank0
5324 16:33:09.756726 Final RX Vref Byte 0 = 57 to rank1
5325 16:33:09.759387 Final RX Vref Byte 1 = 50 to rank1==
5326 16:33:09.763041 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 16:33:09.766519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 16:33:09.766599 ==
5329 16:33:09.769457 DQS Delay:
5330 16:33:09.769563 DQS0 = 0, DQS1 = 0
5331 16:33:09.773119 DQM Delay:
5332 16:33:09.773224 DQM0 = 104, DQM1 = 95
5333 16:33:09.773328 DQ Delay:
5334 16:33:09.779671 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5335 16:33:09.783048 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5336 16:33:09.785958 DQ8 =88, DQ9 =84, DQ10 =96, DQ11 =92
5337 16:33:09.789642 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5338 16:33:09.789726
5339 16:33:09.789793
5340 16:33:09.796115 [DQSOSCAuto] RK0, (LSB)MR18= 0x3027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5341 16:33:09.799156 CH0 RK0: MR19=505, MR18=3027
5342 16:33:09.805848 CH0_RK0: MR19=0x505, MR18=0x3027, DQSOSC=406, MR23=63, INC=65, DEC=43
5343 16:33:09.805949
5344 16:33:09.809652 ----->DramcWriteLeveling(PI) begin...
5345 16:33:09.809728 ==
5346 16:33:09.812382 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 16:33:09.816015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 16:33:09.816103 ==
5349 16:33:09.818973 Write leveling (Byte 0): 32 => 32
5350 16:33:09.822670 Write leveling (Byte 1): 29 => 29
5351 16:33:09.825641 DramcWriteLeveling(PI) end<-----
5352 16:33:09.825739
5353 16:33:09.825825 ==
5354 16:33:09.829228 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 16:33:09.832203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 16:33:09.835908 ==
5357 16:33:09.835978 [Gating] SW mode calibration
5358 16:33:09.842651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5359 16:33:09.849017 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5360 16:33:09.852037 0 14 0 | B1->B0 | 3434 3333 | 0 0 | (0 0) (1 1)
5361 16:33:09.858723 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 16:33:09.862499 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 16:33:09.865995 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 16:33:09.872154 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 16:33:09.875669 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 16:33:09.878596 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5367 16:33:09.885888 0 14 28 | B1->B0 | 2b2b 2e2e | 0 0 | (0 1) (0 1)
5368 16:33:09.888610 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5369 16:33:09.892253 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 16:33:09.898806 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 16:33:09.902490 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 16:33:09.905248 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 16:33:09.911915 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 16:33:09.915684 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5375 16:33:09.918601 0 15 28 | B1->B0 | 3939 3636 | 0 1 | (0 0) (0 0)
5376 16:33:09.925239 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 16:33:09.928872 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:33:09.931731 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 16:33:09.935438 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 16:33:09.942482 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 16:33:09.945394 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 16:33:09.949011 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5383 16:33:09.955662 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 16:33:09.958533 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 16:33:09.961582 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 16:33:09.968895 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:33:09.971864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:33:09.975396 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 16:33:09.981925 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 16:33:09.985430 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 16:33:09.988800 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 16:33:09.995248 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 16:33:09.998852 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 16:33:10.001642 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 16:33:10.008730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 16:33:10.011787 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 16:33:10.015480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 16:33:10.021431 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 16:33:10.025272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5400 16:33:10.028187 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5401 16:33:10.031731 Total UI for P1: 0, mck2ui 16
5402 16:33:10.034625 best dqsien dly found for B1: ( 1, 2, 30)
5403 16:33:10.041339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 16:33:10.041422 Total UI for P1: 0, mck2ui 16
5405 16:33:10.045106 best dqsien dly found for B0: ( 1, 2, 30)
5406 16:33:10.051595 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5407 16:33:10.054657 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5408 16:33:10.054747
5409 16:33:10.058346 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5410 16:33:10.061926 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5411 16:33:10.064841 [Gating] SW calibration Done
5412 16:33:10.064926 ==
5413 16:33:10.068562 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 16:33:10.071616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 16:33:10.071715 ==
5416 16:33:10.074596 RX Vref Scan: 0
5417 16:33:10.074695
5418 16:33:10.074782 RX Vref 0 -> 0, step: 1
5419 16:33:10.074874
5420 16:33:10.078337 RX Delay -80 -> 252, step: 8
5421 16:33:10.081333 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5422 16:33:10.088090 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5423 16:33:10.091706 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5424 16:33:10.094538 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5425 16:33:10.098035 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5426 16:33:10.101406 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5427 16:33:10.104496 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5428 16:33:10.111566 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5429 16:33:10.114778 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5430 16:33:10.117683 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5431 16:33:10.121056 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5432 16:33:10.124895 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5433 16:33:10.127913 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5434 16:33:10.134886 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5435 16:33:10.137947 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5436 16:33:10.141600 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5437 16:33:10.141681 ==
5438 16:33:10.144536 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 16:33:10.148411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 16:33:10.148511 ==
5441 16:33:10.151460 DQS Delay:
5442 16:33:10.151556 DQS0 = 0, DQS1 = 0
5443 16:33:10.151651 DQM Delay:
5444 16:33:10.154479 DQM0 = 104, DQM1 = 94
5445 16:33:10.154574 DQ Delay:
5446 16:33:10.158122 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5447 16:33:10.160945 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5448 16:33:10.164726 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =87
5449 16:33:10.167859 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5450 16:33:10.171406
5451 16:33:10.171511
5452 16:33:10.171597 ==
5453 16:33:10.174390 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 16:33:10.178165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 16:33:10.178261 ==
5456 16:33:10.178349
5457 16:33:10.178431
5458 16:33:10.181309 TX Vref Scan disable
5459 16:33:10.181402 == TX Byte 0 ==
5460 16:33:10.187989 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5461 16:33:10.190970 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5462 16:33:10.191068 == TX Byte 1 ==
5463 16:33:10.197988 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5464 16:33:10.200990 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5465 16:33:10.201092 ==
5466 16:33:10.204742 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 16:33:10.207784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 16:33:10.207883 ==
5469 16:33:10.207970
5470 16:33:10.208053
5471 16:33:10.210654 TX Vref Scan disable
5472 16:33:10.214286 == TX Byte 0 ==
5473 16:33:10.217684 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5474 16:33:10.221102 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5475 16:33:10.224544 == TX Byte 1 ==
5476 16:33:10.228036 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5477 16:33:10.230827 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5478 16:33:10.230914
5479 16:33:10.234563 [DATLAT]
5480 16:33:10.234651 Freq=933, CH0 RK1
5481 16:33:10.234712
5482 16:33:10.238097 DATLAT Default: 0xb
5483 16:33:10.238177 0, 0xFFFF, sum = 0
5484 16:33:10.241004 1, 0xFFFF, sum = 0
5485 16:33:10.241111 2, 0xFFFF, sum = 0
5486 16:33:10.244003 3, 0xFFFF, sum = 0
5487 16:33:10.244098 4, 0xFFFF, sum = 0
5488 16:33:10.247701 5, 0xFFFF, sum = 0
5489 16:33:10.247768 6, 0xFFFF, sum = 0
5490 16:33:10.250645 7, 0xFFFF, sum = 0
5491 16:33:10.250737 8, 0xFFFF, sum = 0
5492 16:33:10.254363 9, 0xFFFF, sum = 0
5493 16:33:10.254456 10, 0x0, sum = 1
5494 16:33:10.257195 11, 0x0, sum = 2
5495 16:33:10.257290 12, 0x0, sum = 3
5496 16:33:10.260880 13, 0x0, sum = 4
5497 16:33:10.260976 best_step = 11
5498 16:33:10.261058
5499 16:33:10.261140 ==
5500 16:33:10.264517 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 16:33:10.270695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 16:33:10.270791 ==
5503 16:33:10.270875 RX Vref Scan: 0
5504 16:33:10.270957
5505 16:33:10.274554 RX Vref 0 -> 0, step: 1
5506 16:33:10.274652
5507 16:33:10.277494 RX Delay -45 -> 252, step: 4
5508 16:33:10.281224 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5509 16:33:10.284039 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5510 16:33:10.290922 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5511 16:33:10.294552 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5512 16:33:10.297721 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5513 16:33:10.300714 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5514 16:33:10.303889 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5515 16:33:10.310590 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5516 16:33:10.314505 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5517 16:33:10.317466 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5518 16:33:10.320394 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5519 16:33:10.324023 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5520 16:33:10.327096 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5521 16:33:10.334298 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5522 16:33:10.337329 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5523 16:33:10.340847 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5524 16:33:10.340917 ==
5525 16:33:10.343722 Dram Type= 6, Freq= 0, CH_0, rank 1
5526 16:33:10.347375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 16:33:10.350645 ==
5528 16:33:10.350740 DQS Delay:
5529 16:33:10.350824 DQS0 = 0, DQS1 = 0
5530 16:33:10.353715 DQM Delay:
5531 16:33:10.353789 DQM0 = 104, DQM1 = 94
5532 16:33:10.357076 DQ Delay:
5533 16:33:10.360311 DQ0 =102, DQ1 =104, DQ2 =100, DQ3 =100
5534 16:33:10.363705 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5535 16:33:10.367059 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =88
5536 16:33:10.370494 DQ12 =98, DQ13 =100, DQ14 =104, DQ15 =104
5537 16:33:10.370596
5538 16:33:10.370681
5539 16:33:10.376985 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5540 16:33:10.380028 CH0 RK1: MR19=505, MR18=2E06
5541 16:33:10.386663 CH0_RK1: MR19=0x505, MR18=0x2E06, DQSOSC=407, MR23=63, INC=65, DEC=43
5542 16:33:10.390262 [RxdqsGatingPostProcess] freq 933
5543 16:33:10.393915 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5544 16:33:10.396759 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 16:33:10.400565 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 16:33:10.403495 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 16:33:10.406443 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 16:33:10.410063 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 16:33:10.413841 best DQS1 dly(2T, 0.5T) = (0, 10)
5550 16:33:10.416796 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 16:33:10.419828 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5552 16:33:10.423425 Pre-setting of DQS Precalculation
5553 16:33:10.427029 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5554 16:33:10.429948 ==
5555 16:33:10.433434 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 16:33:10.436875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 16:33:10.436973 ==
5558 16:33:10.440329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 16:33:10.446413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5560 16:33:10.450207 [CA 0] Center 36 (6~67) winsize 62
5561 16:33:10.453888 [CA 1] Center 37 (7~68) winsize 62
5562 16:33:10.456714 [CA 2] Center 34 (4~65) winsize 62
5563 16:33:10.460291 [CA 3] Center 34 (4~65) winsize 62
5564 16:33:10.463734 [CA 4] Center 34 (4~65) winsize 62
5565 16:33:10.467046 [CA 5] Center 33 (3~64) winsize 62
5566 16:33:10.467121
5567 16:33:10.470676 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5568 16:33:10.470758
5569 16:33:10.473991 [CATrainingPosCal] consider 1 rank data
5570 16:33:10.476696 u2DelayCellTimex100 = 270/100 ps
5571 16:33:10.480267 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5572 16:33:10.483672 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5573 16:33:10.489999 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 16:33:10.493461 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5575 16:33:10.497105 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 16:33:10.500623 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5577 16:33:10.500773
5578 16:33:10.503582 CA PerBit enable=1, Macro0, CA PI delay=33
5579 16:33:10.503703
5580 16:33:10.507365 [CBTSetCACLKResult] CA Dly = 33
5581 16:33:10.507469 CS Dly: 7 (0~38)
5582 16:33:10.507556 ==
5583 16:33:10.510351 Dram Type= 6, Freq= 0, CH_1, rank 1
5584 16:33:10.516912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 16:33:10.517017 ==
5586 16:33:10.520600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5587 16:33:10.527354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5588 16:33:10.530414 [CA 0] Center 36 (6~67) winsize 62
5589 16:33:10.533921 [CA 1] Center 37 (7~68) winsize 62
5590 16:33:10.536817 [CA 2] Center 35 (5~65) winsize 61
5591 16:33:10.540610 [CA 3] Center 34 (4~65) winsize 62
5592 16:33:10.543628 [CA 4] Center 34 (4~65) winsize 62
5593 16:33:10.547199 [CA 5] Center 33 (3~64) winsize 62
5594 16:33:10.547295
5595 16:33:10.550049 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5596 16:33:10.550143
5597 16:33:10.553097 [CATrainingPosCal] consider 2 rank data
5598 16:33:10.556942 u2DelayCellTimex100 = 270/100 ps
5599 16:33:10.559896 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5600 16:33:10.563653 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5601 16:33:10.570020 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5602 16:33:10.573821 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5603 16:33:10.576783 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5604 16:33:10.580349 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5605 16:33:10.580444
5606 16:33:10.583121 CA PerBit enable=1, Macro0, CA PI delay=33
5607 16:33:10.583190
5608 16:33:10.586683 [CBTSetCACLKResult] CA Dly = 33
5609 16:33:10.586805 CS Dly: 8 (0~40)
5610 16:33:10.590349
5611 16:33:10.593259 ----->DramcWriteLeveling(PI) begin...
5612 16:33:10.593365 ==
5613 16:33:10.596695 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 16:33:10.600228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 16:33:10.600324 ==
5616 16:33:10.603617 Write leveling (Byte 0): 25 => 25
5617 16:33:10.606346 Write leveling (Byte 1): 29 => 29
5618 16:33:10.609613 DramcWriteLeveling(PI) end<-----
5619 16:33:10.609688
5620 16:33:10.609750 ==
5621 16:33:10.613540 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 16:33:10.616726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 16:33:10.616817 ==
5624 16:33:10.619892 [Gating] SW mode calibration
5625 16:33:10.626856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5626 16:33:10.633424 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5627 16:33:10.636482 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 16:33:10.640110 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 16:33:10.646813 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 16:33:10.649765 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 16:33:10.653325 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 16:33:10.659805 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 16:33:10.662801 0 14 24 | B1->B0 | 3333 2727 | 0 0 | (1 0) (0 0)
5634 16:33:10.666567 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5635 16:33:10.673220 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 16:33:10.676054 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 16:33:10.679840 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 16:33:10.682781 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 16:33:10.689630 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 16:33:10.693269 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 16:33:10.696194 0 15 24 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
5642 16:33:10.702874 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5643 16:33:10.706567 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 16:33:10.709536 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 16:33:10.716194 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 16:33:10.719783 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 16:33:10.722770 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 16:33:10.729706 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 16:33:10.733245 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5650 16:33:10.736053 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5651 16:33:10.742625 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:33:10.746034 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:33:10.749348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:33:10.756376 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 16:33:10.759361 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 16:33:10.763187 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 16:33:10.769542 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 16:33:10.772527 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 16:33:10.776460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 16:33:10.782663 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 16:33:10.785675 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 16:33:10.789626 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 16:33:10.795648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 16:33:10.799387 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 16:33:10.802840 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5666 16:33:10.809457 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 16:33:10.809564 Total UI for P1: 0, mck2ui 16
5668 16:33:10.812471 best dqsien dly found for B0: ( 1, 2, 24)
5669 16:33:10.816053 Total UI for P1: 0, mck2ui 16
5670 16:33:10.819071 best dqsien dly found for B1: ( 1, 2, 24)
5671 16:33:10.822633 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5672 16:33:10.829468 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5673 16:33:10.829575
5674 16:33:10.832442 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5675 16:33:10.835610 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5676 16:33:10.839245 [Gating] SW calibration Done
5677 16:33:10.839326 ==
5678 16:33:10.842277 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 16:33:10.845905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 16:33:10.845978 ==
5681 16:33:10.848960 RX Vref Scan: 0
5682 16:33:10.849055
5683 16:33:10.849146 RX Vref 0 -> 0, step: 1
5684 16:33:10.849247
5685 16:33:10.851964 RX Delay -80 -> 252, step: 8
5686 16:33:10.855765 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5687 16:33:10.858798 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5688 16:33:10.865783 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5689 16:33:10.869208 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5690 16:33:10.872463 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5691 16:33:10.875680 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5692 16:33:10.878953 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5693 16:33:10.882089 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5694 16:33:10.888934 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5695 16:33:10.892146 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5696 16:33:10.895390 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5697 16:33:10.898779 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5698 16:33:10.902827 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5699 16:33:10.905619 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5700 16:33:10.912140 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5701 16:33:10.915883 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5702 16:33:10.915954 ==
5703 16:33:10.918947 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 16:33:10.922693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 16:33:10.922790 ==
5706 16:33:10.925570 DQS Delay:
5707 16:33:10.925743 DQS0 = 0, DQS1 = 0
5708 16:33:10.925849 DQM Delay:
5709 16:33:10.929221 DQM0 = 102, DQM1 = 98
5710 16:33:10.929323 DQ Delay:
5711 16:33:10.932284 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5712 16:33:10.935424 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5713 16:33:10.939152 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5714 16:33:10.942169 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5715 16:33:10.942269
5716 16:33:10.945119
5717 16:33:10.945217 ==
5718 16:33:10.948835 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 16:33:10.951818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 16:33:10.951919 ==
5721 16:33:10.952015
5722 16:33:10.952101
5723 16:33:10.955454 TX Vref Scan disable
5724 16:33:10.955546 == TX Byte 0 ==
5725 16:33:10.962207 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 16:33:10.965303 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 16:33:10.965402 == TX Byte 1 ==
5728 16:33:10.971944 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5729 16:33:10.975102 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5730 16:33:10.975196 ==
5731 16:33:10.978170 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 16:33:10.981842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 16:33:10.981914 ==
5734 16:33:10.981972
5735 16:33:10.982027
5736 16:33:10.985292 TX Vref Scan disable
5737 16:33:10.988234 == TX Byte 0 ==
5738 16:33:10.991868 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5739 16:33:10.994886 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5740 16:33:10.998299 == TX Byte 1 ==
5741 16:33:11.001916 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5742 16:33:11.004735 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5743 16:33:11.004813
5744 16:33:11.008276 [DATLAT]
5745 16:33:11.008353 Freq=933, CH1 RK0
5746 16:33:11.008413
5747 16:33:11.011681 DATLAT Default: 0xd
5748 16:33:11.011778 0, 0xFFFF, sum = 0
5749 16:33:11.014991 1, 0xFFFF, sum = 0
5750 16:33:11.015065 2, 0xFFFF, sum = 0
5751 16:33:11.018351 3, 0xFFFF, sum = 0
5752 16:33:11.018422 4, 0xFFFF, sum = 0
5753 16:33:11.021869 5, 0xFFFF, sum = 0
5754 16:33:11.021940 6, 0xFFFF, sum = 0
5755 16:33:11.024899 7, 0xFFFF, sum = 0
5756 16:33:11.024973 8, 0xFFFF, sum = 0
5757 16:33:11.027840 9, 0xFFFF, sum = 0
5758 16:33:11.027913 10, 0x0, sum = 1
5759 16:33:11.031800 11, 0x0, sum = 2
5760 16:33:11.031900 12, 0x0, sum = 3
5761 16:33:11.034624 13, 0x0, sum = 4
5762 16:33:11.034694 best_step = 11
5763 16:33:11.034751
5764 16:33:11.034804 ==
5765 16:33:11.038130 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 16:33:11.044824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 16:33:11.044919 ==
5768 16:33:11.045003 RX Vref Scan: 1
5769 16:33:11.045084
5770 16:33:11.047846 RX Vref 0 -> 0, step: 1
5771 16:33:11.047938
5772 16:33:11.051655 RX Delay -45 -> 252, step: 4
5773 16:33:11.051723
5774 16:33:11.054667 Set Vref, RX VrefLevel [Byte0]: 54
5775 16:33:11.058301 [Byte1]: 50
5776 16:33:11.058376
5777 16:33:11.061154 Final RX Vref Byte 0 = 54 to rank0
5778 16:33:11.064977 Final RX Vref Byte 1 = 50 to rank0
5779 16:33:11.068040 Final RX Vref Byte 0 = 54 to rank1
5780 16:33:11.071079 Final RX Vref Byte 1 = 50 to rank1==
5781 16:33:11.074840 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 16:33:11.077787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 16:33:11.077860 ==
5784 16:33:11.081507 DQS Delay:
5785 16:33:11.081639 DQS0 = 0, DQS1 = 0
5786 16:33:11.081722 DQM Delay:
5787 16:33:11.084447 DQM0 = 103, DQM1 = 98
5788 16:33:11.084515 DQ Delay:
5789 16:33:11.087939 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5790 16:33:11.091474 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5791 16:33:11.094460 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5792 16:33:11.101022 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =106
5793 16:33:11.101122
5794 16:33:11.101207
5795 16:33:11.107471 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5796 16:33:11.111305 CH1 RK0: MR19=505, MR18=172F
5797 16:33:11.118024 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5798 16:33:11.118098
5799 16:33:11.120891 ----->DramcWriteLeveling(PI) begin...
5800 16:33:11.120959 ==
5801 16:33:11.124560 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 16:33:11.127475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 16:33:11.127567 ==
5804 16:33:11.131065 Write leveling (Byte 0): 28 => 28
5805 16:33:11.134497 Write leveling (Byte 1): 29 => 29
5806 16:33:11.137297 DramcWriteLeveling(PI) end<-----
5807 16:33:11.137389
5808 16:33:11.137471 ==
5809 16:33:11.140708 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 16:33:11.144261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 16:33:11.144350 ==
5812 16:33:11.147677 [Gating] SW mode calibration
5813 16:33:11.154076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5814 16:33:11.160709 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5815 16:33:11.163992 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 16:33:11.167246 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 16:33:11.174382 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 16:33:11.177249 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 16:33:11.181005 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 16:33:11.187849 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 16:33:11.190829 0 14 24 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (1 1)
5822 16:33:11.194415 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5823 16:33:11.201244 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 16:33:11.204241 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 16:33:11.207183 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 16:33:11.214466 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 16:33:11.217413 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 16:33:11.220379 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 16:33:11.227181 0 15 24 | B1->B0 | 3838 2828 | 0 0 | (0 0) (0 0)
5830 16:33:11.230917 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5831 16:33:11.233926 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 16:33:11.240688 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 16:33:11.243739 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 16:33:11.247261 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 16:33:11.254054 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 16:33:11.257495 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 16:33:11.260343 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 16:33:11.266942 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5839 16:33:11.270559 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5840 16:33:11.273995 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 16:33:11.280097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:33:11.283733 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:33:11.287151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 16:33:11.293328 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 16:33:11.296664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 16:33:11.300288 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 16:33:11.303952 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 16:33:11.310565 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 16:33:11.313658 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 16:33:11.317358 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 16:33:11.323918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 16:33:11.326835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 16:33:11.329849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 16:33:11.336672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5855 16:33:11.339871 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 16:33:11.343698 Total UI for P1: 0, mck2ui 16
5857 16:33:11.346655 best dqsien dly found for B0: ( 1, 2, 28)
5858 16:33:11.350321 Total UI for P1: 0, mck2ui 16
5859 16:33:11.353390 best dqsien dly found for B1: ( 1, 2, 28)
5860 16:33:11.356403 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5861 16:33:11.360186 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5862 16:33:11.360258
5863 16:33:11.363761 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5864 16:33:11.366815 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5865 16:33:11.369735 [Gating] SW calibration Done
5866 16:33:11.369835 ==
5867 16:33:11.373435 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 16:33:11.380163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 16:33:11.380240 ==
5870 16:33:11.380303 RX Vref Scan: 0
5871 16:33:11.380360
5872 16:33:11.383018 RX Vref 0 -> 0, step: 1
5873 16:33:11.383109
5874 16:33:11.386517 RX Delay -80 -> 252, step: 8
5875 16:33:11.390031 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5876 16:33:11.392999 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5877 16:33:11.396688 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5878 16:33:11.399782 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5879 16:33:11.403337 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5880 16:33:11.409670 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5881 16:33:11.413139 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5882 16:33:11.416374 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5883 16:33:11.419540 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5884 16:33:11.423352 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5885 16:33:11.429863 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5886 16:33:11.432900 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5887 16:33:11.436662 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5888 16:33:11.439427 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5889 16:33:11.443144 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5890 16:33:11.449235 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5891 16:33:11.449331 ==
5892 16:33:11.452864 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 16:33:11.455902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 16:33:11.455998 ==
5895 16:33:11.456068 DQS Delay:
5896 16:33:11.459728 DQS0 = 0, DQS1 = 0
5897 16:33:11.459847 DQM Delay:
5898 16:33:11.462690 DQM0 = 102, DQM1 = 99
5899 16:33:11.462809 DQ Delay:
5900 16:33:11.465756 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5901 16:33:11.469490 DQ4 =95, DQ5 =111, DQ6 =115, DQ7 =99
5902 16:33:11.472369 DQ8 =83, DQ9 =91, DQ10 =103, DQ11 =91
5903 16:33:11.475865 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5904 16:33:11.475980
5905 16:33:11.476042
5906 16:33:11.476110 ==
5907 16:33:11.478951 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 16:33:11.485599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 16:33:11.485724 ==
5910 16:33:11.485788
5911 16:33:11.485844
5912 16:33:11.485897 TX Vref Scan disable
5913 16:33:11.489209 == TX Byte 0 ==
5914 16:33:11.492806 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5915 16:33:11.495793 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5916 16:33:11.499461 == TX Byte 1 ==
5917 16:33:11.503081 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5918 16:33:11.509384 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5919 16:33:11.509508 ==
5920 16:33:11.512388 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 16:33:11.516144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 16:33:11.516274 ==
5923 16:33:11.516375
5924 16:33:11.516465
5925 16:33:11.519222 TX Vref Scan disable
5926 16:33:11.519336 == TX Byte 0 ==
5927 16:33:11.525717 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 16:33:11.529232 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 16:33:11.529308 == TX Byte 1 ==
5930 16:33:11.535955 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5931 16:33:11.539346 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5932 16:33:11.539422
5933 16:33:11.539509 [DATLAT]
5934 16:33:11.542775 Freq=933, CH1 RK1
5935 16:33:11.542848
5936 16:33:11.542911 DATLAT Default: 0xb
5937 16:33:11.545945 0, 0xFFFF, sum = 0
5938 16:33:11.546019 1, 0xFFFF, sum = 0
5939 16:33:11.549509 2, 0xFFFF, sum = 0
5940 16:33:11.549590 3, 0xFFFF, sum = 0
5941 16:33:11.552437 4, 0xFFFF, sum = 0
5942 16:33:11.552509 5, 0xFFFF, sum = 0
5943 16:33:11.556198 6, 0xFFFF, sum = 0
5944 16:33:11.556273 7, 0xFFFF, sum = 0
5945 16:33:11.559008 8, 0xFFFF, sum = 0
5946 16:33:11.562737 9, 0xFFFF, sum = 0
5947 16:33:11.562811 10, 0x0, sum = 1
5948 16:33:11.562873 11, 0x0, sum = 2
5949 16:33:11.565859 12, 0x0, sum = 3
5950 16:33:11.565932 13, 0x0, sum = 4
5951 16:33:11.568940 best_step = 11
5952 16:33:11.569010
5953 16:33:11.569068 ==
5954 16:33:11.572644 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 16:33:11.575716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 16:33:11.575787 ==
5957 16:33:11.579309 RX Vref Scan: 0
5958 16:33:11.579408
5959 16:33:11.579493 RX Vref 0 -> 0, step: 1
5960 16:33:11.579577
5961 16:33:11.582166 RX Delay -53 -> 252, step: 4
5962 16:33:11.589944 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5963 16:33:11.592833 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5964 16:33:11.596688 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5965 16:33:11.599914 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5966 16:33:11.602889 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5967 16:33:11.609521 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5968 16:33:11.612765 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5969 16:33:11.616349 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5970 16:33:11.619777 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5971 16:33:11.622792 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5972 16:33:11.629664 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5973 16:33:11.632690 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5974 16:33:11.635708 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5975 16:33:11.639364 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5976 16:33:11.643053 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5977 16:33:11.649019 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5978 16:33:11.649098 ==
5979 16:33:11.652614 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 16:33:11.656240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 16:33:11.656322 ==
5982 16:33:11.656383 DQS Delay:
5983 16:33:11.658989 DQS0 = 0, DQS1 = 0
5984 16:33:11.659057 DQM Delay:
5985 16:33:11.662323 DQM0 = 105, DQM1 = 99
5986 16:33:11.662421 DQ Delay:
5987 16:33:11.665682 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5988 16:33:11.669352 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5989 16:33:11.672165 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =94
5990 16:33:11.675839 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5991 16:33:11.675932
5992 16:33:11.675996
5993 16:33:11.685683 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5994 16:33:11.689315 CH1 RK1: MR19=505, MR18=2F02
5995 16:33:11.692158 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5996 16:33:11.695707 [RxdqsGatingPostProcess] freq 933
5997 16:33:11.702643 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5998 16:33:11.705691 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 16:33:11.708799 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 16:33:11.712462 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 16:33:11.715612 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 16:33:11.719346 best DQS0 dly(2T, 0.5T) = (0, 10)
6003 16:33:11.722111 best DQS1 dly(2T, 0.5T) = (0, 10)
6004 16:33:11.725613 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6005 16:33:11.729142 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6006 16:33:11.732047 Pre-setting of DQS Precalculation
6007 16:33:11.735905 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6008 16:33:11.742502 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6009 16:33:11.749134 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6010 16:33:11.749224
6011 16:33:11.749285
6012 16:33:11.752231 [Calibration Summary] 1866 Mbps
6013 16:33:11.755784 CH 0, Rank 0
6014 16:33:11.755864 SW Impedance : PASS
6015 16:33:11.759476 DUTY Scan : NO K
6016 16:33:11.762445 ZQ Calibration : PASS
6017 16:33:11.762524 Jitter Meter : NO K
6018 16:33:11.765561 CBT Training : PASS
6019 16:33:11.765640 Write leveling : PASS
6020 16:33:11.769270 RX DQS gating : PASS
6021 16:33:11.772791 RX DQ/DQS(RDDQC) : PASS
6022 16:33:11.772868 TX DQ/DQS : PASS
6023 16:33:11.775796 RX DATLAT : PASS
6024 16:33:11.779185 RX DQ/DQS(Engine): PASS
6025 16:33:11.779262 TX OE : NO K
6026 16:33:11.782543 All Pass.
6027 16:33:11.782619
6028 16:33:11.782677 CH 0, Rank 1
6029 16:33:11.785687 SW Impedance : PASS
6030 16:33:11.785760 DUTY Scan : NO K
6031 16:33:11.788848 ZQ Calibration : PASS
6032 16:33:11.792187 Jitter Meter : NO K
6033 16:33:11.792283 CBT Training : PASS
6034 16:33:11.795484 Write leveling : PASS
6035 16:33:11.798972 RX DQS gating : PASS
6036 16:33:11.799054 RX DQ/DQS(RDDQC) : PASS
6037 16:33:11.802538 TX DQ/DQS : PASS
6038 16:33:11.805355 RX DATLAT : PASS
6039 16:33:11.805436 RX DQ/DQS(Engine): PASS
6040 16:33:11.808797 TX OE : NO K
6041 16:33:11.808870 All Pass.
6042 16:33:11.808929
6043 16:33:11.812307 CH 1, Rank 0
6044 16:33:11.812383 SW Impedance : PASS
6045 16:33:11.815875 DUTY Scan : NO K
6046 16:33:11.818803 ZQ Calibration : PASS
6047 16:33:11.818875 Jitter Meter : NO K
6048 16:33:11.822545 CBT Training : PASS
6049 16:33:11.822618 Write leveling : PASS
6050 16:33:11.825565 RX DQS gating : PASS
6051 16:33:11.828487 RX DQ/DQS(RDDQC) : PASS
6052 16:33:11.828566 TX DQ/DQS : PASS
6053 16:33:11.832182 RX DATLAT : PASS
6054 16:33:11.835638 RX DQ/DQS(Engine): PASS
6055 16:33:11.835733 TX OE : NO K
6056 16:33:11.838593 All Pass.
6057 16:33:11.838681
6058 16:33:11.838751 CH 1, Rank 1
6059 16:33:11.842134 SW Impedance : PASS
6060 16:33:11.842220 DUTY Scan : NO K
6061 16:33:11.845828 ZQ Calibration : PASS
6062 16:33:11.848721 Jitter Meter : NO K
6063 16:33:11.848815 CBT Training : PASS
6064 16:33:11.852366 Write leveling : PASS
6065 16:33:11.855363 RX DQS gating : PASS
6066 16:33:11.855434 RX DQ/DQS(RDDQC) : PASS
6067 16:33:11.858975 TX DQ/DQS : PASS
6068 16:33:11.862024 RX DATLAT : PASS
6069 16:33:11.862105 RX DQ/DQS(Engine): PASS
6070 16:33:11.865056 TX OE : NO K
6071 16:33:11.865141 All Pass.
6072 16:33:11.865203
6073 16:33:11.868867 DramC Write-DBI off
6074 16:33:11.871879 PER_BANK_REFRESH: Hybrid Mode
6075 16:33:11.871959 TX_TRACKING: ON
6076 16:33:11.882240 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6077 16:33:11.885150 [FAST_K] Save calibration result to emmc
6078 16:33:11.888820 dramc_set_vcore_voltage set vcore to 650000
6079 16:33:11.891741 Read voltage for 400, 6
6080 16:33:11.891859 Vio18 = 0
6081 16:33:11.891948 Vcore = 650000
6082 16:33:11.895393 Vdram = 0
6083 16:33:11.895473 Vddq = 0
6084 16:33:11.895535 Vmddr = 0
6085 16:33:11.901556 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6086 16:33:11.904971 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6087 16:33:11.908457 MEM_TYPE=3, freq_sel=20
6088 16:33:11.911814 sv_algorithm_assistance_LP4_800
6089 16:33:11.915150 ============ PULL DRAM RESETB DOWN ============
6090 16:33:11.918436 ========== PULL DRAM RESETB DOWN end =========
6091 16:33:11.925430 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6092 16:33:11.928563 ===================================
6093 16:33:11.928642 LPDDR4 DRAM CONFIGURATION
6094 16:33:11.931951 ===================================
6095 16:33:11.935444 EX_ROW_EN[0] = 0x0
6096 16:33:11.938344 EX_ROW_EN[1] = 0x0
6097 16:33:11.938448 LP4Y_EN = 0x0
6098 16:33:11.941926 WORK_FSP = 0x0
6099 16:33:11.942021 WL = 0x2
6100 16:33:11.944794 RL = 0x2
6101 16:33:11.944895 BL = 0x2
6102 16:33:11.948437 RPST = 0x0
6103 16:33:11.948529 RD_PRE = 0x0
6104 16:33:11.952020 WR_PRE = 0x1
6105 16:33:11.952117 WR_PST = 0x0
6106 16:33:11.955030 DBI_WR = 0x0
6107 16:33:11.955128 DBI_RD = 0x0
6108 16:33:11.957970 OTF = 0x1
6109 16:33:11.961733 ===================================
6110 16:33:11.965352 ===================================
6111 16:33:11.965446 ANA top config
6112 16:33:11.968324 ===================================
6113 16:33:11.971311 DLL_ASYNC_EN = 0
6114 16:33:11.974924 ALL_SLAVE_EN = 1
6115 16:33:11.978487 NEW_RANK_MODE = 1
6116 16:33:11.978591 DLL_IDLE_MODE = 1
6117 16:33:11.981449 LP45_APHY_COMB_EN = 1
6118 16:33:11.985110 TX_ODT_DIS = 1
6119 16:33:11.988064 NEW_8X_MODE = 1
6120 16:33:11.991336 ===================================
6121 16:33:11.994988 ===================================
6122 16:33:11.997936 data_rate = 800
6123 16:33:11.998016 CKR = 1
6124 16:33:12.001801 DQ_P2S_RATIO = 4
6125 16:33:12.004724 ===================================
6126 16:33:12.007739 CA_P2S_RATIO = 4
6127 16:33:12.011306 DQ_CA_OPEN = 0
6128 16:33:12.014347 DQ_SEMI_OPEN = 1
6129 16:33:12.017708 CA_SEMI_OPEN = 1
6130 16:33:12.017811 CA_FULL_RATE = 0
6131 16:33:12.021371 DQ_CKDIV4_EN = 0
6132 16:33:12.024254 CA_CKDIV4_EN = 1
6133 16:33:12.027852 CA_PREDIV_EN = 0
6134 16:33:12.031390 PH8_DLY = 0
6135 16:33:12.031470 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6136 16:33:12.034247 DQ_AAMCK_DIV = 0
6137 16:33:12.037807 CA_AAMCK_DIV = 0
6138 16:33:12.041015 CA_ADMCK_DIV = 4
6139 16:33:12.044272 DQ_TRACK_CA_EN = 0
6140 16:33:12.047370 CA_PICK = 800
6141 16:33:12.051016 CA_MCKIO = 400
6142 16:33:12.054386 MCKIO_SEMI = 400
6143 16:33:12.054485 PLL_FREQ = 3016
6144 16:33:12.057702 DQ_UI_PI_RATIO = 32
6145 16:33:12.061211 CA_UI_PI_RATIO = 32
6146 16:33:12.064455 ===================================
6147 16:33:12.067918 ===================================
6148 16:33:12.071298 memory_type:LPDDR4
6149 16:33:12.071384 GP_NUM : 10
6150 16:33:12.074035 SRAM_EN : 1
6151 16:33:12.077698 MD32_EN : 0
6152 16:33:12.080612 ===================================
6153 16:33:12.080694 [ANA_INIT] >>>>>>>>>>>>>>
6154 16:33:12.084312 <<<<<< [CONFIGURE PHASE]: ANA_TX
6155 16:33:12.087281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6156 16:33:12.091046 ===================================
6157 16:33:12.093952 data_rate = 800,PCW = 0X7400
6158 16:33:12.097586 ===================================
6159 16:33:12.100734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6160 16:33:12.107413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 16:33:12.117770 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 16:33:12.124337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6163 16:33:12.127269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6164 16:33:12.130947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6165 16:33:12.131035 [ANA_INIT] flow start
6166 16:33:12.133899 [ANA_INIT] PLL >>>>>>>>
6167 16:33:12.137489 [ANA_INIT] PLL <<<<<<<<
6168 16:33:12.137607 [ANA_INIT] MIDPI >>>>>>>>
6169 16:33:12.140332 [ANA_INIT] MIDPI <<<<<<<<
6170 16:33:12.143983 [ANA_INIT] DLL >>>>>>>>
6171 16:33:12.144088 [ANA_INIT] flow end
6172 16:33:12.150854 ============ LP4 DIFF to SE enter ============
6173 16:33:12.153821 ============ LP4 DIFF to SE exit ============
6174 16:33:12.153911 [ANA_INIT] <<<<<<<<<<<<<
6175 16:33:12.157466 [Flow] Enable top DCM control >>>>>
6176 16:33:12.160826 [Flow] Enable top DCM control <<<<<
6177 16:33:12.164192 Enable DLL master slave shuffle
6178 16:33:12.170734 ==============================================================
6179 16:33:12.174014 Gating Mode config
6180 16:33:12.177166 ==============================================================
6181 16:33:12.181015 Config description:
6182 16:33:12.190719 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6183 16:33:12.197307 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6184 16:33:12.201006 SELPH_MODE 0: By rank 1: By Phase
6185 16:33:12.207708 ==============================================================
6186 16:33:12.210744 GAT_TRACK_EN = 0
6187 16:33:12.214368 RX_GATING_MODE = 2
6188 16:33:12.214450 RX_GATING_TRACK_MODE = 2
6189 16:33:12.217390 SELPH_MODE = 1
6190 16:33:12.220529 PICG_EARLY_EN = 1
6191 16:33:12.224243 VALID_LAT_VALUE = 1
6192 16:33:12.230316 ==============================================================
6193 16:33:12.233860 Enter into Gating configuration >>>>
6194 16:33:12.237427 Exit from Gating configuration <<<<
6195 16:33:12.240446 Enter into DVFS_PRE_config >>>>>
6196 16:33:12.250660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6197 16:33:12.253528 Exit from DVFS_PRE_config <<<<<
6198 16:33:12.257246 Enter into PICG configuration >>>>
6199 16:33:12.260286 Exit from PICG configuration <<<<
6200 16:33:12.263358 [RX_INPUT] configuration >>>>>
6201 16:33:12.267044 [RX_INPUT] configuration <<<<<
6202 16:33:12.269999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6203 16:33:12.277232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6204 16:33:12.283314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 16:33:12.290579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 16:33:12.293401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 16:33:12.300214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 16:33:12.303416 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6209 16:33:12.310213 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6210 16:33:12.313531 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6211 16:33:12.316316 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6212 16:33:12.319682 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6213 16:33:12.326814 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 16:33:12.329821 ===================================
6215 16:33:12.333451 LPDDR4 DRAM CONFIGURATION
6216 16:33:12.336559 ===================================
6217 16:33:12.336653 EX_ROW_EN[0] = 0x0
6218 16:33:12.340044 EX_ROW_EN[1] = 0x0
6219 16:33:12.340193 LP4Y_EN = 0x0
6220 16:33:12.343111 WORK_FSP = 0x0
6221 16:33:12.343214 WL = 0x2
6222 16:33:12.346715 RL = 0x2
6223 16:33:12.346811 BL = 0x2
6224 16:33:12.349732 RPST = 0x0
6225 16:33:12.349808 RD_PRE = 0x0
6226 16:33:12.353384 WR_PRE = 0x1
6227 16:33:12.353477 WR_PST = 0x0
6228 16:33:12.356450 DBI_WR = 0x0
6229 16:33:12.356539 DBI_RD = 0x0
6230 16:33:12.359478 OTF = 0x1
6231 16:33:12.363174 ===================================
6232 16:33:12.366150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6233 16:33:12.369891 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6234 16:33:12.376763 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 16:33:12.379595 ===================================
6236 16:33:12.379693 LPDDR4 DRAM CONFIGURATION
6237 16:33:12.383156 ===================================
6238 16:33:12.386192 EX_ROW_EN[0] = 0x10
6239 16:33:12.389276 EX_ROW_EN[1] = 0x0
6240 16:33:12.389365 LP4Y_EN = 0x0
6241 16:33:12.392994 WORK_FSP = 0x0
6242 16:33:12.393095 WL = 0x2
6243 16:33:12.395999 RL = 0x2
6244 16:33:12.396091 BL = 0x2
6245 16:33:12.399783 RPST = 0x0
6246 16:33:12.399872 RD_PRE = 0x0
6247 16:33:12.402781 WR_PRE = 0x1
6248 16:33:12.402921 WR_PST = 0x0
6249 16:33:12.406523 DBI_WR = 0x0
6250 16:33:12.406604 DBI_RD = 0x0
6251 16:33:12.409682 OTF = 0x1
6252 16:33:12.412609 ===================================
6253 16:33:12.419154 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6254 16:33:12.422737 nWR fixed to 30
6255 16:33:12.426085 [ModeRegInit_LP4] CH0 RK0
6256 16:33:12.426170 [ModeRegInit_LP4] CH0 RK1
6257 16:33:12.429414 [ModeRegInit_LP4] CH1 RK0
6258 16:33:12.432672 [ModeRegInit_LP4] CH1 RK1
6259 16:33:12.432768 match AC timing 19
6260 16:33:12.439201 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6261 16:33:12.442455 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6262 16:33:12.445809 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6263 16:33:12.452943 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6264 16:33:12.455895 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6265 16:33:12.455984 ==
6266 16:33:12.459544 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 16:33:12.462424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 16:33:12.462543 ==
6269 16:33:12.469160 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 16:33:12.475922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6271 16:33:12.478967 [CA 0] Center 36 (8~64) winsize 57
6272 16:33:12.482709 [CA 1] Center 36 (8~64) winsize 57
6273 16:33:12.482809 [CA 2] Center 36 (8~64) winsize 57
6274 16:33:12.485669 [CA 3] Center 36 (8~64) winsize 57
6275 16:33:12.489334 [CA 4] Center 36 (8~64) winsize 57
6276 16:33:12.492765 [CA 5] Center 36 (8~64) winsize 57
6277 16:33:12.492856
6278 16:33:12.495752 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6279 16:33:12.498750
6280 16:33:12.502458 [CATrainingPosCal] consider 1 rank data
6281 16:33:12.502543 u2DelayCellTimex100 = 270/100 ps
6282 16:33:12.509040 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 16:33:12.512162 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 16:33:12.515809 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 16:33:12.518819 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 16:33:12.522516 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 16:33:12.525418 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 16:33:12.525524
6289 16:33:12.528496 CA PerBit enable=1, Macro0, CA PI delay=36
6290 16:33:12.528579
6291 16:33:12.532224 [CBTSetCACLKResult] CA Dly = 36
6292 16:33:12.535214 CS Dly: 1 (0~32)
6293 16:33:12.535299 ==
6294 16:33:12.538839 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 16:33:12.542460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 16:33:12.542570 ==
6297 16:33:12.548609 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 16:33:12.552120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6299 16:33:12.555571 [CA 0] Center 36 (8~64) winsize 57
6300 16:33:12.558849 [CA 1] Center 36 (8~64) winsize 57
6301 16:33:12.562304 [CA 2] Center 36 (8~64) winsize 57
6302 16:33:12.565195 [CA 3] Center 36 (8~64) winsize 57
6303 16:33:12.568602 [CA 4] Center 36 (8~64) winsize 57
6304 16:33:12.571828 [CA 5] Center 36 (8~64) winsize 57
6305 16:33:12.571916
6306 16:33:12.575586 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6307 16:33:12.575673
6308 16:33:12.578627 [CATrainingPosCal] consider 2 rank data
6309 16:33:12.581911 u2DelayCellTimex100 = 270/100 ps
6310 16:33:12.585378 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 16:33:12.588887 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 16:33:12.591882 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 16:33:12.598481 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 16:33:12.601991 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 16:33:12.604980 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 16:33:12.605062
6317 16:33:12.608153 CA PerBit enable=1, Macro0, CA PI delay=36
6318 16:33:12.608233
6319 16:33:12.611906 [CBTSetCACLKResult] CA Dly = 36
6320 16:33:12.611989 CS Dly: 1 (0~32)
6321 16:33:12.612068
6322 16:33:12.615030 ----->DramcWriteLeveling(PI) begin...
6323 16:33:12.615113 ==
6324 16:33:12.618855 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 16:33:12.625502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 16:33:12.625631 ==
6327 16:33:12.628563 Write leveling (Byte 0): 40 => 8
6328 16:33:12.631645 Write leveling (Byte 1): 40 => 8
6329 16:33:12.631717 DramcWriteLeveling(PI) end<-----
6330 16:33:12.631774
6331 16:33:12.635472 ==
6332 16:33:12.638418 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 16:33:12.642239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 16:33:12.642312 ==
6335 16:33:12.645243 [Gating] SW mode calibration
6336 16:33:12.651580 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6337 16:33:12.655234 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6338 16:33:12.661759 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 16:33:12.664700 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 16:33:12.668274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 16:33:12.674925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 16:33:12.678539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 16:33:12.682203 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 16:33:12.688431 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 16:33:12.691750 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 16:33:12.695046 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 16:33:12.698415 Total UI for P1: 0, mck2ui 16
6348 16:33:12.702057 best dqsien dly found for B0: ( 0, 14, 24)
6349 16:33:12.704824 Total UI for P1: 0, mck2ui 16
6350 16:33:12.708320 best dqsien dly found for B1: ( 0, 14, 24)
6351 16:33:12.711928 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6352 16:33:12.714679 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6353 16:33:12.714760
6354 16:33:12.718594 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 16:33:12.725310 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 16:33:12.725452 [Gating] SW calibration Done
6357 16:33:12.728082 ==
6358 16:33:12.728166 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 16:33:12.734792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 16:33:12.734881 ==
6361 16:33:12.734961 RX Vref Scan: 0
6362 16:33:12.735037
6363 16:33:12.738457 RX Vref 0 -> 0, step: 1
6364 16:33:12.738542
6365 16:33:12.741421 RX Delay -410 -> 252, step: 16
6366 16:33:12.745300 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6367 16:33:12.748339 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6368 16:33:12.754959 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6369 16:33:12.757855 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6370 16:33:12.761626 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6371 16:33:12.764468 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6372 16:33:12.770991 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6373 16:33:12.774701 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6374 16:33:12.777582 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6375 16:33:12.781299 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6376 16:33:12.787966 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6377 16:33:12.790880 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6378 16:33:12.794586 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6379 16:33:12.801207 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6380 16:33:12.803981 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6381 16:33:12.807356 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6382 16:33:12.807431 ==
6383 16:33:12.810834 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 16:33:12.814558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 16:33:12.817452 ==
6386 16:33:12.817532 DQS Delay:
6387 16:33:12.817631 DQS0 = 27, DQS1 = 35
6388 16:33:12.820995 DQM Delay:
6389 16:33:12.821067 DQM0 = 8, DQM1 = 11
6390 16:33:12.823966 DQ Delay:
6391 16:33:12.824039 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6392 16:33:12.827511 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6393 16:33:12.830683 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6394 16:33:12.833847 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6395 16:33:12.833918
6396 16:33:12.833973
6397 16:33:12.834031 ==
6398 16:33:12.837793 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 16:33:12.843868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 16:33:12.843955 ==
6401 16:33:12.844014
6402 16:33:12.844074
6403 16:33:12.844125 TX Vref Scan disable
6404 16:33:12.847344 == TX Byte 0 ==
6405 16:33:12.851021 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 16:33:12.853970 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 16:33:12.857508 == TX Byte 1 ==
6408 16:33:12.860462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 16:33:12.864304 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 16:33:12.867142 ==
6411 16:33:12.867217 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 16:33:12.874040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 16:33:12.874131 ==
6414 16:33:12.874192
6415 16:33:12.874247
6416 16:33:12.877181 TX Vref Scan disable
6417 16:33:12.877258 == TX Byte 0 ==
6418 16:33:12.880747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 16:33:12.887150 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 16:33:12.887239 == TX Byte 1 ==
6421 16:33:12.890913 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 16:33:12.893794 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 16:33:12.897453
6424 16:33:12.897537 [DATLAT]
6425 16:33:12.897638 Freq=400, CH0 RK0
6426 16:33:12.897723
6427 16:33:12.900468 DATLAT Default: 0xf
6428 16:33:12.900547 0, 0xFFFF, sum = 0
6429 16:33:12.904186 1, 0xFFFF, sum = 0
6430 16:33:12.904266 2, 0xFFFF, sum = 0
6431 16:33:12.907195 3, 0xFFFF, sum = 0
6432 16:33:12.907284 4, 0xFFFF, sum = 0
6433 16:33:12.910098 5, 0xFFFF, sum = 0
6434 16:33:12.913779 6, 0xFFFF, sum = 0
6435 16:33:12.913892 7, 0xFFFF, sum = 0
6436 16:33:12.916723 8, 0xFFFF, sum = 0
6437 16:33:12.916802 9, 0xFFFF, sum = 0
6438 16:33:12.920086 10, 0xFFFF, sum = 0
6439 16:33:12.920168 11, 0xFFFF, sum = 0
6440 16:33:12.923794 12, 0xFFFF, sum = 0
6441 16:33:12.923875 13, 0x0, sum = 1
6442 16:33:12.926704 14, 0x0, sum = 2
6443 16:33:12.926785 15, 0x0, sum = 3
6444 16:33:12.930459 16, 0x0, sum = 4
6445 16:33:12.930541 best_step = 14
6446 16:33:12.930600
6447 16:33:12.930684 ==
6448 16:33:12.933388 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 16:33:12.937015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 16:33:12.937095 ==
6451 16:33:12.940598 RX Vref Scan: 1
6452 16:33:12.940679
6453 16:33:12.943489 RX Vref 0 -> 0, step: 1
6454 16:33:12.943566
6455 16:33:12.943625 RX Delay -311 -> 252, step: 8
6456 16:33:12.947142
6457 16:33:12.947224 Set Vref, RX VrefLevel [Byte0]: 57
6458 16:33:12.950551 [Byte1]: 50
6459 16:33:12.955810
6460 16:33:12.955894 Final RX Vref Byte 0 = 57 to rank0
6461 16:33:12.959104 Final RX Vref Byte 1 = 50 to rank0
6462 16:33:12.962408 Final RX Vref Byte 0 = 57 to rank1
6463 16:33:12.965936 Final RX Vref Byte 1 = 50 to rank1==
6464 16:33:12.968818 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 16:33:12.975395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 16:33:12.975487 ==
6467 16:33:12.975549 DQS Delay:
6468 16:33:12.979090 DQS0 = 24, DQS1 = 36
6469 16:33:12.979170 DQM Delay:
6470 16:33:12.979230 DQM0 = 7, DQM1 = 13
6471 16:33:12.982094 DQ Delay:
6472 16:33:12.985096 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6473 16:33:12.985176 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6474 16:33:12.988898 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6475 16:33:12.992415 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6476 16:33:12.992501
6477 16:33:12.992562
6478 16:33:13.002112 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0bd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6479 16:33:13.005152 CH0 RK0: MR19=C0C, MR18=D0BD
6480 16:33:13.012365 CH0_RK0: MR19=0xC0C, MR18=0xD0BD, DQSOSC=384, MR23=63, INC=400, DEC=267
6481 16:33:13.012486 ==
6482 16:33:13.015460 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 16:33:13.018451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 16:33:13.018533 ==
6485 16:33:13.022009 [Gating] SW mode calibration
6486 16:33:13.028466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6487 16:33:13.031965 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6488 16:33:13.038561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 16:33:13.042253 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 16:33:13.045241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 16:33:13.051858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 16:33:13.055577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 16:33:13.058560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 16:33:13.065194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 16:33:13.068696 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 16:33:13.071534 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 16:33:13.074888 Total UI for P1: 0, mck2ui 16
6498 16:33:13.078072 best dqsien dly found for B0: ( 0, 14, 24)
6499 16:33:13.081477 Total UI for P1: 0, mck2ui 16
6500 16:33:13.084854 best dqsien dly found for B1: ( 0, 14, 24)
6501 16:33:13.088098 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6502 16:33:13.091887 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6503 16:33:13.094744
6504 16:33:13.098355 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 16:33:13.101859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 16:33:13.104878 [Gating] SW calibration Done
6507 16:33:13.104960 ==
6508 16:33:13.107910 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 16:33:13.111639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 16:33:13.111719 ==
6511 16:33:13.111778 RX Vref Scan: 0
6512 16:33:13.111832
6513 16:33:13.114642 RX Vref 0 -> 0, step: 1
6514 16:33:13.114708
6515 16:33:13.118411 RX Delay -410 -> 252, step: 16
6516 16:33:13.121386 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6517 16:33:13.128647 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6518 16:33:13.131519 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6519 16:33:13.134557 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6520 16:33:13.138056 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6521 16:33:13.144924 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6522 16:33:13.148569 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6523 16:33:13.151593 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6524 16:33:13.154540 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6525 16:33:13.158230 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6526 16:33:13.164791 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6527 16:33:13.168383 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6528 16:33:13.171471 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6529 16:33:13.178387 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6530 16:33:13.181225 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6531 16:33:13.184830 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6532 16:33:13.184903 ==
6533 16:33:13.187952 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 16:33:13.191535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 16:33:13.194289 ==
6536 16:33:13.194398 DQS Delay:
6537 16:33:13.194491 DQS0 = 19, DQS1 = 35
6538 16:33:13.197876 DQM Delay:
6539 16:33:13.197965 DQM0 = 7, DQM1 = 12
6540 16:33:13.201185 DQ Delay:
6541 16:33:13.201265 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6542 16:33:13.204409 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6543 16:33:13.207765 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6544 16:33:13.211725 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6545 16:33:13.211809
6546 16:33:13.211870
6547 16:33:13.211925 ==
6548 16:33:13.214789 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 16:33:13.221004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 16:33:13.221100 ==
6551 16:33:13.221161
6552 16:33:13.221214
6553 16:33:13.221270 TX Vref Scan disable
6554 16:33:13.224752 == TX Byte 0 ==
6555 16:33:13.227707 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6556 16:33:13.231620 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6557 16:33:13.234391 == TX Byte 1 ==
6558 16:33:13.238037 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6559 16:33:13.241057 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6560 16:33:13.241131 ==
6561 16:33:13.244704 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 16:33:13.250928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 16:33:13.251010 ==
6564 16:33:13.251076
6565 16:33:13.251129
6566 16:33:13.251180 TX Vref Scan disable
6567 16:33:13.254472 == TX Byte 0 ==
6568 16:33:13.257868 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6569 16:33:13.260917 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6570 16:33:13.264642 == TX Byte 1 ==
6571 16:33:13.267735 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6572 16:33:13.270645 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6573 16:33:13.270717
6574 16:33:13.274288 [DATLAT]
6575 16:33:13.274357 Freq=400, CH0 RK1
6576 16:33:13.274413
6577 16:33:13.277305 DATLAT Default: 0xe
6578 16:33:13.277371 0, 0xFFFF, sum = 0
6579 16:33:13.280985 1, 0xFFFF, sum = 0
6580 16:33:13.281057 2, 0xFFFF, sum = 0
6581 16:33:13.284547 3, 0xFFFF, sum = 0
6582 16:33:13.284614 4, 0xFFFF, sum = 0
6583 16:33:13.287306 5, 0xFFFF, sum = 0
6584 16:33:13.287373 6, 0xFFFF, sum = 0
6585 16:33:13.291053 7, 0xFFFF, sum = 0
6586 16:33:13.291119 8, 0xFFFF, sum = 0
6587 16:33:13.294200 9, 0xFFFF, sum = 0
6588 16:33:13.297854 10, 0xFFFF, sum = 0
6589 16:33:13.297926 11, 0xFFFF, sum = 0
6590 16:33:13.301005 12, 0xFFFF, sum = 0
6591 16:33:13.301080 13, 0x0, sum = 1
6592 16:33:13.304010 14, 0x0, sum = 2
6593 16:33:13.304123 15, 0x0, sum = 3
6594 16:33:13.307541 16, 0x0, sum = 4
6595 16:33:13.307621 best_step = 14
6596 16:33:13.307682
6597 16:33:13.307738 ==
6598 16:33:13.311251 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 16:33:13.314153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 16:33:13.314233 ==
6601 16:33:13.317778 RX Vref Scan: 0
6602 16:33:13.317874
6603 16:33:13.317966 RX Vref 0 -> 0, step: 1
6604 16:33:13.320497
6605 16:33:13.320603 RX Delay -311 -> 252, step: 8
6606 16:33:13.329414 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6607 16:33:13.332850 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6608 16:33:13.335957 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6609 16:33:13.339308 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6610 16:33:13.345723 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6611 16:33:13.349479 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6612 16:33:13.352407 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6613 16:33:13.356012 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6614 16:33:13.362608 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6615 16:33:13.366072 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6616 16:33:13.368737 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6617 16:33:13.372118 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6618 16:33:13.379255 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6619 16:33:13.382221 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6620 16:33:13.386039 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6621 16:33:13.392250 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6622 16:33:13.392356 ==
6623 16:33:13.395298 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 16:33:13.399048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 16:33:13.399132 ==
6626 16:33:13.399193 DQS Delay:
6627 16:33:13.402038 DQS0 = 24, DQS1 = 32
6628 16:33:13.402125 DQM Delay:
6629 16:33:13.405771 DQM0 = 8, DQM1 = 9
6630 16:33:13.405852 DQ Delay:
6631 16:33:13.408579 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6632 16:33:13.412283 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6633 16:33:13.415334 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6634 16:33:13.418863 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6635 16:33:13.418949
6636 16:33:13.419010
6637 16:33:13.425583 [DQSOSCAuto] RK1, (LSB)MR18= 0xb858, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6638 16:33:13.428515 CH0 RK1: MR19=C0C, MR18=B858
6639 16:33:13.435732 CH0_RK1: MR19=0xC0C, MR18=0xB858, DQSOSC=386, MR23=63, INC=396, DEC=264
6640 16:33:13.438796 [RxdqsGatingPostProcess] freq 400
6641 16:33:13.442277 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6642 16:33:13.445646 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 16:33:13.449036 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 16:33:13.451774 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 16:33:13.455018 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 16:33:13.458897 best DQS0 dly(2T, 0.5T) = (0, 10)
6647 16:33:13.462171 best DQS1 dly(2T, 0.5T) = (0, 10)
6648 16:33:13.464930 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6649 16:33:13.468415 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6650 16:33:13.472156 Pre-setting of DQS Precalculation
6651 16:33:13.475057 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6652 16:33:13.478637 ==
6653 16:33:13.482089 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 16:33:13.485490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 16:33:13.485616 ==
6656 16:33:13.488314 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 16:33:13.494915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6658 16:33:13.498470 [CA 0] Center 36 (8~64) winsize 57
6659 16:33:13.501456 [CA 1] Center 36 (8~64) winsize 57
6660 16:33:13.505092 [CA 2] Center 36 (8~64) winsize 57
6661 16:33:13.508074 [CA 3] Center 36 (8~64) winsize 57
6662 16:33:13.511808 [CA 4] Center 36 (8~64) winsize 57
6663 16:33:13.514678 [CA 5] Center 36 (8~64) winsize 57
6664 16:33:13.514762
6665 16:33:13.518383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6666 16:33:13.518462
6667 16:33:13.521315 [CATrainingPosCal] consider 1 rank data
6668 16:33:13.524897 u2DelayCellTimex100 = 270/100 ps
6669 16:33:13.527910 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 16:33:13.531517 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 16:33:13.535185 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 16:33:13.538168 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 16:33:13.544918 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 16:33:13.547940 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 16:33:13.548027
6676 16:33:13.551796 CA PerBit enable=1, Macro0, CA PI delay=36
6677 16:33:13.551878
6678 16:33:13.554769 [CBTSetCACLKResult] CA Dly = 36
6679 16:33:13.554848 CS Dly: 1 (0~32)
6680 16:33:13.554924 ==
6681 16:33:13.558308 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 16:33:13.561313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 16:33:13.564965 ==
6684 16:33:13.568389 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 16:33:13.575180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6686 16:33:13.578613 [CA 0] Center 36 (8~64) winsize 57
6687 16:33:13.581280 [CA 1] Center 36 (8~64) winsize 57
6688 16:33:13.584657 [CA 2] Center 36 (8~64) winsize 57
6689 16:33:13.588666 [CA 3] Center 36 (8~64) winsize 57
6690 16:33:13.591902 [CA 4] Center 36 (8~64) winsize 57
6691 16:33:13.595235 [CA 5] Center 36 (8~64) winsize 57
6692 16:33:13.595328
6693 16:33:13.597993 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6694 16:33:13.598092
6695 16:33:13.601479 [CATrainingPosCal] consider 2 rank data
6696 16:33:13.604928 u2DelayCellTimex100 = 270/100 ps
6697 16:33:13.608207 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 16:33:13.611359 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 16:33:13.614929 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 16:33:13.617912 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 16:33:13.621684 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 16:33:13.624710 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 16:33:13.624812
6704 16:33:13.628404 CA PerBit enable=1, Macro0, CA PI delay=36
6705 16:33:13.631213
6706 16:33:13.631294 [CBTSetCACLKResult] CA Dly = 36
6707 16:33:13.634997 CS Dly: 1 (0~32)
6708 16:33:13.635098
6709 16:33:13.638003 ----->DramcWriteLeveling(PI) begin...
6710 16:33:13.638074 ==
6711 16:33:13.641721 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 16:33:13.644524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 16:33:13.644595 ==
6714 16:33:13.648195 Write leveling (Byte 0): 40 => 8
6715 16:33:13.651283 Write leveling (Byte 1): 40 => 8
6716 16:33:13.654356 DramcWriteLeveling(PI) end<-----
6717 16:33:13.654425
6718 16:33:13.654486 ==
6719 16:33:13.658053 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 16:33:13.661484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 16:33:13.661598 ==
6722 16:33:13.664483 [Gating] SW mode calibration
6723 16:33:13.674317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6724 16:33:13.677933 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6725 16:33:13.680892 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 16:33:13.687541 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 16:33:13.691223 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 16:33:13.694170 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 16:33:13.700673 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 16:33:13.704243 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 16:33:13.707196 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 16:33:13.713944 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 16:33:13.717423 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 16:33:13.720824 Total UI for P1: 0, mck2ui 16
6735 16:33:13.723746 best dqsien dly found for B0: ( 0, 14, 24)
6736 16:33:13.727163 Total UI for P1: 0, mck2ui 16
6737 16:33:13.730511 best dqsien dly found for B1: ( 0, 14, 24)
6738 16:33:13.733883 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6739 16:33:13.737193 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6740 16:33:13.737271
6741 16:33:13.740208 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 16:33:13.743972 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 16:33:13.747596 [Gating] SW calibration Done
6744 16:33:13.747679 ==
6745 16:33:13.750626 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 16:33:13.753622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 16:33:13.757390 ==
6748 16:33:13.757465 RX Vref Scan: 0
6749 16:33:13.757526
6750 16:33:13.760454 RX Vref 0 -> 0, step: 1
6751 16:33:13.760521
6752 16:33:13.764157 RX Delay -410 -> 252, step: 16
6753 16:33:13.766921 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6754 16:33:13.770462 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6755 16:33:13.774214 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6756 16:33:13.780859 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6757 16:33:13.783945 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6758 16:33:13.786872 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6759 16:33:13.790588 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6760 16:33:13.797073 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6761 16:33:13.800630 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6762 16:33:13.803500 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6763 16:33:13.807135 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6764 16:33:13.813679 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6765 16:33:13.816881 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6766 16:33:13.820658 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6767 16:33:13.823694 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6768 16:33:13.830392 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6769 16:33:13.830493 ==
6770 16:33:13.834030 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 16:33:13.837137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 16:33:13.837219 ==
6773 16:33:13.837281 DQS Delay:
6774 16:33:13.840026 DQS0 = 27, DQS1 = 27
6775 16:33:13.840106 DQM Delay:
6776 16:33:13.843734 DQM0 = 11, DQM1 = 8
6777 16:33:13.843816 DQ Delay:
6778 16:33:13.846765 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6779 16:33:13.850445 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6780 16:33:13.853347 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6781 16:33:13.856895 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6782 16:33:13.856986
6783 16:33:13.857063
6784 16:33:13.857120 ==
6785 16:33:13.860393 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 16:33:13.863567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 16:33:13.863663 ==
6788 16:33:13.863747
6789 16:33:13.863836
6790 16:33:13.866732 TX Vref Scan disable
6791 16:33:13.866829 == TX Byte 0 ==
6792 16:33:13.873901 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 16:33:13.876712 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 16:33:13.876795 == TX Byte 1 ==
6795 16:33:13.883648 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 16:33:13.887486 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 16:33:13.887579 ==
6798 16:33:13.890492 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 16:33:13.893410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 16:33:13.893526 ==
6801 16:33:13.893639
6802 16:33:13.893720
6803 16:33:13.897185 TX Vref Scan disable
6804 16:33:13.897266 == TX Byte 0 ==
6805 16:33:13.903985 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 16:33:13.906832 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 16:33:13.906923 == TX Byte 1 ==
6808 16:33:13.913988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 16:33:13.916880 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 16:33:13.916966
6811 16:33:13.917028 [DATLAT]
6812 16:33:13.920615 Freq=400, CH1 RK0
6813 16:33:13.920714
6814 16:33:13.920790 DATLAT Default: 0xf
6815 16:33:13.924116 0, 0xFFFF, sum = 0
6816 16:33:13.924200 1, 0xFFFF, sum = 0
6817 16:33:13.927205 2, 0xFFFF, sum = 0
6818 16:33:13.927288 3, 0xFFFF, sum = 0
6819 16:33:13.930109 4, 0xFFFF, sum = 0
6820 16:33:13.930191 5, 0xFFFF, sum = 0
6821 16:33:13.933769 6, 0xFFFF, sum = 0
6822 16:33:13.933852 7, 0xFFFF, sum = 0
6823 16:33:13.936610 8, 0xFFFF, sum = 0
6824 16:33:13.936692 9, 0xFFFF, sum = 0
6825 16:33:13.940435 10, 0xFFFF, sum = 0
6826 16:33:13.943240 11, 0xFFFF, sum = 0
6827 16:33:13.943325 12, 0xFFFF, sum = 0
6828 16:33:13.946965 13, 0x0, sum = 1
6829 16:33:13.947074 14, 0x0, sum = 2
6830 16:33:13.947162 15, 0x0, sum = 3
6831 16:33:13.949937 16, 0x0, sum = 4
6832 16:33:13.950018 best_step = 14
6833 16:33:13.950079
6834 16:33:13.953709 ==
6835 16:33:13.953791 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 16:33:13.960454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 16:33:13.960549 ==
6838 16:33:13.960612 RX Vref Scan: 1
6839 16:33:13.960669
6840 16:33:13.963512 RX Vref 0 -> 0, step: 1
6841 16:33:13.963592
6842 16:33:13.966546 RX Delay -295 -> 252, step: 8
6843 16:33:13.966643
6844 16:33:13.970264 Set Vref, RX VrefLevel [Byte0]: 54
6845 16:33:13.973840 [Byte1]: 50
6846 16:33:13.973922
6847 16:33:13.976810 Final RX Vref Byte 0 = 54 to rank0
6848 16:33:13.980466 Final RX Vref Byte 1 = 50 to rank0
6849 16:33:13.983287 Final RX Vref Byte 0 = 54 to rank1
6850 16:33:13.986685 Final RX Vref Byte 1 = 50 to rank1==
6851 16:33:13.990039 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 16:33:13.993451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 16:33:13.996763 ==
6854 16:33:13.996847 DQS Delay:
6855 16:33:13.996909 DQS0 = 32, DQS1 = 32
6856 16:33:13.999962 DQM Delay:
6857 16:33:14.000043 DQM0 = 13, DQM1 = 10
6858 16:33:14.003067 DQ Delay:
6859 16:33:14.006651 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6860 16:33:14.009697 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6861 16:33:14.009778 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6862 16:33:14.013394 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6863 16:33:14.013475
6864 16:33:14.016292
6865 16:33:14.023387 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6866 16:33:14.026791 CH1 RK0: MR19=C0C, MR18=90C8
6867 16:33:14.033316 CH1_RK0: MR19=0xC0C, MR18=0x90C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6868 16:33:14.033458 ==
6869 16:33:14.036249 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 16:33:14.039209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 16:33:14.039287 ==
6872 16:33:14.042800 [Gating] SW mode calibration
6873 16:33:14.049572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6874 16:33:14.056113 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6875 16:33:14.059088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 16:33:14.062869 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 16:33:14.068954 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 16:33:14.072598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 16:33:14.075660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 16:33:14.082887 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 16:33:14.085875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 16:33:14.089077 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 16:33:14.095738 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 16:33:14.095850 Total UI for P1: 0, mck2ui 16
6885 16:33:14.102529 best dqsien dly found for B0: ( 0, 14, 24)
6886 16:33:14.102623 Total UI for P1: 0, mck2ui 16
6887 16:33:14.106032 best dqsien dly found for B1: ( 0, 14, 24)
6888 16:33:14.112368 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6889 16:33:14.115736 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6890 16:33:14.115824
6891 16:33:14.119046 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 16:33:14.122204 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 16:33:14.125971 [Gating] SW calibration Done
6894 16:33:14.126060 ==
6895 16:33:14.129269 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 16:33:14.132805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 16:33:14.132892 ==
6898 16:33:14.135668 RX Vref Scan: 0
6899 16:33:14.135820
6900 16:33:14.135915 RX Vref 0 -> 0, step: 1
6901 16:33:14.136003
6902 16:33:14.139300 RX Delay -410 -> 252, step: 16
6903 16:33:14.142640 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6904 16:33:14.148949 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6905 16:33:14.152605 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6906 16:33:14.155706 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6907 16:33:14.159434 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6908 16:33:14.166087 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6909 16:33:14.169023 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6910 16:33:14.172783 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6911 16:33:14.175783 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6912 16:33:14.182760 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6913 16:33:14.185764 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6914 16:33:14.188668 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6915 16:33:14.192391 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6916 16:33:14.198890 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6917 16:33:14.202598 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6918 16:33:14.205609 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6919 16:33:14.205699 ==
6920 16:33:14.209088 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 16:33:14.215900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 16:33:14.215993 ==
6923 16:33:14.216058 DQS Delay:
6924 16:33:14.218844 DQS0 = 35, DQS1 = 35
6925 16:33:14.218917 DQM Delay:
6926 16:33:14.218979 DQM0 = 18, DQM1 = 13
6927 16:33:14.222636 DQ Delay:
6928 16:33:14.225527 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6929 16:33:14.229272 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6930 16:33:14.229370 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6931 16:33:14.232130 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6932 16:33:14.235651
6933 16:33:14.235759
6934 16:33:14.235845 ==
6935 16:33:14.238484 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 16:33:14.242454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 16:33:14.242538 ==
6938 16:33:14.242599
6939 16:33:14.242654
6940 16:33:14.245722 TX Vref Scan disable
6941 16:33:14.245806 == TX Byte 0 ==
6942 16:33:14.249062 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6943 16:33:14.255594 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6944 16:33:14.255692 == TX Byte 1 ==
6945 16:33:14.258726 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6946 16:33:14.265632 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6947 16:33:14.265733 ==
6948 16:33:14.268759 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 16:33:14.272187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 16:33:14.272273 ==
6951 16:33:14.272336
6952 16:33:14.272391
6953 16:33:14.275118 TX Vref Scan disable
6954 16:33:14.275198 == TX Byte 0 ==
6955 16:33:14.278904 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6956 16:33:14.285515 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6957 16:33:14.285643 == TX Byte 1 ==
6958 16:33:14.288568 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6959 16:33:14.295123 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6960 16:33:14.295223
6961 16:33:14.295286 [DATLAT]
6962 16:33:14.295342 Freq=400, CH1 RK1
6963 16:33:14.298802
6964 16:33:14.298896 DATLAT Default: 0xe
6965 16:33:14.301803 0, 0xFFFF, sum = 0
6966 16:33:14.301885 1, 0xFFFF, sum = 0
6967 16:33:14.305612 2, 0xFFFF, sum = 0
6968 16:33:14.305697 3, 0xFFFF, sum = 0
6969 16:33:14.308562 4, 0xFFFF, sum = 0
6970 16:33:14.308645 5, 0xFFFF, sum = 0
6971 16:33:14.311544 6, 0xFFFF, sum = 0
6972 16:33:14.311626 7, 0xFFFF, sum = 0
6973 16:33:14.315307 8, 0xFFFF, sum = 0
6974 16:33:14.315390 9, 0xFFFF, sum = 0
6975 16:33:14.318334 10, 0xFFFF, sum = 0
6976 16:33:14.318417 11, 0xFFFF, sum = 0
6977 16:33:14.321994 12, 0xFFFF, sum = 0
6978 16:33:14.322078 13, 0x0, sum = 1
6979 16:33:14.324977 14, 0x0, sum = 2
6980 16:33:14.325059 15, 0x0, sum = 3
6981 16:33:14.328640 16, 0x0, sum = 4
6982 16:33:14.328723 best_step = 14
6983 16:33:14.328812
6984 16:33:14.328869 ==
6985 16:33:14.331737 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 16:33:14.338335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 16:33:14.338438 ==
6988 16:33:14.338501 RX Vref Scan: 0
6989 16:33:14.338559
6990 16:33:14.341984 RX Vref 0 -> 0, step: 1
6991 16:33:14.342067
6992 16:33:14.345016 RX Delay -311 -> 252, step: 8
6993 16:33:14.352131 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6994 16:33:14.355079 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6995 16:33:14.358731 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6996 16:33:14.361632 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6997 16:33:14.368706 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6998 16:33:14.371482 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6999 16:33:14.374963 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7000 16:33:14.378615 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
7001 16:33:14.381892 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7002 16:33:14.388361 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7003 16:33:14.391608 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
7004 16:33:14.395357 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7005 16:33:14.398668 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7006 16:33:14.405426 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7007 16:33:14.408359 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7008 16:33:14.411979 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7009 16:33:14.412071 ==
7010 16:33:14.414830 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 16:33:14.421616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 16:33:14.421718 ==
7013 16:33:14.421781 DQS Delay:
7014 16:33:14.425450 DQS0 = 28, DQS1 = 36
7015 16:33:14.425565 DQM Delay:
7016 16:33:14.425644 DQM0 = 11, DQM1 = 15
7017 16:33:14.428331 DQ Delay:
7018 16:33:14.431252 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =4
7019 16:33:14.434999 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7020 16:33:14.435089 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
7021 16:33:14.438029 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7022 16:33:14.441974
7023 16:33:14.442066
7024 16:33:14.447784 [DQSOSCAuto] RK1, (LSB)MR18= 0xc757, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7025 16:33:14.451607 CH1 RK1: MR19=C0C, MR18=C757
7026 16:33:14.458072 CH1_RK1: MR19=0xC0C, MR18=0xC757, DQSOSC=385, MR23=63, INC=398, DEC=265
7027 16:33:14.460922 [RxdqsGatingPostProcess] freq 400
7028 16:33:14.464722 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7029 16:33:14.467782 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 16:33:14.471561 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 16:33:14.474446 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 16:33:14.478033 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 16:33:14.481105 best DQS0 dly(2T, 0.5T) = (0, 10)
7034 16:33:14.484884 best DQS1 dly(2T, 0.5T) = (0, 10)
7035 16:33:14.487788 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7036 16:33:14.490746 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7037 16:33:14.494435 Pre-setting of DQS Precalculation
7038 16:33:14.497410 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7039 16:33:14.507686 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7040 16:33:14.514063 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7041 16:33:14.514179
7042 16:33:14.514244
7043 16:33:14.517329 [Calibration Summary] 800 Mbps
7044 16:33:14.517429 CH 0, Rank 0
7045 16:33:14.521105 SW Impedance : PASS
7046 16:33:14.521182 DUTY Scan : NO K
7047 16:33:14.524479 ZQ Calibration : PASS
7048 16:33:14.527805 Jitter Meter : NO K
7049 16:33:14.527884 CBT Training : PASS
7050 16:33:14.531191 Write leveling : PASS
7051 16:33:14.533996 RX DQS gating : PASS
7052 16:33:14.534082 RX DQ/DQS(RDDQC) : PASS
7053 16:33:14.537776 TX DQ/DQS : PASS
7054 16:33:14.537853 RX DATLAT : PASS
7055 16:33:14.540725 RX DQ/DQS(Engine): PASS
7056 16:33:14.544390 TX OE : NO K
7057 16:33:14.544467 All Pass.
7058 16:33:14.544529
7059 16:33:14.544586 CH 0, Rank 1
7060 16:33:14.547398 SW Impedance : PASS
7061 16:33:14.550397 DUTY Scan : NO K
7062 16:33:14.550470 ZQ Calibration : PASS
7063 16:33:14.554190 Jitter Meter : NO K
7064 16:33:14.557069 CBT Training : PASS
7065 16:33:14.557144 Write leveling : NO K
7066 16:33:14.560858 RX DQS gating : PASS
7067 16:33:14.563826 RX DQ/DQS(RDDQC) : PASS
7068 16:33:14.563897 TX DQ/DQS : PASS
7069 16:33:14.567332 RX DATLAT : PASS
7070 16:33:14.571040 RX DQ/DQS(Engine): PASS
7071 16:33:14.571113 TX OE : NO K
7072 16:33:14.574021 All Pass.
7073 16:33:14.574089
7074 16:33:14.574144 CH 1, Rank 0
7075 16:33:14.577050 SW Impedance : PASS
7076 16:33:14.577117 DUTY Scan : NO K
7077 16:33:14.580688 ZQ Calibration : PASS
7078 16:33:14.583588 Jitter Meter : NO K
7079 16:33:14.583664 CBT Training : PASS
7080 16:33:14.587295 Write leveling : PASS
7081 16:33:14.590787 RX DQS gating : PASS
7082 16:33:14.590861 RX DQ/DQS(RDDQC) : PASS
7083 16:33:14.593749 TX DQ/DQS : PASS
7084 16:33:14.593822 RX DATLAT : PASS
7085 16:33:14.597457 RX DQ/DQS(Engine): PASS
7086 16:33:14.600373 TX OE : NO K
7087 16:33:14.600447 All Pass.
7088 16:33:14.600503
7089 16:33:14.600559 CH 1, Rank 1
7090 16:33:14.603459 SW Impedance : PASS
7091 16:33:14.607188 DUTY Scan : NO K
7092 16:33:14.607272 ZQ Calibration : PASS
7093 16:33:14.610778 Jitter Meter : NO K
7094 16:33:14.613864 CBT Training : PASS
7095 16:33:14.613963 Write leveling : NO K
7096 16:33:14.617544 RX DQS gating : PASS
7097 16:33:14.620399 RX DQ/DQS(RDDQC) : PASS
7098 16:33:14.620482 TX DQ/DQS : PASS
7099 16:33:14.623898 RX DATLAT : PASS
7100 16:33:14.626799 RX DQ/DQS(Engine): PASS
7101 16:33:14.626889 TX OE : NO K
7102 16:33:14.630382 All Pass.
7103 16:33:14.630455
7104 16:33:14.630513 DramC Write-DBI off
7105 16:33:14.633977 PER_BANK_REFRESH: Hybrid Mode
7106 16:33:14.634085 TX_TRACKING: ON
7107 16:33:14.643787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7108 16:33:14.647242 [FAST_K] Save calibration result to emmc
7109 16:33:14.650579 dramc_set_vcore_voltage set vcore to 725000
7110 16:33:14.654039 Read voltage for 1600, 0
7111 16:33:14.654115 Vio18 = 0
7112 16:33:14.657327 Vcore = 725000
7113 16:33:14.657418 Vdram = 0
7114 16:33:14.657522 Vddq = 0
7115 16:33:14.657657 Vmddr = 0
7116 16:33:14.663922 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7117 16:33:14.670448 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7118 16:33:14.670565 MEM_TYPE=3, freq_sel=13
7119 16:33:14.673745 sv_algorithm_assistance_LP4_3733
7120 16:33:14.676783 ============ PULL DRAM RESETB DOWN ============
7121 16:33:14.683546 ========== PULL DRAM RESETB DOWN end =========
7122 16:33:14.687045 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7123 16:33:14.689913 ===================================
7124 16:33:14.693677 LPDDR4 DRAM CONFIGURATION
7125 16:33:14.696625 ===================================
7126 16:33:14.696731 EX_ROW_EN[0] = 0x0
7127 16:33:14.700173 EX_ROW_EN[1] = 0x0
7128 16:33:14.700291 LP4Y_EN = 0x0
7129 16:33:14.703803 WORK_FSP = 0x1
7130 16:33:14.706850 WL = 0x5
7131 16:33:14.706935 RL = 0x5
7132 16:33:14.710509 BL = 0x2
7133 16:33:14.710591 RPST = 0x0
7134 16:33:14.713376 RD_PRE = 0x0
7135 16:33:14.713448 WR_PRE = 0x1
7136 16:33:14.717104 WR_PST = 0x1
7137 16:33:14.717172 DBI_WR = 0x0
7138 16:33:14.719970 DBI_RD = 0x0
7139 16:33:14.720041 OTF = 0x1
7140 16:33:14.723393 ===================================
7141 16:33:14.726887 ===================================
7142 16:33:14.730349 ANA top config
7143 16:33:14.733172 ===================================
7144 16:33:14.733252 DLL_ASYNC_EN = 0
7145 16:33:14.736846 ALL_SLAVE_EN = 0
7146 16:33:14.740448 NEW_RANK_MODE = 1
7147 16:33:14.743235 DLL_IDLE_MODE = 1
7148 16:33:14.743307 LP45_APHY_COMB_EN = 1
7149 16:33:14.746770 TX_ODT_DIS = 0
7150 16:33:14.750469 NEW_8X_MODE = 1
7151 16:33:14.753467 ===================================
7152 16:33:14.756453 ===================================
7153 16:33:14.760013 data_rate = 3200
7154 16:33:14.763649 CKR = 1
7155 16:33:14.766383 DQ_P2S_RATIO = 8
7156 16:33:14.769863 ===================================
7157 16:33:14.769944 CA_P2S_RATIO = 8
7158 16:33:14.773158 DQ_CA_OPEN = 0
7159 16:33:14.776806 DQ_SEMI_OPEN = 0
7160 16:33:14.780324 CA_SEMI_OPEN = 0
7161 16:33:14.783111 CA_FULL_RATE = 0
7162 16:33:14.783196 DQ_CKDIV4_EN = 0
7163 16:33:14.786798 CA_CKDIV4_EN = 0
7164 16:33:14.789756 CA_PREDIV_EN = 0
7165 16:33:14.793205 PH8_DLY = 12
7166 16:33:14.796794 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7167 16:33:14.799687 DQ_AAMCK_DIV = 4
7168 16:33:14.803450 CA_AAMCK_DIV = 4
7169 16:33:14.803615 CA_ADMCK_DIV = 4
7170 16:33:14.806647 DQ_TRACK_CA_EN = 0
7171 16:33:14.810142 CA_PICK = 1600
7172 16:33:14.813080 CA_MCKIO = 1600
7173 16:33:14.816859 MCKIO_SEMI = 0
7174 16:33:14.819791 PLL_FREQ = 3068
7175 16:33:14.823554 DQ_UI_PI_RATIO = 32
7176 16:33:14.823634 CA_UI_PI_RATIO = 0
7177 16:33:14.826497 ===================================
7178 16:33:14.830255 ===================================
7179 16:33:14.833014 memory_type:LPDDR4
7180 16:33:14.836448 GP_NUM : 10
7181 16:33:14.836528 SRAM_EN : 1
7182 16:33:14.840005 MD32_EN : 0
7183 16:33:14.843592 ===================================
7184 16:33:14.846442 [ANA_INIT] >>>>>>>>>>>>>>
7185 16:33:14.850032 <<<<<< [CONFIGURE PHASE]: ANA_TX
7186 16:33:14.853399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7187 16:33:14.856335 ===================================
7188 16:33:14.856487 data_rate = 3200,PCW = 0X7600
7189 16:33:14.860065 ===================================
7190 16:33:14.863029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7191 16:33:14.869534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 16:33:14.876004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 16:33:14.879547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7194 16:33:14.882998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7195 16:33:14.886394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7196 16:33:14.889516 [ANA_INIT] flow start
7197 16:33:14.889673 [ANA_INIT] PLL >>>>>>>>
7198 16:33:14.893043 [ANA_INIT] PLL <<<<<<<<
7199 16:33:14.895980 [ANA_INIT] MIDPI >>>>>>>>
7200 16:33:14.899483 [ANA_INIT] MIDPI <<<<<<<<
7201 16:33:14.899626 [ANA_INIT] DLL >>>>>>>>
7202 16:33:14.902541 [ANA_INIT] DLL <<<<<<<<
7203 16:33:14.906171 [ANA_INIT] flow end
7204 16:33:14.909156 ============ LP4 DIFF to SE enter ============
7205 16:33:14.912760 ============ LP4 DIFF to SE exit ============
7206 16:33:14.916358 [ANA_INIT] <<<<<<<<<<<<<
7207 16:33:14.919285 [Flow] Enable top DCM control >>>>>
7208 16:33:14.922333 [Flow] Enable top DCM control <<<<<
7209 16:33:14.925935 Enable DLL master slave shuffle
7210 16:33:14.929598 ==============================================================
7211 16:33:14.932629 Gating Mode config
7212 16:33:14.935712 ==============================================================
7213 16:33:14.939354 Config description:
7214 16:33:14.948864 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7215 16:33:14.955378 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7216 16:33:14.958942 SELPH_MODE 0: By rank 1: By Phase
7217 16:33:14.965744 ==============================================================
7218 16:33:14.969275 GAT_TRACK_EN = 1
7219 16:33:14.972623 RX_GATING_MODE = 2
7220 16:33:14.975548 RX_GATING_TRACK_MODE = 2
7221 16:33:14.979214 SELPH_MODE = 1
7222 16:33:14.982282 PICG_EARLY_EN = 1
7223 16:33:14.985832 VALID_LAT_VALUE = 1
7224 16:33:14.988735 ==============================================================
7225 16:33:14.992328 Enter into Gating configuration >>>>
7226 16:33:14.995187 Exit from Gating configuration <<<<
7227 16:33:14.998743 Enter into DVFS_PRE_config >>>>>
7228 16:33:15.008571 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7229 16:33:15.012093 Exit from DVFS_PRE_config <<<<<
7230 16:33:15.015478 Enter into PICG configuration >>>>
7231 16:33:15.019054 Exit from PICG configuration <<<<
7232 16:33:15.021922 [RX_INPUT] configuration >>>>>
7233 16:33:15.025708 [RX_INPUT] configuration <<<<<
7234 16:33:15.032314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7235 16:33:15.035285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7236 16:33:15.042000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 16:33:15.048534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 16:33:15.055179 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 16:33:15.061703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 16:33:15.065348 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7241 16:33:15.069068 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7242 16:33:15.072432 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7243 16:33:15.078977 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7244 16:33:15.081725 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7245 16:33:15.085476 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 16:33:15.088480 ===================================
7247 16:33:15.092324 LPDDR4 DRAM CONFIGURATION
7248 16:33:15.095318 ===================================
7249 16:33:15.095417 EX_ROW_EN[0] = 0x0
7250 16:33:15.098388 EX_ROW_EN[1] = 0x0
7251 16:33:15.098476 LP4Y_EN = 0x0
7252 16:33:15.102205 WORK_FSP = 0x1
7253 16:33:15.105080 WL = 0x5
7254 16:33:15.105173 RL = 0x5
7255 16:33:15.108877 BL = 0x2
7256 16:33:15.108992 RPST = 0x0
7257 16:33:15.111773 RD_PRE = 0x0
7258 16:33:15.111859 WR_PRE = 0x1
7259 16:33:15.115437 WR_PST = 0x1
7260 16:33:15.115528 DBI_WR = 0x0
7261 16:33:15.118180 DBI_RD = 0x0
7262 16:33:15.118263 OTF = 0x1
7263 16:33:15.121581 ===================================
7264 16:33:15.124921 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7265 16:33:15.131575 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7266 16:33:15.134696 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 16:33:15.138021 ===================================
7268 16:33:15.141754 LPDDR4 DRAM CONFIGURATION
7269 16:33:15.144668 ===================================
7270 16:33:15.144749 EX_ROW_EN[0] = 0x10
7271 16:33:15.148478 EX_ROW_EN[1] = 0x0
7272 16:33:15.148556 LP4Y_EN = 0x0
7273 16:33:15.151479 WORK_FSP = 0x1
7274 16:33:15.151555 WL = 0x5
7275 16:33:15.155348 RL = 0x5
7276 16:33:15.155430 BL = 0x2
7277 16:33:15.158325 RPST = 0x0
7278 16:33:15.161303 RD_PRE = 0x0
7279 16:33:15.161403 WR_PRE = 0x1
7280 16:33:15.165054 WR_PST = 0x1
7281 16:33:15.165131 DBI_WR = 0x0
7282 16:33:15.167904 DBI_RD = 0x0
7283 16:33:15.167978 OTF = 0x1
7284 16:33:15.171565 ===================================
7285 16:33:15.178267 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7286 16:33:15.178369 ==
7287 16:33:15.181920 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 16:33:15.184748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 16:33:15.184822 ==
7290 16:33:15.188210 [Duty_Offset_Calibration]
7291 16:33:15.191463 B0:2 B1:1 CA:1
7292 16:33:15.191560
7293 16:33:15.194385 [DutyScan_Calibration_Flow] k_type=0
7294 16:33:15.203417
7295 16:33:15.203528 ==CLK 0==
7296 16:33:15.206447 Final CLK duty delay cell = 0
7297 16:33:15.209389 [0] MAX Duty = 5156%(X100), DQS PI = 22
7298 16:33:15.213098 [0] MIN Duty = 4844%(X100), DQS PI = 48
7299 16:33:15.213173 [0] AVG Duty = 5000%(X100)
7300 16:33:15.216806
7301 16:33:15.219800 CH0 CLK Duty spec in!! Max-Min= 312%
7302 16:33:15.222841 [DutyScan_Calibration_Flow] ====Done====
7303 16:33:15.222912
7304 16:33:15.226494 [DutyScan_Calibration_Flow] k_type=1
7305 16:33:15.242345
7306 16:33:15.242467 ==DQS 0 ==
7307 16:33:15.245763 Final DQS duty delay cell = -4
7308 16:33:15.248923 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7309 16:33:15.252384 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7310 16:33:15.255651 [-4] AVG Duty = 4891%(X100)
7311 16:33:15.255738
7312 16:33:15.255832 ==DQS 1 ==
7313 16:33:15.258721 Final DQS duty delay cell = 0
7314 16:33:15.262431 [0] MAX Duty = 5187%(X100), DQS PI = 20
7315 16:33:15.265698 [0] MIN Duty = 5031%(X100), DQS PI = 50
7316 16:33:15.268826 [0] AVG Duty = 5109%(X100)
7317 16:33:15.268910
7318 16:33:15.271850 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7319 16:33:15.271931
7320 16:33:15.275424 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7321 16:33:15.278479 [DutyScan_Calibration_Flow] ====Done====
7322 16:33:15.278605
7323 16:33:15.282251 [DutyScan_Calibration_Flow] k_type=3
7324 16:33:15.299792
7325 16:33:15.299904 ==DQM 0 ==
7326 16:33:15.302858 Final DQM duty delay cell = 0
7327 16:33:15.306756 [0] MAX Duty = 5187%(X100), DQS PI = 32
7328 16:33:15.309540 [0] MIN Duty = 4876%(X100), DQS PI = 60
7329 16:33:15.313273 [0] AVG Duty = 5031%(X100)
7330 16:33:15.313355
7331 16:33:15.313416 ==DQM 1 ==
7332 16:33:15.316348 Final DQM duty delay cell = 0
7333 16:33:15.319354 [0] MAX Duty = 5187%(X100), DQS PI = 20
7334 16:33:15.322999 [0] MIN Duty = 5031%(X100), DQS PI = 50
7335 16:33:15.326048 [0] AVG Duty = 5109%(X100)
7336 16:33:15.326122
7337 16:33:15.329778 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7338 16:33:15.329848
7339 16:33:15.332752 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7340 16:33:15.336247 [DutyScan_Calibration_Flow] ====Done====
7341 16:33:15.336325
7342 16:33:15.339189 [DutyScan_Calibration_Flow] k_type=2
7343 16:33:15.356753
7344 16:33:15.356864 ==DQ 0 ==
7345 16:33:15.360363 Final DQ duty delay cell = 0
7346 16:33:15.363295 [0] MAX Duty = 5062%(X100), DQS PI = 28
7347 16:33:15.366807 [0] MIN Duty = 4907%(X100), DQS PI = 0
7348 16:33:15.366880 [0] AVG Duty = 4984%(X100)
7349 16:33:15.366937
7350 16:33:15.370380 ==DQ 1 ==
7351 16:33:15.373161 Final DQ duty delay cell = 0
7352 16:33:15.377071 [0] MAX Duty = 5125%(X100), DQS PI = 6
7353 16:33:15.380381 [0] MIN Duty = 4907%(X100), DQS PI = 32
7354 16:33:15.380456 [0] AVG Duty = 5016%(X100)
7355 16:33:15.380520
7356 16:33:15.383532 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7357 16:33:15.386672
7358 16:33:15.389792 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7359 16:33:15.393241 [DutyScan_Calibration_Flow] ====Done====
7360 16:33:15.393317 ==
7361 16:33:15.396668 Dram Type= 6, Freq= 0, CH_1, rank 0
7362 16:33:15.400213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7363 16:33:15.400290 ==
7364 16:33:15.403508 [Duty_Offset_Calibration]
7365 16:33:15.403591 B0:1 B1:0 CA:0
7366 16:33:15.403661
7367 16:33:15.406982 [DutyScan_Calibration_Flow] k_type=0
7368 16:33:15.416587
7369 16:33:15.416691 ==CLK 0==
7370 16:33:15.419459 Final CLK duty delay cell = -4
7371 16:33:15.423256 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7372 16:33:15.426257 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7373 16:33:15.429954 [-4] AVG Duty = 4906%(X100)
7374 16:33:15.430040
7375 16:33:15.433064 CH1 CLK Duty spec in!! Max-Min= 125%
7376 16:33:15.435901 [DutyScan_Calibration_Flow] ====Done====
7377 16:33:15.435982
7378 16:33:15.439423 [DutyScan_Calibration_Flow] k_type=1
7379 16:33:15.456302
7380 16:33:15.456432 ==DQS 0 ==
7381 16:33:15.459288 Final DQS duty delay cell = 0
7382 16:33:15.462929 [0] MAX Duty = 5062%(X100), DQS PI = 8
7383 16:33:15.465942 [0] MIN Duty = 4844%(X100), DQS PI = 2
7384 16:33:15.466029 [0] AVG Duty = 4953%(X100)
7385 16:33:15.469738
7386 16:33:15.469822 ==DQS 1 ==
7387 16:33:15.472811 Final DQS duty delay cell = 0
7388 16:33:15.475931 [0] MAX Duty = 5249%(X100), DQS PI = 16
7389 16:33:15.479621 [0] MIN Duty = 4938%(X100), DQS PI = 8
7390 16:33:15.479705 [0] AVG Duty = 5093%(X100)
7391 16:33:15.482669
7392 16:33:15.486277 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7393 16:33:15.486358
7394 16:33:15.489059 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7395 16:33:15.492755 [DutyScan_Calibration_Flow] ====Done====
7396 16:33:15.492837
7397 16:33:15.495692 [DutyScan_Calibration_Flow] k_type=3
7398 16:33:15.512653
7399 16:33:15.512819 ==DQM 0 ==
7400 16:33:15.516235 Final DQM duty delay cell = 0
7401 16:33:15.519502 [0] MAX Duty = 5187%(X100), DQS PI = 10
7402 16:33:15.522999 [0] MIN Duty = 4938%(X100), DQS PI = 48
7403 16:33:15.526675 [0] AVG Duty = 5062%(X100)
7404 16:33:15.526768
7405 16:33:15.526830 ==DQM 1 ==
7406 16:33:15.529459 Final DQM duty delay cell = 0
7407 16:33:15.533046 [0] MAX Duty = 5062%(X100), DQS PI = 16
7408 16:33:15.535960 [0] MIN Duty = 4907%(X100), DQS PI = 34
7409 16:33:15.539695 [0] AVG Duty = 4984%(X100)
7410 16:33:15.539782
7411 16:33:15.542658 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7412 16:33:15.542735
7413 16:33:15.546476 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7414 16:33:15.549239 [DutyScan_Calibration_Flow] ====Done====
7415 16:33:15.549320
7416 16:33:15.552777 [DutyScan_Calibration_Flow] k_type=2
7417 16:33:15.569063
7418 16:33:15.569193 ==DQ 0 ==
7419 16:33:15.572670 Final DQ duty delay cell = -4
7420 16:33:15.575552 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7421 16:33:15.579247 [-4] MIN Duty = 4875%(X100), DQS PI = 44
7422 16:33:15.582192 [-4] AVG Duty = 4953%(X100)
7423 16:33:15.582323
7424 16:33:15.582450 ==DQ 1 ==
7425 16:33:15.585994 Final DQ duty delay cell = 0
7426 16:33:15.588941 [0] MAX Duty = 5156%(X100), DQS PI = 18
7427 16:33:15.592570 [0] MIN Duty = 4938%(X100), DQS PI = 8
7428 16:33:15.595439 [0] AVG Duty = 5047%(X100)
7429 16:33:15.595544
7430 16:33:15.599151 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7431 16:33:15.599238
7432 16:33:15.602060 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7433 16:33:15.605759 [DutyScan_Calibration_Flow] ====Done====
7434 16:33:15.608615 nWR fixed to 30
7435 16:33:15.612264 [ModeRegInit_LP4] CH0 RK0
7436 16:33:15.612365 [ModeRegInit_LP4] CH0 RK1
7437 16:33:15.615980 [ModeRegInit_LP4] CH1 RK0
7438 16:33:15.618810 [ModeRegInit_LP4] CH1 RK1
7439 16:33:15.618925 match AC timing 5
7440 16:33:15.625226 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7441 16:33:15.628676 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7442 16:33:15.632273 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7443 16:33:15.638692 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7444 16:33:15.642290 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7445 16:33:15.642380 [MiockJmeterHQA]
7446 16:33:15.642440
7447 16:33:15.645310 [DramcMiockJmeter] u1RxGatingPI = 0
7448 16:33:15.648941 0 : 4255, 4026
7449 16:33:15.649026 4 : 4253, 4027
7450 16:33:15.652506 8 : 4253, 4027
7451 16:33:15.652588 12 : 4252, 4027
7452 16:33:15.652649 16 : 4253, 4026
7453 16:33:15.655439 20 : 4252, 4027
7454 16:33:15.655520 24 : 4253, 4026
7455 16:33:15.659014 28 : 4366, 4139
7456 16:33:15.659095 32 : 4253, 4027
7457 16:33:15.661983 36 : 4255, 4029
7458 16:33:15.662062 40 : 4252, 4027
7459 16:33:15.662123 44 : 4363, 4137
7460 16:33:15.665666 48 : 4252, 4027
7461 16:33:15.665761 52 : 4363, 4137
7462 16:33:15.668618 56 : 4250, 4027
7463 16:33:15.668697 60 : 4250, 4027
7464 16:33:15.672354 64 : 4250, 4027
7465 16:33:15.672437 68 : 4253, 4029
7466 16:33:15.675333 72 : 4361, 4137
7467 16:33:15.675413 76 : 4250, 4026
7468 16:33:15.675473 80 : 4360, 4138
7469 16:33:15.679019 84 : 4250, 4026
7470 16:33:15.679100 88 : 4250, 115
7471 16:33:15.681884 92 : 4363, 0
7472 16:33:15.681964 96 : 4250, 0
7473 16:33:15.682023 100 : 4363, 0
7474 16:33:15.685466 104 : 4250, 0
7475 16:33:15.685595 108 : 4251, 0
7476 16:33:15.688491 112 : 4361, 0
7477 16:33:15.688571 116 : 4361, 0
7478 16:33:15.688631 120 : 4250, 0
7479 16:33:15.692039 124 : 4250, 0
7480 16:33:15.692120 128 : 4252, 0
7481 16:33:15.695710 132 : 4361, 0
7482 16:33:15.695791 136 : 4250, 0
7483 16:33:15.695851 140 : 4250, 0
7484 16:33:15.698643 144 : 4250, 0
7485 16:33:15.698727 148 : 4361, 0
7486 16:33:15.698788 152 : 4360, 0
7487 16:33:15.702347 156 : 4250, 0
7488 16:33:15.702429 160 : 4250, 0
7489 16:33:15.705322 164 : 4250, 0
7490 16:33:15.705402 168 : 4252, 0
7491 16:33:15.705462 172 : 4250, 0
7492 16:33:15.709167 176 : 4250, 0
7493 16:33:15.709265 180 : 4252, 0
7494 16:33:15.712020 184 : 4361, 0
7495 16:33:15.712115 188 : 4250, 0
7496 16:33:15.712178 192 : 4250, 0
7497 16:33:15.715496 196 : 4250, 0
7498 16:33:15.715579 200 : 4250, 0
7499 16:33:15.718995 204 : 4363, 1170
7500 16:33:15.719077 208 : 4250, 3989
7501 16:33:15.721748 212 : 4250, 4027
7502 16:33:15.721827 216 : 4250, 4027
7503 16:33:15.725071 220 : 4250, 4026
7504 16:33:15.725164 224 : 4250, 4027
7505 16:33:15.725278 228 : 4250, 4027
7506 16:33:15.728457 232 : 4250, 4027
7507 16:33:15.728536 236 : 4252, 4029
7508 16:33:15.731909 240 : 4250, 4027
7509 16:33:15.731991 244 : 4361, 4137
7510 16:33:15.735385 248 : 4361, 4137
7511 16:33:15.735467 252 : 4250, 4026
7512 16:33:15.738308 256 : 4363, 4140
7513 16:33:15.738405 260 : 4361, 4137
7514 16:33:15.741637 264 : 4250, 4027
7515 16:33:15.741718 268 : 4250, 4027
7516 16:33:15.745131 272 : 4253, 4029
7517 16:33:15.745212 276 : 4250, 4027
7518 16:33:15.748833 280 : 4250, 4027
7519 16:33:15.748915 284 : 4250, 4026
7520 16:33:15.748977 288 : 4250, 4026
7521 16:33:15.751764 292 : 4250, 4027
7522 16:33:15.751847 296 : 4361, 4137
7523 16:33:15.755421 300 : 4361, 4137
7524 16:33:15.755501 304 : 4250, 4026
7525 16:33:15.758414 308 : 4363, 4037
7526 16:33:15.758493 312 : 4361, 2208
7527 16:33:15.761873 316 : 4249, 4
7528 16:33:15.761953
7529 16:33:15.762012 MIOCK jitter meter ch=0
7530 16:33:15.762068
7531 16:33:15.764924 1T = (316-88) = 228 dly cells
7532 16:33:15.771642 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7533 16:33:15.771737 ==
7534 16:33:15.775417 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 16:33:15.778296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 16:33:15.778445 ==
7537 16:33:15.784857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 16:33:15.788656 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 16:33:15.791425 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 16:33:15.798485 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 16:33:15.807858 [CA 0] Center 42 (12~73) winsize 62
7542 16:33:15.811559 [CA 1] Center 42 (12~73) winsize 62
7543 16:33:15.814543 [CA 2] Center 38 (8~68) winsize 61
7544 16:33:15.818170 [CA 3] Center 37 (8~67) winsize 60
7545 16:33:15.821073 [CA 4] Center 36 (6~66) winsize 61
7546 16:33:15.824781 [CA 5] Center 35 (6~64) winsize 59
7547 16:33:15.824877
7548 16:33:15.827698 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7549 16:33:15.827775
7550 16:33:15.831301 [CATrainingPosCal] consider 1 rank data
7551 16:33:15.834770 u2DelayCellTimex100 = 285/100 ps
7552 16:33:15.837494 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7553 16:33:15.844440 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7554 16:33:15.847841 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7555 16:33:15.851384 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7556 16:33:15.854642 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7557 16:33:15.858260 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7558 16:33:15.858353
7559 16:33:15.861132 CA PerBit enable=1, Macro0, CA PI delay=35
7560 16:33:15.861233
7561 16:33:15.864519 [CBTSetCACLKResult] CA Dly = 35
7562 16:33:15.864592 CS Dly: 9 (0~40)
7563 16:33:15.871604 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 16:33:15.874432 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 16:33:15.874540 ==
7566 16:33:15.877424 Dram Type= 6, Freq= 0, CH_0, rank 1
7567 16:33:15.881254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 16:33:15.884402 ==
7569 16:33:15.887307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7570 16:33:15.890768 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7571 16:33:15.897608 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7572 16:33:15.901174 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7573 16:33:15.911117 [CA 0] Center 42 (12~72) winsize 61
7574 16:33:15.914871 [CA 1] Center 42 (12~73) winsize 62
7575 16:33:15.917810 [CA 2] Center 38 (8~68) winsize 61
7576 16:33:15.921542 [CA 3] Center 37 (7~68) winsize 62
7577 16:33:15.924518 [CA 4] Center 35 (5~65) winsize 61
7578 16:33:15.927579 [CA 5] Center 35 (5~65) winsize 61
7579 16:33:15.927659
7580 16:33:15.931376 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7581 16:33:15.931487
7582 16:33:15.934264 [CATrainingPosCal] consider 2 rank data
7583 16:33:15.938002 u2DelayCellTimex100 = 285/100 ps
7584 16:33:15.941015 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7585 16:33:15.947501 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7586 16:33:15.950936 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7587 16:33:15.954294 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7588 16:33:15.957697 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7589 16:33:15.961130 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7590 16:33:15.961213
7591 16:33:15.964564 CA PerBit enable=1, Macro0, CA PI delay=35
7592 16:33:15.964643
7593 16:33:15.967851 [CBTSetCACLKResult] CA Dly = 35
7594 16:33:15.970699 CS Dly: 10 (0~42)
7595 16:33:15.974235 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7596 16:33:15.977566 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7597 16:33:15.977714
7598 16:33:15.981031 ----->DramcWriteLeveling(PI) begin...
7599 16:33:15.981110 ==
7600 16:33:15.984343 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 16:33:15.991022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 16:33:15.991188 ==
7603 16:33:15.993833 Write leveling (Byte 0): 33 => 33
7604 16:33:15.993923 Write leveling (Byte 1): 30 => 30
7605 16:33:15.997561 DramcWriteLeveling(PI) end<-----
7606 16:33:15.997725
7607 16:33:16.000524 ==
7608 16:33:16.000625 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 16:33:16.007204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 16:33:16.007332 ==
7611 16:33:16.010586 [Gating] SW mode calibration
7612 16:33:16.017444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7613 16:33:16.020397 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7614 16:33:16.027077 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7615 16:33:16.030247 1 4 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7616 16:33:16.034173 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7617 16:33:16.040085 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7618 16:33:16.043812 1 4 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7619 16:33:16.047632 1 4 20 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7620 16:33:16.053514 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7621 16:33:16.057385 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7622 16:33:16.060277 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7623 16:33:16.067052 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7624 16:33:16.070321 1 5 8 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 1)
7625 16:33:16.074136 1 5 12 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (1 0)
7626 16:33:16.077355 1 5 16 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
7627 16:33:16.084162 1 5 20 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
7628 16:33:16.087102 1 5 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7629 16:33:16.090630 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7630 16:33:16.096915 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7631 16:33:16.100477 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7632 16:33:16.104047 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7633 16:33:16.110507 1 6 12 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
7634 16:33:16.114069 1 6 16 | B1->B0 | 2b2b 4645 | 0 1 | (0 0) (0 0)
7635 16:33:16.117013 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (0 0)
7636 16:33:16.124030 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 16:33:16.127435 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 16:33:16.130324 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 16:33:16.136811 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 16:33:16.140533 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 16:33:16.143502 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 16:33:16.150294 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7643 16:33:16.153897 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7644 16:33:16.156810 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 16:33:16.163495 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 16:33:16.167165 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 16:33:16.170052 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 16:33:16.176767 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 16:33:16.180269 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 16:33:16.183708 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 16:33:16.189915 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 16:33:16.193217 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 16:33:16.196908 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 16:33:16.203713 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 16:33:16.207078 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 16:33:16.210402 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 16:33:16.213760 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 16:33:16.220225 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7659 16:33:16.223618 Total UI for P1: 0, mck2ui 16
7660 16:33:16.226551 best dqsien dly found for B0: ( 1, 9, 10)
7661 16:33:16.230144 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7662 16:33:16.233642 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 16:33:16.236496 Total UI for P1: 0, mck2ui 16
7664 16:33:16.240018 best dqsien dly found for B1: ( 1, 9, 20)
7665 16:33:16.243658 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7666 16:33:16.246692 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7667 16:33:16.249859
7668 16:33:16.253576 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7669 16:33:16.256508 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7670 16:33:16.260464 [Gating] SW calibration Done
7671 16:33:16.260564 ==
7672 16:33:16.263393 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 16:33:16.267091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 16:33:16.267186 ==
7675 16:33:16.267281 RX Vref Scan: 0
7676 16:33:16.270057
7677 16:33:16.270125 RX Vref 0 -> 0, step: 1
7678 16:33:16.270182
7679 16:33:16.273082 RX Delay 0 -> 252, step: 8
7680 16:33:16.276864 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7681 16:33:16.279826 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7682 16:33:16.286534 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7683 16:33:16.290299 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7684 16:33:16.293528 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7685 16:33:16.296417 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7686 16:33:16.300192 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7687 16:33:16.306782 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7688 16:33:16.310058 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7689 16:33:16.313392 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7690 16:33:16.316633 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7691 16:33:16.319950 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7692 16:33:16.326256 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7693 16:33:16.329568 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7694 16:33:16.333135 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7695 16:33:16.336421 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7696 16:33:16.336525 ==
7697 16:33:16.339720 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 16:33:16.343069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 16:33:16.346268 ==
7700 16:33:16.346372 DQS Delay:
7701 16:33:16.346459 DQS0 = 0, DQS1 = 0
7702 16:33:16.349524 DQM Delay:
7703 16:33:16.349639 DQM0 = 137, DQM1 = 131
7704 16:33:16.352999 DQ Delay:
7705 16:33:16.356516 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7706 16:33:16.359327 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7707 16:33:16.362980 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7708 16:33:16.366027 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =135
7709 16:33:16.366099
7710 16:33:16.366159
7711 16:33:16.366213 ==
7712 16:33:16.369602 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 16:33:16.372746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 16:33:16.372824 ==
7715 16:33:16.376561
7716 16:33:16.376639
7717 16:33:16.376698 TX Vref Scan disable
7718 16:33:16.379493 == TX Byte 0 ==
7719 16:33:16.382482 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7720 16:33:16.386360 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7721 16:33:16.389365 == TX Byte 1 ==
7722 16:33:16.393044 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7723 16:33:16.395972 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7724 16:33:16.396105 ==
7725 16:33:16.399655 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 16:33:16.405488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 16:33:16.405644 ==
7728 16:33:16.416503
7729 16:33:16.420219 TX Vref early break, caculate TX vref
7730 16:33:16.423115 TX Vref=16, minBit 4, minWin=23, winSum=379
7731 16:33:16.426630 TX Vref=18, minBit 3, minWin=23, winSum=391
7732 16:33:16.430107 TX Vref=20, minBit 4, minWin=24, winSum=400
7733 16:33:16.433469 TX Vref=22, minBit 4, minWin=24, winSum=410
7734 16:33:16.436838 TX Vref=24, minBit 5, minWin=25, winSum=422
7735 16:33:16.443410 TX Vref=26, minBit 0, minWin=26, winSum=430
7736 16:33:16.446456 TX Vref=28, minBit 6, minWin=25, winSum=428
7737 16:33:16.450235 TX Vref=30, minBit 6, minWin=24, winSum=420
7738 16:33:16.453168 TX Vref=32, minBit 1, minWin=24, winSum=406
7739 16:33:16.459527 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
7740 16:33:16.459617
7741 16:33:16.462959 Final TX Range 0 Vref 26
7742 16:33:16.463037
7743 16:33:16.463098 ==
7744 16:33:16.466327 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 16:33:16.470056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 16:33:16.470139 ==
7747 16:33:16.470200
7748 16:33:16.470275
7749 16:33:16.472730 TX Vref Scan disable
7750 16:33:16.476192 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7751 16:33:16.479951 == TX Byte 0 ==
7752 16:33:16.482851 u2DelayCellOfst[0]=13 cells (4 PI)
7753 16:33:16.486552 u2DelayCellOfst[1]=13 cells (4 PI)
7754 16:33:16.489543 u2DelayCellOfst[2]=10 cells (3 PI)
7755 16:33:16.493315 u2DelayCellOfst[3]=10 cells (3 PI)
7756 16:33:16.496224 u2DelayCellOfst[4]=6 cells (2 PI)
7757 16:33:16.499865 u2DelayCellOfst[5]=0 cells (0 PI)
7758 16:33:16.499984 u2DelayCellOfst[6]=17 cells (5 PI)
7759 16:33:16.502866 u2DelayCellOfst[7]=17 cells (5 PI)
7760 16:33:16.509272 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7761 16:33:16.512919 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7762 16:33:16.513032 == TX Byte 1 ==
7763 16:33:16.515867 u2DelayCellOfst[8]=3 cells (1 PI)
7764 16:33:16.519596 u2DelayCellOfst[9]=0 cells (0 PI)
7765 16:33:16.522681 u2DelayCellOfst[10]=6 cells (2 PI)
7766 16:33:16.526445 u2DelayCellOfst[11]=3 cells (1 PI)
7767 16:33:16.529211 u2DelayCellOfst[12]=10 cells (3 PI)
7768 16:33:16.532846 u2DelayCellOfst[13]=10 cells (3 PI)
7769 16:33:16.536602 u2DelayCellOfst[14]=13 cells (4 PI)
7770 16:33:16.539631 u2DelayCellOfst[15]=10 cells (3 PI)
7771 16:33:16.543137 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7772 16:33:16.545876 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7773 16:33:16.549373 DramC Write-DBI on
7774 16:33:16.549457 ==
7775 16:33:16.552787 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 16:33:16.556425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 16:33:16.556506 ==
7778 16:33:16.556567
7779 16:33:16.556624
7780 16:33:16.559432 TX Vref Scan disable
7781 16:33:16.562508 == TX Byte 0 ==
7782 16:33:16.566290 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7783 16:33:16.569334 == TX Byte 1 ==
7784 16:33:16.572834 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7785 16:33:16.572920 DramC Write-DBI off
7786 16:33:16.572981
7787 16:33:16.575638 [DATLAT]
7788 16:33:16.575719 Freq=1600, CH0 RK0
7789 16:33:16.575781
7790 16:33:16.579231 DATLAT Default: 0xf
7791 16:33:16.579310 0, 0xFFFF, sum = 0
7792 16:33:16.582866 1, 0xFFFF, sum = 0
7793 16:33:16.582946 2, 0xFFFF, sum = 0
7794 16:33:16.586101 3, 0xFFFF, sum = 0
7795 16:33:16.586206 4, 0xFFFF, sum = 0
7796 16:33:16.589431 5, 0xFFFF, sum = 0
7797 16:33:16.589513 6, 0xFFFF, sum = 0
7798 16:33:16.593016 7, 0xFFFF, sum = 0
7799 16:33:16.593151 8, 0xFFFF, sum = 0
7800 16:33:16.595924 9, 0xFFFF, sum = 0
7801 16:33:16.599526 10, 0xFFFF, sum = 0
7802 16:33:16.599641 11, 0xFFFF, sum = 0
7803 16:33:16.602387 12, 0xFFFF, sum = 0
7804 16:33:16.602484 13, 0xFFFF, sum = 0
7805 16:33:16.606025 14, 0x0, sum = 1
7806 16:33:16.606128 15, 0x0, sum = 2
7807 16:33:16.608983 16, 0x0, sum = 3
7808 16:33:16.609108 17, 0x0, sum = 4
7809 16:33:16.609171 best_step = 15
7810 16:33:16.612515
7811 16:33:16.612613 ==
7812 16:33:16.615536 Dram Type= 6, Freq= 0, CH_0, rank 0
7813 16:33:16.619277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7814 16:33:16.619424 ==
7815 16:33:16.619503 RX Vref Scan: 1
7816 16:33:16.619591
7817 16:33:16.622269 Set Vref Range= 24 -> 127
7818 16:33:16.622353
7819 16:33:16.625831 RX Vref 24 -> 127, step: 1
7820 16:33:16.625909
7821 16:33:16.628794 RX Delay 27 -> 252, step: 4
7822 16:33:16.628872
7823 16:33:16.632546 Set Vref, RX VrefLevel [Byte0]: 24
7824 16:33:16.635399 [Byte1]: 24
7825 16:33:16.635546
7826 16:33:16.638483 Set Vref, RX VrefLevel [Byte0]: 25
7827 16:33:16.642179 [Byte1]: 25
7828 16:33:16.642258
7829 16:33:16.645841 Set Vref, RX VrefLevel [Byte0]: 26
7830 16:33:16.648800 [Byte1]: 26
7831 16:33:16.652593
7832 16:33:16.652700 Set Vref, RX VrefLevel [Byte0]: 27
7833 16:33:16.656048 [Byte1]: 27
7834 16:33:16.660184
7835 16:33:16.660282 Set Vref, RX VrefLevel [Byte0]: 28
7836 16:33:16.663485 [Byte1]: 28
7837 16:33:16.667392
7838 16:33:16.667473 Set Vref, RX VrefLevel [Byte0]: 29
7839 16:33:16.670906 [Byte1]: 29
7840 16:33:16.674684
7841 16:33:16.674764 Set Vref, RX VrefLevel [Byte0]: 30
7842 16:33:16.678399 [Byte1]: 30
7843 16:33:16.682786
7844 16:33:16.682869 Set Vref, RX VrefLevel [Byte0]: 31
7845 16:33:16.685897 [Byte1]: 31
7846 16:33:16.690410
7847 16:33:16.690488 Set Vref, RX VrefLevel [Byte0]: 32
7848 16:33:16.693221 [Byte1]: 32
7849 16:33:16.697403
7850 16:33:16.697560 Set Vref, RX VrefLevel [Byte0]: 33
7851 16:33:16.701049 [Byte1]: 33
7852 16:33:16.705057
7853 16:33:16.705203 Set Vref, RX VrefLevel [Byte0]: 34
7854 16:33:16.708480 [Byte1]: 34
7855 16:33:16.712715
7856 16:33:16.712800 Set Vref, RX VrefLevel [Byte0]: 35
7857 16:33:16.716298 [Byte1]: 35
7858 16:33:16.719935
7859 16:33:16.720014 Set Vref, RX VrefLevel [Byte0]: 36
7860 16:33:16.723290 [Byte1]: 36
7861 16:33:16.727543
7862 16:33:16.727624 Set Vref, RX VrefLevel [Byte0]: 37
7863 16:33:16.731149 [Byte1]: 37
7864 16:33:16.734930
7865 16:33:16.735040 Set Vref, RX VrefLevel [Byte0]: 38
7866 16:33:16.738567 [Byte1]: 38
7867 16:33:16.742818
7868 16:33:16.742937 Set Vref, RX VrefLevel [Byte0]: 39
7869 16:33:16.745760 [Byte1]: 39
7870 16:33:16.750279
7871 16:33:16.750378 Set Vref, RX VrefLevel [Byte0]: 40
7872 16:33:16.753390 [Byte1]: 40
7873 16:33:16.800606
7874 16:33:16.800712 Set Vref, RX VrefLevel [Byte0]: 41
7875 16:33:16.800809 [Byte1]: 41
7876 16:33:16.800893
7877 16:33:16.800985 Set Vref, RX VrefLevel [Byte0]: 42
7878 16:33:16.801068 [Byte1]: 42
7879 16:33:16.801146
7880 16:33:16.801234 Set Vref, RX VrefLevel [Byte0]: 43
7881 16:33:16.801315 [Byte1]: 43
7882 16:33:16.801392
7883 16:33:16.801479 Set Vref, RX VrefLevel [Byte0]: 44
7884 16:33:16.801570 [Byte1]: 44
7885 16:33:16.801650
7886 16:33:16.801737 Set Vref, RX VrefLevel [Byte0]: 45
7887 16:33:16.801817 [Byte1]: 45
7888 16:33:16.801894
7889 16:33:16.801982 Set Vref, RX VrefLevel [Byte0]: 46
7890 16:33:16.802061 [Byte1]: 46
7891 16:33:16.803128
7892 16:33:16.803221 Set Vref, RX VrefLevel [Byte0]: 47
7893 16:33:16.806105 [Byte1]: 47
7894 16:33:16.810534
7895 16:33:16.810632 Set Vref, RX VrefLevel [Byte0]: 48
7896 16:33:16.814208 [Byte1]: 48
7897 16:33:16.817805
7898 16:33:16.817957 Set Vref, RX VrefLevel [Byte0]: 49
7899 16:33:16.821207 [Byte1]: 49
7900 16:33:16.876208
7901 16:33:16.876402 Set Vref, RX VrefLevel [Byte0]: 50
7902 16:33:16.876521 [Byte1]: 50
7903 16:33:16.876635
7904 16:33:16.876715 Set Vref, RX VrefLevel [Byte0]: 51
7905 16:33:16.876801 [Byte1]: 51
7906 16:33:16.876899
7907 16:33:16.876976 Set Vref, RX VrefLevel [Byte0]: 52
7908 16:33:16.877069 [Byte1]: 52
7909 16:33:16.877159
7910 16:33:16.877233 Set Vref, RX VrefLevel [Byte0]: 53
7911 16:33:16.877325 [Byte1]: 53
7912 16:33:16.877424
7913 16:33:16.877520 Set Vref, RX VrefLevel [Byte0]: 54
7914 16:33:16.877638 [Byte1]: 54
7915 16:33:16.877706
7916 16:33:16.877772 Set Vref, RX VrefLevel [Byte0]: 55
7917 16:33:16.877826 [Byte1]: 55
7918 16:33:16.877876
7919 16:33:16.877926 Set Vref, RX VrefLevel [Byte0]: 56
7920 16:33:16.877975 [Byte1]: 56
7921 16:33:16.878276
7922 16:33:16.878364 Set Vref, RX VrefLevel [Byte0]: 57
7923 16:33:16.881326 [Byte1]: 57
7924 16:33:16.885731
7925 16:33:16.885848 Set Vref, RX VrefLevel [Byte0]: 58
7926 16:33:16.889501 [Byte1]: 58
7927 16:33:16.893785
7928 16:33:16.893894 Set Vref, RX VrefLevel [Byte0]: 59
7929 16:33:16.896631 [Byte1]: 59
7930 16:33:16.900753
7931 16:33:16.900881 Set Vref, RX VrefLevel [Byte0]: 60
7932 16:33:16.904046 [Byte1]: 60
7933 16:33:16.908347
7934 16:33:16.908449 Set Vref, RX VrefLevel [Byte0]: 61
7935 16:33:16.912020 [Byte1]: 61
7936 16:33:16.970435
7937 16:33:16.970553 Set Vref, RX VrefLevel [Byte0]: 62
7938 16:33:16.970620 [Byte1]: 62
7939 16:33:16.970678
7940 16:33:16.970734 Set Vref, RX VrefLevel [Byte0]: 63
7941 16:33:16.970819 [Byte1]: 63
7942 16:33:16.970879
7943 16:33:16.970932 Set Vref, RX VrefLevel [Byte0]: 64
7944 16:33:16.970984 [Byte1]: 64
7945 16:33:16.971036
7946 16:33:16.971087 Set Vref, RX VrefLevel [Byte0]: 65
7947 16:33:16.971139 [Byte1]: 65
7948 16:33:16.971189
7949 16:33:16.971239 Set Vref, RX VrefLevel [Byte0]: 66
7950 16:33:16.971289 [Byte1]: 66
7951 16:33:16.971339
7952 16:33:16.971388 Set Vref, RX VrefLevel [Byte0]: 67
7953 16:33:16.971438 [Byte1]: 67
7954 16:33:16.971487
7955 16:33:16.971536 Set Vref, RX VrefLevel [Byte0]: 68
7956 16:33:16.971586 [Byte1]: 68
7957 16:33:16.971636
7958 16:33:16.971685 Set Vref, RX VrefLevel [Byte0]: 69
7959 16:33:16.972420 [Byte1]: 69
7960 16:33:16.976202
7961 16:33:16.976279 Set Vref, RX VrefLevel [Byte0]: 70
7962 16:33:16.979972 [Byte1]: 70
7963 16:33:16.983634
7964 16:33:16.983730 Set Vref, RX VrefLevel [Byte0]: 71
7965 16:33:16.987276 [Byte1]: 71
7966 16:33:16.991551
7967 16:33:16.991658 Set Vref, RX VrefLevel [Byte0]: 72
7968 16:33:16.994536 [Byte1]: 72
7969 16:33:16.998996
7970 16:33:16.999085 Final RX Vref Byte 0 = 55 to rank0
7971 16:33:17.002519 Final RX Vref Byte 1 = 61 to rank0
7972 16:33:17.005315 Final RX Vref Byte 0 = 55 to rank1
7973 16:33:17.008666 Final RX Vref Byte 1 = 61 to rank1==
7974 16:33:17.012226 Dram Type= 6, Freq= 0, CH_0, rank 0
7975 16:33:17.018751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 16:33:17.018967 ==
7977 16:33:17.019104 DQS Delay:
7978 16:33:17.019221 DQS0 = 0, DQS1 = 0
7979 16:33:17.022467 DQM Delay:
7980 16:33:17.022672 DQM0 = 133, DQM1 = 127
7981 16:33:17.025316 DQ Delay:
7982 16:33:17.028383 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7983 16:33:17.032231 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7984 16:33:17.035165 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7985 16:33:17.038929 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7986 16:33:17.039063
7987 16:33:17.039183
7988 16:33:17.039263
7989 16:33:17.041725 [DramC_TX_OE_Calibration] TA2
7990 16:33:17.045362 Original DQ_B0 (3 6) =30, OEN = 27
7991 16:33:17.048348 Original DQ_B1 (3 6) =30, OEN = 27
7992 16:33:17.052033 24, 0x0, End_B0=24 End_B1=24
7993 16:33:17.052196 25, 0x0, End_B0=25 End_B1=25
7994 16:33:17.055128 26, 0x0, End_B0=26 End_B1=26
7995 16:33:17.058898 27, 0x0, End_B0=27 End_B1=27
7996 16:33:17.061853 28, 0x0, End_B0=28 End_B1=28
7997 16:33:17.065258 29, 0x0, End_B0=29 End_B1=29
7998 16:33:17.065359 30, 0x0, End_B0=30 End_B1=30
7999 16:33:17.068615 31, 0x4141, End_B0=30 End_B1=30
8000 16:33:17.071921 Byte0 end_step=30 best_step=27
8001 16:33:17.075354 Byte1 end_step=30 best_step=27
8002 16:33:17.078701 Byte0 TX OE(2T, 0.5T) = (3, 3)
8003 16:33:17.082043 Byte1 TX OE(2T, 0.5T) = (3, 3)
8004 16:33:17.082147
8005 16:33:17.082234
8006 16:33:17.088141 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
8007 16:33:17.091838 CH0 RK0: MR19=303, MR18=2824
8008 16:33:17.098262 CH0_RK0: MR19=0x303, MR18=0x2824, DQSOSC=389, MR23=63, INC=24, DEC=16
8009 16:33:17.098391
8010 16:33:17.101832 ----->DramcWriteLeveling(PI) begin...
8011 16:33:17.101911 ==
8012 16:33:17.104854 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 16:33:17.108412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 16:33:17.108506 ==
8015 16:33:17.111649 Write leveling (Byte 0): 36 => 36
8016 16:33:17.115357 Write leveling (Byte 1): 27 => 27
8017 16:33:17.118063 DramcWriteLeveling(PI) end<-----
8018 16:33:17.118168
8019 16:33:17.118252 ==
8020 16:33:17.121383 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 16:33:17.124968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 16:33:17.125110 ==
8023 16:33:17.128609 [Gating] SW mode calibration
8024 16:33:17.135134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8025 16:33:17.141974 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8026 16:33:17.144937 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 16:33:17.148687 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 16:33:17.155044 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 16:33:17.158027 1 4 12 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8030 16:33:17.161797 1 4 16 | B1->B0 | 2b2a 3535 | 1 1 | (1 1) (1 1)
8031 16:33:17.168378 1 4 20 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8032 16:33:17.171368 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
8033 16:33:17.174800 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8034 16:33:17.181481 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8035 16:33:17.185171 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8036 16:33:17.188060 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 0)
8037 16:33:17.195106 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
8038 16:33:17.198311 1 5 16 | B1->B0 | 2c2c 2a2a | 1 0 | (1 0) (0 0)
8039 16:33:17.201634 1 5 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8040 16:33:17.208219 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8041 16:33:17.211320 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8042 16:33:17.214372 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8043 16:33:17.221028 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
8044 16:33:17.224361 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 16:33:17.227737 1 6 12 | B1->B0 | 2424 3232 | 0 0 | (0 0) (1 1)
8046 16:33:17.234623 1 6 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8047 16:33:17.238331 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8048 16:33:17.241275 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8049 16:33:17.247781 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 16:33:17.251550 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 16:33:17.254496 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 16:33:17.261161 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 16:33:17.264691 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8054 16:33:17.267707 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8055 16:33:17.271485 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 16:33:17.278281 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 16:33:17.281147 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 16:33:17.284841 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 16:33:17.291629 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 16:33:17.294619 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 16:33:17.297492 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 16:33:17.304665 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 16:33:17.307642 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 16:33:17.311293 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 16:33:17.317990 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 16:33:17.320763 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 16:33:17.324286 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 16:33:17.330936 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 16:33:17.334147 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8070 16:33:17.337456 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8071 16:33:17.344453 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 16:33:17.344569 Total UI for P1: 0, mck2ui 16
8073 16:33:17.351152 best dqsien dly found for B0: ( 1, 9, 14)
8074 16:33:17.351259 Total UI for P1: 0, mck2ui 16
8075 16:33:17.357382 best dqsien dly found for B1: ( 1, 9, 14)
8076 16:33:17.360697 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8077 16:33:17.363985 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8078 16:33:17.364104
8079 16:33:17.367408 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8080 16:33:17.370787 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8081 16:33:17.374503 [Gating] SW calibration Done
8082 16:33:17.374588 ==
8083 16:33:17.377650 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 16:33:17.380648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 16:33:17.380759 ==
8086 16:33:17.384374 RX Vref Scan: 0
8087 16:33:17.384473
8088 16:33:17.384558 RX Vref 0 -> 0, step: 1
8089 16:33:17.384629
8090 16:33:17.387209 RX Delay 0 -> 252, step: 8
8091 16:33:17.390962 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8092 16:33:17.397681 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8093 16:33:17.400696 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8094 16:33:17.404400 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8095 16:33:17.407289 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8096 16:33:17.411212 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8097 16:33:17.417047 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8098 16:33:17.420791 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8099 16:33:17.423749 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8100 16:33:17.427465 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8101 16:33:17.430576 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8102 16:33:17.437229 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8103 16:33:17.440217 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8104 16:33:17.443894 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8105 16:33:17.447541 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8106 16:33:17.450487 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8107 16:33:17.454292 ==
8108 16:33:17.457156 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 16:33:17.460740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 16:33:17.460829 ==
8111 16:33:17.460893 DQS Delay:
8112 16:33:17.463699 DQS0 = 0, DQS1 = 0
8113 16:33:17.463766 DQM Delay:
8114 16:33:17.467202 DQM0 = 137, DQM1 = 129
8115 16:33:17.467309 DQ Delay:
8116 16:33:17.470534 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8117 16:33:17.473751 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8118 16:33:17.476958 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8119 16:33:17.480417 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8120 16:33:17.480518
8121 16:33:17.480593
8122 16:33:17.480650 ==
8123 16:33:17.483435 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 16:33:17.489972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 16:33:17.490081 ==
8126 16:33:17.490174
8127 16:33:17.490258
8128 16:33:17.490343 TX Vref Scan disable
8129 16:33:17.493710 == TX Byte 0 ==
8130 16:33:17.497278 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8131 16:33:17.501132 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8132 16:33:17.504229 == TX Byte 1 ==
8133 16:33:17.507561 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8134 16:33:17.510955 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8135 16:33:17.513812 ==
8136 16:33:17.517490 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 16:33:17.520423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 16:33:17.520551 ==
8139 16:33:17.535537
8140 16:33:17.538533 TX Vref early break, caculate TX vref
8141 16:33:17.542290 TX Vref=16, minBit 0, minWin=23, winSum=387
8142 16:33:17.545271 TX Vref=18, minBit 1, minWin=23, winSum=397
8143 16:33:17.548950 TX Vref=20, minBit 1, minWin=23, winSum=404
8144 16:33:17.551881 TX Vref=22, minBit 1, minWin=24, winSum=411
8145 16:33:17.554840 TX Vref=24, minBit 1, minWin=25, winSum=420
8146 16:33:17.564127 TX Vref=26, minBit 7, minWin=24, winSum=423
8147 16:33:17.565177 TX Vref=28, minBit 7, minWin=24, winSum=421
8148 16:33:17.568056 TX Vref=30, minBit 0, minWin=25, winSum=415
8149 16:33:17.571870 TX Vref=32, minBit 1, minWin=24, winSum=409
8150 16:33:17.574834 TX Vref=34, minBit 0, minWin=24, winSum=401
8151 16:33:17.580335 TX Vref=36, minBit 7, minWin=23, winSum=395
8152 16:33:17.585346 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 24
8153 16:33:17.585475
8154 16:33:17.588300 Final TX Range 0 Vref 24
8155 16:33:17.588405
8156 16:33:17.588494 ==
8157 16:33:17.591986 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 16:33:17.594983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 16:33:17.595134 ==
8160 16:33:17.595227
8161 16:33:17.595345
8162 16:33:17.598344 TX Vref Scan disable
8163 16:33:17.605096 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8164 16:33:17.605278 == TX Byte 0 ==
8165 16:33:17.608327 u2DelayCellOfst[0]=13 cells (4 PI)
8166 16:33:17.611557 u2DelayCellOfst[1]=17 cells (5 PI)
8167 16:33:17.615117 u2DelayCellOfst[2]=13 cells (4 PI)
8168 16:33:17.617899 u2DelayCellOfst[3]=10 cells (3 PI)
8169 16:33:17.621377 u2DelayCellOfst[4]=10 cells (3 PI)
8170 16:33:17.624589 u2DelayCellOfst[5]=0 cells (0 PI)
8171 16:33:17.628352 u2DelayCellOfst[6]=17 cells (5 PI)
8172 16:33:17.631536 u2DelayCellOfst[7]=17 cells (5 PI)
8173 16:33:17.634684 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8174 16:33:17.637931 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8175 16:33:17.641649 == TX Byte 1 ==
8176 16:33:17.644903 u2DelayCellOfst[8]=3 cells (1 PI)
8177 16:33:17.647735 u2DelayCellOfst[9]=0 cells (0 PI)
8178 16:33:17.651529 u2DelayCellOfst[10]=6 cells (2 PI)
8179 16:33:17.651664 u2DelayCellOfst[11]=3 cells (1 PI)
8180 16:33:17.654498 u2DelayCellOfst[12]=10 cells (3 PI)
8181 16:33:17.658148 u2DelayCellOfst[13]=10 cells (3 PI)
8182 16:33:17.661172 u2DelayCellOfst[14]=13 cells (4 PI)
8183 16:33:17.664850 u2DelayCellOfst[15]=10 cells (3 PI)
8184 16:33:17.668506 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8185 16:33:17.674716 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8186 16:33:17.674842 DramC Write-DBI on
8187 16:33:17.674930 ==
8188 16:33:17.678489 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 16:33:17.684471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 16:33:17.684588 ==
8191 16:33:17.684652
8192 16:33:17.684707
8193 16:33:17.684760 TX Vref Scan disable
8194 16:33:17.688814 == TX Byte 0 ==
8195 16:33:17.691933 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8196 16:33:17.695600 == TX Byte 1 ==
8197 16:33:17.698483 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8198 16:33:17.702199 DramC Write-DBI off
8199 16:33:17.702384
8200 16:33:17.702484 [DATLAT]
8201 16:33:17.702574 Freq=1600, CH0 RK1
8202 16:33:17.702664
8203 16:33:17.705064 DATLAT Default: 0xf
8204 16:33:17.705252 0, 0xFFFF, sum = 0
8205 16:33:17.708769 1, 0xFFFF, sum = 0
8206 16:33:17.711862 2, 0xFFFF, sum = 0
8207 16:33:17.712042 3, 0xFFFF, sum = 0
8208 16:33:17.715457 4, 0xFFFF, sum = 0
8209 16:33:17.715613 5, 0xFFFF, sum = 0
8210 16:33:17.718407 6, 0xFFFF, sum = 0
8211 16:33:17.718602 7, 0xFFFF, sum = 0
8212 16:33:17.722178 8, 0xFFFF, sum = 0
8213 16:33:17.722368 9, 0xFFFF, sum = 0
8214 16:33:17.725048 10, 0xFFFF, sum = 0
8215 16:33:17.725163 11, 0xFFFF, sum = 0
8216 16:33:17.728786 12, 0xFFFF, sum = 0
8217 16:33:17.728869 13, 0xFFFF, sum = 0
8218 16:33:17.731681 14, 0x0, sum = 1
8219 16:33:17.731750 15, 0x0, sum = 2
8220 16:33:17.735570 16, 0x0, sum = 3
8221 16:33:17.735638 17, 0x0, sum = 4
8222 16:33:17.738450 best_step = 15
8223 16:33:17.738516
8224 16:33:17.738576 ==
8225 16:33:17.742087 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 16:33:17.745388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 16:33:17.745475 ==
8228 16:33:17.748819 RX Vref Scan: 0
8229 16:33:17.748888
8230 16:33:17.748945 RX Vref 0 -> 0, step: 1
8231 16:33:17.748997
8232 16:33:17.751541 RX Delay 19 -> 252, step: 4
8233 16:33:17.755022 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8234 16:33:17.761907 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8235 16:33:17.764908 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8236 16:33:17.768329 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8237 16:33:17.771725 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8238 16:33:17.774839 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8239 16:33:17.781684 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8240 16:33:17.784609 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8241 16:33:17.788423 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8242 16:33:17.791443 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8243 16:33:17.795234 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8244 16:33:17.801283 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8245 16:33:17.804912 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8246 16:33:17.807975 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8247 16:33:17.811690 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8248 16:33:17.814607 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8249 16:33:17.818354 ==
8250 16:33:17.821199 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 16:33:17.824938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 16:33:17.825078 ==
8253 16:33:17.825186 DQS Delay:
8254 16:33:17.827973 DQS0 = 0, DQS1 = 0
8255 16:33:17.828098 DQM Delay:
8256 16:33:17.830958 DQM0 = 134, DQM1 = 127
8257 16:33:17.831092 DQ Delay:
8258 16:33:17.834782 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8259 16:33:17.837745 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8260 16:33:17.840910 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8261 16:33:17.844679 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =134
8262 16:33:17.844834
8263 16:33:17.844936
8264 16:33:17.845022
8265 16:33:17.847702 [DramC_TX_OE_Calibration] TA2
8266 16:33:17.851396 Original DQ_B0 (3 6) =30, OEN = 27
8267 16:33:17.854287 Original DQ_B1 (3 6) =30, OEN = 27
8268 16:33:17.857724 24, 0x0, End_B0=24 End_B1=24
8269 16:33:17.860743 25, 0x0, End_B0=25 End_B1=25
8270 16:33:17.860871 26, 0x0, End_B0=26 End_B1=26
8271 16:33:17.864491 27, 0x0, End_B0=27 End_B1=27
8272 16:33:17.867433 28, 0x0, End_B0=28 End_B1=28
8273 16:33:17.871044 29, 0x0, End_B0=29 End_B1=29
8274 16:33:17.874705 30, 0x0, End_B0=30 End_B1=30
8275 16:33:17.874826 31, 0x4141, End_B0=30 End_B1=30
8276 16:33:17.877481 Byte0 end_step=30 best_step=27
8277 16:33:17.881092 Byte1 end_step=30 best_step=27
8278 16:33:17.884724 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 16:33:17.887905 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 16:33:17.888024
8281 16:33:17.888108
8282 16:33:17.894694 [DQSOSCAuto] RK1, (LSB)MR18= 0x2009, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8283 16:33:17.898023 CH0 RK1: MR19=303, MR18=2009
8284 16:33:17.904557 CH0_RK1: MR19=0x303, MR18=0x2009, DQSOSC=393, MR23=63, INC=23, DEC=15
8285 16:33:17.907534 [RxdqsGatingPostProcess] freq 1600
8286 16:33:17.911164 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 16:33:17.914877 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 16:33:17.917837 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 16:33:17.920928 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 16:33:17.924673 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 16:33:17.927623 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 16:33:17.931411 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 16:33:17.934337 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 16:33:17.938033 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 16:33:17.940810 Pre-setting of DQS Precalculation
8296 16:33:17.944488 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 16:33:17.944566 ==
8298 16:33:17.947723 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 16:33:17.954542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 16:33:17.954634 ==
8301 16:33:17.957381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 16:33:17.964692 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 16:33:17.967697 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 16:33:17.974129 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 16:33:17.981545 [CA 0] Center 42 (13~72) winsize 60
8306 16:33:17.984680 [CA 1] Center 42 (13~72) winsize 60
8307 16:33:17.988320 [CA 2] Center 39 (10~68) winsize 59
8308 16:33:17.991842 [CA 3] Center 38 (9~68) winsize 60
8309 16:33:17.994696 [CA 4] Center 39 (10~68) winsize 59
8310 16:33:17.998216 [CA 5] Center 37 (8~67) winsize 60
8311 16:33:17.998319
8312 16:33:18.001645 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8313 16:33:18.001751
8314 16:33:18.008042 [CATrainingPosCal] consider 1 rank data
8315 16:33:18.008147 u2DelayCellTimex100 = 285/100 ps
8316 16:33:18.014900 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8317 16:33:18.017907 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8318 16:33:18.021371 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8319 16:33:18.024384 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8320 16:33:18.028055 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8321 16:33:18.031591 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8322 16:33:18.031725
8323 16:33:18.034699 CA PerBit enable=1, Macro0, CA PI delay=37
8324 16:33:18.034819
8325 16:33:18.037697 [CBTSetCACLKResult] CA Dly = 37
8326 16:33:18.041314 CS Dly: 10 (0~41)
8327 16:33:18.045002 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 16:33:18.048029 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 16:33:18.048167 ==
8330 16:33:18.051824 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 16:33:18.057872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 16:33:18.058009 ==
8333 16:33:18.061669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 16:33:18.064649 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 16:33:18.071172 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 16:33:18.077899 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 16:33:18.085042 [CA 0] Center 42 (13~72) winsize 60
8338 16:33:18.088759 [CA 1] Center 42 (13~72) winsize 60
8339 16:33:18.091738 [CA 2] Center 39 (10~69) winsize 60
8340 16:33:18.094788 [CA 3] Center 39 (10~68) winsize 59
8341 16:33:18.098518 [CA 4] Center 39 (9~69) winsize 61
8342 16:33:18.101740 [CA 5] Center 38 (9~68) winsize 60
8343 16:33:18.101834
8344 16:33:18.105440 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8345 16:33:18.105544
8346 16:33:18.111409 [CATrainingPosCal] consider 2 rank data
8347 16:33:18.111491 u2DelayCellTimex100 = 285/100 ps
8348 16:33:18.118374 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8349 16:33:18.121822 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8350 16:33:18.124798 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8351 16:33:18.128232 CA3 delay=39 (10~68),Diff = 1 PI (3 cell)
8352 16:33:18.131587 CA4 delay=39 (10~68),Diff = 1 PI (3 cell)
8353 16:33:18.135179 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8354 16:33:18.135260
8355 16:33:18.138784 CA PerBit enable=1, Macro0, CA PI delay=38
8356 16:33:18.138889
8357 16:33:18.141942 [CBTSetCACLKResult] CA Dly = 38
8358 16:33:18.144947 CS Dly: 11 (0~44)
8359 16:33:18.148622 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 16:33:18.151503 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 16:33:18.151586
8362 16:33:18.155250 ----->DramcWriteLeveling(PI) begin...
8363 16:33:18.155332 ==
8364 16:33:18.158208 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 16:33:18.165058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 16:33:18.165163 ==
8367 16:33:18.168808 Write leveling (Byte 0): 25 => 25
8368 16:33:18.168879 Write leveling (Byte 1): 26 => 26
8369 16:33:18.171978 DramcWriteLeveling(PI) end<-----
8370 16:33:18.172072
8371 16:33:18.172171 ==
8372 16:33:18.174781 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 16:33:18.182003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 16:33:18.182092 ==
8375 16:33:18.184872 [Gating] SW mode calibration
8376 16:33:18.192061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 16:33:18.195015 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 16:33:18.201742 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 16:33:18.205396 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 16:33:18.208421 1 4 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8381 16:33:18.214818 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 16:33:18.218315 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 16:33:18.221917 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 16:33:18.228233 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 16:33:18.231818 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 16:33:18.234714 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 16:33:18.241792 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 16:33:18.244646 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8389 16:33:18.248066 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
8390 16:33:18.251456 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 16:33:18.258100 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 16:33:18.261681 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 16:33:18.264579 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 16:33:18.271249 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 16:33:18.275015 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 16:33:18.278076 1 6 8 | B1->B0 | 2424 3c3b | 0 1 | (0 0) (0 0)
8397 16:33:18.284520 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8398 16:33:18.288133 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 16:33:18.291032 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 16:33:18.298012 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 16:33:18.301086 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 16:33:18.304853 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 16:33:18.311612 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 16:33:18.314504 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 16:33:18.318163 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 16:33:18.324547 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8407 16:33:18.327597 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 16:33:18.331137 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 16:33:18.337793 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 16:33:18.340787 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 16:33:18.344474 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 16:33:18.351127 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 16:33:18.354577 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 16:33:18.357294 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 16:33:18.364437 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 16:33:18.367240 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 16:33:18.370678 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 16:33:18.377427 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 16:33:18.380495 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 16:33:18.384286 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 16:33:18.391009 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 16:33:18.393804 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 16:33:18.397284 Total UI for P1: 0, mck2ui 16
8424 16:33:18.400655 best dqsien dly found for B0: ( 1, 9, 10)
8425 16:33:18.404145 Total UI for P1: 0, mck2ui 16
8426 16:33:18.407018 best dqsien dly found for B1: ( 1, 9, 10)
8427 16:33:18.410517 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8428 16:33:18.414322 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8429 16:33:18.414395
8430 16:33:18.417486 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8431 16:33:18.420596 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 16:33:18.423735 [Gating] SW calibration Done
8433 16:33:18.423827 ==
8434 16:33:18.427158 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 16:33:18.430775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 16:33:18.430845 ==
8437 16:33:18.433767 RX Vref Scan: 0
8438 16:33:18.433837
8439 16:33:18.437408 RX Vref 0 -> 0, step: 1
8440 16:33:18.437503
8441 16:33:18.437625 RX Delay 0 -> 252, step: 8
8442 16:33:18.443866 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8443 16:33:18.446765 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8444 16:33:18.450574 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8445 16:33:18.453513 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8446 16:33:18.457204 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8447 16:33:18.463404 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8448 16:33:18.467033 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8449 16:33:18.470595 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8450 16:33:18.473316 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8451 16:33:18.476761 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8452 16:33:18.483738 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8453 16:33:18.486567 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8454 16:33:18.490180 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8455 16:33:18.493249 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8456 16:33:18.496971 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8457 16:33:18.503489 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8458 16:33:18.503589 ==
8459 16:33:18.506989 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 16:33:18.510521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 16:33:18.510612 ==
8462 16:33:18.510723 DQS Delay:
8463 16:33:18.513527 DQS0 = 0, DQS1 = 0
8464 16:33:18.513618 DQM Delay:
8465 16:33:18.517010 DQM0 = 136, DQM1 = 133
8466 16:33:18.517099 DQ Delay:
8467 16:33:18.520395 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8468 16:33:18.523365 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8469 16:33:18.527236 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8470 16:33:18.530166 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8471 16:33:18.530258
8472 16:33:18.533685
8473 16:33:18.533756 ==
8474 16:33:18.536576 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 16:33:18.540260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 16:33:18.540362 ==
8477 16:33:18.540447
8478 16:33:18.540578
8479 16:33:18.543259 TX Vref Scan disable
8480 16:33:18.543354 == TX Byte 0 ==
8481 16:33:18.546955 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8482 16:33:18.553360 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8483 16:33:18.553455 == TX Byte 1 ==
8484 16:33:18.557169 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8485 16:33:18.563193 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8486 16:33:18.563291 ==
8487 16:33:18.566890 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 16:33:18.569822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 16:33:18.569911 ==
8490 16:33:18.583745
8491 16:33:18.587362 TX Vref early break, caculate TX vref
8492 16:33:18.590433 TX Vref=16, minBit 0, minWin=22, winSum=377
8493 16:33:18.593929 TX Vref=18, minBit 1, minWin=23, winSum=389
8494 16:33:18.597281 TX Vref=20, minBit 0, minWin=23, winSum=401
8495 16:33:18.600121 TX Vref=22, minBit 0, minWin=24, winSum=408
8496 16:33:18.603771 TX Vref=24, minBit 1, minWin=25, winSum=420
8497 16:33:18.610358 TX Vref=26, minBit 0, minWin=25, winSum=427
8498 16:33:18.614001 TX Vref=28, minBit 0, minWin=25, winSum=428
8499 16:33:18.617484 TX Vref=30, minBit 2, minWin=24, winSum=422
8500 16:33:18.620464 TX Vref=32, minBit 6, minWin=24, winSum=417
8501 16:33:18.624062 TX Vref=34, minBit 0, minWin=24, winSum=406
8502 16:33:18.626905 TX Vref=36, minBit 0, minWin=23, winSum=393
8503 16:33:18.633866 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8504 16:33:18.633946
8505 16:33:18.637370 Final TX Range 0 Vref 28
8506 16:33:18.637465
8507 16:33:18.637578 ==
8508 16:33:18.640185 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 16:33:18.643834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 16:33:18.643937 ==
8511 16:33:18.644030
8512 16:33:18.644146
8513 16:33:18.646994 TX Vref Scan disable
8514 16:33:18.653500 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8515 16:33:18.653640 == TX Byte 0 ==
8516 16:33:18.657127 u2DelayCellOfst[0]=13 cells (4 PI)
8517 16:33:18.660728 u2DelayCellOfst[1]=10 cells (3 PI)
8518 16:33:18.663753 u2DelayCellOfst[2]=0 cells (0 PI)
8519 16:33:18.666802 u2DelayCellOfst[3]=6 cells (2 PI)
8520 16:33:18.670733 u2DelayCellOfst[4]=6 cells (2 PI)
8521 16:33:18.673705 u2DelayCellOfst[5]=17 cells (5 PI)
8522 16:33:18.676772 u2DelayCellOfst[6]=17 cells (5 PI)
8523 16:33:18.680442 u2DelayCellOfst[7]=3 cells (1 PI)
8524 16:33:18.683473 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8525 16:33:18.687122 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8526 16:33:18.690003 == TX Byte 1 ==
8527 16:33:18.690100 u2DelayCellOfst[8]=0 cells (0 PI)
8528 16:33:18.693670 u2DelayCellOfst[9]=3 cells (1 PI)
8529 16:33:18.696606 u2DelayCellOfst[10]=13 cells (4 PI)
8530 16:33:18.700382 u2DelayCellOfst[11]=3 cells (1 PI)
8531 16:33:18.703280 u2DelayCellOfst[12]=17 cells (5 PI)
8532 16:33:18.706877 u2DelayCellOfst[13]=17 cells (5 PI)
8533 16:33:18.710361 u2DelayCellOfst[14]=17 cells (5 PI)
8534 16:33:18.713369 u2DelayCellOfst[15]=17 cells (5 PI)
8535 16:33:18.717055 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8536 16:33:18.723357 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8537 16:33:18.723441 DramC Write-DBI on
8538 16:33:18.723503 ==
8539 16:33:18.727197 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 16:33:18.729993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 16:33:18.733079 ==
8542 16:33:18.733157
8543 16:33:18.733217
8544 16:33:18.733272 TX Vref Scan disable
8545 16:33:18.737307 == TX Byte 0 ==
8546 16:33:18.740040 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8547 16:33:18.743613 == TX Byte 1 ==
8548 16:33:18.747087 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8549 16:33:18.750536 DramC Write-DBI off
8550 16:33:18.750615
8551 16:33:18.750676 [DATLAT]
8552 16:33:18.750733 Freq=1600, CH1 RK0
8553 16:33:18.750788
8554 16:33:18.753493 DATLAT Default: 0xf
8555 16:33:18.753581 0, 0xFFFF, sum = 0
8556 16:33:18.756989 1, 0xFFFF, sum = 0
8557 16:33:18.757071 2, 0xFFFF, sum = 0
8558 16:33:18.760461 3, 0xFFFF, sum = 0
8559 16:33:18.763416 4, 0xFFFF, sum = 0
8560 16:33:18.763496 5, 0xFFFF, sum = 0
8561 16:33:18.766903 6, 0xFFFF, sum = 0
8562 16:33:18.766983 7, 0xFFFF, sum = 0
8563 16:33:18.770731 8, 0xFFFF, sum = 0
8564 16:33:18.770811 9, 0xFFFF, sum = 0
8565 16:33:18.773727 10, 0xFFFF, sum = 0
8566 16:33:18.773806 11, 0xFFFF, sum = 0
8567 16:33:18.776767 12, 0xFFFF, sum = 0
8568 16:33:18.776847 13, 0xFFFF, sum = 0
8569 16:33:18.780365 14, 0x0, sum = 1
8570 16:33:18.780446 15, 0x0, sum = 2
8571 16:33:18.783234 16, 0x0, sum = 3
8572 16:33:18.783314 17, 0x0, sum = 4
8573 16:33:18.786984 best_step = 15
8574 16:33:18.787062
8575 16:33:18.787123 ==
8576 16:33:18.789885 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 16:33:18.793565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 16:33:18.793646 ==
8579 16:33:18.793708 RX Vref Scan: 1
8580 16:33:18.797024
8581 16:33:18.797092 Set Vref Range= 24 -> 127
8582 16:33:18.797147
8583 16:33:18.799907 RX Vref 24 -> 127, step: 1
8584 16:33:18.799997
8585 16:33:18.803685 RX Delay 27 -> 252, step: 4
8586 16:33:18.803778
8587 16:33:18.806703 Set Vref, RX VrefLevel [Byte0]: 24
8588 16:33:18.809619 [Byte1]: 24
8589 16:33:18.809714
8590 16:33:18.813365 Set Vref, RX VrefLevel [Byte0]: 25
8591 16:33:18.816209 [Byte1]: 25
8592 16:33:18.816282
8593 16:33:18.819776 Set Vref, RX VrefLevel [Byte0]: 26
8594 16:33:18.822723 [Byte1]: 26
8595 16:33:18.826860
8596 16:33:18.826957 Set Vref, RX VrefLevel [Byte0]: 27
8597 16:33:18.830470 [Byte1]: 27
8598 16:33:18.834810
8599 16:33:18.834876 Set Vref, RX VrefLevel [Byte0]: 28
8600 16:33:18.837741 [Byte1]: 28
8601 16:33:18.842202
8602 16:33:18.842296 Set Vref, RX VrefLevel [Byte0]: 29
8603 16:33:18.845685 [Byte1]: 29
8604 16:33:18.849333
8605 16:33:18.849424 Set Vref, RX VrefLevel [Byte0]: 30
8606 16:33:18.853027 [Byte1]: 30
8607 16:33:18.857341
8608 16:33:18.857437 Set Vref, RX VrefLevel [Byte0]: 31
8609 16:33:18.860223 [Byte1]: 31
8610 16:33:18.864481
8611 16:33:18.864576 Set Vref, RX VrefLevel [Byte0]: 32
8612 16:33:18.867924 [Byte1]: 32
8613 16:33:18.871966
8614 16:33:18.872065 Set Vref, RX VrefLevel [Byte0]: 33
8615 16:33:18.875714 [Byte1]: 33
8616 16:33:18.879507
8617 16:33:18.879599 Set Vref, RX VrefLevel [Byte0]: 34
8618 16:33:18.883163 [Byte1]: 34
8619 16:33:18.887634
8620 16:33:18.887702 Set Vref, RX VrefLevel [Byte0]: 35
8621 16:33:18.890676 [Byte1]: 35
8622 16:33:18.895194
8623 16:33:18.895286 Set Vref, RX VrefLevel [Byte0]: 36
8624 16:33:18.898241 [Byte1]: 36
8625 16:33:18.902659
8626 16:33:18.902730 Set Vref, RX VrefLevel [Byte0]: 37
8627 16:33:18.905572 [Byte1]: 37
8628 16:33:18.909985
8629 16:33:18.910077 Set Vref, RX VrefLevel [Byte0]: 38
8630 16:33:18.913053 [Byte1]: 38
8631 16:33:18.917409
8632 16:33:18.917501 Set Vref, RX VrefLevel [Byte0]: 39
8633 16:33:18.920933 [Byte1]: 39
8634 16:33:18.925322
8635 16:33:18.925412 Set Vref, RX VrefLevel [Byte0]: 40
8636 16:33:18.928190 [Byte1]: 40
8637 16:33:18.932371
8638 16:33:18.932465 Set Vref, RX VrefLevel [Byte0]: 41
8639 16:33:18.936009 [Byte1]: 41
8640 16:33:18.940240
8641 16:33:18.940336 Set Vref, RX VrefLevel [Byte0]: 42
8642 16:33:18.943768 [Byte1]: 42
8643 16:33:18.947490
8644 16:33:18.947582 Set Vref, RX VrefLevel [Byte0]: 43
8645 16:33:18.950643 [Byte1]: 43
8646 16:33:18.955206
8647 16:33:18.955300 Set Vref, RX VrefLevel [Byte0]: 44
8648 16:33:18.958122 [Byte1]: 44
8649 16:33:18.962488
8650 16:33:18.962576 Set Vref, RX VrefLevel [Byte0]: 45
8651 16:33:18.966074 [Byte1]: 45
8652 16:33:18.970333
8653 16:33:18.970398 Set Vref, RX VrefLevel [Byte0]: 46
8654 16:33:18.973245 [Byte1]: 46
8655 16:33:18.977535
8656 16:33:18.977744 Set Vref, RX VrefLevel [Byte0]: 47
8657 16:33:18.980992 [Byte1]: 47
8658 16:33:18.985527
8659 16:33:18.985707 Set Vref, RX VrefLevel [Byte0]: 48
8660 16:33:18.988258 [Byte1]: 48
8661 16:33:18.992815
8662 16:33:18.992925 Set Vref, RX VrefLevel [Byte0]: 49
8663 16:33:18.995711 [Byte1]: 49
8664 16:33:19.000277
8665 16:33:19.000401 Set Vref, RX VrefLevel [Byte0]: 50
8666 16:33:19.003297 [Byte1]: 50
8667 16:33:19.007599
8668 16:33:19.007714 Set Vref, RX VrefLevel [Byte0]: 51
8669 16:33:19.011194 [Byte1]: 51
8670 16:33:19.015495
8671 16:33:19.015592 Set Vref, RX VrefLevel [Byte0]: 52
8672 16:33:19.018487 [Byte1]: 52
8673 16:33:19.022791
8674 16:33:19.022860 Set Vref, RX VrefLevel [Byte0]: 53
8675 16:33:19.026587 [Byte1]: 53
8676 16:33:19.030345
8677 16:33:19.030459 Set Vref, RX VrefLevel [Byte0]: 54
8678 16:33:19.034065 [Byte1]: 54
8679 16:33:19.038272
8680 16:33:19.038365 Set Vref, RX VrefLevel [Byte0]: 55
8681 16:33:19.041048 [Byte1]: 55
8682 16:33:19.045423
8683 16:33:19.045527 Set Vref, RX VrefLevel [Byte0]: 56
8684 16:33:19.049012 [Byte1]: 56
8685 16:33:19.053302
8686 16:33:19.053397 Set Vref, RX VrefLevel [Byte0]: 57
8687 16:33:19.056226 [Byte1]: 57
8688 16:33:19.060277
8689 16:33:19.060406 Set Vref, RX VrefLevel [Byte0]: 58
8690 16:33:19.063871 [Byte1]: 58
8691 16:33:19.068283
8692 16:33:19.068357 Set Vref, RX VrefLevel [Byte0]: 59
8693 16:33:19.071091 [Byte1]: 59
8694 16:33:19.075570
8695 16:33:19.075664 Set Vref, RX VrefLevel [Byte0]: 60
8696 16:33:19.079220 [Byte1]: 60
8697 16:33:19.082859
8698 16:33:19.082957 Set Vref, RX VrefLevel [Byte0]: 61
8699 16:33:19.086815 [Byte1]: 61
8700 16:33:19.090434
8701 16:33:19.090509 Set Vref, RX VrefLevel [Byte0]: 62
8702 16:33:19.093786 [Byte1]: 62
8703 16:33:19.098550
8704 16:33:19.098625 Set Vref, RX VrefLevel [Byte0]: 63
8705 16:33:19.101406 [Byte1]: 63
8706 16:33:19.105916
8707 16:33:19.105990 Set Vref, RX VrefLevel [Byte0]: 64
8708 16:33:19.108905 [Byte1]: 64
8709 16:33:19.113303
8710 16:33:19.113391 Set Vref, RX VrefLevel [Byte0]: 65
8711 16:33:19.116363 [Byte1]: 65
8712 16:33:19.120760
8713 16:33:19.120856 Set Vref, RX VrefLevel [Byte0]: 66
8714 16:33:19.124482 [Byte1]: 66
8715 16:33:19.128177
8716 16:33:19.128272 Set Vref, RX VrefLevel [Byte0]: 67
8717 16:33:19.131284 [Byte1]: 67
8718 16:33:19.135841
8719 16:33:19.135917 Set Vref, RX VrefLevel [Byte0]: 68
8720 16:33:19.139432 [Byte1]: 68
8721 16:33:19.143663
8722 16:33:19.143761 Set Vref, RX VrefLevel [Byte0]: 69
8723 16:33:19.146559 [Byte1]: 69
8724 16:33:19.150999
8725 16:33:19.151073 Set Vref, RX VrefLevel [Byte0]: 70
8726 16:33:19.153973 [Byte1]: 70
8727 16:33:19.158325
8728 16:33:19.158399 Set Vref, RX VrefLevel [Byte0]: 71
8729 16:33:19.161978 [Byte1]: 71
8730 16:33:19.166280
8731 16:33:19.166376 Set Vref, RX VrefLevel [Byte0]: 72
8732 16:33:19.169087 [Byte1]: 72
8733 16:33:19.173162
8734 16:33:19.173256 Set Vref, RX VrefLevel [Byte0]: 73
8735 16:33:19.177017 [Byte1]: 73
8736 16:33:19.181093
8737 16:33:19.181167 Set Vref, RX VrefLevel [Byte0]: 74
8738 16:33:19.184278 [Byte1]: 74
8739 16:33:19.188899
8740 16:33:19.188977 Set Vref, RX VrefLevel [Byte0]: 75
8741 16:33:19.191670 [Byte1]: 75
8742 16:33:19.196012
8743 16:33:19.196117 Set Vref, RX VrefLevel [Byte0]: 76
8744 16:33:19.199627 [Byte1]: 76
8745 16:33:19.203704
8746 16:33:19.203827 Set Vref, RX VrefLevel [Byte0]: 77
8747 16:33:19.206989 [Byte1]: 77
8748 16:33:19.211021
8749 16:33:19.211126 Final RX Vref Byte 0 = 57 to rank0
8750 16:33:19.214751 Final RX Vref Byte 1 = 53 to rank0
8751 16:33:19.217691 Final RX Vref Byte 0 = 57 to rank1
8752 16:33:19.221389 Final RX Vref Byte 1 = 53 to rank1==
8753 16:33:19.224281 Dram Type= 6, Freq= 0, CH_1, rank 0
8754 16:33:19.231232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 16:33:19.231389 ==
8756 16:33:19.231481 DQS Delay:
8757 16:33:19.231565 DQS0 = 0, DQS1 = 0
8758 16:33:19.234817 DQM Delay:
8759 16:33:19.234956 DQM0 = 134, DQM1 = 131
8760 16:33:19.237967 DQ Delay:
8761 16:33:19.240791 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8762 16:33:19.244465 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =134
8763 16:33:19.247517 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8764 16:33:19.251075 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8765 16:33:19.251221
8766 16:33:19.251315
8767 16:33:19.251407
8768 16:33:19.254608 [DramC_TX_OE_Calibration] TA2
8769 16:33:19.257432 Original DQ_B0 (3 6) =30, OEN = 27
8770 16:33:19.261259 Original DQ_B1 (3 6) =30, OEN = 27
8771 16:33:19.264139 24, 0x0, End_B0=24 End_B1=24
8772 16:33:19.264252 25, 0x0, End_B0=25 End_B1=25
8773 16:33:19.267839 26, 0x0, End_B0=26 End_B1=26
8774 16:33:19.270770 27, 0x0, End_B0=27 End_B1=27
8775 16:33:19.273889 28, 0x0, End_B0=28 End_B1=28
8776 16:33:19.277516 29, 0x0, End_B0=29 End_B1=29
8777 16:33:19.277650 30, 0x0, End_B0=30 End_B1=30
8778 16:33:19.281304 31, 0x4141, End_B0=30 End_B1=30
8779 16:33:19.283990 Byte0 end_step=30 best_step=27
8780 16:33:19.287590 Byte1 end_step=30 best_step=27
8781 16:33:19.291135 Byte0 TX OE(2T, 0.5T) = (3, 3)
8782 16:33:19.294554 Byte1 TX OE(2T, 0.5T) = (3, 3)
8783 16:33:19.294694
8784 16:33:19.294813
8785 16:33:19.300596 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8786 16:33:19.304049 CH1 RK0: MR19=303, MR18=1826
8787 16:33:19.310669 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8788 16:33:19.310858
8789 16:33:19.314187 ----->DramcWriteLeveling(PI) begin...
8790 16:33:19.314286 ==
8791 16:33:19.317481 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 16:33:19.320840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 16:33:19.320925 ==
8794 16:33:19.323862 Write leveling (Byte 0): 25 => 25
8795 16:33:19.327498 Write leveling (Byte 1): 27 => 27
8796 16:33:19.330550 DramcWriteLeveling(PI) end<-----
8797 16:33:19.330670
8798 16:33:19.330759 ==
8799 16:33:19.334213 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 16:33:19.337207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 16:33:19.337309 ==
8802 16:33:19.340653 [Gating] SW mode calibration
8803 16:33:19.347317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8804 16:33:19.353887 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8805 16:33:19.357490 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 16:33:19.360394 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 16:33:19.367134 1 4 8 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
8808 16:33:19.370224 1 4 12 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (0 0)
8809 16:33:19.373729 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 16:33:19.380283 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 16:33:19.383973 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 16:33:19.386987 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 16:33:19.393565 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 16:33:19.397320 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8815 16:33:19.400579 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
8816 16:33:19.406999 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8817 16:33:19.410661 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 16:33:19.414089 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 16:33:19.420873 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 16:33:19.423613 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 16:33:19.426984 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 16:33:19.433808 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8823 16:33:19.437568 1 6 8 | B1->B0 | 3737 2323 | 0 0 | (0 0) (0 0)
8824 16:33:19.440466 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 16:33:19.446999 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 16:33:19.450679 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 16:33:19.453681 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 16:33:19.460518 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 16:33:19.463447 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 16:33:19.467022 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8831 16:33:19.470741 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8832 16:33:19.477338 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8833 16:33:19.480192 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 16:33:19.483919 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 16:33:19.490565 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 16:33:19.493518 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 16:33:19.497104 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 16:33:19.503718 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 16:33:19.506692 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 16:33:19.510491 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 16:33:19.517199 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 16:33:19.520096 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 16:33:19.523545 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 16:33:19.530022 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 16:33:19.533440 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 16:33:19.537011 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8847 16:33:19.543369 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8848 16:33:19.543449 Total UI for P1: 0, mck2ui 16
8849 16:33:19.550005 best dqsien dly found for B1: ( 1, 9, 4)
8850 16:33:19.553845 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8851 16:33:19.557059 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 16:33:19.559787 Total UI for P1: 0, mck2ui 16
8853 16:33:19.563611 best dqsien dly found for B0: ( 1, 9, 10)
8854 16:33:19.566623 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8855 16:33:19.570373 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8856 16:33:19.570503
8857 16:33:19.573214 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8858 16:33:19.580378 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8859 16:33:19.580512 [Gating] SW calibration Done
8860 16:33:19.583354 ==
8861 16:33:19.583451 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 16:33:19.589996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 16:33:19.590114 ==
8864 16:33:19.590179 RX Vref Scan: 0
8865 16:33:19.590236
8866 16:33:19.592948 RX Vref 0 -> 0, step: 1
8867 16:33:19.593054
8868 16:33:19.596493 RX Delay 0 -> 252, step: 8
8869 16:33:19.600215 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8870 16:33:19.603155 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8871 16:33:19.606817 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8872 16:33:19.613489 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8873 16:33:19.616408 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8874 16:33:19.620195 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8875 16:33:19.623143 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8876 16:33:19.626905 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8877 16:33:19.633495 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8878 16:33:19.636290 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8879 16:33:19.639816 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8880 16:33:19.643225 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8881 16:33:19.646620 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8882 16:33:19.653099 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8883 16:33:19.656704 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8884 16:33:19.659699 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8885 16:33:19.659778 ==
8886 16:33:19.663245 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 16:33:19.666078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 16:33:19.666156 ==
8889 16:33:19.669574 DQS Delay:
8890 16:33:19.669657 DQS0 = 0, DQS1 = 0
8891 16:33:19.673243 DQM Delay:
8892 16:33:19.673326 DQM0 = 136, DQM1 = 134
8893 16:33:19.676135 DQ Delay:
8894 16:33:19.679805 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8895 16:33:19.682633 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8896 16:33:19.686045 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8897 16:33:19.689715 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8898 16:33:19.689787
8899 16:33:19.689845
8900 16:33:19.689899 ==
8901 16:33:19.693306 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 16:33:19.696424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 16:33:19.696488 ==
8904 16:33:19.696541
8905 16:33:19.696594
8906 16:33:19.699328 TX Vref Scan disable
8907 16:33:19.702958 == TX Byte 0 ==
8908 16:33:19.705814 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8909 16:33:19.709503 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8910 16:33:19.712566 == TX Byte 1 ==
8911 16:33:19.716522 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8912 16:33:19.719569 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8913 16:33:19.719670 ==
8914 16:33:19.722564 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 16:33:19.729299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 16:33:19.729428 ==
8917 16:33:19.740341
8918 16:33:19.743989 TX Vref early break, caculate TX vref
8919 16:33:19.747588 TX Vref=16, minBit 0, minWin=23, winSum=380
8920 16:33:19.750478 TX Vref=18, minBit 0, minWin=23, winSum=395
8921 16:33:19.753975 TX Vref=20, minBit 0, minWin=24, winSum=402
8922 16:33:19.757443 TX Vref=22, minBit 0, minWin=24, winSum=410
8923 16:33:19.760234 TX Vref=24, minBit 0, minWin=25, winSum=422
8924 16:33:19.767499 TX Vref=26, minBit 0, minWin=26, winSum=430
8925 16:33:19.770390 TX Vref=28, minBit 0, minWin=25, winSum=428
8926 16:33:19.773670 TX Vref=30, minBit 1, minWin=25, winSum=420
8927 16:33:19.776885 TX Vref=32, minBit 6, minWin=24, winSum=416
8928 16:33:19.780283 TX Vref=34, minBit 6, minWin=23, winSum=404
8929 16:33:19.786856 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
8930 16:33:19.786927
8931 16:33:19.790363 Final TX Range 0 Vref 26
8932 16:33:19.790431
8933 16:33:19.790487 ==
8934 16:33:19.793911 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 16:33:19.797491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 16:33:19.797578 ==
8937 16:33:19.797641
8938 16:33:19.797696
8939 16:33:19.800376 TX Vref Scan disable
8940 16:33:19.807388 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8941 16:33:19.807470 == TX Byte 0 ==
8942 16:33:19.810223 u2DelayCellOfst[0]=17 cells (5 PI)
8943 16:33:19.814068 u2DelayCellOfst[1]=10 cells (3 PI)
8944 16:33:19.817019 u2DelayCellOfst[2]=0 cells (0 PI)
8945 16:33:19.819998 u2DelayCellOfst[3]=6 cells (2 PI)
8946 16:33:19.823785 u2DelayCellOfst[4]=6 cells (2 PI)
8947 16:33:19.826864 u2DelayCellOfst[5]=17 cells (5 PI)
8948 16:33:19.826931 u2DelayCellOfst[6]=17 cells (5 PI)
8949 16:33:19.830608 u2DelayCellOfst[7]=6 cells (2 PI)
8950 16:33:19.836561 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8951 16:33:19.840371 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8952 16:33:19.840441 == TX Byte 1 ==
8953 16:33:19.843313 u2DelayCellOfst[8]=0 cells (0 PI)
8954 16:33:19.847066 u2DelayCellOfst[9]=3 cells (1 PI)
8955 16:33:19.850011 u2DelayCellOfst[10]=10 cells (3 PI)
8956 16:33:19.853401 u2DelayCellOfst[11]=3 cells (1 PI)
8957 16:33:19.856366 u2DelayCellOfst[12]=13 cells (4 PI)
8958 16:33:19.860089 u2DelayCellOfst[13]=13 cells (4 PI)
8959 16:33:19.863848 u2DelayCellOfst[14]=17 cells (5 PI)
8960 16:33:19.866747 u2DelayCellOfst[15]=17 cells (5 PI)
8961 16:33:19.870242 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8962 16:33:19.876552 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8963 16:33:19.876630 DramC Write-DBI on
8964 16:33:19.876690 ==
8965 16:33:19.880038 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 16:33:19.883513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 16:33:19.883591 ==
8968 16:33:19.886294
8969 16:33:19.886369
8970 16:33:19.886476 TX Vref Scan disable
8971 16:33:19.889693 == TX Byte 0 ==
8972 16:33:19.893147 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8973 16:33:19.896362 == TX Byte 1 ==
8974 16:33:19.899902 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8975 16:33:19.900008 DramC Write-DBI off
8976 16:33:19.902830
8977 16:33:19.902927 [DATLAT]
8978 16:33:19.903026 Freq=1600, CH1 RK1
8979 16:33:19.903129
8980 16:33:19.906571 DATLAT Default: 0xf
8981 16:33:19.906715 0, 0xFFFF, sum = 0
8982 16:33:19.909987 1, 0xFFFF, sum = 0
8983 16:33:19.910085 2, 0xFFFF, sum = 0
8984 16:33:19.912746 3, 0xFFFF, sum = 0
8985 16:33:19.912839 4, 0xFFFF, sum = 0
8986 16:33:19.916826 5, 0xFFFF, sum = 0
8987 16:33:19.919603 6, 0xFFFF, sum = 0
8988 16:33:19.919707 7, 0xFFFF, sum = 0
8989 16:33:19.923298 8, 0xFFFF, sum = 0
8990 16:33:19.923404 9, 0xFFFF, sum = 0
8991 16:33:19.926251 10, 0xFFFF, sum = 0
8992 16:33:19.926351 11, 0xFFFF, sum = 0
8993 16:33:19.929955 12, 0xFFFF, sum = 0
8994 16:33:19.930065 13, 0xFFFF, sum = 0
8995 16:33:19.932931 14, 0x0, sum = 1
8996 16:33:19.933086 15, 0x0, sum = 2
8997 16:33:19.935898 16, 0x0, sum = 3
8998 16:33:19.936018 17, 0x0, sum = 4
8999 16:33:19.939675 best_step = 15
9000 16:33:19.939792
9001 16:33:19.939944 ==
9002 16:33:19.942687 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 16:33:19.946358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 16:33:19.946438 ==
9005 16:33:19.949296 RX Vref Scan: 0
9006 16:33:19.949410
9007 16:33:19.949502 RX Vref 0 -> 0, step: 1
9008 16:33:19.949641
9009 16:33:19.952920 RX Delay 19 -> 252, step: 4
9010 16:33:19.955790 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9011 16:33:19.962518 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9012 16:33:19.966189 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9013 16:33:19.969241 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9014 16:33:19.972258 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9015 16:33:19.976086 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9016 16:33:19.982777 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9017 16:33:19.985615 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9018 16:33:19.989331 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9019 16:33:19.992208 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9020 16:33:19.995781 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9021 16:33:20.002625 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9022 16:33:20.005467 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9023 16:33:20.008864 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9024 16:33:20.012172 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9025 16:33:20.015523 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9026 16:33:20.015595 ==
9027 16:33:20.019018 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 16:33:20.025565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 16:33:20.025646 ==
9030 16:33:20.025724 DQS Delay:
9031 16:33:20.028954 DQS0 = 0, DQS1 = 0
9032 16:33:20.029055 DQM Delay:
9033 16:33:20.032484 DQM0 = 134, DQM1 = 131
9034 16:33:20.032592 DQ Delay:
9035 16:33:20.035984 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9036 16:33:20.038782 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9037 16:33:20.042577 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9038 16:33:20.045473 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
9039 16:33:20.045580
9040 16:33:20.045675
9041 16:33:20.045757
9042 16:33:20.049226 [DramC_TX_OE_Calibration] TA2
9043 16:33:20.052232 Original DQ_B0 (3 6) =30, OEN = 27
9044 16:33:20.055803 Original DQ_B1 (3 6) =30, OEN = 27
9045 16:33:20.058792 24, 0x0, End_B0=24 End_B1=24
9046 16:33:20.062426 25, 0x0, End_B0=25 End_B1=25
9047 16:33:20.062526 26, 0x0, End_B0=26 End_B1=26
9048 16:33:20.065296 27, 0x0, End_B0=27 End_B1=27
9049 16:33:20.069155 28, 0x0, End_B0=28 End_B1=28
9050 16:33:20.072053 29, 0x0, End_B0=29 End_B1=29
9051 16:33:20.072157 30, 0x0, End_B0=30 End_B1=30
9052 16:33:20.075806 31, 0x4141, End_B0=30 End_B1=30
9053 16:33:20.078769 Byte0 end_step=30 best_step=27
9054 16:33:20.081723 Byte1 end_step=30 best_step=27
9055 16:33:20.085292 Byte0 TX OE(2T, 0.5T) = (3, 3)
9056 16:33:20.088389 Byte1 TX OE(2T, 0.5T) = (3, 3)
9057 16:33:20.088466
9058 16:33:20.088549
9059 16:33:20.095138 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9060 16:33:20.098753 CH1 RK1: MR19=303, MR18=250A
9061 16:33:20.105354 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9062 16:33:20.108892 [RxdqsGatingPostProcess] freq 1600
9063 16:33:20.111756 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9064 16:33:20.115295 best DQS0 dly(2T, 0.5T) = (1, 1)
9065 16:33:20.118849 best DQS1 dly(2T, 0.5T) = (1, 1)
9066 16:33:20.121724 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9067 16:33:20.124965 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9068 16:33:20.128653 best DQS0 dly(2T, 0.5T) = (1, 1)
9069 16:33:20.132189 best DQS1 dly(2T, 0.5T) = (1, 1)
9070 16:33:20.135232 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9071 16:33:20.138794 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9072 16:33:20.141689 Pre-setting of DQS Precalculation
9073 16:33:20.145079 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9074 16:33:20.151666 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9075 16:33:20.161540 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9076 16:33:20.161647
9077 16:33:20.161705
9078 16:33:20.165283 [Calibration Summary] 3200 Mbps
9079 16:33:20.165342 CH 0, Rank 0
9080 16:33:20.168793 SW Impedance : PASS
9081 16:33:20.168860 DUTY Scan : NO K
9082 16:33:20.171635 ZQ Calibration : PASS
9083 16:33:20.175250 Jitter Meter : NO K
9084 16:33:20.175315 CBT Training : PASS
9085 16:33:20.178247 Write leveling : PASS
9086 16:33:20.178318 RX DQS gating : PASS
9087 16:33:20.181909 RX DQ/DQS(RDDQC) : PASS
9088 16:33:20.184946 TX DQ/DQS : PASS
9089 16:33:20.185013 RX DATLAT : PASS
9090 16:33:20.188424 RX DQ/DQS(Engine): PASS
9091 16:33:20.191384 TX OE : PASS
9092 16:33:20.191445 All Pass.
9093 16:33:20.191498
9094 16:33:20.191548 CH 0, Rank 1
9095 16:33:20.195066 SW Impedance : PASS
9096 16:33:20.198109 DUTY Scan : NO K
9097 16:33:20.198166 ZQ Calibration : PASS
9098 16:33:20.201834 Jitter Meter : NO K
9099 16:33:20.204788 CBT Training : PASS
9100 16:33:20.204851 Write leveling : PASS
9101 16:33:20.208526 RX DQS gating : PASS
9102 16:33:20.211856 RX DQ/DQS(RDDQC) : PASS
9103 16:33:20.211927 TX DQ/DQS : PASS
9104 16:33:20.214966 RX DATLAT : PASS
9105 16:33:20.218690 RX DQ/DQS(Engine): PASS
9106 16:33:20.218761 TX OE : PASS
9107 16:33:20.218817 All Pass.
9108 16:33:20.221945
9109 16:33:20.222018 CH 1, Rank 0
9110 16:33:20.224770 SW Impedance : PASS
9111 16:33:20.224831 DUTY Scan : NO K
9112 16:33:20.228406 ZQ Calibration : PASS
9113 16:33:20.228477 Jitter Meter : NO K
9114 16:33:20.231291 CBT Training : PASS
9115 16:33:20.234922 Write leveling : PASS
9116 16:33:20.234991 RX DQS gating : PASS
9117 16:33:20.238286 RX DQ/DQS(RDDQC) : PASS
9118 16:33:20.241539 TX DQ/DQS : PASS
9119 16:33:20.241638 RX DATLAT : PASS
9120 16:33:20.244995 RX DQ/DQS(Engine): PASS
9121 16:33:20.248539 TX OE : PASS
9122 16:33:20.248603 All Pass.
9123 16:33:20.248658
9124 16:33:20.248710 CH 1, Rank 1
9125 16:33:20.251449 SW Impedance : PASS
9126 16:33:20.255018 DUTY Scan : NO K
9127 16:33:20.255087 ZQ Calibration : PASS
9128 16:33:20.257930 Jitter Meter : NO K
9129 16:33:20.261515 CBT Training : PASS
9130 16:33:20.261608 Write leveling : PASS
9131 16:33:20.264561 RX DQS gating : PASS
9132 16:33:20.268312 RX DQ/DQS(RDDQC) : PASS
9133 16:33:20.268376 TX DQ/DQS : PASS
9134 16:33:20.271344 RX DATLAT : PASS
9135 16:33:20.271404 RX DQ/DQS(Engine): PASS
9136 16:33:20.275063 TX OE : PASS
9137 16:33:20.275128 All Pass.
9138 16:33:20.275185
9139 16:33:20.277958 DramC Write-DBI on
9140 16:33:20.281506 PER_BANK_REFRESH: Hybrid Mode
9141 16:33:20.281610 TX_TRACKING: ON
9142 16:33:20.291184 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9143 16:33:20.297616 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9144 16:33:20.307973 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9145 16:33:20.311489 [FAST_K] Save calibration result to emmc
9146 16:33:20.314343 sync common calibartion params.
9147 16:33:20.314415 sync cbt_mode0:1, 1:1
9148 16:33:20.318028 dram_init: ddr_geometry: 2
9149 16:33:20.320888 dram_init: ddr_geometry: 2
9150 16:33:20.320952 dram_init: ddr_geometry: 2
9151 16:33:20.324214 0:dram_rank_size:100000000
9152 16:33:20.327693 1:dram_rank_size:100000000
9153 16:33:20.331326 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9154 16:33:20.334400 DFS_SHUFFLE_HW_MODE: ON
9155 16:33:20.338094 dramc_set_vcore_voltage set vcore to 725000
9156 16:33:20.341075 Read voltage for 1600, 0
9157 16:33:20.341145 Vio18 = 0
9158 16:33:20.344748 Vcore = 725000
9159 16:33:20.344817 Vdram = 0
9160 16:33:20.344877 Vddq = 0
9161 16:33:20.344930 Vmddr = 0
9162 16:33:20.347682 switch to 3200 Mbps bootup
9163 16:33:20.351247 [DramcRunTimeConfig]
9164 16:33:20.351306 PHYPLL
9165 16:33:20.354519 DPM_CONTROL_AFTERK: ON
9166 16:33:20.354580 PER_BANK_REFRESH: ON
9167 16:33:20.357757 REFRESH_OVERHEAD_REDUCTION: ON
9168 16:33:20.360738 CMD_PICG_NEW_MODE: OFF
9169 16:33:20.360802 XRTWTW_NEW_MODE: ON
9170 16:33:20.364320 XRTRTR_NEW_MODE: ON
9171 16:33:20.364387 TX_TRACKING: ON
9172 16:33:20.367208 RDSEL_TRACKING: OFF
9173 16:33:20.370667 DQS Precalculation for DVFS: ON
9174 16:33:20.370735 RX_TRACKING: OFF
9175 16:33:20.374338 HW_GATING DBG: ON
9176 16:33:20.374408 ZQCS_ENABLE_LP4: ON
9177 16:33:20.377351 RX_PICG_NEW_MODE: ON
9178 16:33:20.377435 TX_PICG_NEW_MODE: ON
9179 16:33:20.380987 ENABLE_RX_DCM_DPHY: ON
9180 16:33:20.383851 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9181 16:33:20.387567 DUMMY_READ_FOR_TRACKING: OFF
9182 16:33:20.387635 !!! SPM_CONTROL_AFTERK: OFF
9183 16:33:20.390628 !!! SPM could not control APHY
9184 16:33:20.394344 IMPEDANCE_TRACKING: ON
9185 16:33:20.394446 TEMP_SENSOR: ON
9186 16:33:20.397190 HW_SAVE_FOR_SR: OFF
9187 16:33:20.400779 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9188 16:33:20.403711 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9189 16:33:20.403819 Read ODT Tracking: ON
9190 16:33:20.407441 Refresh Rate DeBounce: ON
9191 16:33:20.410525 DFS_NO_QUEUE_FLUSH: ON
9192 16:33:20.414282 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9193 16:33:20.414358 ENABLE_DFS_RUNTIME_MRW: OFF
9194 16:33:20.417105 DDR_RESERVE_NEW_MODE: ON
9195 16:33:20.420599 MR_CBT_SWITCH_FREQ: ON
9196 16:33:20.420705 =========================
9197 16:33:20.440659 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9198 16:33:20.444311 dram_init: ddr_geometry: 2
9199 16:33:20.462083 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9200 16:33:20.465716 dram_init: dram init end (result: 0)
9201 16:33:20.471947 DRAM-K: Full calibration passed in 24444 msecs
9202 16:33:20.475384 MRC: failed to locate region type 0.
9203 16:33:20.475453 DRAM rank0 size:0x100000000,
9204 16:33:20.479176 DRAM rank1 size=0x100000000
9205 16:33:20.488837 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9206 16:33:20.495603 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9207 16:33:20.501961 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9208 16:33:20.509202 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9209 16:33:20.512261 DRAM rank0 size:0x100000000,
9210 16:33:20.515163 DRAM rank1 size=0x100000000
9211 16:33:20.515242 CBMEM:
9212 16:33:20.518759 IMD: root @ 0xfffff000 254 entries.
9213 16:33:20.521819 IMD: root @ 0xffffec00 62 entries.
9214 16:33:20.525450 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9215 16:33:20.528895 WARNING: RO_VPD is uninitialized or empty.
9216 16:33:20.534948 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9217 16:33:20.542302 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9218 16:33:20.554832 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9219 16:33:20.566775 BS: romstage times (exec / console): total (unknown) / 23978 ms
9220 16:33:20.566857
9221 16:33:20.566971
9222 16:33:20.576223 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9223 16:33:20.579905 ARM64: Exception handlers installed.
9224 16:33:20.582988 ARM64: Testing exception
9225 16:33:20.586614 ARM64: Done test exception
9226 16:33:20.586713 Enumerating buses...
9227 16:33:20.589382 Show all devs... Before device enumeration.
9228 16:33:20.592804 Root Device: enabled 1
9229 16:33:20.596269 CPU_CLUSTER: 0: enabled 1
9230 16:33:20.596339 CPU: 00: enabled 1
9231 16:33:20.599670 Compare with tree...
9232 16:33:20.599737 Root Device: enabled 1
9233 16:33:20.602918 CPU_CLUSTER: 0: enabled 1
9234 16:33:20.606277 CPU: 00: enabled 1
9235 16:33:20.606353 Root Device scanning...
9236 16:33:20.609441 scan_static_bus for Root Device
9237 16:33:20.613344 CPU_CLUSTER: 0 enabled
9238 16:33:20.616554 scan_static_bus for Root Device done
9239 16:33:20.619434 scan_bus: bus Root Device finished in 8 msecs
9240 16:33:20.619536 done
9241 16:33:20.626035 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9242 16:33:20.629751 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9243 16:33:20.636084 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9244 16:33:20.639501 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9245 16:33:20.642518 Allocating resources...
9246 16:33:20.646269 Reading resources...
9247 16:33:20.649211 Root Device read_resources bus 0 link: 0
9248 16:33:20.649309 DRAM rank0 size:0x100000000,
9249 16:33:20.652908 DRAM rank1 size=0x100000000
9250 16:33:20.655739 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9251 16:33:20.659068 CPU: 00 missing read_resources
9252 16:33:20.662653 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9253 16:33:20.669218 Root Device read_resources bus 0 link: 0 done
9254 16:33:20.669313 Done reading resources.
9255 16:33:20.675925 Show resources in subtree (Root Device)...After reading.
9256 16:33:20.679586 Root Device child on link 0 CPU_CLUSTER: 0
9257 16:33:20.682565 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 16:33:20.692361 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 16:33:20.692441 CPU: 00
9260 16:33:20.695984 Root Device assign_resources, bus 0 link: 0
9261 16:33:20.699444 CPU_CLUSTER: 0 missing set_resources
9262 16:33:20.703002 Root Device assign_resources, bus 0 link: 0 done
9263 16:33:20.706073 Done setting resources.
9264 16:33:20.712675 Show resources in subtree (Root Device)...After assigning values.
9265 16:33:20.715568 Root Device child on link 0 CPU_CLUSTER: 0
9266 16:33:20.719183 CPU_CLUSTER: 0 child on link 0 CPU: 00
9267 16:33:20.729421 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9268 16:33:20.729523 CPU: 00
9269 16:33:20.732786 Done allocating resources.
9270 16:33:20.736022 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9271 16:33:20.739412 Enabling resources...
9272 16:33:20.739486 done.
9273 16:33:20.745761 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9274 16:33:20.745841 Initializing devices...
9275 16:33:20.749323 Root Device init
9276 16:33:20.749390 init hardware done!
9277 16:33:20.752272 0x00000018: ctrlr->caps
9278 16:33:20.756002 52.000 MHz: ctrlr->f_max
9279 16:33:20.756069 0.400 MHz: ctrlr->f_min
9280 16:33:20.758982 0x40ff8080: ctrlr->voltages
9281 16:33:20.759045 sclk: 390625
9282 16:33:20.762713 Bus Width = 1
9283 16:33:20.762774 sclk: 390625
9284 16:33:20.765463 Bus Width = 1
9285 16:33:20.765521 Early init status = 3
9286 16:33:20.772019 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9287 16:33:20.775536 in-header: 03 fc 00 00 01 00 00 00
9288 16:33:20.778990 in-data: 00
9289 16:33:20.781953 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9290 16:33:20.787185 in-header: 03 fd 00 00 00 00 00 00
9291 16:33:20.790876 in-data:
9292 16:33:20.793791 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9293 16:33:20.798283 in-header: 03 fc 00 00 01 00 00 00
9294 16:33:20.801309 in-data: 00
9295 16:33:20.805097 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9296 16:33:20.810654 in-header: 03 fd 00 00 00 00 00 00
9297 16:33:20.813704 in-data:
9298 16:33:20.817288 [SSUSB] Setting up USB HOST controller...
9299 16:33:20.820329 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9300 16:33:20.823950 [SSUSB] phy power-on done.
9301 16:33:20.826969 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9302 16:33:20.833830 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9303 16:33:20.836886 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9304 16:33:20.843351 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9305 16:33:20.850118 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9306 16:33:20.856803 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9307 16:33:20.863702 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9308 16:33:20.869873 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9309 16:33:20.873438 SPM: binary array size = 0x9dc
9310 16:33:20.877112 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9311 16:33:20.883388 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9312 16:33:20.889950 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9313 16:33:20.893612 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9314 16:33:20.899575 configure_display: Starting display init
9315 16:33:20.934106 anx7625_power_on_init: Init interface.
9316 16:33:20.937039 anx7625_disable_pd_protocol: Disabled PD feature.
9317 16:33:20.940624 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9318 16:33:20.968101 anx7625_start_dp_work: Secure OCM version=00
9319 16:33:20.971566 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9320 16:33:20.986513 sp_tx_get_edid_block: EDID Block = 1
9321 16:33:21.088631 Extracted contents:
9322 16:33:21.092458 header: 00 ff ff ff ff ff ff 00
9323 16:33:21.095290 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9324 16:33:21.098866 version: 01 04
9325 16:33:21.101705 basic params: 95 1f 11 78 0a
9326 16:33:21.105164 chroma info: 76 90 94 55 54 90 27 21 50 54
9327 16:33:21.108691 established: 00 00 00
9328 16:33:21.115147 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9329 16:33:21.118772 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9330 16:33:21.125437 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9331 16:33:21.131454 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9332 16:33:21.138324 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9333 16:33:21.141810 extensions: 00
9334 16:33:21.141879 checksum: fb
9335 16:33:21.141940
9336 16:33:21.145256 Manufacturer: IVO Model 57d Serial Number 0
9337 16:33:21.148279 Made week 0 of 2020
9338 16:33:21.148351 EDID version: 1.4
9339 16:33:21.152001 Digital display
9340 16:33:21.154997 6 bits per primary color channel
9341 16:33:21.155087 DisplayPort interface
9342 16:33:21.158751 Maximum image size: 31 cm x 17 cm
9343 16:33:21.161689 Gamma: 220%
9344 16:33:21.161762 Check DPMS levels
9345 16:33:21.165336 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9346 16:33:21.168501 First detailed timing is preferred timing
9347 16:33:21.171455 Established timings supported:
9348 16:33:21.175062 Standard timings supported:
9349 16:33:21.175136 Detailed timings
9350 16:33:21.181824 Hex of detail: 383680a07038204018303c0035ae10000019
9351 16:33:21.184806 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9352 16:33:21.191591 0780 0798 07c8 0820 hborder 0
9353 16:33:21.195276 0438 043b 0447 0458 vborder 0
9354 16:33:21.198094 -hsync -vsync
9355 16:33:21.198185 Did detailed timing
9356 16:33:21.204783 Hex of detail: 000000000000000000000000000000000000
9357 16:33:21.204915 Manufacturer-specified data, tag 0
9358 16:33:21.211289 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9359 16:33:21.214929 ASCII string: InfoVision
9360 16:33:21.217789 Hex of detail: 000000fe00523134304e574635205248200a
9361 16:33:21.221664 ASCII string: R140NWF5 RH
9362 16:33:21.221731 Checksum
9363 16:33:21.224417 Checksum: 0xfb (valid)
9364 16:33:21.228039 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9365 16:33:21.231013 DSI data_rate: 832800000 bps
9366 16:33:21.237773 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9367 16:33:21.241458 anx7625_parse_edid: pixelclock(138800).
9368 16:33:21.244490 hactive(1920), hsync(48), hfp(24), hbp(88)
9369 16:33:21.247519 vactive(1080), vsync(12), vfp(3), vbp(17)
9370 16:33:21.250860 anx7625_dsi_config: config dsi.
9371 16:33:21.257735 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9372 16:33:21.270919 anx7625_dsi_config: success to config DSI
9373 16:33:21.273740 anx7625_dp_start: MIPI phy setup OK.
9374 16:33:21.277364 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9375 16:33:21.281050 mtk_ddp_mode_set invalid vrefresh 60
9376 16:33:21.284268 main_disp_path_setup
9377 16:33:21.284347 ovl_layer_smi_id_en
9378 16:33:21.287291 ovl_layer_smi_id_en
9379 16:33:21.287369 ccorr_config
9380 16:33:21.287447 aal_config
9381 16:33:21.290995 gamma_config
9382 16:33:21.291072 postmask_config
9383 16:33:21.293988 dither_config
9384 16:33:21.297705 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9385 16:33:21.304280 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9386 16:33:21.307060 Root Device init finished in 555 msecs
9387 16:33:21.307139 CPU_CLUSTER: 0 init
9388 16:33:21.317542 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9389 16:33:21.320532 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9390 16:33:21.324176 APU_MBOX 0x190000b0 = 0x10001
9391 16:33:21.326996 APU_MBOX 0x190001b0 = 0x10001
9392 16:33:21.330631 APU_MBOX 0x190005b0 = 0x10001
9393 16:33:21.333566 APU_MBOX 0x190006b0 = 0x10001
9394 16:33:21.337034 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9395 16:33:21.349809 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9396 16:33:21.362308 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9397 16:33:21.369095 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9398 16:33:21.380563 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9399 16:33:21.389894 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9400 16:33:21.392922 CPU_CLUSTER: 0 init finished in 81 msecs
9401 16:33:21.395913 Devices initialized
9402 16:33:21.399658 Show all devs... After init.
9403 16:33:21.399735 Root Device: enabled 1
9404 16:33:21.402623 CPU_CLUSTER: 0: enabled 1
9405 16:33:21.406387 CPU: 00: enabled 1
9406 16:33:21.409334 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9407 16:33:21.413001 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9408 16:33:21.415828 ELOG: NV offset 0x57f000 size 0x1000
9409 16:33:21.422623 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9410 16:33:21.429410 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9411 16:33:21.432313 ELOG: Event(17) added with size 13 at 2024-06-17 16:33:21 UTC
9412 16:33:21.438922 out: cmd=0x121: 03 db 21 01 00 00 00 00
9413 16:33:21.442229 in-header: 03 05 00 00 2c 00 00 00
9414 16:33:21.452742 in-data: 38 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9415 16:33:21.459426 ELOG: Event(A1) added with size 10 at 2024-06-17 16:33:21 UTC
9416 16:33:21.465927 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9417 16:33:21.472447 ELOG: Event(A0) added with size 9 at 2024-06-17 16:33:21 UTC
9418 16:33:21.475803 elog_add_boot_reason: Logged dev mode boot
9419 16:33:21.478760 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9420 16:33:21.482395 Finalize devices...
9421 16:33:21.485839 Devices finalized
9422 16:33:21.488949 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9423 16:33:21.492041 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9424 16:33:21.495594 in-header: 03 07 00 00 08 00 00 00
9425 16:33:21.499196 in-data: aa e4 47 04 13 02 00 00
9426 16:33:21.502287 Chrome EC: UHEPI supported
9427 16:33:21.508825 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9428 16:33:21.512540 in-header: 03 a9 00 00 08 00 00 00
9429 16:33:21.515606 in-data: 84 60 60 08 00 00 00 00
9430 16:33:21.522047 ELOG: Event(91) added with size 10 at 2024-06-17 16:33:21 UTC
9431 16:33:21.525492 Chrome EC: clear events_b mask to 0x0000000020004000
9432 16:33:21.532786 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9433 16:33:21.535787 in-header: 03 fd 00 00 00 00 00 00
9434 16:33:21.538750 in-data:
9435 16:33:21.542450 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9436 16:33:21.545412 Writing coreboot table at 0xffe64000
9437 16:33:21.549058 0. 000000000010a000-0000000000113fff: RAMSTAGE
9438 16:33:21.555699 1. 0000000040000000-00000000400fffff: RAM
9439 16:33:21.559289 2. 0000000040100000-000000004032afff: RAMSTAGE
9440 16:33:21.562184 3. 000000004032b000-00000000545fffff: RAM
9441 16:33:21.565769 4. 0000000054600000-000000005465ffff: BL31
9442 16:33:21.568815 5. 0000000054660000-00000000ffe63fff: RAM
9443 16:33:21.575655 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9444 16:33:21.579356 7. 0000000100000000-000000023fffffff: RAM
9445 16:33:21.582157 Passing 5 GPIOs to payload:
9446 16:33:21.586025 NAME | PORT | POLARITY | VALUE
9447 16:33:21.592693 EC in RW | 0x000000aa | low | undefined
9448 16:33:21.595639 EC interrupt | 0x00000005 | low | undefined
9449 16:33:21.599266 TPM interrupt | 0x000000ab | high | undefined
9450 16:33:21.605510 SD card detect | 0x00000011 | high | undefined
9451 16:33:21.609217 speaker enable | 0x00000093 | high | undefined
9452 16:33:21.612097 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9453 16:33:21.615159 in-header: 03 f9 00 00 02 00 00 00
9454 16:33:21.618945 in-data: 02 00
9455 16:33:21.621899 ADC[4]: Raw value=904726 ID=7
9456 16:33:21.621966 ADC[3]: Raw value=213441 ID=1
9457 16:33:21.625542 RAM Code: 0x71
9458 16:33:21.628535 ADC[6]: Raw value=75332 ID=0
9459 16:33:21.628602 ADC[5]: Raw value=212703 ID=1
9460 16:33:21.632151 SKU Code: 0x1
9461 16:33:21.635793 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4323
9462 16:33:21.638727 coreboot table: 964 bytes.
9463 16:33:21.642177 IMD ROOT 0. 0xfffff000 0x00001000
9464 16:33:21.645796 IMD SMALL 1. 0xffffe000 0x00001000
9465 16:33:21.648911 RO MCACHE 2. 0xffffc000 0x00001104
9466 16:33:21.652525 CONSOLE 3. 0xfff7c000 0x00080000
9467 16:33:21.655554 FMAP 4. 0xfff7b000 0x00000452
9468 16:33:21.658492 TIME STAMP 5. 0xfff7a000 0x00000910
9469 16:33:21.662091 VBOOT WORK 6. 0xfff66000 0x00014000
9470 16:33:21.665758 RAMOOPS 7. 0xffe66000 0x00100000
9471 16:33:21.668554 COREBOOT 8. 0xffe64000 0x00002000
9472 16:33:21.672163 IMD small region:
9473 16:33:21.675068 IMD ROOT 0. 0xffffec00 0x00000400
9474 16:33:21.678816 VPD 1. 0xffffeb80 0x0000006c
9475 16:33:21.681764 MMC STATUS 2. 0xffffeb60 0x00000004
9476 16:33:21.685308 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9477 16:33:21.692092 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9478 16:33:21.732457 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9479 16:33:21.735461 Checking segment from ROM address 0x40100000
9480 16:33:21.739280 Checking segment from ROM address 0x4010001c
9481 16:33:21.745672 Loading segment from ROM address 0x40100000
9482 16:33:21.745741 code (compression=0)
9483 16:33:21.752760 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9484 16:33:21.762429 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9485 16:33:21.762507 it's not compressed!
9486 16:33:21.769329 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9487 16:33:21.772255 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9488 16:33:21.792545 Loading segment from ROM address 0x4010001c
9489 16:33:21.792618 Entry Point 0x80000000
9490 16:33:21.796363 Loaded segments
9491 16:33:21.799391 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9492 16:33:21.806641 Jumping to boot code at 0x80000000(0xffe64000)
9493 16:33:21.813025 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9494 16:33:21.819591 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9495 16:33:21.827198 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9496 16:33:21.830543 Checking segment from ROM address 0x40100000
9497 16:33:21.834227 Checking segment from ROM address 0x4010001c
9498 16:33:21.840856 Loading segment from ROM address 0x40100000
9499 16:33:21.840928 code (compression=1)
9500 16:33:21.847631 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9501 16:33:21.857009 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9502 16:33:21.857082 using LZMA
9503 16:33:21.865707 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9504 16:33:21.872690 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9505 16:33:21.875638 Loading segment from ROM address 0x4010001c
9506 16:33:21.875719 Entry Point 0x54601000
9507 16:33:21.879362 Loaded segments
9508 16:33:21.882279 NOTICE: MT8192 bl31_setup
9509 16:33:21.889418 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9510 16:33:21.892850 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9511 16:33:21.896205 WARNING: region 0:
9512 16:33:21.899195 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 16:33:21.899262 WARNING: region 1:
9514 16:33:21.905808 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9515 16:33:21.909536 WARNING: region 2:
9516 16:33:21.912548 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9517 16:33:21.915492 WARNING: region 3:
9518 16:33:21.919048 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 16:33:21.922439 WARNING: region 4:
9520 16:33:21.929043 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 16:33:21.929119 WARNING: region 5:
9522 16:33:21.932850 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 16:33:21.935785 WARNING: region 6:
9524 16:33:21.939208 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 16:33:21.942748 WARNING: region 7:
9526 16:33:21.945771 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 16:33:21.952589 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9528 16:33:21.956314 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9529 16:33:21.959176 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9530 16:33:21.977790 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9531 16:33:21.977894 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9532 16:33:21.977988 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9533 16:33:21.979694 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9534 16:33:21.982911 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9535 16:33:21.989358 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9536 16:33:21.992964 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9537 16:33:21.995726 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9538 16:33:22.002584 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9539 16:33:22.005734 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9540 16:33:22.009543 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9541 16:33:22.016294 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9542 16:33:22.019192 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9543 16:33:22.022840 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9544 16:33:22.029230 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9545 16:33:22.032502 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9546 16:33:22.039622 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9547 16:33:22.042569 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9548 16:33:22.046097 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9549 16:33:22.052756 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9550 16:33:22.056416 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9551 16:33:22.062746 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9552 16:33:22.066078 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9553 16:33:22.069037 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9554 16:33:22.075799 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9555 16:33:22.079440 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9556 16:33:22.086002 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9557 16:33:22.088844 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9558 16:33:22.092485 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9559 16:33:22.099578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9560 16:33:22.102415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9561 16:33:22.106007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9562 16:33:22.108890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9563 16:33:22.115924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9564 16:33:22.119198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9565 16:33:22.122456 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9566 16:33:22.125787 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9567 16:33:22.132650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9568 16:33:22.135873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9569 16:33:22.139276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9570 16:33:22.142534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9571 16:33:22.149190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9572 16:33:22.152559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9573 16:33:22.155405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9574 16:33:22.158768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9575 16:33:22.165559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9576 16:33:22.169188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9577 16:33:22.175760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9578 16:33:22.178668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9579 16:33:22.182337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9580 16:33:22.188916 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9581 16:33:22.192660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9582 16:33:22.198875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9583 16:33:22.202281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9584 16:33:22.208828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9585 16:33:22.212503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9586 16:33:22.218949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9587 16:33:22.222517 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9588 16:33:22.225376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9589 16:33:22.231937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9590 16:33:22.235635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9591 16:33:22.241719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9592 16:33:22.245018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9593 16:33:22.251806 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9594 16:33:22.255217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9595 16:33:22.259172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9596 16:33:22.265522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9597 16:33:22.268813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9598 16:33:22.275158 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9599 16:33:22.278420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9600 16:33:22.285445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9601 16:33:22.289200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9602 16:33:22.292071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9603 16:33:22.298494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9604 16:33:22.302048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9605 16:33:22.309053 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9606 16:33:22.311908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9607 16:33:22.318674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9608 16:33:22.322305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9609 16:33:22.328675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9610 16:33:22.332268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9611 16:33:22.335192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9612 16:33:22.342246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9613 16:33:22.345778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9614 16:33:22.352224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9615 16:33:22.355280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9616 16:33:22.358957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9617 16:33:22.365385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9618 16:33:22.368953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9619 16:33:22.375269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9620 16:33:22.378809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9621 16:33:22.385791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9622 16:33:22.388443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9623 16:33:22.391774 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9624 16:33:22.398927 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9625 16:33:22.402302 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9626 16:33:22.406260 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9627 16:33:22.408510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9628 16:33:22.415609 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9629 16:33:22.418490 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9630 16:33:22.425602 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9631 16:33:22.428510 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9632 16:33:22.432052 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9633 16:33:22.438580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9634 16:33:22.442292 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9635 16:33:22.448556 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9636 16:33:22.452098 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9637 16:33:22.455616 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9638 16:33:22.462014 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9639 16:33:22.465407 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9640 16:33:22.471889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9641 16:33:22.475310 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9642 16:33:22.478270 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9643 16:33:22.485199 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9644 16:33:22.488813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9645 16:33:22.491713 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9646 16:33:22.498222 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9647 16:33:22.501774 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9648 16:33:22.505121 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9649 16:33:22.508389 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9650 16:33:22.514903 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9651 16:33:22.518228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9652 16:33:22.521999 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9653 16:33:22.528495 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9654 16:33:22.532010 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9655 16:33:22.535494 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9656 16:33:22.541909 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9657 16:33:22.545513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9658 16:33:22.551970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9659 16:33:22.554799 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9660 16:33:22.558367 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9661 16:33:22.564866 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9662 16:33:22.568383 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9663 16:33:22.575029 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9664 16:33:22.578388 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9665 16:33:22.581954 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9666 16:33:22.592195 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9667 16:33:22.592298 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9668 16:33:22.595388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9669 16:33:22.601838 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9670 16:33:22.604780 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9671 16:33:22.611917 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9672 16:33:22.615296 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9673 16:33:22.618390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9674 16:33:22.625228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9675 16:33:22.628693 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9676 16:33:22.635055 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9677 16:33:22.638273 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9678 16:33:22.641858 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9679 16:33:22.648233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9680 16:33:22.651852 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9681 16:33:22.655299 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9682 16:33:22.661796 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9683 16:33:22.664718 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9684 16:33:22.671913 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9685 16:33:22.674789 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9686 16:33:22.678524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9687 16:33:22.684789 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9688 16:33:22.688312 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9689 16:33:22.694893 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9690 16:33:22.698194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9691 16:33:22.701518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9692 16:33:22.708023 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9693 16:33:22.711706 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9694 16:33:22.718199 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9695 16:33:22.721835 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9696 16:33:22.724529 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9697 16:33:22.731580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9698 16:33:22.735009 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9699 16:33:22.737898 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9700 16:33:22.744845 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9701 16:33:22.748469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9702 16:33:22.754562 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9703 16:33:22.758300 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9704 16:33:22.761479 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9705 16:33:22.768221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9706 16:33:22.771689 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9707 16:33:22.777971 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9708 16:33:22.781685 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9709 16:33:22.784622 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9710 16:33:22.791141 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9711 16:33:22.794993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9712 16:33:22.801363 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9713 16:33:22.804915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9714 16:33:22.808269 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9715 16:33:22.814704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9716 16:33:22.817602 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9717 16:33:22.824778 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9718 16:33:22.827642 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9719 16:33:22.831184 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9720 16:33:22.838178 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9721 16:33:22.841071 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9722 16:33:22.847777 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9723 16:33:22.851298 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9724 16:33:22.854756 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9725 16:33:22.861248 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9726 16:33:22.864860 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9727 16:33:22.870844 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9728 16:33:22.874769 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9729 16:33:22.878103 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9730 16:33:22.884277 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9731 16:33:22.888159 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9732 16:33:22.894157 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9733 16:33:22.897957 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9734 16:33:22.904164 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9735 16:33:22.907803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9736 16:33:22.910648 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9737 16:33:22.917564 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9738 16:33:22.921137 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9739 16:33:22.927650 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9740 16:33:22.930582 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9741 16:33:22.937216 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9742 16:33:22.940833 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9743 16:33:22.943802 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9744 16:33:22.950742 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9745 16:33:22.954232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9746 16:33:22.960592 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9747 16:33:22.964269 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9748 16:33:22.967078 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9749 16:33:22.974160 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9750 16:33:22.977032 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9751 16:33:22.984241 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9752 16:33:22.986906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9753 16:33:22.993926 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9754 16:33:22.997403 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9755 16:33:23.000927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9756 16:33:23.007582 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9757 16:33:23.010628 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9758 16:33:23.013717 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9759 16:33:23.017497 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9760 16:33:23.020353 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9761 16:33:23.027284 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9762 16:33:23.030570 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9763 16:33:23.037356 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9764 16:33:23.040132 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9765 16:33:23.043737 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9766 16:33:23.050096 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9767 16:33:23.053774 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9768 16:33:23.057210 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9769 16:33:23.063483 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9770 16:33:23.066837 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9771 16:33:23.070390 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9772 16:33:23.076892 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9773 16:33:23.080490 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9774 16:33:23.086869 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9775 16:33:23.090558 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9776 16:33:23.093396 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9777 16:33:23.100350 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9778 16:33:23.103326 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9779 16:33:23.110586 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9780 16:33:23.113481 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9781 16:33:23.116994 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9782 16:33:23.123207 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9783 16:33:23.127256 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9784 16:33:23.129915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9785 16:33:23.136916 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9786 16:33:23.140250 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9787 16:33:23.143511 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9788 16:33:23.150006 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9789 16:33:23.153489 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9790 16:33:23.156770 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9791 16:33:23.163664 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9792 16:33:23.167177 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9793 16:33:23.173324 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9794 16:33:23.176738 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9795 16:33:23.180410 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9796 16:33:23.183249 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9797 16:33:23.190439 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9798 16:33:23.193331 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9799 16:33:23.197025 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9800 16:33:23.199831 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9801 16:33:23.203255 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9802 16:33:23.210279 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9803 16:33:23.213197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9804 16:33:23.216834 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9805 16:33:23.220398 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9806 16:33:23.226784 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9807 16:33:23.230346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9808 16:33:23.233690 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9809 16:33:23.240042 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9810 16:33:23.243559 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9811 16:33:23.250037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9812 16:33:23.253668 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9813 16:33:23.256960 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9814 16:33:23.263761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9815 16:33:23.266488 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9816 16:33:23.273223 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9817 16:33:23.277104 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9818 16:33:23.280285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9819 16:33:23.286771 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9820 16:33:23.290207 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9821 16:33:23.296472 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9822 16:33:23.300184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9823 16:33:23.303796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9824 16:33:23.310407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9825 16:33:23.313099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9826 16:33:23.319824 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9827 16:33:23.323500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9828 16:33:23.326382 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9829 16:33:23.333428 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9830 16:33:23.336196 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9831 16:33:23.343196 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9832 16:33:23.346676 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9833 16:33:23.350218 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9834 16:33:23.356755 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9835 16:33:23.359729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9836 16:33:23.366674 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9837 16:33:23.369512 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9838 16:33:23.376772 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9839 16:33:23.379541 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9840 16:33:23.383052 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9841 16:33:23.389557 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9842 16:33:23.392571 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9843 16:33:23.399204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9844 16:33:23.403191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9845 16:33:23.406297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9846 16:33:23.413124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9847 16:33:23.416434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9848 16:33:23.422688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9849 16:33:23.426326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9850 16:33:23.429320 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9851 16:33:23.436448 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9852 16:33:23.439282 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9853 16:33:23.446441 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9854 16:33:23.449828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9855 16:33:23.456044 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9856 16:33:23.459643 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9857 16:33:23.462546 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9858 16:33:23.469638 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9859 16:33:23.473079 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9860 16:33:23.476039 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9861 16:33:23.483191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9862 16:33:23.485933 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9863 16:33:23.492676 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9864 16:33:23.496443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9865 16:33:23.499368 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9866 16:33:23.506010 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9867 16:33:23.509494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9868 16:33:23.516019 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9869 16:33:23.519672 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9870 16:33:23.526256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9871 16:33:23.529412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9872 16:33:23.532796 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9873 16:33:23.539237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9874 16:33:23.542953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9875 16:33:23.546105 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9876 16:33:23.552763 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9877 16:33:23.556353 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9878 16:33:23.562711 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9879 16:33:23.566231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9880 16:33:23.569883 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9881 16:33:23.576228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9882 16:33:23.579881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9883 16:33:23.586225 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9884 16:33:23.589534 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9885 16:33:23.595983 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9886 16:33:23.599506 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9887 16:33:23.606050 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9888 16:33:23.609670 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9889 16:33:23.613361 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9890 16:33:23.619798 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9891 16:33:23.623381 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9892 16:33:23.629713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9893 16:33:23.633392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9894 16:33:23.639659 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9895 16:33:23.643271 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9896 16:33:23.646054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9897 16:33:23.652989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9898 16:33:23.656376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9899 16:33:23.662700 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9900 16:33:23.666392 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9901 16:33:23.672705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9902 16:33:23.676434 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9903 16:33:23.679549 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9904 16:33:23.686606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9905 16:33:23.689997 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9906 16:33:23.696423 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9907 16:33:23.699190 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9908 16:33:23.706254 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9909 16:33:23.710055 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9910 16:33:23.716282 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9911 16:33:23.719256 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9912 16:33:23.722737 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9913 16:33:23.729317 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9914 16:33:23.733169 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9915 16:33:23.739370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9916 16:33:23.742964 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9917 16:33:23.746417 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9918 16:33:23.752810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9919 16:33:23.756809 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9920 16:33:23.762895 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9921 16:33:23.765842 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9922 16:33:23.772326 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9923 16:33:23.775923 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9924 16:33:23.782786 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9925 16:33:23.786089 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9926 16:33:23.789334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9927 16:33:23.796310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9928 16:33:23.799313 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9929 16:33:23.802800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9930 16:33:23.809488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9931 16:33:23.812744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9932 16:33:23.819373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9933 16:33:23.822493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9934 16:33:23.828843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9935 16:33:23.832407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9936 16:33:23.838700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9937 16:33:23.841735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9938 16:33:23.848760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9939 16:33:23.851778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9940 16:33:23.858875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9941 16:33:23.861765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9942 16:33:23.868871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9943 16:33:23.871729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9944 16:33:23.878957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9945 16:33:23.881837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9946 16:33:23.888406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9947 16:33:23.891820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9948 16:33:23.899227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9949 16:33:23.902027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9950 16:33:23.909226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9951 16:33:23.912147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9952 16:33:23.919048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9953 16:33:23.922281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9954 16:33:23.928820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9955 16:33:23.932198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9956 16:33:23.938855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9957 16:33:23.941983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9958 16:33:23.948595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9959 16:33:23.951874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9960 16:33:23.958940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9961 16:33:23.962433 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9962 16:33:23.962898 INFO: [APUAPC] vio 0
9963 16:33:23.969792 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9964 16:33:23.972800 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9965 16:33:23.976163 INFO: [APUAPC] D0_APC_0: 0x400510
9966 16:33:23.979809 INFO: [APUAPC] D0_APC_1: 0x0
9967 16:33:23.982674 INFO: [APUAPC] D0_APC_2: 0x1540
9968 16:33:23.986102 INFO: [APUAPC] D0_APC_3: 0x0
9969 16:33:23.989851 INFO: [APUAPC] D1_APC_0: 0xffffffff
9970 16:33:23.992690 INFO: [APUAPC] D1_APC_1: 0xffffffff
9971 16:33:23.996088 INFO: [APUAPC] D1_APC_2: 0x3fffff
9972 16:33:23.999725 INFO: [APUAPC] D1_APC_3: 0x0
9973 16:33:24.002673 INFO: [APUAPC] D2_APC_0: 0xffffffff
9974 16:33:24.006333 INFO: [APUAPC] D2_APC_1: 0xffffffff
9975 16:33:24.009884 INFO: [APUAPC] D2_APC_2: 0x3fffff
9976 16:33:24.012656 INFO: [APUAPC] D2_APC_3: 0x0
9977 16:33:24.016275 INFO: [APUAPC] D3_APC_0: 0xffffffff
9978 16:33:24.019787 INFO: [APUAPC] D3_APC_1: 0xffffffff
9979 16:33:24.022634 INFO: [APUAPC] D3_APC_2: 0x3fffff
9980 16:33:24.023152 INFO: [APUAPC] D3_APC_3: 0x0
9981 16:33:24.026311 INFO: [APUAPC] D4_APC_0: 0xffffffff
9982 16:33:24.033121 INFO: [APUAPC] D4_APC_1: 0xffffffff
9983 16:33:24.033506 INFO: [APUAPC] D4_APC_2: 0x3fffff
9984 16:33:24.036062 INFO: [APUAPC] D4_APC_3: 0x0
9985 16:33:24.039688 INFO: [APUAPC] D5_APC_0: 0xffffffff
9986 16:33:24.042629 INFO: [APUAPC] D5_APC_1: 0xffffffff
9987 16:33:24.046227 INFO: [APUAPC] D5_APC_2: 0x3fffff
9988 16:33:24.049139 INFO: [APUAPC] D5_APC_3: 0x0
9989 16:33:24.052700 INFO: [APUAPC] D6_APC_0: 0xffffffff
9990 16:33:24.056157 INFO: [APUAPC] D6_APC_1: 0xffffffff
9991 16:33:24.059702 INFO: [APUAPC] D6_APC_2: 0x3fffff
9992 16:33:24.063188 INFO: [APUAPC] D6_APC_3: 0x0
9993 16:33:24.066442 INFO: [APUAPC] D7_APC_0: 0xffffffff
9994 16:33:24.069838 INFO: [APUAPC] D7_APC_1: 0xffffffff
9995 16:33:24.073234 INFO: [APUAPC] D7_APC_2: 0x3fffff
9996 16:33:24.076412 INFO: [APUAPC] D7_APC_3: 0x0
9997 16:33:24.079682 INFO: [APUAPC] D8_APC_0: 0xffffffff
9998 16:33:24.082763 INFO: [APUAPC] D8_APC_1: 0xffffffff
9999 16:33:24.086313 INFO: [APUAPC] D8_APC_2: 0x3fffff
10000 16:33:24.089375 INFO: [APUAPC] D8_APC_3: 0x0
10001 16:33:24.093030 INFO: [APUAPC] D9_APC_0: 0xffffffff
10002 16:33:24.096311 INFO: [APUAPC] D9_APC_1: 0xffffffff
10003 16:33:24.099185 INFO: [APUAPC] D9_APC_2: 0x3fffff
10004 16:33:24.102318 INFO: [APUAPC] D9_APC_3: 0x0
10005 16:33:24.106312 INFO: [APUAPC] D10_APC_0: 0xffffffff
10006 16:33:24.109753 INFO: [APUAPC] D10_APC_1: 0xffffffff
10007 16:33:24.112564 INFO: [APUAPC] D10_APC_2: 0x3fffff
10008 16:33:24.116177 INFO: [APUAPC] D10_APC_3: 0x0
10009 16:33:24.119092 INFO: [APUAPC] D11_APC_0: 0xffffffff
10010 16:33:24.122656 INFO: [APUAPC] D11_APC_1: 0xffffffff
10011 16:33:24.126216 INFO: [APUAPC] D11_APC_2: 0x3fffff
10012 16:33:24.129075 INFO: [APUAPC] D11_APC_3: 0x0
10013 16:33:24.132834 INFO: [APUAPC] D12_APC_0: 0xffffffff
10014 16:33:24.135712 INFO: [APUAPC] D12_APC_1: 0xffffffff
10015 16:33:24.139663 INFO: [APUAPC] D12_APC_2: 0x3fffff
10016 16:33:24.142273 INFO: [APUAPC] D12_APC_3: 0x0
10017 16:33:24.145793 INFO: [APUAPC] D13_APC_0: 0xffffffff
10018 16:33:24.149356 INFO: [APUAPC] D13_APC_1: 0xffffffff
10019 16:33:24.152287 INFO: [APUAPC] D13_APC_2: 0x3fffff
10020 16:33:24.155451 INFO: [APUAPC] D13_APC_3: 0x0
10021 16:33:24.159099 INFO: [APUAPC] D14_APC_0: 0xffffffff
10022 16:33:24.162747 INFO: [APUAPC] D14_APC_1: 0xffffffff
10023 16:33:24.165636 INFO: [APUAPC] D14_APC_2: 0x3fffff
10024 16:33:24.169215 INFO: [APUAPC] D14_APC_3: 0x0
10025 16:33:24.172631 INFO: [APUAPC] D15_APC_0: 0xffffffff
10026 16:33:24.176128 INFO: [APUAPC] D15_APC_1: 0xffffffff
10027 16:33:24.178800 INFO: [APUAPC] D15_APC_2: 0x3fffff
10028 16:33:24.182300 INFO: [APUAPC] D15_APC_3: 0x0
10029 16:33:24.185944 INFO: [APUAPC] APC_CON: 0x4
10030 16:33:24.188741 INFO: [NOCDAPC] D0_APC_0: 0x0
10031 16:33:24.192144 INFO: [NOCDAPC] D0_APC_1: 0x0
10032 16:33:24.192315 INFO: [NOCDAPC] D1_APC_0: 0x0
10033 16:33:24.195503 INFO: [NOCDAPC] D1_APC_1: 0xfff
10034 16:33:24.198807 INFO: [NOCDAPC] D2_APC_0: 0x0
10035 16:33:24.202186 INFO: [NOCDAPC] D2_APC_1: 0xfff
10036 16:33:24.205544 INFO: [NOCDAPC] D3_APC_0: 0x0
10037 16:33:24.208886 INFO: [NOCDAPC] D3_APC_1: 0xfff
10038 16:33:24.212177 INFO: [NOCDAPC] D4_APC_0: 0x0
10039 16:33:24.215763 INFO: [NOCDAPC] D4_APC_1: 0xfff
10040 16:33:24.218702 INFO: [NOCDAPC] D5_APC_0: 0x0
10041 16:33:24.221996 INFO: [NOCDAPC] D5_APC_1: 0xfff
10042 16:33:24.225777 INFO: [NOCDAPC] D6_APC_0: 0x0
10043 16:33:24.225934 INFO: [NOCDAPC] D6_APC_1: 0xfff
10044 16:33:24.228514 INFO: [NOCDAPC] D7_APC_0: 0x0
10045 16:33:24.232132 INFO: [NOCDAPC] D7_APC_1: 0xfff
10046 16:33:24.235776 INFO: [NOCDAPC] D8_APC_0: 0x0
10047 16:33:24.238834 INFO: [NOCDAPC] D8_APC_1: 0xfff
10048 16:33:24.242459 INFO: [NOCDAPC] D9_APC_0: 0x0
10049 16:33:24.245416 INFO: [NOCDAPC] D9_APC_1: 0xfff
10050 16:33:24.248767 INFO: [NOCDAPC] D10_APC_0: 0x0
10051 16:33:24.252157 INFO: [NOCDAPC] D10_APC_1: 0xfff
10052 16:33:24.255543 INFO: [NOCDAPC] D11_APC_0: 0x0
10053 16:33:24.259250 INFO: [NOCDAPC] D11_APC_1: 0xfff
10054 16:33:24.262191 INFO: [NOCDAPC] D12_APC_0: 0x0
10055 16:33:24.262302 INFO: [NOCDAPC] D12_APC_1: 0xfff
10056 16:33:24.266018 INFO: [NOCDAPC] D13_APC_0: 0x0
10057 16:33:24.268935 INFO: [NOCDAPC] D13_APC_1: 0xfff
10058 16:33:24.272494 INFO: [NOCDAPC] D14_APC_0: 0x0
10059 16:33:24.275454 INFO: [NOCDAPC] D14_APC_1: 0xfff
10060 16:33:24.278885 INFO: [NOCDAPC] D15_APC_0: 0x0
10061 16:33:24.282482 INFO: [NOCDAPC] D15_APC_1: 0xfff
10062 16:33:24.285874 INFO: [NOCDAPC] APC_CON: 0x4
10063 16:33:24.288800 INFO: [APUAPC] set_apusys_apc done
10064 16:33:24.292466 INFO: [DEVAPC] devapc_init done
10065 16:33:24.295215 INFO: GICv3 without legacy support detected.
10066 16:33:24.298762 INFO: ARM GICv3 driver initialized in EL3
10067 16:33:24.302293 INFO: Maximum SPI INTID supported: 639
10068 16:33:24.308535 INFO: BL31: Initializing runtime services
10069 16:33:24.312204 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10070 16:33:24.315133 INFO: SPM: enable CPC mode
10071 16:33:24.322298 INFO: mcdi ready for mcusys-off-idle and system suspend
10072 16:33:24.325770 INFO: BL31: Preparing for EL3 exit to normal world
10073 16:33:24.328314 INFO: Entry point address = 0x80000000
10074 16:33:24.331686 INFO: SPSR = 0x8
10075 16:33:24.337252
10076 16:33:24.337343
10077 16:33:24.337408
10078 16:33:24.340289 Starting depthcharge on Spherion...
10079 16:33:24.340377
10080 16:33:24.340442 Wipe memory regions:
10081 16:33:24.340503
10082 16:33:24.341183 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10083 16:33:24.341290 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10084 16:33:24.341371 Setting prompt string to ['asurada:']
10085 16:33:24.341454 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10086 16:33:24.343904 [0x00000040000000, 0x00000054600000)
10087 16:33:24.466274
10088 16:33:24.466389 [0x00000054660000, 0x00000080000000)
10089 16:33:24.727399
10090 16:33:24.727877 [0x000000821a7280, 0x000000ffe64000)
10091 16:33:25.472144
10092 16:33:25.472609 [0x00000100000000, 0x00000240000000)
10093 16:33:27.361893
10094 16:33:27.365269 Initializing XHCI USB controller at 0x11200000.
10095 16:33:28.403608
10096 16:33:28.407051 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10097 16:33:28.407166
10098 16:33:28.407251
10099 16:33:28.407554 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10101 16:33:28.507897 asurada: tftpboot 192.168.201.1 14396140/tftp-deploy-98og2484/kernel/image.itb 14396140/tftp-deploy-98og2484/kernel/cmdline
10102 16:33:28.508141 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10103 16:33:28.508280 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10104 16:33:28.512701 tftpboot 192.168.201.1 14396140/tftp-deploy-98og2484/kernel/image.ittp-deploy-98og2484/kernel/cmdline
10105 16:33:28.512780
10106 16:33:28.512845 Waiting for link
10107 16:33:28.671208
10108 16:33:28.671342 R8152: Initializing
10109 16:33:28.671432
10110 16:33:28.674579 Version 9 (ocp_data = 6010)
10111 16:33:28.674651
10112 16:33:28.677358 R8152: Done initializing
10113 16:33:28.677448
10114 16:33:28.677531 Adding net device
10115 16:33:30.625456
10116 16:33:30.625628 done.
10117 16:33:30.625717
10118 16:33:30.625803 MAC: 00:e0:4c:78:7a:aa
10119 16:33:30.625884
10120 16:33:30.628791 Sending DHCP discover... done.
10121 16:33:30.628895
10122 16:33:30.632148 Waiting for reply... done.
10123 16:33:30.632248
10124 16:33:30.635430 Sending DHCP request... done.
10125 16:33:30.635527
10126 16:33:30.647944 Waiting for reply... done.
10127 16:33:30.648048
10128 16:33:30.648135 My ip is 192.168.201.12
10129 16:33:30.648217
10130 16:33:30.651376 The DHCP server ip is 192.168.201.1
10131 16:33:30.651465
10132 16:33:30.657735 TFTP server IP predefined by user: 192.168.201.1
10133 16:33:30.657831
10134 16:33:30.664635 Bootfile predefined by user: 14396140/tftp-deploy-98og2484/kernel/image.itb
10135 16:33:30.664728
10136 16:33:30.667376 Sending tftp read request... done.
10137 16:33:30.667468
10138 16:33:30.671547 Waiting for the transfer...
10139 16:33:30.671636
10140 16:33:30.930293 00000000 ################################################################
10141 16:33:30.930407
10142 16:33:31.185970 00080000 ################################################################
10143 16:33:31.186105
10144 16:33:31.435889 00100000 ################################################################
10145 16:33:31.436079
10146 16:33:31.713967 00180000 ################################################################
10147 16:33:31.714079
10148 16:33:31.960976 00200000 ################################################################
10149 16:33:31.961118
10150 16:33:32.216660 00280000 ################################################################
10151 16:33:32.216776
10152 16:33:32.473488 00300000 ################################################################
10153 16:33:32.473647
10154 16:33:32.729846 00380000 ################################################################
10155 16:33:32.729958
10156 16:33:32.998948 00400000 ################################################################
10157 16:33:32.999082
10158 16:33:33.274489 00480000 ################################################################
10159 16:33:33.274631
10160 16:33:33.549531 00500000 ################################################################
10161 16:33:33.549739
10162 16:33:33.810978 00580000 ################################################################
10163 16:33:33.811099
10164 16:33:34.057031 00600000 ################################################################
10165 16:33:34.057177
10166 16:33:34.310538 00680000 ################################################################
10167 16:33:34.310684
10168 16:33:34.559620 00700000 ################################################################
10169 16:33:34.559739
10170 16:33:34.823473 00780000 ################################################################
10171 16:33:34.823590
10172 16:33:35.082910 00800000 ################################################################
10173 16:33:35.083037
10174 16:33:35.346745 00880000 ################################################################
10175 16:33:35.346883
10176 16:33:35.618988 00900000 ################################################################
10177 16:33:35.619119
10178 16:33:35.883649 00980000 ################################################################
10179 16:33:35.883764
10180 16:33:36.135836 00a00000 ################################################################
10181 16:33:36.135961
10182 16:33:36.397542 00a80000 ################################################################
10183 16:33:36.397670
10184 16:33:36.647232 00b00000 ################################################################
10185 16:33:36.647343
10186 16:33:36.911673 00b80000 ################################################################
10187 16:33:36.911788
10188 16:33:37.160049 00c00000 ################################################################
10189 16:33:37.160177
10190 16:33:37.420594 00c80000 ################################################################
10191 16:33:37.420714
10192 16:33:37.666070 00d00000 ################################################################
10193 16:33:37.666185
10194 16:33:37.914938 00d80000 ################################################################
10195 16:33:37.915050
10196 16:33:38.157929 00e00000 ################################################################
10197 16:33:38.158039
10198 16:33:38.414318 00e80000 ################################################################
10199 16:33:38.414433
10200 16:33:38.674749 00f00000 ################################################################
10201 16:33:38.674864
10202 16:33:38.924213 00f80000 ################################################################
10203 16:33:38.924324
10204 16:33:39.167577 01000000 ################################################################
10205 16:33:39.167692
10206 16:33:39.411911 01080000 ################################################################
10207 16:33:39.412019
10208 16:33:39.654777 01100000 ################################################################
10209 16:33:39.654903
10210 16:33:39.898387 01180000 ################################################################
10211 16:33:39.898550
10212 16:33:40.147928 01200000 ################################################################
10213 16:33:40.148045
10214 16:33:40.400126 01280000 ################################################################
10215 16:33:40.400242
10216 16:33:40.661650 01300000 ################################################################
10217 16:33:40.661764
10218 16:33:40.913827 01380000 ################################################################
10219 16:33:40.913994
10220 16:33:41.168469 01400000 ################################################################
10221 16:33:41.168615
10222 16:33:41.434134 01480000 ################################################################
10223 16:33:41.434255
10224 16:33:41.689391 01500000 ################################################################
10225 16:33:41.689528
10226 16:33:41.939850 01580000 ################################################################
10227 16:33:41.939990
10228 16:33:42.194827 01600000 ################################################################
10229 16:33:42.194994
10230 16:33:42.456040 01680000 ################################################################
10231 16:33:42.456196
10232 16:33:42.719519 01700000 ################################################################
10233 16:33:42.719645
10234 16:33:42.991423 01780000 ################################################################
10235 16:33:42.991545
10236 16:33:43.265614 01800000 ################################################################
10237 16:33:43.265731
10238 16:33:43.527615 01880000 ################################################################
10239 16:33:43.527744
10240 16:33:43.779642 01900000 ################################################################
10241 16:33:43.779761
10242 16:33:44.043311 01980000 ################################################################
10243 16:33:44.043427
10244 16:33:44.311495 01a00000 ################################################################
10245 16:33:44.311610
10246 16:33:44.574748 01a80000 ################################################################
10247 16:33:44.574888
10248 16:33:44.832145 01b00000 ################################################################
10249 16:33:44.832321
10250 16:33:45.102469 01b80000 ################################################################
10251 16:33:45.102582
10252 16:33:45.356484 01c00000 ################################################################
10253 16:33:45.356599
10254 16:33:45.614174 01c80000 ################################################################
10255 16:33:45.614298
10256 16:33:45.873476 01d00000 ################################################################
10257 16:33:45.873646
10258 16:33:46.131146 01d80000 ################################################################
10259 16:33:46.131275
10260 16:33:46.355972 01e00000 ######################################################### done.
10261 16:33:46.356091
10262 16:33:46.358819 The bootfile was 31923898 bytes long.
10263 16:33:46.358905
10264 16:33:46.362286 Sending tftp read request... done.
10265 16:33:46.362379
10266 16:33:46.362441 Waiting for the transfer...
10267 16:33:46.362498
10268 16:33:46.365785 00000000 # done.
10269 16:33:46.365892
10270 16:33:46.372198 Command line loaded dynamically from TFTP file: 14396140/tftp-deploy-98og2484/kernel/cmdline
10271 16:33:46.372321
10272 16:33:46.395394 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10273 16:33:46.395545
10274 16:33:46.395636 Loading FIT.
10275 16:33:46.395719
10276 16:33:46.398906 Image ramdisk-1 has 18745857 bytes.
10277 16:33:46.398983
10278 16:33:46.402476 Image fdt-1 has 47258 bytes.
10279 16:33:46.402562
10280 16:33:46.405169 Image kernel-1 has 13128753 bytes.
10281 16:33:46.405251
10282 16:33:46.415312 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10283 16:33:46.415444
10284 16:33:46.431717 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10285 16:33:46.431837
10286 16:33:46.438466 Choosing best match conf-1 for compat google,spherion-rev2.
10287 16:33:46.438562
10288 16:33:46.446529 Connected to device vid:did:rid of 1ae0:0028:00
10289 16:33:46.454716
10290 16:33:46.457446 tpm_get_response: command 0x17b, return code 0x0
10291 16:33:46.457559
10292 16:33:46.464488 ec_init: CrosEC protocol v3 supported (256, 248)
10293 16:33:46.464581
10294 16:33:46.468075 tpm_cleanup: add release locality here.
10295 16:33:46.468174
10296 16:33:46.470831 Shutting down all USB controllers.
10297 16:33:46.470902
10298 16:33:46.474246 Removing current net device
10299 16:33:46.474319
10300 16:33:46.477689 Exiting depthcharge with code 4 at timestamp: 51406754
10301 16:33:46.477785
10302 16:33:46.484713 LZMA decompressing kernel-1 to 0x821a6718
10303 16:33:46.484796
10304 16:33:46.487601 LZMA decompressing kernel-1 to 0x40000000
10305 16:33:48.103352
10306 16:33:48.103503 jumping to kernel
10307 16:33:48.104096 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10308 16:33:48.104203 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10309 16:33:48.104273 Setting prompt string to ['Linux version [0-9]']
10310 16:33:48.104346 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10311 16:33:48.104413 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10312 16:33:48.185687
10313 16:33:48.188887 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10314 16:33:48.192343 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10315 16:33:48.192438 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10316 16:33:48.192506 Setting prompt string to []
10317 16:33:48.192581 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10318 16:33:48.192651 Using line separator: #'\n'#
10319 16:33:48.192718 No login prompt set.
10320 16:33:48.192778 Parsing kernel messages
10321 16:33:48.192829 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10322 16:33:48.192928 [login-action] Waiting for messages, (timeout 00:03:56)
10323 16:33:48.192992 Waiting using forced prompt support (timeout 00:01:58)
10324 16:33:48.212504 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10325 16:33:48.215922 [ 0.000000] random: crng init done
10326 16:33:48.222520 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 16:33:48.225650 [ 0.000000] efi: UEFI not found.
10328 16:33:48.232429 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 16:33:48.238772 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 16:33:48.249228 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 16:33:48.259300 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 16:33:48.265571 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 16:33:48.269195 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 16:33:48.277644 [ 0.000000] NUMA: No NUMA configuration found
10335 16:33:48.284027 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 16:33:48.291104 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10337 16:33:48.291227 [ 0.000000] Zone ranges:
10338 16:33:48.297865 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 16:33:48.300675 [ 0.000000] DMA32 empty
10340 16:33:48.307554 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 16:33:48.310692 [ 0.000000] Movable zone start for each node
10342 16:33:48.314241 [ 0.000000] Early memory node ranges
10343 16:33:48.320629 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 16:33:48.327768 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 16:33:48.334253 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 16:33:48.340518 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 16:33:48.347528 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 16:33:48.353714 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 16:33:48.410163 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 16:33:48.416820 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 16:33:48.423997 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 16:33:48.427191 [ 0.000000] psci: probing for conduit method from DT.
10353 16:33:48.433664 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 16:33:48.436682 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 16:33:48.443259 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 16:33:48.446891 [ 0.000000] psci: SMC Calling Convention v1.2
10357 16:33:48.453645 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10358 16:33:48.456752 [ 0.000000] Detected VIPT I-cache on CPU0
10359 16:33:48.463165 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 16:33:48.469935 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 16:33:48.476692 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 16:33:48.482973 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 16:33:48.490148 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 16:33:48.499909 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 16:33:48.503334 [ 0.000000] alternatives: applying boot alternatives
10366 16:33:48.509492 [ 0.000000] Fallback order for Node 0: 0
10367 16:33:48.516482 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 16:33:48.519714 [ 0.000000] Policy zone: Normal
10369 16:33:48.543008 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10370 16:33:48.552893 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 16:33:48.563577 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 16:33:48.573415 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 16:33:48.579854 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 16:33:48.583098 <6>[ 0.000000] software IO TLB: area num 8.
10375 16:33:48.639926 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 16:33:48.789467 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10377 16:33:48.796304 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 16:33:48.802759 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 16:33:48.806249 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 16:33:48.813077 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 16:33:48.819986 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 16:33:48.823280 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 16:33:48.832634 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 16:33:48.839358 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 16:33:48.842755 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 16:33:48.850848 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 16:33:48.854167 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 16:33:48.860406 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 16:33:48.863775 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 16:33:48.866983 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 16:33:48.876830 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 16:33:48.886582 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 16:33:48.899975 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 16:33:48.907087 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 16:33:48.916422 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 16:33:48.929184 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 16:33:48.936165 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 16:33:48.942417 <6>[ 0.009231] Console: colour dummy device 80x25
10399 16:33:48.952437 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 16:33:48.958777 <6>[ 0.024448] pid_max: default: 32768 minimum: 301
10401 16:33:48.962380 <6>[ 0.029318] LSM: Security Framework initializing
10402 16:33:48.969183 <6>[ 0.034257] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 16:33:48.978943 <6>[ 0.042071] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 16:33:48.985964 <6>[ 0.051484] cblist_init_generic: Setting adjustable number of callback queues.
10405 16:33:48.992380 <6>[ 0.058927] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 16:33:49.002403 <6>[ 0.065267] cblist_init_generic: Setting adjustable number of callback queues.
10407 16:33:49.008957 <6>[ 0.072694] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 16:33:49.012544 <6>[ 0.079133] rcu: Hierarchical SRCU implementation.
10409 16:33:49.018768 <6>[ 0.084148] rcu: Max phase no-delay instances is 1000.
10410 16:33:49.025869 <6>[ 0.091179] EFI services will not be available.
10411 16:33:49.028723 <6>[ 0.096164] smp: Bringing up secondary CPUs ...
10412 16:33:49.036936 <6>[ 0.101246] Detected VIPT I-cache on CPU1
10413 16:33:49.043535 <6>[ 0.101318] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10414 16:33:49.050186 <6>[ 0.101350] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10415 16:33:49.053246 <6>[ 0.101695] Detected VIPT I-cache on CPU2
10416 16:33:49.059955 <6>[ 0.101747] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10417 16:33:49.067273 <6>[ 0.101767] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10418 16:33:49.073808 <6>[ 0.102028] Detected VIPT I-cache on CPU3
10419 16:33:49.079866 <6>[ 0.102077] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10420 16:33:49.086963 <6>[ 0.102092] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10421 16:33:49.090356 <6>[ 0.102400] CPU features: detected: Spectre-v4
10422 16:33:49.096415 <6>[ 0.102405] CPU features: detected: Spectre-BHB
10423 16:33:49.099683 <6>[ 0.102410] Detected PIPT I-cache on CPU4
10424 16:33:49.106741 <6>[ 0.102468] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10425 16:33:49.113210 <6>[ 0.102485] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10426 16:33:49.119678 <6>[ 0.102767] Detected PIPT I-cache on CPU5
10427 16:33:49.126853 <6>[ 0.102822] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10428 16:33:49.132745 <6>[ 0.102838] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10429 16:33:49.136480 <6>[ 0.103112] Detected PIPT I-cache on CPU6
10430 16:33:49.143220 <6>[ 0.103176] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10431 16:33:49.149534 <6>[ 0.103191] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10432 16:33:49.156429 <6>[ 0.103487] Detected PIPT I-cache on CPU7
10433 16:33:49.163121 <6>[ 0.103552] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10434 16:33:49.169233 <6>[ 0.103568] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10435 16:33:49.173069 <6>[ 0.103616] smp: Brought up 1 node, 8 CPUs
10436 16:33:49.179371 <6>[ 0.245089] SMP: Total of 8 processors activated.
10437 16:33:49.183003 <6>[ 0.250010] CPU features: detected: 32-bit EL0 Support
10438 16:33:49.193010 <6>[ 0.255373] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10439 16:33:49.199860 <6>[ 0.264226] CPU features: detected: Common not Private translations
10440 16:33:49.202697 <6>[ 0.270702] CPU features: detected: CRC32 instructions
10441 16:33:49.209454 <6>[ 0.276053] CPU features: detected: RCpc load-acquire (LDAPR)
10442 16:33:49.215814 <6>[ 0.282050] CPU features: detected: LSE atomic instructions
10443 16:33:49.223119 <6>[ 0.287832] CPU features: detected: Privileged Access Never
10444 16:33:49.225987 <6>[ 0.293612] CPU features: detected: RAS Extension Support
10445 16:33:49.235916 <6>[ 0.299255] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10446 16:33:49.239413 <6>[ 0.306474] CPU: All CPU(s) started at EL2
10447 16:33:49.245754 <6>[ 0.310791] alternatives: applying system-wide alternatives
10448 16:33:49.254658 <6>[ 0.321636] devtmpfs: initialized
10449 16:33:49.267539 <6>[ 0.330587] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10450 16:33:49.277193 <6>[ 0.340547] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10451 16:33:49.283546 <6>[ 0.348566] pinctrl core: initialized pinctrl subsystem
10452 16:33:49.287047 <6>[ 0.355224] DMI not present or invalid.
10453 16:33:49.293857 <6>[ 0.359637] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10454 16:33:49.303565 <6>[ 0.366502] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10455 16:33:49.310119 <6>[ 0.374091] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10456 16:33:49.320202 <6>[ 0.382308] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10457 16:33:49.323475 <6>[ 0.390551] audit: initializing netlink subsys (disabled)
10458 16:33:49.333243 <5>[ 0.396245] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10459 16:33:49.340550 <6>[ 0.396964] thermal_sys: Registered thermal governor 'step_wise'
10460 16:33:49.346827 <6>[ 0.404212] thermal_sys: Registered thermal governor 'power_allocator'
10461 16:33:49.350147 <6>[ 0.410465] cpuidle: using governor menu
10462 16:33:49.356881 <6>[ 0.421423] NET: Registered PF_QIPCRTR protocol family
10463 16:33:49.363094 <6>[ 0.426909] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10464 16:33:49.366551 <6>[ 0.434013] ASID allocator initialised with 32768 entries
10465 16:33:49.374100 <6>[ 0.440598] Serial: AMBA PL011 UART driver
10466 16:33:49.382923 <4>[ 0.449478] Trying to register duplicate clock ID: 134
10467 16:33:49.442647 <6>[ 0.512885] KASLR enabled
10468 16:33:49.457085 <6>[ 0.520634] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10469 16:33:49.463643 <6>[ 0.527645] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10470 16:33:49.470645 <6>[ 0.534132] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10471 16:33:49.477422 <6>[ 0.541137] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10472 16:33:49.483687 <6>[ 0.547624] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10473 16:33:49.490498 <6>[ 0.554629] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10474 16:33:49.497095 <6>[ 0.561116] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10475 16:33:49.503721 <6>[ 0.568120] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10476 16:33:49.507119 <6>[ 0.575638] ACPI: Interpreter disabled.
10477 16:33:49.515234 <6>[ 0.582086] iommu: Default domain type: Translated
10478 16:33:49.522207 <6>[ 0.587198] iommu: DMA domain TLB invalidation policy: strict mode
10479 16:33:49.525643 <5>[ 0.593862] SCSI subsystem initialized
10480 16:33:49.532289 <6>[ 0.598025] usbcore: registered new interface driver usbfs
10481 16:33:49.538736 <6>[ 0.603759] usbcore: registered new interface driver hub
10482 16:33:49.541868 <6>[ 0.609309] usbcore: registered new device driver usb
10483 16:33:49.548842 <6>[ 0.615417] pps_core: LinuxPPS API ver. 1 registered
10484 16:33:49.558676 <6>[ 0.620611] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10485 16:33:49.562164 <6>[ 0.629958] PTP clock support registered
10486 16:33:49.564872 <6>[ 0.634202] EDAC MC: Ver: 3.0.0
10487 16:33:49.572551 <6>[ 0.639339] FPGA manager framework
10488 16:33:49.576143 <6>[ 0.643026] Advanced Linux Sound Architecture Driver Initialized.
10489 16:33:49.579526 <6>[ 0.649810] vgaarb: loaded
10490 16:33:49.586686 <6>[ 0.652965] clocksource: Switched to clocksource arch_sys_counter
10491 16:33:49.592888 <5>[ 0.659406] VFS: Disk quotas dquot_6.6.0
10492 16:33:49.599665 <6>[ 0.663593] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10493 16:33:49.603161 <6>[ 0.670784] pnp: PnP ACPI: disabled
10494 16:33:49.610899 <6>[ 0.677537] NET: Registered PF_INET protocol family
10495 16:33:49.620802 <6>[ 0.683132] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10496 16:33:49.631990 <6>[ 0.695444] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10497 16:33:49.642112 <6>[ 0.704258] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10498 16:33:49.648771 <6>[ 0.712230] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10499 16:33:49.658636 <6>[ 0.720929] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10500 16:33:49.664886 <6>[ 0.730684] TCP: Hash tables configured (established 65536 bind 65536)
10501 16:33:49.671322 <6>[ 0.737549] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 16:33:49.681653 <6>[ 0.744752] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10503 16:33:49.688442 <6>[ 0.752453] NET: Registered PF_UNIX/PF_LOCAL protocol family
10504 16:33:49.691178 <6>[ 0.758607] RPC: Registered named UNIX socket transport module.
10505 16:33:49.698109 <6>[ 0.764760] RPC: Registered udp transport module.
10506 16:33:49.701540 <6>[ 0.769692] RPC: Registered tcp transport module.
10507 16:33:49.707854 <6>[ 0.774625] RPC: Registered tcp NFSv4.1 backchannel transport module.
10508 16:33:49.714910 <6>[ 0.781291] PCI: CLS 0 bytes, default 64
10509 16:33:49.717587 <6>[ 0.785610] Unpacking initramfs...
10510 16:33:49.738416 <6>[ 0.801472] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10511 16:33:49.747728 <6>[ 0.810118] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10512 16:33:49.751646 <6>[ 0.818965] kvm [1]: IPA Size Limit: 40 bits
10513 16:33:49.757980 <6>[ 0.823478] kvm [1]: GICv3: no GICV resource entry
10514 16:33:49.761245 <6>[ 0.828498] kvm [1]: disabling GICv2 emulation
10515 16:33:49.767990 <6>[ 0.833185] kvm [1]: GIC system register CPU interface enabled
10516 16:33:49.771233 <6>[ 0.839337] kvm [1]: vgic interrupt IRQ18
10517 16:33:49.777535 <6>[ 0.843696] kvm [1]: VHE mode initialized successfully
10518 16:33:49.784685 <5>[ 0.850105] Initialise system trusted keyrings
10519 16:33:49.790645 <6>[ 0.854917] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10520 16:33:49.798664 <6>[ 0.864979] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10521 16:33:49.805087 <5>[ 0.871410] NFS: Registering the id_resolver key type
10522 16:33:49.808737 <5>[ 0.876715] Key type id_resolver registered
10523 16:33:49.814827 <5>[ 0.881129] Key type id_legacy registered
10524 16:33:49.821167 <6>[ 0.885407] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10525 16:33:49.827828 <6>[ 0.892329] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10526 16:33:49.834225 <6>[ 0.900056] 9p: Installing v9fs 9p2000 file system support
10527 16:33:49.871792 <5>[ 0.938619] Key type asymmetric registered
10528 16:33:49.875198 <5>[ 0.942950] Asymmetric key parser 'x509' registered
10529 16:33:49.885356 <6>[ 0.948097] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10530 16:33:49.888606 <6>[ 0.955711] io scheduler mq-deadline registered
10531 16:33:49.891713 <6>[ 0.960484] io scheduler kyber registered
10532 16:33:49.910796 <6>[ 0.977726] EINJ: ACPI disabled.
10533 16:33:49.944096 <4>[ 1.004255] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 16:33:49.954081 <4>[ 1.014885] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 16:33:49.969265 <6>[ 1.036004] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10536 16:33:49.976967 <6>[ 1.044043] printk: console [ttyS0] disabled
10537 16:33:50.005283 <6>[ 1.068679] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10538 16:33:50.011635 <6>[ 1.078160] printk: console [ttyS0] enabled
10539 16:33:50.015627 <6>[ 1.078160] printk: console [ttyS0] enabled
10540 16:33:50.021713 <6>[ 1.087057] printk: bootconsole [mtk8250] disabled
10541 16:33:50.025048 <6>[ 1.087057] printk: bootconsole [mtk8250] disabled
10542 16:33:50.031880 <6>[ 1.098358] SuperH (H)SCI(F) driver initialized
10543 16:33:50.034813 <6>[ 1.103659] msm_serial: driver initialized
10544 16:33:50.049064 <6>[ 1.112615] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10545 16:33:50.058692 <6>[ 1.121168] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10546 16:33:50.065318 <6>[ 1.129710] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10547 16:33:50.075606 <6>[ 1.138338] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10548 16:33:50.085421 <6>[ 1.147044] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10549 16:33:50.092227 <6>[ 1.155764] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10550 16:33:50.102175 <6>[ 1.164306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10551 16:33:50.108278 <6>[ 1.173116] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10552 16:33:50.118271 <6>[ 1.181664] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10553 16:33:50.130658 <6>[ 1.197547] loop: module loaded
10554 16:33:50.137428 <6>[ 1.203589] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10555 16:33:50.159781 <4>[ 1.226628] mtk-pmic-keys: Failed to locate of_node [id: -1]
10556 16:33:50.166678 <6>[ 1.233493] megasas: 07.719.03.00-rc1
10557 16:33:50.176826 <6>[ 1.243266] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10558 16:33:50.185717 <6>[ 1.252361] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10559 16:33:50.202519 <6>[ 1.269097] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10560 16:33:50.259072 <6>[ 1.319183] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10561 16:33:50.542117 <6>[ 1.608710] Freeing initrd memory: 18304K
10562 16:33:50.553222 <6>[ 1.620212] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10563 16:33:50.564487 <6>[ 1.631273] tun: Universal TUN/TAP device driver, 1.6
10564 16:33:50.567700 <6>[ 1.637361] thunder_xcv, ver 1.0
10565 16:33:50.570824 <6>[ 1.640856] thunder_bgx, ver 1.0
10566 16:33:50.574605 <6>[ 1.644354] nicpf, ver 1.0
10567 16:33:50.585108 <6>[ 1.648393] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10568 16:33:50.588569 <6>[ 1.655871] hns3: Copyright (c) 2017 Huawei Corporation.
10569 16:33:50.591319 <6>[ 1.661462] hclge is initializing
10570 16:33:50.598123 <6>[ 1.665044] e1000: Intel(R) PRO/1000 Network Driver
10571 16:33:50.604943 <6>[ 1.670176] e1000: Copyright (c) 1999-2006 Intel Corporation.
10572 16:33:50.608372 <6>[ 1.676193] e1000e: Intel(R) PRO/1000 Network Driver
10573 16:33:50.615340 <6>[ 1.681408] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10574 16:33:50.622167 <6>[ 1.687594] igb: Intel(R) Gigabit Ethernet Network Driver
10575 16:33:50.628258 <6>[ 1.693245] igb: Copyright (c) 2007-2014 Intel Corporation.
10576 16:33:50.635322 <6>[ 1.699082] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10577 16:33:50.638296 <6>[ 1.705600] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10578 16:33:50.645413 <6>[ 1.712065] sky2: driver version 1.30
10579 16:33:50.652191 <6>[ 1.717006] usbcore: registered new device driver r8152-cfgselector
10580 16:33:50.658684 <6>[ 1.723540] usbcore: registered new interface driver r8152
10581 16:33:50.662061 <6>[ 1.729363] VFIO - User Level meta-driver version: 0.3
10582 16:33:50.671272 <6>[ 1.737642] usbcore: registered new interface driver usb-storage
10583 16:33:50.677329 <6>[ 1.744089] usbcore: registered new device driver onboard-usb-hub
10584 16:33:50.686449 <6>[ 1.753266] mt6397-rtc mt6359-rtc: registered as rtc0
10585 16:33:50.696382 <6>[ 1.758734] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:33:50 UTC (1718642030)
10586 16:33:50.699815 <6>[ 1.768308] i2c_dev: i2c /dev entries driver
10587 16:33:50.713599 <4>[ 1.780428] cpu cpu0: supply cpu not found, using dummy regulator
10588 16:33:50.720168 <4>[ 1.786847] cpu cpu1: supply cpu not found, using dummy regulator
10589 16:33:50.726592 <4>[ 1.793251] cpu cpu2: supply cpu not found, using dummy regulator
10590 16:33:50.733835 <4>[ 1.799647] cpu cpu3: supply cpu not found, using dummy regulator
10591 16:33:50.740507 <4>[ 1.806065] cpu cpu4: supply cpu not found, using dummy regulator
10592 16:33:50.746627 <4>[ 1.812459] cpu cpu5: supply cpu not found, using dummy regulator
10593 16:33:50.753482 <4>[ 1.818856] cpu cpu6: supply cpu not found, using dummy regulator
10594 16:33:50.760465 <4>[ 1.825255] cpu cpu7: supply cpu not found, using dummy regulator
10595 16:33:50.778872 <6>[ 1.845845] cpu cpu0: EM: created perf domain
10596 16:33:50.782067 <6>[ 1.850780] cpu cpu4: EM: created perf domain
10597 16:33:50.789293 <6>[ 1.856383] sdhci: Secure Digital Host Controller Interface driver
10598 16:33:50.795917 <6>[ 1.862814] sdhci: Copyright(c) Pierre Ossman
10599 16:33:50.803093 <6>[ 1.867772] Synopsys Designware Multimedia Card Interface Driver
10600 16:33:50.809412 <6>[ 1.874405] sdhci-pltfm: SDHCI platform and OF driver helper
10601 16:33:50.812590 <6>[ 1.874412] mmc0: CQHCI version 5.10
10602 16:33:50.819375 <6>[ 1.884276] ledtrig-cpu: registered to indicate activity on CPUs
10603 16:33:50.826238 <6>[ 1.891262] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10604 16:33:50.833130 <6>[ 1.898309] usbcore: registered new interface driver usbhid
10605 16:33:50.836479 <6>[ 1.904132] usbhid: USB HID core driver
10606 16:33:50.842751 <6>[ 1.908325] spi_master spi0: will run message pump with realtime priority
10607 16:33:50.886093 <6>[ 1.946464] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10608 16:33:50.904833 <6>[ 1.961856] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10609 16:33:50.908754 <6>[ 1.975249] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10610 16:33:50.915497 <6>[ 1.982247] cros-ec-spi spi0.0: Chrome EC device registered
10611 16:33:50.922195 <6>[ 1.988271] mmc0: Command Queue Engine enabled
10612 16:33:50.929224 <6>[ 1.993041] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10613 16:33:50.932400 <6>[ 2.000692] mmcblk0: mmc0:0001 DA4128 116 GiB
10614 16:33:50.942439 <6>[ 2.009603] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10615 16:33:50.950619 <6>[ 2.017215] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10616 16:33:50.960325 <6>[ 2.022837] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10617 16:33:50.967114 <6>[ 2.023176] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10618 16:33:50.970628 <6>[ 2.033664] NET: Registered PF_PACKET protocol family
10619 16:33:50.977440 <6>[ 2.038112] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10620 16:33:50.980335 <6>[ 2.042749] 9pnet: Installing 9P2000 support
10621 16:33:50.987004 <5>[ 2.053761] Key type dns_resolver registered
10622 16:33:50.990276 <6>[ 2.058750] registered taskstats version 1
10623 16:33:50.996849 <5>[ 2.063139] Loading compiled-in X.509 certificates
10624 16:33:51.025354 <4>[ 2.085315] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 16:33:51.034775 <4>[ 2.096040] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 16:33:51.049301 <6>[ 2.116374] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10627 16:33:51.056695 <6>[ 2.123251] xhci-mtk 11200000.usb: xHCI Host Controller
10628 16:33:51.062853 <6>[ 2.128798] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10629 16:33:51.073212 <6>[ 2.136655] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10630 16:33:51.079860 <6>[ 2.146089] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10631 16:33:51.086708 <6>[ 2.152243] xhci-mtk 11200000.usb: xHCI Host Controller
10632 16:33:51.093449 <6>[ 2.157739] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10633 16:33:51.100211 <6>[ 2.165391] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10634 16:33:51.106281 <6>[ 2.173247] hub 1-0:1.0: USB hub found
10635 16:33:51.109593 <6>[ 2.177265] hub 1-0:1.0: 1 port detected
10636 16:33:51.116334 <6>[ 2.181567] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10637 16:33:51.123691 <6>[ 2.190297] hub 2-0:1.0: USB hub found
10638 16:33:51.126510 <6>[ 2.194319] hub 2-0:1.0: 1 port detected
10639 16:33:51.134571 <6>[ 2.201450] mtk-msdc 11f70000.mmc: Got CD GPIO
10640 16:33:51.153899 <6>[ 2.217571] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10641 16:33:51.164084 <6>[ 2.225942] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10642 16:33:51.170934 <6>[ 2.234286] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10643 16:33:51.181182 <6>[ 2.242625] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10644 16:33:51.187436 <6>[ 2.250969] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10645 16:33:51.194310 <6>[ 2.259306] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10646 16:33:51.204292 <6>[ 2.267645] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10647 16:33:51.211117 <6>[ 2.275983] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10648 16:33:51.220816 <6>[ 2.284322] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10649 16:33:51.230888 <6>[ 2.292660] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10650 16:33:51.237457 <6>[ 2.301009] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10651 16:33:51.247153 <6>[ 2.309347] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10652 16:33:51.253790 <6>[ 2.317685] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10653 16:33:51.264104 <6>[ 2.326023] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10654 16:33:51.270386 <6>[ 2.334360] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10655 16:33:51.277143 <6>[ 2.343087] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10656 16:33:51.283494 <6>[ 2.350252] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10657 16:33:51.290263 <6>[ 2.357090] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10658 16:33:51.296770 <6>[ 2.363859] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10659 16:33:51.307070 <6>[ 2.370833] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10660 16:33:51.313685 <6>[ 2.377687] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10661 16:33:51.323961 <6>[ 2.386820] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10662 16:33:51.333603 <6>[ 2.395940] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10663 16:33:51.343738 <6>[ 2.405237] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10664 16:33:51.353695 <6>[ 2.414705] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10665 16:33:51.360156 <6>[ 2.424172] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10666 16:33:51.370224 <6>[ 2.433292] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10667 16:33:51.380548 <6>[ 2.442759] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10668 16:33:51.390107 <6>[ 2.451887] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10669 16:33:51.400262 <6>[ 2.461183] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10670 16:33:51.409756 <6>[ 2.471343] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10671 16:33:51.419709 <6>[ 2.483112] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10672 16:33:51.427280 <6>[ 2.493904] Trying to probe devices needed for running init ...
10673 16:33:51.437424 <3>[ 2.501343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10674 16:33:51.518024 <6>[ 2.581517] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10675 16:33:51.546462 <6>[ 2.613064] hub 2-1:1.0: USB hub found
10676 16:33:51.549148 <6>[ 2.617554] hub 2-1:1.0: 3 ports detected
10677 16:33:51.560038 <6>[ 2.626698] hub 2-1:1.0: USB hub found
10678 16:33:51.562726 <6>[ 2.631132] hub 2-1:1.0: 3 ports detected
10679 16:33:51.669667 <6>[ 2.733263] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10680 16:33:51.824157 <6>[ 2.891268] hub 1-1:1.0: USB hub found
10681 16:33:51.827836 <6>[ 2.895758] hub 1-1:1.0: 4 ports detected
10682 16:33:51.840744 <6>[ 2.907380] hub 1-1:1.0: USB hub found
10683 16:33:51.843947 <6>[ 2.911777] hub 1-1:1.0: 4 ports detected
10684 16:33:51.909778 <6>[ 2.973504] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10685 16:33:52.018479 <6>[ 3.081929] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10686 16:33:52.053947 <4>[ 3.117280] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10687 16:33:52.063688 <4>[ 3.126354] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10688 16:33:52.108265 <6>[ 3.175191] r8152 2-1.3:1.0 eth0: v1.12.13
10689 16:33:52.165718 <6>[ 3.229242] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10690 16:33:52.297832 <6>[ 3.364572] hub 1-1.4:1.0: USB hub found
10691 16:33:52.300962 <6>[ 3.369119] hub 1-1.4:1.0: 2 ports detected
10692 16:33:52.314220 <6>[ 3.381441] hub 1-1.4:1.0: USB hub found
10693 16:33:52.317652 <6>[ 3.385972] hub 1-1.4:1.0: 2 ports detected
10694 16:33:52.613411 <6>[ 3.677119] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10695 16:33:52.805643 <6>[ 3.869125] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10696 16:33:53.750391 <6>[ 4.817603] r8152 2-1.3:1.0 eth0: carrier on
10697 16:33:56.233763 <5>[ 4.845080] Sending DHCP requests .., OK
10698 16:33:56.240368 <6>[ 7.305474] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10699 16:33:56.243808 <6>[ 7.313806] IP-Config: Complete:
10700 16:33:56.256933 <6>[ 7.317310] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10701 16:33:56.263970 <6>[ 7.328022] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10702 16:33:56.270254 <6>[ 7.336641] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10703 16:33:56.277105 <6>[ 7.336650] nameserver0=192.168.201.1
10704 16:33:56.280537 <6>[ 7.348796] clk: Disabling unused clocks
10705 16:33:56.283985 <6>[ 7.354305] ALSA device list:
10706 16:33:56.290246 <6>[ 7.357583] No soundcards found.
10707 16:33:56.297906 <6>[ 7.365339] Freeing unused kernel memory: 8512K
10708 16:33:56.301367 <6>[ 7.370262] Run /init as init process
10709 16:33:56.310982 Loading, please wait...
10710 16:33:56.340856 Starting systemd-udevd version 252.22-1~deb12u1
10711 16:33:56.639397 <6>[ 7.703411] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10712 16:33:56.645980 <6>[ 7.706035] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10713 16:33:56.658551 <6>[ 7.722434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10714 16:33:56.661910 <6>[ 7.729820] remoteproc remoteproc0: scp is available
10715 16:33:56.671545 <6>[ 7.731014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10716 16:33:56.678617 <6>[ 7.731533] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10717 16:33:56.688015 <6>[ 7.731559] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10718 16:33:56.695010 <6>[ 7.731566] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10719 16:33:56.701821 <6>[ 7.735845] remoteproc remoteproc0: powering up scp
10720 16:33:56.711672 <4>[ 7.744095] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10721 16:33:56.718062 <6>[ 7.751154] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10722 16:33:56.724516 <6>[ 7.751171] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10723 16:33:56.731469 <3>[ 7.760017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 16:33:56.741134 <6>[ 7.760882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10725 16:33:56.747745 <6>[ 7.760891] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10726 16:33:56.757938 <6>[ 7.766400] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10727 16:33:56.764189 <6>[ 7.766413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10728 16:33:56.771308 <6>[ 7.766416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10729 16:33:56.780696 <6>[ 7.766421] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10730 16:33:56.787788 <6>[ 7.792889] mc: Linux media interface: v0.10
10731 16:33:56.794789 <3>[ 7.797003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 16:33:56.801472 <6>[ 7.798832] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10733 16:33:56.808547 <4>[ 7.813116] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10734 16:33:56.814851 <4>[ 7.821460] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10735 16:33:56.825287 <3>[ 7.829915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 16:33:56.828377 <6>[ 7.830505] videodev: Linux video capture interface: v2.00
10737 16:33:56.838317 <4>[ 7.838044] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10738 16:33:56.844916 <4>[ 7.838044] Fallback method does not support PEC.
10739 16:33:56.851385 <3>[ 7.846365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 16:33:56.858216 <6>[ 7.851021] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10741 16:33:56.865198 <6>[ 7.851028] pci_bus 0000:00: root bus resource [bus 00-ff]
10742 16:33:56.871696 <6>[ 7.851033] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10743 16:33:56.881147 <6>[ 7.851037] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10744 16:33:56.888283 <6>[ 7.851079] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10745 16:33:56.894936 <6>[ 7.851097] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10746 16:33:56.901138 <6>[ 7.851171] pci 0000:00:00.0: supports D1 D2
10747 16:33:56.908288 <6>[ 7.851174] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 16:33:56.914425 <6>[ 7.852180] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10749 16:33:56.921034 <6>[ 7.852279] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10750 16:33:56.927544 <6>[ 7.852305] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10751 16:33:56.937473 <6>[ 7.852324] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10752 16:33:56.944217 <6>[ 7.852339] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10753 16:33:56.947351 <6>[ 7.852451] pci 0000:01:00.0: supports D1 D2
10754 16:33:56.954520 <6>[ 7.852452] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10755 16:33:56.960847 <6>[ 7.857057] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10756 16:33:56.970913 <3>[ 7.858528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 16:33:56.977384 <6>[ 7.866827] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10758 16:33:56.987582 <3>[ 7.870036] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10759 16:33:56.994292 <3>[ 7.874330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 16:33:57.003826 <6>[ 7.881449] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10761 16:33:57.013594 <6>[ 7.881578] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10762 16:33:57.020202 <6>[ 7.881968] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10763 16:33:57.030388 <3>[ 7.888815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 16:33:57.040651 <3>[ 7.893291] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10765 16:33:57.047151 <6>[ 7.896135] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10766 16:33:57.054237 <6>[ 7.896903] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10767 16:33:57.063477 <6>[ 7.901068] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10768 16:33:57.070306 <6>[ 7.901085] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10769 16:33:57.076563 <6>[ 7.901098] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10770 16:33:57.083568 <6>[ 7.901110] pci 0000:00:00.0: PCI bridge to [bus 01]
10771 16:33:57.090279 <6>[ 7.901115] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10772 16:33:57.096656 <6>[ 7.901259] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10773 16:33:57.103190 <6>[ 7.901734] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10774 16:33:57.110093 <6>[ 7.902276] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10775 16:33:57.116850 <3>[ 7.902626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 16:33:57.123398 <6>[ 7.916259] remoteproc remoteproc0: remote processor scp is now up
10777 16:33:57.133595 <6>[ 7.917622] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10778 16:33:57.139503 <6>[ 7.920086] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10779 16:33:57.149738 <3>[ 7.924365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 16:33:57.159905 <6>[ 7.960821] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10781 16:33:57.166345 <3>[ 7.967721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 16:33:57.172759 <5>[ 7.996214] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10783 16:33:57.183051 <3>[ 8.001071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 16:33:57.189412 <3>[ 8.001076] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 16:33:57.199364 <3>[ 8.001137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 16:33:57.203258 <6>[ 8.021304] Bluetooth: Core ver 2.22
10787 16:33:57.209602 <5>[ 8.024304] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10788 16:33:57.215937 <5>[ 8.024796] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10789 16:33:57.225880 <4>[ 8.024879] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10790 16:33:57.232279 <6>[ 8.024887] cfg80211: failed to load regulatory.db
10791 16:33:57.238907 <3>[ 8.027465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 16:33:57.245770 <6>[ 8.034384] NET: Registered PF_BLUETOOTH protocol family
10793 16:33:57.252493 <6>[ 8.035927] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10794 16:33:57.265438 <6>[ 8.037306] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10795 16:33:57.269172 <6>[ 8.037439] usbcore: registered new interface driver uvcvideo
10796 16:33:57.278806 <3>[ 8.042412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 16:33:57.285345 <6>[ 8.050492] Bluetooth: HCI device and connection manager initialized
10798 16:33:57.292282 <3>[ 8.059267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 16:33:57.298423 <6>[ 8.067355] Bluetooth: HCI socket layer initialized
10800 16:33:57.305252 <6>[ 8.068560] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10801 16:33:57.311673 <3>[ 8.077419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 16:33:57.319017 <6>[ 8.085416] Bluetooth: L2CAP socket layer initialized
10803 16:33:57.325404 <3>[ 8.094457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 16:33:57.331683 <6>[ 8.102534] Bluetooth: SCO socket layer initialized
10805 16:33:57.338775 <6>[ 8.138751] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10806 16:33:57.345384 <6>[ 8.190964] usbcore: registered new interface driver btusb
10807 16:33:57.354902 <4>[ 8.191984] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10808 16:33:57.361781 <3>[ 8.191991] Bluetooth: hci0: Failed to load firmware file (-2)
10809 16:33:57.368008 <3>[ 8.191994] Bluetooth: hci0: Failed to set up firmware (-2)
10810 16:33:57.377919 <4>[ 8.191996] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10811 16:33:57.384931 <6>[ 8.197117] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10812 16:33:57.409243 <6>[ 8.476732] mt7921e 0000:01:00.0: ASIC revision: 79610010
10813 16:33:57.512675 <6>[ 8.576846] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10814 16:33:57.515677 <6>[ 8.576846]
10815 16:33:57.519205 Begin: Loading essential drivers ... done.
10816 16:33:57.522723 Begin: Running /scripts/init-premount ... done.
10817 16:33:57.529480 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10818 16:33:57.539547 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10819 16:33:57.542312 Device /sys/class/net/eth0 found
10820 16:33:57.542379 done.
10821 16:33:57.554557 Begin: Waiting up to 180 secs for any network device to become available ... done.
10822 16:33:57.589535 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10823 16:33:57.596529 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10824 16:33:57.602574 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10825 16:33:57.609346 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10826 16:33:57.615818 host : mt8192-asurada-spherion-r0-cbg-0
10827 16:33:57.623013 domain : lava-rack
10828 16:33:57.625796 rootserver: 192.168.201.1 rootpath:
10829 16:33:57.629421 filename :
10830 16:33:57.629512 done.
10831 16:33:57.632829 Begin: Running /scripts/nfs-bottom ... done.
10832 16:33:57.651818 Begin: Running /scripts/init-bottom ... done.
10833 16:33:57.782409 <6>[ 8.847002] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10834 16:33:58.953849 <6>[ 10.021233] NET: Registered PF_INET6 protocol family
10835 16:33:58.961259 <6>[ 10.028884] Segment Routing with IPv6
10836 16:33:58.964817 <6>[ 10.032889] In-situ OAM (IOAM) with IPv6
10837 16:33:59.136254 <30>[ 10.177214] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10838 16:33:59.142750 <30>[ 10.210299] systemd[1]: Detected architecture arm64.
10839 16:33:59.150207
10840 16:33:59.153126 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10841 16:33:59.153219
10842 16:33:59.177875 <30>[ 10.245956] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10843 16:34:00.262678 <30>[ 11.327042] systemd[1]: Queued start job for default target graphical.target.
10844 16:34:00.305808 <30>[ 11.370558] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10845 16:34:00.312730 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10846 16:34:00.334316 <30>[ 11.399011] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10847 16:34:00.344644 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10848 16:34:00.362228 <30>[ 11.426959] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10849 16:34:00.372268 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10850 16:34:00.390000 <30>[ 11.454605] systemd[1]: Created slice user.slice - User and Session Slice.
10851 16:34:00.396341 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10852 16:34:00.420939 <30>[ 11.482146] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10853 16:34:00.430752 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10854 16:34:00.448888 <30>[ 11.509516] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10855 16:34:00.455127 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10856 16:34:00.483251 <30>[ 11.537826] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10857 16:34:00.493410 <30>[ 11.557727] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10858 16:34:00.500067 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10859 16:34:00.517606 <30>[ 11.581647] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10860 16:34:00.524000 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10861 16:34:00.546050 <30>[ 11.609790] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10862 16:34:00.555173 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10863 16:34:00.570522 <30>[ 11.637804] systemd[1]: Reached target paths.target - Path Units.
10864 16:34:00.580170 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10865 16:34:00.597485 <30>[ 11.661722] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10866 16:34:00.604085 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10867 16:34:00.617947 <30>[ 11.685243] systemd[1]: Reached target slices.target - Slice Units.
10868 16:34:00.628535 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10869 16:34:00.642844 <30>[ 11.709744] systemd[1]: Reached target swap.target - Swaps.
10870 16:34:00.648851 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10871 16:34:00.669735 <30>[ 11.733765] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10872 16:34:00.679600 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10873 16:34:00.698059 <30>[ 11.762156] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10874 16:34:00.707982 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10875 16:34:00.728571 <30>[ 11.792928] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10876 16:34:00.738785 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10877 16:34:00.754360 <30>[ 11.818797] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10878 16:34:00.764757 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10879 16:34:00.781818 <30>[ 11.846037] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10880 16:34:00.788133 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10881 16:34:00.806740 <30>[ 11.871029] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10882 16:34:00.816585 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10883 16:34:00.835952 <30>[ 11.900121] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10884 16:34:00.845928 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10885 16:34:00.862351 <30>[ 11.926444] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10886 16:34:00.872896 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10887 16:34:00.921245 <30>[ 11.985635] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10888 16:34:00.928112 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10889 16:34:00.947316 <30>[ 12.011774] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10890 16:34:00.954288 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10891 16:34:00.976812 <30>[ 12.040751] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10892 16:34:00.983196 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10893 16:34:01.008586 <30>[ 12.065793] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10894 16:34:01.046112 <30>[ 12.110089] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10895 16:34:01.055772 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10896 16:34:01.078980 <30>[ 12.143075] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10897 16:34:01.085576 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10898 16:34:01.142361 <30>[ 12.206015] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10899 16:34:01.148708 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10900 16:34:01.172343 <30>[ 12.236476] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10901 16:34:01.185531 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 12.248919] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10902 16:34:01.188422 l Module drm...
10903 16:34:01.211020 <30>[ 12.275081] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10904 16:34:01.221047 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10905 16:34:01.242621 <30>[ 12.306868] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10906 16:34:01.249376 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10907 16:34:01.274701 <30>[ 12.338799] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10908 16:34:01.280906 Starting [0;1;39mmodpr<6>[ 12.348822] fuse: init (API version 7.37)
10909 16:34:01.287333 obe@loop.ser…e[0m - Load Kernel Module loop...
10910 16:34:01.309669 <30>[ 12.374162] systemd[1]: Starting systemd-journald.service - Journal Service...
10911 16:34:01.316112 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10912 16:34:01.381918 <30>[ 12.446377] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10913 16:34:01.388133 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10914 16:34:01.416206 <30>[ 12.477118] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10915 16:34:01.422789 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10916 16:34:01.444325 <30>[ 12.508305] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10917 16:34:01.454551 <3>[ 12.515571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 16:34:01.460704 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10919 16:34:01.484053 <3>[ 12.548518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 16:34:01.494364 <30>[ 12.548942] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10921 16:34:01.500836 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10922 16:34:01.525650 <30>[ 12.589453] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10923 16:34:01.532050 <3>[ 12.592384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 16:34:01.541907 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10925 16:34:01.562027 <3>[ 12.626793] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 16:34:01.572128 <30>[ 12.636473] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10927 16:34:01.579149 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10928 16:34:01.592402 <3>[ 12.656752] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 16:34:01.605023 <30>[ 12.669562] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10930 16:34:01.612507 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10931 16:34:01.622216 <3>[ 12.686125] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 16:34:01.631985 <30>[ 12.696531] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10933 16:34:01.641888 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10934 16:34:01.662804 <3>[ 12.727757] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 16:34:01.674064 <30>[ 12.738480] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10936 16:34:01.683733 <30>[ 12.746686] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10937 16:34:01.690091 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10938 16:34:01.709538 <30>[ 12.774087] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10939 16:34:01.716128 <30>[ 12.781939] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10940 16:34:01.725856 <3>[ 12.790175] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 16:34:01.735949 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10942 16:34:01.751505 <30>[ 12.818903] systemd[1]: modprobe@drm.service: Deactivated successfully.
10943 16:34:01.762096 <30>[ 12.826575] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10944 16:34:01.768731 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10945 16:34:01.793140 <30>[ 12.857883] systemd[1]: Started systemd-journald.service - Journal Service.
10946 16:34:01.799974 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10947 16:34:01.821389 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10948 16:34:01.843230 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10949 16:34:01.863682 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10950 16:34:01.882695 <4>[ 12.950575] power_supply_show_property: 2 callbacks suppressed
10951 16:34:01.892864 <3>[ 12.950588] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 16:34:01.908948 <4>[ 12.965487] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10953 16:34:01.915462 <3>[ 12.981119] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10954 16:34:01.922842 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10955 16:34:01.933460 <3>[ 12.998108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 16:34:01.946163 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10957 16:34:01.963364 <3>[ 13.028411] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 16:34:01.974577 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10959 16:34:01.993849 <3>[ 13.058348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 16:34:02.004789 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10961 16:34:02.026742 [[0;32m OK [<3>[ 13.088433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 16:34:02.033379 0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10963 16:34:02.053396 <3>[ 13.118032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 16:34:02.081317 Mountin<3>[ 13.147288] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 16:34:02.088208 g [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10966 16:34:02.117555 Mountin<3>[ 13.178934] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 16:34:02.120952 g [0;1;39msys-kernel-config…ernel Configuration File System...
10968 16:34:02.147517 Starting [0;1;39msyste<3>[ 13.210408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 16:34:02.150363 md-journal-f…h Journal to Persistent Storage...
10970 16:34:02.178517 <3>[ 13.243281] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 16:34:02.201361 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10972 16:34:02.224145 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10973 16:34:02.234237 <46>[ 13.298911] systemd-journald[309]: Received client request to flush runtime journal.
10974 16:34:02.254487 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10975 16:34:02.550528 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10976 16:34:02.568970 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10977 16:34:02.590932 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10978 16:34:02.999720 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10979 16:34:03.341990 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10980 16:34:03.389411 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10981 16:34:03.640456 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10982 16:34:03.734402 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10983 16:34:03.753647 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10984 16:34:03.769160 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10985 16:34:03.817348 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10986 16:34:03.839349 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10987 16:34:04.062946 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10988 16:34:04.134424 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10989 16:34:04.160550 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10990 16:34:04.199772 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10991 16:34:04.419930 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10992 16:34:04.446642 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10993 16:34:04.516387 <6>[ 15.584572] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10994 16:34:04.592912 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10995 16:34:04.613221 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10996 16:34:04.661290 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10997 16:34:04.717767 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10998 16:34:04.753279 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10999 16:34:04.773337 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11000 16:34:04.799307 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11001 16:34:04.821416 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11002 16:34:04.842273 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11003 16:34:04.865683 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11004 16:34:04.900802 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11005 16:34:04.924411 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11006 16:34:04.940639 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11007 16:34:04.956391 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11008 16:34:04.978437 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11009 16:34:04.998608 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11010 16:34:05.016575 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11011 16:34:05.045953 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11012 16:34:05.066665 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11013 16:34:05.084626 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11014 16:34:05.102170 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11015 16:34:05.120611 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11016 16:34:05.136865 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11017 16:34:05.170331 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11018 16:34:05.257840 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11019 16:34:05.349416 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11020 16:34:05.380856 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11021 16:34:05.403800 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11022 16:34:05.440783 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11023 16:34:05.483014 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11024 16:34:05.512599 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11025 16:34:05.528566 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11026 16:34:05.550736 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11027 16:34:05.714648 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11028 16:34:05.734683 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11029 16:34:05.757066 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11030 16:34:05.821817 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11031 16:34:05.858868 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11032 16:34:05.930740
11033 16:34:05.934131 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11034 16:34:05.934209
11035 16:34:05.937651 debian-bookworm-arm64 login: root (automatic login)
11036 16:34:05.937723
11037 16:34:06.189642 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11038 16:34:06.189790
11039 16:34:06.196202 The programs included with the Debian GNU/Linux system are free software;
11040 16:34:06.202711 the exact distribution terms for each program are described in the
11041 16:34:06.205543 individual files in /usr/share/doc/*/copyright.
11042 16:34:06.205636
11043 16:34:06.212273 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11044 16:34:06.215733 permitted by applicable law.
11045 16:34:07.115861 Matched prompt #10: / #
11047 16:34:07.116202 Setting prompt string to ['/ #']
11048 16:34:07.116321 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11050 16:34:07.116624 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11051 16:34:07.116733 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11052 16:34:07.116827 Setting prompt string to ['/ #']
11053 16:34:07.116912 Forcing a shell prompt, looking for ['/ #']
11055 16:34:07.167114 / #
11056 16:34:07.167314 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11057 16:34:07.167389 Waiting using forced prompt support (timeout 00:02:30)
11058 16:34:07.172678
11059 16:34:07.172949 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11060 16:34:07.173044 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11062 16:34:07.273362 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h'
11063 16:34:07.278145 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396140/extract-nfsrootfs-rjgtcj2h'
11065 16:34:07.378644 / # export NFS_SERVER_IP='192.168.201.1'
11066 16:34:07.384264 export NFS_SERVER_IP='192.168.201.1'
11067 16:34:07.384549 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11068 16:34:07.384643 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11069 16:34:07.384731 end: 2 depthcharge-action (duration 00:01:23) [common]
11070 16:34:07.384819 start: 3 lava-test-retry (timeout 00:07:57) [common]
11071 16:34:07.384904 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
11072 16:34:07.384971 Using namespace: common
11074 16:34:07.485260 / # #
11075 16:34:07.485469 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11076 16:34:07.490459 #
11077 16:34:07.490722 Using /lava-14396140
11079 16:34:07.591021 / # export SHELL=/bin/bash
11080 16:34:07.596398 export SHELL=/bin/bash
11082 16:34:07.696906 / # . /lava-14396140/environment
11083 16:34:07.702209 . /lava-14396140/environment
11085 16:34:07.807785 / # /lava-14396140/bin/lava-test-runner /lava-14396140/0
11086 16:34:07.807976 Test shell timeout: 10s (minimum of the action and connection timeout)
11087 16:34:07.813140 /lava-14396140/bin/lava-test-runner /lava-14396140/0
11088 16:34:08.016579 + export TESTRUN_ID=0_timesync-off
11089 16:34:08.020029 + TESTRUN_ID=0_timesync-off
11090 16:34:08.023226 + cd /lava-14396140/0/tests/0_timesync-off
11091 16:34:08.026387 ++ cat uuid
11092 16:34:08.026488 + UUID=14396140_1.6.2.3.1
11093 16:34:08.029826 + set +x
11094 16:34:08.033393 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14396140_1.6.2.3.1>
11095 16:34:08.033674 Received signal: <STARTRUN> 0_timesync-off 14396140_1.6.2.3.1
11096 16:34:08.033743 Starting test lava.0_timesync-off (14396140_1.6.2.3.1)
11097 16:34:08.033866 Skipping test definition patterns.
11098 16:34:08.036241 + systemctl stop systemd-timesyncd
11099 16:34:08.098556 + set +x
11100 16:34:08.102028 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14396140_1.6.2.3.1>
11101 16:34:08.102297 Received signal: <ENDRUN> 0_timesync-off 14396140_1.6.2.3.1
11102 16:34:08.102388 Ending use of test pattern.
11103 16:34:08.102447 Ending test lava.0_timesync-off (14396140_1.6.2.3.1), duration 0.07
11105 16:34:08.148083 + export TESTRUN_ID=1_kselftest-rtc
11106 16:34:08.150794 + TESTRUN_ID=1_kselftest-rtc
11107 16:34:08.154400 + cd /lava-14396140/0/tests/1_kselftest-rtc
11108 16:34:08.157362 ++ cat uuid
11109 16:34:08.157481 + UUID=14396140_1.6.2.3.5
11110 16:34:08.160823 + set +x
11111 16:34:08.164388 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14396140_1.6.2.3.5>
11112 16:34:08.164669 Received signal: <STARTRUN> 1_kselftest-rtc 14396140_1.6.2.3.5
11113 16:34:08.164769 Starting test lava.1_kselftest-rtc (14396140_1.6.2.3.5)
11114 16:34:08.164879 Skipping test definition patterns.
11115 16:34:08.167315 + cd ./automated/linux/kselftest/
11116 16:34:08.197256 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11117 16:34:08.212202 INFO: install_deps skipped
11118 16:34:08.695168 --2024-06-17 16:34:08-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11119 16:34:08.707474 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11120 16:34:08.839667 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11121 16:34:08.970825 HTTP request sent, awaiting response... 200 OK
11122 16:34:08.974513 Length: 1650228 (1.6M) [application/octet-stream]
11123 16:34:08.977477 Saving to: 'kselftest_armhf.tar.gz'
11124 16:34:08.977591
11125 16:34:08.977656
11126 16:34:09.234239 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11127 16:34:09.496062 kselftest_armhf.tar 2%[ ] 46.39K 177KB/s
11128 16:34:09.933440 kselftest_armhf.tar 13%[=> ] 214.67K 409KB/s
11129 16:34:09.939742 kselftest_armhf.tar 45%[========> ] 740.70K 770KB/s
11130 16:34:09.946942 kselftest_armhf.tar 100%[===================>] 1.57M 1.62MB/s in 1.0s
11131 16:34:09.947068
11132 16:34:10.093620 2024-06-17 16:34:09 (1.62 MB/s) - 'kselftest_armhf.tar.gz' saved [1650228/1650228]
11133 16:34:10.093734
11134 16:34:14.073614 skiplist:
11135 16:34:14.077137 ========================================
11136 16:34:14.080117 ========================================
11137 16:34:14.118839 rtc:rtctest
11138 16:34:14.137023 ============== Tests to run ===============
11139 16:34:14.137166 rtc:rtctest
11140 16:34:14.139879 ===========End Tests to run ===============
11141 16:34:14.143392 shardfile-rtc pass
11142 16:34:14.267951 <12>[ 25.337088] kselftest: Running tests in rtc
11143 16:34:14.276165 TAP version 13
11144 16:34:14.288324 1..1
11145 16:34:14.313315 # selftests: rtc: rtctest
11146 16:34:14.756382 # TAP version 13
11147 16:34:14.756509 # 1..8
11148 16:34:14.759350 # # Starting 8 tests from 2 test cases.
11149 16:34:14.762723 # # RUN rtc.date_read ...
11150 16:34:14.769141 # # rtctest.c:49:date_read:Current RTC date/time is 17/06/2024 16:34:14.
11151 16:34:14.772636 # # OK rtc.date_read
11152 16:34:14.776125 # ok 1 rtc.date_read
11153 16:34:14.779513 # # RUN rtc.date_read_loop ...
11154 16:34:14.788899 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11155 16:34:26.890754 <6>[ 37.965280] vpu: disabling
11156 16:34:26.894248 <6>[ 37.968581] vproc2: disabling
11157 16:34:26.897785 <6>[ 37.971992] vproc1: disabling
11158 16:34:26.901461 <6>[ 37.975412] vaud18: disabling
11159 16:34:26.907749 <6>[ 37.979013] vsram_others: disabling
11160 16:34:26.911213 <6>[ 37.983223] va09: disabling
11161 16:34:26.914613 <6>[ 37.986484] vsram_md: disabling
11162 16:34:26.917877 <6>[ 37.990149] Vgpu: disabling
11163 16:34:44.971661 # # rtctest.c:115:date_read_loop:Performed 2645 RTC time reads.
11164 16:34:44.974617 # # OK rtc.date_read_loop
11165 16:34:44.978313 # ok 2 rtc.date_read_loop
11166 16:34:44.981285 # # RUN rtc.uie_read ...
11167 16:34:47.956551 # # OK rtc.uie_read
11168 16:34:47.959668 # ok 3 rtc.uie_read
11169 16:34:47.962716 # # RUN rtc.uie_select ...
11170 16:34:50.955881 # # OK rtc.uie_select
11171 16:34:50.959446 # ok 4 rtc.uie_select
11172 16:34:50.962959 # # RUN rtc.alarm_alm_set ...
11173 16:34:50.969179 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 16:34:54.
11174 16:34:50.972528 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11175 16:34:50.979231 # # alarm_alm_set: Test terminated by assertion
11176 16:34:50.982527 # # FAIL rtc.alarm_alm_set
11177 16:34:50.982611 # not ok 5 rtc.alarm_alm_set
11178 16:34:50.988925 # # RUN rtc.alarm_wkalm_set ...
11179 16:34:50.995309 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 17/06/2024 16:34:54.
11180 16:34:53.958466 # # OK rtc.alarm_wkalm_set
11181 16:34:53.958608 # ok 6 rtc.alarm_wkalm_set
11182 16:34:53.965362 # # RUN rtc.alarm_alm_set_minute ...
11183 16:34:53.968228 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 16:35:00.
11184 16:34:53.975439 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11185 16:34:53.981826 # # alarm_alm_set_minute: Test terminated by assertion
11186 16:34:53.985392 # # FAIL rtc.alarm_alm_set_minute
11187 16:34:53.988228 # not ok 7 rtc.alarm_alm_set_minute
11188 16:34:53.991670 # # RUN rtc.alarm_wkalm_set_minute ...
11189 16:34:53.998383 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 17/06/2024 16:35:00.
11190 16:34:59.958033 # # OK rtc.alarm_wkalm_set_minute
11191 16:34:59.960859 # ok 8 rtc.alarm_wkalm_set_minute
11192 16:34:59.964491 # # FAILED: 6 / 8 tests passed.
11193 16:34:59.968127 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11194 16:34:59.970810 not ok 1 selftests: rtc: rtctest # exit=1
11195 16:35:01.329349 rtc_rtctest_rtc_date_read pass
11196 16:35:01.332816 rtc_rtctest_rtc_date_read_loop pass
11197 16:35:01.335339 rtc_rtctest_rtc_uie_read pass
11198 16:35:01.339064 rtc_rtctest_rtc_uie_select pass
11199 16:35:01.342548 rtc_rtctest_rtc_alarm_alm_set fail
11200 16:35:01.345956 rtc_rtctest_rtc_alarm_wkalm_set pass
11201 16:35:01.349272 rtc_rtctest_rtc_alarm_alm_set_minute fail
11202 16:35:01.352705 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11203 16:35:01.355872 rtc_rtctest fail
11204 16:35:01.404551 + ../../utils/send-to-lava.sh ./output/result.txt
11205 16:35:01.454274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11206 16:35:01.454567 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11208 16:35:01.490878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11209 16:35:01.491190 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11211 16:35:01.525945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11212 16:35:01.526219 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11214 16:35:01.550088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11215 16:35:01.550345 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11217 16:35:01.582219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11218 16:35:01.582494 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11220 16:35:01.621262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11221 16:35:01.621569 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11223 16:35:01.649382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11224 16:35:01.649691 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11226 16:35:01.680551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11227 16:35:01.680838 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11229 16:35:01.710461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11230 16:35:01.710767 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11232 16:35:01.738710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11233 16:35:01.738801 + set +x
11234 16:35:01.739041 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11236 16:35:01.745529 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14396140_1.6.2.3.5>
11237 16:35:01.745610 <LAVA_TEST_RUNNER EXIT>
11238 16:35:01.745832 Received signal: <ENDRUN> 1_kselftest-rtc 14396140_1.6.2.3.5
11239 16:35:01.745899 Ending use of test pattern.
11240 16:35:01.745954 Ending test lava.1_kselftest-rtc (14396140_1.6.2.3.5), duration 53.58
11242 16:35:01.746151 ok: lava_test_shell seems to have completed
11243 16:35:01.746272 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11244 16:35:01.746362 end: 3.1 lava-test-shell (duration 00:00:54) [common]
11245 16:35:01.746438 end: 3 lava-test-retry (duration 00:00:54) [common]
11246 16:35:01.746520 start: 4 finalize (timeout 00:07:03) [common]
11247 16:35:01.746601 start: 4.1 power-off (timeout 00:00:30) [common]
11248 16:35:01.746734 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11249 16:35:03.827213 >> Command sent successfully.
11250 16:35:03.830780 Returned 0 in 2 seconds
11251 16:35:03.931143 end: 4.1 power-off (duration 00:00:02) [common]
11253 16:35:03.931482 start: 4.2 read-feedback (timeout 00:07:00) [common]
11254 16:35:03.931753 Listened to connection for namespace 'common' for up to 1s
11255 16:35:03.932056 Listened to connection for namespace 'common' for up to 1s
11256 16:35:04.932672 Finalising connection for namespace 'common'
11257 16:35:04.932831 Disconnecting from shell: Finalise
11258 16:35:04.932908 / #
11259 16:35:05.033153 end: 4.2 read-feedback (duration 00:00:01) [common]
11260 16:35:05.033335 end: 4 finalize (duration 00:00:03) [common]
11261 16:35:05.033484 Cleaning after the job
11262 16:35:05.033636 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/ramdisk
11263 16:35:05.036179 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/kernel
11264 16:35:05.048278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/dtb
11265 16:35:05.048528 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/nfsrootfs
11266 16:35:05.116673 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396140/tftp-deploy-98og2484/modules
11267 16:35:05.122637 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396140
11268 16:35:05.762116 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396140
11269 16:35:05.762305 Job finished correctly