Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 16:33:15.927668 lava-dispatcher, installed at version: 2024.03
2 16:33:15.927923 start: 0 validate
3 16:33:15.928095 Start time: 2024-06-17 16:33:15.928086+00:00 (UTC)
4 16:33:15.928276 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:33:15.928470 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:33:16.186469 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:33:16.186646 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:33:16.442192 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:33:16.442423 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:33:16.708411 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:33:16.708562 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:33:16.967153 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:33:16.967341 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:33:17.232239 validate duration: 1.30
16 16:33:17.232525 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:33:17.232630 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:33:17.232716 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:33:17.232839 Not decompressing ramdisk as can be used compressed.
20 16:33:17.232922 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:33:17.232985 saving as /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/ramdisk/initrd.cpio.gz
22 16:33:17.233049 total size: 5628169 (5 MB)
23 16:33:17.234125 progress 0 % (0 MB)
24 16:33:17.235733 progress 5 % (0 MB)
25 16:33:17.237338 progress 10 % (0 MB)
26 16:33:17.238799 progress 15 % (0 MB)
27 16:33:17.240392 progress 20 % (1 MB)
28 16:33:17.241867 progress 25 % (1 MB)
29 16:33:17.243444 progress 30 % (1 MB)
30 16:33:17.245046 progress 35 % (1 MB)
31 16:33:17.246450 progress 40 % (2 MB)
32 16:33:17.247997 progress 45 % (2 MB)
33 16:33:17.249399 progress 50 % (2 MB)
34 16:33:17.250956 progress 55 % (2 MB)
35 16:33:17.252519 progress 60 % (3 MB)
36 16:33:17.253916 progress 65 % (3 MB)
37 16:33:17.255535 progress 70 % (3 MB)
38 16:33:17.257024 progress 75 % (4 MB)
39 16:33:17.258591 progress 80 % (4 MB)
40 16:33:17.259974 progress 85 % (4 MB)
41 16:33:17.261580 progress 90 % (4 MB)
42 16:33:17.263135 progress 95 % (5 MB)
43 16:33:17.264561 progress 100 % (5 MB)
44 16:33:17.264826 5 MB downloaded in 0.03 s (168.93 MB/s)
45 16:33:17.265043 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:33:17.265378 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:33:17.265466 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:33:17.265550 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:33:17.265689 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:33:17.265759 saving as /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/kernel/Image
52 16:33:17.265821 total size: 54813184 (52 MB)
53 16:33:17.265882 No compression specified
54 16:33:17.266993 progress 0 % (0 MB)
55 16:33:17.281051 progress 5 % (2 MB)
56 16:33:17.295199 progress 10 % (5 MB)
57 16:33:17.309386 progress 15 % (7 MB)
58 16:33:17.323840 progress 20 % (10 MB)
59 16:33:17.338290 progress 25 % (13 MB)
60 16:33:17.352559 progress 30 % (15 MB)
61 16:33:17.367140 progress 35 % (18 MB)
62 16:33:17.381693 progress 40 % (20 MB)
63 16:33:17.395987 progress 45 % (23 MB)
64 16:33:17.410500 progress 50 % (26 MB)
65 16:33:17.425050 progress 55 % (28 MB)
66 16:33:17.439310 progress 60 % (31 MB)
67 16:33:17.453826 progress 65 % (34 MB)
68 16:33:17.468294 progress 70 % (36 MB)
69 16:33:17.482662 progress 75 % (39 MB)
70 16:33:17.496835 progress 80 % (41 MB)
71 16:33:17.510878 progress 85 % (44 MB)
72 16:33:17.525053 progress 90 % (47 MB)
73 16:33:17.539114 progress 95 % (49 MB)
74 16:33:17.552880 progress 100 % (52 MB)
75 16:33:17.553140 52 MB downloaded in 0.29 s (181.94 MB/s)
76 16:33:17.553307 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:33:17.553546 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:33:17.553632 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:33:17.553716 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:33:17.553858 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:33:17.553933 saving as /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/dtb/mt8192-asurada-spherion-r0.dtb
83 16:33:17.553994 total size: 47258 (0 MB)
84 16:33:17.554054 No compression specified
85 16:33:17.555189 progress 69 % (0 MB)
86 16:33:17.555468 progress 100 % (0 MB)
87 16:33:17.555625 0 MB downloaded in 0.00 s (27.68 MB/s)
88 16:33:17.555747 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:33:17.555971 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:33:17.556056 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:33:17.556139 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:33:17.556257 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:33:17.556326 saving as /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/nfsrootfs/full.rootfs.tar
95 16:33:17.556386 total size: 120894716 (115 MB)
96 16:33:17.556448 Using unxz to decompress xz
97 16:33:17.561255 progress 0 % (0 MB)
98 16:33:17.939117 progress 5 % (5 MB)
99 16:33:18.312977 progress 10 % (11 MB)
100 16:33:18.670120 progress 15 % (17 MB)
101 16:33:19.008556 progress 20 % (23 MB)
102 16:33:19.313138 progress 25 % (28 MB)
103 16:33:19.699843 progress 30 % (34 MB)
104 16:33:20.062342 progress 35 % (40 MB)
105 16:33:20.237709 progress 40 % (46 MB)
106 16:33:20.428753 progress 45 % (51 MB)
107 16:33:20.773389 progress 50 % (57 MB)
108 16:33:21.195794 progress 55 % (63 MB)
109 16:33:21.545559 progress 60 % (69 MB)
110 16:33:21.887251 progress 65 % (74 MB)
111 16:33:22.258072 progress 70 % (80 MB)
112 16:33:22.627727 progress 75 % (86 MB)
113 16:33:22.986863 progress 80 % (92 MB)
114 16:33:23.340056 progress 85 % (98 MB)
115 16:33:23.704746 progress 90 % (103 MB)
116 16:33:24.044604 progress 95 % (109 MB)
117 16:33:24.408901 progress 100 % (115 MB)
118 16:33:24.414453 115 MB downloaded in 6.86 s (16.81 MB/s)
119 16:33:24.414720 end: 1.4.1 http-download (duration 00:00:07) [common]
121 16:33:24.414996 end: 1.4 download-retry (duration 00:00:07) [common]
122 16:33:24.415090 start: 1.5 download-retry (timeout 00:09:53) [common]
123 16:33:24.415177 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 16:33:24.415335 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:33:24.415409 saving as /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/modules/modules.tar
126 16:33:24.415470 total size: 8628772 (8 MB)
127 16:33:24.415534 Using unxz to decompress xz
128 16:33:24.419532 progress 0 % (0 MB)
129 16:33:24.440884 progress 5 % (0 MB)
130 16:33:24.465738 progress 10 % (0 MB)
131 16:33:24.490176 progress 15 % (1 MB)
132 16:33:24.515172 progress 20 % (1 MB)
133 16:33:24.540984 progress 25 % (2 MB)
134 16:33:24.565956 progress 30 % (2 MB)
135 16:33:24.594295 progress 35 % (2 MB)
136 16:33:24.620597 progress 40 % (3 MB)
137 16:33:24.646043 progress 45 % (3 MB)
138 16:33:24.673079 progress 50 % (4 MB)
139 16:33:24.698451 progress 55 % (4 MB)
140 16:33:24.725084 progress 60 % (4 MB)
141 16:33:24.754100 progress 65 % (5 MB)
142 16:33:24.780971 progress 70 % (5 MB)
143 16:33:24.804821 progress 75 % (6 MB)
144 16:33:24.828871 progress 80 % (6 MB)
145 16:33:24.856835 progress 85 % (7 MB)
146 16:33:24.885009 progress 90 % (7 MB)
147 16:33:24.910501 progress 95 % (7 MB)
148 16:33:24.936080 progress 100 % (8 MB)
149 16:33:24.941336 8 MB downloaded in 0.53 s (15.65 MB/s)
150 16:33:24.941603 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:33:24.941885 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:33:24.941981 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 16:33:24.942076 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 16:33:28.551925 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc
156 16:33:28.552112 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 16:33:28.552210 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 16:33:28.552389 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet
159 16:33:28.552521 makedir: /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin
160 16:33:28.552622 makedir: /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/tests
161 16:33:28.552720 makedir: /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/results
162 16:33:28.552824 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-add-keys
163 16:33:28.552967 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-add-sources
164 16:33:28.553098 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-background-process-start
165 16:33:28.553232 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-background-process-stop
166 16:33:28.553403 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-common-functions
167 16:33:28.553528 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-echo-ipv4
168 16:33:28.553656 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-install-packages
169 16:33:28.553782 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-installed-packages
170 16:33:28.553905 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-os-build
171 16:33:28.554029 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-probe-channel
172 16:33:28.554158 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-probe-ip
173 16:33:28.554282 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-target-ip
174 16:33:28.554404 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-target-mac
175 16:33:28.554525 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-target-storage
176 16:33:28.554664 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-case
177 16:33:28.554787 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-event
178 16:33:28.554934 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-feedback
179 16:33:28.555097 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-raise
180 16:33:28.555227 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-reference
181 16:33:28.555352 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-runner
182 16:33:28.555476 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-set
183 16:33:28.555644 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-test-shell
184 16:33:28.555769 Updating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-add-keys (debian)
185 16:33:28.555923 Updating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-add-sources (debian)
186 16:33:28.556062 Updating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-install-packages (debian)
187 16:33:28.556201 Updating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-installed-packages (debian)
188 16:33:28.556338 Updating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/bin/lava-os-build (debian)
189 16:33:28.556456 Creating /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/environment
190 16:33:28.556553 LAVA metadata
191 16:33:28.556618 - LAVA_JOB_ID=14396153
192 16:33:28.556678 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:33:28.556776 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 16:33:28.556841 skipped lava-vland-overlay
195 16:33:28.556914 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:33:28.556992 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 16:33:28.557051 skipped lava-multinode-overlay
198 16:33:28.557121 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:33:28.557199 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 16:33:28.557421 Loading test definitions
201 16:33:28.557517 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 16:33:28.557587 Using /lava-14396153 at stage 0
203 16:33:28.557876 uuid=14396153_1.6.2.3.1 testdef=None
204 16:33:28.558005 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:33:28.558123 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 16:33:28.558604 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:33:28.558870 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 16:33:28.559425 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:33:28.559650 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 16:33:28.560191 runner path: /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/0/tests/0_timesync-off test_uuid 14396153_1.6.2.3.1
213 16:33:28.560377 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:33:28.560602 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 16:33:28.560673 Using /lava-14396153 at stage 0
217 16:33:28.560767 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:33:28.560858 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/0/tests/1_kselftest-tpm2'
219 16:33:32.339146 Running '/usr/bin/git checkout kernelci.org
220 16:33:32.495273 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 16:33:32.496029 uuid=14396153_1.6.2.3.5 testdef=None
222 16:33:32.496192 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 16:33:32.496479 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 16:33:32.497490 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:33:32.497743 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 16:33:32.499431 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:33:32.499833 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 16:33:32.501154 runner path: /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/0/tests/1_kselftest-tpm2 test_uuid 14396153_1.6.2.3.5
232 16:33:32.501300 BOARD='mt8192-asurada-spherion-r0'
233 16:33:32.501401 BRANCH='cip-gitlab'
234 16:33:32.501490 SKIPFILE='/dev/null'
235 16:33:32.501575 SKIP_INSTALL='True'
236 16:33:32.501668 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:33:32.501755 TST_CASENAME=''
238 16:33:32.501841 TST_CMDFILES='tpm2'
239 16:33:32.502031 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:33:32.502298 Creating lava-test-runner.conf files
242 16:33:32.502363 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396153/lava-overlay-mfda4tet/lava-14396153/0 for stage 0
243 16:33:32.502464 - 0_timesync-off
244 16:33:32.502534 - 1_kselftest-tpm2
245 16:33:32.502629 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 16:33:32.502732 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 16:33:40.420920 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 16:33:40.421092 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 16:33:40.421192 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:33:40.421346 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 16:33:40.421448 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 16:33:40.597976 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:33:40.598377 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 16:33:40.598499 extracting modules file /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc
255 16:33:40.856721 extracting modules file /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396153/extract-overlay-ramdisk-r89lw5q7/ramdisk
256 16:33:41.096788 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:33:41.097010 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 16:33:41.097145 [common] Applying overlay to NFS
259 16:33:41.097266 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396153/compress-overlay-mj500tis/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc
260 16:33:42.257813 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:33:42.257997 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 16:33:42.258097 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:33:42.258198 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 16:33:42.258283 Building ramdisk /var/lib/lava/dispatcher/tmp/14396153/extract-overlay-ramdisk-r89lw5q7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396153/extract-overlay-ramdisk-r89lw5q7/ramdisk
265 16:33:42.582835 >> 130466 blocks
266 16:33:44.709838 rename /var/lib/lava/dispatcher/tmp/14396153/extract-overlay-ramdisk-r89lw5q7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/ramdisk/ramdisk.cpio.gz
267 16:33:44.710306 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 16:33:44.710430 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 16:33:44.710546 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 16:33:44.710661 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/kernel/Image']
271 16:33:59.431949 Returned 0 in 14 seconds
272 16:33:59.532854 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/kernel/image.itb
273 16:33:59.905401 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:33:59.905770 output: Created: Mon Jun 17 17:33:59 2024
275 16:33:59.905847 output: Image 0 (kernel-1)
276 16:33:59.905912 output: Description:
277 16:33:59.905976 output: Created: Mon Jun 17 17:33:59 2024
278 16:33:59.906036 output: Type: Kernel Image
279 16:33:59.906095 output: Compression: lzma compressed
280 16:33:59.906152 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
281 16:33:59.906211 output: Architecture: AArch64
282 16:33:59.906271 output: OS: Linux
283 16:33:59.906354 output: Load Address: 0x00000000
284 16:33:59.906415 output: Entry Point: 0x00000000
285 16:33:59.906537 output: Hash algo: crc32
286 16:33:59.906614 output: Hash value: 106ffd6f
287 16:33:59.906715 output: Image 1 (fdt-1)
288 16:33:59.906773 output: Description: mt8192-asurada-spherion-r0
289 16:33:59.906832 output: Created: Mon Jun 17 17:33:59 2024
290 16:33:59.906908 output: Type: Flat Device Tree
291 16:33:59.906963 output: Compression: uncompressed
292 16:33:59.907015 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 16:33:59.907068 output: Architecture: AArch64
294 16:33:59.907119 output: Hash algo: crc32
295 16:33:59.907171 output: Hash value: 0f8e4d2e
296 16:33:59.907223 output: Image 2 (ramdisk-1)
297 16:33:59.907275 output: Description: unavailable
298 16:33:59.907327 output: Created: Mon Jun 17 17:33:59 2024
299 16:33:59.907379 output: Type: RAMDisk Image
300 16:33:59.907430 output: Compression: Unknown Compression
301 16:33:59.907482 output: Data Size: 18731582 Bytes = 18292.56 KiB = 17.86 MiB
302 16:33:59.907534 output: Architecture: AArch64
303 16:33:59.907585 output: OS: Linux
304 16:33:59.907637 output: Load Address: unavailable
305 16:33:59.907688 output: Entry Point: unavailable
306 16:33:59.907739 output: Hash algo: crc32
307 16:33:59.907790 output: Hash value: 21cb97ba
308 16:33:59.907842 output: Default Configuration: 'conf-1'
309 16:33:59.907893 output: Configuration 0 (conf-1)
310 16:33:59.907944 output: Description: mt8192-asurada-spherion-r0
311 16:33:59.907995 output: Kernel: kernel-1
312 16:33:59.908046 output: Init Ramdisk: ramdisk-1
313 16:33:59.908098 output: FDT: fdt-1
314 16:33:59.908149 output: Loadables: kernel-1
315 16:33:59.908200 output:
316 16:33:59.908406 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 16:33:59.908502 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 16:33:59.908604 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 16:33:59.908696 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 16:33:59.908771 No LXC device requested
321 16:33:59.908848 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:33:59.908935 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 16:33:59.909010 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:33:59.909079 Checking files for TFTP limit of 4294967296 bytes.
325 16:33:59.909619 end: 1 tftp-deploy (duration 00:00:43) [common]
326 16:33:59.909726 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:33:59.909815 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:33:59.909938 substitutions:
329 16:33:59.910007 - {DTB}: 14396153/tftp-deploy-iw5mv4ot/dtb/mt8192-asurada-spherion-r0.dtb
330 16:33:59.910072 - {INITRD}: 14396153/tftp-deploy-iw5mv4ot/ramdisk/ramdisk.cpio.gz
331 16:33:59.910130 - {KERNEL}: 14396153/tftp-deploy-iw5mv4ot/kernel/Image
332 16:33:59.910186 - {LAVA_MAC}: None
333 16:33:59.910240 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc
334 16:33:59.910295 - {NFS_SERVER_IP}: 192.168.201.1
335 16:33:59.910348 - {PRESEED_CONFIG}: None
336 16:33:59.910401 - {PRESEED_LOCAL}: None
337 16:33:59.910454 - {RAMDISK}: 14396153/tftp-deploy-iw5mv4ot/ramdisk/ramdisk.cpio.gz
338 16:33:59.910508 - {ROOT_PART}: None
339 16:33:59.910561 - {ROOT}: None
340 16:33:59.910615 - {SERVER_IP}: 192.168.201.1
341 16:33:59.910667 - {TEE}: None
342 16:33:59.910722 Parsed boot commands:
343 16:33:59.910774 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:33:59.910950 Parsed boot commands: tftpboot 192.168.201.1 14396153/tftp-deploy-iw5mv4ot/kernel/image.itb 14396153/tftp-deploy-iw5mv4ot/kernel/cmdline
345 16:33:59.911037 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:33:59.911132 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:33:59.911223 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:33:59.911308 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:33:59.911384 Not connected, no need to disconnect.
350 16:33:59.911457 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:33:59.911537 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:33:59.911601 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 16:33:59.915307 Setting prompt string to ['lava-test: # ']
354 16:33:59.915677 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:33:59.915786 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:33:59.915888 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:33:59.915977 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:33:59.916190 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 16:34:13.910404 Returned 0 in 13 seconds
360 16:34:14.011257 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 16:34:14.012201 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 16:34:14.012498 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 16:34:14.012749 Setting prompt string to 'Starting depthcharge on Spherion...'
365 16:34:14.013014 Changing prompt to 'Starting depthcharge on Spherion...'
366 16:34:14.013220 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 16:34:14.015130 [Enter `^Ec?' for help]
368 16:34:14.015622
369 16:34:14.015929
370 16:34:14.016119 F0: 102B 0000
371 16:34:14.016300
372 16:34:14.016477 F3: 1001 0000 [0200]
373 16:34:14.016653
374 16:34:14.016823 F3: 1001 0000
375 16:34:14.016991
376 16:34:14.017151 F7: 102D 0000
377 16:34:14.017339
378 16:34:14.017504 F1: 0000 0000
379 16:34:14.017664
380 16:34:14.017821 V0: 0000 0000 [0001]
381 16:34:14.017979
382 16:34:14.018135 00: 0007 8000
383 16:34:14.018304
384 16:34:14.018462 01: 0000 0000
385 16:34:14.018622
386 16:34:14.018884 BP: 0C00 0209 [0000]
387 16:34:14.019109
388 16:34:14.019273 G0: 1182 0000
389 16:34:14.019432
390 16:34:14.019590 EC: 0000 0021 [4000]
391 16:34:14.019746
392 16:34:14.019903 S7: 0000 0000 [0000]
393 16:34:14.020059
394 16:34:14.020214 CC: 0000 0000 [0001]
395 16:34:14.020373
396 16:34:14.020569 T0: 0000 0040 [010F]
397 16:34:14.020731
398 16:34:14.020889 Jump to BL
399 16:34:14.021048
400 16:34:14.021203
401 16:34:14.021387
402 16:34:14.021546 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 16:34:14.021713 ARM64: Exception handlers installed.
404 16:34:14.021871 ARM64: Testing exception
405 16:34:14.022028 ARM64: Done test exception
406 16:34:14.022186 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 16:34:14.022344 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 16:34:14.022504 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 16:34:14.022699 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 16:34:14.022862 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 16:34:14.023020 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 16:34:14.023176 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 16:34:14.023336 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 16:34:14.023494 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 16:34:14.023652 WDT: Last reset was cold boot
416 16:34:14.023807 SPI1(PAD0) initialized at 2873684 Hz
417 16:34:14.023964 SPI5(PAD0) initialized at 992727 Hz
418 16:34:14.024119 VBOOT: Loading verstage.
419 16:34:14.024275 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 16:34:14.024432 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 16:34:14.024590 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 16:34:14.024747 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 16:34:14.024904 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 16:34:14.025065 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 16:34:14.025225 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 16:34:14.025417
427 16:34:14.025573
428 16:34:14.025730 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 16:34:14.025888 ARM64: Exception handlers installed.
430 16:34:14.026042 ARM64: Testing exception
431 16:34:14.026197 ARM64: Done test exception
432 16:34:14.026354 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 16:34:14.026515 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 16:34:14.026674 Probing TPM: . done!
435 16:34:14.026829 TPM ready after 0 ms
436 16:34:14.026987 Connected to device vid:did:rid of 1ae0:0028:00
437 16:34:14.027143 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 16:34:14.027302 Initialized TPM device CR50 revision 0
439 16:34:14.027458 tlcl_send_startup: Startup return code is 0
440 16:34:14.027613 TPM: setup succeeded
441 16:34:14.027768 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 16:34:14.027925 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 16:34:14.028081 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 16:34:14.028239 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 16:34:14.028395 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 16:34:14.028553 in-header: 03 07 00 00 08 00 00 00
447 16:34:14.028712 in-data: aa e4 47 04 13 02 00 00
448 16:34:14.028871 Chrome EC: UHEPI supported
449 16:34:14.029028 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 16:34:14.029185 in-header: 03 a9 00 00 08 00 00 00
451 16:34:14.029372 in-data: 84 60 60 08 00 00 00 00
452 16:34:14.029529 Phase 1
453 16:34:14.029683 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 16:34:14.029839 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 16:34:14.029997 VB2:vb2_check_recovery() Recovery was requested manually
456 16:34:14.030153 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 16:34:14.030308 Recovery requested (1009000e)
458 16:34:14.030463 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 16:34:14.030620 tlcl_extend: response is 0
460 16:34:14.030774 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 16:34:14.030931 tlcl_extend: response is 0
462 16:34:14.031087 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 16:34:14.031245 read SPI 0x210d4 0x2173b: 15142 us, 9048 KB/s, 72.384 Mbps
464 16:34:14.031403 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 16:34:14.031559
466 16:34:14.031716
467 16:34:14.031871 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 16:34:14.032032 ARM64: Exception handlers installed.
469 16:34:14.032187 ARM64: Testing exception
470 16:34:14.032341 ARM64: Done test exception
471 16:34:14.032497 pmic_efuse_setting: Set efuses in 11 msecs
472 16:34:14.032651 pmwrap_interface_init: Select PMIF_VLD_RDY
473 16:34:14.032804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 16:34:14.032928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 16:34:14.033330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 16:34:14.033477 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 16:34:14.033605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 16:34:14.033729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 16:34:14.033853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 16:34:14.033976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 16:34:14.034100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 16:34:14.034223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 16:34:14.034396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 16:34:14.034525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 16:34:14.034648 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 16:34:14.034773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 16:34:14.034898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 16:34:14.035021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 16:34:14.035145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 16:34:14.035269 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 16:34:14.035392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 16:34:14.035516 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 16:34:14.035641 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 16:34:14.035766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 16:34:14.035893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 16:34:14.036019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 16:34:14.036144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 16:34:14.036362 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 16:34:14.036549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 16:34:14.036697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 16:34:14.036912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 16:34:14.037071 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 16:34:14.037200 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 16:34:14.037351 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 16:34:14.037592 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 16:34:14.037804 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 16:34:14.037994 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 16:34:14.038170 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 16:34:14.038303 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 16:34:14.038409 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 16:34:14.038514 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 16:34:14.038617 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 16:34:14.038721 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 16:34:14.038824 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 16:34:14.038927 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 16:34:14.039029 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 16:34:14.039131 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 16:34:14.039232 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 16:34:14.039334 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 16:34:14.039436 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 16:34:14.039537 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 16:34:14.039640 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 16:34:14.039742 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 16:34:14.039844 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 16:34:14.039948 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 16:34:14.040053 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 16:34:14.040156 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 16:34:14.040260 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 16:34:14.040363 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 16:34:14.040465 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 16:34:14.040566 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 16:34:14.040668 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
533 16:34:14.040770 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 16:34:14.040873 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 16:34:14.040974 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 16:34:14.041075 [RTC]rtc_get_frequency_meter,154: input=15, output=853
537 16:34:14.041177 [RTC]rtc_get_frequency_meter,154: input=7, output=725
538 16:34:14.041296 [RTC]rtc_get_frequency_meter,154: input=11, output=788
539 16:34:14.041403 [RTC]rtc_get_frequency_meter,154: input=13, output=821
540 16:34:14.041505 [RTC]rtc_get_frequency_meter,154: input=12, output=805
541 16:34:14.041607 [RTC]rtc_get_frequency_meter,154: input=11, output=790
542 16:34:14.041709 [RTC]rtc_get_frequency_meter,154: input=12, output=805
543 16:34:14.041810 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 16:34:14.041911 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 16:34:14.042268 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 16:34:14.042389 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 16:34:14.042494 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 16:34:14.042599 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 16:34:14.042715 ADC[4]: Raw value=905172 ID=7
550 16:34:14.042803 ADC[3]: Raw value=213546 ID=1
551 16:34:14.042891 RAM Code: 0x71
552 16:34:14.042978 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 16:34:14.043067 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 16:34:14.043154 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 16:34:14.043243 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 16:34:14.043331 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 16:34:14.043424 in-header: 03 07 00 00 08 00 00 00
558 16:34:14.043513 in-data: aa e4 47 04 13 02 00 00
559 16:34:14.043661 Chrome EC: UHEPI supported
560 16:34:14.043793 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 16:34:14.043888 in-header: 03 a9 00 00 08 00 00 00
562 16:34:14.043977 in-data: 84 60 60 08 00 00 00 00
563 16:34:14.044066 MRC: failed to locate region type 0.
564 16:34:14.044154 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 16:34:14.044242 DRAM-K: Running full calibration
566 16:34:14.044329 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 16:34:14.044418 header.status = 0x0
568 16:34:14.044506 header.version = 0x6 (expected: 0x6)
569 16:34:14.044593 header.size = 0xd00 (expected: 0xd00)
570 16:34:14.044680 header.flags = 0x0
571 16:34:14.044775 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 16:34:14.044878 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 16:34:14.044967 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 16:34:14.045055 dram_init: ddr_geometry: 2
575 16:34:14.045142 [EMI] MDL number = 2
576 16:34:14.045229 [EMI] Get MDL freq = 0
577 16:34:14.045335 dram_init: ddr_type: 0
578 16:34:14.045424 is_discrete_lpddr4: 1
579 16:34:14.045510 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 16:34:14.045597
581 16:34:14.045684
582 16:34:14.045770 [Bian_co] ETT version 0.0.0.1
583 16:34:14.045879 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 16:34:14.045971
585 16:34:14.046057 dramc_set_vcore_voltage set vcore to 650000
586 16:34:14.046144 Read voltage for 800, 4
587 16:34:14.046230 Vio18 = 0
588 16:34:14.046316 Vcore = 650000
589 16:34:14.046402 Vdram = 0
590 16:34:14.046488 Vddq = 0
591 16:34:14.046574 Vmddr = 0
592 16:34:14.046660 dram_init: config_dvfs: 1
593 16:34:14.046746 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 16:34:14.046892 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 16:34:14.047009 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 16:34:14.047099 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 16:34:14.047187 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 16:34:14.047274 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 16:34:14.047360 MEM_TYPE=3, freq_sel=18
600 16:34:14.047447 sv_algorithm_assistance_LP4_1600
601 16:34:14.047533 ============ PULL DRAM RESETB DOWN ============
602 16:34:14.047626 ========== PULL DRAM RESETB DOWN end =========
603 16:34:14.047723 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 16:34:14.047800 ===================================
605 16:34:14.047875 LPDDR4 DRAM CONFIGURATION
606 16:34:14.047950 ===================================
607 16:34:14.048025 EX_ROW_EN[0] = 0x0
608 16:34:14.048100 EX_ROW_EN[1] = 0x0
609 16:34:14.048175 LP4Y_EN = 0x0
610 16:34:14.048249 WORK_FSP = 0x0
611 16:34:14.048322 WL = 0x2
612 16:34:14.048397 RL = 0x2
613 16:34:14.048473 BL = 0x2
614 16:34:14.048548 RPST = 0x0
615 16:34:14.048622 RD_PRE = 0x0
616 16:34:14.048696 WR_PRE = 0x1
617 16:34:14.048770 WR_PST = 0x0
618 16:34:14.048844 DBI_WR = 0x0
619 16:34:14.048918 DBI_RD = 0x0
620 16:34:14.048993 OTF = 0x1
621 16:34:14.049069 ===================================
622 16:34:14.049144 ===================================
623 16:34:14.049219 ANA top config
624 16:34:14.049304 ===================================
625 16:34:14.049380 DLL_ASYNC_EN = 0
626 16:34:14.049455 ALL_SLAVE_EN = 1
627 16:34:14.049529 NEW_RANK_MODE = 1
628 16:34:14.049604 DLL_IDLE_MODE = 1
629 16:34:14.049680 LP45_APHY_COMB_EN = 1
630 16:34:14.049754 TX_ODT_DIS = 1
631 16:34:14.049829 NEW_8X_MODE = 1
632 16:34:14.049905 ===================================
633 16:34:14.049980 ===================================
634 16:34:14.050055 data_rate = 1600
635 16:34:14.050130 CKR = 1
636 16:34:14.050206 DQ_P2S_RATIO = 8
637 16:34:14.050281 ===================================
638 16:34:14.050357 CA_P2S_RATIO = 8
639 16:34:14.050430 DQ_CA_OPEN = 0
640 16:34:14.050505 DQ_SEMI_OPEN = 0
641 16:34:14.050580 CA_SEMI_OPEN = 0
642 16:34:14.050655 CA_FULL_RATE = 0
643 16:34:14.050729 DQ_CKDIV4_EN = 1
644 16:34:14.050803 CA_CKDIV4_EN = 1
645 16:34:14.050877 CA_PREDIV_EN = 0
646 16:34:14.050952 PH8_DLY = 0
647 16:34:14.051026 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 16:34:14.051102 DQ_AAMCK_DIV = 4
649 16:34:14.051176 CA_AAMCK_DIV = 4
650 16:34:14.051250 CA_ADMCK_DIV = 4
651 16:34:14.051325 DQ_TRACK_CA_EN = 0
652 16:34:14.051400 CA_PICK = 800
653 16:34:14.051474 CA_MCKIO = 800
654 16:34:14.051549 MCKIO_SEMI = 0
655 16:34:14.051623 PLL_FREQ = 3068
656 16:34:14.051698 DQ_UI_PI_RATIO = 32
657 16:34:14.051774 CA_UI_PI_RATIO = 0
658 16:34:14.051849 ===================================
659 16:34:14.051924 ===================================
660 16:34:14.051999 memory_type:LPDDR4
661 16:34:14.052074 GP_NUM : 10
662 16:34:14.052148 SRAM_EN : 1
663 16:34:14.052223 MD32_EN : 0
664 16:34:14.052298 ===================================
665 16:34:14.052618 [ANA_INIT] >>>>>>>>>>>>>>
666 16:34:14.052706 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 16:34:14.052798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 16:34:14.052866 ===================================
669 16:34:14.052949 data_rate = 1600,PCW = 0X7600
670 16:34:14.053067 ===================================
671 16:34:14.053179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 16:34:14.053294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 16:34:14.053368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 16:34:14.053437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 16:34:14.053506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 16:34:14.053574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 16:34:14.053642 [ANA_INIT] flow start
678 16:34:14.053709 [ANA_INIT] PLL >>>>>>>>
679 16:34:14.053776 [ANA_INIT] PLL <<<<<<<<
680 16:34:14.053843 [ANA_INIT] MIDPI >>>>>>>>
681 16:34:14.053910 [ANA_INIT] MIDPI <<<<<<<<
682 16:34:14.053978 [ANA_INIT] DLL >>>>>>>>
683 16:34:14.054044 [ANA_INIT] flow end
684 16:34:14.054111 ============ LP4 DIFF to SE enter ============
685 16:34:14.054179 ============ LP4 DIFF to SE exit ============
686 16:34:14.054247 [ANA_INIT] <<<<<<<<<<<<<
687 16:34:14.054314 [Flow] Enable top DCM control >>>>>
688 16:34:14.054382 [Flow] Enable top DCM control <<<<<
689 16:34:14.054449 Enable DLL master slave shuffle
690 16:34:14.054517 ==============================================================
691 16:34:14.054585 Gating Mode config
692 16:34:14.054652 ==============================================================
693 16:34:14.054720 Config description:
694 16:34:14.054787 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 16:34:14.054855 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 16:34:14.054924 SELPH_MODE 0: By rank 1: By Phase
697 16:34:14.054992 ==============================================================
698 16:34:14.055061 GAT_TRACK_EN = 1
699 16:34:14.055128 RX_GATING_MODE = 2
700 16:34:14.055195 RX_GATING_TRACK_MODE = 2
701 16:34:14.055262 SELPH_MODE = 1
702 16:34:14.055329 PICG_EARLY_EN = 1
703 16:34:14.055396 VALID_LAT_VALUE = 1
704 16:34:14.055463 ==============================================================
705 16:34:14.055531 Enter into Gating configuration >>>>
706 16:34:14.055598 Exit from Gating configuration <<<<
707 16:34:14.055665 Enter into DVFS_PRE_config >>>>>
708 16:34:14.055733 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 16:34:14.055806 Exit from DVFS_PRE_config <<<<<
710 16:34:14.055873 Enter into PICG configuration >>>>
711 16:34:14.055940 Exit from PICG configuration <<<<
712 16:34:14.056007 [RX_INPUT] configuration >>>>>
713 16:34:14.056074 [RX_INPUT] configuration <<<<<
714 16:34:14.056139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 16:34:14.056206 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 16:34:14.056274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 16:34:14.056342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 16:34:14.056409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 16:34:14.056477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 16:34:14.056544 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 16:34:14.056611 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 16:34:14.056678 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 16:34:14.056745 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 16:34:14.056813 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 16:34:14.056879 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 16:34:14.056946 ===================================
727 16:34:14.057014 LPDDR4 DRAM CONFIGURATION
728 16:34:14.057081 ===================================
729 16:34:14.057148 EX_ROW_EN[0] = 0x0
730 16:34:14.057215 EX_ROW_EN[1] = 0x0
731 16:34:14.057294 LP4Y_EN = 0x0
732 16:34:14.057364 WORK_FSP = 0x0
733 16:34:14.057431 WL = 0x2
734 16:34:14.057498 RL = 0x2
735 16:34:14.057565 BL = 0x2
736 16:34:14.057631 RPST = 0x0
737 16:34:14.057697 RD_PRE = 0x0
738 16:34:14.057772 WR_PRE = 0x1
739 16:34:14.057832 WR_PST = 0x0
740 16:34:14.057893 DBI_WR = 0x0
741 16:34:14.057953 DBI_RD = 0x0
742 16:34:14.058014 OTF = 0x1
743 16:34:14.058074 ===================================
744 16:34:14.058135 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 16:34:14.058195 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 16:34:14.058256 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 16:34:14.058317 ===================================
748 16:34:14.058378 LPDDR4 DRAM CONFIGURATION
749 16:34:14.058437 ===================================
750 16:34:14.058497 EX_ROW_EN[0] = 0x10
751 16:34:14.058557 EX_ROW_EN[1] = 0x0
752 16:34:14.058617 LP4Y_EN = 0x0
753 16:34:14.058677 WORK_FSP = 0x0
754 16:34:14.058737 WL = 0x2
755 16:34:14.058797 RL = 0x2
756 16:34:14.058856 BL = 0x2
757 16:34:14.058916 RPST = 0x0
758 16:34:14.058975 RD_PRE = 0x0
759 16:34:14.059036 WR_PRE = 0x1
760 16:34:14.059095 WR_PST = 0x0
761 16:34:14.059155 DBI_WR = 0x0
762 16:34:14.059214 DBI_RD = 0x0
763 16:34:14.059274 OTF = 0x1
764 16:34:14.059335 ===================================
765 16:34:14.059395 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 16:34:14.059456 nWR fixed to 40
767 16:34:14.059517 [ModeRegInit_LP4] CH0 RK0
768 16:34:14.059578 [ModeRegInit_LP4] CH0 RK1
769 16:34:14.059637 [ModeRegInit_LP4] CH1 RK0
770 16:34:14.059697 [ModeRegInit_LP4] CH1 RK1
771 16:34:14.059757 match AC timing 13
772 16:34:14.059816 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 16:34:14.060094 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 16:34:14.060166 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 16:34:14.060228 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 16:34:14.060290 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 16:34:14.060351 [EMI DOE] emi_dcm 0
778 16:34:14.060411 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 16:34:14.060472 ==
780 16:34:14.060533 Dram Type= 6, Freq= 0, CH_0, rank 0
781 16:34:14.060594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 16:34:14.060656 ==
783 16:34:14.060717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 16:34:14.060777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 16:34:14.060838 [CA 0] Center 38 (7~69) winsize 63
786 16:34:14.060899 [CA 1] Center 37 (6~68) winsize 63
787 16:34:14.060959 [CA 2] Center 34 (4~65) winsize 62
788 16:34:14.061018 [CA 3] Center 34 (4~65) winsize 62
789 16:34:14.061079 [CA 4] Center 34 (3~65) winsize 63
790 16:34:14.061139 [CA 5] Center 33 (3~64) winsize 62
791 16:34:14.061199
792 16:34:14.061275 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 16:34:14.061340
794 16:34:14.061401 [CATrainingPosCal] consider 1 rank data
795 16:34:14.061462 u2DelayCellTimex100 = 270/100 ps
796 16:34:14.061522 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
797 16:34:14.061583 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 16:34:14.061643 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 16:34:14.061703 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 16:34:14.061763 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
801 16:34:14.061824 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 16:34:14.061884
803 16:34:14.061944 CA PerBit enable=1, Macro0, CA PI delay=33
804 16:34:14.062004
805 16:34:14.062063 [CBTSetCACLKResult] CA Dly = 33
806 16:34:14.062123 CS Dly: 5 (0~36)
807 16:34:14.062183 ==
808 16:34:14.062243 Dram Type= 6, Freq= 0, CH_0, rank 1
809 16:34:14.062304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 16:34:14.062366 ==
811 16:34:14.062426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 16:34:14.062486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 16:34:14.062546 [CA 0] Center 38 (7~69) winsize 63
814 16:34:14.062606 [CA 1] Center 37 (7~68) winsize 62
815 16:34:14.062666 [CA 2] Center 35 (4~66) winsize 63
816 16:34:14.062738 [CA 3] Center 35 (4~66) winsize 63
817 16:34:14.062793 [CA 4] Center 34 (3~65) winsize 63
818 16:34:14.062847 [CA 5] Center 33 (3~64) winsize 62
819 16:34:14.062907
820 16:34:14.062963 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 16:34:14.063018
822 16:34:14.063072 [CATrainingPosCal] consider 2 rank data
823 16:34:14.063126 u2DelayCellTimex100 = 270/100 ps
824 16:34:14.063181 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
825 16:34:14.063235 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 16:34:14.063289 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 16:34:14.063344 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 16:34:14.063398 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
829 16:34:14.063453 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 16:34:14.063507
831 16:34:14.063561 CA PerBit enable=1, Macro0, CA PI delay=33
832 16:34:14.063615
833 16:34:14.063669 [CBTSetCACLKResult] CA Dly = 33
834 16:34:14.063723 CS Dly: 6 (0~38)
835 16:34:14.063777
836 16:34:14.063831 ----->DramcWriteLeveling(PI) begin...
837 16:34:14.063891 ==
838 16:34:14.063946 Dram Type= 6, Freq= 0, CH_0, rank 0
839 16:34:14.064002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 16:34:14.064057 ==
841 16:34:14.064111 Write leveling (Byte 0): 30 => 30
842 16:34:14.064166 Write leveling (Byte 1): 28 => 28
843 16:34:14.064220 DramcWriteLeveling(PI) end<-----
844 16:34:14.064275
845 16:34:14.064329 ==
846 16:34:14.064384 Dram Type= 6, Freq= 0, CH_0, rank 0
847 16:34:14.064438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 16:34:14.064494 ==
849 16:34:14.064548 [Gating] SW mode calibration
850 16:34:14.064603 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 16:34:14.064659 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 16:34:14.064715 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 16:34:14.064770 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
854 16:34:14.064826 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 16:34:14.064881 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 16:34:14.064937 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:34:14.064993 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:34:14.065047 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:34:14.065102 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:34:14.065157 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:34:14.065211 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:34:14.065278 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:34:14.065336 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:34:14.065391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:34:14.065445 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:34:14.065500 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:34:14.065555 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 16:34:14.065610 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 16:34:14.065666 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 16:34:14.065721 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 16:34:14.065794 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 16:34:14.065851 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 16:34:14.065906 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:34:14.065960 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:34:14.066015 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 16:34:14.066070 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 16:34:14.066124 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 16:34:14.066189 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
879 16:34:14.066294 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
880 16:34:14.066361 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 16:34:14.066645 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:34:14.066714 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 16:34:14.066771 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 16:34:14.066827 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 16:34:14.066910 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
886 16:34:14.067003 0 10 8 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
887 16:34:14.067068 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
888 16:34:14.067124 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 16:34:14.067180 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:34:14.067236 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:34:14.067290 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 16:34:14.067346 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 16:34:14.067401 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
894 16:34:14.067457 0 11 8 | B1->B0 | 2a2a 3f3f | 0 0 | (0 0) (0 0)
895 16:34:14.067513 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
896 16:34:14.067568 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 16:34:14.067623 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:34:14.067679 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:34:14.067747 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 16:34:14.067858 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 16:34:14.067962 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 16:34:14.068049 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 16:34:14.068135 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 16:34:14.068221 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 16:34:14.068307 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:34:14.068396 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:34:14.068482 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:34:14.068569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:34:14.068655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:34:14.068740 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:34:14.068827 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:34:14.068919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:34:14.069005 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:34:14.069091 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 16:34:14.069177 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 16:34:14.069292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 16:34:14.069394 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 16:34:14.069480 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 16:34:14.069566 Total UI for P1: 0, mck2ui 16
920 16:34:14.069696 best dqsien dly found for B0: ( 0, 14, 4)
921 16:34:14.069848 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 16:34:14.070022 Total UI for P1: 0, mck2ui 16
923 16:34:14.070144 best dqsien dly found for B1: ( 0, 14, 8)
924 16:34:14.070235 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
925 16:34:14.070324 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 16:34:14.070412
927 16:34:14.070499 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
928 16:34:14.070587 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 16:34:14.070675 [Gating] SW calibration Done
930 16:34:14.070763 ==
931 16:34:14.070852 Dram Type= 6, Freq= 0, CH_0, rank 0
932 16:34:14.070944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 16:34:14.071028 ==
934 16:34:14.071111 RX Vref Scan: 0
935 16:34:14.071194
936 16:34:14.071282 RX Vref 0 -> 0, step: 1
937 16:34:14.071379
938 16:34:14.071464 RX Delay -130 -> 252, step: 16
939 16:34:14.071548 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 16:34:14.071632 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 16:34:14.071716 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
942 16:34:14.071800 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
943 16:34:14.071883 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 16:34:14.071966 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 16:34:14.072050 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 16:34:14.072133 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
947 16:34:14.072217 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 16:34:14.072300 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
949 16:34:14.072387 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 16:34:14.072471 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 16:34:14.072555 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
952 16:34:14.072639 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
953 16:34:14.072722 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 16:34:14.072806 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 16:34:14.072888 ==
956 16:34:14.072972 Dram Type= 6, Freq= 0, CH_0, rank 0
957 16:34:14.073055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 16:34:14.073138 ==
959 16:34:14.073221 DQS Delay:
960 16:34:14.073316 DQS0 = 0, DQS1 = 0
961 16:34:14.073371 DQM Delay:
962 16:34:14.073455 DQM0 = 92, DQM1 = 75
963 16:34:14.073533 DQ Delay:
964 16:34:14.073657 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
965 16:34:14.073713 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
966 16:34:14.073819 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
967 16:34:14.073893 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
968 16:34:14.074018
969 16:34:14.074150
970 16:34:14.074254 ==
971 16:34:14.074336 Dram Type= 6, Freq= 0, CH_0, rank 0
972 16:34:14.074408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 16:34:14.074504 ==
974 16:34:14.074598
975 16:34:14.074690
976 16:34:14.074776 TX Vref Scan disable
977 16:34:14.074873 == TX Byte 0 ==
978 16:34:14.075000 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
979 16:34:14.075084 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
980 16:34:14.075166 == TX Byte 1 ==
981 16:34:14.075257 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
982 16:34:14.075314 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
983 16:34:14.075368 ==
984 16:34:14.075422 Dram Type= 6, Freq= 0, CH_0, rank 0
985 16:34:14.075476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 16:34:14.075531 ==
987 16:34:14.075584 TX Vref=22, minBit 0, minWin=27, winSum=441
988 16:34:14.075638 TX Vref=24, minBit 5, minWin=26, winSum=443
989 16:34:14.075901 TX Vref=26, minBit 0, minWin=27, winSum=443
990 16:34:14.075993 TX Vref=28, minBit 3, minWin=27, winSum=450
991 16:34:14.076049 TX Vref=30, minBit 1, minWin=27, winSum=453
992 16:34:14.076103 TX Vref=32, minBit 1, minWin=27, winSum=448
993 16:34:14.076158 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30
994 16:34:14.076212
995 16:34:14.076265 Final TX Range 1 Vref 30
996 16:34:14.076319
997 16:34:14.076402 ==
998 16:34:14.076469 Dram Type= 6, Freq= 0, CH_0, rank 0
999 16:34:14.076521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 16:34:14.076573 ==
1001 16:34:14.076625
1002 16:34:14.076676
1003 16:34:14.076727 TX Vref Scan disable
1004 16:34:14.076794 == TX Byte 0 ==
1005 16:34:14.076872 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 16:34:14.076926 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 16:34:14.076979 == TX Byte 1 ==
1008 16:34:14.077031 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1009 16:34:14.077127 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1010 16:34:14.077233
1011 16:34:14.077321 [DATLAT]
1012 16:34:14.077410 Freq=800, CH0 RK0
1013 16:34:14.077477
1014 16:34:14.077553 DATLAT Default: 0xa
1015 16:34:14.077639 0, 0xFFFF, sum = 0
1016 16:34:14.077717 1, 0xFFFF, sum = 0
1017 16:34:14.077803 2, 0xFFFF, sum = 0
1018 16:34:14.077879 3, 0xFFFF, sum = 0
1019 16:34:14.077989 4, 0xFFFF, sum = 0
1020 16:34:14.078093 5, 0xFFFF, sum = 0
1021 16:34:14.078210 6, 0xFFFF, sum = 0
1022 16:34:14.078299 7, 0xFFFF, sum = 0
1023 16:34:14.078400 8, 0xFFFF, sum = 0
1024 16:34:14.078533 9, 0x0, sum = 1
1025 16:34:14.078631 10, 0x0, sum = 2
1026 16:34:14.078722 11, 0x0, sum = 3
1027 16:34:14.078810 12, 0x0, sum = 4
1028 16:34:14.078899 best_step = 10
1029 16:34:14.078986
1030 16:34:14.079079 ==
1031 16:34:14.079170 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 16:34:14.079257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 16:34:14.079346 ==
1034 16:34:14.079433 RX Vref Scan: 1
1035 16:34:14.079524
1036 16:34:14.079613 Set Vref Range= 32 -> 127
1037 16:34:14.079735
1038 16:34:14.079830 RX Vref 32 -> 127, step: 1
1039 16:34:14.079927
1040 16:34:14.080020 RX Delay -111 -> 252, step: 8
1041 16:34:14.080104
1042 16:34:14.080187 Set Vref, RX VrefLevel [Byte0]: 32
1043 16:34:14.080299 [Byte1]: 32
1044 16:34:14.080382
1045 16:34:14.080476 Set Vref, RX VrefLevel [Byte0]: 33
1046 16:34:14.080601 [Byte1]: 33
1047 16:34:14.080731
1048 16:34:14.080823 Set Vref, RX VrefLevel [Byte0]: 34
1049 16:34:14.080878 [Byte1]: 34
1050 16:34:14.080931
1051 16:34:14.081004 Set Vref, RX VrefLevel [Byte0]: 35
1052 16:34:14.081087 [Byte1]: 35
1053 16:34:14.081168
1054 16:34:14.081280 Set Vref, RX VrefLevel [Byte0]: 36
1055 16:34:14.081366 [Byte1]: 36
1056 16:34:14.081448
1057 16:34:14.081566 Set Vref, RX VrefLevel [Byte0]: 37
1058 16:34:14.081681 [Byte1]: 37
1059 16:34:14.081767
1060 16:34:14.081857 Set Vref, RX VrefLevel [Byte0]: 38
1061 16:34:14.081948 [Byte1]: 38
1062 16:34:14.082031
1063 16:34:14.082113 Set Vref, RX VrefLevel [Byte0]: 39
1064 16:34:14.082201 [Byte1]: 39
1065 16:34:14.082271
1066 16:34:14.082361 Set Vref, RX VrefLevel [Byte0]: 40
1067 16:34:14.082450 [Byte1]: 40
1068 16:34:14.082550
1069 16:34:14.082644 Set Vref, RX VrefLevel [Byte0]: 41
1070 16:34:14.082741 [Byte1]: 41
1071 16:34:14.082824
1072 16:34:14.082911 Set Vref, RX VrefLevel [Byte0]: 42
1073 16:34:14.082999 [Byte1]: 42
1074 16:34:14.083081
1075 16:34:14.083164 Set Vref, RX VrefLevel [Byte0]: 43
1076 16:34:14.083249 [Byte1]: 43
1077 16:34:14.083339
1078 16:34:14.083438 Set Vref, RX VrefLevel [Byte0]: 44
1079 16:34:14.083523 [Byte1]: 44
1080 16:34:14.083605
1081 16:34:14.083698 Set Vref, RX VrefLevel [Byte0]: 45
1082 16:34:14.083805 [Byte1]: 45
1083 16:34:14.083896
1084 16:34:14.083983 Set Vref, RX VrefLevel [Byte0]: 46
1085 16:34:14.084074 [Byte1]: 46
1086 16:34:14.084158
1087 16:34:14.084241 Set Vref, RX VrefLevel [Byte0]: 47
1088 16:34:14.084333 [Byte1]: 47
1089 16:34:14.084428
1090 16:34:14.084539 Set Vref, RX VrefLevel [Byte0]: 48
1091 16:34:14.084658 [Byte1]: 48
1092 16:34:14.084739
1093 16:34:14.084854 Set Vref, RX VrefLevel [Byte0]: 49
1094 16:34:14.084962 [Byte1]: 49
1095 16:34:14.085046
1096 16:34:14.085128 Set Vref, RX VrefLevel [Byte0]: 50
1097 16:34:14.085210 [Byte1]: 50
1098 16:34:14.085334
1099 16:34:14.085431 Set Vref, RX VrefLevel [Byte0]: 51
1100 16:34:14.085559 [Byte1]: 51
1101 16:34:14.085677
1102 16:34:14.085772 Set Vref, RX VrefLevel [Byte0]: 52
1103 16:34:14.085885 [Byte1]: 52
1104 16:34:14.085984
1105 16:34:14.086065 Set Vref, RX VrefLevel [Byte0]: 53
1106 16:34:14.086148 [Byte1]: 53
1107 16:34:14.086242
1108 16:34:14.086322 Set Vref, RX VrefLevel [Byte0]: 54
1109 16:34:14.086402 [Byte1]: 54
1110 16:34:14.086481
1111 16:34:14.086561 Set Vref, RX VrefLevel [Byte0]: 55
1112 16:34:14.086658 [Byte1]: 55
1113 16:34:14.086739
1114 16:34:14.086820 Set Vref, RX VrefLevel [Byte0]: 56
1115 16:34:14.086902 [Byte1]: 56
1116 16:34:14.086988
1117 16:34:14.087088 Set Vref, RX VrefLevel [Byte0]: 57
1118 16:34:14.087169 [Byte1]: 57
1119 16:34:14.087228
1120 16:34:14.087281 Set Vref, RX VrefLevel [Byte0]: 58
1121 16:34:14.087341 [Byte1]: 58
1122 16:34:14.087444
1123 16:34:14.087573 Set Vref, RX VrefLevel [Byte0]: 59
1124 16:34:14.087628 [Byte1]: 59
1125 16:34:14.087681
1126 16:34:14.087734 Set Vref, RX VrefLevel [Byte0]: 60
1127 16:34:14.087787 [Byte1]: 60
1128 16:34:14.087840
1129 16:34:14.087893 Set Vref, RX VrefLevel [Byte0]: 61
1130 16:34:14.087946 [Byte1]: 61
1131 16:34:14.088033
1132 16:34:14.088116 Set Vref, RX VrefLevel [Byte0]: 62
1133 16:34:14.088211 [Byte1]: 62
1134 16:34:14.088290
1135 16:34:14.088370 Set Vref, RX VrefLevel [Byte0]: 63
1136 16:34:14.088451 [Byte1]: 63
1137 16:34:14.088530
1138 16:34:14.088610 Set Vref, RX VrefLevel [Byte0]: 64
1139 16:34:14.088706 [Byte1]: 64
1140 16:34:14.088787
1141 16:34:14.088881 Set Vref, RX VrefLevel [Byte0]: 65
1142 16:34:14.088961 [Byte1]: 65
1143 16:34:14.089040
1144 16:34:14.089147 Set Vref, RX VrefLevel [Byte0]: 66
1145 16:34:14.089254 [Byte1]: 66
1146 16:34:14.089411
1147 16:34:14.089512 Set Vref, RX VrefLevel [Byte0]: 67
1148 16:34:14.089594 [Byte1]: 67
1149 16:34:14.089674
1150 16:34:14.089754 Set Vref, RX VrefLevel [Byte0]: 68
1151 16:34:14.089835 [Byte1]: 68
1152 16:34:14.089914
1153 16:34:14.089995 Set Vref, RX VrefLevel [Byte0]: 69
1154 16:34:14.090075 [Byte1]: 69
1155 16:34:14.090155
1156 16:34:14.090264 Set Vref, RX VrefLevel [Byte0]: 70
1157 16:34:14.090554 [Byte1]: 70
1158 16:34:14.090640
1159 16:34:14.090728 Set Vref, RX VrefLevel [Byte0]: 71
1160 16:34:14.090811 [Byte1]: 71
1161 16:34:14.090899
1162 16:34:14.090984 Set Vref, RX VrefLevel [Byte0]: 72
1163 16:34:14.091066 [Byte1]: 72
1164 16:34:14.091192
1165 16:34:14.091286 Set Vref, RX VrefLevel [Byte0]: 73
1166 16:34:14.091367 [Byte1]: 73
1167 16:34:14.091452
1168 16:34:14.091534 Set Vref, RX VrefLevel [Byte0]: 74
1169 16:34:14.091616 [Byte1]: 74
1170 16:34:14.091754
1171 16:34:14.091847 Final RX Vref Byte 0 = 57 to rank0
1172 16:34:14.091932 Final RX Vref Byte 1 = 59 to rank0
1173 16:34:14.092015 Final RX Vref Byte 0 = 57 to rank1
1174 16:34:14.092098 Final RX Vref Byte 1 = 59 to rank1==
1175 16:34:14.092181 Dram Type= 6, Freq= 0, CH_0, rank 0
1176 16:34:14.092263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 16:34:14.092346 ==
1178 16:34:14.092429 DQS Delay:
1179 16:34:14.092510 DQS0 = 0, DQS1 = 0
1180 16:34:14.092595 DQM Delay:
1181 16:34:14.092677 DQM0 = 87, DQM1 = 76
1182 16:34:14.092759 DQ Delay:
1183 16:34:14.092842 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1184 16:34:14.092924 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1185 16:34:14.093006 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1186 16:34:14.093089 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1187 16:34:14.093170
1188 16:34:14.093251
1189 16:34:14.093319 [DQSOSCAuto] RK0, (LSB)MR18= 0x3730, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1190 16:34:14.093374 CH0 RK0: MR19=606, MR18=3730
1191 16:34:14.093427 CH0_RK0: MR19=0x606, MR18=0x3730, DQSOSC=395, MR23=63, INC=94, DEC=63
1192 16:34:14.093481
1193 16:34:14.093533 ----->DramcWriteLeveling(PI) begin...
1194 16:34:14.093602 ==
1195 16:34:14.093654 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 16:34:14.093707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 16:34:14.093758 ==
1198 16:34:14.093810 Write leveling (Byte 0): 34 => 34
1199 16:34:14.093861 Write leveling (Byte 1): 28 => 28
1200 16:34:14.093913 DramcWriteLeveling(PI) end<-----
1201 16:34:14.093964
1202 16:34:14.094014 ==
1203 16:34:14.094066 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 16:34:14.094117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 16:34:14.094169 ==
1206 16:34:14.094220 [Gating] SW mode calibration
1207 16:34:14.094272 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1208 16:34:14.094324 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1209 16:34:14.094376 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1210 16:34:14.094428 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 16:34:14.094480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1212 16:34:14.094531 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 16:34:14.094583 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 16:34:14.094634 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 16:34:14.094685 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 16:34:14.094737 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 16:34:14.094787 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 16:34:14.094838 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 16:34:14.094889 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 16:34:14.094941 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 16:34:14.094992 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 16:34:14.095043 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 16:34:14.095094 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:34:14.095146 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 16:34:14.095197 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1226 16:34:14.095248 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1227 16:34:14.095300 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:34:14.095351 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:34:14.095403 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:34:14.095488 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:34:14.095561 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:34:14.095644 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 16:34:14.095725 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 16:34:14.095820 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1235 16:34:14.095903 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1236 16:34:14.095985 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1237 16:34:14.096068 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 16:34:14.096150 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 16:34:14.096233 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 16:34:14.096315 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 16:34:14.096398 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 16:34:14.096481 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
1243 16:34:14.096563 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
1244 16:34:14.096645 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 16:34:14.096728 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 16:34:14.096811 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 16:34:14.096893 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 16:34:14.096975 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 16:34:14.097058 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 16:34:14.097140 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1251 16:34:14.097222 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
1252 16:34:14.097300 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1253 16:34:14.097355 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 16:34:14.097409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 16:34:14.097474 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 16:34:14.097525 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 16:34:14.097576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 16:34:14.097627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1259 16:34:14.097678 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1260 16:34:14.097938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 16:34:14.098001 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 16:34:14.098054 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 16:34:14.098106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 16:34:14.098158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 16:34:14.098210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 16:34:14.098262 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 16:34:14.098313 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 16:34:14.098365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 16:34:14.098416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 16:34:14.098467 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 16:34:14.098519 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 16:34:14.098570 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 16:34:14.098622 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 16:34:14.098673 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1275 16:34:14.098724 Total UI for P1: 0, mck2ui 16
1276 16:34:14.098776 best dqsien dly found for B0: ( 0, 14, 2)
1277 16:34:14.098828 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 16:34:14.098880 Total UI for P1: 0, mck2ui 16
1279 16:34:14.098931 best dqsien dly found for B1: ( 0, 14, 6)
1280 16:34:14.098982 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1281 16:34:14.099034 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1282 16:34:14.099085
1283 16:34:14.099135 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1284 16:34:14.099187 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1285 16:34:14.099238 [Gating] SW calibration Done
1286 16:34:14.099289 ==
1287 16:34:14.099340 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 16:34:14.099392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 16:34:14.099443 ==
1290 16:34:14.099494 RX Vref Scan: 0
1291 16:34:14.099544
1292 16:34:14.099595 RX Vref 0 -> 0, step: 1
1293 16:34:14.099646
1294 16:34:14.099697 RX Delay -130 -> 252, step: 16
1295 16:34:14.099748 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1296 16:34:14.099800 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1297 16:34:14.099851 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1298 16:34:14.099903 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1299 16:34:14.099954 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1300 16:34:14.100005 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1301 16:34:14.100056 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1302 16:34:14.100107 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1303 16:34:14.100158 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1304 16:34:14.100210 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1305 16:34:14.100261 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1306 16:34:14.100312 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1307 16:34:14.100363 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1308 16:34:14.100414 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1309 16:34:14.100465 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1310 16:34:14.100516 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1311 16:34:14.100567 ==
1312 16:34:14.100618 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 16:34:14.100669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 16:34:14.100720 ==
1315 16:34:14.100772 DQS Delay:
1316 16:34:14.100823 DQS0 = 0, DQS1 = 0
1317 16:34:14.100874 DQM Delay:
1318 16:34:14.100925 DQM0 = 86, DQM1 = 77
1319 16:34:14.100977 DQ Delay:
1320 16:34:14.101041 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1321 16:34:14.101123 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1322 16:34:14.101203 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1323 16:34:14.101321 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1324 16:34:14.101402
1325 16:34:14.101481
1326 16:34:14.101560 ==
1327 16:34:14.101640 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 16:34:14.101721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 16:34:14.101802 ==
1330 16:34:14.101881
1331 16:34:14.101961
1332 16:34:14.102040 TX Vref Scan disable
1333 16:34:14.102138 == TX Byte 0 ==
1334 16:34:14.102206 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1335 16:34:14.102276 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1336 16:34:14.102328 == TX Byte 1 ==
1337 16:34:14.102379 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1338 16:34:14.102431 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1339 16:34:14.102482 ==
1340 16:34:14.102534 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 16:34:14.102586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 16:34:14.102638 ==
1343 16:34:14.102689 TX Vref=22, minBit 1, minWin=27, winSum=443
1344 16:34:14.102741 TX Vref=24, minBit 2, minWin=27, winSum=447
1345 16:34:14.102793 TX Vref=26, minBit 5, minWin=27, winSum=448
1346 16:34:14.102844 TX Vref=28, minBit 5, minWin=27, winSum=451
1347 16:34:14.102895 TX Vref=30, minBit 5, minWin=27, winSum=450
1348 16:34:14.102946 TX Vref=32, minBit 5, minWin=27, winSum=448
1349 16:34:14.102998 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 28
1350 16:34:14.103050
1351 16:34:14.103101 Final TX Range 1 Vref 28
1352 16:34:14.103152
1353 16:34:14.103204 ==
1354 16:34:14.103254 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 16:34:14.103305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 16:34:14.103357 ==
1357 16:34:14.103408
1358 16:34:14.103459
1359 16:34:14.103509 TX Vref Scan disable
1360 16:34:14.103560 == TX Byte 0 ==
1361 16:34:14.103611 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1362 16:34:14.103662 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1363 16:34:14.103713 == TX Byte 1 ==
1364 16:34:14.103764 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1365 16:34:14.103814 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1366 16:34:14.103865
1367 16:34:14.103915 [DATLAT]
1368 16:34:14.103965 Freq=800, CH0 RK1
1369 16:34:14.104016
1370 16:34:14.104066 DATLAT Default: 0xa
1371 16:34:14.104117 0, 0xFFFF, sum = 0
1372 16:34:14.104169 1, 0xFFFF, sum = 0
1373 16:34:14.104221 2, 0xFFFF, sum = 0
1374 16:34:14.104272 3, 0xFFFF, sum = 0
1375 16:34:14.104324 4, 0xFFFF, sum = 0
1376 16:34:14.104376 5, 0xFFFF, sum = 0
1377 16:34:14.104428 6, 0xFFFF, sum = 0
1378 16:34:14.104479 7, 0xFFFF, sum = 0
1379 16:34:14.104531 8, 0xFFFF, sum = 0
1380 16:34:14.104583 9, 0x0, sum = 1
1381 16:34:14.104634 10, 0x0, sum = 2
1382 16:34:14.104686 11, 0x0, sum = 3
1383 16:34:14.104737 12, 0x0, sum = 4
1384 16:34:14.104788 best_step = 10
1385 16:34:14.104839
1386 16:34:14.104889 ==
1387 16:34:14.104954 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 16:34:14.105006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 16:34:14.105059 ==
1390 16:34:14.105111 RX Vref Scan: 0
1391 16:34:14.105163
1392 16:34:14.105214 RX Vref 0 -> 0, step: 1
1393 16:34:14.105274
1394 16:34:14.105327 RX Delay -95 -> 252, step: 8
1395 16:34:14.105579 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1396 16:34:14.105641 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1397 16:34:14.105695 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1398 16:34:14.105748 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1399 16:34:14.105800 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1400 16:34:14.105852 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1401 16:34:14.105905 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1402 16:34:14.105956 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1403 16:34:14.106009 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1404 16:34:14.106061 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1405 16:34:14.106113 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1406 16:34:14.106166 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1407 16:34:14.106219 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1408 16:34:14.106271 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1409 16:34:14.106323 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1410 16:34:14.106375 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1411 16:34:14.106427 ==
1412 16:34:14.106479 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 16:34:14.106531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 16:34:14.106583 ==
1415 16:34:14.106635 DQS Delay:
1416 16:34:14.106686 DQS0 = 0, DQS1 = 0
1417 16:34:14.106737 DQM Delay:
1418 16:34:14.106789 DQM0 = 86, DQM1 = 76
1419 16:34:14.106841 DQ Delay:
1420 16:34:14.106892 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1421 16:34:14.106943 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1422 16:34:14.106995 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1423 16:34:14.107047 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1424 16:34:14.107099
1425 16:34:14.107150
1426 16:34:14.107201 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1427 16:34:14.107254 CH0 RK1: MR19=606, MR18=2B27
1428 16:34:14.107306 CH0_RK1: MR19=0x606, MR18=0x2B27, DQSOSC=398, MR23=63, INC=93, DEC=62
1429 16:34:14.107358 [RxdqsGatingPostProcess] freq 800
1430 16:34:14.107410 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1431 16:34:14.107462 Pre-setting of DQS Precalculation
1432 16:34:14.107514 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1433 16:34:14.107566 ==
1434 16:34:14.107618 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 16:34:14.107670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 16:34:14.107722 ==
1437 16:34:14.107773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 16:34:14.107825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 16:34:14.107877 [CA 0] Center 36 (6~67) winsize 62
1440 16:34:14.107929 [CA 1] Center 36 (6~67) winsize 62
1441 16:34:14.107981 [CA 2] Center 34 (4~65) winsize 62
1442 16:34:14.108033 [CA 3] Center 34 (4~65) winsize 62
1443 16:34:14.108085 [CA 4] Center 34 (4~65) winsize 62
1444 16:34:14.108136 [CA 5] Center 33 (3~64) winsize 62
1445 16:34:14.108188
1446 16:34:14.108240 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1447 16:34:14.108291
1448 16:34:14.108343 [CATrainingPosCal] consider 1 rank data
1449 16:34:14.108395 u2DelayCellTimex100 = 270/100 ps
1450 16:34:14.108447 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1451 16:34:14.108499 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1452 16:34:14.108551 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1453 16:34:14.108602 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1454 16:34:14.108654 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1455 16:34:14.108705 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1456 16:34:14.108756
1457 16:34:14.108808 CA PerBit enable=1, Macro0, CA PI delay=33
1458 16:34:14.108860
1459 16:34:14.108912 [CBTSetCACLKResult] CA Dly = 33
1460 16:34:14.108963 CS Dly: 4 (0~35)
1461 16:34:14.109014 ==
1462 16:34:14.109066 Dram Type= 6, Freq= 0, CH_1, rank 1
1463 16:34:14.109118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 16:34:14.109170 ==
1465 16:34:14.109222 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1466 16:34:14.109310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1467 16:34:14.109395 [CA 0] Center 37 (6~68) winsize 63
1468 16:34:14.109474 [CA 1] Center 36 (6~67) winsize 62
1469 16:34:14.109529 [CA 2] Center 34 (4~65) winsize 62
1470 16:34:14.109582 [CA 3] Center 33 (3~64) winsize 62
1471 16:34:14.109634 [CA 4] Center 34 (3~65) winsize 63
1472 16:34:14.109686 [CA 5] Center 34 (4~64) winsize 61
1473 16:34:14.109738
1474 16:34:14.109789 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1475 16:34:14.109841
1476 16:34:14.109893 [CATrainingPosCal] consider 2 rank data
1477 16:34:14.109945 u2DelayCellTimex100 = 270/100 ps
1478 16:34:14.109998 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1479 16:34:14.110049 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 16:34:14.110102 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 16:34:14.110154 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1482 16:34:14.110206 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 16:34:14.110258 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1484 16:34:14.110309
1485 16:34:14.110360 CA PerBit enable=1, Macro0, CA PI delay=34
1486 16:34:14.110412
1487 16:34:14.110463 [CBTSetCACLKResult] CA Dly = 34
1488 16:34:14.110515 CS Dly: 5 (0~37)
1489 16:34:14.110566
1490 16:34:14.110618 ----->DramcWriteLeveling(PI) begin...
1491 16:34:14.110671 ==
1492 16:34:14.110723 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 16:34:14.110775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 16:34:14.110827 ==
1495 16:34:14.110880 Write leveling (Byte 0): 26 => 26
1496 16:34:14.110932 Write leveling (Byte 1): 28 => 28
1497 16:34:14.110983 DramcWriteLeveling(PI) end<-----
1498 16:34:14.111034
1499 16:34:14.111086 ==
1500 16:34:14.111138 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 16:34:14.111189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 16:34:14.111241 ==
1503 16:34:14.111293 [Gating] SW mode calibration
1504 16:34:14.111345 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1505 16:34:14.111397 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1506 16:34:14.111449 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1507 16:34:14.111501 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1508 16:34:14.111553 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 16:34:14.111605 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 16:34:14.111658 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 16:34:14.111709 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 16:34:14.111956 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 16:34:14.112015 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 16:34:14.112068 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 16:34:14.112121 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 16:34:14.112173 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 16:34:14.112226 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 16:34:14.112279 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 16:34:14.112331 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 16:34:14.112383 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 16:34:14.112435 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:34:14.112487 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:34:14.112539 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1524 16:34:14.112591 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:34:14.112644 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:34:14.112696 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:34:14.112747 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:34:14.112800 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:34:14.112852 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 16:34:14.112904 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 16:34:14.112955 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 16:34:14.113007 0 9 8 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
1533 16:34:14.113060 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 16:34:14.113111 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 16:34:14.113163 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 16:34:14.113214 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 16:34:14.113281 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 16:34:14.113344 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 16:34:14.113410 0 10 4 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 0)
1540 16:34:14.113472 0 10 8 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
1541 16:34:14.113559 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 16:34:14.113615 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 16:34:14.113668 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 16:34:14.113721 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 16:34:14.113774 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 16:34:14.113826 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 16:34:14.113878 0 11 4 | B1->B0 | 2929 3232 | 0 0 | (0 0) (0 0)
1548 16:34:14.113930 0 11 8 | B1->B0 | 3c3c 4040 | 0 0 | (1 1) (0 0)
1549 16:34:14.113981 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 16:34:14.114033 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 16:34:14.114086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 16:34:14.114138 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 16:34:14.114191 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 16:34:14.114242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 16:34:14.114294 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1556 16:34:14.114346 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1557 16:34:14.114397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 16:34:14.114449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 16:34:14.114501 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 16:34:14.114552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 16:34:14.114604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 16:34:14.114656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 16:34:14.114708 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 16:34:14.114759 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 16:34:14.114812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 16:34:14.114863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 16:34:14.114915 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 16:34:14.114967 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 16:34:14.115019 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 16:34:14.115071 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 16:34:14.115123 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1572 16:34:14.115174 Total UI for P1: 0, mck2ui 16
1573 16:34:14.115226 best dqsien dly found for B1: ( 0, 14, 2)
1574 16:34:14.115278 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1575 16:34:14.115331 Total UI for P1: 0, mck2ui 16
1576 16:34:14.115383 best dqsien dly found for B0: ( 0, 14, 4)
1577 16:34:14.115435 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1578 16:34:14.115487 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1579 16:34:14.115539
1580 16:34:14.115590 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1581 16:34:14.115642 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1582 16:34:14.115693 [Gating] SW calibration Done
1583 16:34:14.115745 ==
1584 16:34:14.115798 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 16:34:14.115850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 16:34:14.115902 ==
1587 16:34:14.115954 RX Vref Scan: 0
1588 16:34:14.116006
1589 16:34:14.116057 RX Vref 0 -> 0, step: 1
1590 16:34:14.116108
1591 16:34:14.116159 RX Delay -130 -> 252, step: 16
1592 16:34:14.116210 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1593 16:34:14.116263 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1594 16:34:14.116315 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1595 16:34:14.116366 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1596 16:34:14.116419 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1597 16:34:14.116470 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1598 16:34:14.116522 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1599 16:34:14.116573 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1600 16:34:14.116625 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1601 16:34:14.116676 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1602 16:34:14.116922 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1603 16:34:14.116980 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1604 16:34:14.117034 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1605 16:34:14.117086 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1606 16:34:14.117138 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1607 16:34:14.117189 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1608 16:34:14.117241 ==
1609 16:34:14.117326 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 16:34:14.117409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 16:34:14.117490 ==
1612 16:34:14.117572 DQS Delay:
1613 16:34:14.117653 DQS0 = 0, DQS1 = 0
1614 16:34:14.117734 DQM Delay:
1615 16:34:14.117815 DQM0 = 84, DQM1 = 79
1616 16:34:14.117896 DQ Delay:
1617 16:34:14.117978 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1618 16:34:14.118059 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =77
1619 16:34:14.118141 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1620 16:34:14.118222 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1621 16:34:14.118303
1622 16:34:14.118383
1623 16:34:14.118464 ==
1624 16:34:14.118545 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 16:34:14.118627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 16:34:14.118709 ==
1627 16:34:14.118790
1628 16:34:14.118870
1629 16:34:14.118953 TX Vref Scan disable
1630 16:34:14.119034 == TX Byte 0 ==
1631 16:34:14.119116 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1632 16:34:14.119198 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1633 16:34:14.119279 == TX Byte 1 ==
1634 16:34:14.119361 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1635 16:34:14.119443 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1636 16:34:14.119523 ==
1637 16:34:14.119605 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 16:34:14.119687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 16:34:14.119768 ==
1640 16:34:14.119850 TX Vref=22, minBit 1, minWin=27, winSum=443
1641 16:34:14.119932 TX Vref=24, minBit 4, minWin=27, winSum=446
1642 16:34:14.120014 TX Vref=26, minBit 4, minWin=27, winSum=453
1643 16:34:14.120096 TX Vref=28, minBit 5, minWin=27, winSum=455
1644 16:34:14.120178 TX Vref=30, minBit 1, minWin=28, winSum=457
1645 16:34:14.120260 TX Vref=32, minBit 5, minWin=27, winSum=451
1646 16:34:14.120343 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
1647 16:34:14.120424
1648 16:34:14.120505 Final TX Range 1 Vref 30
1649 16:34:14.120591
1650 16:34:14.120673 ==
1651 16:34:14.120755 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 16:34:14.120837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 16:34:14.120918 ==
1654 16:34:14.120999
1655 16:34:14.121079
1656 16:34:14.121160 TX Vref Scan disable
1657 16:34:14.121241 == TX Byte 0 ==
1658 16:34:14.121336 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1659 16:34:14.121420 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1660 16:34:14.121501 == TX Byte 1 ==
1661 16:34:14.121583 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1662 16:34:14.121665 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1663 16:34:14.121746
1664 16:34:14.121827 [DATLAT]
1665 16:34:14.121907 Freq=800, CH1 RK0
1666 16:34:14.121989
1667 16:34:14.122070 DATLAT Default: 0xa
1668 16:34:14.122151 0, 0xFFFF, sum = 0
1669 16:34:14.122235 1, 0xFFFF, sum = 0
1670 16:34:14.122318 2, 0xFFFF, sum = 0
1671 16:34:14.122405 3, 0xFFFF, sum = 0
1672 16:34:14.122489 4, 0xFFFF, sum = 0
1673 16:34:14.122584 5, 0xFFFF, sum = 0
1674 16:34:14.122673 6, 0xFFFF, sum = 0
1675 16:34:14.122733 7, 0xFFFF, sum = 0
1676 16:34:14.122786 8, 0xFFFF, sum = 0
1677 16:34:14.122839 9, 0x0, sum = 1
1678 16:34:14.122892 10, 0x0, sum = 2
1679 16:34:14.122945 11, 0x0, sum = 3
1680 16:34:14.122998 12, 0x0, sum = 4
1681 16:34:14.123073 best_step = 10
1682 16:34:14.123127
1683 16:34:14.123179 ==
1684 16:34:14.123245 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 16:34:14.123329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 16:34:14.123411 ==
1687 16:34:14.123503 RX Vref Scan: 1
1688 16:34:14.123585
1689 16:34:14.123674 Set Vref Range= 32 -> 127
1690 16:34:14.123755
1691 16:34:14.123846 RX Vref 32 -> 127, step: 1
1692 16:34:14.123928
1693 16:34:14.124010 RX Delay -95 -> 252, step: 8
1694 16:34:14.124091
1695 16:34:14.124172 Set Vref, RX VrefLevel [Byte0]: 32
1696 16:34:14.124254 [Byte1]: 32
1697 16:34:14.124335
1698 16:34:14.124417 Set Vref, RX VrefLevel [Byte0]: 33
1699 16:34:14.124499 [Byte1]: 33
1700 16:34:14.124580
1701 16:34:14.124661 Set Vref, RX VrefLevel [Byte0]: 34
1702 16:34:14.124742 [Byte1]: 34
1703 16:34:14.124824
1704 16:34:14.124905 Set Vref, RX VrefLevel [Byte0]: 35
1705 16:34:14.124987 [Byte1]: 35
1706 16:34:14.125067
1707 16:34:14.125148 Set Vref, RX VrefLevel [Byte0]: 36
1708 16:34:14.125230 [Byte1]: 36
1709 16:34:14.125337
1710 16:34:14.125425 Set Vref, RX VrefLevel [Byte0]: 37
1711 16:34:14.125480 [Byte1]: 37
1712 16:34:14.125557
1713 16:34:14.125613 Set Vref, RX VrefLevel [Byte0]: 38
1714 16:34:14.125666 [Byte1]: 38
1715 16:34:14.125743
1716 16:34:14.125827 Set Vref, RX VrefLevel [Byte0]: 39
1717 16:34:14.125909 [Byte1]: 39
1718 16:34:14.125991
1719 16:34:14.126072 Set Vref, RX VrefLevel [Byte0]: 40
1720 16:34:14.126163 [Byte1]: 40
1721 16:34:14.126246
1722 16:34:14.126336 Set Vref, RX VrefLevel [Byte0]: 41
1723 16:34:14.126419 [Byte1]: 41
1724 16:34:14.126500
1725 16:34:14.126582 Set Vref, RX VrefLevel [Byte0]: 42
1726 16:34:14.126664 [Byte1]: 42
1727 16:34:14.126745
1728 16:34:14.126826 Set Vref, RX VrefLevel [Byte0]: 43
1729 16:34:14.126907 [Byte1]: 43
1730 16:34:14.126988
1731 16:34:14.127069 Set Vref, RX VrefLevel [Byte0]: 44
1732 16:34:14.127150 [Byte1]: 44
1733 16:34:14.127238
1734 16:34:14.127320 Set Vref, RX VrefLevel [Byte0]: 45
1735 16:34:14.127413 [Byte1]: 45
1736 16:34:14.127504
1737 16:34:14.127592 Set Vref, RX VrefLevel [Byte0]: 46
1738 16:34:14.127685 [Byte1]: 46
1739 16:34:14.127767
1740 16:34:14.127849 Set Vref, RX VrefLevel [Byte0]: 47
1741 16:34:14.127931 [Byte1]: 47
1742 16:34:14.128012
1743 16:34:14.128093 Set Vref, RX VrefLevel [Byte0]: 48
1744 16:34:14.128175 [Byte1]: 48
1745 16:34:14.128256
1746 16:34:14.128337 Set Vref, RX VrefLevel [Byte0]: 49
1747 16:34:14.128419 [Byte1]: 49
1748 16:34:14.128500
1749 16:34:14.128581 Set Vref, RX VrefLevel [Byte0]: 50
1750 16:34:14.128663 [Byte1]: 50
1751 16:34:14.128744
1752 16:34:14.128825 Set Vref, RX VrefLevel [Byte0]: 51
1753 16:34:14.128907 [Byte1]: 51
1754 16:34:14.128988
1755 16:34:14.129070 Set Vref, RX VrefLevel [Byte0]: 52
1756 16:34:14.129152 [Byte1]: 52
1757 16:34:14.129233
1758 16:34:14.129310 Set Vref, RX VrefLevel [Byte0]: 53
1759 16:34:14.129364 [Byte1]: 53
1760 16:34:14.129416
1761 16:34:14.129467 Set Vref, RX VrefLevel [Byte0]: 54
1762 16:34:14.129519 [Byte1]: 54
1763 16:34:14.129570
1764 16:34:14.129622 Set Vref, RX VrefLevel [Byte0]: 55
1765 16:34:14.129673 [Byte1]: 55
1766 16:34:14.129725
1767 16:34:14.129979 Set Vref, RX VrefLevel [Byte0]: 56
1768 16:34:14.130043 [Byte1]: 56
1769 16:34:14.130096
1770 16:34:14.130148 Set Vref, RX VrefLevel [Byte0]: 57
1771 16:34:14.130201 [Byte1]: 57
1772 16:34:14.130253
1773 16:34:14.130305 Set Vref, RX VrefLevel [Byte0]: 58
1774 16:34:14.130361 [Byte1]: 58
1775 16:34:14.130450
1776 16:34:14.130533 Set Vref, RX VrefLevel [Byte0]: 59
1777 16:34:14.130614 [Byte1]: 59
1778 16:34:14.130695
1779 16:34:14.130776 Set Vref, RX VrefLevel [Byte0]: 60
1780 16:34:14.130858 [Byte1]: 60
1781 16:34:14.130938
1782 16:34:14.131019 Set Vref, RX VrefLevel [Byte0]: 61
1783 16:34:14.131075 [Byte1]: 61
1784 16:34:14.131128
1785 16:34:14.131180 Set Vref, RX VrefLevel [Byte0]: 62
1786 16:34:14.131232 [Byte1]: 62
1787 16:34:14.131284
1788 16:34:14.131336 Set Vref, RX VrefLevel [Byte0]: 63
1789 16:34:14.131388 [Byte1]: 63
1790 16:34:14.131440
1791 16:34:14.131492 Set Vref, RX VrefLevel [Byte0]: 64
1792 16:34:14.131544 [Byte1]: 64
1793 16:34:14.131596
1794 16:34:14.131647 Set Vref, RX VrefLevel [Byte0]: 65
1795 16:34:14.131699 [Byte1]: 65
1796 16:34:14.131752
1797 16:34:14.131803 Set Vref, RX VrefLevel [Byte0]: 66
1798 16:34:14.131855 [Byte1]: 66
1799 16:34:14.131906
1800 16:34:14.131958 Set Vref, RX VrefLevel [Byte0]: 67
1801 16:34:14.132010 [Byte1]: 67
1802 16:34:14.132061
1803 16:34:14.132112 Set Vref, RX VrefLevel [Byte0]: 68
1804 16:34:14.132164 [Byte1]: 68
1805 16:34:14.132216
1806 16:34:14.132267 Set Vref, RX VrefLevel [Byte0]: 69
1807 16:34:14.132318 [Byte1]: 69
1808 16:34:14.132370
1809 16:34:14.132422 Set Vref, RX VrefLevel [Byte0]: 70
1810 16:34:14.132473 [Byte1]: 70
1811 16:34:14.132524
1812 16:34:14.132576 Set Vref, RX VrefLevel [Byte0]: 71
1813 16:34:14.132628 [Byte1]: 71
1814 16:34:14.132679
1815 16:34:14.132731 Set Vref, RX VrefLevel [Byte0]: 72
1816 16:34:14.132782 [Byte1]: 72
1817 16:34:14.132834
1818 16:34:14.132885 Set Vref, RX VrefLevel [Byte0]: 73
1819 16:34:14.132937 [Byte1]: 73
1820 16:34:14.132989
1821 16:34:14.133041 Set Vref, RX VrefLevel [Byte0]: 74
1822 16:34:14.133092 [Byte1]: 74
1823 16:34:14.133148
1824 16:34:14.133201 Final RX Vref Byte 0 = 56 to rank0
1825 16:34:14.133254 Final RX Vref Byte 1 = 52 to rank0
1826 16:34:14.133314 Final RX Vref Byte 0 = 56 to rank1
1827 16:34:14.133366 Final RX Vref Byte 1 = 52 to rank1==
1828 16:34:14.133419 Dram Type= 6, Freq= 0, CH_1, rank 0
1829 16:34:14.133471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 16:34:14.133524 ==
1831 16:34:14.133577 DQS Delay:
1832 16:34:14.133629 DQS0 = 0, DQS1 = 0
1833 16:34:14.133681 DQM Delay:
1834 16:34:14.133733 DQM0 = 85, DQM1 = 80
1835 16:34:14.133810 DQ Delay:
1836 16:34:14.133865 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1837 16:34:14.133918 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1838 16:34:14.133971 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1839 16:34:14.134023 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1840 16:34:14.134075
1841 16:34:14.134126
1842 16:34:14.134177 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c30, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1843 16:34:14.134231 CH1 RK0: MR19=606, MR18=1C30
1844 16:34:14.134283 CH1_RK0: MR19=0x606, MR18=0x1C30, DQSOSC=397, MR23=63, INC=93, DEC=62
1845 16:34:14.134335
1846 16:34:14.134390 ----->DramcWriteLeveling(PI) begin...
1847 16:34:14.134454 ==
1848 16:34:14.134507 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 16:34:14.134560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 16:34:14.134612 ==
1851 16:34:14.134664 Write leveling (Byte 0): 27 => 27
1852 16:34:14.134741 Write leveling (Byte 1): 29 => 29
1853 16:34:14.134823 DramcWriteLeveling(PI) end<-----
1854 16:34:14.134905
1855 16:34:14.134986 ==
1856 16:34:14.135065 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 16:34:14.135141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 16:34:14.135218 ==
1859 16:34:14.135294 [Gating] SW mode calibration
1860 16:34:14.135369 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1861 16:34:14.135446 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1862 16:34:14.135520 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1863 16:34:14.135594 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1864 16:34:14.135668 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1865 16:34:14.135743 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 16:34:14.135818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 16:34:14.135894 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 16:34:14.135968 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 16:34:14.136041 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 16:34:14.136114 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 16:34:14.136187 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 16:34:14.136258 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 16:34:14.136330 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 16:34:14.136403 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 16:34:14.136479 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 16:34:14.136555 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 16:34:14.136631 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 16:34:14.136708 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1879 16:34:14.136784 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1880 16:34:14.136859 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1881 16:34:14.136933 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:34:14.137009 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:34:14.137085 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:34:14.137162 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:34:14.137289 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:34:14.137351 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:34:14.137408 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1888 16:34:14.137462 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1889 16:34:14.137519 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 16:34:14.137620 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 16:34:14.137935 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 16:34:14.138036 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 16:34:14.138129 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 16:34:14.138206 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1895 16:34:14.138271 0 10 4 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
1896 16:34:14.138361 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1897 16:34:14.138455 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 16:34:14.138540 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 16:34:14.138619 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 16:34:14.138702 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 16:34:14.138781 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 16:34:14.138859 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 16:34:14.138941 0 11 4 | B1->B0 | 2828 3a3a | 1 0 | (0 0) (0 0)
1904 16:34:14.139020 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1905 16:34:14.139097 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 16:34:14.139174 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 16:34:14.139252 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 16:34:14.139343 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 16:34:14.139430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 16:34:14.139529 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1911 16:34:14.139615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1912 16:34:14.139711 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1913 16:34:14.139796 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 16:34:14.139879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 16:34:14.139962 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 16:34:14.140047 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 16:34:14.140130 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 16:34:14.140212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 16:34:14.140297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 16:34:14.140380 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 16:34:14.140464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 16:34:14.140548 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 16:34:14.140630 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 16:34:14.140712 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 16:34:14.140795 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 16:34:14.140876 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1927 16:34:14.140959 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1928 16:34:14.141042 Total UI for P1: 0, mck2ui 16
1929 16:34:14.141126 best dqsien dly found for B0: ( 0, 14, 0)
1930 16:34:14.141212 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 16:34:14.141309 Total UI for P1: 0, mck2ui 16
1932 16:34:14.141366 best dqsien dly found for B1: ( 0, 14, 4)
1933 16:34:14.141421 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1934 16:34:14.141476 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1935 16:34:14.141529
1936 16:34:14.141581 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1937 16:34:14.141634 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1938 16:34:14.141689 [Gating] SW calibration Done
1939 16:34:14.141742 ==
1940 16:34:14.141794 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 16:34:14.141848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 16:34:14.141906 ==
1943 16:34:14.142000 RX Vref Scan: 0
1944 16:34:14.142098
1945 16:34:14.142181 RX Vref 0 -> 0, step: 1
1946 16:34:14.142263
1947 16:34:14.142351 RX Delay -130 -> 252, step: 16
1948 16:34:14.142440 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1949 16:34:14.142524 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1950 16:34:14.142610 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1951 16:34:14.142667 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1952 16:34:14.142735 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1953 16:34:14.142790 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1954 16:34:14.142843 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1955 16:34:14.142896 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1956 16:34:14.142948 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1957 16:34:14.143000 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1958 16:34:14.143053 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1959 16:34:14.143105 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1960 16:34:14.143158 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1961 16:34:14.143210 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1962 16:34:14.143271 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1963 16:34:14.143353 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1964 16:34:14.143428 ==
1965 16:34:14.143482 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 16:34:14.143536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 16:34:14.143589 ==
1968 16:34:14.143642 DQS Delay:
1969 16:34:14.143727 DQS0 = 0, DQS1 = 0
1970 16:34:14.143826 DQM Delay:
1971 16:34:14.143917 DQM0 = 81, DQM1 = 80
1972 16:34:14.143998 DQ Delay:
1973 16:34:14.144089 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1974 16:34:14.144189 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1975 16:34:14.144275 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1976 16:34:14.144370 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1977 16:34:14.144460
1978 16:34:14.144548
1979 16:34:14.144637 ==
1980 16:34:14.144725 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 16:34:14.144812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 16:34:14.144898 ==
1983 16:34:14.144986
1984 16:34:14.443460
1985 16:34:14.443639 TX Vref Scan disable
1986 16:34:14.443784 == TX Byte 0 ==
1987 16:34:14.443895 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1988 16:34:14.443972 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1989 16:34:14.444044 == TX Byte 1 ==
1990 16:34:14.444112 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1991 16:34:14.444179 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1992 16:34:14.444298 ==
1993 16:34:14.444407 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 16:34:14.444493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 16:34:14.444571 ==
1996 16:34:14.444646 TX Vref=22, minBit 6, minWin=27, winSum=450
1997 16:34:14.444713 TX Vref=24, minBit 1, minWin=27, winSum=451
1998 16:34:14.445007 TX Vref=26, minBit 0, minWin=28, winSum=453
1999 16:34:14.445083 TX Vref=28, minBit 0, minWin=28, winSum=454
2000 16:34:14.445151 TX Vref=30, minBit 0, minWin=27, winSum=453
2001 16:34:14.445246 TX Vref=32, minBit 5, minWin=27, winSum=455
2002 16:34:14.445344 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
2003 16:34:14.445413
2004 16:34:14.445478 Final TX Range 1 Vref 28
2005 16:34:14.445552
2006 16:34:14.445626 ==
2007 16:34:14.445708 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 16:34:14.445808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 16:34:14.445922 ==
2010 16:34:14.446034
2011 16:34:14.446151
2012 16:34:14.446252 TX Vref Scan disable
2013 16:34:14.446359 == TX Byte 0 ==
2014 16:34:14.446459 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 16:34:14.446566 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 16:34:14.446666 == TX Byte 1 ==
2017 16:34:14.446772 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2018 16:34:14.446875 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2019 16:34:14.446979
2020 16:34:14.447083 [DATLAT]
2021 16:34:14.447185 Freq=800, CH1 RK1
2022 16:34:14.447289
2023 16:34:14.447389 DATLAT Default: 0xa
2024 16:34:14.447490 0, 0xFFFF, sum = 0
2025 16:34:14.447592 1, 0xFFFF, sum = 0
2026 16:34:14.447695 2, 0xFFFF, sum = 0
2027 16:34:14.447797 3, 0xFFFF, sum = 0
2028 16:34:14.447899 4, 0xFFFF, sum = 0
2029 16:34:14.448000 5, 0xFFFF, sum = 0
2030 16:34:14.448101 6, 0xFFFF, sum = 0
2031 16:34:14.448202 7, 0xFFFF, sum = 0
2032 16:34:14.448303 8, 0xFFFF, sum = 0
2033 16:34:14.448404 9, 0x0, sum = 1
2034 16:34:14.448505 10, 0x0, sum = 2
2035 16:34:14.448608 11, 0x0, sum = 3
2036 16:34:14.448677 12, 0x0, sum = 4
2037 16:34:14.448771 best_step = 10
2038 16:34:14.448879
2039 16:34:14.448983 ==
2040 16:34:14.449085 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 16:34:14.449191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 16:34:14.449304 ==
2043 16:34:14.449375 RX Vref Scan: 0
2044 16:34:14.449476
2045 16:34:14.449543 RX Vref 0 -> 0, step: 1
2046 16:34:14.449607
2047 16:34:14.449670 RX Delay -95 -> 252, step: 8
2048 16:34:14.449733 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2049 16:34:14.449797 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2050 16:34:14.449860 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2051 16:34:14.449924 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2052 16:34:14.449987 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2053 16:34:14.450050 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2054 16:34:14.450114 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2055 16:34:14.450176 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2056 16:34:14.450239 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2057 16:34:14.450301 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2058 16:34:14.450365 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2059 16:34:14.450427 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2060 16:34:14.450491 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2061 16:34:14.450553 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2062 16:34:14.450616 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2063 16:34:14.450679 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2064 16:34:14.450742 ==
2065 16:34:14.450804 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 16:34:14.450866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 16:34:14.450929 ==
2068 16:34:14.450992 DQS Delay:
2069 16:34:14.451054 DQS0 = 0, DQS1 = 0
2070 16:34:14.451117 DQM Delay:
2071 16:34:14.451179 DQM0 = 87, DQM1 = 81
2072 16:34:14.451242 DQ Delay:
2073 16:34:14.451346 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2074 16:34:14.451451 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2075 16:34:14.451559 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2076 16:34:14.451668 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
2077 16:34:14.451774
2078 16:34:14.451891
2079 16:34:14.452000 [DQSOSCAuto] RK1, (LSB)MR18= 0x2540, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2080 16:34:14.452121 CH1 RK1: MR19=606, MR18=2540
2081 16:34:14.452232 CH1_RK1: MR19=0x606, MR18=0x2540, DQSOSC=393, MR23=63, INC=95, DEC=63
2082 16:34:14.452349 [RxdqsGatingPostProcess] freq 800
2083 16:34:14.452467 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2084 16:34:14.452578 Pre-setting of DQS Precalculation
2085 16:34:14.452694 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2086 16:34:14.452812 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2087 16:34:14.452918 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2088 16:34:14.453018
2089 16:34:14.453117
2090 16:34:14.453220 [Calibration Summary] 1600 Mbps
2091 16:34:14.453342 CH 0, Rank 0
2092 16:34:14.453450 SW Impedance : PASS
2093 16:34:14.453560 DUTY Scan : NO K
2094 16:34:14.453670 ZQ Calibration : PASS
2095 16:34:14.453747 Jitter Meter : NO K
2096 16:34:14.453857 CBT Training : PASS
2097 16:34:14.453925 Write leveling : PASS
2098 16:34:14.453989 RX DQS gating : PASS
2099 16:34:14.454087 RX DQ/DQS(RDDQC) : PASS
2100 16:34:14.454207 TX DQ/DQS : PASS
2101 16:34:14.454320 RX DATLAT : PASS
2102 16:34:14.454424 RX DQ/DQS(Engine): PASS
2103 16:34:14.454539 TX OE : NO K
2104 16:34:14.454654 All Pass.
2105 16:34:14.454759
2106 16:34:14.454863 CH 0, Rank 1
2107 16:34:14.454968 SW Impedance : PASS
2108 16:34:14.455072 DUTY Scan : NO K
2109 16:34:14.455184 ZQ Calibration : PASS
2110 16:34:14.455285 Jitter Meter : NO K
2111 16:34:14.455385 CBT Training : PASS
2112 16:34:14.455484 Write leveling : PASS
2113 16:34:14.455583 RX DQS gating : PASS
2114 16:34:14.455683 RX DQ/DQS(RDDQC) : PASS
2115 16:34:14.455790 TX DQ/DQS : PASS
2116 16:34:14.455892 RX DATLAT : PASS
2117 16:34:14.455991 RX DQ/DQS(Engine): PASS
2118 16:34:14.456091 TX OE : NO K
2119 16:34:14.456192 All Pass.
2120 16:34:14.456292
2121 16:34:14.456391 CH 1, Rank 0
2122 16:34:14.456497 SW Impedance : PASS
2123 16:34:14.456602 DUTY Scan : NO K
2124 16:34:14.456706 ZQ Calibration : PASS
2125 16:34:14.456813 Jitter Meter : NO K
2126 16:34:14.456917 CBT Training : PASS
2127 16:34:14.457023 Write leveling : PASS
2128 16:34:14.457128 RX DQS gating : PASS
2129 16:34:14.457229 RX DQ/DQS(RDDQC) : PASS
2130 16:34:14.457363 TX DQ/DQS : PASS
2131 16:34:14.457467 RX DATLAT : PASS
2132 16:34:14.457569 RX DQ/DQS(Engine): PASS
2133 16:34:14.457669 TX OE : NO K
2134 16:34:14.457769 All Pass.
2135 16:34:14.457868
2136 16:34:14.457935 CH 1, Rank 1
2137 16:34:14.458000 SW Impedance : PASS
2138 16:34:14.458064 DUTY Scan : NO K
2139 16:34:14.458159 ZQ Calibration : PASS
2140 16:34:14.458260 Jitter Meter : NO K
2141 16:34:14.458360 CBT Training : PASS
2142 16:34:14.458459 Write leveling : PASS
2143 16:34:14.458562 RX DQS gating : PASS
2144 16:34:14.458663 RX DQ/DQS(RDDQC) : PASS
2145 16:34:14.458763 TX DQ/DQS : PASS
2146 16:34:14.458867 RX DATLAT : PASS
2147 16:34:14.458967 RX DQ/DQS(Engine): PASS
2148 16:34:14.459066 TX OE : NO K
2149 16:34:14.459187 All Pass.
2150 16:34:14.459257
2151 16:34:14.459321 DramC Write-DBI off
2152 16:34:14.459615 PER_BANK_REFRESH: Hybrid Mode
2153 16:34:14.459726 TX_TRACKING: ON
2154 16:34:14.459833 [GetDramInforAfterCalByMRR] Vendor 6.
2155 16:34:14.459939 [GetDramInforAfterCalByMRR] Revision 606.
2156 16:34:14.460041 [GetDramInforAfterCalByMRR] Revision 2 0.
2157 16:34:14.460141 MR0 0x3b3b
2158 16:34:14.460240 MR8 0x5151
2159 16:34:14.460341 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 16:34:14.460440
2161 16:34:14.460538 MR0 0x3b3b
2162 16:34:14.460637 MR8 0x5151
2163 16:34:14.460736 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 16:34:14.460835
2165 16:34:14.460936 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2166 16:34:14.461038 [FAST_K] Save calibration result to emmc
2167 16:34:14.461138 [FAST_K] Save calibration result to emmc
2168 16:34:14.461245 dram_init: config_dvfs: 1
2169 16:34:14.461375 dramc_set_vcore_voltage set vcore to 662500
2170 16:34:14.461490 Read voltage for 1200, 2
2171 16:34:14.461597 Vio18 = 0
2172 16:34:14.461708 Vcore = 662500
2173 16:34:14.461820 Vdram = 0
2174 16:34:14.461927 Vddq = 0
2175 16:34:14.462032 Vmddr = 0
2176 16:34:14.462141 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2177 16:34:14.462254 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2178 16:34:14.462358 MEM_TYPE=3, freq_sel=15
2179 16:34:14.462459 sv_algorithm_assistance_LP4_1600
2180 16:34:14.462546 ============ PULL DRAM RESETB DOWN ============
2181 16:34:14.462614 ========== PULL DRAM RESETB DOWN end =========
2182 16:34:14.462679 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 16:34:14.462744 ===================================
2184 16:34:14.462808 LPDDR4 DRAM CONFIGURATION
2185 16:34:14.462877 ===================================
2186 16:34:14.462959 EX_ROW_EN[0] = 0x0
2187 16:34:14.463024 EX_ROW_EN[1] = 0x0
2188 16:34:14.463089 LP4Y_EN = 0x0
2189 16:34:14.463153 WORK_FSP = 0x0
2190 16:34:14.463216 WL = 0x4
2191 16:34:14.463279 RL = 0x4
2192 16:34:14.463343 BL = 0x2
2193 16:34:14.463414 RPST = 0x0
2194 16:34:14.463509 RD_PRE = 0x0
2195 16:34:14.463611 WR_PRE = 0x1
2196 16:34:14.463714 WR_PST = 0x0
2197 16:34:14.463824 DBI_WR = 0x0
2198 16:34:14.463943 DBI_RD = 0x0
2199 16:34:14.464061 OTF = 0x1
2200 16:34:14.464179 ===================================
2201 16:34:14.464287 ===================================
2202 16:34:14.464388 ANA top config
2203 16:34:14.464489 ===================================
2204 16:34:14.464602 DLL_ASYNC_EN = 0
2205 16:34:14.464703 ALL_SLAVE_EN = 0
2206 16:34:14.464803 NEW_RANK_MODE = 1
2207 16:34:14.464904 DLL_IDLE_MODE = 1
2208 16:34:14.465005 LP45_APHY_COMB_EN = 1
2209 16:34:14.465104 TX_ODT_DIS = 1
2210 16:34:14.465205 NEW_8X_MODE = 1
2211 16:34:14.465317 ===================================
2212 16:34:14.465385 ===================================
2213 16:34:14.465451 data_rate = 2400
2214 16:34:14.465515 CKR = 1
2215 16:34:14.465579 DQ_P2S_RATIO = 8
2216 16:34:14.465643 ===================================
2217 16:34:14.465707 CA_P2S_RATIO = 8
2218 16:34:14.465791 DQ_CA_OPEN = 0
2219 16:34:14.465859 DQ_SEMI_OPEN = 0
2220 16:34:14.465948 CA_SEMI_OPEN = 0
2221 16:34:14.466062 CA_FULL_RATE = 0
2222 16:34:14.466165 DQ_CKDIV4_EN = 0
2223 16:34:14.466279 CA_CKDIV4_EN = 0
2224 16:34:14.466364 CA_PREDIV_EN = 0
2225 16:34:14.466430 PH8_DLY = 17
2226 16:34:14.466494 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2227 16:34:14.466576 DQ_AAMCK_DIV = 4
2228 16:34:14.466681 CA_AAMCK_DIV = 4
2229 16:34:14.466800 CA_ADMCK_DIV = 4
2230 16:34:14.466905 DQ_TRACK_CA_EN = 0
2231 16:34:14.467013 CA_PICK = 1200
2232 16:34:14.467134 CA_MCKIO = 1200
2233 16:34:14.467258 MCKIO_SEMI = 0
2234 16:34:14.467378 PLL_FREQ = 2366
2235 16:34:14.467484 DQ_UI_PI_RATIO = 32
2236 16:34:14.467590 CA_UI_PI_RATIO = 0
2237 16:34:14.467698 ===================================
2238 16:34:14.467809 ===================================
2239 16:34:14.467919 memory_type:LPDDR4
2240 16:34:14.468021 GP_NUM : 10
2241 16:34:14.468123 SRAM_EN : 1
2242 16:34:14.468223 MD32_EN : 0
2243 16:34:14.468324 ===================================
2244 16:34:14.468425 [ANA_INIT] >>>>>>>>>>>>>>
2245 16:34:14.468525 <<<<<< [CONFIGURE PHASE]: ANA_TX
2246 16:34:14.468626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2247 16:34:14.468742 ===================================
2248 16:34:14.468833 data_rate = 2400,PCW = 0X5b00
2249 16:34:14.468923 ===================================
2250 16:34:14.469014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2251 16:34:14.469106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 16:34:14.469197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 16:34:14.469331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2254 16:34:14.469424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2255 16:34:14.469515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2256 16:34:14.469624 [ANA_INIT] flow start
2257 16:34:14.469694 [ANA_INIT] PLL >>>>>>>>
2258 16:34:14.469754 [ANA_INIT] PLL <<<<<<<<
2259 16:34:14.469811 [ANA_INIT] MIDPI >>>>>>>>
2260 16:34:14.469869 [ANA_INIT] MIDPI <<<<<<<<
2261 16:34:14.469926 [ANA_INIT] DLL >>>>>>>>
2262 16:34:14.470015 [ANA_INIT] DLL <<<<<<<<
2263 16:34:14.470076 [ANA_INIT] flow end
2264 16:34:14.470135 ============ LP4 DIFF to SE enter ============
2265 16:34:14.470195 ============ LP4 DIFF to SE exit ============
2266 16:34:14.470254 [ANA_INIT] <<<<<<<<<<<<<
2267 16:34:14.470313 [Flow] Enable top DCM control >>>>>
2268 16:34:14.470414 [Flow] Enable top DCM control <<<<<
2269 16:34:14.470493 Enable DLL master slave shuffle
2270 16:34:14.470561 ==============================================================
2271 16:34:14.470652 Gating Mode config
2272 16:34:14.470713 ==============================================================
2273 16:34:14.470772 Config description:
2274 16:34:14.470830 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2275 16:34:14.470889 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2276 16:34:14.471160 SELPH_MODE 0: By rank 1: By Phase
2277 16:34:14.471227 ==============================================================
2278 16:34:14.471288 GAT_TRACK_EN = 1
2279 16:34:14.471347 RX_GATING_MODE = 2
2280 16:34:14.471405 RX_GATING_TRACK_MODE = 2
2281 16:34:14.471462 SELPH_MODE = 1
2282 16:34:14.471519 PICG_EARLY_EN = 1
2283 16:34:14.471577 VALID_LAT_VALUE = 1
2284 16:34:14.471635 ==============================================================
2285 16:34:14.471693 Enter into Gating configuration >>>>
2286 16:34:14.471750 Exit from Gating configuration <<<<
2287 16:34:14.471807 Enter into DVFS_PRE_config >>>>>
2288 16:34:14.471864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2289 16:34:14.471923 Exit from DVFS_PRE_config <<<<<
2290 16:34:14.471980 Enter into PICG configuration >>>>
2291 16:34:14.472038 Exit from PICG configuration <<<<
2292 16:34:14.472095 [RX_INPUT] configuration >>>>>
2293 16:34:14.472157 [RX_INPUT] configuration <<<<<
2294 16:34:14.472229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2295 16:34:14.472289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2296 16:34:14.472348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 16:34:14.472406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 16:34:14.472464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 16:34:14.472521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 16:34:14.472579 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2301 16:34:14.472636 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2302 16:34:14.472703 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2303 16:34:14.472762 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2304 16:34:14.472845 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2305 16:34:14.472947 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 16:34:14.473045 ===================================
2307 16:34:14.473135 LPDDR4 DRAM CONFIGURATION
2308 16:34:14.473225 ===================================
2309 16:34:14.473311 EX_ROW_EN[0] = 0x0
2310 16:34:14.473389 EX_ROW_EN[1] = 0x0
2311 16:34:14.473448 LP4Y_EN = 0x0
2312 16:34:14.473506 WORK_FSP = 0x0
2313 16:34:14.473563 WL = 0x4
2314 16:34:14.473620 RL = 0x4
2315 16:34:14.473677 BL = 0x2
2316 16:34:14.473734 RPST = 0x0
2317 16:34:14.473801 RD_PRE = 0x0
2318 16:34:14.473867 WR_PRE = 0x1
2319 16:34:14.473920 WR_PST = 0x0
2320 16:34:14.473972 DBI_WR = 0x0
2321 16:34:14.474028 DBI_RD = 0x0
2322 16:34:14.474084 OTF = 0x1
2323 16:34:14.474136 ===================================
2324 16:34:14.474189 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2325 16:34:14.474242 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2326 16:34:14.474295 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 16:34:14.474347 ===================================
2328 16:34:14.474399 LPDDR4 DRAM CONFIGURATION
2329 16:34:14.474451 ===================================
2330 16:34:14.474504 EX_ROW_EN[0] = 0x10
2331 16:34:14.474556 EX_ROW_EN[1] = 0x0
2332 16:34:14.474607 LP4Y_EN = 0x0
2333 16:34:14.474659 WORK_FSP = 0x0
2334 16:34:14.474711 WL = 0x4
2335 16:34:14.474764 RL = 0x4
2336 16:34:14.474815 BL = 0x2
2337 16:34:14.474867 RPST = 0x0
2338 16:34:14.474919 RD_PRE = 0x0
2339 16:34:14.474970 WR_PRE = 0x1
2340 16:34:14.475022 WR_PST = 0x0
2341 16:34:14.475073 DBI_WR = 0x0
2342 16:34:14.475125 DBI_RD = 0x0
2343 16:34:14.475176 OTF = 0x1
2344 16:34:14.475229 ===================================
2345 16:34:14.475281 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2346 16:34:14.475333 ==
2347 16:34:14.475385 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 16:34:14.475438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2349 16:34:14.475502 ==
2350 16:34:14.475556 [Duty_Offset_Calibration]
2351 16:34:14.475608 B0:2 B1:0 CA:4
2352 16:34:14.475660
2353 16:34:14.475726 [DutyScan_Calibration_Flow] k_type=0
2354 16:34:14.475787
2355 16:34:14.475840 ==CLK 0==
2356 16:34:14.475919 Final CLK duty delay cell = 0
2357 16:34:14.476002 [0] MAX Duty = 5156%(X100), DQS PI = 14
2358 16:34:14.476094 [0] MIN Duty = 4969%(X100), DQS PI = 8
2359 16:34:14.476178 [0] AVG Duty = 5062%(X100)
2360 16:34:14.476263
2361 16:34:14.476320 CH0 CLK Duty spec in!! Max-Min= 187%
2362 16:34:14.476374 [DutyScan_Calibration_Flow] ====Done====
2363 16:34:14.476426
2364 16:34:14.476500 [DutyScan_Calibration_Flow] k_type=1
2365 16:34:14.476563
2366 16:34:14.476656 ==DQS 0 ==
2367 16:34:14.476746 Final DQS duty delay cell = 0
2368 16:34:14.476830 [0] MAX Duty = 5156%(X100), DQS PI = 18
2369 16:34:14.476926 [0] MIN Duty = 5093%(X100), DQS PI = 0
2370 16:34:14.477009 [0] AVG Duty = 5124%(X100)
2371 16:34:14.477091
2372 16:34:14.477171 ==DQS 1 ==
2373 16:34:14.477253 Final DQS duty delay cell = 0
2374 16:34:14.477324 [0] MAX Duty = 5125%(X100), DQS PI = 52
2375 16:34:14.477377 [0] MIN Duty = 5000%(X100), DQS PI = 0
2376 16:34:14.477429 [0] AVG Duty = 5062%(X100)
2377 16:34:14.477480
2378 16:34:14.477532 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2379 16:34:14.477584
2380 16:34:14.477635 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2381 16:34:14.477686 [DutyScan_Calibration_Flow] ====Done====
2382 16:34:14.477737
2383 16:34:14.477817 [DutyScan_Calibration_Flow] k_type=3
2384 16:34:14.477901
2385 16:34:14.477956 ==DQM 0 ==
2386 16:34:14.478009 Final DQM duty delay cell = 0
2387 16:34:14.478061 [0] MAX Duty = 5094%(X100), DQS PI = 20
2388 16:34:14.478113 [0] MIN Duty = 4844%(X100), DQS PI = 44
2389 16:34:14.478165 [0] AVG Duty = 4969%(X100)
2390 16:34:14.478216
2391 16:34:14.478268 ==DQM 1 ==
2392 16:34:14.478319 Final DQM duty delay cell = 0
2393 16:34:14.478372 [0] MAX Duty = 4969%(X100), DQS PI = 4
2394 16:34:14.478423 [0] MIN Duty = 4875%(X100), DQS PI = 12
2395 16:34:14.478475 [0] AVG Duty = 4922%(X100)
2396 16:34:14.478526
2397 16:34:14.478576 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2398 16:34:14.478630
2399 16:34:14.478682 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2400 16:34:14.478746 [DutyScan_Calibration_Flow] ====Done====
2401 16:34:14.478797
2402 16:34:14.478847 [DutyScan_Calibration_Flow] k_type=2
2403 16:34:14.478897
2404 16:34:14.478948 ==DQ 0 ==
2405 16:34:14.478999 Final DQ duty delay cell = 0
2406 16:34:14.479050 [0] MAX Duty = 5156%(X100), DQS PI = 18
2407 16:34:14.479306 [0] MIN Duty = 4969%(X100), DQS PI = 50
2408 16:34:14.479379 [0] AVG Duty = 5062%(X100)
2409 16:34:14.479432
2410 16:34:14.479514 ==DQ 1 ==
2411 16:34:14.479596 Final DQ duty delay cell = 0
2412 16:34:14.479648 [0] MAX Duty = 5125%(X100), DQS PI = 4
2413 16:34:14.479699 [0] MIN Duty = 4938%(X100), DQS PI = 0
2414 16:34:14.479750 [0] AVG Duty = 5031%(X100)
2415 16:34:14.479837
2416 16:34:14.479889 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2417 16:34:14.479963
2418 16:34:14.480053 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2419 16:34:14.480133 [DutyScan_Calibration_Flow] ====Done====
2420 16:34:14.480212 ==
2421 16:34:14.480292 Dram Type= 6, Freq= 0, CH_1, rank 0
2422 16:34:14.480372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2423 16:34:14.480452 ==
2424 16:34:14.480531 [Duty_Offset_Calibration]
2425 16:34:14.480611 B0:0 B1:-1 CA:3
2426 16:34:14.480690
2427 16:34:14.480769 [DutyScan_Calibration_Flow] k_type=0
2428 16:34:14.480848
2429 16:34:14.480927 ==CLK 0==
2430 16:34:14.481006 Final CLK duty delay cell = 0
2431 16:34:14.481087 [0] MAX Duty = 5187%(X100), DQS PI = 32
2432 16:34:14.481166 [0] MIN Duty = 5000%(X100), DQS PI = 2
2433 16:34:14.481246 [0] AVG Duty = 5093%(X100)
2434 16:34:14.481348
2435 16:34:14.481400 CH1 CLK Duty spec in!! Max-Min= 187%
2436 16:34:14.481451 [DutyScan_Calibration_Flow] ====Done====
2437 16:34:14.481501
2438 16:34:14.481552 [DutyScan_Calibration_Flow] k_type=1
2439 16:34:14.481602
2440 16:34:14.481652 ==DQS 0 ==
2441 16:34:14.481702 Final DQS duty delay cell = 0
2442 16:34:14.481753 [0] MAX Duty = 5156%(X100), DQS PI = 50
2443 16:34:14.481804 [0] MIN Duty = 4907%(X100), DQS PI = 6
2444 16:34:14.481855 [0] AVG Duty = 5031%(X100)
2445 16:34:14.481904
2446 16:34:14.481954 ==DQS 1 ==
2447 16:34:14.482005 Final DQS duty delay cell = 0
2448 16:34:14.482056 [0] MAX Duty = 5156%(X100), DQS PI = 28
2449 16:34:14.482106 [0] MIN Duty = 5000%(X100), DQS PI = 52
2450 16:34:14.482156 [0] AVG Duty = 5078%(X100)
2451 16:34:14.482206
2452 16:34:14.482256 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2453 16:34:14.482307
2454 16:34:14.482357 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2455 16:34:14.482407 [DutyScan_Calibration_Flow] ====Done====
2456 16:34:14.482457
2457 16:34:14.482525 [DutyScan_Calibration_Flow] k_type=3
2458 16:34:14.482577
2459 16:34:14.482628 ==DQM 0 ==
2460 16:34:14.482678 Final DQM duty delay cell = 0
2461 16:34:14.482728 [0] MAX Duty = 5031%(X100), DQS PI = 60
2462 16:34:14.482779 [0] MIN Duty = 4782%(X100), DQS PI = 6
2463 16:34:14.482829 [0] AVG Duty = 4906%(X100)
2464 16:34:14.482880
2465 16:34:14.482930 ==DQM 1 ==
2466 16:34:14.482985 Final DQM duty delay cell = 0
2467 16:34:14.483037 [0] MAX Duty = 4969%(X100), DQS PI = 2
2468 16:34:14.483087 [0] MIN Duty = 4844%(X100), DQS PI = 48
2469 16:34:14.483144 [0] AVG Duty = 4906%(X100)
2470 16:34:14.483194
2471 16:34:14.483267 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2472 16:34:14.483319
2473 16:34:14.483369 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2474 16:34:14.483419 [DutyScan_Calibration_Flow] ====Done====
2475 16:34:14.483494
2476 16:34:14.483547 [DutyScan_Calibration_Flow] k_type=2
2477 16:34:14.483598
2478 16:34:14.483648 ==DQ 0 ==
2479 16:34:14.483698 Final DQ duty delay cell = -4
2480 16:34:14.483749 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2481 16:34:14.483800 [-4] MIN Duty = 4844%(X100), DQS PI = 4
2482 16:34:14.483861 [-4] AVG Duty = 4937%(X100)
2483 16:34:14.483914
2484 16:34:14.483965 ==DQ 1 ==
2485 16:34:14.484015 Final DQ duty delay cell = 0
2486 16:34:14.484066 [0] MAX Duty = 5031%(X100), DQS PI = 2
2487 16:34:14.484117 [0] MIN Duty = 4876%(X100), DQS PI = 30
2488 16:34:14.484167 [0] AVG Duty = 4953%(X100)
2489 16:34:14.484218
2490 16:34:14.484269 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2491 16:34:14.484319
2492 16:34:14.484368 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2493 16:34:14.484418 [DutyScan_Calibration_Flow] ====Done====
2494 16:34:14.484469 nWR fixed to 30
2495 16:34:14.484520 [ModeRegInit_LP4] CH0 RK0
2496 16:34:14.484570 [ModeRegInit_LP4] CH0 RK1
2497 16:34:14.484622 [ModeRegInit_LP4] CH1 RK0
2498 16:34:14.484673 [ModeRegInit_LP4] CH1 RK1
2499 16:34:14.484723 match AC timing 7
2500 16:34:14.484773 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2501 16:34:14.484823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2502 16:34:14.484874 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2503 16:34:14.484925 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2504 16:34:14.484976 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2505 16:34:14.485026 ==
2506 16:34:14.485076 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 16:34:14.485127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 16:34:14.485177 ==
2509 16:34:14.485228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 16:34:14.485316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 16:34:14.485368 [CA 0] Center 39 (9~70) winsize 62
2512 16:34:14.485418 [CA 1] Center 38 (8~69) winsize 62
2513 16:34:14.485468 [CA 2] Center 35 (5~66) winsize 62
2514 16:34:14.485518 [CA 3] Center 35 (5~66) winsize 62
2515 16:34:14.485568 [CA 4] Center 33 (3~64) winsize 62
2516 16:34:14.485618 [CA 5] Center 33 (3~63) winsize 61
2517 16:34:14.485668
2518 16:34:14.485718 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 16:34:14.485769
2520 16:34:14.485819 [CATrainingPosCal] consider 1 rank data
2521 16:34:14.485869 u2DelayCellTimex100 = 270/100 ps
2522 16:34:14.485920 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 16:34:14.485970 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2524 16:34:14.486022 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 16:34:14.486072 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 16:34:14.486123 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2527 16:34:14.486173 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2528 16:34:14.486224
2529 16:34:14.486275 CA PerBit enable=1, Macro0, CA PI delay=33
2530 16:34:14.486325
2531 16:34:14.486375 [CBTSetCACLKResult] CA Dly = 33
2532 16:34:14.486425 CS Dly: 7 (0~38)
2533 16:34:14.486476 ==
2534 16:34:14.486541 Dram Type= 6, Freq= 0, CH_0, rank 1
2535 16:34:14.486593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 16:34:14.486644 ==
2537 16:34:14.486695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 16:34:14.486746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2539 16:34:14.486797 [CA 0] Center 39 (9~70) winsize 62
2540 16:34:14.486847 [CA 1] Center 39 (9~70) winsize 62
2541 16:34:14.486898 [CA 2] Center 35 (5~66) winsize 62
2542 16:34:14.486948 [CA 3] Center 35 (4~66) winsize 63
2543 16:34:14.486998 [CA 4] Center 34 (4~65) winsize 62
2544 16:34:14.487048 [CA 5] Center 33 (3~64) winsize 62
2545 16:34:14.487099
2546 16:34:14.487149 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2547 16:34:14.487199
2548 16:34:14.487250 [CATrainingPosCal] consider 2 rank data
2549 16:34:14.487300 u2DelayCellTimex100 = 270/100 ps
2550 16:34:14.487355 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 16:34:14.487616 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2552 16:34:14.487713 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 16:34:14.487766 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 16:34:14.487818 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2555 16:34:14.487869 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2556 16:34:14.487920
2557 16:34:14.487970 CA PerBit enable=1, Macro0, CA PI delay=33
2558 16:34:14.488022
2559 16:34:14.488072 [CBTSetCACLKResult] CA Dly = 33
2560 16:34:14.488123 CS Dly: 8 (0~41)
2561 16:34:14.488173
2562 16:34:14.488223 ----->DramcWriteLeveling(PI) begin...
2563 16:34:14.488279 ==
2564 16:34:14.488340 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 16:34:14.488392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 16:34:14.488443 ==
2567 16:34:14.488494 Write leveling (Byte 0): 31 => 31
2568 16:34:14.488545 Write leveling (Byte 1): 27 => 27
2569 16:34:14.488597 DramcWriteLeveling(PI) end<-----
2570 16:34:14.488648
2571 16:34:14.488698 ==
2572 16:34:14.488749 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 16:34:14.488800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 16:34:14.488851 ==
2575 16:34:14.488902 [Gating] SW mode calibration
2576 16:34:14.488952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2577 16:34:14.489004 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2578 16:34:14.489055 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2579 16:34:14.489106 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2580 16:34:14.489157 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 16:34:14.489207 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 16:34:14.489288 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 16:34:14.489358 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 16:34:14.489409 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 16:34:14.489460 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2586 16:34:14.489511 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2587 16:34:14.489561 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 16:34:14.489611 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 16:34:14.489662 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 16:34:14.489712 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 16:34:14.489763 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 16:34:14.489813 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2593 16:34:14.489864 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2594 16:34:14.489914 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2595 16:34:14.489964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 16:34:14.490015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 16:34:14.490065 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 16:34:14.490116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 16:34:14.490166 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 16:34:14.490217 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 16:34:14.490267 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2602 16:34:14.490318 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 16:34:14.490369 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 16:34:14.490421 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 16:34:14.490471 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 16:34:14.490521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 16:34:14.490572 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 16:34:14.490622 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 16:34:14.490672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 16:34:14.490722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 16:34:14.490773 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 16:34:14.490822 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 16:34:14.490873 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 16:34:14.490923 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 16:34:14.490974 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 16:34:14.491024 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 16:34:14.491074 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 16:34:14.491125 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2619 16:34:14.491175 Total UI for P1: 0, mck2ui 16
2620 16:34:14.491226 best dqsien dly found for B0: ( 1, 3, 26)
2621 16:34:14.491277 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 16:34:14.491328 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 16:34:14.491379 Total UI for P1: 0, mck2ui 16
2624 16:34:14.491430 best dqsien dly found for B1: ( 1, 4, 2)
2625 16:34:14.491480 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2626 16:34:14.491531 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2627 16:34:14.491581
2628 16:34:14.491632 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2629 16:34:14.491682 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2630 16:34:14.491733 [Gating] SW calibration Done
2631 16:34:14.491783 ==
2632 16:34:14.491833 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 16:34:14.491884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 16:34:14.491935 ==
2635 16:34:14.491985 RX Vref Scan: 0
2636 16:34:14.492034
2637 16:34:14.492085 RX Vref 0 -> 0, step: 1
2638 16:34:14.492134
2639 16:34:14.492184 RX Delay -40 -> 252, step: 8
2640 16:34:14.492234 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2641 16:34:14.492285 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2642 16:34:14.492337 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2643 16:34:14.492387 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2644 16:34:14.492438 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2645 16:34:14.492489 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2646 16:34:14.492539 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2647 16:34:14.492589 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2648 16:34:14.492640 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2649 16:34:14.492691 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2650 16:34:14.492742 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2651 16:34:14.492792 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2652 16:34:14.493033 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2653 16:34:14.493090 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2654 16:34:14.493142 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2655 16:34:14.493194 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2656 16:34:14.493245 ==
2657 16:34:14.493343 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 16:34:14.493396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 16:34:14.493447 ==
2660 16:34:14.493498 DQS Delay:
2661 16:34:14.493548 DQS0 = 0, DQS1 = 0
2662 16:34:14.493598 DQM Delay:
2663 16:34:14.493648 DQM0 = 120, DQM1 = 106
2664 16:34:14.493699 DQ Delay:
2665 16:34:14.493750 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2666 16:34:14.493800 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2667 16:34:14.493851 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2668 16:34:14.493901 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =111
2669 16:34:14.493952
2670 16:34:14.494002
2671 16:34:14.494052 ==
2672 16:34:14.494102 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 16:34:14.494153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 16:34:14.494206 ==
2675 16:34:14.494258
2676 16:34:14.494307
2677 16:34:14.494357 TX Vref Scan disable
2678 16:34:14.494408 == TX Byte 0 ==
2679 16:34:14.494458 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2680 16:34:14.494508 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2681 16:34:14.494559 == TX Byte 1 ==
2682 16:34:14.494610 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2683 16:34:14.494660 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2684 16:34:14.494711 ==
2685 16:34:14.494761 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 16:34:14.494812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 16:34:14.494863 ==
2688 16:34:14.494914 TX Vref=22, minBit 0, minWin=25, winSum=409
2689 16:34:14.494964 TX Vref=24, minBit 1, minWin=25, winSum=413
2690 16:34:14.495016 TX Vref=26, minBit 4, minWin=25, winSum=416
2691 16:34:14.495066 TX Vref=28, minBit 0, minWin=26, winSum=427
2692 16:34:14.495116 TX Vref=30, minBit 5, minWin=26, winSum=429
2693 16:34:14.495167 TX Vref=32, minBit 5, minWin=25, winSum=424
2694 16:34:14.495217 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 30
2695 16:34:14.495267
2696 16:34:14.495317 Final TX Range 1 Vref 30
2697 16:34:14.495368
2698 16:34:14.495418 ==
2699 16:34:14.495468 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 16:34:14.495518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 16:34:14.495569 ==
2702 16:34:14.495619
2703 16:34:14.495668
2704 16:34:14.495718 TX Vref Scan disable
2705 16:34:14.495768 == TX Byte 0 ==
2706 16:34:14.495818 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2707 16:34:14.495868 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2708 16:34:14.495919 == TX Byte 1 ==
2709 16:34:14.495969 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2710 16:34:14.496019 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2711 16:34:14.496073
2712 16:34:14.496123 [DATLAT]
2713 16:34:14.496174 Freq=1200, CH0 RK0
2714 16:34:14.496224
2715 16:34:14.496274 DATLAT Default: 0xd
2716 16:34:14.496325 0, 0xFFFF, sum = 0
2717 16:34:14.496376 1, 0xFFFF, sum = 0
2718 16:34:14.496428 2, 0xFFFF, sum = 0
2719 16:34:14.496479 3, 0xFFFF, sum = 0
2720 16:34:14.496530 4, 0xFFFF, sum = 0
2721 16:34:14.496581 5, 0xFFFF, sum = 0
2722 16:34:14.496632 6, 0xFFFF, sum = 0
2723 16:34:14.496684 7, 0xFFFF, sum = 0
2724 16:34:14.496734 8, 0xFFFF, sum = 0
2725 16:34:14.496786 9, 0xFFFF, sum = 0
2726 16:34:14.496837 10, 0xFFFF, sum = 0
2727 16:34:14.496888 11, 0xFFFF, sum = 0
2728 16:34:14.496939 12, 0x0, sum = 1
2729 16:34:14.496991 13, 0x0, sum = 2
2730 16:34:14.497042 14, 0x0, sum = 3
2731 16:34:14.497093 15, 0x0, sum = 4
2732 16:34:14.497144 best_step = 13
2733 16:34:14.497195
2734 16:34:14.497245 ==
2735 16:34:14.497352 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 16:34:14.497404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 16:34:14.497456 ==
2738 16:34:14.497507 RX Vref Scan: 1
2739 16:34:14.497557
2740 16:34:14.497607 Set Vref Range= 32 -> 127
2741 16:34:14.497658
2742 16:34:14.497708 RX Vref 32 -> 127, step: 1
2743 16:34:14.497758
2744 16:34:14.497808 RX Delay -21 -> 252, step: 4
2745 16:34:14.497858
2746 16:34:14.497908 Set Vref, RX VrefLevel [Byte0]: 32
2747 16:34:14.497959 [Byte1]: 32
2748 16:34:14.498010
2749 16:34:14.498059 Set Vref, RX VrefLevel [Byte0]: 33
2750 16:34:14.498109 [Byte1]: 33
2751 16:34:14.498160
2752 16:34:14.498210 Set Vref, RX VrefLevel [Byte0]: 34
2753 16:34:14.498260 [Byte1]: 34
2754 16:34:14.498311
2755 16:34:14.498360 Set Vref, RX VrefLevel [Byte0]: 35
2756 16:34:14.498411 [Byte1]: 35
2757 16:34:14.498461
2758 16:34:14.498510 Set Vref, RX VrefLevel [Byte0]: 36
2759 16:34:14.498560 [Byte1]: 36
2760 16:34:14.498610
2761 16:34:14.498660 Set Vref, RX VrefLevel [Byte0]: 37
2762 16:34:14.498711 [Byte1]: 37
2763 16:34:14.498761
2764 16:34:14.498812 Set Vref, RX VrefLevel [Byte0]: 38
2765 16:34:14.498862 [Byte1]: 38
2766 16:34:14.498912
2767 16:34:14.498962 Set Vref, RX VrefLevel [Byte0]: 39
2768 16:34:14.499013 [Byte1]: 39
2769 16:34:14.499063
2770 16:34:14.499113 Set Vref, RX VrefLevel [Byte0]: 40
2771 16:34:14.499164 [Byte1]: 40
2772 16:34:14.499214
2773 16:34:14.499264 Set Vref, RX VrefLevel [Byte0]: 41
2774 16:34:14.499314 [Byte1]: 41
2775 16:34:14.499364
2776 16:34:14.499414 Set Vref, RX VrefLevel [Byte0]: 42
2777 16:34:14.499464 [Byte1]: 42
2778 16:34:14.499514
2779 16:34:14.499564 Set Vref, RX VrefLevel [Byte0]: 43
2780 16:34:14.499614 [Byte1]: 43
2781 16:34:14.499664
2782 16:34:14.499713 Set Vref, RX VrefLevel [Byte0]: 44
2783 16:34:14.499764 [Byte1]: 44
2784 16:34:14.499814
2785 16:34:14.499864 Set Vref, RX VrefLevel [Byte0]: 45
2786 16:34:14.499914 [Byte1]: 45
2787 16:34:14.499964
2788 16:34:14.500014 Set Vref, RX VrefLevel [Byte0]: 46
2789 16:34:14.500064 [Byte1]: 46
2790 16:34:14.500115
2791 16:34:14.500165 Set Vref, RX VrefLevel [Byte0]: 47
2792 16:34:14.500216 [Byte1]: 47
2793 16:34:14.500266
2794 16:34:14.500316 Set Vref, RX VrefLevel [Byte0]: 48
2795 16:34:14.500366 [Byte1]: 48
2796 16:34:14.500417
2797 16:34:14.500467 Set Vref, RX VrefLevel [Byte0]: 49
2798 16:34:14.500516 [Byte1]: 49
2799 16:34:14.500567
2800 16:34:14.500617 Set Vref, RX VrefLevel [Byte0]: 50
2801 16:34:14.500667 [Byte1]: 50
2802 16:34:14.500717
2803 16:34:14.500767 Set Vref, RX VrefLevel [Byte0]: 51
2804 16:34:14.500818 [Byte1]: 51
2805 16:34:14.500868
2806 16:34:14.500918 Set Vref, RX VrefLevel [Byte0]: 52
2807 16:34:14.500968 [Byte1]: 52
2808 16:34:14.501019
2809 16:34:14.501068 Set Vref, RX VrefLevel [Byte0]: 53
2810 16:34:14.501119 [Byte1]: 53
2811 16:34:14.501169
2812 16:34:14.501219 Set Vref, RX VrefLevel [Byte0]: 54
2813 16:34:14.501305 [Byte1]: 54
2814 16:34:14.501370
2815 16:34:14.501420 Set Vref, RX VrefLevel [Byte0]: 55
2816 16:34:14.501470 [Byte1]: 55
2817 16:34:14.501521
2818 16:34:14.501767 Set Vref, RX VrefLevel [Byte0]: 56
2819 16:34:14.501824 [Byte1]: 56
2820 16:34:14.501875
2821 16:34:14.501926 Set Vref, RX VrefLevel [Byte0]: 57
2822 16:34:14.501977 [Byte1]: 57
2823 16:34:14.502027
2824 16:34:14.502077 Set Vref, RX VrefLevel [Byte0]: 58
2825 16:34:14.502127 [Byte1]: 58
2826 16:34:14.502177
2827 16:34:14.502227 Set Vref, RX VrefLevel [Byte0]: 59
2828 16:34:14.502277 [Byte1]: 59
2829 16:34:14.502327
2830 16:34:14.502377 Set Vref, RX VrefLevel [Byte0]: 60
2831 16:34:14.502427 [Byte1]: 60
2832 16:34:14.502477
2833 16:34:14.502527 Set Vref, RX VrefLevel [Byte0]: 61
2834 16:34:14.502578 [Byte1]: 61
2835 16:34:14.502628
2836 16:34:14.502677 Set Vref, RX VrefLevel [Byte0]: 62
2837 16:34:14.502727 [Byte1]: 62
2838 16:34:14.502778
2839 16:34:14.502828 Set Vref, RX VrefLevel [Byte0]: 63
2840 16:34:14.502878 [Byte1]: 63
2841 16:34:14.502928
2842 16:34:14.502977 Set Vref, RX VrefLevel [Byte0]: 64
2843 16:34:14.503028 [Byte1]: 64
2844 16:34:14.503078
2845 16:34:14.503128 Set Vref, RX VrefLevel [Byte0]: 65
2846 16:34:14.503177 [Byte1]: 65
2847 16:34:14.503227
2848 16:34:14.503277 Set Vref, RX VrefLevel [Byte0]: 66
2849 16:34:14.503328 [Byte1]: 66
2850 16:34:14.503377
2851 16:34:14.503427 Set Vref, RX VrefLevel [Byte0]: 67
2852 16:34:14.503478 [Byte1]: 67
2853 16:34:14.503528
2854 16:34:14.503578 Final RX Vref Byte 0 = 58 to rank0
2855 16:34:14.503628 Final RX Vref Byte 1 = 49 to rank0
2856 16:34:14.503679 Final RX Vref Byte 0 = 58 to rank1
2857 16:34:14.503730 Final RX Vref Byte 1 = 49 to rank1==
2858 16:34:14.503781 Dram Type= 6, Freq= 0, CH_0, rank 0
2859 16:34:14.503831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 16:34:14.503909 ==
2861 16:34:14.503992 DQS Delay:
2862 16:34:14.504073 DQS0 = 0, DQS1 = 0
2863 16:34:14.504155 DQM Delay:
2864 16:34:14.504218 DQM0 = 119, DQM1 = 105
2865 16:34:14.504271 DQ Delay:
2866 16:34:14.504329 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2867 16:34:14.504382 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2868 16:34:14.504441 DQ8 =94, DQ9 =92, DQ10 =104, DQ11 =100
2869 16:34:14.504492 DQ12 =116, DQ13 =108, DQ14 =114, DQ15 =112
2870 16:34:14.504543
2871 16:34:14.504593
2872 16:34:14.504644 [DQSOSCAuto] RK0, (LSB)MR18= 0x601, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2873 16:34:14.504695 CH0 RK0: MR19=404, MR18=601
2874 16:34:14.504746 CH0_RK0: MR19=0x404, MR18=0x601, DQSOSC=407, MR23=63, INC=39, DEC=26
2875 16:34:14.504797
2876 16:34:14.504847 ----->DramcWriteLeveling(PI) begin...
2877 16:34:14.504898 ==
2878 16:34:14.504962 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 16:34:14.505014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 16:34:14.505067 ==
2881 16:34:14.505118 Write leveling (Byte 0): 31 => 31
2882 16:34:14.505169 Write leveling (Byte 1): 26 => 26
2883 16:34:14.505220 DramcWriteLeveling(PI) end<-----
2884 16:34:14.505283
2885 16:34:14.505337 ==
2886 16:34:14.505389 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 16:34:14.505440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 16:34:14.505493 ==
2889 16:34:14.505545 [Gating] SW mode calibration
2890 16:34:14.505596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2891 16:34:14.505649 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2892 16:34:14.505702 0 15 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
2893 16:34:14.505755 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 16:34:14.505806 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 16:34:14.505858 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 16:34:14.505910 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 16:34:14.505961 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2898 16:34:14.506013 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2899 16:34:14.506065 0 15 28 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
2900 16:34:14.506116 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2901 16:34:14.506168 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 16:34:14.506220 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 16:34:14.506271 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 16:34:14.506323 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 16:34:14.506375 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 16:34:14.506426 1 0 24 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
2907 16:34:14.506507 1 0 28 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
2908 16:34:14.506562 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 16:34:14.506614 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 16:34:14.506694 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 16:34:14.506750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 16:34:14.506803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 16:34:14.506855 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 16:34:14.506907 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 16:34:14.506960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2916 16:34:14.507011 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2917 16:34:14.507064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 16:34:14.507116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 16:34:14.507168 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 16:34:14.507220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 16:34:14.507272 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 16:34:14.507323 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 16:34:14.507375 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 16:34:14.507442 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 16:34:14.507500 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 16:34:14.507553 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 16:34:14.507605 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 16:34:14.507685 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 16:34:14.507740 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 16:34:14.507792 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 16:34:14.508083 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2932 16:34:14.508149 Total UI for P1: 0, mck2ui 16
2933 16:34:14.508211 best dqsien dly found for B0: ( 1, 3, 24)
2934 16:34:14.508306 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2935 16:34:14.508390 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 16:34:14.508447 Total UI for P1: 0, mck2ui 16
2937 16:34:14.508500 best dqsien dly found for B1: ( 1, 3, 30)
2938 16:34:14.508553 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2939 16:34:14.508606 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2940 16:34:14.508658
2941 16:34:14.508708 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2942 16:34:14.508760 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2943 16:34:14.508812 [Gating] SW calibration Done
2944 16:34:14.508863 ==
2945 16:34:14.508915 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 16:34:14.508967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 16:34:14.509027 ==
2948 16:34:14.509116 RX Vref Scan: 0
2949 16:34:14.509197
2950 16:34:14.509293 RX Vref 0 -> 0, step: 1
2951 16:34:14.509349
2952 16:34:14.509401 RX Delay -40 -> 252, step: 8
2953 16:34:14.509454 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2954 16:34:14.509506 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2955 16:34:14.509558 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2956 16:34:14.509610 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2957 16:34:14.509683 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2958 16:34:14.509740 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2959 16:34:14.509793 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2960 16:34:14.509870 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2961 16:34:14.509958 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2962 16:34:14.510069 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2963 16:34:14.510158 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2964 16:34:14.510239 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2965 16:34:14.510296 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2966 16:34:14.510348 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2967 16:34:14.510402 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2968 16:34:14.510493 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2969 16:34:14.510548 ==
2970 16:34:14.510604 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 16:34:14.510657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 16:34:14.510709 ==
2973 16:34:14.510761 DQS Delay:
2974 16:34:14.510813 DQS0 = 0, DQS1 = 0
2975 16:34:14.510864 DQM Delay:
2976 16:34:14.510916 DQM0 = 118, DQM1 = 107
2977 16:34:14.510967 DQ Delay:
2978 16:34:14.511019 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2979 16:34:14.511070 DQ4 =123, DQ5 =107, DQ6 =127, DQ7 =127
2980 16:34:14.511121 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2981 16:34:14.511172 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2982 16:34:14.511223
2983 16:34:14.511274
2984 16:34:14.511324 ==
2985 16:34:14.511375 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 16:34:14.511427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 16:34:14.511479 ==
2988 16:34:14.511530
2989 16:34:14.511581
2990 16:34:14.511632 TX Vref Scan disable
2991 16:34:14.511683 == TX Byte 0 ==
2992 16:34:14.511734 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2993 16:34:14.511786 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2994 16:34:14.511838 == TX Byte 1 ==
2995 16:34:14.511893 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2996 16:34:14.511946 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2997 16:34:14.511996 ==
2998 16:34:14.512048 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 16:34:14.512100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 16:34:14.512152 ==
3001 16:34:14.512203 TX Vref=22, minBit 2, minWin=25, winSum=415
3002 16:34:14.512255 TX Vref=24, minBit 3, minWin=25, winSum=414
3003 16:34:14.668890 TX Vref=26, minBit 13, minWin=25, winSum=420
3004 16:34:14.669423 TX Vref=28, minBit 0, minWin=26, winSum=422
3005 16:34:14.669770 TX Vref=30, minBit 5, minWin=25, winSum=420
3006 16:34:14.670076 TX Vref=32, minBit 5, minWin=25, winSum=422
3007 16:34:14.670369 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
3008 16:34:14.670662
3009 16:34:14.670946 Final TX Range 1 Vref 28
3010 16:34:14.671229
3011 16:34:14.671502 ==
3012 16:34:14.671776 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 16:34:14.672053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 16:34:14.672330 ==
3015 16:34:14.672602
3016 16:34:14.672868
3017 16:34:14.673135 TX Vref Scan disable
3018 16:34:14.673463 == TX Byte 0 ==
3019 16:34:14.673742 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3020 16:34:14.674015 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3021 16:34:14.674287 == TX Byte 1 ==
3022 16:34:14.674554 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3023 16:34:14.674823 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3024 16:34:14.675092
3025 16:34:14.675358 [DATLAT]
3026 16:34:14.675627 Freq=1200, CH0 RK1
3027 16:34:14.675898
3028 16:34:14.676165 DATLAT Default: 0xd
3029 16:34:14.676429 0, 0xFFFF, sum = 0
3030 16:34:14.676702 1, 0xFFFF, sum = 0
3031 16:34:14.676972 2, 0xFFFF, sum = 0
3032 16:34:14.677242 3, 0xFFFF, sum = 0
3033 16:34:14.677551 4, 0xFFFF, sum = 0
3034 16:34:14.677826 5, 0xFFFF, sum = 0
3035 16:34:14.678098 6, 0xFFFF, sum = 0
3036 16:34:14.678371 7, 0xFFFF, sum = 0
3037 16:34:14.678641 8, 0xFFFF, sum = 0
3038 16:34:14.678914 9, 0xFFFF, sum = 0
3039 16:34:14.679184 10, 0xFFFF, sum = 0
3040 16:34:14.679455 11, 0xFFFF, sum = 0
3041 16:34:14.679722 12, 0x0, sum = 1
3042 16:34:14.679993 13, 0x0, sum = 2
3043 16:34:14.680263 14, 0x0, sum = 3
3044 16:34:14.680533 15, 0x0, sum = 4
3045 16:34:14.680802 best_step = 13
3046 16:34:14.681066
3047 16:34:14.681376 ==
3048 16:34:14.681657 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 16:34:14.681924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 16:34:14.682193 ==
3051 16:34:14.682463 RX Vref Scan: 0
3052 16:34:14.682730
3053 16:34:14.682993 RX Vref 0 -> 0, step: 1
3054 16:34:14.683255
3055 16:34:14.683520 RX Delay -21 -> 252, step: 4
3056 16:34:14.683787 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3057 16:34:14.684056 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3058 16:34:14.684321 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3059 16:34:14.684588 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3060 16:34:14.684855 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3061 16:34:14.685122 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3062 16:34:14.685431 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3063 16:34:14.685702 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3064 16:34:14.685970 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3065 16:34:14.686238 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3066 16:34:14.686502 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3067 16:34:14.686770 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3068 16:34:14.687040 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3069 16:34:14.687310 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3070 16:34:14.687992 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3071 16:34:14.688302 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3072 16:34:14.688574 ==
3073 16:34:14.688846 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 16:34:14.689117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 16:34:14.689447 ==
3076 16:34:14.689736 DQS Delay:
3077 16:34:14.689932 DQS0 = 0, DQS1 = 0
3078 16:34:14.690126 DQM Delay:
3079 16:34:14.690317 DQM0 = 118, DQM1 = 106
3080 16:34:14.690511 DQ Delay:
3081 16:34:14.690703 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =116
3082 16:34:14.690894 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =122
3083 16:34:14.691089 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3084 16:34:14.691299 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3085 16:34:14.691495
3086 16:34:14.691687
3087 16:34:14.691898 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3088 16:34:14.692264 CH0 RK1: MR19=303, MR18=FFFC
3089 16:34:14.692584 CH0_RK1: MR19=0x303, MR18=0xFFFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3090 16:34:14.692792 [RxdqsGatingPostProcess] freq 1200
3091 16:34:14.692988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3092 16:34:14.693184 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 16:34:14.693540 best DQS1 dly(2T, 0.5T) = (0, 12)
3094 16:34:14.693745 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 16:34:14.693940 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3096 16:34:14.694134 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 16:34:14.694327 best DQS1 dly(2T, 0.5T) = (0, 11)
3098 16:34:14.694519 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 16:34:14.694721 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3100 16:34:14.694864 Pre-setting of DQS Precalculation
3101 16:34:14.695009 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3102 16:34:14.695153 ==
3103 16:34:14.695299 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 16:34:14.695442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 16:34:14.695587 ==
3106 16:34:14.695729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 16:34:14.695874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3108 16:34:14.696021 [CA 0] Center 38 (8~68) winsize 61
3109 16:34:14.696167 [CA 1] Center 37 (7~68) winsize 62
3110 16:34:14.696311 [CA 2] Center 35 (5~65) winsize 61
3111 16:34:14.696453 [CA 3] Center 34 (4~64) winsize 61
3112 16:34:14.696606 [CA 4] Center 34 (4~65) winsize 62
3113 16:34:14.696750 [CA 5] Center 33 (3~63) winsize 61
3114 16:34:14.696893
3115 16:34:14.697035 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 16:34:14.697180
3117 16:34:14.697353 [CATrainingPosCal] consider 1 rank data
3118 16:34:14.697500 u2DelayCellTimex100 = 270/100 ps
3119 16:34:14.697644 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3120 16:34:14.697788 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 16:34:14.697931 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3122 16:34:14.698074 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 16:34:14.698217 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3124 16:34:14.698361 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3125 16:34:14.698516
3126 16:34:14.698679 CA PerBit enable=1, Macro0, CA PI delay=33
3127 16:34:14.698824
3128 16:34:14.698968 [CBTSetCACLKResult] CA Dly = 33
3129 16:34:14.699112 CS Dly: 4 (0~35)
3130 16:34:14.699254 ==
3131 16:34:14.699398 Dram Type= 6, Freq= 0, CH_1, rank 1
3132 16:34:14.699541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 16:34:14.699687 ==
3134 16:34:14.699827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 16:34:14.699943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3136 16:34:14.700059 [CA 0] Center 37 (7~68) winsize 62
3137 16:34:14.700176 [CA 1] Center 37 (7~68) winsize 62
3138 16:34:14.700292 [CA 2] Center 35 (5~65) winsize 61
3139 16:34:14.700408 [CA 3] Center 33 (3~64) winsize 62
3140 16:34:14.700524 [CA 4] Center 34 (4~64) winsize 61
3141 16:34:14.700660 [CA 5] Center 33 (3~64) winsize 62
3142 16:34:14.700777
3143 16:34:14.700894 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3144 16:34:14.701011
3145 16:34:14.701125 [CATrainingPosCal] consider 2 rank data
3146 16:34:14.701240 u2DelayCellTimex100 = 270/100 ps
3147 16:34:14.701379 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 16:34:14.701497 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 16:34:14.701614 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3150 16:34:14.701731 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 16:34:14.701848 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 16:34:14.701964 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3153 16:34:14.702080
3154 16:34:14.702196 CA PerBit enable=1, Macro0, CA PI delay=33
3155 16:34:14.702312
3156 16:34:14.702428 [CBTSetCACLKResult] CA Dly = 33
3157 16:34:14.702544 CS Dly: 6 (0~39)
3158 16:34:14.702718
3159 16:34:14.702908 ----->DramcWriteLeveling(PI) begin...
3160 16:34:14.703036 ==
3161 16:34:14.703155 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 16:34:14.703274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 16:34:14.703394 ==
3164 16:34:14.703511 Write leveling (Byte 0): 24 => 24
3165 16:34:14.703627 Write leveling (Byte 1): 27 => 27
3166 16:34:14.703743 DramcWriteLeveling(PI) end<-----
3167 16:34:14.703860
3168 16:34:14.703977 ==
3169 16:34:14.704092 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 16:34:14.704208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 16:34:14.704325 ==
3172 16:34:14.704441 [Gating] SW mode calibration
3173 16:34:14.704557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3174 16:34:14.704676 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3175 16:34:14.704794 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3176 16:34:14.704892 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 16:34:14.704988 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 16:34:14.705084 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 16:34:14.705181 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 16:34:14.705293 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 16:34:14.705394 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3182 16:34:14.705490 0 15 28 | B1->B0 | 2c2c 2727 | 1 0 | (1 0) (1 0)
3183 16:34:14.705588 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 16:34:14.705686 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 16:34:14.705784 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 16:34:14.705881 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 16:34:14.706227 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 16:34:14.706411 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 16:34:14.706567 1 0 24 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
3190 16:34:14.706721 1 0 28 | B1->B0 | 4040 4343 | 1 0 | (0 0) (0 0)
3191 16:34:14.706880 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 16:34:14.707078 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 16:34:14.707282 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 16:34:14.707487 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 16:34:14.707663 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 16:34:14.707817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 16:34:14.707969 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3198 16:34:14.708120 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3199 16:34:14.708271 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 16:34:14.708423 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 16:34:14.708574 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 16:34:14.708725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 16:34:14.708876 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 16:34:14.709027 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 16:34:14.709178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 16:34:14.709348 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 16:34:14.709500 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 16:34:14.709651 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 16:34:14.709799 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 16:34:14.709929 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 16:34:14.710058 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 16:34:14.710188 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 16:34:14.710317 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 16:34:14.710447 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 16:34:14.710576 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 16:34:14.710705 Total UI for P1: 0, mck2ui 16
3217 16:34:14.710836 best dqsien dly found for B0: ( 1, 3, 28)
3218 16:34:14.710966 Total UI for P1: 0, mck2ui 16
3219 16:34:14.711096 best dqsien dly found for B1: ( 1, 3, 28)
3220 16:34:14.711225 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3221 16:34:14.711355 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3222 16:34:14.711483
3223 16:34:14.711612 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3224 16:34:14.711742 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3225 16:34:14.711871 [Gating] SW calibration Done
3226 16:34:14.711998 ==
3227 16:34:14.712128 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 16:34:14.712257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 16:34:14.712386 ==
3230 16:34:14.712515 RX Vref Scan: 0
3231 16:34:14.712642
3232 16:34:14.712770 RX Vref 0 -> 0, step: 1
3233 16:34:14.712898
3234 16:34:14.713026 RX Delay -40 -> 252, step: 8
3235 16:34:14.713156 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3236 16:34:14.713294 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3237 16:34:14.713384 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3238 16:34:14.713470 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3239 16:34:14.713556 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3240 16:34:14.713640 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3241 16:34:14.713724 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3242 16:34:14.713808 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3243 16:34:14.713892 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3244 16:34:14.713976 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3245 16:34:14.714059 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3246 16:34:14.714143 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3247 16:34:14.714226 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3248 16:34:14.714310 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3249 16:34:14.714393 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3250 16:34:14.714477 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3251 16:34:14.714560 ==
3252 16:34:14.714643 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 16:34:14.714726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 16:34:14.714814 ==
3255 16:34:14.714886 DQS Delay:
3256 16:34:14.714959 DQS0 = 0, DQS1 = 0
3257 16:34:14.715032 DQM Delay:
3258 16:34:14.715104 DQM0 = 116, DQM1 = 113
3259 16:34:14.715178 DQ Delay:
3260 16:34:14.715250 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3261 16:34:14.715323 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3262 16:34:14.715395 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3263 16:34:14.715469 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3264 16:34:14.715541
3265 16:34:14.715613
3266 16:34:14.715685 ==
3267 16:34:14.715758 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 16:34:14.715830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 16:34:14.715904 ==
3270 16:34:14.715977
3271 16:34:14.716048
3272 16:34:14.716121 TX Vref Scan disable
3273 16:34:14.716193 == TX Byte 0 ==
3274 16:34:14.716266 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3275 16:34:14.716339 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3276 16:34:14.716412 == TX Byte 1 ==
3277 16:34:14.716484 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3278 16:34:14.716558 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3279 16:34:14.716630 ==
3280 16:34:14.716716 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 16:34:14.716790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 16:34:14.716864 ==
3283 16:34:14.716937 TX Vref=22, minBit 2, minWin=25, winSum=413
3284 16:34:14.717012 TX Vref=24, minBit 4, minWin=25, winSum=415
3285 16:34:14.717086 TX Vref=26, minBit 1, minWin=26, winSum=423
3286 16:34:14.717159 TX Vref=28, minBit 0, minWin=26, winSum=423
3287 16:34:14.717233 TX Vref=30, minBit 9, minWin=25, winSum=428
3288 16:34:14.717319 TX Vref=32, minBit 9, minWin=25, winSum=428
3289 16:34:14.717395 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 26
3290 16:34:14.717482
3291 16:34:14.717604 Final TX Range 1 Vref 26
3292 16:34:14.717725
3293 16:34:14.717843 ==
3294 16:34:14.717957 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 16:34:14.718072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 16:34:14.718185 ==
3297 16:34:14.718301
3298 16:34:14.718403
3299 16:34:14.718479 TX Vref Scan disable
3300 16:34:14.718554 == TX Byte 0 ==
3301 16:34:14.718627 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3302 16:34:14.718701 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3303 16:34:14.718989 == TX Byte 1 ==
3304 16:34:14.719086 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3305 16:34:14.719203 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3306 16:34:14.719316
3307 16:34:14.719429 [DATLAT]
3308 16:34:14.719538 Freq=1200, CH1 RK0
3309 16:34:14.719617
3310 16:34:14.719697 DATLAT Default: 0xd
3311 16:34:14.719817 0, 0xFFFF, sum = 0
3312 16:34:14.719897 1, 0xFFFF, sum = 0
3313 16:34:14.719965 2, 0xFFFF, sum = 0
3314 16:34:14.720032 3, 0xFFFF, sum = 0
3315 16:34:14.720099 4, 0xFFFF, sum = 0
3316 16:34:14.720173 5, 0xFFFF, sum = 0
3317 16:34:14.720245 6, 0xFFFF, sum = 0
3318 16:34:14.720314 7, 0xFFFF, sum = 0
3319 16:34:14.720381 8, 0xFFFF, sum = 0
3320 16:34:14.720447 9, 0xFFFF, sum = 0
3321 16:34:14.720514 10, 0xFFFF, sum = 0
3322 16:34:14.720579 11, 0xFFFF, sum = 0
3323 16:34:14.720646 12, 0x0, sum = 1
3324 16:34:14.720712 13, 0x0, sum = 2
3325 16:34:14.720785 14, 0x0, sum = 3
3326 16:34:14.720857 15, 0x0, sum = 4
3327 16:34:14.720924 best_step = 13
3328 16:34:14.720990
3329 16:34:14.721054 ==
3330 16:34:14.721120 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 16:34:14.721186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 16:34:14.721252 ==
3333 16:34:14.721339 RX Vref Scan: 1
3334 16:34:14.721407
3335 16:34:14.721477 Set Vref Range= 32 -> 127
3336 16:34:14.721543
3337 16:34:14.721608 RX Vref 32 -> 127, step: 1
3338 16:34:14.721672
3339 16:34:14.721736 RX Delay -13 -> 252, step: 4
3340 16:34:14.721801
3341 16:34:14.721866 Set Vref, RX VrefLevel [Byte0]: 32
3342 16:34:14.721931 [Byte1]: 32
3343 16:34:14.722000
3344 16:34:14.722072 Set Vref, RX VrefLevel [Byte0]: 33
3345 16:34:14.722152 [Byte1]: 33
3346 16:34:14.722259
3347 16:34:14.722361 Set Vref, RX VrefLevel [Byte0]: 34
3348 16:34:14.722468 [Byte1]: 34
3349 16:34:14.722575
3350 16:34:14.722680 Set Vref, RX VrefLevel [Byte0]: 35
3351 16:34:14.722781 [Byte1]: 35
3352 16:34:14.722881
3353 16:34:14.722981 Set Vref, RX VrefLevel [Byte0]: 36
3354 16:34:14.723082 [Byte1]: 36
3355 16:34:14.723170
3356 16:34:14.723239 Set Vref, RX VrefLevel [Byte0]: 37
3357 16:34:14.723305 [Byte1]: 37
3358 16:34:14.723375
3359 16:34:14.723446 Set Vref, RX VrefLevel [Byte0]: 38
3360 16:34:14.723512 [Byte1]: 38
3361 16:34:14.723577
3362 16:34:14.723642 Set Vref, RX VrefLevel [Byte0]: 39
3363 16:34:14.723711 [Byte1]: 39
3364 16:34:14.723803
3365 16:34:14.723904 Set Vref, RX VrefLevel [Byte0]: 40
3366 16:34:14.724004 [Byte1]: 40
3367 16:34:14.724103
3368 16:34:14.724202 Set Vref, RX VrefLevel [Byte0]: 41
3369 16:34:14.724302 [Byte1]: 41
3370 16:34:14.724401
3371 16:34:14.724508 Set Vref, RX VrefLevel [Byte0]: 42
3372 16:34:14.724610 [Byte1]: 42
3373 16:34:14.724709
3374 16:34:14.724816 Set Vref, RX VrefLevel [Byte0]: 43
3375 16:34:14.724907 [Byte1]: 43
3376 16:34:14.724996
3377 16:34:14.725086 Set Vref, RX VrefLevel [Byte0]: 44
3378 16:34:14.725177 [Byte1]: 44
3379 16:34:14.725271
3380 16:34:14.725334 Set Vref, RX VrefLevel [Byte0]: 45
3381 16:34:14.725393 [Byte1]: 45
3382 16:34:14.725451
3383 16:34:14.725510 Set Vref, RX VrefLevel [Byte0]: 46
3384 16:34:14.725567 [Byte1]: 46
3385 16:34:14.725626
3386 16:34:14.725682 Set Vref, RX VrefLevel [Byte0]: 47
3387 16:34:14.725741 [Byte1]: 47
3388 16:34:14.725799
3389 16:34:14.725857 Set Vref, RX VrefLevel [Byte0]: 48
3390 16:34:14.725914 [Byte1]: 48
3391 16:34:14.725972
3392 16:34:14.726029 Set Vref, RX VrefLevel [Byte0]: 49
3393 16:34:14.726086 [Byte1]: 49
3394 16:34:14.726144
3395 16:34:14.726201 Set Vref, RX VrefLevel [Byte0]: 50
3396 16:34:14.726258 [Byte1]: 50
3397 16:34:14.726323
3398 16:34:14.726385 Set Vref, RX VrefLevel [Byte0]: 51
3399 16:34:14.726445 [Byte1]: 51
3400 16:34:14.726503
3401 16:34:14.726561 Set Vref, RX VrefLevel [Byte0]: 52
3402 16:34:14.726619 [Byte1]: 52
3403 16:34:14.726695
3404 16:34:14.726770 Set Vref, RX VrefLevel [Byte0]: 53
3405 16:34:14.726861 [Byte1]: 53
3406 16:34:14.726923
3407 16:34:14.726981 Set Vref, RX VrefLevel [Byte0]: 54
3408 16:34:14.727040 [Byte1]: 54
3409 16:34:14.727097
3410 16:34:14.727155 Set Vref, RX VrefLevel [Byte0]: 55
3411 16:34:14.727213 [Byte1]: 55
3412 16:34:14.727271
3413 16:34:14.727329 Set Vref, RX VrefLevel [Byte0]: 56
3414 16:34:14.727388 [Byte1]: 56
3415 16:34:14.727445
3416 16:34:14.727503 Set Vref, RX VrefLevel [Byte0]: 57
3417 16:34:14.727560 [Byte1]: 57
3418 16:34:14.727618
3419 16:34:14.727676 Set Vref, RX VrefLevel [Byte0]: 58
3420 16:34:14.727734 [Byte1]: 58
3421 16:34:14.727791
3422 16:34:14.727848 Set Vref, RX VrefLevel [Byte0]: 59
3423 16:34:14.727907 [Byte1]: 59
3424 16:34:14.727964
3425 16:34:14.728021 Set Vref, RX VrefLevel [Byte0]: 60
3426 16:34:14.728079 [Byte1]: 60
3427 16:34:14.728137
3428 16:34:14.728195 Set Vref, RX VrefLevel [Byte0]: 61
3429 16:34:14.728252 [Byte1]: 61
3430 16:34:14.728309
3431 16:34:14.728367 Set Vref, RX VrefLevel [Byte0]: 62
3432 16:34:14.728425 [Byte1]: 62
3433 16:34:14.728482
3434 16:34:14.728539 Set Vref, RX VrefLevel [Byte0]: 63
3435 16:34:14.728596 [Byte1]: 63
3436 16:34:14.728654
3437 16:34:14.728711 Set Vref, RX VrefLevel [Byte0]: 64
3438 16:34:14.728769 [Byte1]: 64
3439 16:34:14.728826
3440 16:34:14.728884 Set Vref, RX VrefLevel [Byte0]: 65
3441 16:34:14.728941 [Byte1]: 65
3442 16:34:14.728998
3443 16:34:14.729056 Final RX Vref Byte 0 = 52 to rank0
3444 16:34:14.729114 Final RX Vref Byte 1 = 52 to rank0
3445 16:34:14.729173 Final RX Vref Byte 0 = 52 to rank1
3446 16:34:14.729232 Final RX Vref Byte 1 = 52 to rank1==
3447 16:34:14.729316 Dram Type= 6, Freq= 0, CH_1, rank 0
3448 16:34:14.729408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 16:34:14.729499 ==
3450 16:34:14.729589 DQS Delay:
3451 16:34:14.729678 DQS0 = 0, DQS1 = 0
3452 16:34:14.729774 DQM Delay:
3453 16:34:14.729855 DQM0 = 116, DQM1 = 114
3454 16:34:14.729937 DQ Delay:
3455 16:34:14.730021 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =116
3456 16:34:14.730108 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =112
3457 16:34:14.730173 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3458 16:34:14.730227 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =122
3459 16:34:14.730280
3460 16:34:14.730332
3461 16:34:14.730385 [DQSOSCAuto] RK0, (LSB)MR18= 0xf805, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3462 16:34:14.730438 CH1 RK0: MR19=304, MR18=F805
3463 16:34:14.730492 CH1_RK0: MR19=0x304, MR18=0xF805, DQSOSC=408, MR23=63, INC=39, DEC=26
3464 16:34:14.730545
3465 16:34:14.730597 ----->DramcWriteLeveling(PI) begin...
3466 16:34:14.730651 ==
3467 16:34:14.730703 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 16:34:14.730959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 16:34:14.731021 ==
3470 16:34:14.731076 Write leveling (Byte 0): 26 => 26
3471 16:34:14.731129 Write leveling (Byte 1): 29 => 29
3472 16:34:14.731182 DramcWriteLeveling(PI) end<-----
3473 16:34:14.731236
3474 16:34:14.731288 ==
3475 16:34:14.731340 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 16:34:14.731394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 16:34:14.731447 ==
3478 16:34:14.731500 [Gating] SW mode calibration
3479 16:34:14.731553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3480 16:34:14.731606 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3481 16:34:14.731659 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3482 16:34:14.731712 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 16:34:14.731765 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 16:34:14.731819 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 16:34:14.731872 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 16:34:14.731924 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3487 16:34:14.731977 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
3488 16:34:14.732030 0 15 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
3489 16:34:14.732083 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 16:34:14.732136 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 16:34:14.732189 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 16:34:14.732242 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 16:34:14.732295 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 16:34:14.732353 1 0 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
3495 16:34:14.732439 1 0 24 | B1->B0 | 2323 4444 | 1 0 | (0 0) (0 0)
3496 16:34:14.732523 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3497 16:34:14.732606 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 16:34:14.732688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 16:34:14.732765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 16:34:14.732821 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 16:34:14.732874 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 16:34:14.732928 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 16:34:14.732981 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3504 16:34:14.733040 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3505 16:34:14.733099 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 16:34:14.733153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 16:34:14.733206 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 16:34:14.733272 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 16:34:14.733334 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 16:34:14.733394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 16:34:14.733448 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 16:34:14.733502 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 16:34:14.733555 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 16:34:14.733607 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 16:34:14.733660 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 16:34:14.733713 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 16:34:14.733769 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 16:34:14.733825 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 16:34:14.733884 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3520 16:34:14.733938 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3521 16:34:14.733992 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 16:34:14.734044 Total UI for P1: 0, mck2ui 16
3523 16:34:14.734098 best dqsien dly found for B0: ( 1, 3, 26)
3524 16:34:14.734151 Total UI for P1: 0, mck2ui 16
3525 16:34:14.734204 best dqsien dly found for B1: ( 1, 3, 28)
3526 16:34:14.734256 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3527 16:34:14.734309 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3528 16:34:14.734362
3529 16:34:14.734418 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3530 16:34:14.734476 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3531 16:34:14.734530 [Gating] SW calibration Done
3532 16:34:14.734583 ==
3533 16:34:14.734636 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 16:34:14.734702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 16:34:14.734754 ==
3536 16:34:14.734806 RX Vref Scan: 0
3537 16:34:14.734857
3538 16:34:14.734911 RX Vref 0 -> 0, step: 1
3539 16:34:14.734963
3540 16:34:14.735013 RX Delay -40 -> 252, step: 8
3541 16:34:14.735065 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3542 16:34:14.735116 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3543 16:34:14.735174 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3544 16:34:14.735231 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3545 16:34:14.735284 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3546 16:34:14.735336 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3547 16:34:14.735387 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3548 16:34:14.735439 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3549 16:34:14.735490 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3550 16:34:14.735545 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3551 16:34:14.735597 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3552 16:34:14.735650 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3553 16:34:14.735701 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3554 16:34:14.735758 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3555 16:34:14.735812 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3556 16:34:14.735864 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3557 16:34:14.735916 ==
3558 16:34:14.735968 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 16:34:14.736019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 16:34:14.736071 ==
3561 16:34:14.736123 DQS Delay:
3562 16:34:14.736174 DQS0 = 0, DQS1 = 0
3563 16:34:14.736225 DQM Delay:
3564 16:34:14.736277 DQM0 = 116, DQM1 = 112
3565 16:34:14.736328 DQ Delay:
3566 16:34:14.736379 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3567 16:34:14.736431 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =119
3568 16:34:14.736483 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3569 16:34:14.736535 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3570 16:34:14.736587
3571 16:34:14.736638
3572 16:34:14.736689 ==
3573 16:34:14.736935 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 16:34:14.736994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 16:34:14.737047 ==
3576 16:34:14.737099
3577 16:34:14.737151
3578 16:34:14.737203 TX Vref Scan disable
3579 16:34:14.737254 == TX Byte 0 ==
3580 16:34:14.737347 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3581 16:34:14.737399 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3582 16:34:14.737451 == TX Byte 1 ==
3583 16:34:14.737503 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3584 16:34:14.737555 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3585 16:34:14.737607 ==
3586 16:34:14.737658 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 16:34:14.737711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 16:34:14.737763 ==
3589 16:34:14.737815 TX Vref=22, minBit 3, minWin=25, winSum=421
3590 16:34:14.737867 TX Vref=24, minBit 6, minWin=25, winSum=431
3591 16:34:14.737919 TX Vref=26, minBit 0, minWin=26, winSum=431
3592 16:34:14.737971 TX Vref=28, minBit 0, minWin=26, winSum=435
3593 16:34:14.738023 TX Vref=30, minBit 0, minWin=26, winSum=434
3594 16:34:14.738075 TX Vref=32, minBit 1, minWin=26, winSum=434
3595 16:34:14.738146 [TxChooseVref] Worse bit 0, Min win 26, Win sum 435, Final Vref 28
3596 16:34:14.738213
3597 16:34:14.738265 Final TX Range 1 Vref 28
3598 16:34:14.738317
3599 16:34:14.738368 ==
3600 16:34:14.738419 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 16:34:14.738471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 16:34:14.738523 ==
3603 16:34:14.738575
3604 16:34:14.738626
3605 16:34:14.738676 TX Vref Scan disable
3606 16:34:14.738728 == TX Byte 0 ==
3607 16:34:14.738779 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3608 16:34:14.738832 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3609 16:34:14.738883 == TX Byte 1 ==
3610 16:34:14.738935 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3611 16:34:14.738987 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3612 16:34:14.739038
3613 16:34:14.739089 [DATLAT]
3614 16:34:14.739140 Freq=1200, CH1 RK1
3615 16:34:14.739192
3616 16:34:14.739242 DATLAT Default: 0xd
3617 16:34:14.739294 0, 0xFFFF, sum = 0
3618 16:34:14.739347 1, 0xFFFF, sum = 0
3619 16:34:14.739399 2, 0xFFFF, sum = 0
3620 16:34:14.739452 3, 0xFFFF, sum = 0
3621 16:34:14.739504 4, 0xFFFF, sum = 0
3622 16:34:14.739556 5, 0xFFFF, sum = 0
3623 16:34:14.739608 6, 0xFFFF, sum = 0
3624 16:34:14.739660 7, 0xFFFF, sum = 0
3625 16:34:14.739713 8, 0xFFFF, sum = 0
3626 16:34:14.739765 9, 0xFFFF, sum = 0
3627 16:34:14.739818 10, 0xFFFF, sum = 0
3628 16:34:14.739870 11, 0xFFFF, sum = 0
3629 16:34:14.739922 12, 0x0, sum = 1
3630 16:34:14.740013 13, 0x0, sum = 2
3631 16:34:14.740066 14, 0x0, sum = 3
3632 16:34:14.740118 15, 0x0, sum = 4
3633 16:34:14.740170 best_step = 13
3634 16:34:14.740221
3635 16:34:14.740273 ==
3636 16:34:14.740324 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 16:34:14.740375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 16:34:14.740427 ==
3639 16:34:14.740479 RX Vref Scan: 0
3640 16:34:14.740531
3641 16:34:14.740582 RX Vref 0 -> 0, step: 1
3642 16:34:14.740633
3643 16:34:14.740684 RX Delay -13 -> 252, step: 4
3644 16:34:14.740736 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3645 16:34:14.740788 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3646 16:34:14.740840 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3647 16:34:14.740891 iDelay=191, Bit 3, Center 114 (51 ~ 178) 128
3648 16:34:14.740943 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3649 16:34:14.740994 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3650 16:34:14.741045 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3651 16:34:14.741096 iDelay=191, Bit 7, Center 114 (47 ~ 182) 136
3652 16:34:14.741147 iDelay=191, Bit 8, Center 102 (43 ~ 162) 120
3653 16:34:14.741199 iDelay=191, Bit 9, Center 104 (43 ~ 166) 124
3654 16:34:14.741251 iDelay=191, Bit 10, Center 116 (55 ~ 178) 124
3655 16:34:14.741340 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3656 16:34:14.741393 iDelay=191, Bit 12, Center 122 (63 ~ 182) 120
3657 16:34:14.741445 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3658 16:34:14.741497 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3659 16:34:14.741548 iDelay=191, Bit 15, Center 124 (63 ~ 186) 124
3660 16:34:14.741600 ==
3661 16:34:14.741652 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 16:34:14.741703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 16:34:14.741755 ==
3664 16:34:14.741806 DQS Delay:
3665 16:34:14.741858 DQS0 = 0, DQS1 = 0
3666 16:34:14.741909 DQM Delay:
3667 16:34:14.741960 DQM0 = 115, DQM1 = 113
3668 16:34:14.742011 DQ Delay:
3669 16:34:14.742063 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =114
3670 16:34:14.742114 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =114
3671 16:34:14.742166 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =106
3672 16:34:14.742218 DQ12 =122, DQ13 =118, DQ14 =116, DQ15 =124
3673 16:34:14.742269
3674 16:34:14.742320
3675 16:34:14.742372 [DQSOSCAuto] RK1, (LSB)MR18= 0xf708, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3676 16:34:14.742425 CH1 RK1: MR19=304, MR18=F708
3677 16:34:14.742476 CH1_RK1: MR19=0x304, MR18=0xF708, DQSOSC=406, MR23=63, INC=39, DEC=26
3678 16:34:14.742528 [RxdqsGatingPostProcess] freq 1200
3679 16:34:14.742581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3680 16:34:14.742633 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 16:34:14.742685 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 16:34:14.742736 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 16:34:14.742787 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 16:34:14.742839 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 16:34:14.742891 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 16:34:14.742943 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 16:34:14.742995 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 16:34:14.743046 Pre-setting of DQS Precalculation
3689 16:34:14.743098 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3690 16:34:14.743149 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3691 16:34:14.743202 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3692 16:34:14.743254
3693 16:34:14.743305
3694 16:34:14.743356 [Calibration Summary] 2400 Mbps
3695 16:34:14.743407 CH 0, Rank 0
3696 16:34:14.743459 SW Impedance : PASS
3697 16:34:14.743510 DUTY Scan : NO K
3698 16:34:14.743562 ZQ Calibration : PASS
3699 16:34:14.743613 Jitter Meter : NO K
3700 16:34:14.743665 CBT Training : PASS
3701 16:34:14.743716 Write leveling : PASS
3702 16:34:14.743767 RX DQS gating : PASS
3703 16:34:14.743818 RX DQ/DQS(RDDQC) : PASS
3704 16:34:14.743869 TX DQ/DQS : PASS
3705 16:34:14.743921 RX DATLAT : PASS
3706 16:34:14.743972 RX DQ/DQS(Engine): PASS
3707 16:34:14.744024 TX OE : NO K
3708 16:34:14.744076 All Pass.
3709 16:34:14.744127
3710 16:34:14.744177 CH 0, Rank 1
3711 16:34:14.744229 SW Impedance : PASS
3712 16:34:14.744280 DUTY Scan : NO K
3713 16:34:14.744331 ZQ Calibration : PASS
3714 16:34:14.744575 Jitter Meter : NO K
3715 16:34:14.744633 CBT Training : PASS
3716 16:34:14.744685 Write leveling : PASS
3717 16:34:14.744737 RX DQS gating : PASS
3718 16:34:14.744788 RX DQ/DQS(RDDQC) : PASS
3719 16:34:14.744840 TX DQ/DQS : PASS
3720 16:34:14.744891 RX DATLAT : PASS
3721 16:34:14.744943 RX DQ/DQS(Engine): PASS
3722 16:34:14.744994 TX OE : NO K
3723 16:34:14.745046 All Pass.
3724 16:34:14.745098
3725 16:34:14.745148 CH 1, Rank 0
3726 16:34:14.745200 SW Impedance : PASS
3727 16:34:14.745251 DUTY Scan : NO K
3728 16:34:14.745348 ZQ Calibration : PASS
3729 16:34:14.745400 Jitter Meter : NO K
3730 16:34:14.745451 CBT Training : PASS
3731 16:34:14.745503 Write leveling : PASS
3732 16:34:14.745554 RX DQS gating : PASS
3733 16:34:14.745605 RX DQ/DQS(RDDQC) : PASS
3734 16:34:14.745657 TX DQ/DQS : PASS
3735 16:34:14.745709 RX DATLAT : PASS
3736 16:34:14.745759 RX DQ/DQS(Engine): PASS
3737 16:34:14.745811 TX OE : NO K
3738 16:34:14.745862 All Pass.
3739 16:34:14.745913
3740 16:34:14.745964 CH 1, Rank 1
3741 16:34:14.746015 SW Impedance : PASS
3742 16:34:14.746067 DUTY Scan : NO K
3743 16:34:14.746118 ZQ Calibration : PASS
3744 16:34:14.746169 Jitter Meter : NO K
3745 16:34:14.746220 CBT Training : PASS
3746 16:34:14.746272 Write leveling : PASS
3747 16:34:14.746322 RX DQS gating : PASS
3748 16:34:14.746373 RX DQ/DQS(RDDQC) : PASS
3749 16:34:14.746425 TX DQ/DQS : PASS
3750 16:34:14.746477 RX DATLAT : PASS
3751 16:34:14.746528 RX DQ/DQS(Engine): PASS
3752 16:34:14.746579 TX OE : NO K
3753 16:34:14.746631 All Pass.
3754 16:34:14.746682
3755 16:34:14.746733 DramC Write-DBI off
3756 16:34:14.746784 PER_BANK_REFRESH: Hybrid Mode
3757 16:34:14.746836 TX_TRACKING: ON
3758 16:34:14.746888 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3759 16:34:14.746940 [FAST_K] Save calibration result to emmc
3760 16:34:14.746992 dramc_set_vcore_voltage set vcore to 650000
3761 16:34:14.747044 Read voltage for 600, 5
3762 16:34:14.747095 Vio18 = 0
3763 16:34:14.747147 Vcore = 650000
3764 16:34:14.747199 Vdram = 0
3765 16:34:14.747249 Vddq = 0
3766 16:34:14.747300 Vmddr = 0
3767 16:34:14.747352 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3768 16:34:14.747404 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3769 16:34:14.747455 MEM_TYPE=3, freq_sel=19
3770 16:34:14.747506 sv_algorithm_assistance_LP4_1600
3771 16:34:14.747557 ============ PULL DRAM RESETB DOWN ============
3772 16:34:14.747609 ========== PULL DRAM RESETB DOWN end =========
3773 16:34:14.747662 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3774 16:34:14.747713 ===================================
3775 16:34:14.747775 LPDDR4 DRAM CONFIGURATION
3776 16:34:14.747831 ===================================
3777 16:34:14.747883 EX_ROW_EN[0] = 0x0
3778 16:34:14.747934 EX_ROW_EN[1] = 0x0
3779 16:34:14.747985 LP4Y_EN = 0x0
3780 16:34:14.748037 WORK_FSP = 0x0
3781 16:34:14.748088 WL = 0x2
3782 16:34:14.748139 RL = 0x2
3783 16:34:14.748190 BL = 0x2
3784 16:34:14.748241 RPST = 0x0
3785 16:34:14.748293 RD_PRE = 0x0
3786 16:34:14.748344 WR_PRE = 0x1
3787 16:34:14.748394 WR_PST = 0x0
3788 16:34:14.748446 DBI_WR = 0x0
3789 16:34:14.748497 DBI_RD = 0x0
3790 16:34:14.748548 OTF = 0x1
3791 16:34:14.748599 ===================================
3792 16:34:14.748651 ===================================
3793 16:34:14.748703 ANA top config
3794 16:34:14.748754 ===================================
3795 16:34:14.748806 DLL_ASYNC_EN = 0
3796 16:34:14.748857 ALL_SLAVE_EN = 1
3797 16:34:14.748953 NEW_RANK_MODE = 1
3798 16:34:14.749005 DLL_IDLE_MODE = 1
3799 16:34:14.749057 LP45_APHY_COMB_EN = 1
3800 16:34:14.749108 TX_ODT_DIS = 1
3801 16:34:14.749160 NEW_8X_MODE = 1
3802 16:34:14.749212 ===================================
3803 16:34:14.749272 ===================================
3804 16:34:14.749361 data_rate = 1200
3805 16:34:14.749413 CKR = 1
3806 16:34:14.749465 DQ_P2S_RATIO = 8
3807 16:34:14.749516 ===================================
3808 16:34:14.749568 CA_P2S_RATIO = 8
3809 16:34:14.749619 DQ_CA_OPEN = 0
3810 16:34:14.749670 DQ_SEMI_OPEN = 0
3811 16:34:14.749722 CA_SEMI_OPEN = 0
3812 16:34:14.749774 CA_FULL_RATE = 0
3813 16:34:14.749825 DQ_CKDIV4_EN = 1
3814 16:34:14.749876 CA_CKDIV4_EN = 1
3815 16:34:14.749928 CA_PREDIV_EN = 0
3816 16:34:14.749979 PH8_DLY = 0
3817 16:34:14.750030 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3818 16:34:14.750081 DQ_AAMCK_DIV = 4
3819 16:34:14.750133 CA_AAMCK_DIV = 4
3820 16:34:14.750184 CA_ADMCK_DIV = 4
3821 16:34:14.750236 DQ_TRACK_CA_EN = 0
3822 16:34:14.750288 CA_PICK = 600
3823 16:34:14.750339 CA_MCKIO = 600
3824 16:34:14.750391 MCKIO_SEMI = 0
3825 16:34:14.750442 PLL_FREQ = 2288
3826 16:34:14.750494 DQ_UI_PI_RATIO = 32
3827 16:34:14.750545 CA_UI_PI_RATIO = 0
3828 16:34:14.750596 ===================================
3829 16:34:14.750648 ===================================
3830 16:34:14.750700 memory_type:LPDDR4
3831 16:34:14.750752 GP_NUM : 10
3832 16:34:14.750803 SRAM_EN : 1
3833 16:34:14.750855 MD32_EN : 0
3834 16:34:14.750906 ===================================
3835 16:34:14.750958 [ANA_INIT] >>>>>>>>>>>>>>
3836 16:34:14.751009 <<<<<< [CONFIGURE PHASE]: ANA_TX
3837 16:34:14.751061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3838 16:34:14.751113 ===================================
3839 16:34:14.751164 data_rate = 1200,PCW = 0X5800
3840 16:34:14.751215 ===================================
3841 16:34:14.751267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3842 16:34:14.751319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 16:34:14.751371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 16:34:14.751423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3845 16:34:14.751475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3846 16:34:14.751526 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3847 16:34:14.751577 [ANA_INIT] flow start
3848 16:34:14.751629 [ANA_INIT] PLL >>>>>>>>
3849 16:34:14.751680 [ANA_INIT] PLL <<<<<<<<
3850 16:34:14.751731 [ANA_INIT] MIDPI >>>>>>>>
3851 16:34:14.751781 [ANA_INIT] MIDPI <<<<<<<<
3852 16:34:14.751832 [ANA_INIT] DLL >>>>>>>>
3853 16:34:14.751883 [ANA_INIT] flow end
3854 16:34:14.752127 ============ LP4 DIFF to SE enter ============
3855 16:34:14.752186 ============ LP4 DIFF to SE exit ============
3856 16:34:14.752240 [ANA_INIT] <<<<<<<<<<<<<
3857 16:34:14.752292 [Flow] Enable top DCM control >>>>>
3858 16:34:14.752344 [Flow] Enable top DCM control <<<<<
3859 16:34:14.752395 Enable DLL master slave shuffle
3860 16:34:14.752447 ==============================================================
3861 16:34:14.752499 Gating Mode config
3862 16:34:14.752550 ==============================================================
3863 16:34:14.752602 Config description:
3864 16:34:14.752654 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3865 16:34:14.752707 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3866 16:34:14.752758 SELPH_MODE 0: By rank 1: By Phase
3867 16:34:14.752810 ==============================================================
3868 16:34:14.752868 GAT_TRACK_EN = 1
3869 16:34:14.752992 RX_GATING_MODE = 2
3870 16:34:14.753057 RX_GATING_TRACK_MODE = 2
3871 16:34:14.753110 SELPH_MODE = 1
3872 16:34:14.753162 PICG_EARLY_EN = 1
3873 16:34:14.753214 VALID_LAT_VALUE = 1
3874 16:34:14.753290 ==============================================================
3875 16:34:14.753359 Enter into Gating configuration >>>>
3876 16:34:14.753412 Exit from Gating configuration <<<<
3877 16:34:14.753463 Enter into DVFS_PRE_config >>>>>
3878 16:34:14.753516 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3879 16:34:14.753570 Exit from DVFS_PRE_config <<<<<
3880 16:34:14.753621 Enter into PICG configuration >>>>
3881 16:34:14.753673 Exit from PICG configuration <<<<
3882 16:34:14.753724 [RX_INPUT] configuration >>>>>
3883 16:34:14.753775 [RX_INPUT] configuration <<<<<
3884 16:34:14.753827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3885 16:34:14.753879 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3886 16:34:14.753931 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 16:34:14.753983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 16:34:14.754035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 16:34:14.754086 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 16:34:14.754138 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3891 16:34:14.754189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3892 16:34:14.754241 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3893 16:34:14.754293 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3894 16:34:14.754344 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3895 16:34:14.754396 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 16:34:14.754448 ===================================
3897 16:34:14.754500 LPDDR4 DRAM CONFIGURATION
3898 16:34:14.754552 ===================================
3899 16:34:14.754604 EX_ROW_EN[0] = 0x0
3900 16:34:14.754655 EX_ROW_EN[1] = 0x0
3901 16:34:14.754707 LP4Y_EN = 0x0
3902 16:34:14.754758 WORK_FSP = 0x0
3903 16:34:14.754809 WL = 0x2
3904 16:34:14.754860 RL = 0x2
3905 16:34:14.754911 BL = 0x2
3906 16:34:14.754963 RPST = 0x0
3907 16:34:14.755014 RD_PRE = 0x0
3908 16:34:14.755066 WR_PRE = 0x1
3909 16:34:14.755117 WR_PST = 0x0
3910 16:34:14.755168 DBI_WR = 0x0
3911 16:34:14.755219 DBI_RD = 0x0
3912 16:34:14.755270 OTF = 0x1
3913 16:34:14.755321 ===================================
3914 16:34:14.755373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3915 16:34:14.755425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3916 16:34:14.755477 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 16:34:14.755529 ===================================
3918 16:34:14.755581 LPDDR4 DRAM CONFIGURATION
3919 16:34:14.755633 ===================================
3920 16:34:14.755684 EX_ROW_EN[0] = 0x10
3921 16:34:14.755736 EX_ROW_EN[1] = 0x0
3922 16:34:14.755786 LP4Y_EN = 0x0
3923 16:34:14.755838 WORK_FSP = 0x0
3924 16:34:14.755889 WL = 0x2
3925 16:34:14.755941 RL = 0x2
3926 16:34:14.755991 BL = 0x2
3927 16:34:14.756042 RPST = 0x0
3928 16:34:14.756094 RD_PRE = 0x0
3929 16:34:14.756145 WR_PRE = 0x1
3930 16:34:14.756195 WR_PST = 0x0
3931 16:34:14.756246 DBI_WR = 0x0
3932 16:34:14.756296 DBI_RD = 0x0
3933 16:34:14.756348 OTF = 0x1
3934 16:34:14.756399 ===================================
3935 16:34:14.756451 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3936 16:34:14.756503 nWR fixed to 30
3937 16:34:14.756555 [ModeRegInit_LP4] CH0 RK0
3938 16:34:14.756606 [ModeRegInit_LP4] CH0 RK1
3939 16:34:14.756658 [ModeRegInit_LP4] CH1 RK0
3940 16:34:14.756709 [ModeRegInit_LP4] CH1 RK1
3941 16:34:14.756760 match AC timing 17
3942 16:34:14.756812 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3943 16:34:14.756864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3944 16:34:14.756915 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3945 16:34:14.756967 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3946 16:34:14.757019 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3947 16:34:14.757071 ==
3948 16:34:14.757123 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 16:34:14.757175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 16:34:14.757227 ==
3951 16:34:14.757334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 16:34:14.759492 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3953 16:34:14.762836 [CA 0] Center 36 (6~67) winsize 62
3954 16:34:14.766064 [CA 1] Center 36 (6~66) winsize 61
3955 16:34:14.769426 [CA 2] Center 34 (4~65) winsize 62
3956 16:34:14.772782 [CA 3] Center 34 (3~65) winsize 63
3957 16:34:14.776281 [CA 4] Center 33 (3~64) winsize 62
3958 16:34:14.779533 [CA 5] Center 33 (3~64) winsize 62
3959 16:34:14.779614
3960 16:34:14.782954 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3961 16:34:14.783060
3962 16:34:14.785786 [CATrainingPosCal] consider 1 rank data
3963 16:34:14.789204 u2DelayCellTimex100 = 270/100 ps
3964 16:34:14.792446 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3965 16:34:14.795698 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3966 16:34:14.799018 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 16:34:14.805627 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3968 16:34:14.808924 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 16:34:14.812344 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 16:34:14.812418
3971 16:34:14.815571 CA PerBit enable=1, Macro0, CA PI delay=33
3972 16:34:14.815652
3973 16:34:14.818886 [CBTSetCACLKResult] CA Dly = 33
3974 16:34:14.818994 CS Dly: 4 (0~35)
3975 16:34:14.819085 ==
3976 16:34:14.822109 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 16:34:14.828639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 16:34:14.828726 ==
3979 16:34:14.832501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 16:34:14.838615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3981 16:34:14.842325 [CA 0] Center 36 (6~67) winsize 62
3982 16:34:14.845783 [CA 1] Center 36 (6~67) winsize 62
3983 16:34:14.848918 [CA 2] Center 34 (4~65) winsize 62
3984 16:34:14.852151 [CA 3] Center 34 (4~65) winsize 62
3985 16:34:14.855071 [CA 4] Center 34 (3~65) winsize 63
3986 16:34:14.858882 [CA 5] Center 33 (3~64) winsize 62
3987 16:34:14.858978
3988 16:34:14.861997 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3989 16:34:14.862092
3990 16:34:14.865241 [CATrainingPosCal] consider 2 rank data
3991 16:34:14.868414 u2DelayCellTimex100 = 270/100 ps
3992 16:34:14.871608 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 16:34:14.878232 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3994 16:34:14.889335 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 16:34:14.889484 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 16:34:14.889601 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 16:34:14.891521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 16:34:14.891689
3999 16:34:14.894962 CA PerBit enable=1, Macro0, CA PI delay=33
4000 16:34:14.895151
4001 16:34:14.898239 [CBTSetCACLKResult] CA Dly = 33
4002 16:34:14.901738 CS Dly: 5 (0~37)
4003 16:34:14.901907
4004 16:34:14.904955 ----->DramcWriteLeveling(PI) begin...
4005 16:34:14.905180 ==
4006 16:34:14.908322 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 16:34:14.911557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 16:34:14.911729 ==
4009 16:34:14.914931 Write leveling (Byte 0): 34 => 34
4010 16:34:14.918427 Write leveling (Byte 1): 30 => 30
4011 16:34:14.921165 DramcWriteLeveling(PI) end<-----
4012 16:34:14.921377
4013 16:34:14.921568 ==
4014 16:34:14.925087 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 16:34:14.928408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 16:34:14.928631 ==
4017 16:34:14.931096 [Gating] SW mode calibration
4018 16:34:14.938240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4019 16:34:14.944746 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4020 16:34:14.947895 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 16:34:14.950928 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 16:34:14.957982 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 16:34:14.961111 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4024 16:34:14.964629 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
4025 16:34:14.971027 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 16:34:14.974023 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 16:34:14.977692 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 16:34:14.984234 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 16:34:14.987492 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 16:34:14.991009 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 16:34:14.997563 0 10 12 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4032 16:34:15.000288 0 10 16 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
4033 16:34:15.003751 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 16:34:15.010617 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 16:34:15.013953 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 16:34:15.017067 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 16:34:15.023702 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 16:34:15.026854 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 16:34:15.030021 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 16:34:15.036780 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 16:34:15.039877 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 16:34:15.043578 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 16:34:15.050285 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 16:34:15.053563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 16:34:15.056936 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 16:34:15.063527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 16:34:15.067054 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 16:34:15.070252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 16:34:15.076711 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 16:34:15.080013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 16:34:15.083238 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 16:34:15.089662 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 16:34:15.092775 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 16:34:15.096577 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 16:34:15.102694 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4056 16:34:15.105921 Total UI for P1: 0, mck2ui 16
4057 16:34:15.109214 best dqsien dly found for B0: ( 0, 13, 10)
4058 16:34:15.112818 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 16:34:15.116161 Total UI for P1: 0, mck2ui 16
4060 16:34:15.119463 best dqsien dly found for B1: ( 0, 13, 14)
4061 16:34:15.122696 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4062 16:34:15.126141 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4063 16:34:15.126445
4064 16:34:15.129360 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4065 16:34:15.135123 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4066 16:34:15.135359 [Gating] SW calibration Done
4067 16:34:15.138441 ==
4068 16:34:15.138644 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 16:34:15.145175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 16:34:15.145379 ==
4071 16:34:15.145487 RX Vref Scan: 0
4072 16:34:15.145584
4073 16:34:15.148726 RX Vref 0 -> 0, step: 1
4074 16:34:15.148886
4075 16:34:15.151509 RX Delay -230 -> 252, step: 16
4076 16:34:15.154829 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4077 16:34:15.158327 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4078 16:34:15.165066 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4079 16:34:15.168316 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4080 16:34:15.171341 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4081 16:34:15.175076 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4082 16:34:15.181177 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4083 16:34:15.184611 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4084 16:34:15.188829 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4085 16:34:15.192049 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4086 16:34:15.194997 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4087 16:34:15.201523 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4088 16:34:15.204552 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4089 16:34:15.207999 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4090 16:34:15.214328 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4091 16:34:15.217505 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4092 16:34:15.217693 ==
4093 16:34:15.220629 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 16:34:15.224450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 16:34:15.224807 ==
4096 16:34:15.227174 DQS Delay:
4097 16:34:15.227384 DQS0 = 0, DQS1 = 0
4098 16:34:15.227554 DQM Delay:
4099 16:34:15.230626 DQM0 = 46, DQM1 = 36
4100 16:34:15.230847 DQ Delay:
4101 16:34:15.233916 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4102 16:34:15.237324 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4103 16:34:15.241183 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4104 16:34:15.243924 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4105 16:34:15.244144
4106 16:34:15.244315
4107 16:34:15.244474 ==
4108 16:34:15.247222 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 16:34:15.253963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 16:34:15.254238 ==
4111 16:34:15.254463
4112 16:34:15.254629
4113 16:34:15.254830 TX Vref Scan disable
4114 16:34:15.257316 == TX Byte 0 ==
4115 16:34:15.260790 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4116 16:34:15.267697 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4117 16:34:15.267924 == TX Byte 1 ==
4118 16:34:15.270462 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4119 16:34:15.277093 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4120 16:34:15.277349 ==
4121 16:34:15.280570 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 16:34:15.283717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 16:34:15.283968 ==
4124 16:34:15.284224
4125 16:34:15.284394
4126 16:34:15.286921 TX Vref Scan disable
4127 16:34:15.290562 == TX Byte 0 ==
4128 16:34:15.293528 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4129 16:34:15.297052 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4130 16:34:15.300505 == TX Byte 1 ==
4131 16:34:15.303641 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4132 16:34:15.306738 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4133 16:34:15.306967
4134 16:34:15.310402 [DATLAT]
4135 16:34:15.310685 Freq=600, CH0 RK0
4136 16:34:15.310869
4137 16:34:15.313914 DATLAT Default: 0x9
4138 16:34:15.314363 0, 0xFFFF, sum = 0
4139 16:34:15.316891 1, 0xFFFF, sum = 0
4140 16:34:15.317390 2, 0xFFFF, sum = 0
4141 16:34:15.320392 3, 0xFFFF, sum = 0
4142 16:34:15.320817 4, 0xFFFF, sum = 0
4143 16:34:15.323630 5, 0xFFFF, sum = 0
4144 16:34:15.324056 6, 0xFFFF, sum = 0
4145 16:34:15.326925 7, 0xFFFF, sum = 0
4146 16:34:15.327348 8, 0x0, sum = 1
4147 16:34:15.330211 9, 0x0, sum = 2
4148 16:34:15.330736 10, 0x0, sum = 3
4149 16:34:15.333377 11, 0x0, sum = 4
4150 16:34:15.333938 best_step = 9
4151 16:34:15.334288
4152 16:34:15.334595 ==
4153 16:34:15.336633 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 16:34:15.343053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 16:34:15.343490 ==
4156 16:34:15.343815 RX Vref Scan: 1
4157 16:34:15.344286
4158 16:34:15.346208 RX Vref 0 -> 0, step: 1
4159 16:34:15.346626
4160 16:34:15.349395 RX Delay -179 -> 252, step: 8
4161 16:34:15.349814
4162 16:34:15.353465 Set Vref, RX VrefLevel [Byte0]: 58
4163 16:34:15.356602 [Byte1]: 49
4164 16:34:15.357182
4165 16:34:15.359220 Final RX Vref Byte 0 = 58 to rank0
4166 16:34:15.362567 Final RX Vref Byte 1 = 49 to rank0
4167 16:34:15.366087 Final RX Vref Byte 0 = 58 to rank1
4168 16:34:15.369429 Final RX Vref Byte 1 = 49 to rank1==
4169 16:34:15.372661 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 16:34:15.375597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 16:34:15.376057 ==
4172 16:34:15.379049 DQS Delay:
4173 16:34:15.379459 DQS0 = 0, DQS1 = 0
4174 16:34:15.382198 DQM Delay:
4175 16:34:15.382609 DQM0 = 44, DQM1 = 36
4176 16:34:15.382930 DQ Delay:
4177 16:34:15.385392 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4178 16:34:15.388755 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4179 16:34:15.392188 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4180 16:34:15.395576 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4181 16:34:15.395796
4182 16:34:15.395966
4183 16:34:15.405684 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4184 16:34:15.408834 CH0 RK0: MR19=808, MR18=4A42
4185 16:34:15.415527 CH0_RK0: MR19=0x808, MR18=0x4A42, DQSOSC=395, MR23=63, INC=168, DEC=112
4186 16:34:15.415964
4187 16:34:15.419149 ----->DramcWriteLeveling(PI) begin...
4188 16:34:15.419574 ==
4189 16:34:15.422125 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 16:34:15.425534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 16:34:15.425956 ==
4192 16:34:15.428779 Write leveling (Byte 0): 31 => 31
4193 16:34:15.432120 Write leveling (Byte 1): 30 => 30
4194 16:34:15.435608 DramcWriteLeveling(PI) end<-----
4195 16:34:15.436024
4196 16:34:15.436346 ==
4197 16:34:15.438223 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 16:34:15.441964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 16:34:15.442380 ==
4200 16:34:15.445072 [Gating] SW mode calibration
4201 16:34:15.451528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4202 16:34:15.458080 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4203 16:34:15.461673 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 16:34:15.464928 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 16:34:15.471480 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 16:34:15.474914 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 1)
4207 16:34:15.478155 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4208 16:34:15.484745 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 16:34:15.488023 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 16:34:15.491363 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 16:34:15.498050 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 16:34:15.501450 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 16:34:15.504538 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4214 16:34:15.511027 0 10 12 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
4215 16:34:15.514137 0 10 16 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
4216 16:34:15.517200 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 16:34:15.524185 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 16:34:15.527718 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 16:34:15.530765 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 16:34:15.537233 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 16:34:15.540573 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 16:34:15.544283 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4223 16:34:15.550124 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 16:34:15.553828 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 16:34:15.557284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 16:34:15.563857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 16:34:15.566793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 16:34:15.569989 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 16:34:15.576847 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 16:34:15.580093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 16:34:15.586364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 16:34:15.589775 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 16:34:15.592964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 16:34:15.599727 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 16:34:15.602458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 16:34:15.605777 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 16:34:15.612376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 16:34:15.615568 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4239 16:34:15.619725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4240 16:34:15.622709 Total UI for P1: 0, mck2ui 16
4241 16:34:15.625809 best dqsien dly found for B0: ( 0, 13, 12)
4242 16:34:15.631916 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 16:34:15.632215 Total UI for P1: 0, mck2ui 16
4244 16:34:15.635903 best dqsien dly found for B1: ( 0, 13, 14)
4245 16:34:15.642268 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4246 16:34:15.645609 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4247 16:34:15.645838
4248 16:34:15.648780 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4249 16:34:15.652391 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4250 16:34:15.655363 [Gating] SW calibration Done
4251 16:34:15.655447 ==
4252 16:34:15.658347 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 16:34:15.661628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 16:34:15.661713 ==
4255 16:34:15.665207 RX Vref Scan: 0
4256 16:34:15.665334
4257 16:34:15.665422 RX Vref 0 -> 0, step: 1
4258 16:34:15.665511
4259 16:34:15.668767 RX Delay -230 -> 252, step: 16
4260 16:34:15.675306 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4261 16:34:15.678415 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4262 16:34:15.681553 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4263 16:34:15.685031 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4264 16:34:15.688120 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4265 16:34:15.694706 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4266 16:34:15.698051 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4267 16:34:15.701456 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4268 16:34:15.704767 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4269 16:34:15.711297 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4270 16:34:15.714486 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4271 16:34:15.717837 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4272 16:34:15.721246 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4273 16:34:15.727941 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4274 16:34:15.731162 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4275 16:34:15.734292 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4276 16:34:15.734375 ==
4277 16:34:15.737560 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 16:34:15.740819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 16:34:15.744519 ==
4280 16:34:15.744602 DQS Delay:
4281 16:34:15.744665 DQS0 = 0, DQS1 = 0
4282 16:34:15.747737 DQM Delay:
4283 16:34:15.747818 DQM0 = 46, DQM1 = 36
4284 16:34:15.750929 DQ Delay:
4285 16:34:15.754090 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4286 16:34:15.754172 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4287 16:34:15.757199 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4288 16:34:15.763899 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4289 16:34:15.763984
4290 16:34:15.764047
4291 16:34:15.764104 ==
4292 16:34:15.767601 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 16:34:15.770687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 16:34:15.770770 ==
4295 16:34:15.770833
4296 16:34:15.770890
4297 16:34:15.774371 TX Vref Scan disable
4298 16:34:15.774453 == TX Byte 0 ==
4299 16:34:15.780242 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4300 16:34:15.784094 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4301 16:34:15.784202 == TX Byte 1 ==
4302 16:34:15.790154 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4303 16:34:15.793806 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4304 16:34:15.793890 ==
4305 16:34:15.796804 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 16:34:15.800402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 16:34:15.800488 ==
4308 16:34:15.800553
4309 16:34:15.803427
4310 16:34:15.803509 TX Vref Scan disable
4311 16:34:15.807279 == TX Byte 0 ==
4312 16:34:15.810577 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4313 16:34:15.817392 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4314 16:34:15.817475 == TX Byte 1 ==
4315 16:34:15.820549 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4316 16:34:15.827125 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4317 16:34:15.827203
4318 16:34:15.827265 [DATLAT]
4319 16:34:15.827324 Freq=600, CH0 RK1
4320 16:34:15.827381
4321 16:34:15.830394 DATLAT Default: 0x9
4322 16:34:15.833548 0, 0xFFFF, sum = 0
4323 16:34:15.833629 1, 0xFFFF, sum = 0
4324 16:34:15.836931 2, 0xFFFF, sum = 0
4325 16:34:15.837000 3, 0xFFFF, sum = 0
4326 16:34:15.840220 4, 0xFFFF, sum = 0
4327 16:34:15.840302 5, 0xFFFF, sum = 0
4328 16:34:15.843327 6, 0xFFFF, sum = 0
4329 16:34:15.843408 7, 0xFFFF, sum = 0
4330 16:34:15.846635 8, 0x0, sum = 1
4331 16:34:15.846717 9, 0x0, sum = 2
4332 16:34:15.849883 10, 0x0, sum = 3
4333 16:34:15.849991 11, 0x0, sum = 4
4334 16:34:15.850089 best_step = 9
4335 16:34:15.850151
4336 16:34:15.853078 ==
4337 16:34:15.856261 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 16:34:15.859507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 16:34:15.859591 ==
4340 16:34:15.859654 RX Vref Scan: 0
4341 16:34:15.859712
4342 16:34:15.863388 RX Vref 0 -> 0, step: 1
4343 16:34:15.863467
4344 16:34:15.866634 RX Delay -179 -> 252, step: 8
4345 16:34:15.872605 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4346 16:34:15.875865 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4347 16:34:15.879239 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4348 16:34:15.882872 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4349 16:34:15.889472 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4350 16:34:15.892583 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4351 16:34:15.895784 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4352 16:34:15.899074 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4353 16:34:15.902358 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4354 16:34:15.908815 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4355 16:34:15.912434 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4356 16:34:15.915290 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4357 16:34:15.919190 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4358 16:34:15.925796 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4359 16:34:15.928701 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4360 16:34:15.931916 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4361 16:34:15.932009 ==
4362 16:34:15.935204 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 16:34:15.938549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 16:34:15.941795 ==
4365 16:34:15.941904 DQS Delay:
4366 16:34:15.941988 DQS0 = 0, DQS1 = 0
4367 16:34:15.945019 DQM Delay:
4368 16:34:15.945127 DQM0 = 43, DQM1 = 36
4369 16:34:15.948414 DQ Delay:
4370 16:34:15.951517 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4371 16:34:15.951637 DQ4 =48, DQ5 =32, DQ6 =52, DQ7 =48
4372 16:34:15.954896 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4373 16:34:15.958218 DQ12 =36, DQ13 =40, DQ14 =48, DQ15 =44
4374 16:34:15.961607
4375 16:34:15.961782
4376 16:34:15.968329 [DQSOSCAuto] RK1, (LSB)MR18= 0x4844, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4377 16:34:15.971752 CH0 RK1: MR19=808, MR18=4844
4378 16:34:15.978716 CH0_RK1: MR19=0x808, MR18=0x4844, DQSOSC=396, MR23=63, INC=167, DEC=111
4379 16:34:15.981993 [RxdqsGatingPostProcess] freq 600
4380 16:34:15.985132 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 16:34:15.988288 Pre-setting of DQS Precalculation
4382 16:34:15.994863 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 16:34:15.995283 ==
4384 16:34:15.998210 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 16:34:16.001630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 16:34:16.002117 ==
4387 16:34:16.008006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 16:34:16.014655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4389 16:34:16.017888 [CA 0] Center 35 (5~66) winsize 62
4390 16:34:16.020948 [CA 1] Center 36 (6~66) winsize 61
4391 16:34:16.024149 [CA 2] Center 35 (5~65) winsize 61
4392 16:34:16.027716 [CA 3] Center 34 (3~65) winsize 63
4393 16:34:16.030940 [CA 4] Center 34 (4~65) winsize 62
4394 16:34:16.033964 [CA 5] Center 33 (3~64) winsize 62
4395 16:34:16.034705
4396 16:34:16.037924 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4397 16:34:16.038600
4398 16:34:16.040538 [CATrainingPosCal] consider 1 rank data
4399 16:34:16.043876 u2DelayCellTimex100 = 270/100 ps
4400 16:34:16.047172 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 16:34:16.050532 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4402 16:34:16.054533 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4403 16:34:16.057144 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4404 16:34:16.060871 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 16:34:16.064068 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 16:34:16.067240
4407 16:34:16.070298 CA PerBit enable=1, Macro0, CA PI delay=33
4408 16:34:16.070725
4409 16:34:16.074166 [CBTSetCACLKResult] CA Dly = 33
4410 16:34:16.074580 CS Dly: 4 (0~35)
4411 16:34:16.074899 ==
4412 16:34:16.076938 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 16:34:16.080059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 16:34:16.083483 ==
4415 16:34:16.086737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 16:34:16.093778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4417 16:34:16.096966 [CA 0] Center 36 (6~66) winsize 61
4418 16:34:16.100220 [CA 1] Center 35 (5~66) winsize 62
4419 16:34:16.103152 [CA 2] Center 34 (4~65) winsize 62
4420 16:34:16.106897 [CA 3] Center 34 (3~65) winsize 63
4421 16:34:16.110142 [CA 4] Center 34 (4~65) winsize 62
4422 16:34:16.113407 [CA 5] Center 34 (3~65) winsize 63
4423 16:34:16.113821
4424 16:34:16.116452 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4425 16:34:16.116860
4426 16:34:16.120166 [CATrainingPosCal] consider 2 rank data
4427 16:34:16.123323 u2DelayCellTimex100 = 270/100 ps
4428 16:34:16.126475 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4429 16:34:16.129969 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4430 16:34:16.136486 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4431 16:34:16.139368 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4432 16:34:16.143286 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 16:34:16.146288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 16:34:16.146703
4435 16:34:16.149715 CA PerBit enable=1, Macro0, CA PI delay=33
4436 16:34:16.150252
4437 16:34:16.153072 [CBTSetCACLKResult] CA Dly = 33
4438 16:34:16.153533 CS Dly: 5 (0~37)
4439 16:34:16.156170
4440 16:34:16.159760 ----->DramcWriteLeveling(PI) begin...
4441 16:34:16.160185 ==
4442 16:34:16.162411 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 16:34:16.165577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 16:34:16.166069 ==
4445 16:34:16.168670 Write leveling (Byte 0): 30 => 30
4446 16:34:16.172458 Write leveling (Byte 1): 30 => 30
4447 16:34:16.175583 DramcWriteLeveling(PI) end<-----
4448 16:34:16.176170
4449 16:34:16.176558 ==
4450 16:34:16.178954 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 16:34:16.182216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 16:34:16.182662 ==
4453 16:34:16.185623 [Gating] SW mode calibration
4454 16:34:16.192272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 16:34:16.198572 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 16:34:16.202005 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 16:34:16.205317 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 16:34:16.212185 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 16:34:16.215278 0 9 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
4460 16:34:16.218636 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4461 16:34:16.224989 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 16:34:16.227818 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 16:34:16.231097 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 16:34:16.237910 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 16:34:16.241163 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 16:34:16.244383 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 16:34:16.251303 0 10 12 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)
4468 16:34:16.254337 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 16:34:16.257554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 16:34:16.264366 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 16:34:16.267888 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 16:34:16.271196 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 16:34:16.277282 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 16:34:16.280605 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 16:34:16.283890 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4476 16:34:16.290583 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 16:34:16.294427 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 16:34:16.297566 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 16:34:16.304062 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 16:34:16.307351 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 16:34:16.310455 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 16:34:16.317377 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 16:34:16.320600 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 16:34:16.323829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 16:34:16.330332 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 16:34:16.333572 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 16:34:16.336766 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 16:34:16.343712 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 16:34:16.346767 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 16:34:16.350113 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 16:34:16.356769 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4492 16:34:16.360301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 16:34:16.363548 Total UI for P1: 0, mck2ui 16
4494 16:34:16.366774 best dqsien dly found for B0: ( 0, 13, 12)
4495 16:34:16.369756 Total UI for P1: 0, mck2ui 16
4496 16:34:16.373390 best dqsien dly found for B1: ( 0, 13, 12)
4497 16:34:16.376749 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4498 16:34:16.380176 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4499 16:34:16.380259
4500 16:34:16.383018 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4501 16:34:16.386605 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4502 16:34:16.389900 [Gating] SW calibration Done
4503 16:34:16.389975 ==
4504 16:34:16.393184 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 16:34:16.399975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 16:34:16.400062 ==
4507 16:34:16.400126 RX Vref Scan: 0
4508 16:34:16.400186
4509 16:34:16.402911 RX Vref 0 -> 0, step: 1
4510 16:34:16.403001
4511 16:34:16.406002 RX Delay -230 -> 252, step: 16
4512 16:34:16.409798 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4513 16:34:16.413031 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4514 16:34:16.416257 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4515 16:34:16.422347 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 16:34:16.425911 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 16:34:16.429386 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4518 16:34:16.432492 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4519 16:34:16.439222 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 16:34:16.442496 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4521 16:34:16.445703 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4522 16:34:16.448917 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4523 16:34:16.455727 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4524 16:34:16.458821 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 16:34:16.462063 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 16:34:16.465483 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4527 16:34:16.471846 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 16:34:16.471931 ==
4529 16:34:16.475085 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 16:34:16.478772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 16:34:16.478860 ==
4532 16:34:16.478944 DQS Delay:
4533 16:34:16.481879 DQS0 = 0, DQS1 = 0
4534 16:34:16.481978 DQM Delay:
4535 16:34:16.485201 DQM0 = 48, DQM1 = 40
4536 16:34:16.485324 DQ Delay:
4537 16:34:16.488311 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4538 16:34:16.492040 DQ4 =41, DQ5 =65, DQ6 =57, DQ7 =41
4539 16:34:16.494992 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4540 16:34:16.498361 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4541 16:34:16.498446
4542 16:34:16.498529
4543 16:34:16.498626 ==
4544 16:34:16.501563 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 16:34:16.505007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 16:34:16.505093 ==
4547 16:34:16.508251
4548 16:34:16.508358
4549 16:34:16.508441 TX Vref Scan disable
4550 16:34:16.511478 == TX Byte 0 ==
4551 16:34:16.514660 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4552 16:34:16.518097 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4553 16:34:16.521322 == TX Byte 1 ==
4554 16:34:16.524513 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 16:34:16.527718 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 16:34:16.531090 ==
4557 16:34:16.534436 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 16:34:16.537724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 16:34:16.537804 ==
4560 16:34:16.537884
4561 16:34:16.537961
4562 16:34:16.540893 TX Vref Scan disable
4563 16:34:16.540964 == TX Byte 0 ==
4564 16:34:16.547427 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4565 16:34:16.551123 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4566 16:34:16.554550 == TX Byte 1 ==
4567 16:34:16.557264 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4568 16:34:16.560563 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4569 16:34:16.560646
4570 16:34:16.560729 [DATLAT]
4571 16:34:16.564441 Freq=600, CH1 RK0
4572 16:34:16.564525
4573 16:34:16.564608 DATLAT Default: 0x9
4574 16:34:16.567547 0, 0xFFFF, sum = 0
4575 16:34:16.570827 1, 0xFFFF, sum = 0
4576 16:34:16.570912 2, 0xFFFF, sum = 0
4577 16:34:16.574121 3, 0xFFFF, sum = 0
4578 16:34:16.574269 4, 0xFFFF, sum = 0
4579 16:34:16.577519 5, 0xFFFF, sum = 0
4580 16:34:16.577601 6, 0xFFFF, sum = 0
4581 16:34:16.580652 7, 0xFFFF, sum = 0
4582 16:34:16.580734 8, 0x0, sum = 1
4583 16:34:16.583881 9, 0x0, sum = 2
4584 16:34:16.583963 10, 0x0, sum = 3
4585 16:34:16.587030 11, 0x0, sum = 4
4586 16:34:16.587111 best_step = 9
4587 16:34:16.587174
4588 16:34:16.587232 ==
4589 16:34:16.590653 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 16:34:16.593471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 16:34:16.593552 ==
4592 16:34:16.597323 RX Vref Scan: 1
4593 16:34:16.597404
4594 16:34:16.600436 RX Vref 0 -> 0, step: 1
4595 16:34:16.600517
4596 16:34:16.600580 RX Delay -179 -> 252, step: 8
4597 16:34:16.600638
4598 16:34:16.603456 Set Vref, RX VrefLevel [Byte0]: 52
4599 16:34:16.606995 [Byte1]: 52
4600 16:34:16.611557
4601 16:34:16.611637 Final RX Vref Byte 0 = 52 to rank0
4602 16:34:16.614814 Final RX Vref Byte 1 = 52 to rank0
4603 16:34:16.617862 Final RX Vref Byte 0 = 52 to rank1
4604 16:34:16.621150 Final RX Vref Byte 1 = 52 to rank1==
4605 16:34:16.624272 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 16:34:16.631668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 16:34:16.631788 ==
4608 16:34:16.631888 DQS Delay:
4609 16:34:16.634212 DQS0 = 0, DQS1 = 0
4610 16:34:16.634298 DQM Delay:
4611 16:34:16.634366 DQM0 = 44, DQM1 = 36
4612 16:34:16.638008 DQ Delay:
4613 16:34:16.641197 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4614 16:34:16.644520 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =36
4615 16:34:16.647924 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =32
4616 16:34:16.651382 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4617 16:34:16.651463
4618 16:34:16.651526
4619 16:34:16.657663 [DQSOSCAuto] RK0, (LSB)MR18= 0x364f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4620 16:34:16.660783 CH1 RK0: MR19=808, MR18=364F
4621 16:34:16.667220 CH1_RK0: MR19=0x808, MR18=0x364F, DQSOSC=394, MR23=63, INC=168, DEC=112
4622 16:34:16.667306
4623 16:34:16.671203 ----->DramcWriteLeveling(PI) begin...
4624 16:34:16.671287 ==
4625 16:34:16.674017 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 16:34:16.677145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 16:34:16.677270 ==
4628 16:34:16.680713 Write leveling (Byte 0): 27 => 27
4629 16:34:16.683885 Write leveling (Byte 1): 28 => 28
4630 16:34:16.687207 DramcWriteLeveling(PI) end<-----
4631 16:34:16.687285
4632 16:34:16.687347 ==
4633 16:34:16.690535 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 16:34:16.693764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 16:34:16.696802 ==
4636 16:34:16.696885 [Gating] SW mode calibration
4637 16:34:16.706811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 16:34:16.709986 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 16:34:16.713780 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 16:34:16.720043 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 16:34:16.723431 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 16:34:16.726461 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 0)
4643 16:34:16.732910 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 16:34:16.736807 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 16:34:16.743105 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 16:34:16.746491 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 16:34:16.749724 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 16:34:16.756506 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 16:34:16.759260 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4650 16:34:16.762439 0 10 12 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
4651 16:34:16.769232 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 16:34:16.772841 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 16:34:16.775948 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 16:34:16.782553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 16:34:16.785471 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 16:34:16.788674 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 16:34:16.795311 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 16:34:16.798619 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4659 16:34:16.801956 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 16:34:16.809017 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 16:34:16.811865 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 16:34:16.815065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 16:34:16.821942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 16:34:16.825470 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 16:34:16.828746 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 16:34:16.835146 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 16:34:16.838205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 16:34:16.841192 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 16:34:16.847989 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 16:34:16.851249 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 16:34:16.854373 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 16:34:16.861225 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 16:34:16.864759 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 16:34:16.868026 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 16:34:16.871481 Total UI for P1: 0, mck2ui 16
4676 16:34:16.875016 best dqsien dly found for B0: ( 0, 13, 10)
4677 16:34:16.877575 Total UI for P1: 0, mck2ui 16
4678 16:34:16.880830 best dqsien dly found for B1: ( 0, 13, 10)
4679 16:34:16.884265 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4680 16:34:16.887611 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4681 16:34:16.887721
4682 16:34:16.894252 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4683 16:34:16.897652 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4684 16:34:16.900915 [Gating] SW calibration Done
4685 16:34:16.900999 ==
4686 16:34:16.904255 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 16:34:16.907092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 16:34:16.907192 ==
4689 16:34:16.907294 RX Vref Scan: 0
4690 16:34:16.907384
4691 16:34:16.910783 RX Vref 0 -> 0, step: 1
4692 16:34:16.910922
4693 16:34:16.913994 RX Delay -230 -> 252, step: 16
4694 16:34:16.917373 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4695 16:34:16.924148 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4696 16:34:16.927354 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4697 16:34:16.930554 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4698 16:34:16.933857 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4699 16:34:16.936657 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4700 16:34:16.943883 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4701 16:34:16.946986 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4702 16:34:16.949972 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4703 16:34:16.953474 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4704 16:34:16.960055 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4705 16:34:16.963457 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4706 16:34:16.966889 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4707 16:34:16.970523 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4708 16:34:16.976997 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4709 16:34:16.980363 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4710 16:34:16.980470 ==
4711 16:34:16.983657 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 16:34:16.987234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 16:34:16.987340 ==
4714 16:34:16.990481 DQS Delay:
4715 16:34:16.990569 DQS0 = 0, DQS1 = 0
4716 16:34:16.990633 DQM Delay:
4717 16:34:16.993182 DQM0 = 46, DQM1 = 43
4718 16:34:16.993326 DQ Delay:
4719 16:34:16.996554 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4720 16:34:16.999756 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4721 16:34:17.003136 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4722 16:34:17.006532 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4723 16:34:17.006616
4724 16:34:17.006679
4725 16:34:17.006737 ==
4726 16:34:17.009878 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 16:34:17.016015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 16:34:17.016126 ==
4729 16:34:17.016224
4730 16:34:17.016313
4731 16:34:17.016400 TX Vref Scan disable
4732 16:34:17.019912 == TX Byte 0 ==
4733 16:34:17.023370 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4734 16:34:17.030372 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4735 16:34:17.030459 == TX Byte 1 ==
4736 16:34:17.033761 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4737 16:34:17.037180 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4738 16:34:17.039823 ==
4739 16:34:17.043061 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 16:34:17.046498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 16:34:17.046607 ==
4742 16:34:17.046701
4743 16:34:17.046760
4744 16:34:17.050091 TX Vref Scan disable
4745 16:34:17.053485 == TX Byte 0 ==
4746 16:34:17.056174 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4747 16:34:17.059644 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4748 16:34:17.063172 == TX Byte 1 ==
4749 16:34:17.066013 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4750 16:34:17.069504 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4751 16:34:17.069587
4752 16:34:17.069650 [DATLAT]
4753 16:34:17.072863 Freq=600, CH1 RK1
4754 16:34:17.072954
4755 16:34:17.075983 DATLAT Default: 0x9
4756 16:34:17.076114 0, 0xFFFF, sum = 0
4757 16:34:17.079368 1, 0xFFFF, sum = 0
4758 16:34:17.079496 2, 0xFFFF, sum = 0
4759 16:34:17.082813 3, 0xFFFF, sum = 0
4760 16:34:17.082902 4, 0xFFFF, sum = 0
4761 16:34:17.086263 5, 0xFFFF, sum = 0
4762 16:34:17.086371 6, 0xFFFF, sum = 0
4763 16:34:17.089635 7, 0xFFFF, sum = 0
4764 16:34:17.089769 8, 0x0, sum = 1
4765 16:34:17.092732 9, 0x0, sum = 2
4766 16:34:17.092814 10, 0x0, sum = 3
4767 16:34:17.096034 11, 0x0, sum = 4
4768 16:34:17.096116 best_step = 9
4769 16:34:17.096180
4770 16:34:17.096239 ==
4771 16:34:17.099213 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 16:34:17.102464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 16:34:17.102553 ==
4774 16:34:17.105887 RX Vref Scan: 0
4775 16:34:17.106043
4776 16:34:17.109208 RX Vref 0 -> 0, step: 1
4777 16:34:17.109350
4778 16:34:17.109444 RX Delay -179 -> 252, step: 8
4779 16:34:17.117433 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4780 16:34:17.120016 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4781 16:34:17.123429 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4782 16:34:17.126619 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4783 16:34:17.133794 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4784 16:34:17.137026 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4785 16:34:17.140301 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4786 16:34:17.143878 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4787 16:34:17.149883 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4788 16:34:17.153815 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4789 16:34:17.156551 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4790 16:34:17.159787 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4791 16:34:17.166335 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4792 16:34:17.169806 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4793 16:34:17.172885 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4794 16:34:17.176052 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4795 16:34:17.176142 ==
4796 16:34:17.179739 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 16:34:17.186146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 16:34:17.186230 ==
4799 16:34:17.186295 DQS Delay:
4800 16:34:17.189235 DQS0 = 0, DQS1 = 0
4801 16:34:17.189355 DQM Delay:
4802 16:34:17.192623 DQM0 = 40, DQM1 = 37
4803 16:34:17.192721 DQ Delay:
4804 16:34:17.195860 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4805 16:34:17.198956 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4806 16:34:17.202661 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4807 16:34:17.206111 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4808 16:34:17.206194
4809 16:34:17.206257
4810 16:34:17.212390 [DQSOSCAuto] RK1, (LSB)MR18= 0x365b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4811 16:34:17.215799 CH1 RK1: MR19=808, MR18=365B
4812 16:34:17.222541 CH1_RK1: MR19=0x808, MR18=0x365B, DQSOSC=392, MR23=63, INC=170, DEC=113
4813 16:34:17.225804 [RxdqsGatingPostProcess] freq 600
4814 16:34:17.232288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4815 16:34:17.235562 Pre-setting of DQS Precalculation
4816 16:34:17.238783 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4817 16:34:17.245124 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4818 16:34:17.251800 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4819 16:34:17.251881
4820 16:34:17.251943
4821 16:34:17.255003 [Calibration Summary] 1200 Mbps
4822 16:34:17.258326 CH 0, Rank 0
4823 16:34:17.258410 SW Impedance : PASS
4824 16:34:17.261844 DUTY Scan : NO K
4825 16:34:17.265021 ZQ Calibration : PASS
4826 16:34:17.265118 Jitter Meter : NO K
4827 16:34:17.268477 CBT Training : PASS
4828 16:34:17.271904 Write leveling : PASS
4829 16:34:17.271991 RX DQS gating : PASS
4830 16:34:17.275135 RX DQ/DQS(RDDQC) : PASS
4831 16:34:17.278191 TX DQ/DQS : PASS
4832 16:34:17.278285 RX DATLAT : PASS
4833 16:34:17.281313 RX DQ/DQS(Engine): PASS
4834 16:34:17.284851 TX OE : NO K
4835 16:34:17.284953 All Pass.
4836 16:34:17.285032
4837 16:34:17.285104 CH 0, Rank 1
4838 16:34:17.288179 SW Impedance : PASS
4839 16:34:17.291339 DUTY Scan : NO K
4840 16:34:17.291462 ZQ Calibration : PASS
4841 16:34:17.295177 Jitter Meter : NO K
4842 16:34:17.295302 CBT Training : PASS
4843 16:34:17.298065 Write leveling : PASS
4844 16:34:17.301297 RX DQS gating : PASS
4845 16:34:17.301434 RX DQ/DQS(RDDQC) : PASS
4846 16:34:17.305126 TX DQ/DQS : PASS
4847 16:34:17.308353 RX DATLAT : PASS
4848 16:34:17.308525 RX DQ/DQS(Engine): PASS
4849 16:34:17.311525 TX OE : NO K
4850 16:34:17.311697 All Pass.
4851 16:34:17.311830
4852 16:34:17.314557 CH 1, Rank 0
4853 16:34:17.314755 SW Impedance : PASS
4854 16:34:17.317894 DUTY Scan : NO K
4855 16:34:17.321136 ZQ Calibration : PASS
4856 16:34:17.321433 Jitter Meter : NO K
4857 16:34:17.324687 CBT Training : PASS
4858 16:34:17.328512 Write leveling : PASS
4859 16:34:17.328891 RX DQS gating : PASS
4860 16:34:17.331245 RX DQ/DQS(RDDQC) : PASS
4861 16:34:17.334511 TX DQ/DQS : PASS
4862 16:34:17.335001 RX DATLAT : PASS
4863 16:34:17.337832 RX DQ/DQS(Engine): PASS
4864 16:34:17.341508 TX OE : NO K
4865 16:34:17.341974 All Pass.
4866 16:34:17.342308
4867 16:34:17.342619 CH 1, Rank 1
4868 16:34:17.344814 SW Impedance : PASS
4869 16:34:17.348036 DUTY Scan : NO K
4870 16:34:17.348505 ZQ Calibration : PASS
4871 16:34:17.351591 Jitter Meter : NO K
4872 16:34:17.354750 CBT Training : PASS
4873 16:34:17.355165 Write leveling : PASS
4874 16:34:17.358048 RX DQS gating : PASS
4875 16:34:17.361469 RX DQ/DQS(RDDQC) : PASS
4876 16:34:17.361885 TX DQ/DQS : PASS
4877 16:34:17.364782 RX DATLAT : PASS
4878 16:34:17.365197 RX DQ/DQS(Engine): PASS
4879 16:34:17.368110 TX OE : NO K
4880 16:34:17.368528 All Pass.
4881 16:34:17.368854
4882 16:34:17.370750 DramC Write-DBI off
4883 16:34:17.374098 PER_BANK_REFRESH: Hybrid Mode
4884 16:34:17.374539 TX_TRACKING: ON
4885 16:34:17.384360 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4886 16:34:17.387642 [FAST_K] Save calibration result to emmc
4887 16:34:17.390873 dramc_set_vcore_voltage set vcore to 662500
4888 16:34:17.394031 Read voltage for 933, 3
4889 16:34:17.394575 Vio18 = 0
4890 16:34:17.397356 Vcore = 662500
4891 16:34:17.397945 Vdram = 0
4892 16:34:17.398488 Vddq = 0
4893 16:34:17.399023 Vmddr = 0
4894 16:34:17.403891 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4895 16:34:17.410471 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4896 16:34:17.410938 MEM_TYPE=3, freq_sel=17
4897 16:34:17.413715 sv_algorithm_assistance_LP4_1600
4898 16:34:17.417092 ============ PULL DRAM RESETB DOWN ============
4899 16:34:17.423545 ========== PULL DRAM RESETB DOWN end =========
4900 16:34:17.427283 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4901 16:34:17.430366 ===================================
4902 16:34:17.433576 LPDDR4 DRAM CONFIGURATION
4903 16:34:17.436898 ===================================
4904 16:34:17.437738 EX_ROW_EN[0] = 0x0
4905 16:34:17.440132 EX_ROW_EN[1] = 0x0
4906 16:34:17.440901 LP4Y_EN = 0x0
4907 16:34:17.443406 WORK_FSP = 0x0
4908 16:34:17.443784 WL = 0x3
4909 16:34:17.446754 RL = 0x3
4910 16:34:17.449651 BL = 0x2
4911 16:34:17.449902 RPST = 0x0
4912 16:34:17.453529 RD_PRE = 0x0
4913 16:34:17.453727 WR_PRE = 0x1
4914 16:34:17.456621 WR_PST = 0x0
4915 16:34:17.456830 DBI_WR = 0x0
4916 16:34:17.459836 DBI_RD = 0x0
4917 16:34:17.459998 OTF = 0x1
4918 16:34:17.463081 ===================================
4919 16:34:17.466422 ===================================
4920 16:34:17.469702 ANA top config
4921 16:34:17.473009 ===================================
4922 16:34:17.473179 DLL_ASYNC_EN = 0
4923 16:34:17.476541 ALL_SLAVE_EN = 1
4924 16:34:17.479855 NEW_RANK_MODE = 1
4925 16:34:17.483137 DLL_IDLE_MODE = 1
4926 16:34:17.486218 LP45_APHY_COMB_EN = 1
4927 16:34:17.486390 TX_ODT_DIS = 1
4928 16:34:17.489456 NEW_8X_MODE = 1
4929 16:34:17.492447 ===================================
4930 16:34:17.495868 ===================================
4931 16:34:17.499459 data_rate = 1866
4932 16:34:17.502770 CKR = 1
4933 16:34:17.506081 DQ_P2S_RATIO = 8
4934 16:34:17.509343 ===================================
4935 16:34:17.512382 CA_P2S_RATIO = 8
4936 16:34:17.512460 DQ_CA_OPEN = 0
4937 16:34:17.515449 DQ_SEMI_OPEN = 0
4938 16:34:17.518571 CA_SEMI_OPEN = 0
4939 16:34:17.521853 CA_FULL_RATE = 0
4940 16:34:17.525834 DQ_CKDIV4_EN = 1
4941 16:34:17.528848 CA_CKDIV4_EN = 1
4942 16:34:17.528930 CA_PREDIV_EN = 0
4943 16:34:17.532080 PH8_DLY = 0
4944 16:34:17.535344 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4945 16:34:17.538956 DQ_AAMCK_DIV = 4
4946 16:34:17.541638 CA_AAMCK_DIV = 4
4947 16:34:17.545578 CA_ADMCK_DIV = 4
4948 16:34:17.545662 DQ_TRACK_CA_EN = 0
4949 16:34:17.548324 CA_PICK = 933
4950 16:34:17.551658 CA_MCKIO = 933
4951 16:34:17.554988 MCKIO_SEMI = 0
4952 16:34:17.558651 PLL_FREQ = 3732
4953 16:34:17.561808 DQ_UI_PI_RATIO = 32
4954 16:34:17.564986 CA_UI_PI_RATIO = 0
4955 16:34:17.568201 ===================================
4956 16:34:17.571540 ===================================
4957 16:34:17.571614 memory_type:LPDDR4
4958 16:34:17.574807 GP_NUM : 10
4959 16:34:17.578105 SRAM_EN : 1
4960 16:34:17.578193 MD32_EN : 0
4961 16:34:17.581490 ===================================
4962 16:34:17.584786 [ANA_INIT] >>>>>>>>>>>>>>
4963 16:34:17.587928 <<<<<< [CONFIGURE PHASE]: ANA_TX
4964 16:34:17.591408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4965 16:34:17.594459 ===================================
4966 16:34:17.597741 data_rate = 1866,PCW = 0X8f00
4967 16:34:17.601040 ===================================
4968 16:34:17.604460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4969 16:34:17.607705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 16:34:17.614319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 16:34:17.617507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4972 16:34:17.621180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4973 16:34:17.627723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4974 16:34:17.627834 [ANA_INIT] flow start
4975 16:34:17.631608 [ANA_INIT] PLL >>>>>>>>
4976 16:34:17.631693 [ANA_INIT] PLL <<<<<<<<
4977 16:34:17.634786 [ANA_INIT] MIDPI >>>>>>>>
4978 16:34:17.637578 [ANA_INIT] MIDPI <<<<<<<<
4979 16:34:17.640921 [ANA_INIT] DLL >>>>>>>>
4980 16:34:17.641005 [ANA_INIT] flow end
4981 16:34:17.644136 ============ LP4 DIFF to SE enter ============
4982 16:34:17.650736 ============ LP4 DIFF to SE exit ============
4983 16:34:17.650826 [ANA_INIT] <<<<<<<<<<<<<
4984 16:34:17.654061 [Flow] Enable top DCM control >>>>>
4985 16:34:17.657464 [Flow] Enable top DCM control <<<<<
4986 16:34:17.660634 Enable DLL master slave shuffle
4987 16:34:17.667328 ==============================================================
4988 16:34:17.670646 Gating Mode config
4989 16:34:17.673692 ==============================================================
4990 16:34:17.677530 Config description:
4991 16:34:17.687001 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4992 16:34:17.693459 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4993 16:34:17.697397 SELPH_MODE 0: By rank 1: By Phase
4994 16:34:17.703588 ==============================================================
4995 16:34:17.706897 GAT_TRACK_EN = 1
4996 16:34:17.710228 RX_GATING_MODE = 2
4997 16:34:17.713604 RX_GATING_TRACK_MODE = 2
4998 16:34:17.716859 SELPH_MODE = 1
4999 16:34:17.716941 PICG_EARLY_EN = 1
5000 16:34:17.720213 VALID_LAT_VALUE = 1
5001 16:34:17.726573 ==============================================================
5002 16:34:17.729663 Enter into Gating configuration >>>>
5003 16:34:17.732787 Exit from Gating configuration <<<<
5004 16:34:17.736483 Enter into DVFS_PRE_config >>>>>
5005 16:34:17.746485 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5006 16:34:17.749655 Exit from DVFS_PRE_config <<<<<
5007 16:34:17.752959 Enter into PICG configuration >>>>
5008 16:34:17.756153 Exit from PICG configuration <<<<
5009 16:34:17.759352 [RX_INPUT] configuration >>>>>
5010 16:34:17.762605 [RX_INPUT] configuration <<<<<
5011 16:34:17.769138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5012 16:34:17.772582 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5013 16:34:17.778935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5014 16:34:17.785886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5015 16:34:17.792399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 16:34:17.799139 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 16:34:17.802535 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5018 16:34:17.805296 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5019 16:34:17.808464 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5020 16:34:17.815206 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5021 16:34:17.818519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5022 16:34:17.821792 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 16:34:17.825123 ===================================
5024 16:34:17.828534 LPDDR4 DRAM CONFIGURATION
5025 16:34:17.832104 ===================================
5026 16:34:17.835347 EX_ROW_EN[0] = 0x0
5027 16:34:17.835427 EX_ROW_EN[1] = 0x0
5028 16:34:17.838404 LP4Y_EN = 0x0
5029 16:34:17.838484 WORK_FSP = 0x0
5030 16:34:17.842071 WL = 0x3
5031 16:34:17.842151 RL = 0x3
5032 16:34:17.845211 BL = 0x2
5033 16:34:17.845362 RPST = 0x0
5034 16:34:17.848308 RD_PRE = 0x0
5035 16:34:17.848388 WR_PRE = 0x1
5036 16:34:17.851557 WR_PST = 0x0
5037 16:34:17.851637 DBI_WR = 0x0
5038 16:34:17.854904 DBI_RD = 0x0
5039 16:34:17.854984 OTF = 0x1
5040 16:34:17.858092 ===================================
5041 16:34:17.865074 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5042 16:34:17.868157 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5043 16:34:17.871611 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 16:34:17.874769 ===================================
5045 16:34:17.878078 LPDDR4 DRAM CONFIGURATION
5046 16:34:17.881232 ===================================
5047 16:34:17.884828 EX_ROW_EN[0] = 0x10
5048 16:34:17.885237 EX_ROW_EN[1] = 0x0
5049 16:34:17.888032 LP4Y_EN = 0x0
5050 16:34:17.888443 WORK_FSP = 0x0
5051 16:34:17.891684 WL = 0x3
5052 16:34:17.892192 RL = 0x3
5053 16:34:17.894981 BL = 0x2
5054 16:34:17.895469 RPST = 0x0
5055 16:34:17.898200 RD_PRE = 0x0
5056 16:34:17.898724 WR_PRE = 0x1
5057 16:34:17.901473 WR_PST = 0x0
5058 16:34:17.901900 DBI_WR = 0x0
5059 16:34:17.904889 DBI_RD = 0x0
5060 16:34:17.905351 OTF = 0x1
5061 16:34:17.908058 ===================================
5062 16:34:17.914449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5063 16:34:17.919848 nWR fixed to 30
5064 16:34:17.923046 [ModeRegInit_LP4] CH0 RK0
5065 16:34:17.923469 [ModeRegInit_LP4] CH0 RK1
5066 16:34:17.926340 [ModeRegInit_LP4] CH1 RK0
5067 16:34:17.929735 [ModeRegInit_LP4] CH1 RK1
5068 16:34:17.930153 match AC timing 9
5069 16:34:17.936155 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5070 16:34:17.939482 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5071 16:34:17.942754 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5072 16:34:17.948901 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5073 16:34:17.952746 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5074 16:34:17.953193 ==
5075 16:34:17.955667 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 16:34:17.959188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 16:34:17.959613 ==
5078 16:34:17.965855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 16:34:17.972319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 16:34:17.975427 [CA 0] Center 38 (7~69) winsize 63
5081 16:34:17.979029 [CA 1] Center 37 (7~68) winsize 62
5082 16:34:17.982404 [CA 2] Center 34 (4~65) winsize 62
5083 16:34:17.985421 [CA 3] Center 34 (4~65) winsize 62
5084 16:34:17.988750 [CA 4] Center 33 (2~64) winsize 63
5085 16:34:17.992086 [CA 5] Center 32 (2~63) winsize 62
5086 16:34:17.992647
5087 16:34:17.995465 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 16:34:17.996106
5089 16:34:17.998512 [CATrainingPosCal] consider 1 rank data
5090 16:34:18.001513 u2DelayCellTimex100 = 270/100 ps
5091 16:34:18.005294 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5092 16:34:18.008530 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5093 16:34:18.011318 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5094 16:34:18.018167 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5095 16:34:18.021487 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5096 16:34:18.024856 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5097 16:34:18.025313
5098 16:34:18.028189 CA PerBit enable=1, Macro0, CA PI delay=32
5099 16:34:18.028609
5100 16:34:18.031546 [CBTSetCACLKResult] CA Dly = 32
5101 16:34:18.031964 CS Dly: 5 (0~36)
5102 16:34:18.032290 ==
5103 16:34:18.034848 Dram Type= 6, Freq= 0, CH_0, rank 1
5104 16:34:18.041504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 16:34:18.042321 ==
5106 16:34:18.044873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 16:34:18.051138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5108 16:34:18.055077 [CA 0] Center 38 (8~69) winsize 62
5109 16:34:18.058339 [CA 1] Center 37 (7~68) winsize 62
5110 16:34:18.061501 [CA 2] Center 34 (4~65) winsize 62
5111 16:34:18.064528 [CA 3] Center 34 (4~65) winsize 62
5112 16:34:18.067736 [CA 4] Center 33 (3~64) winsize 62
5113 16:34:18.071733 [CA 5] Center 33 (3~63) winsize 61
5114 16:34:18.072310
5115 16:34:18.074311 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5116 16:34:18.074732
5117 16:34:18.078041 [CATrainingPosCal] consider 2 rank data
5118 16:34:18.081223 u2DelayCellTimex100 = 270/100 ps
5119 16:34:18.084173 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5120 16:34:18.091177 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 16:34:18.094406 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5122 16:34:18.097952 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 16:34:18.100643 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5124 16:34:18.103824 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5125 16:34:18.104423
5126 16:34:18.107845 CA PerBit enable=1, Macro0, CA PI delay=33
5127 16:34:18.108401
5128 16:34:18.110787 [CBTSetCACLKResult] CA Dly = 33
5129 16:34:18.114040 CS Dly: 6 (0~39)
5130 16:34:18.114454
5131 16:34:18.117219 ----->DramcWriteLeveling(PI) begin...
5132 16:34:18.117688 ==
5133 16:34:18.120490 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 16:34:18.123757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 16:34:18.124422 ==
5136 16:34:18.127055 Write leveling (Byte 0): 31 => 31
5137 16:34:18.130496 Write leveling (Byte 1): 29 => 29
5138 16:34:18.133766 DramcWriteLeveling(PI) end<-----
5139 16:34:18.134297
5140 16:34:18.134770 ==
5141 16:34:18.136890 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 16:34:18.140317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 16:34:18.140812 ==
5144 16:34:18.143597 [Gating] SW mode calibration
5145 16:34:18.150181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5146 16:34:18.157335 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5147 16:34:18.160423 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5148 16:34:18.163892 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 16:34:18.170301 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 16:34:18.173585 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 16:34:18.176617 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 16:34:18.183265 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 16:34:18.186702 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 16:34:18.189833 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5155 16:34:18.196609 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5156 16:34:18.199849 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 16:34:18.203903 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 16:34:18.209612 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 16:34:18.212983 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 16:34:18.216159 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 16:34:18.222834 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 16:34:18.226232 0 15 28 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5163 16:34:18.229624 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5164 16:34:18.236174 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 16:34:18.239508 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 16:34:18.242835 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 16:34:18.249374 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 16:34:18.252682 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 16:34:18.255872 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5170 16:34:18.262531 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5171 16:34:18.265515 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 16:34:18.269232 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 16:34:18.275291 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 16:34:18.279051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 16:34:18.282310 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 16:34:18.288639 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 16:34:18.291734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 16:34:18.294983 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 16:34:18.301939 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 16:34:18.305250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 16:34:18.308239 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 16:34:18.314721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 16:34:18.318086 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 16:34:18.321579 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 16:34:18.328319 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5186 16:34:18.331325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 16:34:18.335036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5188 16:34:18.338092 Total UI for P1: 0, mck2ui 16
5189 16:34:18.341594 best dqsien dly found for B0: ( 1, 2, 26)
5190 16:34:18.348144 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 16:34:18.351404 Total UI for P1: 0, mck2ui 16
5192 16:34:18.354528 best dqsien dly found for B1: ( 1, 3, 0)
5193 16:34:18.357938 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5194 16:34:18.361105 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5195 16:34:18.361618
5196 16:34:18.364738 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5197 16:34:18.367988 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5198 16:34:18.371251 [Gating] SW calibration Done
5199 16:34:18.371831 ==
5200 16:34:18.374283 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 16:34:18.377380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 16:34:18.377833 ==
5203 16:34:18.380598 RX Vref Scan: 0
5204 16:34:18.381074
5205 16:34:18.384219 RX Vref 0 -> 0, step: 1
5206 16:34:18.384676
5207 16:34:18.385162 RX Delay -80 -> 252, step: 8
5208 16:34:18.390628 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5209 16:34:18.394076 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5210 16:34:18.397029 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5211 16:34:18.409953 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5212 16:34:18.410256 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5213 16:34:18.410531 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5214 16:34:18.413801 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5215 16:34:18.416884 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5216 16:34:18.420434 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5217 16:34:18.423780 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5218 16:34:18.426908 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5219 16:34:18.433409 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5220 16:34:18.436727 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5221 16:34:18.439749 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5222 16:34:18.443430 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5223 16:34:18.446774 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5224 16:34:18.447239 ==
5225 16:34:18.449743 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 16:34:18.456303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 16:34:18.456616 ==
5228 16:34:18.456866 DQS Delay:
5229 16:34:18.459892 DQS0 = 0, DQS1 = 0
5230 16:34:18.460190 DQM Delay:
5231 16:34:18.462991 DQM0 = 101, DQM1 = 87
5232 16:34:18.463288 DQ Delay:
5233 16:34:18.466223 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5234 16:34:18.469683 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5235 16:34:18.472701 DQ8 =83, DQ9 =71, DQ10 =87, DQ11 =79
5236 16:34:18.475974 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5237 16:34:18.476327
5238 16:34:18.476586
5239 16:34:18.476804 ==
5240 16:34:18.479205 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 16:34:18.483045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 16:34:18.483359 ==
5243 16:34:18.486094
5244 16:34:18.486401
5245 16:34:18.486713 TX Vref Scan disable
5246 16:34:18.489329 == TX Byte 0 ==
5247 16:34:18.492566 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5248 16:34:18.495954 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5249 16:34:18.499110 == TX Byte 1 ==
5250 16:34:18.502924 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5251 16:34:18.506168 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5252 16:34:18.506588 ==
5253 16:34:18.509424 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 16:34:18.515915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 16:34:18.516349 ==
5256 16:34:18.516723
5257 16:34:18.517041
5258 16:34:18.519006 TX Vref Scan disable
5259 16:34:18.519363 == TX Byte 0 ==
5260 16:34:18.525997 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5261 16:34:18.528656 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5262 16:34:18.528886 == TX Byte 1 ==
5263 16:34:18.534971 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5264 16:34:18.538308 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5265 16:34:18.538444
5266 16:34:18.538544 [DATLAT]
5267 16:34:18.541446 Freq=933, CH0 RK0
5268 16:34:18.541574
5269 16:34:18.541675 DATLAT Default: 0xd
5270 16:34:18.544741 0, 0xFFFF, sum = 0
5271 16:34:18.544855 1, 0xFFFF, sum = 0
5272 16:34:18.548006 2, 0xFFFF, sum = 0
5273 16:34:18.548112 3, 0xFFFF, sum = 0
5274 16:34:18.551311 4, 0xFFFF, sum = 0
5275 16:34:18.554913 5, 0xFFFF, sum = 0
5276 16:34:18.555005 6, 0xFFFF, sum = 0
5277 16:34:18.557932 7, 0xFFFF, sum = 0
5278 16:34:18.558015 8, 0xFFFF, sum = 0
5279 16:34:18.561374 9, 0xFFFF, sum = 0
5280 16:34:18.561491 10, 0x0, sum = 1
5281 16:34:18.564546 11, 0x0, sum = 2
5282 16:34:18.564651 12, 0x0, sum = 3
5283 16:34:18.564745 13, 0x0, sum = 4
5284 16:34:18.567737 best_step = 11
5285 16:34:18.567850
5286 16:34:18.567920 ==
5287 16:34:18.571154 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 16:34:18.574317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 16:34:18.574394 ==
5290 16:34:18.577656 RX Vref Scan: 1
5291 16:34:18.577762
5292 16:34:18.580910 RX Vref 0 -> 0, step: 1
5293 16:34:18.581049
5294 16:34:18.581144 RX Delay -69 -> 252, step: 4
5295 16:34:18.581237
5296 16:34:18.584239 Set Vref, RX VrefLevel [Byte0]: 58
5297 16:34:18.587532 [Byte1]: 49
5298 16:34:18.592262
5299 16:34:18.592363 Final RX Vref Byte 0 = 58 to rank0
5300 16:34:18.595998 Final RX Vref Byte 1 = 49 to rank0
5301 16:34:18.599077 Final RX Vref Byte 0 = 58 to rank1
5302 16:34:18.602457 Final RX Vref Byte 1 = 49 to rank1==
5303 16:34:18.605546 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 16:34:18.612041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 16:34:18.612161 ==
5306 16:34:18.612262 DQS Delay:
5307 16:34:18.615363 DQS0 = 0, DQS1 = 0
5308 16:34:18.615473 DQM Delay:
5309 16:34:18.615579 DQM0 = 102, DQM1 = 90
5310 16:34:18.619353 DQ Delay:
5311 16:34:18.622390 DQ0 =102, DQ1 =102, DQ2 =98, DQ3 =98
5312 16:34:18.625636 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5313 16:34:18.629078 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =86
5314 16:34:18.632473 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5315 16:34:18.632556
5316 16:34:18.632620
5317 16:34:18.638777 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5318 16:34:18.641859 CH0 RK0: MR19=505, MR18=1F19
5319 16:34:18.648470 CH0_RK0: MR19=0x505, MR18=0x1F19, DQSOSC=412, MR23=63, INC=63, DEC=42
5320 16:34:18.648553
5321 16:34:18.652222 ----->DramcWriteLeveling(PI) begin...
5322 16:34:18.652334 ==
5323 16:34:18.655458 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 16:34:18.658667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 16:34:18.658749 ==
5326 16:34:18.661891 Write leveling (Byte 0): 31 => 31
5327 16:34:18.665572 Write leveling (Byte 1): 28 => 28
5328 16:34:18.668588 DramcWriteLeveling(PI) end<-----
5329 16:34:18.668669
5330 16:34:18.668731 ==
5331 16:34:18.671770 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 16:34:18.678132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 16:34:18.678213 ==
5334 16:34:18.678276 [Gating] SW mode calibration
5335 16:34:18.687984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5336 16:34:18.691281 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5337 16:34:18.697847 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5338 16:34:18.701523 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 16:34:18.704719 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 16:34:18.711139 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 16:34:18.714413 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 16:34:18.717578 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 16:34:18.724186 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5344 16:34:18.727399 0 14 28 | B1->B0 | 3434 2929 | 0 0 | (0 1) (1 1)
5345 16:34:18.730743 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5346 16:34:18.737099 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 16:34:18.740601 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 16:34:18.744423 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 16:34:18.751085 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 16:34:18.754241 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 16:34:18.757126 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 16:34:18.763870 0 15 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
5353 16:34:18.767068 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5354 16:34:18.770279 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 16:34:18.776887 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 16:34:18.779935 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 16:34:18.783186 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 16:34:18.789816 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 16:34:18.793617 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 16:34:18.796859 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5361 16:34:18.803408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5362 16:34:18.806321 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 16:34:18.809425 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 16:34:18.816035 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 16:34:18.819896 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 16:34:18.822589 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 16:34:18.829582 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 16:34:18.832784 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 16:34:18.835985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 16:34:18.842571 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 16:34:18.845716 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 16:34:18.849180 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 16:34:18.855772 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 16:34:18.858979 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 16:34:18.862370 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5376 16:34:18.868625 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5377 16:34:18.872296 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:34:18.875024 Total UI for P1: 0, mck2ui 16
5379 16:34:18.878598 best dqsien dly found for B0: ( 1, 2, 26)
5380 16:34:18.882057 Total UI for P1: 0, mck2ui 16
5381 16:34:18.885147 best dqsien dly found for B1: ( 1, 2, 28)
5382 16:34:18.888758 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5383 16:34:18.892086 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5384 16:34:18.892169
5385 16:34:18.895495 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5386 16:34:18.902028 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5387 16:34:18.902111 [Gating] SW calibration Done
5388 16:34:18.902174 ==
5389 16:34:18.905185 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 16:34:18.911577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 16:34:18.911661 ==
5392 16:34:18.911724 RX Vref Scan: 0
5393 16:34:18.911782
5394 16:34:18.914784 RX Vref 0 -> 0, step: 1
5395 16:34:18.914868
5396 16:34:18.917993 RX Delay -80 -> 252, step: 8
5397 16:34:18.921147 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5398 16:34:18.924340 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5399 16:34:18.927602 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5400 16:34:18.930984 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5401 16:34:18.937414 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5402 16:34:18.941571 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5403 16:34:18.944171 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5404 16:34:18.947460 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5405 16:34:18.950748 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5406 16:34:18.957593 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5407 16:34:18.960541 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5408 16:34:18.964416 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5409 16:34:18.967707 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5410 16:34:18.971043 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5411 16:34:18.977581 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5412 16:34:18.980810 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5413 16:34:18.980888 ==
5414 16:34:18.984055 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 16:34:18.987029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 16:34:18.987132 ==
5417 16:34:18.987230 DQS Delay:
5418 16:34:18.990056 DQS0 = 0, DQS1 = 0
5419 16:34:18.990131 DQM Delay:
5420 16:34:18.993489 DQM0 = 99, DQM1 = 89
5421 16:34:18.993571 DQ Delay:
5422 16:34:18.996685 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5423 16:34:19.000457 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5424 16:34:19.003389 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5425 16:34:19.006651 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5426 16:34:19.006737
5427 16:34:19.006800
5428 16:34:19.006869 ==
5429 16:34:19.010004 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 16:34:19.016314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 16:34:19.016418 ==
5432 16:34:19.016508
5433 16:34:19.016593
5434 16:34:19.016677 TX Vref Scan disable
5435 16:34:19.020145 == TX Byte 0 ==
5436 16:34:19.023308 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5437 16:34:19.030362 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5438 16:34:19.030466 == TX Byte 1 ==
5439 16:34:19.033702 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 16:34:19.040345 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 16:34:19.040445 ==
5442 16:34:19.043231 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 16:34:19.046635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 16:34:19.046713 ==
5445 16:34:19.046775
5446 16:34:19.046833
5447 16:34:19.050412 TX Vref Scan disable
5448 16:34:19.050494 == TX Byte 0 ==
5449 16:34:19.056208 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5450 16:34:19.059612 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5451 16:34:19.062958 == TX Byte 1 ==
5452 16:34:19.066753 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5453 16:34:19.069506 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5454 16:34:19.069588
5455 16:34:19.069651 [DATLAT]
5456 16:34:19.073192 Freq=933, CH0 RK1
5457 16:34:19.073313
5458 16:34:19.073377 DATLAT Default: 0xb
5459 16:34:19.076660 0, 0xFFFF, sum = 0
5460 16:34:19.079331 1, 0xFFFF, sum = 0
5461 16:34:19.079414 2, 0xFFFF, sum = 0
5462 16:34:19.083088 3, 0xFFFF, sum = 0
5463 16:34:19.083170 4, 0xFFFF, sum = 0
5464 16:34:19.086320 5, 0xFFFF, sum = 0
5465 16:34:19.086402 6, 0xFFFF, sum = 0
5466 16:34:19.089551 7, 0xFFFF, sum = 0
5467 16:34:19.089633 8, 0xFFFF, sum = 0
5468 16:34:19.092921 9, 0xFFFF, sum = 0
5469 16:34:19.093003 10, 0x0, sum = 1
5470 16:34:19.096139 11, 0x0, sum = 2
5471 16:34:19.096222 12, 0x0, sum = 3
5472 16:34:19.099576 13, 0x0, sum = 4
5473 16:34:19.099659 best_step = 11
5474 16:34:19.099722
5475 16:34:19.099780 ==
5476 16:34:19.102687 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 16:34:19.105662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 16:34:19.109058 ==
5479 16:34:19.109164 RX Vref Scan: 0
5480 16:34:19.109254
5481 16:34:19.112731 RX Vref 0 -> 0, step: 1
5482 16:34:19.112801
5483 16:34:19.115254 RX Delay -61 -> 252, step: 4
5484 16:34:19.118877 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5485 16:34:19.122314 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5486 16:34:19.128542 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5487 16:34:19.132164 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5488 16:34:19.135283 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5489 16:34:19.138556 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5490 16:34:19.141839 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5491 16:34:19.148235 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5492 16:34:19.151989 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5493 16:34:19.154754 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5494 16:34:19.158104 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5495 16:34:19.161412 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5496 16:34:19.165393 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5497 16:34:19.171845 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5498 16:34:19.174537 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5499 16:34:19.177758 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5500 16:34:19.177839 ==
5501 16:34:19.181491 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 16:34:19.184769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 16:34:19.187953 ==
5504 16:34:19.188032 DQS Delay:
5505 16:34:19.188095 DQS0 = 0, DQS1 = 0
5506 16:34:19.191362 DQM Delay:
5507 16:34:19.191441 DQM0 = 101, DQM1 = 90
5508 16:34:19.194531 DQ Delay:
5509 16:34:19.197744 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5510 16:34:19.200975 DQ4 =104, DQ5 =92, DQ6 =108, DQ7 =108
5511 16:34:19.204306 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5512 16:34:19.207528 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5513 16:34:19.207610
5514 16:34:19.207674
5515 16:34:19.214119 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5516 16:34:19.217588 CH0 RK1: MR19=505, MR18=1A17
5517 16:34:19.223902 CH0_RK1: MR19=0x505, MR18=0x1A17, DQSOSC=413, MR23=63, INC=63, DEC=42
5518 16:34:19.227094 [RxdqsGatingPostProcess] freq 933
5519 16:34:19.234255 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 16:34:19.234359 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 16:34:19.236930 best DQS1 dly(2T, 0.5T) = (0, 11)
5522 16:34:19.240251 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 16:34:19.243476 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5524 16:34:19.246734 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 16:34:19.250326 best DQS1 dly(2T, 0.5T) = (0, 10)
5526 16:34:19.253961 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 16:34:19.256620 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5528 16:34:19.259938 Pre-setting of DQS Precalculation
5529 16:34:19.266545 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 16:34:19.266631 ==
5531 16:34:19.270049 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 16:34:19.273336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 16:34:19.273414 ==
5534 16:34:19.279741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 16:34:19.286471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 16:34:19.289607 [CA 0] Center 36 (6~67) winsize 62
5537 16:34:19.292841 [CA 1] Center 36 (6~67) winsize 62
5538 16:34:19.296044 [CA 2] Center 35 (4~66) winsize 63
5539 16:34:19.300066 [CA 3] Center 34 (4~65) winsize 62
5540 16:34:19.302723 [CA 4] Center 34 (4~65) winsize 62
5541 16:34:19.302805 [CA 5] Center 33 (3~64) winsize 62
5542 16:34:19.306455
5543 16:34:19.309801 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 16:34:19.309882
5545 16:34:19.312925 [CATrainingPosCal] consider 1 rank data
5546 16:34:19.316150 u2DelayCellTimex100 = 270/100 ps
5547 16:34:19.319469 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 16:34:19.322756 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 16:34:19.326167 CA2 delay=35 (4~66),Diff = 2 PI (12 cell)
5550 16:34:19.328824 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 16:34:19.332125 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5552 16:34:19.335285 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 16:34:19.335367
5554 16:34:19.342436 CA PerBit enable=1, Macro0, CA PI delay=33
5555 16:34:19.342519
5556 16:34:19.345599 [CBTSetCACLKResult] CA Dly = 33
5557 16:34:19.345681 CS Dly: 5 (0~36)
5558 16:34:19.345764 ==
5559 16:34:19.348862 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 16:34:19.352135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 16:34:19.352242 ==
5562 16:34:19.358445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 16:34:19.365069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5564 16:34:19.368771 [CA 0] Center 36 (6~67) winsize 62
5565 16:34:19.371722 [CA 1] Center 36 (6~67) winsize 62
5566 16:34:19.375113 [CA 2] Center 34 (4~65) winsize 62
5567 16:34:19.378771 [CA 3] Center 33 (3~64) winsize 62
5568 16:34:19.381868 [CA 4] Center 33 (3~64) winsize 62
5569 16:34:19.385168 [CA 5] Center 33 (3~64) winsize 62
5570 16:34:19.385249
5571 16:34:19.387979 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5572 16:34:19.388061
5573 16:34:19.391432 [CATrainingPosCal] consider 2 rank data
5574 16:34:19.394895 u2DelayCellTimex100 = 270/100 ps
5575 16:34:19.397861 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5576 16:34:19.401443 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5577 16:34:19.404569 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5578 16:34:19.411068 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5579 16:34:19.414308 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5580 16:34:19.417692 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5581 16:34:19.417773
5582 16:34:19.420903 CA PerBit enable=1, Macro0, CA PI delay=33
5583 16:34:19.420984
5584 16:34:19.424152 [CBTSetCACLKResult] CA Dly = 33
5585 16:34:19.424234 CS Dly: 6 (0~38)
5586 16:34:19.424297
5587 16:34:19.427817 ----->DramcWriteLeveling(PI) begin...
5588 16:34:19.427900 ==
5589 16:34:19.431264 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 16:34:19.437682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 16:34:19.437773 ==
5592 16:34:19.440849 Write leveling (Byte 0): 26 => 26
5593 16:34:19.444138 Write leveling (Byte 1): 24 => 24
5594 16:34:19.447331 DramcWriteLeveling(PI) end<-----
5595 16:34:19.447413
5596 16:34:19.447476 ==
5597 16:34:19.450571 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 16:34:19.453847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 16:34:19.453934 ==
5600 16:34:19.457201 [Gating] SW mode calibration
5601 16:34:19.463620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 16:34:19.470643 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 16:34:19.473914 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 16:34:19.477222 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 16:34:19.483753 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 16:34:19.486987 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 16:34:19.490112 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 16:34:19.497028 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 16:34:19.499999 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (1 0) (1 0)
5610 16:34:19.503435 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (1 0)
5611 16:34:19.509759 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 16:34:19.513265 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 16:34:19.516770 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 16:34:19.523207 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 16:34:19.526317 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 16:34:19.530093 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 16:34:19.536560 0 15 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5618 16:34:19.539770 0 15 28 | B1->B0 | 3636 4141 | 0 1 | (0 0) (0 0)
5619 16:34:19.542918 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 16:34:19.549583 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 16:34:19.552882 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 16:34:19.556116 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 16:34:19.562749 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 16:34:19.566095 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 16:34:19.569274 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5626 16:34:19.575453 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5627 16:34:19.578889 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 16:34:19.582190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 16:34:19.588742 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 16:34:19.592052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 16:34:19.595281 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 16:34:19.601921 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 16:34:19.605352 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 16:34:19.608634 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 16:34:19.615626 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 16:34:19.618917 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 16:34:19.622017 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 16:34:19.628880 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 16:34:19.631950 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 16:34:19.635522 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 16:34:19.642307 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5642 16:34:19.645051 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5643 16:34:19.648826 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 16:34:19.651779 Total UI for P1: 0, mck2ui 16
5645 16:34:19.654977 best dqsien dly found for B0: ( 1, 2, 26)
5646 16:34:19.658554 Total UI for P1: 0, mck2ui 16
5647 16:34:19.661611 best dqsien dly found for B1: ( 1, 2, 26)
5648 16:34:19.664819 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5649 16:34:19.668213 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5650 16:34:19.668512
5651 16:34:19.674752 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5652 16:34:19.677974 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5653 16:34:19.678272 [Gating] SW calibration Done
5654 16:34:19.681493 ==
5655 16:34:19.684657 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 16:34:19.687810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 16:34:19.688120 ==
5658 16:34:19.688432 RX Vref Scan: 0
5659 16:34:19.688724
5660 16:34:19.691175 RX Vref 0 -> 0, step: 1
5661 16:34:19.691482
5662 16:34:19.694635 RX Delay -80 -> 252, step: 8
5663 16:34:19.697798 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5664 16:34:19.700972 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5665 16:34:19.707694 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5666 16:34:19.710722 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5667 16:34:19.713924 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5668 16:34:19.717218 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5669 16:34:19.720487 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5670 16:34:19.723853 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5671 16:34:19.730592 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5672 16:34:19.733892 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5673 16:34:19.737026 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5674 16:34:19.740506 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5675 16:34:19.743783 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5676 16:34:19.749836 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5677 16:34:19.753178 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5678 16:34:19.756432 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5679 16:34:19.756512 ==
5680 16:34:19.760071 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 16:34:19.762880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 16:34:19.762962 ==
5683 16:34:19.766433 DQS Delay:
5684 16:34:19.766514 DQS0 = 0, DQS1 = 0
5685 16:34:19.766577 DQM Delay:
5686 16:34:19.769741 DQM0 = 98, DQM1 = 94
5687 16:34:19.769822 DQ Delay:
5688 16:34:19.773190 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5689 16:34:19.776431 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5690 16:34:19.779841 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5691 16:34:19.783085 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5692 16:34:19.783170
5693 16:34:19.786217
5694 16:34:19.786298 ==
5695 16:34:19.789714 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 16:34:19.793020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 16:34:19.793104 ==
5698 16:34:19.793167
5699 16:34:19.793227
5700 16:34:19.796382 TX Vref Scan disable
5701 16:34:19.796462 == TX Byte 0 ==
5702 16:34:19.802778 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5703 16:34:19.806098 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5704 16:34:19.806179 == TX Byte 1 ==
5705 16:34:19.812648 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5706 16:34:19.815783 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5707 16:34:19.815864 ==
5708 16:34:19.819131 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 16:34:19.822874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 16:34:19.822955 ==
5711 16:34:19.823019
5712 16:34:19.823078
5713 16:34:19.826152 TX Vref Scan disable
5714 16:34:19.829607 == TX Byte 0 ==
5715 16:34:19.832730 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5716 16:34:19.835380 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5717 16:34:19.839223 == TX Byte 1 ==
5718 16:34:19.842168 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5719 16:34:19.845612 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5720 16:34:19.845693
5721 16:34:19.848754 [DATLAT]
5722 16:34:19.848833 Freq=933, CH1 RK0
5723 16:34:19.848897
5724 16:34:19.852091 DATLAT Default: 0xd
5725 16:34:19.852171 0, 0xFFFF, sum = 0
5726 16:34:19.855350 1, 0xFFFF, sum = 0
5727 16:34:19.855432 2, 0xFFFF, sum = 0
5728 16:34:19.858587 3, 0xFFFF, sum = 0
5729 16:34:19.858669 4, 0xFFFF, sum = 0
5730 16:34:19.861877 5, 0xFFFF, sum = 0
5731 16:34:19.861958 6, 0xFFFF, sum = 0
5732 16:34:19.865297 7, 0xFFFF, sum = 0
5733 16:34:19.868441 8, 0xFFFF, sum = 0
5734 16:34:19.868523 9, 0xFFFF, sum = 0
5735 16:34:19.871702 10, 0x0, sum = 1
5736 16:34:19.871784 11, 0x0, sum = 2
5737 16:34:19.871847 12, 0x0, sum = 3
5738 16:34:19.874949 13, 0x0, sum = 4
5739 16:34:19.875031 best_step = 11
5740 16:34:19.875111
5741 16:34:19.878598 ==
5742 16:34:19.878679 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 16:34:19.885458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 16:34:19.885549 ==
5745 16:34:19.885633 RX Vref Scan: 1
5746 16:34:19.885712
5747 16:34:19.888377 RX Vref 0 -> 0, step: 1
5748 16:34:19.888477
5749 16:34:19.892036 RX Delay -53 -> 252, step: 4
5750 16:34:19.892120
5751 16:34:19.894918 Set Vref, RX VrefLevel [Byte0]: 52
5752 16:34:19.898269 [Byte1]: 52
5753 16:34:19.898353
5754 16:34:19.901409 Final RX Vref Byte 0 = 52 to rank0
5755 16:34:19.904747 Final RX Vref Byte 1 = 52 to rank0
5756 16:34:19.908073 Final RX Vref Byte 0 = 52 to rank1
5757 16:34:19.911534 Final RX Vref Byte 1 = 52 to rank1==
5758 16:34:19.914734 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 16:34:19.917878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 16:34:19.921064 ==
5761 16:34:19.921149 DQS Delay:
5762 16:34:19.921248 DQS0 = 0, DQS1 = 0
5763 16:34:19.924861 DQM Delay:
5764 16:34:19.924945 DQM0 = 97, DQM1 = 95
5765 16:34:19.928183 DQ Delay:
5766 16:34:19.931352 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5767 16:34:19.934435 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5768 16:34:19.937647 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =86
5769 16:34:19.941032 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =104
5770 16:34:19.941117
5771 16:34:19.941217
5772 16:34:19.947803 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5773 16:34:19.951034 CH1 RK0: MR19=505, MR18=B1B
5774 16:34:19.957691 CH1_RK0: MR19=0x505, MR18=0xB1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5775 16:34:19.957776
5776 16:34:19.961003 ----->DramcWriteLeveling(PI) begin...
5777 16:34:19.961088 ==
5778 16:34:19.964377 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 16:34:19.967523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 16:34:19.967607 ==
5781 16:34:19.970899 Write leveling (Byte 0): 25 => 25
5782 16:34:19.974163 Write leveling (Byte 1): 28 => 28
5783 16:34:19.977498 DramcWriteLeveling(PI) end<-----
5784 16:34:19.977582
5785 16:34:19.977665 ==
5786 16:34:19.980591 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 16:34:19.984043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 16:34:19.987186 ==
5789 16:34:19.987271 [Gating] SW mode calibration
5790 16:34:19.994024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5791 16:34:20.000569 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5792 16:34:20.004246 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 16:34:20.010683 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 16:34:20.013595 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 16:34:20.017248 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 16:34:20.023706 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 16:34:20.027267 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 16:34:20.030414 0 14 24 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
5799 16:34:20.036777 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5800 16:34:20.039892 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5801 16:34:20.043261 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 16:34:20.049479 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 16:34:20.053251 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 16:34:20.056190 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 16:34:20.062786 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 16:34:20.066268 0 15 24 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
5807 16:34:20.069500 0 15 28 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5808 16:34:20.076065 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 16:34:20.079510 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 16:34:20.082567 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 16:34:20.089227 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 16:34:20.092521 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 16:34:20.095463 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 16:34:20.102495 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5815 16:34:20.105176 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 16:34:20.109193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 16:34:20.115717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 16:34:20.119062 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 16:34:20.122244 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 16:34:20.128723 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 16:34:20.132194 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 16:34:20.138241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 16:34:20.141643 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 16:34:20.145335 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 16:34:20.152196 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 16:34:20.155321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 16:34:20.158563 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 16:34:20.164689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 16:34:20.168037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 16:34:20.171205 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5831 16:34:20.177959 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 16:34:20.178381 Total UI for P1: 0, mck2ui 16
5833 16:34:20.184373 best dqsien dly found for B0: ( 1, 2, 24)
5834 16:34:20.184798 Total UI for P1: 0, mck2ui 16
5835 16:34:20.187685 best dqsien dly found for B1: ( 1, 2, 24)
5836 16:34:20.194695 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5837 16:34:20.198052 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5838 16:34:20.198467
5839 16:34:20.201151 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5840 16:34:20.204237 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5841 16:34:20.208054 [Gating] SW calibration Done
5842 16:34:20.208473 ==
5843 16:34:20.211203 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 16:34:20.214508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 16:34:20.214928 ==
5846 16:34:20.217604 RX Vref Scan: 0
5847 16:34:20.218052
5848 16:34:20.218486 RX Vref 0 -> 0, step: 1
5849 16:34:20.218895
5850 16:34:20.220837 RX Delay -80 -> 252, step: 8
5851 16:34:20.224046 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5852 16:34:20.230971 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5853 16:34:20.234246 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5854 16:34:20.237411 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5855 16:34:20.240488 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5856 16:34:20.244278 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5857 16:34:20.247426 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5858 16:34:20.253726 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5859 16:34:20.257188 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5860 16:34:20.260518 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5861 16:34:20.263515 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5862 16:34:20.267268 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5863 16:34:20.273060 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5864 16:34:20.276188 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5865 16:34:20.279624 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5866 16:34:20.283375 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5867 16:34:20.283470 ==
5868 16:34:20.286620 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 16:34:20.289412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 16:34:20.292936 ==
5871 16:34:20.293023 DQS Delay:
5872 16:34:20.293090 DQS0 = 0, DQS1 = 0
5873 16:34:20.296002 DQM Delay:
5874 16:34:20.296088 DQM0 = 97, DQM1 = 94
5875 16:34:20.299346 DQ Delay:
5876 16:34:20.302675 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5877 16:34:20.305899 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5878 16:34:20.309108 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5879 16:34:20.312778 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5880 16:34:20.312874
5881 16:34:20.312959
5882 16:34:20.313033 ==
5883 16:34:20.316139 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 16:34:20.319521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 16:34:20.319634 ==
5886 16:34:20.319737
5887 16:34:20.319833
5888 16:34:20.322695 TX Vref Scan disable
5889 16:34:20.322807 == TX Byte 0 ==
5890 16:34:20.329145 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5891 16:34:20.332659 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5892 16:34:20.335315 == TX Byte 1 ==
5893 16:34:20.338628 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5894 16:34:20.341888 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5895 16:34:20.341970 ==
5896 16:34:20.345736 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 16:34:20.348931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 16:34:20.352231 ==
5899 16:34:20.352313
5900 16:34:20.352376
5901 16:34:20.352435 TX Vref Scan disable
5902 16:34:20.355526 == TX Byte 0 ==
5903 16:34:20.358835 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5904 16:34:20.365893 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5905 16:34:20.365977 == TX Byte 1 ==
5906 16:34:20.368665 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5907 16:34:20.375225 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5908 16:34:20.375308
5909 16:34:20.375372 [DATLAT]
5910 16:34:20.375432 Freq=933, CH1 RK1
5911 16:34:20.375490
5912 16:34:20.378737 DATLAT Default: 0xb
5913 16:34:20.378817 0, 0xFFFF, sum = 0
5914 16:34:20.382198 1, 0xFFFF, sum = 0
5915 16:34:20.385997 2, 0xFFFF, sum = 0
5916 16:34:20.386080 3, 0xFFFF, sum = 0
5917 16:34:20.388828 4, 0xFFFF, sum = 0
5918 16:34:20.388911 5, 0xFFFF, sum = 0
5919 16:34:20.391626 6, 0xFFFF, sum = 0
5920 16:34:20.391708 7, 0xFFFF, sum = 0
5921 16:34:20.395031 8, 0xFFFF, sum = 0
5922 16:34:20.395114 9, 0xFFFF, sum = 0
5923 16:34:20.398744 10, 0x0, sum = 1
5924 16:34:20.398826 11, 0x0, sum = 2
5925 16:34:20.401451 12, 0x0, sum = 3
5926 16:34:20.401533 13, 0x0, sum = 4
5927 16:34:20.404605 best_step = 11
5928 16:34:20.404686
5929 16:34:20.404749 ==
5930 16:34:20.407988 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 16:34:20.411220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 16:34:20.411326 ==
5933 16:34:20.411418 RX Vref Scan: 0
5934 16:34:20.411480
5935 16:34:20.414792 RX Vref 0 -> 0, step: 1
5936 16:34:20.414875
5937 16:34:20.418395 RX Delay -53 -> 252, step: 4
5938 16:34:20.424839 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5939 16:34:20.428230 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5940 16:34:20.431556 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5941 16:34:20.434333 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5942 16:34:20.438322 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5943 16:34:20.444368 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5944 16:34:20.447735 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5945 16:34:20.450990 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5946 16:34:20.454169 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5947 16:34:20.457536 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5948 16:34:20.460803 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5949 16:34:20.467454 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5950 16:34:20.470818 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5951 16:34:20.474299 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5952 16:34:20.477504 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5953 16:34:20.480637 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5954 16:34:20.483761 ==
5955 16:34:20.487597 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 16:34:20.490690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 16:34:20.490919 ==
5958 16:34:20.491084 DQS Delay:
5959 16:34:20.493859 DQS0 = 0, DQS1 = 0
5960 16:34:20.493999 DQM Delay:
5961 16:34:20.497493 DQM0 = 97, DQM1 = 93
5962 16:34:20.497668 DQ Delay:
5963 16:34:20.500716 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5964 16:34:20.503719 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =94
5965 16:34:20.507682 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =86
5966 16:34:20.510525 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
5967 16:34:20.510789
5968 16:34:20.510974
5969 16:34:20.520586 [DQSOSCAuto] RK1, (LSB)MR18= 0xb21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5970 16:34:20.520959 CH1 RK1: MR19=505, MR18=B21
5971 16:34:20.527072 CH1_RK1: MR19=0x505, MR18=0xB21, DQSOSC=411, MR23=63, INC=64, DEC=42
5972 16:34:20.530257 [RxdqsGatingPostProcess] freq 933
5973 16:34:20.536765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5974 16:34:20.539802 best DQS0 dly(2T, 0.5T) = (0, 10)
5975 16:34:20.543083 best DQS1 dly(2T, 0.5T) = (0, 10)
5976 16:34:20.546619 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5977 16:34:20.549783 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5978 16:34:20.552996 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 16:34:20.553444 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 16:34:20.556194 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 16:34:20.560045 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 16:34:20.563265 Pre-setting of DQS Precalculation
5983 16:34:20.569626 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5984 16:34:20.576036 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5985 16:34:20.583228 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5986 16:34:20.583736
5987 16:34:20.584113
5988 16:34:20.586505 [Calibration Summary] 1866 Mbps
5989 16:34:20.589803 CH 0, Rank 0
5990 16:34:20.590213 SW Impedance : PASS
5991 16:34:20.592849 DUTY Scan : NO K
5992 16:34:20.595996 ZQ Calibration : PASS
5993 16:34:20.596409 Jitter Meter : NO K
5994 16:34:20.599295 CBT Training : PASS
5995 16:34:20.599707 Write leveling : PASS
5996 16:34:20.603046 RX DQS gating : PASS
5997 16:34:20.606160 RX DQ/DQS(RDDQC) : PASS
5998 16:34:20.606715 TX DQ/DQS : PASS
5999 16:34:20.609642 RX DATLAT : PASS
6000 16:34:20.612807 RX DQ/DQS(Engine): PASS
6001 16:34:20.613239 TX OE : NO K
6002 16:34:20.616166 All Pass.
6003 16:34:20.616584
6004 16:34:20.616966 CH 0, Rank 1
6005 16:34:20.619602 SW Impedance : PASS
6006 16:34:20.620011 DUTY Scan : NO K
6007 16:34:20.622664 ZQ Calibration : PASS
6008 16:34:20.625559 Jitter Meter : NO K
6009 16:34:20.626080 CBT Training : PASS
6010 16:34:20.629364 Write leveling : PASS
6011 16:34:20.632361 RX DQS gating : PASS
6012 16:34:20.632769 RX DQ/DQS(RDDQC) : PASS
6013 16:34:20.635815 TX DQ/DQS : PASS
6014 16:34:20.639104 RX DATLAT : PASS
6015 16:34:20.639515 RX DQ/DQS(Engine): PASS
6016 16:34:20.642219 TX OE : NO K
6017 16:34:20.642734 All Pass.
6018 16:34:20.643062
6019 16:34:20.645477 CH 1, Rank 0
6020 16:34:20.645887 SW Impedance : PASS
6021 16:34:20.649867 DUTY Scan : NO K
6022 16:34:20.653087 ZQ Calibration : PASS
6023 16:34:20.653645 Jitter Meter : NO K
6024 16:34:20.655701 CBT Training : PASS
6025 16:34:20.658852 Write leveling : PASS
6026 16:34:20.659263 RX DQS gating : PASS
6027 16:34:20.662266 RX DQ/DQS(RDDQC) : PASS
6028 16:34:20.665145 TX DQ/DQS : PASS
6029 16:34:20.665733 RX DATLAT : PASS
6030 16:34:20.668530 RX DQ/DQS(Engine): PASS
6031 16:34:20.672250 TX OE : NO K
6032 16:34:20.672713 All Pass.
6033 16:34:20.673075
6034 16:34:20.673510 CH 1, Rank 1
6035 16:34:20.675202 SW Impedance : PASS
6036 16:34:20.678594 DUTY Scan : NO K
6037 16:34:20.679120 ZQ Calibration : PASS
6038 16:34:20.681794 Jitter Meter : NO K
6039 16:34:20.682315 CBT Training : PASS
6040 16:34:20.685322 Write leveling : PASS
6041 16:34:20.688490 RX DQS gating : PASS
6042 16:34:20.688928 RX DQ/DQS(RDDQC) : PASS
6043 16:34:20.691517 TX DQ/DQS : PASS
6044 16:34:20.695409 RX DATLAT : PASS
6045 16:34:20.695819 RX DQ/DQS(Engine): PASS
6046 16:34:20.698662 TX OE : NO K
6047 16:34:20.699071 All Pass.
6048 16:34:20.699490
6049 16:34:20.701853 DramC Write-DBI off
6050 16:34:20.705058 PER_BANK_REFRESH: Hybrid Mode
6051 16:34:20.705602 TX_TRACKING: ON
6052 16:34:20.715165 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6053 16:34:20.718253 [FAST_K] Save calibration result to emmc
6054 16:34:20.721737 dramc_set_vcore_voltage set vcore to 650000
6055 16:34:20.725006 Read voltage for 400, 6
6056 16:34:20.725532 Vio18 = 0
6057 16:34:20.725864 Vcore = 650000
6058 16:34:20.728068 Vdram = 0
6059 16:34:20.728481 Vddq = 0
6060 16:34:20.728803 Vmddr = 0
6061 16:34:20.734947 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6062 16:34:20.741444 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6063 16:34:20.741866 MEM_TYPE=3, freq_sel=20
6064 16:34:20.744501 sv_algorithm_assistance_LP4_800
6065 16:34:20.747868 ============ PULL DRAM RESETB DOWN ============
6066 16:34:20.754594 ========== PULL DRAM RESETB DOWN end =========
6067 16:34:20.757844 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6068 16:34:20.761212 ===================================
6069 16:34:20.764479 LPDDR4 DRAM CONFIGURATION
6070 16:34:20.767703 ===================================
6071 16:34:20.768119 EX_ROW_EN[0] = 0x0
6072 16:34:20.771123 EX_ROW_EN[1] = 0x0
6073 16:34:20.771535 LP4Y_EN = 0x0
6074 16:34:20.774371 WORK_FSP = 0x0
6075 16:34:20.774784 WL = 0x2
6076 16:34:20.777702 RL = 0x2
6077 16:34:20.781028 BL = 0x2
6078 16:34:20.781624 RPST = 0x0
6079 16:34:20.784160 RD_PRE = 0x0
6080 16:34:20.784571 WR_PRE = 0x1
6081 16:34:20.787241 WR_PST = 0x0
6082 16:34:20.787733 DBI_WR = 0x0
6083 16:34:20.790663 DBI_RD = 0x0
6084 16:34:20.791156 OTF = 0x1
6085 16:34:20.793920 ===================================
6086 16:34:20.796920 ===================================
6087 16:34:20.800437 ANA top config
6088 16:34:20.803469 ===================================
6089 16:34:20.803905 DLL_ASYNC_EN = 0
6090 16:34:20.807178 ALL_SLAVE_EN = 1
6091 16:34:20.810419 NEW_RANK_MODE = 1
6092 16:34:20.813594 DLL_IDLE_MODE = 1
6093 16:34:20.816938 LP45_APHY_COMB_EN = 1
6094 16:34:20.817437 TX_ODT_DIS = 1
6095 16:34:20.820197 NEW_8X_MODE = 1
6096 16:34:20.823464 ===================================
6097 16:34:20.826602 ===================================
6098 16:34:20.830314 data_rate = 800
6099 16:34:20.833528 CKR = 1
6100 16:34:20.836903 DQ_P2S_RATIO = 4
6101 16:34:20.840001 ===================================
6102 16:34:20.842955 CA_P2S_RATIO = 4
6103 16:34:20.843372 DQ_CA_OPEN = 0
6104 16:34:20.846553 DQ_SEMI_OPEN = 1
6105 16:34:20.849825 CA_SEMI_OPEN = 1
6106 16:34:20.853148 CA_FULL_RATE = 0
6107 16:34:20.856070 DQ_CKDIV4_EN = 0
6108 16:34:20.859937 CA_CKDIV4_EN = 1
6109 16:34:20.860467 CA_PREDIV_EN = 0
6110 16:34:20.862802 PH8_DLY = 0
6111 16:34:20.865991 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6112 16:34:20.869519 DQ_AAMCK_DIV = 0
6113 16:34:20.872923 CA_AAMCK_DIV = 0
6114 16:34:20.876252 CA_ADMCK_DIV = 4
6115 16:34:20.878829 DQ_TRACK_CA_EN = 0
6116 16:34:20.879246 CA_PICK = 800
6117 16:34:20.882041 CA_MCKIO = 400
6118 16:34:20.885875 MCKIO_SEMI = 400
6119 16:34:20.888934 PLL_FREQ = 3016
6120 16:34:20.892435 DQ_UI_PI_RATIO = 32
6121 16:34:20.895656 CA_UI_PI_RATIO = 32
6122 16:34:20.899190 ===================================
6123 16:34:20.902208 ===================================
6124 16:34:20.905599 memory_type:LPDDR4
6125 16:34:20.906014 GP_NUM : 10
6126 16:34:20.908799 SRAM_EN : 1
6127 16:34:20.909215 MD32_EN : 0
6128 16:34:20.911899 ===================================
6129 16:34:20.915053 [ANA_INIT] >>>>>>>>>>>>>>
6130 16:34:20.918428 <<<<<< [CONFIGURE PHASE]: ANA_TX
6131 16:34:20.921899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6132 16:34:20.925600 ===================================
6133 16:34:20.928331 data_rate = 800,PCW = 0X7400
6134 16:34:20.931475 ===================================
6135 16:34:20.935222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6136 16:34:20.941842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 16:34:20.951359 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 16:34:20.954499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6139 16:34:20.958479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6140 16:34:20.964330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6141 16:34:20.964842 [ANA_INIT] flow start
6142 16:34:20.968112 [ANA_INIT] PLL >>>>>>>>
6143 16:34:20.971281 [ANA_INIT] PLL <<<<<<<<
6144 16:34:20.971735 [ANA_INIT] MIDPI >>>>>>>>
6145 16:34:20.974309 [ANA_INIT] MIDPI <<<<<<<<
6146 16:34:20.977894 [ANA_INIT] DLL >>>>>>>>
6147 16:34:20.978506 [ANA_INIT] flow end
6148 16:34:20.984434 ============ LP4 DIFF to SE enter ============
6149 16:34:20.987803 ============ LP4 DIFF to SE exit ============
6150 16:34:20.988380 [ANA_INIT] <<<<<<<<<<<<<
6151 16:34:20.991013 [Flow] Enable top DCM control >>>>>
6152 16:34:20.994269 [Flow] Enable top DCM control <<<<<
6153 16:34:20.997667 Enable DLL master slave shuffle
6154 16:34:21.004192 ==============================================================
6155 16:34:21.007290 Gating Mode config
6156 16:34:21.010781 ==============================================================
6157 16:34:21.013799 Config description:
6158 16:34:21.024090 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6159 16:34:21.030400 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6160 16:34:21.033783 SELPH_MODE 0: By rank 1: By Phase
6161 16:34:21.039974 ==============================================================
6162 16:34:21.044134 GAT_TRACK_EN = 0
6163 16:34:21.047381 RX_GATING_MODE = 2
6164 16:34:21.050318 RX_GATING_TRACK_MODE = 2
6165 16:34:21.053300 SELPH_MODE = 1
6166 16:34:21.056402 PICG_EARLY_EN = 1
6167 16:34:21.056903 VALID_LAT_VALUE = 1
6168 16:34:21.063280 ==============================================================
6169 16:34:21.066553 Enter into Gating configuration >>>>
6170 16:34:21.069682 Exit from Gating configuration <<<<
6171 16:34:21.073156 Enter into DVFS_PRE_config >>>>>
6172 16:34:21.082907 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6173 16:34:21.085993 Exit from DVFS_PRE_config <<<<<
6174 16:34:21.089599 Enter into PICG configuration >>>>
6175 16:34:21.092729 Exit from PICG configuration <<<<
6176 16:34:21.096214 [RX_INPUT] configuration >>>>>
6177 16:34:21.099399 [RX_INPUT] configuration <<<<<
6178 16:34:21.106251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6179 16:34:21.109311 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6180 16:34:21.116146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6181 16:34:21.122993 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6182 16:34:21.129302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 16:34:21.135763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 16:34:21.139250 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6185 16:34:21.142095 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6186 16:34:21.145279 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6187 16:34:21.152450 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6188 16:34:21.155412 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6189 16:34:21.158675 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 16:34:21.162484 ===================================
6191 16:34:21.165657 LPDDR4 DRAM CONFIGURATION
6192 16:34:21.168872 ===================================
6193 16:34:21.171847 EX_ROW_EN[0] = 0x0
6194 16:34:21.172268 EX_ROW_EN[1] = 0x0
6195 16:34:21.175561 LP4Y_EN = 0x0
6196 16:34:21.176084 WORK_FSP = 0x0
6197 16:34:21.178454 WL = 0x2
6198 16:34:21.178871 RL = 0x2
6199 16:34:21.182125 BL = 0x2
6200 16:34:21.182656 RPST = 0x0
6201 16:34:21.185097 RD_PRE = 0x0
6202 16:34:21.185573 WR_PRE = 0x1
6203 16:34:21.188281 WR_PST = 0x0
6204 16:34:21.188702 DBI_WR = 0x0
6205 16:34:21.191631 DBI_RD = 0x0
6206 16:34:21.194803 OTF = 0x1
6207 16:34:21.198314 ===================================
6208 16:34:21.201498 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6209 16:34:21.204422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6210 16:34:21.208114 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 16:34:21.211182 ===================================
6212 16:34:21.214528 LPDDR4 DRAM CONFIGURATION
6213 16:34:21.217706 ===================================
6214 16:34:21.221449 EX_ROW_EN[0] = 0x10
6215 16:34:21.221938 EX_ROW_EN[1] = 0x0
6216 16:34:21.224963 LP4Y_EN = 0x0
6217 16:34:21.225546 WORK_FSP = 0x0
6218 16:34:21.227755 WL = 0x2
6219 16:34:21.228167 RL = 0x2
6220 16:34:21.230867 BL = 0x2
6221 16:34:21.231282 RPST = 0x0
6222 16:34:21.234185 RD_PRE = 0x0
6223 16:34:21.234611 WR_PRE = 0x1
6224 16:34:21.237645 WR_PST = 0x0
6225 16:34:21.238056 DBI_WR = 0x0
6226 16:34:21.241052 DBI_RD = 0x0
6227 16:34:21.244596 OTF = 0x1
6228 16:34:21.247557 ===================================
6229 16:34:21.251694 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6230 16:34:21.255942 nWR fixed to 30
6231 16:34:21.259441 [ModeRegInit_LP4] CH0 RK0
6232 16:34:21.259948 [ModeRegInit_LP4] CH0 RK1
6233 16:34:21.262771 [ModeRegInit_LP4] CH1 RK0
6234 16:34:21.265855 [ModeRegInit_LP4] CH1 RK1
6235 16:34:21.266312 match AC timing 19
6236 16:34:21.272795 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6237 16:34:21.276003 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6238 16:34:21.279155 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6239 16:34:21.285580 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6240 16:34:21.288771 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6241 16:34:21.289182 ==
6242 16:34:21.291914 Dram Type= 6, Freq= 0, CH_0, rank 0
6243 16:34:21.295283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 16:34:21.295700 ==
6245 16:34:21.302008 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 16:34:21.308760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6247 16:34:21.311857 [CA 0] Center 36 (8~64) winsize 57
6248 16:34:21.315048 [CA 1] Center 36 (8~64) winsize 57
6249 16:34:21.318948 [CA 2] Center 36 (8~64) winsize 57
6250 16:34:21.321949 [CA 3] Center 36 (8~64) winsize 57
6251 16:34:21.324957 [CA 4] Center 36 (8~64) winsize 57
6252 16:34:21.328585 [CA 5] Center 36 (8~64) winsize 57
6253 16:34:21.329002
6254 16:34:21.331837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6255 16:34:21.332250
6256 16:34:21.334895 [CATrainingPosCal] consider 1 rank data
6257 16:34:21.338519 u2DelayCellTimex100 = 270/100 ps
6258 16:34:21.341459 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 16:34:21.344596 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 16:34:21.348100 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 16:34:21.351341 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 16:34:21.354883 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 16:34:21.358237 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 16:34:21.358546
6265 16:34:21.364704 CA PerBit enable=1, Macro0, CA PI delay=36
6266 16:34:21.365011
6267 16:34:21.367847 [CBTSetCACLKResult] CA Dly = 36
6268 16:34:21.368095 CS Dly: 1 (0~32)
6269 16:34:21.368268 ==
6270 16:34:21.371080 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 16:34:21.374067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 16:34:21.374305 ==
6273 16:34:21.380948 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6274 16:34:21.387565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6275 16:34:21.390710 [CA 0] Center 36 (8~64) winsize 57
6276 16:34:21.394499 [CA 1] Center 36 (8~64) winsize 57
6277 16:34:21.397833 [CA 2] Center 36 (8~64) winsize 57
6278 16:34:21.401291 [CA 3] Center 36 (8~64) winsize 57
6279 16:34:21.404581 [CA 4] Center 36 (8~64) winsize 57
6280 16:34:21.405224 [CA 5] Center 36 (8~64) winsize 57
6281 16:34:21.407499
6282 16:34:21.410959 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6283 16:34:21.411372
6284 16:34:21.413818 [CATrainingPosCal] consider 2 rank data
6285 16:34:21.417692 u2DelayCellTimex100 = 270/100 ps
6286 16:34:21.420525 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 16:34:21.423931 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 16:34:21.427740 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 16:34:21.430732 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 16:34:21.433722 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 16:34:21.437348 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 16:34:21.437872
6293 16:34:21.440588 CA PerBit enable=1, Macro0, CA PI delay=36
6294 16:34:21.443653
6295 16:34:21.444098 [CBTSetCACLKResult] CA Dly = 36
6296 16:34:21.447340 CS Dly: 1 (0~32)
6297 16:34:21.447763
6298 16:34:21.450050 ----->DramcWriteLeveling(PI) begin...
6299 16:34:21.450480 ==
6300 16:34:21.453549 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 16:34:21.456731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 16:34:21.457185 ==
6303 16:34:21.459840 Write leveling (Byte 0): 40 => 8
6304 16:34:21.463142 Write leveling (Byte 1): 40 => 8
6305 16:34:21.466364 DramcWriteLeveling(PI) end<-----
6306 16:34:21.466777
6307 16:34:21.467098 ==
6308 16:34:21.469814 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 16:34:21.473028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 16:34:21.476333 ==
6311 16:34:21.476743 [Gating] SW mode calibration
6312 16:34:21.486761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6313 16:34:21.490172 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6314 16:34:21.492864 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 16:34:21.499745 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 16:34:21.502992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 16:34:21.506322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 16:34:21.512861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 16:34:21.516076 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 16:34:21.519296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 16:34:21.526328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 16:34:21.529300 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 16:34:21.532547 Total UI for P1: 0, mck2ui 16
6324 16:34:21.535525 best dqsien dly found for B0: ( 0, 14, 24)
6325 16:34:21.538940 Total UI for P1: 0, mck2ui 16
6326 16:34:21.542794 best dqsien dly found for B1: ( 0, 14, 24)
6327 16:34:21.545780 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6328 16:34:21.549020 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6329 16:34:21.549559
6330 16:34:21.552424 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 16:34:21.558489 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 16:34:21.558898 [Gating] SW calibration Done
6333 16:34:21.559216 ==
6334 16:34:21.561966 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 16:34:21.568479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 16:34:21.568974 ==
6337 16:34:21.569365 RX Vref Scan: 0
6338 16:34:21.569701
6339 16:34:21.571791 RX Vref 0 -> 0, step: 1
6340 16:34:21.572372
6341 16:34:21.575607 RX Delay -410 -> 252, step: 16
6342 16:34:21.578847 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6343 16:34:21.582172 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6344 16:34:21.588788 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6345 16:34:21.592127 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6346 16:34:21.595319 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6347 16:34:21.599129 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6348 16:34:21.605117 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6349 16:34:21.608318 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6350 16:34:21.611752 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6351 16:34:21.615342 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6352 16:34:21.622120 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6353 16:34:21.625002 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6354 16:34:21.628194 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6355 16:34:21.634689 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6356 16:34:21.637719 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6357 16:34:21.641793 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6358 16:34:21.642315 ==
6359 16:34:21.645008 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 16:34:21.647795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 16:34:21.651475 ==
6362 16:34:21.651889 DQS Delay:
6363 16:34:21.652212 DQS0 = 35, DQS1 = 59
6364 16:34:21.654813 DQM Delay:
6365 16:34:21.655228 DQM0 = 5, DQM1 = 17
6366 16:34:21.658112 DQ Delay:
6367 16:34:21.658669 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6368 16:34:21.660866 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6369 16:34:21.664732 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6370 16:34:21.667962 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6371 16:34:21.668422
6372 16:34:21.668747
6373 16:34:21.669047 ==
6374 16:34:21.671291 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 16:34:21.677916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 16:34:21.678701 ==
6377 16:34:21.679034
6378 16:34:21.679334
6379 16:34:21.680933 TX Vref Scan disable
6380 16:34:21.681374 == TX Byte 0 ==
6381 16:34:21.683998 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 16:34:21.690588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 16:34:21.691007 == TX Byte 1 ==
6384 16:34:21.693909 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 16:34:21.700655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 16:34:21.701067 ==
6387 16:34:21.703876 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 16:34:21.707162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 16:34:21.707578 ==
6390 16:34:21.707904
6391 16:34:21.708203
6392 16:34:21.710389 TX Vref Scan disable
6393 16:34:21.710802 == TX Byte 0 ==
6394 16:34:21.713551 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 16:34:21.720698 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 16:34:21.721119 == TX Byte 1 ==
6397 16:34:21.724032 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 16:34:21.730473 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 16:34:21.730990
6400 16:34:21.731314 [DATLAT]
6401 16:34:21.731614 Freq=400, CH0 RK0
6402 16:34:21.733708
6403 16:34:21.734230 DATLAT Default: 0xf
6404 16:34:21.737012 0, 0xFFFF, sum = 0
6405 16:34:21.737574 1, 0xFFFF, sum = 0
6406 16:34:21.740011 2, 0xFFFF, sum = 0
6407 16:34:21.740466 3, 0xFFFF, sum = 0
6408 16:34:21.743307 4, 0xFFFF, sum = 0
6409 16:34:21.743727 5, 0xFFFF, sum = 0
6410 16:34:21.746570 6, 0xFFFF, sum = 0
6411 16:34:21.746991 7, 0xFFFF, sum = 0
6412 16:34:21.750475 8, 0xFFFF, sum = 0
6413 16:34:21.751016 9, 0xFFFF, sum = 0
6414 16:34:21.753380 10, 0xFFFF, sum = 0
6415 16:34:21.753801 11, 0xFFFF, sum = 0
6416 16:34:21.756448 12, 0xFFFF, sum = 0
6417 16:34:21.756885 13, 0x0, sum = 1
6418 16:34:21.759969 14, 0x0, sum = 2
6419 16:34:21.760406 15, 0x0, sum = 3
6420 16:34:21.762886 16, 0x0, sum = 4
6421 16:34:21.763399 best_step = 14
6422 16:34:21.763890
6423 16:34:21.764364 ==
6424 16:34:21.766180 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 16:34:21.773474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 16:34:21.773984 ==
6427 16:34:21.774315 RX Vref Scan: 1
6428 16:34:21.774619
6429 16:34:21.776580 RX Vref 0 -> 0, step: 1
6430 16:34:21.777097
6431 16:34:21.779536 RX Delay -359 -> 252, step: 8
6432 16:34:21.779953
6433 16:34:21.782772 Set Vref, RX VrefLevel [Byte0]: 58
6434 16:34:21.786063 [Byte1]: 49
6435 16:34:21.789512
6436 16:34:21.789932 Final RX Vref Byte 0 = 58 to rank0
6437 16:34:21.792956 Final RX Vref Byte 1 = 49 to rank0
6438 16:34:21.796118 Final RX Vref Byte 0 = 58 to rank1
6439 16:34:21.799673 Final RX Vref Byte 1 = 49 to rank1==
6440 16:34:21.802561 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 16:34:21.809409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 16:34:21.809829 ==
6443 16:34:21.810154 DQS Delay:
6444 16:34:21.812803 DQS0 = 44, DQS1 = 60
6445 16:34:21.813213 DQM Delay:
6446 16:34:21.813590 DQM0 = 10, DQM1 = 17
6447 16:34:21.815922 DQ Delay:
6448 16:34:21.819617 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6449 16:34:21.823019 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6450 16:34:21.823438 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6451 16:34:21.828953 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6452 16:34:21.829425
6453 16:34:21.829775
6454 16:34:21.835762 [DQSOSCAuto] RK0, (LSB)MR18= 0x998c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6455 16:34:21.839697 CH0 RK0: MR19=C0C, MR18=998C
6456 16:34:21.845929 CH0_RK0: MR19=0xC0C, MR18=0x998C, DQSOSC=390, MR23=63, INC=388, DEC=258
6457 16:34:21.846525 ==
6458 16:34:21.849113 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 16:34:21.851806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 16:34:21.852266 ==
6461 16:34:21.856075 [Gating] SW mode calibration
6462 16:34:21.861817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6463 16:34:21.868712 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6464 16:34:21.871587 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 16:34:21.875170 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 16:34:21.882157 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 16:34:21.885503 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 16:34:21.888260 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 16:34:21.894499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 16:34:21.898350 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 16:34:21.901622 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 16:34:21.907914 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 16:34:21.911549 Total UI for P1: 0, mck2ui 16
6474 16:34:21.914489 best dqsien dly found for B0: ( 0, 14, 24)
6475 16:34:21.917642 Total UI for P1: 0, mck2ui 16
6476 16:34:21.921173 best dqsien dly found for B1: ( 0, 14, 24)
6477 16:34:21.924217 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6478 16:34:21.928177 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6479 16:34:21.928697
6480 16:34:21.930691 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 16:34:21.934276 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 16:34:21.937480 [Gating] SW calibration Done
6483 16:34:21.937895 ==
6484 16:34:21.940907 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 16:34:21.944163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 16:34:21.944578 ==
6487 16:34:21.947395 RX Vref Scan: 0
6488 16:34:21.947808
6489 16:34:21.950595 RX Vref 0 -> 0, step: 1
6490 16:34:21.951007
6491 16:34:21.954754 RX Delay -410 -> 252, step: 16
6492 16:34:21.957637 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6493 16:34:21.960968 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6494 16:34:21.964379 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6495 16:34:21.970488 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6496 16:34:21.973961 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6497 16:34:21.977456 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6498 16:34:21.980276 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6499 16:34:21.986865 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6500 16:34:21.990009 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6501 16:34:21.993821 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6502 16:34:21.997082 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6503 16:34:22.003298 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6504 16:34:22.006389 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6505 16:34:22.009754 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6506 16:34:22.016389 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6507 16:34:22.019423 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6508 16:34:22.019849 ==
6509 16:34:22.022906 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 16:34:22.026407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 16:34:22.026830 ==
6512 16:34:22.029499 DQS Delay:
6513 16:34:22.029932 DQS0 = 35, DQS1 = 59
6514 16:34:22.032637 DQM Delay:
6515 16:34:22.033054 DQM0 = 5, DQM1 = 17
6516 16:34:22.033429 DQ Delay:
6517 16:34:22.036396 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6518 16:34:22.039127 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6519 16:34:22.042817 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6520 16:34:22.045657 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6521 16:34:22.045929
6522 16:34:22.046108
6523 16:34:22.046272 ==
6524 16:34:22.049331 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 16:34:22.055891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 16:34:22.056083 ==
6527 16:34:22.056205
6528 16:34:22.056315
6529 16:34:22.056420 TX Vref Scan disable
6530 16:34:22.059081 == TX Byte 0 ==
6531 16:34:22.062405 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6532 16:34:22.065540 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6533 16:34:22.068517 == TX Byte 1 ==
6534 16:34:22.072323 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6535 16:34:22.075493 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6536 16:34:22.075586 ==
6537 16:34:22.078781 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 16:34:22.085677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 16:34:22.085761 ==
6540 16:34:22.085825
6541 16:34:22.085884
6542 16:34:22.085941 TX Vref Scan disable
6543 16:34:22.088677 == TX Byte 0 ==
6544 16:34:22.092361 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6545 16:34:22.095634 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6546 16:34:22.098915 == TX Byte 1 ==
6547 16:34:22.102072 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6548 16:34:22.104954 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6549 16:34:22.105046
6550 16:34:22.108095 [DATLAT]
6551 16:34:22.108202 Freq=400, CH0 RK1
6552 16:34:22.108281
6553 16:34:22.112029 DATLAT Default: 0xe
6554 16:34:22.112110 0, 0xFFFF, sum = 0
6555 16:34:22.115123 1, 0xFFFF, sum = 0
6556 16:34:22.115212 2, 0xFFFF, sum = 0
6557 16:34:22.118389 3, 0xFFFF, sum = 0
6558 16:34:22.118477 4, 0xFFFF, sum = 0
6559 16:34:22.121449 5, 0xFFFF, sum = 0
6560 16:34:22.121545 6, 0xFFFF, sum = 0
6561 16:34:22.124554 7, 0xFFFF, sum = 0
6562 16:34:22.124663 8, 0xFFFF, sum = 0
6563 16:34:22.128495 9, 0xFFFF, sum = 0
6564 16:34:22.131679 10, 0xFFFF, sum = 0
6565 16:34:22.131847 11, 0xFFFF, sum = 0
6566 16:34:22.134504 12, 0xFFFF, sum = 0
6567 16:34:22.134685 13, 0x0, sum = 1
6568 16:34:22.138234 14, 0x0, sum = 2
6569 16:34:22.138323 15, 0x0, sum = 3
6570 16:34:22.141677 16, 0x0, sum = 4
6571 16:34:22.141766 best_step = 14
6572 16:34:22.141834
6573 16:34:22.141898 ==
6574 16:34:22.144988 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 16:34:22.148046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 16:34:22.148141 ==
6577 16:34:22.151629 RX Vref Scan: 0
6578 16:34:22.151810
6579 16:34:22.154552 RX Vref 0 -> 0, step: 1
6580 16:34:22.154734
6581 16:34:22.154831 RX Delay -359 -> 252, step: 8
6582 16:34:22.163481 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6583 16:34:22.166876 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6584 16:34:22.170294 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6585 16:34:22.176353 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6586 16:34:22.179571 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6587 16:34:22.183263 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6588 16:34:22.186408 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6589 16:34:22.192856 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6590 16:34:22.195983 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6591 16:34:22.199554 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6592 16:34:22.203086 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6593 16:34:22.209255 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6594 16:34:22.212757 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6595 16:34:22.215971 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6596 16:34:22.222430 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6597 16:34:22.225614 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6598 16:34:22.225761 ==
6599 16:34:22.228862 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 16:34:22.232328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 16:34:22.232510 ==
6602 16:34:22.236105 DQS Delay:
6603 16:34:22.236274 DQS0 = 40, DQS1 = 60
6604 16:34:22.236356 DQM Delay:
6605 16:34:22.238967 DQM0 = 6, DQM1 = 13
6606 16:34:22.239126 DQ Delay:
6607 16:34:22.241933 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6608 16:34:22.245404 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6609 16:34:22.249011 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6610 16:34:22.252217 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6611 16:34:22.252392
6612 16:34:22.252481
6613 16:34:22.262111 [DQSOSCAuto] RK1, (LSB)MR18= 0x9087, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6614 16:34:22.262279 CH0 RK1: MR19=C0C, MR18=9087
6615 16:34:22.268606 CH0_RK1: MR19=0xC0C, MR18=0x9087, DQSOSC=391, MR23=63, INC=386, DEC=257
6616 16:34:22.272157 [RxdqsGatingPostProcess] freq 400
6617 16:34:22.278842 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6618 16:34:22.281486 best DQS0 dly(2T, 0.5T) = (0, 10)
6619 16:34:22.284927 best DQS1 dly(2T, 0.5T) = (0, 10)
6620 16:34:22.288358 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6621 16:34:22.291439 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6622 16:34:22.295120 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 16:34:22.298367 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 16:34:22.301592 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 16:34:22.304895 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 16:34:22.305227 Pre-setting of DQS Precalculation
6627 16:34:22.311485 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6628 16:34:22.311859 ==
6629 16:34:22.315182 Dram Type= 6, Freq= 0, CH_1, rank 0
6630 16:34:22.317933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 16:34:22.318351 ==
6632 16:34:22.325046 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 16:34:22.334971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 16:34:22.335659 [CA 0] Center 36 (8~64) winsize 57
6635 16:34:22.337784 [CA 1] Center 36 (8~64) winsize 57
6636 16:34:22.340977 [CA 2] Center 36 (8~64) winsize 57
6637 16:34:22.344391 [CA 3] Center 36 (8~64) winsize 57
6638 16:34:22.348170 [CA 4] Center 36 (8~64) winsize 57
6639 16:34:22.348590 [CA 5] Center 36 (8~64) winsize 57
6640 16:34:22.351429
6641 16:34:22.354656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 16:34:22.355166
6643 16:34:22.358034 [CATrainingPosCal] consider 1 rank data
6644 16:34:22.361011 u2DelayCellTimex100 = 270/100 ps
6645 16:34:22.364914 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 16:34:22.367825 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 16:34:22.370694 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 16:34:22.374095 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 16:34:22.377609 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 16:34:22.380552 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 16:34:22.380966
6652 16:34:22.383646 CA PerBit enable=1, Macro0, CA PI delay=36
6653 16:34:22.387603
6654 16:34:22.388012 [CBTSetCACLKResult] CA Dly = 36
6655 16:34:22.390626 CS Dly: 1 (0~32)
6656 16:34:22.391040 ==
6657 16:34:22.393925 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 16:34:22.397032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 16:34:22.397503 ==
6660 16:34:22.403610 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6661 16:34:22.410363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6662 16:34:22.413872 [CA 0] Center 36 (8~64) winsize 57
6663 16:34:22.416734 [CA 1] Center 36 (8~64) winsize 57
6664 16:34:22.420067 [CA 2] Center 36 (8~64) winsize 57
6665 16:34:22.423440 [CA 3] Center 36 (8~64) winsize 57
6666 16:34:22.423859 [CA 4] Center 36 (8~64) winsize 57
6667 16:34:22.426921 [CA 5] Center 36 (8~64) winsize 57
6668 16:34:22.427571
6669 16:34:22.433778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6670 16:34:22.434292
6671 16:34:22.436591 [CATrainingPosCal] consider 2 rank data
6672 16:34:22.440125 u2DelayCellTimex100 = 270/100 ps
6673 16:34:22.442972 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 16:34:22.446841 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 16:34:22.449861 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 16:34:22.453240 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 16:34:22.456490 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 16:34:22.460130 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 16:34:22.460642
6680 16:34:22.463570 CA PerBit enable=1, Macro0, CA PI delay=36
6681 16:34:22.464080
6682 16:34:22.466182 [CBTSetCACLKResult] CA Dly = 36
6683 16:34:22.469735 CS Dly: 1 (0~32)
6684 16:34:22.470292
6685 16:34:22.472758 ----->DramcWriteLeveling(PI) begin...
6686 16:34:22.473218 ==
6687 16:34:22.475875 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 16:34:22.479999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 16:34:22.480510 ==
6690 16:34:22.482995 Write leveling (Byte 0): 40 => 8
6691 16:34:22.486373 Write leveling (Byte 1): 40 => 8
6692 16:34:22.489662 DramcWriteLeveling(PI) end<-----
6693 16:34:22.490178
6694 16:34:22.490504 ==
6695 16:34:22.492624 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 16:34:22.495798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 16:34:22.496216 ==
6698 16:34:22.498838 [Gating] SW mode calibration
6699 16:34:22.505555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6700 16:34:22.512037 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6701 16:34:22.515319 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 16:34:22.522236 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 16:34:22.525029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 16:34:22.528487 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 16:34:22.535696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 16:34:22.538803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 16:34:22.542072 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 16:34:22.548555 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 16:34:22.551773 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 16:34:22.555031 Total UI for P1: 0, mck2ui 16
6711 16:34:22.558246 best dqsien dly found for B0: ( 0, 14, 24)
6712 16:34:22.561391 Total UI for P1: 0, mck2ui 16
6713 16:34:22.564930 best dqsien dly found for B1: ( 0, 14, 24)
6714 16:34:22.568212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6715 16:34:22.571290 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6716 16:34:22.571709
6717 16:34:22.574873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 16:34:22.581538 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 16:34:22.582001 [Gating] SW calibration Done
6720 16:34:22.582471 ==
6721 16:34:22.584747 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 16:34:22.591231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 16:34:22.591651 ==
6724 16:34:22.591975 RX Vref Scan: 0
6725 16:34:22.592276
6726 16:34:22.594365 RX Vref 0 -> 0, step: 1
6727 16:34:22.594778
6728 16:34:22.597737 RX Delay -410 -> 252, step: 16
6729 16:34:22.601538 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6730 16:34:22.604643 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6731 16:34:22.611009 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6732 16:34:22.614408 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6733 16:34:22.617498 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6734 16:34:22.620643 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6735 16:34:22.627134 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6736 16:34:22.630606 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6737 16:34:22.633976 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6738 16:34:22.637021 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6739 16:34:22.643845 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6740 16:34:22.647378 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6741 16:34:22.650817 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6742 16:34:22.656892 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6743 16:34:22.660161 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6744 16:34:22.663309 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6745 16:34:22.663727 ==
6746 16:34:22.666994 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 16:34:22.669981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 16:34:22.673132 ==
6749 16:34:22.673590 DQS Delay:
6750 16:34:22.673940 DQS0 = 43, DQS1 = 51
6751 16:34:22.676984 DQM Delay:
6752 16:34:22.677532 DQM0 = 13, DQM1 = 13
6753 16:34:22.680223 DQ Delay:
6754 16:34:22.683071 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6755 16:34:22.683502 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6756 16:34:22.686685 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6757 16:34:22.689819 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6758 16:34:22.690362
6759 16:34:22.690822
6760 16:34:22.693127 ==
6761 16:34:22.696233 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 16:34:22.700196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 16:34:22.700641 ==
6764 16:34:22.700968
6765 16:34:22.701304
6766 16:34:22.703761 TX Vref Scan disable
6767 16:34:22.704294 == TX Byte 0 ==
6768 16:34:22.706707 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 16:34:22.712873 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 16:34:22.713341 == TX Byte 1 ==
6771 16:34:22.716110 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 16:34:22.722826 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 16:34:22.723320 ==
6774 16:34:22.725924 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 16:34:22.729485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 16:34:22.729916 ==
6777 16:34:22.730244
6778 16:34:22.730545
6779 16:34:22.732915 TX Vref Scan disable
6780 16:34:22.733355 == TX Byte 0 ==
6781 16:34:22.736046 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 16:34:22.742264 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 16:34:22.742680 == TX Byte 1 ==
6784 16:34:22.745660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 16:34:22.752557 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 16:34:22.753121
6787 16:34:22.753567 [DATLAT]
6788 16:34:22.755915 Freq=400, CH1 RK0
6789 16:34:22.756431
6790 16:34:22.756755 DATLAT Default: 0xf
6791 16:34:22.758973 0, 0xFFFF, sum = 0
6792 16:34:22.759496 1, 0xFFFF, sum = 0
6793 16:34:22.762213 2, 0xFFFF, sum = 0
6794 16:34:22.762637 3, 0xFFFF, sum = 0
6795 16:34:22.765891 4, 0xFFFF, sum = 0
6796 16:34:22.766313 5, 0xFFFF, sum = 0
6797 16:34:22.769115 6, 0xFFFF, sum = 0
6798 16:34:22.769574 7, 0xFFFF, sum = 0
6799 16:34:22.772212 8, 0xFFFF, sum = 0
6800 16:34:22.772630 9, 0xFFFF, sum = 0
6801 16:34:22.775375 10, 0xFFFF, sum = 0
6802 16:34:22.775793 11, 0xFFFF, sum = 0
6803 16:34:22.779180 12, 0xFFFF, sum = 0
6804 16:34:22.779600 13, 0x0, sum = 1
6805 16:34:22.782554 14, 0x0, sum = 2
6806 16:34:22.783070 15, 0x0, sum = 3
6807 16:34:22.785572 16, 0x0, sum = 4
6808 16:34:22.786126 best_step = 14
6809 16:34:22.786470
6810 16:34:22.786775 ==
6811 16:34:22.788580 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 16:34:22.795218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 16:34:22.795651 ==
6814 16:34:22.795975 RX Vref Scan: 1
6815 16:34:22.796278
6816 16:34:22.798988 RX Vref 0 -> 0, step: 1
6817 16:34:22.799415
6818 16:34:22.802002 RX Delay -343 -> 252, step: 8
6819 16:34:22.802414
6820 16:34:22.805180 Set Vref, RX VrefLevel [Byte0]: 52
6821 16:34:22.808347 [Byte1]: 52
6822 16:34:22.812187
6823 16:34:22.812597 Final RX Vref Byte 0 = 52 to rank0
6824 16:34:22.815379 Final RX Vref Byte 1 = 52 to rank0
6825 16:34:22.818575 Final RX Vref Byte 0 = 52 to rank1
6826 16:34:22.821516 Final RX Vref Byte 1 = 52 to rank1==
6827 16:34:22.824698 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 16:34:22.831574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 16:34:22.832059 ==
6830 16:34:22.832385 DQS Delay:
6831 16:34:22.834817 DQS0 = 44, DQS1 = 52
6832 16:34:22.835228 DQM Delay:
6833 16:34:22.835550 DQM0 = 10, DQM1 = 10
6834 16:34:22.838234 DQ Delay:
6835 16:34:22.841477 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6836 16:34:22.844876 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6837 16:34:22.845431 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6838 16:34:22.848274 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6839 16:34:22.851767
6840 16:34:22.852399
6841 16:34:22.858266 [DQSOSCAuto] RK0, (LSB)MR18= 0x739a, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6842 16:34:22.861454 CH1 RK0: MR19=C0C, MR18=739A
6843 16:34:22.867948 CH1_RK0: MR19=0xC0C, MR18=0x739A, DQSOSC=390, MR23=63, INC=388, DEC=258
6844 16:34:22.868363 ==
6845 16:34:22.871287 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 16:34:22.874221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 16:34:22.874636 ==
6848 16:34:22.877735 [Gating] SW mode calibration
6849 16:34:22.884755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6850 16:34:22.891424 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6851 16:34:22.894419 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 16:34:22.897587 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 16:34:22.904406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 16:34:22.907309 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 16:34:22.910488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 16:34:22.917815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 16:34:22.920854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 16:34:22.924089 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 16:34:22.930631 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 16:34:22.931128 Total UI for P1: 0, mck2ui 16
6861 16:34:22.937221 best dqsien dly found for B0: ( 0, 14, 24)
6862 16:34:22.937689 Total UI for P1: 0, mck2ui 16
6863 16:34:22.943825 best dqsien dly found for B1: ( 0, 14, 24)
6864 16:34:22.947299 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6865 16:34:22.950251 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6866 16:34:22.950664
6867 16:34:22.953601 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 16:34:22.957074 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 16:34:22.960239 [Gating] SW calibration Done
6870 16:34:22.960661 ==
6871 16:34:22.963691 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 16:34:22.966791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 16:34:22.967208 ==
6874 16:34:22.969896 RX Vref Scan: 0
6875 16:34:22.970311
6876 16:34:22.973245 RX Vref 0 -> 0, step: 1
6877 16:34:22.973677
6878 16:34:22.974038 RX Delay -410 -> 252, step: 16
6879 16:34:22.979659 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6880 16:34:22.983140 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6881 16:34:22.986705 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6882 16:34:22.992933 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6883 16:34:22.996280 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6884 16:34:22.999754 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6885 16:34:23.003007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6886 16:34:23.009215 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6887 16:34:23.012493 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6888 16:34:23.016714 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6889 16:34:23.019597 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6890 16:34:23.025850 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6891 16:34:23.028906 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6892 16:34:23.032368 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6893 16:34:23.039002 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6894 16:34:23.042065 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6895 16:34:23.042572 ==
6896 16:34:23.045360 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 16:34:23.049203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 16:34:23.049757 ==
6899 16:34:23.052376 DQS Delay:
6900 16:34:23.052884 DQS0 = 43, DQS1 = 51
6901 16:34:23.053213 DQM Delay:
6902 16:34:23.055677 DQM0 = 8, DQM1 = 14
6903 16:34:23.056184 DQ Delay:
6904 16:34:23.058764 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6905 16:34:23.062209 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6906 16:34:23.065209 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6907 16:34:23.068742 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6908 16:34:23.069162
6909 16:34:23.069550
6910 16:34:23.069854 ==
6911 16:34:23.071934 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 16:34:23.075181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 16:34:23.075637 ==
6914 16:34:23.078286
6915 16:34:23.078697
6916 16:34:23.079018 TX Vref Scan disable
6917 16:34:23.082223 == TX Byte 0 ==
6918 16:34:23.085210 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6919 16:34:23.088407 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6920 16:34:23.091533 == TX Byte 1 ==
6921 16:34:23.094767 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6922 16:34:23.098603 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6923 16:34:23.099019 ==
6924 16:34:23.101785 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 16:34:23.104914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 16:34:23.107982 ==
6927 16:34:23.108394
6928 16:34:23.108728
6929 16:34:23.109027 TX Vref Scan disable
6930 16:34:23.111602 == TX Byte 0 ==
6931 16:34:23.114582 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6932 16:34:23.117930 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6933 16:34:23.121308 == TX Byte 1 ==
6934 16:34:23.124395 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6935 16:34:23.128147 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6936 16:34:23.128659
6937 16:34:23.131388 [DATLAT]
6938 16:34:23.131801 Freq=400, CH1 RK1
6939 16:34:23.132139
6940 16:34:23.134728 DATLAT Default: 0xe
6941 16:34:23.135250 0, 0xFFFF, sum = 0
6942 16:34:23.137619 1, 0xFFFF, sum = 0
6943 16:34:23.138037 2, 0xFFFF, sum = 0
6944 16:34:23.141247 3, 0xFFFF, sum = 0
6945 16:34:23.141787 4, 0xFFFF, sum = 0
6946 16:34:23.144412 5, 0xFFFF, sum = 0
6947 16:34:23.144988 6, 0xFFFF, sum = 0
6948 16:34:23.147422 7, 0xFFFF, sum = 0
6949 16:34:23.147840 8, 0xFFFF, sum = 0
6950 16:34:23.150879 9, 0xFFFF, sum = 0
6951 16:34:23.151433 10, 0xFFFF, sum = 0
6952 16:34:23.154720 11, 0xFFFF, sum = 0
6953 16:34:23.157400 12, 0xFFFF, sum = 0
6954 16:34:23.157825 13, 0x0, sum = 1
6955 16:34:23.160815 14, 0x0, sum = 2
6956 16:34:23.161615 15, 0x0, sum = 3
6957 16:34:23.161998 16, 0x0, sum = 4
6958 16:34:23.164298 best_step = 14
6959 16:34:23.164713
6960 16:34:23.165034 ==
6961 16:34:23.167291 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 16:34:23.170775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 16:34:23.171191 ==
6964 16:34:23.173739 RX Vref Scan: 0
6965 16:34:23.174153
6966 16:34:23.177330 RX Vref 0 -> 0, step: 1
6967 16:34:23.177742
6968 16:34:23.178068 RX Delay -343 -> 252, step: 8
6969 16:34:23.185724 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6970 16:34:23.189448 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6971 16:34:23.192981 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6972 16:34:23.195795 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6973 16:34:23.202273 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6974 16:34:23.206054 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6975 16:34:23.209220 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6976 16:34:23.212358 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6977 16:34:23.219062 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6978 16:34:23.221994 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6979 16:34:23.225413 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6980 16:34:23.232079 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6981 16:34:23.235236 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6982 16:34:23.238418 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6983 16:34:23.242155 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6984 16:34:23.248511 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6985 16:34:23.248928 ==
6986 16:34:23.251752 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 16:34:23.254996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 16:34:23.255521 ==
6989 16:34:23.255856 DQS Delay:
6990 16:34:23.257953 DQS0 = 48, DQS1 = 52
6991 16:34:23.258368 DQM Delay:
6992 16:34:23.262168 DQM0 = 10, DQM1 = 10
6993 16:34:23.262683 DQ Delay:
6994 16:34:23.264667 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6995 16:34:23.268163 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6996 16:34:23.271960 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6997 16:34:23.274787 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6998 16:34:23.275210
6999 16:34:23.275536
7000 16:34:23.281494 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cb3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7001 16:34:23.284719 CH1 RK1: MR19=C0C, MR18=7CB3
7002 16:34:23.291273 CH1_RK1: MR19=0xC0C, MR18=0x7CB3, DQSOSC=387, MR23=63, INC=394, DEC=262
7003 16:34:23.294376 [RxdqsGatingPostProcess] freq 400
7004 16:34:23.301009 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7005 16:34:23.304183 best DQS0 dly(2T, 0.5T) = (0, 10)
7006 16:34:23.307457 best DQS1 dly(2T, 0.5T) = (0, 10)
7007 16:34:23.310654 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7008 16:34:23.313949 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7009 16:34:23.317778 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 16:34:23.318493 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 16:34:23.320811 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 16:34:23.324278 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 16:34:23.327787 Pre-setting of DQS Precalculation
7014 16:34:23.333736 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7015 16:34:23.340784 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7016 16:34:23.346999 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7017 16:34:23.347479
7018 16:34:23.347862
7019 16:34:23.350708 [Calibration Summary] 800 Mbps
7020 16:34:23.353578 CH 0, Rank 0
7021 16:34:23.354006 SW Impedance : PASS
7022 16:34:23.357206 DUTY Scan : NO K
7023 16:34:23.360512 ZQ Calibration : PASS
7024 16:34:23.361026 Jitter Meter : NO K
7025 16:34:23.363616 CBT Training : PASS
7026 16:34:23.364031 Write leveling : PASS
7027 16:34:23.366692 RX DQS gating : PASS
7028 16:34:23.370224 RX DQ/DQS(RDDQC) : PASS
7029 16:34:23.370639 TX DQ/DQS : PASS
7030 16:34:23.373315 RX DATLAT : PASS
7031 16:34:23.376838 RX DQ/DQS(Engine): PASS
7032 16:34:23.377252 TX OE : NO K
7033 16:34:23.380377 All Pass.
7034 16:34:23.380792
7035 16:34:23.381115 CH 0, Rank 1
7036 16:34:23.383708 SW Impedance : PASS
7037 16:34:23.384226 DUTY Scan : NO K
7038 16:34:23.386388 ZQ Calibration : PASS
7039 16:34:23.389842 Jitter Meter : NO K
7040 16:34:23.390258 CBT Training : PASS
7041 16:34:23.393446 Write leveling : NO K
7042 16:34:23.396589 RX DQS gating : PASS
7043 16:34:23.397020 RX DQ/DQS(RDDQC) : PASS
7044 16:34:23.399904 TX DQ/DQS : PASS
7045 16:34:23.403143 RX DATLAT : PASS
7046 16:34:23.403652 RX DQ/DQS(Engine): PASS
7047 16:34:23.406435 TX OE : NO K
7048 16:34:23.406897 All Pass.
7049 16:34:23.407226
7050 16:34:23.409590 CH 1, Rank 0
7051 16:34:23.410003 SW Impedance : PASS
7052 16:34:23.412921 DUTY Scan : NO K
7053 16:34:23.416246 ZQ Calibration : PASS
7054 16:34:23.416662 Jitter Meter : NO K
7055 16:34:23.419636 CBT Training : PASS
7056 16:34:23.422659 Write leveling : PASS
7057 16:34:23.423075 RX DQS gating : PASS
7058 16:34:23.425838 RX DQ/DQS(RDDQC) : PASS
7059 16:34:23.429515 TX DQ/DQS : PASS
7060 16:34:23.430067 RX DATLAT : PASS
7061 16:34:23.432635 RX DQ/DQS(Engine): PASS
7062 16:34:23.435699 TX OE : NO K
7063 16:34:23.436115 All Pass.
7064 16:34:23.436437
7065 16:34:23.436737 CH 1, Rank 1
7066 16:34:23.439426 SW Impedance : PASS
7067 16:34:23.442562 DUTY Scan : NO K
7068 16:34:23.443071 ZQ Calibration : PASS
7069 16:34:23.445734 Jitter Meter : NO K
7070 16:34:23.448900 CBT Training : PASS
7071 16:34:23.449370 Write leveling : NO K
7072 16:34:23.452693 RX DQS gating : PASS
7073 16:34:23.455671 RX DQ/DQS(RDDQC) : PASS
7074 16:34:23.456074 TX DQ/DQS : PASS
7075 16:34:23.458732 RX DATLAT : PASS
7076 16:34:23.459152 RX DQ/DQS(Engine): PASS
7077 16:34:23.462097 TX OE : NO K
7078 16:34:23.462652 All Pass.
7079 16:34:23.462987
7080 16:34:23.465936 DramC Write-DBI off
7081 16:34:23.469018 PER_BANK_REFRESH: Hybrid Mode
7082 16:34:23.469465 TX_TRACKING: ON
7083 16:34:23.478872 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7084 16:34:23.482594 [FAST_K] Save calibration result to emmc
7085 16:34:23.485689 dramc_set_vcore_voltage set vcore to 725000
7086 16:34:23.488374 Read voltage for 1600, 0
7087 16:34:23.488928 Vio18 = 0
7088 16:34:23.491887 Vcore = 725000
7089 16:34:23.492446 Vdram = 0
7090 16:34:23.492917 Vddq = 0
7091 16:34:23.493465 Vmddr = 0
7092 16:34:23.498503 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7093 16:34:23.504808 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7094 16:34:23.505228 MEM_TYPE=3, freq_sel=13
7095 16:34:23.508054 sv_algorithm_assistance_LP4_3733
7096 16:34:23.515278 ============ PULL DRAM RESETB DOWN ============
7097 16:34:23.518408 ========== PULL DRAM RESETB DOWN end =========
7098 16:34:23.521443 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7099 16:34:23.524849 ===================================
7100 16:34:23.528395 LPDDR4 DRAM CONFIGURATION
7101 16:34:23.531761 ===================================
7102 16:34:23.532179 EX_ROW_EN[0] = 0x0
7103 16:34:23.534835 EX_ROW_EN[1] = 0x0
7104 16:34:23.537801 LP4Y_EN = 0x0
7105 16:34:23.538229 WORK_FSP = 0x1
7106 16:34:23.541543 WL = 0x5
7107 16:34:23.541953 RL = 0x5
7108 16:34:23.544615 BL = 0x2
7109 16:34:23.545026 RPST = 0x0
7110 16:34:23.547611 RD_PRE = 0x0
7111 16:34:23.548027 WR_PRE = 0x1
7112 16:34:23.551306 WR_PST = 0x1
7113 16:34:23.551717 DBI_WR = 0x0
7114 16:34:23.554962 DBI_RD = 0x0
7115 16:34:23.555481 OTF = 0x1
7116 16:34:23.557831 ===================================
7117 16:34:23.561078 ===================================
7118 16:34:23.564230 ANA top config
7119 16:34:23.567513 ===================================
7120 16:34:23.570521 DLL_ASYNC_EN = 0
7121 16:34:23.570933 ALL_SLAVE_EN = 0
7122 16:34:23.573933 NEW_RANK_MODE = 1
7123 16:34:23.577610 DLL_IDLE_MODE = 1
7124 16:34:23.580765 LP45_APHY_COMB_EN = 1
7125 16:34:23.581180 TX_ODT_DIS = 0
7126 16:34:23.584019 NEW_8X_MODE = 1
7127 16:34:23.587451 ===================================
7128 16:34:23.590506 ===================================
7129 16:34:23.593752 data_rate = 3200
7130 16:34:23.597232 CKR = 1
7131 16:34:23.600318 DQ_P2S_RATIO = 8
7132 16:34:23.603513 ===================================
7133 16:34:23.606765 CA_P2S_RATIO = 8
7134 16:34:23.610208 DQ_CA_OPEN = 0
7135 16:34:23.610620 DQ_SEMI_OPEN = 0
7136 16:34:23.613613 CA_SEMI_OPEN = 0
7137 16:34:23.616785 CA_FULL_RATE = 0
7138 16:34:23.620089 DQ_CKDIV4_EN = 0
7139 16:34:23.623197 CA_CKDIV4_EN = 0
7140 16:34:23.627022 CA_PREDIV_EN = 0
7141 16:34:23.627435 PH8_DLY = 12
7142 16:34:23.630617 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7143 16:34:23.633475 DQ_AAMCK_DIV = 4
7144 16:34:23.636790 CA_AAMCK_DIV = 4
7145 16:34:23.639969 CA_ADMCK_DIV = 4
7146 16:34:23.643356 DQ_TRACK_CA_EN = 0
7147 16:34:23.646692 CA_PICK = 1600
7148 16:34:23.647117 CA_MCKIO = 1600
7149 16:34:23.649670 MCKIO_SEMI = 0
7150 16:34:23.653221 PLL_FREQ = 3068
7151 16:34:23.656237 DQ_UI_PI_RATIO = 32
7152 16:34:23.660020 CA_UI_PI_RATIO = 0
7153 16:34:23.663395 ===================================
7154 16:34:23.666472 ===================================
7155 16:34:23.669573 memory_type:LPDDR4
7156 16:34:23.669989 GP_NUM : 10
7157 16:34:23.673403 SRAM_EN : 1
7158 16:34:23.673921 MD32_EN : 0
7159 16:34:23.676358 ===================================
7160 16:34:23.679191 [ANA_INIT] >>>>>>>>>>>>>>
7161 16:34:23.682980 <<<<<< [CONFIGURE PHASE]: ANA_TX
7162 16:34:23.686397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7163 16:34:23.689422 ===================================
7164 16:34:23.692706 data_rate = 3200,PCW = 0X7600
7165 16:34:23.695746 ===================================
7166 16:34:23.698971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7167 16:34:23.706018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 16:34:23.709436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 16:34:23.715814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7170 16:34:23.718896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7171 16:34:23.722267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7172 16:34:23.722711 [ANA_INIT] flow start
7173 16:34:23.725606 [ANA_INIT] PLL >>>>>>>>
7174 16:34:23.728637 [ANA_INIT] PLL <<<<<<<<
7175 16:34:23.731829 [ANA_INIT] MIDPI >>>>>>>>
7176 16:34:23.732239 [ANA_INIT] MIDPI <<<<<<<<
7177 16:34:23.735213 [ANA_INIT] DLL >>>>>>>>
7178 16:34:23.738477 [ANA_INIT] DLL <<<<<<<<
7179 16:34:23.738896 [ANA_INIT] flow end
7180 16:34:23.742250 ============ LP4 DIFF to SE enter ============
7181 16:34:23.748729 ============ LP4 DIFF to SE exit ============
7182 16:34:23.749141 [ANA_INIT] <<<<<<<<<<<<<
7183 16:34:23.751854 [Flow] Enable top DCM control >>>>>
7184 16:34:23.754906 [Flow] Enable top DCM control <<<<<
7185 16:34:23.758012 Enable DLL master slave shuffle
7186 16:34:23.764826 ==============================================================
7187 16:34:23.767935 Gating Mode config
7188 16:34:23.771735 ==============================================================
7189 16:34:23.774756 Config description:
7190 16:34:23.784671 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7191 16:34:23.791081 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7192 16:34:23.794256 SELPH_MODE 0: By rank 1: By Phase
7193 16:34:23.800826 ==============================================================
7194 16:34:23.804560 GAT_TRACK_EN = 1
7195 16:34:23.807804 RX_GATING_MODE = 2
7196 16:34:23.811136 RX_GATING_TRACK_MODE = 2
7197 16:34:23.813984 SELPH_MODE = 1
7198 16:34:23.814609 PICG_EARLY_EN = 1
7199 16:34:23.817485 VALID_LAT_VALUE = 1
7200 16:34:23.824203 ==============================================================
7201 16:34:23.827496 Enter into Gating configuration >>>>
7202 16:34:23.830601 Exit from Gating configuration <<<<
7203 16:34:23.834160 Enter into DVFS_PRE_config >>>>>
7204 16:34:23.844226 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7205 16:34:23.847932 Exit from DVFS_PRE_config <<<<<
7206 16:34:23.850695 Enter into PICG configuration >>>>
7207 16:34:23.853956 Exit from PICG configuration <<<<
7208 16:34:23.856865 [RX_INPUT] configuration >>>>>
7209 16:34:23.860727 [RX_INPUT] configuration <<<<<
7210 16:34:23.866999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7211 16:34:23.870287 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7212 16:34:23.877431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7213 16:34:23.883410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7214 16:34:23.890207 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 16:34:23.896925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 16:34:23.899906 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7217 16:34:23.903821 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7218 16:34:23.907016 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7219 16:34:23.913420 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7220 16:34:23.916465 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7221 16:34:23.920191 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 16:34:23.923385 ===================================
7223 16:34:23.926171 LPDDR4 DRAM CONFIGURATION
7224 16:34:23.929481 ===================================
7225 16:34:23.929893 EX_ROW_EN[0] = 0x0
7226 16:34:23.933240 EX_ROW_EN[1] = 0x0
7227 16:34:23.936434 LP4Y_EN = 0x0
7228 16:34:23.936845 WORK_FSP = 0x1
7229 16:34:23.939457 WL = 0x5
7230 16:34:23.939897 RL = 0x5
7231 16:34:23.942822 BL = 0x2
7232 16:34:23.943268 RPST = 0x0
7233 16:34:23.946408 RD_PRE = 0x0
7234 16:34:23.946837 WR_PRE = 0x1
7235 16:34:23.949227 WR_PST = 0x1
7236 16:34:23.949676 DBI_WR = 0x0
7237 16:34:23.952598 DBI_RD = 0x0
7238 16:34:23.953004 OTF = 0x1
7239 16:34:23.955985 ===================================
7240 16:34:23.962856 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7241 16:34:23.965781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7242 16:34:23.969186 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 16:34:23.972838 ===================================
7244 16:34:23.975777 LPDDR4 DRAM CONFIGURATION
7245 16:34:23.979209 ===================================
7246 16:34:23.982436 EX_ROW_EN[0] = 0x10
7247 16:34:23.982942 EX_ROW_EN[1] = 0x0
7248 16:34:23.985551 LP4Y_EN = 0x0
7249 16:34:23.985964 WORK_FSP = 0x1
7250 16:34:23.989003 WL = 0x5
7251 16:34:23.989596 RL = 0x5
7252 16:34:23.991969 BL = 0x2
7253 16:34:23.992380 RPST = 0x0
7254 16:34:23.995460 RD_PRE = 0x0
7255 16:34:23.995869 WR_PRE = 0x1
7256 16:34:23.998644 WR_PST = 0x1
7257 16:34:23.999066 DBI_WR = 0x0
7258 16:34:24.001967 DBI_RD = 0x0
7259 16:34:24.002390 OTF = 0x1
7260 16:34:24.005721 ===================================
7261 16:34:24.012277 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7262 16:34:24.012827 ==
7263 16:34:24.015335 Dram Type= 6, Freq= 0, CH_0, rank 0
7264 16:34:24.022093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7265 16:34:24.022505 ==
7266 16:34:24.022825 [Duty_Offset_Calibration]
7267 16:34:24.025231 B0:2 B1:0 CA:4
7268 16:34:24.025679
7269 16:34:24.028559 [DutyScan_Calibration_Flow] k_type=0
7270 16:34:24.037232
7271 16:34:24.037781 ==CLK 0==
7272 16:34:24.040490 Final CLK duty delay cell = -4
7273 16:34:24.043597 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7274 16:34:24.047230 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7275 16:34:24.050684 [-4] AVG Duty = 4937%(X100)
7276 16:34:24.051104
7277 16:34:24.053805 CH0 CLK Duty spec in!! Max-Min= 187%
7278 16:34:24.057321 [DutyScan_Calibration_Flow] ====Done====
7279 16:34:24.057844
7280 16:34:24.060380 [DutyScan_Calibration_Flow] k_type=1
7281 16:34:24.077546
7282 16:34:24.078061 ==DQS 0 ==
7283 16:34:24.080466 Final DQS duty delay cell = 0
7284 16:34:24.084074 [0] MAX Duty = 5218%(X100), DQS PI = 38
7285 16:34:24.087311 [0] MIN Duty = 5062%(X100), DQS PI = 12
7286 16:34:24.090140 [0] AVG Duty = 5140%(X100)
7287 16:34:24.090648
7288 16:34:24.090979 ==DQS 1 ==
7289 16:34:24.093778 Final DQS duty delay cell = 0
7290 16:34:24.096826 [0] MAX Duty = 5156%(X100), DQS PI = 2
7291 16:34:24.100256 [0] MIN Duty = 4938%(X100), DQS PI = 58
7292 16:34:24.103545 [0] AVG Duty = 5047%(X100)
7293 16:34:24.103955
7294 16:34:24.107294 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7295 16:34:24.107706
7296 16:34:24.110395 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7297 16:34:24.113306 [DutyScan_Calibration_Flow] ====Done====
7298 16:34:24.113734
7299 16:34:24.116675 [DutyScan_Calibration_Flow] k_type=3
7300 16:34:24.134747
7301 16:34:24.135259 ==DQM 0 ==
7302 16:34:24.137779 Final DQM duty delay cell = 0
7303 16:34:24.140880 [0] MAX Duty = 5124%(X100), DQS PI = 22
7304 16:34:24.144647 [0] MIN Duty = 4844%(X100), DQS PI = 56
7305 16:34:24.147770 [0] AVG Duty = 4984%(X100)
7306 16:34:24.148229
7307 16:34:24.148553 ==DQM 1 ==
7308 16:34:24.150829 Final DQM duty delay cell = 0
7309 16:34:24.154439 [0] MAX Duty = 4969%(X100), DQS PI = 0
7310 16:34:24.157510 [0] MIN Duty = 4844%(X100), DQS PI = 12
7311 16:34:24.160801 [0] AVG Duty = 4906%(X100)
7312 16:34:24.161357
7313 16:34:24.163754 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7314 16:34:24.164325
7315 16:34:24.167686 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7316 16:34:24.170881 [DutyScan_Calibration_Flow] ====Done====
7317 16:34:24.171396
7318 16:34:24.174099 [DutyScan_Calibration_Flow] k_type=2
7319 16:34:24.191123
7320 16:34:24.191356 ==DQ 0 ==
7321 16:34:24.194463 Final DQ duty delay cell = 0
7322 16:34:24.197887 [0] MAX Duty = 5156%(X100), DQS PI = 22
7323 16:34:24.200834 [0] MIN Duty = 4938%(X100), DQS PI = 58
7324 16:34:24.201068 [0] AVG Duty = 5047%(X100)
7325 16:34:24.204365
7326 16:34:24.204530 ==DQ 1 ==
7327 16:34:24.207341 Final DQ duty delay cell = 0
7328 16:34:24.210891 [0] MAX Duty = 5187%(X100), DQS PI = 2
7329 16:34:24.214353 [0] MIN Duty = 4907%(X100), DQS PI = 34
7330 16:34:24.214499 [0] AVG Duty = 5047%(X100)
7331 16:34:24.217388
7332 16:34:24.221080 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7333 16:34:24.221230
7334 16:34:24.224392 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7335 16:34:24.227645 [DutyScan_Calibration_Flow] ====Done====
7336 16:34:24.227831 ==
7337 16:34:24.230800 Dram Type= 6, Freq= 0, CH_1, rank 0
7338 16:34:24.234190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7339 16:34:24.234363 ==
7340 16:34:24.237399 [Duty_Offset_Calibration]
7341 16:34:24.237574 B0:0 B1:-1 CA:3
7342 16:34:24.237704
7343 16:34:24.240542 [DutyScan_Calibration_Flow] k_type=0
7344 16:34:24.250387
7345 16:34:24.250504 ==CLK 0==
7346 16:34:24.254345 Final CLK duty delay cell = -4
7347 16:34:24.257300 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7348 16:34:24.260795 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7349 16:34:24.264084 [-4] AVG Duty = 4922%(X100)
7350 16:34:24.264210
7351 16:34:24.267399 CH1 CLK Duty spec in!! Max-Min= 156%
7352 16:34:24.270517 [DutyScan_Calibration_Flow] ====Done====
7353 16:34:24.270762
7354 16:34:24.273715 [DutyScan_Calibration_Flow] k_type=1
7355 16:34:24.290042
7356 16:34:24.290401 ==DQS 0 ==
7357 16:34:24.293224 Final DQS duty delay cell = 0
7358 16:34:24.296485 [0] MAX Duty = 5218%(X100), DQS PI = 28
7359 16:34:24.300201 [0] MIN Duty = 4907%(X100), DQS PI = 58
7360 16:34:24.303246 [0] AVG Duty = 5062%(X100)
7361 16:34:24.303664
7362 16:34:24.304002 ==DQS 1 ==
7363 16:34:24.306148 Final DQS duty delay cell = -4
7364 16:34:24.309556 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7365 16:34:24.312914 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7366 16:34:24.316296 [-4] AVG Duty = 4906%(X100)
7367 16:34:24.316710
7368 16:34:24.319326 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7369 16:34:24.319755
7370 16:34:24.322720 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7371 16:34:24.325870 [DutyScan_Calibration_Flow] ====Done====
7372 16:34:24.326209
7373 16:34:24.329126 [DutyScan_Calibration_Flow] k_type=3
7374 16:34:24.347349
7375 16:34:24.347726 ==DQM 0 ==
7376 16:34:24.350437 Final DQM duty delay cell = 0
7377 16:34:24.353684 [0] MAX Duty = 5062%(X100), DQS PI = 30
7378 16:34:24.357311 [0] MIN Duty = 4782%(X100), DQS PI = 38
7379 16:34:24.360253 [0] AVG Duty = 4922%(X100)
7380 16:34:24.360549
7381 16:34:24.360827 ==DQM 1 ==
7382 16:34:24.363751 Final DQM duty delay cell = 0
7383 16:34:24.367061 [0] MAX Duty = 4969%(X100), DQS PI = 30
7384 16:34:24.370123 [0] MIN Duty = 4813%(X100), DQS PI = 60
7385 16:34:24.373231 [0] AVG Duty = 4891%(X100)
7386 16:34:24.373685
7387 16:34:24.377364 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7388 16:34:24.377866
7389 16:34:24.380514 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7390 16:34:24.383606 [DutyScan_Calibration_Flow] ====Done====
7391 16:34:24.384023
7392 16:34:24.386952 [DutyScan_Calibration_Flow] k_type=2
7393 16:34:24.403307
7394 16:34:24.403805 ==DQ 0 ==
7395 16:34:24.406802 Final DQ duty delay cell = -4
7396 16:34:24.410126 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7397 16:34:24.413452 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7398 16:34:24.416415 [-4] AVG Duty = 4891%(X100)
7399 16:34:24.416883
7400 16:34:24.417423 ==DQ 1 ==
7401 16:34:24.419918 Final DQ duty delay cell = 0
7402 16:34:24.423236 [0] MAX Duty = 5031%(X100), DQS PI = 32
7403 16:34:24.426679 [0] MIN Duty = 4875%(X100), DQS PI = 52
7404 16:34:24.429790 [0] AVG Duty = 4953%(X100)
7405 16:34:24.430207
7406 16:34:24.433429 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7407 16:34:24.433844
7408 16:34:24.436155 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7409 16:34:24.439950 [DutyScan_Calibration_Flow] ====Done====
7410 16:34:24.443418 nWR fixed to 30
7411 16:34:24.446345 [ModeRegInit_LP4] CH0 RK0
7412 16:34:24.446909 [ModeRegInit_LP4] CH0 RK1
7413 16:34:24.450061 [ModeRegInit_LP4] CH1 RK0
7414 16:34:24.453236 [ModeRegInit_LP4] CH1 RK1
7415 16:34:24.453693 match AC timing 5
7416 16:34:24.459809 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7417 16:34:24.462958 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7418 16:34:24.466210 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7419 16:34:24.472620 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7420 16:34:24.476432 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7421 16:34:24.476744 [MiockJmeterHQA]
7422 16:34:24.476923
7423 16:34:24.479482 [DramcMiockJmeter] u1RxGatingPI = 0
7424 16:34:24.482643 0 : 4253, 4026
7425 16:34:24.482893 4 : 4255, 4027
7426 16:34:24.485702 8 : 4255, 4030
7427 16:34:24.485952 12 : 4363, 4137
7428 16:34:24.489363 16 : 4255, 4029
7429 16:34:24.489679 20 : 4253, 4027
7430 16:34:24.489877 24 : 4363, 4137
7431 16:34:24.492561 28 : 4252, 4027
7432 16:34:24.492876 32 : 4363, 4138
7433 16:34:24.495600 36 : 4250, 4026
7434 16:34:24.495973 40 : 4365, 4140
7435 16:34:24.499276 44 : 4250, 4027
7436 16:34:24.499547 48 : 4253, 4027
7437 16:34:24.502401 52 : 4249, 4027
7438 16:34:24.502773 56 : 4250, 4027
7439 16:34:24.505430 60 : 4363, 4140
7440 16:34:24.505833 64 : 4364, 4140
7441 16:34:24.506161 68 : 4250, 4026
7442 16:34:24.509434 72 : 4252, 4029
7443 16:34:24.509946 76 : 4361, 4137
7444 16:34:24.512462 80 : 4250, 4027
7445 16:34:24.512994 84 : 4362, 4140
7446 16:34:24.515462 88 : 4250, 4027
7447 16:34:24.515889 92 : 4250, 4027
7448 16:34:24.518714 96 : 4250, 2594
7449 16:34:24.519232 100 : 4250, 0
7450 16:34:24.519572 104 : 4250, 0
7451 16:34:24.522637 108 : 4250, 0
7452 16:34:24.523057 112 : 4250, 0
7453 16:34:24.523387 116 : 4252, 0
7454 16:34:24.525316 120 : 4361, 0
7455 16:34:24.525822 124 : 4250, 0
7456 16:34:24.529079 128 : 4250, 0
7457 16:34:24.529613 132 : 4366, 0
7458 16:34:24.529946 136 : 4361, 0
7459 16:34:24.531914 140 : 4250, 0
7460 16:34:24.532337 144 : 4360, 0
7461 16:34:24.535471 148 : 4250, 0
7462 16:34:24.535892 152 : 4250, 0
7463 16:34:24.536219 156 : 4250, 0
7464 16:34:24.538941 160 : 4250, 0
7465 16:34:24.539452 164 : 4250, 0
7466 16:34:24.542474 168 : 4360, 0
7467 16:34:24.542896 172 : 4365, 0
7468 16:34:24.543224 176 : 4250, 0
7469 16:34:24.545556 180 : 4250, 0
7470 16:34:24.545978 184 : 4252, 0
7471 16:34:24.546305 188 : 4364, 0
7472 16:34:24.548598 192 : 4250, 0
7473 16:34:24.549020 196 : 4250, 0
7474 16:34:24.551919 200 : 4361, 0
7475 16:34:24.552340 204 : 4250, 0
7476 16:34:24.552666 208 : 4250, 0
7477 16:34:24.555286 212 : 4250, 0
7478 16:34:24.555860 216 : 4254, 0
7479 16:34:24.558828 220 : 4360, 527
7480 16:34:24.559340 224 : 4250, 4006
7481 16:34:24.562017 228 : 4250, 4027
7482 16:34:24.562438 232 : 4250, 4027
7483 16:34:24.565460 236 : 4250, 4027
7484 16:34:24.565973 240 : 4252, 4029
7485 16:34:24.568243 244 : 4250, 4027
7486 16:34:24.568662 248 : 4361, 4138
7487 16:34:24.568989 252 : 4252, 4027
7488 16:34:24.571608 256 : 4250, 4027
7489 16:34:24.572118 260 : 4251, 4027
7490 16:34:24.574686 264 : 4361, 4138
7491 16:34:24.575106 268 : 4361, 4137
7492 16:34:24.578625 272 : 4250, 4027
7493 16:34:24.579139 276 : 4363, 4140
7494 16:34:24.581596 280 : 4250, 4027
7495 16:34:24.582017 284 : 4252, 4029
7496 16:34:24.585113 288 : 4250, 4026
7497 16:34:24.585776 292 : 4252, 4029
7498 16:34:24.588451 296 : 4250, 4027
7499 16:34:24.589245 300 : 4361, 4138
7500 16:34:24.591236 304 : 4250, 4027
7501 16:34:24.591647 308 : 4250, 4027
7502 16:34:24.594732 312 : 4250, 4027
7503 16:34:24.595260 316 : 4360, 4137
7504 16:34:24.595590 320 : 4361, 4137
7505 16:34:24.597976 324 : 4253, 4026
7506 16:34:24.598492 328 : 4250, 4027
7507 16:34:24.601740 332 : 4250, 3951
7508 16:34:24.602159 336 : 4250, 1594
7509 16:34:24.602484
7510 16:34:24.604871 MIOCK jitter meter ch=0
7511 16:34:24.605713
7512 16:34:24.608296 1T = (336-100) = 236 dly cells
7513 16:34:24.614220 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7514 16:34:24.614632 ==
7515 16:34:24.617579 Dram Type= 6, Freq= 0, CH_0, rank 0
7516 16:34:24.621118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 16:34:24.621678 ==
7518 16:34:24.627926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 16:34:24.631216 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 16:34:24.634174 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 16:34:24.640915 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 16:34:24.650009 [CA 0] Center 43 (13~73) winsize 61
7523 16:34:24.653353 [CA 1] Center 43 (13~73) winsize 61
7524 16:34:24.657193 [CA 2] Center 38 (9~67) winsize 59
7525 16:34:24.660327 [CA 3] Center 37 (8~67) winsize 60
7526 16:34:24.663737 [CA 4] Center 35 (6~65) winsize 60
7527 16:34:24.666990 [CA 5] Center 35 (5~66) winsize 62
7528 16:34:24.667494
7529 16:34:24.669972 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7530 16:34:24.670484
7531 16:34:24.672938 [CATrainingPosCal] consider 1 rank data
7532 16:34:24.676485 u2DelayCellTimex100 = 275/100 ps
7533 16:34:24.682881 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7534 16:34:24.686591 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7535 16:34:24.689908 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7536 16:34:24.692683 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7537 16:34:24.696339 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7538 16:34:24.699468 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7539 16:34:24.699873
7540 16:34:24.702577 CA PerBit enable=1, Macro0, CA PI delay=35
7541 16:34:24.702986
7542 16:34:24.705966 [CBTSetCACLKResult] CA Dly = 35
7543 16:34:24.709782 CS Dly: 11 (0~42)
7544 16:34:24.712806 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 16:34:24.715715 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 16:34:24.716124 ==
7547 16:34:24.718960 Dram Type= 6, Freq= 0, CH_0, rank 1
7548 16:34:24.725987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 16:34:24.726397 ==
7550 16:34:24.729486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 16:34:24.735586 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 16:34:24.738764 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 16:34:24.745637 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 16:34:24.753973 [CA 0] Center 44 (14~75) winsize 62
7555 16:34:24.757374 [CA 1] Center 44 (14~74) winsize 61
7556 16:34:24.760305 [CA 2] Center 39 (10~69) winsize 60
7557 16:34:24.763409 [CA 3] Center 39 (10~68) winsize 59
7558 16:34:24.766975 [CA 4] Center 37 (7~67) winsize 61
7559 16:34:24.770228 [CA 5] Center 36 (7~66) winsize 60
7560 16:34:24.770738
7561 16:34:24.773636 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7562 16:34:24.774050
7563 16:34:24.780630 [CATrainingPosCal] consider 2 rank data
7564 16:34:24.781169 u2DelayCellTimex100 = 275/100 ps
7565 16:34:24.786423 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7566 16:34:24.790463 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7567 16:34:24.793174 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7568 16:34:24.796503 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7569 16:34:24.800074 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7570 16:34:24.803342 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7571 16:34:24.803754
7572 16:34:24.806302 CA PerBit enable=1, Macro0, CA PI delay=36
7573 16:34:24.807051
7574 16:34:24.809858 [CBTSetCACLKResult] CA Dly = 36
7575 16:34:24.813362 CS Dly: 11 (0~43)
7576 16:34:24.816657 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 16:34:24.820006 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 16:34:24.820481
7579 16:34:24.823149 ----->DramcWriteLeveling(PI) begin...
7580 16:34:24.823563 ==
7581 16:34:24.826085 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 16:34:24.833167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 16:34:24.833739 ==
7584 16:34:24.836339 Write leveling (Byte 0): 34 => 34
7585 16:34:24.839624 Write leveling (Byte 1): 24 => 24
7586 16:34:24.842762 DramcWriteLeveling(PI) end<-----
7587 16:34:24.843179
7588 16:34:24.843495 ==
7589 16:34:24.845872 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 16:34:24.849133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 16:34:24.849594 ==
7592 16:34:24.852924 [Gating] SW mode calibration
7593 16:34:24.859067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7594 16:34:24.866111 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7595 16:34:24.868686 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 16:34:24.872503 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 16:34:24.878978 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7598 16:34:24.882225 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7599 16:34:24.885386 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7600 16:34:24.891762 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
7601 16:34:24.895574 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 16:34:24.898657 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 16:34:24.905171 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 16:34:24.908297 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 16:34:24.911822 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7606 16:34:24.918409 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7607 16:34:24.921436 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7608 16:34:24.924922 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7609 16:34:24.931689 1 5 24 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
7610 16:34:24.935278 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 16:34:24.938417 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 16:34:24.944830 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 16:34:24.948203 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7614 16:34:24.951394 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7615 16:34:24.957734 1 6 16 | B1->B0 | 2423 4646 | 1 0 | (0 0) (0 0)
7616 16:34:24.961107 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7617 16:34:24.964773 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 16:34:24.971347 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 16:34:24.974252 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 16:34:24.978058 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 16:34:24.984358 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7622 16:34:24.987831 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 16:34:24.990809 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7624 16:34:24.997991 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 16:34:25.001290 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7626 16:34:25.004239 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 16:34:25.011066 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 16:34:25.014132 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 16:34:25.017147 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 16:34:25.023587 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 16:34:25.027090 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 16:34:25.030525 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 16:34:25.036796 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 16:34:25.040095 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 16:34:25.043432 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 16:34:25.050231 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 16:34:25.053715 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7638 16:34:25.057192 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7639 16:34:25.060465 Total UI for P1: 0, mck2ui 16
7640 16:34:25.063625 best dqsien dly found for B0: ( 1, 9, 8)
7641 16:34:25.069872 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7642 16:34:25.073363 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 16:34:25.076610 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 16:34:25.080041 Total UI for P1: 0, mck2ui 16
7645 16:34:25.082800 best dqsien dly found for B1: ( 1, 9, 20)
7646 16:34:25.086249 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7647 16:34:25.089401 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7648 16:34:25.089812
7649 16:34:25.096044 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7650 16:34:25.100147 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7651 16:34:25.100658 [Gating] SW calibration Done
7652 16:34:25.102676 ==
7653 16:34:25.106231 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 16:34:25.109113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 16:34:25.109526 ==
7656 16:34:25.109838 RX Vref Scan: 0
7657 16:34:25.110132
7658 16:34:25.112384 RX Vref 0 -> 0, step: 1
7659 16:34:25.112702
7660 16:34:25.116164 RX Delay 0 -> 252, step: 8
7661 16:34:25.119363 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7662 16:34:25.122531 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7663 16:34:25.129161 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7664 16:34:25.132160 iDelay=192, Bit 3, Center 127 (80 ~ 175) 96
7665 16:34:25.135952 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7666 16:34:25.139163 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7667 16:34:25.142201 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7668 16:34:25.145368 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7669 16:34:25.151958 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7670 16:34:25.155356 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7671 16:34:25.159141 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7672 16:34:25.162135 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7673 16:34:25.168880 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7674 16:34:25.171776 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7675 16:34:25.175105 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7676 16:34:25.178662 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7677 16:34:25.179094 ==
7678 16:34:25.182115 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 16:34:25.188662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 16:34:25.189160 ==
7681 16:34:25.189534 DQS Delay:
7682 16:34:25.191581 DQS0 = 0, DQS1 = 0
7683 16:34:25.191992 DQM Delay:
7684 16:34:25.192310 DQM0 = 131, DQM1 = 127
7685 16:34:25.195115 DQ Delay:
7686 16:34:25.198420 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7687 16:34:25.201464 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7688 16:34:25.205143 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7689 16:34:25.208456 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7690 16:34:25.208862
7691 16:34:25.209178
7692 16:34:25.209542 ==
7693 16:34:25.211432 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 16:34:25.218004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 16:34:25.218411 ==
7696 16:34:25.218727
7697 16:34:25.219017
7698 16:34:25.219295 TX Vref Scan disable
7699 16:34:25.221166 == TX Byte 0 ==
7700 16:34:25.224797 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7701 16:34:25.228027 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7702 16:34:25.231749 == TX Byte 1 ==
7703 16:34:25.234981 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7704 16:34:25.241109 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7705 16:34:25.241538 ==
7706 16:34:25.244122 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 16:34:25.247992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 16:34:25.248408 ==
7709 16:34:25.261559
7710 16:34:25.264400 TX Vref early break, caculate TX vref
7711 16:34:25.268130 TX Vref=16, minBit 8, minWin=22, winSum=373
7712 16:34:25.271075 TX Vref=18, minBit 8, minWin=22, winSum=377
7713 16:34:25.275150 TX Vref=20, minBit 7, minWin=23, winSum=392
7714 16:34:25.277649 TX Vref=22, minBit 1, minWin=24, winSum=398
7715 16:34:25.281075 TX Vref=24, minBit 0, minWin=25, winSum=406
7716 16:34:25.287256 TX Vref=26, minBit 1, minWin=25, winSum=412
7717 16:34:25.290368 TX Vref=28, minBit 1, minWin=25, winSum=414
7718 16:34:25.294227 TX Vref=30, minBit 2, minWin=25, winSum=415
7719 16:34:25.297233 TX Vref=32, minBit 4, minWin=24, winSum=403
7720 16:34:25.300510 TX Vref=34, minBit 2, minWin=23, winSum=393
7721 16:34:25.307431 [TxChooseVref] Worse bit 2, Min win 25, Win sum 415, Final Vref 30
7722 16:34:25.307858
7723 16:34:25.310536 Final TX Range 0 Vref 30
7724 16:34:25.310955
7725 16:34:25.311338 ==
7726 16:34:25.313718 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 16:34:25.317242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 16:34:25.317568 ==
7729 16:34:25.317802
7730 16:34:25.318017
7731 16:34:25.320506 TX Vref Scan disable
7732 16:34:25.327019 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7733 16:34:25.327280 == TX Byte 0 ==
7734 16:34:25.330477 u2DelayCellOfst[0]=10 cells (3 PI)
7735 16:34:25.333579 u2DelayCellOfst[1]=17 cells (5 PI)
7736 16:34:25.336997 u2DelayCellOfst[2]=10 cells (3 PI)
7737 16:34:25.340243 u2DelayCellOfst[3]=10 cells (3 PI)
7738 16:34:25.343435 u2DelayCellOfst[4]=7 cells (2 PI)
7739 16:34:25.346668 u2DelayCellOfst[5]=0 cells (0 PI)
7740 16:34:25.349609 u2DelayCellOfst[6]=14 cells (4 PI)
7741 16:34:25.353375 u2DelayCellOfst[7]=17 cells (5 PI)
7742 16:34:25.356772 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7743 16:34:25.360002 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7744 16:34:25.363136 == TX Byte 1 ==
7745 16:34:25.366263 u2DelayCellOfst[8]=0 cells (0 PI)
7746 16:34:25.370101 u2DelayCellOfst[9]=0 cells (0 PI)
7747 16:34:25.373412 u2DelayCellOfst[10]=3 cells (1 PI)
7748 16:34:25.376626 u2DelayCellOfst[11]=0 cells (0 PI)
7749 16:34:25.376998 u2DelayCellOfst[12]=7 cells (2 PI)
7750 16:34:25.379906 u2DelayCellOfst[13]=7 cells (2 PI)
7751 16:34:25.383430 u2DelayCellOfst[14]=10 cells (3 PI)
7752 16:34:25.387090 u2DelayCellOfst[15]=7 cells (2 PI)
7753 16:34:25.393215 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7754 16:34:25.396078 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7755 16:34:25.396488 DramC Write-DBI on
7756 16:34:25.396806 ==
7757 16:34:25.399821 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 16:34:25.406113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 16:34:25.406727 ==
7760 16:34:25.407069
7761 16:34:25.407367
7762 16:34:25.409344 TX Vref Scan disable
7763 16:34:25.409754 == TX Byte 0 ==
7764 16:34:25.416016 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7765 16:34:25.416562 == TX Byte 1 ==
7766 16:34:25.419199 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7767 16:34:25.422466 DramC Write-DBI off
7768 16:34:25.422877
7769 16:34:25.423193 [DATLAT]
7770 16:34:25.425717 Freq=1600, CH0 RK0
7771 16:34:25.426139
7772 16:34:25.426513 DATLAT Default: 0xf
7773 16:34:25.429561 0, 0xFFFF, sum = 0
7774 16:34:25.429979 1, 0xFFFF, sum = 0
7775 16:34:25.432790 2, 0xFFFF, sum = 0
7776 16:34:25.433223 3, 0xFFFF, sum = 0
7777 16:34:25.436055 4, 0xFFFF, sum = 0
7778 16:34:25.436471 5, 0xFFFF, sum = 0
7779 16:34:25.439159 6, 0xFFFF, sum = 0
7780 16:34:25.439590 7, 0xFFFF, sum = 0
7781 16:34:25.442179 8, 0xFFFF, sum = 0
7782 16:34:25.445777 9, 0xFFFF, sum = 0
7783 16:34:25.446197 10, 0xFFFF, sum = 0
7784 16:34:25.448954 11, 0xFFFF, sum = 0
7785 16:34:25.449418 12, 0xFFFF, sum = 0
7786 16:34:25.452514 13, 0xFFFF, sum = 0
7787 16:34:25.452937 14, 0x0, sum = 1
7788 16:34:25.455746 15, 0x0, sum = 2
7789 16:34:25.456167 16, 0x0, sum = 3
7790 16:34:25.459179 17, 0x0, sum = 4
7791 16:34:25.459688 best_step = 15
7792 16:34:25.460011
7793 16:34:25.460311 ==
7794 16:34:25.462212 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 16:34:25.465326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 16:34:25.468962 ==
7797 16:34:25.469521 RX Vref Scan: 1
7798 16:34:25.469855
7799 16:34:25.472628 Set Vref Range= 24 -> 127
7800 16:34:25.473142
7801 16:34:25.475762 RX Vref 24 -> 127, step: 1
7802 16:34:25.476269
7803 16:34:25.476594 RX Delay 11 -> 252, step: 4
7804 16:34:25.476900
7805 16:34:25.478520 Set Vref, RX VrefLevel [Byte0]: 24
7806 16:34:25.481863 [Byte1]: 24
7807 16:34:25.485422
7808 16:34:25.485836 Set Vref, RX VrefLevel [Byte0]: 25
7809 16:34:25.489421 [Byte1]: 25
7810 16:34:25.493067
7811 16:34:25.493529 Set Vref, RX VrefLevel [Byte0]: 26
7812 16:34:25.496963 [Byte1]: 26
7813 16:34:25.501146
7814 16:34:25.501684 Set Vref, RX VrefLevel [Byte0]: 27
7815 16:34:25.504587 [Byte1]: 27
7816 16:34:25.508333
7817 16:34:25.508744 Set Vref, RX VrefLevel [Byte0]: 28
7818 16:34:25.511823 [Byte1]: 28
7819 16:34:25.516514
7820 16:34:25.517035 Set Vref, RX VrefLevel [Byte0]: 29
7821 16:34:25.519779 [Byte1]: 29
7822 16:34:25.523715
7823 16:34:25.524124 Set Vref, RX VrefLevel [Byte0]: 30
7824 16:34:25.526825 [Byte1]: 30
7825 16:34:25.531554
7826 16:34:25.531960 Set Vref, RX VrefLevel [Byte0]: 31
7827 16:34:25.534413 [Byte1]: 31
7828 16:34:25.538943
7829 16:34:25.539351 Set Vref, RX VrefLevel [Byte0]: 32
7830 16:34:25.542159 [Byte1]: 32
7831 16:34:25.546464
7832 16:34:25.546871 Set Vref, RX VrefLevel [Byte0]: 33
7833 16:34:25.550145 [Byte1]: 33
7834 16:34:25.554066
7835 16:34:25.554609 Set Vref, RX VrefLevel [Byte0]: 34
7836 16:34:25.557562 [Byte1]: 34
7837 16:34:25.561970
7838 16:34:25.562553 Set Vref, RX VrefLevel [Byte0]: 35
7839 16:34:25.564866 [Byte1]: 35
7840 16:34:25.569189
7841 16:34:25.569636 Set Vref, RX VrefLevel [Byte0]: 36
7842 16:34:25.572634 [Byte1]: 36
7843 16:34:25.577123
7844 16:34:25.577570 Set Vref, RX VrefLevel [Byte0]: 37
7845 16:34:25.580566 [Byte1]: 37
7846 16:34:25.584964
7847 16:34:25.585415 Set Vref, RX VrefLevel [Byte0]: 38
7848 16:34:25.588218 [Byte1]: 38
7849 16:34:25.592647
7850 16:34:25.593154 Set Vref, RX VrefLevel [Byte0]: 39
7851 16:34:25.595612 [Byte1]: 39
7852 16:34:25.600101
7853 16:34:25.600506 Set Vref, RX VrefLevel [Byte0]: 40
7854 16:34:25.603314 [Byte1]: 40
7855 16:34:25.607652
7856 16:34:25.608076 Set Vref, RX VrefLevel [Byte0]: 41
7857 16:34:25.610696 [Byte1]: 41
7858 16:34:25.615082
7859 16:34:25.615608 Set Vref, RX VrefLevel [Byte0]: 42
7860 16:34:25.618345 [Byte1]: 42
7861 16:34:25.623049
7862 16:34:25.623457 Set Vref, RX VrefLevel [Byte0]: 43
7863 16:34:25.626143 [Byte1]: 43
7864 16:34:25.630310
7865 16:34:25.630839 Set Vref, RX VrefLevel [Byte0]: 44
7866 16:34:25.634080 [Byte1]: 44
7867 16:34:25.638100
7868 16:34:25.638545 Set Vref, RX VrefLevel [Byte0]: 45
7869 16:34:25.640997 [Byte1]: 45
7870 16:34:25.645686
7871 16:34:25.646194 Set Vref, RX VrefLevel [Byte0]: 46
7872 16:34:25.648651 [Byte1]: 46
7873 16:34:25.653217
7874 16:34:25.653657 Set Vref, RX VrefLevel [Byte0]: 47
7875 16:34:25.656334 [Byte1]: 47
7876 16:34:25.660774
7877 16:34:25.661188 Set Vref, RX VrefLevel [Byte0]: 48
7878 16:34:25.664174 [Byte1]: 48
7879 16:34:25.668627
7880 16:34:25.669295 Set Vref, RX VrefLevel [Byte0]: 49
7881 16:34:25.671602 [Byte1]: 49
7882 16:34:25.676080
7883 16:34:25.676593 Set Vref, RX VrefLevel [Byte0]: 50
7884 16:34:25.679087 [Byte1]: 50
7885 16:34:25.683629
7886 16:34:25.684074 Set Vref, RX VrefLevel [Byte0]: 51
7887 16:34:25.686852 [Byte1]: 51
7888 16:34:25.691299
7889 16:34:25.691706 Set Vref, RX VrefLevel [Byte0]: 52
7890 16:34:25.694197 [Byte1]: 52
7891 16:34:25.698982
7892 16:34:25.699549 Set Vref, RX VrefLevel [Byte0]: 53
7893 16:34:25.701958 [Byte1]: 53
7894 16:34:25.706427
7895 16:34:25.707035 Set Vref, RX VrefLevel [Byte0]: 54
7896 16:34:25.709929 [Byte1]: 54
7897 16:34:25.713870
7898 16:34:25.714452 Set Vref, RX VrefLevel [Byte0]: 55
7899 16:34:25.717245 [Byte1]: 55
7900 16:34:25.721610
7901 16:34:25.722027 Set Vref, RX VrefLevel [Byte0]: 56
7902 16:34:25.724636 [Byte1]: 56
7903 16:34:25.729244
7904 16:34:25.729703 Set Vref, RX VrefLevel [Byte0]: 57
7905 16:34:25.732774 [Byte1]: 57
7906 16:34:25.736660
7907 16:34:25.737071 Set Vref, RX VrefLevel [Byte0]: 58
7908 16:34:25.739901 [Byte1]: 58
7909 16:34:25.744747
7910 16:34:25.745347 Set Vref, RX VrefLevel [Byte0]: 59
7911 16:34:25.748079 [Byte1]: 59
7912 16:34:25.752292
7913 16:34:25.752785 Set Vref, RX VrefLevel [Byte0]: 60
7914 16:34:25.755794 [Byte1]: 60
7915 16:34:25.760247
7916 16:34:25.760764 Set Vref, RX VrefLevel [Byte0]: 61
7917 16:34:25.763336 [Byte1]: 61
7918 16:34:25.767437
7919 16:34:25.767981 Set Vref, RX VrefLevel [Byte0]: 62
7920 16:34:25.770719 [Byte1]: 62
7921 16:34:25.775009
7922 16:34:25.775419 Set Vref, RX VrefLevel [Byte0]: 63
7923 16:34:25.778095 [Byte1]: 63
7924 16:34:25.782501
7925 16:34:25.783021 Set Vref, RX VrefLevel [Byte0]: 64
7926 16:34:25.785851 [Byte1]: 64
7927 16:34:25.790459
7928 16:34:25.790871 Set Vref, RX VrefLevel [Byte0]: 65
7929 16:34:25.793530 [Byte1]: 65
7930 16:34:25.798024
7931 16:34:25.798652 Set Vref, RX VrefLevel [Byte0]: 66
7932 16:34:25.801024 [Byte1]: 66
7933 16:34:25.805629
7934 16:34:25.806230 Set Vref, RX VrefLevel [Byte0]: 67
7935 16:34:25.808524 [Byte1]: 67
7936 16:34:25.812968
7937 16:34:25.813424 Set Vref, RX VrefLevel [Byte0]: 68
7938 16:34:25.816100 [Byte1]: 68
7939 16:34:25.820842
7940 16:34:25.821426 Set Vref, RX VrefLevel [Byte0]: 69
7941 16:34:25.824012 [Byte1]: 69
7942 16:34:25.828188
7943 16:34:25.828603 Set Vref, RX VrefLevel [Byte0]: 70
7944 16:34:25.831279 [Byte1]: 70
7945 16:34:25.836105
7946 16:34:25.836525 Set Vref, RX VrefLevel [Byte0]: 71
7947 16:34:25.839022 [Byte1]: 71
7948 16:34:25.843724
7949 16:34:25.844171 Set Vref, RX VrefLevel [Byte0]: 72
7950 16:34:25.846682 [Byte1]: 72
7951 16:34:25.851091
7952 16:34:25.851507 Final RX Vref Byte 0 = 56 to rank0
7953 16:34:25.854282 Final RX Vref Byte 1 = 58 to rank0
7954 16:34:25.857568 Final RX Vref Byte 0 = 56 to rank1
7955 16:34:25.861072 Final RX Vref Byte 1 = 58 to rank1==
7956 16:34:25.863888 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 16:34:25.870677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 16:34:25.870922 ==
7959 16:34:25.871101 DQS Delay:
7960 16:34:25.873653 DQS0 = 0, DQS1 = 0
7961 16:34:25.873854 DQM Delay:
7962 16:34:25.877159 DQM0 = 128, DQM1 = 124
7963 16:34:25.877375 DQ Delay:
7964 16:34:25.880247 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7965 16:34:25.883444 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7966 16:34:25.886631 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7967 16:34:25.890304 DQ12 =132, DQ13 =128, DQ14 =132, DQ15 =130
7968 16:34:25.890482
7969 16:34:25.890597
7970 16:34:25.890692
7971 16:34:25.893241 [DramC_TX_OE_Calibration] TA2
7972 16:34:25.896401 Original DQ_B0 (3 6) =30, OEN = 27
7973 16:34:25.900197 Original DQ_B1 (3 6) =30, OEN = 27
7974 16:34:25.903289 24, 0x0, End_B0=24 End_B1=24
7975 16:34:25.906769 25, 0x0, End_B0=25 End_B1=25
7976 16:34:25.906938 26, 0x0, End_B0=26 End_B1=26
7977 16:34:25.909722 27, 0x0, End_B0=27 End_B1=27
7978 16:34:25.912992 28, 0x0, End_B0=28 End_B1=28
7979 16:34:25.916197 29, 0x0, End_B0=29 End_B1=29
7980 16:34:25.919376 30, 0x0, End_B0=30 End_B1=30
7981 16:34:25.919587 31, 0x4141, End_B0=30 End_B1=30
7982 16:34:25.923271 Byte0 end_step=30 best_step=27
7983 16:34:25.926476 Byte1 end_step=30 best_step=27
7984 16:34:25.929651 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 16:34:25.962677 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 16:34:25.962944
7987 16:34:25.963118
7988 16:34:25.963290 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7989 16:34:25.963459 CH0 RK0: MR19=303, MR18=1916
7990 16:34:25.963629 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7991 16:34:25.963825
7992 16:34:25.964015 ----->DramcWriteLeveling(PI) begin...
7993 16:34:25.964207 ==
7994 16:34:25.964393 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 16:34:25.964570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 16:34:25.964745 ==
7997 16:34:25.965696 Write leveling (Byte 0): 34 => 34
7998 16:34:25.965899 Write leveling (Byte 1): 25 => 25
7999 16:34:25.968681 DramcWriteLeveling(PI) end<-----
8000 16:34:25.968891
8001 16:34:25.969079 ==
8002 16:34:25.971812 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 16:34:25.978677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 16:34:25.978846 ==
8005 16:34:25.982019 [Gating] SW mode calibration
8006 16:34:25.988552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 16:34:25.992095 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 16:34:25.998159 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 16:34:26.001914 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 16:34:26.005086 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8011 16:34:26.011495 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8012 16:34:26.014651 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8013 16:34:26.017694 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8014 16:34:26.024917 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 16:34:26.028141 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 16:34:26.031335 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 16:34:26.037759 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 16:34:26.041037 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8019 16:34:26.044762 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8020 16:34:26.051322 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
8021 16:34:26.054462 1 5 20 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
8022 16:34:26.057870 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 16:34:26.064061 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 16:34:26.067880 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 16:34:26.070976 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8026 16:34:26.077316 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8027 16:34:26.080433 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8028 16:34:26.084096 1 6 16 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8029 16:34:26.090666 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 16:34:26.094019 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 16:34:26.096820 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 16:34:26.103897 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 16:34:26.106692 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 16:34:26.110076 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 16:34:26.117018 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 16:34:26.120105 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 16:34:26.123281 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 16:34:26.129621 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8039 16:34:26.133630 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 16:34:26.136759 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 16:34:26.143230 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 16:34:26.146176 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 16:34:26.149942 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 16:34:26.156759 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 16:34:26.160028 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 16:34:26.163214 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 16:34:26.170030 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 16:34:26.172741 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 16:34:26.176344 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 16:34:26.183326 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 16:34:26.186317 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 16:34:26.190078 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 16:34:26.192806 Total UI for P1: 0, mck2ui 16
8054 16:34:26.195849 best dqsien dly found for B0: ( 1, 9, 8)
8055 16:34:26.202308 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 16:34:26.205989 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 16:34:26.209185 Total UI for P1: 0, mck2ui 16
8058 16:34:26.212271 best dqsien dly found for B1: ( 1, 9, 18)
8059 16:34:26.216194 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8060 16:34:26.218967 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8061 16:34:26.219376
8062 16:34:26.222622 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8063 16:34:26.229081 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8064 16:34:26.229934 [Gating] SW calibration Done
8065 16:34:26.230437 ==
8066 16:34:26.232093 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 16:34:26.238900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 16:34:26.239345 ==
8069 16:34:26.239784 RX Vref Scan: 0
8070 16:34:26.240189
8071 16:34:26.242044 RX Vref 0 -> 0, step: 1
8072 16:34:26.242475
8073 16:34:26.245130 RX Delay 0 -> 252, step: 8
8074 16:34:26.249046 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8075 16:34:26.252163 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8076 16:34:26.255207 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8077 16:34:26.261577 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8078 16:34:26.265199 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8079 16:34:26.268395 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8080 16:34:26.271632 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8081 16:34:26.274808 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8082 16:34:26.281622 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8083 16:34:26.284349 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8084 16:34:26.288084 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8085 16:34:26.291609 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8086 16:34:26.294632 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8087 16:34:26.301034 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8088 16:34:26.304220 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8089 16:34:26.307390 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8090 16:34:26.307516 ==
8091 16:34:26.310945 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 16:34:26.314169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 16:34:26.317315 ==
8094 16:34:26.317485 DQS Delay:
8095 16:34:26.317604 DQS0 = 0, DQS1 = 0
8096 16:34:26.320857 DQM Delay:
8097 16:34:26.321046 DQM0 = 131, DQM1 = 127
8098 16:34:26.323862 DQ Delay:
8099 16:34:26.327337 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8100 16:34:26.330974 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8101 16:34:26.334024 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8102 16:34:26.337095 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8103 16:34:26.337281
8104 16:34:26.337379
8105 16:34:26.337456 ==
8106 16:34:26.340777 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 16:34:26.343582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 16:34:26.346991 ==
8109 16:34:26.347156
8110 16:34:26.347274
8111 16:34:26.347381 TX Vref Scan disable
8112 16:34:26.350338 == TX Byte 0 ==
8113 16:34:26.353410 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8114 16:34:26.356687 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8115 16:34:26.360017 == TX Byte 1 ==
8116 16:34:26.363337 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8117 16:34:26.370409 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8118 16:34:26.370588 ==
8119 16:34:26.373652 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 16:34:26.376872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 16:34:26.377017 ==
8122 16:34:26.389967
8123 16:34:26.393572 TX Vref early break, caculate TX vref
8124 16:34:26.396582 TX Vref=16, minBit 8, minWin=23, winSum=383
8125 16:34:26.399694 TX Vref=18, minBit 11, minWin=23, winSum=384
8126 16:34:26.403563 TX Vref=20, minBit 4, minWin=24, winSum=395
8127 16:34:26.406379 TX Vref=22, minBit 2, minWin=24, winSum=397
8128 16:34:26.413363 TX Vref=24, minBit 1, minWin=25, winSum=410
8129 16:34:26.416616 TX Vref=26, minBit 3, minWin=25, winSum=414
8130 16:34:26.419643 TX Vref=28, minBit 8, minWin=25, winSum=416
8131 16:34:26.422617 TX Vref=30, minBit 1, minWin=25, winSum=409
8132 16:34:26.426601 TX Vref=32, minBit 0, minWin=24, winSum=401
8133 16:34:26.429722 TX Vref=34, minBit 1, minWin=24, winSum=394
8134 16:34:26.436654 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
8135 16:34:26.437213
8136 16:34:26.439521 Final TX Range 0 Vref 28
8137 16:34:26.439931
8138 16:34:26.440248 ==
8139 16:34:26.442653 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 16:34:26.445733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 16:34:26.446144 ==
8142 16:34:26.446499
8143 16:34:26.449573
8144 16:34:26.450028 TX Vref Scan disable
8145 16:34:26.455995 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8146 16:34:26.456424 == TX Byte 0 ==
8147 16:34:26.459365 u2DelayCellOfst[0]=10 cells (3 PI)
8148 16:34:26.462607 u2DelayCellOfst[1]=14 cells (4 PI)
8149 16:34:26.466176 u2DelayCellOfst[2]=7 cells (2 PI)
8150 16:34:26.469171 u2DelayCellOfst[3]=10 cells (3 PI)
8151 16:34:26.472313 u2DelayCellOfst[4]=7 cells (2 PI)
8152 16:34:26.475539 u2DelayCellOfst[5]=0 cells (0 PI)
8153 16:34:26.479658 u2DelayCellOfst[6]=14 cells (4 PI)
8154 16:34:26.482554 u2DelayCellOfst[7]=14 cells (4 PI)
8155 16:34:26.485553 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8156 16:34:26.489308 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8157 16:34:26.492398 == TX Byte 1 ==
8158 16:34:26.495267 u2DelayCellOfst[8]=0 cells (0 PI)
8159 16:34:26.498940 u2DelayCellOfst[9]=0 cells (0 PI)
8160 16:34:26.502078 u2DelayCellOfst[10]=7 cells (2 PI)
8161 16:34:26.505188 u2DelayCellOfst[11]=3 cells (1 PI)
8162 16:34:26.508674 u2DelayCellOfst[12]=7 cells (2 PI)
8163 16:34:26.509198 u2DelayCellOfst[13]=7 cells (2 PI)
8164 16:34:26.511800 u2DelayCellOfst[14]=14 cells (4 PI)
8165 16:34:26.514945 u2DelayCellOfst[15]=7 cells (2 PI)
8166 16:34:26.521976 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8167 16:34:26.525572 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8168 16:34:26.525981 DramC Write-DBI on
8169 16:34:26.528157 ==
8170 16:34:26.531583 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 16:34:26.534813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 16:34:26.535224 ==
8173 16:34:26.535543
8174 16:34:26.535839
8175 16:34:26.538073 TX Vref Scan disable
8176 16:34:26.538481 == TX Byte 0 ==
8177 16:34:26.544678 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8178 16:34:26.545087 == TX Byte 1 ==
8179 16:34:26.548834 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8180 16:34:26.551484 DramC Write-DBI off
8181 16:34:26.551998
8182 16:34:26.552393 [DATLAT]
8183 16:34:26.554495 Freq=1600, CH0 RK1
8184 16:34:26.554903
8185 16:34:26.555218 DATLAT Default: 0xf
8186 16:34:26.557753 0, 0xFFFF, sum = 0
8187 16:34:26.558187 1, 0xFFFF, sum = 0
8188 16:34:26.561825 2, 0xFFFF, sum = 0
8189 16:34:26.564563 3, 0xFFFF, sum = 0
8190 16:34:26.564985 4, 0xFFFF, sum = 0
8191 16:34:26.568526 5, 0xFFFF, sum = 0
8192 16:34:26.569039 6, 0xFFFF, sum = 0
8193 16:34:26.571090 7, 0xFFFF, sum = 0
8194 16:34:26.571649 8, 0xFFFF, sum = 0
8195 16:34:26.574477 9, 0xFFFF, sum = 0
8196 16:34:26.574916 10, 0xFFFF, sum = 0
8197 16:34:26.577668 11, 0xFFFF, sum = 0
8198 16:34:26.578240 12, 0xFFFF, sum = 0
8199 16:34:26.580912 13, 0xFFFF, sum = 0
8200 16:34:26.581494 14, 0x0, sum = 1
8201 16:34:26.584042 15, 0x0, sum = 2
8202 16:34:26.584479 16, 0x0, sum = 3
8203 16:34:26.587206 17, 0x0, sum = 4
8204 16:34:26.587633 best_step = 15
8205 16:34:26.587957
8206 16:34:26.588274 ==
8207 16:34:26.590735 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 16:34:26.597031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 16:34:26.597510 ==
8210 16:34:26.597843 RX Vref Scan: 0
8211 16:34:26.598146
8212 16:34:26.600786 RX Vref 0 -> 0, step: 1
8213 16:34:26.601200
8214 16:34:26.604325 RX Delay 11 -> 252, step: 4
8215 16:34:26.607455 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8216 16:34:26.610637 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8217 16:34:26.613736 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8218 16:34:26.620577 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8219 16:34:26.623809 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8220 16:34:26.627235 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8221 16:34:26.630176 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8222 16:34:26.633764 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8223 16:34:26.640286 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8224 16:34:26.643677 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8225 16:34:26.647181 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8226 16:34:26.650196 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8227 16:34:26.657444 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8228 16:34:26.660068 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8229 16:34:26.663048 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8230 16:34:26.666716 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8231 16:34:26.667137 ==
8232 16:34:26.670010 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 16:34:26.676496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 16:34:26.677012 ==
8235 16:34:26.677382 DQS Delay:
8236 16:34:26.677697 DQS0 = 0, DQS1 = 0
8237 16:34:26.679911 DQM Delay:
8238 16:34:26.680326 DQM0 = 128, DQM1 = 124
8239 16:34:26.683747 DQ Delay:
8240 16:34:26.686431 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8241 16:34:26.689902 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8242 16:34:26.693404 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8243 16:34:26.696306 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8244 16:34:26.696725
8245 16:34:26.697052
8246 16:34:26.697404
8247 16:34:26.699380 [DramC_TX_OE_Calibration] TA2
8248 16:34:26.702516 Original DQ_B0 (3 6) =30, OEN = 27
8249 16:34:26.706610 Original DQ_B1 (3 6) =30, OEN = 27
8250 16:34:26.709034 24, 0x0, End_B0=24 End_B1=24
8251 16:34:26.712849 25, 0x0, End_B0=25 End_B1=25
8252 16:34:26.713322 26, 0x0, End_B0=26 End_B1=26
8253 16:34:26.715940 27, 0x0, End_B0=27 End_B1=27
8254 16:34:26.718987 28, 0x0, End_B0=28 End_B1=28
8255 16:34:26.722304 29, 0x0, End_B0=29 End_B1=29
8256 16:34:26.722726 30, 0x0, End_B0=30 End_B1=30
8257 16:34:26.725757 31, 0x4141, End_B0=30 End_B1=30
8258 16:34:26.728930 Byte0 end_step=30 best_step=27
8259 16:34:26.732159 Byte1 end_step=30 best_step=27
8260 16:34:26.736473 Byte0 TX OE(2T, 0.5T) = (3, 3)
8261 16:34:26.739250 Byte1 TX OE(2T, 0.5T) = (3, 3)
8262 16:34:26.739662
8263 16:34:26.739980
8264 16:34:26.745345 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8265 16:34:26.749608 CH0 RK1: MR19=303, MR18=1210
8266 16:34:26.755393 CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15
8267 16:34:26.758474 [RxdqsGatingPostProcess] freq 1600
8268 16:34:26.765648 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8269 16:34:26.766152 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 16:34:26.768722 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 16:34:26.771842 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 16:34:26.775123 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 16:34:26.778452 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 16:34:26.781565 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 16:34:26.784873 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 16:34:26.788805 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 16:34:26.792122 Pre-setting of DQS Precalculation
8278 16:34:26.794996 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8279 16:34:26.798127 ==
8280 16:34:26.801732 Dram Type= 6, Freq= 0, CH_1, rank 0
8281 16:34:26.804565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 16:34:26.805079 ==
8283 16:34:26.807920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 16:34:26.814461 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 16:34:26.818050 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 16:34:26.824314 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 16:34:26.832963 [CA 0] Center 42 (13~72) winsize 60
8288 16:34:26.836353 [CA 1] Center 42 (12~72) winsize 61
8289 16:34:26.839286 [CA 2] Center 38 (9~68) winsize 60
8290 16:34:26.842626 [CA 3] Center 37 (8~67) winsize 60
8291 16:34:26.845925 [CA 4] Center 38 (8~68) winsize 61
8292 16:34:26.849898 [CA 5] Center 37 (7~67) winsize 61
8293 16:34:26.850415
8294 16:34:26.852834 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8295 16:34:26.853243
8296 16:34:26.859112 [CATrainingPosCal] consider 1 rank data
8297 16:34:26.859546 u2DelayCellTimex100 = 275/100 ps
8298 16:34:26.865920 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8299 16:34:26.869338 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8300 16:34:26.872157 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8301 16:34:26.875420 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8302 16:34:26.878847 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8303 16:34:26.882107 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8304 16:34:26.882521
8305 16:34:26.885502 CA PerBit enable=1, Macro0, CA PI delay=37
8306 16:34:26.885963
8307 16:34:26.888402 [CBTSetCACLKResult] CA Dly = 37
8308 16:34:26.892343 CS Dly: 8 (0~39)
8309 16:34:26.895357 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 16:34:26.898398 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 16:34:26.898855 ==
8312 16:34:26.902070 Dram Type= 6, Freq= 0, CH_1, rank 1
8313 16:34:26.908325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 16:34:26.908761 ==
8315 16:34:26.912319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 16:34:26.918427 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 16:34:26.922053 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 16:34:26.928563 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 16:34:26.936284 [CA 0] Center 42 (12~72) winsize 61
8320 16:34:26.939269 [CA 1] Center 42 (13~72) winsize 60
8321 16:34:26.942166 [CA 2] Center 38 (9~68) winsize 60
8322 16:34:26.945836 [CA 3] Center 37 (7~67) winsize 61
8323 16:34:26.949079 [CA 4] Center 37 (8~67) winsize 60
8324 16:34:26.952102 [CA 5] Center 37 (7~67) winsize 61
8325 16:34:26.952514
8326 16:34:26.955732 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 16:34:26.956213
8328 16:34:26.958677 [CATrainingPosCal] consider 2 rank data
8329 16:34:26.962223 u2DelayCellTimex100 = 275/100 ps
8330 16:34:26.968885 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8331 16:34:26.972137 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8332 16:34:26.975081 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8333 16:34:26.978213 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8334 16:34:26.981458 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8335 16:34:26.984958 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8336 16:34:26.985135
8337 16:34:26.988210 CA PerBit enable=1, Macro0, CA PI delay=37
8338 16:34:26.988359
8339 16:34:26.991349 [CBTSetCACLKResult] CA Dly = 37
8340 16:34:26.995153 CS Dly: 9 (0~42)
8341 16:34:26.997908 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 16:34:27.001471 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 16:34:27.001571
8344 16:34:27.004770 ----->DramcWriteLeveling(PI) begin...
8345 16:34:27.004946 ==
8346 16:34:27.008696 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 16:34:27.014820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 16:34:27.015010 ==
8349 16:34:27.018015 Write leveling (Byte 0): 23 => 23
8350 16:34:27.021449 Write leveling (Byte 1): 27 => 27
8351 16:34:27.021549 DramcWriteLeveling(PI) end<-----
8352 16:34:27.024584
8353 16:34:27.024769 ==
8354 16:34:27.027493 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 16:34:27.031074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 16:34:27.031207 ==
8357 16:34:27.034824 [Gating] SW mode calibration
8358 16:34:27.040887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8359 16:34:27.044952 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8360 16:34:27.050639 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 16:34:27.054367 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 16:34:27.057564 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 16:34:27.064847 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
8364 16:34:27.068172 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 16:34:27.070849 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 16:34:27.077551 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 16:34:27.080727 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 16:34:27.083862 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 16:34:27.090947 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 16:34:27.093879 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 16:34:27.097072 1 5 12 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 1)
8372 16:34:27.103966 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8373 16:34:27.107018 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 16:34:27.110655 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 16:34:27.116995 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 16:34:27.120454 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 16:34:27.124338 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 16:34:27.130239 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 16:34:27.134235 1 6 12 | B1->B0 | 2b2b 4141 | 0 1 | (0 0) (0 0)
8380 16:34:27.137592 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 16:34:27.143712 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 16:34:27.146903 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 16:34:27.150035 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 16:34:27.157089 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 16:34:27.159908 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 16:34:27.163430 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 16:34:27.170527 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8388 16:34:27.173741 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 16:34:27.176648 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 16:34:27.183122 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 16:34:27.186447 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 16:34:27.190068 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 16:34:27.196935 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 16:34:27.199842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 16:34:27.202880 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 16:34:27.209860 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 16:34:27.212879 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 16:34:27.215982 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 16:34:27.223099 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 16:34:27.226395 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 16:34:27.229387 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 16:34:27.236365 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8403 16:34:27.239660 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8404 16:34:27.243076 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8405 16:34:27.245973 Total UI for P1: 0, mck2ui 16
8406 16:34:27.248819 best dqsien dly found for B0: ( 1, 9, 10)
8407 16:34:27.255792 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 16:34:27.256214 Total UI for P1: 0, mck2ui 16
8409 16:34:27.262240 best dqsien dly found for B1: ( 1, 9, 14)
8410 16:34:27.265625 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8411 16:34:27.269235 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8412 16:34:27.269682
8413 16:34:27.272269 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8414 16:34:27.275405 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8415 16:34:27.278586 [Gating] SW calibration Done
8416 16:34:27.279005 ==
8417 16:34:27.281716 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 16:34:27.285101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 16:34:27.285568 ==
8420 16:34:27.288715 RX Vref Scan: 0
8421 16:34:27.289132
8422 16:34:27.291746 RX Vref 0 -> 0, step: 1
8423 16:34:27.292163
8424 16:34:27.292489 RX Delay 0 -> 252, step: 8
8425 16:34:27.298127 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8426 16:34:27.301842 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8427 16:34:27.304674 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8428 16:34:27.308383 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8429 16:34:27.311723 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8430 16:34:27.317932 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8431 16:34:27.321095 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8432 16:34:27.324342 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8433 16:34:27.327657 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8434 16:34:27.331427 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8435 16:34:27.337696 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8436 16:34:27.341046 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8437 16:34:27.344665 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8438 16:34:27.347949 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8439 16:34:27.354180 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8440 16:34:27.357789 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8441 16:34:27.358234 ==
8442 16:34:27.361142 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 16:34:27.364490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 16:34:27.365129 ==
8445 16:34:27.367840 DQS Delay:
8446 16:34:27.368258 DQS0 = 0, DQS1 = 0
8447 16:34:27.368583 DQM Delay:
8448 16:34:27.370931 DQM0 = 134, DQM1 = 129
8449 16:34:27.371353 DQ Delay:
8450 16:34:27.374070 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8451 16:34:27.377140 DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =131
8452 16:34:27.383903 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8453 16:34:27.387020 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8454 16:34:27.387495
8455 16:34:27.387826
8456 16:34:27.388133 ==
8457 16:34:27.390825 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 16:34:27.393860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 16:34:27.394283 ==
8460 16:34:27.394667
8461 16:34:27.394975
8462 16:34:27.397193 TX Vref Scan disable
8463 16:34:27.400439 == TX Byte 0 ==
8464 16:34:27.404000 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8465 16:34:27.406942 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8466 16:34:27.410018 == TX Byte 1 ==
8467 16:34:27.413367 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8468 16:34:27.416925 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 16:34:27.417529 ==
8470 16:34:27.420076 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 16:34:27.423698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 16:34:27.426858 ==
8473 16:34:27.438284
8474 16:34:27.441497 TX Vref early break, caculate TX vref
8475 16:34:27.444521 TX Vref=16, minBit 8, minWin=21, winSum=368
8476 16:34:27.448454 TX Vref=18, minBit 9, minWin=22, winSum=379
8477 16:34:27.451533 TX Vref=20, minBit 8, minWin=23, winSum=386
8478 16:34:27.454886 TX Vref=22, minBit 8, minWin=23, winSum=394
8479 16:34:27.457908 TX Vref=24, minBit 8, minWin=24, winSum=409
8480 16:34:27.464131 TX Vref=26, minBit 9, minWin=24, winSum=411
8481 16:34:27.467770 TX Vref=28, minBit 9, minWin=25, winSum=419
8482 16:34:27.470931 TX Vref=30, minBit 0, minWin=25, winSum=413
8483 16:34:27.474148 TX Vref=32, minBit 9, minWin=24, winSum=405
8484 16:34:27.477219 TX Vref=34, minBit 9, minWin=22, winSum=394
8485 16:34:27.484185 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8486 16:34:27.484485
8487 16:34:27.487345 Final TX Range 0 Vref 28
8488 16:34:27.487644
8489 16:34:27.487877 ==
8490 16:34:27.490852 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 16:34:27.493952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 16:34:27.494262 ==
8493 16:34:27.494496
8494 16:34:27.494717
8495 16:34:27.497460 TX Vref Scan disable
8496 16:34:27.503962 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8497 16:34:27.504339 == TX Byte 0 ==
8498 16:34:27.507563 u2DelayCellOfst[0]=14 cells (4 PI)
8499 16:34:27.510837 u2DelayCellOfst[1]=10 cells (3 PI)
8500 16:34:27.514218 u2DelayCellOfst[2]=0 cells (0 PI)
8501 16:34:27.517119 u2DelayCellOfst[3]=7 cells (2 PI)
8502 16:34:27.520873 u2DelayCellOfst[4]=10 cells (3 PI)
8503 16:34:27.523759 u2DelayCellOfst[5]=14 cells (4 PI)
8504 16:34:27.527180 u2DelayCellOfst[6]=17 cells (5 PI)
8505 16:34:27.530523 u2DelayCellOfst[7]=7 cells (2 PI)
8506 16:34:27.533971 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8507 16:34:27.537434 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8508 16:34:27.540321 == TX Byte 1 ==
8509 16:34:27.544067 u2DelayCellOfst[8]=0 cells (0 PI)
8510 16:34:27.546851 u2DelayCellOfst[9]=3 cells (1 PI)
8511 16:34:27.547268 u2DelayCellOfst[10]=10 cells (3 PI)
8512 16:34:27.550376 u2DelayCellOfst[11]=7 cells (2 PI)
8513 16:34:27.553770 u2DelayCellOfst[12]=14 cells (4 PI)
8514 16:34:27.556859 u2DelayCellOfst[13]=14 cells (4 PI)
8515 16:34:27.560430 u2DelayCellOfst[14]=17 cells (5 PI)
8516 16:34:27.563650 u2DelayCellOfst[15]=17 cells (5 PI)
8517 16:34:27.570322 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8518 16:34:27.573577 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 16:34:27.574109 DramC Write-DBI on
8520 16:34:27.576977 ==
8521 16:34:27.577415 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 16:34:27.583512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 16:34:27.583935 ==
8524 16:34:27.584262
8525 16:34:27.584757
8526 16:34:27.585149 TX Vref Scan disable
8527 16:34:27.587224 == TX Byte 0 ==
8528 16:34:27.590613 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8529 16:34:27.593907 == TX Byte 1 ==
8530 16:34:27.597648 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8531 16:34:27.600509 DramC Write-DBI off
8532 16:34:27.600922
8533 16:34:27.601387 [DATLAT]
8534 16:34:27.601827 Freq=1600, CH1 RK0
8535 16:34:27.602277
8536 16:34:27.604018 DATLAT Default: 0xf
8537 16:34:27.607375 0, 0xFFFF, sum = 0
8538 16:34:27.607917 1, 0xFFFF, sum = 0
8539 16:34:27.610553 2, 0xFFFF, sum = 0
8540 16:34:27.610979 3, 0xFFFF, sum = 0
8541 16:34:27.613898 4, 0xFFFF, sum = 0
8542 16:34:27.614378 5, 0xFFFF, sum = 0
8543 16:34:27.617068 6, 0xFFFF, sum = 0
8544 16:34:27.617595 7, 0xFFFF, sum = 0
8545 16:34:27.620270 8, 0xFFFF, sum = 0
8546 16:34:27.620690 9, 0xFFFF, sum = 0
8547 16:34:27.623546 10, 0xFFFF, sum = 0
8548 16:34:27.623965 11, 0xFFFF, sum = 0
8549 16:34:27.626917 12, 0xFFFF, sum = 0
8550 16:34:27.627451 13, 0xFFFF, sum = 0
8551 16:34:27.629924 14, 0x0, sum = 1
8552 16:34:27.630364 15, 0x0, sum = 2
8553 16:34:27.633641 16, 0x0, sum = 3
8554 16:34:27.634096 17, 0x0, sum = 4
8555 16:34:27.636759 best_step = 15
8556 16:34:27.637173
8557 16:34:27.637562 ==
8558 16:34:27.640163 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 16:34:27.643432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 16:34:27.643852 ==
8561 16:34:27.646640 RX Vref Scan: 1
8562 16:34:27.647053
8563 16:34:27.647378 Set Vref Range= 24 -> 127
8564 16:34:27.649619
8565 16:34:27.650029 RX Vref 24 -> 127, step: 1
8566 16:34:27.650353
8567 16:34:27.653055 RX Delay 11 -> 252, step: 4
8568 16:34:27.653509
8569 16:34:27.656840 Set Vref, RX VrefLevel [Byte0]: 24
8570 16:34:27.659927 [Byte1]: 24
8571 16:34:27.660343
8572 16:34:27.663118 Set Vref, RX VrefLevel [Byte0]: 25
8573 16:34:27.666125 [Byte1]: 25
8574 16:34:27.670435
8575 16:34:27.670979 Set Vref, RX VrefLevel [Byte0]: 26
8576 16:34:27.673827 [Byte1]: 26
8577 16:34:27.677992
8578 16:34:27.678494 Set Vref, RX VrefLevel [Byte0]: 27
8579 16:34:27.681000 [Byte1]: 27
8580 16:34:27.685234
8581 16:34:27.685692 Set Vref, RX VrefLevel [Byte0]: 28
8582 16:34:27.689001 [Byte1]: 28
8583 16:34:27.693040
8584 16:34:27.693600 Set Vref, RX VrefLevel [Byte0]: 29
8585 16:34:27.696112 [Byte1]: 29
8586 16:34:27.700695
8587 16:34:27.701103 Set Vref, RX VrefLevel [Byte0]: 30
8588 16:34:27.703741 [Byte1]: 30
8589 16:34:27.707942
8590 16:34:27.708477 Set Vref, RX VrefLevel [Byte0]: 31
8591 16:34:27.711791 [Byte1]: 31
8592 16:34:27.716596
8593 16:34:27.717013 Set Vref, RX VrefLevel [Byte0]: 32
8594 16:34:27.719295 [Byte1]: 32
8595 16:34:27.723966
8596 16:34:27.724473 Set Vref, RX VrefLevel [Byte0]: 33
8597 16:34:27.727205 [Byte1]: 33
8598 16:34:27.731367
8599 16:34:27.731786 Set Vref, RX VrefLevel [Byte0]: 34
8600 16:34:27.734537 [Byte1]: 34
8601 16:34:27.738998
8602 16:34:27.739414 Set Vref, RX VrefLevel [Byte0]: 35
8603 16:34:27.742160 [Byte1]: 35
8604 16:34:27.746571
8605 16:34:27.747061 Set Vref, RX VrefLevel [Byte0]: 36
8606 16:34:27.749741 [Byte1]: 36
8607 16:34:27.753832
8608 16:34:27.754311 Set Vref, RX VrefLevel [Byte0]: 37
8609 16:34:27.757340 [Byte1]: 37
8610 16:34:27.761765
8611 16:34:27.762219 Set Vref, RX VrefLevel [Byte0]: 38
8612 16:34:27.765049 [Byte1]: 38
8613 16:34:27.769421
8614 16:34:27.769838 Set Vref, RX VrefLevel [Byte0]: 39
8615 16:34:27.772429 [Byte1]: 39
8616 16:34:27.776711
8617 16:34:27.777125 Set Vref, RX VrefLevel [Byte0]: 40
8618 16:34:27.780319 [Byte1]: 40
8619 16:34:27.784425
8620 16:34:27.784869 Set Vref, RX VrefLevel [Byte0]: 41
8621 16:34:27.787737 [Byte1]: 41
8622 16:34:27.792311
8623 16:34:27.792829 Set Vref, RX VrefLevel [Byte0]: 42
8624 16:34:27.795587 [Byte1]: 42
8625 16:34:27.799395
8626 16:34:27.799806 Set Vref, RX VrefLevel [Byte0]: 43
8627 16:34:27.803152 [Byte1]: 43
8628 16:34:27.807584
8629 16:34:27.808100 Set Vref, RX VrefLevel [Byte0]: 44
8630 16:34:27.810617 [Byte1]: 44
8631 16:34:27.814898
8632 16:34:27.815319 Set Vref, RX VrefLevel [Byte0]: 45
8633 16:34:27.817966 [Byte1]: 45
8634 16:34:27.822292
8635 16:34:27.822731 Set Vref, RX VrefLevel [Byte0]: 46
8636 16:34:27.825988 [Byte1]: 46
8637 16:34:27.830285
8638 16:34:27.830693 Set Vref, RX VrefLevel [Byte0]: 47
8639 16:34:27.833580 [Byte1]: 47
8640 16:34:27.837990
8641 16:34:27.838396 Set Vref, RX VrefLevel [Byte0]: 48
8642 16:34:27.841350 [Byte1]: 48
8643 16:34:27.845327
8644 16:34:27.845895 Set Vref, RX VrefLevel [Byte0]: 49
8645 16:34:27.849126 [Byte1]: 49
8646 16:34:27.852909
8647 16:34:27.853473 Set Vref, RX VrefLevel [Byte0]: 50
8648 16:34:27.856468 [Byte1]: 50
8649 16:34:27.860395
8650 16:34:27.860801 Set Vref, RX VrefLevel [Byte0]: 51
8651 16:34:27.864046 [Byte1]: 51
8652 16:34:27.868574
8653 16:34:27.869132 Set Vref, RX VrefLevel [Byte0]: 52
8654 16:34:27.871374 [Byte1]: 52
8655 16:34:27.875924
8656 16:34:27.876438 Set Vref, RX VrefLevel [Byte0]: 53
8657 16:34:27.879244 [Byte1]: 53
8658 16:34:27.883659
8659 16:34:27.884272 Set Vref, RX VrefLevel [Byte0]: 54
8660 16:34:27.886801 [Byte1]: 54
8661 16:34:27.891138
8662 16:34:27.891646 Set Vref, RX VrefLevel [Byte0]: 55
8663 16:34:27.894106 [Byte1]: 55
8664 16:34:27.898809
8665 16:34:27.899219 Set Vref, RX VrefLevel [Byte0]: 56
8666 16:34:27.901739 [Byte1]: 56
8667 16:34:27.906221
8668 16:34:27.906628 Set Vref, RX VrefLevel [Byte0]: 57
8669 16:34:27.909306 [Byte1]: 57
8670 16:34:27.914215
8671 16:34:27.914727 Set Vref, RX VrefLevel [Byte0]: 58
8672 16:34:27.917062 [Byte1]: 58
8673 16:34:27.921815
8674 16:34:27.922383 Set Vref, RX VrefLevel [Byte0]: 59
8675 16:34:27.924641 [Byte1]: 59
8676 16:34:27.929072
8677 16:34:27.929768 Set Vref, RX VrefLevel [Byte0]: 60
8678 16:34:27.932835 [Byte1]: 60
8679 16:34:27.936912
8680 16:34:27.937485 Set Vref, RX VrefLevel [Byte0]: 61
8681 16:34:27.940254 [Byte1]: 61
8682 16:34:27.944605
8683 16:34:27.945023 Set Vref, RX VrefLevel [Byte0]: 62
8684 16:34:27.947692 [Byte1]: 62
8685 16:34:27.951704
8686 16:34:27.952120 Set Vref, RX VrefLevel [Byte0]: 63
8687 16:34:27.955472 [Byte1]: 63
8688 16:34:27.959360
8689 16:34:27.963287 Set Vref, RX VrefLevel [Byte0]: 64
8690 16:34:27.963922 [Byte1]: 64
8691 16:34:27.967634
8692 16:34:27.968145 Set Vref, RX VrefLevel [Byte0]: 65
8693 16:34:27.970587 [Byte1]: 65
8694 16:34:27.974982
8695 16:34:27.975491 Set Vref, RX VrefLevel [Byte0]: 66
8696 16:34:27.977922 [Byte1]: 66
8697 16:34:27.982525
8698 16:34:27.982938 Set Vref, RX VrefLevel [Byte0]: 67
8699 16:34:27.985722 [Byte1]: 67
8700 16:34:27.989978
8701 16:34:27.990422 Set Vref, RX VrefLevel [Byte0]: 68
8702 16:34:27.993436 [Byte1]: 68
8703 16:34:27.997459
8704 16:34:27.997868 Set Vref, RX VrefLevel [Byte0]: 69
8705 16:34:28.000640 [Byte1]: 69
8706 16:34:28.005237
8707 16:34:28.005731 Set Vref, RX VrefLevel [Byte0]: 70
8708 16:34:28.008339 [Byte1]: 70
8709 16:34:28.012833
8710 16:34:28.013452 Set Vref, RX VrefLevel [Byte0]: 71
8711 16:34:28.015766 [Byte1]: 71
8712 16:34:28.020449
8713 16:34:28.020863 Set Vref, RX VrefLevel [Byte0]: 72
8714 16:34:28.023467 [Byte1]: 72
8715 16:34:28.027767
8716 16:34:28.028318 Final RX Vref Byte 0 = 54 to rank0
8717 16:34:28.031467 Final RX Vref Byte 1 = 63 to rank0
8718 16:34:28.034666 Final RX Vref Byte 0 = 54 to rank1
8719 16:34:28.037934 Final RX Vref Byte 1 = 63 to rank1==
8720 16:34:28.041069 Dram Type= 6, Freq= 0, CH_1, rank 0
8721 16:34:28.047883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 16:34:28.048297 ==
8723 16:34:28.048620 DQS Delay:
8724 16:34:28.051437 DQS0 = 0, DQS1 = 0
8725 16:34:28.051942 DQM Delay:
8726 16:34:28.052270 DQM0 = 132, DQM1 = 128
8727 16:34:28.054232 DQ Delay:
8728 16:34:28.057421 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =130
8729 16:34:28.060656 DQ4 =126, DQ5 =144, DQ6 =146, DQ7 =126
8730 16:34:28.064579 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8731 16:34:28.067458 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8732 16:34:28.067946
8733 16:34:28.068268
8734 16:34:28.068566
8735 16:34:28.070772 [DramC_TX_OE_Calibration] TA2
8736 16:34:28.073928 Original DQ_B0 (3 6) =30, OEN = 27
8737 16:34:28.077060 Original DQ_B1 (3 6) =30, OEN = 27
8738 16:34:28.080883 24, 0x0, End_B0=24 End_B1=24
8739 16:34:28.084155 25, 0x0, End_B0=25 End_B1=25
8740 16:34:28.084576 26, 0x0, End_B0=26 End_B1=26
8741 16:34:28.087358 27, 0x0, End_B0=27 End_B1=27
8742 16:34:28.090286 28, 0x0, End_B0=28 End_B1=28
8743 16:34:28.093836 29, 0x0, End_B0=29 End_B1=29
8744 16:34:28.094252 30, 0x0, End_B0=30 End_B1=30
8745 16:34:28.096885 31, 0x4545, End_B0=30 End_B1=30
8746 16:34:28.100839 Byte0 end_step=30 best_step=27
8747 16:34:28.103729 Byte1 end_step=30 best_step=27
8748 16:34:28.106763 Byte0 TX OE(2T, 0.5T) = (3, 3)
8749 16:34:28.110354 Byte1 TX OE(2T, 0.5T) = (3, 3)
8750 16:34:28.110821
8751 16:34:28.111333
8752 16:34:28.116795 [DQSOSCAuto] RK0, (LSB)MR18= 0x1019, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
8753 16:34:28.120489 CH1 RK0: MR19=303, MR18=1019
8754 16:34:28.126967 CH1_RK0: MR19=0x303, MR18=0x1019, DQSOSC=397, MR23=63, INC=23, DEC=15
8755 16:34:28.127490
8756 16:34:28.129734 ----->DramcWriteLeveling(PI) begin...
8757 16:34:28.130174 ==
8758 16:34:28.133218 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 16:34:28.136400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 16:34:28.136838 ==
8761 16:34:28.140032 Write leveling (Byte 0): 23 => 23
8762 16:34:28.142941 Write leveling (Byte 1): 26 => 26
8763 16:34:28.146627 DramcWriteLeveling(PI) end<-----
8764 16:34:28.147141
8765 16:34:28.147463 ==
8766 16:34:28.149379 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 16:34:28.156730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 16:34:28.157242 ==
8769 16:34:28.157607 [Gating] SW mode calibration
8770 16:34:28.165980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8771 16:34:28.169638 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8772 16:34:28.176030 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 16:34:28.179245 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8774 16:34:28.183285 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8775 16:34:28.189364 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8776 16:34:28.192515 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 16:34:28.195729 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 16:34:28.202638 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 16:34:28.205653 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 16:34:28.208848 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 16:34:28.215735 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8782 16:34:28.218720 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8783 16:34:28.221753 1 5 12 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8784 16:34:28.228959 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 16:34:28.231674 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 16:34:28.235536 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 16:34:28.241623 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 16:34:28.244873 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 16:34:28.248236 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8790 16:34:28.254953 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8791 16:34:28.258095 1 6 12 | B1->B0 | 2726 4646 | 1 0 | (0 0) (0 0)
8792 16:34:28.261978 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 16:34:28.268302 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 16:34:28.271185 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 16:34:28.275278 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 16:34:28.281487 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 16:34:28.284807 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8798 16:34:28.287640 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8799 16:34:28.294561 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8800 16:34:28.297700 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 16:34:28.300859 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 16:34:28.307744 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 16:34:28.310885 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 16:34:28.314004 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 16:34:28.321031 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 16:34:28.324344 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 16:34:28.327505 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 16:34:28.334205 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 16:34:28.337053 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 16:34:28.340843 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 16:34:28.346727 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 16:34:28.350496 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 16:34:28.353910 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8814 16:34:28.360257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 16:34:28.364083 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8816 16:34:28.366867 Total UI for P1: 0, mck2ui 16
8817 16:34:28.370126 best dqsien dly found for B0: ( 1, 9, 6)
8818 16:34:28.373361 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8819 16:34:28.379887 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 16:34:28.380314 Total UI for P1: 0, mck2ui 16
8821 16:34:28.386941 best dqsien dly found for B1: ( 1, 9, 12)
8822 16:34:28.390145 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8823 16:34:28.393208 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8824 16:34:28.393766
8825 16:34:28.396330 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8826 16:34:28.399659 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8827 16:34:28.403008 [Gating] SW calibration Done
8828 16:34:28.403446 ==
8829 16:34:28.406002 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 16:34:28.409329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 16:34:28.409753 ==
8832 16:34:28.412902 RX Vref Scan: 0
8833 16:34:28.413374
8834 16:34:28.413715 RX Vref 0 -> 0, step: 1
8835 16:34:28.415977
8836 16:34:28.416449 RX Delay 0 -> 252, step: 8
8837 16:34:28.419158 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8838 16:34:28.426287 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8839 16:34:28.429428 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8840 16:34:28.432725 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8841 16:34:28.436114 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8842 16:34:28.439266 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8843 16:34:28.445819 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8844 16:34:28.449400 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8845 16:34:28.452175 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8846 16:34:28.455814 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8847 16:34:28.462280 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8848 16:34:28.465601 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8849 16:34:28.468693 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8850 16:34:28.471816 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8851 16:34:28.475414 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8852 16:34:28.481578 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8853 16:34:28.481988 ==
8854 16:34:28.484941 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 16:34:28.488463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 16:34:28.488884 ==
8857 16:34:28.489202 DQS Delay:
8858 16:34:28.491885 DQS0 = 0, DQS1 = 0
8859 16:34:28.492293 DQM Delay:
8860 16:34:28.494944 DQM0 = 133, DQM1 = 130
8861 16:34:28.495410 DQ Delay:
8862 16:34:28.498605 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8863 16:34:28.501328 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8864 16:34:28.505198 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8865 16:34:28.511619 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8866 16:34:28.512042
8867 16:34:28.512370
8868 16:34:28.512676 ==
8869 16:34:28.514953 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 16:34:28.518628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 16:34:28.519066 ==
8872 16:34:28.519611
8873 16:34:28.519940
8874 16:34:28.521731 TX Vref Scan disable
8875 16:34:28.522152 == TX Byte 0 ==
8876 16:34:28.528249 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8877 16:34:28.531235 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8878 16:34:28.531658 == TX Byte 1 ==
8879 16:34:28.538020 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8880 16:34:28.541610 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8881 16:34:28.542128 ==
8882 16:34:28.544911 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 16:34:28.547877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 16:34:28.548507 ==
8885 16:34:28.562798
8886 16:34:28.566341 TX Vref early break, caculate TX vref
8887 16:34:28.569903 TX Vref=16, minBit 9, minWin=22, winSum=380
8888 16:34:28.573013 TX Vref=18, minBit 9, minWin=22, winSum=388
8889 16:34:28.576189 TX Vref=20, minBit 9, minWin=22, winSum=393
8890 16:34:28.579555 TX Vref=22, minBit 9, minWin=23, winSum=403
8891 16:34:28.582902 TX Vref=24, minBit 9, minWin=24, winSum=412
8892 16:34:28.589411 TX Vref=26, minBit 9, minWin=23, winSum=412
8893 16:34:28.592950 TX Vref=28, minBit 9, minWin=23, winSum=414
8894 16:34:28.596148 TX Vref=30, minBit 9, minWin=24, winSum=419
8895 16:34:28.599146 TX Vref=32, minBit 0, minWin=24, winSum=406
8896 16:34:28.602730 TX Vref=34, minBit 9, minWin=23, winSum=402
8897 16:34:28.605959 TX Vref=36, minBit 9, minWin=22, winSum=395
8898 16:34:28.613089 [TxChooseVref] Worse bit 9, Min win 24, Win sum 419, Final Vref 30
8899 16:34:28.613749
8900 16:34:28.615830 Final TX Range 0 Vref 30
8901 16:34:28.616259
8902 16:34:28.616685 ==
8903 16:34:28.619451 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 16:34:28.622448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 16:34:28.622866 ==
8906 16:34:28.623187
8907 16:34:28.626138
8908 16:34:28.626565 TX Vref Scan disable
8909 16:34:28.632727 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8910 16:34:28.633141 == TX Byte 0 ==
8911 16:34:28.635833 u2DelayCellOfst[0]=14 cells (4 PI)
8912 16:34:28.638888 u2DelayCellOfst[1]=10 cells (3 PI)
8913 16:34:28.642249 u2DelayCellOfst[2]=0 cells (0 PI)
8914 16:34:28.645549 u2DelayCellOfst[3]=7 cells (2 PI)
8915 16:34:28.648803 u2DelayCellOfst[4]=10 cells (3 PI)
8916 16:34:28.652232 u2DelayCellOfst[5]=14 cells (4 PI)
8917 16:34:28.655600 u2DelayCellOfst[6]=14 cells (4 PI)
8918 16:34:28.658650 u2DelayCellOfst[7]=7 cells (2 PI)
8919 16:34:28.661762 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8920 16:34:28.665742 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8921 16:34:28.668970 == TX Byte 1 ==
8922 16:34:28.671931 u2DelayCellOfst[8]=0 cells (0 PI)
8923 16:34:28.675671 u2DelayCellOfst[9]=3 cells (1 PI)
8924 16:34:28.678400 u2DelayCellOfst[10]=10 cells (3 PI)
8925 16:34:28.681833 u2DelayCellOfst[11]=7 cells (2 PI)
8926 16:34:28.684983 u2DelayCellOfst[12]=14 cells (4 PI)
8927 16:34:28.685661 u2DelayCellOfst[13]=17 cells (5 PI)
8928 16:34:28.688310 u2DelayCellOfst[14]=17 cells (5 PI)
8929 16:34:28.691449 u2DelayCellOfst[15]=17 cells (5 PI)
8930 16:34:28.698516 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8931 16:34:28.701589 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8932 16:34:28.705057 DramC Write-DBI on
8933 16:34:28.705522 ==
8934 16:34:28.708893 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 16:34:28.711736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 16:34:28.712159 ==
8937 16:34:28.712485
8938 16:34:28.712788
8939 16:34:28.714987 TX Vref Scan disable
8940 16:34:28.715406 == TX Byte 0 ==
8941 16:34:28.721345 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8942 16:34:28.721765 == TX Byte 1 ==
8943 16:34:28.724904 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8944 16:34:28.727958 DramC Write-DBI off
8945 16:34:28.728377
8946 16:34:28.728703 [DATLAT]
8947 16:34:28.731392 Freq=1600, CH1 RK1
8948 16:34:28.731811
8949 16:34:28.732135 DATLAT Default: 0xf
8950 16:34:28.734398 0, 0xFFFF, sum = 0
8951 16:34:28.734826 1, 0xFFFF, sum = 0
8952 16:34:28.737908 2, 0xFFFF, sum = 0
8953 16:34:28.741235 3, 0xFFFF, sum = 0
8954 16:34:28.741687 4, 0xFFFF, sum = 0
8955 16:34:28.744944 5, 0xFFFF, sum = 0
8956 16:34:28.745522 6, 0xFFFF, sum = 0
8957 16:34:28.747821 7, 0xFFFF, sum = 0
8958 16:34:28.748287 8, 0xFFFF, sum = 0
8959 16:34:28.751054 9, 0xFFFF, sum = 0
8960 16:34:28.751483 10, 0xFFFF, sum = 0
8961 16:34:28.754146 11, 0xFFFF, sum = 0
8962 16:34:28.754666 12, 0xFFFF, sum = 0
8963 16:34:28.757424 13, 0xFFFF, sum = 0
8964 16:34:28.757851 14, 0x0, sum = 1
8965 16:34:28.761171 15, 0x0, sum = 2
8966 16:34:28.761664 16, 0x0, sum = 3
8967 16:34:28.764353 17, 0x0, sum = 4
8968 16:34:28.764777 best_step = 15
8969 16:34:28.765106
8970 16:34:28.765532 ==
8971 16:34:28.767990 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 16:34:28.773841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 16:34:28.774266 ==
8974 16:34:28.774597 RX Vref Scan: 0
8975 16:34:28.774905
8976 16:34:28.777368 RX Vref 0 -> 0, step: 1
8977 16:34:28.777789
8978 16:34:28.781062 RX Delay 19 -> 252, step: 4
8979 16:34:28.784547 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8980 16:34:28.787437 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8981 16:34:28.790417 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8982 16:34:28.797505 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8983 16:34:28.800716 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8984 16:34:28.804162 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8985 16:34:28.807375 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8986 16:34:28.810600 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8987 16:34:28.816689 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8988 16:34:28.819897 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8989 16:34:28.823741 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8990 16:34:28.827008 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8991 16:34:28.833371 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8992 16:34:28.836772 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8993 16:34:28.839782 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8994 16:34:28.843337 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8995 16:34:28.843909 ==
8996 16:34:28.846489 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 16:34:28.853060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 16:34:28.853344 ==
8999 16:34:28.853615 DQS Delay:
9000 16:34:28.853792 DQS0 = 0, DQS1 = 0
9001 16:34:28.856183 DQM Delay:
9002 16:34:28.856408 DQM0 = 131, DQM1 = 127
9003 16:34:28.859730 DQ Delay:
9004 16:34:28.863130 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =128
9005 16:34:28.866426 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =130
9006 16:34:28.869802 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =120
9007 16:34:28.873055 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
9008 16:34:28.873533
9009 16:34:28.873864
9010 16:34:28.874170
9011 16:34:28.876291 [DramC_TX_OE_Calibration] TA2
9012 16:34:28.879578 Original DQ_B0 (3 6) =30, OEN = 27
9013 16:34:28.882653 Original DQ_B1 (3 6) =30, OEN = 27
9014 16:34:28.886062 24, 0x0, End_B0=24 End_B1=24
9015 16:34:28.886492 25, 0x0, End_B0=25 End_B1=25
9016 16:34:28.888998 26, 0x0, End_B0=26 End_B1=26
9017 16:34:28.892796 27, 0x0, End_B0=27 End_B1=27
9018 16:34:28.896041 28, 0x0, End_B0=28 End_B1=28
9019 16:34:28.899139 29, 0x0, End_B0=29 End_B1=29
9020 16:34:28.899655 30, 0x0, End_B0=30 End_B1=30
9021 16:34:28.902596 31, 0x4141, End_B0=30 End_B1=30
9022 16:34:28.905696 Byte0 end_step=30 best_step=27
9023 16:34:28.908873 Byte1 end_step=30 best_step=27
9024 16:34:28.912462 Byte0 TX OE(2T, 0.5T) = (3, 3)
9025 16:34:28.915384 Byte1 TX OE(2T, 0.5T) = (3, 3)
9026 16:34:28.915805
9027 16:34:28.916128
9028 16:34:28.922421 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9029 16:34:28.925563 CH1 RK1: MR19=303, MR18=E1C
9030 16:34:28.931931 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9031 16:34:28.935114 [RxdqsGatingPostProcess] freq 1600
9032 16:34:28.941732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9033 16:34:28.942221 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 16:34:28.944940 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 16:34:28.948323 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 16:34:28.952023 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 16:34:28.954912 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 16:34:28.958440 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 16:34:28.961935 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 16:34:28.965066 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 16:34:28.968354 Pre-setting of DQS Precalculation
9042 16:34:28.971661 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9043 16:34:28.981084 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9044 16:34:28.987886 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9045 16:34:28.988087
9046 16:34:28.988231
9047 16:34:28.990773 [Calibration Summary] 3200 Mbps
9048 16:34:28.990927 CH 0, Rank 0
9049 16:34:28.994249 SW Impedance : PASS
9050 16:34:28.994401 DUTY Scan : NO K
9051 16:34:28.997824 ZQ Calibration : PASS
9052 16:34:29.000910 Jitter Meter : NO K
9053 16:34:29.001062 CBT Training : PASS
9054 16:34:29.004459 Write leveling : PASS
9055 16:34:29.007515 RX DQS gating : PASS
9056 16:34:29.007730 RX DQ/DQS(RDDQC) : PASS
9057 16:34:29.010640 TX DQ/DQS : PASS
9058 16:34:29.014130 RX DATLAT : PASS
9059 16:34:29.014283 RX DQ/DQS(Engine): PASS
9060 16:34:29.017187 TX OE : PASS
9061 16:34:29.017362 All Pass.
9062 16:34:29.017484
9063 16:34:29.020970 CH 0, Rank 1
9064 16:34:29.021143 SW Impedance : PASS
9065 16:34:29.024092 DUTY Scan : NO K
9066 16:34:29.027694 ZQ Calibration : PASS
9067 16:34:29.027895 Jitter Meter : NO K
9068 16:34:29.030944 CBT Training : PASS
9069 16:34:29.033839 Write leveling : PASS
9070 16:34:29.034215 RX DQS gating : PASS
9071 16:34:29.037322 RX DQ/DQS(RDDQC) : PASS
9072 16:34:29.040731 TX DQ/DQS : PASS
9073 16:34:29.041119 RX DATLAT : PASS
9074 16:34:29.044183 RX DQ/DQS(Engine): PASS
9075 16:34:29.044692 TX OE : PASS
9076 16:34:29.047079 All Pass.
9077 16:34:29.047497
9078 16:34:29.047820 CH 1, Rank 0
9079 16:34:29.050386 SW Impedance : PASS
9080 16:34:29.054065 DUTY Scan : NO K
9081 16:34:29.054485 ZQ Calibration : PASS
9082 16:34:29.056855 Jitter Meter : NO K
9083 16:34:29.057319 CBT Training : PASS
9084 16:34:29.060083 Write leveling : PASS
9085 16:34:29.064125 RX DQS gating : PASS
9086 16:34:29.064641 RX DQ/DQS(RDDQC) : PASS
9087 16:34:29.066920 TX DQ/DQS : PASS
9088 16:34:29.070625 RX DATLAT : PASS
9089 16:34:29.071045 RX DQ/DQS(Engine): PASS
9090 16:34:29.073620 TX OE : PASS
9091 16:34:29.074065 All Pass.
9092 16:34:29.074403
9093 16:34:29.076888 CH 1, Rank 1
9094 16:34:29.077351 SW Impedance : PASS
9095 16:34:29.080177 DUTY Scan : NO K
9096 16:34:29.083236 ZQ Calibration : PASS
9097 16:34:29.083653 Jitter Meter : NO K
9098 16:34:29.086808 CBT Training : PASS
9099 16:34:29.089844 Write leveling : PASS
9100 16:34:29.090313 RX DQS gating : PASS
9101 16:34:29.093737 RX DQ/DQS(RDDQC) : PASS
9102 16:34:29.096843 TX DQ/DQS : PASS
9103 16:34:29.097347 RX DATLAT : PASS
9104 16:34:29.099909 RX DQ/DQS(Engine): PASS
9105 16:34:29.102942 TX OE : PASS
9106 16:34:29.103365 All Pass.
9107 16:34:29.103817
9108 16:34:29.104145 DramC Write-DBI on
9109 16:34:29.106569 PER_BANK_REFRESH: Hybrid Mode
9110 16:34:29.109893 TX_TRACKING: ON
9111 16:34:29.116245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9112 16:34:29.126266 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9113 16:34:29.132692 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9114 16:34:29.135759 [FAST_K] Save calibration result to emmc
9115 16:34:29.139307 sync common calibartion params.
9116 16:34:29.142475 sync cbt_mode0:1, 1:1
9117 16:34:29.142701 dram_init: ddr_geometry: 2
9118 16:34:29.145994 dram_init: ddr_geometry: 2
9119 16:34:29.149096 dram_init: ddr_geometry: 2
9120 16:34:29.152382 0:dram_rank_size:100000000
9121 16:34:29.152611 1:dram_rank_size:100000000
9122 16:34:29.158708 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9123 16:34:29.162359 DFS_SHUFFLE_HW_MODE: ON
9124 16:34:29.165882 dramc_set_vcore_voltage set vcore to 725000
9125 16:34:29.169098 Read voltage for 1600, 0
9126 16:34:29.169664 Vio18 = 0
9127 16:34:29.170000 Vcore = 725000
9128 16:34:29.172225 Vdram = 0
9129 16:34:29.172639 Vddq = 0
9130 16:34:29.172961 Vmddr = 0
9131 16:34:29.175615 switch to 3200 Mbps bootup
9132 16:34:29.176133 [DramcRunTimeConfig]
9133 16:34:29.179332 PHYPLL
9134 16:34:29.179849 DPM_CONTROL_AFTERK: ON
9135 16:34:29.182341 PER_BANK_REFRESH: ON
9136 16:34:29.185687 REFRESH_OVERHEAD_REDUCTION: ON
9137 16:34:29.186214 CMD_PICG_NEW_MODE: OFF
9138 16:34:29.188736 XRTWTW_NEW_MODE: ON
9139 16:34:29.189223 XRTRTR_NEW_MODE: ON
9140 16:34:29.192032 TX_TRACKING: ON
9141 16:34:29.192449 RDSEL_TRACKING: OFF
9142 16:34:29.195263 DQS Precalculation for DVFS: ON
9143 16:34:29.198498 RX_TRACKING: OFF
9144 16:34:29.199008 HW_GATING DBG: ON
9145 16:34:29.203076 ZQCS_ENABLE_LP4: ON
9146 16:34:29.203846 RX_PICG_NEW_MODE: ON
9147 16:34:29.204875 TX_PICG_NEW_MODE: ON
9148 16:34:29.208652 ENABLE_RX_DCM_DPHY: ON
9149 16:34:29.209097 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9150 16:34:29.211768 DUMMY_READ_FOR_TRACKING: OFF
9151 16:34:29.215103 !!! SPM_CONTROL_AFTERK: OFF
9152 16:34:29.218276 !!! SPM could not control APHY
9153 16:34:29.219030 IMPEDANCE_TRACKING: ON
9154 16:34:29.221471 TEMP_SENSOR: ON
9155 16:34:29.221904 HW_SAVE_FOR_SR: OFF
9156 16:34:29.224793 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9157 16:34:29.228284 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9158 16:34:29.231377 Read ODT Tracking: ON
9159 16:34:29.235159 Refresh Rate DeBounce: ON
9160 16:34:29.235572 DFS_NO_QUEUE_FLUSH: ON
9161 16:34:29.238325 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9162 16:34:29.241488 ENABLE_DFS_RUNTIME_MRW: OFF
9163 16:34:29.245155 DDR_RESERVE_NEW_MODE: ON
9164 16:34:29.245827 MR_CBT_SWITCH_FREQ: ON
9165 16:34:29.248101 =========================
9166 16:34:29.267922 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9167 16:34:29.270894 dram_init: ddr_geometry: 2
9168 16:34:29.289626 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9169 16:34:29.292628 dram_init: dram init end (result: 0)
9170 16:34:29.298635 DRAM-K: Full calibration passed in 24381 msecs
9171 16:34:29.301811 MRC: failed to locate region type 0.
9172 16:34:29.302224 DRAM rank0 size:0x100000000,
9173 16:34:29.305819 DRAM rank1 size=0x100000000
9174 16:34:29.315812 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9175 16:34:29.322231 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9176 16:34:29.328810 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9177 16:34:29.335251 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9178 16:34:29.339125 DRAM rank0 size:0x100000000,
9179 16:34:29.342042 DRAM rank1 size=0x100000000
9180 16:34:29.342463 CBMEM:
9181 16:34:29.344959 IMD: root @ 0xfffff000 254 entries.
9182 16:34:29.348613 IMD: root @ 0xffffec00 62 entries.
9183 16:34:29.351853 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9184 16:34:29.358141 WARNING: RO_VPD is uninitialized or empty.
9185 16:34:29.361603 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9186 16:34:29.368927 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9187 16:34:29.381797 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9188 16:34:29.393217 BS: romstage times (exec / console): total (unknown) / 23912 ms
9189 16:34:29.393754
9190 16:34:29.394087
9191 16:34:29.403217 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9192 16:34:29.406539 ARM64: Exception handlers installed.
9193 16:34:29.409538 ARM64: Testing exception
9194 16:34:29.412895 ARM64: Done test exception
9195 16:34:29.413353 Enumerating buses...
9196 16:34:29.416214 Show all devs... Before device enumeration.
9197 16:34:29.420034 Root Device: enabled 1
9198 16:34:29.423175 CPU_CLUSTER: 0: enabled 1
9199 16:34:29.423608 CPU: 00: enabled 1
9200 16:34:29.426437 Compare with tree...
9201 16:34:29.426852 Root Device: enabled 1
9202 16:34:29.429610 CPU_CLUSTER: 0: enabled 1
9203 16:34:29.432736 CPU: 00: enabled 1
9204 16:34:29.433146 Root Device scanning...
9205 16:34:29.436090 scan_static_bus for Root Device
9206 16:34:29.439499 CPU_CLUSTER: 0 enabled
9207 16:34:29.442355 scan_static_bus for Root Device done
9208 16:34:29.446072 scan_bus: bus Root Device finished in 8 msecs
9209 16:34:29.446255 done
9210 16:34:29.452725 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9211 16:34:29.455800 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9212 16:34:29.462388 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9213 16:34:29.465272 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9214 16:34:29.468918 Allocating resources...
9215 16:34:29.472272 Reading resources...
9216 16:34:29.475295 Root Device read_resources bus 0 link: 0
9217 16:34:29.478382 DRAM rank0 size:0x100000000,
9218 16:34:29.478534 DRAM rank1 size=0x100000000
9219 16:34:29.485064 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9220 16:34:29.485210 CPU: 00 missing read_resources
9221 16:34:29.491491 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9222 16:34:29.494735 Root Device read_resources bus 0 link: 0 done
9223 16:34:29.498377 Done reading resources.
9224 16:34:29.501514 Show resources in subtree (Root Device)...After reading.
9225 16:34:29.504649 Root Device child on link 0 CPU_CLUSTER: 0
9226 16:34:29.507875 CPU_CLUSTER: 0 child on link 0 CPU: 00
9227 16:34:29.517664 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9228 16:34:29.517764 CPU: 00
9229 16:34:29.524155 Root Device assign_resources, bus 0 link: 0
9230 16:34:29.527515 CPU_CLUSTER: 0 missing set_resources
9231 16:34:29.531404 Root Device assign_resources, bus 0 link: 0 done
9232 16:34:29.534943 Done setting resources.
9233 16:34:29.538017 Show resources in subtree (Root Device)...After assigning values.
9234 16:34:29.541240 Root Device child on link 0 CPU_CLUSTER: 0
9235 16:34:29.548041 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 16:34:29.554606 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 16:34:29.557735 CPU: 00
9238 16:34:29.558314 Done allocating resources.
9239 16:34:29.564624 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9240 16:34:29.565170 Enabling resources...
9241 16:34:29.567753 done.
9242 16:34:29.570687 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9243 16:34:29.574197 Initializing devices...
9244 16:34:29.574616 Root Device init
9245 16:34:29.577079 init hardware done!
9246 16:34:29.577546 0x00000018: ctrlr->caps
9247 16:34:29.580593 52.000 MHz: ctrlr->f_max
9248 16:34:29.584245 0.400 MHz: ctrlr->f_min
9249 16:34:29.587330 0x40ff8080: ctrlr->voltages
9250 16:34:29.587762 sclk: 390625
9251 16:34:29.588092 Bus Width = 1
9252 16:34:29.590993 sclk: 390625
9253 16:34:29.591409 Bus Width = 1
9254 16:34:29.593906 Early init status = 3
9255 16:34:29.597207 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9256 16:34:29.600919 in-header: 03 fc 00 00 01 00 00 00
9257 16:34:29.603884 in-data: 00
9258 16:34:29.607020 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9259 16:34:29.612064 in-header: 03 fd 00 00 00 00 00 00
9260 16:34:29.615429 in-data:
9261 16:34:29.618405 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9262 16:34:29.621880 in-header: 03 fc 00 00 01 00 00 00
9263 16:34:29.624968 in-data: 00
9264 16:34:29.628283 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9265 16:34:29.633297 in-header: 03 fd 00 00 00 00 00 00
9266 16:34:29.636553 in-data:
9267 16:34:29.640061 [SSUSB] Setting up USB HOST controller...
9268 16:34:29.643974 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9269 16:34:29.646930 [SSUSB] phy power-on done.
9270 16:34:29.650031 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9271 16:34:29.656443 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9272 16:34:29.659702 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9273 16:34:29.666450 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9274 16:34:29.673564 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9275 16:34:29.679891 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9276 16:34:29.686618 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9277 16:34:29.692609 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9278 16:34:29.696612 SPM: binary array size = 0x9dc
9279 16:34:29.699356 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9280 16:34:29.706483 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9281 16:34:29.712480 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9282 16:34:29.718950 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9283 16:34:29.722119 configure_display: Starting display init
9284 16:34:29.756332 anx7625_power_on_init: Init interface.
9285 16:34:29.759380 anx7625_disable_pd_protocol: Disabled PD feature.
9286 16:34:29.763107 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9287 16:34:29.791240 anx7625_start_dp_work: Secure OCM version=00
9288 16:34:29.793927 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9289 16:34:29.809034 sp_tx_get_edid_block: EDID Block = 1
9290 16:34:29.911845 Extracted contents:
9291 16:34:29.915252 header: 00 ff ff ff ff ff ff 00
9292 16:34:29.918269 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9293 16:34:29.921598 version: 01 04
9294 16:34:29.924907 basic params: 95 1f 11 78 0a
9295 16:34:29.928148 chroma info: 76 90 94 55 54 90 27 21 50 54
9296 16:34:29.931861 established: 00 00 00
9297 16:34:29.938285 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9298 16:34:29.944873 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9299 16:34:29.947913 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9300 16:34:29.954251 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9301 16:34:29.961384 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9302 16:34:29.964845 extensions: 00
9303 16:34:29.965413 checksum: fb
9304 16:34:29.965857
9305 16:34:29.971218 Manufacturer: IVO Model 57d Serial Number 0
9306 16:34:29.971716 Made week 0 of 2020
9307 16:34:29.974325 EDID version: 1.4
9308 16:34:29.974734 Digital display
9309 16:34:29.977510 6 bits per primary color channel
9310 16:34:29.980647 DisplayPort interface
9311 16:34:29.981057 Maximum image size: 31 cm x 17 cm
9312 16:34:29.983769 Gamma: 220%
9313 16:34:29.984177 Check DPMS levels
9314 16:34:29.990612 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9315 16:34:29.993764 First detailed timing is preferred timing
9316 16:34:29.996986 Established timings supported:
9317 16:34:29.997670 Standard timings supported:
9318 16:34:30.000806 Detailed timings
9319 16:34:30.003912 Hex of detail: 383680a07038204018303c0035ae10000019
9320 16:34:30.010737 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9321 16:34:30.014114 0780 0798 07c8 0820 hborder 0
9322 16:34:30.017058 0438 043b 0447 0458 vborder 0
9323 16:34:30.020331 -hsync -vsync
9324 16:34:30.020739 Did detailed timing
9325 16:34:30.026903 Hex of detail: 000000000000000000000000000000000000
9326 16:34:30.030101 Manufacturer-specified data, tag 0
9327 16:34:30.033466 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9328 16:34:30.036577 ASCII string: InfoVision
9329 16:34:30.039951 Hex of detail: 000000fe00523134304e574635205248200a
9330 16:34:30.043201 ASCII string: R140NWF5 RH
9331 16:34:30.043753 Checksum
9332 16:34:30.046816 Checksum: 0xfb (valid)
9333 16:34:30.049720 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9334 16:34:30.052917 DSI data_rate: 832800000 bps
9335 16:34:30.060243 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9336 16:34:30.063493 anx7625_parse_edid: pixelclock(138800).
9337 16:34:30.066374 hactive(1920), hsync(48), hfp(24), hbp(88)
9338 16:34:30.069656 vactive(1080), vsync(12), vfp(3), vbp(17)
9339 16:34:30.072807 anx7625_dsi_config: config dsi.
9340 16:34:30.080046 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9341 16:34:30.093645 anx7625_dsi_config: success to config DSI
9342 16:34:30.096894 anx7625_dp_start: MIPI phy setup OK.
9343 16:34:30.100819 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9344 16:34:30.103429 mtk_ddp_mode_set invalid vrefresh 60
9345 16:34:30.106856 main_disp_path_setup
9346 16:34:30.107267 ovl_layer_smi_id_en
9347 16:34:30.110084 ovl_layer_smi_id_en
9348 16:34:30.110495 ccorr_config
9349 16:34:30.110839 aal_config
9350 16:34:30.113519 gamma_config
9351 16:34:30.113929 postmask_config
9352 16:34:30.116696 dither_config
9353 16:34:30.119957 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9354 16:34:30.126566 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9355 16:34:30.129907 Root Device init finished in 551 msecs
9356 16:34:30.133173 CPU_CLUSTER: 0 init
9357 16:34:30.139500 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9358 16:34:30.146413 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9359 16:34:30.146827 APU_MBOX 0x190000b0 = 0x10001
9360 16:34:30.149486 APU_MBOX 0x190001b0 = 0x10001
9361 16:34:30.152801 APU_MBOX 0x190005b0 = 0x10001
9362 16:34:30.156433 APU_MBOX 0x190006b0 = 0x10001
9363 16:34:30.162565 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9364 16:34:30.172977 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9365 16:34:30.185374 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9366 16:34:30.191876 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9367 16:34:30.203429 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9368 16:34:30.212783 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9369 16:34:30.216169 CPU_CLUSTER: 0 init finished in 81 msecs
9370 16:34:30.219117 Devices initialized
9371 16:34:30.222564 Show all devs... After init.
9372 16:34:30.222970 Root Device: enabled 1
9373 16:34:30.226099 CPU_CLUSTER: 0: enabled 1
9374 16:34:30.228726 CPU: 00: enabled 1
9375 16:34:30.232503 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9376 16:34:30.235672 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9377 16:34:30.239174 ELOG: NV offset 0x57f000 size 0x1000
9378 16:34:30.245789 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9379 16:34:30.252457 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9380 16:34:30.255741 ELOG: Event(17) added with size 13 at 2024-06-17 16:34:30 UTC
9381 16:34:30.262158 out: cmd=0x121: 03 db 21 01 00 00 00 00
9382 16:34:30.265646 in-header: 03 23 00 00 2c 00 00 00
9383 16:34:30.275032 in-data: 1a 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9384 16:34:30.281835 ELOG: Event(A1) added with size 10 at 2024-06-17 16:34:30 UTC
9385 16:34:30.288925 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9386 16:34:30.295280 ELOG: Event(A0) added with size 9 at 2024-06-17 16:34:30 UTC
9387 16:34:30.298301 elog_add_boot_reason: Logged dev mode boot
9388 16:34:30.305496 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9389 16:34:30.305913 Finalize devices...
9390 16:34:30.308604 Devices finalized
9391 16:34:30.311851 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9392 16:34:30.315119 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9393 16:34:30.318154 in-header: 03 07 00 00 08 00 00 00
9394 16:34:30.322091 in-data: aa e4 47 04 13 02 00 00
9395 16:34:30.324857 Chrome EC: UHEPI supported
9396 16:34:30.332053 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9397 16:34:30.334876 in-header: 03 a9 00 00 08 00 00 00
9398 16:34:30.338537 in-data: 84 60 60 08 00 00 00 00
9399 16:34:30.345155 ELOG: Event(91) added with size 10 at 2024-06-17 16:34:30 UTC
9400 16:34:30.348237 Chrome EC: clear events_b mask to 0x0000000020004000
9401 16:34:30.354549 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9402 16:34:30.358678 in-header: 03 fd 00 00 00 00 00 00
9403 16:34:30.361827 in-data:
9404 16:34:30.364934 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9405 16:34:30.369088 Writing coreboot table at 0xffe64000
9406 16:34:30.375486 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 16:34:30.378570 1. 0000000040000000-00000000400fffff: RAM
9408 16:34:30.381724 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 16:34:30.385284 3. 000000004032b000-00000000545fffff: RAM
9410 16:34:30.388287 4. 0000000054600000-000000005465ffff: BL31
9411 16:34:30.391556 5. 0000000054660000-00000000ffe63fff: RAM
9412 16:34:30.398737 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 16:34:30.401868 7. 0000000100000000-000000023fffffff: RAM
9414 16:34:30.404829 Passing 5 GPIOs to payload:
9415 16:34:30.408148 NAME | PORT | POLARITY | VALUE
9416 16:34:30.415455 EC in RW | 0x000000aa | low | undefined
9417 16:34:30.418537 EC interrupt | 0x00000005 | low | undefined
9418 16:34:30.425111 TPM interrupt | 0x000000ab | high | undefined
9419 16:34:30.427917 SD card detect | 0x00000011 | high | undefined
9420 16:34:30.431459 speaker enable | 0x00000093 | high | undefined
9421 16:34:30.434551 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 16:34:30.437760 in-header: 03 f9 00 00 02 00 00 00
9423 16:34:30.441812 in-data: 02 00
9424 16:34:30.444811 ADC[4]: Raw value=901847 ID=7
9425 16:34:30.448208 ADC[3]: Raw value=213546 ID=1
9426 16:34:30.448713 RAM Code: 0x71
9427 16:34:30.451113 ADC[6]: Raw value=74630 ID=0
9428 16:34:30.454696 ADC[5]: Raw value=213546 ID=1
9429 16:34:30.455117 SKU Code: 0x1
9430 16:34:30.461398 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cba3
9431 16:34:30.461917 coreboot table: 964 bytes.
9432 16:34:30.464375 IMD ROOT 0. 0xfffff000 0x00001000
9433 16:34:30.467808 IMD SMALL 1. 0xffffe000 0x00001000
9434 16:34:30.471015 RO MCACHE 2. 0xffffc000 0x00001104
9435 16:34:30.474455 CONSOLE 3. 0xfff7c000 0x00080000
9436 16:34:30.477362 FMAP 4. 0xfff7b000 0x00000452
9437 16:34:30.480927 TIME STAMP 5. 0xfff7a000 0x00000910
9438 16:34:30.484062 VBOOT WORK 6. 0xfff66000 0x00014000
9439 16:34:30.487291 RAMOOPS 7. 0xffe66000 0x00100000
9440 16:34:30.491318 COREBOOT 8. 0xffe64000 0x00002000
9441 16:34:30.494353 IMD small region:
9442 16:34:30.497522 IMD ROOT 0. 0xffffec00 0x00000400
9443 16:34:30.500693 VPD 1. 0xffffeb80 0x0000006c
9444 16:34:30.503888 MMC STATUS 2. 0xffffeb60 0x00000004
9445 16:34:30.510815 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 16:34:30.517124 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 16:34:30.555614 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9448 16:34:30.558680 Checking segment from ROM address 0x40100000
9449 16:34:30.565381 Checking segment from ROM address 0x4010001c
9450 16:34:30.568678 Loading segment from ROM address 0x40100000
9451 16:34:30.569096 code (compression=0)
9452 16:34:30.578810 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 16:34:30.585596 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 16:34:30.586185 it's not compressed!
9455 16:34:30.592075 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 16:34:30.598214 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 16:34:30.616242 Loading segment from ROM address 0x4010001c
9458 16:34:30.616788 Entry Point 0x80000000
9459 16:34:30.619374 Loaded segments
9460 16:34:30.622367 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 16:34:30.628862 Jumping to boot code at 0x80000000(0xffe64000)
9462 16:34:30.635849 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 16:34:30.642125 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 16:34:30.650485 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9465 16:34:30.654265 Checking segment from ROM address 0x40100000
9466 16:34:30.656737 Checking segment from ROM address 0x4010001c
9467 16:34:30.663875 Loading segment from ROM address 0x40100000
9468 16:34:30.664295 code (compression=1)
9469 16:34:30.670591 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 16:34:30.680086 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 16:34:30.680577 using LZMA
9472 16:34:30.688464 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 16:34:30.695388 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 16:34:30.698840 Loading segment from ROM address 0x4010001c
9475 16:34:30.701738 Entry Point 0x54601000
9476 16:34:30.702340 Loaded segments
9477 16:34:30.705106 NOTICE: MT8192 bl31_setup
9478 16:34:30.712882 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 16:34:30.715791 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 16:34:30.719193 WARNING: region 0:
9481 16:34:30.722246 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 16:34:30.722667 WARNING: region 1:
9483 16:34:30.728989 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 16:34:30.732069 WARNING: region 2:
9485 16:34:30.735442 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 16:34:30.738598 WARNING: region 3:
9487 16:34:30.744995 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 16:34:30.745562 WARNING: region 4:
9489 16:34:30.751840 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 16:34:30.752256 WARNING: region 5:
9491 16:34:30.755473 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 16:34:30.758788 WARNING: region 6:
9493 16:34:30.761809 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 16:34:30.765330 WARNING: region 7:
9495 16:34:30.768487 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 16:34:30.775104 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 16:34:30.778409 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 16:34:30.784620 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 16:34:30.788853 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 16:34:30.791741 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 16:34:30.797951 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 16:34:30.800977 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 16:34:30.805254 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 16:34:30.811537 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 16:34:30.814340 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 16:34:30.820859 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 16:34:30.824560 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 16:34:30.827498 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 16:34:30.834114 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 16:34:30.837801 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 16:34:30.843929 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 16:34:30.847193 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 16:34:30.850552 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 16:34:30.857315 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 16:34:30.860720 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 16:34:30.867191 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 16:34:30.870359 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 16:34:30.873441 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 16:34:30.880620 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 16:34:30.883610 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 16:34:30.890009 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 16:34:30.893525 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 16:34:30.897206 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 16:34:30.903087 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 16:34:30.906445 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 16:34:30.913518 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 16:34:30.916577 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 16:34:30.919582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 16:34:30.925912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 16:34:30.929439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 16:34:30.932786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 16:34:30.936138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 16:34:30.942634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 16:34:30.946222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 16:34:30.949351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 16:34:30.952388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 16:34:30.958803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 16:34:30.962157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 16:34:30.965723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 16:34:30.972325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 16:34:30.975243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 16:34:30.978616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 16:34:30.982236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 16:34:30.988771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 16:34:30.992037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 16:34:30.999019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 16:34:31.002067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 16:34:31.008371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 16:34:31.011313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 16:34:31.018617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 16:34:31.021768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 16:34:31.024796 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 16:34:31.031644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 16:34:31.034660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 16:34:31.041390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 16:34:31.044819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 16:34:31.051112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 16:34:31.054727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 16:34:31.060908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 16:34:31.064328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 16:34:31.070689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 16:34:31.074143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 16:34:31.077816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 16:34:31.083710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 16:34:31.087609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 16:34:31.093718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 16:34:31.097901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 16:34:31.103842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 16:34:31.106983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 16:34:31.113478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 16:34:31.117449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 16:34:31.120356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 16:34:31.127429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 16:34:31.130187 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 16:34:31.137099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 16:34:31.139990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 16:34:31.146365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 16:34:31.149965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 16:34:31.156498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 16:34:31.159665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 16:34:31.162955 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 16:34:31.169944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 16:34:31.172963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 16:34:31.179396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 16:34:31.182601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 16:34:31.189626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 16:34:31.192687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 16:34:31.198956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 16:34:31.202154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 16:34:31.209135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 16:34:31.212495 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 16:34:31.215779 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 16:34:31.222451 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 16:34:31.225533 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 16:34:31.228718 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 16:34:31.231798 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 16:34:31.238699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 16:34:31.241892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 16:34:31.248526 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 16:34:31.251579 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 16:34:31.255244 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 16:34:31.261724 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 16:34:31.265250 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 16:34:31.271766 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 16:34:31.275172 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 16:34:31.278405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 16:34:31.285391 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 16:34:31.288372 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 16:34:31.294365 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 16:34:31.297916 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 16:34:31.304923 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 16:34:31.307630 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 16:34:31.311171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 16:34:31.314438 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 16:34:31.321544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 16:34:31.324628 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 16:34:31.327876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 16:34:31.330967 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 16:34:31.338031 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 16:34:31.341038 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 16:34:31.347554 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 16:34:31.350685 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 16:34:31.353912 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 16:34:31.360416 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 16:34:31.364187 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 16:34:31.371237 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 16:34:31.374056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 16:34:31.377397 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 16:34:31.383934 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 16:34:31.387329 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 16:34:31.394058 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 16:34:31.397212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 16:34:31.400123 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 16:34:31.407073 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 16:34:31.410181 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 16:34:31.417004 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 16:34:31.420344 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 16:34:31.423328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 16:34:31.430003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 16:34:31.432958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 16:34:31.439781 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 16:34:31.442997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 16:34:31.446284 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 16:34:31.452691 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 16:34:31.456406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 16:34:31.462813 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 16:34:31.466195 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 16:34:31.469226 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 16:34:31.476514 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 16:34:31.479127 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 16:34:31.485898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 16:34:31.489342 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 16:34:31.492226 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 16:34:31.498962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 16:34:31.502109 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 16:34:31.508581 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 16:34:31.512342 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 16:34:31.515834 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 16:34:31.522616 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 16:34:31.525426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 16:34:31.531828 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 16:34:31.535230 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 16:34:31.538769 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 16:34:31.545193 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 16:34:31.548154 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 16:34:31.555016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 16:34:31.558577 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 16:34:31.561558 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 16:34:31.567924 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 16:34:31.571423 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 16:34:31.578407 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 16:34:31.581430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 16:34:31.584568 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 16:34:31.591366 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 16:34:31.594611 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 16:34:31.601448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 16:34:31.604805 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 16:34:31.607643 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 16:34:31.614178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 16:34:31.618112 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 16:34:31.624153 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 16:34:31.627265 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 16:34:31.630791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 16:34:31.636986 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 16:34:31.641070 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 16:34:31.647133 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 16:34:31.650708 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 16:34:31.657164 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 16:34:31.660480 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 16:34:31.663669 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 16:34:31.671020 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 16:34:31.673815 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 16:34:31.680247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 16:34:31.684227 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 16:34:31.690326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 16:34:31.693612 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 16:34:31.697083 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 16:34:31.703275 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 16:34:31.706344 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 16:34:31.712804 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 16:34:31.716753 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 16:34:31.723262 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 16:34:31.726406 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 16:34:31.729941 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 16:34:31.736465 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 16:34:31.739653 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 16:34:31.746518 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 16:34:31.749922 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 16:34:31.756523 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 16:34:31.759215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 16:34:31.763036 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 16:34:31.769711 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 16:34:31.772839 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 16:34:31.778925 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 16:34:31.782466 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 16:34:31.788723 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 16:34:31.792707 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 16:34:31.795784 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 16:34:31.802108 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 16:34:31.805586 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 16:34:31.812158 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 16:34:31.815406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 16:34:31.821762 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 16:34:31.825796 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 16:34:31.828715 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 16:34:31.831724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 16:34:31.838642 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 16:34:31.841843 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 16:34:31.845318 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 16:34:31.848438 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 16:34:31.854594 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 16:34:31.858538 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 16:34:31.864732 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 16:34:31.868066 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 16:34:31.872360 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 16:34:31.878242 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 16:34:31.881344 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 16:34:31.887802 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 16:34:31.891521 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 16:34:31.894815 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 16:34:31.901415 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 16:34:31.904465 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 16:34:31.910543 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 16:34:31.914329 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 16:34:31.917510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 16:34:31.924489 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 16:34:31.927156 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 16:34:31.930288 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 16:34:31.937162 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 16:34:31.940226 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 16:34:31.943531 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 16:34:31.950410 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 16:34:31.953527 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 16:34:31.960052 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 16:34:31.963256 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 16:34:31.966510 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 16:34:31.973421 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 16:34:31.976542 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 16:34:31.979876 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 16:34:31.986538 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 16:34:31.989516 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 16:34:31.995960 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 16:34:32.000188 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 16:34:32.002866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 16:34:32.009370 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 16:34:32.012788 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 16:34:32.015803 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 16:34:32.019822 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 16:34:32.022676 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 16:34:32.029760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 16:34:32.032470 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 16:34:32.035695 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 16:34:32.038955 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 16:34:32.045663 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 16:34:32.048810 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 16:34:32.052851 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 16:34:32.059343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 16:34:32.062364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 16:34:32.069113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 16:34:32.072200 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 16:34:32.075127 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 16:34:32.081978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 16:34:32.085037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 16:34:32.091917 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 16:34:32.094986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 16:34:32.098627 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 16:34:32.105027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 16:34:32.108350 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 16:34:32.114631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 16:34:32.117988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 16:34:32.124501 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 16:34:32.128634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 16:34:32.131512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 16:34:32.138107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 16:34:32.141480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 16:34:32.147606 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 16:34:32.151533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 16:34:32.157606 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 16:34:32.160964 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 16:34:32.164402 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 16:34:32.170836 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 16:34:32.174597 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 16:34:32.181026 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 16:34:32.184401 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 16:34:32.187590 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 16:34:32.193785 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 16:34:32.197217 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 16:34:32.203769 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 16:34:32.207569 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 16:34:32.210433 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 16:34:32.217053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 16:34:32.220785 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 16:34:32.227076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 16:34:32.230267 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 16:34:32.237103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 16:34:32.240214 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 16:34:32.243366 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 16:34:32.250094 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 16:34:32.252843 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 16:34:32.259724 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 16:34:32.263092 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 16:34:32.269753 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 16:34:32.272736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 16:34:32.279482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 16:34:32.282816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 16:34:32.285975 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 16:34:32.292789 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 16:34:32.295905 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 16:34:32.302619 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 16:34:32.305642 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 16:34:32.309050 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 16:34:32.317624 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 16:34:32.319436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 16:34:32.325573 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 16:34:32.329370 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 16:34:32.332603 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 16:34:32.338789 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 16:34:32.342893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 16:34:32.348883 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 16:34:32.352642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 16:34:32.355732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 16:34:32.361977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 16:34:32.365734 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 16:34:32.372211 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 16:34:32.375568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 16:34:32.382478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 16:34:32.385560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 16:34:32.388551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 16:34:32.395607 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 16:34:32.398760 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 16:34:32.405344 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 16:34:32.408282 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 16:34:32.415431 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 16:34:32.418611 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 16:34:32.421648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 16:34:32.428393 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 16:34:32.431483 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 16:34:32.438301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 16:34:32.441409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 16:34:32.448349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 16:34:32.451580 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 16:34:32.457860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 16:34:32.461476 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 16:34:32.467561 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 16:34:32.471468 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 16:34:32.474832 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 16:34:32.480697 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 16:34:32.484264 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 16:34:32.490887 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 16:34:32.493995 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 16:34:32.500738 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 16:34:32.503938 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 16:34:32.506895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 16:34:32.513560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 16:34:32.517347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 16:34:32.523740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 16:34:32.526881 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 16:34:32.533487 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 16:34:32.536781 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 16:34:32.543756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 16:34:32.546423 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 16:34:32.549610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 16:34:32.556911 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 16:34:32.559792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 16:34:32.566018 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 16:34:32.569733 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 16:34:32.576510 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 16:34:32.579621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 16:34:32.586540 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 16:34:32.589466 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 16:34:32.596124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 16:34:32.599275 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 16:34:32.602573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 16:34:32.609078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 16:34:32.612780 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 16:34:32.618743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 16:34:32.622571 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 16:34:32.625826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 16:34:32.631828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 16:34:32.635507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 16:34:32.641676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 16:34:32.645782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 16:34:32.651805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 16:34:32.655381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 16:34:32.661752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 16:34:32.664623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 16:34:32.671455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 16:34:32.675193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 16:34:32.681389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 16:34:32.685144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 16:34:32.691562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 16:34:32.695079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 16:34:32.701121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 16:34:32.704370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 16:34:32.710825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 16:34:32.714951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 16:34:32.721334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 16:34:32.724714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 16:34:32.730950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 16:34:32.734119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 16:34:32.740606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 16:34:32.743878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 16:34:32.750367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 16:34:32.753879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 16:34:32.760808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 16:34:32.766827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 16:34:32.770477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 16:34:32.776680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 16:34:32.781090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 16:34:32.784207 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 16:34:32.787376 INFO: [APUAPC] vio 0
9932 16:34:32.790150 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 16:34:32.796663 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 16:34:32.799923 INFO: [APUAPC] D0_APC_0: 0x400510
9935 16:34:32.803167 INFO: [APUAPC] D0_APC_1: 0x0
9936 16:34:32.806951 INFO: [APUAPC] D0_APC_2: 0x1540
9937 16:34:32.807364 INFO: [APUAPC] D0_APC_3: 0x0
9938 16:34:32.813603 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 16:34:32.816690 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 16:34:32.819840 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 16:34:32.820291 INFO: [APUAPC] D1_APC_3: 0x0
9942 16:34:32.822802 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 16:34:32.829732 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 16:34:32.833151 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 16:34:32.833694 INFO: [APUAPC] D2_APC_3: 0x0
9946 16:34:32.836279 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 16:34:32.839458 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 16:34:32.843097 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 16:34:32.846457 INFO: [APUAPC] D3_APC_3: 0x0
9950 16:34:32.849612 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 16:34:32.853366 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 16:34:32.856582 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 16:34:32.859860 INFO: [APUAPC] D4_APC_3: 0x0
9954 16:34:32.862735 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 16:34:32.866028 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 16:34:32.869022 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 16:34:32.872238 INFO: [APUAPC] D5_APC_3: 0x0
9958 16:34:32.875690 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 16:34:32.879221 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 16:34:32.882349 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 16:34:32.885372 INFO: [APUAPC] D6_APC_3: 0x0
9962 16:34:32.889180 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 16:34:32.891784 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 16:34:32.895618 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 16:34:32.898809 INFO: [APUAPC] D7_APC_3: 0x0
9966 16:34:32.902004 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 16:34:32.905299 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 16:34:32.908393 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 16:34:32.911584 INFO: [APUAPC] D8_APC_3: 0x0
9970 16:34:32.914873 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 16:34:32.918000 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 16:34:32.921708 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 16:34:32.924912 INFO: [APUAPC] D9_APC_3: 0x0
9974 16:34:32.928209 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 16:34:32.931636 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 16:34:32.934683 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 16:34:32.937876 INFO: [APUAPC] D10_APC_3: 0x0
9978 16:34:32.941563 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 16:34:32.944770 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 16:34:32.948205 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 16:34:32.950943 INFO: [APUAPC] D11_APC_3: 0x0
9982 16:34:32.954204 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 16:34:32.957820 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 16:34:32.960905 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 16:34:32.964269 INFO: [APUAPC] D12_APC_3: 0x0
9986 16:34:32.968120 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 16:34:32.970892 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 16:34:32.974347 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 16:34:32.977969 INFO: [APUAPC] D13_APC_3: 0x0
9990 16:34:32.980778 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 16:34:32.984286 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 16:34:32.990631 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 16:34:32.991046 INFO: [APUAPC] D14_APC_3: 0x0
9994 16:34:32.994022 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 16:34:33.000795 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 16:34:33.003971 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 16:34:33.004387 INFO: [APUAPC] D15_APC_3: 0x0
9998 16:34:33.007068 INFO: [APUAPC] APC_CON: 0x4
9999 16:34:33.010450 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 16:34:33.013759 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 16:34:33.016851 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 16:34:33.020064 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 16:34:33.023396 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 16:34:33.026622 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 16:34:33.030441 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 16:34:33.033645 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 16:34:33.034073 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 16:34:33.036950 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 16:34:33.040067 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 16:34:33.043213 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 16:34:33.046939 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 16:34:33.050260 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 16:34:33.053347 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 16:34:33.056360 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 16:34:33.059980 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 16:34:33.062943 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 16:34:33.066542 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 16:34:33.069765 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 16:34:33.070338 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 16:34:33.072810 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 16:34:33.076725 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 16:34:33.079615 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 16:34:33.083107 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 16:34:33.086018 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 16:34:33.089840 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 16:34:33.092985 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 16:34:33.096015 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 16:34:33.099526 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 16:34:33.102595 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 16:34:33.105913 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 16:34:33.109440 INFO: [NOCDAPC] APC_CON: 0x4
10032 16:34:33.112267 INFO: [APUAPC] set_apusys_apc done
10033 16:34:33.115547 INFO: [DEVAPC] devapc_init done
10034 16:34:33.118983 INFO: GICv3 without legacy support detected.
10035 16:34:33.122075 INFO: ARM GICv3 driver initialized in EL3
10036 16:34:33.125725 INFO: Maximum SPI INTID supported: 639
10037 16:34:33.132184 INFO: BL31: Initializing runtime services
10038 16:34:33.135448 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 16:34:33.139332 INFO: SPM: enable CPC mode
10040 16:34:33.145779 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 16:34:33.148783 INFO: BL31: Preparing for EL3 exit to normal world
10042 16:34:33.152001 INFO: Entry point address = 0x80000000
10043 16:34:33.155149 INFO: SPSR = 0x8
10044 16:34:33.160146
10045 16:34:33.160696
10046 16:34:33.161336
10047 16:34:33.163592 Starting depthcharge on Spherion...
10048 16:34:33.164012
10049 16:34:33.164335 Wipe memory regions:
10050 16:34:33.164640
10051 16:34:33.166917 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10052 16:34:33.167417 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10053 16:34:33.167814 Setting prompt string to ['asurada:']
10054 16:34:33.168209 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10055 16:34:33.168935 [0x00000040000000, 0x00000054600000)
10056 16:34:33.288853
10057 16:34:33.289005 [0x00000054660000, 0x00000080000000)
10058 16:34:33.549363
10059 16:34:33.549870 [0x000000821a7280, 0x000000ffe64000)
10060 16:34:34.293095
10061 16:34:34.293652 [0x00000100000000, 0x00000240000000)
10062 16:34:36.180322
10063 16:34:36.183971 Initializing XHCI USB controller at 0x11200000.
10064 16:34:37.222723
10065 16:34:37.225387 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 16:34:37.225804
10067 16:34:37.226126
10068 16:34:37.226891 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 16:34:37.328033 asurada: tftpboot 192.168.201.1 14396153/tftp-deploy-iw5mv4ot/kernel/image.itb 14396153/tftp-deploy-iw5mv4ot/kernel/cmdline
10071 16:34:37.328634 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 16:34:37.329034 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10073 16:34:37.333923 tftpboot 192.168.201.1 14396153/tftp-deploy-iw5mv4ot/kernel/image.itp-deploy-iw5mv4ot/kernel/cmdline
10074 16:34:37.334344
10075 16:34:37.334662 Waiting for link
10076 16:34:37.492380
10077 16:34:37.492886 R8152: Initializing
10078 16:34:37.493215
10079 16:34:37.495780 Version 6 (ocp_data = 5c30)
10080 16:34:37.496192
10081 16:34:37.498696 R8152: Done initializing
10082 16:34:37.499116
10083 16:34:37.499442 Adding net device
10084 16:34:39.431654
10085 16:34:39.431803 done.
10086 16:34:39.431878
10087 16:34:39.431940 MAC: 00:24:32:30:7c:7b
10088 16:34:39.431998
10089 16:34:39.435398 Sending DHCP discover... done.
10090 16:34:39.435509
10091 16:34:39.438552 Waiting for reply... done.
10092 16:34:39.438649
10093 16:34:39.441530 Sending DHCP request... done.
10094 16:34:39.441646
10095 16:34:39.447064 Waiting for reply... done.
10096 16:34:39.447156
10097 16:34:39.447221 My ip is 192.168.201.14
10098 16:34:39.447282
10099 16:34:39.450238 The DHCP server ip is 192.168.201.1
10100 16:34:39.450341
10101 16:34:39.456956 TFTP server IP predefined by user: 192.168.201.1
10102 16:34:39.457072
10103 16:34:39.463371 Bootfile predefined by user: 14396153/tftp-deploy-iw5mv4ot/kernel/image.itb
10104 16:34:39.463458
10105 16:34:39.466708 Sending tftp read request... done.
10106 16:34:39.466801
10107 16:34:39.470839 Waiting for the transfer...
10108 16:34:39.470918
10109 16:34:40.031292 00000000 ################################################################
10110 16:34:40.031478
10111 16:34:40.595466 00080000 ################################################################
10112 16:34:40.595636
10113 16:34:41.135715 00100000 ################################################################
10114 16:34:41.135867
10115 16:34:41.667748 00180000 ################################################################
10116 16:34:41.667898
10117 16:34:42.197851 00200000 ################################################################
10118 16:34:42.198002
10119 16:34:42.754216 00280000 ################################################################
10120 16:34:42.754364
10121 16:34:43.290012 00300000 ################################################################
10122 16:34:43.290154
10123 16:34:43.829416 00380000 ################################################################
10124 16:34:43.829593
10125 16:34:44.374714 00400000 ################################################################
10126 16:34:44.374865
10127 16:34:44.924068 00480000 ################################################################
10128 16:34:44.924257
10129 16:34:45.474728 00500000 ################################################################
10130 16:34:45.474874
10131 16:34:46.022412 00580000 ################################################################
10132 16:34:46.022553
10133 16:34:46.565083 00600000 ################################################################
10134 16:34:46.565314
10135 16:34:47.088516 00680000 ################################################################
10136 16:34:47.088721
10137 16:34:47.617132 00700000 ################################################################
10138 16:34:47.617380
10139 16:34:48.185616 00780000 ################################################################
10140 16:34:48.185790
10141 16:34:48.721445 00800000 ################################################################
10142 16:34:48.721593
10143 16:34:49.247646 00880000 ################################################################
10144 16:34:49.247787
10145 16:34:49.793075 00900000 ################################################################
10146 16:34:49.793246
10147 16:34:50.349820 00980000 ################################################################
10148 16:34:50.349964
10149 16:34:50.888236 00a00000 ################################################################
10150 16:34:50.888439
10151 16:34:51.426433 00a80000 ################################################################
10152 16:34:51.426575
10153 16:34:52.012415 00b00000 ################################################################
10154 16:34:52.012559
10155 16:34:52.633407 00b80000 ################################################################
10156 16:34:52.633558
10157 16:34:53.248112 00c00000 ################################################################
10158 16:34:53.248580
10159 16:34:53.894571 00c80000 ################################################################
10160 16:34:53.895078
10161 16:34:54.540026 00d00000 ################################################################
10162 16:34:54.540746
10163 16:34:55.137154 00d80000 ################################################################
10164 16:34:55.137367
10165 16:34:55.711543 00e00000 ################################################################
10166 16:34:55.711695
10167 16:34:56.352123 00e80000 ################################################################
10168 16:34:56.352265
10169 16:34:56.940874 00f00000 ################################################################
10170 16:34:56.941019
10171 16:34:57.546384 00f80000 ################################################################
10172 16:34:57.546907
10173 16:34:58.217684 01000000 ################################################################
10174 16:34:58.218217
10175 16:34:58.768012 01080000 ################################################################
10176 16:34:58.768187
10177 16:34:59.399006 01100000 ################################################################
10178 16:34:59.399180
10179 16:34:59.967688 01180000 ################################################################
10180 16:34:59.967824
10181 16:35:00.529310 01200000 ################################################################
10182 16:35:00.529440
10183 16:35:01.094962 01280000 ################################################################
10184 16:35:01.095108
10185 16:35:01.622506 01300000 ################################################################
10186 16:35:01.622703
10187 16:35:02.150239 01380000 ################################################################
10188 16:35:02.150418
10189 16:35:02.678990 01400000 ################################################################
10190 16:35:02.679157
10191 16:35:03.204072 01480000 ################################################################
10192 16:35:03.204231
10193 16:35:03.734613 01500000 ################################################################
10194 16:35:03.734785
10195 16:35:04.272372 01580000 ################################################################
10196 16:35:04.272525
10197 16:35:04.807589 01600000 ################################################################
10198 16:35:04.807763
10199 16:35:05.332903 01680000 ################################################################
10200 16:35:05.333053
10201 16:35:05.866490 01700000 ################################################################
10202 16:35:05.866677
10203 16:35:06.397281 01780000 ################################################################
10204 16:35:06.397440
10205 16:35:06.922584 01800000 ################################################################
10206 16:35:06.922745
10207 16:35:07.446493 01880000 ################################################################
10208 16:35:07.446675
10209 16:35:07.984840 01900000 ################################################################
10210 16:35:07.984999
10211 16:35:08.510901 01980000 ################################################################
10212 16:35:08.511049
10213 16:35:09.038196 01a00000 ################################################################
10214 16:35:09.038346
10215 16:35:09.554943 01a80000 ################################################################
10216 16:35:09.555099
10217 16:35:10.077119 01b00000 ################################################################
10218 16:35:10.077298
10219 16:35:10.607348 01b80000 ################################################################
10220 16:35:10.607515
10221 16:35:11.121839 01c00000 ################################################################
10222 16:35:11.121990
10223 16:35:11.632052 01c80000 ################################################################
10224 16:35:11.632193
10225 16:35:12.147574 01d00000 ################################################################
10226 16:35:12.147728
10227 16:35:12.662654 01d80000 ################################################################
10228 16:35:12.662834
10229 16:35:13.104927 01e00000 ######################################################## done.
10230 16:35:13.105073
10231 16:35:13.108327 The bootfile was 31909630 bytes long.
10232 16:35:13.108409
10233 16:35:13.111839 Sending tftp read request... done.
10234 16:35:13.111943
10235 16:35:13.115163 Waiting for the transfer...
10236 16:35:13.115244
10237 16:35:13.115308 00000000 # done.
10238 16:35:13.115379
10239 16:35:13.124687 Command line loaded dynamically from TFTP file: 14396153/tftp-deploy-iw5mv4ot/kernel/cmdline
10240 16:35:13.124774
10241 16:35:13.144724 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10242 16:35:13.147994
10243 16:35:13.148101 Loading FIT.
10244 16:35:13.148194
10245 16:35:13.151032 Image ramdisk-1 has 18731582 bytes.
10246 16:35:13.151115
10247 16:35:13.154737 Image fdt-1 has 47258 bytes.
10248 16:35:13.154820
10249 16:35:13.157848 Image kernel-1 has 13128753 bytes.
10250 16:35:13.157930
10251 16:35:13.164204 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10252 16:35:13.164288
10253 16:35:13.184284 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10254 16:35:13.184401
10255 16:35:13.187569 Choosing best match conf-1 for compat google,spherion-rev2.
10256 16:35:13.192616
10257 16:35:13.197041 Connected to device vid:did:rid of 1ae0:0028:00
10258 16:35:13.203824
10259 16:35:13.207374 tpm_get_response: command 0x17b, return code 0x0
10260 16:35:13.207478
10261 16:35:13.210798 ec_init: CrosEC protocol v3 supported (256, 248)
10262 16:35:13.214920
10263 16:35:13.217949 tpm_cleanup: add release locality here.
10264 16:35:13.218023
10265 16:35:13.218083 Shutting down all USB controllers.
10266 16:35:13.221414
10267 16:35:13.221486 Removing current net device
10268 16:35:13.221546
10269 16:35:13.228189 Exiting depthcharge with code 4 at timestamp: 69262207
10270 16:35:13.228299
10271 16:35:13.231228 LZMA decompressing kernel-1 to 0x821a6718
10272 16:35:13.231299
10273 16:35:13.234387 LZMA decompressing kernel-1 to 0x40000000
10274 16:35:14.851681
10275 16:35:14.851837 jumping to kernel
10276 16:35:14.852492 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10277 16:35:14.852628 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10278 16:35:14.852740 Setting prompt string to ['Linux version [0-9]']
10279 16:35:14.852847 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10280 16:35:14.852960 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10281 16:35:14.933312
10282 16:35:14.936730 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10283 16:35:14.940138 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10284 16:35:14.940267 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10285 16:35:14.940366 Setting prompt string to []
10286 16:35:14.940471 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10287 16:35:14.940571 Using line separator: #'\n'#
10288 16:35:14.940656 No login prompt set.
10289 16:35:14.940721 Parsing kernel messages
10290 16:35:14.940777 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10291 16:35:14.940947 [login-action] Waiting for messages, (timeout 00:03:45)
10292 16:35:14.941041 Waiting using forced prompt support (timeout 00:01:52)
10293 16:35:14.960086 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10294 16:35:14.963325 [ 0.000000] random: crng init done
10295 16:35:14.969472 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 16:35:14.972990 [ 0.000000] efi: UEFI not found.
10297 16:35:14.980063 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 16:35:14.986206 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 16:35:14.996053 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 16:35:15.006091 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 16:35:15.013121 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10302 16:35:15.019537 [ 0.000000] printk: bootconsole [mtk8250] enabled
10303 16:35:15.026541 [ 0.000000] NUMA: No NUMA configuration found
10304 16:35:15.032865 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10305 16:35:15.036008 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10306 16:35:15.039698 [ 0.000000] Zone ranges:
10307 16:35:15.046071 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10308 16:35:15.049789 [ 0.000000] DMA32 empty
10309 16:35:15.056132 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10310 16:35:15.059805 [ 0.000000] Movable zone start for each node
10311 16:35:15.063002 [ 0.000000] Early memory node ranges
10312 16:35:15.069238 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10313 16:35:15.076089 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10314 16:35:15.082775 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10315 16:35:15.085858 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10316 16:35:15.092925 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10317 16:35:15.099443 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10318 16:35:15.157949 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10319 16:35:15.164860 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10320 16:35:15.171019 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10321 16:35:15.174923 [ 0.000000] psci: probing for conduit method from DT.
10322 16:35:15.181100 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10323 16:35:15.184265 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10324 16:35:15.191077 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10325 16:35:15.194663 [ 0.000000] psci: SMC Calling Convention v1.2
10326 16:35:15.200975 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10327 16:35:15.204429 [ 0.000000] Detected VIPT I-cache on CPU0
10328 16:35:15.210751 [ 0.000000] CPU features: detected: GIC system register CPU interface
10329 16:35:15.217621 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10330 16:35:15.224634 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10331 16:35:15.230751 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10332 16:35:15.237439 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10333 16:35:15.247255 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10334 16:35:15.250523 [ 0.000000] alternatives: applying boot alternatives
10335 16:35:15.257113 [ 0.000000] Fallback order for Node 0: 0
10336 16:35:15.263890 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10337 16:35:15.267066 [ 0.000000] Policy zone: Normal
10338 16:35:15.290312 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10339 16:35:15.300577 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10340 16:35:15.310814 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10341 16:35:15.320817 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10342 16:35:15.327759 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10343 16:35:15.330933 <6>[ 0.000000] software IO TLB: area num 8.
10344 16:35:15.388064 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10345 16:35:15.537621 <6>[ 0.000000] Memory: 7945764K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407004K reserved, 32768K cma-reserved)
10346 16:35:15.544203 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10347 16:35:15.551079 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10348 16:35:15.554110 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10349 16:35:15.560852 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10350 16:35:15.567563 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10351 16:35:15.570486 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10352 16:35:15.581144 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10353 16:35:15.587414 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10354 16:35:15.590455 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10355 16:35:15.598385 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10356 16:35:15.602010 <6>[ 0.000000] GICv3: 608 SPIs implemented
10357 16:35:15.608762 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10358 16:35:15.611986 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10359 16:35:15.615202 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10360 16:35:15.625114 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10361 16:35:15.634748 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10362 16:35:15.647944 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10363 16:35:15.654869 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10364 16:35:15.663997 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10365 16:35:15.677471 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10366 16:35:15.683840 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10367 16:35:15.690422 <6>[ 0.009186] Console: colour dummy device 80x25
10368 16:35:15.700747 <6>[ 0.013915] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10369 16:35:15.704216 <6>[ 0.024356] pid_max: default: 32768 minimum: 301
10370 16:35:15.710837 <6>[ 0.029228] LSM: Security Framework initializing
10371 16:35:15.717552 <6>[ 0.034167] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 16:35:15.727422 <6>[ 0.041981] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 16:35:15.733746 <6>[ 0.051407] cblist_init_generic: Setting adjustable number of callback queues.
10374 16:35:15.740595 <6>[ 0.058898] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 16:35:15.750721 <6>[ 0.065237] cblist_init_generic: Setting adjustable number of callback queues.
10376 16:35:15.753766 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 16:35:15.760548 <6>[ 0.079109] rcu: Hierarchical SRCU implementation.
10378 16:35:15.767219 <6>[ 0.084124] rcu: Max phase no-delay instances is 1000.
10379 16:35:15.773558 <6>[ 0.091158] EFI services will not be available.
10380 16:35:15.777345 <6>[ 0.096111] smp: Bringing up secondary CPUs ...
10381 16:35:15.785215 <6>[ 0.101160] Detected VIPT I-cache on CPU1
10382 16:35:15.791682 <6>[ 0.101233] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10383 16:35:15.798344 <6>[ 0.101265] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10384 16:35:15.801501 <6>[ 0.101596] Detected VIPT I-cache on CPU2
10385 16:35:15.808247 <6>[ 0.101648] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10386 16:35:15.817921 <6>[ 0.101664] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10387 16:35:15.821131 <6>[ 0.101920] Detected VIPT I-cache on CPU3
10388 16:35:15.827869 <6>[ 0.101970] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10389 16:35:15.834696 <6>[ 0.101983] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10390 16:35:15.837932 <6>[ 0.102287] CPU features: detected: Spectre-v4
10391 16:35:15.844632 <6>[ 0.102292] CPU features: detected: Spectre-BHB
10392 16:35:15.847789 <6>[ 0.102297] Detected PIPT I-cache on CPU4
10393 16:35:15.854717 <6>[ 0.102357] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10394 16:35:15.860924 <6>[ 0.102373] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10395 16:35:15.867575 <6>[ 0.102662] Detected PIPT I-cache on CPU5
10396 16:35:15.874379 <6>[ 0.102725] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10397 16:35:15.880761 <6>[ 0.102741] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10398 16:35:15.883994 <6>[ 0.103022] Detected PIPT I-cache on CPU6
10399 16:35:15.890697 <6>[ 0.103088] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10400 16:35:15.897529 <6>[ 0.103104] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10401 16:35:15.903910 <6>[ 0.103399] Detected PIPT I-cache on CPU7
10402 16:35:15.910577 <6>[ 0.103464] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10403 16:35:15.917721 <6>[ 0.103480] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10404 16:35:15.920686 <6>[ 0.103526] smp: Brought up 1 node, 8 CPUs
10405 16:35:15.926963 <6>[ 0.244865] SMP: Total of 8 processors activated.
10406 16:35:15.930929 <6>[ 0.249786] CPU features: detected: 32-bit EL0 Support
10407 16:35:15.940284 <6>[ 0.255150] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10408 16:35:15.947062 <6>[ 0.263950] CPU features: detected: Common not Private translations
10409 16:35:15.953990 <6>[ 0.270426] CPU features: detected: CRC32 instructions
10410 16:35:15.957064 <6>[ 0.275778] CPU features: detected: RCpc load-acquire (LDAPR)
10411 16:35:15.963511 <6>[ 0.281775] CPU features: detected: LSE atomic instructions
10412 16:35:15.970380 <6>[ 0.287592] CPU features: detected: Privileged Access Never
10413 16:35:15.977146 <6>[ 0.293408] CPU features: detected: RAS Extension Support
10414 16:35:15.983496 <6>[ 0.299051] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10415 16:35:15.986630 <6>[ 0.306271] CPU: All CPU(s) started at EL2
10416 16:35:15.993667 <6>[ 0.310588] alternatives: applying system-wide alternatives
10417 16:35:16.002553 <6>[ 0.321474] devtmpfs: initialized
10418 16:35:16.015238 <6>[ 0.330290] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10419 16:35:16.025145 <6>[ 0.340251] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10420 16:35:16.031716 <6>[ 0.348269] pinctrl core: initialized pinctrl subsystem
10421 16:35:16.034723 <6>[ 0.354952] DMI not present or invalid.
10422 16:35:16.041790 <6>[ 0.359358] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10423 16:35:16.051157 <6>[ 0.366220] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10424 16:35:16.057965 <6>[ 0.373806] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10425 16:35:16.068168 <6>[ 0.382023] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10426 16:35:16.071003 <6>[ 0.390263] audit: initializing netlink subsys (disabled)
10427 16:35:16.080939 <5>[ 0.395957] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10428 16:35:16.087800 <6>[ 0.396678] thermal_sys: Registered thermal governor 'step_wise'
10429 16:35:16.094157 <6>[ 0.403922] thermal_sys: Registered thermal governor 'power_allocator'
10430 16:35:16.097849 <6>[ 0.410175] cpuidle: using governor menu
10431 16:35:16.104577 <6>[ 0.421136] NET: Registered PF_QIPCRTR protocol family
10432 16:35:16.111214 <6>[ 0.426623] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10433 16:35:16.114290 <6>[ 0.433726] ASID allocator initialised with 32768 entries
10434 16:35:16.121606 <6>[ 0.440313] Serial: AMBA PL011 UART driver
10435 16:35:16.130721 <4>[ 0.449162] Trying to register duplicate clock ID: 134
10436 16:35:16.189079 <6>[ 0.510919] KASLR enabled
10437 16:35:16.203402 <6>[ 0.518648] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10438 16:35:16.210438 <6>[ 0.525661] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10439 16:35:16.217179 <6>[ 0.532151] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10440 16:35:16.223338 <6>[ 0.539156] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10441 16:35:16.229835 <6>[ 0.545646] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10442 16:35:16.236550 <6>[ 0.552652] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10443 16:35:16.243352 <6>[ 0.559141] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10444 16:35:16.250220 <6>[ 0.566143] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10445 16:35:16.253140 <6>[ 0.573666] ACPI: Interpreter disabled.
10446 16:35:16.261457 <6>[ 0.580106] iommu: Default domain type: Translated
10447 16:35:16.268212 <6>[ 0.585219] iommu: DMA domain TLB invalidation policy: strict mode
10448 16:35:16.271749 <5>[ 0.591880] SCSI subsystem initialized
10449 16:35:16.277926 <6>[ 0.596045] usbcore: registered new interface driver usbfs
10450 16:35:16.284600 <6>[ 0.601775] usbcore: registered new interface driver hub
10451 16:35:16.288056 <6>[ 0.607325] usbcore: registered new device driver usb
10452 16:35:16.294893 <6>[ 0.613424] pps_core: LinuxPPS API ver. 1 registered
10453 16:35:16.304916 <6>[ 0.618616] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10454 16:35:16.308165 <6>[ 0.627960] PTP clock support registered
10455 16:35:16.311230 <6>[ 0.632204] EDAC MC: Ver: 3.0.0
10456 16:35:16.318738 <6>[ 0.637354] FPGA manager framework
10457 16:35:16.325548 <6>[ 0.641038] Advanced Linux Sound Architecture Driver Initialized.
10458 16:35:16.328705 <6>[ 0.647812] vgaarb: loaded
10459 16:35:16.335098 <6>[ 0.650970] clocksource: Switched to clocksource arch_sys_counter
10460 16:35:16.338775 <5>[ 0.657415] VFS: Disk quotas dquot_6.6.0
10461 16:35:16.345115 <6>[ 0.661603] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10462 16:35:16.348396 <6>[ 0.668794] pnp: PnP ACPI: disabled
10463 16:35:16.356955 <6>[ 0.675559] NET: Registered PF_INET protocol family
10464 16:35:16.366863 <6>[ 0.681164] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10465 16:35:16.377949 <6>[ 0.693418] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10466 16:35:16.388126 <6>[ 0.702232] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10467 16:35:16.395129 <6>[ 0.710199] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10468 16:35:16.404718 <6>[ 0.718898] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10469 16:35:16.411682 <6>[ 0.728617] TCP: Hash tables configured (established 65536 bind 65536)
10470 16:35:16.417732 <6>[ 0.735480] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 16:35:16.427875 <6>[ 0.742681] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10472 16:35:16.434393 <6>[ 0.750383] NET: Registered PF_UNIX/PF_LOCAL protocol family
10473 16:35:16.440960 <6>[ 0.756539] RPC: Registered named UNIX socket transport module.
10474 16:35:16.444060 <6>[ 0.762696] RPC: Registered udp transport module.
10475 16:35:16.450619 <6>[ 0.767632] RPC: Registered tcp transport module.
10476 16:35:16.457325 <6>[ 0.772564] RPC: Registered tcp NFSv4.1 backchannel transport module.
10477 16:35:16.460628 <6>[ 0.779231] PCI: CLS 0 bytes, default 64
10478 16:35:16.463697 <6>[ 0.783560] Unpacking initramfs...
10479 16:35:16.480443 <6>[ 0.795472] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10480 16:35:16.490512 <6>[ 0.804124] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10481 16:35:16.493534 <6>[ 0.812951] kvm [1]: IPA Size Limit: 40 bits
10482 16:35:16.500218 <6>[ 0.817480] kvm [1]: GICv3: no GICV resource entry
10483 16:35:16.503947 <6>[ 0.822500] kvm [1]: disabling GICv2 emulation
10484 16:35:16.510420 <6>[ 0.827189] kvm [1]: GIC system register CPU interface enabled
10485 16:35:16.513405 <6>[ 0.833354] kvm [1]: vgic interrupt IRQ18
10486 16:35:16.520327 <6>[ 0.837735] kvm [1]: VHE mode initialized successfully
10487 16:35:16.526634 <5>[ 0.844126] Initialise system trusted keyrings
10488 16:35:16.533458 <6>[ 0.848921] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10489 16:35:16.540310 <6>[ 0.858886] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10490 16:35:16.547265 <5>[ 0.865256] NFS: Registering the id_resolver key type
10491 16:35:16.550701 <5>[ 0.870553] Key type id_resolver registered
10492 16:35:16.556826 <5>[ 0.874972] Key type id_legacy registered
10493 16:35:16.563854 <6>[ 0.879253] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10494 16:35:16.570697 <6>[ 0.886175] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10495 16:35:16.577073 <6>[ 0.893874] 9p: Installing v9fs 9p2000 file system support
10496 16:35:16.614209 <5>[ 0.932278] Key type asymmetric registered
10497 16:35:16.617169 <5>[ 0.936608] Asymmetric key parser 'x509' registered
10498 16:35:16.627037 <6>[ 0.941751] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10499 16:35:16.630898 <6>[ 0.949365] io scheduler mq-deadline registered
10500 16:35:16.634070 <6>[ 0.954127] io scheduler kyber registered
10501 16:35:16.653084 <6>[ 0.971241] EINJ: ACPI disabled.
10502 16:35:16.685534 <4>[ 0.997428] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 16:35:16.695540 <4>[ 1.008073] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 16:35:16.710824 <6>[ 1.029061] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10505 16:35:16.718827 <6>[ 1.037037] printk: console [ttyS0] disabled
10506 16:35:16.746432 <6>[ 1.061663] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10507 16:35:16.753225 <6>[ 1.071137] printk: console [ttyS0] enabled
10508 16:35:16.756393 <6>[ 1.071137] printk: console [ttyS0] enabled
10509 16:35:16.762994 <6>[ 1.080031] printk: bootconsole [mtk8250] disabled
10510 16:35:16.766635 <6>[ 1.080031] printk: bootconsole [mtk8250] disabled
10511 16:35:16.773046 <6>[ 1.091081] SuperH (H)SCI(F) driver initialized
10512 16:35:16.776311 <6>[ 1.096335] msm_serial: driver initialized
10513 16:35:16.790466 <6>[ 1.105264] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10514 16:35:16.800575 <6>[ 1.113809] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10515 16:35:16.807111 <6>[ 1.122352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10516 16:35:16.816573 <6>[ 1.130991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10517 16:35:16.826798 <6>[ 1.139698] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10518 16:35:16.833332 <6>[ 1.148418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10519 16:35:16.843258 <6>[ 1.156959] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10520 16:35:16.849865 <6>[ 1.165766] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10521 16:35:16.860109 <6>[ 1.174309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10522 16:35:16.871676 <6>[ 1.189736] loop: module loaded
10523 16:35:16.877975 <6>[ 1.195687] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10524 16:35:16.900901 <4>[ 1.218925] mtk-pmic-keys: Failed to locate of_node [id: -1]
10525 16:35:16.906994 <6>[ 1.225642] megasas: 07.719.03.00-rc1
10526 16:35:16.916931 <6>[ 1.235278] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10527 16:35:16.926081 <6>[ 1.242351] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10528 16:35:16.940162 <6>[ 1.258842] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10529 16:35:16.996253 <6>[ 1.308370] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10530 16:35:17.257830 <6>[ 1.576896] Freeing initrd memory: 18292K
10531 16:35:17.269617 <6>[ 1.588536] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10532 16:35:17.280492 <6>[ 1.599507] tun: Universal TUN/TAP device driver, 1.6
10533 16:35:17.284261 <6>[ 1.605573] thunder_xcv, ver 1.0
10534 16:35:17.287273 <6>[ 1.609077] thunder_bgx, ver 1.0
10535 16:35:17.290379 <6>[ 1.612572] nicpf, ver 1.0
10536 16:35:17.301274 <6>[ 1.616596] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10537 16:35:17.304494 <6>[ 1.624072] hns3: Copyright (c) 2017 Huawei Corporation.
10538 16:35:17.311003 <6>[ 1.629659] hclge is initializing
10539 16:35:17.314160 <6>[ 1.633239] e1000: Intel(R) PRO/1000 Network Driver
10540 16:35:17.321092 <6>[ 1.638368] e1000: Copyright (c) 1999-2006 Intel Corporation.
10541 16:35:17.324314 <6>[ 1.644383] e1000e: Intel(R) PRO/1000 Network Driver
10542 16:35:17.331339 <6>[ 1.649598] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10543 16:35:17.337603 <6>[ 1.655782] igb: Intel(R) Gigabit Ethernet Network Driver
10544 16:35:17.344569 <6>[ 1.661431] igb: Copyright (c) 2007-2014 Intel Corporation.
10545 16:35:17.351156 <6>[ 1.667268] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10546 16:35:17.357446 <6>[ 1.673786] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10547 16:35:17.361120 <6>[ 1.680244] sky2: driver version 1.30
10548 16:35:17.367333 <6>[ 1.685183] usbcore: registered new device driver r8152-cfgselector
10549 16:35:17.374383 <6>[ 1.691718] usbcore: registered new interface driver r8152
10550 16:35:17.380535 <6>[ 1.697537] VFIO - User Level meta-driver version: 0.3
10551 16:35:17.387561 <6>[ 1.705778] usbcore: registered new interface driver usb-storage
10552 16:35:17.393984 <6>[ 1.712225] usbcore: registered new device driver onboard-usb-hub
10553 16:35:17.402643 <6>[ 1.721393] mt6397-rtc mt6359-rtc: registered as rtc0
10554 16:35:17.412485 <6>[ 1.726859] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:35:17 UTC (1718642117)
10555 16:35:17.416024 <6>[ 1.736426] i2c_dev: i2c /dev entries driver
10556 16:35:17.429641 <4>[ 1.748526] cpu cpu0: supply cpu not found, using dummy regulator
10557 16:35:17.436585 <4>[ 1.754951] cpu cpu1: supply cpu not found, using dummy regulator
10558 16:35:17.443440 <4>[ 1.761355] cpu cpu2: supply cpu not found, using dummy regulator
10559 16:35:17.449882 <4>[ 1.767775] cpu cpu3: supply cpu not found, using dummy regulator
10560 16:35:17.456381 <4>[ 1.774170] cpu cpu4: supply cpu not found, using dummy regulator
10561 16:35:17.462618 <4>[ 1.780566] cpu cpu5: supply cpu not found, using dummy regulator
10562 16:35:17.469459 <4>[ 1.786969] cpu cpu6: supply cpu not found, using dummy regulator
10563 16:35:17.476068 <4>[ 1.793366] cpu cpu7: supply cpu not found, using dummy regulator
10564 16:35:17.495269 <6>[ 1.813991] cpu cpu0: EM: created perf domain
10565 16:35:17.498451 <6>[ 1.818923] cpu cpu4: EM: created perf domain
10566 16:35:17.505660 <6>[ 1.824560] sdhci: Secure Digital Host Controller Interface driver
10567 16:35:17.512542 <6>[ 1.830993] sdhci: Copyright(c) Pierre Ossman
10568 16:35:17.518934 <6>[ 1.835948] Synopsys Designware Multimedia Card Interface Driver
10569 16:35:17.525671 <6>[ 1.842579] sdhci-pltfm: SDHCI platform and OF driver helper
10570 16:35:17.529156 <6>[ 1.842705] mmc0: CQHCI version 5.10
10571 16:35:17.535602 <6>[ 1.852909] ledtrig-cpu: registered to indicate activity on CPUs
10572 16:35:17.542282 <6>[ 1.860046] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10573 16:35:17.548670 <6>[ 1.867103] usbcore: registered new interface driver usbhid
10574 16:35:17.552497 <6>[ 1.872924] usbhid: USB HID core driver
10575 16:35:17.558965 <6>[ 1.877122] spi_master spi0: will run message pump with realtime priority
10576 16:35:17.603195 <6>[ 1.915404] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10577 16:35:17.621437 <6>[ 1.930465] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10578 16:35:17.625016 <6>[ 1.943784] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10579 16:35:17.633146 <6>[ 1.951340] cros-ec-spi spi0.0: Chrome EC device registered
10580 16:35:17.639341 <6>[ 1.957348] mmc0: Command Queue Engine enabled
10581 16:35:17.646025 <6>[ 1.962080] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10582 16:35:17.649154 <6>[ 1.969738] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 16:35:17.660137 <6>[ 1.978621] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10584 16:35:17.667135 <6>[ 1.986024] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10585 16:35:17.677160 <6>[ 1.990392] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10586 16:35:17.680346 <6>[ 1.991955] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10587 16:35:17.687268 <6>[ 2.001792] NET: Registered PF_PACKET protocol family
10588 16:35:17.693716 <6>[ 2.006401] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10589 16:35:17.696887 <6>[ 2.011182] 9pnet: Installing 9P2000 support
10590 16:35:17.703830 <5>[ 2.022162] Key type dns_resolver registered
10591 16:35:17.707039 <6>[ 2.027164] registered taskstats version 1
10592 16:35:17.713842 <5>[ 2.031542] Loading compiled-in X.509 certificates
10593 16:35:17.742277 <4>[ 2.054508] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 16:35:17.752272 <4>[ 2.065249] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 16:35:17.767652 <6>[ 2.085980] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10596 16:35:17.774194 <6>[ 2.092726] xhci-mtk 11200000.usb: xHCI Host Controller
10597 16:35:17.780840 <6>[ 2.098232] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10598 16:35:17.790399 <6>[ 2.106087] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10599 16:35:17.797139 <6>[ 2.115533] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10600 16:35:17.803585 <6>[ 2.121608] xhci-mtk 11200000.usb: xHCI Host Controller
10601 16:35:17.810732 <6>[ 2.127104] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10602 16:35:17.817082 <6>[ 2.134848] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10603 16:35:17.823899 <6>[ 2.142724] hub 1-0:1.0: USB hub found
10604 16:35:17.827365 <6>[ 2.146758] hub 1-0:1.0: 1 port detected
10605 16:35:17.837529 <6>[ 2.151089] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10606 16:35:17.840727 <6>[ 2.159897] hub 2-0:1.0: USB hub found
10607 16:35:17.843814 <6>[ 2.163932] hub 2-0:1.0: 1 port detected
10608 16:35:17.852872 <6>[ 2.171582] mtk-msdc 11f70000.mmc: Got CD GPIO
10609 16:35:17.867120 <6>[ 2.182736] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10610 16:35:17.877577 <6>[ 2.191123] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10611 16:35:17.883967 <6>[ 2.199464] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10612 16:35:17.894253 <6>[ 2.207805] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10613 16:35:17.900401 <6>[ 2.216144] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10614 16:35:17.910592 <6>[ 2.224484] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10615 16:35:17.917165 <6>[ 2.232823] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10616 16:35:17.927158 <6>[ 2.241161] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10617 16:35:17.933780 <6>[ 2.249499] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10618 16:35:17.943830 <6>[ 2.257837] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10619 16:35:17.950150 <6>[ 2.266175] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10620 16:35:17.960258 <6>[ 2.274520] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10621 16:35:17.966827 <6>[ 2.282858] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10622 16:35:17.976302 <6>[ 2.291195] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10623 16:35:17.983276 <6>[ 2.299533] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10624 16:35:17.989484 <6>[ 2.308238] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10625 16:35:17.996419 <6>[ 2.315404] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10626 16:35:18.003265 <6>[ 2.322163] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10627 16:35:18.013728 <6>[ 2.328979] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10628 16:35:18.019908 <6>[ 2.335901] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10629 16:35:18.026889 <6>[ 2.342781] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10630 16:35:18.036372 <6>[ 2.351929] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10631 16:35:18.046461 <6>[ 2.361048] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10632 16:35:18.056546 <6>[ 2.370342] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10633 16:35:18.066149 <6>[ 2.379809] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10634 16:35:18.076171 <6>[ 2.389280] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10635 16:35:18.083182 <6>[ 2.398400] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10636 16:35:18.093042 <6>[ 2.407866] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10637 16:35:18.102371 <6>[ 2.416988] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10638 16:35:18.112383 <6>[ 2.426283] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10639 16:35:18.122291 <6>[ 2.436443] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10640 16:35:18.132783 <6>[ 2.448096] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10641 16:35:18.140553 <6>[ 2.459371] Trying to probe devices needed for running init ...
10642 16:35:18.150739 <3>[ 2.466547] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10643 16:35:18.259482 <6>[ 2.575307] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10644 16:35:18.417998 <6>[ 2.737107] hub 1-1:1.0: USB hub found
10645 16:35:18.421729 <6>[ 2.741614] hub 1-1:1.0: 4 ports detected
10646 16:35:18.431721 <6>[ 2.750776] hub 1-1:1.0: USB hub found
10647 16:35:18.435412 <6>[ 2.755184] hub 1-1:1.0: 4 ports detected
10648 16:35:18.547793 <6>[ 2.863510] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10649 16:35:18.574397 <6>[ 2.893336] hub 2-1:1.0: USB hub found
10650 16:35:18.578020 <6>[ 2.897869] hub 2-1:1.0: 3 ports detected
10651 16:35:18.590241 <6>[ 2.909288] hub 2-1:1.0: USB hub found
10652 16:35:18.593474 <6>[ 2.913734] hub 2-1:1.0: 3 ports detected
10653 16:35:18.755303 <6>[ 3.071289] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10654 16:35:18.888008 <6>[ 3.207105] hub 1-1.4:1.0: USB hub found
10655 16:35:18.891156 <6>[ 3.211764] hub 1-1.4:1.0: 2 ports detected
10656 16:35:18.904251 <6>[ 3.223102] hub 1-1.4:1.0: USB hub found
10657 16:35:18.907379 <6>[ 3.227697] hub 1-1.4:1.0: 2 ports detected
10658 16:35:18.971718 <6>[ 3.287495] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10659 16:35:19.080325 <6>[ 3.395920] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10660 16:35:19.116575 <4>[ 3.432413] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10661 16:35:19.126694 <4>[ 3.441503] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10662 16:35:19.161589 <6>[ 3.480744] r8152 2-1.3:1.0 eth0: v1.12.13
10663 16:35:19.207098 <6>[ 3.523046] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10664 16:35:19.395347 <6>[ 3.711265] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10665 16:35:20.783165 <6>[ 5.072787] r8152 2-1.3:1.0 eth0: carrier on
10666 16:35:24.191716 <5>[ 5.103072] Sending DHCP requests .., OK
10667 16:35:24.198267 <6>[ 8.515522] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10668 16:35:24.201640 <6>[ 8.523836] IP-Config: Complete:
10669 16:35:24.214888 <6>[ 8.527333] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10670 16:35:24.221141 <6>[ 8.538042] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10671 16:35:24.227971 <6>[ 8.546659] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10672 16:35:24.234533 <6>[ 8.546668] nameserver0=192.168.201.1
10673 16:35:24.238250 <6>[ 8.558822] clk: Disabling unused clocks
10674 16:35:24.241214 <6>[ 8.564340] ALSA device list:
10675 16:35:24.248220 <6>[ 8.567624] No soundcards found.
10676 16:35:24.255680 <6>[ 8.575247] Freeing unused kernel memory: 8512K
10677 16:35:24.259273 <6>[ 8.580172] Run /init as init process
10678 16:35:24.268653 Loading, please wait...
10679 16:35:24.297367 Starting systemd-udevd version 252.22-1~deb12u1
10680 16:35:24.546609 <6>[ 8.862823] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10681 16:35:24.553000 <6>[ 8.863020] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10682 16:35:24.566960 <6>[ 8.883038] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10683 16:35:24.573213 <6>[ 8.890098] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10684 16:35:24.583647 <6>[ 8.891904] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10685 16:35:24.589996 <3>[ 8.903594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 16:35:24.600293 <6>[ 8.905229] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10687 16:35:24.606553 <6>[ 8.905248] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10688 16:35:24.616366 <4>[ 8.907052] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10689 16:35:24.623096 <6>[ 8.908124] remoteproc remoteproc0: scp is available
10690 16:35:24.626773 <6>[ 8.908230] remoteproc remoteproc0: powering up scp
10691 16:35:24.636467 <6>[ 8.908237] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10692 16:35:24.639442 <6>[ 8.908259] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10693 16:35:24.649492 <3>[ 8.915009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 16:35:24.656158 <6>[ 8.923997] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10695 16:35:24.665764 <3>[ 8.932135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 16:35:24.672549 <6>[ 8.941172] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10697 16:35:24.679319 <6>[ 8.942088] mc: Linux media interface: v0.10
10698 16:35:24.686015 <6>[ 8.947051] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10699 16:35:24.695670 <3>[ 8.951526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 16:35:24.702378 <3>[ 8.951546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 16:35:24.708632 <3>[ 8.951555] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 16:35:24.718783 <3>[ 8.951570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 16:35:24.725336 <3>[ 8.951574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 16:35:24.735273 <3>[ 8.952921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 16:35:24.741544 <4>[ 8.956554] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10706 16:35:24.749074 <6>[ 8.960107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10707 16:35:24.758659 <6>[ 8.960112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10708 16:35:24.766023 <6>[ 8.960117] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10709 16:35:24.772825 <4>[ 8.997233] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10710 16:35:24.779471 <6>[ 9.002550] Bluetooth: Core ver 2.22
10711 16:35:24.785751 <3>[ 9.025502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 16:35:24.792600 <6>[ 9.027179] NET: Registered PF_BLUETOOTH protocol family
10713 16:35:24.799011 <6>[ 9.031952] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10714 16:35:24.805939 <6>[ 9.032467] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10715 16:35:24.812704 <6>[ 9.032476] pci_bus 0000:00: root bus resource [bus 00-ff]
10716 16:35:24.818981 <6>[ 9.032484] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10717 16:35:24.828691 <6>[ 9.032489] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10718 16:35:24.835374 <6>[ 9.032537] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10719 16:35:24.842339 <6>[ 9.032559] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10720 16:35:24.845655 <6>[ 9.032658] pci 0000:00:00.0: supports D1 D2
10721 16:35:24.855623 <6>[ 9.032662] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 16:35:24.862001 <6>[ 9.034434] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10723 16:35:24.868790 <6>[ 9.034583] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10724 16:35:24.875076 <6>[ 9.034617] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10725 16:35:24.881924 <6>[ 9.034639] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10726 16:35:24.891884 <6>[ 9.034659] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10727 16:35:24.898477 <3>[ 9.034758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 16:35:24.908586 <3>[ 9.034765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 16:35:24.911619 <6>[ 9.034806] pci 0000:01:00.0: supports D1 D2
10730 16:35:24.917963 <6>[ 9.034816] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10731 16:35:24.928335 <6>[ 9.034864] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10732 16:35:24.934378 <6>[ 9.034864] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10733 16:35:24.940934 <6>[ 9.034890] remoteproc remoteproc0: remote processor scp is now up
10734 16:35:24.947941 <3>[ 9.034927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 16:35:24.957401 <3>[ 9.034932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 16:35:24.961100 <6>[ 9.038472] videodev: Linux video capture interface: v2.00
10737 16:35:24.967277 <6>[ 9.043064] Bluetooth: HCI device and connection manager initialized
10738 16:35:24.974381 <6>[ 9.047116] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10739 16:35:24.984315 <6>[ 9.047177] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10740 16:35:24.990655 <6>[ 9.047184] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10741 16:35:25.000850 <6>[ 9.047200] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10742 16:35:25.007466 <6>[ 9.047216] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10743 16:35:25.017183 <6>[ 9.047233] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10744 16:35:25.020451 <6>[ 9.047251] pci 0000:00:00.0: PCI bridge to [bus 01]
10745 16:35:25.030354 <6>[ 9.047262] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10746 16:35:25.033430 <6>[ 9.047569] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10747 16:35:25.043618 <3>[ 9.051130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 16:35:25.050129 <6>[ 9.054204] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10749 16:35:25.057097 <4>[ 9.057349] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10750 16:35:25.063410 <4>[ 9.057349] Fallback method does not support PEC.
10751 16:35:25.070246 <6>[ 9.057493] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10752 16:35:25.073348 <6>[ 9.059273] Bluetooth: HCI socket layer initialized
10753 16:35:25.083308 <3>[ 9.066520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 16:35:25.090072 <3>[ 9.074138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10755 16:35:25.096342 <6>[ 9.074334] Bluetooth: L2CAP socket layer initialized
10756 16:35:25.103267 <3>[ 9.082150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 16:35:25.113052 <6>[ 9.083223] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10758 16:35:25.119886 <6>[ 9.084453] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10759 16:35:25.126028 <6>[ 9.091272] Bluetooth: SCO socket layer initialized
10760 16:35:25.132920 <3>[ 9.095034] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10761 16:35:25.146152 <6>[ 9.095430] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10762 16:35:25.152767 <6>[ 9.095814] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10763 16:35:25.162456 <3>[ 9.098574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 16:35:25.172520 <6>[ 9.118995] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10765 16:35:25.189800 <6>[ 9.509547] usbcore: registered new interface driver btusb
10766 16:35:25.196589 <6>[ 9.512778] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10767 16:35:25.206233 <5>[ 9.519635] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10768 16:35:25.216102 <4>[ 9.522798] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10769 16:35:25.229561 <6>[ 9.525047] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10770 16:35:25.235912 <6>[ 9.525328] usbcore: registered new interface driver uvcvideo
10771 16:35:25.242768 <6>[ 9.542241] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10772 16:35:25.249497 <5>[ 9.547395] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10773 16:35:25.255721 <5>[ 9.547918] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10774 16:35:25.266121 <4>[ 9.548010] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10775 16:35:25.269147 <6>[ 9.548019] cfg80211: failed to load regulatory.db
10776 16:35:25.276015 <3>[ 9.553615] Bluetooth: hci0: Failed to load firmware file (-2)
10777 16:35:25.282273 <3>[ 9.601141] Bluetooth: hci0: Failed to set up firmware (-2)
10778 16:35:25.292322 <4>[ 9.606964] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10779 16:35:25.328747 <6>[ 9.644898] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10780 16:35:25.334989 <6>[ 9.652402] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10781 16:35:25.359700 <6>[ 9.679076] mt7921e 0000:01:00.0: ASIC revision: 79610010
10782 16:35:25.462629 <6>[ 9.778826] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10783 16:35:25.465538 <6>[ 9.778826]
10784 16:35:25.480303 Begin: Loading essential drivers ... done.
10785 16:35:25.484124 Begin: Running /scripts/init-premount ... done.
10786 16:35:25.490488 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10787 16:35:25.500381 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10788 16:35:25.503902 Device /sys/class/net/eth0 found
10789 16:35:25.503998 done.
10790 16:35:25.509995 Begin: Waiting up to 180 secs for any network device to become available ... done.
10791 16:35:25.563629 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10792 16:35:25.570610 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10793 16:35:25.576916 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10794 16:35:25.583154 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10795 16:35:25.590078 host : mt8192-asurada-spherion-r0-cbg-2
10796 16:35:25.596790 domain : lava-rack
10797 16:35:25.600206 rootserver: 192.168.201.1 rootpath:
10798 16:35:25.603120 filename :
10799 16:35:25.733207 <6>[ 10.049470] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10800 16:35:25.748696 done.
10801 16:35:25.756661 Begin: Running /scripts/nfs-bottom ... done.
10802 16:35:25.770131 Begin: Running /scripts/init-bottom ... done.
10803 16:35:27.121032 <6>[ 11.441089] NET: Registered PF_INET6 protocol family
10804 16:35:27.128602 <6>[ 11.448231] Segment Routing with IPv6
10805 16:35:27.131508 <6>[ 11.452249] In-situ OAM (IOAM) with IPv6
10806 16:35:27.303046 <30>[ 11.596716] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10807 16:35:27.309976 <30>[ 11.629823] systemd[1]: Detected architecture arm64.
10808 16:35:27.318381
10809 16:35:27.321236 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10810 16:35:27.321346
10811 16:35:27.348859 <30>[ 11.668823] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10812 16:35:28.407335 <30>[ 12.724089] systemd[1]: Queued start job for default target graphical.target.
10813 16:35:28.459701 <30>[ 12.776672] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10814 16:35:28.466353 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10815 16:35:28.488158 <30>[ 12.805126] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10816 16:35:28.498061 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10817 16:35:28.516656 <30>[ 12.832988] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10818 16:35:28.526023 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10819 16:35:28.544809 <30>[ 12.861500] systemd[1]: Created slice user.slice - User and Session Slice.
10820 16:35:28.551188 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10821 16:35:28.574761 <30>[ 12.888174] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10822 16:35:28.584638 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10823 16:35:28.602382 <30>[ 12.915515] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10824 16:35:28.608725 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10825 16:35:28.636785 <30>[ 12.943930] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10826 16:35:28.647075 <30>[ 12.963827] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10827 16:35:28.653895 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10828 16:35:28.671481 <30>[ 12.987660] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10829 16:35:28.677614 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10830 16:35:28.699034 <30>[ 13.015785] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10831 16:35:28.709160 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10832 16:35:28.723888 <30>[ 13.043702] systemd[1]: Reached target paths.target - Path Units.
10833 16:35:28.733340 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10834 16:35:28.751219 <30>[ 13.067741] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10835 16:35:28.757961 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10836 16:35:28.770971 <30>[ 13.091247] systemd[1]: Reached target slices.target - Slice Units.
10837 16:35:28.781026 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10838 16:35:28.795416 <30>[ 13.115655] systemd[1]: Reached target swap.target - Swaps.
10839 16:35:28.801956 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10840 16:35:28.822982 <30>[ 13.139701] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10841 16:35:28.833114 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10842 16:35:28.851255 <30>[ 13.167780] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10843 16:35:28.860872 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10844 16:35:28.882050 <30>[ 13.198550] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10845 16:35:28.891425 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10846 16:35:28.908277 <30>[ 13.224667] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10847 16:35:28.917796 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10848 16:35:28.935190 <30>[ 13.251909] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10849 16:35:28.942014 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10850 16:35:28.960299 <30>[ 13.276787] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10851 16:35:28.970283 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10852 16:35:28.989490 <30>[ 13.306113] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10853 16:35:28.999606 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10854 16:35:29.015301 <30>[ 13.331750] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10855 16:35:29.024591 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10856 16:35:29.090890 <30>[ 13.407826] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10857 16:35:29.097478 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10858 16:35:29.117638 <30>[ 13.434548] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10859 16:35:29.124503 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10860 16:35:29.148028 <30>[ 13.464370] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10861 16:35:29.153971 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10862 16:35:29.181620 <30>[ 13.491818] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10863 16:35:29.198118 <30>[ 13.514835] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10864 16:35:29.207619 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10865 16:35:29.275547 <30>[ 13.592107] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10866 16:35:29.285478 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10867 16:35:29.308316 <30>[ 13.625167] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10868 16:35:29.315170 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10869 16:35:29.340039 <30>[ 13.657074] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10870 16:35:29.350111 Starting [0;1;39mmodpr<6>[ 13.667668] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10871 16:35:29.356545 obe@drm.service[0m - Load Kernel Module drm...
10872 16:35:29.380701 <30>[ 13.697285] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10873 16:35:29.389968 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10874 16:35:29.412194 <30>[ 13.729156] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10875 16:35:29.419191 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10876 16:35:29.444702 <30>[ 13.761207] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10877 16:35:29.450995 Startin<6>[ 13.770406] fuse: init (API version 7.37)
10878 16:35:29.457875 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10879 16:35:29.484138 <30>[ 13.800939] systemd[1]: Starting systemd-journald.service - Journal Service...
10880 16:35:29.490911 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10881 16:35:29.523792 <30>[ 13.840635] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10882 16:35:29.530577 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10883 16:35:29.561736 <30>[ 13.875349] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10884 16:35:29.568791 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10885 16:35:29.620078 <30>[ 13.936595] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10886 16:35:29.629621 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10887 16:35:29.642145 <3>[ 13.958756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 16:35:29.654869 <30>[ 13.971758] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10889 16:35:29.661699 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10890 16:35:29.672332 <3>[ 13.989298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 16:35:29.687547 <30>[ 14.004300] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10892 16:35:29.694327 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10893 16:35:29.709391 <3>[ 14.025762] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 16:35:29.718931 <30>[ 14.035431] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10895 16:35:29.725791 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10896 16:35:29.737896 <3>[ 14.054929] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 16:35:29.748078 <30>[ 14.064557] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10898 16:35:29.754824 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10899 16:35:29.768452 <3>[ 14.084952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 16:35:29.777874 <30>[ 14.094640] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10901 16:35:29.788515 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10902 16:35:29.798730 <3>[ 14.113659] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 16:35:29.805277 <30>[ 14.123495] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10904 16:35:29.815544 <30>[ 14.131307] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10905 16:35:29.828593 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 14.143307] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 16:35:29.831693 onfigfs…[0m - Load Kernel Module configfs.
10907 16:35:29.855433 <30>[ 14.172069] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10908 16:35:29.861540 <30>[ 14.179874] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10909 16:35:29.875106 [[0;32m OK [<3>[ 14.188349] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 16:35:29.881565 0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10911 16:35:29.897198 <30>[ 14.217026] systemd[1]: modprobe@drm.service: Deactivated successfully.
10912 16:35:29.907085 <3>[ 14.219449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 16:35:29.914023 <30>[ 14.224700] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10914 16:35:29.924035 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10915 16:35:29.936484 <3>[ 14.253561] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 16:35:29.947062 <30>[ 14.264123] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10917 16:35:29.958059 <30>[ 14.272799] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10918 16:35:29.968117 [[0;32m OK [<3>[ 14.282613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 16:35:29.974358 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10920 16:35:29.991139 <30>[ 14.308075] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10921 16:35:29.998026 <3>[ 14.313032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 16:35:30.008038 <30>[ 14.315471] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10923 16:35:30.014548 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10924 16:35:30.029665 <3>[ 14.346283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 16:35:30.039513 <30>[ 14.356669] systemd[1]: modprobe@loop.service: Deactivated successfully.
10926 16:35:30.046439 <30>[ 14.364148] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10927 16:35:30.056683 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10928 16:35:30.067206 <3>[ 14.382825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 16:35:30.073832 <30>[ 14.392598] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10930 16:35:30.094099 [[0;32m OK [<4>[ 14.401698] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10931 16:35:30.101806 0m] Finished [0<3>[ 14.418070] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10932 16:35:30.108060 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10933 16:35:30.134445 <30>[ 14.447239] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10934 16:35:30.140606 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10935 16:35:30.163619 <30>[ 14.480138] systemd[1]: Started systemd-journald.service - Journal Service.
10936 16:35:30.170015 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10937 16:35:30.190166 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10938 16:35:30.208087 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10939 16:35:30.229504 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10940 16:35:30.286985 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10941 16:35:30.309450 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10942 16:35:30.332217 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10943 16:35:30.356516 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10944 16:35:30.388693 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10945 16:35:30.398410 <46>[ 14.714866] systemd-journald[301]: Received client request to flush runtime journal.
10946 16:35:30.414475 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10947 16:35:30.442100 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10948 16:35:30.460166 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10949 16:35:30.479773 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10950 16:35:31.176653 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10951 16:35:31.511471 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10952 16:35:31.571271 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10953 16:35:31.817469 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10954 16:35:31.928556 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10955 16:35:31.946753 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10956 16:35:31.966992 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10957 16:35:32.036647 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10958 16:35:32.060494 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10959 16:35:32.270051 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10960 16:35:32.315141 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10961 16:35:32.394536 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10962 16:35:32.697930 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10963 16:35:32.730947 <6>[ 17.051472] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10964 16:35:32.756186 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10965 16:35:32.780531 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10966 16:35:32.823407 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10967 16:35:32.915352 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10968 16:35:32.941527 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10969 16:35:32.960011 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10970 16:35:33.000184 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10971 16:35:33.018308 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10972 16:35:33.044727 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10973 16:35:33.091775 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10974 16:35:33.122475 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10975 16:35:33.141088 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10976 16:35:33.171474 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10977 16:35:33.191404 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10978 16:35:33.210718 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10979 16:35:33.226380 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10980 16:35:33.250502 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10981 16:35:33.300251 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10982 16:35:33.322434 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10983 16:35:33.342053 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10984 16:35:33.365353 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10985 16:35:33.382179 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10986 16:35:33.400194 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10987 16:35:33.418097 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10988 16:35:33.434574 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10989 16:35:33.475968 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10990 16:35:33.530708 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10991 16:35:33.619192 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10992 16:35:33.644724 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10993 16:35:33.683173 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10994 16:35:33.734929 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10995 16:35:33.799008 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10996 16:35:33.820383 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10997 16:35:33.843667 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10998 16:35:33.878761 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10999 16:35:33.985716 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11000 16:35:34.006468 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11001 16:35:34.023969 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11002 16:35:34.074060 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11003 16:35:34.119136 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11004 16:35:34.206896
11005 16:35:34.210576 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11006 16:35:34.210692
11007 16:35:34.213939 debian-bookworm-arm64 login: root (automatic login)
11008 16:35:34.214047
11009 16:35:34.521153 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11010 16:35:34.521346
11011 16:35:34.528062 The programs included with the Debian GNU/Linux system are free software;
11012 16:35:34.534280 the exact distribution terms for each program are described in the
11013 16:35:34.537935 individual files in /usr/share/doc/*/copyright.
11014 16:35:34.538054
11015 16:35:34.544243 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11016 16:35:34.547891 permitted by applicable law.
11017 16:35:35.555551 Matched prompt #10: / #
11019 16:35:35.555837 Setting prompt string to ['/ #']
11020 16:35:35.555932 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11022 16:35:35.556128 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11023 16:35:35.556217 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11024 16:35:35.556286 Setting prompt string to ['/ #']
11025 16:35:35.556345 Forcing a shell prompt, looking for ['/ #']
11027 16:35:35.606546 / #
11028 16:35:35.606764 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11029 16:35:35.606902 Waiting using forced prompt support (timeout 00:02:30)
11030 16:35:35.612210
11031 16:35:35.612564 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11032 16:35:35.612672 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11034 16:35:35.713025 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc'
11035 16:35:35.718468 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396153/extract-nfsrootfs-fpj03suc'
11037 16:35:35.819033 / # export NFS_SERVER_IP='192.168.201.1'
11038 16:35:35.824213 export NFS_SERVER_IP='192.168.201.1'
11039 16:35:35.824566 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11040 16:35:35.824699 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11041 16:35:35.824820 end: 2 depthcharge-action (duration 00:01:36) [common]
11042 16:35:35.824935 start: 3 lava-test-retry (timeout 00:07:41) [common]
11043 16:35:35.825069 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11044 16:35:35.825173 Using namespace: common
11046 16:35:35.925592 / # #
11047 16:35:35.925748 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11048 16:35:35.931887 #
11049 16:35:35.932180 Using /lava-14396153
11051 16:35:36.032581 / # export SHELL=/bin/bash
11052 16:35:36.037888 export SHELL=/bin/bash
11054 16:35:36.138412 / # . /lava-14396153/environment
11055 16:35:36.143948 . /lava-14396153/environment
11057 16:35:36.249889 / # /lava-14396153/bin/lava-test-runner /lava-14396153/0
11058 16:35:36.250052 Test shell timeout: 10s (minimum of the action and connection timeout)
11059 16:35:36.254964 /lava-14396153/bin/lava-test-runner /lava-14396153/0
11060 16:35:36.515186 + export TESTRUN_ID=0_timesync-off
11061 16:35:36.518750 + TESTRUN_ID=0_timesync-off
11062 16:35:36.521842 + cd /lava-14396153/0/tests/0_timesync-off
11063 16:35:36.524833 ++ cat uuid
11064 16:35:36.531006 + UUID=14396153_1.6.2.3.1
11065 16:35:36.531120 + set +x
11066 16:35:36.537469 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14396153_1.6.2.3.1>
11067 16:35:36.537777 Received signal: <STARTRUN> 0_timesync-off 14396153_1.6.2.3.1
11068 16:35:36.537873 Starting test lava.0_timesync-off (14396153_1.6.2.3.1)
11069 16:35:36.537992 Skipping test definition patterns.
11070 16:35:36.540654 + systemctl stop systemd-timesyncd
11071 16:35:36.605557 + set +x
11072 16:35:36.608495 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14396153_1.6.2.3.1>
11073 16:35:36.608795 Received signal: <ENDRUN> 0_timesync-off 14396153_1.6.2.3.1
11074 16:35:36.608912 Ending use of test pattern.
11075 16:35:36.608999 Ending test lava.0_timesync-off (14396153_1.6.2.3.1), duration 0.07
11077 16:35:36.687535 + export TESTRUN_ID=1_kselftest-tpm2
11078 16:35:36.691441 + TESTRUN_ID=1_kselftest-tpm2
11079 16:35:36.697441 + cd /lava-14396153/0/tests/1_kselftest-tpm2
11080 16:35:36.697610 ++ cat uuid
11081 16:35:36.703046 + UUID=14396153_1.6.2.3.5
11082 16:35:36.703148 + set +x
11083 16:35:36.709961 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14396153_1.6.2.3.5>
11084 16:35:36.710336 Received signal: <STARTRUN> 1_kselftest-tpm2 14396153_1.6.2.3.5
11085 16:35:36.710457 Starting test lava.1_kselftest-tpm2 (14396153_1.6.2.3.5)
11086 16:35:36.710539 Skipping test definition patterns.
11087 16:35:36.712973 + cd ./automated/linux/kselftest/
11088 16:35:36.742532 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11089 16:35:36.779704 INFO: install_deps skipped
11090 16:35:37.285123 --2024-06-17 16:35:37-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11091 16:35:37.294604 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11092 16:35:37.428041 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11093 16:35:37.561283 HTTP request sent, awaiting response... 200 OK
11094 16:35:37.564783 Length: 1650228 (1.6M) [application/octet-stream]
11095 16:35:37.567789 Saving to: 'kselftest_armhf.tar.gz'
11096 16:35:37.567872
11097 16:35:37.567935
11098 16:35:37.826282 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11099 16:35:38.090296 kselftest_armhf.tar 2%[ ] 47.81K 182KB/s
11100 16:35:38.402442 kselftest_armhf.tar 13%[=> ] 217.50K 415KB/s
11101 16:35:38.536955 kselftest_armhf.tar 51%[=========> ] 824.13K 988KB/s
11102 16:35:38.543242 kselftest_armhf.tar 100%[===================>] 1.57M 1.63MB/s in 1.0s
11103 16:35:38.543378
11104 16:35:38.688671 2024-06-17 16:35:38 (1.63 MB/s) - 'kselftest_armhf.tar.gz' saved [1650228/1650228]
11105 16:35:38.688866
11106 16:35:43.337594 skiplist:
11107 16:35:43.341193 ========================================
11108 16:35:43.344277 ========================================
11109 16:35:43.393275 tpm2:test_smoke.sh
11110 16:35:43.396931 tpm2:test_space.sh
11111 16:35:43.414843 ============== Tests to run ===============
11112 16:35:43.418010 tpm2:test_smoke.sh
11113 16:35:43.418126 tpm2:test_space.sh
11114 16:35:43.421105 ===========End Tests to run ===============
11115 16:35:43.424193 shardfile-tpm2 pass
11116 16:35:43.541054 <12>[ 27.862580] kselftest: Running tests in tpm2
11117 16:35:43.550954 TAP version 13
11118 16:35:43.567735 1..2
11119 16:35:43.602798 # selftests: tpm2: test_smoke.sh
11120 16:35:45.422465 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11121 16:35:45.429137 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11122 16:35:45.435618 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11123 16:35:45.438761 # Traceback (most recent call last):
11124 16:35:45.448609 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11125 16:35:45.448744 # if self.tpm:
11126 16:35:45.451885 # ^^^^^^^^
11127 16:35:45.455147 # AttributeError: 'Client' object has no attribute 'tpm'
11128 16:35:45.462118 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11129 16:35:45.468366 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11130 16:35:45.472271 # Traceback (most recent call last):
11131 16:35:45.481786 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11132 16:35:45.481931 # if self.tpm:
11133 16:35:45.484949 # ^^^^^^^^
11134 16:35:45.491731 # AttributeError: 'Client' object has no attribute 'tpm'
11135 16:35:45.498748 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11136 16:35:45.501844 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11137 16:35:45.505093 # Traceback (most recent call last):
11138 16:35:45.514674 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11139 16:35:45.518318 # if self.tpm:
11140 16:35:45.518438 # ^^^^^^^^
11141 16:35:45.524834 # AttributeError: 'Client' object has no attribute 'tpm'
11142 16:35:45.531383 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11143 16:35:45.538027 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11144 16:35:45.541538 # Traceback (most recent call last):
11145 16:35:45.551106 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11146 16:35:45.554337 # if self.tpm:
11147 16:35:45.554465 # ^^^^^^^^
11148 16:35:45.561103 # AttributeError: 'Client' object has no attribute 'tpm'
11149 16:35:45.567932 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11150 16:35:45.573970 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11151 16:35:45.577703 # Traceback (most recent call last):
11152 16:35:45.584146 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11153 16:35:45.587386 # if self.tpm:
11154 16:35:45.587471 # ^^^^^^^^
11155 16:35:45.594231 # AttributeError: 'Client' object has no attribute 'tpm'
11156 16:35:45.600639 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11157 16:35:45.607723 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11158 16:35:45.610888 # Traceback (most recent call last):
11159 16:35:45.620832 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11160 16:35:45.620935 # if self.tpm:
11161 16:35:45.623857 # ^^^^^^^^
11162 16:35:45.627326 # AttributeError: 'Client' object has no attribute 'tpm'
11163 16:35:45.637207 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11164 16:35:45.640616 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11165 16:35:45.644195 # Traceback (most recent call last):
11166 16:35:45.653842 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11167 16:35:45.657116 # if self.tpm:
11168 16:35:45.657204 # ^^^^^^^^
11169 16:35:45.663596 # AttributeError: 'Client' object has no attribute 'tpm'
11170 16:35:45.670574 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11171 16:35:45.676744 # Exception ignored in: <function Client.__del__ at 0xffff931dccc0>
11172 16:35:45.680555 # Traceback (most recent call last):
11173 16:35:45.690311 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11174 16:35:45.693623 # if self.tpm:
11175 16:35:45.693714 # ^^^^^^^^
11176 16:35:45.700193 # AttributeError: 'Client' object has no attribute 'tpm'
11177 16:35:45.700315 #
11178 16:35:45.706543 # ======================================================================
11179 16:35:45.713389 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11180 16:35:45.720221 # ----------------------------------------------------------------------
11181 16:35:45.723489 # Traceback (most recent call last):
11182 16:35:45.733570 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11183 16:35:45.740174 # self.root_key = self.client.create_root_key()
11184 16:35:45.743089 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11185 16:35:45.753190 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11186 16:35:45.759970 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11187 16:35:45.763372 # ^^^^^^^^^^^^^^^^^^
11188 16:35:45.773138 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11189 16:35:45.776351 # raise ProtocolError(cc, rc)
11190 16:35:45.783823 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11191 16:35:45.783924 #
11192 16:35:45.790962 # ======================================================================
11193 16:35:45.797422 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11194 16:35:45.804229 # ----------------------------------------------------------------------
11195 16:35:45.807286 # Traceback (most recent call last):
11196 16:35:45.817460 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11197 16:35:45.820548 # self.client = tpm2.Client()
11198 16:35:45.823724 # ^^^^^^^^^^^^^
11199 16:35:45.834093 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11200 16:35:45.837289 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11201 16:35:45.840432 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11202 16:35:45.847233 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11203 16:35:45.847317 #
11204 16:35:45.853798 # ======================================================================
11205 16:35:45.860397 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11206 16:35:45.866815 # ----------------------------------------------------------------------
11207 16:35:45.869864 # Traceback (most recent call last):
11208 16:35:45.880103 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11209 16:35:45.883223 # self.client = tpm2.Client()
11210 16:35:45.886392 # ^^^^^^^^^^^^^
11211 16:35:45.896621 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11212 16:35:45.899909 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11213 16:35:45.906699 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11214 16:35:45.909938 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11215 16:35:45.910032 #
11216 16:35:45.916214 # ======================================================================
11217 16:35:45.923243 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11218 16:35:45.929730 # ----------------------------------------------------------------------
11219 16:35:45.932967 # Traceback (most recent call last):
11220 16:35:45.943029 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11221 16:35:45.946275 # self.client = tpm2.Client()
11222 16:35:45.949510 # ^^^^^^^^^^^^^
11223 16:35:45.959583 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11224 16:35:45.966063 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11225 16:35:45.969575 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11226 16:35:45.976153 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11227 16:35:45.976247 #
11228 16:35:45.982497 # ======================================================================
11229 16:35:45.989320 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11230 16:35:45.995628 # ----------------------------------------------------------------------
11231 16:35:45.998858 # Traceback (most recent call last):
11232 16:35:46.009178 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11233 16:35:46.012070 # self.client = tpm2.Client()
11234 16:35:46.015927 # ^^^^^^^^^^^^^
11235 16:35:46.025512 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11236 16:35:46.028681 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11237 16:35:46.035656 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11238 16:35:46.042298 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11239 16:35:46.042383 #
11240 16:35:46.048737 # ======================================================================
11241 16:35:46.052025 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11242 16:35:46.058361 # ----------------------------------------------------------------------
11243 16:35:46.062026 # Traceback (most recent call last):
11244 16:35:46.071617 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11245 16:35:46.075085 # self.client = tpm2.Client()
11246 16:35:46.078222 # ^^^^^^^^^^^^^
11247 16:35:46.088554 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11248 16:35:46.095054 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11249 16:35:46.098144 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11250 16:35:46.104597 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11251 16:35:46.104685 #
11252 16:35:46.111514 # ======================================================================
11253 16:35:46.118117 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11254 16:35:46.125028 # ----------------------------------------------------------------------
11255 16:35:46.128074 # Traceback (most recent call last):
11256 16:35:46.138254 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11257 16:35:46.142085 # self.client = tpm2.Client()
11258 16:35:46.142169 # ^^^^^^^^^^^^^
11259 16:35:46.153597 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11260 16:35:46.156379 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11261 16:35:46.165297 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11262 16:35:46.168641 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11263 16:35:46.168724 #
11264 16:35:46.179381 # ======================================================================
11265 16:35:46.182433 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11266 16:35:46.190293 # ----------------------------------------------------------------------
11267 16:35:46.190433 # Traceback (most recent call last):
11268 16:35:46.200900 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11269 16:35:46.204570 # self.client = tpm2.Client()
11270 16:35:46.207495 # ^^^^^^^^^^^^^
11271 16:35:46.217176 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11272 16:35:46.224180 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11273 16:35:46.227501 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11274 16:35:46.234211 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11275 16:35:46.234301 #
11276 16:35:46.240545 # ======================================================================
11277 16:35:46.247659 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11278 16:35:46.253862 # ----------------------------------------------------------------------
11279 16:35:46.257600 # Traceback (most recent call last):
11280 16:35:46.266999 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11281 16:35:46.270845 # self.client = tpm2.Client()
11282 16:35:46.274086 # ^^^^^^^^^^^^^
11283 16:35:46.283574 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11284 16:35:46.287338 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11285 16:35:46.293964 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11286 16:35:46.296911 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11287 16:35:46.300491 #
11288 16:35:46.303720 # ----------------------------------------------------------------------
11289 16:35:46.306763 # Ran 9 tests in 0.053s
11290 16:35:46.306844 #
11291 16:35:46.310360 # FAILED (errors=9)
11292 16:35:46.313287 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11293 16:35:46.320116 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11294 16:35:46.323581 #
11295 16:35:46.330451 # ----------------------------------------------------------------------
11296 16:35:46.330538 # Ran 2 tests in 0.067s
11297 16:35:46.330601 #
11298 16:35:46.330660 # OK
11299 16:35:46.333573 ok 1 selftests: tpm2: test_smoke.sh
11300 16:35:46.336736 # selftests: tpm2: test_space.sh
11301 16:35:46.343766 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11302 16:35:46.350188 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11303 16:35:46.356944 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11304 16:35:46.363486 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11305 16:35:46.363577 #
11306 16:35:46.369612 # ======================================================================
11307 16:35:46.376576 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11308 16:35:46.383010 # ----------------------------------------------------------------------
11309 16:35:46.385989 # Traceback (most recent call last):
11310 16:35:46.396576 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11311 16:35:46.399671 # root1 = space1.create_root_key()
11312 16:35:46.402757 # ^^^^^^^^^^^^^^^^^^^^^^^^
11313 16:35:46.416122 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11314 16:35:46.419677 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11315 16:35:46.425847 # ^^^^^^^^^^^^^^^^^^
11316 16:35:46.436236 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11317 16:35:46.436323 # raise ProtocolError(cc, rc)
11318 16:35:46.442479 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11319 16:35:46.442564 #
11320 16:35:46.449404 # ======================================================================
11321 16:35:46.456070 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11322 16:35:46.462812 # ----------------------------------------------------------------------
11323 16:35:46.465866 # Traceback (most recent call last):
11324 16:35:46.476115 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11325 16:35:46.479340 # space1.create_root_key()
11326 16:35:46.489182 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11327 16:35:46.496039 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11328 16:35:46.499224 # ^^^^^^^^^^^^^^^^^^
11329 16:35:46.509182 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11330 16:35:46.512381 # raise ProtocolError(cc, rc)
11331 16:35:46.519063 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11332 16:35:46.519148 #
11333 16:35:46.525289 # ======================================================================
11334 16:35:46.532741 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11335 16:35:46.539311 # ----------------------------------------------------------------------
11336 16:35:46.542480 # Traceback (most recent call last):
11337 16:35:46.552202 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11338 16:35:46.555839 # root1 = space1.create_root_key()
11339 16:35:46.559048 # ^^^^^^^^^^^^^^^^^^^^^^^^
11340 16:35:46.568869 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11341 16:35:46.575629 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11342 16:35:46.578873 # ^^^^^^^^^^^^^^^^^^
11343 16:35:46.588990 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11344 16:35:46.592205 # raise ProtocolError(cc, rc)
11345 16:35:46.599181 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11346 16:35:46.599287 #
11347 16:35:46.605461 # ======================================================================
11348 16:35:46.612364 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11349 16:35:46.618573 # ----------------------------------------------------------------------
11350 16:35:46.622122 # Traceback (most recent call last):
11351 16:35:46.632155 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11352 16:35:46.638426 # root1 = space1.create_root_key()
11353 16:35:46.641805 # ^^^^^^^^^^^^^^^^^^^^^^^^
11354 16:35:46.651860 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11355 16:35:46.655346 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11356 16:35:46.661762 # ^^^^^^^^^^^^^^^^^^
11357 16:35:46.671691 # File "/lava-14396153/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11358 16:35:46.674860 # raise ProtocolError(cc, rc)
11359 16:35:46.681699 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11360 16:35:46.681849 #
11361 16:35:46.688031 # ----------------------------------------------------------------------
11362 16:35:46.688342 # Ran 4 tests in 0.063s
11363 16:35:46.688511 #
11364 16:35:46.691370 # FAILED (errors=4)
11365 16:35:46.694430 not ok 2 selftests: tpm2: test_space.sh # exit=1
11366 16:35:47.090722 tpm2_test_smoke_sh pass
11367 16:35:47.094301 tpm2_test_space_sh fail
11368 16:35:47.163369 + ../../utils/send-to-lava.sh ./output/result.txt
11369 16:35:47.238727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11370 16:35:47.239051 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11372 16:35:47.292415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11373 16:35:47.292695 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11375 16:35:47.347164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11376 16:35:47.347456 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11378 16:35:47.350397 + set +x
11379 16:35:47.353522 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14396153_1.6.2.3.5>
11380 16:35:47.353774 Received signal: <ENDRUN> 1_kselftest-tpm2 14396153_1.6.2.3.5
11381 16:35:47.353847 Ending use of test pattern.
11382 16:35:47.353907 Ending test lava.1_kselftest-tpm2 (14396153_1.6.2.3.5), duration 10.64
11384 16:35:47.356983 <LAVA_TEST_RUNNER EXIT>
11385 16:35:47.357233 ok: lava_test_shell seems to have completed
11386 16:35:47.357383 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11387 16:35:47.357470 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11388 16:35:47.357553 end: 3 lava-test-retry (duration 00:00:12) [common]
11389 16:35:47.357641 start: 4 finalize (timeout 00:07:30) [common]
11390 16:35:47.357733 start: 4.1 power-off (timeout 00:00:30) [common]
11391 16:35:47.357903 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11392 16:35:47.557008 >> Command sent successfully.
11393 16:35:47.559451 Returned 0 in 0 seconds
11394 16:35:47.659842 end: 4.1 power-off (duration 00:00:00) [common]
11396 16:35:47.660207 start: 4.2 read-feedback (timeout 00:07:30) [common]
11397 16:35:47.660468 Listened to connection for namespace 'common' for up to 1s
11398 16:35:48.661365 Finalising connection for namespace 'common'
11399 16:35:48.661570 Disconnecting from shell: Finalise
11400 16:35:48.661648 / #
11401 16:35:48.761969 end: 4.2 read-feedback (duration 00:00:01) [common]
11402 16:35:48.762148 end: 4 finalize (duration 00:00:01) [common]
11403 16:35:48.762259 Cleaning after the job
11404 16:35:48.762358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/ramdisk
11405 16:35:48.764518 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/kernel
11406 16:35:48.775523 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/dtb
11407 16:35:48.775733 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/nfsrootfs
11408 16:35:48.839329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396153/tftp-deploy-iw5mv4ot/modules
11409 16:35:48.844862 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396153
11410 16:35:49.418159 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396153
11411 16:35:49.418331 Job finished correctly