Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 16:35:42.980149 lava-dispatcher, installed at version: 2024.03
2 16:35:42.980383 start: 0 validate
3 16:35:42.980501 Start time: 2024-06-17 16:35:42.980493+00:00 (UTC)
4 16:35:42.980663 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:35:42.980844 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:35:43.269333 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:35:43.270034 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:35:43.529353 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:35:43.529653 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:35:43.795222 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:35:43.796168 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:35:44.057325 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:35:44.058058 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:35:44.330466 validate duration: 1.35
16 16:35:44.331947 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:35:44.332606 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:35:44.333115 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:35:44.333922 Not decompressing ramdisk as can be used compressed.
20 16:35:44.334454 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 16:35:44.334813 saving as /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/ramdisk/initrd.cpio.gz
22 16:35:44.335190 total size: 5628151 (5 MB)
23 16:35:44.340140 progress 0 % (0 MB)
24 16:35:44.348224 progress 5 % (0 MB)
25 16:35:44.353498 progress 10 % (0 MB)
26 16:35:44.357208 progress 15 % (0 MB)
27 16:35:44.360836 progress 20 % (1 MB)
28 16:35:44.363582 progress 25 % (1 MB)
29 16:35:44.366492 progress 30 % (1 MB)
30 16:35:44.368888 progress 35 % (1 MB)
31 16:35:44.371091 progress 40 % (2 MB)
32 16:35:44.373255 progress 45 % (2 MB)
33 16:35:44.375262 progress 50 % (2 MB)
34 16:35:44.377282 progress 55 % (2 MB)
35 16:35:44.379225 progress 60 % (3 MB)
36 16:35:44.381028 progress 65 % (3 MB)
37 16:35:44.382845 progress 70 % (3 MB)
38 16:35:44.384374 progress 75 % (4 MB)
39 16:35:44.386147 progress 80 % (4 MB)
40 16:35:44.387631 progress 85 % (4 MB)
41 16:35:44.389256 progress 90 % (4 MB)
42 16:35:44.390816 progress 95 % (5 MB)
43 16:35:44.392278 progress 100 % (5 MB)
44 16:35:44.392509 5 MB downloaded in 0.06 s (93.64 MB/s)
45 16:35:44.392707 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:35:44.392958 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:35:44.393039 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:35:44.393116 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:35:44.393246 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:35:44.393308 saving as /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/kernel/Image
52 16:35:44.393379 total size: 54813184 (52 MB)
53 16:35:44.393478 No compression specified
54 16:35:44.394604 progress 0 % (0 MB)
55 16:35:44.408764 progress 5 % (2 MB)
56 16:35:44.422958 progress 10 % (5 MB)
57 16:35:44.436773 progress 15 % (7 MB)
58 16:35:44.451013 progress 20 % (10 MB)
59 16:35:44.465381 progress 25 % (13 MB)
60 16:35:44.479794 progress 30 % (15 MB)
61 16:35:44.494205 progress 35 % (18 MB)
62 16:35:44.508279 progress 40 % (20 MB)
63 16:35:44.522268 progress 45 % (23 MB)
64 16:35:44.536404 progress 50 % (26 MB)
65 16:35:44.550423 progress 55 % (28 MB)
66 16:35:44.564008 progress 60 % (31 MB)
67 16:35:44.577996 progress 65 % (34 MB)
68 16:35:44.592090 progress 70 % (36 MB)
69 16:35:44.606425 progress 75 % (39 MB)
70 16:35:44.620228 progress 80 % (41 MB)
71 16:35:44.634108 progress 85 % (44 MB)
72 16:35:44.647993 progress 90 % (47 MB)
73 16:35:44.661928 progress 95 % (49 MB)
74 16:35:44.675244 progress 100 % (52 MB)
75 16:35:44.675466 52 MB downloaded in 0.28 s (185.31 MB/s)
76 16:35:44.675615 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:35:44.675832 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:35:44.675950 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:35:44.676026 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:35:44.676149 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:35:44.676226 saving as /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/dtb/mt8192-asurada-spherion-r0.dtb
83 16:35:44.676281 total size: 47258 (0 MB)
84 16:35:44.676341 No compression specified
85 16:35:44.677420 progress 69 % (0 MB)
86 16:35:44.677749 progress 100 % (0 MB)
87 16:35:44.677903 0 MB downloaded in 0.00 s (27.83 MB/s)
88 16:35:44.678016 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:35:44.678220 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:35:44.678307 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:35:44.678384 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:35:44.678524 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 16:35:44.678615 saving as /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/nfsrootfs/full.rootfs.tar
95 16:35:44.678702 total size: 69067788 (65 MB)
96 16:35:44.678784 Using unxz to decompress xz
97 16:35:44.680543 progress 0 % (0 MB)
98 16:35:44.877442 progress 5 % (3 MB)
99 16:35:45.077739 progress 10 % (6 MB)
100 16:35:46.020854 progress 15 % (9 MB)
101 16:35:46.186190 progress 20 % (13 MB)
102 16:35:46.371200 progress 25 % (16 MB)
103 16:35:46.565020 progress 30 % (19 MB)
104 16:35:46.689636 progress 35 % (23 MB)
105 16:35:46.790668 progress 40 % (26 MB)
106 16:35:46.995431 progress 45 % (29 MB)
107 16:35:47.211205 progress 50 % (32 MB)
108 16:35:47.424289 progress 55 % (36 MB)
109 16:35:47.650933 progress 60 % (39 MB)
110 16:35:47.852690 progress 65 % (42 MB)
111 16:35:48.055412 progress 70 % (46 MB)
112 16:35:48.249926 progress 75 % (49 MB)
113 16:35:48.456554 progress 80 % (52 MB)
114 16:35:48.665869 progress 85 % (56 MB)
115 16:35:48.872655 progress 90 % (59 MB)
116 16:35:49.108973 progress 95 % (62 MB)
117 16:35:49.314522 progress 100 % (65 MB)
118 16:35:49.320626 65 MB downloaded in 4.64 s (14.19 MB/s)
119 16:35:49.320828 end: 1.4.1 http-download (duration 00:00:05) [common]
121 16:35:49.321161 end: 1.4 download-retry (duration 00:00:05) [common]
122 16:35:49.321270 start: 1.5 download-retry (timeout 00:09:55) [common]
123 16:35:49.321374 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 16:35:49.321532 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:35:49.321610 saving as /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/modules/modules.tar
126 16:35:49.321667 total size: 8628772 (8 MB)
127 16:35:49.321724 Using unxz to decompress xz
128 16:35:49.323089 progress 0 % (0 MB)
129 16:35:49.344016 progress 5 % (0 MB)
130 16:35:49.431506 progress 10 % (0 MB)
131 16:35:49.464997 progress 15 % (1 MB)
132 16:35:49.497203 progress 20 % (1 MB)
133 16:35:49.524142 progress 25 % (2 MB)
134 16:35:49.555163 progress 30 % (2 MB)
135 16:35:49.583961 progress 35 % (2 MB)
136 16:35:49.608616 progress 40 % (3 MB)
137 16:35:49.633595 progress 45 % (3 MB)
138 16:35:49.660199 progress 50 % (4 MB)
139 16:35:49.685226 progress 55 % (4 MB)
140 16:35:49.712877 progress 60 % (4 MB)
141 16:35:49.742385 progress 65 % (5 MB)
142 16:35:49.768999 progress 70 % (5 MB)
143 16:35:49.794128 progress 75 % (6 MB)
144 16:35:49.818142 progress 80 % (6 MB)
145 16:35:49.845366 progress 85 % (7 MB)
146 16:35:49.872111 progress 90 % (7 MB)
147 16:35:49.897041 progress 95 % (7 MB)
148 16:35:49.921633 progress 100 % (8 MB)
149 16:35:49.926668 8 MB downloaded in 0.60 s (13.60 MB/s)
150 16:35:49.926848 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:35:49.927067 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:35:49.927158 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 16:35:49.927260 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 16:35:51.879868 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon
156 16:35:51.880029 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 16:35:51.880125 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 16:35:51.880300 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz
159 16:35:51.880449 makedir: /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin
160 16:35:51.880582 makedir: /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/tests
161 16:35:51.880676 makedir: /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/results
162 16:35:51.880764 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-add-keys
163 16:35:51.880902 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-add-sources
164 16:35:51.881022 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-background-process-start
165 16:35:51.881141 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-background-process-stop
166 16:35:51.881272 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-common-functions
167 16:35:51.881391 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-echo-ipv4
168 16:35:51.881506 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-install-packages
169 16:35:51.881629 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-installed-packages
170 16:35:51.881743 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-os-build
171 16:35:51.881856 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-probe-channel
172 16:35:51.881970 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-probe-ip
173 16:35:51.882093 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-target-ip
174 16:35:51.882209 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-target-mac
175 16:35:51.882323 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-target-storage
176 16:35:51.882448 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-case
177 16:35:51.882571 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-event
178 16:35:51.882684 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-feedback
179 16:35:51.882795 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-raise
180 16:35:51.882921 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-reference
181 16:35:51.883040 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-runner
182 16:35:51.883156 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-set
183 16:35:51.883277 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-test-shell
184 16:35:51.883392 Updating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-install-packages (oe)
185 16:35:51.883533 Updating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/bin/lava-installed-packages (oe)
186 16:35:51.883670 Creating /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/environment
187 16:35:51.883784 LAVA metadata
188 16:35:51.883886 - LAVA_JOB_ID=14396170
189 16:35:51.883975 - LAVA_DISPATCHER_IP=192.168.201.1
190 16:35:51.884101 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 16:35:51.884184 skipped lava-vland-overlay
192 16:35:51.884290 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 16:35:51.884393 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 16:35:51.884473 skipped lava-multinode-overlay
195 16:35:51.884568 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 16:35:51.884678 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 16:35:51.884768 Loading test definitions
198 16:35:51.884873 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 16:35:51.884960 Using /lava-14396170 at stage 0
200 16:35:51.885364 uuid=14396170_1.6.2.3.1 testdef=None
201 16:35:51.885477 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 16:35:51.885593 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 16:35:51.886036 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 16:35:51.886246 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 16:35:51.886841 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 16:35:51.887055 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 16:35:51.887617 runner path: /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/0/tests/0_lc-compliance test_uuid 14396170_1.6.2.3.1
210 16:35:51.887763 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 16:35:51.887958 Creating lava-test-runner.conf files
213 16:35:51.888014 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396170/lava-overlay-b3tmc8lz/lava-14396170/0 for stage 0
214 16:35:51.888096 - 0_lc-compliance
215 16:35:51.888196 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 16:35:51.888273 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 16:35:51.894222 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 16:35:51.894344 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 16:35:51.894429 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 16:35:51.894509 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 16:35:51.894596 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 16:35:52.059478 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 16:35:52.059641 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 16:35:52.059748 extracting modules file /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon
225 16:35:52.314720 extracting modules file /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396170/extract-overlay-ramdisk-ykptk1qm/ramdisk
226 16:35:52.552446 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 16:35:52.552579 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 16:35:52.552665 [common] Applying overlay to NFS
229 16:35:52.552727 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396170/compress-overlay-n0aynxc9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon
230 16:35:52.559060 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 16:35:52.559169 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 16:35:52.559251 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 16:35:52.559329 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 16:35:52.559396 Building ramdisk /var/lib/lava/dispatcher/tmp/14396170/extract-overlay-ramdisk-ykptk1qm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396170/extract-overlay-ramdisk-ykptk1qm/ramdisk
235 16:35:52.869794 >> 130466 blocks
236 16:35:55.070798 rename /var/lib/lava/dispatcher/tmp/14396170/extract-overlay-ramdisk-ykptk1qm/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/ramdisk/ramdisk.cpio.gz
237 16:35:55.070955 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 16:35:55.071063 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 16:35:55.071145 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 16:35:55.071225 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/kernel/Image']
241 16:36:10.229037 Returned 0 in 15 seconds
242 16:36:10.329636 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/kernel/image.itb
243 16:36:10.855609 output: FIT description: Kernel Image image with one or more FDT blobs
244 16:36:10.855766 output: Created: Mon Jun 17 17:36:10 2024
245 16:36:10.855860 output: Image 0 (kernel-1)
246 16:36:10.855953 output: Description:
247 16:36:10.856041 output: Created: Mon Jun 17 17:36:10 2024
248 16:36:10.856131 output: Type: Kernel Image
249 16:36:10.856217 output: Compression: lzma compressed
250 16:36:10.856307 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
251 16:36:10.856397 output: Architecture: AArch64
252 16:36:10.856482 output: OS: Linux
253 16:36:10.856565 output: Load Address: 0x00000000
254 16:36:10.856651 output: Entry Point: 0x00000000
255 16:36:10.856732 output: Hash algo: crc32
256 16:36:10.856816 output: Hash value: 106ffd6f
257 16:36:10.856900 output: Image 1 (fdt-1)
258 16:36:10.856980 output: Description: mt8192-asurada-spherion-r0
259 16:36:10.857060 output: Created: Mon Jun 17 17:36:10 2024
260 16:36:10.857141 output: Type: Flat Device Tree
261 16:36:10.857218 output: Compression: uncompressed
262 16:36:10.857304 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 16:36:10.857386 output: Architecture: AArch64
264 16:36:10.857463 output: Hash algo: crc32
265 16:36:10.857540 output: Hash value: 0f8e4d2e
266 16:36:10.857608 output: Image 2 (ramdisk-1)
267 16:36:10.857688 output: Description: unavailable
268 16:36:10.857772 output: Created: Mon Jun 17 17:36:10 2024
269 16:36:10.857859 output: Type: RAMDisk Image
270 16:36:10.857945 output: Compression: uncompressed
271 16:36:10.858030 output: Data Size: 18743182 Bytes = 18303.89 KiB = 17.87 MiB
272 16:36:10.858118 output: Architecture: AArch64
273 16:36:10.858204 output: OS: Linux
274 16:36:10.858290 output: Load Address: unavailable
275 16:36:10.858378 output: Entry Point: unavailable
276 16:36:10.858468 output: Hash algo: crc32
277 16:36:10.858555 output: Hash value: d7c877cd
278 16:36:10.858642 output: Default Configuration: 'conf-1'
279 16:36:10.858728 output: Configuration 0 (conf-1)
280 16:36:10.858813 output: Description: mt8192-asurada-spherion-r0
281 16:36:10.858900 output: Kernel: kernel-1
282 16:36:10.858985 output: Init Ramdisk: ramdisk-1
283 16:36:10.859070 output: FDT: fdt-1
284 16:36:10.859156 output: Loadables: kernel-1
285 16:36:10.859241 output:
286 16:36:10.859427 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
287 16:36:10.859559 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
288 16:36:10.859692 end: 1.6 prepare-tftp-overlay (duration 00:00:21) [common]
289 16:36:10.859813 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
290 16:36:10.859918 No LXC device requested
291 16:36:10.860029 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 16:36:10.860148 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
293 16:36:10.860257 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 16:36:10.860354 Checking files for TFTP limit of 4294967296 bytes.
295 16:36:10.860971 end: 1 tftp-deploy (duration 00:00:27) [common]
296 16:36:10.861113 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 16:36:10.861236 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 16:36:10.861403 substitutions:
299 16:36:10.861496 - {DTB}: 14396170/tftp-deploy-it2kh7ii/dtb/mt8192-asurada-spherion-r0.dtb
300 16:36:10.861600 - {INITRD}: 14396170/tftp-deploy-it2kh7ii/ramdisk/ramdisk.cpio.gz
301 16:36:10.861692 - {KERNEL}: 14396170/tftp-deploy-it2kh7ii/kernel/Image
302 16:36:10.861784 - {LAVA_MAC}: None
303 16:36:10.861873 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon
304 16:36:10.861962 - {NFS_SERVER_IP}: 192.168.201.1
305 16:36:10.862051 - {PRESEED_CONFIG}: None
306 16:36:10.862148 - {PRESEED_LOCAL}: None
307 16:36:10.862235 - {RAMDISK}: 14396170/tftp-deploy-it2kh7ii/ramdisk/ramdisk.cpio.gz
308 16:36:10.862322 - {ROOT_PART}: None
309 16:36:10.862409 - {ROOT}: None
310 16:36:10.862496 - {SERVER_IP}: 192.168.201.1
311 16:36:10.862581 - {TEE}: None
312 16:36:10.862668 Parsed boot commands:
313 16:36:10.862752 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 16:36:10.862960 Parsed boot commands: tftpboot 192.168.201.1 14396170/tftp-deploy-it2kh7ii/kernel/image.itb 14396170/tftp-deploy-it2kh7ii/kernel/cmdline
315 16:36:10.863080 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 16:36:10.863197 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 16:36:10.863320 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 16:36:10.863436 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 16:36:10.863535 Not connected, no need to disconnect.
320 16:36:10.863646 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 16:36:10.863765 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 16:36:10.863862 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 16:36:10.867334 Setting prompt string to ['lava-test: # ']
324 16:36:10.867722 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 16:36:10.867870 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 16:36:10.868007 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 16:36:10.868134 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 16:36:10.868446 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
329 16:36:20.035770 >> Command sent successfully.
330 16:36:20.039509 Returned 0 in 9 seconds
331 16:36:20.139987 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 16:36:20.140267 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 16:36:20.140359 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 16:36:20.140516 Setting prompt string to 'Starting depthcharge on Spherion...'
336 16:36:20.140591 Changing prompt to 'Starting depthcharge on Spherion...'
337 16:36:20.140773 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 16:36:20.141307 [Enter `^Ec?' for help]
339 16:36:21.362032
340 16:36:21.362145
341 16:36:21.362211 F0: 102B 0000
342 16:36:21.362280
343 16:36:21.362340 F3: 1001 0000 [0200]
344 16:36:21.362398
345 16:36:21.365622 F3: 1001 0000
346 16:36:21.365704
347 16:36:21.365769 F7: 102D 0000
348 16:36:21.365827
349 16:36:21.365886 F1: 0000 0000
350 16:36:21.365942
351 16:36:21.369179 V0: 0000 0000 [0001]
352 16:36:21.369257
353 16:36:21.369316 00: 0007 8000
354 16:36:21.369372
355 16:36:21.372579 01: 0000 0000
356 16:36:21.372656
357 16:36:21.372714 BP: 0C00 0209 [0000]
358 16:36:21.372769
359 16:36:21.376400 G0: 1182 0000
360 16:36:21.376476
361 16:36:21.376535 EC: 0000 0021 [4000]
362 16:36:21.376589
363 16:36:21.380114 S7: 0000 0000 [0000]
364 16:36:21.380217
365 16:36:21.380288 CC: 0000 0000 [0001]
366 16:36:21.380356
367 16:36:21.383041 T0: 0000 0040 [010F]
368 16:36:21.383118
369 16:36:21.383176 Jump to BL
370 16:36:21.383230
371 16:36:21.408604
372 16:36:21.408730
373 16:36:21.416226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 16:36:21.419456 ARM64: Exception handlers installed.
375 16:36:21.423700 ARM64: Testing exception
376 16:36:21.423814 ARM64: Done test exception
377 16:36:21.431289 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 16:36:21.442669 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 16:36:21.450287 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 16:36:21.461710 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 16:36:21.468386 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 16:36:21.475805 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 16:36:21.486944 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 16:36:21.493859 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 16:36:21.511419 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 16:36:21.514396 WDT: Last reset was cold boot
387 16:36:21.517493 SPI1(PAD0) initialized at 2873684 Hz
388 16:36:21.521343 SPI5(PAD0) initialized at 992727 Hz
389 16:36:21.525312 VBOOT: Loading verstage.
390 16:36:21.532041 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 16:36:21.535434 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 16:36:21.539235 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 16:36:21.542513 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 16:36:21.550424 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 16:36:21.557361 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 16:36:21.567052 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 16:36:21.567189
398 16:36:21.567277
399 16:36:21.577091 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 16:36:21.580002 ARM64: Exception handlers installed.
401 16:36:21.583664 ARM64: Testing exception
402 16:36:21.583771 ARM64: Done test exception
403 16:36:21.590194 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 16:36:21.593698 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 16:36:21.607334 Probing TPM: . done!
406 16:36:21.607442 TPM ready after 0 ms
407 16:36:21.613823 Connected to device vid:did:rid of 1ae0:0028:00
408 16:36:21.620520 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 16:36:21.661592 Initialized TPM device CR50 revision 0
410 16:36:21.672696 tlcl_send_startup: Startup return code is 0
411 16:36:21.672868 TPM: setup succeeded
412 16:36:21.684464 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 16:36:21.693520 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 16:36:21.703469 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 16:36:21.712466 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 16:36:21.715464 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 16:36:21.719184 in-header: 03 07 00 00 08 00 00 00
418 16:36:21.722231 in-data: aa e4 47 04 13 02 00 00
419 16:36:21.725639 Chrome EC: UHEPI supported
420 16:36:21.732315 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 16:36:21.735426 in-header: 03 a9 00 00 08 00 00 00
422 16:36:21.739046 in-data: 84 60 60 08 00 00 00 00
423 16:36:21.739288 Phase 1
424 16:36:21.745889 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 16:36:21.749090 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 16:36:21.756105 VB2:vb2_check_recovery() Recovery was requested manually
427 16:36:21.762015 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 16:36:21.762254 Recovery requested (1009000e)
429 16:36:21.771013 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 16:36:21.776782 tlcl_extend: response is 0
431 16:36:21.785003 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 16:36:21.790399 tlcl_extend: response is 0
433 16:36:21.796801 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 16:36:21.817736 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 16:36:21.824292 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 16:36:21.824726
437 16:36:21.825190
438 16:36:21.834471 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 16:36:21.837963 ARM64: Exception handlers installed.
440 16:36:21.841059 ARM64: Testing exception
441 16:36:21.841535 ARM64: Done test exception
442 16:36:21.862642 pmic_efuse_setting: Set efuses in 11 msecs
443 16:36:21.866576 pmwrap_interface_init: Select PMIF_VLD_RDY
444 16:36:21.872802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 16:36:21.876423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 16:36:21.883164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 16:36:21.886178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 16:36:21.892718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 16:36:21.896219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 16:36:21.900211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 16:36:21.906383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 16:36:21.910371 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 16:36:21.916941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 16:36:21.919963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 16:36:21.923575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 16:36:21.929928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 16:36:21.936422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 16:36:21.940062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 16:36:21.946595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 16:36:21.953685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 16:36:21.956708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 16:36:21.963549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 16:36:21.970367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 16:36:21.973352 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 16:36:21.979970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 16:36:21.986778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 16:36:21.990617 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 16:36:21.996375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 16:36:22.003475 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 16:36:22.006404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 16:36:22.013651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 16:36:22.017164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 16:36:22.023705 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 16:36:22.026653 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 16:36:22.033536 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 16:36:22.036448 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 16:36:22.043775 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 16:36:22.046638 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 16:36:22.053920 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 16:36:22.056661 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 16:36:22.061071 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 16:36:22.067377 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 16:36:22.071123 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 16:36:22.074149 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 16:36:22.080728 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 16:36:22.084606 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 16:36:22.087547 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 16:36:22.094271 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 16:36:22.097222 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 16:36:22.101138 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 16:36:22.104328 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 16:36:22.111526 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 16:36:22.115146 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 16:36:22.118992 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 16:36:22.126825 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 16:36:22.132905 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 16:36:22.139857 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 16:36:22.146577 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 16:36:22.156883 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 16:36:22.160471 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 16:36:22.163354 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 16:36:22.169937 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 16:36:22.176524 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 16:36:22.180283 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 16:36:22.187395 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 16:36:22.190487 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 16:36:22.200408 [RTC]rtc_get_frequency_meter,154: input=15, output=759
508 16:36:22.209691 [RTC]rtc_get_frequency_meter,154: input=23, output=939
509 16:36:22.219003 [RTC]rtc_get_frequency_meter,154: input=19, output=851
510 16:36:22.228636 [RTC]rtc_get_frequency_meter,154: input=17, output=804
511 16:36:22.237847 [RTC]rtc_get_frequency_meter,154: input=16, output=783
512 16:36:22.247408 [RTC]rtc_get_frequency_meter,154: input=16, output=783
513 16:36:22.257195 [RTC]rtc_get_frequency_meter,154: input=17, output=804
514 16:36:22.260619 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 16:36:22.267518 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 16:36:22.271283 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 16:36:22.274851 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 16:36:22.281210 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 16:36:22.284918 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 16:36:22.287899 ADC[4]: Raw value=905465 ID=7
521 16:36:22.288002 ADC[3]: Raw value=213441 ID=1
522 16:36:22.291433 RAM Code: 0x71
523 16:36:22.294367 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 16:36:22.301440 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 16:36:22.308308 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 16:36:22.315379 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 16:36:22.318173 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 16:36:22.321200 in-header: 03 07 00 00 08 00 00 00
529 16:36:22.324809 in-data: aa e4 47 04 13 02 00 00
530 16:36:22.327854 Chrome EC: UHEPI supported
531 16:36:22.334618 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 16:36:22.338357 in-header: 03 a9 00 00 08 00 00 00
533 16:36:22.341487 in-data: 84 60 60 08 00 00 00 00
534 16:36:22.345194 MRC: failed to locate region type 0.
535 16:36:22.351384 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 16:36:22.355171 DRAM-K: Running full calibration
537 16:36:22.361600 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 16:36:22.361775 header.status = 0x0
539 16:36:22.364442 header.version = 0x6 (expected: 0x6)
540 16:36:22.367918 header.size = 0xd00 (expected: 0xd00)
541 16:36:22.371379 header.flags = 0x0
542 16:36:22.378126 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 16:36:22.394338 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 16:36:22.400693 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 16:36:22.404018 dram_init: ddr_geometry: 2
546 16:36:22.407525 [EMI] MDL number = 2
547 16:36:22.407671 [EMI] Get MDL freq = 0
548 16:36:22.410542 dram_init: ddr_type: 0
549 16:36:22.410694 is_discrete_lpddr4: 1
550 16:36:22.414358 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 16:36:22.414498
552 16:36:22.414607
553 16:36:22.417358 [Bian_co] ETT version 0.0.0.1
554 16:36:22.424188 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 16:36:22.424333
556 16:36:22.427203 dramc_set_vcore_voltage set vcore to 650000
557 16:36:22.427349 Read voltage for 800, 4
558 16:36:22.430950 Vio18 = 0
559 16:36:22.431095 Vcore = 650000
560 16:36:22.431238 Vdram = 0
561 16:36:22.433806 Vddq = 0
562 16:36:22.433887 Vmddr = 0
563 16:36:22.437368 dram_init: config_dvfs: 1
564 16:36:22.440495 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 16:36:22.447181 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 16:36:22.450840 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 16:36:22.453695 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 16:36:22.457447 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 16:36:22.460652 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 16:36:22.464264 MEM_TYPE=3, freq_sel=18
571 16:36:22.467239 sv_algorithm_assistance_LP4_1600
572 16:36:22.470807 ============ PULL DRAM RESETB DOWN ============
573 16:36:22.473558 ========== PULL DRAM RESETB DOWN end =========
574 16:36:22.480366 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 16:36:22.484067 ===================================
576 16:36:22.487724 LPDDR4 DRAM CONFIGURATION
577 16:36:22.490769 ===================================
578 16:36:22.490848 EX_ROW_EN[0] = 0x0
579 16:36:22.494322 EX_ROW_EN[1] = 0x0
580 16:36:22.494427 LP4Y_EN = 0x0
581 16:36:22.497176 WORK_FSP = 0x0
582 16:36:22.497275 WL = 0x2
583 16:36:22.500555 RL = 0x2
584 16:36:22.500653 BL = 0x2
585 16:36:22.503996 RPST = 0x0
586 16:36:22.504074 RD_PRE = 0x0
587 16:36:22.507787 WR_PRE = 0x1
588 16:36:22.507864 WR_PST = 0x0
589 16:36:22.510651 DBI_WR = 0x0
590 16:36:22.510752 DBI_RD = 0x0
591 16:36:22.514274 OTF = 0x1
592 16:36:22.517199 ===================================
593 16:36:22.520617 ===================================
594 16:36:22.520717 ANA top config
595 16:36:22.523999 ===================================
596 16:36:22.527987 DLL_ASYNC_EN = 0
597 16:36:22.531052 ALL_SLAVE_EN = 1
598 16:36:22.534047 NEW_RANK_MODE = 1
599 16:36:22.534130 DLL_IDLE_MODE = 1
600 16:36:22.537858 LP45_APHY_COMB_EN = 1
601 16:36:22.540771 TX_ODT_DIS = 1
602 16:36:22.544519 NEW_8X_MODE = 1
603 16:36:22.547521 ===================================
604 16:36:22.550811 ===================================
605 16:36:22.554542 data_rate = 1600
606 16:36:22.554690 CKR = 1
607 16:36:22.557597 DQ_P2S_RATIO = 8
608 16:36:22.561484 ===================================
609 16:36:22.564500 CA_P2S_RATIO = 8
610 16:36:22.567677 DQ_CA_OPEN = 0
611 16:36:22.570763 DQ_SEMI_OPEN = 0
612 16:36:22.570950 CA_SEMI_OPEN = 0
613 16:36:22.574822 CA_FULL_RATE = 0
614 16:36:22.577572 DQ_CKDIV4_EN = 1
615 16:36:22.581346 CA_CKDIV4_EN = 1
616 16:36:22.584290 CA_PREDIV_EN = 0
617 16:36:22.588150 PH8_DLY = 0
618 16:36:22.588459 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 16:36:22.591114 DQ_AAMCK_DIV = 4
620 16:36:22.594846 CA_AAMCK_DIV = 4
621 16:36:22.597868 CA_ADMCK_DIV = 4
622 16:36:22.601478 DQ_TRACK_CA_EN = 0
623 16:36:22.604494 CA_PICK = 800
624 16:36:22.604773 CA_MCKIO = 800
625 16:36:22.608056 MCKIO_SEMI = 0
626 16:36:22.611557 PLL_FREQ = 3068
627 16:36:22.614313 DQ_UI_PI_RATIO = 32
628 16:36:22.618236 CA_UI_PI_RATIO = 0
629 16:36:22.621015 ===================================
630 16:36:22.624949 ===================================
631 16:36:22.627604 memory_type:LPDDR4
632 16:36:22.627751 GP_NUM : 10
633 16:36:22.631385 SRAM_EN : 1
634 16:36:22.631542 MD32_EN : 0
635 16:36:22.634801 ===================================
636 16:36:22.638324 [ANA_INIT] >>>>>>>>>>>>>>
637 16:36:22.641244 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 16:36:22.644549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 16:36:22.647947 ===================================
640 16:36:22.651321 data_rate = 1600,PCW = 0X7600
641 16:36:22.655045 ===================================
642 16:36:22.657989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 16:36:22.661631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 16:36:22.668379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 16:36:22.671402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 16:36:22.674578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 16:36:22.678184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 16:36:22.681182 [ANA_INIT] flow start
649 16:36:22.685047 [ANA_INIT] PLL >>>>>>>>
650 16:36:22.685190 [ANA_INIT] PLL <<<<<<<<
651 16:36:22.688587 [ANA_INIT] MIDPI >>>>>>>>
652 16:36:22.691644 [ANA_INIT] MIDPI <<<<<<<<
653 16:36:22.691784 [ANA_INIT] DLL >>>>>>>>
654 16:36:22.694685 [ANA_INIT] flow end
655 16:36:22.698423 ============ LP4 DIFF to SE enter ============
656 16:36:22.705191 ============ LP4 DIFF to SE exit ============
657 16:36:22.705437 [ANA_INIT] <<<<<<<<<<<<<
658 16:36:22.708264 [Flow] Enable top DCM control >>>>>
659 16:36:22.711316 [Flow] Enable top DCM control <<<<<
660 16:36:22.715019 Enable DLL master slave shuffle
661 16:36:22.721799 ==============================================================
662 16:36:22.722006 Gating Mode config
663 16:36:22.728252 ==============================================================
664 16:36:22.728451 Config description:
665 16:36:22.738254 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 16:36:22.745112 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 16:36:22.751770 SELPH_MODE 0: By rank 1: By Phase
668 16:36:22.755370 ==============================================================
669 16:36:22.758189 GAT_TRACK_EN = 1
670 16:36:22.761815 RX_GATING_MODE = 2
671 16:36:22.765315 RX_GATING_TRACK_MODE = 2
672 16:36:22.768723 SELPH_MODE = 1
673 16:36:22.771465 PICG_EARLY_EN = 1
674 16:36:22.775751 VALID_LAT_VALUE = 1
675 16:36:22.778884 ==============================================================
676 16:36:22.783185 Enter into Gating configuration >>>>
677 16:36:22.786952 Exit from Gating configuration <<<<
678 16:36:22.790723 Enter into DVFS_PRE_config >>>>>
679 16:36:22.801912 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 16:36:22.805586 Exit from DVFS_PRE_config <<<<<
681 16:36:22.809320 Enter into PICG configuration >>>>
682 16:36:22.809494 Exit from PICG configuration <<<<
683 16:36:22.812505 [RX_INPUT] configuration >>>>>
684 16:36:22.815598 [RX_INPUT] configuration <<<<<
685 16:36:22.822363 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 16:36:22.826135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 16:36:22.832912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 16:36:22.839309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 16:36:22.845642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 16:36:22.852628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 16:36:22.855555 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 16:36:22.859291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 16:36:22.862304 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 16:36:22.869178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 16:36:22.872315 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 16:36:22.875925 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 16:36:22.879627 ===================================
698 16:36:22.882416 LPDDR4 DRAM CONFIGURATION
699 16:36:22.885960 ===================================
700 16:36:22.886102 EX_ROW_EN[0] = 0x0
701 16:36:22.889501 EX_ROW_EN[1] = 0x0
702 16:36:22.889647 LP4Y_EN = 0x0
703 16:36:22.893082 WORK_FSP = 0x0
704 16:36:22.893217 WL = 0x2
705 16:36:22.895943 RL = 0x2
706 16:36:22.896074 BL = 0x2
707 16:36:22.899476 RPST = 0x0
708 16:36:22.899639 RD_PRE = 0x0
709 16:36:22.902750 WR_PRE = 0x1
710 16:36:22.902884 WR_PST = 0x0
711 16:36:22.906601 DBI_WR = 0x0
712 16:36:22.906753 DBI_RD = 0x0
713 16:36:22.909771 OTF = 0x1
714 16:36:22.912658 ===================================
715 16:36:22.916485 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 16:36:22.919557 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 16:36:22.926477 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 16:36:22.930287 ===================================
719 16:36:22.930443 LPDDR4 DRAM CONFIGURATION
720 16:36:22.933235 ===================================
721 16:36:22.936868 EX_ROW_EN[0] = 0x10
722 16:36:22.939762 EX_ROW_EN[1] = 0x0
723 16:36:22.939887 LP4Y_EN = 0x0
724 16:36:22.942881 WORK_FSP = 0x0
725 16:36:22.943004 WL = 0x2
726 16:36:22.946753 RL = 0x2
727 16:36:22.946859 BL = 0x2
728 16:36:22.949803 RPST = 0x0
729 16:36:22.949909 RD_PRE = 0x0
730 16:36:22.953356 WR_PRE = 0x1
731 16:36:22.953471 WR_PST = 0x0
732 16:36:22.956947 DBI_WR = 0x0
733 16:36:22.957056 DBI_RD = 0x0
734 16:36:22.960363 OTF = 0x1
735 16:36:22.963127 ===================================
736 16:36:22.970172 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 16:36:22.973532 nWR fixed to 40
738 16:36:22.973658 [ModeRegInit_LP4] CH0 RK0
739 16:36:22.976436 [ModeRegInit_LP4] CH0 RK1
740 16:36:22.980182 [ModeRegInit_LP4] CH1 RK0
741 16:36:22.980316 [ModeRegInit_LP4] CH1 RK1
742 16:36:22.983237 match AC timing 13
743 16:36:22.986991 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 16:36:22.989891 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 16:36:22.996601 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 16:36:23.000250 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 16:36:23.006551 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 16:36:23.006686 [EMI DOE] emi_dcm 0
749 16:36:23.010402 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 16:36:23.013290 ==
751 16:36:23.016382 Dram Type= 6, Freq= 0, CH_0, rank 0
752 16:36:23.020288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 16:36:23.020402 ==
754 16:36:23.023340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 16:36:23.030181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 16:36:23.039850 [CA 0] Center 36 (6~67) winsize 62
757 16:36:23.042927 [CA 1] Center 36 (6~67) winsize 62
758 16:36:23.046771 [CA 2] Center 34 (4~65) winsize 62
759 16:36:23.049939 [CA 3] Center 33 (3~64) winsize 62
760 16:36:23.053257 [CA 4] Center 33 (3~64) winsize 62
761 16:36:23.056939 [CA 5] Center 32 (3~62) winsize 60
762 16:36:23.057050
763 16:36:23.060657 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 16:36:23.060744
765 16:36:23.063593 [CATrainingPosCal] consider 1 rank data
766 16:36:23.067475 u2DelayCellTimex100 = 270/100 ps
767 16:36:23.070666 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 16:36:23.074369 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 16:36:23.077438 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 16:36:23.080411 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
771 16:36:23.083789 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
772 16:36:23.090621 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
773 16:36:23.090757
774 16:36:23.093883 CA PerBit enable=1, Macro0, CA PI delay=32
775 16:36:23.093992
776 16:36:23.097193 [CBTSetCACLKResult] CA Dly = 32
777 16:36:23.097343 CS Dly: 4 (0~35)
778 16:36:23.097451 ==
779 16:36:23.100519 Dram Type= 6, Freq= 0, CH_0, rank 1
780 16:36:23.103860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 16:36:23.107599 ==
782 16:36:23.110635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 16:36:23.117217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 16:36:23.126199 [CA 0] Center 36 (6~67) winsize 62
785 16:36:23.129009 [CA 1] Center 36 (6~67) winsize 62
786 16:36:23.132889 [CA 2] Center 34 (3~65) winsize 63
787 16:36:23.135993 [CA 3] Center 33 (3~64) winsize 62
788 16:36:23.139090 [CA 4] Center 32 (2~63) winsize 62
789 16:36:23.142789 [CA 5] Center 32 (2~63) winsize 62
790 16:36:23.142889
791 16:36:23.145937 [CmdBusTrainingLP45] Vref(ca) range 1: 30
792 16:36:23.146036
793 16:36:23.149677 [CATrainingPosCal] consider 2 rank data
794 16:36:23.152701 u2DelayCellTimex100 = 270/100 ps
795 16:36:23.155723 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 16:36:23.159395 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 16:36:23.166110 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
798 16:36:23.169841 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
799 16:36:23.172990 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
800 16:36:23.176002 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
801 16:36:23.176131
802 16:36:23.179843 CA PerBit enable=1, Macro0, CA PI delay=32
803 16:36:23.179946
804 16:36:23.182902 [CBTSetCACLKResult] CA Dly = 32
805 16:36:23.183008 CS Dly: 5 (0~37)
806 16:36:23.183133
807 16:36:23.186071 ----->DramcWriteLeveling(PI) begin...
808 16:36:23.186221 ==
809 16:36:23.190070 Dram Type= 6, Freq= 0, CH_0, rank 0
810 16:36:23.196643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 16:36:23.196852 ==
812 16:36:23.199533 Write leveling (Byte 0): 33 => 33
813 16:36:23.203091 Write leveling (Byte 1): 33 => 33
814 16:36:23.203316 DramcWriteLeveling(PI) end<-----
815 16:36:23.206606
816 16:36:23.206707 ==
817 16:36:23.209355 Dram Type= 6, Freq= 0, CH_0, rank 0
818 16:36:23.212845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 16:36:23.212927 ==
820 16:36:23.216365 [Gating] SW mode calibration
821 16:36:23.222770 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 16:36:23.226486 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 16:36:23.232968 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 16:36:23.236790 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 16:36:23.239789 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 16:36:23.246140 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 16:36:23.250094 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 16:36:23.253074 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 16:36:23.259786 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 16:36:23.263694 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 16:36:23.266878 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 16:36:23.269654 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 16:36:23.276322 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 16:36:23.280055 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 16:36:23.283000 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 16:36:23.289861 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 16:36:23.293589 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 16:36:23.296534 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 16:36:23.303342 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 16:36:23.306932 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 16:36:23.309857 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 16:36:23.316826 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 16:36:23.319657 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 16:36:23.323363 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 16:36:23.329862 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 16:36:23.333301 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 16:36:23.336783 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 16:36:23.340063 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 16:36:23.346448 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
850 16:36:23.349958 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
851 16:36:23.353363 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 16:36:23.360480 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 16:36:23.364279 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 16:36:23.367300 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 16:36:23.371121 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 16:36:23.377938 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
857 16:36:23.380926 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (0 0)
858 16:36:23.384534 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
859 16:36:23.390659 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:36:23.394313 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:36:23.397222 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:36:23.404177 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:36:23.407928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:36:23.411048 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
865 16:36:23.417196 0 11 8 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
866 16:36:23.420849 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
867 16:36:23.424269 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 16:36:23.431037 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 16:36:23.433922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 16:36:23.437430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 16:36:23.444180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 16:36:23.447777 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 16:36:23.450573 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 16:36:23.457332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 16:36:23.461055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 16:36:23.463836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 16:36:23.467344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 16:36:23.474247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 16:36:23.477285 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 16:36:23.481228 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 16:36:23.487243 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 16:36:23.491321 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 16:36:23.494256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 16:36:23.500929 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 16:36:23.503894 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 16:36:23.507707 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 16:36:23.514460 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 16:36:23.517483 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 16:36:23.521425 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 16:36:23.524533 Total UI for P1: 0, mck2ui 16
891 16:36:23.527541 best dqsien dly found for B0: ( 0, 14, 6)
892 16:36:23.531214 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
893 16:36:23.537742 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 16:36:23.541292 Total UI for P1: 0, mck2ui 16
895 16:36:23.544804 best dqsien dly found for B1: ( 0, 14, 10)
896 16:36:23.547592 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
897 16:36:23.551075 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
898 16:36:23.551151
899 16:36:23.554792 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
900 16:36:23.557858 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
901 16:36:23.560910 [Gating] SW calibration Done
902 16:36:23.560982 ==
903 16:36:23.564509 Dram Type= 6, Freq= 0, CH_0, rank 0
904 16:36:23.568407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 16:36:23.568570 ==
906 16:36:23.571540 RX Vref Scan: 0
907 16:36:23.571617
908 16:36:23.571674 RX Vref 0 -> 0, step: 1
909 16:36:23.571727
910 16:36:23.574519 RX Delay -130 -> 252, step: 16
911 16:36:23.581230 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
912 16:36:23.584859 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
913 16:36:23.588301 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
914 16:36:23.591166 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
915 16:36:23.594903 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
916 16:36:23.597941 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
917 16:36:23.604926 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
918 16:36:23.607773 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
919 16:36:23.611641 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
920 16:36:23.614858 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
921 16:36:23.617933 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
922 16:36:23.624676 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
923 16:36:23.628390 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
924 16:36:23.631241 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
925 16:36:23.635061 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
926 16:36:23.638166 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
927 16:36:23.641214 ==
928 16:36:23.645041 Dram Type= 6, Freq= 0, CH_0, rank 0
929 16:36:23.648130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 16:36:23.648202 ==
931 16:36:23.648272 DQS Delay:
932 16:36:23.651705 DQS0 = 0, DQS1 = 0
933 16:36:23.651777 DQM Delay:
934 16:36:23.654610 DQM0 = 90, DQM1 = 81
935 16:36:23.654682 DQ Delay:
936 16:36:23.658336 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
937 16:36:23.661165 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
938 16:36:23.664675 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
939 16:36:23.667951 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
940 16:36:23.668030
941 16:36:23.668090
942 16:36:23.668143 ==
943 16:36:23.671579 Dram Type= 6, Freq= 0, CH_0, rank 0
944 16:36:23.674544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 16:36:23.674613 ==
946 16:36:23.674670
947 16:36:23.674736
948 16:36:23.677913 TX Vref Scan disable
949 16:36:23.681364 == TX Byte 0 ==
950 16:36:23.685222 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
951 16:36:23.688169 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
952 16:36:23.691895 == TX Byte 1 ==
953 16:36:23.694921 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
954 16:36:23.698454 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
955 16:36:23.698525 ==
956 16:36:23.702062 Dram Type= 6, Freq= 0, CH_0, rank 0
957 16:36:23.704926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 16:36:23.707894 ==
959 16:36:23.719134 TX Vref=22, minBit 8, minWin=27, winSum=445
960 16:36:23.722328 TX Vref=24, minBit 10, minWin=27, winSum=451
961 16:36:23.726146 TX Vref=26, minBit 11, minWin=27, winSum=454
962 16:36:23.729107 TX Vref=28, minBit 0, minWin=28, winSum=454
963 16:36:23.732973 TX Vref=30, minBit 5, minWin=28, winSum=456
964 16:36:23.738943 TX Vref=32, minBit 11, minWin=27, winSum=453
965 16:36:23.742860 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
966 16:36:23.742950
967 16:36:23.745899 Final TX Range 1 Vref 30
968 16:36:23.745966
969 16:36:23.746029 ==
970 16:36:23.749027 Dram Type= 6, Freq= 0, CH_0, rank 0
971 16:36:23.752213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 16:36:23.756062 ==
973 16:36:23.756134
974 16:36:23.756190
975 16:36:23.756242 TX Vref Scan disable
976 16:36:23.759063 == TX Byte 0 ==
977 16:36:23.762903 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
978 16:36:23.765896 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
979 16:36:23.768997 == TX Byte 1 ==
980 16:36:23.772789 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 16:36:23.776200 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 16:36:23.779073
983 16:36:23.779225 [DATLAT]
984 16:36:23.779313 Freq=800, CH0 RK0
985 16:36:23.779402
986 16:36:23.782972 DATLAT Default: 0xa
987 16:36:23.783066 0, 0xFFFF, sum = 0
988 16:36:23.785958 1, 0xFFFF, sum = 0
989 16:36:23.786028 2, 0xFFFF, sum = 0
990 16:36:23.789422 3, 0xFFFF, sum = 0
991 16:36:23.789522 4, 0xFFFF, sum = 0
992 16:36:23.792875 5, 0xFFFF, sum = 0
993 16:36:23.792997 6, 0xFFFF, sum = 0
994 16:36:23.795858 7, 0xFFFF, sum = 0
995 16:36:23.799558 8, 0xFFFF, sum = 0
996 16:36:23.799649 9, 0x0, sum = 1
997 16:36:23.799718 10, 0x0, sum = 2
998 16:36:23.802761 11, 0x0, sum = 3
999 16:36:23.802841 12, 0x0, sum = 4
1000 16:36:23.806279 best_step = 10
1001 16:36:23.806371
1002 16:36:23.806480 ==
1003 16:36:23.809144 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 16:36:23.812876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 16:36:23.812953 ==
1006 16:36:23.816322 RX Vref Scan: 1
1007 16:36:23.816417
1008 16:36:23.816478 Set Vref Range= 32 -> 127
1009 16:36:23.816533
1010 16:36:23.819208 RX Vref 32 -> 127, step: 1
1011 16:36:23.819289
1012 16:36:23.822891 RX Delay -79 -> 252, step: 8
1013 16:36:23.822974
1014 16:36:23.826412 Set Vref, RX VrefLevel [Byte0]: 32
1015 16:36:23.829532 [Byte1]: 32
1016 16:36:23.829675
1017 16:36:23.832782 Set Vref, RX VrefLevel [Byte0]: 33
1018 16:36:23.835753 [Byte1]: 33
1019 16:36:23.839500
1020 16:36:23.839577 Set Vref, RX VrefLevel [Byte0]: 34
1021 16:36:23.842527 [Byte1]: 34
1022 16:36:23.847226
1023 16:36:23.847303 Set Vref, RX VrefLevel [Byte0]: 35
1024 16:36:23.850288 [Byte1]: 35
1025 16:36:23.854870
1026 16:36:23.854947 Set Vref, RX VrefLevel [Byte0]: 36
1027 16:36:23.857739 [Byte1]: 36
1028 16:36:23.862381
1029 16:36:23.862459 Set Vref, RX VrefLevel [Byte0]: 37
1030 16:36:23.865391 [Byte1]: 37
1031 16:36:23.869864
1032 16:36:23.869947 Set Vref, RX VrefLevel [Byte0]: 38
1033 16:36:23.872783 [Byte1]: 38
1034 16:36:23.877208
1035 16:36:23.877333 Set Vref, RX VrefLevel [Byte0]: 39
1036 16:36:23.880998 [Byte1]: 39
1037 16:36:23.884494
1038 16:36:23.884569 Set Vref, RX VrefLevel [Byte0]: 40
1039 16:36:23.888084 [Byte1]: 40
1040 16:36:23.892461
1041 16:36:23.892540 Set Vref, RX VrefLevel [Byte0]: 41
1042 16:36:23.896134 [Byte1]: 41
1043 16:36:23.899688
1044 16:36:23.899762 Set Vref, RX VrefLevel [Byte0]: 42
1045 16:36:23.903226 [Byte1]: 42
1046 16:36:23.907108
1047 16:36:23.907190 Set Vref, RX VrefLevel [Byte0]: 43
1048 16:36:23.910910 [Byte1]: 43
1049 16:36:23.915416
1050 16:36:23.915490 Set Vref, RX VrefLevel [Byte0]: 44
1051 16:36:23.918481 [Byte1]: 44
1052 16:36:23.922947
1053 16:36:23.923026 Set Vref, RX VrefLevel [Byte0]: 45
1054 16:36:23.925952 [Byte1]: 45
1055 16:36:23.930238
1056 16:36:23.930311 Set Vref, RX VrefLevel [Byte0]: 46
1057 16:36:23.933049 [Byte1]: 46
1058 16:36:23.937332
1059 16:36:23.937434 Set Vref, RX VrefLevel [Byte0]: 47
1060 16:36:23.940962 [Byte1]: 47
1061 16:36:23.945352
1062 16:36:23.945494 Set Vref, RX VrefLevel [Byte0]: 48
1063 16:36:23.948386 [Byte1]: 48
1064 16:36:23.952730
1065 16:36:23.952811 Set Vref, RX VrefLevel [Byte0]: 49
1066 16:36:23.955856 [Byte1]: 49
1067 16:36:23.960352
1068 16:36:23.960428 Set Vref, RX VrefLevel [Byte0]: 50
1069 16:36:23.963315 [Byte1]: 50
1070 16:36:23.967980
1071 16:36:23.968056 Set Vref, RX VrefLevel [Byte0]: 51
1072 16:36:23.970981 [Byte1]: 51
1073 16:36:23.975471
1074 16:36:23.975543 Set Vref, RX VrefLevel [Byte0]: 52
1075 16:36:23.978617 [Byte1]: 52
1076 16:36:23.983220
1077 16:36:23.983294 Set Vref, RX VrefLevel [Byte0]: 53
1078 16:36:23.986403 [Byte1]: 53
1079 16:36:23.990748
1080 16:36:23.990822 Set Vref, RX VrefLevel [Byte0]: 54
1081 16:36:23.993792 [Byte1]: 54
1082 16:36:23.997966
1083 16:36:23.998035 Set Vref, RX VrefLevel [Byte0]: 55
1084 16:36:24.001528 [Byte1]: 55
1085 16:36:24.005912
1086 16:36:24.005986 Set Vref, RX VrefLevel [Byte0]: 56
1087 16:36:24.008918 [Byte1]: 56
1088 16:36:24.013122
1089 16:36:24.013217 Set Vref, RX VrefLevel [Byte0]: 57
1090 16:36:24.016536 [Byte1]: 57
1091 16:36:24.020987
1092 16:36:24.021067 Set Vref, RX VrefLevel [Byte0]: 58
1093 16:36:24.023989 [Byte1]: 58
1094 16:36:24.028518
1095 16:36:24.028614 Set Vref, RX VrefLevel [Byte0]: 59
1096 16:36:24.031771 [Byte1]: 59
1097 16:36:24.036220
1098 16:36:24.036325 Set Vref, RX VrefLevel [Byte0]: 60
1099 16:36:24.039158 [Byte1]: 60
1100 16:36:24.043304
1101 16:36:24.043399 Set Vref, RX VrefLevel [Byte0]: 61
1102 16:36:24.046811 [Byte1]: 61
1103 16:36:24.050920
1104 16:36:24.051016 Set Vref, RX VrefLevel [Byte0]: 62
1105 16:36:24.054041 [Byte1]: 62
1106 16:36:24.058504
1107 16:36:24.058575 Set Vref, RX VrefLevel [Byte0]: 63
1108 16:36:24.061507 [Byte1]: 63
1109 16:36:24.066221
1110 16:36:24.066297 Set Vref, RX VrefLevel [Byte0]: 64
1111 16:36:24.069299 [Byte1]: 64
1112 16:36:24.073790
1113 16:36:24.073869 Set Vref, RX VrefLevel [Byte0]: 65
1114 16:36:24.076781 [Byte1]: 65
1115 16:36:24.081217
1116 16:36:24.081299 Set Vref, RX VrefLevel [Byte0]: 66
1117 16:36:24.084265 [Byte1]: 66
1118 16:36:24.088873
1119 16:36:24.088951 Set Vref, RX VrefLevel [Byte0]: 67
1120 16:36:24.091901 [Byte1]: 67
1121 16:36:24.096512
1122 16:36:24.096608 Set Vref, RX VrefLevel [Byte0]: 68
1123 16:36:24.099582 [Byte1]: 68
1124 16:36:24.104135
1125 16:36:24.104210 Set Vref, RX VrefLevel [Byte0]: 69
1126 16:36:24.107087 [Byte1]: 69
1127 16:36:24.111374
1128 16:36:24.111473 Set Vref, RX VrefLevel [Byte0]: 70
1129 16:36:24.114375 [Byte1]: 70
1130 16:36:24.119046
1131 16:36:24.119123 Set Vref, RX VrefLevel [Byte0]: 71
1132 16:36:24.121930 [Byte1]: 71
1133 16:36:24.126278
1134 16:36:24.126358 Set Vref, RX VrefLevel [Byte0]: 72
1135 16:36:24.130032 [Byte1]: 72
1136 16:36:24.133906
1137 16:36:24.137432 Set Vref, RX VrefLevel [Byte0]: 73
1138 16:36:24.140590 [Byte1]: 73
1139 16:36:24.140680
1140 16:36:24.143582 Set Vref, RX VrefLevel [Byte0]: 74
1141 16:36:24.147338 [Byte1]: 74
1142 16:36:24.147444
1143 16:36:24.150228 Set Vref, RX VrefLevel [Byte0]: 75
1144 16:36:24.153865 [Byte1]: 75
1145 16:36:24.153945
1146 16:36:24.157394 Set Vref, RX VrefLevel [Byte0]: 76
1147 16:36:24.160380 [Byte1]: 76
1148 16:36:24.164224
1149 16:36:24.164307 Set Vref, RX VrefLevel [Byte0]: 77
1150 16:36:24.167283 [Byte1]: 77
1151 16:36:24.171627
1152 16:36:24.171703 Final RX Vref Byte 0 = 54 to rank0
1153 16:36:24.175411 Final RX Vref Byte 1 = 55 to rank0
1154 16:36:24.178560 Final RX Vref Byte 0 = 54 to rank1
1155 16:36:24.182015 Final RX Vref Byte 1 = 55 to rank1==
1156 16:36:24.185124 Dram Type= 6, Freq= 0, CH_0, rank 0
1157 16:36:24.192262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 16:36:24.192367 ==
1159 16:36:24.192442 DQS Delay:
1160 16:36:24.192510 DQS0 = 0, DQS1 = 0
1161 16:36:24.195110 DQM Delay:
1162 16:36:24.195218 DQM0 = 91, DQM1 = 84
1163 16:36:24.198145 DQ Delay:
1164 16:36:24.202109 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1165 16:36:24.205093 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1166 16:36:24.208229 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1167 16:36:24.211943 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1168 16:36:24.212105
1169 16:36:24.212265
1170 16:36:24.218442 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a40, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1171 16:36:24.222214 CH0 RK0: MR19=606, MR18=4A40
1172 16:36:24.228304 CH0_RK0: MR19=0x606, MR18=0x4A40, DQSOSC=391, MR23=63, INC=96, DEC=64
1173 16:36:24.228531
1174 16:36:24.232094 ----->DramcWriteLeveling(PI) begin...
1175 16:36:24.232386 ==
1176 16:36:24.235323 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 16:36:24.239076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 16:36:24.239576 ==
1179 16:36:24.242090 Write leveling (Byte 0): 32 => 32
1180 16:36:24.245724 Write leveling (Byte 1): 30 => 30
1181 16:36:24.248544 DramcWriteLeveling(PI) end<-----
1182 16:36:24.249045
1183 16:36:24.249369 ==
1184 16:36:24.252336 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 16:36:24.255396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 16:36:24.255789 ==
1187 16:36:24.259214 [Gating] SW mode calibration
1188 16:36:24.265245 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1189 16:36:24.272380 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1190 16:36:24.275116 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 16:36:24.278822 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1192 16:36:24.322279 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1193 16:36:24.322725 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 16:36:24.322813 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 16:36:24.322918 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 16:36:24.322974 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 16:36:24.323028 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 16:36:24.323090 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 16:36:24.323145 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 16:36:24.323198 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 16:36:24.323250 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 16:36:24.364481 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 16:36:24.364622 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 16:36:24.364908 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 16:36:24.364978 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 16:36:24.365039 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 16:36:24.365098 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 16:36:24.365155 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1209 16:36:24.365210 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 16:36:24.368388 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 16:36:24.368473 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 16:36:24.372152 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 16:36:24.375216 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 16:36:24.381774 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 16:36:24.385693 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 16:36:24.388558 0 9 8 | B1->B0 | 2f2f 2d2c | 1 1 | (0 0) (0 0)
1217 16:36:24.395265 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 16:36:24.398292 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 16:36:24.402001 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 16:36:24.408584 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 16:36:24.411628 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 16:36:24.415389 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 16:36:24.421478 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1224 16:36:24.425238 0 10 8 | B1->B0 | 2a2a 2c2c | 0 0 | (0 1) (0 1)
1225 16:36:24.428185 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:36:24.431837 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:36:24.438490 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:36:24.441362 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:36:24.445222 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:36:24.451589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:36:24.455322 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:36:24.458366 0 11 8 | B1->B0 | 3d3d 3939 | 0 1 | (0 0) (0 0)
1233 16:36:24.465179 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 16:36:24.468630 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 16:36:24.471477 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 16:36:24.478243 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 16:36:24.481894 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 16:36:24.484828 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 16:36:24.491729 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 16:36:24.495446 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 16:36:24.498441 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 16:36:24.505214 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 16:36:24.508922 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 16:36:24.511884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 16:36:24.515501 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 16:36:24.522076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 16:36:24.525100 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 16:36:24.528838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 16:36:24.535635 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 16:36:24.538724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 16:36:24.542460 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 16:36:24.548525 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 16:36:24.552360 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 16:36:24.555389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 16:36:24.562402 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1256 16:36:24.565385 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1257 16:36:24.569104 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 16:36:24.572079 Total UI for P1: 0, mck2ui 16
1259 16:36:24.575784 best dqsien dly found for B0: ( 0, 14, 6)
1260 16:36:24.579236 Total UI for P1: 0, mck2ui 16
1261 16:36:24.582296 best dqsien dly found for B1: ( 0, 14, 10)
1262 16:36:24.585357 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1263 16:36:24.589197 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1264 16:36:24.589301
1265 16:36:24.592196 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1266 16:36:24.598972 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1267 16:36:24.599065 [Gating] SW calibration Done
1268 16:36:24.599127 ==
1269 16:36:24.602716 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 16:36:24.609239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 16:36:24.609326 ==
1272 16:36:24.609418 RX Vref Scan: 0
1273 16:36:24.609502
1274 16:36:24.612083 RX Vref 0 -> 0, step: 1
1275 16:36:24.612156
1276 16:36:24.615925 RX Delay -130 -> 252, step: 16
1277 16:36:24.618805 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1278 16:36:24.622553 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1279 16:36:24.625483 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1280 16:36:24.632122 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1281 16:36:24.635906 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1282 16:36:24.639015 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1283 16:36:24.642623 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1284 16:36:24.645433 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1285 16:36:24.649117 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1286 16:36:24.655761 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1287 16:36:24.658889 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1288 16:36:24.662824 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1289 16:36:24.665886 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1290 16:36:24.668972 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1291 16:36:24.675531 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1292 16:36:24.679254 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1293 16:36:24.679337 ==
1294 16:36:24.682256 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 16:36:24.685867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 16:36:24.685945 ==
1297 16:36:24.689241 DQS Delay:
1298 16:36:24.689320 DQS0 = 0, DQS1 = 0
1299 16:36:24.689393 DQM Delay:
1300 16:36:24.692349 DQM0 = 89, DQM1 = 82
1301 16:36:24.692426 DQ Delay:
1302 16:36:24.696078 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1303 16:36:24.699164 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1304 16:36:24.702193 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1305 16:36:24.705692 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1306 16:36:24.705769
1307 16:36:24.705829
1308 16:36:24.705885 ==
1309 16:36:24.709410 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 16:36:24.715921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 16:36:24.716005 ==
1312 16:36:24.716071
1313 16:36:24.716146
1314 16:36:24.716201 TX Vref Scan disable
1315 16:36:24.719001 == TX Byte 0 ==
1316 16:36:24.722633 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1317 16:36:24.725627 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1318 16:36:24.729481 == TX Byte 1 ==
1319 16:36:24.732428 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1320 16:36:24.736141 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1321 16:36:24.739124 ==
1322 16:36:24.742890 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 16:36:24.745916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 16:36:24.746020 ==
1325 16:36:24.758619 TX Vref=22, minBit 8, minWin=27, winSum=448
1326 16:36:24.762084 TX Vref=24, minBit 11, minWin=27, winSum=454
1327 16:36:24.765060 TX Vref=26, minBit 8, minWin=27, winSum=453
1328 16:36:24.768845 TX Vref=28, minBit 5, minWin=28, winSum=456
1329 16:36:24.771844 TX Vref=30, minBit 7, minWin=28, winSum=458
1330 16:36:24.778686 TX Vref=32, minBit 7, minWin=28, winSum=459
1331 16:36:24.781595 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 32
1332 16:36:24.781672
1333 16:36:24.785206 Final TX Range 1 Vref 32
1334 16:36:24.785283
1335 16:36:24.785342 ==
1336 16:36:24.788233 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 16:36:24.791956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 16:36:24.792033 ==
1339 16:36:24.794847
1340 16:36:24.794923
1341 16:36:24.794982 TX Vref Scan disable
1342 16:36:24.798288 == TX Byte 0 ==
1343 16:36:24.801946 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1344 16:36:24.805013 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1345 16:36:24.808792 == TX Byte 1 ==
1346 16:36:24.811896 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1347 16:36:24.815648 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1348 16:36:24.818719
1349 16:36:24.818814 [DATLAT]
1350 16:36:24.818875 Freq=800, CH0 RK1
1351 16:36:24.818931
1352 16:36:24.822296 DATLAT Default: 0xa
1353 16:36:24.822368 0, 0xFFFF, sum = 0
1354 16:36:24.825366 1, 0xFFFF, sum = 0
1355 16:36:24.825437 2, 0xFFFF, sum = 0
1356 16:36:24.828306 3, 0xFFFF, sum = 0
1357 16:36:24.828428 4, 0xFFFF, sum = 0
1358 16:36:24.832052 5, 0xFFFF, sum = 0
1359 16:36:24.832149 6, 0xFFFF, sum = 0
1360 16:36:24.834957 7, 0xFFFF, sum = 0
1361 16:36:24.838752 8, 0xFFFF, sum = 0
1362 16:36:24.838847 9, 0x0, sum = 1
1363 16:36:24.838935 10, 0x0, sum = 2
1364 16:36:24.841702 11, 0x0, sum = 3
1365 16:36:24.841800 12, 0x0, sum = 4
1366 16:36:24.845525 best_step = 10
1367 16:36:24.845642
1368 16:36:24.845705 ==
1369 16:36:24.848585 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 16:36:24.851612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 16:36:24.851711 ==
1372 16:36:24.855394 RX Vref Scan: 0
1373 16:36:24.855471
1374 16:36:24.855530 RX Vref 0 -> 0, step: 1
1375 16:36:24.855585
1376 16:36:24.859075 RX Delay -79 -> 252, step: 8
1377 16:36:24.865471 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1378 16:36:24.868893 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1379 16:36:24.872323 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1380 16:36:24.875285 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1381 16:36:24.879003 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1382 16:36:24.885126 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1383 16:36:24.889003 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1384 16:36:24.891900 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1385 16:36:24.895576 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1386 16:36:24.898776 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1387 16:36:24.902341 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1388 16:36:24.908450 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1389 16:36:24.912071 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1390 16:36:24.915477 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1391 16:36:24.918585 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1392 16:36:24.925445 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1393 16:36:24.925574 ==
1394 16:36:24.928983 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 16:36:24.931921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 16:36:24.932037 ==
1397 16:36:24.932121 DQS Delay:
1398 16:36:24.935517 DQS0 = 0, DQS1 = 0
1399 16:36:24.935612 DQM Delay:
1400 16:36:24.939222 DQM0 = 93, DQM1 = 83
1401 16:36:24.939297 DQ Delay:
1402 16:36:24.942055 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1403 16:36:24.945732 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1404 16:36:24.948792 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1405 16:36:24.952397 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1406 16:36:24.952474
1407 16:36:24.952532
1408 16:36:24.959047 [DQSOSCAuto] RK1, (LSB)MR18= 0x4516, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1409 16:36:24.962045 CH0 RK1: MR19=606, MR18=4516
1410 16:36:24.969396 CH0_RK1: MR19=0x606, MR18=0x4516, DQSOSC=392, MR23=63, INC=96, DEC=64
1411 16:36:24.972404 [RxdqsGatingPostProcess] freq 800
1412 16:36:24.979031 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1413 16:36:24.979112 Pre-setting of DQS Precalculation
1414 16:36:24.985554 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1415 16:36:24.985660 ==
1416 16:36:24.989278 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 16:36:24.992365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 16:36:24.992441 ==
1419 16:36:24.998968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 16:36:25.005642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 16:36:25.013504 [CA 0] Center 36 (6~67) winsize 62
1422 16:36:25.017233 [CA 1] Center 36 (6~67) winsize 62
1423 16:36:25.020177 [CA 2] Center 35 (4~66) winsize 63
1424 16:36:25.024002 [CA 3] Center 34 (4~65) winsize 62
1425 16:36:25.026793 [CA 4] Center 35 (5~65) winsize 61
1426 16:36:25.030314 [CA 5] Center 34 (4~64) winsize 61
1427 16:36:25.030388
1428 16:36:25.033236 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 16:36:25.033343
1430 16:36:25.036774 [CATrainingPosCal] consider 1 rank data
1431 16:36:25.039936 u2DelayCellTimex100 = 270/100 ps
1432 16:36:25.043589 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 16:36:25.047357 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 16:36:25.053561 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1435 16:36:25.056637 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 16:36:25.060370 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1437 16:36:25.063349 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1438 16:36:25.063448
1439 16:36:25.066999 CA PerBit enable=1, Macro0, CA PI delay=34
1440 16:36:25.067093
1441 16:36:25.070112 [CBTSetCACLKResult] CA Dly = 34
1442 16:36:25.070210 CS Dly: 6 (0~37)
1443 16:36:25.070309 ==
1444 16:36:25.073115 Dram Type= 6, Freq= 0, CH_1, rank 1
1445 16:36:25.080034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 16:36:25.080129 ==
1447 16:36:25.083866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 16:36:25.090271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 16:36:25.099808 [CA 0] Center 36 (6~67) winsize 62
1450 16:36:25.102974 [CA 1] Center 37 (6~68) winsize 63
1451 16:36:25.106372 [CA 2] Center 35 (4~66) winsize 63
1452 16:36:25.109367 [CA 3] Center 34 (4~65) winsize 62
1453 16:36:25.113258 [CA 4] Center 35 (5~66) winsize 62
1454 16:36:25.116256 [CA 5] Center 34 (4~65) winsize 62
1455 16:36:25.116352
1456 16:36:25.120127 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 16:36:25.120223
1458 16:36:25.123205 [CATrainingPosCal] consider 2 rank data
1459 16:36:25.126337 u2DelayCellTimex100 = 270/100 ps
1460 16:36:25.130027 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 16:36:25.133118 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 16:36:25.139885 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1463 16:36:25.143314 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 16:36:25.146803 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1465 16:36:25.149631 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 16:36:25.149722
1467 16:36:25.153301 CA PerBit enable=1, Macro0, CA PI delay=34
1468 16:36:25.153412
1469 16:36:25.156381 [CBTSetCACLKResult] CA Dly = 34
1470 16:36:25.156452 CS Dly: 6 (0~38)
1471 16:36:25.156524
1472 16:36:25.160091 ----->DramcWriteLeveling(PI) begin...
1473 16:36:25.160244 ==
1474 16:36:25.163218 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 16:36:25.170175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 16:36:25.170257 ==
1477 16:36:25.173200 Write leveling (Byte 0): 27 => 27
1478 16:36:25.176824 Write leveling (Byte 1): 27 => 27
1479 16:36:25.176903 DramcWriteLeveling(PI) end<-----
1480 16:36:25.176964
1481 16:36:25.179827 ==
1482 16:36:25.183686 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 16:36:25.186809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 16:36:25.186887 ==
1485 16:36:25.189683 [Gating] SW mode calibration
1486 16:36:25.197008 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1487 16:36:25.199867 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1488 16:36:25.206546 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1489 16:36:25.210378 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1490 16:36:25.213369 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 16:36:25.220364 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 16:36:25.223395 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 16:36:25.226617 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 16:36:25.233375 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 16:36:25.237117 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 16:36:25.240238 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 16:36:25.243364 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 16:36:25.250198 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 16:36:25.253187 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 16:36:25.256792 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 16:36:25.263546 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 16:36:25.266429 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 16:36:25.269898 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 16:36:25.276943 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1505 16:36:25.279910 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1506 16:36:25.283399 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 16:36:25.290502 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 16:36:25.293059 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 16:36:25.297099 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 16:36:25.303559 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 16:36:25.306462 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 16:36:25.310206 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 16:36:25.317170 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1514 16:36:25.320176 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1515 16:36:25.323781 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 16:36:25.329782 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 16:36:25.333345 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 16:36:25.336872 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 16:36:25.339888 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 16:36:25.346757 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1521 16:36:25.350295 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (1 1) (1 1)
1522 16:36:25.353265 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1523 16:36:25.359979 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 16:36:25.363467 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:36:25.366575 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:36:25.373255 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:36:25.376866 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:36:25.379853 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:36:25.386594 0 11 4 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
1530 16:36:25.390329 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1531 16:36:25.393220 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 16:36:25.399772 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 16:36:25.403502 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 16:36:25.406520 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 16:36:25.413260 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 16:36:25.416707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 16:36:25.419955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1538 16:36:25.426778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 16:36:25.430454 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 16:36:25.433491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 16:36:25.437239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 16:36:25.443828 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 16:36:25.447393 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 16:36:25.450080 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 16:36:25.456783 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 16:36:25.460456 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 16:36:25.463491 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 16:36:25.470250 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 16:36:25.474129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 16:36:25.476996 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 16:36:25.483695 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 16:36:25.486743 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 16:36:25.490386 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1554 16:36:25.497575 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 16:36:25.498030 Total UI for P1: 0, mck2ui 16
1556 16:36:25.504115 best dqsien dly found for B0: ( 0, 14, 4)
1557 16:36:25.504338 Total UI for P1: 0, mck2ui 16
1558 16:36:25.506871 best dqsien dly found for B1: ( 0, 14, 4)
1559 16:36:25.513627 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1560 16:36:25.516653 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1561 16:36:25.516879
1562 16:36:25.520250 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1563 16:36:25.523630 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1564 16:36:25.526746 [Gating] SW calibration Done
1565 16:36:25.527049 ==
1566 16:36:25.530855 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 16:36:25.533760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 16:36:25.534084 ==
1569 16:36:25.534274 RX Vref Scan: 0
1570 16:36:25.536728
1571 16:36:25.537039 RX Vref 0 -> 0, step: 1
1572 16:36:25.537252
1573 16:36:25.540543 RX Delay -130 -> 252, step: 16
1574 16:36:25.543361 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1575 16:36:25.547411 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1576 16:36:25.553334 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1577 16:36:25.557122 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1578 16:36:25.560038 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1579 16:36:25.563535 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1580 16:36:25.566970 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1581 16:36:25.573951 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1582 16:36:25.576813 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1583 16:36:25.580584 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1584 16:36:25.583445 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1585 16:36:25.587112 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1586 16:36:25.593648 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1587 16:36:25.596590 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1588 16:36:25.600488 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1589 16:36:25.603981 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1590 16:36:25.604209 ==
1591 16:36:25.607048 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 16:36:25.613484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 16:36:25.613735 ==
1594 16:36:25.613933 DQS Delay:
1595 16:36:25.617262 DQS0 = 0, DQS1 = 0
1596 16:36:25.617392 DQM Delay:
1597 16:36:25.617501 DQM0 = 93, DQM1 = 87
1598 16:36:25.620436 DQ Delay:
1599 16:36:25.624252 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1600 16:36:25.627487 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1601 16:36:25.630711 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1602 16:36:25.634440 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1603 16:36:25.634838
1604 16:36:25.635139
1605 16:36:25.635420 ==
1606 16:36:25.637363 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 16:36:25.640994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 16:36:25.641384 ==
1609 16:36:25.641827
1610 16:36:25.642136
1611 16:36:25.643998 TX Vref Scan disable
1612 16:36:25.644386 == TX Byte 0 ==
1613 16:36:25.650661 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1614 16:36:25.654450 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1615 16:36:25.654850 == TX Byte 1 ==
1616 16:36:25.660329 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1617 16:36:25.663836 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1618 16:36:25.664114 ==
1619 16:36:25.667454 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 16:36:25.670420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 16:36:25.670600 ==
1622 16:36:25.684368 TX Vref=22, minBit 0, minWin=26, winSum=439
1623 16:36:25.687719 TX Vref=24, minBit 4, minWin=26, winSum=444
1624 16:36:25.690626 TX Vref=26, minBit 2, minWin=27, winSum=449
1625 16:36:25.694146 TX Vref=28, minBit 1, minWin=27, winSum=450
1626 16:36:25.697787 TX Vref=30, minBit 1, minWin=27, winSum=451
1627 16:36:25.700558 TX Vref=32, minBit 1, minWin=27, winSum=447
1628 16:36:25.707300 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1629 16:36:25.707455
1630 16:36:25.710930 Final TX Range 1 Vref 30
1631 16:36:25.711089
1632 16:36:25.711212 ==
1633 16:36:25.713950 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 16:36:25.717666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 16:36:25.717842 ==
1636 16:36:25.717958
1637 16:36:25.720525
1638 16:36:25.720711 TX Vref Scan disable
1639 16:36:25.724357 == TX Byte 0 ==
1640 16:36:25.727504 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 16:36:25.731191 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 16:36:25.734229 == TX Byte 1 ==
1643 16:36:25.737829 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 16:36:25.740653 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 16:36:25.740812
1646 16:36:25.744074 [DATLAT]
1647 16:36:25.744262 Freq=800, CH1 RK0
1648 16:36:25.744427
1649 16:36:25.747179 DATLAT Default: 0xa
1650 16:36:25.747326 0, 0xFFFF, sum = 0
1651 16:36:25.750885 1, 0xFFFF, sum = 0
1652 16:36:25.751031 2, 0xFFFF, sum = 0
1653 16:36:25.754077 3, 0xFFFF, sum = 0
1654 16:36:25.754221 4, 0xFFFF, sum = 0
1655 16:36:25.757924 5, 0xFFFF, sum = 0
1656 16:36:25.758066 6, 0xFFFF, sum = 0
1657 16:36:25.760948 7, 0xFFFF, sum = 0
1658 16:36:25.761091 8, 0xFFFF, sum = 0
1659 16:36:25.764021 9, 0x0, sum = 1
1660 16:36:25.764162 10, 0x0, sum = 2
1661 16:36:25.767691 11, 0x0, sum = 3
1662 16:36:25.767832 12, 0x0, sum = 4
1663 16:36:25.770605 best_step = 10
1664 16:36:25.770755
1665 16:36:25.770916 ==
1666 16:36:25.774332 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 16:36:25.777268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 16:36:25.777453 ==
1669 16:36:25.780981 RX Vref Scan: 1
1670 16:36:25.781115
1671 16:36:25.781269 Set Vref Range= 32 -> 127
1672 16:36:25.781415
1673 16:36:25.783857 RX Vref 32 -> 127, step: 1
1674 16:36:25.784003
1675 16:36:25.787586 RX Delay -79 -> 252, step: 8
1676 16:36:25.787729
1677 16:36:25.790598 Set Vref, RX VrefLevel [Byte0]: 32
1678 16:36:25.794208 [Byte1]: 32
1679 16:36:25.794386
1680 16:36:25.797151 Set Vref, RX VrefLevel [Byte0]: 33
1681 16:36:25.800564 [Byte1]: 33
1682 16:36:25.804172
1683 16:36:25.804296 Set Vref, RX VrefLevel [Byte0]: 34
1684 16:36:25.807569 [Byte1]: 34
1685 16:36:25.811892
1686 16:36:25.811987 Set Vref, RX VrefLevel [Byte0]: 35
1687 16:36:25.814814 [Byte1]: 35
1688 16:36:25.819081
1689 16:36:25.819182 Set Vref, RX VrefLevel [Byte0]: 36
1690 16:36:25.822257 [Byte1]: 36
1691 16:36:25.826663
1692 16:36:25.826834 Set Vref, RX VrefLevel [Byte0]: 37
1693 16:36:25.830271 [Byte1]: 37
1694 16:36:25.834022
1695 16:36:25.834205 Set Vref, RX VrefLevel [Byte0]: 38
1696 16:36:25.837963 [Byte1]: 38
1697 16:36:25.841668
1698 16:36:25.841793 Set Vref, RX VrefLevel [Byte0]: 39
1699 16:36:25.845318 [Byte1]: 39
1700 16:36:25.849490
1701 16:36:25.849707 Set Vref, RX VrefLevel [Byte0]: 40
1702 16:36:25.852963 [Byte1]: 40
1703 16:36:25.857044
1704 16:36:25.857234 Set Vref, RX VrefLevel [Byte0]: 41
1705 16:36:25.859942 [Byte1]: 41
1706 16:36:25.864415
1707 16:36:25.864608 Set Vref, RX VrefLevel [Byte0]: 42
1708 16:36:25.867508 [Byte1]: 42
1709 16:36:25.872070
1710 16:36:25.872220 Set Vref, RX VrefLevel [Byte0]: 43
1711 16:36:25.875038 [Byte1]: 43
1712 16:36:25.879719
1713 16:36:25.879821 Set Vref, RX VrefLevel [Byte0]: 44
1714 16:36:25.882663 [Byte1]: 44
1715 16:36:25.887394
1716 16:36:25.887958 Set Vref, RX VrefLevel [Byte0]: 45
1717 16:36:25.891014 [Byte1]: 45
1718 16:36:25.894745
1719 16:36:25.895141 Set Vref, RX VrefLevel [Byte0]: 46
1720 16:36:25.898527 [Byte1]: 46
1721 16:36:25.902283
1722 16:36:25.902679 Set Vref, RX VrefLevel [Byte0]: 47
1723 16:36:25.905853 [Byte1]: 47
1724 16:36:25.910192
1725 16:36:25.910598 Set Vref, RX VrefLevel [Byte0]: 48
1726 16:36:25.913215 [Byte1]: 48
1727 16:36:25.917505
1728 16:36:25.917949 Set Vref, RX VrefLevel [Byte0]: 49
1729 16:36:25.921012 [Byte1]: 49
1730 16:36:25.924817
1731 16:36:25.925092 Set Vref, RX VrefLevel [Byte0]: 50
1732 16:36:25.928071 [Byte1]: 50
1733 16:36:25.932652
1734 16:36:25.932826 Set Vref, RX VrefLevel [Byte0]: 51
1735 16:36:25.936095 [Byte1]: 51
1736 16:36:25.939903
1737 16:36:25.940026 Set Vref, RX VrefLevel [Byte0]: 52
1738 16:36:25.942948 [Byte1]: 52
1739 16:36:25.947440
1740 16:36:25.947561 Set Vref, RX VrefLevel [Byte0]: 53
1741 16:36:25.950465 [Byte1]: 53
1742 16:36:25.954945
1743 16:36:25.955065 Set Vref, RX VrefLevel [Byte0]: 54
1744 16:36:25.958712 [Byte1]: 54
1745 16:36:25.962394
1746 16:36:25.962514 Set Vref, RX VrefLevel [Byte0]: 55
1747 16:36:25.966062 [Byte1]: 55
1748 16:36:25.970095
1749 16:36:25.970217 Set Vref, RX VrefLevel [Byte0]: 56
1750 16:36:25.973456 [Byte1]: 56
1751 16:36:25.978006
1752 16:36:25.978172 Set Vref, RX VrefLevel [Byte0]: 57
1753 16:36:25.980926 [Byte1]: 57
1754 16:36:25.985429
1755 16:36:25.985511 Set Vref, RX VrefLevel [Byte0]: 58
1756 16:36:25.988310 [Byte1]: 58
1757 16:36:25.992944
1758 16:36:25.993029 Set Vref, RX VrefLevel [Byte0]: 59
1759 16:36:25.996144 [Byte1]: 59
1760 16:36:26.000587
1761 16:36:26.000666 Set Vref, RX VrefLevel [Byte0]: 60
1762 16:36:26.003669 [Byte1]: 60
1763 16:36:26.008210
1764 16:36:26.008291 Set Vref, RX VrefLevel [Byte0]: 61
1765 16:36:26.011188 [Byte1]: 61
1766 16:36:26.015661
1767 16:36:26.015747 Set Vref, RX VrefLevel [Byte0]: 62
1768 16:36:26.018716 [Byte1]: 62
1769 16:36:26.023165
1770 16:36:26.023254 Set Vref, RX VrefLevel [Byte0]: 63
1771 16:36:26.026214 [Byte1]: 63
1772 16:36:26.030750
1773 16:36:26.030846 Set Vref, RX VrefLevel [Byte0]: 64
1774 16:36:26.033676 [Byte1]: 64
1775 16:36:26.037954
1776 16:36:26.038051 Set Vref, RX VrefLevel [Byte0]: 65
1777 16:36:26.041365 [Byte1]: 65
1778 16:36:26.045510
1779 16:36:26.045678 Set Vref, RX VrefLevel [Byte0]: 66
1780 16:36:26.048919 [Byte1]: 66
1781 16:36:26.053134
1782 16:36:26.053352 Set Vref, RX VrefLevel [Byte0]: 67
1783 16:36:26.056450 [Byte1]: 67
1784 16:36:26.060709
1785 16:36:26.060899 Set Vref, RX VrefLevel [Byte0]: 68
1786 16:36:26.064435 [Byte1]: 68
1787 16:36:26.068261
1788 16:36:26.068408 Set Vref, RX VrefLevel [Byte0]: 69
1789 16:36:26.071264 [Byte1]: 69
1790 16:36:26.075645
1791 16:36:26.075814 Set Vref, RX VrefLevel [Byte0]: 70
1792 16:36:26.079214 [Byte1]: 70
1793 16:36:26.083297
1794 16:36:26.083493 Set Vref, RX VrefLevel [Byte0]: 71
1795 16:36:26.086542 [Byte1]: 71
1796 16:36:26.091263
1797 16:36:26.091567 Final RX Vref Byte 0 = 59 to rank0
1798 16:36:26.094747 Final RX Vref Byte 1 = 53 to rank0
1799 16:36:26.098174 Final RX Vref Byte 0 = 59 to rank1
1800 16:36:26.101140 Final RX Vref Byte 1 = 53 to rank1==
1801 16:36:26.104888 Dram Type= 6, Freq= 0, CH_1, rank 0
1802 16:36:26.110998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 16:36:26.111412 ==
1804 16:36:26.111758 DQS Delay:
1805 16:36:26.112207 DQS0 = 0, DQS1 = 0
1806 16:36:26.114687 DQM Delay:
1807 16:36:26.115237 DQM0 = 95, DQM1 = 90
1808 16:36:26.117828 DQ Delay:
1809 16:36:26.121483 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1810 16:36:26.124475 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1811 16:36:26.128084 DQ8 =80, DQ9 =84, DQ10 =88, DQ11 =84
1812 16:36:26.131031 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1813 16:36:26.131275
1814 16:36:26.131443
1815 16:36:26.137774 [DQSOSCAuto] RK0, (LSB)MR18= 0x324e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1816 16:36:26.140580 CH1 RK0: MR19=606, MR18=324E
1817 16:36:26.147511 CH1_RK0: MR19=0x606, MR18=0x324E, DQSOSC=390, MR23=63, INC=97, DEC=64
1818 16:36:26.147638
1819 16:36:26.151243 ----->DramcWriteLeveling(PI) begin...
1820 16:36:26.151389 ==
1821 16:36:26.154033 Dram Type= 6, Freq= 0, CH_1, rank 1
1822 16:36:26.157880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 16:36:26.157980 ==
1824 16:36:26.160579 Write leveling (Byte 0): 26 => 26
1825 16:36:26.164139 Write leveling (Byte 1): 28 => 28
1826 16:36:26.167584 DramcWriteLeveling(PI) end<-----
1827 16:36:26.167688
1828 16:36:26.167762 ==
1829 16:36:26.171135 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 16:36:26.174010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 16:36:26.174095 ==
1832 16:36:26.177465 [Gating] SW mode calibration
1833 16:36:26.184334 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1834 16:36:26.191042 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1835 16:36:26.194731 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1836 16:36:26.197568 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1837 16:36:26.204483 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 16:36:26.207953 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 16:36:26.211223 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 16:36:26.217801 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 16:36:26.221427 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 16:36:26.224376 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 16:36:26.231115 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 16:36:26.234305 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 16:36:26.238179 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 16:36:26.244450 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 16:36:26.248273 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 16:36:26.251240 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 16:36:26.254342 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 16:36:26.260962 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1851 16:36:26.264935 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1852 16:36:26.268007 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1853 16:36:26.274357 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 16:36:26.277613 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 16:36:26.281236 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 16:36:26.287793 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 16:36:26.291240 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 16:36:26.294958 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 16:36:26.301470 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 16:36:26.304486 0 9 4 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
1861 16:36:26.308259 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1862 16:36:26.315004 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 16:36:26.317940 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 16:36:26.322012 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 16:36:26.324644 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 16:36:26.331596 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 16:36:26.334534 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1868 16:36:26.338168 0 10 4 | B1->B0 | 2727 3131 | 0 1 | (1 0) (1 1)
1869 16:36:26.345085 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 16:36:26.348016 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 16:36:26.351961 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 16:36:26.357891 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 16:36:26.361538 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 16:36:26.365149 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 16:36:26.371340 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1876 16:36:26.375140 0 11 4 | B1->B0 | 3636 3030 | 0 0 | (0 0) (1 1)
1877 16:36:26.378071 0 11 8 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)
1878 16:36:26.385183 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 16:36:26.388018 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 16:36:26.391825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 16:36:26.398439 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 16:36:26.402005 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 16:36:26.404923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1884 16:36:26.408268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1885 16:36:26.414863 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 16:36:26.418690 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 16:36:26.421595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 16:36:26.428382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 16:36:26.431268 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 16:36:26.434794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 16:36:26.441889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 16:36:26.444532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 16:36:26.448219 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 16:36:26.455261 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 16:36:26.458596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 16:36:26.461363 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 16:36:26.468223 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 16:36:26.471861 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 16:36:26.474869 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 16:36:26.481493 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1901 16:36:26.485227 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 16:36:26.488195 Total UI for P1: 0, mck2ui 16
1903 16:36:26.491765 best dqsien dly found for B0: ( 0, 14, 4)
1904 16:36:26.495455 Total UI for P1: 0, mck2ui 16
1905 16:36:26.498264 best dqsien dly found for B1: ( 0, 14, 4)
1906 16:36:26.501825 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1907 16:36:26.504685 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1908 16:36:26.504827
1909 16:36:26.508513 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1910 16:36:26.511540 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1911 16:36:26.514864 [Gating] SW calibration Done
1912 16:36:26.514954 ==
1913 16:36:26.518508 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 16:36:26.521399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 16:36:26.521500 ==
1916 16:36:26.525091 RX Vref Scan: 0
1917 16:36:26.525189
1918 16:36:26.525252 RX Vref 0 -> 0, step: 1
1919 16:36:26.525307
1920 16:36:26.528846 RX Delay -130 -> 252, step: 16
1921 16:36:26.531693 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1922 16:36:26.538545 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1923 16:36:26.541659 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1924 16:36:26.545407 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1925 16:36:26.548399 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1926 16:36:26.552128 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1927 16:36:26.558532 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1928 16:36:26.562172 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1929 16:36:26.565240 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1930 16:36:26.568955 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1931 16:36:26.572075 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1932 16:36:26.578807 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1933 16:36:26.581771 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1934 16:36:26.585398 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1935 16:36:26.589227 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1936 16:36:26.592325 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1937 16:36:26.595637 ==
1938 16:36:26.595937 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 16:36:26.602422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 16:36:26.602989 ==
1941 16:36:26.603548 DQS Delay:
1942 16:36:26.606064 DQS0 = 0, DQS1 = 0
1943 16:36:26.606611 DQM Delay:
1944 16:36:26.608888 DQM0 = 92, DQM1 = 87
1945 16:36:26.609320 DQ Delay:
1946 16:36:26.612556 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1947 16:36:26.615573 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1948 16:36:26.619370 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1949 16:36:26.622317 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1950 16:36:26.622838
1951 16:36:26.623150
1952 16:36:26.623428 ==
1953 16:36:26.625917 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 16:36:26.628875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 16:36:26.629471 ==
1956 16:36:26.629881
1957 16:36:26.630170
1958 16:36:26.632646 TX Vref Scan disable
1959 16:36:26.635642 == TX Byte 0 ==
1960 16:36:26.639460 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1961 16:36:26.642117 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1962 16:36:26.645641 == TX Byte 1 ==
1963 16:36:26.649304 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 16:36:26.651955 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 16:36:26.652264 ==
1966 16:36:26.655482 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 16:36:26.658586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 16:36:26.662158 ==
1969 16:36:26.673105 TX Vref=22, minBit 2, minWin=26, winSum=443
1970 16:36:26.676149 TX Vref=24, minBit 0, minWin=27, winSum=447
1971 16:36:26.679847 TX Vref=26, minBit 0, minWin=27, winSum=446
1972 16:36:26.683401 TX Vref=28, minBit 2, minWin=27, winSum=449
1973 16:36:26.686418 TX Vref=30, minBit 2, minWin=27, winSum=451
1974 16:36:26.689506 TX Vref=32, minBit 2, minWin=27, winSum=450
1975 16:36:26.696462 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1976 16:36:26.696540
1977 16:36:26.700267 Final TX Range 1 Vref 30
1978 16:36:26.700345
1979 16:36:26.700421 ==
1980 16:36:26.703123 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 16:36:26.706935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 16:36:26.707013 ==
1983 16:36:26.707090
1984 16:36:26.707162
1985 16:36:26.709630 TX Vref Scan disable
1986 16:36:26.713273 == TX Byte 0 ==
1987 16:36:26.716876 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1988 16:36:26.719958 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1989 16:36:26.723617 == TX Byte 1 ==
1990 16:36:26.726695 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1991 16:36:26.730306 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1992 16:36:26.730412
1993 16:36:26.733290 [DATLAT]
1994 16:36:26.733442 Freq=800, CH1 RK1
1995 16:36:26.733582
1996 16:36:26.737401 DATLAT Default: 0xa
1997 16:36:26.737884 0, 0xFFFF, sum = 0
1998 16:36:26.740158 1, 0xFFFF, sum = 0
1999 16:36:26.740554 2, 0xFFFF, sum = 0
2000 16:36:26.743957 3, 0xFFFF, sum = 0
2001 16:36:26.744397 4, 0xFFFF, sum = 0
2002 16:36:26.747060 5, 0xFFFF, sum = 0
2003 16:36:26.747465 6, 0xFFFF, sum = 0
2004 16:36:26.750734 7, 0xFFFF, sum = 0
2005 16:36:26.751129 8, 0xFFFF, sum = 0
2006 16:36:26.753716 9, 0x0, sum = 1
2007 16:36:26.754113 10, 0x0, sum = 2
2008 16:36:26.757173 11, 0x0, sum = 3
2009 16:36:26.757751 12, 0x0, sum = 4
2010 16:36:26.760719 best_step = 10
2011 16:36:26.761133
2012 16:36:26.761643 ==
2013 16:36:26.763568 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 16:36:26.767238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 16:36:26.767686 ==
2016 16:36:26.770722 RX Vref Scan: 0
2017 16:36:26.771248
2018 16:36:26.771561 RX Vref 0 -> 0, step: 1
2019 16:36:26.771862
2020 16:36:26.773418 RX Delay -79 -> 252, step: 8
2021 16:36:26.780646 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2022 16:36:26.783526 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2023 16:36:26.787353 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2024 16:36:26.790256 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2025 16:36:26.794054 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2026 16:36:26.797023 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2027 16:36:26.803745 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2028 16:36:26.806828 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2029 16:36:26.810440 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2030 16:36:26.813427 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2031 16:36:26.817058 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2032 16:36:26.820702 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
2033 16:36:26.827006 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2034 16:36:26.830730 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2035 16:36:26.833677 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2036 16:36:26.836740 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2037 16:36:26.837299 ==
2038 16:36:26.840381 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 16:36:26.847040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 16:36:26.847329 ==
2041 16:36:26.847616 DQS Delay:
2042 16:36:26.849958 DQS0 = 0, DQS1 = 0
2043 16:36:26.850191 DQM Delay:
2044 16:36:26.850392 DQM0 = 97, DQM1 = 90
2045 16:36:26.853592 DQ Delay:
2046 16:36:26.856521 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2047 16:36:26.860203 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2048 16:36:26.863136 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =80
2049 16:36:26.866696 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2050 16:36:26.866840
2051 16:36:26.866964
2052 16:36:26.872979 [DQSOSCAuto] RK1, (LSB)MR18= 0x450d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2053 16:36:26.876254 CH1 RK1: MR19=606, MR18=450D
2054 16:36:26.883132 CH1_RK1: MR19=0x606, MR18=0x450D, DQSOSC=392, MR23=63, INC=96, DEC=64
2055 16:36:26.886956 [RxdqsGatingPostProcess] freq 800
2056 16:36:26.890306 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2057 16:36:26.893213 Pre-setting of DQS Precalculation
2058 16:36:26.899945 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2059 16:36:26.906810 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2060 16:36:26.913438 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2061 16:36:26.913537
2062 16:36:26.913621
2063 16:36:26.916341 [Calibration Summary] 1600 Mbps
2064 16:36:26.916437 CH 0, Rank 0
2065 16:36:26.920435 SW Impedance : PASS
2066 16:36:26.923552 DUTY Scan : NO K
2067 16:36:26.923986 ZQ Calibration : PASS
2068 16:36:26.927245 Jitter Meter : NO K
2069 16:36:26.930056 CBT Training : PASS
2070 16:36:26.930449 Write leveling : PASS
2071 16:36:26.933836 RX DQS gating : PASS
2072 16:36:26.937112 RX DQ/DQS(RDDQC) : PASS
2073 16:36:26.937500 TX DQ/DQS : PASS
2074 16:36:26.940203 RX DATLAT : PASS
2075 16:36:26.944002 RX DQ/DQS(Engine): PASS
2076 16:36:26.944396 TX OE : NO K
2077 16:36:26.944833 All Pass.
2078 16:36:26.946948
2079 16:36:26.947431 CH 0, Rank 1
2080 16:36:26.950736 SW Impedance : PASS
2081 16:36:26.951127 DUTY Scan : NO K
2082 16:36:26.953642 ZQ Calibration : PASS
2083 16:36:26.954038 Jitter Meter : NO K
2084 16:36:26.957101 CBT Training : PASS
2085 16:36:26.960078 Write leveling : PASS
2086 16:36:26.960658 RX DQS gating : PASS
2087 16:36:26.963593 RX DQ/DQS(RDDQC) : PASS
2088 16:36:26.967300 TX DQ/DQS : PASS
2089 16:36:26.967757 RX DATLAT : PASS
2090 16:36:26.970375 RX DQ/DQS(Engine): PASS
2091 16:36:26.973314 TX OE : NO K
2092 16:36:26.973966 All Pass.
2093 16:36:26.974451
2094 16:36:26.974969 CH 1, Rank 0
2095 16:36:26.977087 SW Impedance : PASS
2096 16:36:26.979997 DUTY Scan : NO K
2097 16:36:26.980638 ZQ Calibration : PASS
2098 16:36:26.983633 Jitter Meter : NO K
2099 16:36:26.987037 CBT Training : PASS
2100 16:36:26.987483 Write leveling : PASS
2101 16:36:26.990457 RX DQS gating : PASS
2102 16:36:26.990785 RX DQ/DQS(RDDQC) : PASS
2103 16:36:26.993121 TX DQ/DQS : PASS
2104 16:36:26.996834 RX DATLAT : PASS
2105 16:36:26.997007 RX DQ/DQS(Engine): PASS
2106 16:36:27.000228 TX OE : NO K
2107 16:36:27.000384 All Pass.
2108 16:36:27.000524
2109 16:36:27.003689 CH 1, Rank 1
2110 16:36:27.003830 SW Impedance : PASS
2111 16:36:27.006646 DUTY Scan : NO K
2112 16:36:27.010349 ZQ Calibration : PASS
2113 16:36:27.010473 Jitter Meter : NO K
2114 16:36:27.013390 CBT Training : PASS
2115 16:36:27.017000 Write leveling : PASS
2116 16:36:27.017120 RX DQS gating : PASS
2117 16:36:27.019886 RX DQ/DQS(RDDQC) : PASS
2118 16:36:27.023593 TX DQ/DQS : PASS
2119 16:36:27.023715 RX DATLAT : PASS
2120 16:36:27.027285 RX DQ/DQS(Engine): PASS
2121 16:36:27.027406 TX OE : NO K
2122 16:36:27.030142 All Pass.
2123 16:36:27.030261
2124 16:36:27.030355 DramC Write-DBI off
2125 16:36:27.033808 PER_BANK_REFRESH: Hybrid Mode
2126 16:36:27.036734 TX_TRACKING: ON
2127 16:36:27.040393 [GetDramInforAfterCalByMRR] Vendor 6.
2128 16:36:27.043878 [GetDramInforAfterCalByMRR] Revision 606.
2129 16:36:27.046711 [GetDramInforAfterCalByMRR] Revision 2 0.
2130 16:36:27.046863 MR0 0x3b3b
2131 16:36:27.046983 MR8 0x5151
2132 16:36:27.053268 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 16:36:27.053445
2134 16:36:27.053613 MR0 0x3b3b
2135 16:36:27.053747 MR8 0x5151
2136 16:36:27.057180 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 16:36:27.057439
2138 16:36:27.067561 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2139 16:36:27.070612 [FAST_K] Save calibration result to emmc
2140 16:36:27.074397 [FAST_K] Save calibration result to emmc
2141 16:36:27.077271 dram_init: config_dvfs: 1
2142 16:36:27.081049 dramc_set_vcore_voltage set vcore to 662500
2143 16:36:27.083937 Read voltage for 1200, 2
2144 16:36:27.084331 Vio18 = 0
2145 16:36:27.084637 Vcore = 662500
2146 16:36:27.087732 Vdram = 0
2147 16:36:27.088123 Vddq = 0
2148 16:36:27.088432 Vmddr = 0
2149 16:36:27.094380 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2150 16:36:27.097456 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2151 16:36:27.100797 MEM_TYPE=3, freq_sel=15
2152 16:36:27.104202 sv_algorithm_assistance_LP4_1600
2153 16:36:27.107006 ============ PULL DRAM RESETB DOWN ============
2154 16:36:27.110355 ========== PULL DRAM RESETB DOWN end =========
2155 16:36:27.117245 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2156 16:36:27.120483 ===================================
2157 16:36:27.120626 LPDDR4 DRAM CONFIGURATION
2158 16:36:27.124065 ===================================
2159 16:36:27.127265 EX_ROW_EN[0] = 0x0
2160 16:36:27.130427 EX_ROW_EN[1] = 0x0
2161 16:36:27.130569 LP4Y_EN = 0x0
2162 16:36:27.134218 WORK_FSP = 0x0
2163 16:36:27.134367 WL = 0x4
2164 16:36:27.137126 RL = 0x4
2165 16:36:27.137281 BL = 0x2
2166 16:36:27.140614 RPST = 0x0
2167 16:36:27.140758 RD_PRE = 0x0
2168 16:36:27.143912 WR_PRE = 0x1
2169 16:36:27.144053 WR_PST = 0x0
2170 16:36:27.147598 DBI_WR = 0x0
2171 16:36:27.147739 DBI_RD = 0x0
2172 16:36:27.151010 OTF = 0x1
2173 16:36:27.154076 ===================================
2174 16:36:27.157776 ===================================
2175 16:36:27.158187 ANA top config
2176 16:36:27.161291 ===================================
2177 16:36:27.164277 DLL_ASYNC_EN = 0
2178 16:36:27.167926 ALL_SLAVE_EN = 0
2179 16:36:27.168422 NEW_RANK_MODE = 1
2180 16:36:27.170898 DLL_IDLE_MODE = 1
2181 16:36:27.174636 LP45_APHY_COMB_EN = 1
2182 16:36:27.177364 TX_ODT_DIS = 1
2183 16:36:27.180894 NEW_8X_MODE = 1
2184 16:36:27.184099 ===================================
2185 16:36:27.187941 ===================================
2186 16:36:27.188496 data_rate = 2400
2187 16:36:27.191021 CKR = 1
2188 16:36:27.194557 DQ_P2S_RATIO = 8
2189 16:36:27.197447 ===================================
2190 16:36:27.201006 CA_P2S_RATIO = 8
2191 16:36:27.204369 DQ_CA_OPEN = 0
2192 16:36:27.207263 DQ_SEMI_OPEN = 0
2193 16:36:27.207499 CA_SEMI_OPEN = 0
2194 16:36:27.210743 CA_FULL_RATE = 0
2195 16:36:27.214490 DQ_CKDIV4_EN = 0
2196 16:36:27.217366 CA_CKDIV4_EN = 0
2197 16:36:27.220986 CA_PREDIV_EN = 0
2198 16:36:27.224457 PH8_DLY = 17
2199 16:36:27.224605 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2200 16:36:27.227163 DQ_AAMCK_DIV = 4
2201 16:36:27.230541 CA_AAMCK_DIV = 4
2202 16:36:27.234064 CA_ADMCK_DIV = 4
2203 16:36:27.237202 DQ_TRACK_CA_EN = 0
2204 16:36:27.241002 CA_PICK = 1200
2205 16:36:27.241123 CA_MCKIO = 1200
2206 16:36:27.243879 MCKIO_SEMI = 0
2207 16:36:27.247751 PLL_FREQ = 2366
2208 16:36:27.250768 DQ_UI_PI_RATIO = 32
2209 16:36:27.254653 CA_UI_PI_RATIO = 0
2210 16:36:27.257754 ===================================
2211 16:36:27.260833 ===================================
2212 16:36:27.264585 memory_type:LPDDR4
2213 16:36:27.264791 GP_NUM : 10
2214 16:36:27.267580 SRAM_EN : 1
2215 16:36:27.267814 MD32_EN : 0
2216 16:36:27.271888 ===================================
2217 16:36:27.274868 [ANA_INIT] >>>>>>>>>>>>>>
2218 16:36:27.277818 <<<<<< [CONFIGURE PHASE]: ANA_TX
2219 16:36:27.281596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2220 16:36:27.284895 ===================================
2221 16:36:27.288301 data_rate = 2400,PCW = 0X5b00
2222 16:36:27.291141 ===================================
2223 16:36:27.294926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2224 16:36:27.297893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 16:36:27.304808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2226 16:36:27.307708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2227 16:36:27.311411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2228 16:36:27.314428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2229 16:36:27.318000 [ANA_INIT] flow start
2230 16:36:27.321603 [ANA_INIT] PLL >>>>>>>>
2231 16:36:27.321880 [ANA_INIT] PLL <<<<<<<<
2232 16:36:27.324523 [ANA_INIT] MIDPI >>>>>>>>
2233 16:36:27.327604 [ANA_INIT] MIDPI <<<<<<<<
2234 16:36:27.331237 [ANA_INIT] DLL >>>>>>>>
2235 16:36:27.331723 [ANA_INIT] DLL <<<<<<<<
2236 16:36:27.334272 [ANA_INIT] flow end
2237 16:36:27.337841 ============ LP4 DIFF to SE enter ============
2238 16:36:27.341419 ============ LP4 DIFF to SE exit ============
2239 16:36:27.344773 [ANA_INIT] <<<<<<<<<<<<<
2240 16:36:27.347627 [Flow] Enable top DCM control >>>>>
2241 16:36:27.350898 [Flow] Enable top DCM control <<<<<
2242 16:36:27.354469 Enable DLL master slave shuffle
2243 16:36:27.361144 ==============================================================
2244 16:36:27.361529 Gating Mode config
2245 16:36:27.367890 ==============================================================
2246 16:36:27.368180 Config description:
2247 16:36:27.378303 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2248 16:36:27.384463 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2249 16:36:27.391286 SELPH_MODE 0: By rank 1: By Phase
2250 16:36:27.394803 ==============================================================
2251 16:36:27.398809 GAT_TRACK_EN = 1
2252 16:36:27.401596 RX_GATING_MODE = 2
2253 16:36:27.404798 RX_GATING_TRACK_MODE = 2
2254 16:36:27.408294 SELPH_MODE = 1
2255 16:36:27.411302 PICG_EARLY_EN = 1
2256 16:36:27.415012 VALID_LAT_VALUE = 1
2257 16:36:27.417967 ==============================================================
2258 16:36:27.421677 Enter into Gating configuration >>>>
2259 16:36:27.424448 Exit from Gating configuration <<<<
2260 16:36:27.427922 Enter into DVFS_PRE_config >>>>>
2261 16:36:27.438401 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2262 16:36:27.441361 Exit from DVFS_PRE_config <<<<<
2263 16:36:27.445075 Enter into PICG configuration >>>>
2264 16:36:27.447976 Exit from PICG configuration <<<<
2265 16:36:27.451728 [RX_INPUT] configuration >>>>>
2266 16:36:27.454455 [RX_INPUT] configuration <<<<<
2267 16:36:27.461253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2268 16:36:27.464965 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2269 16:36:27.471213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2270 16:36:27.477863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2271 16:36:27.484883 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2272 16:36:27.491680 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2273 16:36:27.494718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2274 16:36:27.498355 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2275 16:36:27.501447 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2276 16:36:27.508073 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2277 16:36:27.511767 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2278 16:36:27.514796 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 16:36:27.517787 ===================================
2280 16:36:27.521477 LPDDR4 DRAM CONFIGURATION
2281 16:36:27.524552 ===================================
2282 16:36:27.524715 EX_ROW_EN[0] = 0x0
2283 16:36:27.528444 EX_ROW_EN[1] = 0x0
2284 16:36:27.528630 LP4Y_EN = 0x0
2285 16:36:27.531665 WORK_FSP = 0x0
2286 16:36:27.531959 WL = 0x4
2287 16:36:27.535024 RL = 0x4
2288 16:36:27.535254 BL = 0x2
2289 16:36:27.538524 RPST = 0x0
2290 16:36:27.538860 RD_PRE = 0x0
2291 16:36:27.542065 WR_PRE = 0x1
2292 16:36:27.544915 WR_PST = 0x0
2293 16:36:27.545279 DBI_WR = 0x0
2294 16:36:27.548773 DBI_RD = 0x0
2295 16:36:27.549211 OTF = 0x1
2296 16:36:27.551803 ===================================
2297 16:36:27.554719 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2298 16:36:27.558502 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2299 16:36:27.565384 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 16:36:27.568343 ===================================
2301 16:36:27.568896 LPDDR4 DRAM CONFIGURATION
2302 16:36:27.571907 ===================================
2303 16:36:27.575612 EX_ROW_EN[0] = 0x10
2304 16:36:27.578434 EX_ROW_EN[1] = 0x0
2305 16:36:27.578871 LP4Y_EN = 0x0
2306 16:36:27.581903 WORK_FSP = 0x0
2307 16:36:27.582275 WL = 0x4
2308 16:36:27.585330 RL = 0x4
2309 16:36:27.585667 BL = 0x2
2310 16:36:27.588425 RPST = 0x0
2311 16:36:27.588633 RD_PRE = 0x0
2312 16:36:27.591792 WR_PRE = 0x1
2313 16:36:27.591999 WR_PST = 0x0
2314 16:36:27.595203 DBI_WR = 0x0
2315 16:36:27.595412 DBI_RD = 0x0
2316 16:36:27.598078 OTF = 0x1
2317 16:36:27.601604 ===================================
2318 16:36:27.608241 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2319 16:36:27.608450 ==
2320 16:36:27.611794 Dram Type= 6, Freq= 0, CH_0, rank 0
2321 16:36:27.614866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2322 16:36:27.615077 ==
2323 16:36:27.618643 [Duty_Offset_Calibration]
2324 16:36:27.618852 B0:2 B1:1 CA:1
2325 16:36:27.619016
2326 16:36:27.621488 [DutyScan_Calibration_Flow] k_type=0
2327 16:36:27.631833
2328 16:36:27.632089 ==CLK 0==
2329 16:36:27.635663 Final CLK duty delay cell = 0
2330 16:36:27.638695 [0] MAX Duty = 5187%(X100), DQS PI = 24
2331 16:36:27.642558 [0] MIN Duty = 4844%(X100), DQS PI = 48
2332 16:36:27.642883 [0] AVG Duty = 5015%(X100)
2333 16:36:27.645487
2334 16:36:27.649116 CH0 CLK Duty spec in!! Max-Min= 343%
2335 16:36:27.651967 [DutyScan_Calibration_Flow] ====Done====
2336 16:36:27.652358
2337 16:36:27.655426 [DutyScan_Calibration_Flow] k_type=1
2338 16:36:27.670949
2339 16:36:27.671455 ==DQS 0 ==
2340 16:36:27.674104 Final DQS duty delay cell = -4
2341 16:36:27.677735 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2342 16:36:27.680734 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2343 16:36:27.684336 [-4] AVG Duty = 4937%(X100)
2344 16:36:27.684772
2345 16:36:27.685076 ==DQS 1 ==
2346 16:36:27.687348 Final DQS duty delay cell = 0
2347 16:36:27.691040 [0] MAX Duty = 5156%(X100), DQS PI = 62
2348 16:36:27.694044 [0] MIN Duty = 5000%(X100), DQS PI = 32
2349 16:36:27.697805 [0] AVG Duty = 5078%(X100)
2350 16:36:27.698142
2351 16:36:27.700656 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2352 16:36:27.700870
2353 16:36:27.703709 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2354 16:36:27.707332 [DutyScan_Calibration_Flow] ====Done====
2355 16:36:27.707594
2356 16:36:27.710367 [DutyScan_Calibration_Flow] k_type=3
2357 16:36:27.727372
2358 16:36:27.727589 ==DQM 0 ==
2359 16:36:27.731235 Final DQM duty delay cell = 0
2360 16:36:27.734251 [0] MAX Duty = 5156%(X100), DQS PI = 32
2361 16:36:27.737282 [0] MIN Duty = 4906%(X100), DQS PI = 50
2362 16:36:27.741346 [0] AVG Duty = 5031%(X100)
2363 16:36:27.741719
2364 16:36:27.741964 ==DQM 1 ==
2365 16:36:27.744181 Final DQM duty delay cell = 0
2366 16:36:27.747127 [0] MAX Duty = 5093%(X100), DQS PI = 0
2367 16:36:27.750873 [0] MIN Duty = 5031%(X100), DQS PI = 14
2368 16:36:27.751130 [0] AVG Duty = 5062%(X100)
2369 16:36:27.753852
2370 16:36:27.757353 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2371 16:36:27.757947
2372 16:36:27.761282 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2373 16:36:27.764054 [DutyScan_Calibration_Flow] ====Done====
2374 16:36:27.764380
2375 16:36:27.767211 [DutyScan_Calibration_Flow] k_type=2
2376 16:36:27.784390
2377 16:36:27.784640 ==DQ 0 ==
2378 16:36:27.787714 Final DQ duty delay cell = 0
2379 16:36:27.790548 [0] MAX Duty = 5031%(X100), DQS PI = 26
2380 16:36:27.794449 [0] MIN Duty = 4844%(X100), DQS PI = 62
2381 16:36:27.794784 [0] AVG Duty = 4937%(X100)
2382 16:36:27.797369
2383 16:36:27.797651 ==DQ 1 ==
2384 16:36:27.800339 Final DQ duty delay cell = 0
2385 16:36:27.803974 [0] MAX Duty = 5093%(X100), DQS PI = 24
2386 16:36:27.807010 [0] MIN Duty = 4907%(X100), DQS PI = 36
2387 16:36:27.807264 [0] AVG Duty = 5000%(X100)
2388 16:36:27.807452
2389 16:36:27.810757 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2390 16:36:27.813839
2391 16:36:27.817263 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2392 16:36:27.820814 [DutyScan_Calibration_Flow] ====Done====
2393 16:36:27.821073 ==
2394 16:36:27.823828 Dram Type= 6, Freq= 0, CH_1, rank 0
2395 16:36:27.827412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2396 16:36:27.827649 ==
2397 16:36:27.830694 [Duty_Offset_Calibration]
2398 16:36:27.830957 B0:1 B1:0 CA:0
2399 16:36:27.831141
2400 16:36:27.833820 [DutyScan_Calibration_Flow] k_type=0
2401 16:36:27.842960
2402 16:36:27.843042 ==CLK 0==
2403 16:36:27.846420 Final CLK duty delay cell = -4
2404 16:36:27.849453 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2405 16:36:27.853188 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2406 16:36:27.856231 [-4] AVG Duty = 4953%(X100)
2407 16:36:27.856307
2408 16:36:27.859410 CH1 CLK Duty spec in!! Max-Min= 93%
2409 16:36:27.863134 [DutyScan_Calibration_Flow] ====Done====
2410 16:36:27.863216
2411 16:36:27.866268 [DutyScan_Calibration_Flow] k_type=1
2412 16:36:27.882984
2413 16:36:27.883147 ==DQS 0 ==
2414 16:36:27.886007 Final DQS duty delay cell = 0
2415 16:36:27.889805 [0] MAX Duty = 5062%(X100), DQS PI = 22
2416 16:36:27.892809 [0] MIN Duty = 4844%(X100), DQS PI = 0
2417 16:36:27.892948 [0] AVG Duty = 4953%(X100)
2418 16:36:27.895879
2419 16:36:27.896080 ==DQS 1 ==
2420 16:36:27.899442 Final DQS duty delay cell = 0
2421 16:36:27.903002 [0] MAX Duty = 5187%(X100), DQS PI = 18
2422 16:36:27.906137 [0] MIN Duty = 4938%(X100), DQS PI = 58
2423 16:36:27.906357 [0] AVG Duty = 5062%(X100)
2424 16:36:27.909979
2425 16:36:27.913018 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2426 16:36:27.913291
2427 16:36:27.916855 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2428 16:36:27.919890 [DutyScan_Calibration_Flow] ====Done====
2429 16:36:27.920243
2430 16:36:27.922875 [DutyScan_Calibration_Flow] k_type=3
2431 16:36:27.940008
2432 16:36:27.940540 ==DQM 0 ==
2433 16:36:27.943093 Final DQM duty delay cell = 0
2434 16:36:27.946724 [0] MAX Duty = 5156%(X100), DQS PI = 8
2435 16:36:27.950024 [0] MIN Duty = 4969%(X100), DQS PI = 62
2436 16:36:27.950409 [0] AVG Duty = 5062%(X100)
2437 16:36:27.953293
2438 16:36:27.953719 ==DQM 1 ==
2439 16:36:27.956599 Final DQM duty delay cell = 0
2440 16:36:27.959726 [0] MAX Duty = 5031%(X100), DQS PI = 24
2441 16:36:27.963069 [0] MIN Duty = 4875%(X100), DQS PI = 36
2442 16:36:27.963702 [0] AVG Duty = 4953%(X100)
2443 16:36:27.966771
2444 16:36:27.969782 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2445 16:36:27.970249
2446 16:36:27.972682 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2447 16:36:27.976400 [DutyScan_Calibration_Flow] ====Done====
2448 16:36:27.976802
2449 16:36:27.979593 [DutyScan_Calibration_Flow] k_type=2
2450 16:36:27.995492
2451 16:36:27.996102 ==DQ 0 ==
2452 16:36:27.999109 Final DQ duty delay cell = -4
2453 16:36:28.001957 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2454 16:36:28.005316 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2455 16:36:28.009032 [-4] AVG Duty = 4984%(X100)
2456 16:36:28.009459
2457 16:36:28.009993 ==DQ 1 ==
2458 16:36:28.012161 Final DQ duty delay cell = 0
2459 16:36:28.015761 [0] MAX Duty = 5125%(X100), DQS PI = 20
2460 16:36:28.018690 [0] MIN Duty = 4969%(X100), DQS PI = 32
2461 16:36:28.019495 [0] AVG Duty = 5047%(X100)
2462 16:36:28.022263
2463 16:36:28.025362 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2464 16:36:28.025683
2465 16:36:28.028813 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2466 16:36:28.031701 [DutyScan_Calibration_Flow] ====Done====
2467 16:36:28.035540 nWR fixed to 30
2468 16:36:28.035727 [ModeRegInit_LP4] CH0 RK0
2469 16:36:28.038642 [ModeRegInit_LP4] CH0 RK1
2470 16:36:28.041755 [ModeRegInit_LP4] CH1 RK0
2471 16:36:28.045450 [ModeRegInit_LP4] CH1 RK1
2472 16:36:28.045662 match AC timing 7
2473 16:36:28.048874 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2474 16:36:28.054930 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2475 16:36:28.058895 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2476 16:36:28.061863 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2477 16:36:28.068428 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2478 16:36:28.068607 ==
2479 16:36:28.071895 Dram Type= 6, Freq= 0, CH_0, rank 0
2480 16:36:28.075188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 16:36:28.075405 ==
2482 16:36:28.081565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 16:36:28.088571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 16:36:28.095774 [CA 0] Center 39 (8~70) winsize 63
2485 16:36:28.099071 [CA 1] Center 39 (8~70) winsize 63
2486 16:36:28.102538 [CA 2] Center 35 (5~66) winsize 62
2487 16:36:28.105447 [CA 3] Center 34 (4~65) winsize 62
2488 16:36:28.109135 [CA 4] Center 33 (3~64) winsize 62
2489 16:36:28.112080 [CA 5] Center 32 (3~62) winsize 60
2490 16:36:28.112469
2491 16:36:28.115746 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2492 16:36:28.116085
2493 16:36:28.119235 [CATrainingPosCal] consider 1 rank data
2494 16:36:28.122842 u2DelayCellTimex100 = 270/100 ps
2495 16:36:28.125490 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2496 16:36:28.129269 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2497 16:36:28.135948 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2498 16:36:28.138926 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2499 16:36:28.142874 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2500 16:36:28.145876 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2501 16:36:28.146655
2502 16:36:28.149092 CA PerBit enable=1, Macro0, CA PI delay=32
2503 16:36:28.149729
2504 16:36:28.152896 [CBTSetCACLKResult] CA Dly = 32
2505 16:36:28.153433 CS Dly: 6 (0~37)
2506 16:36:28.153954 ==
2507 16:36:28.155823 Dram Type= 6, Freq= 0, CH_0, rank 1
2508 16:36:28.162387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 16:36:28.162700 ==
2510 16:36:28.165409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 16:36:28.172120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2512 16:36:28.181289 [CA 0] Center 38 (8~69) winsize 62
2513 16:36:28.184209 [CA 1] Center 38 (8~69) winsize 62
2514 16:36:28.187759 [CA 2] Center 35 (4~66) winsize 63
2515 16:36:28.191398 [CA 3] Center 34 (4~65) winsize 62
2516 16:36:28.194244 [CA 4] Center 33 (3~63) winsize 61
2517 16:36:28.197748 [CA 5] Center 32 (3~62) winsize 60
2518 16:36:28.197919
2519 16:36:28.201271 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2520 16:36:28.201442
2521 16:36:28.204654 [CATrainingPosCal] consider 2 rank data
2522 16:36:28.208205 u2DelayCellTimex100 = 270/100 ps
2523 16:36:28.211225 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2524 16:36:28.214700 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2525 16:36:28.221202 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2526 16:36:28.224701 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2527 16:36:28.228442 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2528 16:36:28.231330 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2529 16:36:28.231818
2530 16:36:28.234807 CA PerBit enable=1, Macro0, CA PI delay=32
2531 16:36:28.235248
2532 16:36:28.238114 [CBTSetCACLKResult] CA Dly = 32
2533 16:36:28.238635 CS Dly: 6 (0~38)
2534 16:36:28.238981
2535 16:36:28.241812 ----->DramcWriteLeveling(PI) begin...
2536 16:36:28.244845 ==
2537 16:36:28.245277 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 16:36:28.251627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 16:36:28.252026 ==
2540 16:36:28.254824 Write leveling (Byte 0): 32 => 32
2541 16:36:28.258442 Write leveling (Byte 1): 28 => 28
2542 16:36:28.258839 DramcWriteLeveling(PI) end<-----
2543 16:36:28.262102
2544 16:36:28.262552 ==
2545 16:36:28.264997 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 16:36:28.267951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 16:36:28.268346 ==
2548 16:36:28.271798 [Gating] SW mode calibration
2549 16:36:28.278511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2550 16:36:28.281382 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2551 16:36:28.288115 0 15 0 | B1->B0 | 2322 3131 | 1 1 | (0 0) (1 1)
2552 16:36:28.291758 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2553 16:36:28.294726 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 16:36:28.301445 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 16:36:28.305056 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 16:36:28.307945 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 16:36:28.314919 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2558 16:36:28.318492 0 15 28 | B1->B0 | 3333 2525 | 0 0 | (0 0) (0 0)
2559 16:36:28.321538 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2560 16:36:28.328356 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 16:36:28.331903 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 16:36:28.335426 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 16:36:28.338090 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 16:36:28.345174 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 16:36:28.348397 1 0 24 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
2566 16:36:28.351397 1 0 28 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
2567 16:36:28.358250 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2568 16:36:28.361590 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 16:36:28.365093 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 16:36:28.372018 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 16:36:28.375089 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 16:36:28.378052 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 16:36:28.384855 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 16:36:28.388568 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2575 16:36:28.391617 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2576 16:36:28.398487 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 16:36:28.402120 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 16:36:28.405024 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 16:36:28.411689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 16:36:28.415605 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 16:36:28.418325 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 16:36:28.424890 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 16:36:28.428403 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 16:36:28.431737 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 16:36:28.435189 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 16:36:28.441870 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 16:36:28.444798 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 16:36:28.448604 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 16:36:28.454850 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 16:36:28.458522 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2591 16:36:28.461410 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2592 16:36:28.464990 Total UI for P1: 0, mck2ui 16
2593 16:36:28.468396 best dqsien dly found for B0: ( 1, 3, 28)
2594 16:36:28.474910 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 16:36:28.475150 Total UI for P1: 0, mck2ui 16
2596 16:36:28.481516 best dqsien dly found for B1: ( 1, 4, 0)
2597 16:36:28.485441 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2598 16:36:28.488451 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2599 16:36:28.488839
2600 16:36:28.491937 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2601 16:36:28.495565 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2602 16:36:28.498679 [Gating] SW calibration Done
2603 16:36:28.499076 ==
2604 16:36:28.502307 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 16:36:28.505214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 16:36:28.505730 ==
2607 16:36:28.508800 RX Vref Scan: 0
2608 16:36:28.509341
2609 16:36:28.509770 RX Vref 0 -> 0, step: 1
2610 16:36:28.510067
2611 16:36:28.511683 RX Delay -40 -> 252, step: 8
2612 16:36:28.515623 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2613 16:36:28.521477 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2614 16:36:28.525136 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2615 16:36:28.528832 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2616 16:36:28.531689 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2617 16:36:28.535351 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2618 16:36:28.538132 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2619 16:36:28.545077 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2620 16:36:28.548594 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2621 16:36:28.551578 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2622 16:36:28.555416 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2623 16:36:28.558560 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2624 16:36:28.565361 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2625 16:36:28.568484 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2626 16:36:28.572240 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2627 16:36:28.575267 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2628 16:36:28.575402 ==
2629 16:36:28.578906 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 16:36:28.582433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 16:36:28.585296 ==
2632 16:36:28.585429 DQS Delay:
2633 16:36:28.585533 DQS0 = 0, DQS1 = 0
2634 16:36:28.589087 DQM Delay:
2635 16:36:28.589350 DQM0 = 121, DQM1 = 113
2636 16:36:28.592202 DQ Delay:
2637 16:36:28.596129 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2638 16:36:28.598765 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2639 16:36:28.601944 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2640 16:36:28.605370 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2641 16:36:28.605685
2642 16:36:28.605887
2643 16:36:28.606071 ==
2644 16:36:28.609254 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 16:36:28.612630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 16:36:28.613021 ==
2647 16:36:28.613321
2648 16:36:28.613637
2649 16:36:28.615610 TX Vref Scan disable
2650 16:36:28.619196 == TX Byte 0 ==
2651 16:36:28.622783 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2652 16:36:28.625760 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2653 16:36:28.629479 == TX Byte 1 ==
2654 16:36:28.632669 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2655 16:36:28.635572 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2656 16:36:28.636064 ==
2657 16:36:28.639309 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 16:36:28.642424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 16:36:28.646013 ==
2660 16:36:28.656747 TX Vref=22, minBit 0, minWin=25, winSum=408
2661 16:36:28.659477 TX Vref=24, minBit 0, minWin=25, winSum=417
2662 16:36:28.663321 TX Vref=26, minBit 12, minWin=25, winSum=421
2663 16:36:28.666260 TX Vref=28, minBit 10, minWin=25, winSum=422
2664 16:36:28.670052 TX Vref=30, minBit 3, minWin=26, winSum=428
2665 16:36:28.673172 TX Vref=32, minBit 0, minWin=26, winSum=423
2666 16:36:28.680100 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 30
2667 16:36:28.680532
2668 16:36:28.683199 Final TX Range 1 Vref 30
2669 16:36:28.683607
2670 16:36:28.684014 ==
2671 16:36:28.686714 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 16:36:28.689634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 16:36:28.690026 ==
2674 16:36:28.690331
2675 16:36:28.690609
2676 16:36:28.693419 TX Vref Scan disable
2677 16:36:28.696613 == TX Byte 0 ==
2678 16:36:28.699676 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2679 16:36:28.703372 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2680 16:36:28.706385 == TX Byte 1 ==
2681 16:36:28.709893 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2682 16:36:28.712734 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2683 16:36:28.712945
2684 16:36:28.716438 [DATLAT]
2685 16:36:28.716648 Freq=1200, CH0 RK0
2686 16:36:28.716815
2687 16:36:28.719651 DATLAT Default: 0xd
2688 16:36:28.719861 0, 0xFFFF, sum = 0
2689 16:36:28.723272 1, 0xFFFF, sum = 0
2690 16:36:28.723487 2, 0xFFFF, sum = 0
2691 16:36:28.726300 3, 0xFFFF, sum = 0
2692 16:36:28.726509 4, 0xFFFF, sum = 0
2693 16:36:28.730036 5, 0xFFFF, sum = 0
2694 16:36:28.730257 6, 0xFFFF, sum = 0
2695 16:36:28.733280 7, 0xFFFF, sum = 0
2696 16:36:28.733506 8, 0xFFFF, sum = 0
2697 16:36:28.736645 9, 0xFFFF, sum = 0
2698 16:36:28.736858 10, 0xFFFF, sum = 0
2699 16:36:28.739806 11, 0xFFFF, sum = 0
2700 16:36:28.739883 12, 0x0, sum = 1
2701 16:36:28.743460 13, 0x0, sum = 2
2702 16:36:28.743860 14, 0x0, sum = 3
2703 16:36:28.746629 15, 0x0, sum = 4
2704 16:36:28.747027 best_step = 13
2705 16:36:28.747331
2706 16:36:28.747610 ==
2707 16:36:28.749819 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 16:36:28.757086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 16:36:28.757631 ==
2710 16:36:28.757961 RX Vref Scan: 1
2711 16:36:28.758318
2712 16:36:28.760070 Set Vref Range= 32 -> 127
2713 16:36:28.760463
2714 16:36:28.763563 RX Vref 32 -> 127, step: 1
2715 16:36:28.763957
2716 16:36:28.764261 RX Delay -13 -> 252, step: 4
2717 16:36:28.766986
2718 16:36:28.767377 Set Vref, RX VrefLevel [Byte0]: 32
2719 16:36:28.769880 [Byte1]: 32
2720 16:36:28.774995
2721 16:36:28.775612 Set Vref, RX VrefLevel [Byte0]: 33
2722 16:36:28.778182 [Byte1]: 33
2723 16:36:28.782529
2724 16:36:28.782912 Set Vref, RX VrefLevel [Byte0]: 34
2725 16:36:28.785665 [Byte1]: 34
2726 16:36:28.790659
2727 16:36:28.791258 Set Vref, RX VrefLevel [Byte0]: 35
2728 16:36:28.793732 [Byte1]: 35
2729 16:36:28.798175
2730 16:36:28.799005 Set Vref, RX VrefLevel [Byte0]: 36
2731 16:36:28.801367 [Byte1]: 36
2732 16:36:28.805813
2733 16:36:28.806484 Set Vref, RX VrefLevel [Byte0]: 37
2734 16:36:28.809617 [Byte1]: 37
2735 16:36:28.813907
2736 16:36:28.814691 Set Vref, RX VrefLevel [Byte0]: 38
2737 16:36:28.817659 [Byte1]: 38
2738 16:36:28.822324
2739 16:36:28.822771 Set Vref, RX VrefLevel [Byte0]: 39
2740 16:36:28.825394 [Byte1]: 39
2741 16:36:28.829746
2742 16:36:28.830028 Set Vref, RX VrefLevel [Byte0]: 40
2743 16:36:28.833244 [Byte1]: 40
2744 16:36:28.837574
2745 16:36:28.837744 Set Vref, RX VrefLevel [Byte0]: 41
2746 16:36:28.840571 [Byte1]: 41
2747 16:36:28.845061
2748 16:36:28.845201 Set Vref, RX VrefLevel [Byte0]: 42
2749 16:36:28.848918 [Byte1]: 42
2750 16:36:28.853330
2751 16:36:28.853470 Set Vref, RX VrefLevel [Byte0]: 43
2752 16:36:28.856150 [Byte1]: 43
2753 16:36:28.860913
2754 16:36:28.860982 Set Vref, RX VrefLevel [Byte0]: 44
2755 16:36:28.864211 [Byte1]: 44
2756 16:36:28.868858
2757 16:36:28.868940 Set Vref, RX VrefLevel [Byte0]: 45
2758 16:36:28.872392 [Byte1]: 45
2759 16:36:28.876872
2760 16:36:28.876940 Set Vref, RX VrefLevel [Byte0]: 46
2761 16:36:28.879983 [Byte1]: 46
2762 16:36:28.884852
2763 16:36:28.884923 Set Vref, RX VrefLevel [Byte0]: 47
2764 16:36:28.887941 [Byte1]: 47
2765 16:36:28.892825
2766 16:36:28.892898 Set Vref, RX VrefLevel [Byte0]: 48
2767 16:36:28.895856 [Byte1]: 48
2768 16:36:28.900220
2769 16:36:28.900298 Set Vref, RX VrefLevel [Byte0]: 49
2770 16:36:28.903830 [Byte1]: 49
2771 16:36:28.908443
2772 16:36:28.908512 Set Vref, RX VrefLevel [Byte0]: 50
2773 16:36:28.911552 [Byte1]: 50
2774 16:36:28.915944
2775 16:36:28.916011 Set Vref, RX VrefLevel [Byte0]: 51
2776 16:36:28.919552 [Byte1]: 51
2777 16:36:28.923871
2778 16:36:28.923937 Set Vref, RX VrefLevel [Byte0]: 52
2779 16:36:28.927712 [Byte1]: 52
2780 16:36:28.932355
2781 16:36:28.932429 Set Vref, RX VrefLevel [Byte0]: 53
2782 16:36:28.935296 [Byte1]: 53
2783 16:36:28.939803
2784 16:36:28.939885 Set Vref, RX VrefLevel [Byte0]: 54
2785 16:36:28.942905 [Byte1]: 54
2786 16:36:28.948248
2787 16:36:28.948332 Set Vref, RX VrefLevel [Byte0]: 55
2788 16:36:28.951072 [Byte1]: 55
2789 16:36:28.955577
2790 16:36:28.955652 Set Vref, RX VrefLevel [Byte0]: 56
2791 16:36:28.958730 [Byte1]: 56
2792 16:36:28.963733
2793 16:36:28.963801 Set Vref, RX VrefLevel [Byte0]: 57
2794 16:36:28.966675 [Byte1]: 57
2795 16:36:28.971189
2796 16:36:28.971254 Set Vref, RX VrefLevel [Byte0]: 58
2797 16:36:28.974769 [Byte1]: 58
2798 16:36:28.979233
2799 16:36:28.979312 Set Vref, RX VrefLevel [Byte0]: 59
2800 16:36:28.982335 [Byte1]: 59
2801 16:36:28.987587
2802 16:36:28.987662 Set Vref, RX VrefLevel [Byte0]: 60
2803 16:36:28.990318 [Byte1]: 60
2804 16:36:28.994803
2805 16:36:28.994897 Set Vref, RX VrefLevel [Byte0]: 61
2806 16:36:28.998342 [Byte1]: 61
2807 16:36:29.002946
2808 16:36:29.003018 Set Vref, RX VrefLevel [Byte0]: 62
2809 16:36:29.006030 [Byte1]: 62
2810 16:36:29.010859
2811 16:36:29.014255 Set Vref, RX VrefLevel [Byte0]: 63
2812 16:36:29.014327 [Byte1]: 63
2813 16:36:29.018493
2814 16:36:29.018569 Set Vref, RX VrefLevel [Byte0]: 64
2815 16:36:29.021937 [Byte1]: 64
2816 16:36:29.026590
2817 16:36:29.026687 Set Vref, RX VrefLevel [Byte0]: 65
2818 16:36:29.030342 [Byte1]: 65
2819 16:36:29.034602
2820 16:36:29.034671 Set Vref, RX VrefLevel [Byte0]: 66
2821 16:36:29.037555 [Byte1]: 66
2822 16:36:29.042386
2823 16:36:29.042478 Set Vref, RX VrefLevel [Byte0]: 67
2824 16:36:29.045978 [Byte1]: 67
2825 16:36:29.050500
2826 16:36:29.050569 Set Vref, RX VrefLevel [Byte0]: 68
2827 16:36:29.053487 [Byte1]: 68
2828 16:36:29.058003
2829 16:36:29.058073 Set Vref, RX VrefLevel [Byte0]: 69
2830 16:36:29.061801 [Byte1]: 69
2831 16:36:29.066251
2832 16:36:29.066325 Final RX Vref Byte 0 = 57 to rank0
2833 16:36:29.069259 Final RX Vref Byte 1 = 46 to rank0
2834 16:36:29.073013 Final RX Vref Byte 0 = 57 to rank1
2835 16:36:29.076033 Final RX Vref Byte 1 = 46 to rank1==
2836 16:36:29.079640 Dram Type= 6, Freq= 0, CH_0, rank 0
2837 16:36:29.083403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 16:36:29.086412 ==
2839 16:36:29.086488 DQS Delay:
2840 16:36:29.086547 DQS0 = 0, DQS1 = 0
2841 16:36:29.089383 DQM Delay:
2842 16:36:29.089458 DQM0 = 120, DQM1 = 110
2843 16:36:29.093279 DQ Delay:
2844 16:36:29.096228 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2845 16:36:29.099939 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2846 16:36:29.102948 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102
2847 16:36:29.106745 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2848 16:36:29.106821
2849 16:36:29.106879
2850 16:36:29.112789 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2851 16:36:29.116459 CH0 RK0: MR19=404, MR18=1610
2852 16:36:29.122887 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2853 16:36:29.122998
2854 16:36:29.126355 ----->DramcWriteLeveling(PI) begin...
2855 16:36:29.126433 ==
2856 16:36:29.129616 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 16:36:29.132911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 16:36:29.132987 ==
2859 16:36:29.136174 Write leveling (Byte 0): 33 => 33
2860 16:36:29.139522 Write leveling (Byte 1): 28 => 28
2861 16:36:29.142859 DramcWriteLeveling(PI) end<-----
2862 16:36:29.142938
2863 16:36:29.143006 ==
2864 16:36:29.146190 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 16:36:29.149938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 16:36:29.152924 ==
2867 16:36:29.153048 [Gating] SW mode calibration
2868 16:36:29.162933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2869 16:36:29.166115 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2870 16:36:29.169847 0 15 0 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
2871 16:36:29.176669 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 16:36:29.179668 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 16:36:29.182861 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 16:36:29.190244 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 16:36:29.193166 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 16:36:29.197013 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 16:36:29.202964 0 15 28 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
2878 16:36:29.206578 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 16:36:29.209568 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 16:36:29.213506 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 16:36:29.220149 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 16:36:29.223117 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 16:36:29.226956 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 16:36:29.233598 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 16:36:29.236643 1 0 28 | B1->B0 | 3e3e 3d3d | 0 0 | (0 0) (0 0)
2886 16:36:29.240346 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 16:36:29.246783 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 16:36:29.249751 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 16:36:29.253389 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 16:36:29.259971 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 16:36:29.263590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 16:36:29.266899 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 16:36:29.273746 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2894 16:36:29.277104 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2895 16:36:29.280295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 16:36:29.283427 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 16:36:29.289904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 16:36:29.293177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 16:36:29.296802 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 16:36:29.303913 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 16:36:29.306900 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 16:36:29.310571 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 16:36:29.316697 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 16:36:29.320453 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 16:36:29.323506 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 16:36:29.330553 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 16:36:29.333423 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 16:36:29.336578 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2909 16:36:29.343417 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2910 16:36:29.347100 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2911 16:36:29.350121 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 16:36:29.353725 Total UI for P1: 0, mck2ui 16
2913 16:36:29.356467 best dqsien dly found for B0: ( 1, 3, 30)
2914 16:36:29.360308 Total UI for P1: 0, mck2ui 16
2915 16:36:29.363341 best dqsien dly found for B1: ( 1, 3, 28)
2916 16:36:29.367248 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2917 16:36:29.370379 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2918 16:36:29.370455
2919 16:36:29.373361 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2920 16:36:29.380141 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2921 16:36:29.380219 [Gating] SW calibration Done
2922 16:36:29.380278 ==
2923 16:36:29.383820 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 16:36:29.390325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 16:36:29.390403 ==
2926 16:36:29.390462 RX Vref Scan: 0
2927 16:36:29.390517
2928 16:36:29.393261 RX Vref 0 -> 0, step: 1
2929 16:36:29.393359
2930 16:36:29.396737 RX Delay -40 -> 252, step: 8
2931 16:36:29.400232 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2932 16:36:29.403565 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2933 16:36:29.406970 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2934 16:36:29.413698 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2935 16:36:29.416534 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2936 16:36:29.419877 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2937 16:36:29.423326 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2938 16:36:29.426947 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2939 16:36:29.429987 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2940 16:36:29.436826 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2941 16:36:29.439847 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2942 16:36:29.443500 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2943 16:36:29.447148 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2944 16:36:29.453848 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2945 16:36:29.456767 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2946 16:36:29.460473 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2947 16:36:29.460576 ==
2948 16:36:29.463301 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 16:36:29.466759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 16:36:29.466856 ==
2951 16:36:29.470376 DQS Delay:
2952 16:36:29.470455 DQS0 = 0, DQS1 = 0
2953 16:36:29.470514 DQM Delay:
2954 16:36:29.473326 DQM0 = 121, DQM1 = 112
2955 16:36:29.473418 DQ Delay:
2956 16:36:29.477098 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2957 16:36:29.479980 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2958 16:36:29.486798 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2959 16:36:29.490587 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2960 16:36:29.490682
2961 16:36:29.490755
2962 16:36:29.490822 ==
2963 16:36:29.493484 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 16:36:29.497142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 16:36:29.497256 ==
2966 16:36:29.497343
2967 16:36:29.497423
2968 16:36:29.500223 TX Vref Scan disable
2969 16:36:29.500335 == TX Byte 0 ==
2970 16:36:29.506820 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2971 16:36:29.510483 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2972 16:36:29.510671 == TX Byte 1 ==
2973 16:36:29.517298 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2974 16:36:29.520161 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2975 16:36:29.520238 ==
2976 16:36:29.523927 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 16:36:29.527043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 16:36:29.527154 ==
2979 16:36:29.540483 TX Vref=22, minBit 1, minWin=25, winSum=411
2980 16:36:29.543315 TX Vref=24, minBit 1, minWin=25, winSum=415
2981 16:36:29.546978 TX Vref=26, minBit 3, minWin=25, winSum=419
2982 16:36:29.549842 TX Vref=28, minBit 0, minWin=26, winSum=424
2983 16:36:29.553637 TX Vref=30, minBit 1, minWin=26, winSum=424
2984 16:36:29.560457 TX Vref=32, minBit 12, minWin=25, winSum=426
2985 16:36:29.563518 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
2986 16:36:29.563632
2987 16:36:29.567221 Final TX Range 1 Vref 28
2988 16:36:29.567349
2989 16:36:29.567445 ==
2990 16:36:29.570170 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 16:36:29.573697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 16:36:29.573845 ==
2993 16:36:29.573956
2994 16:36:29.576594
2995 16:36:29.576753 TX Vref Scan disable
2996 16:36:29.580156 == TX Byte 0 ==
2997 16:36:29.583768 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2998 16:36:29.586771 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2999 16:36:29.590416 == TX Byte 1 ==
3000 16:36:29.593472 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3001 16:36:29.597167 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3002 16:36:29.597353
3003 16:36:29.600193 [DATLAT]
3004 16:36:29.600450 Freq=1200, CH0 RK1
3005 16:36:29.600656
3006 16:36:29.603981 DATLAT Default: 0xd
3007 16:36:29.604248 0, 0xFFFF, sum = 0
3008 16:36:29.606854 1, 0xFFFF, sum = 0
3009 16:36:29.607046 2, 0xFFFF, sum = 0
3010 16:36:29.610503 3, 0xFFFF, sum = 0
3011 16:36:29.610693 4, 0xFFFF, sum = 0
3012 16:36:29.614013 5, 0xFFFF, sum = 0
3013 16:36:29.614204 6, 0xFFFF, sum = 0
3014 16:36:29.617013 7, 0xFFFF, sum = 0
3015 16:36:29.617205 8, 0xFFFF, sum = 0
3016 16:36:29.620602 9, 0xFFFF, sum = 0
3017 16:36:29.620788 10, 0xFFFF, sum = 0
3018 16:36:29.623689 11, 0xFFFF, sum = 0
3019 16:36:29.623914 12, 0x0, sum = 1
3020 16:36:29.627341 13, 0x0, sum = 2
3021 16:36:29.627619 14, 0x0, sum = 3
3022 16:36:29.630830 15, 0x0, sum = 4
3023 16:36:29.631110 best_step = 13
3024 16:36:29.631323
3025 16:36:29.631590 ==
3026 16:36:29.634004 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 16:36:29.640675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 16:36:29.641102 ==
3029 16:36:29.641622 RX Vref Scan: 0
3030 16:36:29.641997
3031 16:36:29.644385 RX Vref 0 -> 0, step: 1
3032 16:36:29.644807
3033 16:36:29.647326 RX Delay -13 -> 252, step: 4
3034 16:36:29.651095 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3035 16:36:29.654423 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3036 16:36:29.661193 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3037 16:36:29.664166 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3038 16:36:29.667954 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3039 16:36:29.670983 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3040 16:36:29.673969 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3041 16:36:29.677821 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3042 16:36:29.683894 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3043 16:36:29.687722 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3044 16:36:29.690635 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3045 16:36:29.694167 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3046 16:36:29.700655 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3047 16:36:29.704226 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3048 16:36:29.707277 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3049 16:36:29.711034 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3050 16:36:29.711451 ==
3051 16:36:29.714135 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 16:36:29.718220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 16:36:29.721084 ==
3054 16:36:29.721591 DQS Delay:
3055 16:36:29.722153 DQS0 = 0, DQS1 = 0
3056 16:36:29.724143 DQM Delay:
3057 16:36:29.724774 DQM0 = 120, DQM1 = 109
3058 16:36:29.727163 DQ Delay:
3059 16:36:29.730732 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3060 16:36:29.733930 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3061 16:36:29.737488 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3062 16:36:29.740342 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =118
3063 16:36:29.740893
3064 16:36:29.741301
3065 16:36:29.747698 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3066 16:36:29.750696 CH0 RK1: MR19=403, MR18=10F1
3067 16:36:29.757349 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3068 16:36:29.760489 [RxdqsGatingPostProcess] freq 1200
3069 16:36:29.766779 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3070 16:36:29.770511 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 16:36:29.773280 best DQS1 dly(2T, 0.5T) = (0, 12)
3072 16:36:29.773349 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 16:36:29.776778 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3074 16:36:29.780479 best DQS0 dly(2T, 0.5T) = (0, 11)
3075 16:36:29.783433 best DQS1 dly(2T, 0.5T) = (0, 11)
3076 16:36:29.787254 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3077 16:36:29.790269 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3078 16:36:29.793784 Pre-setting of DQS Precalculation
3079 16:36:29.800322 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3080 16:36:29.800393 ==
3081 16:36:29.803869 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 16:36:29.806975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 16:36:29.807052 ==
3084 16:36:29.813491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 16:36:29.816722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3086 16:36:29.826263 [CA 0] Center 37 (7~68) winsize 62
3087 16:36:29.829932 [CA 1] Center 37 (7~68) winsize 62
3088 16:36:29.832924 [CA 2] Center 35 (5~65) winsize 61
3089 16:36:29.836644 [CA 3] Center 34 (4~65) winsize 62
3090 16:36:29.839738 [CA 4] Center 34 (5~64) winsize 60
3091 16:36:29.843484 [CA 5] Center 33 (3~63) winsize 61
3092 16:36:29.843548
3093 16:36:29.846422 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3094 16:36:29.846496
3095 16:36:29.849483 [CATrainingPosCal] consider 1 rank data
3096 16:36:29.853207 u2DelayCellTimex100 = 270/100 ps
3097 16:36:29.856272 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3098 16:36:29.863130 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3099 16:36:29.866225 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3100 16:36:29.870065 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3101 16:36:29.873154 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3102 16:36:29.876189 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3103 16:36:29.876264
3104 16:36:29.879949 CA PerBit enable=1, Macro0, CA PI delay=33
3105 16:36:29.880030
3106 16:36:29.882830 [CBTSetCACLKResult] CA Dly = 33
3107 16:36:29.882905 CS Dly: 7 (0~38)
3108 16:36:29.886301 ==
3109 16:36:29.886392 Dram Type= 6, Freq= 0, CH_1, rank 1
3110 16:36:29.893140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 16:36:29.893256 ==
3112 16:36:29.896038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3113 16:36:29.902691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3114 16:36:29.912210 [CA 0] Center 37 (7~68) winsize 62
3115 16:36:29.915688 [CA 1] Center 37 (7~68) winsize 62
3116 16:36:29.919218 [CA 2] Center 35 (5~65) winsize 61
3117 16:36:29.922184 [CA 3] Center 34 (4~65) winsize 62
3118 16:36:29.925801 [CA 4] Center 34 (4~65) winsize 62
3119 16:36:29.928687 [CA 5] Center 33 (3~63) winsize 61
3120 16:36:29.928955
3121 16:36:29.932718 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3122 16:36:29.933219
3123 16:36:29.935674 [CATrainingPosCal] consider 2 rank data
3124 16:36:29.939384 u2DelayCellTimex100 = 270/100 ps
3125 16:36:29.942473 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3126 16:36:29.945535 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3127 16:36:29.952446 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3128 16:36:29.955925 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3129 16:36:29.958832 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3130 16:36:29.962575 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3131 16:36:29.962999
3132 16:36:29.965522 CA PerBit enable=1, Macro0, CA PI delay=33
3133 16:36:29.965952
3134 16:36:29.968622 [CBTSetCACLKResult] CA Dly = 33
3135 16:36:29.969071 CS Dly: 8 (0~40)
3136 16:36:29.972469
3137 16:36:29.975622 ----->DramcWriteLeveling(PI) begin...
3138 16:36:29.976347 ==
3139 16:36:29.978660 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 16:36:29.982369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 16:36:29.982903 ==
3142 16:36:29.985342 Write leveling (Byte 0): 24 => 24
3143 16:36:29.989025 Write leveling (Byte 1): 28 => 28
3144 16:36:29.992006 DramcWriteLeveling(PI) end<-----
3145 16:36:29.992401
3146 16:36:29.992739 ==
3147 16:36:29.995643 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 16:36:29.998477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 16:36:29.998907 ==
3150 16:36:30.002210 [Gating] SW mode calibration
3151 16:36:30.008573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3152 16:36:30.015332 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3153 16:36:30.018467 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3154 16:36:30.022111 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 16:36:30.028402 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 16:36:30.031820 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 16:36:30.035350 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 16:36:30.041744 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 16:36:30.045364 0 15 24 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 0)
3160 16:36:30.048319 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 16:36:30.054934 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 16:36:30.058668 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 16:36:30.061700 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 16:36:30.068011 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 16:36:30.071538 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 16:36:30.075319 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 16:36:30.081417 1 0 24 | B1->B0 | 3535 4242 | 0 0 | (0 0) (1 1)
3168 16:36:30.085138 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 16:36:30.088256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 16:36:30.091964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 16:36:30.097945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 16:36:30.101109 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 16:36:30.104691 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 16:36:30.111371 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 16:36:30.115042 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3176 16:36:30.118091 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3177 16:36:30.124584 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 16:36:30.128132 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 16:36:30.131469 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 16:36:30.138331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 16:36:30.141824 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 16:36:30.144705 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 16:36:30.151693 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 16:36:30.154550 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 16:36:30.157860 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 16:36:30.164744 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 16:36:30.167827 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 16:36:30.170974 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 16:36:30.178332 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 16:36:30.181023 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 16:36:30.184508 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3192 16:36:30.190948 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3193 16:36:30.194817 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 16:36:30.197628 Total UI for P1: 0, mck2ui 16
3195 16:36:30.201295 best dqsien dly found for B0: ( 1, 3, 26)
3196 16:36:30.204273 Total UI for P1: 0, mck2ui 16
3197 16:36:30.207336 best dqsien dly found for B1: ( 1, 3, 26)
3198 16:36:30.211135 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3199 16:36:30.214071 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3200 16:36:30.214488
3201 16:36:30.217809 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3202 16:36:30.220916 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3203 16:36:30.224693 [Gating] SW calibration Done
3204 16:36:30.225156 ==
3205 16:36:30.227643 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 16:36:30.230666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 16:36:30.234327 ==
3208 16:36:30.234715 RX Vref Scan: 0
3209 16:36:30.235019
3210 16:36:30.237314 RX Vref 0 -> 0, step: 1
3211 16:36:30.237809
3212 16:36:30.238122 RX Delay -40 -> 252, step: 8
3213 16:36:30.244425 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3214 16:36:30.247436 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3215 16:36:30.250925 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3216 16:36:30.254040 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3217 16:36:30.257704 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3218 16:36:30.264150 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3219 16:36:30.267710 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3220 16:36:30.271044 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3221 16:36:30.274656 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3222 16:36:30.277614 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3223 16:36:30.284122 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3224 16:36:30.287852 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3225 16:36:30.290802 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3226 16:36:30.294268 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3227 16:36:30.297831 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3228 16:36:30.304172 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3229 16:36:30.304590 ==
3230 16:36:30.307846 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 16:36:30.310881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 16:36:30.311303 ==
3233 16:36:30.311668 DQS Delay:
3234 16:36:30.314555 DQS0 = 0, DQS1 = 0
3235 16:36:30.314942 DQM Delay:
3236 16:36:30.317747 DQM0 = 120, DQM1 = 116
3237 16:36:30.318195 DQ Delay:
3238 16:36:30.321521 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3239 16:36:30.324191 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3240 16:36:30.327237 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3241 16:36:30.330942 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3242 16:36:30.331331
3243 16:36:30.334712
3244 16:36:30.335219 ==
3245 16:36:30.337717 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 16:36:30.340713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 16:36:30.341102 ==
3248 16:36:30.341400
3249 16:36:30.341712
3250 16:36:30.344563 TX Vref Scan disable
3251 16:36:30.344949 == TX Byte 0 ==
3252 16:36:30.351299 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3253 16:36:30.354322 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3254 16:36:30.354843 == TX Byte 1 ==
3255 16:36:30.360970 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3256 16:36:30.364491 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3257 16:36:30.364939 ==
3258 16:36:30.367259 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 16:36:30.370829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 16:36:30.371645 ==
3261 16:36:30.383216 TX Vref=22, minBit 10, minWin=24, winSum=411
3262 16:36:30.386598 TX Vref=24, minBit 9, minWin=25, winSum=418
3263 16:36:30.389488 TX Vref=26, minBit 11, minWin=25, winSum=424
3264 16:36:30.393147 TX Vref=28, minBit 9, minWin=25, winSum=427
3265 16:36:30.396092 TX Vref=30, minBit 2, minWin=26, winSum=427
3266 16:36:30.402841 TX Vref=32, minBit 9, minWin=25, winSum=427
3267 16:36:30.406322 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 30
3268 16:36:30.406609
3269 16:36:30.409867 Final TX Range 1 Vref 30
3270 16:36:30.410151
3271 16:36:30.410430 ==
3272 16:36:30.412573 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 16:36:30.416111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 16:36:30.416398 ==
3275 16:36:30.419404
3276 16:36:30.419761
3277 16:36:30.420046 TX Vref Scan disable
3278 16:36:30.423058 == TX Byte 0 ==
3279 16:36:30.426183 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3280 16:36:30.429857 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3281 16:36:30.432719 == TX Byte 1 ==
3282 16:36:30.436518 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3283 16:36:30.443120 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3284 16:36:30.443382
3285 16:36:30.443618 [DATLAT]
3286 16:36:30.443821 Freq=1200, CH1 RK0
3287 16:36:30.444017
3288 16:36:30.446119 DATLAT Default: 0xd
3289 16:36:30.446356 0, 0xFFFF, sum = 0
3290 16:36:30.449730 1, 0xFFFF, sum = 0
3291 16:36:30.449989 2, 0xFFFF, sum = 0
3292 16:36:30.452701 3, 0xFFFF, sum = 0
3293 16:36:30.452939 4, 0xFFFF, sum = 0
3294 16:36:30.456499 5, 0xFFFF, sum = 0
3295 16:36:30.459446 6, 0xFFFF, sum = 0
3296 16:36:30.459736 7, 0xFFFF, sum = 0
3297 16:36:30.463401 8, 0xFFFF, sum = 0
3298 16:36:30.463689 9, 0xFFFF, sum = 0
3299 16:36:30.466355 10, 0xFFFF, sum = 0
3300 16:36:30.466641 11, 0xFFFF, sum = 0
3301 16:36:30.469936 12, 0x0, sum = 1
3302 16:36:30.470312 13, 0x0, sum = 2
3303 16:36:30.472920 14, 0x0, sum = 3
3304 16:36:30.473207 15, 0x0, sum = 4
3305 16:36:30.473590 best_step = 13
3306 16:36:30.473866
3307 16:36:30.476496 ==
3308 16:36:30.479430 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 16:36:30.483039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 16:36:30.483325 ==
3311 16:36:30.483607 RX Vref Scan: 1
3312 16:36:30.483869
3313 16:36:30.486272 Set Vref Range= 32 -> 127
3314 16:36:30.486555
3315 16:36:30.489273 RX Vref 32 -> 127, step: 1
3316 16:36:30.489351
3317 16:36:30.492565 RX Delay -5 -> 252, step: 4
3318 16:36:30.492643
3319 16:36:30.495928 Set Vref, RX VrefLevel [Byte0]: 32
3320 16:36:30.499355 [Byte1]: 32
3321 16:36:30.499434
3322 16:36:30.502688 Set Vref, RX VrefLevel [Byte0]: 33
3323 16:36:30.505999 [Byte1]: 33
3324 16:36:30.506081
3325 16:36:30.508981 Set Vref, RX VrefLevel [Byte0]: 34
3326 16:36:30.512725 [Byte1]: 34
3327 16:36:30.517033
3328 16:36:30.517113 Set Vref, RX VrefLevel [Byte0]: 35
3329 16:36:30.519986 [Byte1]: 35
3330 16:36:30.524284
3331 16:36:30.524364 Set Vref, RX VrefLevel [Byte0]: 36
3332 16:36:30.527634 [Byte1]: 36
3333 16:36:30.532623
3334 16:36:30.532701 Set Vref, RX VrefLevel [Byte0]: 37
3335 16:36:30.535371 [Byte1]: 37
3336 16:36:30.540543
3337 16:36:30.540621 Set Vref, RX VrefLevel [Byte0]: 38
3338 16:36:30.543620 [Byte1]: 38
3339 16:36:30.548215
3340 16:36:30.548304 Set Vref, RX VrefLevel [Byte0]: 39
3341 16:36:30.551157 [Byte1]: 39
3342 16:36:30.555809
3343 16:36:30.555898 Set Vref, RX VrefLevel [Byte0]: 40
3344 16:36:30.559462 [Byte1]: 40
3345 16:36:30.564048
3346 16:36:30.564126 Set Vref, RX VrefLevel [Byte0]: 41
3347 16:36:30.567091 [Byte1]: 41
3348 16:36:30.571587
3349 16:36:30.571663 Set Vref, RX VrefLevel [Byte0]: 42
3350 16:36:30.575245 [Byte1]: 42
3351 16:36:30.579477
3352 16:36:30.579575 Set Vref, RX VrefLevel [Byte0]: 43
3353 16:36:30.582607 [Byte1]: 43
3354 16:36:30.586956
3355 16:36:30.587030 Set Vref, RX VrefLevel [Byte0]: 44
3356 16:36:30.590651 [Byte1]: 44
3357 16:36:30.595162
3358 16:36:30.595314 Set Vref, RX VrefLevel [Byte0]: 45
3359 16:36:30.598203 [Byte1]: 45
3360 16:36:30.603252
3361 16:36:30.603329 Set Vref, RX VrefLevel [Byte0]: 46
3362 16:36:30.606132 [Byte1]: 46
3363 16:36:30.611013
3364 16:36:30.611090 Set Vref, RX VrefLevel [Byte0]: 47
3365 16:36:30.613927 [Byte1]: 47
3366 16:36:30.618621
3367 16:36:30.618703 Set Vref, RX VrefLevel [Byte0]: 48
3368 16:36:30.622054 [Byte1]: 48
3369 16:36:30.626306
3370 16:36:30.626381 Set Vref, RX VrefLevel [Byte0]: 49
3371 16:36:30.629947 [Byte1]: 49
3372 16:36:30.634200
3373 16:36:30.634307 Set Vref, RX VrefLevel [Byte0]: 50
3374 16:36:30.637929 [Byte1]: 50
3375 16:36:30.642256
3376 16:36:30.642333 Set Vref, RX VrefLevel [Byte0]: 51
3377 16:36:30.645681 [Byte1]: 51
3378 16:36:30.649864
3379 16:36:30.649943 Set Vref, RX VrefLevel [Byte0]: 52
3380 16:36:30.653414 [Byte1]: 52
3381 16:36:30.657799
3382 16:36:30.657897 Set Vref, RX VrefLevel [Byte0]: 53
3383 16:36:30.661477 [Byte1]: 53
3384 16:36:30.665947
3385 16:36:30.666016 Set Vref, RX VrefLevel [Byte0]: 54
3386 16:36:30.669126 [Byte1]: 54
3387 16:36:30.673636
3388 16:36:30.673707 Set Vref, RX VrefLevel [Byte0]: 55
3389 16:36:30.676681 [Byte1]: 55
3390 16:36:30.681849
3391 16:36:30.681961 Set Vref, RX VrefLevel [Byte0]: 56
3392 16:36:30.684752 [Byte1]: 56
3393 16:36:30.689225
3394 16:36:30.689319 Set Vref, RX VrefLevel [Byte0]: 57
3395 16:36:30.693038 [Byte1]: 57
3396 16:36:30.697521
3397 16:36:30.697648 Set Vref, RX VrefLevel [Byte0]: 58
3398 16:36:30.700581 [Byte1]: 58
3399 16:36:30.704844
3400 16:36:30.704969 Set Vref, RX VrefLevel [Byte0]: 59
3401 16:36:30.708259 [Byte1]: 59
3402 16:36:30.712670
3403 16:36:30.712830 Set Vref, RX VrefLevel [Byte0]: 60
3404 16:36:30.716324 [Byte1]: 60
3405 16:36:30.720679
3406 16:36:30.720758 Set Vref, RX VrefLevel [Byte0]: 61
3407 16:36:30.727338 [Byte1]: 61
3408 16:36:30.727415
3409 16:36:30.730913 Set Vref, RX VrefLevel [Byte0]: 62
3410 16:36:30.733717 [Byte1]: 62
3411 16:36:30.733793
3412 16:36:30.736986 Set Vref, RX VrefLevel [Byte0]: 63
3413 16:36:30.740610 [Byte1]: 63
3414 16:36:30.744224
3415 16:36:30.744298 Set Vref, RX VrefLevel [Byte0]: 64
3416 16:36:30.747622 [Byte1]: 64
3417 16:36:30.751804
3418 16:36:30.751880 Set Vref, RX VrefLevel [Byte0]: 65
3419 16:36:30.755369 [Byte1]: 65
3420 16:36:30.759671
3421 16:36:30.759753 Set Vref, RX VrefLevel [Byte0]: 66
3422 16:36:30.763093 [Byte1]: 66
3423 16:36:30.768086
3424 16:36:30.768196 Set Vref, RX VrefLevel [Byte0]: 67
3425 16:36:30.771010 [Byte1]: 67
3426 16:36:30.775586
3427 16:36:30.775661 Set Vref, RX VrefLevel [Byte0]: 68
3428 16:36:30.779353 [Byte1]: 68
3429 16:36:30.783861
3430 16:36:30.783938 Set Vref, RX VrefLevel [Byte0]: 69
3431 16:36:30.786800 [Byte1]: 69
3432 16:36:30.791228
3433 16:36:30.791304 Final RX Vref Byte 0 = 55 to rank0
3434 16:36:30.794978 Final RX Vref Byte 1 = 53 to rank0
3435 16:36:30.797966 Final RX Vref Byte 0 = 55 to rank1
3436 16:36:30.801677 Final RX Vref Byte 1 = 53 to rank1==
3437 16:36:30.804565 Dram Type= 6, Freq= 0, CH_1, rank 0
3438 16:36:30.811081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 16:36:30.811160 ==
3440 16:36:30.811247 DQS Delay:
3441 16:36:30.811304 DQS0 = 0, DQS1 = 0
3442 16:36:30.814606 DQM Delay:
3443 16:36:30.814681 DQM0 = 120, DQM1 = 117
3444 16:36:30.818267 DQ Delay:
3445 16:36:30.821171 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3446 16:36:30.824986 DQ4 =122, DQ5 =128, DQ6 =130, DQ7 =120
3447 16:36:30.827945 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3448 16:36:30.830977 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3449 16:36:30.831053
3450 16:36:30.831112
3451 16:36:30.841388 [DQSOSCAuto] RK0, (LSB)MR18= 0x315, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3452 16:36:30.841465 CH1 RK0: MR19=404, MR18=315
3453 16:36:30.847889 CH1_RK0: MR19=0x404, MR18=0x315, DQSOSC=401, MR23=63, INC=40, DEC=27
3454 16:36:30.847977
3455 16:36:30.851585 ----->DramcWriteLeveling(PI) begin...
3456 16:36:30.851661 ==
3457 16:36:30.854406 Dram Type= 6, Freq= 0, CH_1, rank 1
3458 16:36:30.857911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 16:36:30.861262 ==
3460 16:36:30.861337 Write leveling (Byte 0): 25 => 25
3461 16:36:30.864667 Write leveling (Byte 1): 29 => 29
3462 16:36:30.867504 DramcWriteLeveling(PI) end<-----
3463 16:36:30.867591
3464 16:36:30.867659 ==
3465 16:36:30.871065 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 16:36:30.878238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 16:36:30.878383 ==
3468 16:36:30.878517 [Gating] SW mode calibration
3469 16:36:30.888159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3470 16:36:30.891093 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3471 16:36:30.897432 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 16:36:30.901333 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 16:36:30.904455 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 16:36:30.907409 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 16:36:30.914381 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 16:36:30.918213 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3477 16:36:30.920979 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 1)
3478 16:36:30.927532 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3479 16:36:30.931523 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 16:36:30.934571 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 16:36:30.941127 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 16:36:30.944086 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 16:36:30.947931 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 16:36:30.954747 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3485 16:36:30.957835 1 0 24 | B1->B0 | 4141 2a2a | 1 1 | (0 0) (0 0)
3486 16:36:30.960741 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 16:36:30.967422 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 16:36:30.971040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 16:36:30.974636 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 16:36:30.980913 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 16:36:30.984873 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 16:36:30.987635 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 16:36:30.994170 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3494 16:36:30.997848 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3495 16:36:31.000867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 16:36:31.007546 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 16:36:31.011116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 16:36:31.014147 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 16:36:31.021171 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 16:36:31.023968 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 16:36:31.027564 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 16:36:31.034424 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 16:36:31.037916 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 16:36:31.040960 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 16:36:31.044311 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 16:36:31.050926 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 16:36:31.054246 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 16:36:31.057383 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3509 16:36:31.063743 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3510 16:36:31.067640 Total UI for P1: 0, mck2ui 16
3511 16:36:31.070557 best dqsien dly found for B1: ( 1, 3, 20)
3512 16:36:31.073512 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3513 16:36:31.077431 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 16:36:31.080922 Total UI for P1: 0, mck2ui 16
3515 16:36:31.083910 best dqsien dly found for B0: ( 1, 3, 26)
3516 16:36:31.087616 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3517 16:36:31.090910 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3518 16:36:31.091047
3519 16:36:31.096945 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3520 16:36:31.100422 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3521 16:36:31.104467 [Gating] SW calibration Done
3522 16:36:31.104854 ==
3523 16:36:31.107584 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 16:36:31.110515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 16:36:31.110916 ==
3526 16:36:31.111225 RX Vref Scan: 0
3527 16:36:31.111509
3528 16:36:31.114146 RX Vref 0 -> 0, step: 1
3529 16:36:31.114532
3530 16:36:31.117063 RX Delay -40 -> 252, step: 8
3531 16:36:31.120929 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3532 16:36:31.123938 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3533 16:36:31.130471 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3534 16:36:31.134174 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3535 16:36:31.137656 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3536 16:36:31.140779 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3537 16:36:31.144557 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3538 16:36:31.150859 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3539 16:36:31.154238 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3540 16:36:31.157192 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3541 16:36:31.160852 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3542 16:36:31.163950 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3543 16:36:31.170477 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3544 16:36:31.174465 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3545 16:36:31.177319 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3546 16:36:31.180771 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3547 16:36:31.181054 ==
3548 16:36:31.183674 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 16:36:31.190208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 16:36:31.190383 ==
3551 16:36:31.190516 DQS Delay:
3552 16:36:31.190639 DQS0 = 0, DQS1 = 0
3553 16:36:31.193339 DQM Delay:
3554 16:36:31.193496 DQM0 = 121, DQM1 = 117
3555 16:36:31.196502 DQ Delay:
3556 16:36:31.199908 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3557 16:36:31.203571 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3558 16:36:31.206429 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =111
3559 16:36:31.210170 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3560 16:36:31.210247
3561 16:36:31.210306
3562 16:36:31.210361 ==
3563 16:36:31.213826 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 16:36:31.216658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 16:36:31.219803 ==
3566 16:36:31.219879
3567 16:36:31.219938
3568 16:36:31.219992 TX Vref Scan disable
3569 16:36:31.223517 == TX Byte 0 ==
3570 16:36:31.226508 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3571 16:36:31.230200 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3572 16:36:31.233233 == TX Byte 1 ==
3573 16:36:31.236906 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3574 16:36:31.239929 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3575 16:36:31.240024 ==
3576 16:36:31.242848 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 16:36:31.249488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 16:36:31.249616 ==
3579 16:36:31.260507 TX Vref=22, minBit 9, minWin=25, winSum=421
3580 16:36:31.264092 TX Vref=24, minBit 1, minWin=26, winSum=426
3581 16:36:31.267576 TX Vref=26, minBit 1, minWin=26, winSum=430
3582 16:36:31.270935 TX Vref=28, minBit 9, minWin=26, winSum=430
3583 16:36:31.274755 TX Vref=30, minBit 9, minWin=26, winSum=435
3584 16:36:31.277830 TX Vref=32, minBit 9, minWin=26, winSum=436
3585 16:36:31.284539 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3586 16:36:31.284802
3587 16:36:31.288225 Final TX Range 1 Vref 32
3588 16:36:31.288415
3589 16:36:31.288523 ==
3590 16:36:31.291161 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 16:36:31.294944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 16:36:31.295101 ==
3593 16:36:31.295223
3594 16:36:31.295334
3595 16:36:31.297948 TX Vref Scan disable
3596 16:36:31.300952 == TX Byte 0 ==
3597 16:36:31.304487 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3598 16:36:31.308105 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3599 16:36:31.310990 == TX Byte 1 ==
3600 16:36:31.314651 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3601 16:36:31.317523 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3602 16:36:31.317645
3603 16:36:31.320907 [DATLAT]
3604 16:36:31.321000 Freq=1200, CH1 RK1
3605 16:36:31.321065
3606 16:36:31.324289 DATLAT Default: 0xd
3607 16:36:31.324387 0, 0xFFFF, sum = 0
3608 16:36:31.328055 1, 0xFFFF, sum = 0
3609 16:36:31.328151 2, 0xFFFF, sum = 0
3610 16:36:31.330964 3, 0xFFFF, sum = 0
3611 16:36:31.331061 4, 0xFFFF, sum = 0
3612 16:36:31.334796 5, 0xFFFF, sum = 0
3613 16:36:31.334892 6, 0xFFFF, sum = 0
3614 16:36:31.337761 7, 0xFFFF, sum = 0
3615 16:36:31.337839 8, 0xFFFF, sum = 0
3616 16:36:31.341453 9, 0xFFFF, sum = 0
3617 16:36:31.341539 10, 0xFFFF, sum = 0
3618 16:36:31.344408 11, 0xFFFF, sum = 0
3619 16:36:31.344487 12, 0x0, sum = 1
3620 16:36:31.348242 13, 0x0, sum = 2
3621 16:36:31.348322 14, 0x0, sum = 3
3622 16:36:31.351106 15, 0x0, sum = 4
3623 16:36:31.351186 best_step = 13
3624 16:36:31.351262
3625 16:36:31.351334 ==
3626 16:36:31.354918 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 16:36:31.361374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 16:36:31.361468 ==
3629 16:36:31.361582 RX Vref Scan: 0
3630 16:36:31.361667
3631 16:36:31.364257 RX Vref 0 -> 0, step: 1
3632 16:36:31.364354
3633 16:36:31.367925 RX Delay -5 -> 252, step: 4
3634 16:36:31.370971 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3635 16:36:31.374646 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3636 16:36:31.380967 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3637 16:36:31.384689 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3638 16:36:31.387684 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3639 16:36:31.391417 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3640 16:36:31.394394 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3641 16:36:31.398054 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3642 16:36:31.404936 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3643 16:36:31.407895 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3644 16:36:31.411787 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3645 16:36:31.414786 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3646 16:36:31.421137 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3647 16:36:31.424436 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3648 16:36:31.428148 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3649 16:36:31.431682 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3650 16:36:31.432110 ==
3651 16:36:31.434363 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 16:36:31.437884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 16:36:31.441487 ==
3654 16:36:31.442160 DQS Delay:
3655 16:36:31.442612 DQS0 = 0, DQS1 = 0
3656 16:36:31.444529 DQM Delay:
3657 16:36:31.445008 DQM0 = 120, DQM1 = 118
3658 16:36:31.447649 DQ Delay:
3659 16:36:31.451117 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3660 16:36:31.454799 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3661 16:36:31.457663 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3662 16:36:31.460737 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3663 16:36:31.460989
3664 16:36:31.461208
3665 16:36:31.467453 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3666 16:36:31.471219 CH1 RK1: MR19=403, MR18=11EE
3667 16:36:31.477750 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3668 16:36:31.480807 [RxdqsGatingPostProcess] freq 1200
3669 16:36:31.487289 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3670 16:36:31.491211 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 16:36:31.493962 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 16:36:31.497680 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 16:36:31.500616 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 16:36:31.500737 best DQS0 dly(2T, 0.5T) = (0, 11)
3675 16:36:31.504330 best DQS1 dly(2T, 0.5T) = (0, 11)
3676 16:36:31.507161 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3677 16:36:31.510761 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3678 16:36:31.513701 Pre-setting of DQS Precalculation
3679 16:36:31.520515 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3680 16:36:31.527241 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3681 16:36:31.533748 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3682 16:36:31.533822
3683 16:36:31.533880
3684 16:36:31.537211 [Calibration Summary] 2400 Mbps
3685 16:36:31.537275 CH 0, Rank 0
3686 16:36:31.540046 SW Impedance : PASS
3687 16:36:31.543557 DUTY Scan : NO K
3688 16:36:31.543645 ZQ Calibration : PASS
3689 16:36:31.546985 Jitter Meter : NO K
3690 16:36:31.550601 CBT Training : PASS
3691 16:36:31.550669 Write leveling : PASS
3692 16:36:31.554093 RX DQS gating : PASS
3693 16:36:31.556879 RX DQ/DQS(RDDQC) : PASS
3694 16:36:31.556955 TX DQ/DQS : PASS
3695 16:36:31.560254 RX DATLAT : PASS
3696 16:36:31.564097 RX DQ/DQS(Engine): PASS
3697 16:36:31.564176 TX OE : NO K
3698 16:36:31.564242 All Pass.
3699 16:36:31.566831
3700 16:36:31.566912 CH 0, Rank 1
3701 16:36:31.570244 SW Impedance : PASS
3702 16:36:31.570356 DUTY Scan : NO K
3703 16:36:31.573961 ZQ Calibration : PASS
3704 16:36:31.576906 Jitter Meter : NO K
3705 16:36:31.576983 CBT Training : PASS
3706 16:36:31.579898 Write leveling : PASS
3707 16:36:31.579974 RX DQS gating : PASS
3708 16:36:31.583643 RX DQ/DQS(RDDQC) : PASS
3709 16:36:31.586714 TX DQ/DQS : PASS
3710 16:36:31.586814 RX DATLAT : PASS
3711 16:36:31.589947 RX DQ/DQS(Engine): PASS
3712 16:36:31.593507 TX OE : NO K
3713 16:36:31.593605 All Pass.
3714 16:36:31.593669
3715 16:36:31.593727 CH 1, Rank 0
3716 16:36:31.596516 SW Impedance : PASS
3717 16:36:31.600219 DUTY Scan : NO K
3718 16:36:31.600315 ZQ Calibration : PASS
3719 16:36:31.603810 Jitter Meter : NO K
3720 16:36:31.606865 CBT Training : PASS
3721 16:36:31.606959 Write leveling : PASS
3722 16:36:31.609833 RX DQS gating : PASS
3723 16:36:31.613520 RX DQ/DQS(RDDQC) : PASS
3724 16:36:31.613648 TX DQ/DQS : PASS
3725 16:36:31.616626 RX DATLAT : PASS
3726 16:36:31.620267 RX DQ/DQS(Engine): PASS
3727 16:36:31.620444 TX OE : NO K
3728 16:36:31.623437 All Pass.
3729 16:36:31.623574
3730 16:36:31.623682 CH 1, Rank 1
3731 16:36:31.626499 SW Impedance : PASS
3732 16:36:31.626660 DUTY Scan : NO K
3733 16:36:31.630198 ZQ Calibration : PASS
3734 16:36:31.633210 Jitter Meter : NO K
3735 16:36:31.633401 CBT Training : PASS
3736 16:36:31.636397 Write leveling : PASS
3737 16:36:31.636585 RX DQS gating : PASS
3738 16:36:31.640018 RX DQ/DQS(RDDQC) : PASS
3739 16:36:31.642941 TX DQ/DQS : PASS
3740 16:36:31.643166 RX DATLAT : PASS
3741 16:36:31.646741 RX DQ/DQS(Engine): PASS
3742 16:36:31.649809 TX OE : NO K
3743 16:36:31.650041 All Pass.
3744 16:36:31.650222
3745 16:36:31.653397 DramC Write-DBI off
3746 16:36:31.653685 PER_BANK_REFRESH: Hybrid Mode
3747 16:36:31.656225 TX_TRACKING: ON
3748 16:36:31.666503 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3749 16:36:31.669836 [FAST_K] Save calibration result to emmc
3750 16:36:31.673214 dramc_set_vcore_voltage set vcore to 650000
3751 16:36:31.673591 Read voltage for 600, 5
3752 16:36:31.676725 Vio18 = 0
3753 16:36:31.677080 Vcore = 650000
3754 16:36:31.677359 Vdram = 0
3755 16:36:31.679400 Vddq = 0
3756 16:36:31.679785 Vmddr = 0
3757 16:36:31.686637 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3758 16:36:31.689674 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3759 16:36:31.693364 MEM_TYPE=3, freq_sel=19
3760 16:36:31.696374 sv_algorithm_assistance_LP4_1600
3761 16:36:31.699380 ============ PULL DRAM RESETB DOWN ============
3762 16:36:31.703289 ========== PULL DRAM RESETB DOWN end =========
3763 16:36:31.709083 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3764 16:36:31.712602 ===================================
3765 16:36:31.712883 LPDDR4 DRAM CONFIGURATION
3766 16:36:31.716026 ===================================
3767 16:36:31.718930 EX_ROW_EN[0] = 0x0
3768 16:36:31.722646 EX_ROW_EN[1] = 0x0
3769 16:36:31.722904 LP4Y_EN = 0x0
3770 16:36:31.725603 WORK_FSP = 0x0
3771 16:36:31.725813 WL = 0x2
3772 16:36:31.729416 RL = 0x2
3773 16:36:31.729684 BL = 0x2
3774 16:36:31.732336 RPST = 0x0
3775 16:36:31.732592 RD_PRE = 0x0
3776 16:36:31.735989 WR_PRE = 0x1
3777 16:36:31.736226 WR_PST = 0x0
3778 16:36:31.738763 DBI_WR = 0x0
3779 16:36:31.738839 DBI_RD = 0x0
3780 16:36:31.742527 OTF = 0x1
3781 16:36:31.746063 ===================================
3782 16:36:31.749427 ===================================
3783 16:36:31.749879 ANA top config
3784 16:36:31.752468 ===================================
3785 16:36:31.756303 DLL_ASYNC_EN = 0
3786 16:36:31.759176 ALL_SLAVE_EN = 1
3787 16:36:31.759568 NEW_RANK_MODE = 1
3788 16:36:31.762753 DLL_IDLE_MODE = 1
3789 16:36:31.765774 LP45_APHY_COMB_EN = 1
3790 16:36:31.769401 TX_ODT_DIS = 1
3791 16:36:31.772353 NEW_8X_MODE = 1
3792 16:36:31.775984 ===================================
3793 16:36:31.779067 ===================================
3794 16:36:31.779588 data_rate = 1200
3795 16:36:31.782823 CKR = 1
3796 16:36:31.785771 DQ_P2S_RATIO = 8
3797 16:36:31.789397 ===================================
3798 16:36:31.792099 CA_P2S_RATIO = 8
3799 16:36:31.795674 DQ_CA_OPEN = 0
3800 16:36:31.799156 DQ_SEMI_OPEN = 0
3801 16:36:31.799550 CA_SEMI_OPEN = 0
3802 16:36:31.802676 CA_FULL_RATE = 0
3803 16:36:31.805303 DQ_CKDIV4_EN = 1
3804 16:36:31.808766 CA_CKDIV4_EN = 1
3805 16:36:31.812258 CA_PREDIV_EN = 0
3806 16:36:31.815822 PH8_DLY = 0
3807 16:36:31.816415 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3808 16:36:31.818684 DQ_AAMCK_DIV = 4
3809 16:36:31.822299 CA_AAMCK_DIV = 4
3810 16:36:31.825940 CA_ADMCK_DIV = 4
3811 16:36:31.828723 DQ_TRACK_CA_EN = 0
3812 16:36:31.832439 CA_PICK = 600
3813 16:36:31.835520 CA_MCKIO = 600
3814 16:36:31.835974 MCKIO_SEMI = 0
3815 16:36:31.839390 PLL_FREQ = 2288
3816 16:36:31.842407 DQ_UI_PI_RATIO = 32
3817 16:36:31.845251 CA_UI_PI_RATIO = 0
3818 16:36:31.849137 ===================================
3819 16:36:31.852163 ===================================
3820 16:36:31.855053 memory_type:LPDDR4
3821 16:36:31.855250 GP_NUM : 10
3822 16:36:31.858796 SRAM_EN : 1
3823 16:36:31.861714 MD32_EN : 0
3824 16:36:31.861937 ===================================
3825 16:36:31.865507 [ANA_INIT] >>>>>>>>>>>>>>
3826 16:36:31.868436 <<<<<< [CONFIGURE PHASE]: ANA_TX
3827 16:36:31.872103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3828 16:36:31.875041 ===================================
3829 16:36:31.878001 data_rate = 1200,PCW = 0X5800
3830 16:36:31.881674 ===================================
3831 16:36:31.884687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3832 16:36:31.891386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3833 16:36:31.895248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3834 16:36:31.901905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3835 16:36:31.904792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3836 16:36:31.909060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3837 16:36:31.909409 [ANA_INIT] flow start
3838 16:36:31.912024 [ANA_INIT] PLL >>>>>>>>
3839 16:36:31.915635 [ANA_INIT] PLL <<<<<<<<
3840 16:36:31.916033 [ANA_INIT] MIDPI >>>>>>>>
3841 16:36:31.918575 [ANA_INIT] MIDPI <<<<<<<<
3842 16:36:31.922263 [ANA_INIT] DLL >>>>>>>>
3843 16:36:31.922652 [ANA_INIT] flow end
3844 16:36:31.928979 ============ LP4 DIFF to SE enter ============
3845 16:36:31.932325 ============ LP4 DIFF to SE exit ============
3846 16:36:31.935632 [ANA_INIT] <<<<<<<<<<<<<
3847 16:36:31.938494 [Flow] Enable top DCM control >>>>>
3848 16:36:31.942174 [Flow] Enable top DCM control <<<<<
3849 16:36:31.942717 Enable DLL master slave shuffle
3850 16:36:31.948328 ==============================================================
3851 16:36:31.951966 Gating Mode config
3852 16:36:31.954868 ==============================================================
3853 16:36:31.958466 Config description:
3854 16:36:31.967944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3855 16:36:31.974527 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3856 16:36:31.978202 SELPH_MODE 0: By rank 1: By Phase
3857 16:36:31.985063 ==============================================================
3858 16:36:31.988069 GAT_TRACK_EN = 1
3859 16:36:31.991758 RX_GATING_MODE = 2
3860 16:36:31.994718 RX_GATING_TRACK_MODE = 2
3861 16:36:31.997871 SELPH_MODE = 1
3862 16:36:31.997992 PICG_EARLY_EN = 1
3863 16:36:32.001485 VALID_LAT_VALUE = 1
3864 16:36:32.008377 ==============================================================
3865 16:36:32.011468 Enter into Gating configuration >>>>
3866 16:36:32.014390 Exit from Gating configuration <<<<
3867 16:36:32.018006 Enter into DVFS_PRE_config >>>>>
3868 16:36:32.027955 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3869 16:36:32.030971 Exit from DVFS_PRE_config <<<<<
3870 16:36:32.034650 Enter into PICG configuration >>>>
3871 16:36:32.037806 Exit from PICG configuration <<<<
3872 16:36:32.041254 [RX_INPUT] configuration >>>>>
3873 16:36:32.044591 [RX_INPUT] configuration <<<<<
3874 16:36:32.047864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3875 16:36:32.054363 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3876 16:36:32.060847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 16:36:32.067994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 16:36:32.074570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 16:36:32.077412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 16:36:32.084326 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3881 16:36:32.088266 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3882 16:36:32.091232 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3883 16:36:32.094929 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3884 16:36:32.101125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3885 16:36:32.104813 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3886 16:36:32.107784 ===================================
3887 16:36:32.111461 LPDDR4 DRAM CONFIGURATION
3888 16:36:32.114375 ===================================
3889 16:36:32.114777 EX_ROW_EN[0] = 0x0
3890 16:36:32.117972 EX_ROW_EN[1] = 0x0
3891 16:36:32.118438 LP4Y_EN = 0x0
3892 16:36:32.120900 WORK_FSP = 0x0
3893 16:36:32.121434 WL = 0x2
3894 16:36:32.124679 RL = 0x2
3895 16:36:32.125082 BL = 0x2
3896 16:36:32.127536 RPST = 0x0
3897 16:36:32.127925 RD_PRE = 0x0
3898 16:36:32.131272 WR_PRE = 0x1
3899 16:36:32.134257 WR_PST = 0x0
3900 16:36:32.134651 DBI_WR = 0x0
3901 16:36:32.137978 DBI_RD = 0x0
3902 16:36:32.138369 OTF = 0x1
3903 16:36:32.140668 ===================================
3904 16:36:32.144443 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3905 16:36:32.147312 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3906 16:36:32.154109 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 16:36:32.157121 ===================================
3908 16:36:32.160799 LPDDR4 DRAM CONFIGURATION
3909 16:36:32.163707 ===================================
3910 16:36:32.164412 EX_ROW_EN[0] = 0x10
3911 16:36:32.167288 EX_ROW_EN[1] = 0x0
3912 16:36:32.167612 LP4Y_EN = 0x0
3913 16:36:32.170902 WORK_FSP = 0x0
3914 16:36:32.171147 WL = 0x2
3915 16:36:32.174374 RL = 0x2
3916 16:36:32.174634 BL = 0x2
3917 16:36:32.177135 RPST = 0x0
3918 16:36:32.177440 RD_PRE = 0x0
3919 16:36:32.180407 WR_PRE = 0x1
3920 16:36:32.180618 WR_PST = 0x0
3921 16:36:32.183887 DBI_WR = 0x0
3922 16:36:32.184068 DBI_RD = 0x0
3923 16:36:32.187241 OTF = 0x1
3924 16:36:32.190620 ===================================
3925 16:36:32.196913 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3926 16:36:32.200235 nWR fixed to 30
3927 16:36:32.204027 [ModeRegInit_LP4] CH0 RK0
3928 16:36:32.204240 [ModeRegInit_LP4] CH0 RK1
3929 16:36:32.207071 [ModeRegInit_LP4] CH1 RK0
3930 16:36:32.210136 [ModeRegInit_LP4] CH1 RK1
3931 16:36:32.210447 match AC timing 17
3932 16:36:32.217022 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3933 16:36:32.220626 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3934 16:36:32.223786 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3935 16:36:32.230216 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3936 16:36:32.233447 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3937 16:36:32.233562 ==
3938 16:36:32.237246 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 16:36:32.240388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 16:36:32.240457 ==
3941 16:36:32.246767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 16:36:32.253416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3943 16:36:32.257160 [CA 0] Center 35 (5~66) winsize 62
3944 16:36:32.260185 [CA 1] Center 35 (5~66) winsize 62
3945 16:36:32.264059 [CA 2] Center 33 (3~64) winsize 62
3946 16:36:32.267148 [CA 3] Center 33 (2~64) winsize 63
3947 16:36:32.270193 [CA 4] Center 33 (2~64) winsize 63
3948 16:36:32.274115 [CA 5] Center 32 (2~63) winsize 62
3949 16:36:32.274233
3950 16:36:32.276975 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3951 16:36:32.277148
3952 16:36:32.280622 [CATrainingPosCal] consider 1 rank data
3953 16:36:32.283566 u2DelayCellTimex100 = 270/100 ps
3954 16:36:32.287210 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3955 16:36:32.290152 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3956 16:36:32.293476 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3957 16:36:32.296531 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3958 16:36:32.299796 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3959 16:36:32.303323 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3960 16:36:32.306780
3961 16:36:32.310352 CA PerBit enable=1, Macro0, CA PI delay=32
3962 16:36:32.310456
3963 16:36:32.313567 [CBTSetCACLKResult] CA Dly = 32
3964 16:36:32.313651 CS Dly: 5 (0~36)
3965 16:36:32.313715 ==
3966 16:36:32.316904 Dram Type= 6, Freq= 0, CH_0, rank 1
3967 16:36:32.320143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 16:36:32.320232 ==
3969 16:36:32.326533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3970 16:36:32.333098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3971 16:36:32.337051 [CA 0] Center 35 (5~66) winsize 62
3972 16:36:32.339759 [CA 1] Center 35 (5~66) winsize 62
3973 16:36:32.343559 [CA 2] Center 34 (3~65) winsize 63
3974 16:36:32.346574 [CA 3] Center 33 (3~64) winsize 62
3975 16:36:32.350342 [CA 4] Center 33 (2~64) winsize 63
3976 16:36:32.353118 [CA 5] Center 32 (2~63) winsize 62
3977 16:36:32.353247
3978 16:36:32.356878 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3979 16:36:32.356993
3980 16:36:32.359910 [CATrainingPosCal] consider 2 rank data
3981 16:36:32.363484 u2DelayCellTimex100 = 270/100 ps
3982 16:36:32.366418 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3983 16:36:32.370172 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3984 16:36:32.373114 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3985 16:36:32.377043 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3986 16:36:32.379888 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3987 16:36:32.386623 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3988 16:36:32.387044
3989 16:36:32.390397 CA PerBit enable=1, Macro0, CA PI delay=32
3990 16:36:32.390759
3991 16:36:32.393444 [CBTSetCACLKResult] CA Dly = 32
3992 16:36:32.393929 CS Dly: 5 (0~36)
3993 16:36:32.394325
3994 16:36:32.396475 ----->DramcWriteLeveling(PI) begin...
3995 16:36:32.396915 ==
3996 16:36:32.400102 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 16:36:32.403699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 16:36:32.406593 ==
3999 16:36:32.406953 Write leveling (Byte 0): 34 => 34
4000 16:36:32.410178 Write leveling (Byte 1): 32 => 32
4001 16:36:32.413182 DramcWriteLeveling(PI) end<-----
4002 16:36:32.413638
4003 16:36:32.414037 ==
4004 16:36:32.416901 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 16:36:32.423491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 16:36:32.423892 ==
4007 16:36:32.426993 [Gating] SW mode calibration
4008 16:36:32.433287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4009 16:36:32.436976 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4010 16:36:32.439859 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 16:36:32.446523 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 16:36:32.449838 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 16:36:32.452925 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
4014 16:36:32.460056 0 9 16 | B1->B0 | 3333 2323 | 1 0 | (0 0) (0 0)
4015 16:36:32.463141 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 16:36:32.466886 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 16:36:32.472791 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 16:36:32.476287 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 16:36:32.479414 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 16:36:32.486146 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4021 16:36:32.489804 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4022 16:36:32.492774 0 10 16 | B1->B0 | 3332 4646 | 1 0 | (1 1) (0 0)
4023 16:36:32.499705 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 16:36:32.502597 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 16:36:32.506542 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 16:36:32.512881 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 16:36:32.516427 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 16:36:32.519169 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 16:36:32.526169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4030 16:36:32.529871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 16:36:32.532682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 16:36:32.539937 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 16:36:32.542746 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 16:36:32.545655 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 16:36:32.552921 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 16:36:32.555794 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 16:36:32.559143 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 16:36:32.565946 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 16:36:32.569494 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 16:36:32.572456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 16:36:32.579231 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 16:36:32.582772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 16:36:32.585939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 16:36:32.592585 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 16:36:32.595518 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4046 16:36:32.599369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4047 16:36:32.602318 Total UI for P1: 0, mck2ui 16
4048 16:36:32.605296 best dqsien dly found for B0: ( 0, 13, 12)
4049 16:36:32.609046 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 16:36:32.611980 Total UI for P1: 0, mck2ui 16
4051 16:36:32.615678 best dqsien dly found for B1: ( 0, 13, 18)
4052 16:36:32.618935 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4053 16:36:32.625742 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4054 16:36:32.625822
4055 16:36:32.629164 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4056 16:36:32.631943 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4057 16:36:32.635329 [Gating] SW calibration Done
4058 16:36:32.635436 ==
4059 16:36:32.638892 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 16:36:32.642188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 16:36:32.642306 ==
4062 16:36:32.645810 RX Vref Scan: 0
4063 16:36:32.645922
4064 16:36:32.646027 RX Vref 0 -> 0, step: 1
4065 16:36:32.646128
4066 16:36:32.648701 RX Delay -230 -> 252, step: 16
4067 16:36:32.652157 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4068 16:36:32.658993 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4069 16:36:32.661971 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4070 16:36:32.665694 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4071 16:36:32.669509 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4072 16:36:32.675239 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4073 16:36:32.678988 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4074 16:36:32.681705 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4075 16:36:32.685806 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4076 16:36:32.689165 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4077 16:36:32.695745 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4078 16:36:32.699169 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4079 16:36:32.702078 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4080 16:36:32.705700 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4081 16:36:32.712410 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4082 16:36:32.715437 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4083 16:36:32.715845 ==
4084 16:36:32.718587 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 16:36:32.722364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 16:36:32.722747 ==
4087 16:36:32.725460 DQS Delay:
4088 16:36:32.725972 DQS0 = 0, DQS1 = 0
4089 16:36:32.726364 DQM Delay:
4090 16:36:32.728493 DQM0 = 54, DQM1 = 44
4091 16:36:32.728920 DQ Delay:
4092 16:36:32.732134 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4093 16:36:32.735033 DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =65
4094 16:36:32.738807 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4095 16:36:32.741594 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4096 16:36:32.741846
4097 16:36:32.742059
4098 16:36:32.742238 ==
4099 16:36:32.745405 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 16:36:32.751915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 16:36:32.752113 ==
4102 16:36:32.752275
4103 16:36:32.752437
4104 16:36:32.752587 TX Vref Scan disable
4105 16:36:32.755273 == TX Byte 0 ==
4106 16:36:32.758705 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4107 16:36:32.765253 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4108 16:36:32.765445 == TX Byte 1 ==
4109 16:36:32.768774 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4110 16:36:32.774925 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4111 16:36:32.775084 ==
4112 16:36:32.778447 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 16:36:32.781437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 16:36:32.781570 ==
4115 16:36:32.781661
4116 16:36:32.781745
4117 16:36:32.785125 TX Vref Scan disable
4118 16:36:32.788223 == TX Byte 0 ==
4119 16:36:32.792104 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4120 16:36:32.795047 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4121 16:36:32.798661 == TX Byte 1 ==
4122 16:36:32.801459 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4123 16:36:32.804900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4124 16:36:32.804977
4125 16:36:32.805037 [DATLAT]
4126 16:36:32.808281 Freq=600, CH0 RK0
4127 16:36:32.808361
4128 16:36:32.808421 DATLAT Default: 0x9
4129 16:36:32.811559 0, 0xFFFF, sum = 0
4130 16:36:32.811640 1, 0xFFFF, sum = 0
4131 16:36:32.815117 2, 0xFFFF, sum = 0
4132 16:36:32.817929 3, 0xFFFF, sum = 0
4133 16:36:32.818012 4, 0xFFFF, sum = 0
4134 16:36:32.821880 5, 0xFFFF, sum = 0
4135 16:36:32.821962 6, 0xFFFF, sum = 0
4136 16:36:32.824917 7, 0xFFFF, sum = 0
4137 16:36:32.824998 8, 0x0, sum = 1
4138 16:36:32.825077 9, 0x0, sum = 2
4139 16:36:32.828549 10, 0x0, sum = 3
4140 16:36:32.828621 11, 0x0, sum = 4
4141 16:36:32.831548 best_step = 9
4142 16:36:32.831617
4143 16:36:32.831691 ==
4144 16:36:32.835285 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 16:36:32.838287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 16:36:32.838355 ==
4147 16:36:32.841331 RX Vref Scan: 1
4148 16:36:32.841397
4149 16:36:32.841487 RX Vref 0 -> 0, step: 1
4150 16:36:32.841588
4151 16:36:32.845096 RX Delay -179 -> 252, step: 8
4152 16:36:32.845165
4153 16:36:32.848059 Set Vref, RX VrefLevel [Byte0]: 57
4154 16:36:32.851015 [Byte1]: 46
4155 16:36:32.855555
4156 16:36:32.855635 Final RX Vref Byte 0 = 57 to rank0
4157 16:36:32.858655 Final RX Vref Byte 1 = 46 to rank0
4158 16:36:32.862493 Final RX Vref Byte 0 = 57 to rank1
4159 16:36:32.866161 Final RX Vref Byte 1 = 46 to rank1==
4160 16:36:32.869129 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 16:36:32.875604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 16:36:32.875676 ==
4163 16:36:32.875752 DQS Delay:
4164 16:36:32.875856 DQS0 = 0, DQS1 = 0
4165 16:36:32.878951 DQM Delay:
4166 16:36:32.879024 DQM0 = 53, DQM1 = 46
4167 16:36:32.882312 DQ Delay:
4168 16:36:32.885486 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4169 16:36:32.888793 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4170 16:36:32.892047 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4171 16:36:32.895263 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4172 16:36:32.895342
4173 16:36:32.895424
4174 16:36:32.902030 [DQSOSCAuto] RK0, (LSB)MR18= 0x7467, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4175 16:36:32.905429 CH0 RK0: MR19=808, MR18=7467
4176 16:36:32.912220 CH0_RK0: MR19=0x808, MR18=0x7467, DQSOSC=388, MR23=63, INC=174, DEC=116
4177 16:36:32.912299
4178 16:36:32.915238 ----->DramcWriteLeveling(PI) begin...
4179 16:36:32.915322 ==
4180 16:36:32.918907 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 16:36:32.921700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 16:36:32.921779 ==
4183 16:36:32.924996 Write leveling (Byte 0): 34 => 34
4184 16:36:32.928490 Write leveling (Byte 1): 31 => 31
4185 16:36:32.931865 DramcWriteLeveling(PI) end<-----
4186 16:36:32.931941
4187 16:36:32.931999 ==
4188 16:36:32.935159 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 16:36:32.938851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 16:36:32.938918 ==
4191 16:36:32.941799 [Gating] SW mode calibration
4192 16:36:32.948581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4193 16:36:32.955445 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4194 16:36:32.958436 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4195 16:36:32.962167 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 16:36:32.968939 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 16:36:32.971851 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
4198 16:36:32.974979 0 9 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
4199 16:36:32.981696 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 16:36:32.985322 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 16:36:32.988475 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 16:36:32.995282 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 16:36:32.998312 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 16:36:33.001919 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 16:36:33.008079 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4206 16:36:33.011642 0 10 16 | B1->B0 | 4242 4343 | 0 0 | (0 0) (0 0)
4207 16:36:33.015036 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 16:36:33.021230 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 16:36:33.024496 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 16:36:33.027993 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 16:36:33.034929 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 16:36:33.037813 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 16:36:33.041164 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4214 16:36:33.048163 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4215 16:36:33.051452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 16:36:33.054863 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 16:36:33.061002 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 16:36:33.064914 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 16:36:33.067917 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 16:36:33.074536 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 16:36:33.077480 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 16:36:33.081284 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 16:36:33.088275 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 16:36:33.091248 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 16:36:33.094959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 16:36:33.100842 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 16:36:33.104605 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 16:36:33.107565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 16:36:33.114640 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4230 16:36:33.117480 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 16:36:33.121188 Total UI for P1: 0, mck2ui 16
4232 16:36:33.124070 best dqsien dly found for B0: ( 0, 13, 12)
4233 16:36:33.127802 Total UI for P1: 0, mck2ui 16
4234 16:36:33.130832 best dqsien dly found for B1: ( 0, 13, 14)
4235 16:36:33.134574 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4236 16:36:33.137395 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4237 16:36:33.137497
4238 16:36:33.140729 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4239 16:36:33.144291 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4240 16:36:33.147236 [Gating] SW calibration Done
4241 16:36:33.147318 ==
4242 16:36:33.150787 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 16:36:33.154333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 16:36:33.157102 ==
4245 16:36:33.157182 RX Vref Scan: 0
4246 16:36:33.157289
4247 16:36:33.160553 RX Vref 0 -> 0, step: 1
4248 16:36:33.160631
4249 16:36:33.163933 RX Delay -230 -> 252, step: 16
4250 16:36:33.167182 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4251 16:36:33.170371 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4252 16:36:33.173659 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4253 16:36:33.180337 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4254 16:36:33.183987 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4255 16:36:33.187030 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4256 16:36:33.190060 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4257 16:36:33.193722 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4258 16:36:33.200305 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4259 16:36:33.203271 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4260 16:36:33.207103 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4261 16:36:33.210140 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4262 16:36:33.216866 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4263 16:36:33.220494 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4264 16:36:33.223568 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4265 16:36:33.227194 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4266 16:36:33.227284 ==
4267 16:36:33.230118 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 16:36:33.236692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 16:36:33.236776 ==
4270 16:36:33.236837 DQS Delay:
4271 16:36:33.236893 DQS0 = 0, DQS1 = 0
4272 16:36:33.240355 DQM Delay:
4273 16:36:33.240432 DQM0 = 53, DQM1 = 43
4274 16:36:33.243316 DQ Delay:
4275 16:36:33.246899 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4276 16:36:33.250404 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4277 16:36:33.253879 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4278 16:36:33.256854 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4279 16:36:33.256939
4280 16:36:33.257018
4281 16:36:33.257093 ==
4282 16:36:33.260370 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 16:36:33.263267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 16:36:33.263346 ==
4285 16:36:33.263424
4286 16:36:33.263516
4287 16:36:33.266932 TX Vref Scan disable
4288 16:36:33.267035 == TX Byte 0 ==
4289 16:36:33.273540 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4290 16:36:33.276396 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4291 16:36:33.276471 == TX Byte 1 ==
4292 16:36:33.283352 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4293 16:36:33.286833 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4294 16:36:33.286904 ==
4295 16:36:33.290405 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 16:36:33.293380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 16:36:33.293448 ==
4298 16:36:33.296466
4299 16:36:33.296613
4300 16:36:33.296720 TX Vref Scan disable
4301 16:36:33.300081 == TX Byte 0 ==
4302 16:36:33.303774 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4303 16:36:33.309819 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4304 16:36:33.309893 == TX Byte 1 ==
4305 16:36:33.313668 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4306 16:36:33.319839 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4307 16:36:33.319917
4308 16:36:33.319977 [DATLAT]
4309 16:36:33.320032 Freq=600, CH0 RK1
4310 16:36:33.320084
4311 16:36:33.323589 DATLAT Default: 0x9
4312 16:36:33.323665 0, 0xFFFF, sum = 0
4313 16:36:33.326636 1, 0xFFFF, sum = 0
4314 16:36:33.326713 2, 0xFFFF, sum = 0
4315 16:36:33.330248 3, 0xFFFF, sum = 0
4316 16:36:33.333209 4, 0xFFFF, sum = 0
4317 16:36:33.333286 5, 0xFFFF, sum = 0
4318 16:36:33.336754 6, 0xFFFF, sum = 0
4319 16:36:33.336834 7, 0xFFFF, sum = 0
4320 16:36:33.340394 8, 0x0, sum = 1
4321 16:36:33.340472 9, 0x0, sum = 2
4322 16:36:33.340532 10, 0x0, sum = 3
4323 16:36:33.343397 11, 0x0, sum = 4
4324 16:36:33.343474 best_step = 9
4325 16:36:33.343532
4326 16:36:33.343586 ==
4327 16:36:33.346404 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 16:36:33.353052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 16:36:33.353160 ==
4330 16:36:33.353253 RX Vref Scan: 0
4331 16:36:33.353344
4332 16:36:33.356579 RX Vref 0 -> 0, step: 1
4333 16:36:33.356659
4334 16:36:33.360074 RX Delay -163 -> 252, step: 8
4335 16:36:33.363408 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4336 16:36:33.369859 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4337 16:36:33.373309 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4338 16:36:33.376035 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4339 16:36:33.379590 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4340 16:36:33.383251 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4341 16:36:33.389869 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4342 16:36:33.392770 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4343 16:36:33.396147 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4344 16:36:33.399378 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4345 16:36:33.402835 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4346 16:36:33.409877 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4347 16:36:33.412907 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4348 16:36:33.416553 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4349 16:36:33.419742 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4350 16:36:33.423498 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4351 16:36:33.426438 ==
4352 16:36:33.429432 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 16:36:33.433042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 16:36:33.433135 ==
4355 16:36:33.433217 DQS Delay:
4356 16:36:33.436049 DQS0 = 0, DQS1 = 0
4357 16:36:33.436124 DQM Delay:
4358 16:36:33.439784 DQM0 = 54, DQM1 = 45
4359 16:36:33.439884 DQ Delay:
4360 16:36:33.442736 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4361 16:36:33.446677 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4362 16:36:33.449688 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4363 16:36:33.452760 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4364 16:36:33.452857
4365 16:36:33.452947
4366 16:36:33.459616 [DQSOSCAuto] RK1, (LSB)MR18= 0x6424, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4367 16:36:33.462553 CH0 RK1: MR19=808, MR18=6424
4368 16:36:33.469026 CH0_RK1: MR19=0x808, MR18=0x6424, DQSOSC=391, MR23=63, INC=171, DEC=114
4369 16:36:33.472591 [RxdqsGatingPostProcess] freq 600
4370 16:36:33.479227 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4371 16:36:33.479338 Pre-setting of DQS Precalculation
4372 16:36:33.485974 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4373 16:36:33.486051 ==
4374 16:36:33.489541 Dram Type= 6, Freq= 0, CH_1, rank 0
4375 16:36:33.493008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 16:36:33.493110 ==
4377 16:36:33.499173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 16:36:33.505944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 16:36:33.508939 [CA 0] Center 36 (5~67) winsize 63
4380 16:36:33.512422 [CA 1] Center 36 (5~67) winsize 63
4381 16:36:33.515720 [CA 2] Center 34 (4~65) winsize 62
4382 16:36:33.518859 [CA 3] Center 34 (4~65) winsize 62
4383 16:36:33.522392 [CA 4] Center 34 (4~65) winsize 62
4384 16:36:33.525468 [CA 5] Center 33 (3~64) winsize 62
4385 16:36:33.525606
4386 16:36:33.529066 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 16:36:33.529169
4388 16:36:33.532085 [CATrainingPosCal] consider 1 rank data
4389 16:36:33.535731 u2DelayCellTimex100 = 270/100 ps
4390 16:36:33.538842 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4391 16:36:33.542595 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4392 16:36:33.545441 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 16:36:33.549309 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 16:36:33.552354 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 16:36:33.555295 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 16:36:33.559024
4397 16:36:33.561962 CA PerBit enable=1, Macro0, CA PI delay=33
4398 16:36:33.562029
4399 16:36:33.565717 [CBTSetCACLKResult] CA Dly = 33
4400 16:36:33.565791 CS Dly: 6 (0~37)
4401 16:36:33.565848 ==
4402 16:36:33.569349 Dram Type= 6, Freq= 0, CH_1, rank 1
4403 16:36:33.572438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 16:36:33.572529 ==
4405 16:36:33.579207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4406 16:36:33.585772 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4407 16:36:33.588613 [CA 0] Center 36 (6~67) winsize 62
4408 16:36:33.591948 [CA 1] Center 36 (6~67) winsize 62
4409 16:36:33.595606 [CA 2] Center 35 (4~66) winsize 63
4410 16:36:33.598772 [CA 3] Center 35 (4~66) winsize 63
4411 16:36:33.602352 [CA 4] Center 34 (4~65) winsize 62
4412 16:36:33.605216 [CA 5] Center 34 (4~65) winsize 62
4413 16:36:33.605289
4414 16:36:33.608635 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4415 16:36:33.608726
4416 16:36:33.612175 [CATrainingPosCal] consider 2 rank data
4417 16:36:33.615141 u2DelayCellTimex100 = 270/100 ps
4418 16:36:33.618805 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4419 16:36:33.622501 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4420 16:36:33.625472 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 16:36:33.629266 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4422 16:36:33.632213 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 16:36:33.638511 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4424 16:36:33.638580
4425 16:36:33.641795 CA PerBit enable=1, Macro0, CA PI delay=34
4426 16:36:33.641865
4427 16:36:33.645135 [CBTSetCACLKResult] CA Dly = 34
4428 16:36:33.645234 CS Dly: 7 (0~39)
4429 16:36:33.645317
4430 16:36:33.648970 ----->DramcWriteLeveling(PI) begin...
4431 16:36:33.649101 ==
4432 16:36:33.652155 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 16:36:33.658508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 16:36:33.658591 ==
4435 16:36:33.661994 Write leveling (Byte 0): 32 => 32
4436 16:36:33.662092 Write leveling (Byte 1): 28 => 28
4437 16:36:33.665119 DramcWriteLeveling(PI) end<-----
4438 16:36:33.665196
4439 16:36:33.665254 ==
4440 16:36:33.668789 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 16:36:33.675448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 16:36:33.675550 ==
4443 16:36:33.678405 [Gating] SW mode calibration
4444 16:36:33.685349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4445 16:36:33.688307 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4446 16:36:33.694867 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4447 16:36:33.698359 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 16:36:33.701924 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4449 16:36:33.708789 0 9 12 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
4450 16:36:33.711707 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 16:36:33.715351 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 16:36:33.721804 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 16:36:33.725152 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 16:36:33.728451 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 16:36:33.732004 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 16:36:33.738793 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 16:36:33.741660 0 10 12 | B1->B0 | 3232 3636 | 0 0 | (0 0) (0 0)
4458 16:36:33.745250 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4459 16:36:33.752016 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 16:36:33.754929 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 16:36:33.758421 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 16:36:33.764682 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 16:36:33.768129 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 16:36:33.771608 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 16:36:33.778392 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4466 16:36:33.781366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4467 16:36:33.784489 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 16:36:33.791278 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 16:36:33.795007 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 16:36:33.797968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 16:36:33.804415 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 16:36:33.808154 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 16:36:33.811089 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 16:36:33.817747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 16:36:33.821443 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 16:36:33.824500 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 16:36:33.831200 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 16:36:33.834637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 16:36:33.837725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 16:36:33.844754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4481 16:36:33.847493 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 16:36:33.851016 Total UI for P1: 0, mck2ui 16
4483 16:36:33.854532 best dqsien dly found for B0: ( 0, 13, 8)
4484 16:36:33.857653 Total UI for P1: 0, mck2ui 16
4485 16:36:33.861050 best dqsien dly found for B1: ( 0, 13, 10)
4486 16:36:33.864856 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4487 16:36:33.867805 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4488 16:36:33.867883
4489 16:36:33.871492 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4490 16:36:33.874499 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4491 16:36:33.878018 [Gating] SW calibration Done
4492 16:36:33.878099 ==
4493 16:36:33.880932 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 16:36:33.884391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 16:36:33.884475 ==
4496 16:36:33.887909 RX Vref Scan: 0
4497 16:36:33.887987
4498 16:36:33.891165 RX Vref 0 -> 0, step: 1
4499 16:36:33.891243
4500 16:36:33.891304 RX Delay -230 -> 252, step: 16
4501 16:36:33.897763 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4502 16:36:33.900759 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4503 16:36:33.904307 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4504 16:36:33.908061 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4505 16:36:33.914518 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4506 16:36:33.918168 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4507 16:36:33.921133 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4508 16:36:33.924726 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4509 16:36:33.927787 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4510 16:36:33.934387 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4511 16:36:33.937358 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4512 16:36:33.941228 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4513 16:36:33.944123 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4514 16:36:33.950779 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4515 16:36:33.954198 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4516 16:36:33.957231 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4517 16:36:33.957333 ==
4518 16:36:33.960701 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 16:36:33.964311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 16:36:33.964411 ==
4521 16:36:33.967706 DQS Delay:
4522 16:36:33.967797 DQS0 = 0, DQS1 = 0
4523 16:36:33.970534 DQM Delay:
4524 16:36:33.970631 DQM0 = 51, DQM1 = 49
4525 16:36:33.970716 DQ Delay:
4526 16:36:33.974314 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4527 16:36:33.977275 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41
4528 16:36:33.980952 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4529 16:36:33.983832 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =57
4530 16:36:33.983938
4531 16:36:33.984031
4532 16:36:33.987488 ==
4533 16:36:33.987600 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 16:36:33.994348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 16:36:33.994454 ==
4536 16:36:33.994539
4537 16:36:33.994627
4538 16:36:33.997319 TX Vref Scan disable
4539 16:36:33.997416 == TX Byte 0 ==
4540 16:36:34.000268 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4541 16:36:34.007310 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4542 16:36:34.007387 == TX Byte 1 ==
4543 16:36:34.010739 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4544 16:36:34.017517 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4545 16:36:34.017636 ==
4546 16:36:34.020531 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 16:36:34.024024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 16:36:34.024101 ==
4549 16:36:34.024161
4550 16:36:34.024216
4551 16:36:34.027631 TX Vref Scan disable
4552 16:36:34.030729 == TX Byte 0 ==
4553 16:36:34.034394 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4554 16:36:34.037433 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4555 16:36:34.040492 == TX Byte 1 ==
4556 16:36:34.044290 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4557 16:36:34.047311 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4558 16:36:34.047390
4559 16:36:34.050378 [DATLAT]
4560 16:36:34.050455 Freq=600, CH1 RK0
4561 16:36:34.050516
4562 16:36:34.054058 DATLAT Default: 0x9
4563 16:36:34.054135 0, 0xFFFF, sum = 0
4564 16:36:34.056950 1, 0xFFFF, sum = 0
4565 16:36:34.057029 2, 0xFFFF, sum = 0
4566 16:36:34.060466 3, 0xFFFF, sum = 0
4567 16:36:34.060595 4, 0xFFFF, sum = 0
4568 16:36:34.064082 5, 0xFFFF, sum = 0
4569 16:36:34.064162 6, 0xFFFF, sum = 0
4570 16:36:34.066890 7, 0xFFFF, sum = 0
4571 16:36:34.066969 8, 0x0, sum = 1
4572 16:36:34.070522 9, 0x0, sum = 2
4573 16:36:34.070600 10, 0x0, sum = 3
4574 16:36:34.074126 11, 0x0, sum = 4
4575 16:36:34.074205 best_step = 9
4576 16:36:34.074266
4577 16:36:34.074322 ==
4578 16:36:34.076919 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 16:36:34.080512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 16:36:34.083421 ==
4581 16:36:34.083497 RX Vref Scan: 1
4582 16:36:34.083556
4583 16:36:34.087076 RX Vref 0 -> 0, step: 1
4584 16:36:34.087153
4585 16:36:34.090053 RX Delay -163 -> 252, step: 8
4586 16:36:34.090128
4587 16:36:34.093921 Set Vref, RX VrefLevel [Byte0]: 55
4588 16:36:34.096793 [Byte1]: 53
4589 16:36:34.096870
4590 16:36:34.099841 Final RX Vref Byte 0 = 55 to rank0
4591 16:36:34.103594 Final RX Vref Byte 1 = 53 to rank0
4592 16:36:34.106519 Final RX Vref Byte 0 = 55 to rank1
4593 16:36:34.110103 Final RX Vref Byte 1 = 53 to rank1==
4594 16:36:34.113046 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 16:36:34.116902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 16:36:34.116978 ==
4597 16:36:34.119836 DQS Delay:
4598 16:36:34.119912 DQS0 = 0, DQS1 = 0
4599 16:36:34.119971 DQM Delay:
4600 16:36:34.123400 DQM0 = 48, DQM1 = 45
4601 16:36:34.123477 DQ Delay:
4602 16:36:34.126124 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4603 16:36:34.129510 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4604 16:36:34.132864 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4605 16:36:34.136176 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4606 16:36:34.136253
4607 16:36:34.136312
4608 16:36:34.146684 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4609 16:36:34.146763 CH1 RK0: MR19=808, MR18=4B71
4610 16:36:34.153376 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4611 16:36:34.153453
4612 16:36:34.156423 ----->DramcWriteLeveling(PI) begin...
4613 16:36:34.159423 ==
4614 16:36:34.159500 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 16:36:34.165990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 16:36:34.166068 ==
4617 16:36:34.169798 Write leveling (Byte 0): 29 => 29
4618 16:36:34.172843 Write leveling (Byte 1): 29 => 29
4619 16:36:34.176332 DramcWriteLeveling(PI) end<-----
4620 16:36:34.176445
4621 16:36:34.176505 ==
4622 16:36:34.179773 Dram Type= 6, Freq= 0, CH_1, rank 1
4623 16:36:34.182685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 16:36:34.182763 ==
4625 16:36:34.186217 [Gating] SW mode calibration
4626 16:36:34.192645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4627 16:36:34.196302 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4628 16:36:34.202928 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 16:36:34.205956 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4630 16:36:34.209097 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4631 16:36:34.215825 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
4632 16:36:34.219601 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 16:36:34.222631 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 16:36:34.229418 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 16:36:34.232431 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 16:36:34.236013 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 16:36:34.242477 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 16:36:34.246116 0 10 8 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
4639 16:36:34.248921 0 10 12 | B1->B0 | 3838 3939 | 0 1 | (0 0) (0 0)
4640 16:36:34.255494 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 16:36:34.258881 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 16:36:34.262650 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 16:36:34.268680 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 16:36:34.272418 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 16:36:34.275247 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 16:36:34.282181 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 16:36:34.285873 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4648 16:36:34.288805 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 16:36:34.295463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 16:36:34.299119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 16:36:34.301936 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 16:36:34.308673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 16:36:34.312323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 16:36:34.315342 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 16:36:34.321932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 16:36:34.325796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 16:36:34.328843 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 16:36:34.335683 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 16:36:34.338738 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 16:36:34.342324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 16:36:34.345197 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 16:36:34.351830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4663 16:36:34.355658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 16:36:34.358564 Total UI for P1: 0, mck2ui 16
4665 16:36:34.362278 best dqsien dly found for B0: ( 0, 13, 8)
4666 16:36:34.365193 Total UI for P1: 0, mck2ui 16
4667 16:36:34.368516 best dqsien dly found for B1: ( 0, 13, 8)
4668 16:36:34.371915 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4669 16:36:34.375192 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4670 16:36:34.375271
4671 16:36:34.378630 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4672 16:36:34.382128 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4673 16:36:34.384930 [Gating] SW calibration Done
4674 16:36:34.385005 ==
4675 16:36:34.388750 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 16:36:34.395211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 16:36:34.395291 ==
4678 16:36:34.395351 RX Vref Scan: 0
4679 16:36:34.395406
4680 16:36:34.398214 RX Vref 0 -> 0, step: 1
4681 16:36:34.398290
4682 16:36:34.402104 RX Delay -230 -> 252, step: 16
4683 16:36:34.405128 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4684 16:36:34.408184 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4685 16:36:34.411887 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4686 16:36:34.418689 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4687 16:36:34.421757 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4688 16:36:34.425401 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4689 16:36:34.428453 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4690 16:36:34.431671 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4691 16:36:34.438454 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4692 16:36:34.441409 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4693 16:36:34.445206 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4694 16:36:34.448235 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4695 16:36:34.454687 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4696 16:36:34.458549 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4697 16:36:34.461788 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4698 16:36:34.465002 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4699 16:36:34.465437 ==
4700 16:36:34.468960 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 16:36:34.474898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 16:36:34.475364 ==
4703 16:36:34.475740 DQS Delay:
4704 16:36:34.478529 DQS0 = 0, DQS1 = 0
4705 16:36:34.479081 DQM Delay:
4706 16:36:34.481523 DQM0 = 50, DQM1 = 47
4707 16:36:34.482033 DQ Delay:
4708 16:36:34.485314 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4709 16:36:34.488090 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4710 16:36:34.491698 DQ8 =33, DQ9 =41, DQ10 =41, DQ11 =41
4711 16:36:34.494934 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4712 16:36:34.495326
4713 16:36:34.495629
4714 16:36:34.495906 ==
4715 16:36:34.498507 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 16:36:34.501924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 16:36:34.502362 ==
4718 16:36:34.502667
4719 16:36:34.502949
4720 16:36:34.505350 TX Vref Scan disable
4721 16:36:34.508271 == TX Byte 0 ==
4722 16:36:34.511797 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4723 16:36:34.514796 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4724 16:36:34.518443 == TX Byte 1 ==
4725 16:36:34.521320 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4726 16:36:34.524865 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4727 16:36:34.525285 ==
4728 16:36:34.528605 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 16:36:34.531602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 16:36:34.534508 ==
4731 16:36:34.534977
4732 16:36:34.535286
4733 16:36:34.535569 TX Vref Scan disable
4734 16:36:34.539039 == TX Byte 0 ==
4735 16:36:34.542102 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4736 16:36:34.548830 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4737 16:36:34.549224 == TX Byte 1 ==
4738 16:36:34.551934 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4739 16:36:34.558541 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4740 16:36:34.558933
4741 16:36:34.559234 [DATLAT]
4742 16:36:34.559514 Freq=600, CH1 RK1
4743 16:36:34.559791
4744 16:36:34.562159 DATLAT Default: 0x9
4745 16:36:34.562546 0, 0xFFFF, sum = 0
4746 16:36:34.565099 1, 0xFFFF, sum = 0
4747 16:36:34.565930 2, 0xFFFF, sum = 0
4748 16:36:34.568793 3, 0xFFFF, sum = 0
4749 16:36:34.571872 4, 0xFFFF, sum = 0
4750 16:36:34.572284 5, 0xFFFF, sum = 0
4751 16:36:34.575604 6, 0xFFFF, sum = 0
4752 16:36:34.576081 7, 0xFFFF, sum = 0
4753 16:36:34.578697 8, 0x0, sum = 1
4754 16:36:34.579215 9, 0x0, sum = 2
4755 16:36:34.579680 10, 0x0, sum = 3
4756 16:36:34.581668 11, 0x0, sum = 4
4757 16:36:34.582071 best_step = 9
4758 16:36:34.582411
4759 16:36:34.582774 ==
4760 16:36:34.585213 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 16:36:34.591629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 16:36:34.591989 ==
4763 16:36:34.592304 RX Vref Scan: 0
4764 16:36:34.592598
4765 16:36:34.594610 RX Vref 0 -> 0, step: 1
4766 16:36:34.594889
4767 16:36:34.598348 RX Delay -163 -> 252, step: 8
4768 16:36:34.601381 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4769 16:36:34.608512 iDelay=205, Bit 1, Center 48 (-91 ~ 188) 280
4770 16:36:34.611395 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4771 16:36:34.614722 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4772 16:36:34.618337 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4773 16:36:34.621342 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4774 16:36:34.624809 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4775 16:36:34.631607 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4776 16:36:34.635220 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4777 16:36:34.637992 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4778 16:36:34.641363 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4779 16:36:34.648125 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4780 16:36:34.651855 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4781 16:36:34.654831 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4782 16:36:34.658618 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4783 16:36:34.661610 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4784 16:36:34.665344 ==
4785 16:36:34.665855 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 16:36:34.672052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 16:36:34.672447 ==
4788 16:36:34.672750 DQS Delay:
4789 16:36:34.675099 DQS0 = 0, DQS1 = 0
4790 16:36:34.675490 DQM Delay:
4791 16:36:34.678797 DQM0 = 49, DQM1 = 46
4792 16:36:34.679329 DQ Delay:
4793 16:36:34.681802 DQ0 =52, DQ1 =48, DQ2 =36, DQ3 =44
4794 16:36:34.684779 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4795 16:36:34.688628 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4796 16:36:34.691689 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4797 16:36:34.692083
4798 16:36:34.692387
4799 16:36:34.698536 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4800 16:36:34.701512 CH1 RK1: MR19=808, MR18=6B21
4801 16:36:34.708225 CH1_RK1: MR19=0x808, MR18=0x6B21, DQSOSC=389, MR23=63, INC=173, DEC=115
4802 16:36:34.711240 [RxdqsGatingPostProcess] freq 600
4803 16:36:34.718398 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4804 16:36:34.718697 Pre-setting of DQS Precalculation
4805 16:36:34.724829 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4806 16:36:34.731464 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4807 16:36:34.737856 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4808 16:36:34.737998
4809 16:36:34.738117
4810 16:36:34.741300 [Calibration Summary] 1200 Mbps
4811 16:36:34.741429 CH 0, Rank 0
4812 16:36:34.744898 SW Impedance : PASS
4813 16:36:34.748439 DUTY Scan : NO K
4814 16:36:34.748646 ZQ Calibration : PASS
4815 16:36:34.751135 Jitter Meter : NO K
4816 16:36:34.754439 CBT Training : PASS
4817 16:36:34.754581 Write leveling : PASS
4818 16:36:34.757888 RX DQS gating : PASS
4819 16:36:34.761235 RX DQ/DQS(RDDQC) : PASS
4820 16:36:34.761311 TX DQ/DQS : PASS
4821 16:36:34.764181 RX DATLAT : PASS
4822 16:36:34.767911 RX DQ/DQS(Engine): PASS
4823 16:36:34.767979 TX OE : NO K
4824 16:36:34.770942 All Pass.
4825 16:36:34.771008
4826 16:36:34.771066 CH 0, Rank 1
4827 16:36:34.774564 SW Impedance : PASS
4828 16:36:34.774653 DUTY Scan : NO K
4829 16:36:34.777450 ZQ Calibration : PASS
4830 16:36:34.781121 Jitter Meter : NO K
4831 16:36:34.781197 CBT Training : PASS
4832 16:36:34.784125 Write leveling : PASS
4833 16:36:34.784229 RX DQS gating : PASS
4834 16:36:34.787892 RX DQ/DQS(RDDQC) : PASS
4835 16:36:34.790845 TX DQ/DQS : PASS
4836 16:36:34.790909 RX DATLAT : PASS
4837 16:36:34.794593 RX DQ/DQS(Engine): PASS
4838 16:36:34.797387 TX OE : NO K
4839 16:36:34.797455 All Pass.
4840 16:36:34.797511
4841 16:36:34.797602 CH 1, Rank 0
4842 16:36:34.801164 SW Impedance : PASS
4843 16:36:34.803985 DUTY Scan : NO K
4844 16:36:34.804065 ZQ Calibration : PASS
4845 16:36:34.807485 Jitter Meter : NO K
4846 16:36:34.811187 CBT Training : PASS
4847 16:36:34.811268 Write leveling : PASS
4848 16:36:34.814214 RX DQS gating : PASS
4849 16:36:34.817206 RX DQ/DQS(RDDQC) : PASS
4850 16:36:34.817277 TX DQ/DQS : PASS
4851 16:36:34.821028 RX DATLAT : PASS
4852 16:36:34.823918 RX DQ/DQS(Engine): PASS
4853 16:36:34.823990 TX OE : NO K
4854 16:36:34.827476 All Pass.
4855 16:36:34.827581
4856 16:36:34.827642 CH 1, Rank 1
4857 16:36:34.831184 SW Impedance : PASS
4858 16:36:34.831281 DUTY Scan : NO K
4859 16:36:34.834211 ZQ Calibration : PASS
4860 16:36:34.837142 Jitter Meter : NO K
4861 16:36:34.837230 CBT Training : PASS
4862 16:36:34.840920 Write leveling : PASS
4863 16:36:34.840998 RX DQS gating : PASS
4864 16:36:34.843811 RX DQ/DQS(RDDQC) : PASS
4865 16:36:34.847470 TX DQ/DQS : PASS
4866 16:36:34.847585 RX DATLAT : PASS
4867 16:36:34.850608 RX DQ/DQS(Engine): PASS
4868 16:36:34.854328 TX OE : NO K
4869 16:36:34.854406 All Pass.
4870 16:36:34.854465
4871 16:36:34.857246 DramC Write-DBI off
4872 16:36:34.857326 PER_BANK_REFRESH: Hybrid Mode
4873 16:36:34.860864 TX_TRACKING: ON
4874 16:36:34.867207 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4875 16:36:34.874039 [FAST_K] Save calibration result to emmc
4876 16:36:34.877464 dramc_set_vcore_voltage set vcore to 662500
4877 16:36:34.877543 Read voltage for 933, 3
4878 16:36:34.881016 Vio18 = 0
4879 16:36:34.881092 Vcore = 662500
4880 16:36:34.881154 Vdram = 0
4881 16:36:34.884100 Vddq = 0
4882 16:36:34.884173 Vmddr = 0
4883 16:36:34.887050 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4884 16:36:34.893804 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4885 16:36:34.897480 MEM_TYPE=3, freq_sel=17
4886 16:36:34.900537 sv_algorithm_assistance_LP4_1600
4887 16:36:34.903582 ============ PULL DRAM RESETB DOWN ============
4888 16:36:34.907135 ========== PULL DRAM RESETB DOWN end =========
4889 16:36:34.913690 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4890 16:36:34.917199 ===================================
4891 16:36:34.917272 LPDDR4 DRAM CONFIGURATION
4892 16:36:34.920107 ===================================
4893 16:36:34.924017 EX_ROW_EN[0] = 0x0
4894 16:36:34.924093 EX_ROW_EN[1] = 0x0
4895 16:36:34.926934 LP4Y_EN = 0x0
4896 16:36:34.927005 WORK_FSP = 0x0
4897 16:36:34.930769 WL = 0x3
4898 16:36:34.933487 RL = 0x3
4899 16:36:34.933567 BL = 0x2
4900 16:36:34.937196 RPST = 0x0
4901 16:36:34.937264 RD_PRE = 0x0
4902 16:36:34.940192 WR_PRE = 0x1
4903 16:36:34.940261 WR_PST = 0x0
4904 16:36:34.943200 DBI_WR = 0x0
4905 16:36:34.943269 DBI_RD = 0x0
4906 16:36:34.946932 OTF = 0x1
4907 16:36:34.950500 ===================================
4908 16:36:34.953467 ===================================
4909 16:36:34.953536 ANA top config
4910 16:36:34.957041 ===================================
4911 16:36:34.960189 DLL_ASYNC_EN = 0
4912 16:36:34.963254 ALL_SLAVE_EN = 1
4913 16:36:34.963330 NEW_RANK_MODE = 1
4914 16:36:34.967063 DLL_IDLE_MODE = 1
4915 16:36:34.970097 LP45_APHY_COMB_EN = 1
4916 16:36:34.973151 TX_ODT_DIS = 1
4917 16:36:34.976846 NEW_8X_MODE = 1
4918 16:36:34.980311 ===================================
4919 16:36:34.983184 ===================================
4920 16:36:34.983264 data_rate = 1866
4921 16:36:34.986676 CKR = 1
4922 16:36:34.990053 DQ_P2S_RATIO = 8
4923 16:36:34.993582 ===================================
4924 16:36:34.996642 CA_P2S_RATIO = 8
4925 16:36:35.000012 DQ_CA_OPEN = 0
4926 16:36:35.003765 DQ_SEMI_OPEN = 0
4927 16:36:35.003852 CA_SEMI_OPEN = 0
4928 16:36:35.006677 CA_FULL_RATE = 0
4929 16:36:35.009677 DQ_CKDIV4_EN = 1
4930 16:36:35.013379 CA_CKDIV4_EN = 1
4931 16:36:35.016398 CA_PREDIV_EN = 0
4932 16:36:35.019924 PH8_DLY = 0
4933 16:36:35.020037 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4934 16:36:35.022748 DQ_AAMCK_DIV = 4
4935 16:36:35.026623 CA_AAMCK_DIV = 4
4936 16:36:35.029485 CA_ADMCK_DIV = 4
4937 16:36:35.033352 DQ_TRACK_CA_EN = 0
4938 16:36:35.036465 CA_PICK = 933
4939 16:36:35.040058 CA_MCKIO = 933
4940 16:36:35.040246 MCKIO_SEMI = 0
4941 16:36:35.043037 PLL_FREQ = 3732
4942 16:36:35.046487 DQ_UI_PI_RATIO = 32
4943 16:36:35.049635 CA_UI_PI_RATIO = 0
4944 16:36:35.053499 ===================================
4945 16:36:35.056447 ===================================
4946 16:36:35.060182 memory_type:LPDDR4
4947 16:36:35.060569 GP_NUM : 10
4948 16:36:35.062921 SRAM_EN : 1
4949 16:36:35.063337 MD32_EN : 0
4950 16:36:35.066458 ===================================
4951 16:36:35.069988 [ANA_INIT] >>>>>>>>>>>>>>
4952 16:36:35.073071 <<<<<< [CONFIGURE PHASE]: ANA_TX
4953 16:36:35.076402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4954 16:36:35.079829 ===================================
4955 16:36:35.082886 data_rate = 1866,PCW = 0X8f00
4956 16:36:35.086720 ===================================
4957 16:36:35.089725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4958 16:36:35.096757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 16:36:35.099634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4960 16:36:35.106664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4961 16:36:35.109662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4962 16:36:35.113149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4963 16:36:35.113431 [ANA_INIT] flow start
4964 16:36:35.116339 [ANA_INIT] PLL >>>>>>>>
4965 16:36:35.119588 [ANA_INIT] PLL <<<<<<<<
4966 16:36:35.119798 [ANA_INIT] MIDPI >>>>>>>>
4967 16:36:35.123054 [ANA_INIT] MIDPI <<<<<<<<
4968 16:36:35.125936 [ANA_INIT] DLL >>>>>>>>
4969 16:36:35.126104 [ANA_INIT] flow end
4970 16:36:35.132915 ============ LP4 DIFF to SE enter ============
4971 16:36:35.136094 ============ LP4 DIFF to SE exit ============
4972 16:36:35.136169 [ANA_INIT] <<<<<<<<<<<<<
4973 16:36:35.139144 [Flow] Enable top DCM control >>>>>
4974 16:36:35.142847 [Flow] Enable top DCM control <<<<<
4975 16:36:35.145910 Enable DLL master slave shuffle
4976 16:36:35.152792 ==============================================================
4977 16:36:35.155926 Gating Mode config
4978 16:36:35.159596 ==============================================================
4979 16:36:35.162621 Config description:
4980 16:36:35.173091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4981 16:36:35.179553 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4982 16:36:35.182554 SELPH_MODE 0: By rank 1: By Phase
4983 16:36:35.189338 ==============================================================
4984 16:36:35.192466 GAT_TRACK_EN = 1
4985 16:36:35.195849 RX_GATING_MODE = 2
4986 16:36:35.199636 RX_GATING_TRACK_MODE = 2
4987 16:36:35.199704 SELPH_MODE = 1
4988 16:36:35.202559 PICG_EARLY_EN = 1
4989 16:36:35.205783 VALID_LAT_VALUE = 1
4990 16:36:35.212377 ==============================================================
4991 16:36:35.216045 Enter into Gating configuration >>>>
4992 16:36:35.219000 Exit from Gating configuration <<<<
4993 16:36:35.222628 Enter into DVFS_PRE_config >>>>>
4994 16:36:35.232248 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4995 16:36:35.235721 Exit from DVFS_PRE_config <<<<<
4996 16:36:35.238792 Enter into PICG configuration >>>>
4997 16:36:35.242053 Exit from PICG configuration <<<<
4998 16:36:35.245762 [RX_INPUT] configuration >>>>>
4999 16:36:35.248537 [RX_INPUT] configuration <<<<<
5000 16:36:35.252353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5001 16:36:35.259021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5002 16:36:35.265847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 16:36:35.271825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 16:36:35.279051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5005 16:36:35.281759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5006 16:36:35.288443 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5007 16:36:35.292164 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5008 16:36:35.295121 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5009 16:36:35.298962 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5010 16:36:35.305300 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5011 16:36:35.308311 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 16:36:35.312180 ===================================
5013 16:36:35.314995 LPDDR4 DRAM CONFIGURATION
5014 16:36:35.318679 ===================================
5015 16:36:35.318748 EX_ROW_EN[0] = 0x0
5016 16:36:35.321508 EX_ROW_EN[1] = 0x0
5017 16:36:35.321645 LP4Y_EN = 0x0
5018 16:36:35.325290 WORK_FSP = 0x0
5019 16:36:35.325414 WL = 0x3
5020 16:36:35.328229 RL = 0x3
5021 16:36:35.328297 BL = 0x2
5022 16:36:35.331938 RPST = 0x0
5023 16:36:35.332004 RD_PRE = 0x0
5024 16:36:35.334888 WR_PRE = 0x1
5025 16:36:35.334954 WR_PST = 0x0
5026 16:36:35.338630 DBI_WR = 0x0
5027 16:36:35.338721 DBI_RD = 0x0
5028 16:36:35.341727 OTF = 0x1
5029 16:36:35.345374 ===================================
5030 16:36:35.348301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5031 16:36:35.351673 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5032 16:36:35.358282 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 16:36:35.361542 ===================================
5034 16:36:35.364781 LPDDR4 DRAM CONFIGURATION
5035 16:36:35.364880 ===================================
5036 16:36:35.368196 EX_ROW_EN[0] = 0x10
5037 16:36:35.371607 EX_ROW_EN[1] = 0x0
5038 16:36:35.371711 LP4Y_EN = 0x0
5039 16:36:35.375023 WORK_FSP = 0x0
5040 16:36:35.375125 WL = 0x3
5041 16:36:35.378581 RL = 0x3
5042 16:36:35.378655 BL = 0x2
5043 16:36:35.381500 RPST = 0x0
5044 16:36:35.381613 RD_PRE = 0x0
5045 16:36:35.385228 WR_PRE = 0x1
5046 16:36:35.385303 WR_PST = 0x0
5047 16:36:35.388113 DBI_WR = 0x0
5048 16:36:35.388181 DBI_RD = 0x0
5049 16:36:35.392064 OTF = 0x1
5050 16:36:35.394931 ===================================
5051 16:36:35.401735 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5052 16:36:35.404709 nWR fixed to 30
5053 16:36:35.408280 [ModeRegInit_LP4] CH0 RK0
5054 16:36:35.408387 [ModeRegInit_LP4] CH0 RK1
5055 16:36:35.411146 [ModeRegInit_LP4] CH1 RK0
5056 16:36:35.414944 [ModeRegInit_LP4] CH1 RK1
5057 16:36:35.415061 match AC timing 9
5058 16:36:35.421452 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5059 16:36:35.424483 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5060 16:36:35.428292 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5061 16:36:35.434324 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5062 16:36:35.438049 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5063 16:36:35.438281 ==
5064 16:36:35.441113 Dram Type= 6, Freq= 0, CH_0, rank 0
5065 16:36:35.444996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 16:36:35.445329 ==
5067 16:36:35.451398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 16:36:35.458170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5069 16:36:35.461303 [CA 0] Center 37 (6~68) winsize 63
5070 16:36:35.464807 [CA 1] Center 37 (6~68) winsize 63
5071 16:36:35.467649 [CA 2] Center 34 (4~65) winsize 62
5072 16:36:35.471162 [CA 3] Center 33 (3~64) winsize 62
5073 16:36:35.474676 [CA 4] Center 33 (3~64) winsize 62
5074 16:36:35.477455 [CA 5] Center 32 (2~62) winsize 61
5075 16:36:35.477928
5076 16:36:35.480925 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5077 16:36:35.481520
5078 16:36:35.484196 [CATrainingPosCal] consider 1 rank data
5079 16:36:35.487555 u2DelayCellTimex100 = 270/100 ps
5080 16:36:35.490923 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5081 16:36:35.494311 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5082 16:36:35.497493 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5083 16:36:35.501178 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5084 16:36:35.503720 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5085 16:36:35.510433 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5086 16:36:35.510623
5087 16:36:35.514264 CA PerBit enable=1, Macro0, CA PI delay=32
5088 16:36:35.514407
5089 16:36:35.517077 [CBTSetCACLKResult] CA Dly = 32
5090 16:36:35.517264 CS Dly: 5 (0~36)
5091 16:36:35.517380 ==
5092 16:36:35.520800 Dram Type= 6, Freq= 0, CH_0, rank 1
5093 16:36:35.523734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 16:36:35.527345 ==
5095 16:36:35.530442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 16:36:35.537020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5097 16:36:35.540827 [CA 0] Center 37 (7~67) winsize 61
5098 16:36:35.543706 [CA 1] Center 37 (7~68) winsize 62
5099 16:36:35.546886 [CA 2] Center 34 (3~65) winsize 63
5100 16:36:35.550648 [CA 3] Center 34 (3~65) winsize 63
5101 16:36:35.553581 [CA 4] Center 32 (2~63) winsize 62
5102 16:36:35.557324 [CA 5] Center 32 (2~62) winsize 61
5103 16:36:35.557404
5104 16:36:35.560352 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5105 16:36:35.560432
5106 16:36:35.563435 [CATrainingPosCal] consider 2 rank data
5107 16:36:35.567270 u2DelayCellTimex100 = 270/100 ps
5108 16:36:35.570262 CA0 delay=37 (7~67),Diff = 5 PI (31 cell)
5109 16:36:35.573917 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5110 16:36:35.577381 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5111 16:36:35.580183 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5112 16:36:35.586817 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5113 16:36:35.590449 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5114 16:36:35.590531
5115 16:36:35.593385 CA PerBit enable=1, Macro0, CA PI delay=32
5116 16:36:35.593466
5117 16:36:35.597100 [CBTSetCACLKResult] CA Dly = 32
5118 16:36:35.597181 CS Dly: 5 (0~37)
5119 16:36:35.597276
5120 16:36:35.599902 ----->DramcWriteLeveling(PI) begin...
5121 16:36:35.599984 ==
5122 16:36:35.603475 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 16:36:35.610291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 16:36:35.610368 ==
5125 16:36:35.613531 Write leveling (Byte 0): 31 => 31
5126 16:36:35.616806 Write leveling (Byte 1): 31 => 31
5127 16:36:35.616892 DramcWriteLeveling(PI) end<-----
5128 16:36:35.616972
5129 16:36:35.620029 ==
5130 16:36:35.623184 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 16:36:35.626358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 16:36:35.626472 ==
5133 16:36:35.629818 [Gating] SW mode calibration
5134 16:36:35.636551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5135 16:36:35.640316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5136 16:36:35.646391 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5137 16:36:35.658108 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 16:36:35.658939 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 16:36:35.660068 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 16:36:35.663966 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 16:36:35.667078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 16:36:35.673081 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5143 16:36:35.676885 0 14 28 | B1->B0 | 3333 2525 | 0 0 | (0 0) (0 0)
5144 16:36:35.679996 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5145 16:36:35.686556 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 16:36:35.689920 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 16:36:35.693644 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 16:36:35.700357 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 16:36:35.703257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 16:36:35.707022 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5151 16:36:35.712874 0 15 28 | B1->B0 | 2626 3b3b | 0 1 | (0 0) (0 0)
5152 16:36:35.716878 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5153 16:36:35.720061 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 16:36:35.726623 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 16:36:35.730004 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 16:36:35.733364 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 16:36:35.740209 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 16:36:35.743639 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5159 16:36:35.746690 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5160 16:36:35.749955 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 16:36:35.756550 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 16:36:35.759618 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 16:36:35.763354 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 16:36:35.769736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 16:36:35.772707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 16:36:35.776521 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 16:36:35.783281 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 16:36:35.786208 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 16:36:35.789858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 16:36:35.796498 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 16:36:35.800271 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 16:36:35.803145 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 16:36:35.809874 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 16:36:35.813369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 16:36:35.816263 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5176 16:36:35.823309 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5177 16:36:35.823500 Total UI for P1: 0, mck2ui 16
5178 16:36:35.826204 best dqsien dly found for B0: ( 1, 2, 28)
5179 16:36:35.833144 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 16:36:35.836838 Total UI for P1: 0, mck2ui 16
5181 16:36:35.839795 best dqsien dly found for B1: ( 1, 3, 0)
5182 16:36:35.843523 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5183 16:36:35.846926 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5184 16:36:35.847365
5185 16:36:35.850042 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5186 16:36:35.853139 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5187 16:36:35.856859 [Gating] SW calibration Done
5188 16:36:35.857374 ==
5189 16:36:35.859610 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 16:36:35.863306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 16:36:35.863715 ==
5192 16:36:35.866875 RX Vref Scan: 0
5193 16:36:35.867533
5194 16:36:35.868129 RX Vref 0 -> 0, step: 1
5195 16:36:35.869739
5196 16:36:35.870155 RX Delay -80 -> 252, step: 8
5197 16:36:35.876789 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5198 16:36:35.880022 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5199 16:36:35.883269 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5200 16:36:35.886567 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5201 16:36:35.890049 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5202 16:36:35.892717 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5203 16:36:35.899254 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5204 16:36:35.902926 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5205 16:36:35.905935 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5206 16:36:35.909566 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5207 16:36:35.912623 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5208 16:36:35.916141 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5209 16:36:35.922683 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5210 16:36:35.925594 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5211 16:36:35.929462 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5212 16:36:35.932465 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5213 16:36:35.932671 ==
5214 16:36:35.935666 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 16:36:35.939292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 16:36:35.942336 ==
5217 16:36:35.942530 DQS Delay:
5218 16:36:35.942664 DQS0 = 0, DQS1 = 0
5219 16:36:35.945444 DQM Delay:
5220 16:36:35.945669 DQM0 = 104, DQM1 = 94
5221 16:36:35.949364 DQ Delay:
5222 16:36:35.952131 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5223 16:36:35.955881 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5224 16:36:35.958953 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5225 16:36:35.962813 DQ12 =99, DQ13 =103, DQ14 =99, DQ15 =99
5226 16:36:35.962949
5227 16:36:35.963033
5228 16:36:35.963145 ==
5229 16:36:35.965684 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 16:36:35.969478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 16:36:35.969661 ==
5232 16:36:35.969772
5233 16:36:35.969875
5234 16:36:35.972253 TX Vref Scan disable
5235 16:36:35.972366 == TX Byte 0 ==
5236 16:36:35.979209 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5237 16:36:35.982178 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5238 16:36:35.982277 == TX Byte 1 ==
5239 16:36:35.988800 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5240 16:36:35.992364 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5241 16:36:35.992461 ==
5242 16:36:35.995952 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 16:36:35.999322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 16:36:35.999418 ==
5245 16:36:35.999502
5246 16:36:36.002471
5247 16:36:36.002545 TX Vref Scan disable
5248 16:36:36.005543 == TX Byte 0 ==
5249 16:36:36.008843 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5250 16:36:36.012111 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5251 16:36:36.015405 == TX Byte 1 ==
5252 16:36:36.018848 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5253 16:36:36.022434 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5254 16:36:36.025239
5255 16:36:36.025416 [DATLAT]
5256 16:36:36.025574 Freq=933, CH0 RK0
5257 16:36:36.025684
5258 16:36:36.028625 DATLAT Default: 0xd
5259 16:36:36.028794 0, 0xFFFF, sum = 0
5260 16:36:36.032010 1, 0xFFFF, sum = 0
5261 16:36:36.032189 2, 0xFFFF, sum = 0
5262 16:36:36.035471 3, 0xFFFF, sum = 0
5263 16:36:36.035689 4, 0xFFFF, sum = 0
5264 16:36:36.038616 5, 0xFFFF, sum = 0
5265 16:36:36.038822 6, 0xFFFF, sum = 0
5266 16:36:36.042489 7, 0xFFFF, sum = 0
5267 16:36:36.045533 8, 0xFFFF, sum = 0
5268 16:36:36.045712 9, 0xFFFF, sum = 0
5269 16:36:36.048423 10, 0x0, sum = 1
5270 16:36:36.048533 11, 0x0, sum = 2
5271 16:36:36.048624 12, 0x0, sum = 3
5272 16:36:36.052094 13, 0x0, sum = 4
5273 16:36:36.052210 best_step = 11
5274 16:36:36.052297
5275 16:36:36.055027 ==
5276 16:36:36.055138 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 16:36:36.061566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 16:36:36.061700 ==
5279 16:36:36.061789 RX Vref Scan: 1
5280 16:36:36.061861
5281 16:36:36.065266 RX Vref 0 -> 0, step: 1
5282 16:36:36.065368
5283 16:36:36.068370 RX Delay -53 -> 252, step: 4
5284 16:36:36.068476
5285 16:36:36.071978 Set Vref, RX VrefLevel [Byte0]: 57
5286 16:36:36.074967 [Byte1]: 46
5287 16:36:36.075087
5288 16:36:36.078533 Final RX Vref Byte 0 = 57 to rank0
5289 16:36:36.082112 Final RX Vref Byte 1 = 46 to rank0
5290 16:36:36.085174 Final RX Vref Byte 0 = 57 to rank1
5291 16:36:36.088122 Final RX Vref Byte 1 = 46 to rank1==
5292 16:36:36.091778 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 16:36:36.094756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 16:36:36.094845 ==
5295 16:36:36.098573 DQS Delay:
5296 16:36:36.098681 DQS0 = 0, DQS1 = 0
5297 16:36:36.101473 DQM Delay:
5298 16:36:36.101583 DQM0 = 104, DQM1 = 94
5299 16:36:36.101662 DQ Delay:
5300 16:36:36.105252 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5301 16:36:36.111654 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5302 16:36:36.111757 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =88
5303 16:36:36.118160 DQ12 =100, DQ13 =100, DQ14 =110, DQ15 =100
5304 16:36:36.118240
5305 16:36:36.118301
5306 16:36:36.124983 [DQSOSCAuto] RK0, (LSB)MR18= 0x3027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5307 16:36:36.128375 CH0 RK0: MR19=505, MR18=3027
5308 16:36:36.135093 CH0_RK0: MR19=0x505, MR18=0x3027, DQSOSC=406, MR23=63, INC=65, DEC=43
5309 16:36:36.135199
5310 16:36:36.138438 ----->DramcWriteLeveling(PI) begin...
5311 16:36:36.138539 ==
5312 16:36:36.141975 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 16:36:36.144848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 16:36:36.144943 ==
5315 16:36:36.148074 Write leveling (Byte 0): 33 => 33
5316 16:36:36.151450 Write leveling (Byte 1): 31 => 31
5317 16:36:36.155043 DramcWriteLeveling(PI) end<-----
5318 16:36:36.155117
5319 16:36:36.155180 ==
5320 16:36:36.158768 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 16:36:36.161561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 16:36:36.161667 ==
5323 16:36:36.165194 [Gating] SW mode calibration
5324 16:36:36.171935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5325 16:36:36.178653 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5326 16:36:36.181456 0 14 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
5327 16:36:36.188038 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 16:36:36.191590 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 16:36:36.195500 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 16:36:36.198371 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 16:36:36.205019 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 16:36:36.208739 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5333 16:36:36.211839 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (0 1) (0 1)
5334 16:36:36.218331 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5335 16:36:36.222025 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 16:36:36.224960 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 16:36:36.231854 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 16:36:36.234731 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 16:36:36.238188 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 16:36:36.244765 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5341 16:36:36.248301 0 15 28 | B1->B0 | 3f3f 3535 | 1 0 | (0 0) (0 0)
5342 16:36:36.251323 1 0 0 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
5343 16:36:36.258043 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 16:36:36.261557 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 16:36:36.265122 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 16:36:36.271275 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 16:36:36.274587 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 16:36:36.278076 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 16:36:36.284681 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5350 16:36:36.288323 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5351 16:36:36.291273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 16:36:36.297951 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 16:36:36.301776 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 16:36:36.304714 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 16:36:36.311109 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 16:36:36.314784 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 16:36:36.317813 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 16:36:36.324292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 16:36:36.327874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 16:36:36.330876 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 16:36:36.337724 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 16:36:36.341303 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 16:36:36.344342 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 16:36:36.347960 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 16:36:36.354596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 16:36:36.358045 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5367 16:36:36.360752 Total UI for P1: 0, mck2ui 16
5368 16:36:36.364346 best dqsien dly found for B1: ( 1, 2, 30)
5369 16:36:36.367434 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 16:36:36.371308 Total UI for P1: 0, mck2ui 16
5371 16:36:36.373941 best dqsien dly found for B0: ( 1, 3, 0)
5372 16:36:36.377473 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5373 16:36:36.381215 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5374 16:36:36.381321
5375 16:36:36.387494 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5376 16:36:36.391044 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5377 16:36:36.394388 [Gating] SW calibration Done
5378 16:36:36.394498 ==
5379 16:36:36.397862 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 16:36:36.400713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 16:36:36.400782 ==
5382 16:36:36.400839 RX Vref Scan: 0
5383 16:36:36.400892
5384 16:36:36.404168 RX Vref 0 -> 0, step: 1
5385 16:36:36.404236
5386 16:36:36.407825 RX Delay -80 -> 252, step: 8
5387 16:36:36.410507 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5388 16:36:36.414171 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5389 16:36:36.420883 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5390 16:36:36.423964 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5391 16:36:36.426994 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5392 16:36:36.430840 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5393 16:36:36.433741 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5394 16:36:36.437433 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5395 16:36:36.443525 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5396 16:36:36.447167 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5397 16:36:36.450139 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5398 16:36:36.454019 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5399 16:36:36.457205 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5400 16:36:36.460740 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5401 16:36:36.466716 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5402 16:36:36.470193 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5403 16:36:36.470283 ==
5404 16:36:36.473753 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 16:36:36.476689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 16:36:36.476762 ==
5407 16:36:36.480239 DQS Delay:
5408 16:36:36.480318 DQS0 = 0, DQS1 = 0
5409 16:36:36.480377 DQM Delay:
5410 16:36:36.484048 DQM0 = 105, DQM1 = 94
5411 16:36:36.484154 DQ Delay:
5412 16:36:36.487032 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5413 16:36:36.490002 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5414 16:36:36.493650 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5415 16:36:36.496639 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5416 16:36:36.496732
5417 16:36:36.496808
5418 16:36:36.500322 ==
5419 16:36:36.503303 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 16:36:36.506852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 16:36:36.506944 ==
5422 16:36:36.507007
5423 16:36:36.507072
5424 16:36:36.509741 TX Vref Scan disable
5425 16:36:36.509816 == TX Byte 0 ==
5426 16:36:36.513408 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5427 16:36:36.519561 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5428 16:36:36.519636 == TX Byte 1 ==
5429 16:36:36.523532 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5430 16:36:36.529759 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5431 16:36:36.529836 ==
5432 16:36:36.533422 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 16:36:36.536473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 16:36:36.536550 ==
5435 16:36:36.536608
5436 16:36:36.536665
5437 16:36:36.540187 TX Vref Scan disable
5438 16:36:36.543029 == TX Byte 0 ==
5439 16:36:36.546781 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5440 16:36:36.549787 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5441 16:36:36.553457 == TX Byte 1 ==
5442 16:36:36.556414 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5443 16:36:36.560152 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5444 16:36:36.560229
5445 16:36:36.563208 [DATLAT]
5446 16:36:36.563273 Freq=933, CH0 RK1
5447 16:36:36.563328
5448 16:36:36.566210 DATLAT Default: 0xb
5449 16:36:36.566272 0, 0xFFFF, sum = 0
5450 16:36:36.570041 1, 0xFFFF, sum = 0
5451 16:36:36.570114 2, 0xFFFF, sum = 0
5452 16:36:36.573056 3, 0xFFFF, sum = 0
5453 16:36:36.573120 4, 0xFFFF, sum = 0
5454 16:36:36.576096 5, 0xFFFF, sum = 0
5455 16:36:36.576157 6, 0xFFFF, sum = 0
5456 16:36:36.579734 7, 0xFFFF, sum = 0
5457 16:36:36.579825 8, 0xFFFF, sum = 0
5458 16:36:36.583253 9, 0xFFFF, sum = 0
5459 16:36:36.583319 10, 0x0, sum = 1
5460 16:36:36.586654 11, 0x0, sum = 2
5461 16:36:36.586734 12, 0x0, sum = 3
5462 16:36:36.590109 13, 0x0, sum = 4
5463 16:36:36.590186 best_step = 11
5464 16:36:36.590246
5465 16:36:36.590301 ==
5466 16:36:36.592958 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 16:36:36.596563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 16:36:36.599615 ==
5469 16:36:36.599692 RX Vref Scan: 0
5470 16:36:36.599751
5471 16:36:36.603237 RX Vref 0 -> 0, step: 1
5472 16:36:36.603313
5473 16:36:36.606173 RX Delay -45 -> 252, step: 4
5474 16:36:36.609888 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5475 16:36:36.612820 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5476 16:36:36.619722 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5477 16:36:36.622790 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5478 16:36:36.625990 iDelay=199, Bit 4, Center 108 (23 ~ 194) 172
5479 16:36:36.629497 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5480 16:36:36.632570 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5481 16:36:36.636102 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5482 16:36:36.642953 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5483 16:36:36.645788 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5484 16:36:36.649071 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5485 16:36:36.652813 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5486 16:36:36.656084 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5487 16:36:36.662636 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5488 16:36:36.666370 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5489 16:36:36.669477 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5490 16:36:36.669609 ==
5491 16:36:36.672529 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 16:36:36.676040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 16:36:36.676120 ==
5494 16:36:36.679094 DQS Delay:
5495 16:36:36.679171 DQS0 = 0, DQS1 = 0
5496 16:36:36.682798 DQM Delay:
5497 16:36:36.682877 DQM0 = 104, DQM1 = 94
5498 16:36:36.682954 DQ Delay:
5499 16:36:36.685805 DQ0 =104, DQ1 =104, DQ2 =100, DQ3 =100
5500 16:36:36.689604 DQ4 =108, DQ5 =98, DQ6 =110, DQ7 =112
5501 16:36:36.692574 DQ8 =86, DQ9 =82, DQ10 =96, DQ11 =88
5502 16:36:36.698910 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5503 16:36:36.698988
5504 16:36:36.699065
5505 16:36:36.705771 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5506 16:36:36.709347 CH0 RK1: MR19=505, MR18=2D06
5507 16:36:36.715905 CH0_RK1: MR19=0x505, MR18=0x2D06, DQSOSC=407, MR23=63, INC=65, DEC=43
5508 16:36:36.718931 [RxdqsGatingPostProcess] freq 933
5509 16:36:36.721944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 16:36:36.725692 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 16:36:36.728565 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 16:36:36.732152 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 16:36:36.735354 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 16:36:36.739051 best DQS0 dly(2T, 0.5T) = (0, 11)
5515 16:36:36.741995 best DQS1 dly(2T, 0.5T) = (0, 10)
5516 16:36:36.745383 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5517 16:36:36.749060 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5518 16:36:36.752065 Pre-setting of DQS Precalculation
5519 16:36:36.754959 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 16:36:36.758495 ==
5521 16:36:36.762065 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 16:36:36.764980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 16:36:36.765072 ==
5524 16:36:36.768418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 16:36:36.774987 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 16:36:36.778737 [CA 0] Center 36 (6~67) winsize 62
5527 16:36:36.782271 [CA 1] Center 36 (6~67) winsize 62
5528 16:36:36.785281 [CA 2] Center 34 (4~65) winsize 62
5529 16:36:36.789190 [CA 3] Center 34 (4~65) winsize 62
5530 16:36:36.792407 [CA 4] Center 34 (4~64) winsize 61
5531 16:36:36.795407 [CA 5] Center 33 (3~64) winsize 62
5532 16:36:36.795489
5533 16:36:36.799282 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 16:36:36.799371
5535 16:36:36.802236 [CATrainingPosCal] consider 1 rank data
5536 16:36:36.805291 u2DelayCellTimex100 = 270/100 ps
5537 16:36:36.808892 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 16:36:36.811881 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 16:36:36.818676 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5540 16:36:36.822223 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5541 16:36:36.825530 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5542 16:36:36.828669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5543 16:36:36.828785
5544 16:36:36.832251 CA PerBit enable=1, Macro0, CA PI delay=33
5545 16:36:36.832381
5546 16:36:36.835486 [CBTSetCACLKResult] CA Dly = 33
5547 16:36:36.835615 CS Dly: 7 (0~38)
5548 16:36:36.838595 ==
5549 16:36:36.838747 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 16:36:36.845479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 16:36:36.845691 ==
5552 16:36:36.848512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 16:36:36.855211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5554 16:36:36.858921 [CA 0] Center 36 (6~67) winsize 62
5555 16:36:36.861952 [CA 1] Center 37 (6~68) winsize 63
5556 16:36:36.865880 [CA 2] Center 35 (5~66) winsize 62
5557 16:36:36.869059 [CA 3] Center 34 (4~65) winsize 62
5558 16:36:36.872060 [CA 4] Center 34 (4~65) winsize 62
5559 16:36:36.875649 [CA 5] Center 33 (3~64) winsize 62
5560 16:36:36.875731
5561 16:36:36.878632 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5562 16:36:36.878720
5563 16:36:36.882363 [CATrainingPosCal] consider 2 rank data
5564 16:36:36.885789 u2DelayCellTimex100 = 270/100 ps
5565 16:36:36.888681 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 16:36:36.892192 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 16:36:36.898657 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5568 16:36:36.901860 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 16:36:36.905516 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5570 16:36:36.908553 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 16:36:36.908787
5572 16:36:36.912439 CA PerBit enable=1, Macro0, CA PI delay=33
5573 16:36:36.912567
5574 16:36:36.915302 [CBTSetCACLKResult] CA Dly = 33
5575 16:36:36.915412 CS Dly: 8 (0~40)
5576 16:36:36.915512
5577 16:36:36.919025 ----->DramcWriteLeveling(PI) begin...
5578 16:36:36.921903 ==
5579 16:36:36.925503 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 16:36:36.928536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 16:36:36.928665 ==
5582 16:36:36.931903 Write leveling (Byte 0): 25 => 25
5583 16:36:36.935347 Write leveling (Byte 1): 27 => 27
5584 16:36:36.939081 DramcWriteLeveling(PI) end<-----
5585 16:36:36.939200
5586 16:36:36.939294 ==
5587 16:36:36.942081 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 16:36:36.945530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 16:36:36.945647 ==
5590 16:36:36.948297 [Gating] SW mode calibration
5591 16:36:36.954926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 16:36:36.961531 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 16:36:36.965641 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 16:36:36.969179 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 16:36:36.975399 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 16:36:36.979228 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 16:36:36.982125 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 16:36:36.985920 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5599 16:36:36.991996 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5600 16:36:36.995712 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5601 16:36:36.998698 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 16:36:37.005265 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 16:36:37.008905 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 16:36:37.012419 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 16:36:37.019028 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 16:36:37.022045 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 16:36:37.025780 0 15 24 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
5608 16:36:37.032492 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5609 16:36:37.035361 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 16:36:37.039057 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 16:36:37.045214 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 16:36:37.048781 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 16:36:37.051501 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 16:36:37.058298 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 16:36:37.061738 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5616 16:36:37.065005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5617 16:36:37.071505 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 16:36:37.075200 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 16:36:37.078089 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 16:36:37.084972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 16:36:37.087921 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 16:36:37.091047 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 16:36:37.097889 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 16:36:37.100884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 16:36:37.104784 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 16:36:37.110986 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 16:36:37.114808 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 16:36:37.117786 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 16:36:37.124813 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 16:36:37.127817 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 16:36:37.131439 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 16:36:37.134406 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5633 16:36:37.138159 Total UI for P1: 0, mck2ui 16
5634 16:36:37.141150 best dqsien dly found for B1: ( 1, 2, 24)
5635 16:36:37.148546 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 16:36:37.151341 Total UI for P1: 0, mck2ui 16
5637 16:36:37.155249 best dqsien dly found for B0: ( 1, 2, 26)
5638 16:36:37.157954 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5639 16:36:37.161576 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5640 16:36:37.161968
5641 16:36:37.164604 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 16:36:37.168323 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5643 16:36:37.171252 [Gating] SW calibration Done
5644 16:36:37.171641 ==
5645 16:36:37.174796 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 16:36:37.178191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 16:36:37.178591 ==
5648 16:36:37.181584 RX Vref Scan: 0
5649 16:36:37.182000
5650 16:36:37.182313 RX Vref 0 -> 0, step: 1
5651 16:36:37.185029
5652 16:36:37.185418 RX Delay -80 -> 252, step: 8
5653 16:36:37.191043 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5654 16:36:37.194697 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5655 16:36:37.197791 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5656 16:36:37.201521 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5657 16:36:37.204453 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5658 16:36:37.208427 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5659 16:36:37.214202 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5660 16:36:37.218013 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5661 16:36:37.220990 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5662 16:36:37.224662 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5663 16:36:37.227608 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5664 16:36:37.231254 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5665 16:36:37.237464 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5666 16:36:37.241007 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5667 16:36:37.244618 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5668 16:36:37.247562 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5669 16:36:37.247847 ==
5670 16:36:37.251226 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 16:36:37.254212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 16:36:37.257877 ==
5673 16:36:37.258159 DQS Delay:
5674 16:36:37.258441 DQS0 = 0, DQS1 = 0
5675 16:36:37.260858 DQM Delay:
5676 16:36:37.261142 DQM0 = 101, DQM1 = 98
5677 16:36:37.264315 DQ Delay:
5678 16:36:37.267988 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5679 16:36:37.271005 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =103
5680 16:36:37.274568 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5681 16:36:37.277660 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5682 16:36:37.277944
5683 16:36:37.278283
5684 16:36:37.278549 ==
5685 16:36:37.281409 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 16:36:37.284407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 16:36:37.284688 ==
5688 16:36:37.284903
5689 16:36:37.285102
5690 16:36:37.287456 TX Vref Scan disable
5691 16:36:37.291008 == TX Byte 0 ==
5692 16:36:37.294497 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5693 16:36:37.297848 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5694 16:36:37.301348 == TX Byte 1 ==
5695 16:36:37.304233 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5696 16:36:37.307704 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5697 16:36:37.308083 ==
5698 16:36:37.311112 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 16:36:37.314272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 16:36:37.314640 ==
5701 16:36:37.317820
5702 16:36:37.318153
5703 16:36:37.318470 TX Vref Scan disable
5704 16:36:37.320859 == TX Byte 0 ==
5705 16:36:37.324573 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5706 16:36:37.330606 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5707 16:36:37.330914 == TX Byte 1 ==
5708 16:36:37.334500 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5709 16:36:37.341202 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5710 16:36:37.341610
5711 16:36:37.341863 [DATLAT]
5712 16:36:37.342083 Freq=933, CH1 RK0
5713 16:36:37.342409
5714 16:36:37.344276 DATLAT Default: 0xd
5715 16:36:37.344604 0, 0xFFFF, sum = 0
5716 16:36:37.347192 1, 0xFFFF, sum = 0
5717 16:36:37.347567 2, 0xFFFF, sum = 0
5718 16:36:37.350549 3, 0xFFFF, sum = 0
5719 16:36:37.354117 4, 0xFFFF, sum = 0
5720 16:36:37.354193 5, 0xFFFF, sum = 0
5721 16:36:37.357327 6, 0xFFFF, sum = 0
5722 16:36:37.357404 7, 0xFFFF, sum = 0
5723 16:36:37.360907 8, 0xFFFF, sum = 0
5724 16:36:37.360984 9, 0xFFFF, sum = 0
5725 16:36:37.363759 10, 0x0, sum = 1
5726 16:36:37.363835 11, 0x0, sum = 2
5727 16:36:37.367322 12, 0x0, sum = 3
5728 16:36:37.367409 13, 0x0, sum = 4
5729 16:36:37.367472 best_step = 11
5730 16:36:37.367530
5731 16:36:37.370254 ==
5732 16:36:37.373900 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 16:36:37.376892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 16:36:37.376983 ==
5735 16:36:37.377098 RX Vref Scan: 1
5736 16:36:37.377210
5737 16:36:37.380693 RX Vref 0 -> 0, step: 1
5738 16:36:37.380788
5739 16:36:37.383895 RX Delay -45 -> 252, step: 4
5740 16:36:37.383986
5741 16:36:37.386867 Set Vref, RX VrefLevel [Byte0]: 55
5742 16:36:37.390622 [Byte1]: 53
5743 16:36:37.390743
5744 16:36:37.393659 Final RX Vref Byte 0 = 55 to rank0
5745 16:36:37.397361 Final RX Vref Byte 1 = 53 to rank0
5746 16:36:37.400380 Final RX Vref Byte 0 = 55 to rank1
5747 16:36:37.403449 Final RX Vref Byte 1 = 53 to rank1==
5748 16:36:37.406926 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 16:36:37.410678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 16:36:37.410875 ==
5751 16:36:37.413470 DQS Delay:
5752 16:36:37.413731 DQS0 = 0, DQS1 = 0
5753 16:36:37.417313 DQM Delay:
5754 16:36:37.417692 DQM0 = 103, DQM1 = 99
5755 16:36:37.420484 DQ Delay:
5756 16:36:37.424080 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5757 16:36:37.427131 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5758 16:36:37.430766 DQ8 =88, DQ9 =92, DQ10 =100, DQ11 =92
5759 16:36:37.433808 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =106
5760 16:36:37.434229
5761 16:36:37.434624
5762 16:36:37.440615 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5763 16:36:37.443716 CH1 RK0: MR19=505, MR18=1C33
5764 16:36:37.450501 CH1_RK0: MR19=0x505, MR18=0x1C33, DQSOSC=405, MR23=63, INC=66, DEC=44
5765 16:36:37.451049
5766 16:36:37.453632 ----->DramcWriteLeveling(PI) begin...
5767 16:36:37.454234 ==
5768 16:36:37.457438 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 16:36:37.460255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 16:36:37.460806 ==
5771 16:36:37.463795 Write leveling (Byte 0): 27 => 27
5772 16:36:37.467274 Write leveling (Byte 1): 27 => 27
5773 16:36:37.470172 DramcWriteLeveling(PI) end<-----
5774 16:36:37.470685
5775 16:36:37.471230 ==
5776 16:36:37.473728 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 16:36:37.477246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 16:36:37.477824 ==
5779 16:36:37.480678 [Gating] SW mode calibration
5780 16:36:37.487010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 16:36:37.493943 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 16:36:37.496915 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 16:36:37.503634 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 16:36:37.507091 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 16:36:37.510046 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 16:36:37.516719 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 16:36:37.520423 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5788 16:36:37.523556 0 14 24 | B1->B0 | 2e2e 3131 | 0 0 | (1 0) (0 0)
5789 16:36:37.530300 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
5790 16:36:37.533728 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 16:36:37.536610 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 16:36:37.543125 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 16:36:37.546196 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 16:36:37.549944 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 16:36:37.556838 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 16:36:37.559911 0 15 24 | B1->B0 | 3939 2a2a | 0 0 | (0 0) (0 0)
5797 16:36:37.562906 0 15 28 | B1->B0 | 4545 3e3e | 0 1 | (0 0) (0 0)
5798 16:36:37.569788 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 16:36:37.572783 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 16:36:37.576515 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 16:36:37.580175 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 16:36:37.586501 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 16:36:37.590099 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 16:36:37.593052 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5805 16:36:37.599795 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5806 16:36:37.602956 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 16:36:37.606227 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 16:36:37.612851 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 16:36:37.616572 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 16:36:37.619892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 16:36:37.626324 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 16:36:37.629413 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 16:36:37.633075 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 16:36:37.639850 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 16:36:37.642783 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 16:36:37.646375 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 16:36:37.652489 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 16:36:37.656522 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 16:36:37.659647 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 16:36:37.666352 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5821 16:36:37.669316 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 16:36:37.673003 Total UI for P1: 0, mck2ui 16
5823 16:36:37.675933 best dqsien dly found for B0: ( 1, 2, 26)
5824 16:36:37.679807 Total UI for P1: 0, mck2ui 16
5825 16:36:37.682806 best dqsien dly found for B1: ( 1, 2, 24)
5826 16:36:37.686451 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5827 16:36:37.689526 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5828 16:36:37.690053
5829 16:36:37.693100 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5830 16:36:37.696064 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5831 16:36:37.699544 [Gating] SW calibration Done
5832 16:36:37.699934 ==
5833 16:36:37.702507 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 16:36:37.706080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 16:36:37.709173 ==
5836 16:36:37.709601 RX Vref Scan: 0
5837 16:36:37.709918
5838 16:36:37.712764 RX Vref 0 -> 0, step: 1
5839 16:36:37.713155
5840 16:36:37.715670 RX Delay -80 -> 252, step: 8
5841 16:36:37.719190 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5842 16:36:37.722758 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5843 16:36:37.725713 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5844 16:36:37.729497 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5845 16:36:37.732359 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5846 16:36:37.739101 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5847 16:36:37.742067 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5848 16:36:37.745710 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5849 16:36:37.748766 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5850 16:36:37.752392 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5851 16:36:37.755841 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5852 16:36:37.762334 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5853 16:36:37.765859 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5854 16:36:37.769110 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5855 16:36:37.772338 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5856 16:36:37.775217 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5857 16:36:37.778985 ==
5858 16:36:37.781935 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 16:36:37.785689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 16:36:37.786191 ==
5861 16:36:37.786607 DQS Delay:
5862 16:36:37.788805 DQS0 = 0, DQS1 = 0
5863 16:36:37.789323 DQM Delay:
5864 16:36:37.791759 DQM0 = 102, DQM1 = 99
5865 16:36:37.792151 DQ Delay:
5866 16:36:37.795614 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5867 16:36:37.798466 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5868 16:36:37.802277 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5869 16:36:37.805159 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5870 16:36:37.805581
5871 16:36:37.805906
5872 16:36:37.806189 ==
5873 16:36:37.808738 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 16:36:37.812244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 16:36:37.812637 ==
5876 16:36:37.815271
5877 16:36:37.815660
5878 16:36:37.815965 TX Vref Scan disable
5879 16:36:37.818890 == TX Byte 0 ==
5880 16:36:37.822019 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5881 16:36:37.825443 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5882 16:36:37.828576 == TX Byte 1 ==
5883 16:36:37.831642 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5884 16:36:37.835301 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5885 16:36:37.835716 ==
5886 16:36:37.838261 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 16:36:37.845005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 16:36:37.845433 ==
5889 16:36:37.845843
5890 16:36:37.846241
5891 16:36:37.846652 TX Vref Scan disable
5892 16:36:37.849613 == TX Byte 0 ==
5893 16:36:37.852668 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5894 16:36:37.855793 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5895 16:36:37.859518 == TX Byte 1 ==
5896 16:36:37.862475 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5897 16:36:37.869202 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5898 16:36:37.869776
5899 16:36:37.870100 [DATLAT]
5900 16:36:37.870391 Freq=933, CH1 RK1
5901 16:36:37.870669
5902 16:36:37.872809 DATLAT Default: 0xb
5903 16:36:37.873195 0, 0xFFFF, sum = 0
5904 16:36:37.876550 1, 0xFFFF, sum = 0
5905 16:36:37.876953 2, 0xFFFF, sum = 0
5906 16:36:37.879311 3, 0xFFFF, sum = 0
5907 16:36:37.880005 4, 0xFFFF, sum = 0
5908 16:36:37.882700 5, 0xFFFF, sum = 0
5909 16:36:37.883098 6, 0xFFFF, sum = 0
5910 16:36:37.886133 7, 0xFFFF, sum = 0
5911 16:36:37.889837 8, 0xFFFF, sum = 0
5912 16:36:37.890232 9, 0xFFFF, sum = 0
5913 16:36:37.890766 10, 0x0, sum = 1
5914 16:36:37.892605 11, 0x0, sum = 2
5915 16:36:37.893114 12, 0x0, sum = 3
5916 16:36:37.896317 13, 0x0, sum = 4
5917 16:36:37.896712 best_step = 11
5918 16:36:37.897012
5919 16:36:37.897292 ==
5920 16:36:37.899379 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 16:36:37.906171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 16:36:37.906608 ==
5923 16:36:37.906918 RX Vref Scan: 0
5924 16:36:37.907199
5925 16:36:37.909174 RX Vref 0 -> 0, step: 1
5926 16:36:37.909593
5927 16:36:37.913044 RX Delay -45 -> 252, step: 4
5928 16:36:37.916082 iDelay=203, Bit 0, Center 108 (23 ~ 194) 172
5929 16:36:37.922374 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5930 16:36:37.925832 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5931 16:36:37.929536 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5932 16:36:37.932936 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5933 16:36:37.935854 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5934 16:36:37.942405 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5935 16:36:37.946077 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5936 16:36:37.948932 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5937 16:36:37.952810 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5938 16:36:37.955877 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5939 16:36:37.958906 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5940 16:36:37.965403 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5941 16:36:37.968918 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5942 16:36:37.972674 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5943 16:36:37.975783 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5944 16:36:37.976442 ==
5945 16:36:37.979528 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 16:36:37.985326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 16:36:37.986029 ==
5948 16:36:37.986548 DQS Delay:
5949 16:36:37.989147 DQS0 = 0, DQS1 = 0
5950 16:36:37.989540 DQM Delay:
5951 16:36:37.990160 DQM0 = 104, DQM1 = 99
5952 16:36:37.992832 DQ Delay:
5953 16:36:37.995669 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5954 16:36:37.999122 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5955 16:36:38.002515 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5956 16:36:38.005925 DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =106
5957 16:36:38.006384
5958 16:36:38.006776
5959 16:36:38.012099 [DQSOSCAuto] RK1, (LSB)MR18= 0x3004, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5960 16:36:38.015727 CH1 RK1: MR19=505, MR18=3004
5961 16:36:38.022667 CH1_RK1: MR19=0x505, MR18=0x3004, DQSOSC=406, MR23=63, INC=65, DEC=43
5962 16:36:38.025597 [RxdqsGatingPostProcess] freq 933
5963 16:36:38.032301 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 16:36:38.035734 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 16:36:38.036137 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 16:36:38.039287 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 16:36:38.042061 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 16:36:38.045579 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 16:36:38.048923 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 16:36:38.052498 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 16:36:38.055420 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 16:36:38.058809 Pre-setting of DQS Precalculation
5973 16:36:38.065655 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 16:36:38.072383 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 16:36:38.079188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 16:36:38.079610
5977 16:36:38.079913
5978 16:36:38.082224 [Calibration Summary] 1866 Mbps
5979 16:36:38.082612 CH 0, Rank 0
5980 16:36:38.085913 SW Impedance : PASS
5981 16:36:38.088788 DUTY Scan : NO K
5982 16:36:38.089182 ZQ Calibration : PASS
5983 16:36:38.092592 Jitter Meter : NO K
5984 16:36:38.092997 CBT Training : PASS
5985 16:36:38.095679 Write leveling : PASS
5986 16:36:38.098757 RX DQS gating : PASS
5987 16:36:38.099152 RX DQ/DQS(RDDQC) : PASS
5988 16:36:38.102548 TX DQ/DQS : PASS
5989 16:36:38.105635 RX DATLAT : PASS
5990 16:36:38.106044 RX DQ/DQS(Engine): PASS
5991 16:36:38.108643 TX OE : NO K
5992 16:36:38.109038 All Pass.
5993 16:36:38.109359
5994 16:36:38.112381 CH 0, Rank 1
5995 16:36:38.112731 SW Impedance : PASS
5996 16:36:38.115289 DUTY Scan : NO K
5997 16:36:38.118818 ZQ Calibration : PASS
5998 16:36:38.119276 Jitter Meter : NO K
5999 16:36:38.122225 CBT Training : PASS
6000 16:36:38.125598 Write leveling : PASS
6001 16:36:38.125999 RX DQS gating : PASS
6002 16:36:38.128774 RX DQ/DQS(RDDQC) : PASS
6003 16:36:38.131951 TX DQ/DQS : PASS
6004 16:36:38.132348 RX DATLAT : PASS
6005 16:36:38.134975 RX DQ/DQS(Engine): PASS
6006 16:36:38.138599 TX OE : NO K
6007 16:36:38.138992 All Pass.
6008 16:36:38.139292
6009 16:36:38.139572 CH 1, Rank 0
6010 16:36:38.141624 SW Impedance : PASS
6011 16:36:38.145256 DUTY Scan : NO K
6012 16:36:38.145689 ZQ Calibration : PASS
6013 16:36:38.148222 Jitter Meter : NO K
6014 16:36:38.151878 CBT Training : PASS
6015 16:36:38.152272 Write leveling : PASS
6016 16:36:38.155402 RX DQS gating : PASS
6017 16:36:38.155798 RX DQ/DQS(RDDQC) : PASS
6018 16:36:38.158420 TX DQ/DQS : PASS
6019 16:36:38.162146 RX DATLAT : PASS
6020 16:36:38.162537 RX DQ/DQS(Engine): PASS
6021 16:36:38.164917 TX OE : NO K
6022 16:36:38.165309 All Pass.
6023 16:36:38.165643
6024 16:36:38.168731 CH 1, Rank 1
6025 16:36:38.169122 SW Impedance : PASS
6026 16:36:38.171512 DUTY Scan : NO K
6027 16:36:38.175094 ZQ Calibration : PASS
6028 16:36:38.175481 Jitter Meter : NO K
6029 16:36:38.178075 CBT Training : PASS
6030 16:36:38.181653 Write leveling : PASS
6031 16:36:38.182072 RX DQS gating : PASS
6032 16:36:38.184736 RX DQ/DQS(RDDQC) : PASS
6033 16:36:38.188274 TX DQ/DQS : PASS
6034 16:36:38.188670 RX DATLAT : PASS
6035 16:36:38.191121 RX DQ/DQS(Engine): PASS
6036 16:36:38.194948 TX OE : NO K
6037 16:36:38.195388 All Pass.
6038 16:36:38.195715
6039 16:36:38.196000 DramC Write-DBI off
6040 16:36:38.197927 PER_BANK_REFRESH: Hybrid Mode
6041 16:36:38.201646 TX_TRACKING: ON
6042 16:36:38.208382 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 16:36:38.211486 [FAST_K] Save calibration result to emmc
6044 16:36:38.218251 dramc_set_vcore_voltage set vcore to 650000
6045 16:36:38.218662 Read voltage for 400, 6
6046 16:36:38.221673 Vio18 = 0
6047 16:36:38.222204 Vcore = 650000
6048 16:36:38.222663 Vdram = 0
6049 16:36:38.224720 Vddq = 0
6050 16:36:38.225193 Vmddr = 0
6051 16:36:38.227731 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 16:36:38.235135 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 16:36:38.237933 MEM_TYPE=3, freq_sel=20
6054 16:36:38.238336 sv_algorithm_assistance_LP4_800
6055 16:36:38.244875 ============ PULL DRAM RESETB DOWN ============
6056 16:36:38.248179 ========== PULL DRAM RESETB DOWN end =========
6057 16:36:38.251170 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 16:36:38.255111 ===================================
6059 16:36:38.258334 LPDDR4 DRAM CONFIGURATION
6060 16:36:38.261314 ===================================
6061 16:36:38.264649 EX_ROW_EN[0] = 0x0
6062 16:36:38.265190 EX_ROW_EN[1] = 0x0
6063 16:36:38.268332 LP4Y_EN = 0x0
6064 16:36:38.268746 WORK_FSP = 0x0
6065 16:36:38.271509 WL = 0x2
6066 16:36:38.271931 RL = 0x2
6067 16:36:38.274465 BL = 0x2
6068 16:36:38.274908 RPST = 0x0
6069 16:36:38.278062 RD_PRE = 0x0
6070 16:36:38.278567 WR_PRE = 0x1
6071 16:36:38.281476 WR_PST = 0x0
6072 16:36:38.281927 DBI_WR = 0x0
6073 16:36:38.284269 DBI_RD = 0x0
6074 16:36:38.287895 OTF = 0x1
6075 16:36:38.291478 ===================================
6076 16:36:38.291989 ===================================
6077 16:36:38.294404 ANA top config
6078 16:36:38.297952 ===================================
6079 16:36:38.300966 DLL_ASYNC_EN = 0
6080 16:36:38.301354 ALL_SLAVE_EN = 1
6081 16:36:38.304716 NEW_RANK_MODE = 1
6082 16:36:38.307750 DLL_IDLE_MODE = 1
6083 16:36:38.311572 LP45_APHY_COMB_EN = 1
6084 16:36:38.314552 TX_ODT_DIS = 1
6085 16:36:38.314990 NEW_8X_MODE = 1
6086 16:36:38.317509 ===================================
6087 16:36:38.321228 ===================================
6088 16:36:38.324209 data_rate = 800
6089 16:36:38.327877 CKR = 1
6090 16:36:38.330904 DQ_P2S_RATIO = 4
6091 16:36:38.333960 ===================================
6092 16:36:38.337722 CA_P2S_RATIO = 4
6093 16:36:38.340742 DQ_CA_OPEN = 0
6094 16:36:38.341136 DQ_SEMI_OPEN = 1
6095 16:36:38.344546 CA_SEMI_OPEN = 1
6096 16:36:38.347530 CA_FULL_RATE = 0
6097 16:36:38.350504 DQ_CKDIV4_EN = 0
6098 16:36:38.354132 CA_CKDIV4_EN = 1
6099 16:36:38.357772 CA_PREDIV_EN = 0
6100 16:36:38.358167 PH8_DLY = 0
6101 16:36:38.360664 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 16:36:38.364274 DQ_AAMCK_DIV = 0
6103 16:36:38.367125 CA_AAMCK_DIV = 0
6104 16:36:38.370536 CA_ADMCK_DIV = 4
6105 16:36:38.374109 DQ_TRACK_CA_EN = 0
6106 16:36:38.374503 CA_PICK = 800
6107 16:36:38.376734 CA_MCKIO = 400
6108 16:36:38.380624 MCKIO_SEMI = 400
6109 16:36:38.383864 PLL_FREQ = 3016
6110 16:36:38.387033 DQ_UI_PI_RATIO = 32
6111 16:36:38.390216 CA_UI_PI_RATIO = 32
6112 16:36:38.393408 ===================================
6113 16:36:38.397251 ===================================
6114 16:36:38.399957 memory_type:LPDDR4
6115 16:36:38.400477 GP_NUM : 10
6116 16:36:38.403189 SRAM_EN : 1
6117 16:36:38.403704 MD32_EN : 0
6118 16:36:38.407062 ===================================
6119 16:36:38.410062 [ANA_INIT] >>>>>>>>>>>>>>
6120 16:36:38.413213 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 16:36:38.416563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 16:36:38.420113 ===================================
6123 16:36:38.423325 data_rate = 800,PCW = 0X7400
6124 16:36:38.426984 ===================================
6125 16:36:38.429910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 16:36:38.436577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 16:36:38.446367 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 16:36:38.450118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 16:36:38.453141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 16:36:38.459706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 16:36:38.460121 [ANA_INIT] flow start
6132 16:36:38.463203 [ANA_INIT] PLL >>>>>>>>
6133 16:36:38.463639 [ANA_INIT] PLL <<<<<<<<
6134 16:36:38.466141 [ANA_INIT] MIDPI >>>>>>>>
6135 16:36:38.469247 [ANA_INIT] MIDPI <<<<<<<<
6136 16:36:38.473043 [ANA_INIT] DLL >>>>>>>>
6137 16:36:38.473436 [ANA_INIT] flow end
6138 16:36:38.476013 ============ LP4 DIFF to SE enter ============
6139 16:36:38.482895 ============ LP4 DIFF to SE exit ============
6140 16:36:38.483412 [ANA_INIT] <<<<<<<<<<<<<
6141 16:36:38.485951 [Flow] Enable top DCM control >>>>>
6142 16:36:38.489776 [Flow] Enable top DCM control <<<<<
6143 16:36:38.492782 Enable DLL master slave shuffle
6144 16:36:38.498869 ==============================================================
6145 16:36:38.502535 Gating Mode config
6146 16:36:38.505398 ==============================================================
6147 16:36:38.508808 Config description:
6148 16:36:38.518939 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 16:36:38.525870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 16:36:38.528587 SELPH_MODE 0: By rank 1: By Phase
6151 16:36:38.535572 ==============================================================
6152 16:36:38.538880 GAT_TRACK_EN = 0
6153 16:36:38.542111 RX_GATING_MODE = 2
6154 16:36:38.545616 RX_GATING_TRACK_MODE = 2
6155 16:36:38.546153 SELPH_MODE = 1
6156 16:36:38.548615 PICG_EARLY_EN = 1
6157 16:36:38.552449 VALID_LAT_VALUE = 1
6158 16:36:38.558545 ==============================================================
6159 16:36:38.562442 Enter into Gating configuration >>>>
6160 16:36:38.565356 Exit from Gating configuration <<<<
6161 16:36:38.568969 Enter into DVFS_PRE_config >>>>>
6162 16:36:38.578860 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 16:36:38.581922 Exit from DVFS_PRE_config <<<<<
6164 16:36:38.585087 Enter into PICG configuration >>>>
6165 16:36:38.588802 Exit from PICG configuration <<<<
6166 16:36:38.591822 [RX_INPUT] configuration >>>>>
6167 16:36:38.594802 [RX_INPUT] configuration <<<<<
6168 16:36:38.598682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 16:36:38.605499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 16:36:38.611470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 16:36:38.618291 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 16:36:38.624787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 16:36:38.628146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 16:36:38.634697 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 16:36:38.638378 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 16:36:38.641298 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 16:36:38.644916 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 16:36:38.651479 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 16:36:38.655201 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 16:36:38.658445 ===================================
6181 16:36:38.661320 LPDDR4 DRAM CONFIGURATION
6182 16:36:38.664964 ===================================
6183 16:36:38.665363 EX_ROW_EN[0] = 0x0
6184 16:36:38.667983 EX_ROW_EN[1] = 0x0
6185 16:36:38.668532 LP4Y_EN = 0x0
6186 16:36:38.671779 WORK_FSP = 0x0
6187 16:36:38.672195 WL = 0x2
6188 16:36:38.674740 RL = 0x2
6189 16:36:38.675171 BL = 0x2
6190 16:36:38.677718 RPST = 0x0
6191 16:36:38.678179 RD_PRE = 0x0
6192 16:36:38.681291 WR_PRE = 0x1
6193 16:36:38.681931 WR_PST = 0x0
6194 16:36:38.684762 DBI_WR = 0x0
6195 16:36:38.687632 DBI_RD = 0x0
6196 16:36:38.687847 OTF = 0x1
6197 16:36:38.691475 ===================================
6198 16:36:38.694395 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 16:36:38.698083 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 16:36:38.704290 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 16:36:38.708142 ===================================
6202 16:36:38.711248 LPDDR4 DRAM CONFIGURATION
6203 16:36:38.711459 ===================================
6204 16:36:38.714166 EX_ROW_EN[0] = 0x10
6205 16:36:38.717957 EX_ROW_EN[1] = 0x0
6206 16:36:38.718166 LP4Y_EN = 0x0
6207 16:36:38.720783 WORK_FSP = 0x0
6208 16:36:38.720993 WL = 0x2
6209 16:36:38.724375 RL = 0x2
6210 16:36:38.724584 BL = 0x2
6211 16:36:38.728197 RPST = 0x0
6212 16:36:38.728406 RD_PRE = 0x0
6213 16:36:38.731019 WR_PRE = 0x1
6214 16:36:38.731229 WR_PST = 0x0
6215 16:36:38.734662 DBI_WR = 0x0
6216 16:36:38.734871 DBI_RD = 0x0
6217 16:36:38.738274 OTF = 0x1
6218 16:36:38.740966 ===================================
6219 16:36:38.747809 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 16:36:38.751085 nWR fixed to 30
6221 16:36:38.754139 [ModeRegInit_LP4] CH0 RK0
6222 16:36:38.754354 [ModeRegInit_LP4] CH0 RK1
6223 16:36:38.757817 [ModeRegInit_LP4] CH1 RK0
6224 16:36:38.760802 [ModeRegInit_LP4] CH1 RK1
6225 16:36:38.761014 match AC timing 19
6226 16:36:38.767349 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 16:36:38.771085 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 16:36:38.774484 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 16:36:38.781078 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 16:36:38.784015 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 16:36:38.784230 ==
6232 16:36:38.787169 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 16:36:38.790814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 16:36:38.791026 ==
6235 16:36:38.797451 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 16:36:38.804036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6237 16:36:38.807133 [CA 0] Center 36 (8~64) winsize 57
6238 16:36:38.810981 [CA 1] Center 36 (8~64) winsize 57
6239 16:36:38.811195 [CA 2] Center 36 (8~64) winsize 57
6240 16:36:38.814122 [CA 3] Center 36 (8~64) winsize 57
6241 16:36:38.817801 [CA 4] Center 36 (8~64) winsize 57
6242 16:36:38.820964 [CA 5] Center 36 (8~64) winsize 57
6243 16:36:38.821175
6244 16:36:38.824065 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6245 16:36:38.827289
6246 16:36:38.831152 [CATrainingPosCal] consider 1 rank data
6247 16:36:38.831372 u2DelayCellTimex100 = 270/100 ps
6248 16:36:38.837245 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 16:36:38.840201 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 16:36:38.843935 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 16:36:38.847141 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 16:36:38.850155 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 16:36:38.854020 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 16:36:38.854239
6255 16:36:38.857089 CA PerBit enable=1, Macro0, CA PI delay=36
6256 16:36:38.857308
6257 16:36:38.860537 [CBTSetCACLKResult] CA Dly = 36
6258 16:36:38.863970 CS Dly: 1 (0~32)
6259 16:36:38.864186 ==
6260 16:36:38.867335 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 16:36:38.870531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 16:36:38.870761 ==
6263 16:36:38.877236 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 16:36:38.880493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6265 16:36:38.883810 [CA 0] Center 36 (8~64) winsize 57
6266 16:36:38.887195 [CA 1] Center 36 (8~64) winsize 57
6267 16:36:38.890603 [CA 2] Center 36 (8~64) winsize 57
6268 16:36:38.893456 [CA 3] Center 36 (8~64) winsize 57
6269 16:36:38.896925 [CA 4] Center 36 (8~64) winsize 57
6270 16:36:38.900519 [CA 5] Center 36 (8~64) winsize 57
6271 16:36:38.900616
6272 16:36:38.903450 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6273 16:36:38.903555
6274 16:36:38.907017 [CATrainingPosCal] consider 2 rank data
6275 16:36:38.910583 u2DelayCellTimex100 = 270/100 ps
6276 16:36:38.913910 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 16:36:38.917068 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 16:36:38.920170 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 16:36:38.923917 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 16:36:38.930677 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 16:36:38.933729 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 16:36:38.933917
6283 16:36:38.937493 CA PerBit enable=1, Macro0, CA PI delay=36
6284 16:36:38.937695
6285 16:36:38.940371 [CBTSetCACLKResult] CA Dly = 36
6286 16:36:38.940559 CS Dly: 1 (0~32)
6287 16:36:38.940705
6288 16:36:38.943584 ----->DramcWriteLeveling(PI) begin...
6289 16:36:38.943774 ==
6290 16:36:38.947419 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 16:36:38.953434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 16:36:38.953638 ==
6293 16:36:38.957310 Write leveling (Byte 0): 40 => 8
6294 16:36:38.957497 Write leveling (Byte 1): 40 => 8
6295 16:36:38.960369 DramcWriteLeveling(PI) end<-----
6296 16:36:38.960555
6297 16:36:38.963372 ==
6298 16:36:38.963559 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 16:36:38.970819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 16:36:38.971009 ==
6301 16:36:38.973820 [Gating] SW mode calibration
6302 16:36:38.980481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 16:36:38.983376 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 16:36:38.990515 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 16:36:38.993360 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 16:36:38.996769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 16:36:39.003324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 16:36:39.006861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 16:36:39.009794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 16:36:39.016305 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 16:36:39.020179 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 16:36:39.023337 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 16:36:39.026719 Total UI for P1: 0, mck2ui 16
6314 16:36:39.029832 best dqsien dly found for B0: ( 0, 14, 24)
6315 16:36:39.033325 Total UI for P1: 0, mck2ui 16
6316 16:36:39.036798 best dqsien dly found for B1: ( 0, 14, 24)
6317 16:36:39.039835 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 16:36:39.043536 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 16:36:39.043613
6320 16:36:39.046543 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 16:36:39.053362 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 16:36:39.053442 [Gating] SW calibration Done
6323 16:36:39.056390 ==
6324 16:36:39.056466 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 16:36:39.063200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 16:36:39.063278 ==
6327 16:36:39.063339 RX Vref Scan: 0
6328 16:36:39.063395
6329 16:36:39.066358 RX Vref 0 -> 0, step: 1
6330 16:36:39.066435
6331 16:36:39.070079 RX Delay -410 -> 252, step: 16
6332 16:36:39.072983 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6333 16:36:39.076726 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6334 16:36:39.083403 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6335 16:36:39.086401 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6336 16:36:39.090012 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6337 16:36:39.092730 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6338 16:36:39.099783 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6339 16:36:39.103357 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6340 16:36:39.106342 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6341 16:36:39.109912 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6342 16:36:39.116358 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6343 16:36:39.119373 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6344 16:36:39.123201 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6345 16:36:39.126216 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6346 16:36:39.133092 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6347 16:36:39.135994 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6348 16:36:39.136115 ==
6349 16:36:39.139478 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 16:36:39.142990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 16:36:39.143181 ==
6352 16:36:39.146331 DQS Delay:
6353 16:36:39.146476 DQS0 = 27, DQS1 = 35
6354 16:36:39.149667 DQM Delay:
6355 16:36:39.149832 DQM0 = 10, DQM1 = 12
6356 16:36:39.150003 DQ Delay:
6357 16:36:39.153004 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6358 16:36:39.156367 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6359 16:36:39.159481 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6360 16:36:39.162464 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6361 16:36:39.162793
6362 16:36:39.163037
6363 16:36:39.163348 ==
6364 16:36:39.166068 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 16:36:39.173058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 16:36:39.173477 ==
6367 16:36:39.173956
6368 16:36:39.174368
6369 16:36:39.174656 TX Vref Scan disable
6370 16:36:39.176147 == TX Byte 0 ==
6371 16:36:39.179930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 16:36:39.182945 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 16:36:39.186132 == TX Byte 1 ==
6374 16:36:39.189835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 16:36:39.192894 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 16:36:39.193297 ==
6377 16:36:39.196129 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 16:36:39.202544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 16:36:39.203166 ==
6380 16:36:39.203740
6381 16:36:39.204154
6382 16:36:39.204511 TX Vref Scan disable
6383 16:36:39.206406 == TX Byte 0 ==
6384 16:36:39.209372 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 16:36:39.213057 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 16:36:39.216139 == TX Byte 1 ==
6387 16:36:39.219662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 16:36:39.222697 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 16:36:39.223086
6390 16:36:39.226181 [DATLAT]
6391 16:36:39.227105 Freq=400, CH0 RK0
6392 16:36:39.227448
6393 16:36:39.228907 DATLAT Default: 0xf
6394 16:36:39.229354 0, 0xFFFF, sum = 0
6395 16:36:39.232257 1, 0xFFFF, sum = 0
6396 16:36:39.232666 2, 0xFFFF, sum = 0
6397 16:36:39.236143 3, 0xFFFF, sum = 0
6398 16:36:39.236669 4, 0xFFFF, sum = 0
6399 16:36:39.239217 5, 0xFFFF, sum = 0
6400 16:36:39.239609 6, 0xFFFF, sum = 0
6401 16:36:39.242156 7, 0xFFFF, sum = 0
6402 16:36:39.242568 8, 0xFFFF, sum = 0
6403 16:36:39.245792 9, 0xFFFF, sum = 0
6404 16:36:39.249433 10, 0xFFFF, sum = 0
6405 16:36:39.249908 11, 0xFFFF, sum = 0
6406 16:36:39.252325 12, 0xFFFF, sum = 0
6407 16:36:39.252805 13, 0x0, sum = 1
6408 16:36:39.255939 14, 0x0, sum = 2
6409 16:36:39.256454 15, 0x0, sum = 3
6410 16:36:39.258981 16, 0x0, sum = 4
6411 16:36:39.259373 best_step = 14
6412 16:36:39.259685
6413 16:36:39.260120 ==
6414 16:36:39.262908 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 16:36:39.265853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 16:36:39.266262 ==
6417 16:36:39.268751 RX Vref Scan: 1
6418 16:36:39.269138
6419 16:36:39.272504 RX Vref 0 -> 0, step: 1
6420 16:36:39.273025
6421 16:36:39.273336 RX Delay -311 -> 252, step: 8
6422 16:36:39.273664
6423 16:36:39.275814 Set Vref, RX VrefLevel [Byte0]: 57
6424 16:36:39.279160 [Byte1]: 46
6425 16:36:39.284407
6426 16:36:39.284907 Final RX Vref Byte 0 = 57 to rank0
6427 16:36:39.287836 Final RX Vref Byte 1 = 46 to rank0
6428 16:36:39.290943 Final RX Vref Byte 0 = 57 to rank1
6429 16:36:39.294016 Final RX Vref Byte 1 = 46 to rank1==
6430 16:36:39.297829 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 16:36:39.304480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 16:36:39.304992 ==
6433 16:36:39.305426 DQS Delay:
6434 16:36:39.307463 DQS0 = 28, DQS1 = 36
6435 16:36:39.307874 DQM Delay:
6436 16:36:39.308193 DQM0 = 10, DQM1 = 12
6437 16:36:39.311222 DQ Delay:
6438 16:36:39.313933 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6439 16:36:39.314332 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6440 16:36:39.317794 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6441 16:36:39.320856 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6442 16:36:39.321239
6443 16:36:39.321601
6444 16:36:39.331361 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2bf, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps
6445 16:36:39.334404 CH0 RK0: MR19=C0C, MR18=D2BF
6446 16:36:39.341189 CH0_RK0: MR19=0xC0C, MR18=0xD2BF, DQSOSC=383, MR23=63, INC=402, DEC=268
6447 16:36:39.341635 ==
6448 16:36:39.344081 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 16:36:39.347683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 16:36:39.348072 ==
6451 16:36:39.351087 [Gating] SW mode calibration
6452 16:36:39.357954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 16:36:39.360533 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 16:36:39.367729 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 16:36:39.370784 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 16:36:39.374535 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 16:36:39.380491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 16:36:39.384289 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 16:36:39.387848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 16:36:39.394229 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 16:36:39.397535 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 16:36:39.401038 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 16:36:39.403707 Total UI for P1: 0, mck2ui 16
6464 16:36:39.407131 best dqsien dly found for B0: ( 0, 14, 24)
6465 16:36:39.410366 Total UI for P1: 0, mck2ui 16
6466 16:36:39.414006 best dqsien dly found for B1: ( 0, 14, 24)
6467 16:36:39.417688 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 16:36:39.420468 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 16:36:39.420938
6470 16:36:39.427549 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 16:36:39.430572 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 16:36:39.434272 [Gating] SW calibration Done
6473 16:36:39.434663 ==
6474 16:36:39.437256 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 16:36:39.440393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 16:36:39.440790 ==
6477 16:36:39.441120 RX Vref Scan: 0
6478 16:36:39.441426
6479 16:36:39.444234 RX Vref 0 -> 0, step: 1
6480 16:36:39.444626
6481 16:36:39.447189 RX Delay -410 -> 252, step: 16
6482 16:36:39.451079 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6483 16:36:39.457094 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6484 16:36:39.460766 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6485 16:36:39.463679 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6486 16:36:39.467163 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6487 16:36:39.470654 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6488 16:36:39.477158 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6489 16:36:39.480590 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6490 16:36:39.484220 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6491 16:36:39.487139 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6492 16:36:39.494049 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6493 16:36:39.496870 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6494 16:36:39.500872 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6495 16:36:39.507452 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6496 16:36:39.510207 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6497 16:36:39.513887 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6498 16:36:39.514274 ==
6499 16:36:39.517427 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 16:36:39.520332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 16:36:39.520720 ==
6502 16:36:39.523732 DQS Delay:
6503 16:36:39.524129 DQS0 = 27, DQS1 = 35
6504 16:36:39.527132 DQM Delay:
6505 16:36:39.527520 DQM0 = 12, DQM1 = 13
6506 16:36:39.530437 DQ Delay:
6507 16:36:39.530828 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6508 16:36:39.533855 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6509 16:36:39.537431 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6510 16:36:39.540322 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6511 16:36:39.540713
6512 16:36:39.541040
6513 16:36:39.541323 ==
6514 16:36:39.544102 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 16:36:39.549979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 16:36:39.550374 ==
6517 16:36:39.550755
6518 16:36:39.551149
6519 16:36:39.551561 TX Vref Scan disable
6520 16:36:39.553698 == TX Byte 0 ==
6521 16:36:39.556668 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 16:36:39.560394 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 16:36:39.563535 == TX Byte 1 ==
6524 16:36:39.566984 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6525 16:36:39.569806 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6526 16:36:39.570150 ==
6527 16:36:39.573287 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 16:36:39.580179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 16:36:39.580581 ==
6530 16:36:39.580922
6531 16:36:39.581204
6532 16:36:39.581466 TX Vref Scan disable
6533 16:36:39.583853 == TX Byte 0 ==
6534 16:36:39.586861 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 16:36:39.590498 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 16:36:39.593165 == TX Byte 1 ==
6537 16:36:39.596737 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6538 16:36:39.600302 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6539 16:36:39.600694
6540 16:36:39.603259 [DATLAT]
6541 16:36:39.603647 Freq=400, CH0 RK1
6542 16:36:39.603953
6543 16:36:39.606493 DATLAT Default: 0xe
6544 16:36:39.606882 0, 0xFFFF, sum = 0
6545 16:36:39.610388 1, 0xFFFF, sum = 0
6546 16:36:39.610782 2, 0xFFFF, sum = 0
6547 16:36:39.613272 3, 0xFFFF, sum = 0
6548 16:36:39.613698 4, 0xFFFF, sum = 0
6549 16:36:39.616749 5, 0xFFFF, sum = 0
6550 16:36:39.617142 6, 0xFFFF, sum = 0
6551 16:36:39.619386 7, 0xFFFF, sum = 0
6552 16:36:39.619463 8, 0xFFFF, sum = 0
6553 16:36:39.623197 9, 0xFFFF, sum = 0
6554 16:36:39.626145 10, 0xFFFF, sum = 0
6555 16:36:39.626229 11, 0xFFFF, sum = 0
6556 16:36:39.629969 12, 0xFFFF, sum = 0
6557 16:36:39.630045 13, 0x0, sum = 1
6558 16:36:39.632863 14, 0x0, sum = 2
6559 16:36:39.632939 15, 0x0, sum = 3
6560 16:36:39.633018 16, 0x0, sum = 4
6561 16:36:39.636485 best_step = 14
6562 16:36:39.636560
6563 16:36:39.636619 ==
6564 16:36:39.639355 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 16:36:39.642890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 16:36:39.642966 ==
6567 16:36:39.646345 RX Vref Scan: 0
6568 16:36:39.646420
6569 16:36:39.646479 RX Vref 0 -> 0, step: 1
6570 16:36:39.649751
6571 16:36:39.649826 RX Delay -311 -> 252, step: 8
6572 16:36:39.657906 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6573 16:36:39.660874 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6574 16:36:39.664607 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6575 16:36:39.667508 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6576 16:36:39.674432 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6577 16:36:39.677883 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6578 16:36:39.680782 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6579 16:36:39.684599 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6580 16:36:39.691164 iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440
6581 16:36:39.694148 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6582 16:36:39.697960 iDelay=217, Bit 10, Center -20 (-231 ~ 192) 424
6583 16:36:39.700774 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6584 16:36:39.707352 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6585 16:36:39.710799 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6586 16:36:39.714275 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6587 16:36:39.720876 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6588 16:36:39.720948 ==
6589 16:36:39.724338 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 16:36:39.727332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 16:36:39.727399 ==
6592 16:36:39.727454 DQS Delay:
6593 16:36:39.730999 DQS0 = 24, DQS1 = 36
6594 16:36:39.731064 DQM Delay:
6595 16:36:39.734068 DQM0 = 8, DQM1 = 12
6596 16:36:39.734131 DQ Delay:
6597 16:36:39.737193 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =8
6598 16:36:39.741063 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6599 16:36:39.744008 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6600 16:36:39.747573 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6601 16:36:39.747662
6602 16:36:39.747742
6603 16:36:39.754238 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf60, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6604 16:36:39.757297 CH0 RK1: MR19=C0C, MR18=BF60
6605 16:36:39.764150 CH0_RK1: MR19=0xC0C, MR18=0xBF60, DQSOSC=386, MR23=63, INC=396, DEC=264
6606 16:36:39.766847 [RxdqsGatingPostProcess] freq 400
6607 16:36:39.773988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 16:36:39.774087 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 16:36:39.777013 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 16:36:39.780699 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 16:36:39.784298 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 16:36:39.787273 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 16:36:39.790336 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 16:36:39.793876 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 16:36:39.797585 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 16:36:39.800585 Pre-setting of DQS Precalculation
6617 16:36:39.804313 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 16:36:39.807177 ==
6619 16:36:39.810328 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 16:36:39.813689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 16:36:39.813795 ==
6622 16:36:39.817348 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 16:36:39.823798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 16:36:39.826669 [CA 0] Center 36 (8~64) winsize 57
6625 16:36:39.830244 [CA 1] Center 36 (8~64) winsize 57
6626 16:36:39.833930 [CA 2] Center 36 (8~64) winsize 57
6627 16:36:39.836765 [CA 3] Center 36 (8~64) winsize 57
6628 16:36:39.840380 [CA 4] Center 36 (8~64) winsize 57
6629 16:36:39.843467 [CA 5] Center 36 (8~64) winsize 57
6630 16:36:39.843558
6631 16:36:39.847232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 16:36:39.847299
6633 16:36:39.850355 [CATrainingPosCal] consider 1 rank data
6634 16:36:39.853420 u2DelayCellTimex100 = 270/100 ps
6635 16:36:39.857190 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 16:36:39.860286 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 16:36:39.863306 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 16:36:39.866356 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 16:36:39.873107 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 16:36:39.876655 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 16:36:39.876723
6642 16:36:39.880187 CA PerBit enable=1, Macro0, CA PI delay=36
6643 16:36:39.880274
6644 16:36:39.882952 [CBTSetCACLKResult] CA Dly = 36
6645 16:36:39.883042 CS Dly: 1 (0~32)
6646 16:36:39.883123 ==
6647 16:36:39.886719 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 16:36:39.893156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 16:36:39.893248 ==
6650 16:36:39.896915 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 16:36:39.903532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6652 16:36:39.906484 [CA 0] Center 36 (8~64) winsize 57
6653 16:36:39.910290 [CA 1] Center 36 (8~64) winsize 57
6654 16:36:39.913346 [CA 2] Center 36 (8~64) winsize 57
6655 16:36:39.916402 [CA 3] Center 36 (8~64) winsize 57
6656 16:36:39.920294 [CA 4] Center 36 (8~64) winsize 57
6657 16:36:39.923282 [CA 5] Center 36 (8~64) winsize 57
6658 16:36:39.923360
6659 16:36:39.926337 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6660 16:36:39.926414
6661 16:36:39.929924 [CATrainingPosCal] consider 2 rank data
6662 16:36:39.932991 u2DelayCellTimex100 = 270/100 ps
6663 16:36:39.936688 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 16:36:39.939538 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 16:36:39.943125 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 16:36:39.946617 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 16:36:39.950082 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 16:36:39.953163 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 16:36:39.953264
6670 16:36:39.960052 CA PerBit enable=1, Macro0, CA PI delay=36
6671 16:36:39.960146
6672 16:36:39.960230 [CBTSetCACLKResult] CA Dly = 36
6673 16:36:39.962961 CS Dly: 1 (0~32)
6674 16:36:39.963056
6675 16:36:39.966735 ----->DramcWriteLeveling(PI) begin...
6676 16:36:39.966824 ==
6677 16:36:39.969772 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 16:36:39.973295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 16:36:39.973383 ==
6680 16:36:39.976342 Write leveling (Byte 0): 40 => 8
6681 16:36:39.980155 Write leveling (Byte 1): 40 => 8
6682 16:36:39.983096 DramcWriteLeveling(PI) end<-----
6683 16:36:39.983165
6684 16:36:39.983252 ==
6685 16:36:39.986075 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 16:36:39.989692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 16:36:39.992987 ==
6688 16:36:39.993050 [Gating] SW mode calibration
6689 16:36:39.999317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 16:36:40.006217 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 16:36:40.009512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 16:36:40.015891 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 16:36:40.019541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 16:36:40.022539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 16:36:40.029269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 16:36:40.032976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 16:36:40.035774 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 16:36:40.042990 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 16:36:40.045785 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 16:36:40.049436 Total UI for P1: 0, mck2ui 16
6701 16:36:40.052999 best dqsien dly found for B0: ( 0, 14, 24)
6702 16:36:40.055929 Total UI for P1: 0, mck2ui 16
6703 16:36:40.059395 best dqsien dly found for B1: ( 0, 14, 24)
6704 16:36:40.062527 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 16:36:40.066109 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 16:36:40.066214
6707 16:36:40.068980 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 16:36:40.072652 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 16:36:40.075581 [Gating] SW calibration Done
6710 16:36:40.075712 ==
6711 16:36:40.079323 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 16:36:40.082212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 16:36:40.086033 ==
6714 16:36:40.086104 RX Vref Scan: 0
6715 16:36:40.086161
6716 16:36:40.089021 RX Vref 0 -> 0, step: 1
6717 16:36:40.089083
6718 16:36:40.092707 RX Delay -410 -> 252, step: 16
6719 16:36:40.095776 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6720 16:36:40.099302 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6721 16:36:40.102796 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6722 16:36:40.109354 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6723 16:36:40.112236 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6724 16:36:40.115905 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6725 16:36:40.119475 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6726 16:36:40.125988 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6727 16:36:40.128871 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6728 16:36:40.132573 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6729 16:36:40.135686 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6730 16:36:40.142299 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6731 16:36:40.145972 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6732 16:36:40.148806 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6733 16:36:40.152272 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6734 16:36:40.159034 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6735 16:36:40.159126 ==
6736 16:36:40.161978 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 16:36:40.165512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 16:36:40.165622 ==
6739 16:36:40.165677 DQS Delay:
6740 16:36:40.169074 DQS0 = 35, DQS1 = 35
6741 16:36:40.169160 DQM Delay:
6742 16:36:40.171974 DQM0 = 18, DQM1 = 12
6743 16:36:40.172058 DQ Delay:
6744 16:36:40.175663 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6745 16:36:40.178619 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6746 16:36:40.182365 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6747 16:36:40.185338 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6748 16:36:40.185398
6749 16:36:40.185450
6750 16:36:40.185500 ==
6751 16:36:40.189034 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 16:36:40.192076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 16:36:40.192161 ==
6754 16:36:40.195784
6755 16:36:40.195866
6756 16:36:40.195945 TX Vref Scan disable
6757 16:36:40.198874 == TX Byte 0 ==
6758 16:36:40.201958 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 16:36:40.205669 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 16:36:40.208410 == TX Byte 1 ==
6761 16:36:40.211885 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 16:36:40.215474 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 16:36:40.215560 ==
6764 16:36:40.219187 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 16:36:40.222264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 16:36:40.222352 ==
6767 16:36:40.225232
6768 16:36:40.225320
6769 16:36:40.225400 TX Vref Scan disable
6770 16:36:40.228981 == TX Byte 0 ==
6771 16:36:40.231863 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 16:36:40.235590 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 16:36:40.238536 == TX Byte 1 ==
6774 16:36:40.242227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 16:36:40.245791 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 16:36:40.245882
6777 16:36:40.245964 [DATLAT]
6778 16:36:40.248747 Freq=400, CH1 RK0
6779 16:36:40.248811
6780 16:36:40.252234 DATLAT Default: 0xf
6781 16:36:40.252320 0, 0xFFFF, sum = 0
6782 16:36:40.255711 1, 0xFFFF, sum = 0
6783 16:36:40.255801 2, 0xFFFF, sum = 0
6784 16:36:40.258509 3, 0xFFFF, sum = 0
6785 16:36:40.258602 4, 0xFFFF, sum = 0
6786 16:36:40.262085 5, 0xFFFF, sum = 0
6787 16:36:40.262178 6, 0xFFFF, sum = 0
6788 16:36:40.265499 7, 0xFFFF, sum = 0
6789 16:36:40.265618 8, 0xFFFF, sum = 0
6790 16:36:40.268572 9, 0xFFFF, sum = 0
6791 16:36:40.268642 10, 0xFFFF, sum = 0
6792 16:36:40.272297 11, 0xFFFF, sum = 0
6793 16:36:40.272389 12, 0xFFFF, sum = 0
6794 16:36:40.275222 13, 0x0, sum = 1
6795 16:36:40.275414 14, 0x0, sum = 2
6796 16:36:40.278261 15, 0x0, sum = 3
6797 16:36:40.278363 16, 0x0, sum = 4
6798 16:36:40.282008 best_step = 14
6799 16:36:40.282112
6800 16:36:40.282174 ==
6801 16:36:40.284865 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 16:36:40.288629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 16:36:40.288713 ==
6804 16:36:40.291631 RX Vref Scan: 1
6805 16:36:40.291710
6806 16:36:40.291769 RX Vref 0 -> 0, step: 1
6807 16:36:40.291824
6808 16:36:40.295332 RX Delay -311 -> 252, step: 8
6809 16:36:40.295408
6810 16:36:40.298309 Set Vref, RX VrefLevel [Byte0]: 55
6811 16:36:40.301405 [Byte1]: 53
6812 16:36:40.305917
6813 16:36:40.305994 Final RX Vref Byte 0 = 55 to rank0
6814 16:36:40.309028 Final RX Vref Byte 1 = 53 to rank0
6815 16:36:40.312798 Final RX Vref Byte 0 = 55 to rank1
6816 16:36:40.315739 Final RX Vref Byte 1 = 53 to rank1==
6817 16:36:40.319337 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 16:36:40.326136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 16:36:40.326240 ==
6820 16:36:40.326326 DQS Delay:
6821 16:36:40.329560 DQS0 = 28, DQS1 = 32
6822 16:36:40.329669 DQM Delay:
6823 16:36:40.329729 DQM0 = 10, DQM1 = 10
6824 16:36:40.332367 DQ Delay:
6825 16:36:40.335879 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6826 16:36:40.335958 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6827 16:36:40.339563 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6828 16:36:40.342506 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6829 16:36:40.342580
6830 16:36:40.342638
6831 16:36:40.352869 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6832 16:36:40.355818 CH1 RK0: MR19=C0C, MR18=94CC
6833 16:36:40.362457 CH1_RK0: MR19=0xC0C, MR18=0x94CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6834 16:36:40.362545 ==
6835 16:36:40.366008 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 16:36:40.369480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 16:36:40.369600 ==
6838 16:36:40.372266 [Gating] SW mode calibration
6839 16:36:40.379569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 16:36:40.382454 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 16:36:40.389016 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 16:36:40.392673 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 16:36:40.395663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 16:36:40.402543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 16:36:40.405443 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 16:36:40.409114 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 16:36:40.415844 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 16:36:40.418974 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 16:36:40.422712 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 16:36:40.425712 Total UI for P1: 0, mck2ui 16
6851 16:36:40.428703 best dqsien dly found for B0: ( 0, 14, 24)
6852 16:36:40.432223 Total UI for P1: 0, mck2ui 16
6853 16:36:40.435966 best dqsien dly found for B1: ( 0, 14, 24)
6854 16:36:40.438692 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 16:36:40.442337 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 16:36:40.442427
6857 16:36:40.448946 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 16:36:40.452554 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 16:36:40.456048 [Gating] SW calibration Done
6860 16:36:40.456125 ==
6861 16:36:40.458642 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 16:36:40.462316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 16:36:40.462401 ==
6864 16:36:40.462466 RX Vref Scan: 0
6865 16:36:40.462525
6866 16:36:40.465411 RX Vref 0 -> 0, step: 1
6867 16:36:40.465501
6868 16:36:40.469196 RX Delay -410 -> 252, step: 16
6869 16:36:40.472493 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6870 16:36:40.479526 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6871 16:36:40.482262 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6872 16:36:40.485968 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6873 16:36:40.488862 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6874 16:36:40.496027 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6875 16:36:40.499331 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6876 16:36:40.502225 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6877 16:36:40.505814 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6878 16:36:40.512665 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6879 16:36:40.515483 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6880 16:36:40.519055 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6881 16:36:40.522038 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6882 16:36:40.528753 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6883 16:36:40.532402 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6884 16:36:40.535401 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6885 16:36:40.535564 ==
6886 16:36:40.538446 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 16:36:40.542046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 16:36:40.544984 ==
6889 16:36:40.545093 DQS Delay:
6890 16:36:40.545177 DQS0 = 35, DQS1 = 35
6891 16:36:40.548690 DQM Delay:
6892 16:36:40.548775 DQM0 = 18, DQM1 = 14
6893 16:36:40.551545 DQ Delay:
6894 16:36:40.551633 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6895 16:36:40.555317 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6896 16:36:40.558314 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6897 16:36:40.562010 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6898 16:36:40.562101
6899 16:36:40.562162
6900 16:36:40.564930 ==
6901 16:36:40.568393 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 16:36:40.571803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 16:36:40.571896 ==
6904 16:36:40.571953
6905 16:36:40.572006
6906 16:36:40.575209 TX Vref Scan disable
6907 16:36:40.575291 == TX Byte 0 ==
6908 16:36:40.578204 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 16:36:40.584821 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 16:36:40.584916 == TX Byte 1 ==
6911 16:36:40.588327 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 16:36:40.594846 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 16:36:40.594944 ==
6914 16:36:40.598388 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 16:36:40.601336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 16:36:40.601444 ==
6917 16:36:40.601530
6918 16:36:40.601631
6919 16:36:40.604868 TX Vref Scan disable
6920 16:36:40.604948 == TX Byte 0 ==
6921 16:36:40.608266 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 16:36:40.614605 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 16:36:40.614714 == TX Byte 1 ==
6924 16:36:40.618416 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 16:36:40.624377 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 16:36:40.624471
6927 16:36:40.624531 [DATLAT]
6928 16:36:40.624586 Freq=400, CH1 RK1
6929 16:36:40.624638
6930 16:36:40.628141 DATLAT Default: 0xe
6931 16:36:40.631062 0, 0xFFFF, sum = 0
6932 16:36:40.631142 1, 0xFFFF, sum = 0
6933 16:36:40.634703 2, 0xFFFF, sum = 0
6934 16:36:40.634793 3, 0xFFFF, sum = 0
6935 16:36:40.637716 4, 0xFFFF, sum = 0
6936 16:36:40.637801 5, 0xFFFF, sum = 0
6937 16:36:40.641255 6, 0xFFFF, sum = 0
6938 16:36:40.641362 7, 0xFFFF, sum = 0
6939 16:36:40.644893 8, 0xFFFF, sum = 0
6940 16:36:40.645001 9, 0xFFFF, sum = 0
6941 16:36:40.647748 10, 0xFFFF, sum = 0
6942 16:36:40.647853 11, 0xFFFF, sum = 0
6943 16:36:40.651354 12, 0xFFFF, sum = 0
6944 16:36:40.651446 13, 0x0, sum = 1
6945 16:36:40.654275 14, 0x0, sum = 2
6946 16:36:40.654380 15, 0x0, sum = 3
6947 16:36:40.657943 16, 0x0, sum = 4
6948 16:36:40.658025 best_step = 14
6949 16:36:40.658114
6950 16:36:40.658169 ==
6951 16:36:40.661437 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 16:36:40.664537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 16:36:40.667618 ==
6954 16:36:40.667694 RX Vref Scan: 0
6955 16:36:40.667753
6956 16:36:40.671355 RX Vref 0 -> 0, step: 1
6957 16:36:40.671430
6958 16:36:40.674332 RX Delay -311 -> 252, step: 8
6959 16:36:40.680960 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6960 16:36:40.684220 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6961 16:36:40.687701 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6962 16:36:40.690617 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6963 16:36:40.697798 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6964 16:36:40.700884 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6965 16:36:40.704069 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6966 16:36:40.707977 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6967 16:36:40.710989 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6968 16:36:40.717415 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6969 16:36:40.721030 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6970 16:36:40.724441 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6971 16:36:40.730617 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6972 16:36:40.734348 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6973 16:36:40.737489 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6974 16:36:40.740575 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6975 16:36:40.740641 ==
6976 16:36:40.744244 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 16:36:40.750895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 16:36:40.750973 ==
6979 16:36:40.751033 DQS Delay:
6980 16:36:40.753762 DQS0 = 28, DQS1 = 36
6981 16:36:40.753894 DQM Delay:
6982 16:36:40.754031 DQM0 = 11, DQM1 = 14
6983 16:36:40.757462 DQ Delay:
6984 16:36:40.760416 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6985 16:36:40.764069 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6986 16:36:40.764146 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6987 16:36:40.767767 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6988 16:36:40.770777
6989 16:36:40.770852
6990 16:36:40.776918 [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6991 16:36:40.780595 CH1 RK1: MR19=C0C, MR18=C758
6992 16:36:40.787490 CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265
6993 16:36:40.790537 [RxdqsGatingPostProcess] freq 400
6994 16:36:40.794182 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 16:36:40.797543 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 16:36:40.800302 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 16:36:40.803656 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 16:36:40.807055 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 16:36:40.810806 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 16:36:40.813835 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 16:36:40.816863 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 16:36:40.820580 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 16:36:40.823632 Pre-setting of DQS Precalculation
7004 16:36:40.827235 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 16:36:40.837277 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 16:36:40.843705 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 16:36:40.843789
7008 16:36:40.843851
7009 16:36:40.846897 [Calibration Summary] 800 Mbps
7010 16:36:40.846999 CH 0, Rank 0
7011 16:36:40.850739 SW Impedance : PASS
7012 16:36:40.851127 DUTY Scan : NO K
7013 16:36:40.853768 ZQ Calibration : PASS
7014 16:36:40.857252 Jitter Meter : NO K
7015 16:36:40.857788 CBT Training : PASS
7016 16:36:40.860769 Write leveling : PASS
7017 16:36:40.861158 RX DQS gating : PASS
7018 16:36:40.863750 RX DQ/DQS(RDDQC) : PASS
7019 16:36:40.867389 TX DQ/DQS : PASS
7020 16:36:40.867785 RX DATLAT : PASS
7021 16:36:40.870502 RX DQ/DQS(Engine): PASS
7022 16:36:40.874055 TX OE : NO K
7023 16:36:40.874482 All Pass.
7024 16:36:40.874797
7025 16:36:40.875081 CH 0, Rank 1
7026 16:36:40.877085 SW Impedance : PASS
7027 16:36:40.880758 DUTY Scan : NO K
7028 16:36:40.881144 ZQ Calibration : PASS
7029 16:36:40.883789 Jitter Meter : NO K
7030 16:36:40.887646 CBT Training : PASS
7031 16:36:40.888072 Write leveling : NO K
7032 16:36:40.890667 RX DQS gating : PASS
7033 16:36:40.894438 RX DQ/DQS(RDDQC) : PASS
7034 16:36:40.894901 TX DQ/DQS : PASS
7035 16:36:40.897347 RX DATLAT : PASS
7036 16:36:40.900355 RX DQ/DQS(Engine): PASS
7037 16:36:40.900805 TX OE : NO K
7038 16:36:40.901282 All Pass.
7039 16:36:40.904239
7040 16:36:40.904622 CH 1, Rank 0
7041 16:36:40.904919 SW Impedance : PASS
7042 16:36:40.907628 DUTY Scan : NO K
7043 16:36:40.910514 ZQ Calibration : PASS
7044 16:36:40.910950 Jitter Meter : NO K
7045 16:36:40.913882 CBT Training : PASS
7046 16:36:40.917588 Write leveling : PASS
7047 16:36:40.917978 RX DQS gating : PASS
7048 16:36:40.920333 RX DQ/DQS(RDDQC) : PASS
7049 16:36:40.924291 TX DQ/DQS : PASS
7050 16:36:40.924685 RX DATLAT : PASS
7051 16:36:40.927402 RX DQ/DQS(Engine): PASS
7052 16:36:40.930469 TX OE : NO K
7053 16:36:40.930940 All Pass.
7054 16:36:40.931303
7055 16:36:40.931590 CH 1, Rank 1
7056 16:36:40.933524 SW Impedance : PASS
7057 16:36:40.937309 DUTY Scan : NO K
7058 16:36:40.937832 ZQ Calibration : PASS
7059 16:36:40.940217 Jitter Meter : NO K
7060 16:36:40.943902 CBT Training : PASS
7061 16:36:40.944371 Write leveling : NO K
7062 16:36:40.946851 RX DQS gating : PASS
7063 16:36:40.950458 RX DQ/DQS(RDDQC) : PASS
7064 16:36:40.950941 TX DQ/DQS : PASS
7065 16:36:40.953508 RX DATLAT : PASS
7066 16:36:40.957110 RX DQ/DQS(Engine): PASS
7067 16:36:40.957656 TX OE : NO K
7068 16:36:40.957977 All Pass.
7069 16:36:40.959876
7070 16:36:40.960265 DramC Write-DBI off
7071 16:36:40.963543 PER_BANK_REFRESH: Hybrid Mode
7072 16:36:40.963932 TX_TRACKING: ON
7073 16:36:40.973409 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 16:36:40.976877 [FAST_K] Save calibration result to emmc
7075 16:36:40.980299 dramc_set_vcore_voltage set vcore to 725000
7076 16:36:40.983265 Read voltage for 1600, 0
7077 16:36:40.983656 Vio18 = 0
7078 16:36:40.986863 Vcore = 725000
7079 16:36:40.987275 Vdram = 0
7080 16:36:40.987601 Vddq = 0
7081 16:36:40.987887 Vmddr = 0
7082 16:36:40.993690 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 16:36:40.999822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 16:36:41.000337 MEM_TYPE=3, freq_sel=13
7085 16:36:41.003511 sv_algorithm_assistance_LP4_3733
7086 16:36:41.006497 ============ PULL DRAM RESETB DOWN ============
7087 16:36:41.013284 ========== PULL DRAM RESETB DOWN end =========
7088 16:36:41.017003 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 16:36:41.019676 ===================================
7090 16:36:41.023342 LPDDR4 DRAM CONFIGURATION
7091 16:36:41.026479 ===================================
7092 16:36:41.026963 EX_ROW_EN[0] = 0x0
7093 16:36:41.029937 EX_ROW_EN[1] = 0x0
7094 16:36:41.030328 LP4Y_EN = 0x0
7095 16:36:41.033485 WORK_FSP = 0x1
7096 16:36:41.036767 WL = 0x5
7097 16:36:41.037249 RL = 0x5
7098 16:36:41.039593 BL = 0x2
7099 16:36:41.039984 RPST = 0x0
7100 16:36:41.043477 RD_PRE = 0x0
7101 16:36:41.043889 WR_PRE = 0x1
7102 16:36:41.046519 WR_PST = 0x1
7103 16:36:41.046909 DBI_WR = 0x0
7104 16:36:41.049456 DBI_RD = 0x0
7105 16:36:41.049881 OTF = 0x1
7106 16:36:41.053183 ===================================
7107 16:36:41.056262 ===================================
7108 16:36:41.059900 ANA top config
7109 16:36:41.062912 ===================================
7110 16:36:41.063315 DLL_ASYNC_EN = 0
7111 16:36:41.065962 ALL_SLAVE_EN = 0
7112 16:36:41.069523 NEW_RANK_MODE = 1
7113 16:36:41.073071 DLL_IDLE_MODE = 1
7114 16:36:41.073458 LP45_APHY_COMB_EN = 1
7115 16:36:41.075859 TX_ODT_DIS = 0
7116 16:36:41.079589 NEW_8X_MODE = 1
7117 16:36:41.082837 ===================================
7118 16:36:41.086236 ===================================
7119 16:36:41.089174 data_rate = 3200
7120 16:36:41.092529 CKR = 1
7121 16:36:41.096023 DQ_P2S_RATIO = 8
7122 16:36:41.099475 ===================================
7123 16:36:41.099922 CA_P2S_RATIO = 8
7124 16:36:41.102220 DQ_CA_OPEN = 0
7125 16:36:41.106013 DQ_SEMI_OPEN = 0
7126 16:36:41.109679 CA_SEMI_OPEN = 0
7127 16:36:41.112620 CA_FULL_RATE = 0
7128 16:36:41.115509 DQ_CKDIV4_EN = 0
7129 16:36:41.115991 CA_CKDIV4_EN = 0
7130 16:36:41.119403 CA_PREDIV_EN = 0
7131 16:36:41.122327 PH8_DLY = 12
7132 16:36:41.125228 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 16:36:41.129005 DQ_AAMCK_DIV = 4
7134 16:36:41.131972 CA_AAMCK_DIV = 4
7135 16:36:41.132267 CA_ADMCK_DIV = 4
7136 16:36:41.135685 DQ_TRACK_CA_EN = 0
7137 16:36:41.139162 CA_PICK = 1600
7138 16:36:41.141983 CA_MCKIO = 1600
7139 16:36:41.145498 MCKIO_SEMI = 0
7140 16:36:41.148994 PLL_FREQ = 3068
7141 16:36:41.152323 DQ_UI_PI_RATIO = 32
7142 16:36:41.155569 CA_UI_PI_RATIO = 0
7143 16:36:41.159160 ===================================
7144 16:36:41.162087 ===================================
7145 16:36:41.162364 memory_type:LPDDR4
7146 16:36:41.165769 GP_NUM : 10
7147 16:36:41.166058 SRAM_EN : 1
7148 16:36:41.168643 MD32_EN : 0
7149 16:36:41.172474 ===================================
7150 16:36:41.175586 [ANA_INIT] >>>>>>>>>>>>>>
7151 16:36:41.178648 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 16:36:41.182309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 16:36:41.185220 ===================================
7154 16:36:41.185499 data_rate = 3200,PCW = 0X7600
7155 16:36:41.189027 ===================================
7156 16:36:41.191924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 16:36:41.198811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 16:36:41.205313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 16:36:41.208774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 16:36:41.212280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 16:36:41.215087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 16:36:41.218738 [ANA_INIT] flow start
7163 16:36:41.222367 [ANA_INIT] PLL >>>>>>>>
7164 16:36:41.222707 [ANA_INIT] PLL <<<<<<<<
7165 16:36:41.225470 [ANA_INIT] MIDPI >>>>>>>>
7166 16:36:41.228401 [ANA_INIT] MIDPI <<<<<<<<
7167 16:36:41.228675 [ANA_INIT] DLL >>>>>>>>
7168 16:36:41.232273 [ANA_INIT] DLL <<<<<<<<
7169 16:36:41.235130 [ANA_INIT] flow end
7170 16:36:41.238840 ============ LP4 DIFF to SE enter ============
7171 16:36:41.241735 ============ LP4 DIFF to SE exit ============
7172 16:36:41.245162 [ANA_INIT] <<<<<<<<<<<<<
7173 16:36:41.248195 [Flow] Enable top DCM control >>>>>
7174 16:36:41.251903 [Flow] Enable top DCM control <<<<<
7175 16:36:41.254830 Enable DLL master slave shuffle
7176 16:36:41.258514 ==============================================================
7177 16:36:41.261794 Gating Mode config
7178 16:36:41.268599 ==============================================================
7179 16:36:41.269161 Config description:
7180 16:36:41.278595 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 16:36:41.285186 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 16:36:41.288248 SELPH_MODE 0: By rank 1: By Phase
7183 16:36:41.295315 ==============================================================
7184 16:36:41.298478 GAT_TRACK_EN = 1
7185 16:36:41.301347 RX_GATING_MODE = 2
7186 16:36:41.304517 RX_GATING_TRACK_MODE = 2
7187 16:36:41.308029 SELPH_MODE = 1
7188 16:36:41.311640 PICG_EARLY_EN = 1
7189 16:36:41.314765 VALID_LAT_VALUE = 1
7190 16:36:41.318456 ==============================================================
7191 16:36:41.321294 Enter into Gating configuration >>>>
7192 16:36:41.324573 Exit from Gating configuration <<<<
7193 16:36:41.328254 Enter into DVFS_PRE_config >>>>>
7194 16:36:41.341076 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 16:36:41.341594 Exit from DVFS_PRE_config <<<<<
7196 16:36:41.344795 Enter into PICG configuration >>>>
7197 16:36:41.348641 Exit from PICG configuration <<<<
7198 16:36:41.351528 [RX_INPUT] configuration >>>>>
7199 16:36:41.354419 [RX_INPUT] configuration <<<<<
7200 16:36:41.361124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 16:36:41.364912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 16:36:41.371394 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 16:36:41.377747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 16:36:41.384977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 16:36:41.391120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 16:36:41.394706 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 16:36:41.397515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 16:36:41.401027 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 16:36:41.407451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 16:36:41.411322 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 16:36:41.414320 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 16:36:41.417873 ===================================
7213 16:36:41.420999 LPDDR4 DRAM CONFIGURATION
7214 16:36:41.424043 ===================================
7215 16:36:41.424424 EX_ROW_EN[0] = 0x0
7216 16:36:41.427671 EX_ROW_EN[1] = 0x0
7217 16:36:41.431091 LP4Y_EN = 0x0
7218 16:36:41.431462 WORK_FSP = 0x1
7219 16:36:41.434735 WL = 0x5
7220 16:36:41.435094 RL = 0x5
7221 16:36:41.437803 BL = 0x2
7222 16:36:41.438160 RPST = 0x0
7223 16:36:41.441442 RD_PRE = 0x0
7224 16:36:41.441842 WR_PRE = 0x1
7225 16:36:41.444542 WR_PST = 0x1
7226 16:36:41.444912 DBI_WR = 0x0
7227 16:36:41.447520 DBI_RD = 0x0
7228 16:36:41.447883 OTF = 0x1
7229 16:36:41.451176 ===================================
7230 16:36:41.454702 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 16:36:41.461160 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 16:36:41.463871 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 16:36:41.467727 ===================================
7234 16:36:41.470739 LPDDR4 DRAM CONFIGURATION
7235 16:36:41.474385 ===================================
7236 16:36:41.474759 EX_ROW_EN[0] = 0x10
7237 16:36:41.477259 EX_ROW_EN[1] = 0x0
7238 16:36:41.480885 LP4Y_EN = 0x0
7239 16:36:41.481162 WORK_FSP = 0x1
7240 16:36:41.483988 WL = 0x5
7241 16:36:41.484265 RL = 0x5
7242 16:36:41.487677 BL = 0x2
7243 16:36:41.487899 RPST = 0x0
7244 16:36:41.490647 RD_PRE = 0x0
7245 16:36:41.490822 WR_PRE = 0x1
7246 16:36:41.494187 WR_PST = 0x1
7247 16:36:41.494366 DBI_WR = 0x0
7248 16:36:41.497135 DBI_RD = 0x0
7249 16:36:41.497298 OTF = 0x1
7250 16:36:41.500705 ===================================
7251 16:36:41.507213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 16:36:41.507355 ==
7253 16:36:41.510013 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 16:36:41.513419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 16:36:41.516893 ==
7256 16:36:41.516972 [Duty_Offset_Calibration]
7257 16:36:41.520728 B0:2 B1:1 CA:1
7258 16:36:41.520805
7259 16:36:41.523606 [DutyScan_Calibration_Flow] k_type=0
7260 16:36:41.532645
7261 16:36:41.532723 ==CLK 0==
7262 16:36:41.535730 Final CLK duty delay cell = 0
7263 16:36:41.538601 [0] MAX Duty = 5156%(X100), DQS PI = 22
7264 16:36:41.542007 [0] MIN Duty = 4876%(X100), DQS PI = 48
7265 16:36:41.545738 [0] AVG Duty = 5016%(X100)
7266 16:36:41.545836
7267 16:36:41.548591 CH0 CLK Duty spec in!! Max-Min= 280%
7268 16:36:41.552440 [DutyScan_Calibration_Flow] ====Done====
7269 16:36:41.552547
7270 16:36:41.555393 [DutyScan_Calibration_Flow] k_type=1
7271 16:36:41.571815
7272 16:36:41.571934 ==DQS 0 ==
7273 16:36:41.575006 Final DQS duty delay cell = -4
7274 16:36:41.578552 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7275 16:36:41.581370 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7276 16:36:41.585070 [-4] AVG Duty = 4906%(X100)
7277 16:36:41.585365
7278 16:36:41.585603 ==DQS 1 ==
7279 16:36:41.588166 Final DQS duty delay cell = 0
7280 16:36:41.591759 [0] MAX Duty = 5187%(X100), DQS PI = 6
7281 16:36:41.595132 [0] MIN Duty = 5031%(X100), DQS PI = 52
7282 16:36:41.598674 [0] AVG Duty = 5109%(X100)
7283 16:36:41.598922
7284 16:36:41.601523 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7285 16:36:41.601816
7286 16:36:41.605375 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7287 16:36:41.608412 [DutyScan_Calibration_Flow] ====Done====
7288 16:36:41.608836
7289 16:36:41.612037 [DutyScan_Calibration_Flow] k_type=3
7290 16:36:41.629051
7291 16:36:41.629441 ==DQM 0 ==
7292 16:36:41.632590 Final DQM duty delay cell = 0
7293 16:36:41.635659 [0] MAX Duty = 5187%(X100), DQS PI = 32
7294 16:36:41.639385 [0] MIN Duty = 4875%(X100), DQS PI = 62
7295 16:36:41.642404 [0] AVG Duty = 5031%(X100)
7296 16:36:41.642810
7297 16:36:41.643116 ==DQM 1 ==
7298 16:36:41.646064 Final DQM duty delay cell = 0
7299 16:36:41.648935 [0] MAX Duty = 5187%(X100), DQS PI = 4
7300 16:36:41.652694 [0] MIN Duty = 5031%(X100), DQS PI = 50
7301 16:36:41.655455 [0] AVG Duty = 5109%(X100)
7302 16:36:41.655912
7303 16:36:41.659078 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7304 16:36:41.659611
7305 16:36:41.662101 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7306 16:36:41.665931 [DutyScan_Calibration_Flow] ====Done====
7307 16:36:41.666489
7308 16:36:41.668757 [DutyScan_Calibration_Flow] k_type=2
7309 16:36:41.686579
7310 16:36:41.686971 ==DQ 0 ==
7311 16:36:41.689629 Final DQ duty delay cell = 0
7312 16:36:41.693186 [0] MAX Duty = 5062%(X100), DQS PI = 26
7313 16:36:41.696148 [0] MIN Duty = 4907%(X100), DQS PI = 0
7314 16:36:41.696542 [0] AVG Duty = 4984%(X100)
7315 16:36:41.696847
7316 16:36:41.699775 ==DQ 1 ==
7317 16:36:41.702840 Final DQ duty delay cell = 0
7318 16:36:41.706392 [0] MAX Duty = 5125%(X100), DQS PI = 22
7319 16:36:41.709931 [0] MIN Duty = 4907%(X100), DQS PI = 34
7320 16:36:41.710325 [0] AVG Duty = 5016%(X100)
7321 16:36:41.710644
7322 16:36:41.712813 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7323 16:36:41.713240
7324 16:36:41.716360 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7325 16:36:41.723209 [DutyScan_Calibration_Flow] ====Done====
7326 16:36:41.723621 ==
7327 16:36:41.726161 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 16:36:41.729837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 16:36:41.730246 ==
7330 16:36:41.732839 [Duty_Offset_Calibration]
7331 16:36:41.733260 B0:1 B1:0 CA:0
7332 16:36:41.733603
7333 16:36:41.736574 [DutyScan_Calibration_Flow] k_type=0
7334 16:36:41.745629
7335 16:36:41.746021 ==CLK 0==
7336 16:36:41.749460 Final CLK duty delay cell = -4
7337 16:36:41.752227 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7338 16:36:41.755960 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7339 16:36:41.759001 [-4] AVG Duty = 4922%(X100)
7340 16:36:41.759395
7341 16:36:41.762687 CH1 CLK Duty spec in!! Max-Min= 156%
7342 16:36:41.765585 [DutyScan_Calibration_Flow] ====Done====
7343 16:36:41.765970
7344 16:36:41.768613 [DutyScan_Calibration_Flow] k_type=1
7345 16:36:41.785669
7346 16:36:41.785961 ==DQS 0 ==
7347 16:36:41.788668 Final DQS duty delay cell = 0
7348 16:36:41.792581 [0] MAX Duty = 5062%(X100), DQS PI = 8
7349 16:36:41.795357 [0] MIN Duty = 4844%(X100), DQS PI = 44
7350 16:36:41.799201 [0] AVG Duty = 4953%(X100)
7351 16:36:41.799486
7352 16:36:41.799710 ==DQS 1 ==
7353 16:36:41.802154 Final DQS duty delay cell = 0
7354 16:36:41.805136 [0] MAX Duty = 5249%(X100), DQS PI = 16
7355 16:36:41.808792 [0] MIN Duty = 4938%(X100), DQS PI = 8
7356 16:36:41.812307 [0] AVG Duty = 5093%(X100)
7357 16:36:41.812634
7358 16:36:41.815203 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7359 16:36:41.815478
7360 16:36:41.818325 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7361 16:36:41.822112 [DutyScan_Calibration_Flow] ====Done====
7362 16:36:41.822506
7363 16:36:41.825237 [DutyScan_Calibration_Flow] k_type=3
7364 16:36:41.842225
7365 16:36:41.842637 ==DQM 0 ==
7366 16:36:41.845944 Final DQM duty delay cell = 0
7367 16:36:41.848804 [0] MAX Duty = 5187%(X100), DQS PI = 10
7368 16:36:41.852096 [0] MIN Duty = 4969%(X100), DQS PI = 48
7369 16:36:41.855456 [0] AVG Duty = 5078%(X100)
7370 16:36:41.855532
7371 16:36:41.855590 ==DQM 1 ==
7372 16:36:41.858811 Final DQM duty delay cell = 0
7373 16:36:41.862052 [0] MAX Duty = 5093%(X100), DQS PI = 16
7374 16:36:41.865585 [0] MIN Duty = 4907%(X100), DQS PI = 34
7375 16:36:41.868450 [0] AVG Duty = 5000%(X100)
7376 16:36:41.868544
7377 16:36:41.871584 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7378 16:36:41.871651
7379 16:36:41.875301 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7380 16:36:41.878308 [DutyScan_Calibration_Flow] ====Done====
7381 16:36:41.878373
7382 16:36:41.882047 [DutyScan_Calibration_Flow] k_type=2
7383 16:36:41.898048
7384 16:36:41.898142 ==DQ 0 ==
7385 16:36:41.901716 Final DQ duty delay cell = -4
7386 16:36:41.904681 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7387 16:36:41.908502 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7388 16:36:41.911538 [-4] AVG Duty = 4937%(X100)
7389 16:36:41.911608
7390 16:36:41.911668 ==DQ 1 ==
7391 16:36:41.915147 Final DQ duty delay cell = 0
7392 16:36:41.918012 [0] MAX Duty = 5124%(X100), DQS PI = 16
7393 16:36:41.921809 [0] MIN Duty = 4938%(X100), DQS PI = 8
7394 16:36:41.924650 [0] AVG Duty = 5031%(X100)
7395 16:36:41.924719
7396 16:36:41.928396 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7397 16:36:41.928471
7398 16:36:41.931493 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7399 16:36:41.934575 [DutyScan_Calibration_Flow] ====Done====
7400 16:36:41.938117 nWR fixed to 30
7401 16:36:41.941097 [ModeRegInit_LP4] CH0 RK0
7402 16:36:41.941170 [ModeRegInit_LP4] CH0 RK1
7403 16:36:41.944996 [ModeRegInit_LP4] CH1 RK0
7404 16:36:41.947978 [ModeRegInit_LP4] CH1 RK1
7405 16:36:41.948069 match AC timing 5
7406 16:36:41.954601 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 16:36:41.957536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 16:36:41.961389 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 16:36:41.968031 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 16:36:41.970899 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 16:36:41.971026 [MiockJmeterHQA]
7412 16:36:41.971121
7413 16:36:41.974238 [DramcMiockJmeter] u1RxGatingPI = 0
7414 16:36:41.977651 0 : 4252, 4026
7415 16:36:41.977723 4 : 4253, 4027
7416 16:36:41.980817 8 : 4258, 4032
7417 16:36:41.980890 12 : 4365, 4140
7418 16:36:41.984498 16 : 4252, 4027
7419 16:36:41.984565 20 : 4253, 4026
7420 16:36:41.984700 24 : 4252, 4027
7421 16:36:41.987772 28 : 4253, 4026
7422 16:36:41.987839 32 : 4363, 4137
7423 16:36:41.990839 36 : 4252, 4027
7424 16:36:41.990910 40 : 4252, 4027
7425 16:36:41.994657 44 : 4250, 4027
7426 16:36:41.994744 48 : 4253, 4026
7427 16:36:41.997700 52 : 4252, 4027
7428 16:36:41.997781 56 : 4363, 4140
7429 16:36:41.997845 60 : 4363, 4138
7430 16:36:42.001170 64 : 4361, 4138
7431 16:36:42.001271 68 : 4252, 4029
7432 16:36:42.004646 72 : 4253, 4029
7433 16:36:42.004741 76 : 4250, 4027
7434 16:36:42.007293 80 : 4250, 4026
7435 16:36:42.007389 84 : 4361, 4137
7436 16:36:42.007463 88 : 4250, 73
7437 16:36:42.010668 92 : 4360, 0
7438 16:36:42.010817 96 : 4252, 0
7439 16:36:42.013848 100 : 4361, 0
7440 16:36:42.014003 104 : 4254, 0
7441 16:36:42.014085 108 : 4250, 0
7442 16:36:42.017136 112 : 4252, 0
7443 16:36:42.017251 116 : 4250, 0
7444 16:36:42.021223 120 : 4250, 0
7445 16:36:42.021740 124 : 4250, 0
7446 16:36:42.022056 128 : 4253, 0
7447 16:36:42.024293 132 : 4250, 0
7448 16:36:42.024685 136 : 4250, 0
7449 16:36:42.025051 140 : 4253, 0
7450 16:36:42.027861 144 : 4360, 0
7451 16:36:42.028305 148 : 4250, 0
7452 16:36:42.031004 152 : 4363, 0
7453 16:36:42.031567 156 : 4253, 0
7454 16:36:42.032128 160 : 4249, 0
7455 16:36:42.034372 164 : 4361, 0
7456 16:36:42.034971 168 : 4255, 0
7457 16:36:42.037603 172 : 4250, 0
7458 16:36:42.038074 176 : 4363, 0
7459 16:36:42.038394 180 : 4250, 0
7460 16:36:42.041313 184 : 4250, 0
7461 16:36:42.041750 188 : 4250, 0
7462 16:36:42.044429 192 : 4253, 0
7463 16:36:42.044894 196 : 4360, 0
7464 16:36:42.045432 200 : 4250, 0
7465 16:36:42.048065 204 : 4363, 1226
7466 16:36:42.048677 208 : 4250, 4000
7467 16:36:42.050773 212 : 4249, 4027
7468 16:36:42.051225 216 : 4250, 4027
7469 16:36:42.054164 220 : 4360, 4138
7470 16:36:42.054658 224 : 4253, 4029
7471 16:36:42.057938 228 : 4249, 4027
7472 16:36:42.058348 232 : 4254, 4030
7473 16:36:42.058678 236 : 4252, 4029
7474 16:36:42.060919 240 : 4255, 4029
7475 16:36:42.061323 244 : 4360, 4138
7476 16:36:42.064717 248 : 4363, 4138
7477 16:36:42.065195 252 : 4250, 4027
7478 16:36:42.067554 256 : 4255, 4029
7479 16:36:42.067954 260 : 4253, 4029
7480 16:36:42.071569 264 : 4250, 4027
7481 16:36:42.072050 268 : 4252, 4029
7482 16:36:42.074332 272 : 4363, 4140
7483 16:36:42.074732 276 : 4250, 4027
7484 16:36:42.077915 280 : 4250, 4027
7485 16:36:42.078315 284 : 4363, 4137
7486 16:36:42.080894 288 : 4250, 4027
7487 16:36:42.081293 292 : 4253, 4029
7488 16:36:42.081628 296 : 4360, 4138
7489 16:36:42.084810 300 : 4360, 4138
7490 16:36:42.085284 304 : 4250, 4027
7491 16:36:42.087582 308 : 4250, 3943
7492 16:36:42.087982 312 : 4253, 1940
7493 16:36:42.088318
7494 16:36:42.091053 MIOCK jitter meter ch=0
7495 16:36:42.091523
7496 16:36:42.094601 1T = (312-88) = 224 dly cells
7497 16:36:42.100937 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7498 16:36:42.101410 ==
7499 16:36:42.104491 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 16:36:42.107919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 16:36:42.108319 ==
7502 16:36:42.114587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 16:36:42.117800 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 16:36:42.120873 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 16:36:42.127526 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 16:36:42.136522 [CA 0] Center 42 (12~73) winsize 62
7507 16:36:42.139670 [CA 1] Center 42 (12~73) winsize 62
7508 16:36:42.142982 [CA 2] Center 37 (7~67) winsize 61
7509 16:36:42.146008 [CA 3] Center 37 (7~67) winsize 61
7510 16:36:42.149403 [CA 4] Center 36 (6~66) winsize 61
7511 16:36:42.152702 [CA 5] Center 35 (6~64) winsize 59
7512 16:36:42.153283
7513 16:36:42.155630 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 16:36:42.156021
7515 16:36:42.159446 [CATrainingPosCal] consider 1 rank data
7516 16:36:42.162475 u2DelayCellTimex100 = 290/100 ps
7517 16:36:42.169248 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7518 16:36:42.172189 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7519 16:36:42.175959 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7520 16:36:42.178967 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7521 16:36:42.182787 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7522 16:36:42.185740 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7523 16:36:42.186133
7524 16:36:42.188778 CA PerBit enable=1, Macro0, CA PI delay=35
7525 16:36:42.189281
7526 16:36:42.192621 [CBTSetCACLKResult] CA Dly = 35
7527 16:36:42.195724 CS Dly: 9 (0~40)
7528 16:36:42.198723 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 16:36:42.202497 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 16:36:42.202886 ==
7531 16:36:42.205578 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 16:36:42.209280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 16:36:42.212224 ==
7534 16:36:42.215790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 16:36:42.218689 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 16:36:42.225909 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 16:36:42.231979 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 16:36:42.239462 [CA 0] Center 42 (12~73) winsize 62
7539 16:36:42.243138 [CA 1] Center 42 (12~73) winsize 62
7540 16:36:42.246065 [CA 2] Center 37 (8~67) winsize 60
7541 16:36:42.249620 [CA 3] Center 37 (8~67) winsize 60
7542 16:36:42.252780 [CA 4] Center 36 (6~66) winsize 61
7543 16:36:42.256301 [CA 5] Center 35 (5~65) winsize 61
7544 16:36:42.256685
7545 16:36:42.259340 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 16:36:42.259812
7547 16:36:42.262599 [CATrainingPosCal] consider 2 rank data
7548 16:36:42.266014 u2DelayCellTimex100 = 290/100 ps
7549 16:36:42.269392 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7550 16:36:42.276101 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7551 16:36:42.279593 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7552 16:36:42.282700 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7553 16:36:42.286211 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7554 16:36:42.289199 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7555 16:36:42.289612
7556 16:36:42.293042 CA PerBit enable=1, Macro0, CA PI delay=35
7557 16:36:42.293429
7558 16:36:42.295963 [CBTSetCACLKResult] CA Dly = 35
7559 16:36:42.296349 CS Dly: 10 (0~42)
7560 16:36:42.302864 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 16:36:42.305908 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 16:36:42.306337
7563 16:36:42.309472 ----->DramcWriteLeveling(PI) begin...
7564 16:36:42.309963 ==
7565 16:36:42.312558 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 16:36:42.316169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 16:36:42.319181 ==
7568 16:36:42.319733 Write leveling (Byte 0): 37 => 37
7569 16:36:42.322857 Write leveling (Byte 1): 27 => 27
7570 16:36:42.326401 DramcWriteLeveling(PI) end<-----
7571 16:36:42.326787
7572 16:36:42.327140 ==
7573 16:36:42.329265 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 16:36:42.335734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 16:36:42.336127 ==
7576 16:36:42.336461 [Gating] SW mode calibration
7577 16:36:42.345805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 16:36:42.349502 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 16:36:42.355689 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 16:36:42.359692 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7581 16:36:42.362299 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7582 16:36:42.369080 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
7583 16:36:42.371903 1 4 16 | B1->B0 | 2323 3535 | 1 1 | (1 1) (1 1)
7584 16:36:42.375648 1 4 20 | B1->B0 | 3333 3636 | 0 0 | (0 0) (1 1)
7585 16:36:42.379353 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7586 16:36:42.385397 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7587 16:36:42.388706 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7588 16:36:42.392232 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7589 16:36:42.398881 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
7590 16:36:42.402222 1 5 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7591 16:36:42.405241 1 5 16 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
7592 16:36:42.411950 1 5 20 | B1->B0 | 2a2a 2b2b | 0 0 | (1 0) (0 0)
7593 16:36:42.415587 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7594 16:36:42.418541 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7595 16:36:42.424996 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7596 16:36:42.428813 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
7597 16:36:42.431599 1 6 8 | B1->B0 | 2323 3b3a | 0 1 | (0 0) (0 0)
7598 16:36:42.438064 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7599 16:36:42.441880 1 6 16 | B1->B0 | 3030 4645 | 0 1 | (0 0) (0 0)
7600 16:36:42.444752 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 16:36:42.451423 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 16:36:42.455094 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 16:36:42.457870 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 16:36:42.465174 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 16:36:42.468021 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 16:36:42.471749 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 16:36:42.477717 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7608 16:36:42.481472 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7609 16:36:42.484514 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 16:36:42.491357 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 16:36:42.494427 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 16:36:42.497903 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 16:36:42.504908 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 16:36:42.507771 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 16:36:42.511238 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 16:36:42.517884 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 16:36:42.520970 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 16:36:42.524940 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 16:36:42.530914 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 16:36:42.534985 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 16:36:42.538144 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 16:36:42.544702 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7623 16:36:42.547435 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7624 16:36:42.551264 Total UI for P1: 0, mck2ui 16
7625 16:36:42.554131 best dqsien dly found for B0: ( 1, 9, 10)
7626 16:36:42.557840 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 16:36:42.561052 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 16:36:42.564791 Total UI for P1: 0, mck2ui 16
7629 16:36:42.567602 best dqsien dly found for B1: ( 1, 9, 20)
7630 16:36:42.571239 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7631 16:36:42.577906 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7632 16:36:42.578390
7633 16:36:42.581538 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7634 16:36:42.584435 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7635 16:36:42.587492 [Gating] SW calibration Done
7636 16:36:42.587876 ==
7637 16:36:42.590590 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 16:36:42.594312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 16:36:42.594703 ==
7640 16:36:42.597284 RX Vref Scan: 0
7641 16:36:42.597698
7642 16:36:42.598002 RX Vref 0 -> 0, step: 1
7643 16:36:42.598298
7644 16:36:42.601147 RX Delay 0 -> 252, step: 8
7645 16:36:42.604136 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7646 16:36:42.610701 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7647 16:36:42.614170 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7648 16:36:42.617136 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7649 16:36:42.620825 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7650 16:36:42.624052 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7651 16:36:42.627497 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7652 16:36:42.634437 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7653 16:36:42.637810 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7654 16:36:42.640947 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7655 16:36:42.643982 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7656 16:36:42.647695 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7657 16:36:42.653834 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7658 16:36:42.657506 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7659 16:36:42.660384 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7660 16:36:42.664035 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7661 16:36:42.664423 ==
7662 16:36:42.667016 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 16:36:42.673923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 16:36:42.674317 ==
7665 16:36:42.674623 DQS Delay:
7666 16:36:42.677374 DQS0 = 0, DQS1 = 0
7667 16:36:42.677798 DQM Delay:
7668 16:36:42.678101 DQM0 = 136, DQM1 = 130
7669 16:36:42.680399 DQ Delay:
7670 16:36:42.684074 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7671 16:36:42.687022 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7672 16:36:42.690131 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7673 16:36:42.693906 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7674 16:36:42.694299
7675 16:36:42.694599
7676 16:36:42.694886 ==
7677 16:36:42.696856 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 16:36:42.703529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 16:36:42.703940 ==
7680 16:36:42.704249
7681 16:36:42.704531
7682 16:36:42.704798 TX Vref Scan disable
7683 16:36:42.707105 == TX Byte 0 ==
7684 16:36:42.710155 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7685 16:36:42.713706 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7686 16:36:42.716922 == TX Byte 1 ==
7687 16:36:42.720644 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7688 16:36:42.723525 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7689 16:36:42.727281 ==
7690 16:36:42.730089 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 16:36:42.733656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 16:36:42.734174 ==
7693 16:36:42.746677
7694 16:36:42.750221 TX Vref early break, caculate TX vref
7695 16:36:42.753048 TX Vref=16, minBit 7, minWin=22, winSum=376
7696 16:36:42.756208 TX Vref=18, minBit 0, minWin=23, winSum=382
7697 16:36:42.759636 TX Vref=20, minBit 0, minWin=23, winSum=399
7698 16:36:42.762937 TX Vref=22, minBit 3, minWin=24, winSum=405
7699 16:36:42.766272 TX Vref=24, minBit 3, minWin=24, winSum=413
7700 16:36:42.772989 TX Vref=26, minBit 1, minWin=25, winSum=424
7701 16:36:42.776353 TX Vref=28, minBit 0, minWin=25, winSum=418
7702 16:36:42.779525 TX Vref=30, minBit 4, minWin=24, winSum=411
7703 16:36:42.783136 TX Vref=32, minBit 1, minWin=24, winSum=405
7704 16:36:42.786068 TX Vref=34, minBit 1, minWin=23, winSum=395
7705 16:36:42.793345 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
7706 16:36:42.793471
7707 16:36:42.796351 Final TX Range 0 Vref 26
7708 16:36:42.796476
7709 16:36:42.796598 ==
7710 16:36:42.800205 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 16:36:42.803232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 16:36:42.803385 ==
7713 16:36:42.803509
7714 16:36:42.803624
7715 16:36:42.806157 TX Vref Scan disable
7716 16:36:42.812948 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7717 16:36:42.813109 == TX Byte 0 ==
7718 16:36:42.816055 u2DelayCellOfst[0]=13 cells (4 PI)
7719 16:36:42.819782 u2DelayCellOfst[1]=16 cells (5 PI)
7720 16:36:42.822899 u2DelayCellOfst[2]=13 cells (4 PI)
7721 16:36:42.826716 u2DelayCellOfst[3]=10 cells (3 PI)
7722 16:36:42.829663 u2DelayCellOfst[4]=10 cells (3 PI)
7723 16:36:42.832872 u2DelayCellOfst[5]=0 cells (0 PI)
7724 16:36:42.836486 u2DelayCellOfst[6]=16 cells (5 PI)
7725 16:36:42.839426 u2DelayCellOfst[7]=16 cells (5 PI)
7726 16:36:42.843130 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7727 16:36:42.846734 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7728 16:36:42.849653 == TX Byte 1 ==
7729 16:36:42.850062 u2DelayCellOfst[8]=0 cells (0 PI)
7730 16:36:42.853144 u2DelayCellOfst[9]=0 cells (0 PI)
7731 16:36:42.856295 u2DelayCellOfst[10]=6 cells (2 PI)
7732 16:36:42.859972 u2DelayCellOfst[11]=3 cells (1 PI)
7733 16:36:42.862926 u2DelayCellOfst[12]=10 cells (3 PI)
7734 16:36:42.866536 u2DelayCellOfst[13]=13 cells (4 PI)
7735 16:36:42.869496 u2DelayCellOfst[14]=16 cells (5 PI)
7736 16:36:42.873224 u2DelayCellOfst[15]=10 cells (3 PI)
7737 16:36:42.876098 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7738 16:36:42.883006 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7739 16:36:42.883409 DramC Write-DBI on
7740 16:36:42.883806 ==
7741 16:36:42.886444 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 16:36:42.888760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 16:36:42.892115 ==
7744 16:36:42.892197
7745 16:36:42.892274
7746 16:36:42.892346 TX Vref Scan disable
7747 16:36:42.895990 == TX Byte 0 ==
7748 16:36:42.899149 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7749 16:36:42.903240 == TX Byte 1 ==
7750 16:36:42.906195 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7751 16:36:42.909008 DramC Write-DBI off
7752 16:36:42.909106
7753 16:36:42.909202 [DATLAT]
7754 16:36:42.909292 Freq=1600, CH0 RK0
7755 16:36:42.909381
7756 16:36:42.912958 DATLAT Default: 0xf
7757 16:36:42.913358 0, 0xFFFF, sum = 0
7758 16:36:42.916175 1, 0xFFFF, sum = 0
7759 16:36:42.919991 2, 0xFFFF, sum = 0
7760 16:36:42.920399 3, 0xFFFF, sum = 0
7761 16:36:42.923076 4, 0xFFFF, sum = 0
7762 16:36:42.923484 5, 0xFFFF, sum = 0
7763 16:36:42.926153 6, 0xFFFF, sum = 0
7764 16:36:42.926558 7, 0xFFFF, sum = 0
7765 16:36:42.929953 8, 0xFFFF, sum = 0
7766 16:36:42.930363 9, 0xFFFF, sum = 0
7767 16:36:42.932749 10, 0xFFFF, sum = 0
7768 16:36:42.933152 11, 0xFFFF, sum = 0
7769 16:36:42.935843 12, 0xFFFF, sum = 0
7770 16:36:42.936239 13, 0xFFFF, sum = 0
7771 16:36:42.939609 14, 0x0, sum = 1
7772 16:36:42.940118 15, 0x0, sum = 2
7773 16:36:42.942708 16, 0x0, sum = 3
7774 16:36:42.943103 17, 0x0, sum = 4
7775 16:36:42.946554 best_step = 15
7776 16:36:42.946941
7777 16:36:42.947271 ==
7778 16:36:42.949420 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 16:36:42.953147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 16:36:42.953720 ==
7781 16:36:42.956086 RX Vref Scan: 1
7782 16:36:42.956445
7783 16:36:42.956727 Set Vref Range= 24 -> 127
7784 16:36:42.957000
7785 16:36:42.959175 RX Vref 24 -> 127, step: 1
7786 16:36:42.959570
7787 16:36:42.962909 RX Delay 27 -> 252, step: 4
7788 16:36:42.963332
7789 16:36:42.965948 Set Vref, RX VrefLevel [Byte0]: 24
7790 16:36:42.968908 [Byte1]: 24
7791 16:36:42.969318
7792 16:36:42.972799 Set Vref, RX VrefLevel [Byte0]: 25
7793 16:36:42.975904 [Byte1]: 25
7794 16:36:42.978929
7795 16:36:42.979323 Set Vref, RX VrefLevel [Byte0]: 26
7796 16:36:42.982679 [Byte1]: 26
7797 16:36:42.986417
7798 16:36:42.986855 Set Vref, RX VrefLevel [Byte0]: 27
7799 16:36:42.990001 [Byte1]: 27
7800 16:36:42.994361
7801 16:36:42.994782 Set Vref, RX VrefLevel [Byte0]: 28
7802 16:36:42.997323 [Byte1]: 28
7803 16:36:43.001743
7804 16:36:43.002144 Set Vref, RX VrefLevel [Byte0]: 29
7805 16:36:43.005269 [Byte1]: 29
7806 16:36:43.009364
7807 16:36:43.009830 Set Vref, RX VrefLevel [Byte0]: 30
7808 16:36:43.012271 [Byte1]: 30
7809 16:36:43.016876
7810 16:36:43.017264 Set Vref, RX VrefLevel [Byte0]: 31
7811 16:36:43.019987 [Byte1]: 31
7812 16:36:43.024575
7813 16:36:43.025001 Set Vref, RX VrefLevel [Byte0]: 32
7814 16:36:43.027504 [Byte1]: 32
7815 16:36:43.031545
7816 16:36:43.031937 Set Vref, RX VrefLevel [Byte0]: 33
7817 16:36:43.034942 [Byte1]: 33
7818 16:36:43.039254
7819 16:36:43.039707 Set Vref, RX VrefLevel [Byte0]: 34
7820 16:36:43.042173 [Byte1]: 34
7821 16:36:43.046624
7822 16:36:43.047013 Set Vref, RX VrefLevel [Byte0]: 35
7823 16:36:43.050500 [Byte1]: 35
7824 16:36:43.054282
7825 16:36:43.054669 Set Vref, RX VrefLevel [Byte0]: 36
7826 16:36:43.058052 [Byte1]: 36
7827 16:36:43.061813
7828 16:36:43.062202 Set Vref, RX VrefLevel [Byte0]: 37
7829 16:36:43.065526 [Byte1]: 37
7830 16:36:43.069355
7831 16:36:43.069894 Set Vref, RX VrefLevel [Byte0]: 38
7832 16:36:43.073527 [Byte1]: 38
7833 16:36:43.076842
7834 16:36:43.077231 Set Vref, RX VrefLevel [Byte0]: 39
7835 16:36:43.080663 [Byte1]: 39
7836 16:36:43.084465
7837 16:36:43.084857 Set Vref, RX VrefLevel [Byte0]: 40
7838 16:36:43.087614 [Byte1]: 40
7839 16:36:43.092105
7840 16:36:43.092799 Set Vref, RX VrefLevel [Byte0]: 41
7841 16:36:43.095111 [Byte1]: 41
7842 16:36:43.099404
7843 16:36:43.099868 Set Vref, RX VrefLevel [Byte0]: 42
7844 16:36:43.102926 [Byte1]: 42
7845 16:36:43.107310
7846 16:36:43.107741 Set Vref, RX VrefLevel [Byte0]: 43
7847 16:36:43.110451 [Byte1]: 43
7848 16:36:43.114866
7849 16:36:43.115255 Set Vref, RX VrefLevel [Byte0]: 44
7850 16:36:43.117855 [Byte1]: 44
7851 16:36:43.122204
7852 16:36:43.122478 Set Vref, RX VrefLevel [Byte0]: 45
7853 16:36:43.125177 [Byte1]: 45
7854 16:36:43.129473
7855 16:36:43.129791 Set Vref, RX VrefLevel [Byte0]: 46
7856 16:36:43.133107 [Byte1]: 46
7857 16:36:43.136997
7858 16:36:43.137286 Set Vref, RX VrefLevel [Byte0]: 47
7859 16:36:43.140460 [Byte1]: 47
7860 16:36:43.144563
7861 16:36:43.144884 Set Vref, RX VrefLevel [Byte0]: 48
7862 16:36:43.147970 [Byte1]: 48
7863 16:36:43.152134
7864 16:36:43.152487 Set Vref, RX VrefLevel [Byte0]: 49
7865 16:36:43.155270 [Byte1]: 49
7866 16:36:43.159750
7867 16:36:43.160026 Set Vref, RX VrefLevel [Byte0]: 50
7868 16:36:43.162970 [Byte1]: 50
7869 16:36:43.167396
7870 16:36:43.167672 Set Vref, RX VrefLevel [Byte0]: 51
7871 16:36:43.170630 [Byte1]: 51
7872 16:36:43.174716
7873 16:36:43.175071 Set Vref, RX VrefLevel [Byte0]: 52
7874 16:36:43.178404 [Byte1]: 52
7875 16:36:43.182051
7876 16:36:43.182557 Set Vref, RX VrefLevel [Byte0]: 53
7877 16:36:43.185681 [Byte1]: 53
7878 16:36:43.190170
7879 16:36:43.190700 Set Vref, RX VrefLevel [Byte0]: 54
7880 16:36:43.193149 [Byte1]: 54
7881 16:36:43.197469
7882 16:36:43.197592 Set Vref, RX VrefLevel [Byte0]: 55
7883 16:36:43.200458 [Byte1]: 55
7884 16:36:43.204694
7885 16:36:43.204816 Set Vref, RX VrefLevel [Byte0]: 56
7886 16:36:43.207822 [Byte1]: 56
7887 16:36:43.212270
7888 16:36:43.212380 Set Vref, RX VrefLevel [Byte0]: 57
7889 16:36:43.215216 [Byte1]: 57
7890 16:36:43.219648
7891 16:36:43.219754 Set Vref, RX VrefLevel [Byte0]: 58
7892 16:36:43.222633 [Byte1]: 58
7893 16:36:43.227381
7894 16:36:43.227458 Set Vref, RX VrefLevel [Byte0]: 59
7895 16:36:43.230326 [Byte1]: 59
7896 16:36:43.234772
7897 16:36:43.234853 Set Vref, RX VrefLevel [Byte0]: 60
7898 16:36:43.238518 [Byte1]: 60
7899 16:36:43.242211
7900 16:36:43.242305 Set Vref, RX VrefLevel [Byte0]: 61
7901 16:36:43.245263 [Byte1]: 61
7902 16:36:43.249848
7903 16:36:43.249924 Set Vref, RX VrefLevel [Byte0]: 62
7904 16:36:43.252902 [Byte1]: 62
7905 16:36:43.257388
7906 16:36:43.257494 Set Vref, RX VrefLevel [Byte0]: 63
7907 16:36:43.260574 [Byte1]: 63
7908 16:36:43.264978
7909 16:36:43.265065 Set Vref, RX VrefLevel [Byte0]: 64
7910 16:36:43.268009 [Byte1]: 64
7911 16:36:43.272244
7912 16:36:43.272320 Set Vref, RX VrefLevel [Byte0]: 65
7913 16:36:43.275712 [Byte1]: 65
7914 16:36:43.280452
7915 16:36:43.280533 Set Vref, RX VrefLevel [Byte0]: 66
7916 16:36:43.283117 [Byte1]: 66
7917 16:36:43.287764
7918 16:36:43.287886 Set Vref, RX VrefLevel [Byte0]: 67
7919 16:36:43.291023 [Byte1]: 67
7920 16:36:43.295550
7921 16:36:43.295653 Set Vref, RX VrefLevel [Byte0]: 68
7922 16:36:43.298776 [Byte1]: 68
7923 16:36:43.302831
7924 16:36:43.302965 Set Vref, RX VrefLevel [Byte0]: 69
7925 16:36:43.305742 [Byte1]: 69
7926 16:36:43.310256
7927 16:36:43.310434 Set Vref, RX VrefLevel [Byte0]: 70
7928 16:36:43.313410 [Byte1]: 70
7929 16:36:43.317745
7930 16:36:43.317907 Set Vref, RX VrefLevel [Byte0]: 71
7931 16:36:43.321617 [Byte1]: 71
7932 16:36:43.325313
7933 16:36:43.325570 Set Vref, RX VrefLevel [Byte0]: 72
7934 16:36:43.328419 [Byte1]: 72
7935 16:36:43.333105
7936 16:36:43.333391 Set Vref, RX VrefLevel [Byte0]: 73
7937 16:36:43.336191 [Byte1]: 73
7938 16:36:43.340859
7939 16:36:43.341263 Set Vref, RX VrefLevel [Byte0]: 74
7940 16:36:43.343713 [Byte1]: 74
7941 16:36:43.348209
7942 16:36:43.348598 Final RX Vref Byte 0 = 55 to rank0
7943 16:36:43.351775 Final RX Vref Byte 1 = 62 to rank0
7944 16:36:43.354534 Final RX Vref Byte 0 = 55 to rank1
7945 16:36:43.358171 Final RX Vref Byte 1 = 62 to rank1==
7946 16:36:43.361763 Dram Type= 6, Freq= 0, CH_0, rank 0
7947 16:36:43.367888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 16:36:43.368282 ==
7949 16:36:43.368587 DQS Delay:
7950 16:36:43.368866 DQS0 = 0, DQS1 = 0
7951 16:36:43.371509 DQM Delay:
7952 16:36:43.371894 DQM0 = 133, DQM1 = 127
7953 16:36:43.374944 DQ Delay:
7954 16:36:43.377731 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7955 16:36:43.381590 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7956 16:36:43.385065 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7957 16:36:43.388092 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7958 16:36:43.388479
7959 16:36:43.388779
7960 16:36:43.389055
7961 16:36:43.391596 [DramC_TX_OE_Calibration] TA2
7962 16:36:43.394609 Original DQ_B0 (3 6) =30, OEN = 27
7963 16:36:43.397631 Original DQ_B1 (3 6) =30, OEN = 27
7964 16:36:43.401333 24, 0x0, End_B0=24 End_B1=24
7965 16:36:43.401907 25, 0x0, End_B0=25 End_B1=25
7966 16:36:43.404837 26, 0x0, End_B0=26 End_B1=26
7967 16:36:43.408242 27, 0x0, End_B0=27 End_B1=27
7968 16:36:43.411331 28, 0x0, End_B0=28 End_B1=28
7969 16:36:43.414564 29, 0x0, End_B0=29 End_B1=29
7970 16:36:43.414957 30, 0x0, End_B0=30 End_B1=30
7971 16:36:43.417664 31, 0x4141, End_B0=30 End_B1=30
7972 16:36:43.420788 Byte0 end_step=30 best_step=27
7973 16:36:43.424786 Byte1 end_step=30 best_step=27
7974 16:36:43.427546 Byte0 TX OE(2T, 0.5T) = (3, 3)
7975 16:36:43.430942 Byte1 TX OE(2T, 0.5T) = (3, 3)
7976 16:36:43.431331
7977 16:36:43.431634
7978 16:36:43.437742 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7979 16:36:43.441432 CH0 RK0: MR19=303, MR18=2521
7980 16:36:43.448066 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7981 16:36:43.448492
7982 16:36:43.451397 ----->DramcWriteLeveling(PI) begin...
7983 16:36:43.451877 ==
7984 16:36:43.454255 Dram Type= 6, Freq= 0, CH_0, rank 1
7985 16:36:43.457883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 16:36:43.458278 ==
7987 16:36:43.460675 Write leveling (Byte 0): 38 => 38
7988 16:36:43.464308 Write leveling (Byte 1): 26 => 26
7989 16:36:43.467942 DramcWriteLeveling(PI) end<-----
7990 16:36:43.468359
7991 16:36:43.468663 ==
7992 16:36:43.471066 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 16:36:43.473931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 16:36:43.474384 ==
7995 16:36:43.477833 [Gating] SW mode calibration
7996 16:36:43.484522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7997 16:36:43.490586 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7998 16:36:43.494359 1 4 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7999 16:36:43.497403 1 4 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8000 16:36:43.504161 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8001 16:36:43.507131 1 4 12 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
8002 16:36:43.511156 1 4 16 | B1->B0 | 2c2c 3534 | 0 1 | (0 0) (1 1)
8003 16:36:43.517588 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8004 16:36:43.520831 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8005 16:36:43.523780 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8006 16:36:43.530886 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8007 16:36:43.533728 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8008 16:36:43.537363 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
8009 16:36:43.543889 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8010 16:36:43.547473 1 5 16 | B1->B0 | 2d2d 2827 | 0 1 | (0 0) (1 1)
8011 16:36:43.550789 1 5 20 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
8012 16:36:43.556832 1 5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
8013 16:36:43.560232 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8014 16:36:43.563938 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8015 16:36:43.570590 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8016 16:36:43.573451 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8017 16:36:43.577008 1 6 12 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
8018 16:36:43.584055 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8019 16:36:43.586996 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8020 16:36:43.590707 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 16:36:43.596595 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 16:36:43.600523 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 16:36:43.603575 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 16:36:43.610127 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 16:36:43.613839 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8026 16:36:43.616822 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8027 16:36:43.623216 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 16:36:43.627216 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 16:36:43.630322 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 16:36:43.637150 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 16:36:43.640054 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 16:36:43.643660 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 16:36:43.646654 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 16:36:43.653342 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 16:36:43.656957 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 16:36:43.659697 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 16:36:43.667080 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 16:36:43.669821 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 16:36:43.673232 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 16:36:43.679846 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 16:36:43.683246 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8042 16:36:43.686469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8043 16:36:43.693543 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 16:36:43.696982 Total UI for P1: 0, mck2ui 16
8045 16:36:43.699773 best dqsien dly found for B0: ( 1, 9, 14)
8046 16:36:43.700158 Total UI for P1: 0, mck2ui 16
8047 16:36:43.706891 best dqsien dly found for B1: ( 1, 9, 14)
8048 16:36:43.710027 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8049 16:36:43.713725 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8050 16:36:43.714170
8051 16:36:43.716757 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8052 16:36:43.719871 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8053 16:36:43.723595 [Gating] SW calibration Done
8054 16:36:43.724053 ==
8055 16:36:43.726567 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 16:36:43.730296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 16:36:43.730718 ==
8058 16:36:43.733233 RX Vref Scan: 0
8059 16:36:43.733835
8060 16:36:43.734293 RX Vref 0 -> 0, step: 1
8061 16:36:43.734721
8062 16:36:43.736239 RX Delay 0 -> 252, step: 8
8063 16:36:43.740072 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8064 16:36:43.746720 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8065 16:36:43.749791 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8066 16:36:43.753151 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8067 16:36:43.756872 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8068 16:36:43.759927 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8069 16:36:43.766473 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8070 16:36:43.769464 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8071 16:36:43.773037 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8072 16:36:43.776721 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8073 16:36:43.780013 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8074 16:36:43.786605 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8075 16:36:43.789440 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8076 16:36:43.793088 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8077 16:36:43.796397 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8078 16:36:43.799865 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8079 16:36:43.803142 ==
8080 16:36:43.806262 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 16:36:43.809679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 16:36:43.810044 ==
8083 16:36:43.810411 DQS Delay:
8084 16:36:43.812919 DQS0 = 0, DQS1 = 0
8085 16:36:43.813322 DQM Delay:
8086 16:36:43.816103 DQM0 = 136, DQM1 = 129
8087 16:36:43.816489 DQ Delay:
8088 16:36:43.819686 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8089 16:36:43.822660 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8090 16:36:43.826105 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8091 16:36:43.829400 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8092 16:36:43.829476
8093 16:36:43.829535
8094 16:36:43.829629 ==
8095 16:36:43.832363 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 16:36:43.839185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 16:36:43.839262 ==
8098 16:36:43.839321
8099 16:36:43.839376
8100 16:36:43.839427 TX Vref Scan disable
8101 16:36:43.842953 == TX Byte 0 ==
8102 16:36:43.846531 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8103 16:36:43.852581 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8104 16:36:43.852658 == TX Byte 1 ==
8105 16:36:43.856366 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8106 16:36:43.862749 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8107 16:36:43.862826 ==
8108 16:36:43.866279 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 16:36:43.869237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 16:36:43.869316 ==
8111 16:36:43.884922
8112 16:36:43.887945 TX Vref early break, caculate TX vref
8113 16:36:43.890972 TX Vref=16, minBit 0, minWin=23, winSum=385
8114 16:36:43.894852 TX Vref=18, minBit 1, minWin=23, winSum=396
8115 16:36:43.897745 TX Vref=20, minBit 1, minWin=24, winSum=401
8116 16:36:43.901333 TX Vref=22, minBit 1, minWin=24, winSum=409
8117 16:36:43.904244 TX Vref=24, minBit 0, minWin=25, winSum=420
8118 16:36:43.911531 TX Vref=26, minBit 4, minWin=25, winSum=426
8119 16:36:43.914515 TX Vref=28, minBit 2, minWin=25, winSum=424
8120 16:36:43.917564 TX Vref=30, minBit 4, minWin=25, winSum=419
8121 16:36:43.921336 TX Vref=32, minBit 1, minWin=25, winSum=412
8122 16:36:43.924273 TX Vref=34, minBit 0, minWin=24, winSum=404
8123 16:36:43.927873 TX Vref=36, minBit 0, minWin=24, winSum=390
8124 16:36:43.934272 [TxChooseVref] Worse bit 4, Min win 25, Win sum 426, Final Vref 26
8125 16:36:43.934360
8126 16:36:43.937522 Final TX Range 0 Vref 26
8127 16:36:43.937638
8128 16:36:43.937697 ==
8129 16:36:43.940734 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 16:36:43.944590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 16:36:43.944669 ==
8132 16:36:43.944728
8133 16:36:43.944782
8134 16:36:43.947591 TX Vref Scan disable
8135 16:36:43.954166 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8136 16:36:43.954237 == TX Byte 0 ==
8137 16:36:43.957282 u2DelayCellOfst[0]=13 cells (4 PI)
8138 16:36:43.960845 u2DelayCellOfst[1]=16 cells (5 PI)
8139 16:36:43.964515 u2DelayCellOfst[2]=10 cells (3 PI)
8140 16:36:43.967866 u2DelayCellOfst[3]=13 cells (4 PI)
8141 16:36:43.970680 u2DelayCellOfst[4]=10 cells (3 PI)
8142 16:36:43.974184 u2DelayCellOfst[5]=0 cells (0 PI)
8143 16:36:43.977668 u2DelayCellOfst[6]=16 cells (5 PI)
8144 16:36:43.981164 u2DelayCellOfst[7]=16 cells (5 PI)
8145 16:36:43.984125 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8146 16:36:43.987101 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8147 16:36:43.990944 == TX Byte 1 ==
8148 16:36:43.993924 u2DelayCellOfst[8]=3 cells (1 PI)
8149 16:36:43.997758 u2DelayCellOfst[9]=0 cells (0 PI)
8150 16:36:43.997835 u2DelayCellOfst[10]=6 cells (2 PI)
8151 16:36:44.000660 u2DelayCellOfst[11]=6 cells (2 PI)
8152 16:36:44.003749 u2DelayCellOfst[12]=10 cells (3 PI)
8153 16:36:44.007442 u2DelayCellOfst[13]=10 cells (3 PI)
8154 16:36:44.010460 u2DelayCellOfst[14]=13 cells (4 PI)
8155 16:36:44.014117 u2DelayCellOfst[15]=10 cells (3 PI)
8156 16:36:44.020474 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8157 16:36:44.024181 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8158 16:36:44.024276 DramC Write-DBI on
8159 16:36:44.024361 ==
8160 16:36:44.027265 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 16:36:44.033833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 16:36:44.033927 ==
8163 16:36:44.034011
8164 16:36:44.034091
8165 16:36:44.034172 TX Vref Scan disable
8166 16:36:44.038303 == TX Byte 0 ==
8167 16:36:44.041372 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8168 16:36:44.044544 == TX Byte 1 ==
8169 16:36:44.048288 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8170 16:36:44.051237 DramC Write-DBI off
8171 16:36:44.051326
8172 16:36:44.051407 [DATLAT]
8173 16:36:44.051490 Freq=1600, CH0 RK1
8174 16:36:44.051569
8175 16:36:44.054839 DATLAT Default: 0xf
8176 16:36:44.054927 0, 0xFFFF, sum = 0
8177 16:36:44.058362 1, 0xFFFF, sum = 0
8178 16:36:44.058458 2, 0xFFFF, sum = 0
8179 16:36:44.061326 3, 0xFFFF, sum = 0
8180 16:36:44.064700 4, 0xFFFF, sum = 0
8181 16:36:44.064800 5, 0xFFFF, sum = 0
8182 16:36:44.068128 6, 0xFFFF, sum = 0
8183 16:36:44.068205 7, 0xFFFF, sum = 0
8184 16:36:44.071369 8, 0xFFFF, sum = 0
8185 16:36:44.071471 9, 0xFFFF, sum = 0
8186 16:36:44.074874 10, 0xFFFF, sum = 0
8187 16:36:44.074953 11, 0xFFFF, sum = 0
8188 16:36:44.078037 12, 0xFFFF, sum = 0
8189 16:36:44.078115 13, 0xFFFF, sum = 0
8190 16:36:44.081345 14, 0x0, sum = 1
8191 16:36:44.081421 15, 0x0, sum = 2
8192 16:36:44.084546 16, 0x0, sum = 3
8193 16:36:44.084651 17, 0x0, sum = 4
8194 16:36:44.087734 best_step = 15
8195 16:36:44.087809
8196 16:36:44.087868 ==
8197 16:36:44.091499 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 16:36:44.094750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 16:36:44.094826 ==
8200 16:36:44.094885 RX Vref Scan: 0
8201 16:36:44.097990
8202 16:36:44.098066 RX Vref 0 -> 0, step: 1
8203 16:36:44.098124
8204 16:36:44.101113 RX Delay 19 -> 252, step: 4
8205 16:36:44.104707 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8206 16:36:44.111600 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8207 16:36:44.114502 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8208 16:36:44.118336 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8209 16:36:44.121132 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8210 16:36:44.124741 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8211 16:36:44.131447 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8212 16:36:44.134423 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8213 16:36:44.137459 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8214 16:36:44.141417 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8215 16:36:44.144555 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8216 16:36:44.151417 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8217 16:36:44.154416 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8218 16:36:44.157522 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8219 16:36:44.161368 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8220 16:36:44.164373 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8221 16:36:44.167493 ==
8222 16:36:44.167570 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 16:36:44.174297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 16:36:44.174374 ==
8225 16:36:44.174434 DQS Delay:
8226 16:36:44.177852 DQS0 = 0, DQS1 = 0
8227 16:36:44.177928 DQM Delay:
8228 16:36:44.180910 DQM0 = 134, DQM1 = 127
8229 16:36:44.181007 DQ Delay:
8230 16:36:44.184510 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =134
8231 16:36:44.187517 DQ4 =136, DQ5 =124, DQ6 =136, DQ7 =142
8232 16:36:44.191110 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8233 16:36:44.193985 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8234 16:36:44.194071
8235 16:36:44.194152
8236 16:36:44.194231
8237 16:36:44.197772 [DramC_TX_OE_Calibration] TA2
8238 16:36:44.200848 Original DQ_B0 (3 6) =30, OEN = 27
8239 16:36:44.204587 Original DQ_B1 (3 6) =30, OEN = 27
8240 16:36:44.207535 24, 0x0, End_B0=24 End_B1=24
8241 16:36:44.207628 25, 0x0, End_B0=25 End_B1=25
8242 16:36:44.211216 26, 0x0, End_B0=26 End_B1=26
8243 16:36:44.214714 27, 0x0, End_B0=27 End_B1=27
8244 16:36:44.217515 28, 0x0, End_B0=28 End_B1=28
8245 16:36:44.221094 29, 0x0, End_B0=29 End_B1=29
8246 16:36:44.221194 30, 0x0, End_B0=30 End_B1=30
8247 16:36:44.224425 31, 0x5151, End_B0=30 End_B1=30
8248 16:36:44.227546 Byte0 end_step=30 best_step=27
8249 16:36:44.231292 Byte1 end_step=30 best_step=27
8250 16:36:44.234217 Byte0 TX OE(2T, 0.5T) = (3, 3)
8251 16:36:44.237641 Byte1 TX OE(2T, 0.5T) = (3, 3)
8252 16:36:44.237740
8253 16:36:44.237815
8254 16:36:44.244387 [DQSOSCAuto] RK1, (LSB)MR18= 0x230b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8255 16:36:44.247697 CH0 RK1: MR19=303, MR18=230B
8256 16:36:44.254491 CH0_RK1: MR19=0x303, MR18=0x230B, DQSOSC=392, MR23=63, INC=24, DEC=16
8257 16:36:44.257542 [RxdqsGatingPostProcess] freq 1600
8258 16:36:44.260464 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8259 16:36:44.264093 best DQS0 dly(2T, 0.5T) = (1, 1)
8260 16:36:44.267188 best DQS1 dly(2T, 0.5T) = (1, 1)
8261 16:36:44.270952 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8262 16:36:44.273995 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8263 16:36:44.277575 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 16:36:44.280532 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 16:36:44.284152 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 16:36:44.287781 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 16:36:44.290731 Pre-setting of DQS Precalculation
8268 16:36:44.294339 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8269 16:36:44.294403 ==
8270 16:36:44.297210 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 16:36:44.300862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 16:36:44.303787 ==
8273 16:36:44.307456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 16:36:44.310403 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 16:36:44.317299 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 16:36:44.324163 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 16:36:44.330881 [CA 0] Center 41 (12~71) winsize 60
8278 16:36:44.334460 [CA 1] Center 41 (12~71) winsize 60
8279 16:36:44.337474 [CA 2] Center 38 (9~68) winsize 60
8280 16:36:44.341204 [CA 3] Center 37 (8~66) winsize 59
8281 16:36:44.344313 [CA 4] Center 37 (8~67) winsize 60
8282 16:36:44.347785 [CA 5] Center 36 (7~66) winsize 60
8283 16:36:44.347858
8284 16:36:44.350706 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8285 16:36:44.350774
8286 16:36:44.354108 [CATrainingPosCal] consider 1 rank data
8287 16:36:44.357509 u2DelayCellTimex100 = 290/100 ps
8288 16:36:44.360792 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8289 16:36:44.367858 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8290 16:36:44.370935 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8291 16:36:44.374056 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8292 16:36:44.377460 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8293 16:36:44.380895 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 16:36:44.380979
8295 16:36:44.383737 CA PerBit enable=1, Macro0, CA PI delay=36
8296 16:36:44.383805
8297 16:36:44.387269 [CBTSetCACLKResult] CA Dly = 36
8298 16:36:44.390799 CS Dly: 10 (0~41)
8299 16:36:44.393785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 16:36:44.397537 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 16:36:44.397628 ==
8302 16:36:44.400469 Dram Type= 6, Freq= 0, CH_1, rank 1
8303 16:36:44.403570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 16:36:44.407166 ==
8305 16:36:44.410518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 16:36:44.414347 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 16:36:44.420336 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 16:36:44.427327 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 16:36:44.434911 [CA 0] Center 42 (12~72) winsize 61
8310 16:36:44.437898 [CA 1] Center 41 (12~71) winsize 60
8311 16:36:44.440827 [CA 2] Center 38 (9~68) winsize 60
8312 16:36:44.444563 [CA 3] Center 38 (9~67) winsize 59
8313 16:36:44.447529 [CA 4] Center 38 (8~68) winsize 61
8314 16:36:44.451153 [CA 5] Center 37 (8~67) winsize 60
8315 16:36:44.451295
8316 16:36:44.454230 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8317 16:36:44.454406
8318 16:36:44.457930 [CATrainingPosCal] consider 2 rank data
8319 16:36:44.461070 u2DelayCellTimex100 = 290/100 ps
8320 16:36:44.464129 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8321 16:36:44.471148 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8322 16:36:44.474797 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8323 16:36:44.477621 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8324 16:36:44.481382 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8325 16:36:44.484727 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8326 16:36:44.485130
8327 16:36:44.487527 CA PerBit enable=1, Macro0, CA PI delay=37
8328 16:36:44.487956
8329 16:36:44.490855 [CBTSetCACLKResult] CA Dly = 37
8330 16:36:44.493829 CS Dly: 11 (0~44)
8331 16:36:44.497472 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 16:36:44.500910 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 16:36:44.501301
8334 16:36:44.504285 ----->DramcWriteLeveling(PI) begin...
8335 16:36:44.504726 ==
8336 16:36:44.507497 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 16:36:44.513650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 16:36:44.514207 ==
8339 16:36:44.517325 Write leveling (Byte 0): 24 => 24
8340 16:36:44.517815 Write leveling (Byte 1): 26 => 26
8341 16:36:44.520667 DramcWriteLeveling(PI) end<-----
8342 16:36:44.521255
8343 16:36:44.524282 ==
8344 16:36:44.524772 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 16:36:44.530672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 16:36:44.531061 ==
8347 16:36:44.533624 [Gating] SW mode calibration
8348 16:36:44.539929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8349 16:36:44.543582 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8350 16:36:44.550359 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 16:36:44.553265 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 16:36:44.556998 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8353 16:36:44.563068 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8354 16:36:44.566892 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 16:36:44.569870 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 16:36:44.576821 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 16:36:44.579905 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 16:36:44.583703 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 16:36:44.589932 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 16:36:44.593693 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8361 16:36:44.596720 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
8362 16:36:44.603187 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 16:36:44.606604 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 16:36:44.610207 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 16:36:44.616739 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 16:36:44.620391 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 16:36:44.623298 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 16:36:44.630081 1 6 8 | B1->B0 | 2525 3e3e | 0 0 | (1 1) (0 0)
8369 16:36:44.633242 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8370 16:36:44.636454 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 16:36:44.640038 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 16:36:44.646898 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 16:36:44.650139 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 16:36:44.653153 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 16:36:44.659853 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 16:36:44.663653 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8377 16:36:44.666636 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8378 16:36:44.673508 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8379 16:36:44.676527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 16:36:44.680290 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 16:36:44.686344 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 16:36:44.690083 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 16:36:44.693053 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 16:36:44.699792 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 16:36:44.703743 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 16:36:44.706565 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 16:36:44.713216 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 16:36:44.716640 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 16:36:44.719499 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 16:36:44.726117 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 16:36:44.729824 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8392 16:36:44.733133 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8393 16:36:44.739821 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8394 16:36:44.742786 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 16:36:44.746273 Total UI for P1: 0, mck2ui 16
8396 16:36:44.749853 best dqsien dly found for B0: ( 1, 9, 10)
8397 16:36:44.752819 Total UI for P1: 0, mck2ui 16
8398 16:36:44.756324 best dqsien dly found for B1: ( 1, 9, 8)
8399 16:36:44.759728 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8400 16:36:44.762958 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8401 16:36:44.763346
8402 16:36:44.766189 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8403 16:36:44.769975 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8404 16:36:44.773020 [Gating] SW calibration Done
8405 16:36:44.773544 ==
8406 16:36:44.775990 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 16:36:44.779836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 16:36:44.780225 ==
8409 16:36:44.782960 RX Vref Scan: 0
8410 16:36:44.783367
8411 16:36:44.786251 RX Vref 0 -> 0, step: 1
8412 16:36:44.786645
8413 16:36:44.786946 RX Delay 0 -> 252, step: 8
8414 16:36:44.792980 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8415 16:36:44.796533 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8416 16:36:44.799586 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8417 16:36:44.802564 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8418 16:36:44.806377 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8419 16:36:44.813185 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8420 16:36:44.816136 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8421 16:36:44.819841 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8422 16:36:44.822700 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8423 16:36:44.826286 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8424 16:36:44.833347 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8425 16:36:44.836331 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8426 16:36:44.839413 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8427 16:36:44.843234 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8428 16:36:44.846078 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8429 16:36:44.852828 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8430 16:36:44.853231 ==
8431 16:36:44.855771 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 16:36:44.859352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 16:36:44.859867 ==
8434 16:36:44.860318 DQS Delay:
8435 16:36:44.862491 DQS0 = 0, DQS1 = 0
8436 16:36:44.862878 DQM Delay:
8437 16:36:44.866209 DQM0 = 136, DQM1 = 132
8438 16:36:44.866612 DQ Delay:
8439 16:36:44.869188 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8440 16:36:44.872944 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8441 16:36:44.875853 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8442 16:36:44.879435 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8443 16:36:44.879827
8444 16:36:44.880130
8445 16:36:44.882901 ==
8446 16:36:44.885679 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 16:36:44.889101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 16:36:44.889493 ==
8449 16:36:44.889886
8450 16:36:44.890321
8451 16:36:44.892661 TX Vref Scan disable
8452 16:36:44.893053 == TX Byte 0 ==
8453 16:36:44.896117 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8454 16:36:44.902628 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8455 16:36:44.903037 == TX Byte 1 ==
8456 16:36:44.905989 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8457 16:36:44.912430 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8458 16:36:44.912953 ==
8459 16:36:44.916073 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 16:36:44.919452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 16:36:44.919900 ==
8462 16:36:44.932424
8463 16:36:44.935192 TX Vref early break, caculate TX vref
8464 16:36:44.938636 TX Vref=16, minBit 1, minWin=22, winSum=380
8465 16:36:44.941892 TX Vref=18, minBit 1, minWin=23, winSum=392
8466 16:36:44.944882 TX Vref=20, minBit 0, minWin=24, winSum=405
8467 16:36:44.948691 TX Vref=22, minBit 0, minWin=23, winSum=409
8468 16:36:44.951587 TX Vref=24, minBit 0, minWin=25, winSum=415
8469 16:36:44.958478 TX Vref=26, minBit 1, minWin=25, winSum=427
8470 16:36:44.962144 TX Vref=28, minBit 0, minWin=25, winSum=430
8471 16:36:44.965191 TX Vref=30, minBit 0, minWin=25, winSum=423
8472 16:36:44.968928 TX Vref=32, minBit 0, minWin=25, winSum=419
8473 16:36:44.971952 TX Vref=34, minBit 6, minWin=23, winSum=405
8474 16:36:44.978814 [TxChooseVref] Worse bit 0, Min win 25, Win sum 430, Final Vref 28
8475 16:36:44.979213
8476 16:36:44.981795 Final TX Range 0 Vref 28
8477 16:36:44.982338
8478 16:36:44.982662 ==
8479 16:36:44.985381 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 16:36:44.988043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 16:36:44.988437 ==
8482 16:36:44.988738
8483 16:36:44.989014
8484 16:36:44.991738 TX Vref Scan disable
8485 16:36:44.998274 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8486 16:36:44.998666 == TX Byte 0 ==
8487 16:36:45.001977 u2DelayCellOfst[0]=16 cells (5 PI)
8488 16:36:45.004977 u2DelayCellOfst[1]=10 cells (3 PI)
8489 16:36:45.007965 u2DelayCellOfst[2]=0 cells (0 PI)
8490 16:36:45.011705 u2DelayCellOfst[3]=6 cells (2 PI)
8491 16:36:45.014687 u2DelayCellOfst[4]=10 cells (3 PI)
8492 16:36:45.018331 u2DelayCellOfst[5]=16 cells (5 PI)
8493 16:36:45.021849 u2DelayCellOfst[6]=16 cells (5 PI)
8494 16:36:45.022241 u2DelayCellOfst[7]=3 cells (1 PI)
8495 16:36:45.028044 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8496 16:36:45.031353 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8497 16:36:45.031744 == TX Byte 1 ==
8498 16:36:45.034902 u2DelayCellOfst[8]=0 cells (0 PI)
8499 16:36:45.038487 u2DelayCellOfst[9]=3 cells (1 PI)
8500 16:36:45.041180 u2DelayCellOfst[10]=13 cells (4 PI)
8501 16:36:45.044760 u2DelayCellOfst[11]=3 cells (1 PI)
8502 16:36:45.048197 u2DelayCellOfst[12]=16 cells (5 PI)
8503 16:36:45.051432 u2DelayCellOfst[13]=16 cells (5 PI)
8504 16:36:45.054629 u2DelayCellOfst[14]=16 cells (5 PI)
8505 16:36:45.057878 u2DelayCellOfst[15]=16 cells (5 PI)
8506 16:36:45.061485 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8507 16:36:45.068223 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8508 16:36:45.068618 DramC Write-DBI on
8509 16:36:45.068924 ==
8510 16:36:45.071798 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 16:36:45.074828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 16:36:45.075221 ==
8513 16:36:45.077778
8514 16:36:45.078163
8515 16:36:45.078462 TX Vref Scan disable
8516 16:36:45.081644 == TX Byte 0 ==
8517 16:36:45.084546 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8518 16:36:45.088392 == TX Byte 1 ==
8519 16:36:45.091269 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8520 16:36:45.091687 DramC Write-DBI off
8521 16:36:45.095114
8522 16:36:45.095501 [DATLAT]
8523 16:36:45.095808 Freq=1600, CH1 RK0
8524 16:36:45.096090
8525 16:36:45.098043 DATLAT Default: 0xf
8526 16:36:45.098560 0, 0xFFFF, sum = 0
8527 16:36:45.101881 1, 0xFFFF, sum = 0
8528 16:36:45.102362 2, 0xFFFF, sum = 0
8529 16:36:45.104462 3, 0xFFFF, sum = 0
8530 16:36:45.107898 4, 0xFFFF, sum = 0
8531 16:36:45.108339 5, 0xFFFF, sum = 0
8532 16:36:45.111562 6, 0xFFFF, sum = 0
8533 16:36:45.111970 7, 0xFFFF, sum = 0
8534 16:36:45.114445 8, 0xFFFF, sum = 0
8535 16:36:45.114838 9, 0xFFFF, sum = 0
8536 16:36:45.117950 10, 0xFFFF, sum = 0
8537 16:36:45.118350 11, 0xFFFF, sum = 0
8538 16:36:45.120952 12, 0xFFFF, sum = 0
8539 16:36:45.121343 13, 0xFFFF, sum = 0
8540 16:36:45.124588 14, 0x0, sum = 1
8541 16:36:45.124982 15, 0x0, sum = 2
8542 16:36:45.127612 16, 0x0, sum = 3
8543 16:36:45.128017 17, 0x0, sum = 4
8544 16:36:45.131606 best_step = 15
8545 16:36:45.132003
8546 16:36:45.132398 ==
8547 16:36:45.134586 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 16:36:45.137455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 16:36:45.137903 ==
8550 16:36:45.138292 RX Vref Scan: 1
8551 16:36:45.141531
8552 16:36:45.141969 Set Vref Range= 24 -> 127
8553 16:36:45.142360
8554 16:36:45.144213 RX Vref 24 -> 127, step: 1
8555 16:36:45.144608
8556 16:36:45.147910 RX Delay 27 -> 252, step: 4
8557 16:36:45.148378
8558 16:36:45.151561 Set Vref, RX VrefLevel [Byte0]: 24
8559 16:36:45.154641 [Byte1]: 24
8560 16:36:45.155042
8561 16:36:45.157381 Set Vref, RX VrefLevel [Byte0]: 25
8562 16:36:45.161034 [Byte1]: 25
8563 16:36:45.161474
8564 16:36:45.164655 Set Vref, RX VrefLevel [Byte0]: 26
8565 16:36:45.167949 [Byte1]: 26
8566 16:36:45.171321
8567 16:36:45.171708 Set Vref, RX VrefLevel [Byte0]: 27
8568 16:36:45.174517 [Byte1]: 27
8569 16:36:45.178876
8570 16:36:45.179277 Set Vref, RX VrefLevel [Byte0]: 28
8571 16:36:45.182355 [Byte1]: 28
8572 16:36:45.186594
8573 16:36:45.189637 Set Vref, RX VrefLevel [Byte0]: 29
8574 16:36:45.193400 [Byte1]: 29
8575 16:36:45.193827
8576 16:36:45.196130 Set Vref, RX VrefLevel [Byte0]: 30
8577 16:36:45.199873 [Byte1]: 30
8578 16:36:45.200265
8579 16:36:45.202930 Set Vref, RX VrefLevel [Byte0]: 31
8580 16:36:45.206323 [Byte1]: 31
8581 16:36:45.206715
8582 16:36:45.209290 Set Vref, RX VrefLevel [Byte0]: 32
8583 16:36:45.212376 [Byte1]: 32
8584 16:36:45.216845
8585 16:36:45.217232 Set Vref, RX VrefLevel [Byte0]: 33
8586 16:36:45.219930 [Byte1]: 33
8587 16:36:45.224288
8588 16:36:45.224749 Set Vref, RX VrefLevel [Byte0]: 34
8589 16:36:45.227464 [Byte1]: 34
8590 16:36:45.231715
8591 16:36:45.232100 Set Vref, RX VrefLevel [Byte0]: 35
8592 16:36:45.234803 [Byte1]: 35
8593 16:36:45.239246
8594 16:36:45.239631 Set Vref, RX VrefLevel [Byte0]: 36
8595 16:36:45.242261 [Byte1]: 36
8596 16:36:45.246764
8597 16:36:45.247152 Set Vref, RX VrefLevel [Byte0]: 37
8598 16:36:45.250301 [Byte1]: 37
8599 16:36:45.254356
8600 16:36:45.254744 Set Vref, RX VrefLevel [Byte0]: 38
8601 16:36:45.257776 [Byte1]: 38
8602 16:36:45.261534
8603 16:36:45.261961 Set Vref, RX VrefLevel [Byte0]: 39
8604 16:36:45.265310 [Byte1]: 39
8605 16:36:45.269656
8606 16:36:45.270047 Set Vref, RX VrefLevel [Byte0]: 40
8607 16:36:45.272519 [Byte1]: 40
8608 16:36:45.276843
8609 16:36:45.277394 Set Vref, RX VrefLevel [Byte0]: 41
8610 16:36:45.279956 [Byte1]: 41
8611 16:36:45.284421
8612 16:36:45.284813 Set Vref, RX VrefLevel [Byte0]: 42
8613 16:36:45.288040 [Byte1]: 42
8614 16:36:45.292151
8615 16:36:45.292775 Set Vref, RX VrefLevel [Byte0]: 43
8616 16:36:45.295014 [Byte1]: 43
8617 16:36:45.299312
8618 16:36:45.299705 Set Vref, RX VrefLevel [Byte0]: 44
8619 16:36:45.302561 [Byte1]: 44
8620 16:36:45.307364
8621 16:36:45.307812 Set Vref, RX VrefLevel [Byte0]: 45
8622 16:36:45.310274 [Byte1]: 45
8623 16:36:45.314626
8624 16:36:45.315033 Set Vref, RX VrefLevel [Byte0]: 46
8625 16:36:45.320740 [Byte1]: 46
8626 16:36:45.321187
8627 16:36:45.324353 Set Vref, RX VrefLevel [Byte0]: 47
8628 16:36:45.327944 [Byte1]: 47
8629 16:36:45.328337
8630 16:36:45.330920 Set Vref, RX VrefLevel [Byte0]: 48
8631 16:36:45.334634 [Byte1]: 48
8632 16:36:45.335028
8633 16:36:45.337840 Set Vref, RX VrefLevel [Byte0]: 49
8634 16:36:45.340826 [Byte1]: 49
8635 16:36:45.344653
8636 16:36:45.345044 Set Vref, RX VrefLevel [Byte0]: 50
8637 16:36:45.348320 [Byte1]: 50
8638 16:36:45.352060
8639 16:36:45.352451 Set Vref, RX VrefLevel [Byte0]: 51
8640 16:36:45.355134 [Byte1]: 51
8641 16:36:45.359543
8642 16:36:45.359933 Set Vref, RX VrefLevel [Byte0]: 52
8643 16:36:45.363233 [Byte1]: 52
8644 16:36:45.367409
8645 16:36:45.367801 Set Vref, RX VrefLevel [Byte0]: 53
8646 16:36:45.370940 [Byte1]: 53
8647 16:36:45.374591
8648 16:36:45.374992 Set Vref, RX VrefLevel [Byte0]: 54
8649 16:36:45.378399 [Byte1]: 54
8650 16:36:45.382029
8651 16:36:45.382420 Set Vref, RX VrefLevel [Byte0]: 55
8652 16:36:45.385671 [Byte1]: 55
8653 16:36:45.390030
8654 16:36:45.390424 Set Vref, RX VrefLevel [Byte0]: 56
8655 16:36:45.392952 [Byte1]: 56
8656 16:36:45.397525
8657 16:36:45.397989 Set Vref, RX VrefLevel [Byte0]: 57
8658 16:36:45.400576 [Byte1]: 57
8659 16:36:45.405066
8660 16:36:45.405457 Set Vref, RX VrefLevel [Byte0]: 58
8661 16:36:45.407986 [Byte1]: 58
8662 16:36:45.412354
8663 16:36:45.412747 Set Vref, RX VrefLevel [Byte0]: 59
8664 16:36:45.415924 [Byte1]: 59
8665 16:36:45.420010
8666 16:36:45.420496 Set Vref, RX VrefLevel [Byte0]: 60
8667 16:36:45.423165 [Byte1]: 60
8668 16:36:45.427736
8669 16:36:45.428134 Set Vref, RX VrefLevel [Byte0]: 61
8670 16:36:45.430840 [Byte1]: 61
8671 16:36:45.435085
8672 16:36:45.435477 Set Vref, RX VrefLevel [Byte0]: 62
8673 16:36:45.438221 [Byte1]: 62
8674 16:36:45.442603
8675 16:36:45.443046 Set Vref, RX VrefLevel [Byte0]: 63
8676 16:36:45.446031 [Byte1]: 63
8677 16:36:45.449855
8678 16:36:45.450324 Set Vref, RX VrefLevel [Byte0]: 64
8679 16:36:45.453455 [Byte1]: 64
8680 16:36:45.457315
8681 16:36:45.457759 Set Vref, RX VrefLevel [Byte0]: 65
8682 16:36:45.460815 [Byte1]: 65
8683 16:36:45.465374
8684 16:36:45.465838 Set Vref, RX VrefLevel [Byte0]: 66
8685 16:36:45.468146 [Byte1]: 66
8686 16:36:45.472448
8687 16:36:45.472843 Set Vref, RX VrefLevel [Byte0]: 67
8688 16:36:45.475982 [Byte1]: 67
8689 16:36:45.480336
8690 16:36:45.480728 Set Vref, RX VrefLevel [Byte0]: 68
8691 16:36:45.483794 [Byte1]: 68
8692 16:36:45.487689
8693 16:36:45.488080 Set Vref, RX VrefLevel [Byte0]: 69
8694 16:36:45.491381 [Byte1]: 69
8695 16:36:45.495120
8696 16:36:45.495514 Set Vref, RX VrefLevel [Byte0]: 70
8697 16:36:45.499287 [Byte1]: 70
8698 16:36:45.502754
8699 16:36:45.503255 Set Vref, RX VrefLevel [Byte0]: 71
8700 16:36:45.505855 [Byte1]: 71
8701 16:36:45.510384
8702 16:36:45.510775 Set Vref, RX VrefLevel [Byte0]: 72
8703 16:36:45.513478 [Byte1]: 72
8704 16:36:45.517757
8705 16:36:45.518144 Set Vref, RX VrefLevel [Byte0]: 73
8706 16:36:45.521350 [Byte1]: 73
8707 16:36:45.525120
8708 16:36:45.525681 Set Vref, RX VrefLevel [Byte0]: 74
8709 16:36:45.528986 [Byte1]: 74
8710 16:36:45.532842
8711 16:36:45.533228 Set Vref, RX VrefLevel [Byte0]: 75
8712 16:36:45.536481 [Byte1]: 75
8713 16:36:45.540155
8714 16:36:45.543701 Set Vref, RX VrefLevel [Byte0]: 76
8715 16:36:45.547137 [Byte1]: 76
8716 16:36:45.547582
8717 16:36:45.550416 Set Vref, RX VrefLevel [Byte0]: 77
8718 16:36:45.553760 [Byte1]: 77
8719 16:36:45.554149
8720 16:36:45.556987 Final RX Vref Byte 0 = 60 to rank0
8721 16:36:45.560139 Final RX Vref Byte 1 = 56 to rank0
8722 16:36:45.563234 Final RX Vref Byte 0 = 60 to rank1
8723 16:36:45.566554 Final RX Vref Byte 1 = 56 to rank1==
8724 16:36:45.569841 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 16:36:45.573430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 16:36:45.573863 ==
8727 16:36:45.576665 DQS Delay:
8728 16:36:45.577053 DQS0 = 0, DQS1 = 0
8729 16:36:45.577402 DQM Delay:
8730 16:36:45.580478 DQM0 = 134, DQM1 = 130
8731 16:36:45.580862 DQ Delay:
8732 16:36:45.583211 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8733 16:36:45.586861 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8734 16:36:45.590303 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8735 16:36:45.596673 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8736 16:36:45.597096
8737 16:36:45.597429
8738 16:36:45.597926
8739 16:36:45.600137 [DramC_TX_OE_Calibration] TA2
8740 16:36:45.600533 Original DQ_B0 (3 6) =30, OEN = 27
8741 16:36:45.603185 Original DQ_B1 (3 6) =30, OEN = 27
8742 16:36:45.606974 24, 0x0, End_B0=24 End_B1=24
8743 16:36:45.609917 25, 0x0, End_B0=25 End_B1=25
8744 16:36:45.613706 26, 0x0, End_B0=26 End_B1=26
8745 16:36:45.614324 27, 0x0, End_B0=27 End_B1=27
8746 16:36:45.617285 28, 0x0, End_B0=28 End_B1=28
8747 16:36:45.620096 29, 0x0, End_B0=29 End_B1=29
8748 16:36:45.623932 30, 0x0, End_B0=30 End_B1=30
8749 16:36:45.626921 31, 0x4545, End_B0=30 End_B1=30
8750 16:36:45.630509 Byte0 end_step=30 best_step=27
8751 16:36:45.631071 Byte1 end_step=30 best_step=27
8752 16:36:45.633395 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 16:36:45.637269 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 16:36:45.637710
8755 16:36:45.638016
8756 16:36:45.647225 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8757 16:36:45.647792 CH1 RK0: MR19=303, MR18=1724
8758 16:36:45.653427 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8759 16:36:45.653845
8760 16:36:45.656487 ----->DramcWriteLeveling(PI) begin...
8761 16:36:45.656880 ==
8762 16:36:45.660170 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 16:36:45.666595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 16:36:45.666984 ==
8765 16:36:45.670295 Write leveling (Byte 0): 25 => 25
8766 16:36:45.670680 Write leveling (Byte 1): 29 => 29
8767 16:36:45.673083 DramcWriteLeveling(PI) end<-----
8768 16:36:45.673471
8769 16:36:45.676429 ==
8770 16:36:45.676816 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 16:36:45.683118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 16:36:45.683506 ==
8773 16:36:45.686355 [Gating] SW mode calibration
8774 16:36:45.693366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 16:36:45.696492 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 16:36:45.703257 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 16:36:45.706519 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 16:36:45.709707 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
8779 16:36:45.716558 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
8780 16:36:45.719958 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 16:36:45.723482 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 16:36:45.730353 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 16:36:45.733207 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 16:36:45.736915 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 16:36:45.742978 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8786 16:36:45.746732 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8787 16:36:45.749731 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 1)
8788 16:36:45.753603 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 16:36:45.759539 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 16:36:45.763389 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 16:36:45.766265 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 16:36:45.772921 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 16:36:45.776655 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 16:36:45.779762 1 6 8 | B1->B0 | 3535 2323 | 1 0 | (0 0) (0 0)
8795 16:36:45.786364 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8796 16:36:45.789352 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 16:36:45.793044 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 16:36:45.799621 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 16:36:45.803215 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 16:36:45.805827 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 16:36:45.812752 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8802 16:36:45.816325 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8803 16:36:45.819670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8804 16:36:45.826021 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8805 16:36:45.829514 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 16:36:45.832899 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 16:36:45.839312 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 16:36:45.842378 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 16:36:45.845811 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 16:36:45.852348 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 16:36:45.855916 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 16:36:45.859624 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 16:36:45.865692 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 16:36:45.869446 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 16:36:45.872421 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 16:36:45.879310 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 16:36:45.882253 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8818 16:36:45.885902 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8819 16:36:45.892648 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8820 16:36:45.893119 Total UI for P1: 0, mck2ui 16
8821 16:36:45.895779 best dqsien dly found for B1: ( 1, 9, 6)
8822 16:36:45.902538 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8823 16:36:45.905450 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 16:36:45.909019 Total UI for P1: 0, mck2ui 16
8825 16:36:45.912710 best dqsien dly found for B0: ( 1, 9, 14)
8826 16:36:45.915480 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8827 16:36:45.918980 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8828 16:36:45.919526
8829 16:36:45.922265 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8830 16:36:45.928891 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8831 16:36:45.929420 [Gating] SW calibration Done
8832 16:36:45.929847 ==
8833 16:36:45.932585 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 16:36:45.938711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 16:36:45.939100 ==
8836 16:36:45.939553 RX Vref Scan: 0
8837 16:36:45.939968
8838 16:36:45.942364 RX Vref 0 -> 0, step: 1
8839 16:36:45.942757
8840 16:36:45.945291 RX Delay 0 -> 252, step: 8
8841 16:36:45.949155 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8842 16:36:45.952219 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8843 16:36:45.955659 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8844 16:36:45.959187 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8845 16:36:45.965504 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8846 16:36:45.969335 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8847 16:36:45.972315 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8848 16:36:45.975502 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8849 16:36:45.978624 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8850 16:36:45.985283 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8851 16:36:45.989121 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8852 16:36:45.992031 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8853 16:36:45.995557 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8854 16:36:45.999152 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8855 16:36:46.005129 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8856 16:36:46.009028 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8857 16:36:46.009415 ==
8858 16:36:46.011952 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 16:36:46.015761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 16:36:46.016166 ==
8861 16:36:46.018783 DQS Delay:
8862 16:36:46.019171 DQS0 = 0, DQS1 = 0
8863 16:36:46.019495 DQM Delay:
8864 16:36:46.022532 DQM0 = 136, DQM1 = 133
8865 16:36:46.022915 DQ Delay:
8866 16:36:46.025484 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8867 16:36:46.028507 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8868 16:36:46.035666 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8869 16:36:46.038246 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8870 16:36:46.038641
8871 16:36:46.038944
8872 16:36:46.039230 ==
8873 16:36:46.041822 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 16:36:46.044971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 16:36:46.045365 ==
8876 16:36:46.045725
8877 16:36:46.046041
8878 16:36:46.048953 TX Vref Scan disable
8879 16:36:46.052236 == TX Byte 0 ==
8880 16:36:46.055314 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8881 16:36:46.058507 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8882 16:36:46.062217 == TX Byte 1 ==
8883 16:36:46.065284 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8884 16:36:46.069053 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8885 16:36:46.069711 ==
8886 16:36:46.071935 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 16:36:46.074914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 16:36:46.075315 ==
8889 16:36:46.090716
8890 16:36:46.094075 TX Vref early break, caculate TX vref
8891 16:36:46.096887 TX Vref=16, minBit 0, minWin=23, winSum=382
8892 16:36:46.100165 TX Vref=18, minBit 0, minWin=23, winSum=392
8893 16:36:46.103568 TX Vref=20, minBit 0, minWin=24, winSum=400
8894 16:36:46.107000 TX Vref=22, minBit 0, minWin=24, winSum=409
8895 16:36:46.110269 TX Vref=24, minBit 0, minWin=25, winSum=417
8896 16:36:46.116669 TX Vref=26, minBit 0, minWin=25, winSum=423
8897 16:36:46.120591 TX Vref=28, minBit 0, minWin=25, winSum=422
8898 16:36:46.123505 TX Vref=30, minBit 0, minWin=26, winSum=426
8899 16:36:46.127141 TX Vref=32, minBit 0, minWin=25, winSum=411
8900 16:36:46.130049 TX Vref=34, minBit 0, minWin=24, winSum=405
8901 16:36:46.133933 TX Vref=36, minBit 6, minWin=23, winSum=397
8902 16:36:46.139998 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
8903 16:36:46.140394
8904 16:36:46.143747 Final TX Range 0 Vref 30
8905 16:36:46.144144
8906 16:36:46.144451 ==
8907 16:36:46.146683 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 16:36:46.150467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 16:36:46.150865 ==
8910 16:36:46.151170
8911 16:36:46.153251
8912 16:36:46.153667 TX Vref Scan disable
8913 16:36:46.160267 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8914 16:36:46.160710 == TX Byte 0 ==
8915 16:36:46.163685 u2DelayCellOfst[0]=16 cells (5 PI)
8916 16:36:46.166395 u2DelayCellOfst[1]=10 cells (3 PI)
8917 16:36:46.169924 u2DelayCellOfst[2]=0 cells (0 PI)
8918 16:36:46.173404 u2DelayCellOfst[3]=6 cells (2 PI)
8919 16:36:46.177212 u2DelayCellOfst[4]=10 cells (3 PI)
8920 16:36:46.180298 u2DelayCellOfst[5]=16 cells (5 PI)
8921 16:36:46.183268 u2DelayCellOfst[6]=20 cells (6 PI)
8922 16:36:46.187159 u2DelayCellOfst[7]=6 cells (2 PI)
8923 16:36:46.190036 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8924 16:36:46.193649 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8925 16:36:46.196765 == TX Byte 1 ==
8926 16:36:46.199764 u2DelayCellOfst[8]=0 cells (0 PI)
8927 16:36:46.200156 u2DelayCellOfst[9]=3 cells (1 PI)
8928 16:36:46.203289 u2DelayCellOfst[10]=10 cells (3 PI)
8929 16:36:46.206916 u2DelayCellOfst[11]=3 cells (1 PI)
8930 16:36:46.209632 u2DelayCellOfst[12]=13 cells (4 PI)
8931 16:36:46.213000 u2DelayCellOfst[13]=13 cells (4 PI)
8932 16:36:46.216702 u2DelayCellOfst[14]=13 cells (4 PI)
8933 16:36:46.220048 u2DelayCellOfst[15]=16 cells (5 PI)
8934 16:36:46.226331 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8935 16:36:46.229832 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8936 16:36:46.230041 DramC Write-DBI on
8937 16:36:46.230291 ==
8938 16:36:46.233065 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 16:36:46.239557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 16:36:46.239819 ==
8941 16:36:46.240063
8942 16:36:46.240294
8943 16:36:46.240521 TX Vref Scan disable
8944 16:36:46.243278 == TX Byte 0 ==
8945 16:36:46.247000 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8946 16:36:46.250069 == TX Byte 1 ==
8947 16:36:46.253614 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8948 16:36:46.256613 DramC Write-DBI off
8949 16:36:46.256829
8950 16:36:46.257045 [DATLAT]
8951 16:36:46.257248 Freq=1600, CH1 RK1
8952 16:36:46.257446
8953 16:36:46.260298 DATLAT Default: 0xf
8954 16:36:46.260513 0, 0xFFFF, sum = 0
8955 16:36:46.263403 1, 0xFFFF, sum = 0
8956 16:36:46.266538 2, 0xFFFF, sum = 0
8957 16:36:46.266759 3, 0xFFFF, sum = 0
8958 16:36:46.270275 4, 0xFFFF, sum = 0
8959 16:36:46.270546 5, 0xFFFF, sum = 0
8960 16:36:46.273321 6, 0xFFFF, sum = 0
8961 16:36:46.273603 7, 0xFFFF, sum = 0
8962 16:36:46.276960 8, 0xFFFF, sum = 0
8963 16:36:46.277309 9, 0xFFFF, sum = 0
8964 16:36:46.279897 10, 0xFFFF, sum = 0
8965 16:36:46.280309 11, 0xFFFF, sum = 0
8966 16:36:46.283382 12, 0xFFFF, sum = 0
8967 16:36:46.283792 13, 0xFFFF, sum = 0
8968 16:36:46.287116 14, 0x0, sum = 1
8969 16:36:46.287505 15, 0x0, sum = 2
8970 16:36:46.290007 16, 0x0, sum = 3
8971 16:36:46.290399 17, 0x0, sum = 4
8972 16:36:46.293648 best_step = 15
8973 16:36:46.294235
8974 16:36:46.294578 ==
8975 16:36:46.296625 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 16:36:46.300266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 16:36:46.300652 ==
8978 16:36:46.303401 RX Vref Scan: 0
8979 16:36:46.303786
8980 16:36:46.304084 RX Vref 0 -> 0, step: 1
8981 16:36:46.304363
8982 16:36:46.307074 RX Delay 19 -> 252, step: 4
8983 16:36:46.310035 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8984 16:36:46.316642 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8985 16:36:46.320138 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
8986 16:36:46.323025 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8987 16:36:46.326782 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8988 16:36:46.329672 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8989 16:36:46.333443 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8990 16:36:46.339966 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8991 16:36:46.343418 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8992 16:36:46.346274 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8993 16:36:46.349905 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8994 16:36:46.356379 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8995 16:36:46.360140 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8996 16:36:46.363219 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8997 16:36:46.366271 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8998 16:36:46.369864 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8999 16:36:46.373502 ==
9000 16:36:46.373943 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 16:36:46.380216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 16:36:46.380620 ==
9003 16:36:46.380928 DQS Delay:
9004 16:36:46.383317 DQS0 = 0, DQS1 = 0
9005 16:36:46.383711 DQM Delay:
9006 16:36:46.386286 DQM0 = 134, DQM1 = 130
9007 16:36:46.386676 DQ Delay:
9008 16:36:46.389657 DQ0 =138, DQ1 =132, DQ2 =124, DQ3 =130
9009 16:36:46.393387 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9010 16:36:46.396669 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9011 16:36:46.399656 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9012 16:36:46.400046
9013 16:36:46.400351
9014 16:36:46.400628
9015 16:36:46.403327 [DramC_TX_OE_Calibration] TA2
9016 16:36:46.406280 Original DQ_B0 (3 6) =30, OEN = 27
9017 16:36:46.409266 Original DQ_B1 (3 6) =30, OEN = 27
9018 16:36:46.412893 24, 0x0, End_B0=24 End_B1=24
9019 16:36:46.415918 25, 0x0, End_B0=25 End_B1=25
9020 16:36:46.416476 26, 0x0, End_B0=26 End_B1=26
9021 16:36:46.419747 27, 0x0, End_B0=27 End_B1=27
9022 16:36:46.422735 28, 0x0, End_B0=28 End_B1=28
9023 16:36:46.426514 29, 0x0, End_B0=29 End_B1=29
9024 16:36:46.426977 30, 0x0, End_B0=30 End_B1=30
9025 16:36:46.429504 31, 0x4141, End_B0=30 End_B1=30
9026 16:36:46.433155 Byte0 end_step=30 best_step=27
9027 16:36:46.436046 Byte1 end_step=30 best_step=27
9028 16:36:46.439806 Byte0 TX OE(2T, 0.5T) = (3, 3)
9029 16:36:46.442905 Byte1 TX OE(2T, 0.5T) = (3, 3)
9030 16:36:46.443356
9031 16:36:46.443806
9032 16:36:46.449499 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9033 16:36:46.453201 CH1 RK1: MR19=303, MR18=2208
9034 16:36:46.459698 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
9035 16:36:46.462422 [RxdqsGatingPostProcess] freq 1600
9036 16:36:46.466053 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9037 16:36:46.469643 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 16:36:46.472493 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 16:36:46.475938 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 16:36:46.479784 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 16:36:46.482358 best DQS0 dly(2T, 0.5T) = (1, 1)
9042 16:36:46.486010 best DQS1 dly(2T, 0.5T) = (1, 1)
9043 16:36:46.488837 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9044 16:36:46.492486 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9045 16:36:46.495530 Pre-setting of DQS Precalculation
9046 16:36:46.499312 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9047 16:36:46.505575 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9048 16:36:46.515706 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9049 16:36:46.515816
9050 16:36:46.515891
9051 16:36:46.518855 [Calibration Summary] 3200 Mbps
9052 16:36:46.518951 CH 0, Rank 0
9053 16:36:46.522411 SW Impedance : PASS
9054 16:36:46.522497 DUTY Scan : NO K
9055 16:36:46.525420 ZQ Calibration : PASS
9056 16:36:46.529111 Jitter Meter : NO K
9057 16:36:46.529190 CBT Training : PASS
9058 16:36:46.531969 Write leveling : PASS
9059 16:36:46.532068 RX DQS gating : PASS
9060 16:36:46.535652 RX DQ/DQS(RDDQC) : PASS
9061 16:36:46.539054 TX DQ/DQS : PASS
9062 16:36:46.539131 RX DATLAT : PASS
9063 16:36:46.541927 RX DQ/DQS(Engine): PASS
9064 16:36:46.545538 TX OE : PASS
9065 16:36:46.545630 All Pass.
9066 16:36:46.545687
9067 16:36:46.545740 CH 0, Rank 1
9068 16:36:46.548653 SW Impedance : PASS
9069 16:36:46.552455 DUTY Scan : NO K
9070 16:36:46.552532 ZQ Calibration : PASS
9071 16:36:46.555468 Jitter Meter : NO K
9072 16:36:46.558518 CBT Training : PASS
9073 16:36:46.558594 Write leveling : PASS
9074 16:36:46.562212 RX DQS gating : PASS
9075 16:36:46.565240 RX DQ/DQS(RDDQC) : PASS
9076 16:36:46.565339 TX DQ/DQS : PASS
9077 16:36:46.568999 RX DATLAT : PASS
9078 16:36:46.571980 RX DQ/DQS(Engine): PASS
9079 16:36:46.572056 TX OE : PASS
9080 16:36:46.572115 All Pass.
9081 16:36:46.575503
9082 16:36:46.575578 CH 1, Rank 0
9083 16:36:46.579020 SW Impedance : PASS
9084 16:36:46.579095 DUTY Scan : NO K
9085 16:36:46.581864 ZQ Calibration : PASS
9086 16:36:46.581940 Jitter Meter : NO K
9087 16:36:46.585054 CBT Training : PASS
9088 16:36:46.588343 Write leveling : PASS
9089 16:36:46.588443 RX DQS gating : PASS
9090 16:36:46.591739 RX DQ/DQS(RDDQC) : PASS
9091 16:36:46.595227 TX DQ/DQS : PASS
9092 16:36:46.595329 RX DATLAT : PASS
9093 16:36:46.598384 RX DQ/DQS(Engine): PASS
9094 16:36:46.602105 TX OE : PASS
9095 16:36:46.602179 All Pass.
9096 16:36:46.602236
9097 16:36:46.602306 CH 1, Rank 1
9098 16:36:46.605096 SW Impedance : PASS
9099 16:36:46.608136 DUTY Scan : NO K
9100 16:36:46.608245 ZQ Calibration : PASS
9101 16:36:46.611829 Jitter Meter : NO K
9102 16:36:46.614799 CBT Training : PASS
9103 16:36:46.614904 Write leveling : PASS
9104 16:36:46.618370 RX DQS gating : PASS
9105 16:36:46.621927 RX DQ/DQS(RDDQC) : PASS
9106 16:36:46.622032 TX DQ/DQS : PASS
9107 16:36:46.624758 RX DATLAT : PASS
9108 16:36:46.628004 RX DQ/DQS(Engine): PASS
9109 16:36:46.628173 TX OE : PASS
9110 16:36:46.628295 All Pass.
9111 16:36:46.631945
9112 16:36:46.632069 DramC Write-DBI on
9113 16:36:46.634682 PER_BANK_REFRESH: Hybrid Mode
9114 16:36:46.634849 TX_TRACKING: ON
9115 16:36:46.644684 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9116 16:36:46.651875 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9117 16:36:46.661647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9118 16:36:46.665355 [FAST_K] Save calibration result to emmc
9119 16:36:46.665458 sync common calibartion params.
9120 16:36:46.668303 sync cbt_mode0:1, 1:1
9121 16:36:46.672057 dram_init: ddr_geometry: 2
9122 16:36:46.674917 dram_init: ddr_geometry: 2
9123 16:36:46.675002 dram_init: ddr_geometry: 2
9124 16:36:46.678048 0:dram_rank_size:100000000
9125 16:36:46.681811 1:dram_rank_size:100000000
9126 16:36:46.684731 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9127 16:36:46.688503 DFS_SHUFFLE_HW_MODE: ON
9128 16:36:46.691472 dramc_set_vcore_voltage set vcore to 725000
9129 16:36:46.695100 Read voltage for 1600, 0
9130 16:36:46.695193 Vio18 = 0
9131 16:36:46.697975 Vcore = 725000
9132 16:36:46.698067 Vdram = 0
9133 16:36:46.698137 Vddq = 0
9134 16:36:46.698202 Vmddr = 0
9135 16:36:46.701374 switch to 3200 Mbps bootup
9136 16:36:46.704828 [DramcRunTimeConfig]
9137 16:36:46.704913 PHYPLL
9138 16:36:46.708114 DPM_CONTROL_AFTERK: ON
9139 16:36:46.708199 PER_BANK_REFRESH: ON
9140 16:36:46.711521 REFRESH_OVERHEAD_REDUCTION: ON
9141 16:36:46.714993 CMD_PICG_NEW_MODE: OFF
9142 16:36:46.715081 XRTWTW_NEW_MODE: ON
9143 16:36:46.717984 XRTRTR_NEW_MODE: ON
9144 16:36:46.718064 TX_TRACKING: ON
9145 16:36:46.721729 RDSEL_TRACKING: OFF
9146 16:36:46.721827 DQS Precalculation for DVFS: ON
9147 16:36:46.724653 RX_TRACKING: OFF
9148 16:36:46.724738 HW_GATING DBG: ON
9149 16:36:46.728474 ZQCS_ENABLE_LP4: ON
9150 16:36:46.731467 RX_PICG_NEW_MODE: ON
9151 16:36:46.731546 TX_PICG_NEW_MODE: ON
9152 16:36:46.735140 ENABLE_RX_DCM_DPHY: ON
9153 16:36:46.738109 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9154 16:36:46.738191 DUMMY_READ_FOR_TRACKING: OFF
9155 16:36:46.741224 !!! SPM_CONTROL_AFTERK: OFF
9156 16:36:46.745027 !!! SPM could not control APHY
9157 16:36:46.748433 IMPEDANCE_TRACKING: ON
9158 16:36:46.748542 TEMP_SENSOR: ON
9159 16:36:46.751062 HW_SAVE_FOR_SR: OFF
9160 16:36:46.755194 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9161 16:36:46.758449 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9162 16:36:46.758529 Read ODT Tracking: ON
9163 16:36:46.761061 Refresh Rate DeBounce: ON
9164 16:36:46.764952 DFS_NO_QUEUE_FLUSH: ON
9165 16:36:46.768032 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9166 16:36:46.768112 ENABLE_DFS_RUNTIME_MRW: OFF
9167 16:36:46.771175 DDR_RESERVE_NEW_MODE: ON
9168 16:36:46.774630 MR_CBT_SWITCH_FREQ: ON
9169 16:36:46.774716 =========================
9170 16:36:46.794819 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9171 16:36:46.797762 dram_init: ddr_geometry: 2
9172 16:36:46.816240 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9173 16:36:46.819289 dram_init: dram init end (result: 0)
9174 16:36:46.825945 DRAM-K: Full calibration passed in 24460 msecs
9175 16:36:46.829476 MRC: failed to locate region type 0.
9176 16:36:46.829559 DRAM rank0 size:0x100000000,
9177 16:36:46.832988 DRAM rank1 size=0x100000000
9178 16:36:46.842927 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9179 16:36:46.849532 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9180 16:36:46.855716 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9181 16:36:46.862667 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9182 16:36:46.865696 DRAM rank0 size:0x100000000,
9183 16:36:46.869347 DRAM rank1 size=0x100000000
9184 16:36:46.869435 CBMEM:
9185 16:36:46.872468 IMD: root @ 0xfffff000 254 entries.
9186 16:36:46.875427 IMD: root @ 0xffffec00 62 entries.
9187 16:36:46.879105 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9188 16:36:46.882578 WARNING: RO_VPD is uninitialized or empty.
9189 16:36:46.888806 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9190 16:36:46.896171 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9191 16:36:46.909185 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9192 16:36:46.920566 BS: romstage times (exec / console): total (unknown) / 23991 ms
9193 16:36:46.920653
9194 16:36:46.920717
9195 16:36:46.930474 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9196 16:36:46.933383 ARM64: Exception handlers installed.
9197 16:36:46.937049 ARM64: Testing exception
9198 16:36:46.940475 ARM64: Done test exception
9199 16:36:46.940604 Enumerating buses...
9200 16:36:46.943315 Show all devs... Before device enumeration.
9201 16:36:46.947402 Root Device: enabled 1
9202 16:36:46.950627 CPU_CLUSTER: 0: enabled 1
9203 16:36:46.951050 CPU: 00: enabled 1
9204 16:36:46.954090 Compare with tree...
9205 16:36:46.954594 Root Device: enabled 1
9206 16:36:46.957106 CPU_CLUSTER: 0: enabled 1
9207 16:36:46.960776 CPU: 00: enabled 1
9208 16:36:46.961199 Root Device scanning...
9209 16:36:46.963691 scan_static_bus for Root Device
9210 16:36:46.967459 CPU_CLUSTER: 0 enabled
9211 16:36:46.970497 scan_static_bus for Root Device done
9212 16:36:46.974291 scan_bus: bus Root Device finished in 8 msecs
9213 16:36:46.974683 done
9214 16:36:46.980376 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9215 16:36:46.984231 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9216 16:36:46.990206 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9217 16:36:46.993744 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9218 16:36:46.997426 Allocating resources...
9219 16:36:46.997895 Reading resources...
9220 16:36:47.004199 Root Device read_resources bus 0 link: 0
9221 16:36:47.004769 DRAM rank0 size:0x100000000,
9222 16:36:47.007022 DRAM rank1 size=0x100000000
9223 16:36:47.010570 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9224 16:36:47.013921 CPU: 00 missing read_resources
9225 16:36:47.016663 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9226 16:36:47.023692 Root Device read_resources bus 0 link: 0 done
9227 16:36:47.024366 Done reading resources.
9228 16:36:47.030112 Show resources in subtree (Root Device)...After reading.
9229 16:36:47.033058 Root Device child on link 0 CPU_CLUSTER: 0
9230 16:36:47.036762 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 16:36:47.046367 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 16:36:47.046546 CPU: 00
9233 16:36:47.049993 Root Device assign_resources, bus 0 link: 0
9234 16:36:47.052984 CPU_CLUSTER: 0 missing set_resources
9235 16:36:47.059891 Root Device assign_resources, bus 0 link: 0 done
9236 16:36:47.060024 Done setting resources.
9237 16:36:47.066380 Show resources in subtree (Root Device)...After assigning values.
9238 16:36:47.069883 Root Device child on link 0 CPU_CLUSTER: 0
9239 16:36:47.072670 CPU_CLUSTER: 0 child on link 0 CPU: 00
9240 16:36:47.083362 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9241 16:36:47.083506 CPU: 00
9242 16:36:47.086452 Done allocating resources.
9243 16:36:47.089456 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9244 16:36:47.093189 Enabling resources...
9245 16:36:47.093323 done.
9246 16:36:47.099968 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9247 16:36:47.100119 Initializing devices...
9248 16:36:47.102865 Root Device init
9249 16:36:47.103008 init hardware done!
9250 16:36:47.105978 0x00000018: ctrlr->caps
9251 16:36:47.109967 52.000 MHz: ctrlr->f_max
9252 16:36:47.110387 0.400 MHz: ctrlr->f_min
9253 16:36:47.113021 0x40ff8080: ctrlr->voltages
9254 16:36:47.113424 sclk: 390625
9255 16:36:47.116941 Bus Width = 1
9256 16:36:47.117340 sclk: 390625
9257 16:36:47.119603 Bus Width = 1
9258 16:36:47.120119 Early init status = 3
9259 16:36:47.126120 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9260 16:36:47.129570 in-header: 03 fc 00 00 01 00 00 00
9261 16:36:47.129970 in-data: 00
9262 16:36:47.136691 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9263 16:36:47.140054 in-header: 03 fd 00 00 00 00 00 00
9264 16:36:47.143454 in-data:
9265 16:36:47.146611 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9266 16:36:47.151153 in-header: 03 fc 00 00 01 00 00 00
9267 16:36:47.154031 in-data: 00
9268 16:36:47.157859 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9269 16:36:47.162967 in-header: 03 fd 00 00 00 00 00 00
9270 16:36:47.165853 in-data:
9271 16:36:47.169926 [SSUSB] Setting up USB HOST controller...
9272 16:36:47.172591 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9273 16:36:47.176530 [SSUSB] phy power-on done.
9274 16:36:47.179348 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9275 16:36:47.186550 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9276 16:36:47.189483 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9277 16:36:47.196282 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9278 16:36:47.202979 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9279 16:36:47.209089 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9280 16:36:47.216240 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9281 16:36:47.222819 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9282 16:36:47.225712 SPM: binary array size = 0x9dc
9283 16:36:47.229325 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9284 16:36:47.236362 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9285 16:36:47.242973 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9286 16:36:47.245618 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9287 16:36:47.252656 configure_display: Starting display init
9288 16:36:47.286407 anx7625_power_on_init: Init interface.
9289 16:36:47.289658 anx7625_disable_pd_protocol: Disabled PD feature.
9290 16:36:47.292478 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9291 16:36:47.320706 anx7625_start_dp_work: Secure OCM version=00
9292 16:36:47.323577 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9293 16:36:47.338591 sp_tx_get_edid_block: EDID Block = 1
9294 16:36:47.440612 Extracted contents:
9295 16:36:47.444425 header: 00 ff ff ff ff ff ff 00
9296 16:36:47.447277 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9297 16:36:47.450922 version: 01 04
9298 16:36:47.453817 basic params: 95 1f 11 78 0a
9299 16:36:47.457750 chroma info: 76 90 94 55 54 90 27 21 50 54
9300 16:36:47.460928 established: 00 00 00
9301 16:36:47.467744 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9302 16:36:47.470708 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9303 16:36:47.477610 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9304 16:36:47.484470 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9305 16:36:47.490974 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9306 16:36:47.494188 extensions: 00
9307 16:36:47.494619 checksum: fb
9308 16:36:47.494926
9309 16:36:47.497642 Manufacturer: IVO Model 57d Serial Number 0
9310 16:36:47.500944 Made week 0 of 2020
9311 16:36:47.501335 EDID version: 1.4
9312 16:36:47.504401 Digital display
9313 16:36:47.507770 6 bits per primary color channel
9314 16:36:47.508173 DisplayPort interface
9315 16:36:47.511094 Maximum image size: 31 cm x 17 cm
9316 16:36:47.514462 Gamma: 220%
9317 16:36:47.515132 Check DPMS levels
9318 16:36:47.517505 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9319 16:36:47.520601 First detailed timing is preferred timing
9320 16:36:47.524363 Established timings supported:
9321 16:36:47.527458 Standard timings supported:
9322 16:36:47.531147 Detailed timings
9323 16:36:47.534074 Hex of detail: 383680a07038204018303c0035ae10000019
9324 16:36:47.537642 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9325 16:36:47.544164 0780 0798 07c8 0820 hborder 0
9326 16:36:47.547000 0438 043b 0447 0458 vborder 0
9327 16:36:47.550471 -hsync -vsync
9328 16:36:47.550622 Did detailed timing
9329 16:36:47.553720 Hex of detail: 000000000000000000000000000000000000
9330 16:36:47.556997 Manufacturer-specified data, tag 0
9331 16:36:47.563916 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9332 16:36:47.564087 ASCII string: InfoVision
9333 16:36:47.570589 Hex of detail: 000000fe00523134304e574635205248200a
9334 16:36:47.573560 ASCII string: R140NWF5 RH
9335 16:36:47.573665 Checksum
9336 16:36:47.573740 Checksum: 0xfb (valid)
9337 16:36:47.580306 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9338 16:36:47.584024 DSI data_rate: 832800000 bps
9339 16:36:47.587140 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9340 16:36:47.593845 anx7625_parse_edid: pixelclock(138800).
9341 16:36:47.596730 hactive(1920), hsync(48), hfp(24), hbp(88)
9342 16:36:47.600448 vactive(1080), vsync(12), vfp(3), vbp(17)
9343 16:36:47.603456 anx7625_dsi_config: config dsi.
9344 16:36:47.609852 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9345 16:36:47.623018 anx7625_dsi_config: success to config DSI
9346 16:36:47.626431 anx7625_dp_start: MIPI phy setup OK.
9347 16:36:47.629655 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9348 16:36:47.632935 mtk_ddp_mode_set invalid vrefresh 60
9349 16:36:47.636428 main_disp_path_setup
9350 16:36:47.636528 ovl_layer_smi_id_en
9351 16:36:47.639426 ovl_layer_smi_id_en
9352 16:36:47.639532 ccorr_config
9353 16:36:47.639619 aal_config
9354 16:36:47.643083 gamma_config
9355 16:36:47.643168 postmask_config
9356 16:36:47.646159 dither_config
9357 16:36:47.649926 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9358 16:36:47.656689 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9359 16:36:47.659620 Root Device init finished in 553 msecs
9360 16:36:47.659726 CPU_CLUSTER: 0 init
9361 16:36:47.669783 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9362 16:36:47.673148 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9363 16:36:47.676094 APU_MBOX 0x190000b0 = 0x10001
9364 16:36:47.679731 APU_MBOX 0x190001b0 = 0x10001
9365 16:36:47.683705 APU_MBOX 0x190005b0 = 0x10001
9366 16:36:47.686355 APU_MBOX 0x190006b0 = 0x10001
9367 16:36:47.689367 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9368 16:36:47.701765 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9369 16:36:47.714131 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9370 16:36:47.721371 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9371 16:36:47.732390 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9372 16:36:47.741708 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9373 16:36:47.745232 CPU_CLUSTER: 0 init finished in 81 msecs
9374 16:36:47.748574 Devices initialized
9375 16:36:47.752011 Show all devs... After init.
9376 16:36:47.752113 Root Device: enabled 1
9377 16:36:47.755354 CPU_CLUSTER: 0: enabled 1
9378 16:36:47.758344 CPU: 00: enabled 1
9379 16:36:47.761529 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9380 16:36:47.765294 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9381 16:36:47.768510 ELOG: NV offset 0x57f000 size 0x1000
9382 16:36:47.775169 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9383 16:36:47.781689 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9384 16:36:47.785369 ELOG: Event(17) added with size 13 at 2024-06-17 16:36:47 UTC
9385 16:36:47.788808 out: cmd=0x121: 03 db 21 01 00 00 00 00
9386 16:36:47.792253 in-header: 03 9e 00 00 2c 00 00 00
9387 16:36:47.805299 in-data: a0 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9388 16:36:47.811888 ELOG: Event(A1) added with size 10 at 2024-06-17 16:36:47 UTC
9389 16:36:47.818796 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9390 16:36:47.826024 ELOG: Event(A0) added with size 9 at 2024-06-17 16:36:47 UTC
9391 16:36:47.828924 elog_add_boot_reason: Logged dev mode boot
9392 16:36:47.832588 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9393 16:36:47.835575 Finalize devices...
9394 16:36:47.835968 Devices finalized
9395 16:36:47.842279 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9396 16:36:47.845921 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9397 16:36:47.848809 in-header: 03 07 00 00 08 00 00 00
9398 16:36:47.852581 in-data: aa e4 47 04 13 02 00 00
9399 16:36:47.855592 Chrome EC: UHEPI supported
9400 16:36:47.862387 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9401 16:36:47.865235 in-header: 03 a9 00 00 08 00 00 00
9402 16:36:47.868607 in-data: 84 60 60 08 00 00 00 00
9403 16:36:47.872017 ELOG: Event(91) added with size 10 at 2024-06-17 16:36:47 UTC
9404 16:36:47.879213 Chrome EC: clear events_b mask to 0x0000000020004000
9405 16:36:47.885816 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9406 16:36:47.889379 in-header: 03 fd 00 00 00 00 00 00
9407 16:36:47.890016 in-data:
9408 16:36:47.896245 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9409 16:36:47.899269 Writing coreboot table at 0xffe64000
9410 16:36:47.902184 0. 000000000010a000-0000000000113fff: RAMSTAGE
9411 16:36:47.905982 1. 0000000040000000-00000000400fffff: RAM
9412 16:36:47.909340 2. 0000000040100000-000000004032afff: RAMSTAGE
9413 16:36:47.912788 3. 000000004032b000-00000000545fffff: RAM
9414 16:36:47.918854 4. 0000000054600000-000000005465ffff: BL31
9415 16:36:47.922510 5. 0000000054660000-00000000ffe63fff: RAM
9416 16:36:47.925640 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9417 16:36:47.932761 7. 0000000100000000-000000023fffffff: RAM
9418 16:36:47.933185 Passing 5 GPIOs to payload:
9419 16:36:47.939989 NAME | PORT | POLARITY | VALUE
9420 16:36:47.942227 EC in RW | 0x000000aa | low | undefined
9421 16:36:47.946041 EC interrupt | 0x00000005 | low | undefined
9422 16:36:47.952612 TPM interrupt | 0x000000ab | high | undefined
9423 16:36:47.955653 SD card detect | 0x00000011 | high | undefined
9424 16:36:47.962372 speaker enable | 0x00000093 | high | undefined
9425 16:36:47.965349 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9426 16:36:47.969029 in-header: 03 f9 00 00 02 00 00 00
9427 16:36:47.969439 in-data: 02 00
9428 16:36:47.971953 ADC[4]: Raw value=904357 ID=7
9429 16:36:47.975559 ADC[3]: Raw value=213441 ID=1
9430 16:36:47.975952 RAM Code: 0x71
9431 16:36:47.978977 ADC[6]: Raw value=75332 ID=0
9432 16:36:47.981821 ADC[5]: Raw value=213072 ID=1
9433 16:36:47.982102 SKU Code: 0x1
9434 16:36:47.988483 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f44
9435 16:36:47.992122 coreboot table: 964 bytes.
9436 16:36:47.996053 IMD ROOT 0. 0xfffff000 0x00001000
9437 16:36:47.998876 IMD SMALL 1. 0xffffe000 0x00001000
9438 16:36:48.002587 RO MCACHE 2. 0xffffc000 0x00001104
9439 16:36:48.005705 CONSOLE 3. 0xfff7c000 0x00080000
9440 16:36:48.008729 FMAP 4. 0xfff7b000 0x00000452
9441 16:36:48.008855 TIME STAMP 5. 0xfff7a000 0x00000910
9442 16:36:48.012529 VBOOT WORK 6. 0xfff66000 0x00014000
9443 16:36:48.015518 RAMOOPS 7. 0xffe66000 0x00100000
9444 16:36:48.019054 COREBOOT 8. 0xffe64000 0x00002000
9445 16:36:48.022496 IMD small region:
9446 16:36:48.025328 IMD ROOT 0. 0xffffec00 0x00000400
9447 16:36:48.028756 VPD 1. 0xffffeb80 0x0000006c
9448 16:36:48.032191 MMC STATUS 2. 0xffffeb60 0x00000004
9449 16:36:48.039024 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9450 16:36:48.045272 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9451 16:36:48.083705 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9452 16:36:48.087365 Checking segment from ROM address 0x40100000
9453 16:36:48.090342 Checking segment from ROM address 0x4010001c
9454 16:36:48.097479 Loading segment from ROM address 0x40100000
9455 16:36:48.097642 code (compression=0)
9456 16:36:48.103827 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9457 16:36:48.114165 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9458 16:36:48.114282 it's not compressed!
9459 16:36:48.120846 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9460 16:36:48.123803 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9461 16:36:48.144622 Loading segment from ROM address 0x4010001c
9462 16:36:48.144738 Entry Point 0x80000000
9463 16:36:48.147624 Loaded segments
9464 16:36:48.151521 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9465 16:36:48.157995 Jumping to boot code at 0x80000000(0xffe64000)
9466 16:36:48.164844 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9467 16:36:48.171113 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9468 16:36:48.178961 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9469 16:36:48.181946 Checking segment from ROM address 0x40100000
9470 16:36:48.185636 Checking segment from ROM address 0x4010001c
9471 16:36:48.192508 Loading segment from ROM address 0x40100000
9472 16:36:48.192635 code (compression=1)
9473 16:36:48.199236 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9474 16:36:48.208935 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9475 16:36:48.209189 using LZMA
9476 16:36:48.217179 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9477 16:36:48.224484 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9478 16:36:48.227572 Loading segment from ROM address 0x4010001c
9479 16:36:48.228050 Entry Point 0x54601000
9480 16:36:48.231224 Loaded segments
9481 16:36:48.234307 NOTICE: MT8192 bl31_setup
9482 16:36:48.241154 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9483 16:36:48.244821 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9484 16:36:48.247591 WARNING: region 0:
9485 16:36:48.251213 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 16:36:48.251642 WARNING: region 1:
9487 16:36:48.257807 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9488 16:36:48.260889 WARNING: region 2:
9489 16:36:48.264448 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9490 16:36:48.267366 WARNING: region 3:
9491 16:36:48.270760 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 16:36:48.274396 WARNING: region 4:
9493 16:36:48.281252 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 16:36:48.281671 WARNING: region 5:
9495 16:36:48.284435 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 16:36:48.287360 WARNING: region 6:
9497 16:36:48.291029 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 16:36:48.294578 WARNING: region 7:
9499 16:36:48.297533 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 16:36:48.304262 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9501 16:36:48.307243 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9502 16:36:48.310977 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9503 16:36:48.317540 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9504 16:36:48.320693 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9505 16:36:48.324430 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9506 16:36:48.330793 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9507 16:36:48.334401 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9508 16:36:48.340500 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9509 16:36:48.343765 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9510 16:36:48.347562 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9511 16:36:48.354070 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9512 16:36:48.356969 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9513 16:36:48.360671 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9514 16:36:48.366718 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9515 16:36:48.370416 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9516 16:36:48.377216 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9517 16:36:48.380386 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9518 16:36:48.384143 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9519 16:36:48.390407 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9520 16:36:48.393873 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9521 16:36:48.396821 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9522 16:36:48.404238 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9523 16:36:48.407125 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9524 16:36:48.413762 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9525 16:36:48.416727 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9526 16:36:48.423504 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9527 16:36:48.427386 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9528 16:36:48.430149 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9529 16:36:48.437177 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9530 16:36:48.440439 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9531 16:36:48.443421 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9532 16:36:48.450552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9533 16:36:48.453668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9534 16:36:48.457153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9535 16:36:48.463372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9536 16:36:48.466747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9537 16:36:48.470118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9538 16:36:48.473896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9539 16:36:48.476747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9540 16:36:48.483388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9541 16:36:48.487082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9542 16:36:48.490252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9543 16:36:48.496837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9544 16:36:48.500394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9545 16:36:48.503292 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9546 16:36:48.506819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9547 16:36:48.513610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9548 16:36:48.516552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9549 16:36:48.523417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9550 16:36:48.526496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9551 16:36:48.529582 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9552 16:36:48.536360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9553 16:36:48.540049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9554 16:36:48.546753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9555 16:36:48.549900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9556 16:36:48.556677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9557 16:36:48.559759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9558 16:36:48.562938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9559 16:36:48.569467 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9560 16:36:48.572883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9561 16:36:48.579693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9562 16:36:48.583211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9563 16:36:48.589662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9564 16:36:48.593039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9565 16:36:48.596033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9566 16:36:48.602750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9567 16:36:48.606404 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9568 16:36:48.612880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9569 16:36:48.616520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9570 16:36:48.623122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9571 16:36:48.626189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9572 16:36:48.629820 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9573 16:36:48.635852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9574 16:36:48.639197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9575 16:36:48.645589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9576 16:36:48.649415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9577 16:36:48.656061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9578 16:36:48.659001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9579 16:36:48.665716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9580 16:36:48.669461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9581 16:36:48.672515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9582 16:36:48.679170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9583 16:36:48.682915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9584 16:36:48.689420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9585 16:36:48.692219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9586 16:36:48.699041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9587 16:36:48.702348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9588 16:36:48.706014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9589 16:36:48.712095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9590 16:36:48.715640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9591 16:36:48.722380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9592 16:36:48.725877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9593 16:36:48.732740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9594 16:36:48.735661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9595 16:36:48.742463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9596 16:36:48.745468 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9597 16:36:48.749226 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9598 16:36:48.752033 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9599 16:36:48.758808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9600 16:36:48.762634 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9601 16:36:48.765759 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9602 16:36:48.772376 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9603 16:36:48.775881 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9604 16:36:48.779000 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9605 16:36:48.786255 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9606 16:36:48.789318 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9607 16:36:48.796070 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9608 16:36:48.799279 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9609 16:36:48.802908 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9610 16:36:48.808898 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9611 16:36:48.812305 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9612 16:36:48.819639 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9613 16:36:48.822465 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9614 16:36:48.825859 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9615 16:36:48.832595 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9616 16:36:48.836115 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9617 16:36:48.839502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9618 16:36:48.845862 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9619 16:36:48.849632 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9620 16:36:48.852656 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9621 16:36:48.856384 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9622 16:36:48.858985 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9623 16:36:48.866340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9624 16:36:48.869265 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9625 16:36:48.876030 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9626 16:36:48.878943 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9627 16:36:48.882637 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9628 16:36:48.889805 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9629 16:36:48.892762 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9630 16:36:48.895781 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9631 16:36:48.902491 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9632 16:36:48.906185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9633 16:36:48.912807 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9634 16:36:48.916465 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9635 16:36:48.919469 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9636 16:36:48.925976 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9637 16:36:48.929733 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9638 16:36:48.936284 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9639 16:36:48.939834 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9640 16:36:48.942600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9641 16:36:48.949328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9642 16:36:48.952663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9643 16:36:48.959121 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9644 16:36:48.962851 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9645 16:36:48.966175 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9646 16:36:48.972769 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9647 16:36:48.976297 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9648 16:36:48.979261 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9649 16:36:48.985854 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9650 16:36:48.989329 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9651 16:36:48.995993 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9652 16:36:48.999804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9653 16:36:49.002686 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9654 16:36:49.009462 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9655 16:36:49.012961 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9656 16:36:49.019639 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9657 16:36:49.022545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9658 16:36:49.026290 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9659 16:36:49.032628 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9660 16:36:49.036204 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9661 16:36:49.039156 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9662 16:36:49.046180 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9663 16:36:49.049688 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9664 16:36:49.056556 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9665 16:36:49.059342 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9666 16:36:49.062797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9667 16:36:49.069087 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9668 16:36:49.072735 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9669 16:36:49.079323 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9670 16:36:49.082990 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9671 16:36:49.086587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9672 16:36:49.092886 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9673 16:36:49.096222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9674 16:36:49.099230 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9675 16:36:49.105797 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9676 16:36:49.109646 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9677 16:36:49.116286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9678 16:36:49.119222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9679 16:36:49.122778 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9680 16:36:49.129641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9681 16:36:49.132516 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9682 16:36:49.139266 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9683 16:36:49.142834 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9684 16:36:49.146421 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9685 16:36:49.153032 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9686 16:36:49.155819 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9687 16:36:49.159539 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9688 16:36:49.166089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9689 16:36:49.169029 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9690 16:36:49.176253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9691 16:36:49.179211 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9692 16:36:49.185461 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9693 16:36:49.188544 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9694 16:36:49.192181 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9695 16:36:49.198909 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9696 16:36:49.201819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9697 16:36:49.208829 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9698 16:36:49.212311 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9699 16:36:49.215179 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9700 16:36:49.221810 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9701 16:36:49.225458 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9702 16:36:49.232256 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9703 16:36:49.235384 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9704 16:36:49.241987 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9705 16:36:49.245727 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9706 16:36:49.248519 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9707 16:36:49.255876 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9708 16:36:49.258887 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9709 16:36:49.265390 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9710 16:36:49.268750 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9711 16:36:49.272412 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9712 16:36:49.279116 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9713 16:36:49.281991 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9714 16:36:49.288658 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9715 16:36:49.292384 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9716 16:36:49.295308 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9717 16:36:49.301890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9718 16:36:49.305621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9719 16:36:49.312217 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9720 16:36:49.315224 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9721 16:36:49.321627 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9722 16:36:49.325038 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9723 16:36:49.328419 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9724 16:36:49.335061 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9725 16:36:49.338748 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9726 16:36:49.345321 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9727 16:36:49.348339 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9728 16:36:49.352064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9729 16:36:49.358565 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9730 16:36:49.361536 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9731 16:36:49.365334 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9732 16:36:49.368337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9733 16:36:49.375076 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9734 16:36:49.378668 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9735 16:36:49.382041 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9736 16:36:49.388309 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9737 16:36:49.391960 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9738 16:36:49.394885 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9739 16:36:49.401802 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9740 16:36:49.404677 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9741 16:36:49.411852 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9742 16:36:49.414675 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9743 16:36:49.418381 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9744 16:36:49.425173 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9745 16:36:49.428178 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9746 16:36:49.431866 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9747 16:36:49.438184 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9748 16:36:49.441774 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9749 16:36:49.444627 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9750 16:36:49.452033 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9751 16:36:49.454973 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9752 16:36:49.461815 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9753 16:36:49.464958 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9754 16:36:49.468455 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9755 16:36:49.474788 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9756 16:36:49.477768 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9757 16:36:49.481717 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9758 16:36:49.487801 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9759 16:36:49.491300 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9760 16:36:49.494776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9761 16:36:49.501075 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9762 16:36:49.504876 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9763 16:36:49.507924 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9764 16:36:49.514691 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9765 16:36:49.518284 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9766 16:36:49.524683 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9767 16:36:49.527589 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9768 16:36:49.531292 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9769 16:36:49.535065 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9770 16:36:49.541210 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9771 16:36:49.544890 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9772 16:36:49.548482 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9773 16:36:49.551462 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9774 16:36:49.558154 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9775 16:36:49.561744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9776 16:36:49.564628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9777 16:36:49.568478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9778 16:36:49.574454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9779 16:36:49.578061 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9780 16:36:49.581527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9781 16:36:49.584445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9782 16:36:49.591177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9783 16:36:49.594946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9784 16:36:49.601514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9785 16:36:49.604280 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9786 16:36:49.607760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9787 16:36:49.614546 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9788 16:36:49.618181 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9789 16:36:49.624173 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9790 16:36:49.627843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9791 16:36:49.635071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9792 16:36:49.637914 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9793 16:36:49.641264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9794 16:36:49.647944 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9795 16:36:49.650872 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9796 16:36:49.657442 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9797 16:36:49.661124 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9798 16:36:49.664048 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9799 16:36:49.670875 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9800 16:36:49.674641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9801 16:36:49.680671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9802 16:36:49.684225 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9803 16:36:49.687279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9804 16:36:49.694237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9805 16:36:49.697882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9806 16:36:49.703940 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9807 16:36:49.707562 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9808 16:36:49.710595 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9809 16:36:49.717857 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9810 16:36:49.720711 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9811 16:36:49.727735 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9812 16:36:49.731474 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9813 16:36:49.734163 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9814 16:36:49.740685 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9815 16:36:49.744294 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9816 16:36:49.750919 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9817 16:36:49.754436 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9818 16:36:49.760915 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9819 16:36:49.763807 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9820 16:36:49.767462 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9821 16:36:49.774283 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9822 16:36:49.777346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9823 16:36:49.781114 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9824 16:36:49.787782 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9825 16:36:49.790722 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9826 16:36:49.797994 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9827 16:36:49.800933 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9828 16:36:49.807503 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9829 16:36:49.811312 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9830 16:36:49.814360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9831 16:36:49.821051 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9832 16:36:49.824180 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9833 16:36:49.830744 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9834 16:36:49.834494 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9835 16:36:49.837370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9836 16:36:49.843880 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9837 16:36:49.847439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9838 16:36:49.854049 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9839 16:36:49.857766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9840 16:36:49.860575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9841 16:36:49.867100 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9842 16:36:49.870646 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9843 16:36:49.877015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9844 16:36:49.880680 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9845 16:36:49.883651 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9846 16:36:49.890692 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9847 16:36:49.893421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9848 16:36:49.900249 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9849 16:36:49.903970 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9850 16:36:49.910583 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9851 16:36:49.913455 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9852 16:36:49.917240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9853 16:36:49.923263 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9854 16:36:49.926960 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9855 16:36:49.933433 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9856 16:36:49.937123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9857 16:36:49.940215 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9858 16:36:49.946767 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9859 16:36:49.950283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9860 16:36:49.956836 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9861 16:36:49.960466 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9862 16:36:49.967137 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9863 16:36:49.970109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9864 16:36:49.973688 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9865 16:36:49.980226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9866 16:36:49.983934 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9867 16:36:49.990229 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9868 16:36:49.993834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9869 16:36:50.000309 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9870 16:36:50.003318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9871 16:36:50.007084 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9872 16:36:50.013705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9873 16:36:50.016660 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9874 16:36:50.023628 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9875 16:36:50.026541 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9876 16:36:50.033879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9877 16:36:50.036904 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9878 16:36:50.040527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9879 16:36:50.046478 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9880 16:36:50.050302 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9881 16:36:50.057010 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9882 16:36:50.059802 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9883 16:36:50.067087 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9884 16:36:50.070097 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9885 16:36:50.073775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9886 16:36:50.080455 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9887 16:36:50.083426 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9888 16:36:50.090395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9889 16:36:50.093299 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9890 16:36:50.099944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9891 16:36:50.103544 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9892 16:36:50.110131 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9893 16:36:50.112989 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9894 16:36:50.116514 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9895 16:36:50.123227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9896 16:36:50.126227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9897 16:36:50.132850 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9898 16:36:50.136411 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9899 16:36:50.143167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9900 16:36:50.146191 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9901 16:36:50.149913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9902 16:36:50.156556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9903 16:36:50.159552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9904 16:36:50.166241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9905 16:36:50.169815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9906 16:36:50.176230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9907 16:36:50.179292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9908 16:36:50.186084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9909 16:36:50.189963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9910 16:36:50.196030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9911 16:36:50.199771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9912 16:36:50.202646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9913 16:36:50.209201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9914 16:36:50.212832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9915 16:36:50.219402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9916 16:36:50.223064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9917 16:36:50.229111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9918 16:36:50.232798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9919 16:36:50.239229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9920 16:36:50.242782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9921 16:36:50.249205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9922 16:36:50.252733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9923 16:36:50.259393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9924 16:36:50.262382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9925 16:36:50.269156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9926 16:36:50.272833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9927 16:36:50.279474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9928 16:36:50.282383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9929 16:36:50.289543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9930 16:36:50.292350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9931 16:36:50.299158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9932 16:36:50.302881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9933 16:36:50.309439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9934 16:36:50.312367 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9935 16:36:50.316163 INFO: [APUAPC] vio 0
9936 16:36:50.319149 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9937 16:36:50.325809 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9938 16:36:50.329389 INFO: [APUAPC] D0_APC_0: 0x400510
9939 16:36:50.329464 INFO: [APUAPC] D0_APC_1: 0x0
9940 16:36:50.332398 INFO: [APUAPC] D0_APC_2: 0x1540
9941 16:36:50.336074 INFO: [APUAPC] D0_APC_3: 0x0
9942 16:36:50.339031 INFO: [APUAPC] D1_APC_0: 0xffffffff
9943 16:36:50.342552 INFO: [APUAPC] D1_APC_1: 0xffffffff
9944 16:36:50.346100 INFO: [APUAPC] D1_APC_2: 0x3fffff
9945 16:36:50.348861 INFO: [APUAPC] D1_APC_3: 0x0
9946 16:36:50.352638 INFO: [APUAPC] D2_APC_0: 0xffffffff
9947 16:36:50.356041 INFO: [APUAPC] D2_APC_1: 0xffffffff
9948 16:36:50.359068 INFO: [APUAPC] D2_APC_2: 0x3fffff
9949 16:36:50.362848 INFO: [APUAPC] D2_APC_3: 0x0
9950 16:36:50.365850 INFO: [APUAPC] D3_APC_0: 0xffffffff
9951 16:36:50.369361 INFO: [APUAPC] D3_APC_1: 0xffffffff
9952 16:36:50.372399 INFO: [APUAPC] D3_APC_2: 0x3fffff
9953 16:36:50.376082 INFO: [APUAPC] D3_APC_3: 0x0
9954 16:36:50.379061 INFO: [APUAPC] D4_APC_0: 0xffffffff
9955 16:36:50.382573 INFO: [APUAPC] D4_APC_1: 0xffffffff
9956 16:36:50.386147 INFO: [APUAPC] D4_APC_2: 0x3fffff
9957 16:36:50.389486 INFO: [APUAPC] D4_APC_3: 0x0
9958 16:36:50.392526 INFO: [APUAPC] D5_APC_0: 0xffffffff
9959 16:36:50.396188 INFO: [APUAPC] D5_APC_1: 0xffffffff
9960 16:36:50.399140 INFO: [APUAPC] D5_APC_2: 0x3fffff
9961 16:36:50.402819 INFO: [APUAPC] D5_APC_3: 0x0
9962 16:36:50.405785 INFO: [APUAPC] D6_APC_0: 0xffffffff
9963 16:36:50.409474 INFO: [APUAPC] D6_APC_1: 0xffffffff
9964 16:36:50.412425 INFO: [APUAPC] D6_APC_2: 0x3fffff
9965 16:36:50.416184 INFO: [APUAPC] D6_APC_3: 0x0
9966 16:36:50.419132 INFO: [APUAPC] D7_APC_0: 0xffffffff
9967 16:36:50.422590 INFO: [APUAPC] D7_APC_1: 0xffffffff
9968 16:36:50.425534 INFO: [APUAPC] D7_APC_2: 0x3fffff
9969 16:36:50.429345 INFO: [APUAPC] D7_APC_3: 0x0
9970 16:36:50.432253 INFO: [APUAPC] D8_APC_0: 0xffffffff
9971 16:36:50.435801 INFO: [APUAPC] D8_APC_1: 0xffffffff
9972 16:36:50.438867 INFO: [APUAPC] D8_APC_2: 0x3fffff
9973 16:36:50.438942 INFO: [APUAPC] D8_APC_3: 0x0
9974 16:36:50.445512 INFO: [APUAPC] D9_APC_0: 0xffffffff
9975 16:36:50.449254 INFO: [APUAPC] D9_APC_1: 0xffffffff
9976 16:36:50.452154 INFO: [APUAPC] D9_APC_2: 0x3fffff
9977 16:36:50.452229 INFO: [APUAPC] D9_APC_3: 0x0
9978 16:36:50.455814 INFO: [APUAPC] D10_APC_0: 0xffffffff
9979 16:36:50.462144 INFO: [APUAPC] D10_APC_1: 0xffffffff
9980 16:36:50.465447 INFO: [APUAPC] D10_APC_2: 0x3fffff
9981 16:36:50.465539 INFO: [APUAPC] D10_APC_3: 0x0
9982 16:36:50.471917 INFO: [APUAPC] D11_APC_0: 0xffffffff
9983 16:36:50.475599 INFO: [APUAPC] D11_APC_1: 0xffffffff
9984 16:36:50.478560 INFO: [APUAPC] D11_APC_2: 0x3fffff
9985 16:36:50.478638 INFO: [APUAPC] D11_APC_3: 0x0
9986 16:36:50.485316 INFO: [APUAPC] D12_APC_0: 0xffffffff
9987 16:36:50.489105 INFO: [APUAPC] D12_APC_1: 0xffffffff
9988 16:36:50.491966 INFO: [APUAPC] D12_APC_2: 0x3fffff
9989 16:36:50.492052 INFO: [APUAPC] D12_APC_3: 0x0
9990 16:36:50.498539 INFO: [APUAPC] D13_APC_0: 0xffffffff
9991 16:36:50.502262 INFO: [APUAPC] D13_APC_1: 0xffffffff
9992 16:36:50.505087 INFO: [APUAPC] D13_APC_2: 0x3fffff
9993 16:36:50.508880 INFO: [APUAPC] D13_APC_3: 0x0
9994 16:36:50.511859 INFO: [APUAPC] D14_APC_0: 0xffffffff
9995 16:36:50.515658 INFO: [APUAPC] D14_APC_1: 0xffffffff
9996 16:36:50.518498 INFO: [APUAPC] D14_APC_2: 0x3fffff
9997 16:36:50.522340 INFO: [APUAPC] D14_APC_3: 0x0
9998 16:36:50.525479 INFO: [APUAPC] D15_APC_0: 0xffffffff
9999 16:36:50.528479 INFO: [APUAPC] D15_APC_1: 0xffffffff
10000 16:36:50.532154 INFO: [APUAPC] D15_APC_2: 0x3fffff
10001 16:36:50.534980 INFO: [APUAPC] D15_APC_3: 0x0
10002 16:36:50.535202 INFO: [APUAPC] APC_CON: 0x4
10003 16:36:50.538697 INFO: [NOCDAPC] D0_APC_0: 0x0
10004 16:36:50.541563 INFO: [NOCDAPC] D0_APC_1: 0x0
10005 16:36:50.545399 INFO: [NOCDAPC] D1_APC_0: 0x0
10006 16:36:50.548230 INFO: [NOCDAPC] D1_APC_1: 0xfff
10007 16:36:50.552161 INFO: [NOCDAPC] D2_APC_0: 0x0
10008 16:36:50.554908 INFO: [NOCDAPC] D2_APC_1: 0xfff
10009 16:36:50.558670 INFO: [NOCDAPC] D3_APC_0: 0x0
10010 16:36:50.562201 INFO: [NOCDAPC] D3_APC_1: 0xfff
10011 16:36:50.565170 INFO: [NOCDAPC] D4_APC_0: 0x0
10012 16:36:50.568726 INFO: [NOCDAPC] D4_APC_1: 0xfff
10013 16:36:50.569147 INFO: [NOCDAPC] D5_APC_0: 0x0
10014 16:36:50.571676 INFO: [NOCDAPC] D5_APC_1: 0xfff
10015 16:36:50.575284 INFO: [NOCDAPC] D6_APC_0: 0x0
10016 16:36:50.578628 INFO: [NOCDAPC] D6_APC_1: 0xfff
10017 16:36:50.581873 INFO: [NOCDAPC] D7_APC_0: 0x0
10018 16:36:50.585243 INFO: [NOCDAPC] D7_APC_1: 0xfff
10019 16:36:50.588605 INFO: [NOCDAPC] D8_APC_0: 0x0
10020 16:36:50.591539 INFO: [NOCDAPC] D8_APC_1: 0xfff
10021 16:36:50.595042 INFO: [NOCDAPC] D9_APC_0: 0x0
10022 16:36:50.598775 INFO: [NOCDAPC] D9_APC_1: 0xfff
10023 16:36:50.599262 INFO: [NOCDAPC] D10_APC_0: 0x0
10024 16:36:50.601603 INFO: [NOCDAPC] D10_APC_1: 0xfff
10025 16:36:50.605289 INFO: [NOCDAPC] D11_APC_0: 0x0
10026 16:36:50.608292 INFO: [NOCDAPC] D11_APC_1: 0xfff
10027 16:36:50.611908 INFO: [NOCDAPC] D12_APC_0: 0x0
10028 16:36:50.614817 INFO: [NOCDAPC] D12_APC_1: 0xfff
10029 16:36:50.618560 INFO: [NOCDAPC] D13_APC_0: 0x0
10030 16:36:50.621488 INFO: [NOCDAPC] D13_APC_1: 0xfff
10031 16:36:50.625208 INFO: [NOCDAPC] D14_APC_0: 0x0
10032 16:36:50.628057 INFO: [NOCDAPC] D14_APC_1: 0xfff
10033 16:36:50.632012 INFO: [NOCDAPC] D15_APC_0: 0x0
10034 16:36:50.634899 INFO: [NOCDAPC] D15_APC_1: 0xfff
10035 16:36:50.638471 INFO: [NOCDAPC] APC_CON: 0x4
10036 16:36:50.641390 INFO: [APUAPC] set_apusys_apc done
10037 16:36:50.645060 INFO: [DEVAPC] devapc_init done
10038 16:36:50.648790 INFO: GICv3 without legacy support detected.
10039 16:36:50.651804 INFO: ARM GICv3 driver initialized in EL3
10040 16:36:50.654771 INFO: Maximum SPI INTID supported: 639
10041 16:36:50.658498 INFO: BL31: Initializing runtime services
10042 16:36:50.665111 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10043 16:36:50.668074 INFO: SPM: enable CPC mode
10044 16:36:50.671799 INFO: mcdi ready for mcusys-off-idle and system suspend
10045 16:36:50.678588 INFO: BL31: Preparing for EL3 exit to normal world
10046 16:36:50.681458 INFO: Entry point address = 0x80000000
10047 16:36:50.682076 INFO: SPSR = 0x8
10048 16:36:50.689465
10049 16:36:50.689916
10050 16:36:50.690221
10051 16:36:50.692342 Starting depthcharge on Spherion...
10052 16:36:50.692776
10053 16:36:50.693124 Wipe memory regions:
10054 16:36:50.693405
10055 16:36:50.695991 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10056 16:36:50.696519 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10057 16:36:50.696995 Setting prompt string to ['asurada:']
10058 16:36:50.697603 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10059 16:36:50.698376 [0x00000040000000, 0x00000054600000)
10060 16:36:50.818539
10061 16:36:50.819023 [0x00000054660000, 0x00000080000000)
10062 16:36:51.078058
10063 16:36:51.078175 [0x000000821a7280, 0x000000ffe64000)
10064 16:36:51.822388
10065 16:36:51.822530 [0x00000100000000, 0x00000240000000)
10066 16:36:53.712230
10067 16:36:53.715898 Initializing XHCI USB controller at 0x11200000.
10068 16:36:54.754279
10069 16:36:54.757128 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10070 16:36:54.757206
10071 16:36:54.757294
10072 16:36:54.757619 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 16:36:54.857982 asurada: tftpboot 192.168.201.1 14396170/tftp-deploy-it2kh7ii/kernel/image.itb 14396170/tftp-deploy-it2kh7ii/kernel/cmdline
10075 16:36:54.858214 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 16:36:54.858333 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10077 16:36:54.862433 tftpboot 192.168.201.1 14396170/tftp-deploy-it2kh7ii/kernel/image.ittp-deploy-it2kh7ii/kernel/cmdline
10078 16:36:54.862516
10079 16:36:54.862593 Waiting for link
10080 16:36:55.020601
10081 16:36:55.020717 R8152: Initializing
10082 16:36:55.020779
10083 16:36:55.023619 Version 9 (ocp_data = 6010)
10084 16:36:55.023695
10085 16:36:55.027346 R8152: Done initializing
10086 16:36:55.027423
10087 16:36:55.027482 Adding net device
10088 16:36:56.902308
10089 16:36:56.902424 done.
10090 16:36:56.902484
10091 16:36:56.902562 MAC: 00:e0:4c:78:7a:aa
10092 16:36:56.902644
10093 16:36:56.905564 Sending DHCP discover... done.
10094 16:36:56.905655
10095 16:36:56.909891 Waiting for reply... done.
10096 16:36:56.909969
10097 16:36:56.911691 Sending DHCP request... done.
10098 16:36:56.911782
10099 16:36:56.916190 Waiting for reply... done.
10100 16:36:56.916298
10101 16:36:56.916357 My ip is 192.168.201.12
10102 16:36:56.916413
10103 16:36:56.919176 The DHCP server ip is 192.168.201.1
10104 16:36:56.919253
10105 16:36:56.925782 TFTP server IP predefined by user: 192.168.201.1
10106 16:36:56.925859
10107 16:36:56.932175 Bootfile predefined by user: 14396170/tftp-deploy-it2kh7ii/kernel/image.itb
10108 16:36:56.932253
10109 16:36:56.932313 Sending tftp read request... done.
10110 16:36:56.935350
10111 16:36:56.939100 Waiting for the transfer...
10112 16:36:56.939177
10113 16:36:57.204054 00000000 ################################################################
10114 16:36:57.204192
10115 16:36:57.472891 00080000 ################################################################
10116 16:36:57.473040
10117 16:36:57.732706 00100000 ################################################################
10118 16:36:57.732818
10119 16:36:57.994798 00180000 ################################################################
10120 16:36:57.994945
10121 16:36:58.253760 00200000 ################################################################
10122 16:36:58.253876
10123 16:36:58.509745 00280000 ################################################################
10124 16:36:58.509866
10125 16:36:58.775731 00300000 ################################################################
10126 16:36:58.775848
10127 16:36:59.052613 00380000 ################################################################
10128 16:36:59.052754
10129 16:36:59.312354 00400000 ################################################################
10130 16:36:59.312471
10131 16:36:59.566903 00480000 ################################################################
10132 16:36:59.567019
10133 16:36:59.819230 00500000 ################################################################
10134 16:36:59.819343
10135 16:37:00.074938 00580000 ################################################################
10136 16:37:00.075057
10137 16:37:00.335497 00600000 ################################################################
10138 16:37:00.335635
10139 16:37:00.589294 00680000 ################################################################
10140 16:37:00.589410
10141 16:37:00.851868 00700000 ################################################################
10142 16:37:00.851983
10143 16:37:01.106848 00780000 ################################################################
10144 16:37:01.106966
10145 16:37:01.359978 00800000 ################################################################
10146 16:37:01.360102
10147 16:37:01.620747 00880000 ################################################################
10148 16:37:01.620855
10149 16:37:01.872909 00900000 ################################################################
10150 16:37:01.873037
10151 16:37:02.126978 00980000 ################################################################
10152 16:37:02.127101
10153 16:37:02.380867 00a00000 ################################################################
10154 16:37:02.380981
10155 16:37:02.635507 00a80000 ################################################################
10156 16:37:02.635621
10157 16:37:02.889032 00b00000 ################################################################
10158 16:37:02.889143
10159 16:37:03.140529 00b80000 ################################################################
10160 16:37:03.140645
10161 16:37:03.391316 00c00000 ################################################################
10162 16:37:03.391432
10163 16:37:03.652368 00c80000 ################################################################
10164 16:37:03.652497
10165 16:37:03.907452 00d00000 ################################################################
10166 16:37:03.907571
10167 16:37:04.163388 00d80000 ################################################################
10168 16:37:04.163511
10169 16:37:04.413795 00e00000 ################################################################
10170 16:37:04.413951
10171 16:37:04.670286 00e80000 ################################################################
10172 16:37:04.670415
10173 16:37:04.917184 00f00000 ################################################################
10174 16:37:04.917330
10175 16:37:05.162327 00f80000 ################################################################
10176 16:37:05.162482
10177 16:37:05.418373 01000000 ################################################################
10178 16:37:05.418519
10179 16:37:05.667085 01080000 ################################################################
10180 16:37:05.667207
10181 16:37:05.913951 01100000 ################################################################
10182 16:37:05.914078
10183 16:37:06.162602 01180000 ################################################################
10184 16:37:06.162750
10185 16:37:06.408794 01200000 ################################################################
10186 16:37:06.408919
10187 16:37:06.656539 01280000 ################################################################
10188 16:37:06.656677
10189 16:37:06.908052 01300000 ################################################################
10190 16:37:06.908186
10191 16:37:07.166228 01380000 ################################################################
10192 16:37:07.166388
10193 16:37:07.453594 01400000 ################################################################
10194 16:37:07.453710
10195 16:37:07.660144 01480000 ################################################################
10196 16:37:07.660282
10197 16:37:07.911860 01500000 ################################################################
10198 16:37:07.911996
10199 16:37:08.158775 01580000 ################################################################
10200 16:37:08.158911
10201 16:37:08.406056 01600000 ################################################################
10202 16:37:08.406192
10203 16:37:08.653293 01680000 ################################################################
10204 16:37:08.653406
10205 16:37:08.907469 01700000 ################################################################
10206 16:37:08.907597
10207 16:37:09.156709 01780000 ################################################################
10208 16:37:09.156817
10209 16:37:09.403693 01800000 ################################################################
10210 16:37:09.403823
10211 16:37:09.651412 01880000 ################################################################
10212 16:37:09.651554
10213 16:37:09.903024 01900000 ################################################################
10214 16:37:09.903148
10215 16:37:10.153202 01980000 ################################################################
10216 16:37:10.153341
10217 16:37:10.406000 01a00000 ################################################################
10218 16:37:10.406145
10219 16:37:10.652853 01a80000 ################################################################
10220 16:37:10.652991
10221 16:37:10.904337 01b00000 ################################################################
10222 16:37:10.904464
10223 16:37:11.155831 01b80000 ################################################################
10224 16:37:11.155947
10225 16:37:11.406168 01c00000 ################################################################
10226 16:37:11.406317
10227 16:37:11.658070 01c80000 ################################################################
10228 16:37:11.658190
10229 16:37:11.905968 01d00000 ################################################################
10230 16:37:11.906094
10231 16:37:12.155490 01d80000 ################################################################
10232 16:37:12.155627
10233 16:37:12.375276 01e00000 ######################################################### done.
10234 16:37:12.375396
10235 16:37:12.378802 The bootfile was 31921222 bytes long.
10236 16:37:12.378887
10237 16:37:12.381853 Sending tftp read request... done.
10238 16:37:12.381939
10239 16:37:12.385186 Waiting for the transfer...
10240 16:37:12.385262
10241 16:37:12.388448 00000000 # done.
10242 16:37:12.388530
10243 16:37:12.395586 Command line loaded dynamically from TFTP file: 14396170/tftp-deploy-it2kh7ii/kernel/cmdline
10244 16:37:12.395668
10245 16:37:12.418772 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10246 16:37:12.418879
10247 16:37:12.418963 Loading FIT.
10248 16:37:12.419039
10249 16:37:12.422050 Image ramdisk-1 has 18743182 bytes.
10250 16:37:12.422151
10251 16:37:12.425562 Image fdt-1 has 47258 bytes.
10252 16:37:12.425657
10253 16:37:12.428513 Image kernel-1 has 13128753 bytes.
10254 16:37:12.428624
10255 16:37:12.435042 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10256 16:37:12.435174
10257 16:37:12.455144 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10258 16:37:12.455270
10259 16:37:12.458158 Choosing best match conf-1 for compat google,spherion-rev2.
10260 16:37:12.464064
10261 16:37:12.468374 Connected to device vid:did:rid of 1ae0:0028:00
10262 16:37:12.476273
10263 16:37:12.479917 tpm_get_response: command 0x17b, return code 0x0
10264 16:37:12.479998
10265 16:37:12.482855 ec_init: CrosEC protocol v3 supported (256, 248)
10266 16:37:12.487925
10267 16:37:12.490592 tpm_cleanup: add release locality here.
10268 16:37:12.490703
10269 16:37:12.490793 Shutting down all USB controllers.
10270 16:37:12.493890
10271 16:37:12.493964 Removing current net device
10272 16:37:12.494024
10273 16:37:12.500414 Exiting depthcharge with code 4 at timestamp: 51088591
10274 16:37:12.500525
10275 16:37:12.503747 LZMA decompressing kernel-1 to 0x821a6718
10276 16:37:12.503845
10277 16:37:12.507713 LZMA decompressing kernel-1 to 0x40000000
10278 16:37:14.124110
10279 16:37:14.124258 jumping to kernel
10280 16:37:14.124705 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10281 16:37:14.124831 start: 2.2.5 auto-login-action (timeout 00:03:57) [common]
10282 16:37:14.124900 Setting prompt string to ['Linux version [0-9]']
10283 16:37:14.124963 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10284 16:37:14.125027 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10285 16:37:14.207217
10286 16:37:14.210689 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10287 16:37:14.214349 start: 2.2.5.1 login-action (timeout 00:03:57) [common]
10288 16:37:14.214480 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10289 16:37:14.214579 Setting prompt string to []
10290 16:37:14.214657 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10291 16:37:14.214728 Using line separator: #'\n'#
10292 16:37:14.214793 No login prompt set.
10293 16:37:14.214860 Parsing kernel messages
10294 16:37:14.214913 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10295 16:37:14.215017 [login-action] Waiting for messages, (timeout 00:03:57)
10296 16:37:14.215085 Waiting using forced prompt support (timeout 00:01:58)
10297 16:37:14.234238 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10298 16:37:14.237120 [ 0.000000] random: crng init done
10299 16:37:14.244071 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10300 16:37:14.244196 [ 0.000000] efi: UEFI not found.
10301 16:37:14.253390 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10302 16:37:14.259879 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10303 16:37:14.270279 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10304 16:37:14.279970 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10305 16:37:14.286518 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10306 16:37:14.293005 [ 0.000000] printk: bootconsole [mtk8250] enabled
10307 16:37:14.300004 [ 0.000000] NUMA: No NUMA configuration found
10308 16:37:14.306155 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10309 16:37:14.309561 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10310 16:37:14.313250 [ 0.000000] Zone ranges:
10311 16:37:14.319621 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10312 16:37:14.323191 [ 0.000000] DMA32 empty
10313 16:37:14.329825 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10314 16:37:14.333206 [ 0.000000] Movable zone start for each node
10315 16:37:14.336143 [ 0.000000] Early memory node ranges
10316 16:37:14.342761 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10317 16:37:14.349444 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10318 16:37:14.355953 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10319 16:37:14.362599 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10320 16:37:14.366176 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10321 16:37:14.375643 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10322 16:37:14.431520 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10323 16:37:14.438486 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10324 16:37:14.444703 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10325 16:37:14.448218 [ 0.000000] psci: probing for conduit method from DT.
10326 16:37:14.455031 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10327 16:37:14.458009 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10328 16:37:14.465151 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10329 16:37:14.468062 [ 0.000000] psci: SMC Calling Convention v1.2
10330 16:37:14.474657 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10331 16:37:14.478294 [ 0.000000] Detected VIPT I-cache on CPU0
10332 16:37:14.484435 [ 0.000000] CPU features: detected: GIC system register CPU interface
10333 16:37:14.491005 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10334 16:37:14.497825 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10335 16:37:14.504758 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10336 16:37:14.511215 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10337 16:37:14.521331 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10338 16:37:14.524624 [ 0.000000] alternatives: applying boot alternatives
10339 16:37:14.531529 [ 0.000000] Fallback order for Node 0: 0
10340 16:37:14.538140 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10341 16:37:14.541467 [ 0.000000] Policy zone: Normal
10342 16:37:14.564276 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10343 16:37:14.574430 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10344 16:37:14.584574 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10345 16:37:14.594678 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10346 16:37:14.601706 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10347 16:37:14.604486 <6>[ 0.000000] software IO TLB: area num 8.
10348 16:37:14.661809 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10349 16:37:14.811761 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10350 16:37:14.818009 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10351 16:37:14.824931 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10352 16:37:14.827846 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10353 16:37:14.834792 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10354 16:37:14.841236 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10355 16:37:14.844817 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10356 16:37:14.854690 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10357 16:37:14.861175 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10358 16:37:14.864725 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10359 16:37:14.872658 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10360 16:37:14.875472 <6>[ 0.000000] GICv3: 608 SPIs implemented
10361 16:37:14.882213 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10362 16:37:14.885647 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10363 16:37:14.888988 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10364 16:37:14.899011 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10365 16:37:14.908865 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10366 16:37:14.922432 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10367 16:37:14.928698 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10368 16:37:14.937987 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10369 16:37:14.951197 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10370 16:37:14.958221 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10371 16:37:14.964644 <6>[ 0.009187] Console: colour dummy device 80x25
10372 16:37:14.974815 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10373 16:37:14.977783 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10374 16:37:14.984216 <6>[ 0.029219] LSM: Security Framework initializing
10375 16:37:14.991371 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10376 16:37:15.000914 <6>[ 0.041972] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 16:37:15.007574 <6>[ 0.051388] cblist_init_generic: Setting adjustable number of callback queues.
10378 16:37:15.014084 <6>[ 0.058831] cblist_init_generic: Setting shift to 3 and lim to 1.
10379 16:37:15.024369 <6>[ 0.065171] cblist_init_generic: Setting adjustable number of callback queues.
10380 16:37:15.027959 <6>[ 0.072598] cblist_init_generic: Setting shift to 3 and lim to 1.
10381 16:37:15.034252 <6>[ 0.079037] rcu: Hierarchical SRCU implementation.
10382 16:37:15.040853 <6>[ 0.084051] rcu: Max phase no-delay instances is 1000.
10383 16:37:15.047411 <6>[ 0.091087] EFI services will not be available.
10384 16:37:15.051035 <6>[ 0.096073] smp: Bringing up secondary CPUs ...
10385 16:37:15.058852 <6>[ 0.101124] Detected VIPT I-cache on CPU1
10386 16:37:15.065089 <6>[ 0.101198] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10387 16:37:15.072286 <6>[ 0.101231] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10388 16:37:15.075274 <6>[ 0.101567] Detected VIPT I-cache on CPU2
10389 16:37:15.081843 <6>[ 0.101618] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10390 16:37:15.089077 <6>[ 0.101635] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10391 16:37:15.094994 <6>[ 0.101895] Detected VIPT I-cache on CPU3
10392 16:37:15.102123 <6>[ 0.101943] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10393 16:37:15.108402 <6>[ 0.101958] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10394 16:37:15.111970 <6>[ 0.102262] CPU features: detected: Spectre-v4
10395 16:37:15.118121 <6>[ 0.102267] CPU features: detected: Spectre-BHB
10396 16:37:15.121619 <6>[ 0.102272] Detected PIPT I-cache on CPU4
10397 16:37:15.128010 <6>[ 0.102331] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10398 16:37:15.134674 <6>[ 0.102348] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10399 16:37:15.141436 <6>[ 0.102642] Detected PIPT I-cache on CPU5
10400 16:37:15.147793 <6>[ 0.102707] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10401 16:37:15.154908 <6>[ 0.102723] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10402 16:37:15.157712 <6>[ 0.103002] Detected PIPT I-cache on CPU6
10403 16:37:15.164777 <6>[ 0.103067] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10404 16:37:15.171029 <6>[ 0.103083] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10405 16:37:15.177698 <6>[ 0.103377] Detected PIPT I-cache on CPU7
10406 16:37:15.184232 <6>[ 0.103442] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10407 16:37:15.190955 <6>[ 0.103458] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10408 16:37:15.194556 <6>[ 0.103505] smp: Brought up 1 node, 8 CPUs
10409 16:37:15.201046 <6>[ 0.244867] SMP: Total of 8 processors activated.
10410 16:37:15.204741 <6>[ 0.249788] CPU features: detected: 32-bit EL0 Support
10411 16:37:15.214157 <6>[ 0.255185] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10412 16:37:15.221431 <6>[ 0.263985] CPU features: detected: Common not Private translations
10413 16:37:15.227994 <6>[ 0.270461] CPU features: detected: CRC32 instructions
10414 16:37:15.230790 <6>[ 0.275846] CPU features: detected: RCpc load-acquire (LDAPR)
10415 16:37:15.237770 <6>[ 0.281842] CPU features: detected: LSE atomic instructions
10416 16:37:15.244546 <6>[ 0.287624] CPU features: detected: Privileged Access Never
10417 16:37:15.250769 <6>[ 0.293404] CPU features: detected: RAS Extension Support
10418 16:37:15.257617 <6>[ 0.299013] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10419 16:37:15.260664 <6>[ 0.306274] CPU: All CPU(s) started at EL2
10420 16:37:15.267165 <6>[ 0.310618] alternatives: applying system-wide alternatives
10421 16:37:15.276246 <6>[ 0.321479] devtmpfs: initialized
10422 16:37:15.292491 <6>[ 0.330322] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10423 16:37:15.298829 <6>[ 0.340282] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10424 16:37:15.305386 <6>[ 0.348296] pinctrl core: initialized pinctrl subsystem
10425 16:37:15.309010 <6>[ 0.354989] DMI not present or invalid.
10426 16:37:15.315349 <6>[ 0.359402] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10427 16:37:15.325286 <6>[ 0.366195] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10428 16:37:15.331878 <6>[ 0.373785] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10429 16:37:15.339318 <6>[ 0.382008] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10430 16:37:15.345817 <6>[ 0.390249] audit: initializing netlink subsys (disabled)
10431 16:37:15.355839 <5>[ 0.395941] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10432 16:37:15.359173 <6>[ 0.396665] thermal_sys: Registered thermal governor 'step_wise'
10433 16:37:15.365720 <6>[ 0.403909] thermal_sys: Registered thermal governor 'power_allocator'
10434 16:37:15.371860 <6>[ 0.410162] cpuidle: using governor menu
10435 16:37:15.375267 <6>[ 0.421122] NET: Registered PF_QIPCRTR protocol family
10436 16:37:15.385479 <6>[ 0.426610] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10437 16:37:15.388631 <6>[ 0.433714] ASID allocator initialised with 32768 entries
10438 16:37:15.395405 <6>[ 0.440299] Serial: AMBA PL011 UART driver
10439 16:37:15.404237 <4>[ 0.449132] Trying to register duplicate clock ID: 134
10440 16:37:15.462747 <6>[ 0.510592] KASLR enabled
10441 16:37:15.477120 <6>[ 0.518305] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10442 16:37:15.483545 <6>[ 0.525321] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10443 16:37:15.489998 <6>[ 0.531811] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10444 16:37:15.497102 <6>[ 0.538818] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10445 16:37:15.503114 <6>[ 0.545304] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10446 16:37:15.509771 <6>[ 0.552310] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10447 16:37:15.516662 <6>[ 0.558797] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10448 16:37:15.523201 <6>[ 0.565801] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10449 16:37:15.526576 <6>[ 0.573340] ACPI: Interpreter disabled.
10450 16:37:15.534896 <6>[ 0.579770] iommu: Default domain type: Translated
10451 16:37:15.541731 <6>[ 0.584880] iommu: DMA domain TLB invalidation policy: strict mode
10452 16:37:15.544657 <5>[ 0.591543] SCSI subsystem initialized
10453 16:37:15.551739 <6>[ 0.595712] usbcore: registered new interface driver usbfs
10454 16:37:15.558332 <6>[ 0.601446] usbcore: registered new interface driver hub
10455 16:37:15.561106 <6>[ 0.606996] usbcore: registered new device driver usb
10456 16:37:15.568165 <6>[ 0.613100] pps_core: LinuxPPS API ver. 1 registered
10457 16:37:15.578155 <6>[ 0.618293] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10458 16:37:15.581757 <6>[ 0.627642] PTP clock support registered
10459 16:37:15.584669 <6>[ 0.631884] EDAC MC: Ver: 3.0.0
10460 16:37:15.592022 <6>[ 0.637037] FPGA manager framework
10461 16:37:15.599203 <6>[ 0.640724] Advanced Linux Sound Architecture Driver Initialized.
10462 16:37:15.602197 <6>[ 0.647496] vgaarb: loaded
10463 16:37:15.608741 <6>[ 0.650635] clocksource: Switched to clocksource arch_sys_counter
10464 16:37:15.612341 <5>[ 0.657074] VFS: Disk quotas dquot_6.6.0
10465 16:37:15.618963 <6>[ 0.661261] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10466 16:37:15.621856 <6>[ 0.668451] pnp: PnP ACPI: disabled
10467 16:37:15.630750 <6>[ 0.675258] NET: Registered PF_INET protocol family
10468 16:37:15.640645 <6>[ 0.680863] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10469 16:37:15.651393 <6>[ 0.693191] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10470 16:37:15.661581 <6>[ 0.702006] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10471 16:37:15.668440 <6>[ 0.709976] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10472 16:37:15.677878 <6>[ 0.718684] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10473 16:37:15.684442 <6>[ 0.728431] TCP: Hash tables configured (established 65536 bind 65536)
10474 16:37:15.691792 <6>[ 0.735302] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10475 16:37:15.701422 <6>[ 0.742502] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 16:37:15.708031 <6>[ 0.750211] NET: Registered PF_UNIX/PF_LOCAL protocol family
10477 16:37:15.710951 <6>[ 0.756287] RPC: Registered named UNIX socket transport module.
10478 16:37:15.718167 <6>[ 0.762437] RPC: Registered udp transport module.
10479 16:37:15.721182 <6>[ 0.767368] RPC: Registered tcp transport module.
10480 16:37:15.727884 <6>[ 0.772302] RPC: Registered tcp NFSv4.1 backchannel transport module.
10481 16:37:15.734440 <6>[ 0.778968] PCI: CLS 0 bytes, default 64
10482 16:37:15.737844 <6>[ 0.783293] Unpacking initramfs...
10483 16:37:15.753418 <6>[ 0.795169] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10484 16:37:15.763423 <6>[ 0.803814] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10485 16:37:15.766898 <6>[ 0.812639] kvm [1]: IPA Size Limit: 40 bits
10486 16:37:15.773458 <6>[ 0.817169] kvm [1]: GICv3: no GICV resource entry
10487 16:37:15.776719 <6>[ 0.822191] kvm [1]: disabling GICv2 emulation
10488 16:37:15.782879 <6>[ 0.826878] kvm [1]: GIC system register CPU interface enabled
10489 16:37:15.786669 <6>[ 0.833044] kvm [1]: vgic interrupt IRQ18
10490 16:37:15.793521 <6>[ 0.837396] kvm [1]: VHE mode initialized successfully
10491 16:37:15.799635 <5>[ 0.843923] Initialise system trusted keyrings
10492 16:37:15.806660 <6>[ 0.848724] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10493 16:37:15.814031 <6>[ 0.858722] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10494 16:37:15.820540 <5>[ 0.865124] NFS: Registering the id_resolver key type
10495 16:37:15.824198 <5>[ 0.870424] Key type id_resolver registered
10496 16:37:15.830125 <5>[ 0.874841] Key type id_legacy registered
10497 16:37:15.836656 <6>[ 0.879118] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10498 16:37:15.843891 <6>[ 0.886041] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10499 16:37:15.850405 <6>[ 0.893747] 9p: Installing v9fs 9p2000 file system support
10500 16:37:15.887090 <5>[ 0.932097] Key type asymmetric registered
10501 16:37:15.890808 <5>[ 0.936428] Asymmetric key parser 'x509' registered
10502 16:37:15.900571 <6>[ 0.941566] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10503 16:37:15.903812 <6>[ 0.949180] io scheduler mq-deadline registered
10504 16:37:15.906843 <6>[ 0.953941] io scheduler kyber registered
10505 16:37:15.926312 <6>[ 0.970972] EINJ: ACPI disabled.
10506 16:37:15.959471 <4>[ 0.997296] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10507 16:37:15.968798 <4>[ 1.007939] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 16:37:15.984461 <6>[ 1.029245] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10509 16:37:15.992250 <6>[ 1.037306] printk: console [ttyS0] disabled
10510 16:37:16.020730 <6>[ 1.061938] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10511 16:37:16.026822 <6>[ 1.071411] printk: console [ttyS0] enabled
10512 16:37:16.030498 <6>[ 1.071411] printk: console [ttyS0] enabled
10513 16:37:16.037185 <6>[ 1.080307] printk: bootconsole [mtk8250] disabled
10514 16:37:16.040275 <6>[ 1.080307] printk: bootconsole [mtk8250] disabled
10515 16:37:16.047113 <6>[ 1.091548] SuperH (H)SCI(F) driver initialized
10516 16:37:16.050602 <6>[ 1.096826] msm_serial: driver initialized
10517 16:37:16.064465 <6>[ 1.105754] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10518 16:37:16.074606 <6>[ 1.114302] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10519 16:37:16.080944 <6>[ 1.122845] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10520 16:37:16.090893 <6>[ 1.131473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10521 16:37:16.097144 <6>[ 1.140178] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10522 16:37:16.107370 <6>[ 1.148898] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10523 16:37:16.117450 <6>[ 1.157439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10524 16:37:16.123875 <6>[ 1.166241] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10525 16:37:16.133867 <6>[ 1.174782] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10526 16:37:16.145314 <6>[ 1.190232] loop: module loaded
10527 16:37:16.152077 <6>[ 1.196234] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10528 16:37:16.175084 <4>[ 1.219593] mtk-pmic-keys: Failed to locate of_node [id: -1]
10529 16:37:16.181567 <6>[ 1.226379] megasas: 07.719.03.00-rc1
10530 16:37:16.191414 <6>[ 1.236050] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10531 16:37:16.197736 <6>[ 1.242012] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10532 16:37:16.213534 <6>[ 1.258395] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10533 16:37:16.269268 <6>[ 1.307499] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10534 16:37:16.530454 <6>[ 1.575368] Freeing initrd memory: 18300K
10535 16:37:16.542163 <6>[ 1.586929] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10536 16:37:16.552908 <6>[ 1.597912] tun: Universal TUN/TAP device driver, 1.6
10537 16:37:16.556614 <6>[ 1.603978] thunder_xcv, ver 1.0
10538 16:37:16.559549 <6>[ 1.607485] thunder_bgx, ver 1.0
10539 16:37:16.563189 <6>[ 1.610979] nicpf, ver 1.0
10540 16:37:16.573244 <6>[ 1.615011] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10541 16:37:16.576829 <6>[ 1.622487] hns3: Copyright (c) 2017 Huawei Corporation.
10542 16:37:16.580179 <6>[ 1.628077] hclge is initializing
10543 16:37:16.586880 <6>[ 1.631654] e1000: Intel(R) PRO/1000 Network Driver
10544 16:37:16.593358 <6>[ 1.636783] e1000: Copyright (c) 1999-2006 Intel Corporation.
10545 16:37:16.596989 <6>[ 1.642795] e1000e: Intel(R) PRO/1000 Network Driver
10546 16:37:16.603496 <6>[ 1.648011] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10547 16:37:16.610034 <6>[ 1.654199] igb: Intel(R) Gigabit Ethernet Network Driver
10548 16:37:16.616387 <6>[ 1.659850] igb: Copyright (c) 2007-2014 Intel Corporation.
10549 16:37:16.623078 <6>[ 1.665686] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10550 16:37:16.630082 <6>[ 1.672205] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10551 16:37:16.633521 <6>[ 1.678671] sky2: driver version 1.30
10552 16:37:16.640010 <6>[ 1.683601] usbcore: registered new device driver r8152-cfgselector
10553 16:37:16.646817 <6>[ 1.690139] usbcore: registered new interface driver r8152
10554 16:37:16.650197 <6>[ 1.695959] VFIO - User Level meta-driver version: 0.3
10555 16:37:16.659059 <6>[ 1.704201] usbcore: registered new interface driver usb-storage
10556 16:37:16.665575 <6>[ 1.710646] usbcore: registered new device driver onboard-usb-hub
10557 16:37:16.674949 <6>[ 1.719841] mt6397-rtc mt6359-rtc: registered as rtc0
10558 16:37:16.685051 <6>[ 1.725309] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:37:16 UTC (1718642236)
10559 16:37:16.687966 <6>[ 1.734877] i2c_dev: i2c /dev entries driver
10560 16:37:16.701724 <4>[ 1.746835] cpu cpu0: supply cpu not found, using dummy regulator
10561 16:37:16.708952 <4>[ 1.753262] cpu cpu1: supply cpu not found, using dummy regulator
10562 16:37:16.714952 <4>[ 1.759663] cpu cpu2: supply cpu not found, using dummy regulator
10563 16:37:16.722176 <4>[ 1.766070] cpu cpu3: supply cpu not found, using dummy regulator
10564 16:37:16.728712 <4>[ 1.772483] cpu cpu4: supply cpu not found, using dummy regulator
10565 16:37:16.735502 <4>[ 1.778881] cpu cpu5: supply cpu not found, using dummy regulator
10566 16:37:16.741543 <4>[ 1.785281] cpu cpu6: supply cpu not found, using dummy regulator
10567 16:37:16.748318 <4>[ 1.791685] cpu cpu7: supply cpu not found, using dummy regulator
10568 16:37:16.768704 <6>[ 1.813331] cpu cpu0: EM: created perf domain
10569 16:37:16.771655 <6>[ 1.818270] cpu cpu4: EM: created perf domain
10570 16:37:16.779199 <6>[ 1.823861] sdhci: Secure Digital Host Controller Interface driver
10571 16:37:16.785923 <6>[ 1.830295] sdhci: Copyright(c) Pierre Ossman
10572 16:37:16.792234 <6>[ 1.835252] Synopsys Designware Multimedia Card Interface Driver
10573 16:37:16.798915 <6>[ 1.841885] sdhci-pltfm: SDHCI platform and OF driver helper
10574 16:37:16.802546 <6>[ 1.841927] mmc0: CQHCI version 5.10
10575 16:37:16.808668 <6>[ 1.851839] ledtrig-cpu: registered to indicate activity on CPUs
10576 16:37:16.816000 <6>[ 1.858907] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10577 16:37:16.822432 <6>[ 1.865950] usbcore: registered new interface driver usbhid
10578 16:37:16.825379 <6>[ 1.871771] usbhid: USB HID core driver
10579 16:37:16.831962 <6>[ 1.875968] spi_master spi0: will run message pump with realtime priority
10580 16:37:16.876935 <6>[ 1.915378] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10581 16:37:16.896216 <6>[ 1.931214] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10582 16:37:16.899515 <6>[ 1.935622] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10583 16:37:16.908117 <6>[ 1.953057] cros-ec-spi spi0.0: Chrome EC device registered
10584 16:37:16.914977 <6>[ 1.959051] mmc0: Command Queue Engine enabled
10585 16:37:16.921259 <6>[ 1.963780] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10586 16:37:16.924971 <6>[ 1.971384] mmcblk0: mmc0:0001 DA4128 116 GiB
10587 16:37:16.934704 <6>[ 1.979749] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10588 16:37:16.941960 <6>[ 1.987066] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10589 16:37:16.948731 <6>[ 1.993193] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10590 16:37:16.958890 <6>[ 1.997791] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10591 16:37:16.965692 <6>[ 1.999084] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10592 16:37:16.969006 <6>[ 2.009077] NET: Registered PF_PACKET protocol family
10593 16:37:16.975163 <6>[ 2.019633] 9pnet: Installing 9P2000 support
10594 16:37:16.979062 <5>[ 2.024197] Key type dns_resolver registered
10595 16:37:16.981856 <6>[ 2.029209] registered taskstats version 1
10596 16:37:16.988762 <5>[ 2.033601] Loading compiled-in X.509 certificates
10597 16:37:17.019304 <4>[ 2.057767] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 16:37:17.029401 <4>[ 2.068523] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 16:37:17.044982 <6>[ 2.089872] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10600 16:37:17.052269 <6>[ 2.096887] xhci-mtk 11200000.usb: xHCI Host Controller
10601 16:37:17.058949 <6>[ 2.102391] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10602 16:37:17.068579 <6>[ 2.110246] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10603 16:37:17.075188 <6>[ 2.119686] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10604 16:37:17.082145 <6>[ 2.125771] xhci-mtk 11200000.usb: xHCI Host Controller
10605 16:37:17.088991 <6>[ 2.131257] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10606 16:37:17.095422 <6>[ 2.139018] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10607 16:37:17.102155 <6>[ 2.146892] hub 1-0:1.0: USB hub found
10608 16:37:17.105433 <6>[ 2.150917] hub 1-0:1.0: 1 port detected
10609 16:37:17.111991 <6>[ 2.155229] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10610 16:37:17.119143 <6>[ 2.163966] hub 2-0:1.0: USB hub found
10611 16:37:17.122022 <6>[ 2.167997] hub 2-0:1.0: 1 port detected
10612 16:37:17.130046 <6>[ 2.174787] mtk-msdc 11f70000.mmc: Got CD GPIO
10613 16:37:17.144038 <6>[ 2.185471] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10614 16:37:17.153804 <6>[ 2.193873] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10615 16:37:17.160318 <6>[ 2.202216] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10616 16:37:17.170531 <6>[ 2.210559] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10617 16:37:17.177060 <6>[ 2.218898] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10618 16:37:17.186610 <6>[ 2.227237] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10619 16:37:17.193571 <6>[ 2.235575] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10620 16:37:17.203825 <6>[ 2.243913] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10621 16:37:17.210005 <6>[ 2.252252] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10622 16:37:17.220112 <6>[ 2.260590] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10623 16:37:17.226701 <6>[ 2.268927] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10624 16:37:17.236925 <6>[ 2.277280] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10625 16:37:17.243333 <6>[ 2.285619] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10626 16:37:17.253366 <6>[ 2.293957] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10627 16:37:17.259895 <6>[ 2.302295] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10628 16:37:17.266693 <6>[ 2.311164] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10629 16:37:17.273299 <6>[ 2.318341] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10630 16:37:17.280353 <6>[ 2.325105] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10631 16:37:17.290329 <6>[ 2.331914] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10632 16:37:17.296753 <6>[ 2.338849] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10633 16:37:17.303327 <6>[ 2.345730] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10634 16:37:17.313058 <6>[ 2.354867] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10635 16:37:17.323022 <6>[ 2.363986] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10636 16:37:17.333389 <6>[ 2.373279] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10637 16:37:17.343019 <6>[ 2.382761] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10638 16:37:17.349530 <6>[ 2.392229] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10639 16:37:17.359786 <6>[ 2.401348] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10640 16:37:17.369283 <6>[ 2.410816] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10641 16:37:17.379783 <6>[ 2.419938] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10642 16:37:17.389174 <6>[ 2.429242] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10643 16:37:17.399320 <6>[ 2.439405] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10644 16:37:17.409392 <6>[ 2.450988] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10645 16:37:17.416275 <6>[ 2.461664] Trying to probe devices needed for running init ...
10646 16:37:17.427426 <3>[ 2.468928] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10647 16:37:17.536899 <6>[ 2.578788] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10648 16:37:17.692094 <6>[ 2.736844] hub 1-1:1.0: USB hub found
10649 16:37:17.694876 <6>[ 2.741371] hub 1-1:1.0: 4 ports detected
10650 16:37:17.707739 <6>[ 2.752615] hub 1-1:1.0: USB hub found
10651 16:37:17.710573 <6>[ 2.756955] hub 1-1:1.0: 4 ports detected
10652 16:37:17.817192 <6>[ 2.859272] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10653 16:37:17.844949 <6>[ 2.889924] hub 2-1:1.0: USB hub found
10654 16:37:17.847928 <6>[ 2.894376] hub 2-1:1.0: 3 ports detected
10655 16:37:17.861184 <6>[ 2.905938] hub 2-1:1.0: USB hub found
10656 16:37:17.864504 <6>[ 2.910336] hub 2-1:1.0: 3 ports detected
10657 16:37:18.033322 <6>[ 3.074959] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10658 16:37:18.166125 <6>[ 3.210837] hub 1-1.4:1.0: USB hub found
10659 16:37:18.169051 <6>[ 3.215539] hub 1-1.4:1.0: 2 ports detected
10660 16:37:18.181404 <6>[ 3.226661] hub 1-1.4:1.0: USB hub found
10661 16:37:18.185015 <6>[ 3.231220] hub 1-1.4:1.0: 2 ports detected
10662 16:37:18.245289 <6>[ 3.286950] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10663 16:37:18.354052 <6>[ 3.395591] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10664 16:37:18.389141 <4>[ 3.430966] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10665 16:37:18.399222 <4>[ 3.440059] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10666 16:37:18.439015 <6>[ 3.484477] r8152 2-1.3:1.0 eth0: v1.12.13
10667 16:37:18.480834 <6>[ 3.522742] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10668 16:37:18.673440 <6>[ 3.714978] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10669 16:37:20.065964 <6>[ 5.111263] r8152 2-1.3:1.0 eth0: carrier on
10670 16:37:22.797577 <5>[ 5.138692] Sending DHCP requests .., OK
10671 16:37:22.804397 <6>[ 7.847107] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10672 16:37:22.807997 <6>[ 7.855400] IP-Config: Complete:
10673 16:37:22.820809 <6>[ 7.858900] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10674 16:37:22.827824 <6>[ 7.869608] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10675 16:37:22.834258 <6>[ 7.878225] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10676 16:37:22.840689 <6>[ 7.878234] nameserver0=192.168.201.1
10677 16:37:22.843958 <6>[ 7.890385] clk: Disabling unused clocks
10678 16:37:22.847259 <6>[ 7.895905] ALSA device list:
10679 16:37:22.853938 <6>[ 7.899174] No soundcards found.
10680 16:37:22.861365 <6>[ 7.906745] Freeing unused kernel memory: 8512K
10681 16:37:22.865111 <6>[ 7.911738] Run /init as init process
10682 16:37:22.874009 Loading, please wait...
10683 16:37:22.901474 Starting systemd-udevd version 252.22-1~deb12u1
10684 16:37:23.151660 <6>[ 8.193248] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10685 16:37:23.166935 <6>[ 8.208665] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10686 16:37:23.173762 <6>[ 8.209112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10687 16:37:23.180537 <6>[ 8.223488] remoteproc remoteproc0: scp is available
10688 16:37:23.187043 <6>[ 8.225656] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10689 16:37:23.193500 <6>[ 8.229571] remoteproc remoteproc0: powering up scp
10690 16:37:23.200197 <6>[ 8.234486] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10691 16:37:23.210427 <6>[ 8.234565] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10692 16:37:23.217231 <6>[ 8.234582] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10693 16:37:23.226809 <4>[ 8.237566] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10694 16:37:23.236312 <6>[ 8.244235] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10695 16:37:23.243059 <6>[ 8.250619] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10696 16:37:23.249947 <6>[ 8.258827] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10697 16:37:23.256568 <6>[ 8.267492] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10698 16:37:23.259631 <6>[ 8.277449] mc: Linux media interface: v0.10
10699 16:37:23.269744 <3>[ 8.282040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 16:37:23.276150 <3>[ 8.282054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 16:37:23.286548 <3>[ 8.282062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 16:37:23.292940 <3>[ 8.296323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 16:37:23.302997 <6>[ 8.298363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10704 16:37:23.309607 <6>[ 8.298377] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10705 16:37:23.316405 <6>[ 8.298380] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10706 16:37:23.325864 <6>[ 8.298383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10707 16:37:23.332449 <4>[ 8.321525] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10708 16:37:23.342629 <6>[ 8.321621] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10709 16:37:23.348931 <3>[ 8.327672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 16:37:23.355676 <4>[ 8.338737] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 16:37:23.366022 <3>[ 8.343651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 16:37:23.369369 <6>[ 8.347261] videodev: Linux video capture interface: v2.00
10713 16:37:23.378783 <6>[ 8.356297] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10714 16:37:23.385686 <3>[ 8.360172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 16:37:23.392788 <6>[ 8.367472] pci_bus 0000:00: root bus resource [bus 00-ff]
10716 16:37:23.399765 <3>[ 8.376745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 16:37:23.406122 <6>[ 8.384013] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10718 16:37:23.412778 <3>[ 8.391812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 16:37:23.423242 <6>[ 8.399723] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10720 16:37:23.430036 <6>[ 8.403361] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10721 16:37:23.440341 <6>[ 8.403424] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10722 16:37:23.446853 <6>[ 8.403432] remoteproc remoteproc0: remote processor scp is now up
10723 16:37:23.453346 <3>[ 8.406952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 16:37:23.459852 <6>[ 8.415199] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10725 16:37:23.470419 <3>[ 8.420730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 16:37:23.477085 <3>[ 8.420734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 16:37:23.483789 <3>[ 8.420813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 16:37:23.493128 <6>[ 8.427703] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10729 16:37:23.503509 <6>[ 8.431427] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10730 16:37:23.510106 <4>[ 8.431574] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10731 16:37:23.516558 <4>[ 8.431574] Fallback method does not support PEC.
10732 16:37:23.526314 <6>[ 8.431780] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10733 16:37:23.532629 <3>[ 8.435680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 16:37:23.542974 <3>[ 8.435684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 16:37:23.546420 <6>[ 8.441486] pci 0000:00:00.0: supports D1 D2
10736 16:37:23.556213 <3>[ 8.447100] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10737 16:37:23.562752 <3>[ 8.449498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 16:37:23.569385 <6>[ 8.456618] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10739 16:37:23.578980 <3>[ 8.464693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 16:37:23.585668 <3>[ 8.472148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10741 16:37:23.595507 <6>[ 8.475349] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10742 16:37:23.605895 <6>[ 8.475722] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10743 16:37:23.608906 <6>[ 8.475806] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10744 16:37:23.619096 <6>[ 8.475831] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10745 16:37:23.625661 <6>[ 8.475847] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10746 16:37:23.632354 <6>[ 8.475862] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10747 16:37:23.638614 <6>[ 8.475969] pci 0000:01:00.0: supports D1 D2
10748 16:37:23.645373 <6>[ 8.475971] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 16:37:23.652108 <3>[ 8.481642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 16:37:23.658620 <6>[ 8.491099] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10751 16:37:23.668754 <6>[ 8.509879] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10752 16:37:23.674849 <6>[ 8.511000] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10753 16:37:23.681491 <6>[ 8.522135] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10754 16:37:23.692206 <6>[ 8.527122] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10755 16:37:23.698363 <6>[ 8.527140] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10756 16:37:23.701916 <6>[ 8.527672] Bluetooth: Core ver 2.22
10757 16:37:23.708575 <6>[ 8.527718] NET: Registered PF_BLUETOOTH protocol family
10758 16:37:23.715129 <6>[ 8.527719] Bluetooth: HCI device and connection manager initialized
10759 16:37:23.721850 <6>[ 8.527736] Bluetooth: HCI socket layer initialized
10760 16:37:23.724983 <6>[ 8.527740] Bluetooth: L2CAP socket layer initialized
10761 16:37:23.731455 <6>[ 8.527746] Bluetooth: SCO socket layer initialized
10762 16:37:23.738139 <6>[ 8.543785] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10763 16:37:23.744636 <6>[ 8.552777] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10764 16:37:23.758337 <6>[ 8.567636] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10765 16:37:23.767744 <6>[ 8.575446] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10766 16:37:23.771457 <6>[ 8.583685] usbcore: registered new interface driver uvcvideo
10767 16:37:23.778185 <6>[ 8.591606] pci 0000:00:00.0: PCI bridge to [bus 01]
10768 16:37:23.784530 <6>[ 8.592203] usbcore: registered new interface driver btusb
10769 16:37:23.791041 <6>[ 8.592406] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10770 16:37:23.801399 <4>[ 8.593084] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10771 16:37:23.807342 <3>[ 8.593092] Bluetooth: hci0: Failed to load firmware file (-2)
10772 16:37:23.810801 <3>[ 8.593094] Bluetooth: hci0: Failed to set up firmware (-2)
10773 16:37:23.824448 <4>[ 8.593097] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10774 16:37:23.830555 <6>[ 8.872977] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10775 16:37:23.837848 <6>[ 8.881121] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10776 16:37:23.843839 <6>[ 8.887959] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10777 16:37:23.850454 <6>[ 8.894302] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10778 16:37:23.872695 <5>[ 8.915157] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10779 16:37:23.895071 <5>[ 8.937145] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10780 16:37:23.901367 <5>[ 8.945177] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10781 16:37:23.911853 <4>[ 8.953704] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10782 16:37:23.918520 <6>[ 8.962679] cfg80211: failed to load regulatory.db
10783 16:37:23.976407 <6>[ 9.018537] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10784 16:37:23.983311 <6>[ 9.026106] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10785 16:37:24.007774 <6>[ 9.052955] mt7921e 0000:01:00.0: ASIC revision: 79610010
10786 16:37:24.113725 <6>[ 9.155363] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10787 16:37:24.116705 <6>[ 9.155363]
10788 16:37:24.126261 Begin: Loading essential drivers ... done.
10789 16:37:24.129862 Begin: Running /scripts/init-premount ... done.
10790 16:37:24.136244 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10791 16:37:24.146216 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10792 16:37:24.149637 Device /sys/class/net/eth0 found
10793 16:37:24.150029 done.
10794 16:37:24.156100 Begin: Waiting up to 180 secs for any network device to become available ... done.
10795 16:37:24.221411 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10796 16:37:24.228250 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10797 16:37:24.234872 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10798 16:37:24.241226 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10799 16:37:24.247694 host : mt8192-asurada-spherion-r0-cbg-0
10800 16:37:24.254482 domain : lava-rack
10801 16:37:24.258290 rootserver: 192.168.201.1 rootpath:
10802 16:37:24.258685 filename :
10803 16:37:24.266989 done.
10804 16:37:24.273752 Begin: Running /scripts/nfs-bottom ... done.
10805 16:37:24.292421 Begin: Running /scripts/init-bottom ... done.
10806 16:37:24.383595 <6>[ 9.425394] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10807 16:37:25.612045 <6>[ 10.657665] NET: Registered PF_INET6 protocol family
10808 16:37:25.619236 <6>[ 10.665034] Segment Routing with IPv6
10809 16:37:25.622572 <6>[ 10.669019] In-situ OAM (IOAM) with IPv6
10810 16:37:25.785840 <30>[ 10.804918] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10811 16:37:25.792303 <30>[ 10.838038] systemd[1]: Detected architecture arm64.
10812 16:37:25.799384
10813 16:37:25.803148 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10814 16:37:25.803227
10815 16:37:25.829997 <30>[ 10.875862] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10816 16:37:26.811880 <30>[ 11.854687] systemd[1]: Queued start job for default target graphical.target.
10817 16:37:26.865342 <30>[ 11.907975] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10818 16:37:26.871955 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10819 16:37:26.893960 <30>[ 11.936729] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10820 16:37:26.903445 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10821 16:37:26.922170 <30>[ 11.964730] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10822 16:37:26.932354 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10823 16:37:26.949742 <30>[ 11.992343] systemd[1]: Created slice user.slice - User and Session Slice.
10824 16:37:26.955996 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10825 16:37:26.980119 <30>[ 12.019240] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10826 16:37:26.989690 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10827 16:37:27.008092 <30>[ 12.047163] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10828 16:37:27.014629 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10829 16:37:27.043168 <30>[ 12.075590] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10830 16:37:27.052649 <30>[ 12.095495] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10831 16:37:27.059127 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10832 16:37:27.076249 <30>[ 12.118821] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10833 16:37:27.082977 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10834 16:37:27.100027 <30>[ 12.142981] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10835 16:37:27.110478 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10836 16:37:27.125098 <30>[ 12.171028] systemd[1]: Reached target paths.target - Path Units.
10837 16:37:27.131857 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10838 16:37:27.152766 <30>[ 12.195374] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10839 16:37:27.159491 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10840 16:37:27.173067 <30>[ 12.218926] systemd[1]: Reached target slices.target - Slice Units.
10841 16:37:27.183021 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10842 16:37:27.197305 <30>[ 12.242996] systemd[1]: Reached target swap.target - Swaps.
10843 16:37:27.203356 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10844 16:37:27.228567 <30>[ 12.271033] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10845 16:37:27.238073 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10846 16:37:27.257491 <30>[ 12.299900] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10847 16:37:27.267039 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10848 16:37:27.287211 <30>[ 12.329571] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10849 16:37:27.296716 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10850 16:37:27.314171 <30>[ 12.356929] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10851 16:37:27.324134 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10852 16:37:27.340887 <30>[ 12.383637] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10853 16:37:27.347331 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10854 16:37:27.366093 <30>[ 12.408335] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10855 16:37:27.375554 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10856 16:37:27.394630 <30>[ 12.437594] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10857 16:37:27.404411 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10858 16:37:27.421166 <30>[ 12.464105] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10859 16:37:27.431277 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10860 16:37:27.480648 <30>[ 12.523400] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10861 16:37:27.487292 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10862 16:37:27.506940 <30>[ 12.549436] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10863 16:37:27.513381 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10864 16:37:27.564533 <30>[ 12.607325] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10865 16:37:27.571376 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10866 16:37:27.599674 <30>[ 12.635601] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10867 16:37:27.614876 <30>[ 12.657377] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10868 16:37:27.624233 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10869 16:37:27.646062 <30>[ 12.688407] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10870 16:37:27.652075 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10871 16:37:27.677762 <30>[ 12.720563] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10872 16:37:27.684740 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10873 16:37:27.710283 <30>[ 12.752706] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10874 16:37:27.720166 Startin<6>[ 12.762014] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10875 16:37:27.726651 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10876 16:37:27.750146 <30>[ 12.792721] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10877 16:37:27.759796 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10878 16:37:27.782097 <30>[ 12.824481] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10879 16:37:27.788585 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10880 16:37:27.814002 <30>[ 12.856562] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10881 16:37:27.820332 Startin<6>[ 12.865351] fuse: init (API version 7.37)
10882 16:37:27.826732 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10883 16:37:27.888788 <30>[ 12.931780] systemd[1]: Starting systemd-journald.service - Journal Service...
10884 16:37:27.895329 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10885 16:37:27.927909 <30>[ 12.970683] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10886 16:37:27.934398 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10887 16:37:27.958756 <30>[ 12.998513] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10888 16:37:27.965581 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10889 16:37:27.989950 <30>[ 13.032362] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10890 16:37:27.999258 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10891 16:37:28.045477 <30>[ 13.087656] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10892 16:37:28.058750 Starting [0;1;39msystemd-udev-trig…[<3>[ 13.099986] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 16:37:28.062341 0m - Coldplug All udev Devices...
10894 16:37:28.084788 <30>[ 13.127250] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10895 16:37:28.091433 <3>[ 13.130967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 16:37:28.101475 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10897 16:37:28.120830 <30>[ 13.163441] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10898 16:37:28.134778 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 13.176605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 16:37:28.137603 X Message Queue File System.
10900 16:37:28.156691 <30>[ 13.199146] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10901 16:37:28.163406 <3>[ 13.206568] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 16:37:28.173060 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10903 16:37:28.194055 <30>[ 13.236620] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10904 16:37:28.204000 [[0;32m OK [<3>[ 13.245981] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 16:37:28.210682 0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10906 16:37:28.229251 <30>[ 13.272215] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10907 16:37:28.239412 <30>[ 13.280384] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10908 16:37:28.252893 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 13.292997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 16:37:28.255819 onfigfs…[0m - Load Kernel Module configfs.
10910 16:37:28.270318 <30>[ 13.315742] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10911 16:37:28.281000 <30>[ 13.323588] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10912 16:37:28.291142 <3>[ 13.323822] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 16:37:28.297728 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10914 16:37:28.315494 <30>[ 13.360754] systemd[1]: modprobe@drm.service: Deactivated successfully.
10915 16:37:28.325095 <3>[ 13.364006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 16:37:28.331607 <30>[ 13.368632] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10917 16:37:28.341945 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10918 16:37:28.362552 <30>[ 13.405170] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10919 16:37:28.369969 <30>[ 13.413325] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10920 16:37:28.379287 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10921 16:37:28.397238 <30>[ 13.439818] systemd[1]: Started systemd-journald.service - Journal Service.
10922 16:37:28.403389 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10923 16:37:28.426188 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10924 16:37:28.443015 <4>[ 13.489437] power_supply_show_property: 2 callbacks suppressed
10925 16:37:28.453246 <3>[ 13.489455] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 16:37:28.469704 <4>[ 13.504366] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10927 16:37:28.476444 <3>[ 13.519998] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10928 16:37:28.483774 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10929 16:37:28.493913 <3>[ 13.536666] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 16:37:28.505656 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10931 16:37:28.525128 <3>[ 13.567285] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 16:37:28.534691 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10933 16:37:28.557131 [[0;32m OK [<3>[ 13.596819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 16:37:28.563837 0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10935 16:37:28.582282 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10936 16:37:28.588895 <3>[ 13.632375] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 16:37:28.602869 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10938 16:37:28.623889 <3>[ 13.666885] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 16:37:28.657287 <3>[ 13.700370] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 16:37:28.667392 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10941 16:37:28.694049 Mounting [0;1;39msys-kernel-config…ernel Configuration File System..<3>[ 13.735299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 16:37:28.694169 .
10943 16:37:28.715807 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10944 16:37:28.725929 <3>[ 13.766622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 16:37:28.737342 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10946 16:37:28.754116 <3>[ 13.797090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 16:37:28.774771 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10948 16:37:28.796607 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10949 16:37:28.807006 <46>[ 13.849661] systemd-journald[311]: Received client request to flush runtime journal.
10950 16:37:28.822429 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10951 16:37:28.841074 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10952 16:37:28.865729 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10953 16:37:28.885646 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10954 16:37:29.891906 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10955 16:37:29.952329 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10956 16:37:30.202734 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10957 16:37:30.300877 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10958 16:37:30.320854 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10959 16:37:30.340646 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10960 16:37:30.412460 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10961 16:37:30.439228 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10962 16:37:30.658114 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10963 16:37:30.712843 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10964 16:37:30.773415 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10965 16:37:30.800585 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10966 16:37:30.997704 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10967 16:37:31.022259 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10968 16:37:31.132565 <6>[ 16.178887] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10969 16:37:31.168231 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10970 16:37:31.185284 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10971 16:37:31.244877 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10972 16:37:31.291351 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10973 16:37:31.360864 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10974 16:37:31.381206 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10975 16:37:31.400962 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10976 16:37:31.423934 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10977 16:37:31.441980 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10978 16:37:31.461430 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10979 16:37:31.500800 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10980 16:37:31.520686 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10981 16:37:31.540885 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10982 16:37:31.560275 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10983 16:37:31.587777 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10984 16:37:31.629750 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10985 16:37:31.648935 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10986 16:37:31.671778 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10987 16:37:31.691705 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10988 16:37:31.708031 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10989 16:37:31.726086 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10990 16:37:31.744446 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10991 16:37:31.760925 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10992 16:37:31.810566 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10993 16:37:31.844277 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10994 16:37:31.904546 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10995 16:37:31.926213 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10996 16:37:32.021151 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10997 16:37:32.072876 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10998 16:37:32.091624 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10999 16:37:32.108507 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11000 16:37:32.128903 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11001 16:37:32.166891 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11002 16:37:32.302648 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11003 16:37:32.322915 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11004 16:37:32.341354 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11005 16:37:32.398654 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11006 16:37:32.440534 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11007 16:37:32.508869
11008 16:37:32.511754 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11009 16:37:32.511835
11010 16:37:32.515401 debian-bookworm-arm64 login: root (automatic login)
11011 16:37:32.515503
11012 16:37:32.750059 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11013 16:37:32.750174
11014 16:37:32.756199 The programs included with the Debian GNU/Linux system are free software;
11015 16:37:32.762861 the exact distribution terms for each program are described in the
11016 16:37:32.766516 individual files in /usr/share/doc/*/copyright.
11017 16:37:32.766597
11018 16:37:32.772994 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11019 16:37:32.776298 permitted by applicable law.
11020 16:37:32.818801 Matched prompt #10: / #
11022 16:37:32.819041 Setting prompt string to ['/ #']
11023 16:37:32.819131 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11025 16:37:32.819311 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11026 16:37:32.819391 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11027 16:37:32.819458 Setting prompt string to ['/ #']
11028 16:37:32.819515 Forcing a shell prompt, looking for ['/ #']
11030 16:37:32.869700 / #
11031 16:37:32.869890 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 16:37:32.869977 Waiting using forced prompt support (timeout 00:02:30)
11033 16:37:32.875037
11034 16:37:32.875314 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11035 16:37:32.875449 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11037 16:37:32.975797 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon'
11038 16:37:32.981275 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396170/extract-nfsrootfs-5a8crdon'
11040 16:37:33.081834 / # export NFS_SERVER_IP='192.168.201.1'
11041 16:37:33.086767 export NFS_SERVER_IP='192.168.201.1'
11042 16:37:33.087042 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11043 16:37:33.087134 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11044 16:37:33.087221 end: 2 depthcharge-action (duration 00:01:22) [common]
11045 16:37:33.087306 start: 3 lava-test-retry (timeout 00:30:00) [common]
11046 16:37:33.087389 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11047 16:37:33.087457 Using namespace: common
11049 16:37:33.187764 / # #
11050 16:37:33.187953 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11051 16:37:33.192611 #
11052 16:37:33.192871 Using /lava-14396170
11054 16:37:33.293205 / # export SHELL=/bin/sh
11055 16:37:33.298218 export SHELL=/bin/sh
11057 16:37:33.398706 / # . /lava-14396170/environment
11058 16:37:33.404221 . /lava-14396170/environment
11060 16:37:33.509668 / # /lava-14396170/bin/lava-test-runner /lava-14396170/0
11061 16:37:33.509901 Test shell timeout: 10s (minimum of the action and connection timeout)
11062 16:37:33.514763 /lava-14396170/bin/lava-test-runner /lava-14396170/0
11063 16:37:33.708911 + export TESTRUN_ID=0_lc-compliance
11064 16:37:33.715592 + cd /lava-14396170/0/tests/0_lc-compliance
11065 16:37:33.715706 + cat uuid
11066 16:37:33.719768 + UUID=14396170_1.6.2.3.1
11067 16:37:33.719841 + set +x
11068 16:37:33.726403 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14396170_1.6.2.3.1>
11069 16:37:33.726653 Received signal: <STARTRUN> 0_lc-compliance 14396170_1.6.2.3.1
11070 16:37:33.726721 Starting test lava.0_lc-compliance (14396170_1.6.2.3.1)
11071 16:37:33.726823 Skipping test definition patterns.
11072 16:37:33.729356 + /usr/bin/lc-compliance-parser.sh
11073 16:37:35.313899 [0:00:20.239105769] [416] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11074 16:37:35.316834 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11075 16:37:35.330988 [0:00:20.256348231] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11076 16:37:35.376935 [==========] Running 120 tests from 1 test suite.
11077 16:37:35.393175 [0:00:20.318573693] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11078 16:37:35.425057 [----------] Global test environment set-up.
11079 16:37:35.446807 [0:00:20.372944077] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11080 16:37:35.474441 [----------] 120 tests from CaptureTests/SingleStream
11081 16:37:35.502181 [0:00:20.427375539] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11082 16:37:35.524997 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11083 16:37:35.567238 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11084 16:37:35.567576 Received signal: <TESTSET> START CaptureTests/SingleStream
11085 16:37:35.567678 Starting test_set CaptureTests/SingleStream
11086 16:37:35.570689 Camera needs 4 requests, can't test only 1
11087 16:37:35.625091 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11088 16:37:35.675208
11089 16:37:35.731049 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (62 ms)
11090 16:37:35.802775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11091 16:37:35.803061 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11093 16:37:35.813847 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11094 16:37:35.848708 Camera needs 4 requests, can't test only 2
11095 16:37:35.897846 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11096 16:37:35.930878 [0:00:20.856484693] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 16:37:35.949156
11098 16:37:36.000851 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11099 16:37:36.070178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11100 16:37:36.070520 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11102 16:37:36.083567 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11103 16:37:36.184179 Camera needs 4 requests, can't test only 3
11104 16:37:36.185233 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11105 16:37:36.251809
11106 16:37:36.309685 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
11107 16:37:36.363710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11108 16:37:36.363995 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11110 16:37:36.376174 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11111 16:37:36.415610 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (428 ms)
11112 16:37:36.483231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11113 16:37:36.483518 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11115 16:37:36.496948 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11116 16:37:36.616346 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (694 ms)
11117 16:37:36.626513 [0:00:21.551878308] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11118 16:37:36.697764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11119 16:37:36.698051 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11121 16:37:36.712077 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11122 16:37:37.873314 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1256 ms)
11123 16:37:37.883087 [0:00:22.808718539] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11124 16:37:37.941799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11125 16:37:37.942083 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11127 16:37:37.952520 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11128 16:37:39.690287 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1816 ms)
11129 16:37:39.700363 [0:00:24.625874385] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11130 16:37:39.778691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11131 16:37:39.779391 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11133 16:37:39.794037 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11134 16:37:42.417230 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2727 ms)
11135 16:37:42.426750 [0:00:27.353493078] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 16:37:42.494415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11137 16:37:42.495225 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11139 16:37:42.510918 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11140 16:37:46.614408 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4197 ms)
11141 16:37:46.623791 [0:00:31.550760001] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11142 16:37:46.688851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11143 16:37:46.689146 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11145 16:37:46.699574 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11146 16:37:52.914518 <6>[ 37.967062] vpu: disabling
11147 16:37:52.917766 <6>[ 37.970160] vproc2: disabling
11148 16:37:52.921707 <6>[ 37.973887] vproc1: disabling
11149 16:37:52.925662 <6>[ 37.977925] vaud18: disabling
11150 16:37:52.932469 <6>[ 37.981673] vsram_others: disabling
11151 16:37:52.935913 <6>[ 37.985843] va09: disabling
11152 16:37:52.939203 <6>[ 37.989238] vsram_md: disabling
11153 16:37:52.942747 <6>[ 37.993007] Vgpu: disabling
11154 16:37:53.191457 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6577 ms)
11155 16:37:53.201161 [0:00:38.128727771] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11156 16:37:53.256300 [0:00:38.183985309] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11157 16:37:53.259844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11158 16:37:53.260117 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11160 16:37:53.269129 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11161 16:37:53.309351 [0:00:38.236968540] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11162 16:37:53.312364 Camera needs 4 requests, can't test only 1
11163 16:37:53.351152 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11164 16:37:53.361062 [0:00:38.289612078] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11165 16:37:53.403551
11166 16:37:53.454316 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11167 16:37:53.520240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11168 16:37:53.520525 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11170 16:37:53.532107 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11171 16:37:53.569085 Camera needs 4 requests, can't test only 2
11172 16:37:53.623053 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11173 16:37:53.672087
11174 16:37:53.730253 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11175 16:37:53.792399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11176 16:37:53.792689 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11178 16:37:53.803621 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11179 16:37:53.842940 Camera needs 4 requests, can't test only 3
11180 16:37:53.902013 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11181 16:37:53.956707
11182 16:37:54.016994 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (52 ms)
11183 16:37:54.055266 [0:00:38.982970771] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 16:37:54.078372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11185 16:37:54.078654 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11187 16:37:54.090467 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11188 16:37:54.128199 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (692 ms)
11189 16:37:54.187000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11190 16:37:54.187292 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11192 16:37:54.196873 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11193 16:37:54.954039 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (907 ms)
11194 16:37:54.967388 [0:00:39.891332155] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11195 16:37:55.017561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11196 16:37:55.017904 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11198 16:37:55.029059 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11199 16:37:56.210394 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1256 ms)
11200 16:37:56.223499 [0:00:41.148113617] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11201 16:37:56.281673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11202 16:37:56.281973 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11204 16:37:56.292701 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11205 16:37:58.027971 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1817 ms)
11206 16:37:58.040661 [0:00:42.966087309] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11207 16:37:58.088706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11208 16:37:58.088983 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11210 16:37:58.097809 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11211 16:38:00.757452 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2729 ms)
11212 16:38:00.770787 [0:00:45.695668463] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11213 16:38:00.822344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11214 16:38:00.822621 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11216 16:38:00.832094 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11217 16:38:04.954374 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4197 ms)
11218 16:38:04.967619 [0:00:49.893157156] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11219 16:38:05.027201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11220 16:38:05.027475 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11222 16:38:05.038202 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11223 16:38:11.531401 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6577 ms)
11224 16:38:11.544249 [0:00:56.470956541] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11225 16:38:11.595489 [0:00:56.525002079] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 16:38:11.607128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11227 16:38:11.607423 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11229 16:38:11.618539 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11230 16:38:11.649581 [0:00:56.578997156] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 16:38:11.660169 Camera needs 4 requests, can't test only 1
11232 16:38:11.703937 [0:00:56.633814464] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11233 16:38:11.717136 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11234 16:38:11.766489
11235 16:38:11.819728 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (54 ms)
11236 16:38:11.881855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11237 16:38:11.882140 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11239 16:38:11.894089 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11240 16:38:11.931256 Camera needs 4 requests, can't test only 2
11241 16:38:11.985301 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11242 16:38:12.036412
11243 16:38:12.096492 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
11244 16:38:12.159077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11245 16:38:12.159362 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11247 16:38:12.172422 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11248 16:38:12.212649 Camera needs 4 requests, can't test only 3
11249 16:38:12.263806 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11250 16:38:12.313559
11251 16:38:12.373564 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11252 16:38:12.398854 [0:00:57.328318156] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 16:38:12.442807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11254 16:38:12.443090 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11256 16:38:12.455700 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11257 16:38:12.488591 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (695 ms)
11258 16:38:12.552114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11259 16:38:12.552392 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11261 16:38:12.564506 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11262 16:38:16.400520 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (906 ms)
11263 16:38:16.400668 [0:00:58.235884926] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11264 16:38:16.400765 [0:00:59.492699618] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11265 16:38:16.400847 [0:01:01.308352772] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 16:38:16.421869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11267 16:38:16.422166 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11269 16:38:16.433690 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11270 16:38:16.472120 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1256 ms)
11271 16:38:16.534075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11272 16:38:16.534365 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11274 16:38:16.547422 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11275 16:38:16.586485 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1815 ms)
11276 16:38:16.654475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11277 16:38:16.654751 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11279 16:38:16.667075 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11280 16:38:19.097282 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2728 ms)
11281 16:38:19.110429 [0:01:04.037700464] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11282 16:38:19.168503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11283 16:38:19.168795 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11285 16:38:19.178042 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11286 16:38:23.294674 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4197 ms)
11287 16:38:23.307620 [0:01:08.235142926] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11288 16:38:23.357636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11289 16:38:23.357936 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11291 16:38:23.369385 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11292 16:38:29.871118 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6577 ms)
11293 16:38:29.884380 [0:01:14.812989157] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 16:38:29.934453 [0:01:14.866411773] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 16:38:29.941213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11296 16:38:29.941510 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11298 16:38:29.944133 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11299 16:38:29.981106 Camera needs 4 requests, can't test only 1
11300 16:38:29.991352 [0:01:14.920113850] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 16:38:30.044209 [0:01:14.976159465] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11302 16:38:30.047683 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11303 16:38:30.089792
11304 16:38:30.143713 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11305 16:38:30.192224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11306 16:38:30.192525 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11308 16:38:30.204853 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11309 16:38:30.240689 Camera needs 4 requests, can't test only 2
11310 16:38:30.290562 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11311 16:38:30.341213
11312 16:38:30.393481 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (52 ms)
11313 16:38:30.454833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11314 16:38:30.455141 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11316 16:38:30.466030 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11317 16:38:30.503367 Camera needs 4 requests, can't test only 3
11318 16:38:30.553193 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11319 16:38:30.603140
11320 16:38:30.656830 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (56 ms)
11321 16:38:30.720958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11322 16:38:30.721247 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11324 16:38:30.731108 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11325 16:38:30.741038 [0:01:15.669710927] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11326 16:38:30.770438 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11327 16:38:30.837470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11328 16:38:30.837781 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11330 16:38:30.848310 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11331 16:38:31.634370 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (904 ms)
11332 16:38:31.644161 [0:01:16.576286773] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11333 16:38:31.698098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11334 16:38:31.698383 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11336 16:38:31.706651 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11337 16:38:32.891750 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1256 ms)
11338 16:38:32.904787 [0:01:17.833328696] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11339 16:38:32.982754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11340 16:38:32.983441 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11342 16:38:32.994927 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11343 16:38:34.708529 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1816 ms)
11344 16:38:34.721437 [0:01:19.650224081] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11345 16:38:34.793480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11346 16:38:34.794261 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11348 16:38:34.808066 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11349 16:38:37.435677 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2727 ms)
11350 16:38:37.448639 [0:01:22.377503312] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11351 16:38:37.523984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11352 16:38:37.524657 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11354 16:38:37.537631 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11355 16:38:41.632465 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4197 ms)
11356 16:38:41.644947 [0:01:26.574884235] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11357 16:38:41.708189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11358 16:38:41.708469 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11360 16:38:41.719478 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11361 16:38:48.208929 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6578 ms)
11362 16:38:48.222848 [0:01:33.152860774] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11363 16:38:48.274281 [0:01:33.207823543] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 16:38:48.280723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11365 16:38:48.280989 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11367 16:38:48.290403 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11368 16:38:48.329059 [0:01:33.262998851] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 16:38:48.332612 Camera needs 4 requests, can't test only 1
11370 16:38:48.383477 [0:01:33.317458543] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11371 16:38:48.387064 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11372 16:38:48.434805
11373 16:38:48.485387 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (55 ms)
11374 16:38:48.545420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11375 16:38:48.545733 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11377 16:38:48.557285 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11378 16:38:48.595647 Camera needs 4 requests, can't test only 2
11379 16:38:48.650142 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11380 16:38:48.704219
11381 16:38:48.754078 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11382 16:38:48.814911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11383 16:38:48.815232 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11385 16:38:48.826717 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11386 16:38:48.863903 Camera needs 4 requests, can't test only 3
11387 16:38:48.922775 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11388 16:38:48.976592
11389 16:38:49.028909 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (54 ms)
11390 16:38:49.097387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11391 16:38:49.097685 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11393 16:38:49.109081 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11394 16:38:50.453602 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2079 ms)
11395 16:38:50.466316 [0:01:35.397272697] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11396 16:38:50.522075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11397 16:38:50.522350 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11399 16:38:50.533038 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11400 16:38:53.171304 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2717 ms)
11401 16:38:53.184602 [0:01:38.115349389] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11402 16:38:53.253923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11403 16:38:53.254222 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11405 16:38:53.266418 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11406 16:38:56.932904 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3762 ms)
11407 16:38:56.946230 [0:01:41.877583774] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11408 16:38:57.001111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11409 16:38:57.001387 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11411 16:38:57.010655 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11412 16:39:02.374506 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5441 ms)
11413 16:39:02.387807 [0:01:47.319462005] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11414 16:39:02.455935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11415 16:39:02.456631 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11417 16:39:02.469112 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11418 16:39:10.547575 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8174 ms)
11419 16:39:10.560768 [0:01:55.493773698] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11420 16:39:10.622112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11421 16:39:10.622391 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11423 16:39:10.634377 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11424 16:39:23.129069 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12582 ms)
11425 16:39:23.141960 [0:02:08.076614314] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 16:39:23.198510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11427 16:39:23.198835 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11429 16:39:23.210955 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11430 16:39:42.851598 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19724 ms)
11431 16:39:42.864716 [0:02:27.801385085] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11432 16:39:42.916948 [0:02:27.857027931] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 16:39:42.924081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11434 16:39:42.924375 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11436 16:39:42.934440 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11437 16:39:42.972034 [0:02:27.911886316] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 16:39:42.975353 Camera needs 4 requests, can't test only 1
11439 16:39:43.025130 [0:02:27.964913623] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11440 16:39:43.031989 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11441 16:39:43.075407
11442 16:39:43.135557 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11443 16:39:43.193015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11444 16:39:43.193315 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11446 16:39:43.200854 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11447 16:39:43.245355 Camera needs 4 requests, can't test only 2
11448 16:39:43.307336 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11449 16:39:43.365388
11450 16:39:43.434903 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11451 16:39:43.507040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11452 16:39:43.507375 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11454 16:39:43.519332 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11455 16:39:43.562109 Camera needs 4 requests, can't test only 3
11456 16:39:43.616846 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11457 16:39:43.674359
11458 16:39:43.741329 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11459 16:39:43.804866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11460 16:39:43.805181 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11462 16:39:43.811367 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11463 16:39:45.098570 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2078 ms)
11464 16:39:45.108384 [0:02:30.045120085] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11465 16:39:45.162702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11466 16:39:45.163018 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11468 16:39:45.170608 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11469 16:39:47.810825 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11470 16:39:47.820427 [0:02:32.758009316] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11471 16:39:47.887328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11472 16:39:47.887625 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11474 16:39:47.894810 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11475 16:39:51.572589 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3761 ms)
11476 16:39:51.581987 [0:02:36.519651162] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11477 16:39:51.643130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11478 16:39:51.643430 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11480 16:39:51.651029 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11481 16:39:57.013066 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5441 ms)
11482 16:39:57.023391 [0:02:41.961293624] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11483 16:39:57.074113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11484 16:39:57.074438 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11486 16:39:57.081062 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11487 16:40:05.187354 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8175 ms)
11488 16:40:05.197471 [0:02:50.137056471] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11489 16:40:05.258466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11490 16:40:05.258759 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11492 16:40:05.266013 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11493 16:40:17.770920 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12584 ms)
11494 16:40:17.781011 [0:03:02.721504087] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 16:40:17.842291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11496 16:40:17.842581 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11498 16:40:17.850881 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11499 16:40:37.493444 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19724 ms)
11500 16:40:37.503214 [0:03:22.445973550] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 16:40:37.557447 [0:03:22.503256857] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 16:40:37.568044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11503 16:40:37.568342 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11505 16:40:37.576465 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11506 16:40:37.612468 [0:03:22.558392088] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 16:40:37.615309 Camera needs 4 requests, can't test only 1
11508 16:40:37.664862 [0:03:22.611151703] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11509 16:40:37.668445 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11510 16:40:37.708414
11511 16:40:37.765163 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11512 16:40:37.824703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11513 16:40:37.825006 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11515 16:40:37.832729 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11516 16:40:37.872606 Camera needs 4 requests, can't test only 2
11517 16:40:37.914714 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11518 16:40:37.961838
11519 16:40:38.016280 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11520 16:40:38.074779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11521 16:40:38.075078 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11523 16:40:38.081942 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11524 16:40:38.115424 Camera needs 4 requests, can't test only 3
11525 16:40:38.165290 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11526 16:40:38.211267
11527 16:40:38.266156 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (52 ms)
11528 16:40:38.323780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11529 16:40:38.324103 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11531 16:40:38.332533 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11532 16:40:39.738853 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2078 ms)
11533 16:40:39.748565 [0:03:24.691314934] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11534 16:40:39.806526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11535 16:40:39.806855 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11537 16:40:39.814057 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11538 16:40:42.449120 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2710 ms)
11539 16:40:42.459080 [0:03:27.401391242] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11540 16:40:42.514052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11541 16:40:42.514369 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11543 16:40:42.521456 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11544 16:40:46.207907 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3759 ms)
11545 16:40:46.218065 [0:03:31.160806858] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11546 16:40:46.279882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11547 16:40:46.280164 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11549 16:40:46.290809 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11550 16:40:51.647674 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5439 ms)
11551 16:40:51.657395 [0:03:36.600806012] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11552 16:40:51.733945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11553 16:40:51.734612 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11555 16:40:51.746302 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11556 16:40:59.819564 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8173 ms)
11557 16:40:59.829084 [0:03:44.773531935] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11558 16:40:59.886814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11559 16:40:59.887100 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11561 16:40:59.894105 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11562 16:41:12.399848 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12581 ms)
11563 16:41:12.409203 [0:03:57.355756398] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 16:41:12.465770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11565 16:41:12.466093 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11567 16:41:12.473019 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11568 16:41:32.119806 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19721 ms)
11569 16:41:32.130112 [0:04:17.077468630] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11570 16:41:32.179560 [0:04:17.131255553] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 16:41:32.215601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11572 16:41:32.216535 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11574 16:41:32.234037 [0:04:17.185677784] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11575 16:41:32.240118 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11576 16:41:32.287995 [0:04:17.240143168] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 16:41:32.291633 Camera needs 4 requests, can't test only 1
11578 16:41:32.334490 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11579 16:41:32.394313
11580 16:41:32.463994 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11581 16:41:32.528238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11582 16:41:32.528574 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11584 16:41:32.537435 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11585 16:41:32.578196 Camera needs 4 requests, can't test only 2
11586 16:41:32.629831 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11587 16:41:32.676264
11588 16:41:32.735376 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11589 16:41:32.796088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11590 16:41:32.796397 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11592 16:41:32.802950 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11593 16:41:32.831513 Camera needs 4 requests, can't test only 3
11594 16:41:32.881662 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11595 16:41:32.930827
11596 16:41:32.997017 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (55 ms)
11597 16:41:33.056427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11598 16:41:33.056710 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11600 16:41:33.064074 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11601 16:41:34.362999 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2079 ms)
11602 16:41:34.373006 [0:04:19.321488322] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11603 16:41:34.427522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11604 16:41:34.427808 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11606 16:41:34.434381 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11607 16:41:37.073908 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2710 ms)
11608 16:41:37.083540 [0:04:22.032180092] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11609 16:41:37.135428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11610 16:41:37.135698 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11612 16:41:37.143637 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11613 16:41:40.833057 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3760 ms)
11614 16:41:40.843401 [0:04:25.792509630] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11615 16:41:40.898384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11616 16:41:40.898710 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11618 16:41:40.905757 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11619 16:41:46.272490 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5439 ms)
11620 16:41:46.282086 [0:04:31.232226323] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11621 16:41:46.337757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11622 16:41:46.338055 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11624 16:41:46.346065 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11625 16:41:54.444954 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8173 ms)
11626 16:41:54.454540 [0:04:39.405533708] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11627 16:41:54.511635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11628 16:41:54.511935 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11630 16:41:54.519391 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11631 16:42:07.024641 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12581 ms)
11632 16:42:07.034199 [0:04:51.987188170] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11633 16:42:07.087057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11634 16:42:07.087345 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11636 16:42:07.096064 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11637 16:42:26.745496 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19722 ms)
11638 16:42:26.755545 [0:05:11.709564479] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11639 16:42:26.811869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11640 16:42:26.812142 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11642 16:42:26.819914 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11643 16:42:27.158781 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (416 ms)
11644 16:42:27.171261 [0:05:12.126428248] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11645 16:42:27.231864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11646 16:42:27.232150 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11648 16:42:27.244260 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11649 16:42:27.646850 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (488 ms)
11650 16:42:27.660530 [0:05:12.614907556] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11651 16:42:27.717115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11652 16:42:27.717412 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11654 16:42:27.729662 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11655 16:42:28.203344 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (556 ms)
11656 16:42:28.213348 [0:05:13.171141633] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11657 16:42:28.270577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11658 16:42:28.270862 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11660 16:42:28.281478 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11661 16:42:28.898924 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (695 ms)
11662 16:42:28.909239 [0:05:13.867101787] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11663 16:42:28.964793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11664 16:42:28.965080 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11666 16:42:28.975871 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11667 16:42:29.805759 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (906 ms)
11668 16:42:29.818918 [0:05:14.773683864] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11669 16:42:29.874415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11670 16:42:29.874735 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11672 16:42:29.885190 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11673 16:42:31.062704 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1256 ms)
11674 16:42:31.075260 [0:05:16.030398018] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11675 16:42:31.129504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11676 16:42:31.129830 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11678 16:42:31.141090 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11679 16:42:32.878560 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1816 ms)
11680 16:42:32.891555 [0:05:17.846803172] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11681 16:42:32.938775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11682 16:42:32.939073 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11684 16:42:32.949765 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11685 16:42:35.605456 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2727 ms)
11686 16:42:35.617948 [0:05:20.574359249] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11687 16:42:35.668708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11688 16:42:35.669021 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11690 16:42:35.678376 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11691 16:42:39.802442 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4197 ms)
11692 16:42:39.815066 [0:05:24.771389018] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11693 16:42:39.870626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11694 16:42:39.870908 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11696 16:42:39.882281 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11697 16:42:46.379019 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6577 ms)
11698 16:42:46.392423 [0:05:31.349109326] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 16:42:46.447442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11700 16:42:46.447729 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11702 16:42:46.459110 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11703 16:42:46.798436 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (416 ms)
11704 16:42:46.808526 [0:05:31.765102942] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11705 16:42:46.864866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11706 16:42:46.865151 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11708 16:42:46.873132 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11709 16:42:47.284304 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (485 ms)
11710 16:42:47.294401 [0:05:32.251319096] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11711 16:42:47.359717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11712 16:42:47.360003 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11714 16:42:47.366323 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11715 16:42:47.841334 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (556 ms)
11716 16:42:47.851413 [0:05:32.808158096] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11717 16:42:47.911664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11718 16:42:47.911945 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11720 16:42:47.920104 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11721 16:42:48.538188 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (696 ms)
11722 16:42:48.547897 [0:05:33.504747173] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11723 16:42:48.604253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11724 16:42:48.604540 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11726 16:42:48.612394 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11727 16:42:49.446028 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (908 ms)
11728 16:42:49.456183 [0:05:34.413404019] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11729 16:42:49.509437 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11731 16:42:49.511999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11732 16:42:49.519427 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11733 16:42:50.702562 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1256 ms)
11734 16:42:50.712223 [0:05:35.669269250] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11735 16:42:50.766941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11736 16:42:50.767252 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11738 16:42:50.775193 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11739 16:42:52.518495 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1816 ms)
11740 16:42:52.528323 [0:05:37.485876635] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11741 16:42:52.583773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11742 16:42:52.584106 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11744 16:42:52.591238 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11745 16:42:55.246902 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2728 ms)
11746 16:42:55.256511 [0:05:40.214106096] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11747 16:42:55.310886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11748 16:42:55.311190 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11750 16:42:55.319044 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11751 16:42:59.442813 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4196 ms)
11752 16:42:59.452679 [0:05:44.411252173] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11753 16:42:59.508472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11754 16:42:59.508813 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11756 16:42:59.516109 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11757 16:43:06.020005 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6577 ms)
11758 16:43:06.030068 [0:05:50.989050635] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11759 16:43:06.087202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11760 16:43:06.087516 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11762 16:43:06.096897 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11763 16:43:06.436902 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (416 ms)
11764 16:43:06.446298 [0:05:51.405454328] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11765 16:43:06.499913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11766 16:43:06.500234 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11768 16:43:06.507037 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11769 16:43:06.923215 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (486 ms)
11770 16:43:06.933195 [0:05:51.892413097] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11771 16:43:06.989272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11772 16:43:06.989571 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11774 16:43:06.998073 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11775 16:43:07.479993 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (556 ms)
11776 16:43:07.489232 [0:05:52.448815635] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11777 16:43:07.545795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11778 16:43:07.546089 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11780 16:43:07.552240 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11781 16:43:08.176565 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (696 ms)
11782 16:43:08.186061 [0:05:53.145302482] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11783 16:43:08.240496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11784 16:43:08.240803 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11786 16:43:08.248322 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11787 16:43:09.084541 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (908 ms)
11788 16:43:09.094455 [0:05:54.053547559] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11789 16:43:09.147194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11790 16:43:09.147474 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11792 16:43:09.154478 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11793 16:43:10.340432 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1255 ms)
11794 16:43:10.350175 [0:05:55.309764405] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11795 16:43:10.402961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11796 16:43:10.403247 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11798 16:43:10.410886 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11799 16:43:12.156490 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1816 ms)
11800 16:43:12.166409 [0:05:57.126475174] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11801 16:43:12.227204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11802 16:43:12.227537 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11804 16:43:12.234554 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11805 16:43:14.884182 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2727 ms)
11806 16:43:14.893529 [0:05:59.853627559] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11807 16:43:14.951959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11808 16:43:14.952252 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11810 16:43:14.960694 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11811 16:43:19.080269 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4196 ms)
11812 16:43:19.090408 [0:06:04.050763790] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11813 16:43:19.146744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11814 16:43:19.147022 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11816 16:43:19.154896 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11817 16:43:25.656980 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6577 ms)
11818 16:43:25.666907 [0:06:10.628331098] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11819 16:43:25.723702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11820 16:43:25.724001 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11822 16:43:25.731847 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11823 16:43:26.073495 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (416 ms)
11824 16:43:26.083230 [0:06:11.044786175] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11825 16:43:26.147474 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11827 16:43:26.150957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11828 16:43:26.161228 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11829 16:43:26.559815 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (486 ms)
11830 16:43:26.569841 [0:06:11.530885944] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11831 16:43:26.620181 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11833 16:43:26.623252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11834 16:43:26.632213 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11835 16:43:27.113148 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (556 ms)
11836 16:43:27.126083 [0:06:12.087460560] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11837 16:43:27.182138 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11839 16:43:27.185378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11840 16:43:27.194369 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11841 16:43:27.812469 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (696 ms)
11842 16:43:27.822426 [0:06:12.783854406] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11843 16:43:27.879616 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11845 16:43:27.882534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11846 16:43:27.891732 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11847 16:43:28.719531 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (906 ms)
11848 16:43:28.729180 [0:06:13.690915483] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11849 16:43:28.784050 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11851 16:43:28.786869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11852 16:43:28.795763 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11853 16:43:29.975828 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1256 ms)
11854 16:43:29.985529 [0:06:14.947140714] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11855 16:43:30.052184 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11857 16:43:30.055515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11858 16:43:30.066055 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11859 16:43:31.792027 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1816 ms)
11860 16:43:31.802110 [0:06:16.764154098] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11861 16:43:31.855086 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11863 16:43:31.857776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11864 16:43:31.866612 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11865 16:43:34.519519 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2727 ms)
11866 16:43:34.529784 [0:06:19.491512791] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11867 16:43:34.583343 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11869 16:43:34.586553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11870 16:43:34.595017 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11871 16:43:38.716176 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4196 ms)
11872 16:43:38.725540 [0:06:23.688243099] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11873 16:43:38.792852 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11875 16:43:38.796145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11876 16:43:38.805405 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11877 16:43:45.292811 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6577 ms)
11878 16:43:45.355059 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11880 16:43:45.357883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11881 16:43:45.367292 [----------] 120 tests from CaptureTests/SingleStream (370009 ms total)
11882 16:43:45.418496
11883 16:43:45.474344 [----------] Global test environment tear-down
11884 16:43:45.529841 [==========] 120 tests from 1 test suite ran. (370009 ms total)
11885 16:43:45.588949 <LAVA_SIGNAL_TESTSET STOP>
11886 16:43:45.589087 + set +x
11887 16:43:45.589353 Received signal: <TESTSET> STOP
11888 16:43:45.589456 Closing test_set CaptureTests/SingleStream
11889 16:43:45.596219 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14396170_1.6.2.3.1>
11890 16:43:45.596484 Received signal: <ENDRUN> 0_lc-compliance 14396170_1.6.2.3.1
11891 16:43:45.596588 Ending use of test pattern.
11892 16:43:45.596673 Ending test lava.0_lc-compliance (14396170_1.6.2.3.1), duration 371.87
11894 16:43:45.599088 <LAVA_TEST_RUNNER EXIT>
11895 16:43:45.599350 ok: lava_test_shell seems to have completed
11896 16:43:45.602718 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11897 16:43:45.602945 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11898 16:43:45.603055 end: 3 lava-test-retry (duration 00:06:13) [common]
11899 16:43:45.603166 start: 4 finalize (timeout 00:10:00) [common]
11900 16:43:45.603279 start: 4.1 power-off (timeout 00:00:30) [common]
11901 16:43:45.603509 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11902 16:43:47.670637 >> Command sent successfully.
11903 16:43:47.673704 Returned 0 in 2 seconds
11904 16:43:47.774015 end: 4.1 power-off (duration 00:00:02) [common]
11906 16:43:47.774399 start: 4.2 read-feedback (timeout 00:09:58) [common]
11907 16:43:47.774664 Listened to connection for namespace 'common' for up to 1s
11908 16:43:48.775584 Finalising connection for namespace 'common'
11909 16:43:48.775723 Disconnecting from shell: Finalise
11910 16:43:48.775794 / #
11911 16:43:48.876020 end: 4.2 read-feedback (duration 00:00:01) [common]
11912 16:43:48.876200 end: 4 finalize (duration 00:00:03) [common]
11913 16:43:48.876321 Cleaning after the job
11914 16:43:48.876419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/ramdisk
11915 16:43:48.878586 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/kernel
11916 16:43:48.889543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/dtb
11917 16:43:48.889787 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/nfsrootfs
11918 16:43:48.930552 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396170/tftp-deploy-it2kh7ii/modules
11919 16:43:48.936408 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396170
11920 16:43:49.199498 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396170
11921 16:43:49.199675 Job finished correctly