Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 16:28:56.154856 lava-dispatcher, installed at version: 2024.03
2 16:28:56.155061 start: 0 validate
3 16:28:56.155196 Start time: 2024-06-17 16:28:56.155187+00:00 (UTC)
4 16:28:56.155311 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:28:56.155439 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 16:28:56.430954 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:28:56.431205 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:30:03.995103 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:30:03.995267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:30:04.259129 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:30:04.259288 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:30:04.523736 validate duration: 68.37
14 16:30:04.524013 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:30:04.524120 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:30:04.524219 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:30:04.524350 Not decompressing ramdisk as can be used compressed.
18 16:30:04.524437 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 16:30:04.524502 saving as /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/ramdisk/rootfs.cpio.gz
20 16:30:04.524574 total size: 28105535 (26 MB)
21 16:30:04.780587 progress 0 % (0 MB)
22 16:30:04.788194 progress 5 % (1 MB)
23 16:30:04.795677 progress 10 % (2 MB)
24 16:30:04.803097 progress 15 % (4 MB)
25 16:30:04.810505 progress 20 % (5 MB)
26 16:30:04.818018 progress 25 % (6 MB)
27 16:30:04.825480 progress 30 % (8 MB)
28 16:30:04.833194 progress 35 % (9 MB)
29 16:30:04.840737 progress 40 % (10 MB)
30 16:30:04.847897 progress 45 % (12 MB)
31 16:30:04.855379 progress 50 % (13 MB)
32 16:30:04.862860 progress 55 % (14 MB)
33 16:30:04.870390 progress 60 % (16 MB)
34 16:30:04.877778 progress 65 % (17 MB)
35 16:30:04.885008 progress 70 % (18 MB)
36 16:30:04.892406 progress 75 % (20 MB)
37 16:30:04.899986 progress 80 % (21 MB)
38 16:30:04.907458 progress 85 % (22 MB)
39 16:30:04.914902 progress 90 % (24 MB)
40 16:30:04.922134 progress 95 % (25 MB)
41 16:30:04.929294 progress 100 % (26 MB)
42 16:30:04.929551 26 MB downloaded in 0.40 s (66.19 MB/s)
43 16:30:04.929704 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:30:04.929947 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:30:04.930034 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:30:04.930120 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:30:04.930259 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:30:04.930329 saving as /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/kernel/Image
50 16:30:04.930390 total size: 54813184 (52 MB)
51 16:30:04.930453 No compression specified
52 16:30:04.931740 progress 0 % (0 MB)
53 16:30:04.946466 progress 5 % (2 MB)
54 16:30:04.961053 progress 10 % (5 MB)
55 16:30:04.975672 progress 15 % (7 MB)
56 16:30:04.990251 progress 20 % (10 MB)
57 16:30:05.005156 progress 25 % (13 MB)
58 16:30:05.019196 progress 30 % (15 MB)
59 16:30:05.033616 progress 35 % (18 MB)
60 16:30:05.047808 progress 40 % (20 MB)
61 16:30:05.061833 progress 45 % (23 MB)
62 16:30:05.075962 progress 50 % (26 MB)
63 16:30:05.090156 progress 55 % (28 MB)
64 16:30:05.104250 progress 60 % (31 MB)
65 16:30:05.118329 progress 65 % (34 MB)
66 16:30:05.132651 progress 70 % (36 MB)
67 16:30:05.146776 progress 75 % (39 MB)
68 16:30:05.160946 progress 80 % (41 MB)
69 16:30:05.174952 progress 85 % (44 MB)
70 16:30:05.189001 progress 90 % (47 MB)
71 16:30:05.202917 progress 95 % (49 MB)
72 16:30:05.217292 progress 100 % (52 MB)
73 16:30:05.217565 52 MB downloaded in 0.29 s (182.03 MB/s)
74 16:30:05.217782 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:30:05.218028 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:30:05.218123 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:30:05.218209 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:30:05.218363 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:30:05.218440 saving as /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/dtb/mt8192-asurada-spherion-r0.dtb
81 16:30:05.218504 total size: 47258 (0 MB)
82 16:30:05.218566 No compression specified
83 16:30:05.219810 progress 69 % (0 MB)
84 16:30:05.220116 progress 100 % (0 MB)
85 16:30:05.220279 0 MB downloaded in 0.00 s (25.43 MB/s)
86 16:30:05.220408 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:30:05.220635 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:30:05.220725 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:30:05.220823 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:30:05.220948 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:30:05.221018 saving as /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/modules/modules.tar
93 16:30:05.221080 total size: 8628772 (8 MB)
94 16:30:05.221142 Using unxz to decompress xz
95 16:30:05.225998 progress 0 % (0 MB)
96 16:30:05.248521 progress 5 % (0 MB)
97 16:30:05.274911 progress 10 % (0 MB)
98 16:30:05.300654 progress 15 % (1 MB)
99 16:30:05.326671 progress 20 % (1 MB)
100 16:30:05.353451 progress 25 % (2 MB)
101 16:30:05.378690 progress 30 % (2 MB)
102 16:30:05.407179 progress 35 % (2 MB)
103 16:30:05.434436 progress 40 % (3 MB)
104 16:30:05.460503 progress 45 % (3 MB)
105 16:30:05.487898 progress 50 % (4 MB)
106 16:30:05.513498 progress 55 % (4 MB)
107 16:30:05.541072 progress 60 % (4 MB)
108 16:30:05.569797 progress 65 % (5 MB)
109 16:30:05.596736 progress 70 % (5 MB)
110 16:30:05.621784 progress 75 % (6 MB)
111 16:30:05.647772 progress 80 % (6 MB)
112 16:30:05.678122 progress 85 % (7 MB)
113 16:30:05.709740 progress 90 % (7 MB)
114 16:30:05.737088 progress 95 % (7 MB)
115 16:30:05.762725 progress 100 % (8 MB)
116 16:30:05.767972 8 MB downloaded in 0.55 s (15.05 MB/s)
117 16:30:05.768266 end: 1.4.1 http-download (duration 00:00:01) [common]
119 16:30:05.768575 end: 1.4 download-retry (duration 00:00:01) [common]
120 16:30:05.768688 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:30:05.768816 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:30:05.768922 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:30:05.769060 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:30:05.769373 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg
125 16:30:05.769574 makedir: /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin
126 16:30:05.769732 makedir: /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/tests
127 16:30:05.769878 makedir: /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/results
128 16:30:05.770035 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-add-keys
129 16:30:05.770234 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-add-sources
130 16:30:05.770412 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-background-process-start
131 16:30:05.770593 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-background-process-stop
132 16:30:05.770769 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-common-functions
133 16:30:05.770943 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-echo-ipv4
134 16:30:05.771117 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-install-packages
135 16:30:05.771290 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-installed-packages
136 16:30:05.771463 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-os-build
137 16:30:05.771641 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-probe-channel
138 16:30:05.771817 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-probe-ip
139 16:30:05.771993 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-target-ip
140 16:30:05.772164 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-target-mac
141 16:30:05.772315 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-target-storage
142 16:30:05.772504 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-case
143 16:30:05.772683 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-event
144 16:30:05.772843 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-feedback
145 16:30:05.773019 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-raise
146 16:30:05.773196 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-reference
147 16:30:05.773374 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-runner
148 16:30:05.773522 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-set
149 16:30:05.773670 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-test-shell
150 16:30:05.773820 Updating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-install-packages (oe)
151 16:30:05.773995 Updating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/bin/lava-installed-packages (oe)
152 16:30:05.774140 Creating /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/environment
153 16:30:05.774293 LAVA metadata
154 16:30:05.774404 - LAVA_JOB_ID=14396112
155 16:30:05.774511 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:30:05.774670 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:30:05.774778 skipped lava-vland-overlay
158 16:30:05.774904 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:30:05.775030 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:30:05.775134 skipped lava-multinode-overlay
161 16:30:05.775255 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:30:05.775387 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:30:05.775504 Loading test definitions
164 16:30:05.775649 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:30:05.775762 Using /lava-14396112 at stage 0
166 16:30:05.776208 uuid=14396112_1.5.2.3.1 testdef=None
167 16:30:05.776337 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:30:05.776474 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:30:05.777824 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:30:05.778093 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:30:05.778759 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:30:05.779026 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:30:05.779852 runner path: /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/0/tests/0_v4l2-compliance-uvc test_uuid 14396112_1.5.2.3.1
176 16:30:05.780053 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:30:05.780308 Creating lava-test-runner.conf files
179 16:30:05.780419 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396112/lava-overlay-0jgre3jg/lava-14396112/0 for stage 0
180 16:30:05.780549 - 0_v4l2-compliance-uvc
181 16:30:05.780656 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:30:05.780745 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:30:05.787891 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:30:05.788029 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:30:05.788126 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:30:05.788218 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:30:05.788305 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:30:06.738335 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 16:30:06.738723 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 16:30:06.738845 extracting modules file /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396112/extract-overlay-ramdisk-6i82x98k/ramdisk
191 16:30:06.985424 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:30:06.985595 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 16:30:06.985692 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396112/compress-overlay-re2mq38t/overlay-1.5.2.4.tar.gz to ramdisk
194 16:30:06.985768 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396112/compress-overlay-re2mq38t/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396112/extract-overlay-ramdisk-6i82x98k/ramdisk
195 16:30:06.992695 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:30:06.992879 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 16:30:06.993005 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:30:06.993124 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 16:30:06.993238 Building ramdisk /var/lib/lava/dispatcher/tmp/14396112/extract-overlay-ramdisk-6i82x98k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396112/extract-overlay-ramdisk-6i82x98k/ramdisk
200 16:30:07.766953 >> 276012 blocks
201 16:30:12.035489 rename /var/lib/lava/dispatcher/tmp/14396112/extract-overlay-ramdisk-6i82x98k/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/ramdisk/ramdisk.cpio.gz
202 16:30:12.036025 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 16:30:12.036187 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 16:30:12.036318 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 16:30:12.036467 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/kernel/Image']
206 16:30:27.396410 Returned 0 in 15 seconds
207 16:30:27.497074 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/kernel/image.itb
208 16:30:28.117502 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:30:28.117891 output: Created: Mon Jun 17 17:30:27 2024
210 16:30:28.117972 output: Image 0 (kernel-1)
211 16:30:28.118069 output: Description:
212 16:30:28.118210 output: Created: Mon Jun 17 17:30:27 2024
213 16:30:28.118310 output: Type: Kernel Image
214 16:30:28.118407 output: Compression: lzma compressed
215 16:30:28.118471 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
216 16:30:28.118533 output: Architecture: AArch64
217 16:30:28.118594 output: OS: Linux
218 16:30:28.118657 output: Load Address: 0x00000000
219 16:30:28.118736 output: Entry Point: 0x00000000
220 16:30:28.118798 output: Hash algo: crc32
221 16:30:28.118858 output: Hash value: 106ffd6f
222 16:30:28.118912 output: Image 1 (fdt-1)
223 16:30:28.118967 output: Description: mt8192-asurada-spherion-r0
224 16:30:28.119023 output: Created: Mon Jun 17 17:30:27 2024
225 16:30:28.119078 output: Type: Flat Device Tree
226 16:30:28.119132 output: Compression: uncompressed
227 16:30:28.119186 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 16:30:28.119258 output: Architecture: AArch64
229 16:30:28.119314 output: Hash algo: crc32
230 16:30:28.119368 output: Hash value: 0f8e4d2e
231 16:30:28.119422 output: Image 2 (ramdisk-1)
232 16:30:28.119475 output: Description: unavailable
233 16:30:28.119528 output: Created: Mon Jun 17 17:30:27 2024
234 16:30:28.119582 output: Type: RAMDisk Image
235 16:30:28.119635 output: Compression: Unknown Compression
236 16:30:28.119690 output: Data Size: 41215903 Bytes = 40249.91 KiB = 39.31 MiB
237 16:30:28.119762 output: Architecture: AArch64
238 16:30:28.119823 output: OS: Linux
239 16:30:28.119877 output: Load Address: unavailable
240 16:30:28.119931 output: Entry Point: unavailable
241 16:30:28.119985 output: Hash algo: crc32
242 16:30:28.120038 output: Hash value: cee977da
243 16:30:28.120092 output: Default Configuration: 'conf-1'
244 16:30:28.120145 output: Configuration 0 (conf-1)
245 16:30:28.120199 output: Description: mt8192-asurada-spherion-r0
246 16:30:28.120252 output: Kernel: kernel-1
247 16:30:28.120305 output: Init Ramdisk: ramdisk-1
248 16:30:28.120359 output: FDT: fdt-1
249 16:30:28.120412 output: Loadables: kernel-1
250 16:30:28.120465 output:
251 16:30:28.120669 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 16:30:28.120766 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 16:30:28.120874 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 16:30:28.120971 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 16:30:28.121055 No LXC device requested
256 16:30:28.121137 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:30:28.121225 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 16:30:28.121326 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:30:28.121398 Checking files for TFTP limit of 4294967296 bytes.
260 16:30:28.121952 end: 1 tftp-deploy (duration 00:00:24) [common]
261 16:30:28.122089 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:30:28.122219 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:30:28.122384 substitutions:
264 16:30:28.122504 - {DTB}: 14396112/tftp-deploy-jkkpexh5/dtb/mt8192-asurada-spherion-r0.dtb
265 16:30:28.122647 - {INITRD}: 14396112/tftp-deploy-jkkpexh5/ramdisk/ramdisk.cpio.gz
266 16:30:28.122731 - {KERNEL}: 14396112/tftp-deploy-jkkpexh5/kernel/Image
267 16:30:28.122792 - {LAVA_MAC}: None
268 16:30:28.122883 - {PRESEED_CONFIG}: None
269 16:30:28.122971 - {PRESEED_LOCAL}: None
270 16:30:28.123051 - {RAMDISK}: 14396112/tftp-deploy-jkkpexh5/ramdisk/ramdisk.cpio.gz
271 16:30:28.123139 - {ROOT_PART}: None
272 16:30:28.123219 - {ROOT}: None
273 16:30:28.123280 - {SERVER_IP}: 192.168.201.1
274 16:30:28.123336 - {TEE}: None
275 16:30:28.123391 Parsed boot commands:
276 16:30:28.123445 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:30:28.123630 Parsed boot commands: tftpboot 192.168.201.1 14396112/tftp-deploy-jkkpexh5/kernel/image.itb 14396112/tftp-deploy-jkkpexh5/kernel/cmdline
278 16:30:28.123724 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:30:28.123814 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:30:28.123908 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:30:28.123994 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:30:28.124066 Not connected, no need to disconnect.
283 16:30:28.124140 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:30:28.124222 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:30:28.124290 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 16:30:28.128323 Setting prompt string to ['lava-test: # ']
287 16:30:28.128728 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:30:28.128855 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:30:28.128961 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:30:28.129056 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:30:28.129246 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 16:30:41.765738 Returned 0 in 13 seconds
293 16:30:41.866446 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 16:30:41.867134 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 16:30:41.867276 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 16:30:41.867401 Setting prompt string to 'Starting depthcharge on Spherion...'
298 16:30:41.867503 Changing prompt to 'Starting depthcharge on Spherion...'
299 16:30:41.867605 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 16:30:41.868165 [Enter `^Ec?' for help]
301 16:30:41.868280
302 16:30:41.868376
303 16:30:41.868469 F0: 102B 0000
304 16:30:41.868564
305 16:30:41.868662 F3: 1001 0000 [0200]
306 16:30:41.868760
307 16:30:41.868855 F3: 1001 0000
308 16:30:41.868951
309 16:30:41.869043 F7: 102D 0000
310 16:30:41.869134
311 16:30:41.869224 F1: 0000 0000
312 16:30:41.869326
313 16:30:41.869417 V0: 0000 0000 [0001]
314 16:30:41.869509
315 16:30:41.869600 00: 0007 8000
316 16:30:41.869696
317 16:30:41.869786 01: 0000 0000
318 16:30:41.869878
319 16:30:41.869967 BP: 0C00 0209 [0000]
320 16:30:41.870057
321 16:30:41.870145 G0: 1182 0000
322 16:30:41.870235
323 16:30:41.870324 EC: 0000 0021 [4000]
324 16:30:41.870417
325 16:30:41.870510 S7: 0000 0000 [0000]
326 16:30:41.870601
327 16:30:41.870692 CC: 0000 0000 [0001]
328 16:30:41.870782
329 16:30:41.870872 T0: 0000 0040 [010F]
330 16:30:41.870963
331 16:30:41.871051 Jump to BL
332 16:30:41.871140
333 16:30:41.871229
334 16:30:41.871316
335 16:30:41.871407 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 16:30:41.871501 ARM64: Exception handlers installed.
337 16:30:41.871592 ARM64: Testing exception
338 16:30:41.871682 ARM64: Done test exception
339 16:30:41.871771 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 16:30:41.871861 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 16:30:41.871953 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 16:30:41.872044 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 16:30:41.872136 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 16:30:41.872228 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 16:30:41.872320 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 16:30:41.872411 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 16:30:41.872503 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 16:30:41.872594 WDT: Last reset was cold boot
349 16:30:41.872685 SPI1(PAD0) initialized at 2873684 Hz
350 16:30:41.872775 SPI5(PAD0) initialized at 992727 Hz
351 16:30:41.872865 VBOOT: Loading verstage.
352 16:30:41.872955 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 16:30:41.873046 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 16:30:41.873137 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 16:30:41.873229 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 16:30:41.873327 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 16:30:41.873420 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 16:30:41.873511 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 16:30:41.873601
360 16:30:41.873689
361 16:30:41.873782 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 16:30:41.873874 ARM64: Exception handlers installed.
363 16:30:41.873964 ARM64: Testing exception
364 16:30:41.874055 ARM64: Done test exception
365 16:30:41.874145 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 16:30:41.874236 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 16:30:41.874327 Probing TPM: . done!
368 16:30:41.874418 TPM ready after 0 ms
369 16:30:41.874508 Connected to device vid:did:rid of 1ae0:0028:00
370 16:30:41.874601 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 16:30:41.874695 Initialized TPM device CR50 revision 0
372 16:30:41.874786 tlcl_send_startup: Startup return code is 0
373 16:30:41.874877 TPM: setup succeeded
374 16:30:41.874968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 16:30:41.875058 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 16:30:41.875148 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 16:30:41.875241 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:30:41.875332 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 16:30:41.875423 in-header: 03 07 00 00 08 00 00 00
380 16:30:41.875513 in-data: aa e4 47 04 13 02 00 00
381 16:30:41.875603 Chrome EC: UHEPI supported
382 16:30:41.875695 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 16:30:41.875787 in-header: 03 a9 00 00 08 00 00 00
384 16:30:41.875877 in-data: 84 60 60 08 00 00 00 00
385 16:30:41.875967 Phase 1
386 16:30:41.876057 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 16:30:41.876149 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 16:30:41.876241 VB2:vb2_check_recovery() Recovery was requested manually
389 16:30:41.876333 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 16:30:41.876424 Recovery requested (1009000e)
391 16:30:41.876519 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 16:30:41.876612 tlcl_extend: response is 0
393 16:30:41.876703 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 16:30:41.876794 tlcl_extend: response is 0
395 16:30:41.876885 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 16:30:41.876976 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 16:30:41.877069 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 16:30:41.877160
399 16:30:41.877249
400 16:30:41.877345 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 16:30:41.877438 ARM64: Exception handlers installed.
402 16:30:41.877528 ARM64: Testing exception
403 16:30:41.877618 ARM64: Done test exception
404 16:30:41.877709 pmic_efuse_setting: Set efuses in 11 msecs
405 16:30:41.877800 pmwrap_interface_init: Select PMIF_VLD_RDY
406 16:30:41.877891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 16:30:41.877983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 16:30:41.878281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 16:30:41.878389 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 16:30:41.878484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 16:30:41.878577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 16:30:41.878671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 16:30:41.878762 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 16:30:41.878853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 16:30:41.878945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 16:30:41.879037 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 16:30:41.879127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 16:30:41.879219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 16:30:41.879310 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 16:30:41.879402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 16:30:41.879493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 16:30:41.879584 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 16:30:41.879676 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 16:30:41.879769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 16:30:41.879861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 16:30:41.879953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 16:30:41.880044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 16:30:41.880136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 16:30:41.880227 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 16:30:41.880317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 16:30:41.880408 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 16:30:41.880499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 16:30:41.880590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 16:30:41.880682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 16:30:41.880773 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 16:30:41.880864 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 16:30:41.880957 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 16:30:41.881048 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 16:30:41.881140 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 16:30:41.881231 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 16:30:41.881332 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 16:30:41.881424 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 16:30:41.881517 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 16:30:41.881607 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 16:30:41.881698 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 16:30:41.881789 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 16:30:41.881880 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 16:30:41.881971 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 16:30:41.882062 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 16:30:41.882154 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 16:30:41.882245 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 16:30:41.882341 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 16:30:41.882433 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 16:30:41.882524 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 16:30:41.882615 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 16:30:41.882707 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 16:30:41.882799 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 16:30:41.882891 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 16:30:41.882984 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 16:30:41.883081 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 16:30:41.883176 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 16:30:41.883270 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 16:30:41.883362 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 16:30:41.883455 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:30:41.883547 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
466 16:30:41.883638 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 16:30:41.883731 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 16:30:41.883823 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 16:30:41.883914 [RTC]rtc_get_frequency_meter,154: input=15, output=853
470 16:30:41.884005 [RTC]rtc_get_frequency_meter,154: input=7, output=726
471 16:30:41.884097 [RTC]rtc_get_frequency_meter,154: input=11, output=789
472 16:30:41.884190 [RTC]rtc_get_frequency_meter,154: input=13, output=822
473 16:30:41.884282 [RTC]rtc_get_frequency_meter,154: input=12, output=806
474 16:30:41.884374 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 16:30:41.884466 [RTC]rtc_get_frequency_meter,154: input=12, output=805
476 16:30:41.884557 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 16:30:41.884649 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 16:30:41.884942 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 16:30:41.885047 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 16:30:41.885141 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 16:30:41.885235 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 16:30:41.885342 ADC[4]: Raw value=904802 ID=7
483 16:30:41.885435 ADC[3]: Raw value=213916 ID=1
484 16:30:41.885528 RAM Code: 0x71
485 16:30:41.885619 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 16:30:41.885712 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 16:30:41.885805 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 16:30:41.885898 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 16:30:41.885989 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 16:30:41.886080 in-header: 03 07 00 00 08 00 00 00
491 16:30:41.886171 in-data: aa e4 47 04 13 02 00 00
492 16:30:41.886263 Chrome EC: UHEPI supported
493 16:30:41.886355 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 16:30:41.886448 in-header: 03 a9 00 00 08 00 00 00
495 16:30:41.886539 in-data: 84 60 60 08 00 00 00 00
496 16:30:41.886630 MRC: failed to locate region type 0.
497 16:30:41.886721 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 16:30:41.886814 DRAM-K: Running full calibration
499 16:30:41.886906 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 16:30:41.886998 header.status = 0x0
501 16:30:41.887091 header.version = 0x6 (expected: 0x6)
502 16:30:41.887182 header.size = 0xd00 (expected: 0xd00)
503 16:30:41.887273 header.flags = 0x0
504 16:30:41.887365 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 16:30:41.887456 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 16:30:41.887548 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 16:30:41.887640 dram_init: ddr_geometry: 2
508 16:30:41.887730 [EMI] MDL number = 2
509 16:30:41.887821 [EMI] Get MDL freq = 0
510 16:30:41.887912 dram_init: ddr_type: 0
511 16:30:41.888003 is_discrete_lpddr4: 1
512 16:30:41.888093 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 16:30:41.888184
514 16:30:41.888273
515 16:30:41.888362 [Bian_co] ETT version 0.0.0.1
516 16:30:41.888453 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 16:30:41.888543
518 16:30:41.888633 dramc_set_vcore_voltage set vcore to 650000
519 16:30:41.888724 Read voltage for 800, 4
520 16:30:41.888814 Vio18 = 0
521 16:30:41.888905 Vcore = 650000
522 16:30:41.888996 Vdram = 0
523 16:30:41.889086 Vddq = 0
524 16:30:41.889176 Vmddr = 0
525 16:30:41.889273 dram_init: config_dvfs: 1
526 16:30:41.889365 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 16:30:41.889458 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 16:30:41.889551 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 16:30:41.889641 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 16:30:41.889731 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 16:30:41.889821 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 16:30:41.889912 MEM_TYPE=3, freq_sel=18
533 16:30:41.890002 sv_algorithm_assistance_LP4_1600
534 16:30:41.890090 ============ PULL DRAM RESETB DOWN ============
535 16:30:41.890182 ========== PULL DRAM RESETB DOWN end =========
536 16:30:41.890276 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 16:30:41.890369 ===================================
538 16:30:41.890459 LPDDR4 DRAM CONFIGURATION
539 16:30:41.890548 ===================================
540 16:30:41.890639 EX_ROW_EN[0] = 0x0
541 16:30:41.890729 EX_ROW_EN[1] = 0x0
542 16:30:41.890820 LP4Y_EN = 0x0
543 16:30:41.890909 WORK_FSP = 0x0
544 16:30:41.890998 WL = 0x2
545 16:30:41.891088 RL = 0x2
546 16:30:41.891176 BL = 0x2
547 16:30:41.891265 RPST = 0x0
548 16:30:41.891354 RD_PRE = 0x0
549 16:30:41.891444 WR_PRE = 0x1
550 16:30:41.891533 WR_PST = 0x0
551 16:30:41.891622 DBI_WR = 0x0
552 16:30:41.891713 DBI_RD = 0x0
553 16:30:41.891802 OTF = 0x1
554 16:30:41.891893 ===================================
555 16:30:41.891984 ===================================
556 16:30:41.892074 ANA top config
557 16:30:41.892163 ===================================
558 16:30:41.892252 DLL_ASYNC_EN = 0
559 16:30:41.892343 ALL_SLAVE_EN = 1
560 16:30:41.892433 NEW_RANK_MODE = 1
561 16:30:41.892525 DLL_IDLE_MODE = 1
562 16:30:41.892616 LP45_APHY_COMB_EN = 1
563 16:30:41.892709 TX_ODT_DIS = 1
564 16:30:41.892799 NEW_8X_MODE = 1
565 16:30:41.892891 ===================================
566 16:30:41.892982 ===================================
567 16:30:41.893073 data_rate = 1600
568 16:30:41.893165 CKR = 1
569 16:30:41.893255 DQ_P2S_RATIO = 8
570 16:30:41.893354 ===================================
571 16:30:41.893446 CA_P2S_RATIO = 8
572 16:30:41.893536 DQ_CA_OPEN = 0
573 16:30:41.893627 DQ_SEMI_OPEN = 0
574 16:30:41.893716 CA_SEMI_OPEN = 0
575 16:30:41.893806 CA_FULL_RATE = 0
576 16:30:41.893895 DQ_CKDIV4_EN = 1
577 16:30:41.893984 CA_CKDIV4_EN = 1
578 16:30:41.894073 CA_PREDIV_EN = 0
579 16:30:41.894163 PH8_DLY = 0
580 16:30:41.894253 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 16:30:41.894344 DQ_AAMCK_DIV = 4
582 16:30:41.894434 CA_AAMCK_DIV = 4
583 16:30:41.894524 CA_ADMCK_DIV = 4
584 16:30:41.894612 DQ_TRACK_CA_EN = 0
585 16:30:41.894702 CA_PICK = 800
586 16:30:41.894790 CA_MCKIO = 800
587 16:30:41.894879 MCKIO_SEMI = 0
588 16:30:41.894970 PLL_FREQ = 3068
589 16:30:41.895060 DQ_UI_PI_RATIO = 32
590 16:30:41.895149 CA_UI_PI_RATIO = 0
591 16:30:41.895238 ===================================
592 16:30:41.895329 ===================================
593 16:30:41.895418 memory_type:LPDDR4
594 16:30:41.895509 GP_NUM : 10
595 16:30:41.895600 SRAM_EN : 1
596 16:30:41.895692 MD32_EN : 0
597 16:30:41.895782 ===================================
598 16:30:41.896096 [ANA_INIT] >>>>>>>>>>>>>>
599 16:30:41.896199 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 16:30:41.896297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 16:30:41.896390 ===================================
602 16:30:41.896482 data_rate = 1600,PCW = 0X7600
603 16:30:41.896573 ===================================
604 16:30:41.896665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 16:30:41.896757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 16:30:41.896852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 16:30:41.896945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 16:30:41.897035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 16:30:41.897126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 16:30:41.897216 [ANA_INIT] flow start
611 16:30:41.897316 [ANA_INIT] PLL >>>>>>>>
612 16:30:41.897407 [ANA_INIT] PLL <<<<<<<<
613 16:30:41.897498 [ANA_INIT] MIDPI >>>>>>>>
614 16:30:41.897588 [ANA_INIT] MIDPI <<<<<<<<
615 16:30:41.897679 [ANA_INIT] DLL >>>>>>>>
616 16:30:41.897770 [ANA_INIT] flow end
617 16:30:41.897862 ============ LP4 DIFF to SE enter ============
618 16:30:41.897954 ============ LP4 DIFF to SE exit ============
619 16:30:41.898044 [ANA_INIT] <<<<<<<<<<<<<
620 16:30:41.898136 [Flow] Enable top DCM control >>>>>
621 16:30:41.898227 [Flow] Enable top DCM control <<<<<
622 16:30:41.898318 Enable DLL master slave shuffle
623 16:30:41.898408 ==============================================================
624 16:30:41.898500 Gating Mode config
625 16:30:41.898590 ==============================================================
626 16:30:41.898681 Config description:
627 16:30:41.898770 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 16:30:41.898862 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 16:30:41.898953 SELPH_MODE 0: By rank 1: By Phase
630 16:30:41.899044 ==============================================================
631 16:30:41.899134 GAT_TRACK_EN = 1
632 16:30:41.899224 RX_GATING_MODE = 2
633 16:30:41.899314 RX_GATING_TRACK_MODE = 2
634 16:30:41.899404 SELPH_MODE = 1
635 16:30:41.899493 PICG_EARLY_EN = 1
636 16:30:41.899582 VALID_LAT_VALUE = 1
637 16:30:41.899671 ==============================================================
638 16:30:41.899762 Enter into Gating configuration >>>>
639 16:30:41.899851 Exit from Gating configuration <<<<
640 16:30:41.899941 Enter into DVFS_PRE_config >>>>>
641 16:30:41.900031 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 16:30:41.900124 Exit from DVFS_PRE_config <<<<<
643 16:30:41.900215 Enter into PICG configuration >>>>
644 16:30:41.900305 Exit from PICG configuration <<<<
645 16:30:41.900394 [RX_INPUT] configuration >>>>>
646 16:30:41.900483 [RX_INPUT] configuration <<<<<
647 16:30:41.900572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 16:30:41.900662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 16:30:41.900751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 16:30:41.900842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 16:30:41.900932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 16:30:41.901023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 16:30:41.901113 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 16:30:41.901203 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 16:30:41.901371 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 16:30:41.901462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 16:30:41.901530 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 16:30:41.901592 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 16:30:41.901653 ===================================
660 16:30:41.901712 LPDDR4 DRAM CONFIGURATION
661 16:30:41.901769 ===================================
662 16:30:41.901826 EX_ROW_EN[0] = 0x0
663 16:30:41.901881 EX_ROW_EN[1] = 0x0
664 16:30:41.901937 LP4Y_EN = 0x0
665 16:30:41.901992 WORK_FSP = 0x0
666 16:30:41.902047 WL = 0x2
667 16:30:41.902102 RL = 0x2
668 16:30:41.902158 BL = 0x2
669 16:30:41.902212 RPST = 0x0
670 16:30:41.902266 RD_PRE = 0x0
671 16:30:41.902320 WR_PRE = 0x1
672 16:30:41.902374 WR_PST = 0x0
673 16:30:41.902428 DBI_WR = 0x0
674 16:30:41.902481 DBI_RD = 0x0
675 16:30:41.902535 OTF = 0x1
676 16:30:41.902590 ===================================
677 16:30:41.902645 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 16:30:41.902700 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 16:30:41.902754 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 16:30:41.902808 ===================================
681 16:30:41.902862 LPDDR4 DRAM CONFIGURATION
682 16:30:41.902915 ===================================
683 16:30:41.902969 EX_ROW_EN[0] = 0x10
684 16:30:41.903023 EX_ROW_EN[1] = 0x0
685 16:30:41.903077 LP4Y_EN = 0x0
686 16:30:41.903131 WORK_FSP = 0x0
687 16:30:41.903184 WL = 0x2
688 16:30:41.903248 RL = 0x2
689 16:30:41.903305 BL = 0x2
690 16:30:41.903359 RPST = 0x0
691 16:30:41.903413 RD_PRE = 0x0
692 16:30:41.903467 WR_PRE = 0x1
693 16:30:41.903523 WR_PST = 0x0
694 16:30:41.903577 DBI_WR = 0x0
695 16:30:41.903630 DBI_RD = 0x0
696 16:30:41.903683 OTF = 0x1
697 16:30:41.903738 ===================================
698 16:30:41.903793 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 16:30:41.903848 nWR fixed to 40
700 16:30:41.903903 [ModeRegInit_LP4] CH0 RK0
701 16:30:41.903957 [ModeRegInit_LP4] CH0 RK1
702 16:30:41.904019 [ModeRegInit_LP4] CH1 RK0
703 16:30:41.904111 [ModeRegInit_LP4] CH1 RK1
704 16:30:41.904207 match AC timing 13
705 16:30:41.904297 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 16:30:41.904592 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 16:30:41.904665 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 16:30:41.904728 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 16:30:41.904788 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 16:30:41.904845 [EMI DOE] emi_dcm 0
711 16:30:41.904901 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 16:30:41.904958 ==
713 16:30:41.905013 Dram Type= 6, Freq= 0, CH_0, rank 0
714 16:30:41.905068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 16:30:41.905124 ==
716 16:30:41.905178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 16:30:41.905233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 16:30:41.905300 [CA 0] Center 37 (7~68) winsize 62
719 16:30:41.905355 [CA 1] Center 37 (7~68) winsize 62
720 16:30:41.905410 [CA 2] Center 34 (4~65) winsize 62
721 16:30:41.905464 [CA 3] Center 34 (4~65) winsize 62
722 16:30:41.905518 [CA 4] Center 33 (3~64) winsize 62
723 16:30:41.905571 [CA 5] Center 33 (3~64) winsize 62
724 16:30:41.905625
725 16:30:41.905679 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 16:30:41.905733
727 16:30:41.905786 [CATrainingPosCal] consider 1 rank data
728 16:30:41.905840 u2DelayCellTimex100 = 270/100 ps
729 16:30:41.905894 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 16:30:41.905960 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 16:30:41.906013 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 16:30:41.906067 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 16:30:41.906120 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 16:30:41.906172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 16:30:41.906225
736 16:30:41.906277 CA PerBit enable=1, Macro0, CA PI delay=33
737 16:30:41.906330
738 16:30:41.906383 [CBTSetCACLKResult] CA Dly = 33
739 16:30:41.906436 CS Dly: 5 (0~36)
740 16:30:41.906488 ==
741 16:30:41.906541 Dram Type= 6, Freq= 0, CH_0, rank 1
742 16:30:41.906594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 16:30:41.906647 ==
744 16:30:41.906700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 16:30:41.906753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 16:30:41.906806 [CA 0] Center 38 (7~69) winsize 63
747 16:30:41.906859 [CA 1] Center 37 (7~68) winsize 62
748 16:30:41.906911 [CA 2] Center 35 (5~66) winsize 62
749 16:30:41.906963 [CA 3] Center 35 (4~66) winsize 63
750 16:30:41.907016 [CA 4] Center 34 (3~65) winsize 63
751 16:30:41.907068 [CA 5] Center 33 (3~64) winsize 62
752 16:30:41.907121
753 16:30:41.907173 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 16:30:41.907226
755 16:30:41.907278 [CATrainingPosCal] consider 2 rank data
756 16:30:41.907331 u2DelayCellTimex100 = 270/100 ps
757 16:30:41.907422 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 16:30:41.907507 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 16:30:41.907593 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
760 16:30:41.907678 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 16:30:41.907737 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 16:30:41.907794 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 16:30:41.907848
764 16:30:41.907903 CA PerBit enable=1, Macro0, CA PI delay=33
765 16:30:41.907957
766 16:30:41.908010 [CBTSetCACLKResult] CA Dly = 33
767 16:30:41.908063 CS Dly: 6 (0~38)
768 16:30:41.908116
769 16:30:41.908169 ----->DramcWriteLeveling(PI) begin...
770 16:30:41.908227 ==
771 16:30:41.908280 Dram Type= 6, Freq= 0, CH_0, rank 0
772 16:30:41.908334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 16:30:41.908388 ==
774 16:30:41.908441 Write leveling (Byte 0): 30 => 30
775 16:30:41.908495 Write leveling (Byte 1): 29 => 29
776 16:30:41.908551 DramcWriteLeveling(PI) end<-----
777 16:30:41.908604
778 16:30:41.908657 ==
779 16:30:41.908709 Dram Type= 6, Freq= 0, CH_0, rank 0
780 16:30:41.908761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 16:30:41.908814 ==
782 16:30:41.908867 [Gating] SW mode calibration
783 16:30:41.908920 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 16:30:41.908973 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 16:30:41.909026 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 16:30:41.909080 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 16:30:41.909133 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 16:30:41.909186 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 16:30:41.909239 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:30:41.909333 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:30:41.909387 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:30:41.909440 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:30:41.909493 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 16:30:41.909546 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 16:30:41.909599 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 16:30:41.909651 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 16:30:41.909705 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 16:30:41.909758 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 16:30:41.909810 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 16:30:41.909862 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 16:30:41.909915 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 16:30:41.909967 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 16:30:41.910020 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 16:30:41.910080 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 16:30:41.910151 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 16:30:41.910205 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 16:30:41.910260 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 16:30:41.910313 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 16:30:41.910367 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 16:30:41.910419 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 16:30:41.910472 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
812 16:30:41.910525 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
813 16:30:41.910578 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 16:30:41.910825 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 16:30:41.910884 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 16:30:41.910938 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 16:30:41.910990 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
818 16:30:41.911105 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
819 16:30:41.911192 0 10 8 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 0)
820 16:30:41.911284 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
821 16:30:41.911373 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 16:30:41.911458 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 16:30:41.911535 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 16:30:41.911593 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 16:30:41.911649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 16:30:41.911704 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
827 16:30:41.911758 0 11 8 | B1->B0 | 2525 4343 | 1 0 | (0 0) (0 0)
828 16:30:41.911812 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
829 16:30:41.911865 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 16:30:41.911918 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 16:30:41.911971 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 16:30:41.912024 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 16:30:41.912077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 16:30:41.912130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 16:30:41.912183 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 16:30:41.912236 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 16:30:41.912289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 16:30:41.912342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 16:30:41.912394 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 16:30:41.912448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 16:30:41.912501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 16:30:41.912554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 16:30:41.912606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 16:30:41.912659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 16:30:41.912715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 16:30:41.912768 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 16:30:41.912821 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 16:30:41.912874 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 16:30:41.912927 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 16:30:41.912980 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 16:30:41.913047 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 16:30:41.913113 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 16:30:41.913166 Total UI for P1: 0, mck2ui 16
854 16:30:41.913220 best dqsien dly found for B0: ( 0, 14, 6)
855 16:30:41.913315 Total UI for P1: 0, mck2ui 16
856 16:30:41.913370 best dqsien dly found for B1: ( 0, 14, 8)
857 16:30:41.913424 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 16:30:41.913477 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 16:30:41.913530
860 16:30:41.913582 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 16:30:41.913635 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 16:30:41.913688 [Gating] SW calibration Done
863 16:30:41.913741 ==
864 16:30:41.913793 Dram Type= 6, Freq= 0, CH_0, rank 0
865 16:30:41.913846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 16:30:41.913899 ==
867 16:30:41.913952 RX Vref Scan: 0
868 16:30:41.914004
869 16:30:41.914057 RX Vref 0 -> 0, step: 1
870 16:30:41.914109
871 16:30:41.914162 RX Delay -130 -> 252, step: 16
872 16:30:41.914214 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 16:30:41.914267 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 16:30:41.914325 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 16:30:41.914415 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 16:30:41.914501 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 16:30:41.916404 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 16:30:41.916487 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 16:30:41.916552 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 16:30:41.916613 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 16:30:41.916670 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 16:30:41.916726 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 16:30:41.916781 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 16:30:41.916835 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 16:30:41.916888 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 16:30:41.916955 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 16:30:41.917029 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 16:30:41.917082 ==
889 16:30:41.917135 Dram Type= 6, Freq= 0, CH_0, rank 0
890 16:30:41.917206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 16:30:41.917308 ==
892 16:30:41.917365 DQS Delay:
893 16:30:41.917418 DQS0 = 0, DQS1 = 0
894 16:30:41.917471 DQM Delay:
895 16:30:41.917524 DQM0 = 88, DQM1 = 76
896 16:30:41.917577 DQ Delay:
897 16:30:41.917630 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 16:30:41.917683 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 16:30:41.917735 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
900 16:30:41.917788 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 16:30:41.917840
902 16:30:41.917892
903 16:30:41.917943 ==
904 16:30:41.918067 Dram Type= 6, Freq= 0, CH_0, rank 0
905 16:30:41.918166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 16:30:41.918308 ==
907 16:30:41.918419
908 16:30:41.918518
909 16:30:41.918618 TX Vref Scan disable
910 16:30:41.918675 == TX Byte 0 ==
911 16:30:41.918744 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 16:30:41.918798 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 16:30:41.918851 == TX Byte 1 ==
914 16:30:41.918903 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 16:30:41.918957 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 16:30:41.919013 ==
917 16:30:41.919066 Dram Type= 6, Freq= 0, CH_0, rank 0
918 16:30:41.919118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 16:30:41.919171 ==
920 16:30:41.919224 TX Vref=22, minBit 0, minWin=27, winSum=441
921 16:30:41.919276 TX Vref=24, minBit 1, minWin=27, winSum=444
922 16:30:41.919536 TX Vref=26, minBit 1, minWin=27, winSum=447
923 16:30:41.919595 TX Vref=28, minBit 2, minWin=27, winSum=450
924 16:30:41.919648 TX Vref=30, minBit 0, minWin=28, winSum=455
925 16:30:41.919702 TX Vref=32, minBit 1, minWin=27, winSum=452
926 16:30:41.919754 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
927 16:30:41.919807
928 16:30:41.919867 Final TX Range 1 Vref 30
929 16:30:41.919921
930 16:30:41.919973 ==
931 16:30:41.920025 Dram Type= 6, Freq= 0, CH_0, rank 0
932 16:30:41.920078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 16:30:41.920130 ==
934 16:30:41.920182
935 16:30:41.920233
936 16:30:41.920308 TX Vref Scan disable
937 16:30:41.920376 == TX Byte 0 ==
938 16:30:41.920430 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 16:30:41.920484 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 16:30:41.920537 == TX Byte 1 ==
941 16:30:41.920589 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 16:30:41.920642 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 16:30:41.920698
944 16:30:41.920751 [DATLAT]
945 16:30:41.920804 Freq=800, CH0 RK0
946 16:30:41.920856
947 16:30:41.920908 DATLAT Default: 0xa
948 16:30:41.920960 0, 0xFFFF, sum = 0
949 16:30:41.921013 1, 0xFFFF, sum = 0
950 16:30:41.921066 2, 0xFFFF, sum = 0
951 16:30:41.921118 3, 0xFFFF, sum = 0
952 16:30:41.921223 4, 0xFFFF, sum = 0
953 16:30:41.921339 5, 0xFFFF, sum = 0
954 16:30:41.921437 6, 0xFFFF, sum = 0
955 16:30:41.921497 7, 0xFFFF, sum = 0
956 16:30:41.921552 8, 0xFFFF, sum = 0
957 16:30:41.921606 9, 0x0, sum = 1
958 16:30:41.921660 10, 0x0, sum = 2
959 16:30:41.921713 11, 0x0, sum = 3
960 16:30:41.921766 12, 0x0, sum = 4
961 16:30:41.921818 best_step = 10
962 16:30:41.921871
963 16:30:41.921923 ==
964 16:30:41.921975 Dram Type= 6, Freq= 0, CH_0, rank 0
965 16:30:41.922028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 16:30:41.922080 ==
967 16:30:41.922132 RX Vref Scan: 1
968 16:30:41.922185
969 16:30:41.922236 Set Vref Range= 32 -> 127
970 16:30:41.922288
971 16:30:41.922340 RX Vref 32 -> 127, step: 1
972 16:30:41.922391
973 16:30:41.922443 RX Delay -111 -> 252, step: 8
974 16:30:41.922495
975 16:30:41.922547 Set Vref, RX VrefLevel [Byte0]: 32
976 16:30:41.922599 [Byte1]: 32
977 16:30:41.922651
978 16:30:41.922702 Set Vref, RX VrefLevel [Byte0]: 33
979 16:30:41.922755 [Byte1]: 33
980 16:30:41.922806
981 16:30:41.922858 Set Vref, RX VrefLevel [Byte0]: 34
982 16:30:41.922911 [Byte1]: 34
983 16:30:41.922962
984 16:30:41.923013 Set Vref, RX VrefLevel [Byte0]: 35
985 16:30:41.923066 [Byte1]: 35
986 16:30:41.923118
987 16:30:41.923171 Set Vref, RX VrefLevel [Byte0]: 36
988 16:30:41.923223 [Byte1]: 36
989 16:30:41.923275
990 16:30:41.923327 Set Vref, RX VrefLevel [Byte0]: 37
991 16:30:41.923380 [Byte1]: 37
992 16:30:41.923432
993 16:30:41.923484 Set Vref, RX VrefLevel [Byte0]: 38
994 16:30:41.923536 [Byte1]: 38
995 16:30:41.923588
996 16:30:41.923639 Set Vref, RX VrefLevel [Byte0]: 39
997 16:30:41.923692 [Byte1]: 39
998 16:30:41.923744
999 16:30:41.923796 Set Vref, RX VrefLevel [Byte0]: 40
1000 16:30:41.923848 [Byte1]: 40
1001 16:30:41.923899
1002 16:30:41.923951 Set Vref, RX VrefLevel [Byte0]: 41
1003 16:30:41.924004 [Byte1]: 41
1004 16:30:41.924056
1005 16:30:41.924107 Set Vref, RX VrefLevel [Byte0]: 42
1006 16:30:41.924160 [Byte1]: 42
1007 16:30:41.924212
1008 16:30:41.924264 Set Vref, RX VrefLevel [Byte0]: 43
1009 16:30:41.924316 [Byte1]: 43
1010 16:30:41.924369
1011 16:30:41.924420 Set Vref, RX VrefLevel [Byte0]: 44
1012 16:30:41.924472 [Byte1]: 44
1013 16:30:41.924524
1014 16:30:41.924576 Set Vref, RX VrefLevel [Byte0]: 45
1015 16:30:41.924628 [Byte1]: 45
1016 16:30:41.924681
1017 16:30:41.924733 Set Vref, RX VrefLevel [Byte0]: 46
1018 16:30:41.924787 [Byte1]: 46
1019 16:30:41.924840
1020 16:30:41.924892 Set Vref, RX VrefLevel [Byte0]: 47
1021 16:30:41.924943 [Byte1]: 47
1022 16:30:41.924995
1023 16:30:41.925073 Set Vref, RX VrefLevel [Byte0]: 48
1024 16:30:41.925176 [Byte1]: 48
1025 16:30:41.925279
1026 16:30:41.925352 Set Vref, RX VrefLevel [Byte0]: 49
1027 16:30:41.925408 [Byte1]: 49
1028 16:30:41.925462
1029 16:30:41.925514 Set Vref, RX VrefLevel [Byte0]: 50
1030 16:30:41.925567 [Byte1]: 50
1031 16:30:41.925620
1032 16:30:41.925709 Set Vref, RX VrefLevel [Byte0]: 51
1033 16:30:41.925761 [Byte1]: 51
1034 16:30:41.925813
1035 16:30:41.925865 Set Vref, RX VrefLevel [Byte0]: 52
1036 16:30:41.925927 [Byte1]: 52
1037 16:30:41.926011
1038 16:30:41.926066 Set Vref, RX VrefLevel [Byte0]: 53
1039 16:30:41.926135 [Byte1]: 53
1040 16:30:41.926196
1041 16:30:41.926263 Set Vref, RX VrefLevel [Byte0]: 54
1042 16:30:41.926318 [Byte1]: 54
1043 16:30:41.926411
1044 16:30:41.926463 Set Vref, RX VrefLevel [Byte0]: 55
1045 16:30:41.926516 [Byte1]: 55
1046 16:30:41.926568
1047 16:30:41.926620 Set Vref, RX VrefLevel [Byte0]: 56
1048 16:30:41.926672 [Byte1]: 56
1049 16:30:41.926724
1050 16:30:41.926776 Set Vref, RX VrefLevel [Byte0]: 57
1051 16:30:41.926828 [Byte1]: 57
1052 16:30:41.926880
1053 16:30:41.926931 Set Vref, RX VrefLevel [Byte0]: 58
1054 16:30:41.926983 [Byte1]: 58
1055 16:30:41.927038
1056 16:30:41.927092 Set Vref, RX VrefLevel [Byte0]: 59
1057 16:30:41.927149 [Byte1]: 59
1058 16:30:41.927202
1059 16:30:41.927254 Set Vref, RX VrefLevel [Byte0]: 60
1060 16:30:41.927306 [Byte1]: 60
1061 16:30:41.927358
1062 16:30:41.927410 Set Vref, RX VrefLevel [Byte0]: 61
1063 16:30:41.927461 [Byte1]: 61
1064 16:30:41.927513
1065 16:30:41.927564 Set Vref, RX VrefLevel [Byte0]: 62
1066 16:30:41.927631 [Byte1]: 62
1067 16:30:41.927696
1068 16:30:41.927748 Set Vref, RX VrefLevel [Byte0]: 63
1069 16:30:41.927800 [Byte1]: 63
1070 16:30:41.927852
1071 16:30:41.927903 Set Vref, RX VrefLevel [Byte0]: 64
1072 16:30:41.927984 [Byte1]: 64
1073 16:30:41.928065
1074 16:30:41.928148 Set Vref, RX VrefLevel [Byte0]: 65
1075 16:30:41.928259 [Byte1]: 65
1076 16:30:41.928339
1077 16:30:41.928391 Set Vref, RX VrefLevel [Byte0]: 66
1078 16:30:41.928443 [Byte1]: 66
1079 16:30:41.928495
1080 16:30:41.928547 Set Vref, RX VrefLevel [Byte0]: 67
1081 16:30:41.928599 [Byte1]: 67
1082 16:30:41.928657
1083 16:30:41.928744 Set Vref, RX VrefLevel [Byte0]: 68
1084 16:30:41.928798 [Byte1]: 68
1085 16:30:41.928864
1086 16:30:41.928956 Set Vref, RX VrefLevel [Byte0]: 69
1087 16:30:41.929083 [Byte1]: 69
1088 16:30:41.929181
1089 16:30:41.929281 Set Vref, RX VrefLevel [Byte0]: 70
1090 16:30:41.929553 [Byte1]: 70
1091 16:30:41.929642
1092 16:30:41.929697 Set Vref, RX VrefLevel [Byte0]: 71
1093 16:30:41.929752 [Byte1]: 71
1094 16:30:41.929805
1095 16:30:41.929857 Set Vref, RX VrefLevel [Byte0]: 72
1096 16:30:41.929910 [Byte1]: 72
1097 16:30:41.929963
1098 16:30:41.930015 Set Vref, RX VrefLevel [Byte0]: 73
1099 16:30:41.930082 [Byte1]: 73
1100 16:30:41.930163
1101 16:30:41.930228 Final RX Vref Byte 0 = 56 to rank0
1102 16:30:41.930309 Final RX Vref Byte 1 = 62 to rank0
1103 16:30:41.930375 Final RX Vref Byte 0 = 56 to rank1
1104 16:30:41.930455 Final RX Vref Byte 1 = 62 to rank1==
1105 16:30:41.930523 Dram Type= 6, Freq= 0, CH_0, rank 0
1106 16:30:41.930575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1107 16:30:41.930643 ==
1108 16:30:41.930738 DQS Delay:
1109 16:30:41.930790 DQS0 = 0, DQS1 = 0
1110 16:30:41.930870 DQM Delay:
1111 16:30:41.930950 DQM0 = 88, DQM1 = 76
1112 16:30:41.931016 DQ Delay:
1113 16:30:41.931069 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1114 16:30:41.931123 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1115 16:30:41.931177 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1116 16:30:41.931230 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1117 16:30:41.931283
1118 16:30:41.931335
1119 16:30:41.931424 [DQSOSCAuto] RK0, (LSB)MR18= 0x302a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1120 16:30:41.931489 CH0 RK0: MR19=606, MR18=302A
1121 16:30:41.931544 CH0_RK0: MR19=0x606, MR18=0x302A, DQSOSC=397, MR23=63, INC=93, DEC=62
1122 16:30:41.931599
1123 16:30:41.931652 ----->DramcWriteLeveling(PI) begin...
1124 16:30:41.931707 ==
1125 16:30:41.931761 Dram Type= 6, Freq= 0, CH_0, rank 1
1126 16:30:41.931815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 16:30:41.931869 ==
1128 16:30:41.931923 Write leveling (Byte 0): 32 => 32
1129 16:30:41.931977 Write leveling (Byte 1): 26 => 26
1130 16:30:41.932030 DramcWriteLeveling(PI) end<-----
1131 16:30:41.932083
1132 16:30:41.932136 ==
1133 16:30:41.932189 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 16:30:41.932242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 16:30:41.932308 ==
1136 16:30:41.932450 [Gating] SW mode calibration
1137 16:30:41.932551 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1138 16:30:41.932614 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1139 16:30:41.932669 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1140 16:30:41.932723 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 16:30:41.932776 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1142 16:30:41.932828 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 16:30:41.932881 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 16:30:41.932934 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 16:30:41.932986 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 16:30:41.933054 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 16:30:41.933121 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 16:30:41.933173 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 16:30:41.933225 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 16:30:41.933316 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 16:30:41.933370 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 16:30:41.933422 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 16:30:41.933474 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 16:30:41.933526 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 16:30:41.933578 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1156 16:30:41.933630 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1157 16:30:41.933682 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1158 16:30:41.933734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 16:30:41.933786 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 16:30:41.933838 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 16:30:41.933890 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 16:30:41.933943 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 16:30:41.933995 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 16:30:41.934047 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 16:30:41.934099 0 9 8 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
1166 16:30:41.934160 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1167 16:30:41.934215 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 16:30:41.934291 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 16:30:41.934359 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 16:30:41.934411 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 16:30:41.934464 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 16:30:41.934516 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
1173 16:30:41.934568 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
1174 16:30:41.934621 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1175 16:30:41.934673 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 16:30:41.934725 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 16:30:41.934777 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 16:30:41.934828 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 16:30:41.934880 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 16:30:41.934933 0 11 4 | B1->B0 | 2323 3030 | 1 0 | (0 0) (0 0)
1181 16:30:41.934984 0 11 8 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
1182 16:30:41.935040 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1183 16:30:41.935093 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 16:30:41.935146 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 16:30:41.935197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 16:30:41.935249 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 16:30:41.935302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 16:30:41.935354 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1189 16:30:41.935406 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1190 16:30:41.935458 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 16:30:41.935708 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 16:30:41.935809 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 16:30:41.935885 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 16:30:41.936032 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 16:30:41.936155 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 16:30:41.936253 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 16:30:41.936316 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 16:30:41.936372 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 16:30:41.936427 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 16:30:41.936481 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 16:30:41.936535 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 16:30:41.936588 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 16:30:41.936642 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 16:30:41.936755 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 16:30:41.936821 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 16:30:41.936902 Total UI for P1: 0, mck2ui 16
1207 16:30:41.937015 best dqsien dly found for B0: ( 0, 14, 6)
1208 16:30:41.937084 Total UI for P1: 0, mck2ui 16
1209 16:30:41.937137 best dqsien dly found for B1: ( 0, 14, 6)
1210 16:30:41.937206 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1211 16:30:41.937279 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1212 16:30:41.937348
1213 16:30:41.937400 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1214 16:30:41.937453 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1215 16:30:41.937505 [Gating] SW calibration Done
1216 16:30:41.937574 ==
1217 16:30:41.937640 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 16:30:41.937693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 16:30:41.937746 ==
1220 16:30:41.937798 RX Vref Scan: 0
1221 16:30:41.937850
1222 16:30:41.937901 RX Vref 0 -> 0, step: 1
1223 16:30:41.937953
1224 16:30:41.938005 RX Delay -130 -> 252, step: 16
1225 16:30:41.938058 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1226 16:30:41.938111 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1227 16:30:41.938163 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1228 16:30:41.938216 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1229 16:30:41.938268 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1230 16:30:41.938321 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1231 16:30:41.938372 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1232 16:30:41.938424 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1233 16:30:41.938477 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1234 16:30:41.938529 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1235 16:30:41.938580 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1236 16:30:41.938633 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1237 16:30:41.938685 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1238 16:30:41.938737 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1239 16:30:41.938789 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1240 16:30:41.938842 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1241 16:30:41.938894 ==
1242 16:30:41.938946 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 16:30:41.938999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 16:30:41.939052 ==
1245 16:30:41.939104 DQS Delay:
1246 16:30:41.939156 DQS0 = 0, DQS1 = 0
1247 16:30:41.939209 DQM Delay:
1248 16:30:41.939260 DQM0 = 86, DQM1 = 76
1249 16:30:41.939311 DQ Delay:
1250 16:30:41.939363 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1251 16:30:41.939415 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1252 16:30:41.939467 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1253 16:30:41.939519 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1254 16:30:41.939571
1255 16:30:41.939622
1256 16:30:41.939674 ==
1257 16:30:41.939736 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 16:30:41.939881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 16:30:41.940043 ==
1260 16:30:41.940129
1261 16:30:41.940185
1262 16:30:41.940238 TX Vref Scan disable
1263 16:30:41.940291 == TX Byte 0 ==
1264 16:30:41.940344 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1265 16:30:41.940398 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1266 16:30:41.940451 == TX Byte 1 ==
1267 16:30:41.940503 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1268 16:30:41.940556 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1269 16:30:41.940608 ==
1270 16:30:41.940660 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 16:30:41.940740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 16:30:41.940793 ==
1273 16:30:41.940845 TX Vref=22, minBit 5, minWin=26, winSum=441
1274 16:30:41.940898 TX Vref=24, minBit 1, minWin=27, winSum=448
1275 16:30:41.940951 TX Vref=26, minBit 1, minWin=27, winSum=448
1276 16:30:41.941003 TX Vref=28, minBit 1, minWin=27, winSum=452
1277 16:30:41.941056 TX Vref=30, minBit 5, minWin=27, winSum=452
1278 16:30:41.941108 TX Vref=32, minBit 1, minWin=27, winSum=452
1279 16:30:41.941160 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 28
1280 16:30:41.941213
1281 16:30:41.941288 Final TX Range 1 Vref 28
1282 16:30:41.941357
1283 16:30:41.941409 ==
1284 16:30:41.941462 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 16:30:41.941514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 16:30:41.941567 ==
1287 16:30:41.941619
1288 16:30:41.941670
1289 16:30:41.941721 TX Vref Scan disable
1290 16:30:41.941812 == TX Byte 0 ==
1291 16:30:41.941869 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1292 16:30:41.941922 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1293 16:30:41.941975 == TX Byte 1 ==
1294 16:30:41.942027 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1295 16:30:41.942113 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1296 16:30:41.942164
1297 16:30:41.942216 [DATLAT]
1298 16:30:41.942267 Freq=800, CH0 RK1
1299 16:30:41.942325
1300 16:30:41.942381 DATLAT Default: 0xa
1301 16:30:41.942433 0, 0xFFFF, sum = 0
1302 16:30:41.942485 1, 0xFFFF, sum = 0
1303 16:30:41.942539 2, 0xFFFF, sum = 0
1304 16:30:41.942590 3, 0xFFFF, sum = 0
1305 16:30:41.942642 4, 0xFFFF, sum = 0
1306 16:30:41.942719 5, 0xFFFF, sum = 0
1307 16:30:41.942785 6, 0xFFFF, sum = 0
1308 16:30:41.942836 7, 0xFFFF, sum = 0
1309 16:30:41.942888 8, 0xFFFF, sum = 0
1310 16:30:41.942941 9, 0x0, sum = 1
1311 16:30:41.942992 10, 0x0, sum = 2
1312 16:30:41.943044 11, 0x0, sum = 3
1313 16:30:41.943097 12, 0x0, sum = 4
1314 16:30:41.943148 best_step = 10
1315 16:30:41.943200
1316 16:30:41.943250 ==
1317 16:30:41.943304 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 16:30:41.943440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 16:30:41.943546 ==
1320 16:30:41.943634 RX Vref Scan: 0
1321 16:30:41.943691
1322 16:30:41.943743 RX Vref 0 -> 0, step: 1
1323 16:30:41.943796
1324 16:30:41.943848 RX Delay -95 -> 252, step: 8
1325 16:30:41.943901 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1326 16:30:41.943953 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1327 16:30:41.944225 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1328 16:30:41.944314 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1329 16:30:41.944381 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1330 16:30:41.944433 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1331 16:30:41.944485 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1332 16:30:41.944537 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1333 16:30:41.944589 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1334 16:30:41.944641 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1335 16:30:41.944693 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1336 16:30:41.944746 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1337 16:30:41.944798 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1338 16:30:41.944849 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1339 16:30:41.944901 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1340 16:30:41.944981 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1341 16:30:41.945032 ==
1342 16:30:41.945135 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 16:30:41.945189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 16:30:41.945242 ==
1345 16:30:41.945319 DQS Delay:
1346 16:30:41.945371 DQS0 = 0, DQS1 = 0
1347 16:30:41.945422 DQM Delay:
1348 16:30:41.945473 DQM0 = 86, DQM1 = 75
1349 16:30:41.945525 DQ Delay:
1350 16:30:41.945576 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1351 16:30:41.945627 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1352 16:30:41.945679 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1353 16:30:41.945730 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =80
1354 16:30:41.945782
1355 16:30:41.945833
1356 16:30:41.945884 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1357 16:30:41.945936 CH0 RK1: MR19=606, MR18=2F2B
1358 16:30:41.945988 CH0_RK1: MR19=0x606, MR18=0x2F2B, DQSOSC=397, MR23=63, INC=93, DEC=62
1359 16:30:41.946040 [RxdqsGatingPostProcess] freq 800
1360 16:30:41.946091 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 16:30:41.946214 Pre-setting of DQS Precalculation
1362 16:30:41.946292 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1363 16:30:41.946360 ==
1364 16:30:41.946412 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 16:30:41.946464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 16:30:41.946545 ==
1367 16:30:41.946600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 16:30:41.946652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 16:30:41.946705 [CA 0] Center 37 (6~68) winsize 63
1370 16:30:41.946758 [CA 1] Center 36 (6~67) winsize 62
1371 16:30:41.946835 [CA 2] Center 35 (4~66) winsize 63
1372 16:30:41.946905 [CA 3] Center 34 (4~65) winsize 62
1373 16:30:41.946957 [CA 4] Center 35 (4~66) winsize 63
1374 16:30:41.947015 [CA 5] Center 34 (4~65) winsize 62
1375 16:30:41.947127
1376 16:30:41.947242 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 16:30:41.947337
1378 16:30:41.947450 [CATrainingPosCal] consider 1 rank data
1379 16:30:41.947565 u2DelayCellTimex100 = 270/100 ps
1380 16:30:41.947668 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1381 16:30:41.947753 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1382 16:30:41.947835 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1383 16:30:41.947936 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1384 16:30:41.948112 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1385 16:30:41.948229 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1386 16:30:41.948312
1387 16:30:41.948408 CA PerBit enable=1, Macro0, CA PI delay=34
1388 16:30:41.948489
1389 16:30:41.948570 [CBTSetCACLKResult] CA Dly = 34
1390 16:30:41.948651 CS Dly: 4 (0~35)
1391 16:30:41.948732 ==
1392 16:30:41.948813 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 16:30:41.948901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 16:30:41.948959 ==
1395 16:30:41.949012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 16:30:41.949080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 16:30:41.949146 [CA 0] Center 36 (6~67) winsize 62
1398 16:30:41.949199 [CA 1] Center 36 (6~67) winsize 62
1399 16:30:41.949250 [CA 2] Center 35 (4~66) winsize 63
1400 16:30:41.949341 [CA 3] Center 34 (4~65) winsize 62
1401 16:30:41.949393 [CA 4] Center 34 (4~65) winsize 62
1402 16:30:41.949445 [CA 5] Center 34 (4~65) winsize 62
1403 16:30:41.949496
1404 16:30:41.949548 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 16:30:41.949600
1406 16:30:41.949663 [CATrainingPosCal] consider 2 rank data
1407 16:30:41.949719 u2DelayCellTimex100 = 270/100 ps
1408 16:30:41.949778 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 16:30:41.949832 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1410 16:30:41.949884 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1411 16:30:41.949959 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 16:30:41.950013 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 16:30:41.950066 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 16:30:41.950141
1415 16:30:41.950208 CA PerBit enable=1, Macro0, CA PI delay=34
1416 16:30:41.950260
1417 16:30:41.950312 [CBTSetCACLKResult] CA Dly = 34
1418 16:30:41.950388 CS Dly: 5 (0~37)
1419 16:30:41.950442
1420 16:30:41.950495 ----->DramcWriteLeveling(PI) begin...
1421 16:30:41.950560 ==
1422 16:30:41.950615 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 16:30:41.950667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 16:30:41.950721 ==
1425 16:30:41.950773 Write leveling (Byte 0): 27 => 27
1426 16:30:41.950861 Write leveling (Byte 1): 28 => 28
1427 16:30:41.950951 DramcWriteLeveling(PI) end<-----
1428 16:30:41.951048
1429 16:30:41.951135 ==
1430 16:30:41.951218 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 16:30:41.951314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 16:30:41.951439 ==
1433 16:30:41.951521 [Gating] SW mode calibration
1434 16:30:41.951604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 16:30:41.951686 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 16:30:41.951768 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1437 16:30:41.951851 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1438 16:30:41.951933 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 16:30:41.952014 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 16:30:41.952110 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 16:30:41.952218 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 16:30:41.952327 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 16:30:41.952456 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 16:30:41.952744 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 16:30:41.952807 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 16:30:41.952862 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 16:30:41.952916 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 16:30:41.952968 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 16:30:41.953021 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 16:30:41.953072 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 16:30:41.953125 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 16:30:41.953177 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 16:30:41.953229 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1454 16:30:41.953330 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 16:30:41.953413 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 16:30:41.953495 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 16:30:41.953577 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 16:30:41.953658 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 16:30:41.953740 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 16:30:41.953822 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 16:30:41.953903 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 16:30:41.953985 0 9 8 | B1->B0 | 2d2d 3333 | 1 1 | (0 0) (1 1)
1463 16:30:41.954067 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1464 16:30:41.954148 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 16:30:41.954236 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 16:30:41.954335 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 16:30:41.954431 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 16:30:41.954500 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 16:30:41.954555 0 10 4 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 1)
1470 16:30:41.954609 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1471 16:30:41.954661 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 16:30:41.954713 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 16:30:41.954765 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 16:30:41.954817 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 16:30:41.954869 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 16:30:41.954921 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 16:30:41.954973 0 11 4 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
1478 16:30:41.955025 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1479 16:30:41.955077 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1480 16:30:41.955128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 16:30:41.955181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 16:30:41.955277 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 16:30:41.955371 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 16:30:41.955424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1485 16:30:41.955476 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1486 16:30:41.955528 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1487 16:30:41.955580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 16:30:41.955631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 16:30:41.955682 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 16:30:41.955733 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 16:30:41.955785 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 16:30:41.955836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 16:30:41.955916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 16:30:41.955967 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 16:30:41.956019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 16:30:41.956070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 16:30:41.956140 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 16:30:41.956265 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 16:30:41.956361 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 16:30:41.956467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 16:30:41.956552 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1502 16:30:41.956634 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 16:30:41.956716 Total UI for P1: 0, mck2ui 16
1504 16:30:41.956799 best dqsien dly found for B0: ( 0, 14, 4)
1505 16:30:41.956895 Total UI for P1: 0, mck2ui 16
1506 16:30:41.956992 best dqsien dly found for B1: ( 0, 14, 6)
1507 16:30:41.957073 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1508 16:30:41.957155 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1509 16:30:41.957235
1510 16:30:41.957363 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1511 16:30:41.957446 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1512 16:30:41.957527 [Gating] SW calibration Done
1513 16:30:41.957607 ==
1514 16:30:41.957689 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 16:30:41.957771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 16:30:41.957852 ==
1517 16:30:41.957933 RX Vref Scan: 0
1518 16:30:41.958026
1519 16:30:41.958083 RX Vref 0 -> 0, step: 1
1520 16:30:41.958137
1521 16:30:41.958189 RX Delay -130 -> 252, step: 16
1522 16:30:41.958242 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1523 16:30:41.958294 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1524 16:30:41.958346 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1525 16:30:41.958398 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1526 16:30:41.958480 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1527 16:30:41.958533 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1528 16:30:41.958585 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1529 16:30:41.958637 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1530 16:30:41.958689 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1531 16:30:41.958741 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1532 16:30:41.958792 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1533 16:30:41.958844 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1534 16:30:41.959096 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1535 16:30:41.959155 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1536 16:30:41.959208 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1537 16:30:41.959260 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1538 16:30:41.959312 ==
1539 16:30:41.959364 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 16:30:41.959417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 16:30:41.959469 ==
1542 16:30:41.959520 DQS Delay:
1543 16:30:41.959572 DQS0 = 0, DQS1 = 0
1544 16:30:41.959623 DQM Delay:
1545 16:30:41.959678 DQM0 = 89, DQM1 = 82
1546 16:30:41.959729 DQ Delay:
1547 16:30:41.959781 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1548 16:30:41.959833 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1549 16:30:41.959885 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1550 16:30:41.959937 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1551 16:30:41.959988
1552 16:30:41.960039
1553 16:30:41.960090 ==
1554 16:30:41.960142 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 16:30:41.960194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 16:30:41.960247 ==
1557 16:30:41.960298
1558 16:30:41.960348
1559 16:30:41.960400 TX Vref Scan disable
1560 16:30:41.960453 == TX Byte 0 ==
1561 16:30:41.960504 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1562 16:30:41.960556 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1563 16:30:41.960608 == TX Byte 1 ==
1564 16:30:41.960660 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1565 16:30:41.960712 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1566 16:30:41.960764 ==
1567 16:30:41.960815 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 16:30:41.960867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 16:30:41.960919 ==
1570 16:30:41.960971 TX Vref=22, minBit 2, minWin=26, winSum=440
1571 16:30:41.961022 TX Vref=24, minBit 6, minWin=26, winSum=445
1572 16:30:41.961074 TX Vref=26, minBit 1, minWin=27, winSum=449
1573 16:30:41.961126 TX Vref=28, minBit 0, minWin=27, winSum=450
1574 16:30:41.961178 TX Vref=30, minBit 1, minWin=27, winSum=454
1575 16:30:41.961230 TX Vref=32, minBit 0, minWin=27, winSum=450
1576 16:30:41.961324 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 30
1577 16:30:41.961377
1578 16:30:41.961429 Final TX Range 1 Vref 30
1579 16:30:41.961480
1580 16:30:41.961532 ==
1581 16:30:41.961583 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 16:30:41.961634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 16:30:41.961687 ==
1584 16:30:41.961738
1585 16:30:41.961789
1586 16:30:41.961840 TX Vref Scan disable
1587 16:30:41.961891 == TX Byte 0 ==
1588 16:30:41.961942 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1589 16:30:41.961994 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1590 16:30:41.962046 == TX Byte 1 ==
1591 16:30:41.962097 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1592 16:30:41.962149 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1593 16:30:41.962201
1594 16:30:41.962252 [DATLAT]
1595 16:30:41.962303 Freq=800, CH1 RK0
1596 16:30:41.962355
1597 16:30:41.962406 DATLAT Default: 0xa
1598 16:30:41.962457 0, 0xFFFF, sum = 0
1599 16:30:41.962511 1, 0xFFFF, sum = 0
1600 16:30:41.962564 2, 0xFFFF, sum = 0
1601 16:30:41.962617 3, 0xFFFF, sum = 0
1602 16:30:41.962669 4, 0xFFFF, sum = 0
1603 16:30:41.962721 5, 0xFFFF, sum = 0
1604 16:30:41.962773 6, 0xFFFF, sum = 0
1605 16:30:41.962826 7, 0xFFFF, sum = 0
1606 16:30:41.962878 8, 0xFFFF, sum = 0
1607 16:30:41.962931 9, 0x0, sum = 1
1608 16:30:41.962983 10, 0x0, sum = 2
1609 16:30:41.963035 11, 0x0, sum = 3
1610 16:30:41.963087 12, 0x0, sum = 4
1611 16:30:41.963140 best_step = 10
1612 16:30:41.963191
1613 16:30:41.963241 ==
1614 16:30:41.963293 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 16:30:41.963345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 16:30:41.963397 ==
1617 16:30:41.963448 RX Vref Scan: 1
1618 16:30:41.963498
1619 16:30:41.963549 Set Vref Range= 32 -> 127
1620 16:30:41.963601
1621 16:30:41.963652 RX Vref 32 -> 127, step: 1
1622 16:30:41.963703
1623 16:30:41.963754 RX Delay -95 -> 252, step: 8
1624 16:30:41.963805
1625 16:30:41.963856 Set Vref, RX VrefLevel [Byte0]: 32
1626 16:30:41.963908 [Byte1]: 32
1627 16:30:41.963959
1628 16:30:41.964011 Set Vref, RX VrefLevel [Byte0]: 33
1629 16:30:41.964062 [Byte1]: 33
1630 16:30:41.964114
1631 16:30:41.964165 Set Vref, RX VrefLevel [Byte0]: 34
1632 16:30:41.964216 [Byte1]: 34
1633 16:30:41.964267
1634 16:30:41.964318 Set Vref, RX VrefLevel [Byte0]: 35
1635 16:30:41.964370 [Byte1]: 35
1636 16:30:41.964424
1637 16:30:41.964499 Set Vref, RX VrefLevel [Byte0]: 36
1638 16:30:41.964577 [Byte1]: 36
1639 16:30:41.964631
1640 16:30:41.964683 Set Vref, RX VrefLevel [Byte0]: 37
1641 16:30:41.964772 [Byte1]: 37
1642 16:30:41.964824
1643 16:30:41.964875 Set Vref, RX VrefLevel [Byte0]: 38
1644 16:30:41.964927 [Byte1]: 38
1645 16:30:41.964980
1646 16:30:41.965031 Set Vref, RX VrefLevel [Byte0]: 39
1647 16:30:41.965083 [Byte1]: 39
1648 16:30:41.965158
1649 16:30:41.965211 Set Vref, RX VrefLevel [Byte0]: 40
1650 16:30:41.965271 [Byte1]: 40
1651 16:30:41.965339
1652 16:30:41.965391 Set Vref, RX VrefLevel [Byte0]: 41
1653 16:30:41.965442 [Byte1]: 41
1654 16:30:41.965494
1655 16:30:41.965546 Set Vref, RX VrefLevel [Byte0]: 42
1656 16:30:41.965597 [Byte1]: 42
1657 16:30:41.965649
1658 16:30:41.965700 Set Vref, RX VrefLevel [Byte0]: 43
1659 16:30:41.965751 [Byte1]: 43
1660 16:30:41.965803
1661 16:30:41.965853 Set Vref, RX VrefLevel [Byte0]: 44
1662 16:30:41.965905 [Byte1]: 44
1663 16:30:41.965957
1664 16:30:41.966008 Set Vref, RX VrefLevel [Byte0]: 45
1665 16:30:41.966059 [Byte1]: 45
1666 16:30:41.966110
1667 16:30:41.966161 Set Vref, RX VrefLevel [Byte0]: 46
1668 16:30:41.966213 [Byte1]: 46
1669 16:30:41.966264
1670 16:30:41.966336 Set Vref, RX VrefLevel [Byte0]: 47
1671 16:30:41.966401 [Byte1]: 47
1672 16:30:41.966452
1673 16:30:41.966503 Set Vref, RX VrefLevel [Byte0]: 48
1674 16:30:41.966554 [Byte1]: 48
1675 16:30:41.966605
1676 16:30:41.966656 Set Vref, RX VrefLevel [Byte0]: 49
1677 16:30:41.966707 [Byte1]: 49
1678 16:30:41.966758
1679 16:30:41.966809 Set Vref, RX VrefLevel [Byte0]: 50
1680 16:30:41.966861 [Byte1]: 50
1681 16:30:41.966911
1682 16:30:41.966962 Set Vref, RX VrefLevel [Byte0]: 51
1683 16:30:41.967013 [Byte1]: 51
1684 16:30:41.967064
1685 16:30:41.967115 Set Vref, RX VrefLevel [Byte0]: 52
1686 16:30:41.967167 [Byte1]: 52
1687 16:30:41.967219
1688 16:30:41.967270 Set Vref, RX VrefLevel [Byte0]: 53
1689 16:30:41.967322 [Byte1]: 53
1690 16:30:41.967373
1691 16:30:41.967424 Set Vref, RX VrefLevel [Byte0]: 54
1692 16:30:41.967475 [Byte1]: 54
1693 16:30:41.967526
1694 16:30:41.967577 Set Vref, RX VrefLevel [Byte0]: 55
1695 16:30:41.967629 [Byte1]: 55
1696 16:30:41.967680
1697 16:30:41.967731 Set Vref, RX VrefLevel [Byte0]: 56
1698 16:30:41.967782 [Byte1]: 56
1699 16:30:41.968036
1700 16:30:41.968094 Set Vref, RX VrefLevel [Byte0]: 57
1701 16:30:41.968146 [Byte1]: 57
1702 16:30:41.968198
1703 16:30:41.968250 Set Vref, RX VrefLevel [Byte0]: 58
1704 16:30:41.968302 [Byte1]: 58
1705 16:30:41.968354
1706 16:30:41.968406 Set Vref, RX VrefLevel [Byte0]: 59
1707 16:30:41.968473 [Byte1]: 59
1708 16:30:41.968555
1709 16:30:41.968637 Set Vref, RX VrefLevel [Byte0]: 60
1710 16:30:41.968706 [Byte1]: 60
1711 16:30:41.968841
1712 16:30:41.968939 Set Vref, RX VrefLevel [Byte0]: 61
1713 16:30:41.969036 [Byte1]: 61
1714 16:30:41.969130
1715 16:30:41.969211 Set Vref, RX VrefLevel [Byte0]: 62
1716 16:30:41.969320 [Byte1]: 62
1717 16:30:41.969374
1718 16:30:41.969426 Set Vref, RX VrefLevel [Byte0]: 63
1719 16:30:41.969478 [Byte1]: 63
1720 16:30:41.969530
1721 16:30:41.969582 Set Vref, RX VrefLevel [Byte0]: 64
1722 16:30:41.969633 [Byte1]: 64
1723 16:30:41.969685
1724 16:30:41.969736 Set Vref, RX VrefLevel [Byte0]: 65
1725 16:30:41.969788 [Byte1]: 65
1726 16:30:41.969839
1727 16:30:41.969891 Set Vref, RX VrefLevel [Byte0]: 66
1728 16:30:41.969942 [Byte1]: 66
1729 16:30:41.969994
1730 16:30:41.970045 Set Vref, RX VrefLevel [Byte0]: 67
1731 16:30:41.970097 [Byte1]: 67
1732 16:30:41.970148
1733 16:30:41.970199 Set Vref, RX VrefLevel [Byte0]: 68
1734 16:30:41.970251 [Byte1]: 68
1735 16:30:41.970302
1736 16:30:41.970353 Set Vref, RX VrefLevel [Byte0]: 69
1737 16:30:41.970405 [Byte1]: 69
1738 16:30:41.970455
1739 16:30:41.970506 Set Vref, RX VrefLevel [Byte0]: 70
1740 16:30:41.970558 [Byte1]: 70
1741 16:30:41.970609
1742 16:30:41.970660 Set Vref, RX VrefLevel [Byte0]: 71
1743 16:30:41.970711 [Byte1]: 71
1744 16:30:41.970762
1745 16:30:41.970813 Set Vref, RX VrefLevel [Byte0]: 72
1746 16:30:41.970864 [Byte1]: 72
1747 16:30:41.970916
1748 16:30:41.970967 Set Vref, RX VrefLevel [Byte0]: 73
1749 16:30:41.971019 [Byte1]: 73
1750 16:30:41.971070
1751 16:30:41.971121 Set Vref, RX VrefLevel [Byte0]: 74
1752 16:30:41.971173 [Byte1]: 74
1753 16:30:41.971224
1754 16:30:41.971276 Set Vref, RX VrefLevel [Byte0]: 75
1755 16:30:41.971327 [Byte1]: 75
1756 16:30:41.971378
1757 16:30:41.971429 Final RX Vref Byte 0 = 60 to rank0
1758 16:30:41.971482 Final RX Vref Byte 1 = 52 to rank0
1759 16:30:41.971533 Final RX Vref Byte 0 = 60 to rank1
1760 16:30:41.971585 Final RX Vref Byte 1 = 52 to rank1==
1761 16:30:41.971637 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 16:30:41.971689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 16:30:41.971741 ==
1764 16:30:41.971793 DQS Delay:
1765 16:30:41.971880 DQS0 = 0, DQS1 = 0
1766 16:30:41.971931 DQM Delay:
1767 16:30:41.971983 DQM0 = 87, DQM1 = 81
1768 16:30:41.972033 DQ Delay:
1769 16:30:41.972085 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1770 16:30:41.972136 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1771 16:30:41.972189 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
1772 16:30:41.972241 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1773 16:30:41.972292
1774 16:30:41.972343
1775 16:30:41.972395 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f33, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
1776 16:30:41.972448 CH1 RK0: MR19=606, MR18=1F33
1777 16:30:41.972499 CH1_RK0: MR19=0x606, MR18=0x1F33, DQSOSC=396, MR23=63, INC=94, DEC=62
1778 16:30:41.972552
1779 16:30:41.972603 ----->DramcWriteLeveling(PI) begin...
1780 16:30:41.972656 ==
1781 16:30:41.972707 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 16:30:41.972760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 16:30:41.972812 ==
1784 16:30:41.972864 Write leveling (Byte 0): 26 => 26
1785 16:30:41.972916 Write leveling (Byte 1): 27 => 27
1786 16:30:41.972967 DramcWriteLeveling(PI) end<-----
1787 16:30:41.973019
1788 16:30:41.973071 ==
1789 16:30:41.973122 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 16:30:41.973192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 16:30:41.973245 ==
1792 16:30:41.973334 [Gating] SW mode calibration
1793 16:30:41.973387 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 16:30:41.973439 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 16:30:41.973492 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1796 16:30:41.973544 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1797 16:30:41.973596 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 16:30:41.973648 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 16:30:41.973700 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 16:30:41.973752 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 16:30:41.973804 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 16:30:41.973856 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 16:30:41.973922 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 16:30:41.973976 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 16:30:41.974029 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 16:30:41.974080 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 16:30:41.974132 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 16:30:41.974185 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 16:30:41.974237 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 16:30:41.974289 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 16:30:41.974340 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 16:30:41.974392 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1813 16:30:41.974444 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 16:30:41.974523 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 16:30:41.974593 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 16:30:41.974646 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 16:30:41.974698 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 16:30:41.974750 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 16:30:41.974803 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1820 16:30:41.974856 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1821 16:30:41.974908 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1822 16:30:41.974959 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 16:30:41.975011 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 16:30:41.975264 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 16:30:41.975322 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 16:30:41.975376 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 16:30:41.975428 0 10 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1828 16:30:41.975480 0 10 4 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 1)
1829 16:30:41.975532 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
1830 16:30:41.975599 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 16:30:41.975665 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 16:30:41.975717 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 16:30:41.975768 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 16:30:41.975820 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 16:30:41.975872 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 16:30:41.975923 0 11 4 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (0 0)
1837 16:30:41.975975 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1838 16:30:41.976027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 16:30:41.976079 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 16:30:41.976131 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 16:30:41.976184 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 16:30:41.976235 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 16:30:41.976287 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1844 16:30:41.976339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1845 16:30:41.976391 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 16:30:41.976443 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 16:30:41.976495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 16:30:41.976547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 16:30:41.976598 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 16:30:41.976650 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 16:30:41.976701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 16:30:41.976753 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 16:30:41.976804 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 16:30:41.976855 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 16:30:41.976907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 16:30:41.976959 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 16:30:41.977010 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 16:30:41.977062 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 16:30:41.977113 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1860 16:30:41.977164 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1861 16:30:41.977216 Total UI for P1: 0, mck2ui 16
1862 16:30:41.977310 best dqsien dly found for B0: ( 0, 14, 0)
1863 16:30:41.977366 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 16:30:41.977419 Total UI for P1: 0, mck2ui 16
1865 16:30:41.977472 best dqsien dly found for B1: ( 0, 14, 4)
1866 16:30:41.977524 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1867 16:30:41.977575 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1868 16:30:41.977627
1869 16:30:41.977678 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1870 16:30:41.977730 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1871 16:30:41.977781 [Gating] SW calibration Done
1872 16:30:41.977833 ==
1873 16:30:41.977885 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 16:30:41.977936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 16:30:41.977988 ==
1876 16:30:41.978040 RX Vref Scan: 0
1877 16:30:41.978093
1878 16:30:41.978145 RX Vref 0 -> 0, step: 1
1879 16:30:41.978196
1880 16:30:41.978247 RX Delay -130 -> 252, step: 16
1881 16:30:41.978302 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1882 16:30:41.978354 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1883 16:30:41.978406 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1884 16:30:41.978457 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1885 16:30:41.978508 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1886 16:30:41.978560 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1887 16:30:41.978612 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1888 16:30:41.978664 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1889 16:30:41.978715 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1890 16:30:41.978767 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1891 16:30:41.978818 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1892 16:30:41.978869 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1893 16:30:41.978920 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1894 16:30:41.978972 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1895 16:30:41.979023 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1896 16:30:41.979074 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1897 16:30:41.979125 ==
1898 16:30:41.979176 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 16:30:41.979228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 16:30:41.979279 ==
1901 16:30:41.979330 DQS Delay:
1902 16:30:41.979382 DQS0 = 0, DQS1 = 0
1903 16:30:41.979433 DQM Delay:
1904 16:30:41.979484 DQM0 = 85, DQM1 = 84
1905 16:30:41.979535 DQ Delay:
1906 16:30:41.979605 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =77
1907 16:30:41.979681 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1908 16:30:41.979735 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =69
1909 16:30:41.979787 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1910 16:30:41.979839
1911 16:30:41.979890
1912 16:30:41.979941 ==
1913 16:30:41.979993 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 16:30:41.980044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 16:30:41.980097 ==
1916 16:30:41.980149
1917 16:30:42.186229
1918 16:30:42.186414 TX Vref Scan disable
1919 16:30:42.186523 == TX Byte 0 ==
1920 16:30:42.186627 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1921 16:30:42.186729 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1922 16:30:42.186831 == TX Byte 1 ==
1923 16:30:42.186930 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1924 16:30:42.187030 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1925 16:30:42.187150 ==
1926 16:30:42.187264 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 16:30:42.187363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 16:30:42.187494 ==
1929 16:30:42.187593 TX Vref=22, minBit 1, minWin=26, winSum=445
1930 16:30:42.187692 TX Vref=24, minBit 2, minWin=27, winSum=450
1931 16:30:42.188016 TX Vref=26, minBit 2, minWin=27, winSum=452
1932 16:30:42.188156 TX Vref=28, minBit 2, minWin=27, winSum=456
1933 16:30:42.188259 TX Vref=30, minBit 3, minWin=27, winSum=454
1934 16:30:42.188360 TX Vref=32, minBit 2, minWin=27, winSum=453
1935 16:30:42.188460 [TxChooseVref] Worse bit 2, Min win 27, Win sum 456, Final Vref 28
1936 16:30:42.188558
1937 16:30:42.188704 Final TX Range 1 Vref 28
1938 16:30:42.188815
1939 16:30:42.188911 ==
1940 16:30:42.189007 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 16:30:42.189104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 16:30:42.189220 ==
1943 16:30:42.189343
1944 16:30:42.189440
1945 16:30:42.189535 TX Vref Scan disable
1946 16:30:42.189632 == TX Byte 0 ==
1947 16:30:42.189728 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1948 16:30:42.189827 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1949 16:30:42.189923 == TX Byte 1 ==
1950 16:30:42.190020 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1951 16:30:42.190118 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1952 16:30:42.190215
1953 16:30:42.190310 [DATLAT]
1954 16:30:42.190404 Freq=800, CH1 RK1
1955 16:30:42.190500
1956 16:30:42.190595 DATLAT Default: 0xa
1957 16:30:42.190691 0, 0xFFFF, sum = 0
1958 16:30:42.190789 1, 0xFFFF, sum = 0
1959 16:30:42.190888 2, 0xFFFF, sum = 0
1960 16:30:42.190986 3, 0xFFFF, sum = 0
1961 16:30:42.191084 4, 0xFFFF, sum = 0
1962 16:30:42.191183 5, 0xFFFF, sum = 0
1963 16:30:42.191280 6, 0xFFFF, sum = 0
1964 16:30:42.191377 7, 0xFFFF, sum = 0
1965 16:30:42.191475 8, 0xFFFF, sum = 0
1966 16:30:42.191573 9, 0x0, sum = 1
1967 16:30:42.191669 10, 0x0, sum = 2
1968 16:30:42.191767 11, 0x0, sum = 3
1969 16:30:42.191865 12, 0x0, sum = 4
1970 16:30:42.191963 best_step = 10
1971 16:30:42.192058
1972 16:30:42.192152 ==
1973 16:30:42.192247 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 16:30:42.192343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 16:30:42.192439 ==
1976 16:30:42.192535 RX Vref Scan: 0
1977 16:30:42.192631
1978 16:30:42.192725 RX Vref 0 -> 0, step: 1
1979 16:30:42.192820
1980 16:30:42.192917 RX Delay -95 -> 252, step: 8
1981 16:30:42.193013 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1982 16:30:42.193109 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1983 16:30:42.193205 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1984 16:30:42.193338 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1985 16:30:42.193435 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1986 16:30:42.193531 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1987 16:30:42.193626 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1988 16:30:42.193721 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1989 16:30:42.193816 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1990 16:30:42.193915 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1991 16:30:42.194011 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1992 16:30:42.194106 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1993 16:30:42.194202 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1994 16:30:42.194299 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1995 16:30:42.194393 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1996 16:30:42.194488 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1997 16:30:42.194582 ==
1998 16:30:42.194678 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 16:30:42.194774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 16:30:42.194872 ==
2001 16:30:42.194968 DQS Delay:
2002 16:30:42.195064 DQS0 = 0, DQS1 = 0
2003 16:30:42.195159 DQM Delay:
2004 16:30:42.195253 DQM0 = 86, DQM1 = 82
2005 16:30:42.195346 DQ Delay:
2006 16:30:42.195443 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2007 16:30:42.195539 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2008 16:30:42.195634 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2009 16:30:42.195728 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2010 16:30:42.195824
2011 16:30:42.195919
2012 16:30:42.196013 [DQSOSCAuto] RK1, (LSB)MR18= 0x243f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2013 16:30:42.196110 CH1 RK1: MR19=606, MR18=243F
2014 16:30:42.196209 CH1_RK1: MR19=0x606, MR18=0x243F, DQSOSC=393, MR23=63, INC=95, DEC=63
2015 16:30:42.196306 [RxdqsGatingPostProcess] freq 800
2016 16:30:42.196401 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2017 16:30:42.196497 Pre-setting of DQS Precalculation
2018 16:30:42.196593 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2019 16:30:42.196689 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2020 16:30:42.196787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2021 16:30:42.196883
2022 16:30:42.196978
2023 16:30:42.197071 [Calibration Summary] 1600 Mbps
2024 16:30:42.197183 CH 0, Rank 0
2025 16:30:42.197299 SW Impedance : PASS
2026 16:30:42.197395 DUTY Scan : NO K
2027 16:30:42.197491 ZQ Calibration : PASS
2028 16:30:42.197587 Jitter Meter : NO K
2029 16:30:42.197681 CBT Training : PASS
2030 16:30:42.197776 Write leveling : PASS
2031 16:30:42.197872 RX DQS gating : PASS
2032 16:30:42.197967 RX DQ/DQS(RDDQC) : PASS
2033 16:30:42.198055 TX DQ/DQS : PASS
2034 16:30:42.198132 RX DATLAT : PASS
2035 16:30:42.198205 RX DQ/DQS(Engine): PASS
2036 16:30:42.198278 TX OE : NO K
2037 16:30:42.198351 All Pass.
2038 16:30:42.198443
2039 16:30:42.198535 CH 0, Rank 1
2040 16:30:42.198628 SW Impedance : PASS
2041 16:30:42.198720 DUTY Scan : NO K
2042 16:30:42.198812 ZQ Calibration : PASS
2043 16:30:42.198904 Jitter Meter : NO K
2044 16:30:42.198995 CBT Training : PASS
2045 16:30:42.199087 Write leveling : PASS
2046 16:30:42.199178 RX DQS gating : PASS
2047 16:30:42.199270 RX DQ/DQS(RDDQC) : PASS
2048 16:30:42.199361 TX DQ/DQS : PASS
2049 16:30:42.199453 RX DATLAT : PASS
2050 16:30:42.199544 RX DQ/DQS(Engine): PASS
2051 16:30:42.199635 TX OE : NO K
2052 16:30:42.199727 All Pass.
2053 16:30:42.199823
2054 16:30:42.199923 CH 1, Rank 0
2055 16:30:42.200012 SW Impedance : PASS
2056 16:30:42.200097 DUTY Scan : NO K
2057 16:30:42.200181 ZQ Calibration : PASS
2058 16:30:42.200264 Jitter Meter : NO K
2059 16:30:42.200378 CBT Training : PASS
2060 16:30:42.200460 Write leveling : PASS
2061 16:30:42.200542 RX DQS gating : PASS
2062 16:30:42.200624 RX DQ/DQS(RDDQC) : PASS
2063 16:30:42.200706 TX DQ/DQS : PASS
2064 16:30:42.200788 RX DATLAT : PASS
2065 16:30:42.200873 RX DQ/DQS(Engine): PASS
2066 16:30:42.200955 TX OE : NO K
2067 16:30:42.201037 All Pass.
2068 16:30:42.201119
2069 16:30:42.201200 CH 1, Rank 1
2070 16:30:42.201310 SW Impedance : PASS
2071 16:30:42.201407 DUTY Scan : NO K
2072 16:30:42.201489 ZQ Calibration : PASS
2073 16:30:42.201571 Jitter Meter : NO K
2074 16:30:42.201652 CBT Training : PASS
2075 16:30:42.201734 Write leveling : PASS
2076 16:30:42.201815 RX DQS gating : PASS
2077 16:30:42.201897 RX DQ/DQS(RDDQC) : PASS
2078 16:30:42.201979 TX DQ/DQS : PASS
2079 16:30:42.202061 RX DATLAT : PASS
2080 16:30:42.202143 RX DQ/DQS(Engine): PASS
2081 16:30:42.202224 TX OE : NO K
2082 16:30:42.202305 All Pass.
2083 16:30:42.202386
2084 16:30:42.202501 DramC Write-DBI off
2085 16:30:42.202882 PER_BANK_REFRESH: Hybrid Mode
2086 16:30:42.202993 TX_TRACKING: ON
2087 16:30:42.203086 [GetDramInforAfterCalByMRR] Vendor 6.
2088 16:30:42.203179 [GetDramInforAfterCalByMRR] Revision 606.
2089 16:30:42.203271 [GetDramInforAfterCalByMRR] Revision 2 0.
2090 16:30:42.203363 MR0 0x3b3b
2091 16:30:42.203455 MR8 0x5151
2092 16:30:42.203547 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2093 16:30:42.203640
2094 16:30:42.203728 MR0 0x3b3b
2095 16:30:42.203810 MR8 0x5151
2096 16:30:42.203893 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 16:30:42.203975
2098 16:30:42.204059 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2099 16:30:42.204142 [FAST_K] Save calibration result to emmc
2100 16:30:42.204225 [FAST_K] Save calibration result to emmc
2101 16:30:42.204308 dram_init: config_dvfs: 1
2102 16:30:42.204390 dramc_set_vcore_voltage set vcore to 662500
2103 16:30:42.204472 Read voltage for 1200, 2
2104 16:30:42.204554 Vio18 = 0
2105 16:30:42.204635 Vcore = 662500
2106 16:30:42.204717 Vdram = 0
2107 16:30:42.204798 Vddq = 0
2108 16:30:42.204879 Vmddr = 0
2109 16:30:42.204961 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2110 16:30:42.205044 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2111 16:30:42.205126 MEM_TYPE=3, freq_sel=15
2112 16:30:42.205213 sv_algorithm_assistance_LP4_1600
2113 16:30:42.205342 ============ PULL DRAM RESETB DOWN ============
2114 16:30:42.205421 ========== PULL DRAM RESETB DOWN end =========
2115 16:30:42.205512 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2116 16:30:42.205598 ===================================
2117 16:30:42.205682 LPDDR4 DRAM CONFIGURATION
2118 16:30:42.205766 ===================================
2119 16:30:42.205848 EX_ROW_EN[0] = 0x0
2120 16:30:42.205930 EX_ROW_EN[1] = 0x0
2121 16:30:42.206012 LP4Y_EN = 0x0
2122 16:30:42.206093 WORK_FSP = 0x0
2123 16:30:42.206175 WL = 0x4
2124 16:30:42.206256 RL = 0x4
2125 16:30:42.206337 BL = 0x2
2126 16:30:42.206418 RPST = 0x0
2127 16:30:42.206500 RD_PRE = 0x0
2128 16:30:42.206581 WR_PRE = 0x1
2129 16:30:42.206662 WR_PST = 0x0
2130 16:30:42.206744 DBI_WR = 0x0
2131 16:30:42.206825 DBI_RD = 0x0
2132 16:30:42.206919 OTF = 0x1
2133 16:30:42.207041 ===================================
2134 16:30:42.207123 ===================================
2135 16:30:42.207205 ANA top config
2136 16:30:42.207287 ===================================
2137 16:30:42.207369 DLL_ASYNC_EN = 0
2138 16:30:42.207451 ALL_SLAVE_EN = 0
2139 16:30:42.207533 NEW_RANK_MODE = 1
2140 16:30:42.207616 DLL_IDLE_MODE = 1
2141 16:30:42.207697 LP45_APHY_COMB_EN = 1
2142 16:30:42.207779 TX_ODT_DIS = 1
2143 16:30:42.207861 NEW_8X_MODE = 1
2144 16:30:42.207943 ===================================
2145 16:30:42.208026 ===================================
2146 16:30:42.208108 data_rate = 2400
2147 16:30:42.208190 CKR = 1
2148 16:30:42.208272 DQ_P2S_RATIO = 8
2149 16:30:42.208391 ===================================
2150 16:30:42.208506 CA_P2S_RATIO = 8
2151 16:30:42.208587 DQ_CA_OPEN = 0
2152 16:30:42.208669 DQ_SEMI_OPEN = 0
2153 16:30:42.208756 CA_SEMI_OPEN = 0
2154 16:30:42.208840 CA_FULL_RATE = 0
2155 16:30:42.208936 DQ_CKDIV4_EN = 0
2156 16:30:42.209059 CA_CKDIV4_EN = 0
2157 16:30:42.209137 CA_PREDIV_EN = 0
2158 16:30:42.209239 PH8_DLY = 17
2159 16:30:42.209326 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2160 16:30:42.209382 DQ_AAMCK_DIV = 4
2161 16:30:42.209437 CA_AAMCK_DIV = 4
2162 16:30:42.209490 CA_ADMCK_DIV = 4
2163 16:30:42.209545 DQ_TRACK_CA_EN = 0
2164 16:30:42.209598 CA_PICK = 1200
2165 16:30:42.209651 CA_MCKIO = 1200
2166 16:30:42.209704 MCKIO_SEMI = 0
2167 16:30:42.209758 PLL_FREQ = 2366
2168 16:30:42.209810 DQ_UI_PI_RATIO = 32
2169 16:30:42.209863 CA_UI_PI_RATIO = 0
2170 16:30:42.209916 ===================================
2171 16:30:42.209969 ===================================
2172 16:30:42.210022 memory_type:LPDDR4
2173 16:30:42.210075 GP_NUM : 10
2174 16:30:42.210127 SRAM_EN : 1
2175 16:30:42.210180 MD32_EN : 0
2176 16:30:42.210233 ===================================
2177 16:30:42.210286 [ANA_INIT] >>>>>>>>>>>>>>
2178 16:30:42.210339 <<<<<< [CONFIGURE PHASE]: ANA_TX
2179 16:30:42.210392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2180 16:30:42.210446 ===================================
2181 16:30:42.210499 data_rate = 2400,PCW = 0X5b00
2182 16:30:42.210552 ===================================
2183 16:30:42.210604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2184 16:30:42.210657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2185 16:30:42.210711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 16:30:42.210764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2187 16:30:42.210818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2188 16:30:42.210871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2189 16:30:42.210956 [ANA_INIT] flow start
2190 16:30:42.211039 [ANA_INIT] PLL >>>>>>>>
2191 16:30:42.211094 [ANA_INIT] PLL <<<<<<<<
2192 16:30:42.211147 [ANA_INIT] MIDPI >>>>>>>>
2193 16:30:42.211200 [ANA_INIT] MIDPI <<<<<<<<
2194 16:30:42.211253 [ANA_INIT] DLL >>>>>>>>
2195 16:30:42.211306 [ANA_INIT] DLL <<<<<<<<
2196 16:30:42.211359 [ANA_INIT] flow end
2197 16:30:42.211411 ============ LP4 DIFF to SE enter ============
2198 16:30:42.211466 ============ LP4 DIFF to SE exit ============
2199 16:30:42.211520 [ANA_INIT] <<<<<<<<<<<<<
2200 16:30:42.211573 [Flow] Enable top DCM control >>>>>
2201 16:30:42.211626 [Flow] Enable top DCM control <<<<<
2202 16:30:42.211679 Enable DLL master slave shuffle
2203 16:30:42.211733 ==============================================================
2204 16:30:42.211787 Gating Mode config
2205 16:30:42.211839 ==============================================================
2206 16:30:42.211892 Config description:
2207 16:30:42.211945 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2208 16:30:42.211999 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2209 16:30:42.212257 SELPH_MODE 0: By rank 1: By Phase
2210 16:30:42.212318 ==============================================================
2211 16:30:42.212405 GAT_TRACK_EN = 1
2212 16:30:42.212527 RX_GATING_MODE = 2
2213 16:30:42.212608 RX_GATING_TRACK_MODE = 2
2214 16:30:42.212691 SELPH_MODE = 1
2215 16:30:42.212829 PICG_EARLY_EN = 1
2216 16:30:42.212937 VALID_LAT_VALUE = 1
2217 16:30:42.213066 ==============================================================
2218 16:30:42.213177 Enter into Gating configuration >>>>
2219 16:30:42.213287 Exit from Gating configuration <<<<
2220 16:30:42.213381 Enter into DVFS_PRE_config >>>>>
2221 16:30:42.213475 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2222 16:30:42.213570 Exit from DVFS_PRE_config <<<<<
2223 16:30:42.213663 Enter into PICG configuration >>>>
2224 16:30:42.213755 Exit from PICG configuration <<<<
2225 16:30:42.213848 [RX_INPUT] configuration >>>>>
2226 16:30:42.213940 [RX_INPUT] configuration <<<<<
2227 16:30:42.214031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2228 16:30:42.214124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2229 16:30:42.214216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 16:30:42.214309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 16:30:42.214401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 16:30:42.214493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 16:30:42.214584 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2234 16:30:42.214676 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2235 16:30:42.214767 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2236 16:30:42.214859 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2237 16:30:42.214952 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2238 16:30:42.215044 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2239 16:30:42.215136 ===================================
2240 16:30:42.215229 LPDDR4 DRAM CONFIGURATION
2241 16:30:42.215321 ===================================
2242 16:30:42.215413 EX_ROW_EN[0] = 0x0
2243 16:30:42.215504 EX_ROW_EN[1] = 0x0
2244 16:30:42.215595 LP4Y_EN = 0x0
2245 16:30:42.215687 WORK_FSP = 0x0
2246 16:30:42.215778 WL = 0x4
2247 16:30:42.215869 RL = 0x4
2248 16:30:42.215991 BL = 0x2
2249 16:30:42.216081 RPST = 0x0
2250 16:30:42.216172 RD_PRE = 0x0
2251 16:30:42.216263 WR_PRE = 0x1
2252 16:30:42.216353 WR_PST = 0x0
2253 16:30:42.216444 DBI_WR = 0x0
2254 16:30:42.216534 DBI_RD = 0x0
2255 16:30:42.216625 OTF = 0x1
2256 16:30:42.216716 ===================================
2257 16:30:42.216808 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2258 16:30:42.216899 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2259 16:30:42.216991 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 16:30:42.217083 ===================================
2261 16:30:42.217174 LPDDR4 DRAM CONFIGURATION
2262 16:30:42.217271 ===================================
2263 16:30:42.217401 EX_ROW_EN[0] = 0x10
2264 16:30:42.217492 EX_ROW_EN[1] = 0x0
2265 16:30:42.217583 LP4Y_EN = 0x0
2266 16:30:42.217675 WORK_FSP = 0x0
2267 16:30:42.217766 WL = 0x4
2268 16:30:42.217857 RL = 0x4
2269 16:30:42.217947 BL = 0x2
2270 16:30:42.218039 RPST = 0x0
2271 16:30:42.218129 RD_PRE = 0x0
2272 16:30:42.218220 WR_PRE = 0x1
2273 16:30:42.218311 WR_PST = 0x0
2274 16:30:42.218401 DBI_WR = 0x0
2275 16:30:42.218491 DBI_RD = 0x0
2276 16:30:42.218582 OTF = 0x1
2277 16:30:42.218673 ===================================
2278 16:30:42.218765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2279 16:30:42.218857 ==
2280 16:30:42.218982 Dram Type= 6, Freq= 0, CH_0, rank 0
2281 16:30:42.219074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2282 16:30:42.219166 ==
2283 16:30:42.219258 [Duty_Offset_Calibration]
2284 16:30:42.219348 B0:2 B1:0 CA:4
2285 16:30:42.219441
2286 16:30:42.219531 [DutyScan_Calibration_Flow] k_type=0
2287 16:30:42.219614
2288 16:30:42.219696 ==CLK 0==
2289 16:30:42.219779 Final CLK duty delay cell = -4
2290 16:30:42.219863 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2291 16:30:42.219945 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2292 16:30:42.220027 [-4] AVG Duty = 4937%(X100)
2293 16:30:42.220109
2294 16:30:42.220190 CH0 CLK Duty spec in!! Max-Min= 187%
2295 16:30:42.220272 [DutyScan_Calibration_Flow] ====Done====
2296 16:30:42.220354
2297 16:30:42.220435 [DutyScan_Calibration_Flow] k_type=1
2298 16:30:42.220516
2299 16:30:42.220636 ==DQS 0 ==
2300 16:30:42.220717 Final DQS duty delay cell = 0
2301 16:30:42.220800 [0] MAX Duty = 5156%(X100), DQS PI = 18
2302 16:30:42.220882 [0] MIN Duty = 5093%(X100), DQS PI = 0
2303 16:30:42.220963 [0] AVG Duty = 5124%(X100)
2304 16:30:42.221044
2305 16:30:42.221125 ==DQS 1 ==
2306 16:30:42.221206 Final DQS duty delay cell = 0
2307 16:30:42.221330 [0] MAX Duty = 5093%(X100), DQS PI = 4
2308 16:30:42.221414 [0] MIN Duty = 4969%(X100), DQS PI = 62
2309 16:30:42.221495 [0] AVG Duty = 5031%(X100)
2310 16:30:42.221576
2311 16:30:42.221658 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2312 16:30:42.221739
2313 16:30:42.221821 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2314 16:30:42.221902 [DutyScan_Calibration_Flow] ====Done====
2315 16:30:42.221984
2316 16:30:42.222065 [DutyScan_Calibration_Flow] k_type=3
2317 16:30:42.222146
2318 16:30:42.222227 ==DQM 0 ==
2319 16:30:42.222308 Final DQM duty delay cell = 0
2320 16:30:42.222391 [0] MAX Duty = 5125%(X100), DQS PI = 20
2321 16:30:42.222473 [0] MIN Duty = 4844%(X100), DQS PI = 50
2322 16:30:42.222555 [0] AVG Duty = 4984%(X100)
2323 16:30:42.222636
2324 16:30:42.222735 ==DQM 1 ==
2325 16:30:42.222831 Final DQM duty delay cell = 0
2326 16:30:42.222914 [0] MAX Duty = 4969%(X100), DQS PI = 2
2327 16:30:42.222995 [0] MIN Duty = 4875%(X100), DQS PI = 20
2328 16:30:42.223077 [0] AVG Duty = 4922%(X100)
2329 16:30:42.223199
2330 16:30:42.223280 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2331 16:30:42.223361
2332 16:30:42.223442 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2333 16:30:42.223564 [DutyScan_Calibration_Flow] ====Done====
2334 16:30:42.223645
2335 16:30:42.223726 [DutyScan_Calibration_Flow] k_type=2
2336 16:30:42.223807
2337 16:30:42.223889 ==DQ 0 ==
2338 16:30:42.223971 Final DQ duty delay cell = 0
2339 16:30:42.224124 [0] MAX Duty = 5125%(X100), DQS PI = 18
2340 16:30:42.224476 [0] MIN Duty = 4938%(X100), DQS PI = 58
2341 16:30:42.224623 [0] AVG Duty = 5031%(X100)
2342 16:30:42.224707
2343 16:30:42.224851 ==DQ 1 ==
2344 16:30:42.224935 Final DQ duty delay cell = 0
2345 16:30:42.225019 [0] MAX Duty = 5125%(X100), DQS PI = 6
2346 16:30:42.225117 [0] MIN Duty = 4938%(X100), DQS PI = 16
2347 16:30:42.225199 [0] AVG Duty = 5031%(X100)
2348 16:30:42.225321
2349 16:30:42.225436 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2350 16:30:42.225518
2351 16:30:42.225599 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2352 16:30:42.225713 [DutyScan_Calibration_Flow] ====Done====
2353 16:30:42.225795 ==
2354 16:30:42.225877 Dram Type= 6, Freq= 0, CH_1, rank 0
2355 16:30:42.225991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 16:30:42.226114 ==
2357 16:30:42.226196 [Duty_Offset_Calibration]
2358 16:30:42.226310 B0:0 B1:-1 CA:3
2359 16:30:42.226392
2360 16:30:42.226473 [DutyScan_Calibration_Flow] k_type=0
2361 16:30:42.226554
2362 16:30:42.226634 ==CLK 0==
2363 16:30:42.226716 Final CLK duty delay cell = -4
2364 16:30:42.226798 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2365 16:30:42.226897 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2366 16:30:42.226993 [-4] AVG Duty = 4938%(X100)
2367 16:30:42.227074
2368 16:30:42.227170 CH1 CLK Duty spec in!! Max-Min= 124%
2369 16:30:42.227266 [DutyScan_Calibration_Flow] ====Done====
2370 16:30:42.227348
2371 16:30:42.227429 [DutyScan_Calibration_Flow] k_type=1
2372 16:30:42.227510
2373 16:30:42.227591 ==DQS 0 ==
2374 16:30:42.227672 Final DQS duty delay cell = 0
2375 16:30:42.227755 [0] MAX Duty = 5187%(X100), DQS PI = 28
2376 16:30:42.227836 [0] MIN Duty = 4907%(X100), DQS PI = 38
2377 16:30:42.227918 [0] AVG Duty = 5047%(X100)
2378 16:30:42.227998
2379 16:30:42.228078 ==DQS 1 ==
2380 16:30:42.228161 Final DQS duty delay cell = 0
2381 16:30:42.228274 [0] MAX Duty = 5156%(X100), DQS PI = 8
2382 16:30:42.228356 [0] MIN Duty = 5031%(X100), DQS PI = 18
2383 16:30:42.228437 [0] AVG Duty = 5093%(X100)
2384 16:30:42.228517
2385 16:30:42.228599 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2386 16:30:42.228679
2387 16:30:42.228761 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2388 16:30:42.228859 [DutyScan_Calibration_Flow] ====Done====
2389 16:30:42.229000
2390 16:30:42.229114 [DutyScan_Calibration_Flow] k_type=3
2391 16:30:42.229197
2392 16:30:42.229283 ==DQM 0 ==
2393 16:30:42.229354 Final DQM duty delay cell = 0
2394 16:30:42.229439 [0] MAX Duty = 5031%(X100), DQS PI = 28
2395 16:30:42.229491 [0] MIN Duty = 4813%(X100), DQS PI = 38
2396 16:30:42.229543 [0] AVG Duty = 4922%(X100)
2397 16:30:42.229595
2398 16:30:42.229647 ==DQM 1 ==
2399 16:30:42.229699 Final DQM duty delay cell = 0
2400 16:30:42.229752 [0] MAX Duty = 4969%(X100), DQS PI = 32
2401 16:30:42.229805 [0] MIN Duty = 4813%(X100), DQS PI = 0
2402 16:30:42.229857 [0] AVG Duty = 4891%(X100)
2403 16:30:42.229909
2404 16:30:42.229960 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2405 16:30:42.230013
2406 16:30:42.230065 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2407 16:30:42.230117 [DutyScan_Calibration_Flow] ====Done====
2408 16:30:42.230169
2409 16:30:42.230221 [DutyScan_Calibration_Flow] k_type=2
2410 16:30:42.230273
2411 16:30:42.230325 ==DQ 0 ==
2412 16:30:42.230377 Final DQ duty delay cell = -4
2413 16:30:42.230429 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2414 16:30:42.230481 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2415 16:30:42.230533 [-4] AVG Duty = 4937%(X100)
2416 16:30:42.230585
2417 16:30:42.230636 ==DQ 1 ==
2418 16:30:42.230688 Final DQ duty delay cell = 0
2419 16:30:42.230741 [0] MAX Duty = 5031%(X100), DQS PI = 34
2420 16:30:42.230793 [0] MIN Duty = 4844%(X100), DQS PI = 62
2421 16:30:42.230845 [0] AVG Duty = 4937%(X100)
2422 16:30:42.230897
2423 16:30:42.230950 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2424 16:30:42.231002
2425 16:30:42.231054 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2426 16:30:42.231105 [DutyScan_Calibration_Flow] ====Done====
2427 16:30:42.231157 nWR fixed to 30
2428 16:30:42.231210 [ModeRegInit_LP4] CH0 RK0
2429 16:30:42.231261 [ModeRegInit_LP4] CH0 RK1
2430 16:30:42.231314 [ModeRegInit_LP4] CH1 RK0
2431 16:30:42.231365 [ModeRegInit_LP4] CH1 RK1
2432 16:30:42.231417 match AC timing 7
2433 16:30:42.231469 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2434 16:30:42.231521 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2435 16:30:42.231574 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2436 16:30:42.231626 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2437 16:30:42.231679 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2438 16:30:42.231731 ==
2439 16:30:42.231783 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 16:30:42.231835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 16:30:42.231887 ==
2442 16:30:42.231939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2443 16:30:42.231992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2444 16:30:42.232045 [CA 0] Center 39 (9~70) winsize 62
2445 16:30:42.232097 [CA 1] Center 39 (8~70) winsize 63
2446 16:30:42.232149 [CA 2] Center 35 (5~66) winsize 62
2447 16:30:42.232202 [CA 3] Center 35 (5~66) winsize 62
2448 16:30:42.232254 [CA 4] Center 33 (3~64) winsize 62
2449 16:30:42.232305 [CA 5] Center 33 (3~64) winsize 62
2450 16:30:42.232357
2451 16:30:42.232408 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2452 16:30:42.232460
2453 16:30:42.232512 [CATrainingPosCal] consider 1 rank data
2454 16:30:42.232564 u2DelayCellTimex100 = 270/100 ps
2455 16:30:42.232616 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2456 16:30:42.232718 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2457 16:30:42.232807 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2458 16:30:42.232878 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2459 16:30:42.232932 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2460 16:30:42.232985 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2461 16:30:42.233038
2462 16:30:42.233091 CA PerBit enable=1, Macro0, CA PI delay=33
2463 16:30:42.233143
2464 16:30:42.233196 [CBTSetCACLKResult] CA Dly = 33
2465 16:30:42.233248 CS Dly: 7 (0~38)
2466 16:30:42.233337 ==
2467 16:30:42.233390 Dram Type= 6, Freq= 0, CH_0, rank 1
2468 16:30:42.233443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 16:30:42.233496 ==
2470 16:30:42.233548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 16:30:42.233602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 16:30:42.233655 [CA 0] Center 39 (9~70) winsize 62
2473 16:30:42.233707 [CA 1] Center 39 (9~70) winsize 62
2474 16:30:42.233759 [CA 2] Center 35 (5~66) winsize 62
2475 16:30:42.233812 [CA 3] Center 35 (5~66) winsize 62
2476 16:30:42.233864 [CA 4] Center 34 (4~65) winsize 62
2477 16:30:42.233917 [CA 5] Center 33 (3~64) winsize 62
2478 16:30:42.233969
2479 16:30:42.234021 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2480 16:30:42.234073
2481 16:30:42.234125 [CATrainingPosCal] consider 2 rank data
2482 16:30:42.234177 u2DelayCellTimex100 = 270/100 ps
2483 16:30:42.234229 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2484 16:30:42.234487 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 16:30:42.234546 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 16:30:42.234599 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 16:30:42.234690 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2488 16:30:42.234743 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2489 16:30:42.234795
2490 16:30:42.234848 CA PerBit enable=1, Macro0, CA PI delay=33
2491 16:30:42.234901
2492 16:30:42.234953 [CBTSetCACLKResult] CA Dly = 33
2493 16:30:42.235005 CS Dly: 8 (0~41)
2494 16:30:42.235057
2495 16:30:42.235109 ----->DramcWriteLeveling(PI) begin...
2496 16:30:42.235163 ==
2497 16:30:42.235215 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 16:30:42.235267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 16:30:42.235321 ==
2500 16:30:42.235373 Write leveling (Byte 0): 32 => 32
2501 16:30:42.235425 Write leveling (Byte 1): 27 => 27
2502 16:30:42.235478 DramcWriteLeveling(PI) end<-----
2503 16:30:42.235530
2504 16:30:42.235582 ==
2505 16:30:42.235635 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 16:30:42.235687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 16:30:42.235740 ==
2508 16:30:42.235792 [Gating] SW mode calibration
2509 16:30:42.235845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2510 16:30:42.235898 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2511 16:30:42.235951 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2512 16:30:42.236004 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2513 16:30:42.236066 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 16:30:42.236141 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 16:30:42.236196 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 16:30:42.236249 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 16:30:42.236302 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2518 16:30:42.236354 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2519 16:30:42.236406 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
2520 16:30:42.236459 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 16:30:42.236511 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 16:30:42.236564 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 16:30:42.236616 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 16:30:42.236668 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 16:30:42.236720 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2526 16:30:42.236772 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2527 16:30:42.236825 1 1 0 | B1->B0 | 2e2d 4646 | 1 0 | (1 1) (0 0)
2528 16:30:42.236878 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2529 16:30:42.236930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 16:30:42.236982 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 16:30:42.237034 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 16:30:42.237086 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 16:30:42.237138 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 16:30:42.237190 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 16:30:42.237242 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2536 16:30:42.237332 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 16:30:42.237386 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 16:30:42.237438 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 16:30:42.237491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 16:30:42.237543 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 16:30:42.237595 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 16:30:42.237647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 16:30:42.237699 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 16:30:42.237751 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 16:30:42.237803 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 16:30:42.237855 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 16:30:42.237907 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 16:30:42.237959 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 16:30:42.238011 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 16:30:42.238064 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2551 16:30:42.238116 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2552 16:30:42.238168 Total UI for P1: 0, mck2ui 16
2553 16:30:42.238221 best dqsien dly found for B0: ( 1, 3, 28)
2554 16:30:42.238275 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 16:30:42.238327 Total UI for P1: 0, mck2ui 16
2556 16:30:42.238379 best dqsien dly found for B1: ( 1, 4, 0)
2557 16:30:42.238431 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2558 16:30:42.238483 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2559 16:30:42.238535
2560 16:30:42.238587 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2561 16:30:42.238639 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2562 16:30:42.238691 [Gating] SW calibration Done
2563 16:30:42.238743 ==
2564 16:30:42.238795 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 16:30:42.238847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 16:30:42.238899 ==
2567 16:30:42.238951 RX Vref Scan: 0
2568 16:30:42.239002
2569 16:30:42.239055 RX Vref 0 -> 0, step: 1
2570 16:30:42.239106
2571 16:30:42.239158 RX Delay -40 -> 252, step: 8
2572 16:30:42.239249 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2573 16:30:42.239302 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2574 16:30:42.239355 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2575 16:30:42.239407 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2576 16:30:42.239460 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2577 16:30:42.239511 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2578 16:30:42.239563 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2579 16:30:42.239615 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2580 16:30:42.239667 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2581 16:30:42.239719 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2582 16:30:42.239771 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2583 16:30:42.239823 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2584 16:30:42.239880 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2585 16:30:42.240200 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2586 16:30:42.240262 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2587 16:30:42.240316 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2588 16:30:42.240370 ==
2589 16:30:42.240423 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 16:30:42.240476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 16:30:42.240529 ==
2592 16:30:42.240581 DQS Delay:
2593 16:30:42.240633 DQS0 = 0, DQS1 = 0
2594 16:30:42.240685 DQM Delay:
2595 16:30:42.240737 DQM0 = 117, DQM1 = 107
2596 16:30:42.240789 DQ Delay:
2597 16:30:42.240841 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2598 16:30:42.240894 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2599 16:30:42.240945 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2600 16:30:42.240997 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2601 16:30:42.241049
2602 16:30:42.241101
2603 16:30:42.241152 ==
2604 16:30:42.241205 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 16:30:42.241263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 16:30:42.241355 ==
2607 16:30:42.241406
2608 16:30:42.241458
2609 16:30:42.241510 TX Vref Scan disable
2610 16:30:42.241562 == TX Byte 0 ==
2611 16:30:42.241614 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2612 16:30:42.241667 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2613 16:30:42.241720 == TX Byte 1 ==
2614 16:30:42.241772 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2615 16:30:42.241825 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2616 16:30:42.241880 ==
2617 16:30:42.241933 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 16:30:42.241985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 16:30:42.242038 ==
2620 16:30:42.242090 TX Vref=22, minBit 10, minWin=25, winSum=415
2621 16:30:42.242142 TX Vref=24, minBit 10, minWin=25, winSum=419
2622 16:30:42.242195 TX Vref=26, minBit 1, minWin=25, winSum=424
2623 16:30:42.242247 TX Vref=28, minBit 10, minWin=25, winSum=430
2624 16:30:42.242300 TX Vref=30, minBit 0, minWin=26, winSum=432
2625 16:30:42.242352 TX Vref=32, minBit 13, minWin=25, winSum=427
2626 16:30:42.242404 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2627 16:30:42.242456
2628 16:30:42.242508 Final TX Range 1 Vref 30
2629 16:30:42.242561
2630 16:30:42.242612 ==
2631 16:30:42.242664 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 16:30:42.242717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 16:30:42.242769 ==
2634 16:30:42.242821
2635 16:30:42.242872
2636 16:30:42.242923 TX Vref Scan disable
2637 16:30:42.242975 == TX Byte 0 ==
2638 16:30:42.243027 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2639 16:30:42.243080 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2640 16:30:42.243132 == TX Byte 1 ==
2641 16:30:42.243184 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2642 16:30:42.243236 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2643 16:30:42.243288
2644 16:30:42.243339 [DATLAT]
2645 16:30:42.243391 Freq=1200, CH0 RK0
2646 16:30:42.243444
2647 16:30:42.243495 DATLAT Default: 0xd
2648 16:30:42.243547 0, 0xFFFF, sum = 0
2649 16:30:42.243600 1, 0xFFFF, sum = 0
2650 16:30:42.243654 2, 0xFFFF, sum = 0
2651 16:30:42.243706 3, 0xFFFF, sum = 0
2652 16:30:42.243759 4, 0xFFFF, sum = 0
2653 16:30:42.243811 5, 0xFFFF, sum = 0
2654 16:30:42.243864 6, 0xFFFF, sum = 0
2655 16:30:42.243917 7, 0xFFFF, sum = 0
2656 16:30:42.243970 8, 0xFFFF, sum = 0
2657 16:30:42.244023 9, 0xFFFF, sum = 0
2658 16:30:42.244075 10, 0xFFFF, sum = 0
2659 16:30:42.244128 11, 0xFFFF, sum = 0
2660 16:30:42.244181 12, 0x0, sum = 1
2661 16:30:42.244233 13, 0x0, sum = 2
2662 16:30:42.244286 14, 0x0, sum = 3
2663 16:30:42.244338 15, 0x0, sum = 4
2664 16:30:42.244391 best_step = 13
2665 16:30:42.244442
2666 16:30:42.244493 ==
2667 16:30:42.244545 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 16:30:42.244597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 16:30:42.244649 ==
2670 16:30:42.244701 RX Vref Scan: 1
2671 16:30:42.244753
2672 16:30:42.244804 Set Vref Range= 32 -> 127
2673 16:30:42.244856
2674 16:30:42.244907 RX Vref 32 -> 127, step: 1
2675 16:30:42.244959
2676 16:30:42.245010 RX Delay -21 -> 252, step: 4
2677 16:30:42.245062
2678 16:30:42.245114 Set Vref, RX VrefLevel [Byte0]: 32
2679 16:30:42.245166 [Byte1]: 32
2680 16:30:42.245218
2681 16:30:42.245276 Set Vref, RX VrefLevel [Byte0]: 33
2682 16:30:42.245329 [Byte1]: 33
2683 16:30:42.245382
2684 16:30:42.245433 Set Vref, RX VrefLevel [Byte0]: 34
2685 16:30:42.245485 [Byte1]: 34
2686 16:30:42.245537
2687 16:30:42.245588 Set Vref, RX VrefLevel [Byte0]: 35
2688 16:30:42.245647 [Byte1]: 35
2689 16:30:42.245759
2690 16:30:42.245815 Set Vref, RX VrefLevel [Byte0]: 36
2691 16:30:42.245867 [Byte1]: 36
2692 16:30:42.245920
2693 16:30:42.245971 Set Vref, RX VrefLevel [Byte0]: 37
2694 16:30:42.246024 [Byte1]: 37
2695 16:30:42.246076
2696 16:30:42.246128 Set Vref, RX VrefLevel [Byte0]: 38
2697 16:30:42.246180 [Byte1]: 38
2698 16:30:42.246232
2699 16:30:42.246283 Set Vref, RX VrefLevel [Byte0]: 39
2700 16:30:42.246336 [Byte1]: 39
2701 16:30:42.246389
2702 16:30:42.246440 Set Vref, RX VrefLevel [Byte0]: 40
2703 16:30:42.246493 [Byte1]: 40
2704 16:30:42.246545
2705 16:30:42.246596 Set Vref, RX VrefLevel [Byte0]: 41
2706 16:30:42.246648 [Byte1]: 41
2707 16:30:42.246700
2708 16:30:42.246752 Set Vref, RX VrefLevel [Byte0]: 42
2709 16:30:42.246804 [Byte1]: 42
2710 16:30:42.246856
2711 16:30:42.246907 Set Vref, RX VrefLevel [Byte0]: 43
2712 16:30:42.246959 [Byte1]: 43
2713 16:30:42.247011
2714 16:30:42.247062 Set Vref, RX VrefLevel [Byte0]: 44
2715 16:30:42.247114 [Byte1]: 44
2716 16:30:42.247165
2717 16:30:42.247217 Set Vref, RX VrefLevel [Byte0]: 45
2718 16:30:42.247269 [Byte1]: 45
2719 16:30:42.247320
2720 16:30:42.247372 Set Vref, RX VrefLevel [Byte0]: 46
2721 16:30:42.247424 [Byte1]: 46
2722 16:30:42.247476
2723 16:30:42.247527 Set Vref, RX VrefLevel [Byte0]: 47
2724 16:30:42.247579 [Byte1]: 47
2725 16:30:42.247631
2726 16:30:42.247683 Set Vref, RX VrefLevel [Byte0]: 48
2727 16:30:42.247736 [Byte1]: 48
2728 16:30:42.247788
2729 16:30:42.247839 Set Vref, RX VrefLevel [Byte0]: 49
2730 16:30:42.247892 [Byte1]: 49
2731 16:30:42.247944
2732 16:30:42.247996 Set Vref, RX VrefLevel [Byte0]: 50
2733 16:30:42.248047 [Byte1]: 50
2734 16:30:42.248099
2735 16:30:42.248150 Set Vref, RX VrefLevel [Byte0]: 51
2736 16:30:42.248203 [Byte1]: 51
2737 16:30:42.248254
2738 16:30:42.248306 Set Vref, RX VrefLevel [Byte0]: 52
2739 16:30:42.248358 [Byte1]: 52
2740 16:30:42.248410
2741 16:30:42.248462 Set Vref, RX VrefLevel [Byte0]: 53
2742 16:30:42.248514 [Byte1]: 53
2743 16:30:42.248567
2744 16:30:42.248618 Set Vref, RX VrefLevel [Byte0]: 54
2745 16:30:42.248670 [Byte1]: 54
2746 16:30:42.248721
2747 16:30:42.248790 Set Vref, RX VrefLevel [Byte0]: 55
2748 16:30:42.248921 [Byte1]: 55
2749 16:30:42.249017
2750 16:30:42.249084 Set Vref, RX VrefLevel [Byte0]: 56
2751 16:30:42.249339 [Byte1]: 56
2752 16:30:42.249399
2753 16:30:42.249452 Set Vref, RX VrefLevel [Byte0]: 57
2754 16:30:42.249505 [Byte1]: 57
2755 16:30:42.249558
2756 16:30:42.249609 Set Vref, RX VrefLevel [Byte0]: 58
2757 16:30:42.249661 [Byte1]: 58
2758 16:30:42.249714
2759 16:30:42.249766 Set Vref, RX VrefLevel [Byte0]: 59
2760 16:30:42.249817 [Byte1]: 59
2761 16:30:42.249870
2762 16:30:42.249921 Set Vref, RX VrefLevel [Byte0]: 60
2763 16:30:42.249973 [Byte1]: 60
2764 16:30:42.250024
2765 16:30:42.250077 Set Vref, RX VrefLevel [Byte0]: 61
2766 16:30:42.250128 [Byte1]: 61
2767 16:30:42.250180
2768 16:30:42.250232 Set Vref, RX VrefLevel [Byte0]: 62
2769 16:30:42.250284 [Byte1]: 62
2770 16:30:42.250353
2771 16:30:42.250418 Set Vref, RX VrefLevel [Byte0]: 63
2772 16:30:42.250470 [Byte1]: 63
2773 16:30:42.250522
2774 16:30:42.250574 Set Vref, RX VrefLevel [Byte0]: 64
2775 16:30:42.250626 [Byte1]: 64
2776 16:30:42.250678
2777 16:30:42.250729 Set Vref, RX VrefLevel [Byte0]: 65
2778 16:30:42.250781 [Byte1]: 65
2779 16:30:42.250833
2780 16:30:42.250884 Set Vref, RX VrefLevel [Byte0]: 66
2781 16:30:42.250937 [Byte1]: 66
2782 16:30:42.250988
2783 16:30:42.251039 Set Vref, RX VrefLevel [Byte0]: 67
2784 16:30:42.251091 [Byte1]: 67
2785 16:30:42.251143
2786 16:30:42.251194 Set Vref, RX VrefLevel [Byte0]: 68
2787 16:30:42.251246 [Byte1]: 68
2788 16:30:42.251337
2789 16:30:42.251417 Final RX Vref Byte 0 = 55 to rank0
2790 16:30:42.251470 Final RX Vref Byte 1 = 58 to rank0
2791 16:30:42.251523 Final RX Vref Byte 0 = 55 to rank1
2792 16:30:42.251575 Final RX Vref Byte 1 = 58 to rank1==
2793 16:30:42.251627 Dram Type= 6, Freq= 0, CH_0, rank 0
2794 16:30:42.251679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2795 16:30:42.251732 ==
2796 16:30:42.251784 DQS Delay:
2797 16:30:42.251836 DQS0 = 0, DQS1 = 0
2798 16:30:42.251888 DQM Delay:
2799 16:30:42.251940 DQM0 = 116, DQM1 = 105
2800 16:30:42.251992 DQ Delay:
2801 16:30:42.252043 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2802 16:30:42.252095 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =120
2803 16:30:42.252147 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2804 16:30:42.252199 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2805 16:30:42.252251
2806 16:30:42.252302
2807 16:30:42.252354 [DQSOSCAuto] RK0, (LSB)MR18= 0x702, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2808 16:30:42.252407 CH0 RK0: MR19=404, MR18=702
2809 16:30:42.252459 CH0_RK0: MR19=0x404, MR18=0x702, DQSOSC=407, MR23=63, INC=39, DEC=26
2810 16:30:42.252512
2811 16:30:42.252564 ----->DramcWriteLeveling(PI) begin...
2812 16:30:42.252617 ==
2813 16:30:42.252669 Dram Type= 6, Freq= 0, CH_0, rank 1
2814 16:30:42.252721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 16:30:42.252773 ==
2816 16:30:42.252826 Write leveling (Byte 0): 31 => 31
2817 16:30:42.252878 Write leveling (Byte 1): 26 => 26
2818 16:30:42.252930 DramcWriteLeveling(PI) end<-----
2819 16:30:42.252982
2820 16:30:42.253033 ==
2821 16:30:42.253085 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 16:30:42.253137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 16:30:42.253189 ==
2824 16:30:42.253241 [Gating] SW mode calibration
2825 16:30:42.253336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2826 16:30:42.253389 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2827 16:30:42.253442 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2828 16:30:42.253494 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2829 16:30:42.253547 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 16:30:42.253599 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 16:30:42.253651 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 16:30:42.253703 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2833 16:30:42.253756 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2834 16:30:42.253807 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2835 16:30:42.253860 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2836 16:30:42.253912 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2837 16:30:42.253964 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 16:30:42.254016 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 16:30:42.254068 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 16:30:42.254120 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 16:30:42.254173 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2842 16:30:42.254225 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2843 16:30:42.254277 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
2844 16:30:42.254329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 16:30:42.254382 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 16:30:42.254434 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 16:30:42.254487 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 16:30:42.254539 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 16:30:42.254591 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2850 16:30:42.254644 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2851 16:30:42.254696 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2852 16:30:42.254749 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 16:30:42.254800 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 16:30:42.254853 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 16:30:42.254905 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 16:30:42.254958 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 16:30:42.255010 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 16:30:42.255063 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 16:30:42.255115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 16:30:42.255168 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 16:30:42.255219 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 16:30:42.255271 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 16:30:42.255323 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 16:30:42.255375 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 16:30:42.255630 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2866 16:30:42.255726 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2867 16:30:42.255779 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2868 16:30:42.255832 Total UI for P1: 0, mck2ui 16
2869 16:30:42.255885 best dqsien dly found for B0: ( 1, 3, 26)
2870 16:30:42.255938 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 16:30:42.255991 Total UI for P1: 0, mck2ui 16
2872 16:30:42.256043 best dqsien dly found for B1: ( 1, 4, 0)
2873 16:30:42.256096 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2874 16:30:42.256149 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2875 16:30:42.256201
2876 16:30:42.256253 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2877 16:30:42.256306 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2878 16:30:42.256359 [Gating] SW calibration Done
2879 16:30:42.256411 ==
2880 16:30:42.256464 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 16:30:42.256516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 16:30:42.256569 ==
2883 16:30:42.256621 RX Vref Scan: 0
2884 16:30:42.256673
2885 16:30:42.256724 RX Vref 0 -> 0, step: 1
2886 16:30:42.256776
2887 16:30:42.256827 RX Delay -40 -> 252, step: 8
2888 16:30:42.256879 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2889 16:30:42.256932 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2890 16:30:42.256984 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2891 16:30:42.257036 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2892 16:30:42.257089 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2893 16:30:42.257141 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2894 16:30:42.257193 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2895 16:30:42.257246 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2896 16:30:42.257337 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2897 16:30:42.257390 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2898 16:30:42.257442 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2899 16:30:42.257494 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2900 16:30:42.257546 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2901 16:30:42.257598 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2902 16:30:42.257650 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2903 16:30:42.257702 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2904 16:30:42.257754 ==
2905 16:30:42.257805 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 16:30:42.257857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 16:30:42.257910 ==
2908 16:30:42.257962 DQS Delay:
2909 16:30:42.258013 DQS0 = 0, DQS1 = 0
2910 16:30:42.258065 DQM Delay:
2911 16:30:42.258117 DQM0 = 116, DQM1 = 109
2912 16:30:42.258168 DQ Delay:
2913 16:30:42.258220 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2914 16:30:42.258272 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2915 16:30:42.258324 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2916 16:30:42.258376 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2917 16:30:42.258428
2918 16:30:42.258479
2919 16:30:42.258531 ==
2920 16:30:42.258583 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 16:30:42.258634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 16:30:42.258687 ==
2923 16:30:42.258738
2924 16:30:42.258790
2925 16:30:42.258840 TX Vref Scan disable
2926 16:30:42.258892 == TX Byte 0 ==
2927 16:30:42.258944 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2928 16:30:42.258997 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2929 16:30:42.259049 == TX Byte 1 ==
2930 16:30:42.259101 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2931 16:30:42.259153 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2932 16:30:42.259205 ==
2933 16:30:42.259256 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 16:30:42.259307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 16:30:42.377545 ==
2936 16:30:42.377675 TX Vref=22, minBit 2, minWin=25, winSum=411
2937 16:30:42.377744 TX Vref=24, minBit 1, minWin=25, winSum=416
2938 16:30:42.377805 TX Vref=26, minBit 12, minWin=25, winSum=419
2939 16:30:42.377863 TX Vref=28, minBit 2, minWin=26, winSum=423
2940 16:30:42.377921 TX Vref=30, minBit 4, minWin=26, winSum=426
2941 16:30:42.377977 TX Vref=32, minBit 5, minWin=25, winSum=419
2942 16:30:42.378033 [TxChooseVref] Worse bit 4, Min win 26, Win sum 426, Final Vref 30
2943 16:30:42.378088
2944 16:30:42.378142 Final TX Range 1 Vref 30
2945 16:30:42.378196
2946 16:30:42.378249 ==
2947 16:30:42.378303 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 16:30:42.378356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 16:30:42.378410 ==
2950 16:30:42.378463
2951 16:30:42.378515
2952 16:30:42.378567 TX Vref Scan disable
2953 16:30:42.378620 == TX Byte 0 ==
2954 16:30:42.378672 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2955 16:30:42.378726 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2956 16:30:42.378804 == TX Byte 1 ==
2957 16:30:42.378869 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2958 16:30:42.378925 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2959 16:30:42.378978
2960 16:30:42.379029 [DATLAT]
2961 16:30:42.379081 Freq=1200, CH0 RK1
2962 16:30:42.379133
2963 16:30:42.379185 DATLAT Default: 0xd
2964 16:30:42.379236 0, 0xFFFF, sum = 0
2965 16:30:42.379290 1, 0xFFFF, sum = 0
2966 16:30:42.379343 2, 0xFFFF, sum = 0
2967 16:30:42.379397 3, 0xFFFF, sum = 0
2968 16:30:42.379450 4, 0xFFFF, sum = 0
2969 16:30:42.379503 5, 0xFFFF, sum = 0
2970 16:30:42.379556 6, 0xFFFF, sum = 0
2971 16:30:42.379610 7, 0xFFFF, sum = 0
2972 16:30:42.379662 8, 0xFFFF, sum = 0
2973 16:30:42.379715 9, 0xFFFF, sum = 0
2974 16:30:42.379768 10, 0xFFFF, sum = 0
2975 16:30:42.379821 11, 0xFFFF, sum = 0
2976 16:30:42.379907 12, 0x0, sum = 1
2977 16:30:42.379992 13, 0x0, sum = 2
2978 16:30:42.380076 14, 0x0, sum = 3
2979 16:30:42.380154 15, 0x0, sum = 4
2980 16:30:42.380224 best_step = 13
2981 16:30:42.380280
2982 16:30:42.380333 ==
2983 16:30:42.380386 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 16:30:42.380456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 16:30:42.380542 ==
2986 16:30:42.380629 RX Vref Scan: 0
2987 16:30:42.380740
2988 16:30:42.380793 RX Vref 0 -> 0, step: 1
2989 16:30:42.380846
2990 16:30:42.380899 RX Delay -21 -> 252, step: 4
2991 16:30:42.380952 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
2992 16:30:42.381005 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2993 16:30:42.381058 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
2994 16:30:42.381113 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
2995 16:30:42.381198 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
2996 16:30:42.381310 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
2997 16:30:42.381381 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2998 16:30:42.381434 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
2999 16:30:42.381500 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3000 16:30:42.381567 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3001 16:30:42.381621 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3002 16:30:42.381677 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3003 16:30:42.381748 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3004 16:30:42.382012 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3005 16:30:42.382074 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3006 16:30:42.382129 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3007 16:30:42.382181 ==
3008 16:30:42.382234 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 16:30:42.382287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 16:30:42.382364 ==
3011 16:30:42.382475 DQS Delay:
3012 16:30:42.382529 DQS0 = 0, DQS1 = 0
3013 16:30:42.382581 DQM Delay:
3014 16:30:42.382633 DQM0 = 116, DQM1 = 106
3015 16:30:42.382703 DQ Delay:
3016 16:30:42.382805 DQ0 =112, DQ1 =116, DQ2 =112, DQ3 =112
3017 16:30:42.382889 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3018 16:30:42.382974 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3019 16:30:42.383072 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3020 16:30:42.383163
3021 16:30:42.383220
3022 16:30:42.383274 [DQSOSCAuto] RK1, (LSB)MR18= 0x2ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3023 16:30:42.383329 CH0 RK1: MR19=403, MR18=2FF
3024 16:30:42.383383 CH0_RK1: MR19=0x403, MR18=0x2FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3025 16:30:42.383436 [RxdqsGatingPostProcess] freq 1200
3026 16:30:42.383490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3027 16:30:42.383542 best DQS0 dly(2T, 0.5T) = (0, 11)
3028 16:30:42.383594 best DQS1 dly(2T, 0.5T) = (0, 12)
3029 16:30:42.383648 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3030 16:30:42.383701 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3031 16:30:42.383753 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 16:30:42.383805 best DQS1 dly(2T, 0.5T) = (0, 12)
3033 16:30:42.383857 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 16:30:42.383910 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3035 16:30:42.383962 Pre-setting of DQS Precalculation
3036 16:30:42.384014 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3037 16:30:42.384067 ==
3038 16:30:42.384120 Dram Type= 6, Freq= 0, CH_1, rank 0
3039 16:30:42.384173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 16:30:42.384226 ==
3041 16:30:42.384278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3042 16:30:42.384330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3043 16:30:42.384383 [CA 0] Center 38 (8~68) winsize 61
3044 16:30:42.384435 [CA 1] Center 37 (7~68) winsize 62
3045 16:30:42.384488 [CA 2] Center 35 (5~65) winsize 61
3046 16:30:42.384540 [CA 3] Center 34 (4~64) winsize 61
3047 16:30:42.384593 [CA 4] Center 35 (5~65) winsize 61
3048 16:30:42.384645 [CA 5] Center 33 (3~63) winsize 61
3049 16:30:42.384697
3050 16:30:42.384750 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3051 16:30:42.384803
3052 16:30:42.384855 [CATrainingPosCal] consider 1 rank data
3053 16:30:42.384908 u2DelayCellTimex100 = 270/100 ps
3054 16:30:42.384961 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3055 16:30:42.385013 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3056 16:30:42.385066 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3057 16:30:42.385118 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3058 16:30:42.385171 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3059 16:30:42.385224 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3060 16:30:42.385306
3061 16:30:42.385374 CA PerBit enable=1, Macro0, CA PI delay=33
3062 16:30:42.385427
3063 16:30:42.385480 [CBTSetCACLKResult] CA Dly = 33
3064 16:30:42.385533 CS Dly: 5 (0~36)
3065 16:30:42.385585 ==
3066 16:30:42.385637 Dram Type= 6, Freq= 0, CH_1, rank 1
3067 16:30:42.385691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 16:30:42.385744 ==
3069 16:30:42.385796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 16:30:42.385850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 16:30:42.385903 [CA 0] Center 37 (7~68) winsize 62
3072 16:30:42.385956 [CA 1] Center 37 (7~68) winsize 62
3073 16:30:42.386009 [CA 2] Center 34 (4~65) winsize 62
3074 16:30:42.386061 [CA 3] Center 33 (3~64) winsize 62
3075 16:30:42.386114 [CA 4] Center 34 (5~64) winsize 60
3076 16:30:42.386166 [CA 5] Center 33 (3~63) winsize 61
3077 16:30:42.386222
3078 16:30:42.386305 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3079 16:30:42.386392
3080 16:30:42.386479 [CATrainingPosCal] consider 2 rank data
3081 16:30:42.386568 u2DelayCellTimex100 = 270/100 ps
3082 16:30:42.386646 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3083 16:30:42.386729 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 16:30:42.386788 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3085 16:30:42.386843 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 16:30:42.386898 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3087 16:30:42.386952 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3088 16:30:42.387005
3089 16:30:42.387058 CA PerBit enable=1, Macro0, CA PI delay=33
3090 16:30:42.387112
3091 16:30:42.387164 [CBTSetCACLKResult] CA Dly = 33
3092 16:30:42.387217 CS Dly: 6 (0~39)
3093 16:30:42.387270
3094 16:30:42.387323 ----->DramcWriteLeveling(PI) begin...
3095 16:30:42.387377 ==
3096 16:30:42.387430 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 16:30:42.387483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 16:30:42.387537 ==
3099 16:30:42.387590 Write leveling (Byte 0): 26 => 26
3100 16:30:42.387643 Write leveling (Byte 1): 28 => 28
3101 16:30:42.387696 DramcWriteLeveling(PI) end<-----
3102 16:30:42.387748
3103 16:30:42.387801 ==
3104 16:30:42.387853 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 16:30:42.387906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 16:30:42.387959 ==
3107 16:30:42.388012 [Gating] SW mode calibration
3108 16:30:42.388065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3109 16:30:42.388118 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3110 16:30:42.388172 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3111 16:30:42.388225 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 16:30:42.388279 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 16:30:42.388331 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 16:30:42.388384 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 16:30:42.388437 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 16:30:42.388490 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
3117 16:30:42.388542 0 15 28 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
3118 16:30:42.388595 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 16:30:42.388648 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 16:30:42.388701 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 16:30:42.388954 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 16:30:42.389016 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 16:30:42.389070 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 16:30:42.389124 1 0 24 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
3125 16:30:42.389177 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3126 16:30:42.389230 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 16:30:42.389311 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 16:30:42.389382 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 16:30:42.389463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 16:30:42.389553 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 16:30:42.389642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 16:30:42.389731 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3133 16:30:42.389810 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3134 16:30:42.389892 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 16:30:42.389951 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 16:30:42.390006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 16:30:42.390061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 16:30:42.390115 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 16:30:42.390169 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 16:30:42.390222 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 16:30:42.390307 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 16:30:42.390360 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 16:30:42.390413 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 16:30:42.390467 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 16:30:42.390520 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 16:30:42.390573 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 16:30:42.390626 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 16:30:42.390683 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3149 16:30:42.390737 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3150 16:30:42.390791 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 16:30:42.390844 Total UI for P1: 0, mck2ui 16
3152 16:30:42.390898 best dqsien dly found for B0: ( 1, 3, 26)
3153 16:30:42.390950 Total UI for P1: 0, mck2ui 16
3154 16:30:42.391004 best dqsien dly found for B1: ( 1, 3, 28)
3155 16:30:42.391057 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3156 16:30:42.391111 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3157 16:30:42.391164
3158 16:30:42.391216 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3159 16:30:42.391269 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3160 16:30:42.391322 [Gating] SW calibration Done
3161 16:30:42.391375 ==
3162 16:30:42.391427 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 16:30:42.391480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 16:30:42.391533 ==
3165 16:30:42.391586 RX Vref Scan: 0
3166 16:30:42.391638
3167 16:30:42.391690 RX Vref 0 -> 0, step: 1
3168 16:30:42.391743
3169 16:30:42.391796 RX Delay -40 -> 252, step: 8
3170 16:30:42.391848 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3171 16:30:42.391901 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3172 16:30:42.391954 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3173 16:30:42.392007 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3174 16:30:42.392059 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3175 16:30:42.392111 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3176 16:30:42.392164 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3177 16:30:42.392217 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3178 16:30:42.392270 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3179 16:30:42.392322 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3180 16:30:42.392376 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3181 16:30:42.392429 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3182 16:30:42.392482 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3183 16:30:42.392534 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3184 16:30:42.392587 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3185 16:30:42.392666 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3186 16:30:42.392735 ==
3187 16:30:42.392788 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 16:30:42.392841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 16:30:42.392894 ==
3190 16:30:42.392947 DQS Delay:
3191 16:30:42.392999 DQS0 = 0, DQS1 = 0
3192 16:30:42.393051 DQM Delay:
3193 16:30:42.393123 DQM0 = 115, DQM1 = 112
3194 16:30:42.393206 DQ Delay:
3195 16:30:42.393330 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3196 16:30:42.393424 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3197 16:30:42.393523 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3198 16:30:42.393604 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3199 16:30:42.393681
3200 16:30:42.393757
3201 16:30:42.393830 ==
3202 16:30:42.393904 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 16:30:42.393999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 16:30:42.394093 ==
3205 16:30:42.394187
3206 16:30:42.394279
3207 16:30:42.394371 TX Vref Scan disable
3208 16:30:42.394464 == TX Byte 0 ==
3209 16:30:42.394556 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3210 16:30:42.394651 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3211 16:30:42.394744 == TX Byte 1 ==
3212 16:30:42.394836 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3213 16:30:42.394929 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3214 16:30:42.395021 ==
3215 16:30:42.395114 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 16:30:42.395209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 16:30:42.395302 ==
3218 16:30:42.395395 TX Vref=22, minBit 3, minWin=25, winSum=414
3219 16:30:42.395488 TX Vref=24, minBit 3, minWin=25, winSum=422
3220 16:30:42.395581 TX Vref=26, minBit 2, minWin=25, winSum=420
3221 16:30:42.395674 TX Vref=28, minBit 9, minWin=25, winSum=428
3222 16:30:42.395766 TX Vref=30, minBit 9, minWin=25, winSum=426
3223 16:30:42.395858 TX Vref=32, minBit 8, minWin=26, winSum=427
3224 16:30:42.395950 [TxChooseVref] Worse bit 8, Min win 26, Win sum 427, Final Vref 32
3225 16:30:42.396042
3226 16:30:42.396133 Final TX Range 1 Vref 32
3227 16:30:42.396225
3228 16:30:42.396321 ==
3229 16:30:42.396409 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 16:30:42.396504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 16:30:42.396592 ==
3232 16:30:42.396732
3233 16:30:42.396829
3234 16:30:42.396961 TX Vref Scan disable
3235 16:30:42.397052 == TX Byte 0 ==
3236 16:30:42.397156 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3237 16:30:42.397465 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3238 16:30:42.397530 == TX Byte 1 ==
3239 16:30:42.397602 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 16:30:42.397673 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 16:30:42.397728
3242 16:30:42.397781 [DATLAT]
3243 16:30:42.397834 Freq=1200, CH1 RK0
3244 16:30:42.397887
3245 16:30:42.397939 DATLAT Default: 0xd
3246 16:30:42.398009 0, 0xFFFF, sum = 0
3247 16:30:42.398064 1, 0xFFFF, sum = 0
3248 16:30:42.398155 2, 0xFFFF, sum = 0
3249 16:30:42.398244 3, 0xFFFF, sum = 0
3250 16:30:42.398329 4, 0xFFFF, sum = 0
3251 16:30:42.398431 5, 0xFFFF, sum = 0
3252 16:30:42.398530 6, 0xFFFF, sum = 0
3253 16:30:42.398632 7, 0xFFFF, sum = 0
3254 16:30:42.398730 8, 0xFFFF, sum = 0
3255 16:30:42.398844 9, 0xFFFF, sum = 0
3256 16:30:42.398927 10, 0xFFFF, sum = 0
3257 16:30:42.399058 11, 0xFFFF, sum = 0
3258 16:30:42.399187 12, 0x0, sum = 1
3259 16:30:42.399271 13, 0x0, sum = 2
3260 16:30:42.399355 14, 0x0, sum = 3
3261 16:30:42.399438 15, 0x0, sum = 4
3262 16:30:42.399540 best_step = 13
3263 16:30:42.399622
3264 16:30:42.399718 ==
3265 16:30:42.399800 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 16:30:42.399916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 16:30:42.400046 ==
3268 16:30:42.400152 RX Vref Scan: 1
3269 16:30:42.400241
3270 16:30:42.400329 Set Vref Range= 32 -> 127
3271 16:30:42.400405
3272 16:30:42.400484 RX Vref 32 -> 127, step: 1
3273 16:30:42.400560
3274 16:30:42.400623 RX Delay -13 -> 252, step: 4
3275 16:30:42.400708
3276 16:30:42.400794 Set Vref, RX VrefLevel [Byte0]: 32
3277 16:30:42.400881 [Byte1]: 32
3278 16:30:42.400978
3279 16:30:42.401060 Set Vref, RX VrefLevel [Byte0]: 33
3280 16:30:42.401143 [Byte1]: 33
3281 16:30:42.401225
3282 16:30:42.401335 Set Vref, RX VrefLevel [Byte0]: 34
3283 16:30:42.401391 [Byte1]: 34
3284 16:30:42.401444
3285 16:30:42.401498 Set Vref, RX VrefLevel [Byte0]: 35
3286 16:30:42.401551 [Byte1]: 35
3287 16:30:42.401605
3288 16:30:42.401658 Set Vref, RX VrefLevel [Byte0]: 36
3289 16:30:42.401711 [Byte1]: 36
3290 16:30:42.401764
3291 16:30:42.401816 Set Vref, RX VrefLevel [Byte0]: 37
3292 16:30:42.401887 [Byte1]: 37
3293 16:30:42.401955
3294 16:30:42.402008 Set Vref, RX VrefLevel [Byte0]: 38
3295 16:30:42.402060 [Byte1]: 38
3296 16:30:42.402113
3297 16:30:42.402165 Set Vref, RX VrefLevel [Byte0]: 39
3298 16:30:42.402218 [Byte1]: 39
3299 16:30:42.402270
3300 16:30:42.402322 Set Vref, RX VrefLevel [Byte0]: 40
3301 16:30:42.402375 [Byte1]: 40
3302 16:30:42.402427
3303 16:30:42.402479 Set Vref, RX VrefLevel [Byte0]: 41
3304 16:30:42.402531 [Byte1]: 41
3305 16:30:42.402583
3306 16:30:42.402635 Set Vref, RX VrefLevel [Byte0]: 42
3307 16:30:42.402725 [Byte1]: 42
3308 16:30:42.402778
3309 16:30:42.402830 Set Vref, RX VrefLevel [Byte0]: 43
3310 16:30:42.402883 [Byte1]: 43
3311 16:30:42.402935
3312 16:30:42.402987 Set Vref, RX VrefLevel [Byte0]: 44
3313 16:30:42.403039 [Byte1]: 44
3314 16:30:42.403091
3315 16:30:42.403143 Set Vref, RX VrefLevel [Byte0]: 45
3316 16:30:42.403212 [Byte1]: 45
3317 16:30:42.403311
3318 16:30:42.403400 Set Vref, RX VrefLevel [Byte0]: 46
3319 16:30:42.403483 [Byte1]: 46
3320 16:30:42.403566
3321 16:30:42.403642 Set Vref, RX VrefLevel [Byte0]: 47
3322 16:30:42.403732 [Byte1]: 47
3323 16:30:42.403816
3324 16:30:42.403899 Set Vref, RX VrefLevel [Byte0]: 48
3325 16:30:42.403962 [Byte1]: 48
3326 16:30:42.404016
3327 16:30:42.404068 Set Vref, RX VrefLevel [Byte0]: 49
3328 16:30:42.404121 [Byte1]: 49
3329 16:30:42.404174
3330 16:30:42.404226 Set Vref, RX VrefLevel [Byte0]: 50
3331 16:30:42.404278 [Byte1]: 50
3332 16:30:42.404330
3333 16:30:42.404382 Set Vref, RX VrefLevel [Byte0]: 51
3334 16:30:42.404434 [Byte1]: 51
3335 16:30:42.404486
3336 16:30:42.404538 Set Vref, RX VrefLevel [Byte0]: 52
3337 16:30:42.404592 [Byte1]: 52
3338 16:30:42.404700
3339 16:30:42.404790 Set Vref, RX VrefLevel [Byte0]: 53
3340 16:30:42.404847 [Byte1]: 53
3341 16:30:42.404900
3342 16:30:42.404951 Set Vref, RX VrefLevel [Byte0]: 54
3343 16:30:42.405004 [Byte1]: 54
3344 16:30:42.405056
3345 16:30:42.405108 Set Vref, RX VrefLevel [Byte0]: 55
3346 16:30:42.405160 [Byte1]: 55
3347 16:30:42.405212
3348 16:30:42.405292 Set Vref, RX VrefLevel [Byte0]: 56
3349 16:30:42.405361 [Byte1]: 56
3350 16:30:42.405413
3351 16:30:42.405465 Set Vref, RX VrefLevel [Byte0]: 57
3352 16:30:42.405517 [Byte1]: 57
3353 16:30:42.405569
3354 16:30:42.405621 Set Vref, RX VrefLevel [Byte0]: 58
3355 16:30:42.405673 [Byte1]: 58
3356 16:30:42.405725
3357 16:30:42.405777 Set Vref, RX VrefLevel [Byte0]: 59
3358 16:30:42.405830 [Byte1]: 59
3359 16:30:42.405942
3360 16:30:42.405997 Set Vref, RX VrefLevel [Byte0]: 60
3361 16:30:42.406050 [Byte1]: 60
3362 16:30:42.406102
3363 16:30:42.406155 Set Vref, RX VrefLevel [Byte0]: 61
3364 16:30:42.406207 [Byte1]: 61
3365 16:30:42.406259
3366 16:30:42.406311 Set Vref, RX VrefLevel [Byte0]: 62
3367 16:30:42.406403 [Byte1]: 62
3368 16:30:42.406455
3369 16:30:42.406507 Set Vref, RX VrefLevel [Byte0]: 63
3370 16:30:42.406560 [Byte1]: 63
3371 16:30:42.406612
3372 16:30:42.406687 Set Vref, RX VrefLevel [Byte0]: 64
3373 16:30:42.406770 [Byte1]: 64
3374 16:30:42.406855
3375 16:30:42.406940 Set Vref, RX VrefLevel [Byte0]: 65
3376 16:30:42.407025 [Byte1]: 65
3377 16:30:42.407102
3378 16:30:42.407180 Final RX Vref Byte 0 = 51 to rank0
3379 16:30:42.407239 Final RX Vref Byte 1 = 50 to rank0
3380 16:30:42.407294 Final RX Vref Byte 0 = 51 to rank1
3381 16:30:42.407348 Final RX Vref Byte 1 = 50 to rank1==
3382 16:30:42.407402 Dram Type= 6, Freq= 0, CH_1, rank 0
3383 16:30:42.407455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3384 16:30:42.407509 ==
3385 16:30:42.407562 DQS Delay:
3386 16:30:42.407614 DQS0 = 0, DQS1 = 0
3387 16:30:42.407666 DQM Delay:
3388 16:30:42.407718 DQM0 = 114, DQM1 = 112
3389 16:30:42.407770 DQ Delay:
3390 16:30:42.407822 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3391 16:30:42.407874 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3392 16:30:42.407926 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3393 16:30:42.407979 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3394 16:30:42.408031
3395 16:30:42.408082
3396 16:30:42.408134 [DQSOSCAuto] RK0, (LSB)MR18= 0xf906, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 412 ps
3397 16:30:42.408188 CH1 RK0: MR19=304, MR18=F906
3398 16:30:42.408239 CH1_RK0: MR19=0x304, MR18=0xF906, DQSOSC=407, MR23=63, INC=39, DEC=26
3399 16:30:42.408293
3400 16:30:42.408345 ----->DramcWriteLeveling(PI) begin...
3401 16:30:42.408399 ==
3402 16:30:42.408450 Dram Type= 6, Freq= 0, CH_1, rank 1
3403 16:30:42.408754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 16:30:42.408818 ==
3405 16:30:42.408872 Write leveling (Byte 0): 26 => 26
3406 16:30:42.408925 Write leveling (Byte 1): 28 => 28
3407 16:30:42.408977 DramcWriteLeveling(PI) end<-----
3408 16:30:42.409030
3409 16:30:42.409100 ==
3410 16:30:42.409192 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 16:30:42.409283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 16:30:42.409355 ==
3413 16:30:42.409409 [Gating] SW mode calibration
3414 16:30:42.409461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3415 16:30:42.409515 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3416 16:30:42.409568 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3417 16:30:42.409622 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3418 16:30:42.409674 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3419 16:30:42.409728 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3420 16:30:42.409781 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3421 16:30:42.409834 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3422 16:30:42.409886 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
3423 16:30:42.409938 0 15 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3424 16:30:42.409990 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 16:30:42.410043 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3426 16:30:42.410095 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 16:30:42.410161 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3428 16:30:42.410247 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 16:30:42.410333 1 0 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
3430 16:30:42.410410 1 0 24 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
3431 16:30:42.410490 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3432 16:30:42.410548 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 16:30:42.410604 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3434 16:30:42.410682 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 16:30:42.410750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 16:30:42.410802 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 16:30:42.410855 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3438 16:30:42.410908 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3439 16:30:42.410960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3440 16:30:42.411012 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 16:30:42.411065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 16:30:42.411117 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 16:30:42.411169 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 16:30:42.411221 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 16:30:42.411273 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 16:30:42.411325 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 16:30:42.411377 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 16:30:42.411430 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 16:30:42.411481 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 16:30:42.411534 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 16:30:42.411586 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 16:30:42.411639 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 16:30:42.411691 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3454 16:30:42.411743 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3455 16:30:42.411795 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3456 16:30:42.411870 Total UI for P1: 0, mck2ui 16
3457 16:30:42.411938 best dqsien dly found for B0: ( 1, 3, 22)
3458 16:30:42.412023 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 16:30:42.412075 Total UI for P1: 0, mck2ui 16
3460 16:30:42.412128 best dqsien dly found for B1: ( 1, 3, 26)
3461 16:30:42.412180 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3462 16:30:42.412233 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3463 16:30:42.412302
3464 16:30:42.412355 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3465 16:30:42.412423 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3466 16:30:42.412476 [Gating] SW calibration Done
3467 16:30:42.412581 ==
3468 16:30:42.412635 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 16:30:42.412689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 16:30:42.412759 ==
3471 16:30:42.412828 RX Vref Scan: 0
3472 16:30:42.412880
3473 16:30:42.412932 RX Vref 0 -> 0, step: 1
3474 16:30:42.412983
3475 16:30:42.413035 RX Delay -40 -> 252, step: 8
3476 16:30:42.413087 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3477 16:30:42.413140 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3478 16:30:42.413210 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3479 16:30:42.413274 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3480 16:30:42.413346 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3481 16:30:42.413435 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3482 16:30:42.413519 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3483 16:30:42.413601 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3484 16:30:42.413679 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3485 16:30:42.413743 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3486 16:30:42.413798 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3487 16:30:42.413851 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3488 16:30:42.413903 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3489 16:30:42.413956 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3490 16:30:42.414010 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3491 16:30:42.414063 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3492 16:30:42.414115 ==
3493 16:30:42.414168 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 16:30:42.414221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 16:30:42.414274 ==
3496 16:30:42.414326 DQS Delay:
3497 16:30:42.414378 DQS0 = 0, DQS1 = 0
3498 16:30:42.414430 DQM Delay:
3499 16:30:42.414482 DQM0 = 115, DQM1 = 111
3500 16:30:42.414534 DQ Delay:
3501 16:30:42.414585 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3502 16:30:42.414637 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3503 16:30:42.414690 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3504 16:30:42.414946 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3505 16:30:42.415005
3506 16:30:42.415058
3507 16:30:42.415110 ==
3508 16:30:42.415163 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 16:30:42.415215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 16:30:42.415269 ==
3511 16:30:42.415321
3512 16:30:42.415372
3513 16:30:42.415424 TX Vref Scan disable
3514 16:30:42.415476 == TX Byte 0 ==
3515 16:30:42.415529 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3516 16:30:42.415582 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3517 16:30:42.415635 == TX Byte 1 ==
3518 16:30:42.415687 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3519 16:30:42.415739 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3520 16:30:42.415791 ==
3521 16:30:42.415844 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 16:30:42.415896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 16:30:42.415968 ==
3524 16:30:42.416022 TX Vref=22, minBit 9, minWin=25, winSum=420
3525 16:30:42.416075 TX Vref=24, minBit 9, minWin=25, winSum=423
3526 16:30:42.416128 TX Vref=26, minBit 9, minWin=25, winSum=431
3527 16:30:42.416181 TX Vref=28, minBit 1, minWin=26, winSum=429
3528 16:30:42.416234 TX Vref=30, minBit 1, minWin=26, winSum=431
3529 16:30:42.416290 TX Vref=32, minBit 1, minWin=26, winSum=431
3530 16:30:42.416374 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3531 16:30:42.416459
3532 16:30:42.416548 Final TX Range 1 Vref 30
3533 16:30:42.416636
3534 16:30:42.416714 ==
3535 16:30:42.416794 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 16:30:42.416854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 16:30:42.416910 ==
3538 16:30:42.416964
3539 16:30:42.417016
3540 16:30:42.417069 TX Vref Scan disable
3541 16:30:42.417121 == TX Byte 0 ==
3542 16:30:42.417173 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3543 16:30:42.417227 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3544 16:30:42.417324 == TX Byte 1 ==
3545 16:30:42.417378 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3546 16:30:42.417431 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3547 16:30:42.417483
3548 16:30:42.417535 [DATLAT]
3549 16:30:42.417587 Freq=1200, CH1 RK1
3550 16:30:42.417639
3551 16:30:42.417691 DATLAT Default: 0xd
3552 16:30:42.417743 0, 0xFFFF, sum = 0
3553 16:30:42.417797 1, 0xFFFF, sum = 0
3554 16:30:42.417850 2, 0xFFFF, sum = 0
3555 16:30:42.417903 3, 0xFFFF, sum = 0
3556 16:30:42.417956 4, 0xFFFF, sum = 0
3557 16:30:42.418009 5, 0xFFFF, sum = 0
3558 16:30:42.418062 6, 0xFFFF, sum = 0
3559 16:30:42.418115 7, 0xFFFF, sum = 0
3560 16:30:42.418168 8, 0xFFFF, sum = 0
3561 16:30:42.418220 9, 0xFFFF, sum = 0
3562 16:30:42.418273 10, 0xFFFF, sum = 0
3563 16:30:42.418326 11, 0xFFFF, sum = 0
3564 16:30:42.418379 12, 0x0, sum = 1
3565 16:30:42.418432 13, 0x0, sum = 2
3566 16:30:42.418484 14, 0x0, sum = 3
3567 16:30:42.418537 15, 0x0, sum = 4
3568 16:30:42.418591 best_step = 13
3569 16:30:42.418643
3570 16:30:42.418695 ==
3571 16:30:42.418747 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 16:30:42.418800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 16:30:42.418853 ==
3574 16:30:42.418905 RX Vref Scan: 0
3575 16:30:42.418957
3576 16:30:42.419009 RX Vref 0 -> 0, step: 1
3577 16:30:42.419061
3578 16:30:42.419112 RX Delay -13 -> 252, step: 4
3579 16:30:42.419164 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3580 16:30:42.419218 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3581 16:30:42.419291 iDelay=191, Bit 2, Center 106 (39 ~ 174) 136
3582 16:30:42.419345 iDelay=191, Bit 3, Center 114 (47 ~ 182) 136
3583 16:30:42.419398 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3584 16:30:42.419451 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3585 16:30:42.419503 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3586 16:30:42.419555 iDelay=191, Bit 7, Center 112 (43 ~ 182) 140
3587 16:30:42.419607 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3588 16:30:42.419660 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3589 16:30:42.419715 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3590 16:30:42.419784 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3591 16:30:42.419841 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3592 16:30:42.419930 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3593 16:30:42.420015 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3594 16:30:42.420095 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3595 16:30:42.420176 ==
3596 16:30:42.420236 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 16:30:42.420291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 16:30:42.420345 ==
3599 16:30:42.420397 DQS Delay:
3600 16:30:42.420449 DQS0 = 0, DQS1 = 0
3601 16:30:42.420502 DQM Delay:
3602 16:30:42.420554 DQM0 = 114, DQM1 = 112
3603 16:30:42.420606 DQ Delay:
3604 16:30:42.420658 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3605 16:30:42.420710 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =112
3606 16:30:42.420762 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3607 16:30:42.420814 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3608 16:30:42.420865
3609 16:30:42.420917
3610 16:30:42.420969 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0d, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3611 16:30:42.421022 CH1 RK1: MR19=304, MR18=FB0D
3612 16:30:42.421074 CH1_RK1: MR19=0x304, MR18=0xFB0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3613 16:30:42.421128 [RxdqsGatingPostProcess] freq 1200
3614 16:30:42.421182 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3615 16:30:42.421235 best DQS0 dly(2T, 0.5T) = (0, 11)
3616 16:30:42.421297 best DQS1 dly(2T, 0.5T) = (0, 11)
3617 16:30:42.421350 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3618 16:30:42.421403 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3619 16:30:42.421455 best DQS0 dly(2T, 0.5T) = (0, 11)
3620 16:30:42.421507 best DQS1 dly(2T, 0.5T) = (0, 11)
3621 16:30:42.421559 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3622 16:30:42.421611 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3623 16:30:42.421664 Pre-setting of DQS Precalculation
3624 16:30:42.421716 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3625 16:30:42.421823 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3626 16:30:42.421883 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3627 16:30:42.421937
3628 16:30:42.421989
3629 16:30:42.422041 [Calibration Summary] 2400 Mbps
3630 16:30:42.422111 CH 0, Rank 0
3631 16:30:42.422177 SW Impedance : PASS
3632 16:30:42.422229 DUTY Scan : NO K
3633 16:30:42.422281 ZQ Calibration : PASS
3634 16:30:42.422333 Jitter Meter : NO K
3635 16:30:42.422385 CBT Training : PASS
3636 16:30:42.422438 Write leveling : PASS
3637 16:30:42.422490 RX DQS gating : PASS
3638 16:30:42.422542 RX DQ/DQS(RDDQC) : PASS
3639 16:30:42.422594 TX DQ/DQS : PASS
3640 16:30:42.422652 RX DATLAT : PASS
3641 16:30:42.422767 RX DQ/DQS(Engine): PASS
3642 16:30:42.422823 TX OE : NO K
3643 16:30:42.422940 All Pass.
3644 16:30:42.423016
3645 16:30:42.423069 CH 0, Rank 1
3646 16:30:42.423122 SW Impedance : PASS
3647 16:30:42.423404 DUTY Scan : NO K
3648 16:30:42.423497 ZQ Calibration : PASS
3649 16:30:42.423575 Jitter Meter : NO K
3650 16:30:42.423653 CBT Training : PASS
3651 16:30:42.423711 Write leveling : PASS
3652 16:30:42.423765 RX DQS gating : PASS
3653 16:30:42.423819 RX DQ/DQS(RDDQC) : PASS
3654 16:30:42.423873 TX DQ/DQS : PASS
3655 16:30:42.423927 RX DATLAT : PASS
3656 16:30:42.423980 RX DQ/DQS(Engine): PASS
3657 16:30:42.424033 TX OE : NO K
3658 16:30:42.424086 All Pass.
3659 16:30:42.424138
3660 16:30:42.424191 CH 1, Rank 0
3661 16:30:42.424243 SW Impedance : PASS
3662 16:30:42.424295 DUTY Scan : NO K
3663 16:30:42.424355 ZQ Calibration : PASS
3664 16:30:42.424410 Jitter Meter : NO K
3665 16:30:42.424463 CBT Training : PASS
3666 16:30:42.424516 Write leveling : PASS
3667 16:30:42.424567 RX DQS gating : PASS
3668 16:30:42.424622 RX DQ/DQS(RDDQC) : PASS
3669 16:30:42.424692 TX DQ/DQS : PASS
3670 16:30:42.424746 RX DATLAT : PASS
3671 16:30:42.424798 RX DQ/DQS(Engine): PASS
3672 16:30:42.424850 TX OE : NO K
3673 16:30:42.424903 All Pass.
3674 16:30:42.424955
3675 16:30:42.425007 CH 1, Rank 1
3676 16:30:42.425059 SW Impedance : PASS
3677 16:30:42.425111 DUTY Scan : NO K
3678 16:30:42.425163 ZQ Calibration : PASS
3679 16:30:42.425215 Jitter Meter : NO K
3680 16:30:42.425290 CBT Training : PASS
3681 16:30:42.425357 Write leveling : PASS
3682 16:30:42.425409 RX DQS gating : PASS
3683 16:30:42.425461 RX DQ/DQS(RDDQC) : PASS
3684 16:30:42.425512 TX DQ/DQS : PASS
3685 16:30:42.425564 RX DATLAT : PASS
3686 16:30:42.425616 RX DQ/DQS(Engine): PASS
3687 16:30:42.425669 TX OE : NO K
3688 16:30:42.425721 All Pass.
3689 16:30:42.425773
3690 16:30:42.425824 DramC Write-DBI off
3691 16:30:42.425877 PER_BANK_REFRESH: Hybrid Mode
3692 16:30:42.425929 TX_TRACKING: ON
3693 16:30:42.425982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3694 16:30:42.426035 [FAST_K] Save calibration result to emmc
3695 16:30:42.426088 dramc_set_vcore_voltage set vcore to 650000
3696 16:30:42.426140 Read voltage for 600, 5
3697 16:30:42.426200 Vio18 = 0
3698 16:30:42.426283 Vcore = 650000
3699 16:30:42.426369 Vdram = 0
3700 16:30:42.426453 Vddq = 0
3701 16:30:42.426541 Vmddr = 0
3702 16:30:42.426618 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3703 16:30:42.426699 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3704 16:30:42.426759 MEM_TYPE=3, freq_sel=19
3705 16:30:42.426814 sv_algorithm_assistance_LP4_1600
3706 16:30:42.426868 ============ PULL DRAM RESETB DOWN ============
3707 16:30:42.426922 ========== PULL DRAM RESETB DOWN end =========
3708 16:30:42.426976 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3709 16:30:42.427029 ===================================
3710 16:30:42.427082 LPDDR4 DRAM CONFIGURATION
3711 16:30:42.427135 ===================================
3712 16:30:42.427188 EX_ROW_EN[0] = 0x0
3713 16:30:42.427263 EX_ROW_EN[1] = 0x0
3714 16:30:42.427317 LP4Y_EN = 0x0
3715 16:30:42.427369 WORK_FSP = 0x0
3716 16:30:42.427422 WL = 0x2
3717 16:30:42.427475 RL = 0x2
3718 16:30:42.427527 BL = 0x2
3719 16:30:42.427578 RPST = 0x0
3720 16:30:42.427630 RD_PRE = 0x0
3721 16:30:42.427682 WR_PRE = 0x1
3722 16:30:42.427734 WR_PST = 0x0
3723 16:30:42.427786 DBI_WR = 0x0
3724 16:30:42.427838 DBI_RD = 0x0
3725 16:30:42.427890 OTF = 0x1
3726 16:30:42.427942 ===================================
3727 16:30:42.427995 ===================================
3728 16:30:42.428047 ANA top config
3729 16:30:42.428099 ===================================
3730 16:30:42.428152 DLL_ASYNC_EN = 0
3731 16:30:42.428204 ALL_SLAVE_EN = 1
3732 16:30:42.428256 NEW_RANK_MODE = 1
3733 16:30:42.428308 DLL_IDLE_MODE = 1
3734 16:30:42.428360 LP45_APHY_COMB_EN = 1
3735 16:30:42.428412 TX_ODT_DIS = 1
3736 16:30:42.428464 NEW_8X_MODE = 1
3737 16:30:42.428516 ===================================
3738 16:30:42.428570 ===================================
3739 16:30:42.428623 data_rate = 1200
3740 16:30:42.428675 CKR = 1
3741 16:30:42.428727 DQ_P2S_RATIO = 8
3742 16:30:42.428779 ===================================
3743 16:30:42.428832 CA_P2S_RATIO = 8
3744 16:30:42.428883 DQ_CA_OPEN = 0
3745 16:30:42.428935 DQ_SEMI_OPEN = 0
3746 16:30:42.428987 CA_SEMI_OPEN = 0
3747 16:30:42.429039 CA_FULL_RATE = 0
3748 16:30:42.429091 DQ_CKDIV4_EN = 1
3749 16:30:42.429143 CA_CKDIV4_EN = 1
3750 16:30:42.429194 CA_PREDIV_EN = 0
3751 16:30:42.429246 PH8_DLY = 0
3752 16:30:42.429337 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3753 16:30:42.429389 DQ_AAMCK_DIV = 4
3754 16:30:42.429440 CA_AAMCK_DIV = 4
3755 16:30:42.429492 CA_ADMCK_DIV = 4
3756 16:30:42.429544 DQ_TRACK_CA_EN = 0
3757 16:30:42.429596 CA_PICK = 600
3758 16:30:42.429648 CA_MCKIO = 600
3759 16:30:42.429700 MCKIO_SEMI = 0
3760 16:30:42.429752 PLL_FREQ = 2288
3761 16:30:42.429805 DQ_UI_PI_RATIO = 32
3762 16:30:42.429857 CA_UI_PI_RATIO = 0
3763 16:30:42.429909 ===================================
3764 16:30:42.429994 ===================================
3765 16:30:42.430077 memory_type:LPDDR4
3766 16:30:42.430158 GP_NUM : 10
3767 16:30:42.430233 SRAM_EN : 1
3768 16:30:42.430305 MD32_EN : 0
3769 16:30:42.430361 ===================================
3770 16:30:42.430415 [ANA_INIT] >>>>>>>>>>>>>>
3771 16:30:42.430468 <<<<<< [CONFIGURE PHASE]: ANA_TX
3772 16:30:42.430521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3773 16:30:42.430573 ===================================
3774 16:30:42.430626 data_rate = 1200,PCW = 0X5800
3775 16:30:42.430678 ===================================
3776 16:30:42.430730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3777 16:30:42.430784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3778 16:30:42.430838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3779 16:30:42.430891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3780 16:30:42.430944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3781 16:30:42.430996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3782 16:30:42.431048 [ANA_INIT] flow start
3783 16:30:42.431100 [ANA_INIT] PLL >>>>>>>>
3784 16:30:42.431152 [ANA_INIT] PLL <<<<<<<<
3785 16:30:42.431203 [ANA_INIT] MIDPI >>>>>>>>
3786 16:30:42.431255 [ANA_INIT] MIDPI <<<<<<<<
3787 16:30:42.431307 [ANA_INIT] DLL >>>>>>>>
3788 16:30:42.431560 [ANA_INIT] flow end
3789 16:30:42.431622 ============ LP4 DIFF to SE enter ============
3790 16:30:42.431677 ============ LP4 DIFF to SE exit ============
3791 16:30:42.431731 [ANA_INIT] <<<<<<<<<<<<<
3792 16:30:42.431784 [Flow] Enable top DCM control >>>>>
3793 16:30:42.431836 [Flow] Enable top DCM control <<<<<
3794 16:30:42.431888 Enable DLL master slave shuffle
3795 16:30:42.431940 ==============================================================
3796 16:30:42.431993 Gating Mode config
3797 16:30:42.432046 ==============================================================
3798 16:30:42.432099 Config description:
3799 16:30:42.432174 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3800 16:30:42.432229 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3801 16:30:42.432282 SELPH_MODE 0: By rank 1: By Phase
3802 16:30:42.432336 ==============================================================
3803 16:30:42.432388 GAT_TRACK_EN = 1
3804 16:30:42.432441 RX_GATING_MODE = 2
3805 16:30:42.432493 RX_GATING_TRACK_MODE = 2
3806 16:30:42.432545 SELPH_MODE = 1
3807 16:30:42.432597 PICG_EARLY_EN = 1
3808 16:30:42.432649 VALID_LAT_VALUE = 1
3809 16:30:42.432702 ==============================================================
3810 16:30:42.433183 Enter into Gating configuration >>>>
3811 16:30:42.436433 Exit from Gating configuration <<<<
3812 16:30:42.439514 Enter into DVFS_PRE_config >>>>>
3813 16:30:42.449903 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3814 16:30:42.453061 Exit from DVFS_PRE_config <<<<<
3815 16:30:42.456191 Enter into PICG configuration >>>>
3816 16:30:42.459628 Exit from PICG configuration <<<<
3817 16:30:42.462826 [RX_INPUT] configuration >>>>>
3818 16:30:42.466056 [RX_INPUT] configuration <<<<<
3819 16:30:42.469194 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3820 16:30:42.475695 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3821 16:30:42.482200 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3822 16:30:42.489237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3823 16:30:42.495662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3824 16:30:42.502145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3825 16:30:42.505511 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3826 16:30:42.508651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3827 16:30:42.512190 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3828 16:30:42.519018 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3829 16:30:42.521851 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3830 16:30:42.525272 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 16:30:42.528731 ===================================
3832 16:30:42.531523 LPDDR4 DRAM CONFIGURATION
3833 16:30:42.535102 ===================================
3834 16:30:42.538488 EX_ROW_EN[0] = 0x0
3835 16:30:42.538585 EX_ROW_EN[1] = 0x0
3836 16:30:42.541935 LP4Y_EN = 0x0
3837 16:30:42.542022 WORK_FSP = 0x0
3838 16:30:42.545173 WL = 0x2
3839 16:30:42.545308 RL = 0x2
3840 16:30:42.548007 BL = 0x2
3841 16:30:42.548095 RPST = 0x0
3842 16:30:42.551403 RD_PRE = 0x0
3843 16:30:42.551489 WR_PRE = 0x1
3844 16:30:42.555232 WR_PST = 0x0
3845 16:30:42.555318 DBI_WR = 0x0
3846 16:30:42.558541 DBI_RD = 0x0
3847 16:30:42.558626 OTF = 0x1
3848 16:30:42.561665 ===================================
3849 16:30:42.568165 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3850 16:30:42.571394 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3851 16:30:42.574725 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 16:30:42.577964 ===================================
3853 16:30:42.581163 LPDDR4 DRAM CONFIGURATION
3854 16:30:42.584498 ===================================
3855 16:30:42.587776 EX_ROW_EN[0] = 0x10
3856 16:30:42.587890 EX_ROW_EN[1] = 0x0
3857 16:30:42.590915 LP4Y_EN = 0x0
3858 16:30:42.591023 WORK_FSP = 0x0
3859 16:30:42.594225 WL = 0x2
3860 16:30:42.594311 RL = 0x2
3861 16:30:42.598075 BL = 0x2
3862 16:30:42.598161 RPST = 0x0
3863 16:30:42.601185 RD_PRE = 0x0
3864 16:30:42.601279 WR_PRE = 0x1
3865 16:30:42.604394 WR_PST = 0x0
3866 16:30:42.604477 DBI_WR = 0x0
3867 16:30:42.607591 DBI_RD = 0x0
3868 16:30:42.607676 OTF = 0x1
3869 16:30:42.611162 ===================================
3870 16:30:42.617465 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3871 16:30:42.622308 nWR fixed to 30
3872 16:30:42.625513 [ModeRegInit_LP4] CH0 RK0
3873 16:30:42.625606 [ModeRegInit_LP4] CH0 RK1
3874 16:30:42.628914 [ModeRegInit_LP4] CH1 RK0
3875 16:30:42.631874 [ModeRegInit_LP4] CH1 RK1
3876 16:30:42.631962 match AC timing 17
3877 16:30:42.638475 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3878 16:30:42.642241 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3879 16:30:42.645335 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3880 16:30:42.651949 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3881 16:30:42.654996 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3882 16:30:42.655092 ==
3883 16:30:42.658347 Dram Type= 6, Freq= 0, CH_0, rank 0
3884 16:30:42.661766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3885 16:30:42.665175 ==
3886 16:30:42.668468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3887 16:30:42.675002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3888 16:30:42.678146 [CA 0] Center 36 (6~67) winsize 62
3889 16:30:42.681414 [CA 1] Center 35 (5~66) winsize 62
3890 16:30:42.684633 [CA 2] Center 34 (3~65) winsize 63
3891 16:30:42.687821 [CA 3] Center 34 (3~65) winsize 63
3892 16:30:42.690991 [CA 4] Center 33 (3~64) winsize 62
3893 16:30:42.694842 [CA 5] Center 33 (3~64) winsize 62
3894 16:30:42.694942
3895 16:30:42.697433 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3896 16:30:42.697520
3897 16:30:42.701302 [CATrainingPosCal] consider 1 rank data
3898 16:30:42.704500 u2DelayCellTimex100 = 270/100 ps
3899 16:30:42.707641 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3900 16:30:42.710818 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3901 16:30:42.717752 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3902 16:30:42.720945 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3903 16:30:42.723988 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3904 16:30:42.727398 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3905 16:30:42.727511
3906 16:30:42.730910 CA PerBit enable=1, Macro0, CA PI delay=33
3907 16:30:42.730998
3908 16:30:42.733908 [CBTSetCACLKResult] CA Dly = 33
3909 16:30:42.734056 CS Dly: 5 (0~36)
3910 16:30:42.737600 ==
3911 16:30:42.737689 Dram Type= 6, Freq= 0, CH_0, rank 1
3912 16:30:42.744151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 16:30:42.744251 ==
3914 16:30:42.747020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 16:30:42.753942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3916 16:30:42.757926 [CA 0] Center 36 (6~67) winsize 62
3917 16:30:42.761090 [CA 1] Center 36 (6~67) winsize 62
3918 16:30:42.764272 [CA 2] Center 34 (4~65) winsize 62
3919 16:30:42.769217 [CA 3] Center 34 (4~65) winsize 62
3920 16:30:42.770895 [CA 4] Center 33 (3~64) winsize 62
3921 16:30:42.773923 [CA 5] Center 33 (3~64) winsize 62
3922 16:30:42.774016
3923 16:30:42.777083 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3924 16:30:42.777180
3925 16:30:42.780834 [CATrainingPosCal] consider 2 rank data
3926 16:30:42.784162 u2DelayCellTimex100 = 270/100 ps
3927 16:30:42.787339 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 16:30:42.793779 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3929 16:30:42.796967 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 16:30:42.800110 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 16:30:42.803931 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3932 16:30:42.807077 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 16:30:42.807174
3934 16:30:42.810514 CA PerBit enable=1, Macro0, CA PI delay=33
3935 16:30:42.810666
3936 16:30:42.813655 [CBTSetCACLKResult] CA Dly = 33
3937 16:30:42.816948 CS Dly: 5 (0~37)
3938 16:30:42.817113
3939 16:30:42.820126 ----->DramcWriteLeveling(PI) begin...
3940 16:30:42.820231 ==
3941 16:30:42.823389 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 16:30:42.826486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 16:30:42.826594 ==
3944 16:30:42.830196 Write leveling (Byte 0): 32 => 32
3945 16:30:42.833245 Write leveling (Byte 1): 31 => 31
3946 16:30:42.836374 DramcWriteLeveling(PI) end<-----
3947 16:30:42.836499
3948 16:30:42.836598 ==
3949 16:30:42.840029 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 16:30:42.842916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 16:30:42.843051 ==
3952 16:30:42.846418 [Gating] SW mode calibration
3953 16:30:42.852999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3954 16:30:42.859509 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3955 16:30:42.863354 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3956 16:30:42.869546 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3957 16:30:42.872736 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3958 16:30:42.875989 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
3959 16:30:42.882270 0 9 16 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (0 0)
3960 16:30:42.885747 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 16:30:42.889035 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 16:30:42.895578 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 16:30:42.898784 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 16:30:42.902623 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 16:30:42.909120 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 16:30:42.912430 0 10 12 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
3967 16:30:42.915665 0 10 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
3968 16:30:42.922090 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 16:30:42.925204 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 16:30:42.928375 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 16:30:42.934830 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 16:30:42.938644 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 16:30:42.941674 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 16:30:42.948327 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3975 16:30:42.951262 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3976 16:30:42.954532 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 16:30:42.961342 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 16:30:42.964942 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 16:30:42.967890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 16:30:42.974454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 16:30:42.977691 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 16:30:42.980920 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 16:30:42.988099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 16:30:42.991269 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 16:30:42.994359 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 16:30:43.001129 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 16:30:43.004244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 16:30:43.007544 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 16:30:43.014045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 16:30:43.017277 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3991 16:30:43.020490 Total UI for P1: 0, mck2ui 16
3992 16:30:43.023743 best dqsien dly found for B0: ( 0, 13, 10)
3993 16:30:43.027382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 16:30:43.030522 Total UI for P1: 0, mck2ui 16
3995 16:30:43.033618 best dqsien dly found for B1: ( 0, 13, 12)
3996 16:30:43.037419 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
3997 16:30:43.040590 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
3998 16:30:43.040674
3999 16:30:43.046763 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4000 16:30:43.050634 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4001 16:30:43.053580 [Gating] SW calibration Done
4002 16:30:43.053660 ==
4003 16:30:43.056713 Dram Type= 6, Freq= 0, CH_0, rank 0
4004 16:30:43.060336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4005 16:30:43.060458 ==
4006 16:30:43.060555 RX Vref Scan: 0
4007 16:30:43.063597
4008 16:30:43.063671 RX Vref 0 -> 0, step: 1
4009 16:30:43.063733
4010 16:30:43.066984 RX Delay -230 -> 252, step: 16
4011 16:30:43.070321 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4012 16:30:43.076268 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4013 16:30:43.079878 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4014 16:30:43.083352 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4015 16:30:43.086294 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4016 16:30:43.093026 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4017 16:30:43.096218 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4018 16:30:43.099441 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4019 16:30:43.103197 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4020 16:30:43.106351 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4021 16:30:43.112671 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4022 16:30:43.116230 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4023 16:30:43.119461 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4024 16:30:43.122627 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4025 16:30:43.129117 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4026 16:30:43.132740 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4027 16:30:43.132855 ==
4028 16:30:43.136122 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 16:30:43.139154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 16:30:43.139241 ==
4031 16:30:43.142379 DQS Delay:
4032 16:30:43.142466 DQS0 = 0, DQS1 = 0
4033 16:30:43.145618 DQM Delay:
4034 16:30:43.145773 DQM0 = 42, DQM1 = 35
4035 16:30:43.145877 DQ Delay:
4036 16:30:43.148728 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4037 16:30:43.152325 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4038 16:30:43.155677 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4039 16:30:43.158811 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4040 16:30:43.158896
4041 16:30:43.158976
4042 16:30:43.162185 ==
4043 16:30:43.165331 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 16:30:43.168783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 16:30:43.168895 ==
4046 16:30:43.168995
4047 16:30:43.169090
4048 16:30:43.171889 TX Vref Scan disable
4049 16:30:43.171970 == TX Byte 0 ==
4050 16:30:43.178296 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4051 16:30:43.182079 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4052 16:30:43.182169 == TX Byte 1 ==
4053 16:30:43.188280 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4054 16:30:43.192029 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4055 16:30:43.192119 ==
4056 16:30:43.194809 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 16:30:43.198270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 16:30:43.198362 ==
4059 16:30:43.198458
4060 16:30:43.198517
4061 16:30:43.201421 TX Vref Scan disable
4062 16:30:43.204787 == TX Byte 0 ==
4063 16:30:43.207998 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4064 16:30:43.211335 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4065 16:30:43.214471 == TX Byte 1 ==
4066 16:30:43.218132 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4067 16:30:43.221158 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4068 16:30:43.224643
4069 16:30:43.224733 [DATLAT]
4070 16:30:43.224798 Freq=600, CH0 RK0
4071 16:30:43.224858
4072 16:30:43.228170 DATLAT Default: 0x9
4073 16:30:43.228252 0, 0xFFFF, sum = 0
4074 16:30:43.231395 1, 0xFFFF, sum = 0
4075 16:30:43.231505 2, 0xFFFF, sum = 0
4076 16:30:43.234580 3, 0xFFFF, sum = 0
4077 16:30:43.237802 4, 0xFFFF, sum = 0
4078 16:30:43.237896 5, 0xFFFF, sum = 0
4079 16:30:43.240734 6, 0xFFFF, sum = 0
4080 16:30:43.240818 7, 0xFFFF, sum = 0
4081 16:30:43.244013 8, 0x0, sum = 1
4082 16:30:43.244097 9, 0x0, sum = 2
4083 16:30:43.244162 10, 0x0, sum = 3
4084 16:30:43.247919 11, 0x0, sum = 4
4085 16:30:43.248035 best_step = 9
4086 16:30:43.248100
4087 16:30:43.248173 ==
4088 16:30:43.250943 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 16:30:43.257737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 16:30:43.257828 ==
4091 16:30:43.257893 RX Vref Scan: 1
4092 16:30:43.257953
4093 16:30:43.261066 RX Vref 0 -> 0, step: 1
4094 16:30:43.261173
4095 16:30:43.264356 RX Delay -195 -> 252, step: 8
4096 16:30:43.264446
4097 16:30:43.267646 Set Vref, RX VrefLevel [Byte0]: 55
4098 16:30:43.270537 [Byte1]: 58
4099 16:30:43.270620
4100 16:30:43.274061 Final RX Vref Byte 0 = 55 to rank0
4101 16:30:43.277186 Final RX Vref Byte 1 = 58 to rank0
4102 16:30:43.280606 Final RX Vref Byte 0 = 55 to rank1
4103 16:30:43.283878 Final RX Vref Byte 1 = 58 to rank1==
4104 16:30:43.286974 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 16:30:43.290794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 16:30:43.293973 ==
4107 16:30:43.294060 DQS Delay:
4108 16:30:43.294123 DQS0 = 0, DQS1 = 0
4109 16:30:43.297196 DQM Delay:
4110 16:30:43.297337 DQM0 = 41, DQM1 = 33
4111 16:30:43.300148 DQ Delay:
4112 16:30:43.300250 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4113 16:30:43.303680 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4114 16:30:43.307259 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =32
4115 16:30:43.310248 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4116 16:30:43.313450
4117 16:30:43.313547
4118 16:30:43.319873 [DQSOSCAuto] RK0, (LSB)MR18= 0x5048, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4119 16:30:43.323257 CH0 RK0: MR19=808, MR18=5048
4120 16:30:43.330315 CH0_RK0: MR19=0x808, MR18=0x5048, DQSOSC=394, MR23=63, INC=168, DEC=112
4121 16:30:43.330401
4122 16:30:43.333215 ----->DramcWriteLeveling(PI) begin...
4123 16:30:43.333353 ==
4124 16:30:43.336487 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 16:30:43.339991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 16:30:43.340114 ==
4127 16:30:43.343083 Write leveling (Byte 0): 31 => 31
4128 16:30:43.346230 Write leveling (Byte 1): 28 => 28
4129 16:30:43.349588 DramcWriteLeveling(PI) end<-----
4130 16:30:43.349671
4131 16:30:43.349735 ==
4132 16:30:43.353217 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 16:30:43.356573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 16:30:43.356656 ==
4135 16:30:43.359632 [Gating] SW mode calibration
4136 16:30:43.366167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4137 16:30:43.372579 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4138 16:30:43.375801 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4139 16:30:43.382690 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4140 16:30:43.385656 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4141 16:30:43.389285 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4142 16:30:43.396106 0 9 16 | B1->B0 | 2f2f 2323 | 1 1 | (1 1) (1 0)
4143 16:30:43.399539 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4144 16:30:43.402663 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 16:30:43.408820 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 16:30:43.412367 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 16:30:43.415356 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 16:30:43.422112 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 16:30:43.425523 0 10 12 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
4150 16:30:43.428728 0 10 16 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
4151 16:30:43.435235 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4152 16:30:43.438453 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 16:30:43.442215 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 16:30:43.448583 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 16:30:43.451806 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 16:30:43.455267 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 16:30:43.461792 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4158 16:30:43.465492 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4159 16:30:43.468609 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 16:30:43.474906 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 16:30:43.478115 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 16:30:43.481248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 16:30:43.488105 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 16:30:43.491388 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 16:30:43.494579 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 16:30:43.501449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 16:30:43.504372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 16:30:43.508079 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 16:30:43.514460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 16:30:43.517584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 16:30:43.521235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 16:30:43.527553 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 16:30:43.530777 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4174 16:30:43.534536 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 16:30:43.537245 Total UI for P1: 0, mck2ui 16
4176 16:30:43.540492 best dqsien dly found for B0: ( 0, 13, 12)
4177 16:30:43.544439 Total UI for P1: 0, mck2ui 16
4178 16:30:43.547628 best dqsien dly found for B1: ( 0, 13, 12)
4179 16:30:43.550798 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4180 16:30:43.553989 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4181 16:30:43.554063
4182 16:30:43.560768 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4183 16:30:43.563636 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4184 16:30:43.567291 [Gating] SW calibration Done
4185 16:30:43.567375 ==
4186 16:30:43.570597 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 16:30:43.573885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 16:30:43.573963 ==
4189 16:30:43.574027 RX Vref Scan: 0
4190 16:30:43.574095
4191 16:30:43.577180 RX Vref 0 -> 0, step: 1
4192 16:30:43.577262
4193 16:30:43.580076 RX Delay -230 -> 252, step: 16
4194 16:30:43.583352 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4195 16:30:43.590416 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4196 16:30:43.593622 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4197 16:30:43.596837 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4198 16:30:43.600129 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4199 16:30:43.603254 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4200 16:30:43.609800 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4201 16:30:43.613509 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4202 16:30:43.616677 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4203 16:30:43.619750 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4204 16:30:43.626315 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4205 16:30:43.629854 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4206 16:30:43.632896 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4207 16:30:43.636525 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4208 16:30:43.642880 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4209 16:30:43.646198 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4210 16:30:43.646291 ==
4211 16:30:43.649503 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 16:30:43.652661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 16:30:43.652740 ==
4214 16:30:43.655934 DQS Delay:
4215 16:30:43.656006 DQS0 = 0, DQS1 = 0
4216 16:30:43.656068 DQM Delay:
4217 16:30:43.659691 DQM0 = 43, DQM1 = 34
4218 16:30:43.659775 DQ Delay:
4219 16:30:43.662939 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4220 16:30:43.666152 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4221 16:30:43.669437 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4222 16:30:43.672587 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4223 16:30:43.672672
4224 16:30:43.672796
4225 16:30:43.672891 ==
4226 16:30:43.675797 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 16:30:43.682539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 16:30:43.682628 ==
4229 16:30:43.682694
4230 16:30:43.682754
4231 16:30:43.682810 TX Vref Scan disable
4232 16:30:43.686521 == TX Byte 0 ==
4233 16:30:43.689906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4234 16:30:43.696144 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4235 16:30:43.696284 == TX Byte 1 ==
4236 16:30:43.699493 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4237 16:30:43.706231 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4238 16:30:43.706329 ==
4239 16:30:43.709491 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 16:30:43.712727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 16:30:43.712815 ==
4242 16:30:43.712881
4243 16:30:43.712942
4244 16:30:43.716281 TX Vref Scan disable
4245 16:30:43.719285 == TX Byte 0 ==
4246 16:30:43.722444 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4247 16:30:43.726264 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4248 16:30:43.729461 == TX Byte 1 ==
4249 16:30:43.732644 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4250 16:30:43.735708 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4251 16:30:43.735786
4252 16:30:43.739363 [DATLAT]
4253 16:30:43.739443 Freq=600, CH0 RK1
4254 16:30:43.739506
4255 16:30:43.742535 DATLAT Default: 0x9
4256 16:30:43.742610 0, 0xFFFF, sum = 0
4257 16:30:43.746089 1, 0xFFFF, sum = 0
4258 16:30:43.746167 2, 0xFFFF, sum = 0
4259 16:30:43.749336 3, 0xFFFF, sum = 0
4260 16:30:43.749419 4, 0xFFFF, sum = 0
4261 16:30:43.752594 5, 0xFFFF, sum = 0
4262 16:30:43.752676 6, 0xFFFF, sum = 0
4263 16:30:43.755888 7, 0xFFFF, sum = 0
4264 16:30:43.755965 8, 0x0, sum = 1
4265 16:30:43.759196 9, 0x0, sum = 2
4266 16:30:43.759284 10, 0x0, sum = 3
4267 16:30:43.762192 11, 0x0, sum = 4
4268 16:30:43.762277 best_step = 9
4269 16:30:43.762343
4270 16:30:43.762404 ==
4271 16:30:43.765555 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 16:30:43.768755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 16:30:43.768845 ==
4274 16:30:43.771905 RX Vref Scan: 0
4275 16:30:43.771989
4276 16:30:43.775719 RX Vref 0 -> 0, step: 1
4277 16:30:43.775808
4278 16:30:43.775873 RX Delay -195 -> 252, step: 8
4279 16:30:43.783352 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4280 16:30:43.786592 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4281 16:30:43.790274 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4282 16:30:43.793342 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4283 16:30:43.799634 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4284 16:30:43.803471 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4285 16:30:43.806404 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4286 16:30:43.809836 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4287 16:30:43.816148 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4288 16:30:43.819967 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4289 16:30:43.822997 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4290 16:30:43.825967 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4291 16:30:43.832939 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4292 16:30:43.836160 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4293 16:30:43.839399 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4294 16:30:43.842712 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4295 16:30:43.842807 ==
4296 16:30:43.846107 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 16:30:43.852515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 16:30:43.852622 ==
4299 16:30:43.852696 DQS Delay:
4300 16:30:43.855628 DQS0 = 0, DQS1 = 0
4301 16:30:43.855712 DQM Delay:
4302 16:30:43.859347 DQM0 = 41, DQM1 = 33
4303 16:30:43.859432 DQ Delay:
4304 16:30:43.862515 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4305 16:30:43.865701 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =48
4306 16:30:43.868958 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4307 16:30:43.872238 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4308 16:30:43.872327
4309 16:30:43.872392
4310 16:30:43.878667 [DQSOSCAuto] RK1, (LSB)MR18= 0x433e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4311 16:30:43.881905 CH0 RK1: MR19=808, MR18=433E
4312 16:30:43.888877 CH0_RK1: MR19=0x808, MR18=0x433E, DQSOSC=397, MR23=63, INC=166, DEC=110
4313 16:30:43.892097 [RxdqsGatingPostProcess] freq 600
4314 16:30:43.898921 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4315 16:30:43.899023 Pre-setting of DQS Precalculation
4316 16:30:43.905270 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4317 16:30:43.905362 ==
4318 16:30:43.908406 Dram Type= 6, Freq= 0, CH_1, rank 0
4319 16:30:43.911558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 16:30:43.911643 ==
4321 16:30:43.918733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4322 16:30:43.925191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4323 16:30:43.928077 [CA 0] Center 35 (5~66) winsize 62
4324 16:30:43.931581 [CA 1] Center 35 (5~66) winsize 62
4325 16:30:43.934827 [CA 2] Center 34 (4~65) winsize 62
4326 16:30:43.937770 [CA 3] Center 34 (3~65) winsize 63
4327 16:30:43.941167 [CA 4] Center 34 (4~65) winsize 62
4328 16:30:43.944613 [CA 5] Center 33 (3~64) winsize 62
4329 16:30:43.944696
4330 16:30:43.947755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4331 16:30:43.947850
4332 16:30:43.950985 [CATrainingPosCal] consider 1 rank data
4333 16:30:43.954801 u2DelayCellTimex100 = 270/100 ps
4334 16:30:43.957781 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4335 16:30:43.961189 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4336 16:30:43.964422 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4337 16:30:43.967534 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4338 16:30:43.974420 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4339 16:30:43.977693 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4340 16:30:43.977780
4341 16:30:43.980896 CA PerBit enable=1, Macro0, CA PI delay=33
4342 16:30:43.980975
4343 16:30:43.984073 [CBTSetCACLKResult] CA Dly = 33
4344 16:30:43.984146 CS Dly: 4 (0~35)
4345 16:30:43.984207 ==
4346 16:30:43.987307 Dram Type= 6, Freq= 0, CH_1, rank 1
4347 16:30:43.993668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 16:30:43.993757 ==
4349 16:30:43.996817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 16:30:44.003659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4351 16:30:44.007369 [CA 0] Center 36 (6~66) winsize 61
4352 16:30:44.010778 [CA 1] Center 35 (5~66) winsize 62
4353 16:30:44.013868 [CA 2] Center 34 (4~65) winsize 62
4354 16:30:44.017117 [CA 3] Center 33 (3~64) winsize 62
4355 16:30:44.020292 [CA 4] Center 34 (4~65) winsize 62
4356 16:30:44.023514 [CA 5] Center 34 (3~65) winsize 63
4357 16:30:44.023591
4358 16:30:44.026765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4359 16:30:44.026838
4360 16:30:44.029803 [CATrainingPosCal] consider 2 rank data
4361 16:30:44.033119 u2DelayCellTimex100 = 270/100 ps
4362 16:30:44.036859 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4363 16:30:44.043292 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 16:30:44.046390 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 16:30:44.049891 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 16:30:44.052927 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4367 16:30:44.056436 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 16:30:44.056527
4369 16:30:44.059748 CA PerBit enable=1, Macro0, CA PI delay=33
4370 16:30:44.059841
4371 16:30:44.062968 [CBTSetCACLKResult] CA Dly = 33
4372 16:30:44.066313 CS Dly: 4 (0~36)
4373 16:30:44.066391
4374 16:30:44.069420 ----->DramcWriteLeveling(PI) begin...
4375 16:30:44.069502 ==
4376 16:30:44.072771 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 16:30:44.076055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 16:30:44.076128 ==
4379 16:30:44.079806 Write leveling (Byte 0): 28 => 28
4380 16:30:44.082843 Write leveling (Byte 1): 32 => 32
4381 16:30:44.086269 DramcWriteLeveling(PI) end<-----
4382 16:30:44.086361
4383 16:30:44.086426 ==
4384 16:30:44.089476 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 16:30:44.092727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 16:30:44.092814 ==
4387 16:30:44.095815 [Gating] SW mode calibration
4388 16:30:44.102871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4389 16:30:44.109126 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4390 16:30:44.112761 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4391 16:30:44.115973 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4392 16:30:44.122515 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4393 16:30:44.125751 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (0 0)
4394 16:30:44.128924 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4395 16:30:44.135570 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 16:30:44.138853 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 16:30:44.142092 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 16:30:44.148532 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 16:30:44.151821 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 16:30:44.155355 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4401 16:30:44.161717 0 10 12 | B1->B0 | 3434 3939 | 0 0 | (0 0) (0 0)
4402 16:30:44.164972 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 16:30:44.168219 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 16:30:44.174770 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 16:30:44.178406 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 16:30:44.181367 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 16:30:44.187967 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 16:30:44.191255 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 16:30:44.197781 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4410 16:30:44.201071 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 16:30:44.204829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 16:30:44.211274 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 16:30:44.214413 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 16:30:44.217535 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 16:30:44.224687 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 16:30:44.227332 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 16:30:44.230720 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 16:30:44.237626 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 16:30:44.240695 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 16:30:44.243904 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 16:30:44.250475 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 16:30:44.253722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 16:30:44.257457 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 16:30:44.263532 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 16:30:44.267291 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4426 16:30:44.270450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 16:30:44.273564 Total UI for P1: 0, mck2ui 16
4428 16:30:44.276717 best dqsien dly found for B0: ( 0, 13, 12)
4429 16:30:44.279878 Total UI for P1: 0, mck2ui 16
4430 16:30:44.283610 best dqsien dly found for B1: ( 0, 13, 12)
4431 16:30:44.286674 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4432 16:30:44.290299 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4433 16:30:44.290396
4434 16:30:44.296558 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4435 16:30:44.300256 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4436 16:30:44.300378 [Gating] SW calibration Done
4437 16:30:44.303543 ==
4438 16:30:44.306482 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 16:30:44.309980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 16:30:44.310099 ==
4441 16:30:44.310193 RX Vref Scan: 0
4442 16:30:44.310278
4443 16:30:44.313136 RX Vref 0 -> 0, step: 1
4444 16:30:44.313249
4445 16:30:44.316477 RX Delay -230 -> 252, step: 16
4446 16:30:44.320002 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4447 16:30:44.322943 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4448 16:30:44.330131 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4449 16:30:44.333297 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4450 16:30:44.336567 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4451 16:30:44.339728 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4452 16:30:44.346140 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4453 16:30:44.349319 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4454 16:30:44.353093 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4455 16:30:44.356241 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4456 16:30:44.359387 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4457 16:30:44.366436 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4458 16:30:44.369503 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4459 16:30:44.372629 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4460 16:30:44.375806 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4461 16:30:44.382655 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4462 16:30:44.382789 ==
4463 16:30:44.385832 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 16:30:44.389525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 16:30:44.389662 ==
4466 16:30:44.389773 DQS Delay:
4467 16:30:44.392627 DQS0 = 0, DQS1 = 0
4468 16:30:44.392735 DQM Delay:
4469 16:30:44.395678 DQM0 = 44, DQM1 = 38
4470 16:30:44.395818 DQ Delay:
4471 16:30:44.399302 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4472 16:30:44.402190 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4473 16:30:44.405887 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4474 16:30:44.408973 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4475 16:30:44.409107
4476 16:30:44.409212
4477 16:30:44.409304 ==
4478 16:30:44.412024 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 16:30:44.418839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 16:30:44.418943 ==
4481 16:30:44.419011
4482 16:30:44.419111
4483 16:30:44.419203 TX Vref Scan disable
4484 16:30:44.422391 == TX Byte 0 ==
4485 16:30:44.425743 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4486 16:30:44.432178 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4487 16:30:44.432306 == TX Byte 1 ==
4488 16:30:44.435662 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4489 16:30:44.441913 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4490 16:30:44.442042 ==
4491 16:30:44.445173 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 16:30:44.448844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 16:30:44.448956 ==
4494 16:30:44.449063
4495 16:30:44.449155
4496 16:30:44.452092 TX Vref Scan disable
4497 16:30:44.455331 == TX Byte 0 ==
4498 16:30:44.458605 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 16:30:44.461922 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 16:30:44.464900 == TX Byte 1 ==
4501 16:30:44.468310 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4502 16:30:44.471357 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4503 16:30:44.471439
4504 16:30:44.475166 [DATLAT]
4505 16:30:44.475279 Freq=600, CH1 RK0
4506 16:30:44.475376
4507 16:30:44.478306 DATLAT Default: 0x9
4508 16:30:44.478411 0, 0xFFFF, sum = 0
4509 16:30:44.481417 1, 0xFFFF, sum = 0
4510 16:30:44.481503 2, 0xFFFF, sum = 0
4511 16:30:44.485108 3, 0xFFFF, sum = 0
4512 16:30:44.485213 4, 0xFFFF, sum = 0
4513 16:30:44.488277 5, 0xFFFF, sum = 0
4514 16:30:44.488386 6, 0xFFFF, sum = 0
4515 16:30:44.491466 7, 0xFFFF, sum = 0
4516 16:30:44.491577 8, 0x0, sum = 1
4517 16:30:44.494626 9, 0x0, sum = 2
4518 16:30:44.494732 10, 0x0, sum = 3
4519 16:30:44.497928 11, 0x0, sum = 4
4520 16:30:44.498045 best_step = 9
4521 16:30:44.498156
4522 16:30:44.498255 ==
4523 16:30:44.501127 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 16:30:44.504911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 16:30:44.507810 ==
4526 16:30:44.507944 RX Vref Scan: 1
4527 16:30:44.508043
4528 16:30:44.511493 RX Vref 0 -> 0, step: 1
4529 16:30:44.511602
4530 16:30:44.514603 RX Delay -179 -> 252, step: 8
4531 16:30:44.514716
4532 16:30:44.514813 Set Vref, RX VrefLevel [Byte0]: 51
4533 16:30:44.517832 [Byte1]: 50
4534 16:30:44.522922
4535 16:30:44.523028 Final RX Vref Byte 0 = 51 to rank0
4536 16:30:44.526073 Final RX Vref Byte 1 = 50 to rank0
4537 16:30:44.529797 Final RX Vref Byte 0 = 51 to rank1
4538 16:30:44.532800 Final RX Vref Byte 1 = 50 to rank1==
4539 16:30:44.535878 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 16:30:44.542920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 16:30:44.543042 ==
4542 16:30:44.543155 DQS Delay:
4543 16:30:44.545825 DQS0 = 0, DQS1 = 0
4544 16:30:44.545940 DQM Delay:
4545 16:30:44.546047 DQM0 = 41, DQM1 = 34
4546 16:30:44.548982 DQ Delay:
4547 16:30:44.552585 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4548 16:30:44.555918 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4549 16:30:44.559114 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4550 16:30:44.562369 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4551 16:30:44.562493
4552 16:30:44.562591
4553 16:30:44.568759 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4554 16:30:44.571851 CH1 RK0: MR19=808, MR18=2D47
4555 16:30:44.578611 CH1_RK0: MR19=0x808, MR18=0x2D47, DQSOSC=396, MR23=63, INC=167, DEC=111
4556 16:30:44.578742
4557 16:30:44.581994 ----->DramcWriteLeveling(PI) begin...
4558 16:30:44.582078 ==
4559 16:30:44.585613 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 16:30:44.588644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 16:30:44.588734 ==
4562 16:30:44.592397 Write leveling (Byte 0): 30 => 30
4563 16:30:44.595578 Write leveling (Byte 1): 30 => 30
4564 16:30:44.598896 DramcWriteLeveling(PI) end<-----
4565 16:30:44.599033
4566 16:30:44.599134 ==
4567 16:30:44.602184 Dram Type= 6, Freq= 0, CH_1, rank 1
4568 16:30:44.608461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 16:30:44.608585 ==
4570 16:30:44.608678 [Gating] SW mode calibration
4571 16:30:44.617967 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4572 16:30:44.621226 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4573 16:30:44.624487 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4574 16:30:44.631383 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4575 16:30:44.634649 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4576 16:30:44.638260 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4577 16:30:44.644549 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4578 16:30:44.647776 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4579 16:30:44.651405 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 16:30:44.657850 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 16:30:44.660769 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 16:30:44.664070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 16:30:44.670646 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4584 16:30:44.674552 0 10 12 | B1->B0 | 3333 4141 | 1 1 | (0 0) (0 0)
4585 16:30:44.677871 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4586 16:30:44.684332 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4587 16:30:44.687502 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4588 16:30:44.690787 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 16:30:44.697224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 16:30:44.700680 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 16:30:44.706845 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 16:30:44.710119 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4593 16:30:44.713719 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 16:30:44.720481 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 16:30:44.723480 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 16:30:44.727043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 16:30:44.733466 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 16:30:44.736740 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 16:30:44.739903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 16:30:44.746424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 16:30:44.749475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 16:30:44.753348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 16:30:44.759535 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 16:30:44.762669 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 16:30:44.766253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 16:30:44.772754 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 16:30:44.775949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 16:30:44.779229 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4609 16:30:44.782971 Total UI for P1: 0, mck2ui 16
4610 16:30:44.786350 best dqsien dly found for B0: ( 0, 13, 10)
4611 16:30:44.792282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 16:30:44.792408 Total UI for P1: 0, mck2ui 16
4613 16:30:44.799214 best dqsien dly found for B1: ( 0, 13, 12)
4614 16:30:44.802385 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4615 16:30:44.806126 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4616 16:30:44.806253
4617 16:30:44.808925 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4618 16:30:44.812410 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4619 16:30:44.815310 [Gating] SW calibration Done
4620 16:30:44.815424 ==
4621 16:30:44.818904 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 16:30:44.822029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 16:30:44.822153 ==
4624 16:30:44.825201 RX Vref Scan: 0
4625 16:30:44.825323
4626 16:30:44.825434 RX Vref 0 -> 0, step: 1
4627 16:30:44.828879
4628 16:30:44.828984 RX Delay -230 -> 252, step: 16
4629 16:30:44.835137 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4630 16:30:44.838476 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4631 16:30:44.841645 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4632 16:30:44.845253 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4633 16:30:44.851469 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4634 16:30:44.855129 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4635 16:30:44.858180 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4636 16:30:44.861966 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4637 16:30:44.865140 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4638 16:30:44.871394 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4639 16:30:44.874308 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4640 16:30:44.877999 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4641 16:30:44.884394 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4642 16:30:44.887722 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4643 16:30:44.890920 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4644 16:30:44.894115 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4645 16:30:44.894214 ==
4646 16:30:44.897386 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 16:30:44.904248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 16:30:44.904347 ==
4649 16:30:44.904415 DQS Delay:
4650 16:30:44.907488 DQS0 = 0, DQS1 = 0
4651 16:30:44.907587 DQM Delay:
4652 16:30:44.907678 DQM0 = 45, DQM1 = 42
4653 16:30:44.910590 DQ Delay:
4654 16:30:44.914164 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4655 16:30:44.917246 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4656 16:30:44.920283 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4657 16:30:44.923813 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =57
4658 16:30:44.923915
4659 16:30:44.924006
4660 16:30:44.924095 ==
4661 16:30:44.927111 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 16:30:44.930338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 16:30:44.930442 ==
4664 16:30:44.930532
4665 16:30:44.930621
4666 16:30:44.934103 TX Vref Scan disable
4667 16:30:44.937006 == TX Byte 0 ==
4668 16:30:44.940240 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4669 16:30:44.944058 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4670 16:30:44.947299 == TX Byte 1 ==
4671 16:30:44.950242 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4672 16:30:44.953428 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4673 16:30:44.953542 ==
4674 16:30:44.957112 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 16:30:44.960274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 16:30:44.963325 ==
4677 16:30:44.963405
4678 16:30:44.963468
4679 16:30:44.963533 TX Vref Scan disable
4680 16:30:44.967632 == TX Byte 0 ==
4681 16:30:44.970794 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4682 16:30:44.977192 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4683 16:30:44.977313 == TX Byte 1 ==
4684 16:30:44.980237 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4685 16:30:44.987469 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4686 16:30:44.987586
4687 16:30:44.987681 [DATLAT]
4688 16:30:44.987770 Freq=600, CH1 RK1
4689 16:30:44.987859
4690 16:30:44.990689 DATLAT Default: 0x9
4691 16:30:44.993957 0, 0xFFFF, sum = 0
4692 16:30:44.994034 1, 0xFFFF, sum = 0
4693 16:30:44.997172 2, 0xFFFF, sum = 0
4694 16:30:44.997278 3, 0xFFFF, sum = 0
4695 16:30:45.000402 4, 0xFFFF, sum = 0
4696 16:30:45.000491 5, 0xFFFF, sum = 0
4697 16:30:45.003622 6, 0xFFFF, sum = 0
4698 16:30:45.003709 7, 0xFFFF, sum = 0
4699 16:30:45.006824 8, 0x0, sum = 1
4700 16:30:45.006912 9, 0x0, sum = 2
4701 16:30:45.010102 10, 0x0, sum = 3
4702 16:30:45.010189 11, 0x0, sum = 4
4703 16:30:45.010256 best_step = 9
4704 16:30:45.010317
4705 16:30:45.013342 ==
4706 16:30:45.016529 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 16:30:45.020159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 16:30:45.020278 ==
4709 16:30:45.020348 RX Vref Scan: 0
4710 16:30:45.020411
4711 16:30:45.023362 RX Vref 0 -> 0, step: 1
4712 16:30:45.023447
4713 16:30:45.026540 RX Delay -179 -> 252, step: 8
4714 16:30:45.033120 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4715 16:30:45.036114 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4716 16:30:45.039582 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4717 16:30:45.043112 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4718 16:30:45.049578 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4719 16:30:45.052752 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4720 16:30:45.055789 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4721 16:30:45.059681 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4722 16:30:45.065932 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4723 16:30:45.068975 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4724 16:30:45.072629 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4725 16:30:45.075889 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4726 16:30:45.082293 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4727 16:30:45.085510 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4728 16:30:45.088610 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4729 16:30:45.092142 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4730 16:30:45.092230 ==
4731 16:30:45.095217 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 16:30:45.102387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 16:30:45.102489 ==
4734 16:30:45.102557 DQS Delay:
4735 16:30:45.104979 DQS0 = 0, DQS1 = 0
4736 16:30:45.105086 DQM Delay:
4737 16:30:45.105183 DQM0 = 37, DQM1 = 34
4738 16:30:45.108271 DQ Delay:
4739 16:30:45.111654 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4740 16:30:45.115462 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4741 16:30:45.118618 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4742 16:30:45.121702 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4743 16:30:45.121789
4744 16:30:45.121854
4745 16:30:45.128553 [DQSOSCAuto] RK1, (LSB)MR18= 0x385c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4746 16:30:45.131696 CH1 RK1: MR19=808, MR18=385C
4747 16:30:45.137976 CH1_RK1: MR19=0x808, MR18=0x385C, DQSOSC=392, MR23=63, INC=170, DEC=113
4748 16:30:45.141711 [RxdqsGatingPostProcess] freq 600
4749 16:30:45.148057 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4750 16:30:45.148147 Pre-setting of DQS Precalculation
4751 16:30:45.154460 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4752 16:30:45.161464 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4753 16:30:45.167620 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4754 16:30:45.167711
4755 16:30:45.167775
4756 16:30:45.170878 [Calibration Summary] 1200 Mbps
4757 16:30:45.174539 CH 0, Rank 0
4758 16:30:45.174639 SW Impedance : PASS
4759 16:30:45.177364 DUTY Scan : NO K
4760 16:30:45.180561 ZQ Calibration : PASS
4761 16:30:45.180647 Jitter Meter : NO K
4762 16:30:45.184470 CBT Training : PASS
4763 16:30:45.187348 Write leveling : PASS
4764 16:30:45.187431 RX DQS gating : PASS
4765 16:30:45.190582 RX DQ/DQS(RDDQC) : PASS
4766 16:30:45.193732 TX DQ/DQS : PASS
4767 16:30:45.193815 RX DATLAT : PASS
4768 16:30:45.197452 RX DQ/DQS(Engine): PASS
4769 16:30:45.200659 TX OE : NO K
4770 16:30:45.200746 All Pass.
4771 16:30:45.200811
4772 16:30:45.200871 CH 0, Rank 1
4773 16:30:45.203903 SW Impedance : PASS
4774 16:30:45.207057 DUTY Scan : NO K
4775 16:30:45.207142 ZQ Calibration : PASS
4776 16:30:45.210263 Jitter Meter : NO K
4777 16:30:45.213216 CBT Training : PASS
4778 16:30:45.213332 Write leveling : PASS
4779 16:30:45.216624 RX DQS gating : PASS
4780 16:30:45.220479 RX DQ/DQS(RDDQC) : PASS
4781 16:30:45.220561 TX DQ/DQS : PASS
4782 16:30:45.223704 RX DATLAT : PASS
4783 16:30:45.223786 RX DQ/DQS(Engine): PASS
4784 16:30:45.226925 TX OE : NO K
4785 16:30:45.227008 All Pass.
4786 16:30:45.227073
4787 16:30:45.230179 CH 1, Rank 0
4788 16:30:45.230261 SW Impedance : PASS
4789 16:30:45.233513 DUTY Scan : NO K
4790 16:30:45.236854 ZQ Calibration : PASS
4791 16:30:45.236958 Jitter Meter : NO K
4792 16:30:45.239766 CBT Training : PASS
4793 16:30:45.242821 Write leveling : PASS
4794 16:30:45.242897 RX DQS gating : PASS
4795 16:30:45.246520 RX DQ/DQS(RDDQC) : PASS
4796 16:30:45.249700 TX DQ/DQS : PASS
4797 16:30:45.249786 RX DATLAT : PASS
4798 16:30:45.252907 RX DQ/DQS(Engine): PASS
4799 16:30:45.256063 TX OE : NO K
4800 16:30:45.256136 All Pass.
4801 16:30:45.256196
4802 16:30:45.256253 CH 1, Rank 1
4803 16:30:45.259728 SW Impedance : PASS
4804 16:30:45.263308 DUTY Scan : NO K
4805 16:30:45.263391 ZQ Calibration : PASS
4806 16:30:45.266167 Jitter Meter : NO K
4807 16:30:45.269782 CBT Training : PASS
4808 16:30:45.269867 Write leveling : PASS
4809 16:30:45.272735 RX DQS gating : PASS
4810 16:30:45.276300 RX DQ/DQS(RDDQC) : PASS
4811 16:30:45.276400 TX DQ/DQS : PASS
4812 16:30:45.279396 RX DATLAT : PASS
4813 16:30:45.282756 RX DQ/DQS(Engine): PASS
4814 16:30:45.282841 TX OE : NO K
4815 16:30:45.286005 All Pass.
4816 16:30:45.286140
4817 16:30:45.286283 DramC Write-DBI off
4818 16:30:45.289107 PER_BANK_REFRESH: Hybrid Mode
4819 16:30:45.289229 TX_TRACKING: ON
4820 16:30:45.298616 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4821 16:30:45.302493 [FAST_K] Save calibration result to emmc
4822 16:30:45.305491 dramc_set_vcore_voltage set vcore to 662500
4823 16:30:45.308731 Read voltage for 933, 3
4824 16:30:45.308816 Vio18 = 0
4825 16:30:45.311882 Vcore = 662500
4826 16:30:45.311986 Vdram = 0
4827 16:30:45.312080 Vddq = 0
4828 16:30:45.314952 Vmddr = 0
4829 16:30:45.318756 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4830 16:30:45.325139 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4831 16:30:45.325254 MEM_TYPE=3, freq_sel=17
4832 16:30:45.328541 sv_algorithm_assistance_LP4_1600
4833 16:30:45.335103 ============ PULL DRAM RESETB DOWN ============
4834 16:30:45.338341 ========== PULL DRAM RESETB DOWN end =========
4835 16:30:45.341574 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4836 16:30:45.344773 ===================================
4837 16:30:45.348524 LPDDR4 DRAM CONFIGURATION
4838 16:30:45.351634 ===================================
4839 16:30:45.354855 EX_ROW_EN[0] = 0x0
4840 16:30:45.354945 EX_ROW_EN[1] = 0x0
4841 16:30:45.358027 LP4Y_EN = 0x0
4842 16:30:45.358113 WORK_FSP = 0x0
4843 16:30:45.361243 WL = 0x3
4844 16:30:45.361339 RL = 0x3
4845 16:30:45.364490 BL = 0x2
4846 16:30:45.364573 RPST = 0x0
4847 16:30:45.368160 RD_PRE = 0x0
4848 16:30:45.368247 WR_PRE = 0x1
4849 16:30:45.371585 WR_PST = 0x0
4850 16:30:45.371668 DBI_WR = 0x0
4851 16:30:45.374709 DBI_RD = 0x0
4852 16:30:45.374823 OTF = 0x1
4853 16:30:45.377807 ===================================
4854 16:30:45.381423 ===================================
4855 16:30:45.384262 ANA top config
4856 16:30:45.387930 ===================================
4857 16:30:45.391485 DLL_ASYNC_EN = 0
4858 16:30:45.391598 ALL_SLAVE_EN = 1
4859 16:30:45.394717 NEW_RANK_MODE = 1
4860 16:30:45.397588 DLL_IDLE_MODE = 1
4861 16:30:45.401141 LP45_APHY_COMB_EN = 1
4862 16:30:45.404529 TX_ODT_DIS = 1
4863 16:30:45.404623 NEW_8X_MODE = 1
4864 16:30:45.407479 ===================================
4865 16:30:45.410628 ===================================
4866 16:30:45.414326 data_rate = 1866
4867 16:30:45.417486 CKR = 1
4868 16:30:45.420812 DQ_P2S_RATIO = 8
4869 16:30:45.423996 ===================================
4870 16:30:45.427199 CA_P2S_RATIO = 8
4871 16:30:45.430461 DQ_CA_OPEN = 0
4872 16:30:45.430555 DQ_SEMI_OPEN = 0
4873 16:30:45.433834 CA_SEMI_OPEN = 0
4874 16:30:45.437424 CA_FULL_RATE = 0
4875 16:30:45.440646 DQ_CKDIV4_EN = 1
4876 16:30:45.443877 CA_CKDIV4_EN = 1
4877 16:30:45.447550 CA_PREDIV_EN = 0
4878 16:30:45.447641 PH8_DLY = 0
4879 16:30:45.450777 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4880 16:30:45.453872 DQ_AAMCK_DIV = 4
4881 16:30:45.456949 CA_AAMCK_DIV = 4
4882 16:30:45.460210 CA_ADMCK_DIV = 4
4883 16:30:45.463456 DQ_TRACK_CA_EN = 0
4884 16:30:45.466692 CA_PICK = 933
4885 16:30:45.466803 CA_MCKIO = 933
4886 16:30:45.469931 MCKIO_SEMI = 0
4887 16:30:45.473736 PLL_FREQ = 3732
4888 16:30:45.476844 DQ_UI_PI_RATIO = 32
4889 16:30:45.479964 CA_UI_PI_RATIO = 0
4890 16:30:45.483404 ===================================
4891 16:30:45.486439 ===================================
4892 16:30:45.490241 memory_type:LPDDR4
4893 16:30:45.490323 GP_NUM : 10
4894 16:30:45.493235 SRAM_EN : 1
4895 16:30:45.493345 MD32_EN : 0
4896 16:30:45.496445 ===================================
4897 16:30:45.499519 [ANA_INIT] >>>>>>>>>>>>>>
4898 16:30:45.503201 <<<<<< [CONFIGURE PHASE]: ANA_TX
4899 16:30:45.506345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4900 16:30:45.509250 ===================================
4901 16:30:45.512981 data_rate = 1866,PCW = 0X8f00
4902 16:30:45.515960 ===================================
4903 16:30:45.519018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4904 16:30:45.525791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4905 16:30:45.529074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4906 16:30:45.535496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4907 16:30:45.538773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4908 16:30:45.542541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4909 16:30:45.545548 [ANA_INIT] flow start
4910 16:30:45.545659 [ANA_INIT] PLL >>>>>>>>
4911 16:30:45.548931 [ANA_INIT] PLL <<<<<<<<
4912 16:30:45.552569 [ANA_INIT] MIDPI >>>>>>>>
4913 16:30:45.552683 [ANA_INIT] MIDPI <<<<<<<<
4914 16:30:45.555781 [ANA_INIT] DLL >>>>>>>>
4915 16:30:45.558971 [ANA_INIT] flow end
4916 16:30:45.561982 ============ LP4 DIFF to SE enter ============
4917 16:30:45.565253 ============ LP4 DIFF to SE exit ============
4918 16:30:45.568456 [ANA_INIT] <<<<<<<<<<<<<
4919 16:30:45.571720 [Flow] Enable top DCM control >>>>>
4920 16:30:45.575567 [Flow] Enable top DCM control <<<<<
4921 16:30:45.578770 Enable DLL master slave shuffle
4922 16:30:45.581864 ==============================================================
4923 16:30:45.584949 Gating Mode config
4924 16:30:45.591623 ==============================================================
4925 16:30:45.591766 Config description:
4926 16:30:45.601718 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4927 16:30:45.608319 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4928 16:30:45.615047 SELPH_MODE 0: By rank 1: By Phase
4929 16:30:45.618057 ==============================================================
4930 16:30:45.621076 GAT_TRACK_EN = 1
4931 16:30:45.624698 RX_GATING_MODE = 2
4932 16:30:45.627718 RX_GATING_TRACK_MODE = 2
4933 16:30:45.631057 SELPH_MODE = 1
4934 16:30:45.634345 PICG_EARLY_EN = 1
4935 16:30:45.638119 VALID_LAT_VALUE = 1
4936 16:30:45.641310 ==============================================================
4937 16:30:45.644576 Enter into Gating configuration >>>>
4938 16:30:45.647787 Exit from Gating configuration <<<<
4939 16:30:45.650881 Enter into DVFS_PRE_config >>>>>
4940 16:30:45.664098 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4941 16:30:45.667870 Exit from DVFS_PRE_config <<<<<
4942 16:30:45.670661 Enter into PICG configuration >>>>
4943 16:30:45.674423 Exit from PICG configuration <<<<
4944 16:30:45.674512 [RX_INPUT] configuration >>>>>
4945 16:30:45.677555 [RX_INPUT] configuration <<<<<
4946 16:30:45.683930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4947 16:30:45.687128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4948 16:30:45.694159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4949 16:30:45.700312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4950 16:30:45.707126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4951 16:30:45.713352 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4952 16:30:45.716897 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4953 16:30:45.720239 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4954 16:30:45.726912 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4955 16:30:45.730060 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4956 16:30:45.732994 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4957 16:30:45.739772 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4958 16:30:45.743143 ===================================
4959 16:30:45.743224 LPDDR4 DRAM CONFIGURATION
4960 16:30:45.746289 ===================================
4961 16:30:45.749506 EX_ROW_EN[0] = 0x0
4962 16:30:45.749592 EX_ROW_EN[1] = 0x0
4963 16:30:45.753279 LP4Y_EN = 0x0
4964 16:30:45.756548 WORK_FSP = 0x0
4965 16:30:45.756627 WL = 0x3
4966 16:30:45.759765 RL = 0x3
4967 16:30:45.759880 BL = 0x2
4968 16:30:45.762946 RPST = 0x0
4969 16:30:45.763047 RD_PRE = 0x0
4970 16:30:45.766738 WR_PRE = 0x1
4971 16:30:45.766878 WR_PST = 0x0
4972 16:30:45.769875 DBI_WR = 0x0
4973 16:30:45.769954 DBI_RD = 0x0
4974 16:30:45.772980 OTF = 0x1
4975 16:30:45.776333 ===================================
4976 16:30:45.779660 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4977 16:30:45.782854 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4978 16:30:45.789235 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 16:30:45.792489 ===================================
4980 16:30:45.792571 LPDDR4 DRAM CONFIGURATION
4981 16:30:45.796118 ===================================
4982 16:30:45.799626 EX_ROW_EN[0] = 0x10
4983 16:30:45.799745 EX_ROW_EN[1] = 0x0
4984 16:30:45.802720 LP4Y_EN = 0x0
4985 16:30:45.805921 WORK_FSP = 0x0
4986 16:30:45.806054 WL = 0x3
4987 16:30:45.809049 RL = 0x3
4988 16:30:45.809136 BL = 0x2
4989 16:30:45.812344 RPST = 0x0
4990 16:30:45.812453 RD_PRE = 0x0
4991 16:30:45.815693 WR_PRE = 0x1
4992 16:30:45.815776 WR_PST = 0x0
4993 16:30:45.819515 DBI_WR = 0x0
4994 16:30:45.819601 DBI_RD = 0x0
4995 16:30:45.822606 OTF = 0x1
4996 16:30:45.825599 ===================================
4997 16:30:45.832332 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4998 16:30:45.835496 nWR fixed to 30
4999 16:30:45.835583 [ModeRegInit_LP4] CH0 RK0
5000 16:30:45.839114 [ModeRegInit_LP4] CH0 RK1
5001 16:30:45.842002 [ModeRegInit_LP4] CH1 RK0
5002 16:30:45.845533 [ModeRegInit_LP4] CH1 RK1
5003 16:30:45.845613 match AC timing 9
5004 16:30:45.848587 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5005 16:30:45.855617 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5006 16:30:45.858908 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5007 16:30:45.864990 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5008 16:30:45.868843 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5009 16:30:45.868942 ==
5010 16:30:45.872300 Dram Type= 6, Freq= 0, CH_0, rank 0
5011 16:30:45.875260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5012 16:30:45.875346 ==
5013 16:30:45.881898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5014 16:30:45.888271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5015 16:30:45.891618 [CA 0] Center 37 (7~68) winsize 62
5016 16:30:45.894849 [CA 1] Center 37 (7~68) winsize 62
5017 16:30:45.897979 [CA 2] Center 34 (4~65) winsize 62
5018 16:30:45.901540 [CA 3] Center 34 (4~65) winsize 62
5019 16:30:45.904757 [CA 4] Center 33 (3~63) winsize 61
5020 16:30:45.907817 [CA 5] Center 33 (3~63) winsize 61
5021 16:30:45.907922
5022 16:30:45.911549 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5023 16:30:45.911624
5024 16:30:45.914740 [CATrainingPosCal] consider 1 rank data
5025 16:30:45.917949 u2DelayCellTimex100 = 270/100 ps
5026 16:30:45.921496 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5027 16:30:45.924685 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5028 16:30:45.927766 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5029 16:30:45.931555 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5030 16:30:45.934691 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5031 16:30:45.937620 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5032 16:30:45.937706
5033 16:30:45.944225 CA PerBit enable=1, Macro0, CA PI delay=33
5034 16:30:45.944323
5035 16:30:45.947808 [CBTSetCACLKResult] CA Dly = 33
5036 16:30:45.947888 CS Dly: 5 (0~36)
5037 16:30:45.947953 ==
5038 16:30:45.951269 Dram Type= 6, Freq= 0, CH_0, rank 1
5039 16:30:45.954176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5040 16:30:45.954280 ==
5041 16:30:45.960847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5042 16:30:45.967698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5043 16:30:45.970925 [CA 0] Center 37 (7~68) winsize 62
5044 16:30:45.974150 [CA 1] Center 37 (7~68) winsize 62
5045 16:30:45.977133 [CA 2] Center 34 (4~65) winsize 62
5046 16:30:45.980478 [CA 3] Center 34 (4~65) winsize 62
5047 16:30:45.983761 [CA 4] Center 33 (3~64) winsize 62
5048 16:30:45.987572 [CA 5] Center 32 (2~63) winsize 62
5049 16:30:45.987684
5050 16:30:45.990777 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5051 16:30:45.990888
5052 16:30:45.994140 [CATrainingPosCal] consider 2 rank data
5053 16:30:45.997292 u2DelayCellTimex100 = 270/100 ps
5054 16:30:46.000544 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5055 16:30:46.003627 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5056 16:30:46.006651 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5057 16:30:46.013368 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5058 16:30:46.017210 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5059 16:30:46.020557 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5060 16:30:46.020642
5061 16:30:46.023544 CA PerBit enable=1, Macro0, CA PI delay=33
5062 16:30:46.023628
5063 16:30:46.026729 [CBTSetCACLKResult] CA Dly = 33
5064 16:30:46.026814 CS Dly: 6 (0~39)
5065 16:30:46.026879
5066 16:30:46.030136 ----->DramcWriteLeveling(PI) begin...
5067 16:30:46.033440 ==
5068 16:30:46.033561 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 16:30:46.039833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 16:30:46.039965 ==
5071 16:30:46.042899 Write leveling (Byte 0): 34 => 34
5072 16:30:46.046482 Write leveling (Byte 1): 30 => 30
5073 16:30:46.049662 DramcWriteLeveling(PI) end<-----
5074 16:30:46.049771
5075 16:30:46.049874 ==
5076 16:30:46.052898 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 16:30:46.056582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 16:30:46.056673 ==
5079 16:30:46.059806 [Gating] SW mode calibration
5080 16:30:46.066474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5081 16:30:46.072600 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5082 16:30:46.076032 0 14 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5083 16:30:46.079305 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5084 16:30:46.085509 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5085 16:30:46.089283 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 16:30:46.092510 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 16:30:46.098870 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 16:30:46.102057 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5089 16:30:46.105285 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
5090 16:30:46.112231 0 15 0 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
5091 16:30:46.115319 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5092 16:30:46.118413 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 16:30:46.125383 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 16:30:46.128676 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 16:30:46.131610 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 16:30:46.138297 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 16:30:46.141520 0 15 28 | B1->B0 | 2525 3636 | 0 1 | (0 0) (0 0)
5098 16:30:46.144754 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5099 16:30:46.151705 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5100 16:30:46.154768 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 16:30:46.158070 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 16:30:46.165000 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 16:30:46.168173 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 16:30:46.171287 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 16:30:46.178281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5106 16:30:46.181572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5107 16:30:46.184800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5108 16:30:46.191098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 16:30:46.194339 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 16:30:46.197771 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 16:30:46.203923 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 16:30:46.207871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 16:30:46.211117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 16:30:46.217571 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 16:30:46.220549 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 16:30:46.223723 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 16:30:46.230614 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 16:30:46.233961 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 16:30:46.237089 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 16:30:46.243882 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5121 16:30:46.246760 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5122 16:30:46.250188 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5123 16:30:46.256895 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5124 16:30:46.257079 Total UI for P1: 0, mck2ui 16
5125 16:30:46.263459 best dqsien dly found for B0: ( 1, 2, 28)
5126 16:30:46.267082 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 16:30:46.270140 Total UI for P1: 0, mck2ui 16
5128 16:30:46.273399 best dqsien dly found for B1: ( 1, 3, 4)
5129 16:30:46.276568 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5130 16:30:46.279920 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5131 16:30:46.280034
5132 16:30:46.283080 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5133 16:30:46.286999 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5134 16:30:46.290286 [Gating] SW calibration Done
5135 16:30:46.290452 ==
5136 16:30:46.293699 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 16:30:46.296689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 16:30:46.299805 ==
5139 16:30:46.299923 RX Vref Scan: 0
5140 16:30:46.300022
5141 16:30:46.302981 RX Vref 0 -> 0, step: 1
5142 16:30:46.303192
5143 16:30:46.306512 RX Delay -80 -> 252, step: 8
5144 16:30:46.310147 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5145 16:30:46.312991 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5146 16:30:46.316536 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5147 16:30:46.319458 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5148 16:30:46.322613 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5149 16:30:46.329530 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5150 16:30:46.332608 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5151 16:30:46.335753 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5152 16:30:46.339007 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5153 16:30:46.342783 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5154 16:30:46.349184 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5155 16:30:46.352697 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5156 16:30:46.355639 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5157 16:30:46.359392 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5158 16:30:46.362596 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5159 16:30:46.365924 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5160 16:30:46.369052 ==
5161 16:30:46.372367 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 16:30:46.375389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 16:30:46.375549 ==
5164 16:30:46.375668 DQS Delay:
5165 16:30:46.378614 DQS0 = 0, DQS1 = 0
5166 16:30:46.378755 DQM Delay:
5167 16:30:46.382357 DQM0 = 99, DQM1 = 89
5168 16:30:46.382509 DQ Delay:
5169 16:30:46.385466 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5170 16:30:46.388675 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5171 16:30:46.391867 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5172 16:30:46.395049 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5173 16:30:46.395168
5174 16:30:46.395263
5175 16:30:46.395357 ==
5176 16:30:46.398327 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 16:30:46.401420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 16:30:46.404812 ==
5179 16:30:46.404927
5180 16:30:46.405025
5181 16:30:46.405116 TX Vref Scan disable
5182 16:30:46.408435 == TX Byte 0 ==
5183 16:30:46.411525 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5184 16:30:46.414757 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5185 16:30:46.417897 == TX Byte 1 ==
5186 16:30:46.421657 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5187 16:30:46.424734 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5188 16:30:46.427900 ==
5189 16:30:46.431295 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 16:30:46.434352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 16:30:46.434541 ==
5192 16:30:46.434699
5193 16:30:46.434848
5194 16:30:46.437850 TX Vref Scan disable
5195 16:30:46.438019 == TX Byte 0 ==
5196 16:30:46.444331 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5197 16:30:46.448037 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5198 16:30:46.448225 == TX Byte 1 ==
5199 16:30:46.454532 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5200 16:30:46.457513 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5201 16:30:46.457694
5202 16:30:46.457846 [DATLAT]
5203 16:30:46.461007 Freq=933, CH0 RK0
5204 16:30:46.461169
5205 16:30:46.461329 DATLAT Default: 0xd
5206 16:30:46.464000 0, 0xFFFF, sum = 0
5207 16:30:46.467359 1, 0xFFFF, sum = 0
5208 16:30:46.467535 2, 0xFFFF, sum = 0
5209 16:30:46.470345 3, 0xFFFF, sum = 0
5210 16:30:46.470525 4, 0xFFFF, sum = 0
5211 16:30:46.474045 5, 0xFFFF, sum = 0
5212 16:30:46.474219 6, 0xFFFF, sum = 0
5213 16:30:46.477199 7, 0xFFFF, sum = 0
5214 16:30:46.477367 8, 0xFFFF, sum = 0
5215 16:30:46.480482 9, 0xFFFF, sum = 0
5216 16:30:46.480635 10, 0x0, sum = 1
5217 16:30:46.483591 11, 0x0, sum = 2
5218 16:30:46.483740 12, 0x0, sum = 3
5219 16:30:46.487349 13, 0x0, sum = 4
5220 16:30:46.487516 best_step = 11
5221 16:30:46.487650
5222 16:30:46.487775 ==
5223 16:30:46.490564 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 16:30:46.493708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 16:30:46.496948 ==
5226 16:30:46.497050 RX Vref Scan: 1
5227 16:30:46.497131
5228 16:30:46.500112 RX Vref 0 -> 0, step: 1
5229 16:30:46.500209
5230 16:30:46.500289 RX Delay -61 -> 252, step: 4
5231 16:30:46.503348
5232 16:30:46.503475 Set Vref, RX VrefLevel [Byte0]: 55
5233 16:30:46.507048 [Byte1]: 58
5234 16:30:46.512083
5235 16:30:46.512298 Final RX Vref Byte 0 = 55 to rank0
5236 16:30:46.515272 Final RX Vref Byte 1 = 58 to rank0
5237 16:30:46.518303 Final RX Vref Byte 0 = 55 to rank1
5238 16:30:46.521500 Final RX Vref Byte 1 = 58 to rank1==
5239 16:30:46.525204 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 16:30:46.531628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 16:30:46.531741 ==
5242 16:30:46.531849 DQS Delay:
5243 16:30:46.534757 DQS0 = 0, DQS1 = 0
5244 16:30:46.534864 DQM Delay:
5245 16:30:46.534963 DQM0 = 99, DQM1 = 87
5246 16:30:46.537981 DQ Delay:
5247 16:30:46.541180 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =94
5248 16:30:46.544692 DQ4 =98, DQ5 =90, DQ6 =110, DQ7 =106
5249 16:30:46.547700 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5250 16:30:46.551506 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =92
5251 16:30:46.551631
5252 16:30:46.551730
5253 16:30:46.557695 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5254 16:30:46.560984 CH0 RK0: MR19=505, MR18=1D18
5255 16:30:46.568070 CH0_RK0: MR19=0x505, MR18=0x1D18, DQSOSC=412, MR23=63, INC=63, DEC=42
5256 16:30:46.568267
5257 16:30:46.571139 ----->DramcWriteLeveling(PI) begin...
5258 16:30:46.571327 ==
5259 16:30:46.574222 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 16:30:46.577750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 16:30:46.577935 ==
5262 16:30:46.581273 Write leveling (Byte 0): 29 => 29
5263 16:30:46.584504 Write leveling (Byte 1): 29 => 29
5264 16:30:46.587715 DramcWriteLeveling(PI) end<-----
5265 16:30:46.587926
5266 16:30:46.588065 ==
5267 16:30:46.590924 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 16:30:46.597540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 16:30:46.597723 ==
5270 16:30:46.597827 [Gating] SW mode calibration
5271 16:30:46.607296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5272 16:30:46.610360 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5273 16:30:46.616965 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5274 16:30:46.620229 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 16:30:46.623353 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 16:30:46.629849 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 16:30:46.633098 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 16:30:46.636394 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5279 16:30:46.643477 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5280 16:30:46.646713 0 14 28 | B1->B0 | 3333 2727 | 0 0 | (0 1) (0 1)
5281 16:30:46.650152 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5282 16:30:46.656585 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 16:30:46.659566 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 16:30:46.663272 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 16:30:46.670087 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5286 16:30:46.673184 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 16:30:46.676454 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5288 16:30:46.682684 0 15 28 | B1->B0 | 2d2d 4141 | 0 0 | (0 0) (1 1)
5289 16:30:46.686314 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5290 16:30:46.689593 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 16:30:46.695855 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 16:30:46.699623 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 16:30:46.702462 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 16:30:46.709530 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 16:30:46.712216 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5296 16:30:46.715454 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5297 16:30:46.722554 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5298 16:30:46.725893 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 16:30:46.728928 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 16:30:46.735584 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 16:30:46.738789 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 16:30:46.741982 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 16:30:46.748584 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 16:30:46.751783 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 16:30:46.755109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 16:30:46.762051 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 16:30:46.765461 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 16:30:46.768709 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 16:30:46.774939 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 16:30:46.778572 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 16:30:46.781659 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5312 16:30:46.788331 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5313 16:30:46.791462 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 16:30:46.794738 Total UI for P1: 0, mck2ui 16
5315 16:30:46.798043 best dqsien dly found for B0: ( 1, 2, 26)
5316 16:30:46.801028 Total UI for P1: 0, mck2ui 16
5317 16:30:46.804343 best dqsien dly found for B1: ( 1, 2, 28)
5318 16:30:46.807632 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5319 16:30:46.810787 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5320 16:30:46.810910
5321 16:30:46.814739 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5322 16:30:46.817860 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5323 16:30:46.821218 [Gating] SW calibration Done
5324 16:30:46.821318 ==
5325 16:30:46.824591 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 16:30:46.830623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 16:30:46.830725 ==
5328 16:30:46.830822 RX Vref Scan: 0
5329 16:30:46.830886
5330 16:30:46.834589 RX Vref 0 -> 0, step: 1
5331 16:30:46.834679
5332 16:30:46.837900 RX Delay -80 -> 252, step: 8
5333 16:30:46.840934 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5334 16:30:46.844225 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5335 16:30:46.847406 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5336 16:30:46.850550 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5337 16:30:46.856957 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5338 16:30:46.860847 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5339 16:30:46.863424 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5340 16:30:46.867085 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5341 16:30:46.870456 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5342 16:30:46.873729 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5343 16:30:46.880252 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5344 16:30:46.883487 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5345 16:30:46.886777 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5346 16:30:46.889951 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5347 16:30:46.893575 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5348 16:30:46.896665 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5349 16:30:46.900195 ==
5350 16:30:46.903205 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 16:30:46.906836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 16:30:46.906954 ==
5353 16:30:46.907030 DQS Delay:
5354 16:30:46.910010 DQS0 = 0, DQS1 = 0
5355 16:30:46.910103 DQM Delay:
5356 16:30:46.913377 DQM0 = 97, DQM1 = 91
5357 16:30:46.913462 DQ Delay:
5358 16:30:46.916549 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5359 16:30:46.919897 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5360 16:30:46.923024 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5361 16:30:46.926452 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5362 16:30:46.926566
5363 16:30:46.926637
5364 16:30:46.926697 ==
5365 16:30:46.929773 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 16:30:46.933116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 16:30:46.933336 ==
5368 16:30:46.936256
5369 16:30:46.936422
5370 16:30:46.936507 TX Vref Scan disable
5371 16:30:46.939593 == TX Byte 0 ==
5372 16:30:46.942872 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5373 16:30:46.946021 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5374 16:30:46.949440 == TX Byte 1 ==
5375 16:30:46.952614 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5376 16:30:46.955748 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5377 16:30:46.959185 ==
5378 16:30:46.959411 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 16:30:46.966322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 16:30:46.966522 ==
5381 16:30:46.966649
5382 16:30:46.966759
5383 16:30:46.969493 TX Vref Scan disable
5384 16:30:46.969599 == TX Byte 0 ==
5385 16:30:46.975878 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5386 16:30:46.979034 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5387 16:30:46.979220 == TX Byte 1 ==
5388 16:30:46.985488 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5389 16:30:46.988847 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5390 16:30:46.989037
5391 16:30:46.989181 [DATLAT]
5392 16:30:46.991987 Freq=933, CH0 RK1
5393 16:30:46.992166
5394 16:30:46.992296 DATLAT Default: 0xb
5395 16:30:46.995228 0, 0xFFFF, sum = 0
5396 16:30:46.995412 1, 0xFFFF, sum = 0
5397 16:30:46.998960 2, 0xFFFF, sum = 0
5398 16:30:46.999103 3, 0xFFFF, sum = 0
5399 16:30:47.002136 4, 0xFFFF, sum = 0
5400 16:30:47.005373 5, 0xFFFF, sum = 0
5401 16:30:47.005538 6, 0xFFFF, sum = 0
5402 16:30:47.008312 7, 0xFFFF, sum = 0
5403 16:30:47.008416 8, 0xFFFF, sum = 0
5404 16:30:47.011931 9, 0xFFFF, sum = 0
5405 16:30:47.012032 10, 0x0, sum = 1
5406 16:30:47.015433 11, 0x0, sum = 2
5407 16:30:47.015557 12, 0x0, sum = 3
5408 16:30:47.015661 13, 0x0, sum = 4
5409 16:30:47.018646 best_step = 11
5410 16:30:47.018747
5411 16:30:47.018837 ==
5412 16:30:47.021822 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 16:30:47.025212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 16:30:47.025368 ==
5415 16:30:47.028138 RX Vref Scan: 0
5416 16:30:47.028283
5417 16:30:47.031643 RX Vref 0 -> 0, step: 1
5418 16:30:47.031751
5419 16:30:47.031849 RX Delay -53 -> 252, step: 4
5420 16:30:47.039498 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5421 16:30:47.042599 iDelay=199, Bit 1, Center 100 (11 ~ 190) 180
5422 16:30:47.045741 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5423 16:30:47.049102 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5424 16:30:47.052341 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5425 16:30:47.058651 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5426 16:30:47.062044 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5427 16:30:47.065378 iDelay=199, Bit 7, Center 106 (19 ~ 194) 176
5428 16:30:47.068546 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5429 16:30:47.071821 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5430 16:30:47.075497 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5431 16:30:47.082084 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5432 16:30:47.085446 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5433 16:30:47.088579 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5434 16:30:47.091888 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5435 16:30:47.095117 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5436 16:30:47.098502 ==
5437 16:30:47.101677 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 16:30:47.104819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 16:30:47.104979 ==
5440 16:30:47.105092 DQS Delay:
5441 16:30:47.108076 DQS0 = 0, DQS1 = 0
5442 16:30:47.108237 DQM Delay:
5443 16:30:47.111747 DQM0 = 97, DQM1 = 89
5444 16:30:47.111930 DQ Delay:
5445 16:30:47.115036 DQ0 =96, DQ1 =100, DQ2 =92, DQ3 =94
5446 16:30:47.118074 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =106
5447 16:30:47.121074 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =84
5448 16:30:47.124774 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5449 16:30:47.124930
5450 16:30:47.125038
5451 16:30:47.131433 [DQSOSCAuto] RK1, (LSB)MR18= 0x1511, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5452 16:30:47.134712 CH0 RK1: MR19=505, MR18=1511
5453 16:30:47.140979 CH0_RK1: MR19=0x505, MR18=0x1511, DQSOSC=415, MR23=63, INC=62, DEC=41
5454 16:30:47.144040 [RxdqsGatingPostProcess] freq 933
5455 16:30:47.150957 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5456 16:30:47.154216 best DQS0 dly(2T, 0.5T) = (0, 10)
5457 16:30:47.157577 best DQS1 dly(2T, 0.5T) = (0, 11)
5458 16:30:47.160922 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5459 16:30:47.163896 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5460 16:30:47.167086 best DQS0 dly(2T, 0.5T) = (0, 10)
5461 16:30:47.167234 best DQS1 dly(2T, 0.5T) = (0, 10)
5462 16:30:47.170886 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5463 16:30:47.174270 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5464 16:30:47.177407 Pre-setting of DQS Precalculation
5465 16:30:47.183914 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5466 16:30:47.184094 ==
5467 16:30:47.187078 Dram Type= 6, Freq= 0, CH_1, rank 0
5468 16:30:47.190365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 16:30:47.190503 ==
5470 16:30:47.196891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5471 16:30:47.203437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5472 16:30:47.206623 [CA 0] Center 36 (6~67) winsize 62
5473 16:30:47.209977 [CA 1] Center 36 (6~67) winsize 62
5474 16:30:47.213282 [CA 2] Center 34 (4~65) winsize 62
5475 16:30:47.217050 [CA 3] Center 33 (3~64) winsize 62
5476 16:30:47.220244 [CA 4] Center 34 (3~65) winsize 63
5477 16:30:47.223358 [CA 5] Center 33 (3~64) winsize 62
5478 16:30:47.223494
5479 16:30:47.226654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5480 16:30:47.226784
5481 16:30:47.230365 [CATrainingPosCal] consider 1 rank data
5482 16:30:47.232922 u2DelayCellTimex100 = 270/100 ps
5483 16:30:47.236142 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5484 16:30:47.239444 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5485 16:30:47.242863 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5486 16:30:47.246094 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5487 16:30:47.249533 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5488 16:30:47.255871 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5489 16:30:47.256014
5490 16:30:47.259376 CA PerBit enable=1, Macro0, CA PI delay=33
5491 16:30:47.259494
5492 16:30:47.262571 [CBTSetCACLKResult] CA Dly = 33
5493 16:30:47.262660 CS Dly: 5 (0~36)
5494 16:30:47.262736 ==
5495 16:30:47.266113 Dram Type= 6, Freq= 0, CH_1, rank 1
5496 16:30:47.269224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 16:30:47.272378 ==
5498 16:30:47.275554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5499 16:30:47.282820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5500 16:30:47.285860 [CA 0] Center 36 (6~66) winsize 61
5501 16:30:47.289300 [CA 1] Center 36 (5~67) winsize 63
5502 16:30:47.292431 [CA 2] Center 34 (4~65) winsize 62
5503 16:30:47.295681 [CA 3] Center 33 (3~64) winsize 62
5504 16:30:47.298989 [CA 4] Center 33 (3~64) winsize 62
5505 16:30:47.302342 [CA 5] Center 33 (3~63) winsize 61
5506 16:30:47.302490
5507 16:30:47.305798 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5508 16:30:47.305986
5509 16:30:47.309031 [CATrainingPosCal] consider 2 rank data
5510 16:30:47.312267 u2DelayCellTimex100 = 270/100 ps
5511 16:30:47.315516 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5512 16:30:47.318753 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5513 16:30:47.325078 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5514 16:30:47.328316 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5515 16:30:47.332108 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 16:30:47.335312 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5517 16:30:47.335411
5518 16:30:47.338468 CA PerBit enable=1, Macro0, CA PI delay=33
5519 16:30:47.338550
5520 16:30:47.342000 [CBTSetCACLKResult] CA Dly = 33
5521 16:30:47.342080 CS Dly: 6 (0~38)
5522 16:30:47.342143
5523 16:30:47.345189 ----->DramcWriteLeveling(PI) begin...
5524 16:30:47.348545 ==
5525 16:30:47.351815 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 16:30:47.355115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 16:30:47.355197 ==
5528 16:30:47.358420 Write leveling (Byte 0): 27 => 27
5529 16:30:47.361637 Write leveling (Byte 1): 30 => 30
5530 16:30:47.364796 DramcWriteLeveling(PI) end<-----
5531 16:30:47.364925
5532 16:30:47.365033 ==
5533 16:30:47.368180 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 16:30:47.371455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 16:30:47.371556 ==
5536 16:30:47.374876 [Gating] SW mode calibration
5537 16:30:47.381470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5538 16:30:47.388013 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5539 16:30:47.391181 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5540 16:30:47.394582 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 16:30:47.400832 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 16:30:47.404243 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 16:30:47.407611 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 16:30:47.414156 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 16:30:47.417304 0 14 24 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
5546 16:30:47.420727 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
5547 16:30:47.427675 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 16:30:47.430843 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 16:30:47.434066 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 16:30:47.440492 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 16:30:47.443563 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 16:30:47.446958 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 16:30:47.453534 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5554 16:30:47.456869 0 15 28 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
5555 16:30:47.460559 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 16:30:47.466898 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 16:30:47.470068 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 16:30:47.473238 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 16:30:47.479849 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 16:30:47.483113 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 16:30:47.486460 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 16:30:47.492969 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5563 16:30:47.496145 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 16:30:47.499363 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 16:30:47.506128 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 16:30:47.509822 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 16:30:47.512886 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 16:30:47.519408 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 16:30:47.522813 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 16:30:47.525824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 16:30:47.532807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 16:30:47.535928 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 16:30:47.539138 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 16:30:47.545582 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 16:30:47.549353 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 16:30:47.552487 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 16:30:47.559088 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5578 16:30:47.562380 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5579 16:30:47.565645 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 16:30:47.568932 Total UI for P1: 0, mck2ui 16
5581 16:30:47.571973 best dqsien dly found for B0: ( 1, 2, 28)
5582 16:30:47.575815 Total UI for P1: 0, mck2ui 16
5583 16:30:47.578951 best dqsien dly found for B1: ( 1, 2, 26)
5584 16:30:47.582277 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5585 16:30:47.585563 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5586 16:30:47.585647
5587 16:30:47.592023 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5588 16:30:47.595322 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5589 16:30:47.598417 [Gating] SW calibration Done
5590 16:30:47.598528 ==
5591 16:30:47.601761 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 16:30:47.605601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 16:30:47.605687 ==
5594 16:30:47.605759 RX Vref Scan: 0
5595 16:30:47.605822
5596 16:30:47.608688 RX Vref 0 -> 0, step: 1
5597 16:30:47.608774
5598 16:30:47.612200 RX Delay -80 -> 252, step: 8
5599 16:30:47.615433 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5600 16:30:47.618651 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5601 16:30:47.625345 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5602 16:30:47.628245 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5603 16:30:47.631852 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5604 16:30:47.634874 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5605 16:30:47.638160 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5606 16:30:47.641655 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5607 16:30:47.647955 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5608 16:30:47.651703 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5609 16:30:47.654764 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5610 16:30:47.658242 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5611 16:30:47.661582 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5612 16:30:47.664845 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5613 16:30:47.671387 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5614 16:30:47.674093 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5615 16:30:47.674239 ==
5616 16:30:47.677810 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 16:30:47.681096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 16:30:47.681185 ==
5619 16:30:47.684395 DQS Delay:
5620 16:30:47.684478 DQS0 = 0, DQS1 = 0
5621 16:30:47.684543 DQM Delay:
5622 16:30:47.687610 DQM0 = 99, DQM1 = 95
5623 16:30:47.687719 DQ Delay:
5624 16:30:47.690892 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5625 16:30:47.694233 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5626 16:30:47.697641 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5627 16:30:47.700837 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5628 16:30:47.700967
5629 16:30:47.704132
5630 16:30:47.704245 ==
5631 16:30:47.707311 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 16:30:47.710748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 16:30:47.710869 ==
5634 16:30:47.710965
5635 16:30:47.711055
5636 16:30:47.713836 TX Vref Scan disable
5637 16:30:47.713920 == TX Byte 0 ==
5638 16:30:47.720446 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5639 16:30:47.723474 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5640 16:30:47.723594 == TX Byte 1 ==
5641 16:30:47.730637 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5642 16:30:47.733835 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5643 16:30:47.733967 ==
5644 16:30:47.737004 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 16:30:47.740227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 16:30:47.740350 ==
5647 16:30:47.740418
5648 16:30:47.740483
5649 16:30:47.743555 TX Vref Scan disable
5650 16:30:47.747129 == TX Byte 0 ==
5651 16:30:47.750709 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5652 16:30:47.753736 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5653 16:30:47.757186 == TX Byte 1 ==
5654 16:30:47.759838 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5655 16:30:47.763526 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5656 16:30:47.766681
5657 16:30:47.766763 [DATLAT]
5658 16:30:47.766829 Freq=933, CH1 RK0
5659 16:30:47.766889
5660 16:30:47.769870 DATLAT Default: 0xd
5661 16:30:47.769953 0, 0xFFFF, sum = 0
5662 16:30:47.773105 1, 0xFFFF, sum = 0
5663 16:30:47.773191 2, 0xFFFF, sum = 0
5664 16:30:47.776587 3, 0xFFFF, sum = 0
5665 16:30:47.779668 4, 0xFFFF, sum = 0
5666 16:30:47.779761 5, 0xFFFF, sum = 0
5667 16:30:47.782766 6, 0xFFFF, sum = 0
5668 16:30:47.782852 7, 0xFFFF, sum = 0
5669 16:30:47.785939 8, 0xFFFF, sum = 0
5670 16:30:47.786023 9, 0xFFFF, sum = 0
5671 16:30:47.789230 10, 0x0, sum = 1
5672 16:30:47.789325 11, 0x0, sum = 2
5673 16:30:47.793168 12, 0x0, sum = 3
5674 16:30:47.793252 13, 0x0, sum = 4
5675 16:30:47.793329 best_step = 11
5676 16:30:47.796289
5677 16:30:47.796372 ==
5678 16:30:47.799536 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 16:30:47.802684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 16:30:47.802769 ==
5681 16:30:47.802836 RX Vref Scan: 1
5682 16:30:47.802898
5683 16:30:47.805891 RX Vref 0 -> 0, step: 1
5684 16:30:47.805989
5685 16:30:47.809087 RX Delay -53 -> 252, step: 4
5686 16:30:47.809202
5687 16:30:47.812454 Set Vref, RX VrefLevel [Byte0]: 51
5688 16:30:47.815687 [Byte1]: 50
5689 16:30:47.815774
5690 16:30:47.819394 Final RX Vref Byte 0 = 51 to rank0
5691 16:30:47.822449 Final RX Vref Byte 1 = 50 to rank0
5692 16:30:47.825581 Final RX Vref Byte 0 = 51 to rank1
5693 16:30:47.829138 Final RX Vref Byte 1 = 50 to rank1==
5694 16:30:47.832105 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 16:30:47.838958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 16:30:47.839132 ==
5697 16:30:47.839253 DQS Delay:
5698 16:30:47.842355 DQS0 = 0, DQS1 = 0
5699 16:30:47.842476 DQM Delay:
5700 16:30:47.842579 DQM0 = 99, DQM1 = 94
5701 16:30:47.845510 DQ Delay:
5702 16:30:47.848769 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5703 16:30:47.851927 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5704 16:30:47.855216 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5705 16:30:47.858473 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5706 16:30:47.858580
5707 16:30:47.858672
5708 16:30:47.865438 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
5709 16:30:47.868754 CH1 RK0: MR19=505, MR18=D1D
5710 16:30:47.875397 CH1_RK0: MR19=0x505, MR18=0xD1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5711 16:30:47.875524
5712 16:30:47.878193 ----->DramcWriteLeveling(PI) begin...
5713 16:30:47.878291 ==
5714 16:30:47.881709 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 16:30:47.884910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 16:30:47.885007 ==
5717 16:30:47.888147 Write leveling (Byte 0): 27 => 27
5718 16:30:47.891845 Write leveling (Byte 1): 28 => 28
5719 16:30:47.895154 DramcWriteLeveling(PI) end<-----
5720 16:30:47.895273
5721 16:30:47.895367 ==
5722 16:30:47.898089 Dram Type= 6, Freq= 0, CH_1, rank 1
5723 16:30:47.905023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 16:30:47.905195 ==
5725 16:30:47.905310 [Gating] SW mode calibration
5726 16:30:47.914711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5727 16:30:47.918056 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5728 16:30:47.921237 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5729 16:30:47.927894 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 16:30:47.931043 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 16:30:47.934812 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 16:30:47.940881 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 16:30:47.944568 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5734 16:30:47.951130 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5735 16:30:47.953780 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5736 16:30:47.957094 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5737 16:30:47.963698 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 16:30:47.967017 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 16:30:47.970285 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 16:30:47.976872 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 16:30:47.980647 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 16:30:47.983868 0 15 24 | B1->B0 | 2929 3535 | 1 0 | (0 0) (0 0)
5743 16:30:47.990042 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5744 16:30:47.993928 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5745 16:30:47.996622 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 16:30:48.003620 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 16:30:48.006677 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 16:30:48.010273 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 16:30:48.016577 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 16:30:48.019929 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 16:30:48.023190 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5752 16:30:48.029724 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 16:30:48.032946 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 16:30:48.036316 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 16:30:48.042604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 16:30:48.046208 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 16:30:48.049131 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 16:30:48.055845 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 16:30:48.059221 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 16:30:48.062439 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 16:30:48.069151 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 16:30:48.072449 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 16:30:48.075847 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 16:30:48.082239 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 16:30:48.085425 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 16:30:48.088722 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5767 16:30:48.095863 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 16:30:48.095975 Total UI for P1: 0, mck2ui 16
5769 16:30:48.102324 best dqsien dly found for B0: ( 1, 2, 24)
5770 16:30:48.102446 Total UI for P1: 0, mck2ui 16
5771 16:30:48.108660 best dqsien dly found for B1: ( 1, 2, 24)
5772 16:30:48.112132 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5773 16:30:48.115583 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5774 16:30:48.115706
5775 16:30:48.118653 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5776 16:30:48.121663 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5777 16:30:48.125203 [Gating] SW calibration Done
5778 16:30:48.125369 ==
5779 16:30:48.128266 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 16:30:48.131774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 16:30:48.131939 ==
5782 16:30:48.134988 RX Vref Scan: 0
5783 16:30:48.135095
5784 16:30:48.135187 RX Vref 0 -> 0, step: 1
5785 16:30:48.135281
5786 16:30:48.138366 RX Delay -80 -> 252, step: 8
5787 16:30:48.144760 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5788 16:30:48.148030 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5789 16:30:48.151697 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5790 16:30:48.154817 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5791 16:30:48.157778 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5792 16:30:48.161193 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5793 16:30:48.168207 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5794 16:30:48.171628 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5795 16:30:48.174572 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5796 16:30:48.177926 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5797 16:30:48.181099 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5798 16:30:48.184235 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5799 16:30:48.190795 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5800 16:30:48.194193 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5801 16:30:48.197230 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5802 16:30:48.200338 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5803 16:30:48.200437 ==
5804 16:30:48.203825 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 16:30:48.210490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 16:30:48.210607 ==
5807 16:30:48.210703 DQS Delay:
5808 16:30:48.213723 DQS0 = 0, DQS1 = 0
5809 16:30:48.213825 DQM Delay:
5810 16:30:48.213921 DQM0 = 97, DQM1 = 94
5811 16:30:48.217272 DQ Delay:
5812 16:30:48.220292 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5813 16:30:48.223452 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5814 16:30:48.226727 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5815 16:30:48.230353 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5816 16:30:48.230463
5817 16:30:48.230576
5818 16:30:48.230673 ==
5819 16:30:48.233706 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 16:30:48.236892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 16:30:48.236998 ==
5822 16:30:48.237096
5823 16:30:48.237194
5824 16:30:48.239986 TX Vref Scan disable
5825 16:30:48.243525 == TX Byte 0 ==
5826 16:30:48.246405 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5827 16:30:48.249704 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5828 16:30:48.253022 == TX Byte 1 ==
5829 16:30:48.256361 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5830 16:30:48.259602 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5831 16:30:48.259711 ==
5832 16:30:48.263428 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 16:30:48.269604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 16:30:48.269713 ==
5835 16:30:48.269812
5836 16:30:48.269908
5837 16:30:48.270000 TX Vref Scan disable
5838 16:30:48.273540 == TX Byte 0 ==
5839 16:30:48.276831 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5840 16:30:48.283865 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5841 16:30:48.283987 == TX Byte 1 ==
5842 16:30:48.287039 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5843 16:30:48.293547 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5844 16:30:48.293654
5845 16:30:48.293752 [DATLAT]
5846 16:30:48.293842 Freq=933, CH1 RK1
5847 16:30:48.293939
5848 16:30:48.296853 DATLAT Default: 0xb
5849 16:30:48.300004 0, 0xFFFF, sum = 0
5850 16:30:48.300105 1, 0xFFFF, sum = 0
5851 16:30:48.303175 2, 0xFFFF, sum = 0
5852 16:30:48.303277 3, 0xFFFF, sum = 0
5853 16:30:48.306437 4, 0xFFFF, sum = 0
5854 16:30:48.306524 5, 0xFFFF, sum = 0
5855 16:30:48.309678 6, 0xFFFF, sum = 0
5856 16:30:48.309755 7, 0xFFFF, sum = 0
5857 16:30:48.312972 8, 0xFFFF, sum = 0
5858 16:30:48.313050 9, 0xFFFF, sum = 0
5859 16:30:48.316174 10, 0x0, sum = 1
5860 16:30:48.316278 11, 0x0, sum = 2
5861 16:30:48.320115 12, 0x0, sum = 3
5862 16:30:48.320220 13, 0x0, sum = 4
5863 16:30:48.323215 best_step = 11
5864 16:30:48.323314
5865 16:30:48.323413 ==
5866 16:30:48.326107 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 16:30:48.329870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 16:30:48.329949 ==
5869 16:30:48.330013 RX Vref Scan: 0
5870 16:30:48.332823
5871 16:30:48.332925 RX Vref 0 -> 0, step: 1
5872 16:30:48.333019
5873 16:30:48.336025 RX Delay -53 -> 252, step: 4
5874 16:30:48.343288 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5875 16:30:48.345963 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5876 16:30:48.349297 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5877 16:30:48.352859 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5878 16:30:48.356315 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5879 16:30:48.359244 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5880 16:30:48.366363 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5881 16:30:48.369632 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5882 16:30:48.372926 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5883 16:30:48.375991 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5884 16:30:48.379266 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5885 16:30:48.385575 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5886 16:30:48.389084 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5887 16:30:48.392453 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5888 16:30:48.395438 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5889 16:30:48.399213 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5890 16:30:48.402507 ==
5891 16:30:48.405593 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 16:30:48.408887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 16:30:48.409008 ==
5894 16:30:48.409117 DQS Delay:
5895 16:30:48.412238 DQS0 = 0, DQS1 = 0
5896 16:30:48.412330 DQM Delay:
5897 16:30:48.415451 DQM0 = 96, DQM1 = 92
5898 16:30:48.415565 DQ Delay:
5899 16:30:48.418651 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5900 16:30:48.422030 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5901 16:30:48.425282 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5902 16:30:48.428527 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5903 16:30:48.428607
5904 16:30:48.428672
5905 16:30:48.438536 [DQSOSCAuto] RK1, (LSB)MR18= 0xf26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5906 16:30:48.438646 CH1 RK1: MR19=505, MR18=F26
5907 16:30:48.445155 CH1_RK1: MR19=0x505, MR18=0xF26, DQSOSC=409, MR23=63, INC=64, DEC=43
5908 16:30:48.448356 [RxdqsGatingPostProcess] freq 933
5909 16:30:48.455092 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5910 16:30:48.458344 best DQS0 dly(2T, 0.5T) = (0, 10)
5911 16:30:48.461585 best DQS1 dly(2T, 0.5T) = (0, 10)
5912 16:30:48.464710 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5913 16:30:48.468202 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5914 16:30:48.471140 best DQS0 dly(2T, 0.5T) = (0, 10)
5915 16:30:48.471240 best DQS1 dly(2T, 0.5T) = (0, 10)
5916 16:30:48.474491 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5917 16:30:48.479898 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5918 16:30:48.481014 Pre-setting of DQS Precalculation
5919 16:30:48.487537 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5920 16:30:48.494414 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5921 16:30:48.500866 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5922 16:30:48.500948
5923 16:30:48.501014
5924 16:30:48.504630 [Calibration Summary] 1866 Mbps
5925 16:30:48.507224 CH 0, Rank 0
5926 16:30:48.507327 SW Impedance : PASS
5927 16:30:48.510584 DUTY Scan : NO K
5928 16:30:48.513990 ZQ Calibration : PASS
5929 16:30:48.514086 Jitter Meter : NO K
5930 16:30:48.517765 CBT Training : PASS
5931 16:30:48.517859 Write leveling : PASS
5932 16:30:48.520997 RX DQS gating : PASS
5933 16:30:48.524235 RX DQ/DQS(RDDQC) : PASS
5934 16:30:48.524340 TX DQ/DQS : PASS
5935 16:30:48.527579 RX DATLAT : PASS
5936 16:30:48.530873 RX DQ/DQS(Engine): PASS
5937 16:30:48.530980 TX OE : NO K
5938 16:30:48.534107 All Pass.
5939 16:30:48.534207
5940 16:30:48.534299 CH 0, Rank 1
5941 16:30:48.537345 SW Impedance : PASS
5942 16:30:48.537415 DUTY Scan : NO K
5943 16:30:48.540641 ZQ Calibration : PASS
5944 16:30:48.543747 Jitter Meter : NO K
5945 16:30:48.543847 CBT Training : PASS
5946 16:30:48.546871 Write leveling : PASS
5947 16:30:48.550349 RX DQS gating : PASS
5948 16:30:48.550451 RX DQ/DQS(RDDQC) : PASS
5949 16:30:48.553785 TX DQ/DQS : PASS
5950 16:30:48.556964 RX DATLAT : PASS
5951 16:30:48.557067 RX DQ/DQS(Engine): PASS
5952 16:30:48.563981 TX OE : NO K
5953 16:30:48.564079 All Pass.
5954 16:30:48.564154
5955 16:30:48.564217 CH 1, Rank 0
5956 16:30:48.564280 SW Impedance : PASS
5957 16:30:48.566644 DUTY Scan : NO K
5958 16:30:48.569874 ZQ Calibration : PASS
5959 16:30:48.569958 Jitter Meter : NO K
5960 16:30:48.573724 CBT Training : PASS
5961 16:30:48.576962 Write leveling : PASS
5962 16:30:48.577068 RX DQS gating : PASS
5963 16:30:48.580030 RX DQ/DQS(RDDQC) : PASS
5964 16:30:48.583482 TX DQ/DQS : PASS
5965 16:30:48.583582 RX DATLAT : PASS
5966 16:30:48.586326 RX DQ/DQS(Engine): PASS
5967 16:30:48.590266 TX OE : NO K
5968 16:30:48.590369 All Pass.
5969 16:30:48.590460
5970 16:30:48.590548 CH 1, Rank 1
5971 16:30:48.593447 SW Impedance : PASS
5972 16:30:48.596675 DUTY Scan : NO K
5973 16:30:48.596748 ZQ Calibration : PASS
5974 16:30:48.599861 Jitter Meter : NO K
5975 16:30:48.603246 CBT Training : PASS
5976 16:30:48.603353 Write leveling : PASS
5977 16:30:48.606529 RX DQS gating : PASS
5978 16:30:48.606632 RX DQ/DQS(RDDQC) : PASS
5979 16:30:48.609758 TX DQ/DQS : PASS
5980 16:30:48.612769 RX DATLAT : PASS
5981 16:30:48.612881 RX DQ/DQS(Engine): PASS
5982 16:30:48.616343 TX OE : NO K
5983 16:30:48.616451 All Pass.
5984 16:30:48.616544
5985 16:30:48.619400 DramC Write-DBI off
5986 16:30:48.622787 PER_BANK_REFRESH: Hybrid Mode
5987 16:30:48.622875 TX_TRACKING: ON
5988 16:30:48.632200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5989 16:30:48.635482 [FAST_K] Save calibration result to emmc
5990 16:30:48.639513 dramc_set_vcore_voltage set vcore to 650000
5991 16:30:48.642737 Read voltage for 400, 6
5992 16:30:48.642849 Vio18 = 0
5993 16:30:48.646127 Vcore = 650000
5994 16:30:48.646228 Vdram = 0
5995 16:30:48.646328 Vddq = 0
5996 16:30:48.646425 Vmddr = 0
5997 16:30:48.652525 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5998 16:30:48.658694 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5999 16:30:48.658806 MEM_TYPE=3, freq_sel=20
6000 16:30:48.662387 sv_algorithm_assistance_LP4_800
6001 16:30:48.665187 ============ PULL DRAM RESETB DOWN ============
6002 16:30:48.672014 ========== PULL DRAM RESETB DOWN end =========
6003 16:30:48.675263 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6004 16:30:48.678416 ===================================
6005 16:30:48.681860 LPDDR4 DRAM CONFIGURATION
6006 16:30:48.685117 ===================================
6007 16:30:48.685202 EX_ROW_EN[0] = 0x0
6008 16:30:48.688339 EX_ROW_EN[1] = 0x0
6009 16:30:48.692074 LP4Y_EN = 0x0
6010 16:30:48.692183 WORK_FSP = 0x0
6011 16:30:48.695010 WL = 0x2
6012 16:30:48.695088 RL = 0x2
6013 16:30:48.698420 BL = 0x2
6014 16:30:48.698511 RPST = 0x0
6015 16:30:48.701982 RD_PRE = 0x0
6016 16:30:48.702067 WR_PRE = 0x1
6017 16:30:48.705279 WR_PST = 0x0
6018 16:30:48.705381 DBI_WR = 0x0
6019 16:30:48.708566 DBI_RD = 0x0
6020 16:30:48.708650 OTF = 0x1
6021 16:30:48.711358 ===================================
6022 16:30:48.714570 ===================================
6023 16:30:48.718413 ANA top config
6024 16:30:48.721045 ===================================
6025 16:30:48.721131 DLL_ASYNC_EN = 0
6026 16:30:48.724850 ALL_SLAVE_EN = 1
6027 16:30:48.727977 NEW_RANK_MODE = 1
6028 16:30:48.731040 DLL_IDLE_MODE = 1
6029 16:30:48.734323 LP45_APHY_COMB_EN = 1
6030 16:30:48.734410 TX_ODT_DIS = 1
6031 16:30:48.737616 NEW_8X_MODE = 1
6032 16:30:48.741232 ===================================
6033 16:30:48.744647 ===================================
6034 16:30:48.747608 data_rate = 800
6035 16:30:48.751023 CKR = 1
6036 16:30:48.754372 DQ_P2S_RATIO = 4
6037 16:30:48.757689 ===================================
6038 16:30:48.760925 CA_P2S_RATIO = 4
6039 16:30:48.761004 DQ_CA_OPEN = 0
6040 16:30:48.764171 DQ_SEMI_OPEN = 1
6041 16:30:48.767489 CA_SEMI_OPEN = 1
6042 16:30:48.770700 CA_FULL_RATE = 0
6043 16:30:48.773769 DQ_CKDIV4_EN = 0
6044 16:30:48.777112 CA_CKDIV4_EN = 1
6045 16:30:48.777215 CA_PREDIV_EN = 0
6046 16:30:48.780345 PH8_DLY = 0
6047 16:30:48.784034 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6048 16:30:48.787332 DQ_AAMCK_DIV = 0
6049 16:30:48.790555 CA_AAMCK_DIV = 0
6050 16:30:48.793898 CA_ADMCK_DIV = 4
6051 16:30:48.793981 DQ_TRACK_CA_EN = 0
6052 16:30:48.797154 CA_PICK = 800
6053 16:30:48.800338 CA_MCKIO = 400
6054 16:30:48.803535 MCKIO_SEMI = 400
6055 16:30:48.807094 PLL_FREQ = 3016
6056 16:30:48.810527 DQ_UI_PI_RATIO = 32
6057 16:30:48.813245 CA_UI_PI_RATIO = 32
6058 16:30:48.816537 ===================================
6059 16:30:48.820330 ===================================
6060 16:30:48.823478 memory_type:LPDDR4
6061 16:30:48.823584 GP_NUM : 10
6062 16:30:48.826741 SRAM_EN : 1
6063 16:30:48.826846 MD32_EN : 0
6064 16:30:48.829928 ===================================
6065 16:30:48.833206 [ANA_INIT] >>>>>>>>>>>>>>
6066 16:30:48.836263 <<<<<< [CONFIGURE PHASE]: ANA_TX
6067 16:30:48.839570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6068 16:30:48.842916 ===================================
6069 16:30:48.846661 data_rate = 800,PCW = 0X7400
6070 16:30:48.849628 ===================================
6071 16:30:48.853236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6072 16:30:48.859749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6073 16:30:48.869453 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6074 16:30:48.872878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6075 16:30:48.875974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6076 16:30:48.879933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6077 16:30:48.882730 [ANA_INIT] flow start
6078 16:30:48.886302 [ANA_INIT] PLL >>>>>>>>
6079 16:30:48.886410 [ANA_INIT] PLL <<<<<<<<
6080 16:30:48.889653 [ANA_INIT] MIDPI >>>>>>>>
6081 16:30:48.893050 [ANA_INIT] MIDPI <<<<<<<<
6082 16:30:48.896396 [ANA_INIT] DLL >>>>>>>>
6083 16:30:48.896477 [ANA_INIT] flow end
6084 16:30:48.899528 ============ LP4 DIFF to SE enter ============
6085 16:30:48.906082 ============ LP4 DIFF to SE exit ============
6086 16:30:48.906164 [ANA_INIT] <<<<<<<<<<<<<
6087 16:30:48.909425 [Flow] Enable top DCM control >>>>>
6088 16:30:48.912628 [Flow] Enable top DCM control <<<<<
6089 16:30:48.915726 Enable DLL master slave shuffle
6090 16:30:48.922419 ==============================================================
6091 16:30:48.922500 Gating Mode config
6092 16:30:48.929207 ==============================================================
6093 16:30:48.932400 Config description:
6094 16:30:48.941917 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6095 16:30:48.948483 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6096 16:30:48.951791 SELPH_MODE 0: By rank 1: By Phase
6097 16:30:48.958231 ==============================================================
6098 16:30:48.962019 GAT_TRACK_EN = 0
6099 16:30:48.964815 RX_GATING_MODE = 2
6100 16:30:48.968132 RX_GATING_TRACK_MODE = 2
6101 16:30:48.971840 SELPH_MODE = 1
6102 16:30:48.971943 PICG_EARLY_EN = 1
6103 16:30:48.975100 VALID_LAT_VALUE = 1
6104 16:30:48.981613 ==============================================================
6105 16:30:48.984916 Enter into Gating configuration >>>>
6106 16:30:48.988161 Exit from Gating configuration <<<<
6107 16:30:48.991338 Enter into DVFS_PRE_config >>>>>
6108 16:30:49.001268 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6109 16:30:49.004547 Exit from DVFS_PRE_config <<<<<
6110 16:30:49.008238 Enter into PICG configuration >>>>
6111 16:30:49.011486 Exit from PICG configuration <<<<
6112 16:30:49.014862 [RX_INPUT] configuration >>>>>
6113 16:30:49.018103 [RX_INPUT] configuration <<<<<
6114 16:30:49.021454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6115 16:30:49.027905 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6116 16:30:49.034324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6117 16:30:49.040415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6118 16:30:49.047058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6119 16:30:49.053732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6120 16:30:49.056795 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6121 16:30:49.060143 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6122 16:30:49.063809 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6123 16:30:49.070268 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6124 16:30:49.073502 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6125 16:30:49.077063 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6126 16:30:49.079991 ===================================
6127 16:30:49.083165 LPDDR4 DRAM CONFIGURATION
6128 16:30:49.086534 ===================================
6129 16:30:49.089781 EX_ROW_EN[0] = 0x0
6130 16:30:49.089862 EX_ROW_EN[1] = 0x0
6131 16:30:49.093103 LP4Y_EN = 0x0
6132 16:30:49.093207 WORK_FSP = 0x0
6133 16:30:49.096994 WL = 0x2
6134 16:30:49.097100 RL = 0x2
6135 16:30:49.100370 BL = 0x2
6136 16:30:49.100467 RPST = 0x0
6137 16:30:49.103541 RD_PRE = 0x0
6138 16:30:49.103645 WR_PRE = 0x1
6139 16:30:49.106565 WR_PST = 0x0
6140 16:30:49.106640 DBI_WR = 0x0
6141 16:30:49.109754 DBI_RD = 0x0
6142 16:30:49.109825 OTF = 0x1
6143 16:30:49.113560 ===================================
6144 16:30:49.119903 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6145 16:30:49.123034 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6146 16:30:49.126302 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 16:30:49.129598 ===================================
6148 16:30:49.132779 LPDDR4 DRAM CONFIGURATION
6149 16:30:49.135991 ===================================
6150 16:30:49.139267 EX_ROW_EN[0] = 0x10
6151 16:30:49.139367 EX_ROW_EN[1] = 0x0
6152 16:30:49.142603 LP4Y_EN = 0x0
6153 16:30:49.142673 WORK_FSP = 0x0
6154 16:30:49.145919 WL = 0x2
6155 16:30:49.145992 RL = 0x2
6156 16:30:49.149605 BL = 0x2
6157 16:30:49.149674 RPST = 0x0
6158 16:30:49.152876 RD_PRE = 0x0
6159 16:30:49.152953 WR_PRE = 0x1
6160 16:30:49.156007 WR_PST = 0x0
6161 16:30:49.156076 DBI_WR = 0x0
6162 16:30:49.158982 DBI_RD = 0x0
6163 16:30:49.159094 OTF = 0x1
6164 16:30:49.162296 ===================================
6165 16:30:49.169172 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6166 16:30:49.173786 nWR fixed to 30
6167 16:30:49.177137 [ModeRegInit_LP4] CH0 RK0
6168 16:30:49.177220 [ModeRegInit_LP4] CH0 RK1
6169 16:30:49.180334 [ModeRegInit_LP4] CH1 RK0
6170 16:30:49.183831 [ModeRegInit_LP4] CH1 RK1
6171 16:30:49.183916 match AC timing 19
6172 16:30:49.190232 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6173 16:30:49.193596 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6174 16:30:49.197370 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6175 16:30:49.203415 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6176 16:30:49.207385 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6177 16:30:49.207468 ==
6178 16:30:49.209873 Dram Type= 6, Freq= 0, CH_0, rank 0
6179 16:30:49.213845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6180 16:30:49.213928 ==
6181 16:30:49.219978 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6182 16:30:49.226589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6183 16:30:49.229561 [CA 0] Center 36 (8~64) winsize 57
6184 16:30:49.233442 [CA 1] Center 36 (8~64) winsize 57
6185 16:30:49.236677 [CA 2] Center 36 (8~64) winsize 57
6186 16:30:49.239967 [CA 3] Center 36 (8~64) winsize 57
6187 16:30:49.243193 [CA 4] Center 36 (8~64) winsize 57
6188 16:30:49.246486 [CA 5] Center 36 (8~64) winsize 57
6189 16:30:49.246567
6190 16:30:49.249769 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6191 16:30:49.249851
6192 16:30:49.253074 [CATrainingPosCal] consider 1 rank data
6193 16:30:49.256523 u2DelayCellTimex100 = 270/100 ps
6194 16:30:49.259588 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6195 16:30:49.262889 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 16:30:49.266016 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 16:30:49.269293 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 16:30:49.272458 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 16:30:49.275708 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 16:30:49.275790
6201 16:30:49.282795 CA PerBit enable=1, Macro0, CA PI delay=36
6202 16:30:49.282891
6203 16:30:49.285776 [CBTSetCACLKResult] CA Dly = 36
6204 16:30:49.285920 CS Dly: 1 (0~32)
6205 16:30:49.286016 ==
6206 16:30:49.288778 Dram Type= 6, Freq= 0, CH_0, rank 1
6207 16:30:49.292169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 16:30:49.292337 ==
6209 16:30:49.298792 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 16:30:49.305661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6211 16:30:49.308811 [CA 0] Center 36 (8~64) winsize 57
6212 16:30:49.311936 [CA 1] Center 36 (8~64) winsize 57
6213 16:30:49.315778 [CA 2] Center 36 (8~64) winsize 57
6214 16:30:49.318984 [CA 3] Center 36 (8~64) winsize 57
6215 16:30:49.319076 [CA 4] Center 36 (8~64) winsize 57
6216 16:30:49.322218 [CA 5] Center 36 (8~64) winsize 57
6217 16:30:49.322312
6218 16:30:49.328585 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6219 16:30:49.328664
6220 16:30:49.331922 [CATrainingPosCal] consider 2 rank data
6221 16:30:49.335412 u2DelayCellTimex100 = 270/100 ps
6222 16:30:49.338432 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 16:30:49.342073 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 16:30:49.345244 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 16:30:49.348701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 16:30:49.351777 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 16:30:49.354994 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 16:30:49.355069
6229 16:30:49.358342 CA PerBit enable=1, Macro0, CA PI delay=36
6230 16:30:49.358416
6231 16:30:49.361673 [CBTSetCACLKResult] CA Dly = 36
6232 16:30:49.364948 CS Dly: 1 (0~32)
6233 16:30:49.365030
6234 16:30:49.368086 ----->DramcWriteLeveling(PI) begin...
6235 16:30:49.368173 ==
6236 16:30:49.371369 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 16:30:49.375133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 16:30:49.375228 ==
6239 16:30:49.378378 Write leveling (Byte 0): 40 => 8
6240 16:30:49.381675 Write leveling (Byte 1): 40 => 8
6241 16:30:49.384926 DramcWriteLeveling(PI) end<-----
6242 16:30:49.385039
6243 16:30:49.385135 ==
6244 16:30:49.388164 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 16:30:49.391441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 16:30:49.391548 ==
6247 16:30:49.394780 [Gating] SW mode calibration
6248 16:30:49.401634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6249 16:30:49.407661 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6250 16:30:49.411378 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6251 16:30:49.417852 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6252 16:30:49.420942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6253 16:30:49.424751 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6254 16:30:49.430747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6255 16:30:49.434570 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 16:30:49.437305 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 16:30:49.444118 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 16:30:49.447547 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6259 16:30:49.450639 Total UI for P1: 0, mck2ui 16
6260 16:30:49.453977 best dqsien dly found for B0: ( 0, 14, 24)
6261 16:30:49.457190 Total UI for P1: 0, mck2ui 16
6262 16:30:49.460419 best dqsien dly found for B1: ( 0, 14, 24)
6263 16:30:49.463697 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6264 16:30:49.467414 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6265 16:30:49.467486
6266 16:30:49.470746 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6267 16:30:49.473492 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6268 16:30:49.476696 [Gating] SW calibration Done
6269 16:30:49.476778 ==
6270 16:30:49.480539 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 16:30:49.487037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 16:30:49.487122 ==
6273 16:30:49.487188 RX Vref Scan: 0
6274 16:30:49.487248
6275 16:30:49.490173 RX Vref 0 -> 0, step: 1
6276 16:30:49.490256
6277 16:30:49.493550 RX Delay -410 -> 252, step: 16
6278 16:30:49.496984 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6279 16:30:49.500297 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6280 16:30:49.506745 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6281 16:30:49.509795 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6282 16:30:49.513486 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6283 16:30:49.516544 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6284 16:30:49.523401 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6285 16:30:49.526615 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6286 16:30:49.529831 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6287 16:30:49.533031 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6288 16:30:49.539747 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6289 16:30:49.542790 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6290 16:30:49.546341 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6291 16:30:49.552785 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6292 16:30:49.555699 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6293 16:30:49.559097 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6294 16:30:49.559170 ==
6295 16:30:49.562513 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 16:30:49.565524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 16:30:49.569303 ==
6298 16:30:49.569380 DQS Delay:
6299 16:30:49.569443 DQS0 = 35, DQS1 = 51
6300 16:30:49.572477 DQM Delay:
6301 16:30:49.572558 DQM0 = 4, DQM1 = 11
6302 16:30:49.575756 DQ Delay:
6303 16:30:49.575838 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6304 16:30:49.579014 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6305 16:30:49.582298 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6306 16:30:49.585373 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6307 16:30:49.585508
6308 16:30:49.585574
6309 16:30:49.585697 ==
6310 16:30:49.588506 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 16:30:49.595687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 16:30:49.595800 ==
6313 16:30:49.595898
6314 16:30:49.595984
6315 16:30:49.598935 TX Vref Scan disable
6316 16:30:49.599016 == TX Byte 0 ==
6317 16:30:49.602156 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6318 16:30:49.608829 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6319 16:30:49.608918 == TX Byte 1 ==
6320 16:30:49.612015 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6321 16:30:49.618195 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6322 16:30:49.618271 ==
6323 16:30:49.621785 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 16:30:49.624857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 16:30:49.624937 ==
6326 16:30:49.624998
6327 16:30:49.625054
6328 16:30:49.628548 TX Vref Scan disable
6329 16:30:49.628621 == TX Byte 0 ==
6330 16:30:49.631761 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 16:30:49.638452 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 16:30:49.638535 == TX Byte 1 ==
6333 16:30:49.641593 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 16:30:49.647794 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 16:30:49.647897
6336 16:30:49.647999 [DATLAT]
6337 16:30:49.648088 Freq=400, CH0 RK0
6338 16:30:49.651586
6339 16:30:49.651688 DATLAT Default: 0xf
6340 16:30:49.654590 0, 0xFFFF, sum = 0
6341 16:30:49.654673 1, 0xFFFF, sum = 0
6342 16:30:49.657773 2, 0xFFFF, sum = 0
6343 16:30:49.657849 3, 0xFFFF, sum = 0
6344 16:30:49.661486 4, 0xFFFF, sum = 0
6345 16:30:49.661600 5, 0xFFFF, sum = 0
6346 16:30:49.664559 6, 0xFFFF, sum = 0
6347 16:30:49.664671 7, 0xFFFF, sum = 0
6348 16:30:49.667737 8, 0xFFFF, sum = 0
6349 16:30:49.667808 9, 0xFFFF, sum = 0
6350 16:30:49.671351 10, 0xFFFF, sum = 0
6351 16:30:49.671428 11, 0xFFFF, sum = 0
6352 16:30:49.674211 12, 0xFFFF, sum = 0
6353 16:30:49.674294 13, 0x0, sum = 1
6354 16:30:49.677649 14, 0x0, sum = 2
6355 16:30:49.677732 15, 0x0, sum = 3
6356 16:30:49.680676 16, 0x0, sum = 4
6357 16:30:49.680750 best_step = 14
6358 16:30:49.680818
6359 16:30:49.680875 ==
6360 16:30:49.683877 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 16:30:49.690982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 16:30:49.691084 ==
6363 16:30:49.691183 RX Vref Scan: 1
6364 16:30:49.691269
6365 16:30:49.694418 RX Vref 0 -> 0, step: 1
6366 16:30:49.694515
6367 16:30:49.696996 RX Delay -343 -> 252, step: 8
6368 16:30:49.697076
6369 16:30:49.700870 Set Vref, RX VrefLevel [Byte0]: 55
6370 16:30:49.704080 [Byte1]: 58
6371 16:30:49.707413
6372 16:30:49.707511 Final RX Vref Byte 0 = 55 to rank0
6373 16:30:49.710546 Final RX Vref Byte 1 = 58 to rank0
6374 16:30:49.713933 Final RX Vref Byte 0 = 55 to rank1
6375 16:30:49.717151 Final RX Vref Byte 1 = 58 to rank1==
6376 16:30:49.720353 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 16:30:49.727046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 16:30:49.727129 ==
6379 16:30:49.727193 DQS Delay:
6380 16:30:49.730144 DQS0 = 44, DQS1 = 60
6381 16:30:49.730225 DQM Delay:
6382 16:30:49.733190 DQM0 = 10, DQM1 = 15
6383 16:30:49.733281 DQ Delay:
6384 16:30:49.736949 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6385 16:30:49.740125 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6386 16:30:49.743455 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6387 16:30:49.746518 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6388 16:30:49.746626
6389 16:30:49.746722
6390 16:30:49.753481 [DQSOSCAuto] RK0, (LSB)MR18= 0x998d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6391 16:30:49.756622 CH0 RK0: MR19=C0C, MR18=998D
6392 16:30:49.763364 CH0_RK0: MR19=0xC0C, MR18=0x998D, DQSOSC=390, MR23=63, INC=388, DEC=258
6393 16:30:49.763448 ==
6394 16:30:49.766399 Dram Type= 6, Freq= 0, CH_0, rank 1
6395 16:30:49.769655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 16:30:49.769738 ==
6397 16:30:49.772757 [Gating] SW mode calibration
6398 16:30:49.779311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6399 16:30:49.786101 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6400 16:30:49.789683 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 16:30:49.792794 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 16:30:49.799396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 16:30:49.802711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 16:30:49.805904 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 16:30:49.812590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 16:30:49.815800 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 16:30:49.819053 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 16:30:49.825468 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6409 16:30:49.828642 Total UI for P1: 0, mck2ui 16
6410 16:30:49.832245 best dqsien dly found for B0: ( 0, 14, 24)
6411 16:30:49.835938 Total UI for P1: 0, mck2ui 16
6412 16:30:49.838561 best dqsien dly found for B1: ( 0, 14, 24)
6413 16:30:49.842336 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6414 16:30:49.845491 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6415 16:30:49.845564
6416 16:30:49.848856 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 16:30:49.852043 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 16:30:49.855298 [Gating] SW calibration Done
6419 16:30:49.855396 ==
6420 16:30:49.858450 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 16:30:49.861577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 16:30:49.864868 ==
6423 16:30:49.864939 RX Vref Scan: 0
6424 16:30:49.865001
6425 16:30:49.868552 RX Vref 0 -> 0, step: 1
6426 16:30:49.868621
6427 16:30:49.871457 RX Delay -410 -> 252, step: 16
6428 16:30:49.875345 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6429 16:30:49.878474 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6430 16:30:49.881684 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6431 16:30:49.887761 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6432 16:30:49.891587 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6433 16:30:49.894635 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6434 16:30:49.897653 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6435 16:30:49.904331 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6436 16:30:49.907660 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6437 16:30:49.910912 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6438 16:30:49.917945 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6439 16:30:49.921123 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6440 16:30:49.924382 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6441 16:30:49.927669 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6442 16:30:49.934220 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6443 16:30:49.937326 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6444 16:30:49.937410 ==
6445 16:30:49.940870 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 16:30:49.944452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 16:30:49.944536 ==
6448 16:30:49.947402 DQS Delay:
6449 16:30:49.947484 DQS0 = 35, DQS1 = 59
6450 16:30:49.950604 DQM Delay:
6451 16:30:49.950687 DQM0 = 5, DQM1 = 16
6452 16:30:49.950752 DQ Delay:
6453 16:30:49.953779 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6454 16:30:49.957115 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6455 16:30:49.960477 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6456 16:30:49.963681 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6457 16:30:49.963782
6458 16:30:49.963898
6459 16:30:49.963986 ==
6460 16:30:49.967161 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 16:30:49.973476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 16:30:49.973555 ==
6463 16:30:49.973627
6464 16:30:49.973687
6465 16:30:49.973744 TX Vref Scan disable
6466 16:30:49.976905 == TX Byte 0 ==
6467 16:30:49.980594 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6468 16:30:49.983810 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6469 16:30:49.987036 == TX Byte 1 ==
6470 16:30:49.990249 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6471 16:30:49.993535 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6472 16:30:49.993610 ==
6473 16:30:49.996675 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 16:30:50.003697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 16:30:50.003773 ==
6476 16:30:50.003836
6477 16:30:50.003902
6478 16:30:50.003958 TX Vref Scan disable
6479 16:30:50.006566 == TX Byte 0 ==
6480 16:30:50.010083 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6481 16:30:50.013221 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6482 16:30:50.016633 == TX Byte 1 ==
6483 16:30:50.019876 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6484 16:30:50.023075 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6485 16:30:50.023152
6486 16:30:50.026213 [DATLAT]
6487 16:30:50.026288 Freq=400, CH0 RK1
6488 16:30:50.026359
6489 16:30:50.029473 DATLAT Default: 0xe
6490 16:30:50.029571 0, 0xFFFF, sum = 0
6491 16:30:50.032791 1, 0xFFFF, sum = 0
6492 16:30:50.032904 2, 0xFFFF, sum = 0
6493 16:30:50.036140 3, 0xFFFF, sum = 0
6494 16:30:50.036211 4, 0xFFFF, sum = 0
6495 16:30:50.039343 5, 0xFFFF, sum = 0
6496 16:30:50.039419 6, 0xFFFF, sum = 0
6497 16:30:50.043126 7, 0xFFFF, sum = 0
6498 16:30:50.046260 8, 0xFFFF, sum = 0
6499 16:30:50.046348 9, 0xFFFF, sum = 0
6500 16:30:50.049180 10, 0xFFFF, sum = 0
6501 16:30:50.049315 11, 0xFFFF, sum = 0
6502 16:30:50.052833 12, 0xFFFF, sum = 0
6503 16:30:50.052906 13, 0x0, sum = 1
6504 16:30:50.055843 14, 0x0, sum = 2
6505 16:30:50.055925 15, 0x0, sum = 3
6506 16:30:50.059524 16, 0x0, sum = 4
6507 16:30:50.059600 best_step = 14
6508 16:30:50.059661
6509 16:30:50.059724 ==
6510 16:30:50.062743 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 16:30:50.066013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 16:30:50.069069 ==
6513 16:30:50.069164 RX Vref Scan: 0
6514 16:30:50.069266
6515 16:30:50.072313 RX Vref 0 -> 0, step: 1
6516 16:30:50.072384
6517 16:30:50.075717 RX Delay -359 -> 252, step: 8
6518 16:30:50.079004 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6519 16:30:50.085591 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6520 16:30:50.088716 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6521 16:30:50.092021 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6522 16:30:50.099064 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6523 16:30:50.102316 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6524 16:30:50.105485 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6525 16:30:50.108764 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6526 16:30:50.115118 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6527 16:30:50.118870 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6528 16:30:50.121788 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6529 16:30:50.125041 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6530 16:30:50.132003 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6531 16:30:50.135286 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6532 16:30:50.138539 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6533 16:30:50.145024 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6534 16:30:50.145114 ==
6535 16:30:50.148215 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 16:30:50.151423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 16:30:50.151505 ==
6538 16:30:50.151569 DQS Delay:
6539 16:30:50.154732 DQS0 = 44, DQS1 = 60
6540 16:30:50.154814 DQM Delay:
6541 16:30:50.157888 DQM0 = 9, DQM1 = 16
6542 16:30:50.157969 DQ Delay:
6543 16:30:50.161434 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6544 16:30:50.164411 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6545 16:30:50.167893 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6546 16:30:50.171155 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6547 16:30:50.171234
6548 16:30:50.171312
6549 16:30:50.177510 [DQSOSCAuto] RK1, (LSB)MR18= 0x8d86, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6550 16:30:50.180775 CH0 RK1: MR19=C0C, MR18=8D86
6551 16:30:50.187414 CH0_RK1: MR19=0xC0C, MR18=0x8D86, DQSOSC=392, MR23=63, INC=384, DEC=256
6552 16:30:50.191084 [RxdqsGatingPostProcess] freq 400
6553 16:30:50.197636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6554 16:30:50.200868 best DQS0 dly(2T, 0.5T) = (0, 10)
6555 16:30:50.200979 best DQS1 dly(2T, 0.5T) = (0, 10)
6556 16:30:50.204117 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6557 16:30:50.207386 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6558 16:30:50.210449 best DQS0 dly(2T, 0.5T) = (0, 10)
6559 16:30:50.214439 best DQS1 dly(2T, 0.5T) = (0, 10)
6560 16:30:50.217552 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6561 16:30:50.220725 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6562 16:30:50.223844 Pre-setting of DQS Precalculation
6563 16:30:50.230768 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6564 16:30:50.230852 ==
6565 16:30:50.234026 Dram Type= 6, Freq= 0, CH_1, rank 0
6566 16:30:50.237297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 16:30:50.237395 ==
6568 16:30:50.243820 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6569 16:30:50.247195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6570 16:30:50.250395 [CA 0] Center 36 (8~64) winsize 57
6571 16:30:50.253582 [CA 1] Center 36 (8~64) winsize 57
6572 16:30:50.256860 [CA 2] Center 36 (8~64) winsize 57
6573 16:30:50.260103 [CA 3] Center 36 (8~64) winsize 57
6574 16:30:50.263484 [CA 4] Center 36 (8~64) winsize 57
6575 16:30:50.267092 [CA 5] Center 36 (8~64) winsize 57
6576 16:30:50.267195
6577 16:30:50.270218 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6578 16:30:50.270353
6579 16:30:50.273146 [CATrainingPosCal] consider 1 rank data
6580 16:30:50.276746 u2DelayCellTimex100 = 270/100 ps
6581 16:30:50.279862 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6582 16:30:50.286758 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 16:30:50.289914 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 16:30:50.293052 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 16:30:50.296327 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 16:30:50.299661 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 16:30:50.299743
6588 16:30:50.303455 CA PerBit enable=1, Macro0, CA PI delay=36
6589 16:30:50.303536
6590 16:30:50.306477 [CBTSetCACLKResult] CA Dly = 36
6591 16:30:50.306562 CS Dly: 1 (0~32)
6592 16:30:50.309657 ==
6593 16:30:50.312978 Dram Type= 6, Freq= 0, CH_1, rank 1
6594 16:30:50.316095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 16:30:50.316180 ==
6596 16:30:50.323129 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 16:30:50.326418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6598 16:30:50.329523 [CA 0] Center 36 (8~64) winsize 57
6599 16:30:50.332629 [CA 1] Center 36 (8~64) winsize 57
6600 16:30:50.336296 [CA 2] Center 36 (8~64) winsize 57
6601 16:30:50.339195 [CA 3] Center 36 (8~64) winsize 57
6602 16:30:50.342493 [CA 4] Center 36 (8~64) winsize 57
6603 16:30:50.345808 [CA 5] Center 36 (8~64) winsize 57
6604 16:30:50.345893
6605 16:30:50.349571 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6606 16:30:50.349654
6607 16:30:50.352944 [CATrainingPosCal] consider 2 rank data
6608 16:30:50.356075 u2DelayCellTimex100 = 270/100 ps
6609 16:30:50.359357 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 16:30:50.362540 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 16:30:50.365847 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 16:30:50.372190 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 16:30:50.375759 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 16:30:50.378794 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 16:30:50.378882
6616 16:30:50.382566 CA PerBit enable=1, Macro0, CA PI delay=36
6617 16:30:50.382653
6618 16:30:50.385563 [CBTSetCACLKResult] CA Dly = 36
6619 16:30:50.385646 CS Dly: 1 (0~32)
6620 16:30:50.385712
6621 16:30:50.389284 ----->DramcWriteLeveling(PI) begin...
6622 16:30:50.389368 ==
6623 16:30:50.392681 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 16:30:50.398743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 16:30:50.398828 ==
6626 16:30:50.401912 Write leveling (Byte 0): 40 => 8
6627 16:30:50.405503 Write leveling (Byte 1): 40 => 8
6628 16:30:50.405586 DramcWriteLeveling(PI) end<-----
6629 16:30:50.408990
6630 16:30:50.409074 ==
6631 16:30:50.412081 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 16:30:50.415239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 16:30:50.415330 ==
6634 16:30:50.418427 [Gating] SW mode calibration
6635 16:30:50.425569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6636 16:30:50.428750 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6637 16:30:50.435314 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6638 16:30:50.438559 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6639 16:30:50.441740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6640 16:30:50.448417 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 16:30:50.451796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6642 16:30:50.458225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 16:30:50.461477 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 16:30:50.464832 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 16:30:50.471284 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6646 16:30:50.471369 Total UI for P1: 0, mck2ui 16
6647 16:30:50.474605 best dqsien dly found for B0: ( 0, 14, 24)
6648 16:30:50.477736 Total UI for P1: 0, mck2ui 16
6649 16:30:50.480860 best dqsien dly found for B1: ( 0, 14, 24)
6650 16:30:50.487730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6651 16:30:50.490956 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6652 16:30:50.491050
6653 16:30:50.494045 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6654 16:30:50.497955 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6655 16:30:50.501010 [Gating] SW calibration Done
6656 16:30:50.501091 ==
6657 16:30:50.504199 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 16:30:50.507434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 16:30:50.507529 ==
6660 16:30:50.510955 RX Vref Scan: 0
6661 16:30:50.511040
6662 16:30:50.511105 RX Vref 0 -> 0, step: 1
6663 16:30:50.511166
6664 16:30:50.513888 RX Delay -410 -> 252, step: 16
6665 16:30:50.520602 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6666 16:30:50.523731 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6667 16:30:50.527597 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6668 16:30:50.530709 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6669 16:30:50.537216 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6670 16:30:50.540351 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6671 16:30:50.543673 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6672 16:30:50.546878 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6673 16:30:50.553262 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6674 16:30:50.557030 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6675 16:30:50.560112 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6676 16:30:50.563365 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6677 16:30:50.569872 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6678 16:30:50.573277 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6679 16:30:50.576464 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6680 16:30:50.583134 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6681 16:30:50.583226 ==
6682 16:30:50.586716 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 16:30:50.589694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 16:30:50.589779 ==
6685 16:30:50.589846 DQS Delay:
6686 16:30:50.592920 DQS0 = 35, DQS1 = 51
6687 16:30:50.593027 DQM Delay:
6688 16:30:50.596191 DQM0 = 6, DQM1 = 13
6689 16:30:50.596267 DQ Delay:
6690 16:30:50.599408 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6691 16:30:50.603219 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6692 16:30:50.606452 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6693 16:30:50.609605 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6694 16:30:50.609693
6695 16:30:50.609760
6696 16:30:50.609819 ==
6697 16:30:50.612939 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 16:30:50.616298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 16:30:50.616383 ==
6700 16:30:50.616449
6701 16:30:50.616511
6702 16:30:50.619360 TX Vref Scan disable
6703 16:30:50.622920 == TX Byte 0 ==
6704 16:30:50.625870 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6705 16:30:50.629436 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6706 16:30:50.632447 == TX Byte 1 ==
6707 16:30:50.635685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6708 16:30:50.639011 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6709 16:30:50.639094 ==
6710 16:30:50.642202 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 16:30:50.645531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 16:30:50.648752 ==
6713 16:30:50.648836
6714 16:30:50.648901
6715 16:30:50.648961 TX Vref Scan disable
6716 16:30:50.651987 == TX Byte 0 ==
6717 16:30:50.655348 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 16:30:50.658411 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 16:30:50.661992 == TX Byte 1 ==
6720 16:30:50.665015 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 16:30:50.668329 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 16:30:50.668433
6723 16:30:50.671560 [DATLAT]
6724 16:30:50.671661 Freq=400, CH1 RK0
6725 16:30:50.671757
6726 16:30:50.674851 DATLAT Default: 0xf
6727 16:30:50.674922 0, 0xFFFF, sum = 0
6728 16:30:50.678174 1, 0xFFFF, sum = 0
6729 16:30:50.678248 2, 0xFFFF, sum = 0
6730 16:30:50.681899 3, 0xFFFF, sum = 0
6731 16:30:50.681999 4, 0xFFFF, sum = 0
6732 16:30:50.685127 5, 0xFFFF, sum = 0
6733 16:30:50.685236 6, 0xFFFF, sum = 0
6734 16:30:50.688307 7, 0xFFFF, sum = 0
6735 16:30:50.688411 8, 0xFFFF, sum = 0
6736 16:30:50.691612 9, 0xFFFF, sum = 0
6737 16:30:50.691685 10, 0xFFFF, sum = 0
6738 16:30:50.694543 11, 0xFFFF, sum = 0
6739 16:30:50.698267 12, 0xFFFF, sum = 0
6740 16:30:50.698351 13, 0x0, sum = 1
6741 16:30:50.698418 14, 0x0, sum = 2
6742 16:30:50.701391 15, 0x0, sum = 3
6743 16:30:50.701474 16, 0x0, sum = 4
6744 16:30:50.704635 best_step = 14
6745 16:30:50.704717
6746 16:30:50.704782 ==
6747 16:30:50.707713 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 16:30:50.711687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 16:30:50.711771 ==
6750 16:30:50.714549 RX Vref Scan: 1
6751 16:30:50.714632
6752 16:30:50.714696 RX Vref 0 -> 0, step: 1
6753 16:30:50.717689
6754 16:30:50.717771 RX Delay -343 -> 252, step: 8
6755 16:30:50.717837
6756 16:30:50.721016 Set Vref, RX VrefLevel [Byte0]: 51
6757 16:30:50.724236 [Byte1]: 50
6758 16:30:50.730046
6759 16:30:50.730122 Final RX Vref Byte 0 = 51 to rank0
6760 16:30:50.733187 Final RX Vref Byte 1 = 50 to rank0
6761 16:30:50.736443 Final RX Vref Byte 0 = 51 to rank1
6762 16:30:50.739500 Final RX Vref Byte 1 = 50 to rank1==
6763 16:30:50.742939 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 16:30:50.749646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 16:30:50.749731 ==
6766 16:30:50.749822 DQS Delay:
6767 16:30:50.752695 DQS0 = 44, DQS1 = 56
6768 16:30:50.752769 DQM Delay:
6769 16:30:50.752867 DQM0 = 10, DQM1 = 13
6770 16:30:50.755880 DQ Delay:
6771 16:30:50.759249 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6772 16:30:50.762403 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6773 16:30:50.762482 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6774 16:30:50.766280 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6775 16:30:50.769224
6776 16:30:50.769320
6777 16:30:50.776032 [DQSOSCAuto] RK0, (LSB)MR18= 0x7198, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6778 16:30:50.779348 CH1 RK0: MR19=C0C, MR18=7198
6779 16:30:50.785930 CH1_RK0: MR19=0xC0C, MR18=0x7198, DQSOSC=390, MR23=63, INC=388, DEC=258
6780 16:30:50.786013 ==
6781 16:30:50.789242 Dram Type= 6, Freq= 0, CH_1, rank 1
6782 16:30:50.792555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 16:30:50.792638 ==
6784 16:30:50.795734 [Gating] SW mode calibration
6785 16:30:50.802370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6786 16:30:50.808802 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6787 16:30:50.812471 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 16:30:50.815506 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 16:30:50.822269 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 16:30:50.825477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 16:30:50.828799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 16:30:50.835066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 16:30:50.838507 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 16:30:50.841663 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 16:30:50.848800 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6796 16:30:50.848899 Total UI for P1: 0, mck2ui 16
6797 16:30:50.854806 best dqsien dly found for B0: ( 0, 14, 24)
6798 16:30:50.854886 Total UI for P1: 0, mck2ui 16
6799 16:30:50.861858 best dqsien dly found for B1: ( 0, 14, 24)
6800 16:30:50.864755 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6801 16:30:50.867864 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6802 16:30:50.867972
6803 16:30:50.871886 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 16:30:50.875076 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 16:30:50.878227 [Gating] SW calibration Done
6806 16:30:50.878312 ==
6807 16:30:50.881222 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 16:30:50.884970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 16:30:50.885065 ==
6810 16:30:50.888267 RX Vref Scan: 0
6811 16:30:50.888361
6812 16:30:50.890905 RX Vref 0 -> 0, step: 1
6813 16:30:50.890976
6814 16:30:50.891036 RX Delay -410 -> 252, step: 16
6815 16:30:50.898101 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6816 16:30:50.900868 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6817 16:30:50.904626 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6818 16:30:50.910791 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6819 16:30:50.914073 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6820 16:30:50.917895 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6821 16:30:50.920939 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6822 16:30:50.927821 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6823 16:30:50.930888 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6824 16:30:50.934176 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6825 16:30:50.937133 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6826 16:30:50.944105 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6827 16:30:50.947296 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6828 16:30:50.950698 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6829 16:30:50.953889 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6830 16:30:50.960450 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6831 16:30:50.960527 ==
6832 16:30:50.963637 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 16:30:50.967220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 16:30:50.967295 ==
6835 16:30:50.967358 DQS Delay:
6836 16:30:50.970277 DQS0 = 43, DQS1 = 51
6837 16:30:50.970348 DQM Delay:
6838 16:30:50.973770 DQM0 = 8, DQM1 = 13
6839 16:30:50.973846 DQ Delay:
6840 16:30:50.976873 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6841 16:30:50.980176 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6842 16:30:50.983740 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6843 16:30:50.986757 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6844 16:30:50.986834
6845 16:30:50.986897
6846 16:30:50.986960 ==
6847 16:30:50.989874 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 16:30:50.993294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 16:30:50.993367 ==
6850 16:30:50.996426
6851 16:30:50.996498
6852 16:30:50.996558 TX Vref Scan disable
6853 16:30:51.000354 == TX Byte 0 ==
6854 16:30:51.003535 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6855 16:30:51.006298 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6856 16:30:51.010018 == TX Byte 1 ==
6857 16:30:51.012869 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6858 16:30:51.016483 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6859 16:30:51.016561 ==
6860 16:30:51.019722 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 16:30:51.023004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 16:30:51.026206 ==
6863 16:30:51.026282
6864 16:30:51.026361
6865 16:30:51.026426 TX Vref Scan disable
6866 16:30:51.029230 == TX Byte 0 ==
6867 16:30:51.032940 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6868 16:30:51.035944 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6869 16:30:51.039648 == TX Byte 1 ==
6870 16:30:51.042782 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6871 16:30:51.046122 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6872 16:30:51.046197
6873 16:30:51.049420 [DATLAT]
6874 16:30:51.049508 Freq=400, CH1 RK1
6875 16:30:51.049604
6876 16:30:51.052718 DATLAT Default: 0xe
6877 16:30:51.052802 0, 0xFFFF, sum = 0
6878 16:30:51.056054 1, 0xFFFF, sum = 0
6879 16:30:51.056126 2, 0xFFFF, sum = 0
6880 16:30:51.059361 3, 0xFFFF, sum = 0
6881 16:30:51.059433 4, 0xFFFF, sum = 0
6882 16:30:51.062599 5, 0xFFFF, sum = 0
6883 16:30:51.062670 6, 0xFFFF, sum = 0
6884 16:30:51.065826 7, 0xFFFF, sum = 0
6885 16:30:51.065896 8, 0xFFFF, sum = 0
6886 16:30:51.068967 9, 0xFFFF, sum = 0
6887 16:30:51.069038 10, 0xFFFF, sum = 0
6888 16:30:51.072215 11, 0xFFFF, sum = 0
6889 16:30:51.075441 12, 0xFFFF, sum = 0
6890 16:30:51.075512 13, 0x0, sum = 1
6891 16:30:51.078998 14, 0x0, sum = 2
6892 16:30:51.079103 15, 0x0, sum = 3
6893 16:30:51.079174 16, 0x0, sum = 4
6894 16:30:51.082171 best_step = 14
6895 16:30:51.082262
6896 16:30:51.082340 ==
6897 16:30:51.085394 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 16:30:51.088401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 16:30:51.088507 ==
6900 16:30:51.091952 RX Vref Scan: 0
6901 16:30:51.092054
6902 16:30:51.094901 RX Vref 0 -> 0, step: 1
6903 16:30:51.094987
6904 16:30:51.095050 RX Delay -343 -> 252, step: 8
6905 16:30:51.103760 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6906 16:30:51.107031 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6907 16:30:51.110228 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6908 16:30:51.113600 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6909 16:30:51.120329 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6910 16:30:51.123916 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6911 16:30:51.127248 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6912 16:30:51.130586 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6913 16:30:51.136901 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6914 16:30:51.139969 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6915 16:30:51.143721 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6916 16:30:51.150256 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6917 16:30:51.153698 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6918 16:30:51.156424 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6919 16:30:51.159732 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6920 16:30:51.166881 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6921 16:30:51.166981 ==
6922 16:30:51.169490 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 16:30:51.173401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 16:30:51.173497 ==
6925 16:30:51.173620 DQS Delay:
6926 16:30:51.176723 DQS0 = 48, DQS1 = 56
6927 16:30:51.176916 DQM Delay:
6928 16:30:51.180028 DQM0 = 11, DQM1 = 14
6929 16:30:51.180128 DQ Delay:
6930 16:30:51.183188 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6931 16:30:51.186152 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6932 16:30:51.189238 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6933 16:30:51.192545 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6934 16:30:51.192627
6935 16:30:51.192692
6936 16:30:51.202508 [DQSOSCAuto] RK1, (LSB)MR18= 0x79b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6937 16:30:51.202602 CH1 RK1: MR19=C0C, MR18=79B1
6938 16:30:51.209401 CH1_RK1: MR19=0xC0C, MR18=0x79B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6939 16:30:51.212653 [RxdqsGatingPostProcess] freq 400
6940 16:30:51.219069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6941 16:30:51.222811 best DQS0 dly(2T, 0.5T) = (0, 10)
6942 16:30:51.226071 best DQS1 dly(2T, 0.5T) = (0, 10)
6943 16:30:51.228998 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6944 16:30:51.232692 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6945 16:30:51.236076 best DQS0 dly(2T, 0.5T) = (0, 10)
6946 16:30:51.236150 best DQS1 dly(2T, 0.5T) = (0, 10)
6947 16:30:51.239251 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6948 16:30:51.242585 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6949 16:30:51.245925 Pre-setting of DQS Precalculation
6950 16:30:51.252534 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6951 16:30:51.259001 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6952 16:30:51.265209 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6953 16:30:51.265343
6954 16:30:51.265460
6955 16:30:51.268889 [Calibration Summary] 800 Mbps
6956 16:30:51.272114 CH 0, Rank 0
6957 16:30:51.272194 SW Impedance : PASS
6958 16:30:51.275476 DUTY Scan : NO K
6959 16:30:51.275552 ZQ Calibration : PASS
6960 16:30:51.278849 Jitter Meter : NO K
6961 16:30:51.282038 CBT Training : PASS
6962 16:30:51.282109 Write leveling : PASS
6963 16:30:51.285390 RX DQS gating : PASS
6964 16:30:51.288425 RX DQ/DQS(RDDQC) : PASS
6965 16:30:51.288498 TX DQ/DQS : PASS
6966 16:30:51.291529 RX DATLAT : PASS
6967 16:30:51.295252 RX DQ/DQS(Engine): PASS
6968 16:30:51.295334 TX OE : NO K
6969 16:30:51.298604 All Pass.
6970 16:30:51.298680
6971 16:30:51.298741 CH 0, Rank 1
6972 16:30:51.301851 SW Impedance : PASS
6973 16:30:51.301926 DUTY Scan : NO K
6974 16:30:51.305175 ZQ Calibration : PASS
6975 16:30:51.308433 Jitter Meter : NO K
6976 16:30:51.308508 CBT Training : PASS
6977 16:30:51.311668 Write leveling : NO K
6978 16:30:51.315125 RX DQS gating : PASS
6979 16:30:51.315200 RX DQ/DQS(RDDQC) : PASS
6980 16:30:51.318060 TX DQ/DQS : PASS
6981 16:30:51.321218 RX DATLAT : PASS
6982 16:30:51.321344 RX DQ/DQS(Engine): PASS
6983 16:30:51.324821 TX OE : NO K
6984 16:30:51.324891 All Pass.
6985 16:30:51.324954
6986 16:30:51.328288 CH 1, Rank 0
6987 16:30:51.328362 SW Impedance : PASS
6988 16:30:51.331261 DUTY Scan : NO K
6989 16:30:51.334615 ZQ Calibration : PASS
6990 16:30:51.334688 Jitter Meter : NO K
6991 16:30:51.337880 CBT Training : PASS
6992 16:30:51.341225 Write leveling : PASS
6993 16:30:51.341337 RX DQS gating : PASS
6994 16:30:51.344475 RX DQ/DQS(RDDQC) : PASS
6995 16:30:51.347673 TX DQ/DQS : PASS
6996 16:30:51.347745 RX DATLAT : PASS
6997 16:30:51.351479 RX DQ/DQS(Engine): PASS
6998 16:30:51.351551 TX OE : NO K
6999 16:30:51.354802 All Pass.
7000 16:30:51.354872
7001 16:30:51.354935 CH 1, Rank 1
7002 16:30:51.357494 SW Impedance : PASS
7003 16:30:51.357567 DUTY Scan : NO K
7004 16:30:51.360751 ZQ Calibration : PASS
7005 16:30:51.364014 Jitter Meter : NO K
7006 16:30:51.364085 CBT Training : PASS
7007 16:30:51.367711 Write leveling : NO K
7008 16:30:51.370976 RX DQS gating : PASS
7009 16:30:51.371048 RX DQ/DQS(RDDQC) : PASS
7010 16:30:51.373859 TX DQ/DQS : PASS
7011 16:30:51.377211 RX DATLAT : PASS
7012 16:30:51.377328 RX DQ/DQS(Engine): PASS
7013 16:30:51.380342 TX OE : NO K
7014 16:30:51.380419 All Pass.
7015 16:30:51.380480
7016 16:30:51.384138 DramC Write-DBI off
7017 16:30:51.387395 PER_BANK_REFRESH: Hybrid Mode
7018 16:30:51.387473 TX_TRACKING: ON
7019 16:30:51.396988 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7020 16:30:51.400083 [FAST_K] Save calibration result to emmc
7021 16:30:51.403392 dramc_set_vcore_voltage set vcore to 725000
7022 16:30:51.407305 Read voltage for 1600, 0
7023 16:30:51.407376 Vio18 = 0
7024 16:30:51.410570 Vcore = 725000
7025 16:30:51.410643 Vdram = 0
7026 16:30:51.410708 Vddq = 0
7027 16:30:51.410765 Vmddr = 0
7028 16:30:51.417135 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7029 16:30:51.423582 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7030 16:30:51.423659 MEM_TYPE=3, freq_sel=13
7031 16:30:51.427100 sv_algorithm_assistance_LP4_3733
7032 16:30:51.430213 ============ PULL DRAM RESETB DOWN ============
7033 16:30:51.436604 ========== PULL DRAM RESETB DOWN end =========
7034 16:30:51.439680 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7035 16:30:51.443521 ===================================
7036 16:30:51.446583 LPDDR4 DRAM CONFIGURATION
7037 16:30:51.449602 ===================================
7038 16:30:51.449679 EX_ROW_EN[0] = 0x0
7039 16:30:51.453099 EX_ROW_EN[1] = 0x0
7040 16:30:51.456435 LP4Y_EN = 0x0
7041 16:30:51.456509 WORK_FSP = 0x1
7042 16:30:51.459629 WL = 0x5
7043 16:30:51.459704 RL = 0x5
7044 16:30:51.462768 BL = 0x2
7045 16:30:51.462843 RPST = 0x0
7046 16:30:51.466197 RD_PRE = 0x0
7047 16:30:51.466267 WR_PRE = 0x1
7048 16:30:51.469343 WR_PST = 0x1
7049 16:30:51.469413 DBI_WR = 0x0
7050 16:30:51.472722 DBI_RD = 0x0
7051 16:30:51.472795 OTF = 0x1
7052 16:30:51.475838 ===================================
7053 16:30:51.479866 ===================================
7054 16:30:51.482797 ANA top config
7055 16:30:51.485909 ===================================
7056 16:30:51.485988 DLL_ASYNC_EN = 0
7057 16:30:51.489397 ALL_SLAVE_EN = 0
7058 16:30:51.492871 NEW_RANK_MODE = 1
7059 16:30:51.495642 DLL_IDLE_MODE = 1
7060 16:30:51.499451 LP45_APHY_COMB_EN = 1
7061 16:30:51.499528 TX_ODT_DIS = 0
7062 16:30:51.502583 NEW_8X_MODE = 1
7063 16:30:51.505697 ===================================
7064 16:30:51.509141 ===================================
7065 16:30:51.512152 data_rate = 3200
7066 16:30:51.516000 CKR = 1
7067 16:30:51.519395 DQ_P2S_RATIO = 8
7068 16:30:51.522559 ===================================
7069 16:30:51.525763 CA_P2S_RATIO = 8
7070 16:30:51.525838 DQ_CA_OPEN = 0
7071 16:30:51.529048 DQ_SEMI_OPEN = 0
7072 16:30:51.532446 CA_SEMI_OPEN = 0
7073 16:30:51.535742 CA_FULL_RATE = 0
7074 16:30:51.538924 DQ_CKDIV4_EN = 0
7075 16:30:51.541917 CA_CKDIV4_EN = 0
7076 16:30:51.541992 CA_PREDIV_EN = 0
7077 16:30:51.545107 PH8_DLY = 12
7078 16:30:51.548946 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7079 16:30:51.552155 DQ_AAMCK_DIV = 4
7080 16:30:51.555501 CA_AAMCK_DIV = 4
7081 16:30:51.558512 CA_ADMCK_DIV = 4
7082 16:30:51.558590 DQ_TRACK_CA_EN = 0
7083 16:30:51.561578 CA_PICK = 1600
7084 16:30:51.565108 CA_MCKIO = 1600
7085 16:30:51.568065 MCKIO_SEMI = 0
7086 16:30:51.571696 PLL_FREQ = 3068
7087 16:30:51.574934 DQ_UI_PI_RATIO = 32
7088 16:30:51.578137 CA_UI_PI_RATIO = 0
7089 16:30:51.581470 ===================================
7090 16:30:51.584754 ===================================
7091 16:30:51.587990 memory_type:LPDDR4
7092 16:30:51.588091 GP_NUM : 10
7093 16:30:51.591252 SRAM_EN : 1
7094 16:30:51.591325 MD32_EN : 0
7095 16:30:51.594532 ===================================
7096 16:30:51.598020 [ANA_INIT] >>>>>>>>>>>>>>
7097 16:30:51.600811 <<<<<< [CONFIGURE PHASE]: ANA_TX
7098 16:30:51.604583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7099 16:30:51.607454 ===================================
7100 16:30:51.610865 data_rate = 3200,PCW = 0X7600
7101 16:30:51.614480 ===================================
7102 16:30:51.617386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7103 16:30:51.624345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7104 16:30:51.627542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7105 16:30:51.634064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7106 16:30:51.637373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7107 16:30:51.640705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7108 16:30:51.640837 [ANA_INIT] flow start
7109 16:30:51.643880 [ANA_INIT] PLL >>>>>>>>
7110 16:30:51.646861 [ANA_INIT] PLL <<<<<<<<
7111 16:30:51.647015 [ANA_INIT] MIDPI >>>>>>>>
7112 16:30:51.650607 [ANA_INIT] MIDPI <<<<<<<<
7113 16:30:51.653850 [ANA_INIT] DLL >>>>>>>>
7114 16:30:51.657241 [ANA_INIT] DLL <<<<<<<<
7115 16:30:51.657409 [ANA_INIT] flow end
7116 16:30:51.660425 ============ LP4 DIFF to SE enter ============
7117 16:30:51.666873 ============ LP4 DIFF to SE exit ============
7118 16:30:51.666982 [ANA_INIT] <<<<<<<<<<<<<
7119 16:30:51.669956 [Flow] Enable top DCM control >>>>>
7120 16:30:51.673615 [Flow] Enable top DCM control <<<<<
7121 16:30:51.676591 Enable DLL master slave shuffle
7122 16:30:51.683164 ==============================================================
7123 16:30:51.683306 Gating Mode config
7124 16:30:51.690242 ==============================================================
7125 16:30:51.693589 Config description:
7126 16:30:51.703294 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7127 16:30:51.709529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7128 16:30:51.712600 SELPH_MODE 0: By rank 1: By Phase
7129 16:30:51.719417 ==============================================================
7130 16:30:51.722547 GAT_TRACK_EN = 1
7131 16:30:51.726299 RX_GATING_MODE = 2
7132 16:30:51.729209 RX_GATING_TRACK_MODE = 2
7133 16:30:51.729361 SELPH_MODE = 1
7134 16:30:51.732481 PICG_EARLY_EN = 1
7135 16:30:51.735780 VALID_LAT_VALUE = 1
7136 16:30:51.742420 ==============================================================
7137 16:30:51.745695 Enter into Gating configuration >>>>
7138 16:30:51.749508 Exit from Gating configuration <<<<
7139 16:30:51.752530 Enter into DVFS_PRE_config >>>>>
7140 16:30:51.762524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7141 16:30:51.765846 Exit from DVFS_PRE_config <<<<<
7142 16:30:51.769154 Enter into PICG configuration >>>>
7143 16:30:51.772575 Exit from PICG configuration <<<<
7144 16:30:51.776313 [RX_INPUT] configuration >>>>>
7145 16:30:51.779176 [RX_INPUT] configuration <<<<<
7146 16:30:51.782787 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7147 16:30:51.789215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7148 16:30:51.795977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7149 16:30:51.802604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7150 16:30:51.805779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7151 16:30:51.812771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7152 16:30:51.816104 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7153 16:30:51.822465 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7154 16:30:51.825550 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7155 16:30:51.828823 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7156 16:30:51.832521 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7157 16:30:51.838669 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 16:30:51.842035 ===================================
7159 16:30:51.845285 LPDDR4 DRAM CONFIGURATION
7160 16:30:51.848656 ===================================
7161 16:30:51.848761 EX_ROW_EN[0] = 0x0
7162 16:30:51.851877 EX_ROW_EN[1] = 0x0
7163 16:30:51.851982 LP4Y_EN = 0x0
7164 16:30:51.855156 WORK_FSP = 0x1
7165 16:30:51.855257 WL = 0x5
7166 16:30:51.858246 RL = 0x5
7167 16:30:51.858327 BL = 0x2
7168 16:30:51.861797 RPST = 0x0
7169 16:30:51.864887 RD_PRE = 0x0
7170 16:30:51.864998 WR_PRE = 0x1
7171 16:30:51.868189 WR_PST = 0x1
7172 16:30:51.868296 DBI_WR = 0x0
7173 16:30:51.871385 DBI_RD = 0x0
7174 16:30:51.871488 OTF = 0x1
7175 16:30:51.874739 ===================================
7176 16:30:51.878622 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7177 16:30:51.884964 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7178 16:30:51.887972 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 16:30:51.891247 ===================================
7180 16:30:51.894548 LPDDR4 DRAM CONFIGURATION
7181 16:30:51.897819 ===================================
7182 16:30:51.897930 EX_ROW_EN[0] = 0x10
7183 16:30:51.900880 EX_ROW_EN[1] = 0x0
7184 16:30:51.900988 LP4Y_EN = 0x0
7185 16:30:51.904820 WORK_FSP = 0x1
7186 16:30:51.904943 WL = 0x5
7187 16:30:51.908040 RL = 0x5
7188 16:30:51.911290 BL = 0x2
7189 16:30:51.911423 RPST = 0x0
7190 16:30:51.914568 RD_PRE = 0x0
7191 16:30:51.914681 WR_PRE = 0x1
7192 16:30:51.917785 WR_PST = 0x1
7193 16:30:51.917884 DBI_WR = 0x0
7194 16:30:51.922605 DBI_RD = 0x0
7195 16:30:51.922758 OTF = 0x1
7196 16:30:51.924059 ===================================
7197 16:30:51.930964 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7198 16:30:51.931152 ==
7199 16:30:51.934186 Dram Type= 6, Freq= 0, CH_0, rank 0
7200 16:30:51.937315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7201 16:30:51.937445 ==
7202 16:30:51.941174 [Duty_Offset_Calibration]
7203 16:30:51.944241 B0:2 B1:0 CA:4
7204 16:30:51.944375
7205 16:30:51.947493 [DutyScan_Calibration_Flow] k_type=0
7206 16:30:51.955307
7207 16:30:51.955413 ==CLK 0==
7208 16:30:51.958602 Final CLK duty delay cell = -4
7209 16:30:51.961731 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7210 16:30:51.965012 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7211 16:30:51.968728 [-4] AVG Duty = 4937%(X100)
7212 16:30:51.968806
7213 16:30:51.971814 CH0 CLK Duty spec in!! Max-Min= 187%
7214 16:30:51.976607 [DutyScan_Calibration_Flow] ====Done====
7215 16:30:51.976770
7216 16:30:51.978305 [DutyScan_Calibration_Flow] k_type=1
7217 16:30:51.995646
7218 16:30:51.995750 ==DQS 0 ==
7219 16:30:51.998771 Final DQS duty delay cell = 0
7220 16:30:52.002069 [0] MAX Duty = 5218%(X100), DQS PI = 38
7221 16:30:52.005163 [0] MIN Duty = 5093%(X100), DQS PI = 4
7222 16:30:52.008774 [0] AVG Duty = 5155%(X100)
7223 16:30:52.008878
7224 16:30:52.008986 ==DQS 1 ==
7225 16:30:52.012036 Final DQS duty delay cell = 0
7226 16:30:52.015205 [0] MAX Duty = 5156%(X100), DQS PI = 2
7227 16:30:52.018669 [0] MIN Duty = 4938%(X100), DQS PI = 58
7228 16:30:52.021631 [0] AVG Duty = 5047%(X100)
7229 16:30:52.021744
7230 16:30:52.024902 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7231 16:30:52.025021
7232 16:30:52.028686 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7233 16:30:52.031917 [DutyScan_Calibration_Flow] ====Done====
7234 16:30:52.032023
7235 16:30:52.034863 [DutyScan_Calibration_Flow] k_type=3
7236 16:30:52.052519
7237 16:30:52.052635 ==DQM 0 ==
7238 16:30:52.055712 Final DQM duty delay cell = 0
7239 16:30:52.059020 [0] MAX Duty = 5124%(X100), DQS PI = 22
7240 16:30:52.062082 [0] MIN Duty = 4844%(X100), DQS PI = 56
7241 16:30:52.065845 [0] AVG Duty = 4984%(X100)
7242 16:30:52.065994
7243 16:30:52.066098 ==DQM 1 ==
7244 16:30:52.069116 Final DQM duty delay cell = 0
7245 16:30:52.072336 [0] MAX Duty = 4938%(X100), DQS PI = 0
7246 16:30:52.075890 [0] MIN Duty = 4844%(X100), DQS PI = 14
7247 16:30:52.079027 [0] AVG Duty = 4891%(X100)
7248 16:30:52.079147
7249 16:30:52.082395 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7250 16:30:52.082505
7251 16:30:52.085730 CH0 DQM 1 Duty spec in!! Max-Min= 94%
7252 16:30:52.088881 [DutyScan_Calibration_Flow] ====Done====
7253 16:30:52.088984
7254 16:30:52.092120 [DutyScan_Calibration_Flow] k_type=2
7255 16:30:52.109684
7256 16:30:52.109847 ==DQ 0 ==
7257 16:30:52.112688 Final DQ duty delay cell = 0
7258 16:30:52.115821 [0] MAX Duty = 5124%(X100), DQS PI = 20
7259 16:30:52.119574 [0] MIN Duty = 4938%(X100), DQS PI = 12
7260 16:30:52.122675 [0] AVG Duty = 5031%(X100)
7261 16:30:52.122784
7262 16:30:52.122883 ==DQ 1 ==
7263 16:30:52.125916 Final DQ duty delay cell = 0
7264 16:30:52.129110 [0] MAX Duty = 5218%(X100), DQS PI = 2
7265 16:30:52.132381 [0] MIN Duty = 4907%(X100), DQS PI = 32
7266 16:30:52.132486 [0] AVG Duty = 5062%(X100)
7267 16:30:52.135567
7268 16:30:52.139303 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7269 16:30:52.139389
7270 16:30:52.142456 CH0 DQ 1 Duty spec in!! Max-Min= 311%
7271 16:30:52.145639 [DutyScan_Calibration_Flow] ====Done====
7272 16:30:52.145757 ==
7273 16:30:52.148732 Dram Type= 6, Freq= 0, CH_1, rank 0
7274 16:30:52.152035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 16:30:52.152134 ==
7276 16:30:52.155201 [Duty_Offset_Calibration]
7277 16:30:52.155279 B0:0 B1:-1 CA:3
7278 16:30:52.155343
7279 16:30:52.158880 [DutyScan_Calibration_Flow] k_type=0
7280 16:30:52.169181
7281 16:30:52.169311 ==CLK 0==
7282 16:30:52.172418 Final CLK duty delay cell = -4
7283 16:30:52.175540 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7284 16:30:52.178991 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7285 16:30:52.182008 [-4] AVG Duty = 4906%(X100)
7286 16:30:52.182129
7287 16:30:52.185201 CH1 CLK Duty spec in!! Max-Min= 187%
7288 16:30:52.189098 [DutyScan_Calibration_Flow] ====Done====
7289 16:30:52.189175
7290 16:30:52.191748 [DutyScan_Calibration_Flow] k_type=1
7291 16:30:52.208289
7292 16:30:52.208376 ==DQS 0 ==
7293 16:30:52.211458 Final DQS duty delay cell = 0
7294 16:30:52.214770 [0] MAX Duty = 5218%(X100), DQS PI = 28
7295 16:30:52.217967 [0] MIN Duty = 4907%(X100), DQS PI = 42
7296 16:30:52.221277 [0] AVG Duty = 5062%(X100)
7297 16:30:52.221369
7298 16:30:52.221435 ==DQS 1 ==
7299 16:30:52.225044 Final DQS duty delay cell = -4
7300 16:30:52.227922 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7301 16:30:52.231612 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7302 16:30:52.234752 [-4] AVG Duty = 4906%(X100)
7303 16:30:52.234826
7304 16:30:52.237775 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7305 16:30:52.237852
7306 16:30:52.241565 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7307 16:30:52.244165 [DutyScan_Calibration_Flow] ====Done====
7308 16:30:52.244247
7309 16:30:52.247897 [DutyScan_Calibration_Flow] k_type=3
7310 16:30:52.265447
7311 16:30:52.265536 ==DQM 0 ==
7312 16:30:52.268755 Final DQM duty delay cell = 0
7313 16:30:52.271999 [0] MAX Duty = 5062%(X100), DQS PI = 30
7314 16:30:52.275254 [0] MIN Duty = 4782%(X100), DQS PI = 38
7315 16:30:52.278578 [0] AVG Duty = 4922%(X100)
7316 16:30:52.278662
7317 16:30:52.278727 ==DQM 1 ==
7318 16:30:52.282270 Final DQM duty delay cell = 0
7319 16:30:52.285346 [0] MAX Duty = 4969%(X100), DQS PI = 30
7320 16:30:52.288334 [0] MIN Duty = 4813%(X100), DQS PI = 0
7321 16:30:52.291708 [0] AVG Duty = 4891%(X100)
7322 16:30:52.291790
7323 16:30:52.295559 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7324 16:30:52.295646
7325 16:30:52.298815 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7326 16:30:52.302016 [DutyScan_Calibration_Flow] ====Done====
7327 16:30:52.302105
7328 16:30:52.305338 [DutyScan_Calibration_Flow] k_type=2
7329 16:30:52.321421
7330 16:30:52.321575 ==DQ 0 ==
7331 16:30:52.324577 Final DQ duty delay cell = -4
7332 16:30:52.327825 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7333 16:30:52.331161 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7334 16:30:52.428466 [-4] AVG Duty = 4875%(X100)
7335 16:30:52.428652
7336 16:30:52.428756 ==DQ 1 ==
7337 16:30:52.428854 Final DQ duty delay cell = 0
7338 16:30:52.428967 [0] MAX Duty = 5031%(X100), DQS PI = 30
7339 16:30:52.429085 [0] MIN Duty = 4875%(X100), DQS PI = 52
7340 16:30:52.429182 [0] AVG Duty = 4953%(X100)
7341 16:30:52.429285
7342 16:30:52.429375 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7343 16:30:52.429464
7344 16:30:52.429553 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7345 16:30:52.429640 [DutyScan_Calibration_Flow] ====Done====
7346 16:30:52.429725 nWR fixed to 30
7347 16:30:52.429813 [ModeRegInit_LP4] CH0 RK0
7348 16:30:52.429897 [ModeRegInit_LP4] CH0 RK1
7349 16:30:52.429981 [ModeRegInit_LP4] CH1 RK0
7350 16:30:52.430058 [ModeRegInit_LP4] CH1 RK1
7351 16:30:52.430133 match AC timing 5
7352 16:30:52.430228 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7353 16:30:52.430317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7354 16:30:52.430401 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7355 16:30:52.430496 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7356 16:30:52.430581 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7357 16:30:52.430664 [MiockJmeterHQA]
7358 16:30:52.430745
7359 16:30:52.430833 [DramcMiockJmeter] u1RxGatingPI = 0
7360 16:30:52.430923 0 : 4255, 4029
7361 16:30:52.431012 4 : 4252, 4027
7362 16:30:52.431099 8 : 4363, 4138
7363 16:30:52.431193 12 : 4252, 4027
7364 16:30:52.431282 16 : 4253, 4027
7365 16:30:52.431368 20 : 4363, 4137
7366 16:30:52.431452 24 : 4360, 4138
7367 16:30:52.431539 28 : 4252, 4026
7368 16:30:52.431624 32 : 4250, 4027
7369 16:30:52.431708 36 : 4252, 4027
7370 16:30:52.431796 40 : 4363, 4138
7371 16:30:52.431884 44 : 4249, 4027
7372 16:30:52.431968 48 : 4361, 4137
7373 16:30:52.432056 52 : 4255, 4030
7374 16:30:52.432141 56 : 4250, 4026
7375 16:30:52.432225 60 : 4250, 4027
7376 16:30:52.432312 64 : 4249, 4027
7377 16:30:52.432396 68 : 4361, 4137
7378 16:30:52.432480 72 : 4250, 4027
7379 16:30:52.432547 76 : 4360, 4137
7380 16:30:52.432806 80 : 4250, 4027
7381 16:30:52.432896 84 : 4249, 4027
7382 16:30:52.433466 88 : 4250, 4026
7383 16:30:52.433552 92 : 4366, 4140
7384 16:30:52.436142 96 : 4249, 2588
7385 16:30:52.436252 100 : 4361, 0
7386 16:30:52.436358 104 : 4361, 0
7387 16:30:52.439935 108 : 4252, 0
7388 16:30:52.440044 112 : 4250, 0
7389 16:30:52.443116 116 : 4250, 0
7390 16:30:52.443231 120 : 4250, 0
7391 16:30:52.443330 124 : 4250, 0
7392 16:30:52.446269 128 : 4250, 0
7393 16:30:52.446381 132 : 4250, 0
7394 16:30:52.449580 136 : 4360, 0
7395 16:30:52.449661 140 : 4363, 0
7396 16:30:52.449727 144 : 4247, 0
7397 16:30:52.453607 148 : 4250, 0
7398 16:30:52.453682 152 : 4361, 0
7399 16:30:52.456248 156 : 4360, 0
7400 16:30:52.456338 160 : 4250, 0
7401 16:30:52.456401 164 : 4250, 0
7402 16:30:52.459652 168 : 4250, 0
7403 16:30:52.459764 172 : 4250, 0
7404 16:30:52.462689 176 : 4250, 0
7405 16:30:52.462793 180 : 4250, 0
7406 16:30:52.462886 184 : 4249, 0
7407 16:30:52.465964 188 : 4360, 0
7408 16:30:52.466067 192 : 4361, 0
7409 16:30:52.466160 196 : 4250, 0
7410 16:30:52.469477 200 : 4361, 0
7411 16:30:52.469557 204 : 4361, 0
7412 16:30:52.472954 208 : 4360, 0
7413 16:30:52.473045 212 : 4250, 0
7414 16:30:52.473116 216 : 4253, 0
7415 16:30:52.475992 220 : 4250, 579
7416 16:30:52.476084 224 : 4250, 4014
7417 16:30:52.479106 228 : 4253, 4029
7418 16:30:52.479203 232 : 4252, 4030
7419 16:30:52.482772 236 : 4249, 4027
7420 16:30:52.482857 240 : 4250, 4027
7421 16:30:52.486046 244 : 4250, 4026
7422 16:30:52.486171 248 : 4249, 4027
7423 16:30:52.489150 252 : 4250, 4026
7424 16:30:52.489273 256 : 4361, 4137
7425 16:30:52.492493 260 : 4360, 4138
7426 16:30:52.492618 264 : 4247, 4024
7427 16:30:52.495782 268 : 4360, 4137
7428 16:30:52.495903 272 : 4361, 4137
7429 16:30:52.496014 276 : 4250, 4027
7430 16:30:52.498832 280 : 4250, 4027
7431 16:30:52.498939 284 : 4250, 4027
7432 16:30:52.502535 288 : 4250, 4026
7433 16:30:52.502656 292 : 4250, 4027
7434 16:30:52.505692 296 : 4250, 4027
7435 16:30:52.505804 300 : 4249, 4027
7436 16:30:52.508896 304 : 4250, 4026
7437 16:30:52.509007 308 : 4361, 4137
7438 16:30:52.512200 312 : 4360, 4138
7439 16:30:52.512320 316 : 4248, 4024
7440 16:30:52.515500 320 : 4360, 4137
7441 16:30:52.515616 324 : 4361, 4137
7442 16:30:52.518630 328 : 4250, 4027
7443 16:30:52.518739 332 : 4250, 3643
7444 16:30:52.521916 336 : 4249, 1146
7445 16:30:52.522034
7446 16:30:52.522130 MIOCK jitter meter ch=0
7447 16:30:52.522219
7448 16:30:52.525084 1T = (336-100) = 236 dly cells
7449 16:30:52.531536 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7450 16:30:52.531651 ==
7451 16:30:52.535386 Dram Type= 6, Freq= 0, CH_0, rank 0
7452 16:30:52.538385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7453 16:30:52.538503 ==
7454 16:30:52.545086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7455 16:30:52.548516 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7456 16:30:52.551722 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7457 16:30:52.558383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7458 16:30:52.567846 [CA 0] Center 43 (13~74) winsize 62
7459 16:30:52.571055 [CA 1] Center 42 (12~73) winsize 62
7460 16:30:52.574382 [CA 2] Center 37 (8~67) winsize 60
7461 16:30:52.577929 [CA 3] Center 37 (8~67) winsize 60
7462 16:30:52.581131 [CA 4] Center 36 (6~66) winsize 61
7463 16:30:52.584292 [CA 5] Center 35 (5~66) winsize 62
7464 16:30:52.584410
7465 16:30:52.587942 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7466 16:30:52.588046
7467 16:30:52.594539 [CATrainingPosCal] consider 1 rank data
7468 16:30:52.594672 u2DelayCellTimex100 = 275/100 ps
7469 16:30:52.600897 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7470 16:30:52.604049 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7471 16:30:52.607341 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7472 16:30:52.610582 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7473 16:30:52.613807 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7474 16:30:52.617196 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7475 16:30:52.617333
7476 16:30:52.620426 CA PerBit enable=1, Macro0, CA PI delay=35
7477 16:30:52.620527
7478 16:30:52.623719 [CBTSetCACLKResult] CA Dly = 35
7479 16:30:52.627407 CS Dly: 11 (0~42)
7480 16:30:52.630578 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7481 16:30:52.633907 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7482 16:30:52.634014 ==
7483 16:30:52.637182 Dram Type= 6, Freq= 0, CH_0, rank 1
7484 16:30:52.643515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7485 16:30:52.643598 ==
7486 16:30:52.646647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7487 16:30:52.653374 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7488 16:30:52.656616 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7489 16:30:52.663594 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7490 16:30:52.671418 [CA 0] Center 43 (13~74) winsize 62
7491 16:30:52.674508 [CA 1] Center 43 (13~73) winsize 61
7492 16:30:52.678655 [CA 2] Center 38 (9~68) winsize 60
7493 16:30:52.681186 [CA 3] Center 38 (9~68) winsize 60
7494 16:30:52.684563 [CA 4] Center 36 (6~66) winsize 61
7495 16:30:52.687837 [CA 5] Center 36 (6~66) winsize 61
7496 16:30:52.687948
7497 16:30:52.691049 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7498 16:30:52.691162
7499 16:30:52.694588 [CATrainingPosCal] consider 2 rank data
7500 16:30:52.698082 u2DelayCellTimex100 = 275/100 ps
7501 16:30:52.704718 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7502 16:30:52.707802 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7503 16:30:52.710862 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7504 16:30:52.714267 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7505 16:30:52.717281 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7506 16:30:52.720806 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7507 16:30:52.720925
7508 16:30:52.723931 CA PerBit enable=1, Macro0, CA PI delay=36
7509 16:30:52.724054
7510 16:30:52.727043 [CBTSetCACLKResult] CA Dly = 36
7511 16:30:52.730386 CS Dly: 12 (0~44)
7512 16:30:52.734307 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7513 16:30:52.736934 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7514 16:30:52.737040
7515 16:30:52.740162 ----->DramcWriteLeveling(PI) begin...
7516 16:30:52.743592 ==
7517 16:30:52.743698 Dram Type= 6, Freq= 0, CH_0, rank 0
7518 16:30:52.750763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 16:30:52.750871 ==
7520 16:30:52.753229 Write leveling (Byte 0): 34 => 34
7521 16:30:52.756857 Write leveling (Byte 1): 24 => 24
7522 16:30:52.760462 DramcWriteLeveling(PI) end<-----
7523 16:30:52.760543
7524 16:30:52.760642 ==
7525 16:30:52.763638 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 16:30:52.766987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 16:30:52.767090 ==
7528 16:30:52.770254 [Gating] SW mode calibration
7529 16:30:52.776693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7530 16:30:52.782983 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7531 16:30:52.786335 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7532 16:30:52.789641 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7533 16:30:52.796215 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 16:30:52.799473 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7535 16:30:52.803051 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7536 16:30:52.809476 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7537 16:30:52.812728 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7538 16:30:52.815993 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 16:30:52.822610 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 16:30:52.826070 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 16:30:52.829010 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7542 16:30:52.835371 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7543 16:30:52.839150 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7544 16:30:52.842256 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7545 16:30:52.848912 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 16:30:52.852281 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 16:30:52.855558 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 16:30:52.861806 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 16:30:52.865642 1 6 8 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7550 16:30:52.868569 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7551 16:30:52.875042 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7552 16:30:52.878709 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7553 16:30:52.882113 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7554 16:30:52.888536 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 16:30:52.891824 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 16:30:52.895165 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7557 16:30:52.901582 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7558 16:30:52.904748 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7559 16:30:52.908585 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7560 16:30:52.914546 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7561 16:30:52.918544 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7562 16:30:52.921609 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 16:30:52.927977 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 16:30:52.931152 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 16:30:52.934861 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 16:30:52.941542 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 16:30:52.944631 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 16:30:52.947934 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 16:30:52.954377 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 16:30:52.957316 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 16:30:52.960836 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 16:30:52.967499 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 16:30:52.970812 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7574 16:30:52.973735 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7575 16:30:52.977042 Total UI for P1: 0, mck2ui 16
7576 16:30:52.980486 best dqsien dly found for B0: ( 1, 9, 8)
7577 16:30:52.987403 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7578 16:30:52.990528 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7579 16:30:52.993799 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 16:30:53.000487 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 16:30:53.000563 Total UI for P1: 0, mck2ui 16
7582 16:30:53.006998 best dqsien dly found for B1: ( 1, 9, 24)
7583 16:30:53.010666 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7584 16:30:53.013855 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7585 16:30:53.013931
7586 16:30:53.017065 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7587 16:30:53.020273 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7588 16:30:53.023590 [Gating] SW calibration Done
7589 16:30:53.023671 ==
7590 16:30:53.026904 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 16:30:53.030109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 16:30:53.030191 ==
7593 16:30:53.033386 RX Vref Scan: 0
7594 16:30:53.033466
7595 16:30:53.033530 RX Vref 0 -> 0, step: 1
7596 16:30:53.036393
7597 16:30:53.036474 RX Delay 0 -> 252, step: 8
7598 16:30:53.040231 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7599 16:30:53.046688 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7600 16:30:53.049896 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7601 16:30:53.053078 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7602 16:30:53.056314 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7603 16:30:53.062783 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7604 16:30:53.066698 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7605 16:30:53.069689 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7606 16:30:53.072821 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7607 16:30:53.076424 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7608 16:30:53.079675 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7609 16:30:53.086221 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7610 16:30:53.089379 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7611 16:30:53.092963 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7612 16:30:53.095900 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7613 16:30:53.102787 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7614 16:30:53.102868 ==
7615 16:30:53.106003 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 16:30:53.109460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 16:30:53.109542 ==
7618 16:30:53.109606 DQS Delay:
7619 16:30:53.112632 DQS0 = 0, DQS1 = 0
7620 16:30:53.112712 DQM Delay:
7621 16:30:53.115792 DQM0 = 131, DQM1 = 127
7622 16:30:53.115872 DQ Delay:
7623 16:30:53.119049 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7624 16:30:53.122379 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7625 16:30:53.125532 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7626 16:30:53.128877 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7627 16:30:53.132197
7628 16:30:53.132297
7629 16:30:53.132387 ==
7630 16:30:53.135543 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 16:30:53.138739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 16:30:53.138839 ==
7633 16:30:53.138931
7634 16:30:53.139027
7635 16:30:53.142471 TX Vref Scan disable
7636 16:30:53.142569 == TX Byte 0 ==
7637 16:30:53.148994 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7638 16:30:53.152294 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7639 16:30:53.152374 == TX Byte 1 ==
7640 16:30:53.158652 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7641 16:30:53.162549 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7642 16:30:53.162631 ==
7643 16:30:53.165599 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 16:30:53.168881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 16:30:53.168963 ==
7646 16:30:53.184402
7647 16:30:53.187642 TX Vref early break, caculate TX vref
7648 16:30:53.190879 TX Vref=16, minBit 1, minWin=22, winSum=372
7649 16:30:53.194190 TX Vref=18, minBit 8, minWin=22, winSum=373
7650 16:30:53.197487 TX Vref=20, minBit 8, minWin=22, winSum=386
7651 16:30:53.200761 TX Vref=22, minBit 4, minWin=24, winSum=398
7652 16:30:53.203938 TX Vref=24, minBit 0, minWin=25, winSum=406
7653 16:30:53.210791 TX Vref=26, minBit 1, minWin=25, winSum=413
7654 16:30:53.213890 TX Vref=28, minBit 1, minWin=25, winSum=411
7655 16:30:53.217515 TX Vref=30, minBit 1, minWin=25, winSum=413
7656 16:30:53.220696 TX Vref=32, minBit 2, minWin=24, winSum=407
7657 16:30:53.223830 TX Vref=34, minBit 9, minWin=23, winSum=393
7658 16:30:53.230476 TX Vref=36, minBit 2, minWin=23, winSum=383
7659 16:30:53.233717 [TxChooseVref] Worse bit 1, Min win 25, Win sum 413, Final Vref 26
7660 16:30:53.233822
7661 16:30:53.237158 Final TX Range 0 Vref 26
7662 16:30:53.237289
7663 16:30:53.237356 ==
7664 16:30:53.240253 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 16:30:53.243494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 16:30:53.247214 ==
7667 16:30:53.247295
7668 16:30:53.247359
7669 16:30:53.247418 TX Vref Scan disable
7670 16:30:53.253728 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7671 16:30:53.253812 == TX Byte 0 ==
7672 16:30:53.257109 u2DelayCellOfst[0]=14 cells (4 PI)
7673 16:30:53.260167 u2DelayCellOfst[1]=17 cells (5 PI)
7674 16:30:53.263493 u2DelayCellOfst[2]=10 cells (3 PI)
7675 16:30:53.267376 u2DelayCellOfst[3]=14 cells (4 PI)
7676 16:30:53.270369 u2DelayCellOfst[4]=10 cells (3 PI)
7677 16:30:53.273710 u2DelayCellOfst[5]=0 cells (0 PI)
7678 16:30:53.276891 u2DelayCellOfst[6]=17 cells (5 PI)
7679 16:30:53.280165 u2DelayCellOfst[7]=17 cells (5 PI)
7680 16:30:53.283509 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7681 16:30:53.289571 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7682 16:30:53.289654 == TX Byte 1 ==
7683 16:30:53.293242 u2DelayCellOfst[8]=0 cells (0 PI)
7684 16:30:53.296555 u2DelayCellOfst[9]=0 cells (0 PI)
7685 16:30:53.299876 u2DelayCellOfst[10]=3 cells (1 PI)
7686 16:30:53.303105 u2DelayCellOfst[11]=0 cells (0 PI)
7687 16:30:53.306634 u2DelayCellOfst[12]=7 cells (2 PI)
7688 16:30:53.309698 u2DelayCellOfst[13]=7 cells (2 PI)
7689 16:30:53.312943 u2DelayCellOfst[14]=10 cells (3 PI)
7690 16:30:53.313025 u2DelayCellOfst[15]=7 cells (2 PI)
7691 16:30:53.319413 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7692 16:30:53.322737 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7693 16:30:53.326015 DramC Write-DBI on
7694 16:30:53.326097 ==
7695 16:30:53.329184 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 16:30:53.332778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 16:30:53.332867 ==
7698 16:30:53.332932
7699 16:30:53.332992
7700 16:30:53.336133 TX Vref Scan disable
7701 16:30:53.336214 == TX Byte 0 ==
7702 16:30:53.342816 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7703 16:30:53.342897 == TX Byte 1 ==
7704 16:30:53.349032 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7705 16:30:53.349132 DramC Write-DBI off
7706 16:30:53.349224
7707 16:30:53.349335 [DATLAT]
7708 16:30:53.352435 Freq=1600, CH0 RK0
7709 16:30:53.352623
7710 16:30:53.356173 DATLAT Default: 0xf
7711 16:30:53.356255 0, 0xFFFF, sum = 0
7712 16:30:53.358756 1, 0xFFFF, sum = 0
7713 16:30:53.358841 2, 0xFFFF, sum = 0
7714 16:30:53.362535 3, 0xFFFF, sum = 0
7715 16:30:53.362619 4, 0xFFFF, sum = 0
7716 16:30:53.365780 5, 0xFFFF, sum = 0
7717 16:30:53.365865 6, 0xFFFF, sum = 0
7718 16:30:53.369205 7, 0xFFFF, sum = 0
7719 16:30:53.369354 8, 0xFFFF, sum = 0
7720 16:30:53.372329 9, 0xFFFF, sum = 0
7721 16:30:53.372412 10, 0xFFFF, sum = 0
7722 16:30:53.375385 11, 0xFFFF, sum = 0
7723 16:30:53.375467 12, 0xFFFF, sum = 0
7724 16:30:53.378608 13, 0xFFFF, sum = 0
7725 16:30:53.378706 14, 0x0, sum = 1
7726 16:30:53.381826 15, 0x0, sum = 2
7727 16:30:53.381908 16, 0x0, sum = 3
7728 16:30:53.385650 17, 0x0, sum = 4
7729 16:30:53.385732 best_step = 15
7730 16:30:53.385802
7731 16:30:53.385862 ==
7732 16:30:53.388711 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 16:30:53.395204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 16:30:53.395290 ==
7735 16:30:53.395355 RX Vref Scan: 1
7736 16:30:53.395414
7737 16:30:53.398914 Set Vref Range= 24 -> 127
7738 16:30:53.398995
7739 16:30:53.401859 RX Vref 24 -> 127, step: 1
7740 16:30:53.401940
7741 16:30:53.405155 RX Delay 11 -> 252, step: 4
7742 16:30:53.405250
7743 16:30:53.405341 Set Vref, RX VrefLevel [Byte0]: 24
7744 16:30:53.408443 [Byte1]: 24
7745 16:30:53.412944
7746 16:30:53.413028 Set Vref, RX VrefLevel [Byte0]: 25
7747 16:30:53.415940 [Byte1]: 25
7748 16:30:53.420550
7749 16:30:53.420632 Set Vref, RX VrefLevel [Byte0]: 26
7750 16:30:53.423734 [Byte1]: 26
7751 16:30:53.428340
7752 16:30:53.428420 Set Vref, RX VrefLevel [Byte0]: 27
7753 16:30:53.431631 [Byte1]: 27
7754 16:30:53.435528
7755 16:30:53.435609 Set Vref, RX VrefLevel [Byte0]: 28
7756 16:30:53.438815 [Byte1]: 28
7757 16:30:53.443229
7758 16:30:53.443309 Set Vref, RX VrefLevel [Byte0]: 29
7759 16:30:53.446911 [Byte1]: 29
7760 16:30:53.451213
7761 16:30:53.451294 Set Vref, RX VrefLevel [Byte0]: 30
7762 16:30:53.454336 [Byte1]: 30
7763 16:30:53.458575
7764 16:30:53.458655 Set Vref, RX VrefLevel [Byte0]: 31
7765 16:30:53.461769 [Byte1]: 31
7766 16:30:53.466392
7767 16:30:53.466472 Set Vref, RX VrefLevel [Byte0]: 32
7768 16:30:53.469391 [Byte1]: 32
7769 16:30:53.473878
7770 16:30:53.473960 Set Vref, RX VrefLevel [Byte0]: 33
7771 16:30:53.477179 [Byte1]: 33
7772 16:30:53.481484
7773 16:30:53.481580 Set Vref, RX VrefLevel [Byte0]: 34
7774 16:30:53.484557 [Byte1]: 34
7775 16:30:53.489219
7776 16:30:53.489350 Set Vref, RX VrefLevel [Byte0]: 35
7777 16:30:53.492672 [Byte1]: 35
7778 16:30:53.496480
7779 16:30:53.496563 Set Vref, RX VrefLevel [Byte0]: 36
7780 16:30:53.499783 [Byte1]: 36
7781 16:30:53.504497
7782 16:30:53.504575 Set Vref, RX VrefLevel [Byte0]: 37
7783 16:30:53.507614 [Byte1]: 37
7784 16:30:53.512118
7785 16:30:53.512198 Set Vref, RX VrefLevel [Byte0]: 38
7786 16:30:53.514939 [Byte1]: 38
7787 16:30:53.519642
7788 16:30:53.519720 Set Vref, RX VrefLevel [Byte0]: 39
7789 16:30:53.522923 [Byte1]: 39
7790 16:30:53.526860
7791 16:30:53.526946 Set Vref, RX VrefLevel [Byte0]: 40
7792 16:30:53.530638 [Byte1]: 40
7793 16:30:53.534615
7794 16:30:53.534698 Set Vref, RX VrefLevel [Byte0]: 41
7795 16:30:53.537967 [Byte1]: 41
7796 16:30:53.541937
7797 16:30:53.542055 Set Vref, RX VrefLevel [Byte0]: 42
7798 16:30:53.545451 [Byte1]: 42
7799 16:30:53.549940
7800 16:30:53.550057 Set Vref, RX VrefLevel [Byte0]: 43
7801 16:30:53.553190 [Byte1]: 43
7802 16:30:53.557630
7803 16:30:53.557715 Set Vref, RX VrefLevel [Byte0]: 44
7804 16:30:53.561010 [Byte1]: 44
7805 16:30:53.565055
7806 16:30:53.565165 Set Vref, RX VrefLevel [Byte0]: 45
7807 16:30:53.568488 [Byte1]: 45
7808 16:30:53.572540
7809 16:30:53.572624 Set Vref, RX VrefLevel [Byte0]: 46
7810 16:30:53.576346 [Byte1]: 46
7811 16:30:53.580125
7812 16:30:53.580207 Set Vref, RX VrefLevel [Byte0]: 47
7813 16:30:53.583559 [Byte1]: 47
7814 16:30:53.587568
7815 16:30:53.591003 Set Vref, RX VrefLevel [Byte0]: 48
7816 16:30:53.594641 [Byte1]: 48
7817 16:30:53.594726
7818 16:30:53.597413 Set Vref, RX VrefLevel [Byte0]: 49
7819 16:30:53.600863 [Byte1]: 49
7820 16:30:53.600969
7821 16:30:53.604130 Set Vref, RX VrefLevel [Byte0]: 50
7822 16:30:53.607453 [Byte1]: 50
7823 16:30:53.610858
7824 16:30:53.610973 Set Vref, RX VrefLevel [Byte0]: 51
7825 16:30:53.614046 [Byte1]: 51
7826 16:30:53.618484
7827 16:30:53.618592 Set Vref, RX VrefLevel [Byte0]: 52
7828 16:30:53.621832 [Byte1]: 52
7829 16:30:53.625783
7830 16:30:53.625891 Set Vref, RX VrefLevel [Byte0]: 53
7831 16:30:53.629269 [Byte1]: 53
7832 16:30:53.633843
7833 16:30:53.633961 Set Vref, RX VrefLevel [Byte0]: 54
7834 16:30:53.636712 [Byte1]: 54
7835 16:30:53.641375
7836 16:30:53.641459 Set Vref, RX VrefLevel [Byte0]: 55
7837 16:30:53.644563 [Byte1]: 55
7838 16:30:53.648736
7839 16:30:53.648846 Set Vref, RX VrefLevel [Byte0]: 56
7840 16:30:53.652029 [Byte1]: 56
7841 16:30:53.656594
7842 16:30:53.656705 Set Vref, RX VrefLevel [Byte0]: 57
7843 16:30:53.659657 [Byte1]: 57
7844 16:30:53.664056
7845 16:30:53.664140 Set Vref, RX VrefLevel [Byte0]: 58
7846 16:30:53.667340 [Byte1]: 58
7847 16:30:53.671870
7848 16:30:53.671953 Set Vref, RX VrefLevel [Byte0]: 59
7849 16:30:53.675160 [Byte1]: 59
7850 16:30:53.679101
7851 16:30:53.679184 Set Vref, RX VrefLevel [Byte0]: 60
7852 16:30:53.682790 [Byte1]: 60
7853 16:30:53.686670
7854 16:30:53.686754 Set Vref, RX VrefLevel [Byte0]: 61
7855 16:30:53.690018 [Byte1]: 61
7856 16:30:53.694435
7857 16:30:53.694517 Set Vref, RX VrefLevel [Byte0]: 62
7858 16:30:53.697709 [Byte1]: 62
7859 16:30:53.702045
7860 16:30:53.702128 Set Vref, RX VrefLevel [Byte0]: 63
7861 16:30:53.705659 [Byte1]: 63
7862 16:30:53.709826
7863 16:30:53.709908 Set Vref, RX VrefLevel [Byte0]: 64
7864 16:30:53.712855 [Byte1]: 64
7865 16:30:53.717336
7866 16:30:53.717446 Set Vref, RX VrefLevel [Byte0]: 65
7867 16:30:53.720392 [Byte1]: 65
7868 16:30:53.724786
7869 16:30:53.724864 Set Vref, RX VrefLevel [Byte0]: 66
7870 16:30:53.728036 [Byte1]: 66
7871 16:30:53.732446
7872 16:30:53.732530 Set Vref, RX VrefLevel [Byte0]: 67
7873 16:30:53.735617 [Byte1]: 67
7874 16:30:53.740406
7875 16:30:53.740490 Set Vref, RX VrefLevel [Byte0]: 68
7876 16:30:53.743692 [Byte1]: 68
7877 16:30:53.747509
7878 16:30:53.747592 Set Vref, RX VrefLevel [Byte0]: 69
7879 16:30:53.750817 [Byte1]: 69
7880 16:30:53.755332
7881 16:30:53.755427 Set Vref, RX VrefLevel [Byte0]: 70
7882 16:30:53.758479 [Byte1]: 70
7883 16:30:53.763074
7884 16:30:53.763152 Set Vref, RX VrefLevel [Byte0]: 71
7885 16:30:53.766175 [Byte1]: 71
7886 16:30:53.770501
7887 16:30:53.770577 Set Vref, RX VrefLevel [Byte0]: 72
7888 16:30:53.773740 [Byte1]: 72
7889 16:30:53.778396
7890 16:30:53.778468 Set Vref, RX VrefLevel [Byte0]: 73
7891 16:30:53.781647 [Byte1]: 73
7892 16:30:53.786142
7893 16:30:53.786214 Set Vref, RX VrefLevel [Byte0]: 74
7894 16:30:53.789486 [Byte1]: 74
7895 16:30:53.793292
7896 16:30:53.793365 Final RX Vref Byte 0 = 55 to rank0
7897 16:30:53.796458 Final RX Vref Byte 1 = 59 to rank0
7898 16:30:53.800344 Final RX Vref Byte 0 = 55 to rank1
7899 16:30:53.803662 Final RX Vref Byte 1 = 59 to rank1==
7900 16:30:53.806868 Dram Type= 6, Freq= 0, CH_0, rank 0
7901 16:30:53.813243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7902 16:30:53.813362 ==
7903 16:30:53.813433 DQS Delay:
7904 16:30:53.813502 DQS0 = 0, DQS1 = 0
7905 16:30:53.816375 DQM Delay:
7906 16:30:53.816450 DQM0 = 128, DQM1 = 124
7907 16:30:53.820132 DQ Delay:
7908 16:30:53.823109 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7909 16:30:53.826261 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =136
7910 16:30:53.829969 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7911 16:30:53.832892 DQ12 =132, DQ13 =128, DQ14 =132, DQ15 =132
7912 16:30:53.832980
7913 16:30:53.833051
7914 16:30:53.833121
7915 16:30:53.836546 [DramC_TX_OE_Calibration] TA2
7916 16:30:53.839503 Original DQ_B0 (3 6) =30, OEN = 27
7917 16:30:53.843080 Original DQ_B1 (3 6) =30, OEN = 27
7918 16:30:53.846486 24, 0x0, End_B0=24 End_B1=24
7919 16:30:53.846566 25, 0x0, End_B0=25 End_B1=25
7920 16:30:53.849511 26, 0x0, End_B0=26 End_B1=26
7921 16:30:53.852726 27, 0x0, End_B0=27 End_B1=27
7922 16:30:53.856101 28, 0x0, End_B0=28 End_B1=28
7923 16:30:53.859553 29, 0x0, End_B0=29 End_B1=29
7924 16:30:53.859638 30, 0x0, End_B0=30 End_B1=30
7925 16:30:53.863260 31, 0x4141, End_B0=30 End_B1=30
7926 16:30:53.866389 Byte0 end_step=30 best_step=27
7927 16:30:53.869669 Byte1 end_step=30 best_step=27
7928 16:30:53.872703 Byte0 TX OE(2T, 0.5T) = (3, 3)
7929 16:30:53.875776 Byte1 TX OE(2T, 0.5T) = (3, 3)
7930 16:30:53.875849
7931 16:30:53.875911
7932 16:30:53.882265 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7933 16:30:53.886164 CH0 RK0: MR19=303, MR18=1714
7934 16:30:53.892445 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7935 16:30:53.892524
7936 16:30:53.895641 ----->DramcWriteLeveling(PI) begin...
7937 16:30:53.895716 ==
7938 16:30:53.898785 Dram Type= 6, Freq= 0, CH_0, rank 1
7939 16:30:53.902659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7940 16:30:53.902759 ==
7941 16:30:53.905940 Write leveling (Byte 0): 35 => 35
7942 16:30:53.909177 Write leveling (Byte 1): 24 => 24
7943 16:30:53.912395 DramcWriteLeveling(PI) end<-----
7944 16:30:53.912485
7945 16:30:53.912549 ==
7946 16:30:53.915692 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 16:30:53.918734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 16:30:53.921835 ==
7949 16:30:53.921917 [Gating] SW mode calibration
7950 16:30:53.931935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7951 16:30:53.935540 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7952 16:30:53.938725 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7953 16:30:53.945530 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7954 16:30:53.948762 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7955 16:30:53.951845 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7956 16:30:53.958551 1 4 16 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
7957 16:30:53.961396 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 16:30:53.964906 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7959 16:30:53.971566 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7960 16:30:53.974667 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 16:30:53.977759 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7962 16:30:53.984587 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7963 16:30:53.987896 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7964 16:30:53.991095 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
7965 16:30:53.998079 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7966 16:30:54.001213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7967 16:30:54.004407 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 16:30:54.010763 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 16:30:54.014137 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7970 16:30:54.017433 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7971 16:30:54.024482 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7972 16:30:54.027752 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7973 16:30:54.031166 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 16:30:54.037458 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 16:30:54.040521 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 16:30:54.044263 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 16:30:54.050578 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7978 16:30:54.054266 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7979 16:30:54.057472 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7980 16:30:54.063983 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7981 16:30:54.067224 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 16:30:54.070055 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 16:30:54.077023 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 16:30:54.080002 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 16:30:54.083522 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 16:30:54.090372 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 16:30:54.093627 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 16:30:54.096300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 16:30:54.102901 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 16:30:54.106922 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 16:30:54.109968 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 16:30:54.116360 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 16:30:54.119598 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7994 16:30:54.122882 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7995 16:30:54.129597 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7996 16:30:54.132908 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7997 16:30:54.136168 Total UI for P1: 0, mck2ui 16
7998 16:30:54.139490 best dqsien dly found for B0: ( 1, 9, 8)
7999 16:30:54.142666 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8000 16:30:54.149686 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 16:30:54.152823 Total UI for P1: 0, mck2ui 16
8002 16:30:54.155850 best dqsien dly found for B1: ( 1, 9, 18)
8003 16:30:54.159489 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8004 16:30:54.162280 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8005 16:30:54.162362
8006 16:30:54.166074 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8007 16:30:54.169446 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8008 16:30:54.172675 [Gating] SW calibration Done
8009 16:30:54.172757 ==
8010 16:30:54.175813 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 16:30:54.178828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 16:30:54.178911 ==
8013 16:30:54.182141 RX Vref Scan: 0
8014 16:30:54.182222
8015 16:30:54.185279 RX Vref 0 -> 0, step: 1
8016 16:30:54.185376
8017 16:30:54.185441 RX Delay 0 -> 252, step: 8
8018 16:30:54.192257 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8019 16:30:54.195368 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8020 16:30:54.199031 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8021 16:30:54.202052 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8022 16:30:54.205539 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8023 16:30:54.212003 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8024 16:30:54.215149 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8025 16:30:54.218297 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8026 16:30:54.221529 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8027 16:30:54.225700 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8028 16:30:54.232119 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8029 16:30:54.235282 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8030 16:30:54.238497 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8031 16:30:54.241804 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8032 16:30:54.248169 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8033 16:30:54.251333 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8034 16:30:54.251448 ==
8035 16:30:54.254795 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 16:30:54.257913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 16:30:54.257996 ==
8038 16:30:54.261128 DQS Delay:
8039 16:30:54.261210 DQS0 = 0, DQS1 = 0
8040 16:30:54.261300 DQM Delay:
8041 16:30:54.264928 DQM0 = 131, DQM1 = 126
8042 16:30:54.265010 DQ Delay:
8043 16:30:54.267859 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8044 16:30:54.271056 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8045 16:30:54.277446 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8046 16:30:54.281218 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8047 16:30:54.281329
8048 16:30:54.281394
8049 16:30:54.281453 ==
8050 16:30:54.284323 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 16:30:54.287412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 16:30:54.287494 ==
8053 16:30:54.287559
8054 16:30:54.287619
8055 16:30:54.291179 TX Vref Scan disable
8056 16:30:54.294423 == TX Byte 0 ==
8057 16:30:54.297690 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8058 16:30:54.300904 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8059 16:30:54.304106 == TX Byte 1 ==
8060 16:30:54.307431 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8061 16:30:54.310787 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8062 16:30:54.310869 ==
8063 16:30:54.314061 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 16:30:54.320263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 16:30:54.320377 ==
8066 16:30:54.333054
8067 16:30:54.336206 TX Vref early break, caculate TX vref
8068 16:30:54.339331 TX Vref=16, minBit 8, minWin=22, winSum=377
8069 16:30:54.342685 TX Vref=18, minBit 8, minWin=23, winSum=387
8070 16:30:54.346045 TX Vref=20, minBit 2, minWin=24, winSum=394
8071 16:30:54.349817 TX Vref=22, minBit 10, minWin=24, winSum=402
8072 16:30:54.352942 TX Vref=24, minBit 1, minWin=25, winSum=409
8073 16:30:54.359357 TX Vref=26, minBit 1, minWin=25, winSum=415
8074 16:30:54.362631 TX Vref=28, minBit 4, minWin=25, winSum=416
8075 16:30:54.365760 TX Vref=30, minBit 1, minWin=25, winSum=409
8076 16:30:54.368939 TX Vref=32, minBit 0, minWin=24, winSum=404
8077 16:30:54.372101 TX Vref=34, minBit 0, minWin=24, winSum=392
8078 16:30:54.378745 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
8079 16:30:54.378832
8080 16:30:54.382024 Final TX Range 0 Vref 28
8081 16:30:54.382108
8082 16:30:54.382205 ==
8083 16:30:54.385713 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 16:30:54.388687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 16:30:54.388772 ==
8086 16:30:54.388838
8087 16:30:54.391705
8088 16:30:54.391787 TX Vref Scan disable
8089 16:30:54.398528 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8090 16:30:54.398613 == TX Byte 0 ==
8091 16:30:54.401716 u2DelayCellOfst[0]=10 cells (3 PI)
8092 16:30:54.404881 u2DelayCellOfst[1]=14 cells (4 PI)
8093 16:30:54.408755 u2DelayCellOfst[2]=7 cells (2 PI)
8094 16:30:54.411440 u2DelayCellOfst[3]=10 cells (3 PI)
8095 16:30:54.415252 u2DelayCellOfst[4]=7 cells (2 PI)
8096 16:30:54.418562 u2DelayCellOfst[5]=0 cells (0 PI)
8097 16:30:54.421807 u2DelayCellOfst[6]=14 cells (4 PI)
8098 16:30:54.425109 u2DelayCellOfst[7]=14 cells (4 PI)
8099 16:30:54.428301 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8100 16:30:54.431633 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8101 16:30:54.434667 == TX Byte 1 ==
8102 16:30:54.438185 u2DelayCellOfst[8]=3 cells (1 PI)
8103 16:30:54.441109 u2DelayCellOfst[9]=0 cells (0 PI)
8104 16:30:54.444441 u2DelayCellOfst[10]=7 cells (2 PI)
8105 16:30:54.447706 u2DelayCellOfst[11]=3 cells (1 PI)
8106 16:30:54.451346 u2DelayCellOfst[12]=10 cells (3 PI)
8107 16:30:54.454275 u2DelayCellOfst[13]=10 cells (3 PI)
8108 16:30:54.457664 u2DelayCellOfst[14]=14 cells (4 PI)
8109 16:30:54.457765 u2DelayCellOfst[15]=14 cells (4 PI)
8110 16:30:54.464182 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8111 16:30:54.467489 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8112 16:30:54.470810 DramC Write-DBI on
8113 16:30:54.470894 ==
8114 16:30:54.474071 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 16:30:54.477408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 16:30:54.477522 ==
8117 16:30:54.477587
8118 16:30:54.477647
8119 16:30:54.481081 TX Vref Scan disable
8120 16:30:54.481180 == TX Byte 0 ==
8121 16:30:54.487708 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8122 16:30:54.487810 == TX Byte 1 ==
8123 16:30:54.490876 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8124 16:30:54.493944 DramC Write-DBI off
8125 16:30:54.494030
8126 16:30:54.494096 [DATLAT]
8127 16:30:54.497493 Freq=1600, CH0 RK1
8128 16:30:54.497576
8129 16:30:54.497642 DATLAT Default: 0xf
8130 16:30:54.500552 0, 0xFFFF, sum = 0
8131 16:30:54.503763 1, 0xFFFF, sum = 0
8132 16:30:54.503850 2, 0xFFFF, sum = 0
8133 16:30:54.507559 3, 0xFFFF, sum = 0
8134 16:30:54.507646 4, 0xFFFF, sum = 0
8135 16:30:54.510751 5, 0xFFFF, sum = 0
8136 16:30:54.510841 6, 0xFFFF, sum = 0
8137 16:30:54.514084 7, 0xFFFF, sum = 0
8138 16:30:54.514170 8, 0xFFFF, sum = 0
8139 16:30:54.517407 9, 0xFFFF, sum = 0
8140 16:30:54.517508 10, 0xFFFF, sum = 0
8141 16:30:54.520578 11, 0xFFFF, sum = 0
8142 16:30:54.520664 12, 0xFFFF, sum = 0
8143 16:30:54.523637 13, 0xFFFF, sum = 0
8144 16:30:54.523737 14, 0x0, sum = 1
8145 16:30:54.527520 15, 0x0, sum = 2
8146 16:30:54.527635 16, 0x0, sum = 3
8147 16:30:54.530764 17, 0x0, sum = 4
8148 16:30:54.530849 best_step = 15
8149 16:30:54.530915
8150 16:30:54.530976 ==
8151 16:30:54.533467 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 16:30:54.540582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 16:30:54.540668 ==
8154 16:30:54.540735 RX Vref Scan: 0
8155 16:30:54.540797
8156 16:30:54.543771 RX Vref 0 -> 0, step: 1
8157 16:30:54.543854
8158 16:30:54.546940 RX Delay 11 -> 252, step: 4
8159 16:30:54.550163 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8160 16:30:54.553822 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8161 16:30:54.556856 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8162 16:30:54.563340 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8163 16:30:54.566556 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8164 16:30:54.570202 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8165 16:30:54.573583 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8166 16:30:54.576560 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8167 16:30:54.583526 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8168 16:30:54.586499 iDelay=191, Bit 9, Center 108 (55 ~ 162) 108
8169 16:30:54.589789 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8170 16:30:54.593016 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8171 16:30:54.596555 iDelay=191, Bit 12, Center 126 (71 ~ 182) 112
8172 16:30:54.603049 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8173 16:30:54.606854 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8174 16:30:54.609996 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8175 16:30:54.610109 ==
8176 16:30:54.613277 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 16:30:54.616512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 16:30:54.619852 ==
8179 16:30:54.619976 DQS Delay:
8180 16:30:54.620078 DQS0 = 0, DQS1 = 0
8181 16:30:54.623020 DQM Delay:
8182 16:30:54.623106 DQM0 = 128, DQM1 = 123
8183 16:30:54.626249 DQ Delay:
8184 16:30:54.629450 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8185 16:30:54.632567 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8186 16:30:54.635933 DQ8 =114, DQ9 =108, DQ10 =126, DQ11 =118
8187 16:30:54.639238 DQ12 =126, DQ13 =130, DQ14 =136, DQ15 =130
8188 16:30:54.639325
8189 16:30:54.639412
8190 16:30:54.639529
8191 16:30:54.643001 [DramC_TX_OE_Calibration] TA2
8192 16:30:54.646319 Original DQ_B0 (3 6) =30, OEN = 27
8193 16:30:54.649557 Original DQ_B1 (3 6) =30, OEN = 27
8194 16:30:54.652731 24, 0x0, End_B0=24 End_B1=24
8195 16:30:54.652844 25, 0x0, End_B0=25 End_B1=25
8196 16:30:54.655946 26, 0x0, End_B0=26 End_B1=26
8197 16:30:54.659196 27, 0x0, End_B0=27 End_B1=27
8198 16:30:54.662423 28, 0x0, End_B0=28 End_B1=28
8199 16:30:54.665853 29, 0x0, End_B0=29 End_B1=29
8200 16:30:54.665968 30, 0x0, End_B0=30 End_B1=30
8201 16:30:54.669107 31, 0x4141, End_B0=30 End_B1=30
8202 16:30:54.672276 Byte0 end_step=30 best_step=27
8203 16:30:54.676033 Byte1 end_step=30 best_step=27
8204 16:30:54.678960 Byte0 TX OE(2T, 0.5T) = (3, 3)
8205 16:30:54.682379 Byte1 TX OE(2T, 0.5T) = (3, 3)
8206 16:30:54.682457
8207 16:30:54.682519
8208 16:30:54.689029 [DQSOSCAuto] RK1, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
8209 16:30:54.692346 CH0 RK1: MR19=303, MR18=1613
8210 16:30:54.698931 CH0_RK1: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
8211 16:30:54.702253 [RxdqsGatingPostProcess] freq 1600
8212 16:30:54.705385 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8213 16:30:54.708447 best DQS0 dly(2T, 0.5T) = (1, 1)
8214 16:30:54.711893 best DQS1 dly(2T, 0.5T) = (1, 1)
8215 16:30:54.715315 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8216 16:30:54.718622 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8217 16:30:54.722055 best DQS0 dly(2T, 0.5T) = (1, 1)
8218 16:30:54.724899 best DQS1 dly(2T, 0.5T) = (1, 1)
8219 16:30:54.728711 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8220 16:30:54.731804 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8221 16:30:54.735190 Pre-setting of DQS Precalculation
8222 16:30:54.738497 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8223 16:30:54.738600 ==
8224 16:30:54.741611 Dram Type= 6, Freq= 0, CH_1, rank 0
8225 16:30:54.748054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 16:30:54.748162 ==
8227 16:30:54.751536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8228 16:30:54.757665 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8229 16:30:54.761165 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8230 16:30:54.767438 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8231 16:30:54.775872 [CA 0] Center 42 (12~72) winsize 61
8232 16:30:54.779116 [CA 1] Center 42 (13~72) winsize 60
8233 16:30:54.782442 [CA 2] Center 38 (9~68) winsize 60
8234 16:30:54.785537 [CA 3] Center 37 (8~67) winsize 60
8235 16:30:54.788792 [CA 4] Center 38 (8~68) winsize 61
8236 16:30:54.792062 [CA 5] Center 37 (7~67) winsize 61
8237 16:30:54.792167
8238 16:30:54.794980 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8239 16:30:54.795085
8240 16:30:54.802041 [CATrainingPosCal] consider 1 rank data
8241 16:30:54.802147 u2DelayCellTimex100 = 275/100 ps
8242 16:30:54.808193 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8243 16:30:54.811834 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8244 16:30:54.814825 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8245 16:30:54.818548 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8246 16:30:54.821521 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8247 16:30:54.824935 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8248 16:30:54.825040
8249 16:30:54.827946 CA PerBit enable=1, Macro0, CA PI delay=37
8250 16:30:54.828049
8251 16:30:54.831430 [CBTSetCACLKResult] CA Dly = 37
8252 16:30:54.835031 CS Dly: 7 (0~38)
8253 16:30:54.838071 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8254 16:30:54.841311 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8255 16:30:54.841409 ==
8256 16:30:54.845074 Dram Type= 6, Freq= 0, CH_1, rank 1
8257 16:30:54.851078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 16:30:54.851162 ==
8259 16:30:54.854343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8260 16:30:54.861565 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8261 16:30:54.864762 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8262 16:30:54.871247 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8263 16:30:54.878955 [CA 0] Center 41 (12~71) winsize 60
8264 16:30:54.882307 [CA 1] Center 42 (13~71) winsize 59
8265 16:30:54.885434 [CA 2] Center 37 (8~67) winsize 60
8266 16:30:54.888705 [CA 3] Center 36 (7~65) winsize 59
8267 16:30:54.891901 [CA 4] Center 37 (7~67) winsize 61
8268 16:30:54.895596 [CA 5] Center 36 (7~65) winsize 59
8269 16:30:54.895698
8270 16:30:54.898754 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8271 16:30:54.898833
8272 16:30:54.902018 [CATrainingPosCal] consider 2 rank data
8273 16:30:54.905190 u2DelayCellTimex100 = 275/100 ps
8274 16:30:54.908301 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8275 16:30:54.914885 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8276 16:30:54.918363 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8277 16:30:54.921774 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8278 16:30:54.924704 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8279 16:30:54.928242 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8280 16:30:54.928339
8281 16:30:54.931240 CA PerBit enable=1, Macro0, CA PI delay=36
8282 16:30:54.931324
8283 16:30:54.934841 [CBTSetCACLKResult] CA Dly = 36
8284 16:30:54.938283 CS Dly: 9 (0~42)
8285 16:30:54.941420 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8286 16:30:54.944367 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8287 16:30:54.944449
8288 16:30:54.947841 ----->DramcWriteLeveling(PI) begin...
8289 16:30:54.947924 ==
8290 16:30:54.951547 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 16:30:54.957931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 16:30:54.958027 ==
8293 16:30:54.961204 Write leveling (Byte 0): 25 => 25
8294 16:30:54.964369 Write leveling (Byte 1): 27 => 27
8295 16:30:54.964479 DramcWriteLeveling(PI) end<-----
8296 16:30:54.964578
8297 16:30:54.967490 ==
8298 16:30:54.971392 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 16:30:54.974411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 16:30:54.974492 ==
8301 16:30:54.977585 [Gating] SW mode calibration
8302 16:30:54.984655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8303 16:30:54.987832 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8304 16:30:54.994223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8305 16:30:54.997279 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 16:30:55.000395 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 16:30:55.007373 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8308 16:30:55.010662 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8309 16:30:55.013988 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 16:30:55.020827 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 16:30:55.023763 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 16:30:55.026801 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 16:30:55.033287 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 16:30:55.036825 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8315 16:30:55.040085 1 5 12 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 1)
8316 16:30:55.047089 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 16:30:55.050084 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 16:30:55.053569 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 16:30:55.060186 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 16:30:55.062915 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 16:30:55.066623 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 16:30:55.073379 1 6 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8323 16:30:55.076744 1 6 12 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
8324 16:30:55.079977 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 16:30:55.086519 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 16:30:55.089791 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 16:30:55.092694 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 16:30:55.099222 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 16:30:55.103012 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 16:30:55.106115 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 16:30:55.112363 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8332 16:30:55.115776 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8333 16:30:55.118982 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 16:30:55.126018 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 16:30:55.128923 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 16:30:55.132372 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 16:30:55.139339 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 16:30:55.142240 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 16:30:55.145678 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 16:30:55.152056 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 16:30:55.155508 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 16:30:55.158566 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 16:30:55.165348 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 16:30:55.169117 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 16:30:55.172269 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 16:30:55.178506 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8347 16:30:55.181875 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8348 16:30:55.185163 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8349 16:30:55.188482 Total UI for P1: 0, mck2ui 16
8350 16:30:55.192402 best dqsien dly found for B0: ( 1, 9, 10)
8351 16:30:55.198887 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 16:30:55.201918 Total UI for P1: 0, mck2ui 16
8353 16:30:55.204893 best dqsien dly found for B1: ( 1, 9, 14)
8354 16:30:55.208463 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8355 16:30:55.211565 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8356 16:30:55.211666
8357 16:30:55.214851 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8358 16:30:55.218051 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8359 16:30:55.221348 [Gating] SW calibration Done
8360 16:30:55.221434 ==
8361 16:30:55.224698 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 16:30:55.228414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 16:30:55.228496 ==
8364 16:30:55.231608 RX Vref Scan: 0
8365 16:30:55.231714
8366 16:30:55.234654 RX Vref 0 -> 0, step: 1
8367 16:30:55.234733
8368 16:30:55.234818 RX Delay 0 -> 252, step: 8
8369 16:30:55.241350 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8370 16:30:55.244707 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8371 16:30:55.247746 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8372 16:30:55.250853 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8373 16:30:55.254402 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8374 16:30:55.261086 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8375 16:30:55.264180 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8376 16:30:55.267331 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8377 16:30:55.271121 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8378 16:30:55.273870 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8379 16:30:55.280763 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8380 16:30:55.283886 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8381 16:30:55.287627 iDelay=200, Bit 12, Center 143 (96 ~ 191) 96
8382 16:30:55.290718 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8383 16:30:55.297596 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8384 16:30:55.300669 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8385 16:30:55.300782 ==
8386 16:30:55.303766 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 16:30:55.306946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 16:30:55.307050 ==
8389 16:30:55.310162 DQS Delay:
8390 16:30:55.310269 DQS0 = 0, DQS1 = 0
8391 16:30:55.310345 DQM Delay:
8392 16:30:55.313699 DQM0 = 135, DQM1 = 132
8393 16:30:55.313815 DQ Delay:
8394 16:30:55.316916 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8395 16:30:55.320149 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8396 16:30:55.327156 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8397 16:30:55.330517 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8398 16:30:55.330633
8399 16:30:55.330729
8400 16:30:55.330818 ==
8401 16:30:55.333445 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 16:30:55.336649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 16:30:55.336728 ==
8404 16:30:55.336822
8405 16:30:55.336911
8406 16:30:55.339926 TX Vref Scan disable
8407 16:30:55.342936 == TX Byte 0 ==
8408 16:30:55.346695 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8409 16:30:55.350049 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8410 16:30:55.353353 == TX Byte 1 ==
8411 16:30:55.356435 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8412 16:30:55.360094 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8413 16:30:55.360180 ==
8414 16:30:55.363013 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 16:30:55.366113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 16:30:55.369276 ==
8417 16:30:55.380643
8418 16:30:55.383696 TX Vref early break, caculate TX vref
8419 16:30:55.386959 TX Vref=16, minBit 8, minWin=21, winSum=367
8420 16:30:55.390727 TX Vref=18, minBit 9, minWin=22, winSum=377
8421 16:30:55.393869 TX Vref=20, minBit 8, minWin=23, winSum=388
8422 16:30:55.397061 TX Vref=22, minBit 8, minWin=23, winSum=394
8423 16:30:55.400261 TX Vref=24, minBit 8, minWin=23, winSum=406
8424 16:30:55.406989 TX Vref=26, minBit 3, minWin=25, winSum=416
8425 16:30:55.409936 TX Vref=28, minBit 11, minWin=25, winSum=420
8426 16:30:55.413358 TX Vref=30, minBit 9, minWin=24, winSum=414
8427 16:30:55.416742 TX Vref=32, minBit 0, minWin=24, winSum=405
8428 16:30:55.420366 TX Vref=34, minBit 11, minWin=23, winSum=397
8429 16:30:55.426740 [TxChooseVref] Worse bit 11, Min win 25, Win sum 420, Final Vref 28
8430 16:30:55.426860
8431 16:30:55.429997 Final TX Range 0 Vref 28
8432 16:30:55.430074
8433 16:30:55.430149 ==
8434 16:30:55.433311 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 16:30:55.436494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 16:30:55.436579 ==
8437 16:30:55.436644
8438 16:30:55.439670
8439 16:30:55.439751 TX Vref Scan disable
8440 16:30:55.446719 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8441 16:30:55.446807 == TX Byte 0 ==
8442 16:30:55.449804 u2DelayCellOfst[0]=14 cells (4 PI)
8443 16:30:55.452974 u2DelayCellOfst[1]=10 cells (3 PI)
8444 16:30:55.456433 u2DelayCellOfst[2]=0 cells (0 PI)
8445 16:30:55.459579 u2DelayCellOfst[3]=7 cells (2 PI)
8446 16:30:55.463210 u2DelayCellOfst[4]=10 cells (3 PI)
8447 16:30:55.466456 u2DelayCellOfst[5]=14 cells (4 PI)
8448 16:30:55.470768 u2DelayCellOfst[6]=14 cells (4 PI)
8449 16:30:55.472739 u2DelayCellOfst[7]=7 cells (2 PI)
8450 16:30:55.476323 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8451 16:30:55.479885 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8452 16:30:55.482781 == TX Byte 1 ==
8453 16:30:55.486262 u2DelayCellOfst[8]=0 cells (0 PI)
8454 16:30:55.489610 u2DelayCellOfst[9]=3 cells (1 PI)
8455 16:30:55.489734 u2DelayCellOfst[10]=7 cells (2 PI)
8456 16:30:55.492596 u2DelayCellOfst[11]=3 cells (1 PI)
8457 16:30:55.495970 u2DelayCellOfst[12]=10 cells (3 PI)
8458 16:30:55.499064 u2DelayCellOfst[13]=14 cells (4 PI)
8459 16:30:55.502896 u2DelayCellOfst[14]=14 cells (4 PI)
8460 16:30:55.505947 u2DelayCellOfst[15]=14 cells (4 PI)
8461 16:30:55.512537 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8462 16:30:55.516203 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 16:30:55.516314 DramC Write-DBI on
8464 16:30:55.516384 ==
8465 16:30:55.519271 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 16:30:55.525579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 16:30:55.525682 ==
8468 16:30:55.525751
8469 16:30:55.525812
8470 16:30:55.528692 TX Vref Scan disable
8471 16:30:55.528789 == TX Byte 0 ==
8472 16:30:55.535414 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8473 16:30:55.535563 == TX Byte 1 ==
8474 16:30:55.539120 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8475 16:30:55.542368 DramC Write-DBI off
8476 16:30:55.542513
8477 16:30:55.542585 [DATLAT]
8478 16:30:55.545572 Freq=1600, CH1 RK0
8479 16:30:55.545717
8480 16:30:55.545787 DATLAT Default: 0xf
8481 16:30:55.548753 0, 0xFFFF, sum = 0
8482 16:30:55.548878 1, 0xFFFF, sum = 0
8483 16:30:55.551952 2, 0xFFFF, sum = 0
8484 16:30:55.552072 3, 0xFFFF, sum = 0
8485 16:30:55.555378 4, 0xFFFF, sum = 0
8486 16:30:55.555526 5, 0xFFFF, sum = 0
8487 16:30:55.558369 6, 0xFFFF, sum = 0
8488 16:30:55.562040 7, 0xFFFF, sum = 0
8489 16:30:55.562175 8, 0xFFFF, sum = 0
8490 16:30:55.564870 9, 0xFFFF, sum = 0
8491 16:30:55.564962 10, 0xFFFF, sum = 0
8492 16:30:55.568423 11, 0xFFFF, sum = 0
8493 16:30:55.568532 12, 0xFFFF, sum = 0
8494 16:30:55.571547 13, 0xFFFF, sum = 0
8495 16:30:55.571650 14, 0x0, sum = 1
8496 16:30:55.574896 15, 0x0, sum = 2
8497 16:30:55.574998 16, 0x0, sum = 3
8498 16:30:55.578573 17, 0x0, sum = 4
8499 16:30:55.578676 best_step = 15
8500 16:30:55.578744
8501 16:30:55.578830 ==
8502 16:30:55.581897 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 16:30:55.584914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 16:30:55.588025 ==
8505 16:30:55.588143 RX Vref Scan: 1
8506 16:30:55.588214
8507 16:30:55.591721 Set Vref Range= 24 -> 127
8508 16:30:55.591834
8509 16:30:55.594489 RX Vref 24 -> 127, step: 1
8510 16:30:55.594568
8511 16:30:55.594633 RX Delay 19 -> 252, step: 4
8512 16:30:55.594697
8513 16:30:55.597933 Set Vref, RX VrefLevel [Byte0]: 24
8514 16:30:55.601655 [Byte1]: 24
8515 16:30:55.605146
8516 16:30:55.605293 Set Vref, RX VrefLevel [Byte0]: 25
8517 16:30:55.608552 [Byte1]: 25
8518 16:30:55.613029
8519 16:30:55.613189 Set Vref, RX VrefLevel [Byte0]: 26
8520 16:30:55.616196 [Byte1]: 26
8521 16:30:55.620125
8522 16:30:55.620249 Set Vref, RX VrefLevel [Byte0]: 27
8523 16:30:55.623397 [Byte1]: 27
8524 16:30:55.627696
8525 16:30:55.627794 Set Vref, RX VrefLevel [Byte0]: 28
8526 16:30:55.631577 [Byte1]: 28
8527 16:30:55.635709
8528 16:30:55.635804 Set Vref, RX VrefLevel [Byte0]: 29
8529 16:30:55.638568 [Byte1]: 29
8530 16:30:55.642972
8531 16:30:55.643083 Set Vref, RX VrefLevel [Byte0]: 30
8532 16:30:55.646237 [Byte1]: 30
8533 16:30:55.650687
8534 16:30:55.650852 Set Vref, RX VrefLevel [Byte0]: 31
8535 16:30:55.653896 [Byte1]: 31
8536 16:30:55.657868
8537 16:30:55.658009 Set Vref, RX VrefLevel [Byte0]: 32
8538 16:30:55.661506 [Byte1]: 32
8539 16:30:55.665391
8540 16:30:55.665532 Set Vref, RX VrefLevel [Byte0]: 33
8541 16:30:55.669000 [Byte1]: 33
8542 16:30:55.673199
8543 16:30:55.673301 Set Vref, RX VrefLevel [Byte0]: 34
8544 16:30:55.676301 [Byte1]: 34
8545 16:30:55.680700
8546 16:30:55.680819 Set Vref, RX VrefLevel [Byte0]: 35
8547 16:30:55.683900 [Byte1]: 35
8548 16:30:55.688834
8549 16:30:55.688955 Set Vref, RX VrefLevel [Byte0]: 36
8550 16:30:55.691950 [Byte1]: 36
8551 16:30:55.695763
8552 16:30:55.695855 Set Vref, RX VrefLevel [Byte0]: 37
8553 16:30:55.699546 [Byte1]: 37
8554 16:30:55.703746
8555 16:30:55.703835 Set Vref, RX VrefLevel [Byte0]: 38
8556 16:30:55.706579 [Byte1]: 38
8557 16:30:55.710848
8558 16:30:55.710971 Set Vref, RX VrefLevel [Byte0]: 39
8559 16:30:55.714306 [Byte1]: 39
8560 16:30:55.718559
8561 16:30:55.718674 Set Vref, RX VrefLevel [Byte0]: 40
8562 16:30:55.721723 [Byte1]: 40
8563 16:30:55.726328
8564 16:30:55.726436 Set Vref, RX VrefLevel [Byte0]: 41
8565 16:30:55.729531 [Byte1]: 41
8566 16:30:55.734084
8567 16:30:55.734247 Set Vref, RX VrefLevel [Byte0]: 42
8568 16:30:55.737415 [Byte1]: 42
8569 16:30:55.741178
8570 16:30:55.741323 Set Vref, RX VrefLevel [Byte0]: 43
8571 16:30:55.744919 [Byte1]: 43
8572 16:30:55.749166
8573 16:30:55.749290 Set Vref, RX VrefLevel [Byte0]: 44
8574 16:30:55.751988 [Byte1]: 44
8575 16:30:55.756493
8576 16:30:55.756607 Set Vref, RX VrefLevel [Byte0]: 45
8577 16:30:55.760021 [Byte1]: 45
8578 16:30:55.764100
8579 16:30:55.764230 Set Vref, RX VrefLevel [Byte0]: 46
8580 16:30:55.767332 [Byte1]: 46
8581 16:30:55.771906
8582 16:30:55.772038 Set Vref, RX VrefLevel [Byte0]: 47
8583 16:30:55.774833 [Byte1]: 47
8584 16:30:55.779166
8585 16:30:55.779266 Set Vref, RX VrefLevel [Byte0]: 48
8586 16:30:55.782830 [Byte1]: 48
8587 16:30:55.787147
8588 16:30:55.787302 Set Vref, RX VrefLevel [Byte0]: 49
8589 16:30:55.790385 [Byte1]: 49
8590 16:30:55.794645
8591 16:30:55.794748 Set Vref, RX VrefLevel [Byte0]: 50
8592 16:30:55.797904 [Byte1]: 50
8593 16:30:55.802453
8594 16:30:55.802585 Set Vref, RX VrefLevel [Byte0]: 51
8595 16:30:55.805703 [Byte1]: 51
8596 16:30:55.809390
8597 16:30:55.809528 Set Vref, RX VrefLevel [Byte0]: 52
8598 16:30:55.812538 [Byte1]: 52
8599 16:30:55.816867
8600 16:30:55.817000 Set Vref, RX VrefLevel [Byte0]: 53
8601 16:30:55.820524 [Byte1]: 53
8602 16:30:55.824612
8603 16:30:55.824732 Set Vref, RX VrefLevel [Byte0]: 54
8604 16:30:55.828460 [Byte1]: 54
8605 16:30:55.832138
8606 16:30:55.832269 Set Vref, RX VrefLevel [Byte0]: 55
8607 16:30:55.835333 [Byte1]: 55
8608 16:30:55.839857
8609 16:30:55.840003 Set Vref, RX VrefLevel [Byte0]: 56
8610 16:30:55.843084 [Byte1]: 56
8611 16:30:55.847594
8612 16:30:55.847687 Set Vref, RX VrefLevel [Byte0]: 57
8613 16:30:55.850582 [Byte1]: 57
8614 16:30:55.854989
8615 16:30:55.855107 Set Vref, RX VrefLevel [Byte0]: 58
8616 16:30:55.858154 [Byte1]: 58
8617 16:30:55.862528
8618 16:30:55.862627 Set Vref, RX VrefLevel [Byte0]: 59
8619 16:30:55.865927 [Byte1]: 59
8620 16:30:55.870381
8621 16:30:55.870473 Set Vref, RX VrefLevel [Byte0]: 60
8622 16:30:55.873504 [Byte1]: 60
8623 16:30:55.878042
8624 16:30:55.878158 Set Vref, RX VrefLevel [Byte0]: 61
8625 16:30:55.881031 [Byte1]: 61
8626 16:30:55.885358
8627 16:30:55.885476 Set Vref, RX VrefLevel [Byte0]: 62
8628 16:30:55.888407 [Byte1]: 62
8629 16:30:55.893311
8630 16:30:55.893433 Set Vref, RX VrefLevel [Byte0]: 63
8631 16:30:55.895776 [Byte1]: 63
8632 16:30:55.900427
8633 16:30:55.900535 Set Vref, RX VrefLevel [Byte0]: 64
8634 16:30:55.903505 [Byte1]: 64
8635 16:30:55.907808
8636 16:30:55.907887 Set Vref, RX VrefLevel [Byte0]: 65
8637 16:30:55.911159 [Byte1]: 65
8638 16:30:55.915558
8639 16:30:55.915648 Set Vref, RX VrefLevel [Byte0]: 66
8640 16:30:55.918938 [Byte1]: 66
8641 16:30:55.923354
8642 16:30:55.923447 Set Vref, RX VrefLevel [Byte0]: 67
8643 16:30:55.926446 [Byte1]: 67
8644 16:30:55.930524
8645 16:30:55.930617 Set Vref, RX VrefLevel [Byte0]: 68
8646 16:30:55.934249 [Byte1]: 68
8647 16:30:55.938653
8648 16:30:55.938743 Set Vref, RX VrefLevel [Byte0]: 69
8649 16:30:55.941722 [Byte1]: 69
8650 16:30:55.945631
8651 16:30:55.945720 Set Vref, RX VrefLevel [Byte0]: 70
8652 16:30:55.949445 [Byte1]: 70
8653 16:30:55.953284
8654 16:30:55.953403 Set Vref, RX VrefLevel [Byte0]: 71
8655 16:30:55.956443 [Byte1]: 71
8656 16:30:55.960951
8657 16:30:55.961038 Final RX Vref Byte 0 = 54 to rank0
8658 16:30:55.964238 Final RX Vref Byte 1 = 61 to rank0
8659 16:30:55.967371 Final RX Vref Byte 0 = 54 to rank1
8660 16:30:55.971116 Final RX Vref Byte 1 = 61 to rank1==
8661 16:30:55.974130 Dram Type= 6, Freq= 0, CH_1, rank 0
8662 16:30:55.980606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8663 16:30:55.980725 ==
8664 16:30:55.980822 DQS Delay:
8665 16:30:55.983957 DQS0 = 0, DQS1 = 0
8666 16:30:55.984047 DQM Delay:
8667 16:30:55.987228 DQM0 = 132, DQM1 = 129
8668 16:30:55.987316 DQ Delay:
8669 16:30:55.990727 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8670 16:30:55.993751 DQ4 =126, DQ5 =142, DQ6 =146, DQ7 =126
8671 16:30:55.997289 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =122
8672 16:30:56.000320 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8673 16:30:56.000408
8674 16:30:56.000474
8675 16:30:56.000535
8676 16:30:56.003646 [DramC_TX_OE_Calibration] TA2
8677 16:30:56.007499 Original DQ_B0 (3 6) =30, OEN = 27
8678 16:30:56.010659 Original DQ_B1 (3 6) =30, OEN = 27
8679 16:30:56.013799 24, 0x0, End_B0=24 End_B1=24
8680 16:30:56.017278 25, 0x0, End_B0=25 End_B1=25
8681 16:30:56.017373 26, 0x0, End_B0=26 End_B1=26
8682 16:30:56.020351 27, 0x0, End_B0=27 End_B1=27
8683 16:30:56.023884 28, 0x0, End_B0=28 End_B1=28
8684 16:30:56.026731 29, 0x0, End_B0=29 End_B1=29
8685 16:30:56.026822 30, 0x0, End_B0=30 End_B1=30
8686 16:30:56.030245 31, 0x5151, End_B0=30 End_B1=30
8687 16:30:56.033202 Byte0 end_step=30 best_step=27
8688 16:30:56.037003 Byte1 end_step=30 best_step=27
8689 16:30:56.040038 Byte0 TX OE(2T, 0.5T) = (3, 3)
8690 16:30:56.043414 Byte1 TX OE(2T, 0.5T) = (3, 3)
8691 16:30:56.043528
8692 16:30:56.043617
8693 16:30:56.049908 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8694 16:30:56.053049 CH1 RK0: MR19=303, MR18=C16
8695 16:30:56.059393 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8696 16:30:56.059491
8697 16:30:56.063202 ----->DramcWriteLeveling(PI) begin...
8698 16:30:56.063292 ==
8699 16:30:56.066391 Dram Type= 6, Freq= 0, CH_1, rank 1
8700 16:30:56.069664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8701 16:30:56.069781 ==
8702 16:30:56.072704 Write leveling (Byte 0): 24 => 24
8703 16:30:56.075973 Write leveling (Byte 1): 26 => 26
8704 16:30:56.079402 DramcWriteLeveling(PI) end<-----
8705 16:30:56.079493
8706 16:30:56.079561 ==
8707 16:30:56.082596 Dram Type= 6, Freq= 0, CH_1, rank 1
8708 16:30:56.089083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8709 16:30:56.089204 ==
8710 16:30:56.089315 [Gating] SW mode calibration
8711 16:30:56.099128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8712 16:30:56.102291 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8713 16:30:56.106077 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8714 16:30:56.112726 1 4 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8715 16:30:56.115933 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8716 16:30:56.119059 1 4 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8717 16:30:56.125575 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8718 16:30:56.128581 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8719 16:30:56.132294 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8720 16:30:56.138729 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8721 16:30:56.142216 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8722 16:30:56.145173 1 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8723 16:30:56.151848 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8724 16:30:56.155135 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8725 16:30:56.158416 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
8726 16:30:56.165370 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 16:30:56.168622 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 16:30:56.171794 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 16:30:56.178119 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 16:30:56.181995 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8731 16:30:56.185252 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8732 16:30:56.191479 1 6 12 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
8733 16:30:56.194700 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8734 16:30:56.198202 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8735 16:30:56.204452 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 16:30:56.208227 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8737 16:30:56.211242 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8738 16:30:56.217735 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8739 16:30:56.221324 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8740 16:30:56.224627 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8741 16:30:56.231013 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 16:30:56.234189 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 16:30:56.237447 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 16:30:56.244177 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 16:30:56.247349 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 16:30:56.251037 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 16:30:56.257063 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 16:30:56.260759 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 16:30:56.263940 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 16:30:56.270338 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 16:30:56.273641 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 16:30:56.276875 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 16:30:56.283665 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 16:30:56.287025 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8755 16:30:56.290195 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8756 16:30:56.296725 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8757 16:30:56.300676 Total UI for P1: 0, mck2ui 16
8758 16:30:56.303188 best dqsien dly found for B0: ( 1, 9, 6)
8759 16:30:56.307027 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8760 16:30:56.310200 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 16:30:56.313374 Total UI for P1: 0, mck2ui 16
8762 16:30:56.316181 best dqsien dly found for B1: ( 1, 9, 12)
8763 16:30:56.319967 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8764 16:30:56.326407 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8765 16:30:56.326533
8766 16:30:56.329369 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8767 16:30:56.332767 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8768 16:30:56.336358 [Gating] SW calibration Done
8769 16:30:56.336488 ==
8770 16:30:56.339380 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 16:30:56.343368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 16:30:56.343465 ==
8773 16:30:56.345907 RX Vref Scan: 0
8774 16:30:56.346018
8775 16:30:56.346087 RX Vref 0 -> 0, step: 1
8776 16:30:56.346150
8777 16:30:56.349531 RX Delay 0 -> 252, step: 8
8778 16:30:56.352680 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8779 16:30:56.359200 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8780 16:30:56.362901 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8781 16:30:56.365822 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8782 16:30:56.369475 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8783 16:30:56.372529 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8784 16:30:56.378947 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8785 16:30:56.382864 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8786 16:30:56.385982 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8787 16:30:56.389209 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8788 16:30:56.392375 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8789 16:30:56.398859 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8790 16:30:56.401917 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8791 16:30:56.405222 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8792 16:30:56.408694 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8793 16:30:56.415695 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8794 16:30:56.415836 ==
8795 16:30:56.418736 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 16:30:56.421899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 16:30:56.422016 ==
8798 16:30:56.422111 DQS Delay:
8799 16:30:56.425387 DQS0 = 0, DQS1 = 0
8800 16:30:56.425466 DQM Delay:
8801 16:30:56.428554 DQM0 = 134, DQM1 = 130
8802 16:30:56.428636 DQ Delay:
8803 16:30:56.432095 DQ0 =143, DQ1 =131, DQ2 =119, DQ3 =131
8804 16:30:56.434957 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =131
8805 16:30:56.438060 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8806 16:30:56.441620 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =135
8807 16:30:56.441704
8808 16:30:56.444556
8809 16:30:56.444631 ==
8810 16:30:56.448140 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 16:30:56.451569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 16:30:56.451657 ==
8813 16:30:56.451723
8814 16:30:56.451784
8815 16:30:56.454848 TX Vref Scan disable
8816 16:30:56.454932 == TX Byte 0 ==
8817 16:30:56.461081 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8818 16:30:56.464707 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8819 16:30:56.464803 == TX Byte 1 ==
8820 16:30:56.471236 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8821 16:30:56.474385 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8822 16:30:56.474476 ==
8823 16:30:56.477745 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 16:30:56.480787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 16:30:56.480884 ==
8826 16:30:56.495669
8827 16:30:56.498686 TX Vref early break, caculate TX vref
8828 16:30:56.502520 TX Vref=16, minBit 9, minWin=22, winSum=381
8829 16:30:56.505694 TX Vref=18, minBit 9, minWin=22, winSum=388
8830 16:30:56.508937 TX Vref=20, minBit 9, minWin=23, winSum=393
8831 16:30:56.512060 TX Vref=22, minBit 9, minWin=23, winSum=401
8832 16:30:56.515252 TX Vref=24, minBit 9, minWin=23, winSum=403
8833 16:30:56.522218 TX Vref=26, minBit 9, minWin=24, winSum=415
8834 16:30:56.525216 TX Vref=28, minBit 3, minWin=25, winSum=422
8835 16:30:56.528257 TX Vref=30, minBit 9, minWin=24, winSum=417
8836 16:30:56.531869 TX Vref=32, minBit 8, minWin=24, winSum=413
8837 16:30:56.534984 TX Vref=34, minBit 9, minWin=23, winSum=404
8838 16:30:56.541650 TX Vref=36, minBit 8, minWin=23, winSum=394
8839 16:30:56.545212 [TxChooseVref] Worse bit 3, Min win 25, Win sum 422, Final Vref 28
8840 16:30:56.545322
8841 16:30:56.548481 Final TX Range 0 Vref 28
8842 16:30:56.548560
8843 16:30:56.548624 ==
8844 16:30:56.551719 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 16:30:56.554806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 16:30:56.558349 ==
8847 16:30:56.558440
8848 16:30:56.558508
8849 16:30:56.558570 TX Vref Scan disable
8850 16:30:56.564626 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8851 16:30:56.564733 == TX Byte 0 ==
8852 16:30:56.567909 u2DelayCellOfst[0]=14 cells (4 PI)
8853 16:30:56.571470 u2DelayCellOfst[1]=10 cells (3 PI)
8854 16:30:56.574804 u2DelayCellOfst[2]=0 cells (0 PI)
8855 16:30:56.577977 u2DelayCellOfst[3]=3 cells (1 PI)
8856 16:30:56.581217 u2DelayCellOfst[4]=7 cells (2 PI)
8857 16:30:56.584674 u2DelayCellOfst[5]=17 cells (5 PI)
8858 16:30:56.588100 u2DelayCellOfst[6]=14 cells (4 PI)
8859 16:30:56.591010 u2DelayCellOfst[7]=3 cells (1 PI)
8860 16:30:56.594253 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8861 16:30:56.597470 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8862 16:30:56.601391 == TX Byte 1 ==
8863 16:30:56.604582 u2DelayCellOfst[8]=0 cells (0 PI)
8864 16:30:56.607681 u2DelayCellOfst[9]=0 cells (0 PI)
8865 16:30:56.610939 u2DelayCellOfst[10]=10 cells (3 PI)
8866 16:30:56.614147 u2DelayCellOfst[11]=3 cells (1 PI)
8867 16:30:56.617471 u2DelayCellOfst[12]=14 cells (4 PI)
8868 16:30:56.620591 u2DelayCellOfst[13]=14 cells (4 PI)
8869 16:30:56.624480 u2DelayCellOfst[14]=17 cells (5 PI)
8870 16:30:56.624578 u2DelayCellOfst[15]=17 cells (5 PI)
8871 16:30:56.630659 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8872 16:30:56.634052 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8873 16:30:56.637471 DramC Write-DBI on
8874 16:30:56.637565 ==
8875 16:30:56.640467 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 16:30:56.643641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 16:30:56.643733 ==
8878 16:30:56.643800
8879 16:30:56.643861
8880 16:30:56.647216 TX Vref Scan disable
8881 16:30:56.647306 == TX Byte 0 ==
8882 16:30:56.653518 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8883 16:30:56.653620 == TX Byte 1 ==
8884 16:30:56.656656 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8885 16:30:56.660531 DramC Write-DBI off
8886 16:30:56.660661
8887 16:30:56.660759 [DATLAT]
8888 16:30:56.663547 Freq=1600, CH1 RK1
8889 16:30:56.663661
8890 16:30:56.663767 DATLAT Default: 0xf
8891 16:30:56.666878 0, 0xFFFF, sum = 0
8892 16:30:56.670125 1, 0xFFFF, sum = 0
8893 16:30:56.670263 2, 0xFFFF, sum = 0
8894 16:30:56.673739 3, 0xFFFF, sum = 0
8895 16:30:56.673831 4, 0xFFFF, sum = 0
8896 16:30:56.676779 5, 0xFFFF, sum = 0
8897 16:30:56.676890 6, 0xFFFF, sum = 0
8898 16:30:56.679791 7, 0xFFFF, sum = 0
8899 16:30:56.679901 8, 0xFFFF, sum = 0
8900 16:30:56.683364 9, 0xFFFF, sum = 0
8901 16:30:56.683488 10, 0xFFFF, sum = 0
8902 16:30:56.686420 11, 0xFFFF, sum = 0
8903 16:30:56.686545 12, 0xFFFF, sum = 0
8904 16:30:56.689984 13, 0xFFFF, sum = 0
8905 16:30:56.690100 14, 0x0, sum = 1
8906 16:30:56.693073 15, 0x0, sum = 2
8907 16:30:56.693180 16, 0x0, sum = 3
8908 16:30:56.696533 17, 0x0, sum = 4
8909 16:30:56.696621 best_step = 15
8910 16:30:56.696715
8911 16:30:56.696808 ==
8912 16:30:56.699456 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 16:30:56.706273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 16:30:56.706410 ==
8915 16:30:56.706513 RX Vref Scan: 0
8916 16:30:56.706604
8917 16:30:56.709871 RX Vref 0 -> 0, step: 1
8918 16:30:56.709961
8919 16:30:56.712995 RX Delay 19 -> 252, step: 4
8920 16:30:56.716223 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8921 16:30:56.719391 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8922 16:30:56.725871 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8923 16:30:56.729642 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8924 16:30:56.732861 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8925 16:30:56.735967 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8926 16:30:56.739326 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8927 16:30:56.742378 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8928 16:30:56.749383 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8929 16:30:56.752462 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8930 16:30:56.756113 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8931 16:30:56.758725 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8932 16:30:56.765722 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8933 16:30:56.768692 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8934 16:30:56.772000 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8935 16:30:56.775149 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8936 16:30:56.775321 ==
8937 16:30:56.779164 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 16:30:56.785069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 16:30:56.785210 ==
8940 16:30:56.785313 DQS Delay:
8941 16:30:56.788165 DQS0 = 0, DQS1 = 0
8942 16:30:56.788275 DQM Delay:
8943 16:30:56.791699 DQM0 = 132, DQM1 = 128
8944 16:30:56.791816 DQ Delay:
8945 16:30:56.794889 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =128
8946 16:30:56.798703 DQ4 =132, DQ5 =144, DQ6 =140, DQ7 =130
8947 16:30:56.801928 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8948 16:30:56.804868 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8949 16:30:56.804979
8950 16:30:56.805077
8951 16:30:56.805169
8952 16:30:56.808280 [DramC_TX_OE_Calibration] TA2
8953 16:30:56.811755 Original DQ_B0 (3 6) =30, OEN = 27
8954 16:30:56.814739 Original DQ_B1 (3 6) =30, OEN = 27
8955 16:30:56.818156 24, 0x0, End_B0=24 End_B1=24
8956 16:30:56.821815 25, 0x0, End_B0=25 End_B1=25
8957 16:30:56.821961 26, 0x0, End_B0=26 End_B1=26
8958 16:30:56.824926 27, 0x0, End_B0=27 End_B1=27
8959 16:30:56.828226 28, 0x0, End_B0=28 End_B1=28
8960 16:30:56.831489 29, 0x0, End_B0=29 End_B1=29
8961 16:30:56.831613 30, 0x0, End_B0=30 End_B1=30
8962 16:30:56.834651 31, 0x4141, End_B0=30 End_B1=30
8963 16:30:56.837945 Byte0 end_step=30 best_step=27
8964 16:30:56.841182 Byte1 end_step=30 best_step=27
8965 16:30:56.844426 Byte0 TX OE(2T, 0.5T) = (3, 3)
8966 16:30:56.847556 Byte1 TX OE(2T, 0.5T) = (3, 3)
8967 16:30:56.847680
8968 16:30:56.847780
8969 16:30:56.854335 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8970 16:30:56.857370 CH1 RK1: MR19=303, MR18=111F
8971 16:30:56.864295 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
8972 16:30:56.867378 [RxdqsGatingPostProcess] freq 1600
8973 16:30:56.874143 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8974 16:30:56.877287 best DQS0 dly(2T, 0.5T) = (1, 1)
8975 16:30:56.877426 best DQS1 dly(2T, 0.5T) = (1, 1)
8976 16:30:56.880556 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8977 16:30:56.883766 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8978 16:30:56.887544 best DQS0 dly(2T, 0.5T) = (1, 1)
8979 16:30:56.890379 best DQS1 dly(2T, 0.5T) = (1, 1)
8980 16:30:56.894197 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8981 16:30:56.897254 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8982 16:30:56.900217 Pre-setting of DQS Precalculation
8983 16:30:56.907255 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8984 16:30:56.913210 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8985 16:30:56.920260 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8986 16:30:56.920407
8987 16:30:56.920486
8988 16:30:56.923283 [Calibration Summary] 3200 Mbps
8989 16:30:56.923395 CH 0, Rank 0
8990 16:30:56.926874 SW Impedance : PASS
8991 16:30:56.929643 DUTY Scan : NO K
8992 16:30:56.929752 ZQ Calibration : PASS
8993 16:30:56.933384 Jitter Meter : NO K
8994 16:30:56.936735 CBT Training : PASS
8995 16:30:56.936869 Write leveling : PASS
8996 16:30:56.939946 RX DQS gating : PASS
8997 16:30:56.943106 RX DQ/DQS(RDDQC) : PASS
8998 16:30:56.943238 TX DQ/DQS : PASS
8999 16:30:56.946230 RX DATLAT : PASS
9000 16:30:56.946343 RX DQ/DQS(Engine): PASS
9001 16:30:56.950004 TX OE : PASS
9002 16:30:56.950090 All Pass.
9003 16:30:56.950157
9004 16:30:56.953003 CH 0, Rank 1
9005 16:30:56.953107 SW Impedance : PASS
9006 16:30:56.956002 DUTY Scan : NO K
9007 16:30:56.959526 ZQ Calibration : PASS
9008 16:30:56.959644 Jitter Meter : NO K
9009 16:30:56.963177 CBT Training : PASS
9010 16:30:56.966103 Write leveling : PASS
9011 16:30:56.966221 RX DQS gating : PASS
9012 16:30:56.969178 RX DQ/DQS(RDDQC) : PASS
9013 16:30:56.973154 TX DQ/DQS : PASS
9014 16:30:56.973304 RX DATLAT : PASS
9015 16:30:56.976244 RX DQ/DQS(Engine): PASS
9016 16:30:56.979412 TX OE : PASS
9017 16:30:56.979498 All Pass.
9018 16:30:56.979565
9019 16:30:56.979625 CH 1, Rank 0
9020 16:30:56.982509 SW Impedance : PASS
9021 16:30:56.985792 DUTY Scan : NO K
9022 16:30:56.985891 ZQ Calibration : PASS
9023 16:30:56.989601 Jitter Meter : NO K
9024 16:30:56.992716 CBT Training : PASS
9025 16:30:56.992837 Write leveling : PASS
9026 16:30:56.995966 RX DQS gating : PASS
9027 16:30:56.998944 RX DQ/DQS(RDDQC) : PASS
9028 16:30:56.999060 TX DQ/DQS : PASS
9029 16:30:57.002752 RX DATLAT : PASS
9030 16:30:57.005943 RX DQ/DQS(Engine): PASS
9031 16:30:57.006035 TX OE : PASS
9032 16:30:57.006099 All Pass.
9033 16:30:57.009244
9034 16:30:57.009358 CH 1, Rank 1
9035 16:30:57.012598 SW Impedance : PASS
9036 16:30:57.012708 DUTY Scan : NO K
9037 16:30:57.015589 ZQ Calibration : PASS
9038 16:30:57.019393 Jitter Meter : NO K
9039 16:30:57.019516 CBT Training : PASS
9040 16:30:57.022491 Write leveling : PASS
9041 16:30:57.022609 RX DQS gating : PASS
9042 16:30:57.025785 RX DQ/DQS(RDDQC) : PASS
9043 16:30:57.028952 TX DQ/DQS : PASS
9044 16:30:57.029069 RX DATLAT : PASS
9045 16:30:57.032063 RX DQ/DQS(Engine): PASS
9046 16:30:57.035619 TX OE : PASS
9047 16:30:57.035733 All Pass.
9048 16:30:57.035835
9049 16:30:57.039150 DramC Write-DBI on
9050 16:30:57.039268 PER_BANK_REFRESH: Hybrid Mode
9051 16:30:57.042114 TX_TRACKING: ON
9052 16:30:57.051601 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9053 16:30:57.058778 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9054 16:30:57.064856 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9055 16:30:57.068689 [FAST_K] Save calibration result to emmc
9056 16:30:57.071614 sync common calibartion params.
9057 16:30:57.074758 sync cbt_mode0:1, 1:1
9058 16:30:57.078018 dram_init: ddr_geometry: 2
9059 16:30:57.078118 dram_init: ddr_geometry: 2
9060 16:30:57.081802 dram_init: ddr_geometry: 2
9061 16:30:57.085191 0:dram_rank_size:100000000
9062 16:30:57.085300 1:dram_rank_size:100000000
9063 16:30:57.091522 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9064 16:30:57.094834 DFS_SHUFFLE_HW_MODE: ON
9065 16:30:57.097940 dramc_set_vcore_voltage set vcore to 725000
9066 16:30:57.101776 Read voltage for 1600, 0
9067 16:30:57.101877 Vio18 = 0
9068 16:30:57.101948 Vcore = 725000
9069 16:30:57.104612 Vdram = 0
9070 16:30:57.104717 Vddq = 0
9071 16:30:57.104785 Vmddr = 0
9072 16:30:57.108347 switch to 3200 Mbps bootup
9073 16:30:57.111476 [DramcRunTimeConfig]
9074 16:30:57.111585 PHYPLL
9075 16:30:57.111686 DPM_CONTROL_AFTERK: ON
9076 16:30:57.114411 PER_BANK_REFRESH: ON
9077 16:30:57.117738 REFRESH_OVERHEAD_REDUCTION: ON
9078 16:30:57.117847 CMD_PICG_NEW_MODE: OFF
9079 16:30:57.121431 XRTWTW_NEW_MODE: ON
9080 16:30:57.121513 XRTRTR_NEW_MODE: ON
9081 16:30:57.124869 TX_TRACKING: ON
9082 16:30:57.125011 RDSEL_TRACKING: OFF
9083 16:30:57.128034 DQS Precalculation for DVFS: ON
9084 16:30:57.131269 RX_TRACKING: OFF
9085 16:30:57.131420 HW_GATING DBG: ON
9086 16:30:57.134382 ZQCS_ENABLE_LP4: ON
9087 16:30:57.134476 RX_PICG_NEW_MODE: ON
9088 16:30:57.137660 TX_PICG_NEW_MODE: ON
9089 16:30:57.141374 ENABLE_RX_DCM_DPHY: ON
9090 16:30:57.144447 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9091 16:30:57.144542 DUMMY_READ_FOR_TRACKING: OFF
9092 16:30:57.147706 !!! SPM_CONTROL_AFTERK: OFF
9093 16:30:57.150941 !!! SPM could not control APHY
9094 16:30:57.153990 IMPEDANCE_TRACKING: ON
9095 16:30:57.154126 TEMP_SENSOR: ON
9096 16:30:57.157704 HW_SAVE_FOR_SR: OFF
9097 16:30:57.157819 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9098 16:30:57.164045 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9099 16:30:57.164187 Read ODT Tracking: ON
9100 16:30:57.167184 Refresh Rate DeBounce: ON
9101 16:30:57.170885 DFS_NO_QUEUE_FLUSH: ON
9102 16:30:57.170972 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9103 16:30:57.173895 ENABLE_DFS_RUNTIME_MRW: OFF
9104 16:30:57.176950 DDR_RESERVE_NEW_MODE: ON
9105 16:30:57.180101 MR_CBT_SWITCH_FREQ: ON
9106 16:30:57.180252 =========================
9107 16:30:57.199915 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9108 16:30:57.203197 dram_init: ddr_geometry: 2
9109 16:30:57.221698 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9110 16:30:57.224909 dram_init: dram init end (result: 0)
9111 16:30:57.231779 DRAM-K: Full calibration passed in 24402 msecs
9112 16:30:57.234732 MRC: failed to locate region type 0.
9113 16:30:57.234851 DRAM rank0 size:0x100000000,
9114 16:30:57.238357 DRAM rank1 size=0x100000000
9115 16:30:57.247746 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9116 16:30:57.254174 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9117 16:30:57.264278 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9118 16:30:57.271131 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9119 16:30:57.271250 DRAM rank0 size:0x100000000,
9120 16:30:57.274197 DRAM rank1 size=0x100000000
9121 16:30:57.274288 CBMEM:
9122 16:30:57.277246 IMD: root @ 0xfffff000 254 entries.
9123 16:30:57.280275 IMD: root @ 0xffffec00 62 entries.
9124 16:30:57.287233 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9125 16:30:57.290263 WARNING: RO_VPD is uninitialized or empty.
9126 16:30:57.293508 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9127 16:30:57.301894 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9128 16:30:57.314705 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9129 16:30:57.325927 BS: romstage times (exec / console): total (unknown) / 23933 ms
9130 16:30:57.326057
9131 16:30:57.326135
9132 16:30:57.335685 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9133 16:30:57.339083 ARM64: Exception handlers installed.
9134 16:30:57.342296 ARM64: Testing exception
9135 16:30:57.346075 ARM64: Done test exception
9136 16:30:57.346201 Enumerating buses...
9137 16:30:57.349035 Show all devs... Before device enumeration.
9138 16:30:57.352205 Root Device: enabled 1
9139 16:30:57.355464 CPU_CLUSTER: 0: enabled 1
9140 16:30:57.355564 CPU: 00: enabled 1
9141 16:30:57.358778 Compare with tree...
9142 16:30:57.358875 Root Device: enabled 1
9143 16:30:57.362031 CPU_CLUSTER: 0: enabled 1
9144 16:30:57.365708 CPU: 00: enabled 1
9145 16:30:57.365835 Root Device scanning...
9146 16:30:57.368972 scan_static_bus for Root Device
9147 16:30:57.371819 CPU_CLUSTER: 0 enabled
9148 16:30:57.375511 scan_static_bus for Root Device done
9149 16:30:57.378890 scan_bus: bus Root Device finished in 8 msecs
9150 16:30:57.379009 done
9151 16:30:57.385296 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9152 16:30:57.388287 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9153 16:30:57.395061 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9154 16:30:57.398295 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9155 16:30:57.401517 Allocating resources...
9156 16:30:57.405200 Reading resources...
9157 16:30:57.408517 Root Device read_resources bus 0 link: 0
9158 16:30:57.411675 DRAM rank0 size:0x100000000,
9159 16:30:57.411768 DRAM rank1 size=0x100000000
9160 16:30:57.414931 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9161 16:30:57.418621 CPU: 00 missing read_resources
9162 16:30:57.425004 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9163 16:30:57.428141 Root Device read_resources bus 0 link: 0 done
9164 16:30:57.431561 Done reading resources.
9165 16:30:57.434697 Show resources in subtree (Root Device)...After reading.
9166 16:30:57.438050 Root Device child on link 0 CPU_CLUSTER: 0
9167 16:30:57.441775 CPU_CLUSTER: 0 child on link 0 CPU: 00
9168 16:30:57.451351 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9169 16:30:57.451475 CPU: 00
9170 16:30:57.454655 Root Device assign_resources, bus 0 link: 0
9171 16:30:57.457896 CPU_CLUSTER: 0 missing set_resources
9172 16:30:57.464804 Root Device assign_resources, bus 0 link: 0 done
9173 16:30:57.464972 Done setting resources.
9174 16:30:57.471269 Show resources in subtree (Root Device)...After assigning values.
9175 16:30:57.474440 Root Device child on link 0 CPU_CLUSTER: 0
9176 16:30:57.477667 CPU_CLUSTER: 0 child on link 0 CPU: 00
9177 16:30:57.487570 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9178 16:30:57.487711 CPU: 00
9179 16:30:57.491001 Done allocating resources.
9180 16:30:57.497542 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9181 16:30:57.497662 Enabling resources...
9182 16:30:57.497729 done.
9183 16:30:57.503929 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9184 16:30:57.507569 Initializing devices...
9185 16:30:57.507672 Root Device init
9186 16:30:57.510739 init hardware done!
9187 16:30:57.510829 0x00000018: ctrlr->caps
9188 16:30:57.513981 52.000 MHz: ctrlr->f_max
9189 16:30:57.517086 0.400 MHz: ctrlr->f_min
9190 16:30:57.517208 0x40ff8080: ctrlr->voltages
9191 16:30:57.520421 sclk: 390625
9192 16:30:57.520537 Bus Width = 1
9193 16:30:57.523547 sclk: 390625
9194 16:30:57.523633 Bus Width = 1
9195 16:30:57.527473 Early init status = 3
9196 16:30:57.530599 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9197 16:30:57.534247 in-header: 03 fc 00 00 01 00 00 00
9198 16:30:57.537758 in-data: 00
9199 16:30:57.540688 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9200 16:30:57.546554 in-header: 03 fd 00 00 00 00 00 00
9201 16:30:57.549747 in-data:
9202 16:30:57.553697 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9203 16:30:57.557511 in-header: 03 fc 00 00 01 00 00 00
9204 16:30:57.561211 in-data: 00
9205 16:30:57.564228 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9206 16:30:57.569898 in-header: 03 fd 00 00 00 00 00 00
9207 16:30:57.572880 in-data:
9208 16:30:57.576783 [SSUSB] Setting up USB HOST controller...
9209 16:30:57.579943 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9210 16:30:57.583059 [SSUSB] phy power-on done.
9211 16:30:57.586189 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9212 16:30:57.593210 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9213 16:30:57.596352 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9214 16:30:57.602625 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9215 16:30:57.609165 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9216 16:30:57.615759 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9217 16:30:57.622391 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9218 16:30:57.629131 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9219 16:30:57.632505 SPM: binary array size = 0x9dc
9220 16:30:57.635662 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9221 16:30:57.642688 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9222 16:30:57.648892 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9223 16:30:57.655324 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9224 16:30:57.658599 configure_display: Starting display init
9225 16:30:57.693052 anx7625_power_on_init: Init interface.
9226 16:30:57.696454 anx7625_disable_pd_protocol: Disabled PD feature.
9227 16:30:57.699521 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9228 16:30:57.727634 anx7625_start_dp_work: Secure OCM version=00
9229 16:30:57.731083 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9230 16:30:57.745548 sp_tx_get_edid_block: EDID Block = 1
9231 16:30:57.848242 Extracted contents:
9232 16:30:57.851245 header: 00 ff ff ff ff ff ff 00
9233 16:30:57.854513 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9234 16:30:57.857853 version: 01 04
9235 16:30:57.861425 basic params: 95 1f 11 78 0a
9236 16:30:57.864861 chroma info: 76 90 94 55 54 90 27 21 50 54
9237 16:30:57.868170 established: 00 00 00
9238 16:30:57.874588 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9239 16:30:57.880873 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9240 16:30:57.884683 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9241 16:30:57.890835 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9242 16:30:57.897302 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9243 16:30:57.901203 extensions: 00
9244 16:30:57.901332 checksum: fb
9245 16:30:57.901399
9246 16:30:57.907195 Manufacturer: IVO Model 57d Serial Number 0
9247 16:30:57.907302 Made week 0 of 2020
9248 16:30:57.910561 EDID version: 1.4
9249 16:30:57.910652 Digital display
9250 16:30:57.914031 6 bits per primary color channel
9251 16:30:57.914127 DisplayPort interface
9252 16:30:57.917546 Maximum image size: 31 cm x 17 cm
9253 16:30:57.920757 Gamma: 220%
9254 16:30:57.920857 Check DPMS levels
9255 16:30:57.927425 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9256 16:30:57.930281 First detailed timing is preferred timing
9257 16:30:57.933904 Established timings supported:
9258 16:30:57.934037 Standard timings supported:
9259 16:30:57.937055 Detailed timings
9260 16:30:57.940168 Hex of detail: 383680a07038204018303c0035ae10000019
9261 16:30:57.946719 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9262 16:30:57.950324 0780 0798 07c8 0820 hborder 0
9263 16:30:57.953209 0438 043b 0447 0458 vborder 0
9264 16:30:57.956559 -hsync -vsync
9265 16:30:57.956655 Did detailed timing
9266 16:30:57.963464 Hex of detail: 000000000000000000000000000000000000
9267 16:30:57.966610 Manufacturer-specified data, tag 0
9268 16:30:57.969818 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9269 16:30:57.973157 ASCII string: InfoVision
9270 16:30:57.976725 Hex of detail: 000000fe00523134304e574635205248200a
9271 16:30:57.979876 ASCII string: R140NWF5 RH
9272 16:30:57.979974 Checksum
9273 16:30:57.983079 Checksum: 0xfb (valid)
9274 16:30:57.986282 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9275 16:30:57.990099 DSI data_rate: 832800000 bps
9276 16:30:57.996222 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9277 16:30:57.999597 anx7625_parse_edid: pixelclock(138800).
9278 16:30:58.002713 hactive(1920), hsync(48), hfp(24), hbp(88)
9279 16:30:58.006608 vactive(1080), vsync(12), vfp(3), vbp(17)
9280 16:30:58.009595 anx7625_dsi_config: config dsi.
9281 16:30:58.015913 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9282 16:30:58.030448 anx7625_dsi_config: success to config DSI
9283 16:30:58.033402 anx7625_dp_start: MIPI phy setup OK.
9284 16:30:58.036973 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9285 16:30:58.039967 mtk_ddp_mode_set invalid vrefresh 60
9286 16:30:58.043475 main_disp_path_setup
9287 16:30:58.043579 ovl_layer_smi_id_en
9288 16:30:58.046588 ovl_layer_smi_id_en
9289 16:30:58.046681 ccorr_config
9290 16:30:58.046747 aal_config
9291 16:30:58.049797 gamma_config
9292 16:30:58.049885 postmask_config
9293 16:30:58.053004 dither_config
9294 16:30:58.056223 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9295 16:30:58.062839 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9296 16:30:58.066304 Root Device init finished in 555 msecs
9297 16:30:58.069964 CPU_CLUSTER: 0 init
9298 16:30:58.076276 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9299 16:30:58.083019 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9300 16:30:58.083139 APU_MBOX 0x190000b0 = 0x10001
9301 16:30:58.085977 APU_MBOX 0x190001b0 = 0x10001
9302 16:30:58.089361 APU_MBOX 0x190005b0 = 0x10001
9303 16:30:58.092375 APU_MBOX 0x190006b0 = 0x10001
9304 16:30:58.099313 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9305 16:30:58.109515 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9306 16:30:58.121609 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9307 16:30:58.128317 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9308 16:30:58.139836 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9309 16:30:58.149200 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9310 16:30:58.152176 CPU_CLUSTER: 0 init finished in 81 msecs
9311 16:30:58.155416 Devices initialized
9312 16:30:58.159166 Show all devs... After init.
9313 16:30:58.159265 Root Device: enabled 1
9314 16:30:58.162321 CPU_CLUSTER: 0: enabled 1
9315 16:30:58.165486 CPU: 00: enabled 1
9316 16:30:58.168550 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9317 16:30:58.171863 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9318 16:30:58.175255 ELOG: NV offset 0x57f000 size 0x1000
9319 16:30:58.182014 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9320 16:30:58.189070 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9321 16:30:58.191964 ELOG: Event(17) added with size 13 at 2024-06-17 16:30:57 UTC
9322 16:30:58.198746 out: cmd=0x121: 03 db 21 01 00 00 00 00
9323 16:30:58.201826 in-header: 03 60 00 00 2c 00 00 00
9324 16:30:58.211404 in-data: df 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 16:30:58.218411 ELOG: Event(A1) added with size 10 at 2024-06-17 16:30:57 UTC
9326 16:30:58.224695 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9327 16:30:58.231660 ELOG: Event(A0) added with size 9 at 2024-06-17 16:30:57 UTC
9328 16:30:58.234731 elog_add_boot_reason: Logged dev mode boot
9329 16:30:58.241344 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9330 16:30:58.241467 Finalize devices...
9331 16:30:58.244612 Devices finalized
9332 16:30:58.248044 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9333 16:30:58.251156 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9334 16:30:58.254983 in-header: 03 07 00 00 08 00 00 00
9335 16:30:58.258606 in-data: aa e4 47 04 13 02 00 00
9336 16:30:58.261882 Chrome EC: UHEPI supported
9337 16:30:58.268132 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9338 16:30:58.271318 in-header: 03 a9 00 00 08 00 00 00
9339 16:30:58.274463 in-data: 84 60 60 08 00 00 00 00
9340 16:30:58.281272 ELOG: Event(91) added with size 10 at 2024-06-17 16:30:57 UTC
9341 16:30:58.284811 ELOG: Event(16) added with size 11 at 2024-06-17 16:30:57 UTC
9342 16:30:58.366788 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9343 16:30:58.369927 Chrome EC: clear events_b mask to 0x0000000020004000
9344 16:30:58.376342 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9345 16:30:58.380967 in-header: 03 fd 00 00 00 00 00 00
9346 16:30:58.384084 in-data:
9347 16:30:58.387768 BS: BS_WRITE_TABLES entry times (exec / console): 78 / 56 ms
9348 16:30:58.390855 Writing coreboot table at 0xffe64000
9349 16:30:58.397283 0. 000000000010a000-0000000000113fff: RAMSTAGE
9350 16:30:58.400990 1. 0000000040000000-00000000400fffff: RAM
9351 16:30:58.404145 2. 0000000040100000-000000004032afff: RAMSTAGE
9352 16:30:58.407289 3. 000000004032b000-00000000545fffff: RAM
9353 16:30:58.410607 4. 0000000054600000-000000005465ffff: BL31
9354 16:30:58.413683 5. 0000000054660000-00000000ffe63fff: RAM
9355 16:30:58.420532 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9356 16:30:58.423780 7. 0000000100000000-000000023fffffff: RAM
9357 16:30:58.426799 Passing 5 GPIOs to payload:
9358 16:30:58.430620 NAME | PORT | POLARITY | VALUE
9359 16:30:58.436518 EC in RW | 0x000000aa | low | undefined
9360 16:30:58.440483 EC interrupt | 0x00000005 | low | undefined
9361 16:30:58.446686 TPM interrupt | 0x000000ab | high | undefined
9362 16:30:58.449835 SD card detect | 0x00000011 | high | undefined
9363 16:30:58.453760 speaker enable | 0x00000093 | high | undefined
9364 16:30:58.457003 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9365 16:30:58.460240 in-header: 03 f9 00 00 02 00 00 00
9366 16:30:58.463815 in-data: 02 00
9367 16:30:58.466685 ADC[4]: Raw value=902216 ID=7
9368 16:30:58.470028 ADC[3]: Raw value=213916 ID=1
9369 16:30:58.470158 RAM Code: 0x71
9370 16:30:58.473237 ADC[6]: Raw value=74630 ID=0
9371 16:30:58.476631 ADC[5]: Raw value=213916 ID=1
9372 16:30:58.476770 SKU Code: 0x1
9373 16:30:58.483661 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e337
9374 16:30:58.483814 coreboot table: 964 bytes.
9375 16:30:58.486792 IMD ROOT 0. 0xfffff000 0x00001000
9376 16:30:58.490044 IMD SMALL 1. 0xffffe000 0x00001000
9377 16:30:58.493064 RO MCACHE 2. 0xffffc000 0x00001104
9378 16:30:58.496254 CONSOLE 3. 0xfff7c000 0x00080000
9379 16:30:58.499948 FMAP 4. 0xfff7b000 0x00000452
9380 16:30:58.503313 TIME STAMP 5. 0xfff7a000 0x00000910
9381 16:30:58.506463 VBOOT WORK 6. 0xfff66000 0x00014000
9382 16:30:58.509694 RAMOOPS 7. 0xffe66000 0x00100000
9383 16:30:58.512906 COREBOOT 8. 0xffe64000 0x00002000
9384 16:30:58.516260 IMD small region:
9385 16:30:58.519519 IMD ROOT 0. 0xffffec00 0x00000400
9386 16:30:58.523147 VPD 1. 0xffffeb80 0x0000006c
9387 16:30:58.526100 MMC STATUS 2. 0xffffeb60 0x00000004
9388 16:30:58.532727 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9389 16:30:58.539161 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9390 16:30:58.578115 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9391 16:30:58.580796 Checking segment from ROM address 0x40100000
9392 16:30:58.587344 Checking segment from ROM address 0x4010001c
9393 16:30:58.590945 Loading segment from ROM address 0x40100000
9394 16:30:58.591049 code (compression=0)
9395 16:30:58.600490 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9396 16:30:58.607458 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9397 16:30:58.610629 it's not compressed!
9398 16:30:58.613776 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9399 16:30:58.620329 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9400 16:30:58.638249 Loading segment from ROM address 0x4010001c
9401 16:30:58.638396 Entry Point 0x80000000
9402 16:30:58.641347 Loaded segments
9403 16:30:58.644636 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9404 16:30:58.651834 Jumping to boot code at 0x80000000(0xffe64000)
9405 16:30:58.658356 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9406 16:30:58.664787 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9407 16:30:58.672634 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9408 16:30:58.675848 Checking segment from ROM address 0x40100000
9409 16:30:58.678932 Checking segment from ROM address 0x4010001c
9410 16:30:58.686065 Loading segment from ROM address 0x40100000
9411 16:30:58.686188 code (compression=1)
9412 16:30:58.692191 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9413 16:30:58.702554 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9414 16:30:58.702689 using LZMA
9415 16:30:58.710864 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9416 16:30:58.717768 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9417 16:30:58.720677 Loading segment from ROM address 0x4010001c
9418 16:30:58.720788 Entry Point 0x54601000
9419 16:30:58.724235 Loaded segments
9420 16:30:58.727515 NOTICE: MT8192 bl31_setup
9421 16:30:58.734351 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9422 16:30:58.738250 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9423 16:30:58.741404 WARNING: region 0:
9424 16:30:58.744637 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9425 16:30:58.744738 WARNING: region 1:
9426 16:30:58.751064 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9427 16:30:58.754325 WARNING: region 2:
9428 16:30:58.757253 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9429 16:30:58.760544 WARNING: region 3:
9430 16:30:58.767726 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9431 16:30:58.767863 WARNING: region 4:
9432 16:30:58.774036 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9433 16:30:58.774163 WARNING: region 5:
9434 16:30:58.777162 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 16:30:58.780864 WARNING: region 6:
9436 16:30:58.784169 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 16:30:58.787472 WARNING: region 7:
9438 16:30:58.790424 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 16:30:58.797125 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9440 16:30:58.800343 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9441 16:30:58.807057 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9442 16:30:58.810575 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9443 16:30:58.813587 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9444 16:30:58.820083 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9445 16:30:58.823529 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9446 16:30:58.827068 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9447 16:30:58.833437 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9448 16:30:58.836408 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9449 16:30:58.843700 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9450 16:30:58.846839 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9451 16:30:58.850081 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9452 16:30:58.856402 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9453 16:30:58.859600 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9454 16:30:58.866348 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9455 16:30:58.869638 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9456 16:30:58.872800 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9457 16:30:58.879203 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9458 16:30:58.883142 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9459 16:30:58.889429 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9460 16:30:58.892569 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9461 16:30:58.895709 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9462 16:30:58.902546 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9463 16:30:58.905822 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9464 16:30:58.912640 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9465 16:30:58.915651 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9466 16:30:58.919299 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9467 16:30:58.925623 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9468 16:30:58.928833 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9469 16:30:58.935212 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9470 16:30:58.938868 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9471 16:30:58.942376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9472 16:30:58.948720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9473 16:30:58.952219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9474 16:30:58.955241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9475 16:30:58.958482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9476 16:30:58.964896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9477 16:30:58.968090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9478 16:30:58.971725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9479 16:30:58.975108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9480 16:30:58.981519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9481 16:30:58.984675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9482 16:30:58.987845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9483 16:30:58.991578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9484 16:30:58.998001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9485 16:30:59.001313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9486 16:30:59.004484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9487 16:30:59.010868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9488 16:30:59.014709 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9489 16:30:59.021006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9490 16:30:59.024165 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9491 16:30:59.027756 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9492 16:30:59.034678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9493 16:30:59.037777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9494 16:30:59.044442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9495 16:30:59.047253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9496 16:30:59.054034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9497 16:30:59.057232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9498 16:30:59.063919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9499 16:30:59.067135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9500 16:30:59.073852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9501 16:30:59.076963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9502 16:30:59.080638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9503 16:30:59.086891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9504 16:30:59.090255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9505 16:30:59.096462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9506 16:30:59.099802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9507 16:30:59.106636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9508 16:30:59.109765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9509 16:30:59.116585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9510 16:30:59.119693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9511 16:30:59.122977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9512 16:30:59.129853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9513 16:30:59.132860 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9514 16:30:59.139375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9515 16:30:59.142647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9516 16:30:59.149510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9517 16:30:59.153047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9518 16:30:59.159136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9519 16:30:59.163026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9520 16:30:59.169206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9521 16:30:59.172618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9522 16:30:59.175943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9523 16:30:59.182610 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9524 16:30:59.185613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9525 16:30:59.192510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9526 16:30:59.195596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9527 16:30:59.202101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9528 16:30:59.205853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9529 16:30:59.212054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9530 16:30:59.215212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9531 16:30:59.219070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9532 16:30:59.225429 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9533 16:30:59.228697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9534 16:30:59.235625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9535 16:30:59.238763 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9536 16:30:59.241674 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9537 16:30:59.248636 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9538 16:30:59.251848 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9539 16:30:59.254956 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9540 16:30:59.261533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9541 16:30:59.264858 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9542 16:30:59.268286 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9543 16:30:59.274499 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9544 16:30:59.277960 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9545 16:30:59.284628 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9546 16:30:59.288001 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9547 16:30:59.291094 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9548 16:30:59.297920 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9549 16:30:59.301045 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9550 16:30:59.307948 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9551 16:30:59.311125 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9552 16:30:59.314359 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9553 16:30:59.321253 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9554 16:30:59.324330 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9555 16:30:59.327446 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9556 16:30:59.334503 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9557 16:30:59.337140 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9558 16:30:59.340900 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9559 16:30:59.347098 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9560 16:30:59.350750 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9561 16:30:59.353973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9562 16:30:59.357164 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9563 16:30:59.364247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9564 16:30:59.367324 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9565 16:30:59.374008 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9566 16:30:59.376913 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9567 16:30:59.383956 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9568 16:30:59.386657 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9569 16:30:59.390321 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9570 16:30:59.396566 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9571 16:30:59.400240 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9572 16:30:59.406736 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9573 16:30:59.409811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9574 16:30:59.412917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9575 16:30:59.419858 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9576 16:30:59.423033 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9577 16:30:59.426529 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9578 16:30:59.433047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9579 16:30:59.436015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9580 16:30:59.443108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9581 16:30:59.446258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9582 16:30:59.452451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9583 16:30:59.456215 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9584 16:30:59.459355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9585 16:30:59.465756 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9586 16:30:59.468954 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9587 16:30:59.475988 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9588 16:30:59.479429 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9589 16:30:59.482419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9590 16:30:59.489294 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9591 16:30:59.492328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9592 16:30:59.498692 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9593 16:30:59.501971 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9594 16:30:59.505459 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9595 16:30:59.511913 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9596 16:30:59.515149 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9597 16:30:59.522038 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9598 16:30:59.525241 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9599 16:30:59.528473 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9600 16:30:59.535256 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9601 16:30:59.538358 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9602 16:30:59.544694 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9603 16:30:59.548740 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9604 16:30:59.551881 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9605 16:30:59.557973 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9606 16:30:59.561679 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9607 16:30:59.568094 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9608 16:30:59.571433 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9609 16:30:59.574662 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9610 16:30:59.581596 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9611 16:30:59.584914 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9612 16:30:59.591259 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9613 16:30:59.594302 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9614 16:30:59.598110 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9615 16:30:59.604187 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9616 16:30:59.607902 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9617 16:30:59.614399 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9618 16:30:59.617229 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9619 16:30:59.620839 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9620 16:30:59.627209 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9621 16:30:59.631020 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9622 16:30:59.637204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9623 16:30:59.640453 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9624 16:30:59.644053 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9625 16:30:59.650479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9626 16:30:59.653724 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9627 16:30:59.660551 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9628 16:30:59.663467 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9629 16:30:59.666577 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9630 16:30:59.673774 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9631 16:30:59.676776 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9632 16:30:59.683309 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9633 16:30:59.686701 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9634 16:30:59.693147 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9635 16:30:59.696666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9636 16:30:59.699622 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9637 16:30:59.706575 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9638 16:30:59.709742 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9639 16:30:59.716608 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9640 16:30:59.719701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9641 16:30:59.726035 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9642 16:30:59.730072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9643 16:30:59.732883 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9644 16:30:59.739323 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9645 16:30:59.742906 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9646 16:30:59.749075 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9647 16:30:59.752315 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9648 16:30:59.758791 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9649 16:30:59.762645 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9650 16:30:59.765810 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9651 16:30:59.772325 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9652 16:30:59.775388 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9653 16:30:59.782325 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9654 16:30:59.785359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9655 16:30:59.792486 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9656 16:30:59.795522 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9657 16:30:59.798801 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9658 16:30:59.805637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9659 16:30:59.808491 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9660 16:30:59.815441 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9661 16:30:59.818430 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9662 16:30:59.825343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9663 16:30:59.828416 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9664 16:30:59.831507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9665 16:30:59.838446 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9666 16:30:59.841572 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9667 16:30:59.848267 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9668 16:30:59.851155 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9669 16:30:59.855003 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9670 16:30:59.858333 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9671 16:30:59.864457 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9672 16:30:59.867669 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9673 16:30:59.871345 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9674 16:30:59.877736 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9675 16:30:59.880722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9676 16:30:59.884580 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9677 16:30:59.890875 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9678 16:30:59.894148 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9679 16:30:59.900633 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9680 16:30:59.903807 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9681 16:30:59.907655 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9682 16:30:59.914113 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9683 16:30:59.917143 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9684 16:30:59.920366 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9685 16:30:59.927044 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9686 16:30:59.930080 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9687 16:30:59.933917 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9688 16:30:59.940196 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9689 16:30:59.943495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9690 16:30:59.950359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9691 16:30:59.953524 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9692 16:30:59.956651 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9693 16:30:59.963641 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9694 16:30:59.966854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9695 16:30:59.973344 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9696 16:30:59.976704 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9697 16:30:59.979796 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9698 16:30:59.986417 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9699 16:30:59.989401 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9700 16:30:59.993358 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9701 16:30:59.999477 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9702 16:31:00.002802 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9703 16:31:00.005998 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9704 16:31:00.013115 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9705 16:31:00.016196 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9706 16:31:00.023016 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9707 16:31:00.026236 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9708 16:31:00.029162 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9709 16:31:00.032944 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9710 16:31:00.039211 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9711 16:31:00.042407 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9712 16:31:00.046003 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9713 16:31:00.049191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9714 16:31:00.055504 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9715 16:31:00.058650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9716 16:31:00.062393 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9717 16:31:00.065625 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9718 16:31:00.071900 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9719 16:31:00.075137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9720 16:31:00.078392 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9721 16:31:00.085336 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9722 16:31:00.088235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9723 16:31:00.094989 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9724 16:31:00.098607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9725 16:31:00.104935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9726 16:31:00.108251 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9727 16:31:00.111366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9728 16:31:00.117859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9729 16:31:00.121675 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9730 16:31:00.127762 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9731 16:31:00.131521 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9732 16:31:00.134283 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9733 16:31:00.141073 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9734 16:31:00.144683 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9735 16:31:00.151112 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9736 16:31:00.154106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9737 16:31:00.160580 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9738 16:31:00.164457 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9739 16:31:00.167236 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9740 16:31:00.174068 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9741 16:31:00.177189 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9742 16:31:00.183627 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9743 16:31:00.187409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9744 16:31:00.190392 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9745 16:31:00.197183 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9746 16:31:00.200787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9747 16:31:00.206698 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9748 16:31:00.210393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9749 16:31:00.216719 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9750 16:31:00.220012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9751 16:31:00.223901 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9752 16:31:00.230259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9753 16:31:00.233555 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9754 16:31:00.239967 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9755 16:31:00.243040 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9756 16:31:00.249552 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9757 16:31:00.253236 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9758 16:31:00.256423 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9759 16:31:00.263080 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9760 16:31:00.266285 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9761 16:31:00.273378 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9762 16:31:00.276657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9763 16:31:00.279651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9764 16:31:00.285997 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9765 16:31:00.289185 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9766 16:31:00.295917 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9767 16:31:00.299554 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9768 16:31:00.302601 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9769 16:31:00.309041 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9770 16:31:00.312632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9771 16:31:00.319369 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9772 16:31:00.322917 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9773 16:31:00.328886 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9774 16:31:00.332152 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9775 16:31:00.335358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9776 16:31:00.342175 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9777 16:31:00.345921 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9778 16:31:00.352248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9779 16:31:00.355375 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9780 16:31:00.359007 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9781 16:31:00.365525 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9782 16:31:00.368659 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9783 16:31:00.375516 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9784 16:31:00.378595 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9785 16:31:00.385001 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9786 16:31:00.388235 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9787 16:31:00.392176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9788 16:31:00.398413 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9789 16:31:00.401472 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9790 16:31:00.408281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9791 16:31:00.411464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9792 16:31:00.414736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9793 16:31:00.421734 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9794 16:31:00.424811 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9795 16:31:00.431421 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9796 16:31:00.434320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9797 16:31:00.440913 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9798 16:31:00.444290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9799 16:31:00.451066 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9800 16:31:00.453977 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9801 16:31:00.460501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9802 16:31:00.464541 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9803 16:31:00.467442 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9804 16:31:00.473808 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9805 16:31:00.477193 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9806 16:31:00.484076 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9807 16:31:00.487237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9808 16:31:00.493694 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9809 16:31:00.496835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9810 16:31:00.503634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9811 16:31:00.506799 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9812 16:31:00.509802 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9813 16:31:00.516860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9814 16:31:00.520167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9815 16:31:00.526947 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9816 16:31:00.530391 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9817 16:31:00.536660 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9818 16:31:00.540254 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9819 16:31:00.546700 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9820 16:31:00.549551 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9821 16:31:00.553412 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9822 16:31:00.559716 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9823 16:31:00.562708 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9824 16:31:00.569345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9825 16:31:00.572612 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9826 16:31:00.579587 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9827 16:31:00.582429 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9828 16:31:00.589313 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9829 16:31:00.592346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9830 16:31:00.599441 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9831 16:31:00.602620 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9832 16:31:00.605647 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9833 16:31:00.612384 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9834 16:31:00.615552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9835 16:31:00.622227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9836 16:31:00.625354 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9837 16:31:00.631705 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9838 16:31:00.635000 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9839 16:31:00.641895 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9840 16:31:00.644915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9841 16:31:00.648463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9842 16:31:00.654849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9843 16:31:00.658572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9844 16:31:00.664772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9845 16:31:00.668023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9846 16:31:00.674710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9847 16:31:00.678207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9848 16:31:00.684884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9849 16:31:00.687959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9850 16:31:00.694406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9851 16:31:00.697935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9852 16:31:00.704235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9853 16:31:00.707496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9854 16:31:00.713938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9855 16:31:00.717637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9856 16:31:00.724019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9857 16:31:00.727320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9858 16:31:00.734293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9859 16:31:00.737437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9860 16:31:00.743958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9861 16:31:00.747195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9862 16:31:00.753827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9863 16:31:00.756974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9864 16:31:00.763566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9865 16:31:00.766651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9866 16:31:00.773674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9867 16:31:00.776970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9868 16:31:00.783196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9869 16:31:00.786782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9870 16:31:00.793025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9871 16:31:00.796595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9872 16:31:00.803178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9873 16:31:00.806394 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9874 16:31:00.809839 INFO: [APUAPC] vio 0
9875 16:31:00.813021 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9876 16:31:00.819505 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9877 16:31:00.823035 INFO: [APUAPC] D0_APC_0: 0x400510
9878 16:31:00.823171 INFO: [APUAPC] D0_APC_1: 0x0
9879 16:31:00.826178 INFO: [APUAPC] D0_APC_2: 0x1540
9880 16:31:00.829520 INFO: [APUAPC] D0_APC_3: 0x0
9881 16:31:00.833179 INFO: [APUAPC] D1_APC_0: 0xffffffff
9882 16:31:00.836421 INFO: [APUAPC] D1_APC_1: 0xffffffff
9883 16:31:00.839667 INFO: [APUAPC] D1_APC_2: 0x3fffff
9884 16:31:00.842867 INFO: [APUAPC] D1_APC_3: 0x0
9885 16:31:00.845985 INFO: [APUAPC] D2_APC_0: 0xffffffff
9886 16:31:00.849219 INFO: [APUAPC] D2_APC_1: 0xffffffff
9887 16:31:00.852992 INFO: [APUAPC] D2_APC_2: 0x3fffff
9888 16:31:00.856085 INFO: [APUAPC] D2_APC_3: 0x0
9889 16:31:00.859193 INFO: [APUAPC] D3_APC_0: 0xffffffff
9890 16:31:00.862963 INFO: [APUAPC] D3_APC_1: 0xffffffff
9891 16:31:00.865822 INFO: [APUAPC] D3_APC_2: 0x3fffff
9892 16:31:00.869408 INFO: [APUAPC] D3_APC_3: 0x0
9893 16:31:00.872341 INFO: [APUAPC] D4_APC_0: 0xffffffff
9894 16:31:00.875499 INFO: [APUAPC] D4_APC_1: 0xffffffff
9895 16:31:00.878739 INFO: [APUAPC] D4_APC_2: 0x3fffff
9896 16:31:00.882517 INFO: [APUAPC] D4_APC_3: 0x0
9897 16:31:00.885552 INFO: [APUAPC] D5_APC_0: 0xffffffff
9898 16:31:00.888848 INFO: [APUAPC] D5_APC_1: 0xffffffff
9899 16:31:00.892486 INFO: [APUAPC] D5_APC_2: 0x3fffff
9900 16:31:00.895585 INFO: [APUAPC] D5_APC_3: 0x0
9901 16:31:00.899166 INFO: [APUAPC] D6_APC_0: 0xffffffff
9902 16:31:00.901948 INFO: [APUAPC] D6_APC_1: 0xffffffff
9903 16:31:00.905500 INFO: [APUAPC] D6_APC_2: 0x3fffff
9904 16:31:00.908489 INFO: [APUAPC] D6_APC_3: 0x0
9905 16:31:00.912399 INFO: [APUAPC] D7_APC_0: 0xffffffff
9906 16:31:00.915661 INFO: [APUAPC] D7_APC_1: 0xffffffff
9907 16:31:00.918451 INFO: [APUAPC] D7_APC_2: 0x3fffff
9908 16:31:00.921966 INFO: [APUAPC] D7_APC_3: 0x0
9909 16:31:00.925568 INFO: [APUAPC] D8_APC_0: 0xffffffff
9910 16:31:00.928340 INFO: [APUAPC] D8_APC_1: 0xffffffff
9911 16:31:00.931691 INFO: [APUAPC] D8_APC_2: 0x3fffff
9912 16:31:00.935053 INFO: [APUAPC] D8_APC_3: 0x0
9913 16:31:00.938222 INFO: [APUAPC] D9_APC_0: 0xffffffff
9914 16:31:00.941989 INFO: [APUAPC] D9_APC_1: 0xffffffff
9915 16:31:00.945160 INFO: [APUAPC] D9_APC_2: 0x3fffff
9916 16:31:00.948164 INFO: [APUAPC] D9_APC_3: 0x0
9917 16:31:00.951529 INFO: [APUAPC] D10_APC_0: 0xffffffff
9918 16:31:00.954676 INFO: [APUAPC] D10_APC_1: 0xffffffff
9919 16:31:00.957837 INFO: [APUAPC] D10_APC_2: 0x3fffff
9920 16:31:00.961734 INFO: [APUAPC] D10_APC_3: 0x0
9921 16:31:00.964914 INFO: [APUAPC] D11_APC_0: 0xffffffff
9922 16:31:00.968037 INFO: [APUAPC] D11_APC_1: 0xffffffff
9923 16:31:00.971227 INFO: [APUAPC] D11_APC_2: 0x3fffff
9924 16:31:00.974785 INFO: [APUAPC] D11_APC_3: 0x0
9925 16:31:00.978124 INFO: [APUAPC] D12_APC_0: 0xffffffff
9926 16:31:00.981230 INFO: [APUAPC] D12_APC_1: 0xffffffff
9927 16:31:00.984288 INFO: [APUAPC] D12_APC_2: 0x3fffff
9928 16:31:00.988016 INFO: [APUAPC] D12_APC_3: 0x0
9929 16:31:00.991358 INFO: [APUAPC] D13_APC_0: 0xffffffff
9930 16:31:00.994520 INFO: [APUAPC] D13_APC_1: 0xffffffff
9931 16:31:00.997610 INFO: [APUAPC] D13_APC_2: 0x3fffff
9932 16:31:01.000763 INFO: [APUAPC] D13_APC_3: 0x0
9933 16:31:01.004294 INFO: [APUAPC] D14_APC_0: 0xffffffff
9934 16:31:01.007363 INFO: [APUAPC] D14_APC_1: 0xffffffff
9935 16:31:01.010574 INFO: [APUAPC] D14_APC_2: 0x3fffff
9936 16:31:01.014172 INFO: [APUAPC] D14_APC_3: 0x0
9937 16:31:01.017864 INFO: [APUAPC] D15_APC_0: 0xffffffff
9938 16:31:01.020958 INFO: [APUAPC] D15_APC_1: 0xffffffff
9939 16:31:01.024113 INFO: [APUAPC] D15_APC_2: 0x3fffff
9940 16:31:01.027324 INFO: [APUAPC] D15_APC_3: 0x0
9941 16:31:01.030537 INFO: [APUAPC] APC_CON: 0x4
9942 16:31:01.033581 INFO: [NOCDAPC] D0_APC_0: 0x0
9943 16:31:01.037331 INFO: [NOCDAPC] D0_APC_1: 0x0
9944 16:31:01.040628 INFO: [NOCDAPC] D1_APC_0: 0x0
9945 16:31:01.043731 INFO: [NOCDAPC] D1_APC_1: 0xfff
9946 16:31:01.043857 INFO: [NOCDAPC] D2_APC_0: 0x0
9947 16:31:01.046992 INFO: [NOCDAPC] D2_APC_1: 0xfff
9948 16:31:01.050494 INFO: [NOCDAPC] D3_APC_0: 0x0
9949 16:31:01.053798 INFO: [NOCDAPC] D3_APC_1: 0xfff
9950 16:31:01.056923 INFO: [NOCDAPC] D4_APC_0: 0x0
9951 16:31:01.060561 INFO: [NOCDAPC] D4_APC_1: 0xfff
9952 16:31:01.063901 INFO: [NOCDAPC] D5_APC_0: 0x0
9953 16:31:01.067160 INFO: [NOCDAPC] D5_APC_1: 0xfff
9954 16:31:01.070248 INFO: [NOCDAPC] D6_APC_0: 0x0
9955 16:31:01.073530 INFO: [NOCDAPC] D6_APC_1: 0xfff
9956 16:31:01.076690 INFO: [NOCDAPC] D7_APC_0: 0x0
9957 16:31:01.076801 INFO: [NOCDAPC] D7_APC_1: 0xfff
9958 16:31:01.079841 INFO: [NOCDAPC] D8_APC_0: 0x0
9959 16:31:01.083484 INFO: [NOCDAPC] D8_APC_1: 0xfff
9960 16:31:01.086537 INFO: [NOCDAPC] D9_APC_0: 0x0
9961 16:31:01.089962 INFO: [NOCDAPC] D9_APC_1: 0xfff
9962 16:31:01.093424 INFO: [NOCDAPC] D10_APC_0: 0x0
9963 16:31:01.096450 INFO: [NOCDAPC] D10_APC_1: 0xfff
9964 16:31:01.099615 INFO: [NOCDAPC] D11_APC_0: 0x0
9965 16:31:01.103464 INFO: [NOCDAPC] D11_APC_1: 0xfff
9966 16:31:01.106629 INFO: [NOCDAPC] D12_APC_0: 0x0
9967 16:31:01.109848 INFO: [NOCDAPC] D12_APC_1: 0xfff
9968 16:31:01.112730 INFO: [NOCDAPC] D13_APC_0: 0x0
9969 16:31:01.116528 INFO: [NOCDAPC] D13_APC_1: 0xfff
9970 16:31:01.119628 INFO: [NOCDAPC] D14_APC_0: 0x0
9971 16:31:01.123042 INFO: [NOCDAPC] D14_APC_1: 0xfff
9972 16:31:01.123156 INFO: [NOCDAPC] D15_APC_0: 0x0
9973 16:31:01.126359 INFO: [NOCDAPC] D15_APC_1: 0xfff
9974 16:31:01.129623 INFO: [NOCDAPC] APC_CON: 0x4
9975 16:31:01.132614 INFO: [APUAPC] set_apusys_apc done
9976 16:31:01.136563 INFO: [DEVAPC] devapc_init done
9977 16:31:01.142745 INFO: GICv3 without legacy support detected.
9978 16:31:01.146053 INFO: ARM GICv3 driver initialized in EL3
9979 16:31:01.148988 INFO: Maximum SPI INTID supported: 639
9980 16:31:01.152590 INFO: BL31: Initializing runtime services
9981 16:31:01.158964 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9982 16:31:01.162362 INFO: SPM: enable CPC mode
9983 16:31:01.165662 INFO: mcdi ready for mcusys-off-idle and system suspend
9984 16:31:01.172120 INFO: BL31: Preparing for EL3 exit to normal world
9985 16:31:01.175173 INFO: Entry point address = 0x80000000
9986 16:31:01.175291 INFO: SPSR = 0x8
9987 16:31:01.182274
9988 16:31:01.182412
9989 16:31:01.182512
9990 16:31:01.186169 Starting depthcharge on Spherion...
9991 16:31:01.186282
9992 16:31:01.186377 Wipe memory regions:
9993 16:31:01.186467
9994 16:31:01.187233 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
9995 16:31:01.187373 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
9996 16:31:01.187491 Setting prompt string to ['asurada:']
9997 16:31:01.187601 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
9998 16:31:01.189157 [0x00000040000000, 0x00000054600000)
9999 16:31:01.310451
10000 16:31:01.310618 [0x00000054660000, 0x00000080000000)
10001 16:31:01.571268
10002 16:31:01.571436 [0x000000821a7280, 0x000000ffe64000)
10003 16:31:02.316179
10004 16:31:02.316355 [0x00000100000000, 0x00000240000000)
10005 16:31:04.206384
10006 16:31:04.209581 Initializing XHCI USB controller at 0x11200000.
10007 16:31:05.247670
10008 16:31:05.250695 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10009 16:31:05.250789
10010 16:31:05.250854
10011 16:31:05.251140 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10013 16:31:05.351490 asurada: tftpboot 192.168.201.1 14396112/tftp-deploy-jkkpexh5/kernel/image.itb 14396112/tftp-deploy-jkkpexh5/kernel/cmdline
10014 16:31:05.351704 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10015 16:31:05.351847 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10016 16:31:05.356194 tftpboot 192.168.201.1 14396112/tftp-deploy-jkkpexh5/kernel/image.itp-deploy-jkkpexh5/kernel/cmdline
10017 16:31:05.356309
10018 16:31:05.356376 Waiting for link
10019 16:31:05.514462
10020 16:31:05.514597 R8152: Initializing
10021 16:31:05.514668
10022 16:31:05.517713 Version 6 (ocp_data = 5c30)
10023 16:31:05.517791
10024 16:31:05.520829 R8152: Done initializing
10025 16:31:05.520910
10026 16:31:05.520974 Adding net device
10027 16:31:07.394514
10028 16:31:07.394649 done.
10029 16:31:07.394766
10030 16:31:07.394843 MAC: 00:24:32:30:7c:7b
10031 16:31:07.394902
10032 16:31:07.397672 Sending DHCP discover... done.
10033 16:31:07.397755
10034 16:31:10.726345 Waiting for reply... done.
10035 16:31:10.726548
10036 16:31:10.726638 Sending DHCP request... done.
10037 16:31:10.729663
10038 16:31:10.739048 Waiting for reply... done.
10039 16:31:10.739134
10040 16:31:10.739197 My ip is 192.168.201.14
10041 16:31:10.739257
10042 16:31:10.742573 The DHCP server ip is 192.168.201.1
10043 16:31:10.742654
10044 16:31:10.748977 TFTP server IP predefined by user: 192.168.201.1
10045 16:31:10.749083
10046 16:31:10.755389 Bootfile predefined by user: 14396112/tftp-deploy-jkkpexh5/kernel/image.itb
10047 16:31:10.755497
10048 16:31:10.758596 Sending tftp read request... done.
10049 16:31:10.758668
10050 16:31:10.758728 Waiting for the transfer...
10051 16:31:10.758787
10052 16:31:11.309549 00000000 ################################################################
10053 16:31:11.309710
10054 16:31:11.849817 00080000 ################################################################
10055 16:31:11.849988
10056 16:31:12.378553 00100000 ################################################################
10057 16:31:12.378722
10058 16:31:12.905549 00180000 ################################################################
10059 16:31:12.905684
10060 16:31:13.452364 00200000 ################################################################
10061 16:31:13.452500
10062 16:31:13.990658 00280000 ################################################################
10063 16:31:13.990823
10064 16:31:14.531956 00300000 ################################################################
10065 16:31:14.532118
10066 16:31:15.064147 00380000 ################################################################
10067 16:31:15.064309
10068 16:31:15.600568 00400000 ################################################################
10069 16:31:15.600738
10070 16:31:16.126739 00480000 ################################################################
10071 16:31:16.126875
10072 16:31:16.649223 00500000 ################################################################
10073 16:31:16.649394
10074 16:31:17.178065 00580000 ################################################################
10075 16:31:17.178208
10076 16:31:17.692689 00600000 ################################################################
10077 16:31:17.692859
10078 16:31:18.206902 00680000 ################################################################
10079 16:31:18.207045
10080 16:31:18.720450 00700000 ################################################################
10081 16:31:18.720618
10082 16:31:19.232174 00780000 ################################################################
10083 16:31:19.232327
10084 16:31:19.749199 00800000 ################################################################
10085 16:31:19.749365
10086 16:31:20.264404 00880000 ################################################################
10087 16:31:20.264586
10088 16:31:20.776070 00900000 ################################################################
10089 16:31:20.776234
10090 16:31:21.288516 00980000 ################################################################
10091 16:31:21.288685
10092 16:31:21.802776 00a00000 ################################################################
10093 16:31:21.802950
10094 16:31:22.316214 00a80000 ################################################################
10095 16:31:22.316405
10096 16:31:22.829638 00b00000 ################################################################
10097 16:31:22.829805
10098 16:31:23.343698 00b80000 ################################################################
10099 16:31:23.343886
10100 16:31:23.852356 00c00000 ################################################################
10101 16:31:23.852495
10102 16:31:24.365304 00c80000 ################################################################
10103 16:31:24.365486
10104 16:31:24.886383 00d00000 ################################################################
10105 16:31:24.886529
10106 16:31:25.409881 00d80000 ################################################################
10107 16:31:25.410021
10108 16:31:25.929189 00e00000 ################################################################
10109 16:31:25.929396
10110 16:31:26.452612 00e80000 ################################################################
10111 16:31:26.452763
10112 16:31:26.978073 00f00000 ################################################################
10113 16:31:26.978255
10114 16:31:27.501902 00f80000 ################################################################
10115 16:31:27.502043
10116 16:31:28.020589 01000000 ################################################################
10117 16:31:28.020753
10118 16:31:28.542025 01080000 ################################################################
10119 16:31:28.542178
10120 16:31:29.066237 01100000 ################################################################
10121 16:31:29.066401
10122 16:31:29.579740 01180000 ################################################################
10123 16:31:29.579931
10124 16:31:30.093778 01200000 ################################################################
10125 16:31:30.093944
10126 16:31:30.608423 01280000 ################################################################
10127 16:31:30.608595
10128 16:31:31.126790 01300000 ################################################################
10129 16:31:31.126921
10130 16:31:31.656628 01380000 ################################################################
10131 16:31:31.656843
10132 16:31:32.181778 01400000 ################################################################
10133 16:31:32.181939
10134 16:31:32.725127 01480000 ################################################################
10135 16:31:32.725342
10136 16:31:33.277208 01500000 ################################################################
10137 16:31:33.277383
10138 16:31:33.821620 01580000 ################################################################
10139 16:31:33.821784
10140 16:31:34.370703 01600000 ################################################################
10141 16:31:34.370843
10142 16:31:34.920892 01680000 ################################################################
10143 16:31:34.921035
10144 16:31:35.477895 01700000 ################################################################
10145 16:31:35.478034
10146 16:31:36.019691 01780000 ################################################################
10147 16:31:36.019840
10148 16:31:36.586757 01800000 ################################################################
10149 16:31:36.586938
10150 16:31:37.131091 01880000 ################################################################
10151 16:31:37.131261
10152 16:31:37.665409 01900000 ################################################################
10153 16:31:37.665575
10154 16:31:38.196687 01980000 ################################################################
10155 16:31:38.196823
10156 16:31:38.738287 01a00000 ################################################################
10157 16:31:38.738436
10158 16:31:39.284084 01a80000 ################################################################
10159 16:31:39.284218
10160 16:31:39.813222 01b00000 ################################################################
10161 16:31:39.813373
10162 16:31:40.346724 01b80000 ################################################################
10163 16:31:40.346860
10164 16:31:40.862451 01c00000 ################################################################
10165 16:31:40.862617
10166 16:31:41.378991 01c80000 ################################################################
10167 16:31:41.379149
10168 16:31:41.901321 01d00000 ################################################################
10169 16:31:41.901457
10170 16:31:42.430087 01d80000 ################################################################
10171 16:31:42.430223
10172 16:31:42.996964 01e00000 ################################################################
10173 16:31:42.997106
10174 16:31:43.540781 01e80000 ################################################################
10175 16:31:43.540912
10176 16:31:44.083951 01f00000 ################################################################
10177 16:31:44.084098
10178 16:31:44.625505 01f80000 ################################################################
10179 16:31:44.625638
10180 16:31:45.162371 02000000 ################################################################
10181 16:31:45.162547
10182 16:31:45.693945 02080000 ################################################################
10183 16:31:45.694112
10184 16:31:46.225157 02100000 ################################################################
10185 16:31:46.225334
10186 16:31:46.750003 02180000 ################################################################
10187 16:31:46.750151
10188 16:31:47.280656 02200000 ################################################################
10189 16:31:47.280823
10190 16:31:47.806493 02280000 ################################################################
10191 16:31:47.806655
10192 16:31:48.328453 02300000 ################################################################
10193 16:31:48.328590
10194 16:31:48.849094 02380000 ################################################################
10195 16:31:48.849248
10196 16:31:49.378416 02400000 ################################################################
10197 16:31:49.378568
10198 16:31:49.916849 02480000 ################################################################
10199 16:31:49.916992
10200 16:31:50.453480 02500000 ################################################################
10201 16:31:50.453615
10202 16:31:50.991907 02580000 ################################################################
10203 16:31:50.992047
10204 16:31:51.528095 02600000 ################################################################
10205 16:31:51.528232
10206 16:31:52.054686 02680000 ################################################################
10207 16:31:52.054826
10208 16:31:52.580806 02700000 ################################################################
10209 16:31:52.580986
10210 16:31:53.102245 02780000 ################################################################
10211 16:31:53.102410
10212 16:31:53.623256 02800000 ################################################################
10213 16:31:53.623425
10214 16:31:54.153316 02880000 ################################################################
10215 16:31:54.153468
10216 16:31:54.675028 02900000 ################################################################
10217 16:31:54.675211
10218 16:31:55.193305 02980000 ################################################################
10219 16:31:55.193460
10220 16:31:55.712733 02a00000 ################################################################
10221 16:31:55.712876
10222 16:31:56.238337 02a80000 ################################################################
10223 16:31:56.238481
10224 16:31:56.760853 02b00000 ################################################################
10225 16:31:56.761031
10226 16:31:57.281212 02b80000 ################################################################
10227 16:31:57.281369
10228 16:31:57.802655 02c00000 ################################################################
10229 16:31:57.802813
10230 16:31:58.318415 02c80000 ################################################################
10231 16:31:58.318560
10232 16:31:58.835897 02d00000 ################################################################
10233 16:31:58.836067
10234 16:31:59.353223 02d80000 ################################################################
10235 16:31:59.353406
10236 16:31:59.881708 02e00000 ################################################################
10237 16:31:59.881844
10238 16:32:00.412411 02e80000 ################################################################
10239 16:32:00.412583
10240 16:32:00.940620 02f00000 ################################################################
10241 16:32:00.940794
10242 16:32:01.482938 02f80000 ################################################################
10243 16:32:01.483081
10244 16:32:02.014305 03000000 ################################################################
10245 16:32:02.014445
10246 16:32:02.538497 03080000 ################################################################
10247 16:32:02.538639
10248 16:32:03.066871 03100000 ################################################################
10249 16:32:03.067020
10250 16:32:03.593785 03180000 ################################################################
10251 16:32:03.593947
10252 16:32:04.118788 03200000 ################################################################
10253 16:32:04.118955
10254 16:32:04.654331 03280000 ################################################################
10255 16:32:04.654483
10256 16:32:05.182726 03300000 ################################################################
10257 16:32:05.182867
10258 16:32:05.575729 03380000 ################################################ done.
10259 16:32:05.575900
10260 16:32:05.579049 The bootfile was 54393950 bytes long.
10261 16:32:05.579141
10262 16:32:05.582244 Sending tftp read request... done.
10263 16:32:05.582330
10264 16:32:05.582397 Waiting for the transfer...
10265 16:32:05.582460
10266 16:32:05.585556 00000000 # done.
10267 16:32:05.585643
10268 16:32:05.592234 Command line loaded dynamically from TFTP file: 14396112/tftp-deploy-jkkpexh5/kernel/cmdline
10269 16:32:05.592323
10270 16:32:05.605631 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10271 16:32:05.605728
10272 16:32:05.608418 Loading FIT.
10273 16:32:05.608503
10274 16:32:05.611740 Image ramdisk-1 has 41215903 bytes.
10275 16:32:05.611826
10276 16:32:05.611894 Image fdt-1 has 47258 bytes.
10277 16:32:05.615196
10278 16:32:05.615280 Image kernel-1 has 13128753 bytes.
10279 16:32:05.615348
10280 16:32:05.625051 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10281 16:32:05.625139
10282 16:32:05.641668 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10283 16:32:05.641774
10284 16:32:05.648315 Choosing best match conf-1 for compat google,spherion-rev2.
10285 16:32:05.652969
10286 16:32:05.657309 Connected to device vid:did:rid of 1ae0:0028:00
10287 16:32:05.664370
10288 16:32:05.667449 tpm_get_response: command 0x17b, return code 0x0
10289 16:32:05.667535
10290 16:32:05.670543 ec_init: CrosEC protocol v3 supported (256, 248)
10291 16:32:05.675113
10292 16:32:05.678403 tpm_cleanup: add release locality here.
10293 16:32:05.678489
10294 16:32:05.678556 Shutting down all USB controllers.
10295 16:32:05.681388
10296 16:32:05.681471 Removing current net device
10297 16:32:05.681538
10298 16:32:05.688172 Exiting depthcharge with code 4 at timestamp: 93824706
10299 16:32:05.688262
10300 16:32:05.691300 LZMA decompressing kernel-1 to 0x821a6718
10301 16:32:05.691385
10302 16:32:05.694662 LZMA decompressing kernel-1 to 0x40000000
10303 16:32:07.311374
10304 16:32:07.311521 jumping to kernel
10305 16:32:07.312056 end: 2.2.4 bootloader-commands (duration 00:01:06) [common]
10306 16:32:07.312164 start: 2.2.5 auto-login-action (timeout 00:03:21) [common]
10307 16:32:07.312246 Setting prompt string to ['Linux version [0-9]']
10308 16:32:07.312317 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10309 16:32:07.312385 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10310 16:32:07.394288
10311 16:32:07.397588 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10312 16:32:07.401594 start: 2.2.5.1 login-action (timeout 00:03:21) [common]
10313 16:32:07.401710 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10314 16:32:07.401785 Setting prompt string to []
10315 16:32:07.401863 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10316 16:32:07.401937 Using line separator: #'\n'#
10317 16:32:07.401997 No login prompt set.
10318 16:32:07.402058 Parsing kernel messages
10319 16:32:07.402114 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10320 16:32:07.402220 [login-action] Waiting for messages, (timeout 00:03:21)
10321 16:32:07.402286 Waiting using forced prompt support (timeout 00:01:40)
10322 16:32:07.421499 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10323 16:32:07.424908 [ 0.000000] random: crng init done
10324 16:32:07.431368 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10325 16:32:07.431451 [ 0.000000] efi: UEFI not found.
10326 16:32:07.441112 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10327 16:32:07.447518 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10328 16:32:07.457619 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10329 16:32:07.467711 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10330 16:32:07.474527 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10331 16:32:07.477739 [ 0.000000] printk: bootconsole [mtk8250] enabled
10332 16:32:07.486644 [ 0.000000] NUMA: No NUMA configuration found
10333 16:32:07.493179 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10334 16:32:07.499708 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10335 16:32:07.499794 [ 0.000000] Zone ranges:
10336 16:32:07.506210 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10337 16:32:07.509538 [ 0.000000] DMA32 empty
10338 16:32:07.515971 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10339 16:32:07.519020 [ 0.000000] Movable zone start for each node
10340 16:32:07.522903 [ 0.000000] Early memory node ranges
10341 16:32:07.529314 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10342 16:32:07.535740 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10343 16:32:07.542477 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10344 16:32:07.549122 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10345 16:32:07.555703 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10346 16:32:07.562070 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10347 16:32:07.619395 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10348 16:32:07.625895 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10349 16:32:07.632211 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10350 16:32:07.635551 [ 0.000000] psci: probing for conduit method from DT.
10351 16:32:07.642592 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10352 16:32:07.645950 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10353 16:32:07.652208 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10354 16:32:07.655982 [ 0.000000] psci: SMC Calling Convention v1.2
10355 16:32:07.662269 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10356 16:32:07.665765 [ 0.000000] Detected VIPT I-cache on CPU0
10357 16:32:07.672126 [ 0.000000] CPU features: detected: GIC system register CPU interface
10358 16:32:07.679089 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10359 16:32:07.685701 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10360 16:32:07.692406 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10361 16:32:07.698999 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10362 16:32:07.705519 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10363 16:32:07.712357 [ 0.000000] alternatives: applying boot alternatives
10364 16:32:07.715606 [ 0.000000] Fallback order for Node 0: 0
10365 16:32:07.722225 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10366 16:32:07.725619 [ 0.000000] Policy zone: Normal
10367 16:32:07.742005 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10368 16:32:07.751782 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10369 16:32:07.763335 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10370 16:32:07.773158 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10371 16:32:07.779603 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10372 16:32:07.783121 <6>[ 0.000000] software IO TLB: area num 8.
10373 16:32:07.841137 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10374 16:32:07.990079 <6>[ 0.000000] Memory: 7923808K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428960K reserved, 32768K cma-reserved)
10375 16:32:07.997200 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10376 16:32:08.003977 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10377 16:32:08.007210 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10378 16:32:08.013692 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10379 16:32:08.020147 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10380 16:32:08.023515 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10381 16:32:08.033448 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10382 16:32:08.039666 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10383 16:32:08.046532 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10384 16:32:08.053110 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10385 16:32:08.056386 <6>[ 0.000000] GICv3: 608 SPIs implemented
10386 16:32:08.060111 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10387 16:32:08.066560 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10388 16:32:08.069858 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10389 16:32:08.076331 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10390 16:32:08.089939 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10391 16:32:08.099631 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10392 16:32:08.109654 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10393 16:32:08.116951 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10394 16:32:08.130336 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10395 16:32:08.136663 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10396 16:32:08.143561 <6>[ 0.009180] Console: colour dummy device 80x25
10397 16:32:08.153159 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10398 16:32:08.159769 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10399 16:32:08.163689 <6>[ 0.029254] LSM: Security Framework initializing
10400 16:32:08.169927 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10401 16:32:08.180049 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 16:32:08.186480 <6>[ 0.051464] cblist_init_generic: Setting adjustable number of callback queues.
10403 16:32:08.193022 <6>[ 0.058908] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 16:32:08.203302 <6>[ 0.065248] cblist_init_generic: Setting adjustable number of callback queues.
10405 16:32:08.209634 <6>[ 0.072675] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 16:32:08.213001 <6>[ 0.079077] rcu: Hierarchical SRCU implementation.
10407 16:32:08.219457 <6>[ 0.084092] rcu: Max phase no-delay instances is 1000.
10408 16:32:08.226315 <6>[ 0.091106] EFI services will not be available.
10409 16:32:08.229569 <6>[ 0.096060] smp: Bringing up secondary CPUs ...
10410 16:32:08.237566 <6>[ 0.101107] Detected VIPT I-cache on CPU1
10411 16:32:08.244402 <6>[ 0.101177] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10412 16:32:08.250918 <6>[ 0.101209] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10413 16:32:08.254045 <6>[ 0.101545] Detected VIPT I-cache on CPU2
10414 16:32:08.261053 <6>[ 0.101598] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10415 16:32:08.267350 <6>[ 0.101616] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10416 16:32:08.274075 <6>[ 0.101879] Detected VIPT I-cache on CPU3
10417 16:32:08.280735 <6>[ 0.101926] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10418 16:32:08.287406 <6>[ 0.101941] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10419 16:32:08.290576 <6>[ 0.102243] CPU features: detected: Spectre-v4
10420 16:32:08.297657 <6>[ 0.102249] CPU features: detected: Spectre-BHB
10421 16:32:08.300825 <6>[ 0.102254] Detected PIPT I-cache on CPU4
10422 16:32:08.307246 <6>[ 0.102313] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10423 16:32:08.314405 <6>[ 0.102329] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10424 16:32:08.321131 <6>[ 0.102622] Detected PIPT I-cache on CPU5
10425 16:32:08.327615 <6>[ 0.102685] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10426 16:32:08.333670 <6>[ 0.102701] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10427 16:32:08.337077 <6>[ 0.102981] Detected PIPT I-cache on CPU6
10428 16:32:08.343509 <6>[ 0.103047] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10429 16:32:08.350308 <6>[ 0.103063] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10430 16:32:08.356717 <6>[ 0.103358] Detected PIPT I-cache on CPU7
10431 16:32:08.363869 <6>[ 0.103424] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10432 16:32:08.370305 <6>[ 0.103440] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10433 16:32:08.373392 <6>[ 0.103487] smp: Brought up 1 node, 8 CPUs
10434 16:32:08.380380 <6>[ 0.244969] SMP: Total of 8 processors activated.
10435 16:32:08.383394 <6>[ 0.249891] CPU features: detected: 32-bit EL0 Support
10436 16:32:08.393544 <6>[ 0.255254] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10437 16:32:08.399897 <6>[ 0.264055] CPU features: detected: Common not Private translations
10438 16:32:08.406900 <6>[ 0.270531] CPU features: detected: CRC32 instructions
10439 16:32:08.410048 <6>[ 0.275882] CPU features: detected: RCpc load-acquire (LDAPR)
10440 16:32:08.416664 <6>[ 0.281842] CPU features: detected: LSE atomic instructions
10441 16:32:08.423241 <6>[ 0.287660] CPU features: detected: Privileged Access Never
10442 16:32:08.426414 <6>[ 0.293439] CPU features: detected: RAS Extension Support
10443 16:32:08.436408 <6>[ 0.299083] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10444 16:32:08.439765 <6>[ 0.306303] CPU: All CPU(s) started at EL2
10445 16:32:08.446350 <6>[ 0.310620] alternatives: applying system-wide alternatives
10446 16:32:08.455459 <6>[ 0.321476] devtmpfs: initialized
10447 16:32:08.467993 <6>[ 0.330303] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10448 16:32:08.477540 <6>[ 0.340261] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10449 16:32:08.484067 <6>[ 0.348272] pinctrl core: initialized pinctrl subsystem
10450 16:32:08.487703 <6>[ 0.354949] DMI not present or invalid.
10451 16:32:08.494685 <6>[ 0.359359] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10452 16:32:08.504446 <6>[ 0.366206] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10453 16:32:08.510741 <6>[ 0.373798] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10454 16:32:08.521071 <6>[ 0.382017] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10455 16:32:08.524421 <6>[ 0.390260] audit: initializing netlink subsys (disabled)
10456 16:32:08.534481 <5>[ 0.395953] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10457 16:32:08.540964 <6>[ 0.396678] thermal_sys: Registered thermal governor 'step_wise'
10458 16:32:08.547470 <6>[ 0.403920] thermal_sys: Registered thermal governor 'power_allocator'
10459 16:32:08.550824 <6>[ 0.410175] cpuidle: using governor menu
10460 16:32:08.554118 <6>[ 0.421133] NET: Registered PF_QIPCRTR protocol family
10461 16:32:08.564017 <6>[ 0.426610] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10462 16:32:08.567312 <6>[ 0.433712] ASID allocator initialised with 32768 entries
10463 16:32:08.574312 <6>[ 0.440288] Serial: AMBA PL011 UART driver
10464 16:32:08.583485 <4>[ 0.449126] Trying to register duplicate clock ID: 134
10465 16:32:08.641522 <6>[ 0.510675] KASLR enabled
10466 16:32:08.656071 <6>[ 0.518397] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10467 16:32:08.662587 <6>[ 0.525414] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10468 16:32:08.669436 <6>[ 0.531902] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10469 16:32:08.675707 <6>[ 0.538907] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10470 16:32:08.682251 <6>[ 0.545394] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10471 16:32:08.688921 <6>[ 0.552400] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10472 16:32:08.695570 <6>[ 0.558886] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10473 16:32:08.702573 <6>[ 0.565891] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10474 16:32:08.705691 <6>[ 0.573417] ACPI: Interpreter disabled.
10475 16:32:08.714453 <6>[ 0.579837] iommu: Default domain type: Translated
10476 16:32:08.720631 <6>[ 0.584949] iommu: DMA domain TLB invalidation policy: strict mode
10477 16:32:08.724019 <5>[ 0.591609] SCSI subsystem initialized
10478 16:32:08.730549 <6>[ 0.595780] usbcore: registered new interface driver usbfs
10479 16:32:08.737128 <6>[ 0.601511] usbcore: registered new interface driver hub
10480 16:32:08.740043 <6>[ 0.607063] usbcore: registered new device driver usb
10481 16:32:08.747526 <6>[ 0.613160] pps_core: LinuxPPS API ver. 1 registered
10482 16:32:08.757255 <6>[ 0.618355] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10483 16:32:08.760607 <6>[ 0.627704] PTP clock support registered
10484 16:32:08.763853 <6>[ 0.631948] EDAC MC: Ver: 3.0.0
10485 16:32:08.771281 <6>[ 0.637113] FPGA manager framework
10486 16:32:08.778042 <6>[ 0.640799] Advanced Linux Sound Architecture Driver Initialized.
10487 16:32:08.781316 <6>[ 0.647573] vgaarb: loaded
10488 16:32:08.787690 <6>[ 0.650726] clocksource: Switched to clocksource arch_sys_counter
10489 16:32:08.790913 <5>[ 0.657167] VFS: Disk quotas dquot_6.6.0
10490 16:32:08.797650 <6>[ 0.661354] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10491 16:32:08.801101 <6>[ 0.668544] pnp: PnP ACPI: disabled
10492 16:32:08.809631 <6>[ 0.675303] NET: Registered PF_INET protocol family
10493 16:32:08.819159 <6>[ 0.680915] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10494 16:32:08.830504 <6>[ 0.693251] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10495 16:32:08.840813 <6>[ 0.702067] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10496 16:32:08.847381 <6>[ 0.710037] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10497 16:32:08.857025 <6>[ 0.718743] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10498 16:32:08.863435 <6>[ 0.728473] TCP: Hash tables configured (established 65536 bind 65536)
10499 16:32:08.870570 <6>[ 0.735339] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10500 16:32:08.879817 <6>[ 0.742539] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 16:32:08.886851 <6>[ 0.750242] NET: Registered PF_UNIX/PF_LOCAL protocol family
10502 16:32:08.893454 <6>[ 0.756385] RPC: Registered named UNIX socket transport module.
10503 16:32:08.896650 <6>[ 0.762539] RPC: Registered udp transport module.
10504 16:32:08.903393 <6>[ 0.767470] RPC: Registered tcp transport module.
10505 16:32:08.910007 <6>[ 0.772401] RPC: Registered tcp NFSv4.1 backchannel transport module.
10506 16:32:08.913346 <6>[ 0.779068] PCI: CLS 0 bytes, default 64
10507 16:32:08.915955 <6>[ 0.783389] Unpacking initramfs...
10508 16:32:08.932631 <6>[ 0.795244] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10509 16:32:08.942537 <6>[ 0.803875] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10510 16:32:08.945503 <6>[ 0.812692] kvm [1]: IPA Size Limit: 40 bits
10511 16:32:08.952451 <6>[ 0.817219] kvm [1]: GICv3: no GICV resource entry
10512 16:32:08.955607 <6>[ 0.822241] kvm [1]: disabling GICv2 emulation
10513 16:32:08.962544 <6>[ 0.826927] kvm [1]: GIC system register CPU interface enabled
10514 16:32:08.965872 <6>[ 0.833092] kvm [1]: vgic interrupt IRQ18
10515 16:32:08.971978 <6>[ 0.837470] kvm [1]: VHE mode initialized successfully
10516 16:32:08.978485 <5>[ 0.843761] Initialise system trusted keyrings
10517 16:32:08.985033 <6>[ 0.848550] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10518 16:32:08.992388 <6>[ 0.858572] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10519 16:32:08.999507 <5>[ 0.864955] NFS: Registering the id_resolver key type
10520 16:32:09.003057 <5>[ 0.870256] Key type id_resolver registered
10521 16:32:09.008856 <5>[ 0.874672] Key type id_legacy registered
10522 16:32:09.015500 <6>[ 0.878951] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10523 16:32:09.022164 <6>[ 0.885872] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10524 16:32:09.028604 <6>[ 0.893587] 9p: Installing v9fs 9p2000 file system support
10525 16:32:09.066146 <5>[ 0.931978] Key type asymmetric registered
10526 16:32:09.069226 <5>[ 0.936310] Asymmetric key parser 'x509' registered
10527 16:32:09.079491 <6>[ 0.941449] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10528 16:32:09.082645 <6>[ 0.949063] io scheduler mq-deadline registered
10529 16:32:09.085955 <6>[ 0.953837] io scheduler kyber registered
10530 16:32:09.104351 <6>[ 0.970710] EINJ: ACPI disabled.
10531 16:32:09.137954 <4>[ 0.997073] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 16:32:09.147731 <4>[ 1.007708] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 16:32:09.162920 <6>[ 1.028542] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10534 16:32:09.170767 <6>[ 1.036494] printk: console [ttyS0] disabled
10535 16:32:09.198634 <6>[ 1.061119] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10536 16:32:09.204941 <6>[ 1.070592] printk: console [ttyS0] enabled
10537 16:32:09.208076 <6>[ 1.070592] printk: console [ttyS0] enabled
10538 16:32:09.214635 <6>[ 1.079485] printk: bootconsole [mtk8250] disabled
10539 16:32:09.218039 <6>[ 1.079485] printk: bootconsole [mtk8250] disabled
10540 16:32:09.224722 <6>[ 1.090473] SuperH (H)SCI(F) driver initialized
10541 16:32:09.228009 <6>[ 1.095738] msm_serial: driver initialized
10542 16:32:09.242255 <6>[ 1.104701] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10543 16:32:09.252079 <6>[ 1.113246] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10544 16:32:09.258636 <6>[ 1.121790] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10545 16:32:09.268621 <6>[ 1.130420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10546 16:32:09.278339 <6>[ 1.139127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10547 16:32:09.285080 <6>[ 1.147848] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10548 16:32:09.294779 <6>[ 1.156389] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10549 16:32:09.301218 <6>[ 1.165194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10550 16:32:09.311111 <6>[ 1.173739] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10551 16:32:09.323487 <6>[ 1.189370] loop: module loaded
10552 16:32:09.330234 <6>[ 1.195443] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10553 16:32:09.352430 <4>[ 1.218749] mtk-pmic-keys: Failed to locate of_node [id: -1]
10554 16:32:09.359741 <6>[ 1.225570] megasas: 07.719.03.00-rc1
10555 16:32:09.369557 <6>[ 1.235375] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10556 16:32:09.380189 <6>[ 1.246089] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10557 16:32:09.397030 <6>[ 1.262597] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10558 16:32:09.452647 <6>[ 1.312250] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10559 16:32:10.650101 <6>[ 2.516436] Freeing initrd memory: 40248K
10560 16:32:10.661942 <6>[ 2.528212] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10561 16:32:10.672658 <6>[ 2.538981] tun: Universal TUN/TAP device driver, 1.6
10562 16:32:10.676640 <6>[ 2.545033] thunder_xcv, ver 1.0
10563 16:32:10.679256 <6>[ 2.548536] thunder_bgx, ver 1.0
10564 16:32:10.682422 <6>[ 2.552029] nicpf, ver 1.0
10565 16:32:10.693056 <6>[ 2.556034] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10566 16:32:10.696358 <6>[ 2.563510] hns3: Copyright (c) 2017 Huawei Corporation.
10567 16:32:10.702869 <6>[ 2.569115] hclge is initializing
10568 16:32:10.706679 <6>[ 2.572689] e1000: Intel(R) PRO/1000 Network Driver
10569 16:32:10.712774 <6>[ 2.577819] e1000: Copyright (c) 1999-2006 Intel Corporation.
10570 16:32:10.716296 <6>[ 2.583830] e1000e: Intel(R) PRO/1000 Network Driver
10571 16:32:10.722864 <6>[ 2.589045] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10572 16:32:10.729931 <6>[ 2.595232] igb: Intel(R) Gigabit Ethernet Network Driver
10573 16:32:10.736450 <6>[ 2.600883] igb: Copyright (c) 2007-2014 Intel Corporation.
10574 16:32:10.742839 <6>[ 2.606721] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10575 16:32:10.749542 <6>[ 2.613239] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10576 16:32:10.753070 <6>[ 2.619700] sky2: driver version 1.30
10577 16:32:10.759655 <6>[ 2.624623] usbcore: registered new device driver r8152-cfgselector
10578 16:32:10.765694 <6>[ 2.631159] usbcore: registered new interface driver r8152
10579 16:32:10.772307 <6>[ 2.636967] VFIO - User Level meta-driver version: 0.3
10580 16:32:10.779595 <6>[ 2.645179] usbcore: registered new interface driver usb-storage
10581 16:32:10.786016 <6>[ 2.651624] usbcore: registered new device driver onboard-usb-hub
10582 16:32:10.795016 <6>[ 2.660779] mt6397-rtc mt6359-rtc: registered as rtc0
10583 16:32:10.804575 <6>[ 2.666279] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:32:10 UTC (1718641930)
10584 16:32:10.808099 <6>[ 2.675878] i2c_dev: i2c /dev entries driver
10585 16:32:10.821690 <4>[ 2.687808] cpu cpu0: supply cpu not found, using dummy regulator
10586 16:32:10.828127 <4>[ 2.694240] cpu cpu1: supply cpu not found, using dummy regulator
10587 16:32:10.834824 <4>[ 2.700642] cpu cpu2: supply cpu not found, using dummy regulator
10588 16:32:10.841592 <4>[ 2.707044] cpu cpu3: supply cpu not found, using dummy regulator
10589 16:32:10.848105 <4>[ 2.713442] cpu cpu4: supply cpu not found, using dummy regulator
10590 16:32:10.854680 <4>[ 2.719856] cpu cpu5: supply cpu not found, using dummy regulator
10591 16:32:10.861497 <4>[ 2.726253] cpu cpu6: supply cpu not found, using dummy regulator
10592 16:32:10.868028 <4>[ 2.732645] cpu cpu7: supply cpu not found, using dummy regulator
10593 16:32:10.887484 <6>[ 2.753277] cpu cpu0: EM: created perf domain
10594 16:32:10.890690 <6>[ 2.758203] cpu cpu4: EM: created perf domain
10595 16:32:10.897954 <6>[ 2.763745] sdhci: Secure Digital Host Controller Interface driver
10596 16:32:10.904446 <6>[ 2.770178] sdhci: Copyright(c) Pierre Ossman
10597 16:32:10.911175 <6>[ 2.775135] Synopsys Designware Multimedia Card Interface Driver
10598 16:32:10.917499 <6>[ 2.781764] sdhci-pltfm: SDHCI platform and OF driver helper
10599 16:32:10.920769 <6>[ 2.781904] mmc0: CQHCI version 5.10
10600 16:32:10.927191 <6>[ 2.791765] ledtrig-cpu: registered to indicate activity on CPUs
10601 16:32:10.933634 <6>[ 2.798615] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10602 16:32:10.940791 <6>[ 2.805665] usbcore: registered new interface driver usbhid
10603 16:32:10.943879 <6>[ 2.811487] usbhid: USB HID core driver
10604 16:32:10.949964 <6>[ 2.815682] spi_master spi0: will run message pump with realtime priority
10605 16:32:10.995387 <6>[ 2.854892] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10606 16:32:11.013811 <6>[ 2.869878] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10607 16:32:11.017390 <6>[ 2.883836] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10608 16:32:11.024121 <6>[ 2.890135] cros-ec-spi spi0.0: Chrome EC device registered
10609 16:32:11.030621 <6>[ 2.896189] mmc0: Command Queue Engine enabled
10610 16:32:11.037790 <6>[ 2.900937] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10611 16:32:11.040928 <6>[ 2.908561] mmcblk0: mmc0:0001 DA4128 116 GiB
10612 16:32:11.051383 <6>[ 2.917207] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10613 16:32:11.058470 <6>[ 2.924817] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10614 16:32:11.068666 <6>[ 2.928911] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10615 16:32:11.071929 <6>[ 2.930695] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10616 16:32:11.078402 <6>[ 2.940637] NET: Registered PF_PACKET protocol family
10617 16:32:11.084814 <6>[ 2.945201] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 16:32:11.088132 <6>[ 2.949972] 9pnet: Installing 9P2000 support
10619 16:32:11.095019 <5>[ 2.960959] Key type dns_resolver registered
10620 16:32:11.098169 <6>[ 2.965955] registered taskstats version 1
10621 16:32:11.104602 <5>[ 2.970339] Loading compiled-in X.509 certificates
10622 16:32:11.132905 <4>[ 2.992581] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10623 16:32:11.142584 <4>[ 3.003300] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10624 16:32:11.158259 <6>[ 3.024315] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10625 16:32:11.164984 <6>[ 3.031258] xhci-mtk 11200000.usb: xHCI Host Controller
10626 16:32:11.171587 <6>[ 3.036761] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10627 16:32:11.181923 <6>[ 3.044639] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10628 16:32:11.188121 <6>[ 3.054082] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10629 16:32:11.194845 <6>[ 3.060300] xhci-mtk 11200000.usb: xHCI Host Controller
10630 16:32:11.201556 <6>[ 3.065798] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10631 16:32:11.207909 <6>[ 3.073454] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10632 16:32:11.215180 <6>[ 3.081293] hub 1-0:1.0: USB hub found
10633 16:32:11.218691 <6>[ 3.085319] hub 1-0:1.0: 1 port detected
10634 16:32:11.228638 <6>[ 3.089632] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10635 16:32:11.231845 <6>[ 3.098360] hub 2-0:1.0: USB hub found
10636 16:32:11.234851 <6>[ 3.102383] hub 2-0:1.0: 1 port detected
10637 16:32:11.242911 <6>[ 3.109428] mtk-msdc 11f70000.mmc: Got CD GPIO
10638 16:32:11.256637 <6>[ 3.119640] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10639 16:32:11.266644 <6>[ 3.128028] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10640 16:32:11.273251 <6>[ 3.136374] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10641 16:32:11.283412 <6>[ 3.144713] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10642 16:32:11.290352 <6>[ 3.153051] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10643 16:32:11.299712 <6>[ 3.161389] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10644 16:32:11.306446 <6>[ 3.169730] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10645 16:32:11.316267 <6>[ 3.178069] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10646 16:32:11.322832 <6>[ 3.186414] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10647 16:32:11.332863 <6>[ 3.194755] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10648 16:32:11.339664 <6>[ 3.203093] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10649 16:32:11.349558 <6>[ 3.211439] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10650 16:32:11.356198 <6>[ 3.219777] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10651 16:32:11.365946 <6>[ 3.228115] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10652 16:32:11.372505 <6>[ 3.236452] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10653 16:32:11.378992 <6>[ 3.245163] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10654 16:32:11.385865 <6>[ 3.252309] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10655 16:32:11.393071 <6>[ 3.259113] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10656 16:32:11.402999 <6>[ 3.265872] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10657 16:32:11.409607 <6>[ 3.272851] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10658 16:32:11.416414 <6>[ 3.279710] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10659 16:32:11.426382 <6>[ 3.288841] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10660 16:32:11.435958 <6>[ 3.297963] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10661 16:32:11.445880 <6>[ 3.307257] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10662 16:32:11.456277 <6>[ 3.316723] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10663 16:32:11.462488 <6>[ 3.326190] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10664 16:32:11.472342 <6>[ 3.335311] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10665 16:32:11.481957 <6>[ 3.344777] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10666 16:32:11.491969 <6>[ 3.353896] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10667 16:32:11.502402 <6>[ 3.363190] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10668 16:32:11.511685 <6>[ 3.373350] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10669 16:32:11.522030 <6>[ 3.385021] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10670 16:32:11.644267 <6>[ 3.507011] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10671 16:32:11.798668 <6>[ 3.664776] hub 1-1:1.0: USB hub found
10672 16:32:11.801486 <6>[ 3.669319] hub 1-1:1.0: 4 ports detected
10673 16:32:11.814222 <6>[ 3.680045] hub 1-1:1.0: USB hub found
10674 16:32:11.816847 <6>[ 3.684490] hub 1-1:1.0: 4 ports detected
10675 16:32:11.924299 <6>[ 3.787057] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10676 16:32:11.950797 <6>[ 3.817114] hub 2-1:1.0: USB hub found
10677 16:32:11.954157 <6>[ 3.821578] hub 2-1:1.0: 3 ports detected
10678 16:32:11.964592 <6>[ 3.830979] hub 2-1:1.0: USB hub found
10679 16:32:11.968161 <6>[ 3.835338] hub 2-1:1.0: 3 ports detected
10680 16:32:12.139825 <6>[ 4.003095] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10681 16:32:12.272159 <6>[ 4.138401] hub 1-1.4:1.0: USB hub found
10682 16:32:12.275453 <6>[ 4.143030] hub 1-1.4:1.0: 2 ports detected
10683 16:32:12.287383 <6>[ 4.153419] hub 1-1.4:1.0: USB hub found
10684 16:32:12.290755 <6>[ 4.157970] hub 1-1.4:1.0: 2 ports detected
10685 16:32:12.352181 <6>[ 4.215076] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10686 16:32:12.460815 <6>[ 4.323418] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10687 16:32:12.492381 <4>[ 4.355395] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10688 16:32:12.502399 <4>[ 4.364493] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10689 16:32:12.537282 <6>[ 4.403731] r8152 2-1.3:1.0 eth0: v1.12.13
10690 16:32:12.587673 <6>[ 4.450889] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10691 16:32:12.779541 <6>[ 4.642853] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10692 16:32:14.128586 <6>[ 5.995433] r8152 2-1.3:1.0 eth0: carrier on
10693 16:32:16.524266 <5>[ 6.022839] Sending DHCP requests .., OK
10694 16:32:16.530988 <6>[ 8.395183] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10695 16:32:16.534361 <6>[ 8.403494] IP-Config: Complete:
10696 16:32:16.547548 <6>[ 8.406987] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10697 16:32:16.554019 <6>[ 8.417697] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10698 16:32:16.560635 <6>[ 8.426311] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10699 16:32:16.567296 <6>[ 8.426321] nameserver0=192.168.201.1
10700 16:32:16.570286 <6>[ 8.438483] clk: Disabling unused clocks
10701 16:32:16.574125 <6>[ 8.444046] ALSA device list:
10702 16:32:16.580781 <6>[ 8.447301] No soundcards found.
10703 16:32:16.588070 <6>[ 8.454566] Freeing unused kernel memory: 8512K
10704 16:32:16.591254 <6>[ 8.459512] Run /init as init process
10705 16:32:16.621297 <6>[ 8.488014] NET: Registered PF_INET6 protocol family
10706 16:32:16.627976 <6>[ 8.494507] Segment Routing with IPv6
10707 16:32:16.631471 <6>[ 8.498496] In-situ OAM (IOAM) with IPv6
10708 16:32:16.670842 <30>[ 8.511395] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10709 16:32:16.678012 <30>[ 8.544425] systemd[1]: Detected architecture arm64.
10710 16:32:16.678166
10711 16:32:16.684365 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10712 16:32:16.684453
10713 16:32:16.696040 <30>[ 8.563053] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10714 16:32:16.816901 <30>[ 8.680731] systemd[1]: Queued start job for default target graphical.target.
10715 16:32:16.884965 <30>[ 8.748268] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10716 16:32:16.891268 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10717 16:32:16.911960 <30>[ 8.775687] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10718 16:32:16.921773 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10719 16:32:16.940383 <30>[ 8.803574] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10720 16:32:16.950402 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10721 16:32:16.968809 <30>[ 8.831893] systemd[1]: Created slice user.slice - User and Session Slice.
10722 16:32:16.975285 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10723 16:32:16.995075 <30>[ 8.855009] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10724 16:32:17.001460 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10725 16:32:17.023391 <30>[ 8.883538] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10726 16:32:17.030327 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10727 16:32:17.058480 <30>[ 8.911355] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10728 16:32:17.067907 <30>[ 8.931195] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10729 16:32:17.074411 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10730 16:32:17.091917 <30>[ 8.955296] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10731 16:32:17.101736 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10732 16:32:17.116020 <30>[ 8.978979] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10733 16:32:17.125889 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10734 16:32:17.141240 <30>[ 9.007537] systemd[1]: Reached target paths.target - Path Units.
10735 16:32:17.151056 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10736 16:32:17.168346 <30>[ 9.031480] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10737 16:32:17.174975 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10738 16:32:17.188611 <30>[ 9.055024] systemd[1]: Reached target slices.target - Slice Units.
10739 16:32:17.198504 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10740 16:32:17.213195 <30>[ 9.079531] systemd[1]: Reached target swap.target - Swaps.
10741 16:32:17.219721 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10742 16:32:17.239920 <30>[ 9.103549] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10743 16:32:17.250044 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10744 16:32:17.267857 <30>[ 9.131510] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10745 16:32:17.278086 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10746 16:32:17.297759 <30>[ 9.161090] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10747 16:32:17.307698 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10748 16:32:17.324501 <30>[ 9.187712] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10749 16:32:17.334391 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10750 16:32:17.352184 <30>[ 9.215655] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10751 16:32:17.358961 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10752 16:32:17.376515 <30>[ 9.239692] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10753 16:32:17.386494 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10754 16:32:17.404927 <30>[ 9.268432] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10755 16:32:17.414886 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10756 16:32:17.432966 <30>[ 9.296140] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10757 16:32:17.442723 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10758 16:32:17.491460 <30>[ 9.355221] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10759 16:32:17.498507 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10760 16:32:17.511151 <30>[ 9.374740] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10761 16:32:17.517911 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10762 16:32:17.539739 <30>[ 9.403345] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10763 16:32:17.546531 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10764 16:32:17.570162 <30>[ 9.427496] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10765 16:32:17.584131 <30>[ 9.447540] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10766 16:32:17.593857 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10767 16:32:17.616751 <30>[ 9.479994] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10768 16:32:17.623292 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10769 16:32:17.648541 <30>[ 9.511844] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10770 16:32:17.661719 Starting [0;1;39mmodpr<6>[ 9.522902] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10771 16:32:17.664879 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10772 16:32:17.720005 <30>[ 9.583567] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10773 16:32:17.726816 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10774 16:32:17.752947 <30>[ 9.616021] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10775 16:32:17.762219 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10776 16:32:17.789012 <30>[ 9.652136] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10777 16:32:17.795509 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10778 16:32:17.847731 <30>[ 9.711396] systemd[1]: Starting systemd-journald.service - Journal Service...
10779 16:32:17.854229 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10780 16:32:17.874411 <30>[ 9.738232] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10781 16:32:17.881398 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10782 16:32:17.911480 <30>[ 9.771975] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10783 16:32:17.918555 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10784 16:32:17.944035 <30>[ 9.807837] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10785 16:32:17.954136 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10786 16:32:17.980716 <30>[ 9.843884] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10787 16:32:17.987236 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10788 16:32:18.019625 <30>[ 9.883215] systemd[1]: Started systemd-journald.service - Journal Service.
10789 16:32:18.026177 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10790 16:32:18.052353 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10791 16:32:18.072755 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10792 16:32:18.092602 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10793 16:32:18.113612 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10794 16:32:18.138385 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10795 16:32:18.159004 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10796 16:32:18.181243 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10797 16:32:18.205569 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10798 16:32:18.230310 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10799 16:32:18.252675 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10800 16:32:18.277008 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10801 16:32:18.297568 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10802 16:32:18.315888 See 'systemctl status systemd-remount-fs.service' for details.
10803 16:32:18.341105 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10804 16:32:18.365972 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10805 16:32:18.407534 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10806 16:32:18.432982 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10807 16:32:18.451576 <46>[ 10.315303] systemd-journald[194]: Received client request to flush runtime journal.
10808 16:32:18.458627 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10809 16:32:18.480182 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10810 16:32:18.504871 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10811 16:32:18.529689 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10812 16:32:18.553170 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10813 16:32:18.573464 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10814 16:32:18.592796 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10815 16:32:18.612541 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10816 16:32:18.668330 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10817 16:32:18.698954 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10818 16:32:18.716006 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10819 16:32:18.731663 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10820 16:32:18.771601 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10821 16:32:18.792431 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10822 16:32:18.815235 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10823 16:32:18.835455 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10824 16:32:18.860412 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10825 16:32:18.896950 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10826 16:32:18.932989 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10827 16:32:18.964076 <5>[ 10.827638] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10828 16:32:18.981303 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10829 16:32:19.004346 <5>[ 10.868039] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10830 16:32:19.010693 <5>[ 10.875610] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10831 16:32:19.020642 [[0;32m OK [<4>[ 10.884236] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10832 16:32:19.027921 0m] Finished [0<6>[ 10.894296] cfg80211: failed to load regulatory.db
10833 16:32:19.034513 ;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10834 16:32:19.057807 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10835 16:32:19.077035 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10836 16:32:19.160562 <3>[ 11.024181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10837 16:32:19.170491 <3>[ 11.034395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 16:32:19.177049 <3>[ 11.042841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 16:32:19.198926 <3>[ 11.062204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 16:32:19.205146 <6>[ 11.063373] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10841 16:32:19.215018 <6>[ 11.064582] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10842 16:32:19.221350 <6>[ 11.068894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10843 16:32:19.228452 <6>[ 11.068902] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10844 16:32:19.237868 <4>[ 11.069066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10845 16:32:19.248054 <6>[ 11.069695] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10846 16:32:19.254585 <6>[ 11.069699] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10847 16:32:19.264471 <3>[ 11.070397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 16:32:19.271134 <6>[ 11.077949] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10849 16:32:19.281118 <6>[ 11.080002] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10850 16:32:19.287647 <6>[ 11.080020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10851 16:32:19.294365 <6>[ 11.080025] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10852 16:32:19.303906 <6>[ 11.080033] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10853 16:32:19.314420 <3>[ 11.086043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 16:32:19.320869 <6>[ 11.095346] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10855 16:32:19.331024 <3>[ 11.101830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 16:32:19.337501 <3>[ 11.101835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 16:32:19.344170 <3>[ 11.103456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 16:32:19.354865 <6>[ 11.107730] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10859 16:32:19.358142 <6>[ 11.110370] mc: Linux media interface: v0.10
10860 16:32:19.364926 <4>[ 11.115157] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10861 16:32:19.371490 <6>[ 11.119841] remoteproc remoteproc0: scp is available
10862 16:32:19.378027 <3>[ 11.129182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 16:32:19.384715 <6>[ 11.135297] remoteproc remoteproc0: powering up scp
10864 16:32:19.388077 <6>[ 11.135496] videodev: Linux video capture interface: v2.00
10865 16:32:19.398381 <4>[ 11.135613] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10866 16:32:19.405147 <3>[ 11.143966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 16:32:19.412038 <6>[ 11.151994] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10868 16:32:19.421941 <3>[ 11.159759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 16:32:19.425191 <6>[ 11.167543] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10870 16:32:19.434753 <6>[ 11.170610] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10871 16:32:19.441914 <3>[ 11.176782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 16:32:19.451624 <4>[ 11.195451] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10873 16:32:19.455130 <4>[ 11.195451] Fallback method does not support PEC.
10874 16:32:19.465941 <3>[ 11.201529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 16:32:19.472778 <3>[ 11.201533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 16:32:19.479116 <3>[ 11.201539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 16:32:19.489825 <3>[ 11.225010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 16:32:19.496513 <3>[ 11.229518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 16:32:19.506869 <3>[ 11.229563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 16:32:19.514085 <6>[ 11.230373] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10881 16:32:19.517011 <6>[ 11.230378] pci_bus 0000:00: root bus resource [bus 00-ff]
10882 16:32:19.523659 <6>[ 11.230382] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10883 16:32:19.534007 <6>[ 11.230385] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10884 16:32:19.540360 <6>[ 11.230411] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10885 16:32:19.546915 <6>[ 11.230424] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10886 16:32:19.554095 <6>[ 11.230487] pci 0000:00:00.0: supports D1 D2
10887 16:32:19.560781 <6>[ 11.230489] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10888 16:32:19.567314 <6>[ 11.231360] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10889 16:32:19.574028 <6>[ 11.231442] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10890 16:32:19.581222 <6>[ 11.231466] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10891 16:32:19.587982 <6>[ 11.231482] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10892 16:32:19.598005 <6>[ 11.231497] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10893 16:32:19.601086 <6>[ 11.231601] pci 0000:01:00.0: supports D1 D2
10894 16:32:19.607842 <6>[ 11.231603] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10895 16:32:19.617978 <6>[ 11.241337] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10896 16:32:19.625011 <6>[ 11.250308] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10897 16:32:19.634819 <3>[ 11.271672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 16:32:19.641183 <3>[ 11.272489] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10899 16:32:19.651724 <6>[ 11.275793] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10900 16:32:19.662173 <6>[ 11.276247] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10901 16:32:19.669233 <6>[ 11.276505] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10902 16:32:19.676165 <6>[ 11.309909] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10903 16:32:19.685978 <6>[ 11.314396] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10904 16:32:19.689294 <6>[ 11.314404] remoteproc remoteproc0: remote processor scp is now up
10905 16:32:19.699323 <6>[ 11.314431] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10906 16:32:19.702674 <6>[ 11.316696] Bluetooth: Core ver 2.22
10907 16:32:19.706622 <6>[ 11.316834] NET: Registered PF_BLUETOOTH protocol family
10908 16:32:19.713869 <6>[ 11.316837] Bluetooth: HCI device and connection manager initialized
10909 16:32:19.720054 <6>[ 11.316866] Bluetooth: HCI socket layer initialized
10910 16:32:19.723302 <6>[ 11.316872] Bluetooth: L2CAP socket layer initialized
10911 16:32:19.730055 <6>[ 11.316884] Bluetooth: SCO socket layer initialized
10912 16:32:19.737042 <6>[ 11.338312] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10913 16:32:19.746882 <6>[ 11.338568] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10914 16:32:19.756445 <6>[ 11.339834] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10915 16:32:19.766780 <3>[ 11.339957] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 16:32:19.773433 <6>[ 11.340065] usbcore: registered new interface driver uvcvideo
10917 16:32:19.779395 <6>[ 11.344266] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10918 16:32:19.789386 <6>[ 11.355211] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10919 16:32:19.795914 <6>[ 11.361129] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10920 16:32:19.802511 <6>[ 11.362129] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10921 16:32:19.812403 <3>[ 11.364879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 16:32:19.819087 <3>[ 11.365683] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10923 16:32:19.825806 <6>[ 11.370108] usbcore: registered new interface driver btusb
10924 16:32:19.835776 <4>[ 11.370692] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10925 16:32:19.842429 <3>[ 11.370703] Bluetooth: hci0: Failed to load firmware file (-2)
10926 16:32:19.849067 <3>[ 11.370707] Bluetooth: hci0: Failed to set up firmware (-2)
10927 16:32:19.858596 <4>[ 11.370712] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10928 16:32:19.865480 <6>[ 11.377304] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10929 16:32:19.875208 <3>[ 11.387267] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 16:32:19.878810 <6>[ 11.389904] pci 0000:00:00.0: PCI bridge to [bus 01]
10931 16:32:19.888679 <3>[ 11.422513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 16:32:19.898464 <6>[ 11.425153] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10933 16:32:19.905062 <3>[ 11.454194] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 16:32:19.911632 <6>[ 11.461594] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10935 16:32:19.921662 <3>[ 11.489531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 16:32:19.928122 <6>[ 11.490118] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10937 16:32:19.935046 [[0;32m OK [<6>[ 11.799462] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10938 16:32:19.941622 0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10939 16:32:19.956662 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10940 16:32:19.975602 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10941 16:32:19.985166 <6>[ 11.848795] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10942 16:32:19.991536 <6>[ 11.856326] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10943 16:32:20.015128 <6>[ 11.882389] mt7921e 0000:01:00.0: ASIC revision: 79610010
10944 16:32:20.025996 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10945 16:32:20.046886 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10946 16:32:20.092899 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10947 16:32:20.114007 [[0;32m OK [0m] Reached target [0;1;39msysi<6>[ 11.977996] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10948 16:32:20.117128 <6>[ 11.977996]
10949 16:32:20.120532 nit.target[0m - System Initialization.
10950 16:32:20.137755 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10951 16:32:20.155898 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10952 16:32:20.171272 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10953 16:32:20.187739 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10954 16:32:20.206005 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10955 16:32:20.221825 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10956 16:32:20.237072 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10957 16:32:20.288902 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10958 16:32:20.318287 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10959 16:32:20.336869 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10960 16:32:20.353990 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10961 16:32:20.386496 <6>[ 12.250391] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10962 16:32:20.396350 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10963 16:32:20.432201 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10964 16:32:20.452393 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10965 16:32:20.469843 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10966 16:32:20.508944 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10967 16:32:20.529467 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10968 16:32:20.547772 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10969 16:32:20.569188 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10970 16:32:20.586647 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10971 16:32:20.637750 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10972 16:32:20.674965 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10973 16:32:20.718592
10974 16:32:20.721920 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10975 16:32:20.722021
10976 16:32:20.725128 debian-bookworm-arm64 login: root (automatic login)
10977 16:32:20.725252
10978 16:32:20.738129 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
10979 16:32:20.738270
10980 16:32:20.744243 The programs included with the Debian GNU/Linux system are free software;
10981 16:32:20.751149 the exact distribution terms for each program are described in the
10982 16:32:20.754369 individual files in /usr/share/doc/*/copyright.
10983 16:32:20.754500
10984 16:32:20.761137 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 16:32:20.764338 permitted by applicable law.
10986 16:32:20.764738 Matched prompt #10: / #
10988 16:32:20.764950 Setting prompt string to ['/ #']
10989 16:32:20.765041 end: 2.2.5.1 login-action (duration 00:00:13) [common]
10991 16:32:20.765235 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
10992 16:32:20.765365 start: 2.2.6 expect-shell-connection (timeout 00:03:07) [common]
10993 16:32:20.765436 Setting prompt string to ['/ #']
10994 16:32:20.765497 Forcing a shell prompt, looking for ['/ #']
10996 16:32:20.815690 / #
10997 16:32:20.815856 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 16:32:20.815936 Waiting using forced prompt support (timeout 00:02:30)
10999 16:32:20.820520
11000 16:32:20.820845 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 16:32:20.820978 start: 2.2.7 export-device-env (timeout 00:03:07) [common]
11002 16:32:20.821102 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11003 16:32:20.821219 end: 2.2 depthcharge-retry (duration 00:01:53) [common]
11004 16:32:20.821361 end: 2 depthcharge-action (duration 00:01:53) [common]
11005 16:32:20.821491 start: 3 lava-test-retry (timeout 00:07:44) [common]
11006 16:32:20.821618 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
11007 16:32:20.821731 Using namespace: common
11009 16:32:20.922086 / # #
11010 16:32:20.922245 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11011 16:32:20.927476 #
11012 16:32:20.927780 Using /lava-14396112
11014 16:32:21.028149 / # export SHELL=/bin/sh
11015 16:32:21.033040 export SHELL=/bin/sh
11017 16:32:21.133614 / # . /lava-14396112/environment
11018 16:32:21.138980 . /lava-14396112/environment
11020 16:32:21.239496 / # /lava-14396112/bin/lava-test-runner /lava-14396112/0
11021 16:32:21.239658 Test shell timeout: 10s (minimum of the action and connection timeout)
11022 16:32:21.244829 /lava-14396112/bin/lava-test-runner /lava-14396112/0
11023 16:32:21.256880 <6>[ 13.124154] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11024 16:32:21.268252 + export TESTRUN_ID=0_v4l2-compliance-uvc
11025 16:32:21.271517 + cd /lava-14396112/0/tests/0_v4l2-compliance-uvc
11026 16:32:21.271646 + cat uuid
11027 16:32:21.274697 + UUID=14396112_1.5.2.3.1
11028 16:32:21.274795 + set +x
11029 16:32:21.281134 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14396112_1.5.2.3.1>
11030 16:32:21.281470 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14396112_1.5.2.3.1
11031 16:32:21.281649 Starting test lava.0_v4l2-compliance-uvc (14396112_1.5.2.3.1)
11032 16:32:21.281750 Skipping test definition patterns.
11033 16:32:21.284260 + /usr/bin/v4l2-parser.sh -d uvcvideo
11034 16:32:21.291027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11035 16:32:21.291115 device: /dev/video0
11036 16:32:21.291351 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11038 16:32:27.729735 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11039 16:32:27.740738 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11040 16:32:27.748800
11041 16:32:27.767718 Compliance test for uvcvideo device /dev/video0:
11042 16:32:27.776984
11043 16:32:27.792334 Driver Info:
11044 16:32:27.801845 Driver name : uvcvideo
11045 16:32:27.815858 Card type : HD User Facing: HD User Facing
11046 16:32:27.827918 Bus info : usb-11200000.usb-1.4.1
11047 16:32:27.834076 Driver version : 6.1.92
11048 16:32:27.844209 Capabilities : 0x84a00001
11049 16:32:27.856801 Metadata Capture
11050 16:32:27.871007 Streaming
11051 16:32:27.881251 Extended Pix Format
11052 16:32:27.892220 Device Capabilities
11053 16:32:27.906652 Device Caps : 0x04200001
11054 16:32:27.919591 Streaming
11055 16:32:27.935743 Extended Pix Format
11056 16:32:27.945435 Media Driver Info:
11057 16:32:27.955921 Driver name : uvcvideo
11058 16:32:27.970618 Model : HD User Facing: HD User Facing
11059 16:32:27.980371 Serial : 200901010001
11060 16:32:27.994192 Bus info : usb-11200000.usb-1.4.1
11061 16:32:28.007000 Media version : 6.1.92
11062 16:32:28.021201 Hardware revision: 0x00009758 (38744)
11063 16:32:28.029524 Driver version : 6.1.92
11064 16:32:28.038526 Interface Info:
11065 16:32:28.058150 <LAVA_SIGNAL_TESTSET START Interface-Info>
11066 16:32:28.058449 Received signal: <TESTSET> START Interface-Info
11067 16:32:28.058533 Starting test_set Interface-Info
11068 16:32:28.061230 ID : 0x03000002
11069 16:32:28.068553 Type : V4L Video
11070 16:32:28.080805 Entity Info:
11071 16:32:28.089169 <LAVA_SIGNAL_TESTSET STOP>
11072 16:32:28.089474 Received signal: <TESTSET> STOP
11073 16:32:28.089551 Closing test_set Interface-Info
11074 16:32:28.099744 <LAVA_SIGNAL_TESTSET START Entity-Info>
11075 16:32:28.100008 Received signal: <TESTSET> START Entity-Info
11076 16:32:28.100079 Starting test_set Entity-Info
11077 16:32:28.102889 ID : 0x00000001 (1)
11078 16:32:28.115973 Name : HD User Facing: HD User Facing
11079 16:32:28.125113 Function : V4L2 I/O
11080 16:32:28.139798 Flags : default
11081 16:32:28.149918 Pad 0x01000007 : 0: Sink
11082 16:32:28.172456 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11083 16:32:28.172584
11084 16:32:28.187913 Required ioctls:
11085 16:32:28.199296 <LAVA_SIGNAL_TESTSET STOP>
11086 16:32:28.199593 Received signal: <TESTSET> STOP
11087 16:32:28.199664 Closing test_set Entity-Info
11088 16:32:28.209166 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11089 16:32:28.209460 Received signal: <TESTSET> START Required-ioctls
11090 16:32:28.209533 Starting test_set Required-ioctls
11091 16:32:28.211786 test MC information (see 'Media Driver Info' above): OK
11092 16:32:28.236961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11093 16:32:28.237296 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11095 16:32:28.240202 test VIDIOC_QUERYCAP: OK
11096 16:32:28.260186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11097 16:32:28.260493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11099 16:32:28.263386 test invalid ioctls: OK
11100 16:32:28.289908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11101 16:32:28.290062
11102 16:32:28.290306 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11104 16:32:28.300908 Allow for multiple opens:
11105 16:32:28.307417 <LAVA_SIGNAL_TESTSET STOP>
11106 16:32:28.307684 Received signal: <TESTSET> STOP
11107 16:32:28.307755 Closing test_set Required-ioctls
11108 16:32:28.316575 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11109 16:32:28.316859 Received signal: <TESTSET> START Allow-for-multiple-opens
11110 16:32:28.316950 Starting test_set Allow-for-multiple-opens
11111 16:32:28.319859 test second /dev/video0 open: OK
11112 16:32:28.340878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11113 16:32:28.341159 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11115 16:32:28.344277 test VIDIOC_QUERYCAP: OK
11116 16:32:28.366312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11117 16:32:28.366593 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11119 16:32:28.369535 test VIDIOC_G/S_PRIORITY: OK
11120 16:32:28.390440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11121 16:32:28.390736 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11123 16:32:28.393635 test for unlimited opens: OK
11124 16:32:28.416533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11125 16:32:28.416662
11126 16:32:28.416902 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11128 16:32:28.426129 Debug ioctls:
11129 16:32:28.432724 <LAVA_SIGNAL_TESTSET STOP>
11130 16:32:28.432986 Received signal: <TESTSET> STOP
11131 16:32:28.433056 Closing test_set Allow-for-multiple-opens
11132 16:32:28.442440 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11133 16:32:28.442706 Received signal: <TESTSET> START Debug-ioctls
11134 16:32:28.442778 Starting test_set Debug-ioctls
11135 16:32:28.445489 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11136 16:32:28.467545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11137 16:32:28.467851 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11139 16:32:28.474295 test VIDIOC_LOG_STATUS: OK (Not Supported)
11140 16:32:28.491397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11141 16:32:28.491511
11142 16:32:28.491763 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11144 16:32:28.502019 Input ioctls:
11145 16:32:28.512145 <LAVA_SIGNAL_TESTSET STOP>
11146 16:32:28.512446 Received signal: <TESTSET> STOP
11147 16:32:28.512521 Closing test_set Debug-ioctls
11148 16:32:28.524160 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11149 16:32:28.524527 Received signal: <TESTSET> START Input-ioctls
11150 16:32:28.524658 Starting test_set Input-ioctls
11151 16:32:28.527563 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11152 16:32:28.552476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11153 16:32:28.552796 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11155 16:32:28.555828 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11156 16:32:28.574702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11157 16:32:28.575039 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11159 16:32:28.580914 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11160 16:32:28.600321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11161 16:32:28.600714 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11163 16:32:28.607098 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11164 16:32:28.630210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11165 16:32:28.630556 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11167 16:32:28.633558 test VIDIOC_G/S/ENUMINPUT: OK
11168 16:32:28.653683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11169 16:32:28.654030 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11171 16:32:28.656668 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11172 16:32:28.680088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11173 16:32:28.680408 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11175 16:32:28.683312 Inputs: 1 Audio Inputs: 0 Tuners: 0
11176 16:32:28.689245
11177 16:32:28.706416 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11178 16:32:28.727993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11179 16:32:28.728314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11181 16:32:28.734898 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11182 16:32:28.758434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11183 16:32:28.758775 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11185 16:32:28.765027 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11186 16:32:28.782042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11187 16:32:28.782375 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11189 16:32:28.788408 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11190 16:32:28.806656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11191 16:32:28.806999 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11193 16:32:28.813078 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11194 16:32:28.835081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11195 16:32:28.835212
11196 16:32:28.835459 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11198 16:32:28.854698 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11199 16:32:28.878085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11200 16:32:28.878424 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11202 16:32:28.884529 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11203 16:32:28.907433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11204 16:32:28.907774 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11206 16:32:28.910667 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11207 16:32:28.931782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11208 16:32:28.932091 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11210 16:32:28.935216 test VIDIOC_G/S_EDID: OK (Not Supported)
11211 16:32:28.955805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11212 16:32:28.955961
11213 16:32:28.956243 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11215 16:32:28.966565 Control ioctls (Input 0):
11216 16:32:28.974409 <LAVA_SIGNAL_TESTSET STOP>
11217 16:32:28.974774 Received signal: <TESTSET> STOP
11218 16:32:28.974895 Closing test_set Input-ioctls
11219 16:32:28.984131 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11220 16:32:28.984469 Received signal: <TESTSET> START Control-ioctls-Input-0
11221 16:32:28.984552 Starting test_set Control-ioctls-Input-0
11222 16:32:28.987393 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11223 16:32:29.012747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11224 16:32:29.012914 test VIDIOC_QUERYCTRL: OK
11225 16:32:29.013199 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11227 16:32:29.034795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11228 16:32:29.035140 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11230 16:32:29.037875 test VIDIOC_G/S_CTRL: OK
11231 16:32:29.058817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11232 16:32:29.059175 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11234 16:32:29.062064 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11235 16:32:29.081966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11236 16:32:29.082339 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11238 16:32:29.088399 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11239 16:32:29.111618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11240 16:32:29.111964 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11242 16:32:29.114623 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11243 16:32:29.133503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11244 16:32:29.133847 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11246 16:32:29.136722 Standard Controls: 16 Private Controls: 0
11247 16:32:29.144933
11248 16:32:29.156578 Format ioctls (Input 0):
11249 16:32:29.166971 <LAVA_SIGNAL_TESTSET STOP>
11250 16:32:29.167328 Received signal: <TESTSET> STOP
11251 16:32:29.167444 Closing test_set Control-ioctls-Input-0
11252 16:32:29.176713 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11253 16:32:29.177067 Received signal: <TESTSET> START Format-ioctls-Input-0
11254 16:32:29.177181 Starting test_set Format-ioctls-Input-0
11255 16:32:29.179896 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11256 16:32:29.207964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11257 16:32:29.208303 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11259 16:32:29.211110 test VIDIOC_G/S_PARM: OK
11260 16:32:29.230835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11261 16:32:29.231181 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11263 16:32:29.233994 test VIDIOC_G_FBUF: OK (Not Supported)
11264 16:32:29.260359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11265 16:32:29.260679 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11267 16:32:29.263485 test VIDIOC_G_FMT: OK
11268 16:32:29.284489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11269 16:32:29.284801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11271 16:32:29.287880 test VIDIOC_TRY_FMT: OK
11272 16:32:29.308123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11273 16:32:29.308451 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11275 16:32:29.314565 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11276 16:32:29.322308 test VIDIOC_S_FMT: OK
11277 16:32:29.351195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11278 16:32:29.351550 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11280 16:32:29.354405 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11281 16:32:29.378225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11282 16:32:29.378564 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11284 16:32:29.381203 test Cropping: OK (Not Supported)
11285 16:32:29.402801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11286 16:32:29.403126 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11288 16:32:29.406245 test Composing: OK (Not Supported)
11289 16:32:29.427497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11290 16:32:29.427832 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11292 16:32:29.430565 test Scaling: OK (Not Supported)
11293 16:32:29.456953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11294 16:32:29.457128
11295 16:32:29.457426 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11297 16:32:29.465766 Codec ioctls (Input 0):
11298 16:32:29.474016 <LAVA_SIGNAL_TESTSET STOP>
11299 16:32:29.474361 Received signal: <TESTSET> STOP
11300 16:32:29.474477 Closing test_set Format-ioctls-Input-0
11301 16:32:29.483069 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11302 16:32:29.483411 Received signal: <TESTSET> START Codec-ioctls-Input-0
11303 16:32:29.483527 Starting test_set Codec-ioctls-Input-0
11304 16:32:29.486192 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11305 16:32:29.506965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11306 16:32:29.507307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11308 16:32:29.513247 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11309 16:32:29.535530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11310 16:32:29.535838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11312 16:32:29.542402 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11313 16:32:29.560347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11314 16:32:29.560460
11315 16:32:29.560704 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11317 16:32:29.570084 Buffer ioctls (Input 0):
11318 16:32:29.577271 <LAVA_SIGNAL_TESTSET STOP>
11319 16:32:29.577569 Received signal: <TESTSET> STOP
11320 16:32:29.577655 Closing test_set Codec-ioctls-Input-0
11321 16:32:29.586903 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11322 16:32:29.587209 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11323 16:32:29.587314 Starting test_set Buffer-ioctls-Input-0
11324 16:32:29.590144 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11325 16:32:29.614969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11326 16:32:29.615305 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11328 16:32:29.618134 test CREATE_BUFS maximum buffers: OK
11329 16:32:29.634530 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11331 16:32:29.638126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11332 16:32:29.638245 test VIDIOC_EXPBUF: OK
11333 16:32:29.659210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11334 16:32:29.659562 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11336 16:32:29.663431 test Requests: OK (Not Supported)
11337 16:32:29.682543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11338 16:32:29.682684
11339 16:32:29.682926 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11341 16:32:29.692270 Test input 0:
11342 16:32:29.708402
11343 16:32:29.719303 Streaming ioctls:
11344 16:32:29.726930 <LAVA_SIGNAL_TESTSET STOP>
11345 16:32:29.727220 Received signal: <TESTSET> STOP
11346 16:32:29.727296 Closing test_set Buffer-ioctls-Input-0
11347 16:32:29.736707 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11348 16:32:29.736968 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11349 16:32:29.737044 Starting test_set Streaming-ioctls_Test-input-0
11350 16:32:29.739958 test read/write: OK (Not Supported)
11351 16:32:29.760514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11352 16:32:29.760803 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11354 16:32:29.763515 test blocking wait: OK
11355 16:32:29.789434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11356 16:32:29.789740 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11358 16:32:29.795976 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11359 16:32:29.799337 test MMAP (no poll): FAIL
11360 16:32:29.825579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11361 16:32:29.825881 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11363 16:32:29.832175 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11364 16:32:29.837279 test MMAP (select): FAIL
11365 16:32:29.865731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11366 16:32:29.866014 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11368 16:32:29.872210 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11369 16:32:29.877297 test MMAP (epoll): FAIL
11370 16:32:29.902073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11371 16:32:29.902211
11372 16:32:29.902457 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11374 16:32:29.918781
11375 16:32:30.104140
11376 16:32:30.115769 test USERPTR (no poll): OK
11377 16:32:30.140660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11378 16:32:30.140788
11379 16:32:30.141036 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11381 16:32:30.152854
11382 16:32:30.332932
11383 16:32:30.341135 test USERPTR (select): OK
11384 16:32:30.365253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11385 16:32:30.365554 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11387 16:32:30.372154 test DMABUF: Cannot test, specify --expbuf-device
11388 16:32:30.376062
11389 16:32:30.394517 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11390 16:32:30.397646 <LAVA_TEST_RUNNER EXIT>
11391 16:32:30.397926 ok: lava_test_shell seems to have completed
11392 16:32:30.398039 Marking unfinished test run as failed
11394 16:32:30.400191 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11395 16:32:30.400360 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11396 16:32:30.400454 end: 3 lava-test-retry (duration 00:00:10) [common]
11397 16:32:30.400565 start: 4 finalize (timeout 00:07:34) [common]
11398 16:32:30.400663 start: 4.1 power-off (timeout 00:00:30) [common]
11399 16:32:30.400958 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11400 16:32:30.599457 >> Command sent successfully.
11401 16:32:30.602057 Returned 0 in 0 seconds
11402 16:32:30.702457 end: 4.1 power-off (duration 00:00:00) [common]
11404 16:32:30.702792 start: 4.2 read-feedback (timeout 00:07:34) [common]
11405 16:32:30.703060 Listened to connection for namespace 'common' for up to 1s
11406 16:32:31.703980 Finalising connection for namespace 'common'
11407 16:32:31.704178 Disconnecting from shell: Finalise
11408 16:32:31.704263 / #
11409 16:32:31.804659 end: 4.2 read-feedback (duration 00:00:01) [common]
11410 16:32:31.804849 end: 4 finalize (duration 00:00:01) [common]
11411 16:32:31.804967 Cleaning after the job
11412 16:32:31.805069 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/ramdisk
11413 16:32:31.809398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/kernel
11414 16:32:31.821970 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/dtb
11415 16:32:31.822217 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396112/tftp-deploy-jkkpexh5/modules
11416 16:32:31.827630 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396112
11417 16:32:31.894044 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396112
11418 16:32:31.894204 Job finished correctly