Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 86
1 11:31:22.327623 lava-dispatcher, installed at version: 2024.05
2 11:31:22.327822 start: 0 validate
3 11:31:22.327981 Start time: 2024-07-17 11:31:22.327972+00:00 (UTC)
4 11:31:22.328113 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:31:22.328410 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 11:31:22.590492 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:31:22.590657 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:32:17.619368 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:32:17.620194 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:32:17.882097 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:32:17.882244 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:32:18.389899 validate duration: 56.06
14 11:32:18.390202 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:32:18.390314 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:32:18.390414 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:32:18.390582 Not decompressing ramdisk as can be used compressed.
18 11:32:18.390679 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 11:32:18.390747 saving as /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/ramdisk/rootfs.cpio.gz
20 11:32:18.390818 total size: 8181887 (7 MB)
21 11:32:18.649767 progress 0 % (0 MB)
22 11:32:18.652113 progress 5 % (0 MB)
23 11:32:18.654182 progress 10 % (0 MB)
24 11:32:18.656481 progress 15 % (1 MB)
25 11:32:18.658559 progress 20 % (1 MB)
26 11:32:18.660784 progress 25 % (1 MB)
27 11:32:18.662924 progress 30 % (2 MB)
28 11:32:18.665134 progress 35 % (2 MB)
29 11:32:18.667232 progress 40 % (3 MB)
30 11:32:18.669494 progress 45 % (3 MB)
31 11:32:18.671822 progress 50 % (3 MB)
32 11:32:18.674062 progress 55 % (4 MB)
33 11:32:18.676109 progress 60 % (4 MB)
34 11:32:18.678349 progress 65 % (5 MB)
35 11:32:18.680582 progress 70 % (5 MB)
36 11:32:18.682958 progress 75 % (5 MB)
37 11:32:18.685259 progress 80 % (6 MB)
38 11:32:18.687521 progress 85 % (6 MB)
39 11:32:18.689532 progress 90 % (7 MB)
40 11:32:18.692013 progress 95 % (7 MB)
41 11:32:18.694277 progress 100 % (7 MB)
42 11:32:18.694551 7 MB downloaded in 0.30 s (25.69 MB/s)
43 11:32:18.694730 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:32:18.694964 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:32:18.695045 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:32:18.695128 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:32:18.695387 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:32:18.695454 saving as /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/kernel/Image
50 11:32:18.695523 total size: 54813184 (52 MB)
51 11:32:18.695577 No compression specified
52 11:32:18.696565 progress 0 % (0 MB)
53 11:32:18.711385 progress 5 % (2 MB)
54 11:32:18.725688 progress 10 % (5 MB)
55 11:32:18.739921 progress 15 % (7 MB)
56 11:32:18.754152 progress 20 % (10 MB)
57 11:32:18.768482 progress 25 % (13 MB)
58 11:32:18.783064 progress 30 % (15 MB)
59 11:32:18.797577 progress 35 % (18 MB)
60 11:32:18.811993 progress 40 % (20 MB)
61 11:32:18.826233 progress 45 % (23 MB)
62 11:32:18.840628 progress 50 % (26 MB)
63 11:32:18.854797 progress 55 % (28 MB)
64 11:32:18.868837 progress 60 % (31 MB)
65 11:32:18.883535 progress 65 % (34 MB)
66 11:32:18.897776 progress 70 % (36 MB)
67 11:32:18.912400 progress 75 % (39 MB)
68 11:32:18.927315 progress 80 % (41 MB)
69 11:32:18.941492 progress 85 % (44 MB)
70 11:32:18.956041 progress 90 % (47 MB)
71 11:32:18.971602 progress 95 % (49 MB)
72 11:32:18.986213 progress 100 % (52 MB)
73 11:32:18.986488 52 MB downloaded in 0.29 s (179.66 MB/s)
74 11:32:18.986632 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:32:18.986869 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:32:18.986948 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:32:18.987023 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:32:18.987134 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
80 11:32:18.987198 saving as /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
81 11:32:18.987252 total size: 57695 (0 MB)
82 11:32:18.987305 No compression specified
83 11:32:18.988287 progress 56 % (0 MB)
84 11:32:18.988617 progress 100 % (0 MB)
85 11:32:18.988848 0 MB downloaded in 0.00 s (34.53 MB/s)
86 11:32:18.988976 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:32:18.989225 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:32:18.989333 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:32:18.989408 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:32:18.989511 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:32:18.989573 saving as /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/modules/modules.tar
93 11:32:18.989626 total size: 8610184 (8 MB)
94 11:32:18.989680 Using unxz to decompress xz
95 11:32:18.991145 progress 0 % (0 MB)
96 11:32:19.012698 progress 5 % (0 MB)
97 11:32:19.037416 progress 10 % (0 MB)
98 11:32:19.061913 progress 15 % (1 MB)
99 11:32:19.087468 progress 20 % (1 MB)
100 11:32:19.111326 progress 25 % (2 MB)
101 11:32:19.135300 progress 30 % (2 MB)
102 11:32:19.158289 progress 35 % (2 MB)
103 11:32:19.186430 progress 40 % (3 MB)
104 11:32:19.211420 progress 45 % (3 MB)
105 11:32:19.235973 progress 50 % (4 MB)
106 11:32:19.261248 progress 55 % (4 MB)
107 11:32:19.286144 progress 60 % (4 MB)
108 11:32:19.310485 progress 65 % (5 MB)
109 11:32:19.337744 progress 70 % (5 MB)
110 11:32:19.366091 progress 75 % (6 MB)
111 11:32:19.396164 progress 80 % (6 MB)
112 11:32:19.421379 progress 85 % (7 MB)
113 11:32:19.446471 progress 90 % (7 MB)
114 11:32:19.471524 progress 95 % (7 MB)
115 11:32:19.495995 progress 100 % (8 MB)
116 11:32:19.501916 8 MB downloaded in 0.51 s (16.03 MB/s)
117 11:32:19.502100 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:32:19.502319 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:32:19.502402 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:32:19.502479 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:32:19.502556 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:32:19.502629 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:32:19.502788 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7
125 11:32:19.502905 makedir: /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin
126 11:32:19.502996 makedir: /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/tests
127 11:32:19.503109 makedir: /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/results
128 11:32:19.503230 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-add-keys
129 11:32:19.503387 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-add-sources
130 11:32:19.503510 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-background-process-start
131 11:32:19.503662 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-background-process-stop
132 11:32:19.503820 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-common-functions
133 11:32:19.503968 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-echo-ipv4
134 11:32:19.504118 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-install-packages
135 11:32:19.504263 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-installed-packages
136 11:32:19.504406 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-os-build
137 11:32:19.504548 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-probe-channel
138 11:32:19.504664 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-probe-ip
139 11:32:19.504790 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-target-ip
140 11:32:19.504904 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-target-mac
141 11:32:19.505037 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-target-storage
142 11:32:19.505208 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-case
143 11:32:19.505339 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-event
144 11:32:19.505455 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-feedback
145 11:32:19.505577 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-raise
146 11:32:19.505690 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-reference
147 11:32:19.505803 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-runner
148 11:32:19.505917 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-set
149 11:32:19.506038 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-test-shell
150 11:32:19.506154 Updating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-install-packages (oe)
151 11:32:19.506295 Updating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/bin/lava-installed-packages (oe)
152 11:32:19.506415 Creating /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/environment
153 11:32:19.506514 LAVA metadata
154 11:32:19.506580 - LAVA_JOB_ID=14864604
155 11:32:19.506638 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:32:19.506736 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:32:19.506797 skipped lava-vland-overlay
158 11:32:19.506866 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:32:19.506946 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:32:19.507029 skipped lava-multinode-overlay
161 11:32:19.507122 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:32:19.507213 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:32:19.507280 Loading test definitions
164 11:32:19.507356 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:32:19.507420 Using /lava-14864604 at stage 0
166 11:32:19.507719 uuid=14864604_1.5.2.3.1 testdef=None
167 11:32:19.507800 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:32:19.507876 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:32:19.508493 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:32:19.508693 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:32:19.509399 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:32:19.509611 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:32:19.510185 runner path: /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/0/tests/0_dmesg test_uuid 14864604_1.5.2.3.1
176 11:32:19.510334 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:32:19.510526 Creating lava-test-runner.conf files
179 11:32:19.510584 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864604/lava-overlay-utfyk7n7/lava-14864604/0 for stage 0
180 11:32:19.510663 - 0_dmesg
181 11:32:19.510765 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:32:19.510882 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:32:19.517776 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:32:19.517892 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:32:19.517973 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:32:19.518063 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:32:19.518180 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:32:19.761463 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 11:32:19.761651 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 11:32:19.761765 extracting modules file /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864604/extract-overlay-ramdisk-ecxnrxe6/ramdisk
191 11:32:19.997667 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:32:19.997819 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:32:19.997906 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864604/compress-overlay-j19oeowi/overlay-1.5.2.4.tar.gz to ramdisk
194 11:32:19.997969 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864604/compress-overlay-j19oeowi/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864604/extract-overlay-ramdisk-ecxnrxe6/ramdisk
195 11:32:20.004383 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:32:20.004506 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:32:20.004590 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:32:20.004666 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:32:20.004734 Building ramdisk /var/lib/lava/dispatcher/tmp/14864604/extract-overlay-ramdisk-ecxnrxe6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864604/extract-overlay-ramdisk-ecxnrxe6/ramdisk
200 11:32:20.469117 >> 144748 blocks
201 11:32:22.849031 rename /var/lib/lava/dispatcher/tmp/14864604/extract-overlay-ramdisk-ecxnrxe6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/ramdisk/ramdisk.cpio.gz
202 11:32:22.849271 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 11:32:22.849406 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 11:32:22.849528 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 11:32:22.849645 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/kernel/Image']
206 11:32:38.920974 Returned 0 in 16 seconds
207 11:32:38.921238 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/kernel/image.itb
208 11:32:39.452328 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:32:39.452484 output: Created: Wed Jul 17 12:32:39 2024
210 11:32:39.452574 output: Image 0 (kernel-1)
211 11:32:39.452649 output: Description:
212 11:32:39.452722 output: Created: Wed Jul 17 12:32:39 2024
213 11:32:39.452794 output: Type: Kernel Image
214 11:32:39.452866 output: Compression: lzma compressed
215 11:32:39.452939 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:32:39.453011 output: Architecture: AArch64
217 11:32:39.453081 output: OS: Linux
218 11:32:39.453175 output: Load Address: 0x00000000
219 11:32:39.453247 output: Entry Point: 0x00000000
220 11:32:39.453318 output: Hash algo: crc32
221 11:32:39.453388 output: Hash value: 83448d17
222 11:32:39.453461 output: Image 1 (fdt-1)
223 11:32:39.453531 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
224 11:32:39.453602 output: Created: Wed Jul 17 12:32:39 2024
225 11:32:39.453673 output: Type: Flat Device Tree
226 11:32:39.453742 output: Compression: uncompressed
227 11:32:39.453813 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
228 11:32:39.453882 output: Architecture: AArch64
229 11:32:39.453952 output: Hash algo: crc32
230 11:32:39.454021 output: Hash value: a9713552
231 11:32:39.454090 output: Image 2 (ramdisk-1)
232 11:32:39.454157 output: Description: unavailable
233 11:32:39.454225 output: Created: Wed Jul 17 12:32:39 2024
234 11:32:39.454293 output: Type: RAMDisk Image
235 11:32:39.454361 output: Compression: uncompressed
236 11:32:39.454429 output: Data Size: 21355925 Bytes = 20855.40 KiB = 20.37 MiB
237 11:32:39.454499 output: Architecture: AArch64
238 11:32:39.454567 output: OS: Linux
239 11:32:39.454636 output: Load Address: unavailable
240 11:32:39.454706 output: Entry Point: unavailable
241 11:32:39.454775 output: Hash algo: crc32
242 11:32:39.454843 output: Hash value: 45c9fa3a
243 11:32:39.454911 output: Default Configuration: 'conf-1'
244 11:32:39.454980 output: Configuration 0 (conf-1)
245 11:32:39.455048 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
246 11:32:39.455118 output: Kernel: kernel-1
247 11:32:39.455185 output: Init Ramdisk: ramdisk-1
248 11:32:39.455253 output: FDT: fdt-1
249 11:32:39.455322 output: Loadables: kernel-1
250 11:32:39.455392 output:
251 11:32:39.455529 end: 1.5.8.1 prepare-fit (duration 00:00:17) [common]
252 11:32:39.455635 end: 1.5.8 prepare-kernel (duration 00:00:17) [common]
253 11:32:39.455742 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:32:39.455845 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:32:39.455927 No LXC device requested
256 11:32:39.456025 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:32:39.456129 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:32:39.456229 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:32:39.456312 Checking files for TFTP limit of 4294967296 bytes.
260 11:32:39.456816 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:32:39.456936 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:32:39.457046 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:32:39.457178 substitutions:
264 11:32:39.457263 - {DTB}: 14864604/tftp-deploy-5u8il0ve/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
265 11:32:39.457343 - {INITRD}: 14864604/tftp-deploy-5u8il0ve/ramdisk/ramdisk.cpio.gz
266 11:32:39.457419 - {KERNEL}: 14864604/tftp-deploy-5u8il0ve/kernel/Image
267 11:32:39.457493 - {LAVA_MAC}: None
268 11:32:39.457566 - {PRESEED_CONFIG}: None
269 11:32:39.457639 - {PRESEED_LOCAL}: None
270 11:32:39.457711 - {RAMDISK}: 14864604/tftp-deploy-5u8il0ve/ramdisk/ramdisk.cpio.gz
271 11:32:39.457794 - {ROOT_PART}: None
272 11:32:39.457866 - {ROOT}: None
273 11:32:39.457939 - {SERVER_IP}: 192.168.201.1
274 11:32:39.458011 - {TEE}: None
275 11:32:39.458080 Parsed boot commands:
276 11:32:39.458148 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:32:39.458346 Parsed boot commands: tftpboot 192.168.201.1 14864604/tftp-deploy-5u8il0ve/kernel/image.itb 14864604/tftp-deploy-5u8il0ve/kernel/cmdline
278 11:32:39.458461 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:32:39.458564 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:32:39.458668 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:32:39.458772 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:32:39.458853 Not connected, no need to disconnect.
283 11:32:39.458952 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:32:39.459051 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:32:39.459134 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-3'
286 11:32:39.462910 Setting prompt string to ['lava-test: # ']
287 11:32:39.463363 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:32:39.463509 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:32:39.463638 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:32:39.463759 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:32:39.464035 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3', '--port=1', '--command=reboot']
292 11:32:48.624543 >> Command sent successfully.
293 11:32:48.638161 Returned 0 in 9 seconds
294 11:32:48.638831 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:32:48.640225 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:32:48.640765 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:32:48.641238 Setting prompt string to 'Starting depthcharge on Juniper...'
299 11:32:48.641617 Changing prompt to 'Starting depthcharge on Juniper...'
300 11:32:48.642010 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
301 11:32:48.643903 [Enter `^Ec?' for help]
302 11:32:54.587291 [DL] 00000000 00000000 010701
303 11:32:54.591737
304 11:32:54.592276
305 11:32:54.592559 F0: 102B 0000
306 11:32:54.592928
307 11:32:54.593305 F3: 1006 0033 [0200]
308 11:32:54.595342
309 11:32:54.595768 F3: 4001 00E0 [0200]
310 11:32:54.596060
311 11:32:54.596308 F3: 0000 0000
312 11:32:54.596548
313 11:32:54.598510 V0: 0000 0000 [0001]
314 11:32:54.598782
315 11:32:54.599024 00: 1027 0002
316 11:32:54.599286
317 11:32:54.602457 01: 0000 0000
318 11:32:54.602647
319 11:32:54.602782 BP: 0C00 0251 [0000]
320 11:32:54.602907
321 11:32:54.605095 G0: 1182 0000
322 11:32:54.605291
323 11:32:54.605419 EC: 0004 0000 [0001]
324 11:32:54.605540
325 11:32:54.608226 S7: 0000 0000 [0000]
326 11:32:54.608494
327 11:32:54.608710 CC: 0000 0000 [0001]
328 11:32:54.611537
329 11:32:54.611796 T0: 0000 00DB [000F]
330 11:32:54.612015
331 11:32:54.612218 Jump to BL
332 11:32:54.612415
333 11:32:54.648115
334 11:32:54.648347
335 11:32:54.654418 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
336 11:32:54.657806 ARM64: Exception handlers installed.
337 11:32:54.661181 ARM64: Testing exception
338 11:32:54.664709 ARM64: Done test exception
339 11:32:54.668263 WDT: Last reset was cold boot
340 11:32:54.668498 SPI0(PAD0) initialized at 992727 Hz
341 11:32:54.675472 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
342 11:32:54.675699 Manufacturer: ef
343 11:32:54.682212 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
344 11:32:54.694556 Probing TPM: . done!
345 11:32:54.694728 TPM ready after 0 ms
346 11:32:54.700810 Connected to device vid:did:rid of 1ae0:0028:00
347 11:32:54.707553 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
348 11:32:54.711332 Initialized TPM device CR50 revision 0
349 11:32:54.757944 tlcl_send_startup: Startup return code is 0
350 11:32:54.758071 TPM: setup succeeded
351 11:32:54.766769 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
352 11:32:54.770367 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
353 11:32:54.773860 in-header: 03 19 00 00 08 00 00 00
354 11:32:54.776979 in-data: a2 e0 47 00 13 00 00 00
355 11:32:54.780394 Chrome EC: UHEPI supported
356 11:32:54.787017 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
357 11:32:54.789957 in-header: 03 a1 00 00 08 00 00 00
358 11:32:54.793271 in-data: 84 60 60 10 00 00 00 00
359 11:32:54.793415 Phase 1
360 11:32:54.796776 FMAP: area GBB found @ 3f5000 (12032 bytes)
361 11:32:54.803578 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
362 11:32:54.806751 VB2:vb2_check_recovery() Recovery was requested manually
363 11:32:54.813620 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
364 11:32:54.819627 Recovery requested (1009000e)
365 11:32:54.825508 tlcl_extend: response is 0
366 11:32:54.833749 tlcl_extend: response is 0
367 11:32:54.858764
368 11:32:54.858935
369 11:32:54.865612 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
370 11:32:54.868687 ARM64: Exception handlers installed.
371 11:32:54.872136 ARM64: Testing exception
372 11:32:54.875653 ARM64: Done test exception
373 11:32:54.891279 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xea6b, sec=0x2011
374 11:32:54.897760 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
375 11:32:54.901204 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
376 11:32:54.909048 [RTC]rtc_get_frequency_meter,134: input=0xf, output=864
377 11:32:54.916266 [RTC]rtc_get_frequency_meter,134: input=0x7, output=732
378 11:32:54.923094 [RTC]rtc_get_frequency_meter,134: input=0xb, output=799
379 11:32:54.929985 [RTC]rtc_get_frequency_meter,134: input=0x9, output=766
380 11:32:54.936669 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
381 11:32:54.943747 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
382 11:32:54.950572 [RTC]rtc_get_frequency_meter,134: input=0xb, output=799
383 11:32:54.953852 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xea6b
384 11:32:54.960441 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
385 11:32:54.963852 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
386 11:32:54.966924 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
387 11:32:54.970418 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
388 11:32:54.973626 in-header: 03 19 00 00 08 00 00 00
389 11:32:54.977079 in-data: a2 e0 47 00 13 00 00 00
390 11:32:54.980625 Chrome EC: UHEPI supported
391 11:32:54.987098 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
392 11:32:54.990288 in-header: 03 a1 00 00 08 00 00 00
393 11:32:54.994201 in-data: 84 60 60 10 00 00 00 00
394 11:32:54.997176 Skip loading cached calibration data
395 11:32:55.003871 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
396 11:32:55.007365 in-header: 03 a1 00 00 08 00 00 00
397 11:32:55.010459 in-data: 84 60 60 10 00 00 00 00
398 11:32:55.017058 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
399 11:32:55.020432 in-header: 03 a1 00 00 08 00 00 00
400 11:32:55.024166 in-data: 84 60 60 10 00 00 00 00
401 11:32:55.027122 ADC[3]: Raw value=1037832 ID=8
402 11:32:55.027207 Manufacturer: ef
403 11:32:55.033976 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
404 11:32:55.037477 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
405 11:32:55.040495 CBFS @ 21000 size 3d4000
406 11:32:55.043792 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
407 11:32:55.050433 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
408 11:32:55.054027 CBFS: Found @ offset 3c880 size 4b
409 11:32:55.054118 DRAM-K: Full Calibration
410 11:32:55.060887 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:32:55.061020 CBFS @ 21000 size 3d4000
412 11:32:55.067412 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
413 11:32:55.071132 CBFS: Locating 'fallback/dram'
414 11:32:55.074010 CBFS: Found @ offset 24b00 size 12268
415 11:32:55.101748 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
416 11:32:55.105018 ddr_geometry: 1, config: 0x0
417 11:32:55.108727 header.status = 0x0
418 11:32:55.112044 header.magic = 0x44524d4b (expected: 0x44524d4b)
419 11:32:55.115828 header.version = 0x5 (expected: 0x5)
420 11:32:55.118594 header.size = 0x8f0 (expected: 0x8f0)
421 11:32:55.118673 header.config = 0x0
422 11:32:55.122258 header.flags = 0x0
423 11:32:55.122341 header.checksum = 0x0
424 11:32:55.128989 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
425 11:32:55.135505 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
426 11:32:55.138662 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
427 11:32:55.141980 ddr_geometry:1
428 11:32:55.142127 [EMI] new MDL number = 1
429 11:32:55.145132 dram_cbt_mode_extern: 0
430 11:32:55.148992 dram_cbt_mode [RK0]: 0, [RK1]: 0
431 11:32:55.155488 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
432 11:32:55.155637
433 11:32:55.155751
434 11:32:55.155877 [Bianco] ETT version 0.0.0.1
435 11:32:55.162321 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
436 11:32:55.162520
437 11:32:55.165531 vSetVcoreByFreq with vcore:762500, freq=1600
438 11:32:55.165728
439 11:32:55.165913 [DramcInit]
440 11:32:55.169129 AutoRefreshCKEOff AutoREF OFF
441 11:32:55.172521 DDRPhyPLLSetting-CKEOFF
442 11:32:55.172906 DDRPhyPLLSetting-CKEON
443 11:32:55.176007
444 11:32:55.176506 Enable WDQS
445 11:32:55.179194 [ModeRegInit_LP4] CH0 RK0
446 11:32:55.182664 Write Rank0 MR13 =0x18
447 11:32:55.183188 Write Rank0 MR12 =0x5d
448 11:32:55.186294 Write Rank0 MR1 =0x56
449 11:32:55.189506 Write Rank0 MR2 =0x1a
450 11:32:55.189999 Write Rank0 MR11 =0x0
451 11:32:55.192902 Write Rank0 MR22 =0x38
452 11:32:55.193481 Write Rank0 MR14 =0x5d
453 11:32:55.196215 Write Rank0 MR3 =0x30
454 11:32:55.199537 Write Rank0 MR13 =0x58
455 11:32:55.199927 Write Rank0 MR12 =0x5d
456 11:32:55.202576 Write Rank0 MR1 =0x56
457 11:32:55.202967 Write Rank0 MR2 =0x2d
458 11:32:55.206152 Write Rank0 MR11 =0x23
459 11:32:55.209749 Write Rank0 MR22 =0x34
460 11:32:55.210052 Write Rank0 MR14 =0x10
461 11:32:55.212715 Write Rank0 MR3 =0x30
462 11:32:55.212931 Write Rank0 MR13 =0xd8
463 11:32:55.216218 [ModeRegInit_LP4] CH0 RK1
464 11:32:55.219102 Write Rank1 MR13 =0x18
465 11:32:55.219327 Write Rank1 MR12 =0x5d
466 11:32:55.222816 Write Rank1 MR1 =0x56
467 11:32:55.226391 Write Rank1 MR2 =0x1a
468 11:32:55.226562 Write Rank1 MR11 =0x0
469 11:32:55.229288 Write Rank1 MR22 =0x38
470 11:32:55.229461 Write Rank1 MR14 =0x5d
471 11:32:55.232855 Write Rank1 MR3 =0x30
472 11:32:55.235937 Write Rank1 MR13 =0x58
473 11:32:55.236111 Write Rank1 MR12 =0x5d
474 11:32:55.239011 Write Rank1 MR1 =0x56
475 11:32:55.239181 Write Rank1 MR2 =0x2d
476 11:32:55.242611 Write Rank1 MR11 =0x23
477 11:32:55.245856 Write Rank1 MR22 =0x34
478 11:32:55.246028 Write Rank1 MR14 =0x10
479 11:32:55.249072 Write Rank1 MR3 =0x30
480 11:32:55.253073 Write Rank1 MR13 =0xd8
481 11:32:55.253258 [ModeRegInit_LP4] CH1 RK0
482 11:32:55.256687 Write Rank0 MR13 =0x18
483 11:32:55.256853 Write Rank0 MR12 =0x5d
484 11:32:55.259520 Write Rank0 MR1 =0x56
485 11:32:55.262967 Write Rank0 MR2 =0x1a
486 11:32:55.263188 Write Rank0 MR11 =0x0
487 11:32:55.266403 Write Rank0 MR22 =0x38
488 11:32:55.266601 Write Rank0 MR14 =0x5d
489 11:32:55.269572 Write Rank0 MR3 =0x30
490 11:32:55.273461 Write Rank0 MR13 =0x58
491 11:32:55.273699 Write Rank0 MR12 =0x5d
492 11:32:55.276235 Write Rank0 MR1 =0x56
493 11:32:55.276469 Write Rank0 MR2 =0x2d
494 11:32:55.279392 Write Rank0 MR11 =0x23
495 11:32:55.282971 Write Rank0 MR22 =0x34
496 11:32:55.283267 Write Rank0 MR14 =0x10
497 11:32:55.286599 Write Rank0 MR3 =0x30
498 11:32:55.289660 Write Rank0 MR13 =0xd8
499 11:32:55.289973 [ModeRegInit_LP4] CH1 RK1
500 11:32:55.293202 Write Rank1 MR13 =0x18
501 11:32:55.293503 Write Rank1 MR12 =0x5d
502 11:32:55.296916 Write Rank1 MR1 =0x56
503 11:32:55.300150 Write Rank1 MR2 =0x1a
504 11:32:55.300459 Write Rank1 MR11 =0x0
505 11:32:55.303258 Write Rank1 MR22 =0x38
506 11:32:55.303561 Write Rank1 MR14 =0x5d
507 11:32:55.306269 Write Rank1 MR3 =0x30
508 11:32:55.309626 Write Rank1 MR13 =0x58
509 11:32:55.310073 Write Rank1 MR12 =0x5d
510 11:32:55.313266 Write Rank1 MR1 =0x56
511 11:32:55.313573 Write Rank1 MR2 =0x2d
512 11:32:55.316343 Write Rank1 MR11 =0x23
513 11:32:55.320041 Write Rank1 MR22 =0x34
514 11:32:55.320339 Write Rank1 MR14 =0x10
515 11:32:55.323430 Write Rank1 MR3 =0x30
516 11:32:55.326384 Write Rank1 MR13 =0xd8
517 11:32:55.326614 match AC timing 3
518 11:32:55.336305 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
519 11:32:55.336536 [MiockJmeterHQA]
520 11:32:55.342950 vSetVcoreByFreq with vcore:762500, freq=1600
521 11:32:55.444358
522 11:32:55.444973 MIOCK jitter meter ch=0
523 11:32:55.445483
524 11:32:55.447577 1T = (99-17) = 82 dly cells
525 11:32:55.454064 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 762/100 ps
526 11:32:55.457576 vSetVcoreByFreq with vcore:725000, freq=1200
527 11:32:55.554445
528 11:32:55.554686 MIOCK jitter meter ch=0
529 11:32:55.554855
530 11:32:55.557663 1T = (94-16) = 78 dly cells
531 11:32:55.564137 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
532 11:32:55.567513 vSetVcoreByFreq with vcore:725000, freq=800
533 11:32:55.665252
534 11:32:55.665683 MIOCK jitter meter ch=0
535 11:32:55.665989
536 11:32:55.668685 1T = (94-16) = 78 dly cells
537 11:32:55.674768 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
538 11:32:55.677867 vSetVcoreByFreq with vcore:762500, freq=1600
539 11:32:55.681585 vSetVcoreByFreq with vcore:762500, freq=1600
540 11:32:55.681794
541 11:32:55.681986 K DRVP
542 11:32:55.685161 1. OCD DRVP=0 CALOUT=0
543 11:32:55.688314 1. OCD DRVP=1 CALOUT=0
544 11:32:55.688482 1. OCD DRVP=2 CALOUT=0
545 11:32:55.691787 1. OCD DRVP=3 CALOUT=0
546 11:32:55.691955 1. OCD DRVP=4 CALOUT=0
547 11:32:55.694701 1. OCD DRVP=5 CALOUT=0
548 11:32:55.698110 1. OCD DRVP=6 CALOUT=0
549 11:32:55.698285 1. OCD DRVP=7 CALOUT=0
550 11:32:55.701522 1. OCD DRVP=8 CALOUT=0
551 11:32:55.704598 1. OCD DRVP=9 CALOUT=1
552 11:32:55.704841
553 11:32:55.708229 1. OCD DRVP calibration OK! DRVP=9
554 11:32:55.708446
555 11:32:55.708628
556 11:32:55.708803
557 11:32:55.708975 K ODTN
558 11:32:55.711512 3. OCD ODTN=0 ,CALOUT=1
559 11:32:55.711712 3. OCD ODTN=1 ,CALOUT=1
560 11:32:55.714766 3. OCD ODTN=2 ,CALOUT=1
561 11:32:55.714976 3. OCD ODTN=3 ,CALOUT=1
562 11:32:55.718306 3. OCD ODTN=4 ,CALOUT=1
563 11:32:55.721299 3. OCD ODTN=5 ,CALOUT=1
564 11:32:55.721535 3. OCD ODTN=6 ,CALOUT=1
565 11:32:55.724684 3. OCD ODTN=7 ,CALOUT=0
566 11:32:55.724904
567 11:32:55.728429 3. OCD ODTN calibration OK! ODTN=7
568 11:32:55.728651
569 11:32:55.731571 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
570 11:32:55.734944 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
571 11:32:55.741645 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
572 11:32:55.741970
573 11:32:55.742246 K DRVP
574 11:32:55.744837 1. OCD DRVP=0 CALOUT=0
575 11:32:55.745075 1. OCD DRVP=1 CALOUT=0
576 11:32:55.748582 1. OCD DRVP=2 CALOUT=0
577 11:32:55.752521 1. OCD DRVP=3 CALOUT=0
578 11:32:55.752803 1. OCD DRVP=4 CALOUT=0
579 11:32:55.755426 1. OCD DRVP=5 CALOUT=0
580 11:32:55.755847 1. OCD DRVP=6 CALOUT=0
581 11:32:55.758589 1. OCD DRVP=7 CALOUT=0
582 11:32:55.761861 1. OCD DRVP=8 CALOUT=0
583 11:32:55.762163 1. OCD DRVP=9 CALOUT=0
584 11:32:55.765557 1. OCD DRVP=10 CALOUT=1
585 11:32:55.765857
586 11:32:55.768389 1. OCD DRVP calibration OK! DRVP=10
587 11:32:55.768691
588 11:32:55.768919
589 11:32:55.769134
590 11:32:55.769455 K ODTN
591 11:32:55.772216 3. OCD ODTN=0 ,CALOUT=1
592 11:32:55.775190 3. OCD ODTN=1 ,CALOUT=1
593 11:32:55.775593 3. OCD ODTN=2 ,CALOUT=1
594 11:32:55.778625 3. OCD ODTN=3 ,CALOUT=1
595 11:32:55.782274 3. OCD ODTN=4 ,CALOUT=1
596 11:32:55.782660 3. OCD ODTN=5 ,CALOUT=1
597 11:32:55.785241 3. OCD ODTN=6 ,CALOUT=1
598 11:32:55.785515 3. OCD ODTN=7 ,CALOUT=1
599 11:32:55.788778 3. OCD ODTN=8 ,CALOUT=1
600 11:32:55.792319 3. OCD ODTN=9 ,CALOUT=1
601 11:32:55.792542 3. OCD ODTN=10 ,CALOUT=1
602 11:32:55.795167 3. OCD ODTN=11 ,CALOUT=1
603 11:32:55.798893 3. OCD ODTN=12 ,CALOUT=1
604 11:32:55.799200 3. OCD ODTN=13 ,CALOUT=1
605 11:32:55.801824 3. OCD ODTN=14 ,CALOUT=0
606 11:32:55.802125
607 11:32:55.805248 3. OCD ODTN calibration OK! ODTN=14
608 11:32:55.805554
609 11:32:55.808740 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=14
610 11:32:55.812344 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14
611 11:32:55.819085 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14 (After Adjust)
612 11:32:55.819370
613 11:32:55.819626 [DramcInit]
614 11:32:55.822301 AutoRefreshCKEOff AutoREF OFF
615 11:32:55.825806 DDRPhyPLLSetting-CKEOFF
616 11:32:55.826022 DDRPhyPLLSetting-CKEON
617 11:32:55.826190
618 11:32:55.829113 Enable WDQS
619 11:32:55.829352 ==
620 11:32:55.832527 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
621 11:32:55.835610 fsp= 1, odt_onoff= 1, Byte mode= 0
622 11:32:55.835830 ==
623 11:32:55.839377 [Duty_Offset_Calibration]
624 11:32:55.839596
625 11:32:55.842396 ===========================
626 11:32:55.842668 B0:0 B1:1 CA:1
627 11:32:55.864299 ==
628 11:32:55.867977 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
629 11:32:55.870889 fsp= 1, odt_onoff= 1, Byte mode= 0
630 11:32:55.871274 ==
631 11:32:55.874510 [Duty_Offset_Calibration]
632 11:32:55.874939
633 11:32:55.877961 ===========================
634 11:32:55.878359 B0:1 B1:2 CA:0
635 11:32:55.910154 [ModeRegInit_LP4] CH0 RK0
636 11:32:55.913502 Write Rank0 MR13 =0x18
637 11:32:55.913964 Write Rank0 MR12 =0x5d
638 11:32:55.916481 Write Rank0 MR1 =0x56
639 11:32:55.920172 Write Rank0 MR2 =0x1a
640 11:32:55.920540 Write Rank0 MR11 =0x0
641 11:32:55.923802 Write Rank0 MR22 =0x38
642 11:32:55.924008 Write Rank0 MR14 =0x5d
643 11:32:55.926554 Write Rank0 MR3 =0x30
644 11:32:55.929833 Write Rank0 MR13 =0x58
645 11:32:55.929999 Write Rank0 MR12 =0x5d
646 11:32:55.933522 Write Rank0 MR1 =0x56
647 11:32:55.933660 Write Rank0 MR2 =0x2d
648 11:32:55.936674 Write Rank0 MR11 =0x23
649 11:32:55.940327 Write Rank0 MR22 =0x34
650 11:32:55.940465 Write Rank0 MR14 =0x10
651 11:32:55.943232 Write Rank0 MR3 =0x30
652 11:32:55.943369 Write Rank0 MR13 =0xd8
653 11:32:55.946637 [ModeRegInit_LP4] CH0 RK1
654 11:32:55.950399 Write Rank1 MR13 =0x18
655 11:32:55.950538 Write Rank1 MR12 =0x5d
656 11:32:55.953902 Write Rank1 MR1 =0x56
657 11:32:55.956669 Write Rank1 MR2 =0x1a
658 11:32:55.956818 Write Rank1 MR11 =0x0
659 11:32:55.960092 Write Rank1 MR22 =0x38
660 11:32:55.960238 Write Rank1 MR14 =0x5d
661 11:32:55.964000 Write Rank1 MR3 =0x30
662 11:32:55.967775 Write Rank1 MR13 =0x58
663 11:32:55.967989 Write Rank1 MR12 =0x5d
664 11:32:55.970295 Write Rank1 MR1 =0x56
665 11:32:55.970497 Write Rank1 MR2 =0x2d
666 11:32:55.974095 Write Rank1 MR11 =0x23
667 11:32:55.977805 Write Rank1 MR22 =0x34
668 11:32:55.978084 Write Rank1 MR14 =0x10
669 11:32:55.980469 Write Rank1 MR3 =0x30
670 11:32:55.980747 Write Rank1 MR13 =0xd8
671 11:32:55.984063 [ModeRegInit_LP4] CH1 RK0
672 11:32:55.987752 Write Rank0 MR13 =0x18
673 11:32:55.988205 Write Rank0 MR12 =0x5d
674 11:32:55.990780 Write Rank0 MR1 =0x56
675 11:32:55.994289 Write Rank0 MR2 =0x1a
676 11:32:55.994744 Write Rank0 MR11 =0x0
677 11:32:55.997359 Write Rank0 MR22 =0x38
678 11:32:55.997809 Write Rank0 MR14 =0x5d
679 11:32:56.000516 Write Rank0 MR3 =0x30
680 11:32:56.004003 Write Rank0 MR13 =0x58
681 11:32:56.004453 Write Rank0 MR12 =0x5d
682 11:32:56.007535 Write Rank0 MR1 =0x56
683 11:32:56.007978 Write Rank0 MR2 =0x2d
684 11:32:56.010323 Write Rank0 MR11 =0x23
685 11:32:56.013763 Write Rank0 MR22 =0x34
686 11:32:56.014088 Write Rank0 MR14 =0x10
687 11:32:56.016938 Write Rank0 MR3 =0x30
688 11:32:56.017189 Write Rank0 MR13 =0xd8
689 11:32:56.020380 [ModeRegInit_LP4] CH1 RK1
690 11:32:56.023660 Write Rank1 MR13 =0x18
691 11:32:56.023844 Write Rank1 MR12 =0x5d
692 11:32:56.027720 Write Rank1 MR1 =0x56
693 11:32:56.030479 Write Rank1 MR2 =0x1a
694 11:32:56.030674 Write Rank1 MR11 =0x0
695 11:32:56.034091 Write Rank1 MR22 =0x38
696 11:32:56.034284 Write Rank1 MR14 =0x5d
697 11:32:56.037669 Write Rank1 MR3 =0x30
698 11:32:56.040338 Write Rank1 MR13 =0x58
699 11:32:56.040594 Write Rank1 MR12 =0x5d
700 11:32:56.044062 Write Rank1 MR1 =0x56
701 11:32:56.044263 Write Rank1 MR2 =0x2d
702 11:32:56.047189 Write Rank1 MR11 =0x23
703 11:32:56.050574 Write Rank1 MR22 =0x34
704 11:32:56.050833 Write Rank1 MR14 =0x10
705 11:32:56.054008 Write Rank1 MR3 =0x30
706 11:32:56.057536 Write Rank1 MR13 =0xd8
707 11:32:56.057778 match AC timing 3
708 11:32:56.067253 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
709 11:32:56.067523 DramC Write-DBI off
710 11:32:56.070825 DramC Read-DBI off
711 11:32:56.071064 Write Rank0 MR13 =0x59
712 11:32:56.074313 ==
713 11:32:56.077444 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
714 11:32:56.081163 fsp= 1, odt_onoff= 1, Byte mode= 0
715 11:32:56.081415 ==
716 11:32:56.084206 === u2Vref_new: 0x56 --> 0x2d
717 11:32:56.087457 === u2Vref_new: 0x58 --> 0x38
718 11:32:56.091008 === u2Vref_new: 0x5a --> 0x39
719 11:32:56.094168 === u2Vref_new: 0x5c --> 0x3c
720 11:32:56.097584 === u2Vref_new: 0x5e --> 0x3d
721 11:32:56.097836 === u2Vref_new: 0x60 --> 0xa0
722 11:32:56.101741
723 11:32:56.101979 CBT Vref found, early break!
724 11:32:56.104830 [CA 0] Center 33 (4~63) winsize 60
725 11:32:56.108320 [CA 1] Center 34 (5~63) winsize 59
726 11:32:56.111768 [CA 2] Center 29 (1~57) winsize 57
727 11:32:56.114737 [CA 3] Center 24 (-3~51) winsize 55
728 11:32:56.118172 [CA 4] Center 25 (-2~52) winsize 55
729 11:32:56.121777 [CA 5] Center 30 (2~58) winsize 57
730 11:32:56.122072
731 11:32:56.124784 [CATrainingPosCal] consider 1 rank data
732 11:32:56.128235 u2DelayCellTimex100 = 762/100 ps
733 11:32:56.131596 CA0 delay=33 (4~63),Diff = 9 PI (11 cell)
734 11:32:56.134920 CA1 delay=34 (5~63),Diff = 10 PI (12 cell)
735 11:32:56.138231 CA2 delay=29 (1~57),Diff = 5 PI (6 cell)
736 11:32:56.141578 CA3 delay=24 (-3~51),Diff = 0 PI (0 cell)
737 11:32:56.145127 CA4 delay=25 (-2~52),Diff = 1 PI (1 cell)
738 11:32:56.151985 CA5 delay=30 (2~58),Diff = 6 PI (7 cell)
739 11:32:56.152480
740 11:32:56.155302 CA PerBit enable=1, Macro0, CA PI delay=24
741 11:32:56.158549 === u2Vref_new: 0x56 --> 0x2d
742 11:32:56.158934
743 11:32:56.159230 Vref(ca) range 1: 22
744 11:32:56.159506
745 11:32:56.162033 CS Dly= 10 (41-0-32)
746 11:32:56.162417 Write Rank0 MR13 =0xd8
747 11:32:56.164885 Write Rank0 MR13 =0xd8
748 11:32:56.168679 Write Rank0 MR12 =0x56
749 11:32:56.169097 Write Rank1 MR13 =0x59
750 11:32:56.169542 ==
751 11:32:56.174986 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
752 11:32:56.178543 fsp= 1, odt_onoff= 1, Byte mode= 0
753 11:32:56.178929 ==
754 11:32:56.181952 === u2Vref_new: 0x56 --> 0x2d
755 11:32:56.185361 === u2Vref_new: 0x58 --> 0x38
756 11:32:56.188303 === u2Vref_new: 0x5a --> 0x39
757 11:32:56.188827 === u2Vref_new: 0x5c --> 0x3c
758 11:32:56.192037 === u2Vref_new: 0x5e --> 0x3d
759 11:32:56.195383 === u2Vref_new: 0x60 --> 0xa0
760 11:32:56.195766
761 11:32:56.198763 CBT Vref found, early break!
762 11:32:56.202331 [CA 0] Center 34 (5~63) winsize 59
763 11:32:56.205407 [CA 1] Center 34 (6~63) winsize 58
764 11:32:56.208858 [CA 2] Center 29 (1~58) winsize 58
765 11:32:56.211819 [CA 3] Center 23 (-4~51) winsize 56
766 11:32:56.215317 [CA 4] Center 24 (-3~52) winsize 56
767 11:32:56.218683 [CA 5] Center 30 (1~59) winsize 59
768 11:32:56.219071
769 11:32:56.222187 [CATrainingPosCal] consider 2 rank data
770 11:32:56.225236 u2DelayCellTimex100 = 762/100 ps
771 11:32:56.228803 CA0 delay=34 (5~63),Diff = 10 PI (12 cell)
772 11:32:56.232224 CA1 delay=34 (6~63),Diff = 10 PI (12 cell)
773 11:32:56.235634 CA2 delay=29 (1~57),Diff = 5 PI (6 cell)
774 11:32:56.238397 CA3 delay=24 (-3~51),Diff = 0 PI (0 cell)
775 11:32:56.242079 CA4 delay=25 (-2~52),Diff = 1 PI (1 cell)
776 11:32:56.245419 CA5 delay=30 (2~58),Diff = 6 PI (7 cell)
777 11:32:56.248895
778 11:32:56.251734 CA PerBit enable=1, Macro0, CA PI delay=24
779 11:32:56.252124 === u2Vref_new: 0x56 --> 0x2d
780 11:32:56.255547
781 11:32:56.255926 Vref(ca) range 1: 22
782 11:32:56.256225
783 11:32:56.258713 CS Dly= 11 (42-0-32)
784 11:32:56.259095 Write Rank1 MR13 =0xd8
785 11:32:56.261939 Write Rank1 MR13 =0xd8
786 11:32:56.265104 Write Rank1 MR12 =0x56
787 11:32:56.268605 [RankSwap] Rank num 2, (Multi 1), Rank 0
788 11:32:56.269170 Write Rank0 MR2 =0xad
789 11:32:56.271748 [Write Leveling]
790 11:32:56.275130 delay byte0 byte1 byte2 byte3
791 11:32:56.275654
792 11:32:56.276120 10 0 0
793 11:32:56.278701 11 0 0
794 11:32:56.279221 12 0 0
795 11:32:56.279734 13 0 0
796 11:32:56.282364 14 0 0
797 11:32:56.282900 15 0 0
798 11:32:56.285593 16 0 0
799 11:32:56.286137 17 0 0
800 11:32:56.286606 18 0 0
801 11:32:56.288829 19 0 0
802 11:32:56.289364 20 0 0
803 11:32:56.291942 21 0 0
804 11:32:56.292427 22 0 0
805 11:32:56.292887 23 0 0
806 11:32:56.295447 24 0 0
807 11:32:56.295947 25 0 ff
808 11:32:56.298927 26 0 ff
809 11:32:56.299433 27 0 ff
810 11:32:56.302045 28 0 ff
811 11:32:56.302536 29 0 ff
812 11:32:56.305325 30 0 ff
813 11:32:56.305817 31 0 ff
814 11:32:56.306320 32 ff ff
815 11:32:56.308683 33 ff ff
816 11:32:56.309234 34 ff ff
817 11:32:56.312038 35 ff ff
818 11:32:56.312565 36 ff ff
819 11:32:56.315595 37 ff ff
820 11:32:56.315979 38 ff ff
821 11:32:56.319002 pass bytecount = 0xff (0xff: all bytes pass)
822 11:32:56.319561
823 11:32:56.322022 DQS0 dly: 32
824 11:32:56.322405 DQS1 dly: 25
825 11:32:56.325609 Write Rank0 MR2 =0x2d
826 11:32:56.328732 [RankSwap] Rank num 2, (Multi 1), Rank 0
827 11:32:56.329115 Write Rank0 MR1 =0xd6
828 11:32:56.332036 [Gating]
829 11:32:56.332415 ==
830 11:32:56.335734 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
831 11:32:56.339357 fsp= 1, odt_onoff= 1, Byte mode= 0
832 11:32:56.339739 ==
833 11:32:56.345391 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
834 11:32:56.349333 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
835 11:32:56.352535 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
836 11:32:56.355880 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
837 11:32:56.362421 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
838 11:32:56.365675 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
839 11:32:56.369028 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
840 11:32:56.375712 3 1 28 |2c2c 2c2b |(11 0)(11 11) |(0 0)(1 0)| 0
841 11:32:56.379264 3 2 0 |303 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
842 11:32:56.382149 3 2 4 |3534 404 |(11 11)(11 11) |(0 0)(0 0)| 0
843 11:32:56.385675 3 2 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
844 11:32:56.392646 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
845 11:32:56.395796 3 2 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
846 11:32:56.399134 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
847 11:32:56.405879 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
848 11:32:56.409399 3 2 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
849 11:32:56.412656 3 3 0 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
850 11:32:56.419356 3 3 4 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
851 11:32:56.422652 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
852 11:32:56.426221 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
853 11:32:56.432514 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
854 11:32:56.436001 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
855 11:32:56.439338 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
856 11:32:56.442542 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
857 11:32:56.449162 3 4 0 |505 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
858 11:32:56.452688 3 4 4 |3d3d 2625 |(11 11)(11 11) |(1 1)(1 1)| 0
859 11:32:56.455888 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
860 11:32:56.462992 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
861 11:32:56.466074 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
862 11:32:56.469554 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
863 11:32:56.476276 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
864 11:32:56.479695 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
865 11:32:56.482929 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
866 11:32:56.486575 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
867 11:32:56.493050 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
868 11:32:56.496714 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
869 11:32:56.500113 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
870 11:32:56.506677 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
871 11:32:56.510064 [Byte 0] Lead/lag falling Transition (3, 5, 20)
872 11:32:56.513119 [Byte 1] Lead/lag falling Transition (3, 5, 20)
873 11:32:56.516648 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
874 11:32:56.523330 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
875 11:32:56.526527 [Byte 0] Lead/lag Transition tap number (3)
876 11:32:56.530329 [Byte 1] Lead/lag Transition tap number (3)
877 11:32:56.533389 3 6 0 |202 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
878 11:32:56.540330 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
879 11:32:56.540889 [Byte 0]First pass (3, 6, 4)
880 11:32:56.546672 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
881 11:32:56.547223 [Byte 1]First pass (3, 6, 8)
882 11:32:56.553384 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
883 11:32:56.556743 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
884 11:32:56.560173 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
885 11:32:56.563580 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
886 11:32:56.566890 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
887 11:32:56.569864 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
888 11:32:56.576934 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
889 11:32:56.579987 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
890 11:32:56.583472 All bytes gating window > 1UI, Early break!
891 11:32:56.583692
892 11:32:56.586866 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 26)
893 11:32:56.587159
894 11:32:56.589937 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 26)
895 11:32:56.590139
896 11:32:56.590345
897 11:32:56.590551
898 11:32:56.596705 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
899 11:32:56.596922
900 11:32:56.600440 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
901 11:32:56.600649
902 11:32:56.600806
903 11:32:56.600951 Write Rank0 MR1 =0x56
904 11:32:56.603386
905 11:32:56.603592 best RODT dly(2T, 0.5T) = (2, 2)
906 11:32:56.603750
907 11:32:56.606664 best RODT dly(2T, 0.5T) = (2, 2)
908 11:32:56.606868 ==
909 11:32:56.613361 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
910 11:32:56.616953 fsp= 1, odt_onoff= 1, Byte mode= 0
911 11:32:56.617209 ==
912 11:32:56.620272 Start DQ dly to find pass range UseTestEngine =0
913 11:32:56.623712 x-axis: bit #, y-axis: DQ dly (-127~63)
914 11:32:56.626979 RX Vref Scan = 0
915 11:32:56.630520 -26, [0] xxxxxxxx xxxxxxxx [MSB]
916 11:32:56.630741 -25, [0] xxxxxxxx xxxxxxxx [MSB]
917 11:32:56.633420 -24, [0] xxxxxxxx xxxxxxxx [MSB]
918 11:32:56.636964 -23, [0] xxxxxxxx xxxxxxxx [MSB]
919 11:32:56.640781 -22, [0] xxxxxxxx xxxxxxxx [MSB]
920 11:32:56.644297 -21, [0] xxxxxxxx xxxxxxxx [MSB]
921 11:32:56.647020 -20, [0] xxxxxxxx xxxxxxxx [MSB]
922 11:32:56.650908 -19, [0] xxxxxxxx xxxxxxxx [MSB]
923 11:32:56.653872 -18, [0] xxxxxxxx xxxxxxxx [MSB]
924 11:32:56.654306 -17, [0] xxxxxxxx xxxxxxxx [MSB]
925 11:32:56.657779 -16, [0] xxxxxxxx xxxxxxxx [MSB]
926 11:32:56.660726 -15, [0] xxxxxxxx xxxxxxxx [MSB]
927 11:32:56.664059 -14, [0] xxxxxxxx xxxxxxxx [MSB]
928 11:32:56.667663 -13, [0] xxxxxxxx xxxxxxxx [MSB]
929 11:32:56.670525 -12, [0] xxxxxxxx xxxxxxxx [MSB]
930 11:32:56.673809 -11, [0] xxxxxxxx xxxxxxxx [MSB]
931 11:32:56.677593 -10, [0] xxxxxxxx xxxxxxxx [MSB]
932 11:32:56.677944 -9, [0] xxxxxxxx xxxxxxxx [MSB]
933 11:32:56.680590 -8, [0] xxxxxxxx xxxxxxxx [MSB]
934 11:32:56.684165 -7, [0] xxxxxxxx xxxxxxxx [MSB]
935 11:32:56.687744 -6, [0] xxxxxxxx xxxxxxxx [MSB]
936 11:32:56.690925 -5, [0] xxxxxxxx xxxxxxxx [MSB]
937 11:32:56.694264 -4, [0] xxxxxxxx xxxxxxxx [MSB]
938 11:32:56.697394 -3, [0] xxxxxxxx xxxxxxxx [MSB]
939 11:32:56.697803 -2, [0] xxxxxxxx xxxxxxxx [MSB]
940 11:32:56.700603 -1, [0] xxxxxxxx xxxxxxxx [MSB]
941 11:32:56.704370 0, [0] xxxoxoxx xxxxxxxx [MSB]
942 11:32:56.707582 1, [0] xxxoxoxx xxxoxxxx [MSB]
943 11:32:56.711366 2, [0] xxxoxoxo xxxoxoxx [MSB]
944 11:32:56.714281 3, [0] xxxoxooo oxxoxoox [MSB]
945 11:32:56.714716 4, [0] xxxoxooo ooxoxooo [MSB]
946 11:32:56.718087 5, [0] xxxoxooo ooxooooo [MSB]
947 11:32:56.720905 6, [0] xxxooooo ooxooooo [MSB]
948 11:32:56.724449 7, [0] xxoooooo ooxooooo [MSB]
949 11:32:56.727796 8, [0] xooooooo oooooooo [MSB]
950 11:32:56.728129 9, [0] xooooooo oooooooo [MSB]
951 11:32:56.731457 10, [0] xooooooo oooooooo [MSB]
952 11:32:56.734330 32, [0] oooxoooo oooooooo [MSB]
953 11:32:56.737823 33, [0] oooxoooo oooooxoo [MSB]
954 11:32:56.740950 34, [0] oooxoxxo oooooxxo [MSB]
955 11:32:56.744488 35, [0] oooxoxxx xooooxxo [MSB]
956 11:32:56.748039 36, [0] oooxoxxx xooxoxxo [MSB]
957 11:32:56.748368 37, [0] oooxoxxx xxoxxxxx [MSB]
958 11:32:56.751223 38, [0] oooxoxxx xxoxxxxx [MSB]
959 11:32:56.755708 39, [0] oooxoxxx xxoxxxxx [MSB]
960 11:32:56.757998 40, [0] oooxxxxx xxoxxxxx [MSB]
961 11:32:56.760834 41, [0] xoxxxxxx xxoxxxxx [MSB]
962 11:32:56.764249 42, [0] xxxxxxxx xxxxxxxx [MSB]
963 11:32:56.767847 iDelay=42, Bit 0, Center 25 (11 ~ 40) 30
964 11:32:56.770947 iDelay=42, Bit 1, Center 24 (8 ~ 41) 34
965 11:32:56.774784 iDelay=42, Bit 2, Center 23 (7 ~ 40) 34
966 11:32:56.777524 iDelay=42, Bit 3, Center 15 (0 ~ 31) 32
967 11:32:56.781172 iDelay=42, Bit 4, Center 22 (6 ~ 39) 34
968 11:32:56.784669 iDelay=42, Bit 5, Center 16 (0 ~ 33) 34
969 11:32:56.787859 iDelay=42, Bit 6, Center 18 (3 ~ 33) 31
970 11:32:56.791279 iDelay=42, Bit 7, Center 18 (2 ~ 34) 33
971 11:32:56.794250 iDelay=42, Bit 8, Center 18 (3 ~ 34) 32
972 11:32:56.797802 iDelay=42, Bit 9, Center 20 (4 ~ 36) 33
973 11:32:56.801277 iDelay=42, Bit 10, Center 24 (8 ~ 41) 34
974 11:32:56.804757 iDelay=42, Bit 11, Center 18 (1 ~ 35) 35
975 11:32:56.807895 iDelay=42, Bit 12, Center 20 (5 ~ 36) 32
976 11:32:56.815482 iDelay=42, Bit 13, Center 17 (2 ~ 32) 31
977 11:32:56.817941 iDelay=42, Bit 14, Center 18 (3 ~ 33) 31
978 11:32:56.821364 iDelay=42, Bit 15, Center 20 (4 ~ 36) 33
979 11:32:56.821818 ==
980 11:32:56.824531 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
981 11:32:56.828240 fsp= 1, odt_onoff= 1, Byte mode= 0
982 11:32:56.828564 ==
983 11:32:56.831374 DQS Delay:
984 11:32:56.831701 DQS0 = 0, DQS1 = 0
985 11:32:56.831953 DQM Delay:
986 11:32:56.834571 DQM0 = 20, DQM1 = 19
987 11:32:56.835019 DQ Delay:
988 11:32:56.838157 DQ0 =25, DQ1 =24, DQ2 =23, DQ3 =15
989 11:32:56.841529 DQ4 =22, DQ5 =16, DQ6 =18, DQ7 =18
990 11:32:56.844857 DQ8 =18, DQ9 =20, DQ10 =24, DQ11 =18
991 11:32:56.847814 DQ12 =20, DQ13 =17, DQ14 =18, DQ15 =20
992 11:32:56.848103
993 11:32:56.848349
994 11:32:56.851348 DramC Write-DBI off
995 11:32:56.851675 ==
996 11:32:56.855027 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
997 11:32:56.858538 fsp= 1, odt_onoff= 1, Byte mode= 0
998 11:32:56.858866 ==
999 11:32:56.865094 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1000 11:32:56.865460
1001 11:32:56.868137 Begin, DQ Scan Range 921~1177
1002 11:32:56.868462
1003 11:32:56.868715
1004 11:32:56.868947 TX Vref Scan disable
1005 11:32:56.871669 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1006 11:32:56.875349 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1007 11:32:56.878492 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1008 11:32:56.881833 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1009 11:32:56.884975 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1010 11:32:56.892000 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1011 11:32:56.895306 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1012 11:32:56.898747 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1013 11:32:56.901646 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1014 11:32:56.905037 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1015 11:32:56.908363 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1016 11:32:56.912077 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1017 11:32:56.915119 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1018 11:32:56.918921 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1019 11:32:56.922321 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1020 11:32:56.926056 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1021 11:32:56.928609 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1022 11:32:56.932090 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1023 11:32:56.935236 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1024 11:32:56.938612 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1025 11:32:56.942184 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1026 11:32:56.945242 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1027 11:32:56.948454 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1028 11:32:56.955732 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1029 11:32:56.958895 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1030 11:32:56.961867 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1031 11:32:56.965279 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1032 11:32:56.969133 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1033 11:32:56.972468 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1034 11:32:56.975619 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1035 11:32:56.978968 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1036 11:32:56.982375 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1037 11:32:56.985380 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1038 11:32:56.989220 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1039 11:32:56.992592 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1040 11:32:56.995970 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1041 11:32:56.998988 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1042 11:32:57.002595 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1043 11:32:57.005621 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1044 11:32:57.009478 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1045 11:32:57.012518 961 |3 6 1|[0] xxxxxxxx oxxoxxxx [MSB]
1046 11:32:57.016117 962 |3 6 2|[0] xxxxxxxx oxxoooxx [MSB]
1047 11:32:57.019322 963 |3 6 3|[0] xxxxxxxx ooxoooox [MSB]
1048 11:32:57.022701 964 |3 6 4|[0] xxxxxxxx ooxoooox [MSB]
1049 11:32:57.025969 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1050 11:32:57.032689 966 |3 6 6|[0] xxxxxxxx ooxooooo [MSB]
1051 11:32:57.036002 967 |3 6 7|[0] xxxxxxxx oooooooo [MSB]
1052 11:32:57.039966 968 |3 6 8|[0] xxxxxxxx oooooooo [MSB]
1053 11:32:57.042773 969 |3 6 9|[0] xxxoxoox oooooooo [MSB]
1054 11:32:57.046111 970 |3 6 10|[0] xxxoxoox oooooooo [MSB]
1055 11:32:57.049421 971 |3 6 11|[0] xxxoooox oooooooo [MSB]
1056 11:32:57.052598 972 |3 6 12|[0] xxxooooo oooooooo [MSB]
1057 11:32:57.056369 973 |3 6 13|[0] xxxooooo oooooooo [MSB]
1058 11:32:57.059903 974 |3 6 14|[0] xxoooooo oooooooo [MSB]
1059 11:32:57.062719 985 |3 6 25|[0] oooooooo oooxoxoo [MSB]
1060 11:32:57.066669 986 |3 6 26|[0] oooooooo xxxxxxxx [MSB]
1061 11:32:57.072932 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB]
1062 11:32:57.076691 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1063 11:32:57.079325 989 |3 6 29|[0] oooxoooo xxxxxxxx [MSB]
1064 11:32:57.082991 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1065 11:32:57.086353 991 |3 6 31|[0] oooxoxoo xxxxxxxx [MSB]
1066 11:32:57.089410 992 |3 6 32|[0] xxoxxxxx xxxxxxxx [MSB]
1067 11:32:57.092859 993 |3 6 33|[0] xxxxxxxx xxxxxxxx [MSB]
1068 11:32:57.096414 Byte0, DQ PI dly=980, DQM PI dly= 980
1069 11:32:57.099954 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1070 11:32:57.100419
1071 11:32:57.103581 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1072 11:32:57.104103
1073 11:32:57.106748 Byte1, DQ PI dly=974, DQM PI dly= 974
1074 11:32:57.113597 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
1075 11:32:57.114039
1076 11:32:57.116463 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
1077 11:32:57.116867
1078 11:32:57.117235 ==
1079 11:32:57.123456 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1080 11:32:57.126899 fsp= 1, odt_onoff= 1, Byte mode= 0
1081 11:32:57.127284 ==
1082 11:32:57.130284 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1083 11:32:57.130681
1084 11:32:57.133193 Begin, DQ Scan Range 950~1014
1085 11:32:57.133580 Write Rank0 MR14 =0x0
1086 11:32:57.143285
1087 11:32:57.143664 CH=0, VrefRange= 0, VrefLevel = 0
1088 11:32:57.150198 TX Bit0 (976~993) 18 984, Bit8 (963~982) 20 972,
1089 11:32:57.153166 TX Bit1 (976~992) 17 984, Bit9 (966~982) 17 974,
1090 11:32:57.160203 TX Bit2 (975~991) 17 983, Bit10 (969~987) 19 978,
1091 11:32:57.163687 TX Bit3 (969~985) 17 977, Bit11 (964~982) 19 973,
1092 11:32:57.166600 TX Bit4 (975~992) 18 983, Bit12 (966~982) 17 974,
1093 11:32:57.173165 TX Bit5 (971~986) 16 978, Bit13 (965~982) 18 973,
1094 11:32:57.176826 TX Bit6 (972~986) 15 979, Bit14 (966~983) 18 974,
1095 11:32:57.180326 TX Bit7 (976~989) 14 982, Bit15 (968~983) 16 975,
1096 11:32:57.180600
1097 11:32:57.183435 Write Rank0 MR14 =0x2
1098 11:32:57.191994
1099 11:32:57.192271 CH=0, VrefRange= 0, VrefLevel = 2
1100 11:32:57.198489 TX Bit0 (976~993) 18 984, Bit8 (963~982) 20 972,
1101 11:32:57.201988 TX Bit1 (976~992) 17 984, Bit9 (966~982) 17 974,
1102 11:32:57.208742 TX Bit2 (975~992) 18 983, Bit10 (969~988) 20 978,
1103 11:32:57.212154 TX Bit3 (969~985) 17 977, Bit11 (963~982) 20 972,
1104 11:32:57.215886 TX Bit4 (975~992) 18 983, Bit12 (966~983) 18 974,
1105 11:32:57.222720 TX Bit5 (970~986) 17 978, Bit13 (965~982) 18 973,
1106 11:32:57.225584 TX Bit6 (971~987) 17 979, Bit14 (966~983) 18 974,
1107 11:32:57.228818 TX Bit7 (975~990) 16 982, Bit15 (968~983) 16 975,
1108 11:32:57.229468
1109 11:32:57.232065 Write Rank0 MR14 =0x4
1110 11:32:57.240819
1111 11:32:57.241284 CH=0, VrefRange= 0, VrefLevel = 4
1112 11:32:57.247683 TX Bit0 (976~993) 18 984, Bit8 (963~983) 21 973,
1113 11:32:57.250713 TX Bit1 (976~992) 17 984, Bit9 (965~982) 18 973,
1114 11:32:57.257683 TX Bit2 (975~992) 18 983, Bit10 (968~988) 21 978,
1115 11:32:57.261060 TX Bit3 (969~985) 17 977, Bit11 (963~982) 20 972,
1116 11:32:57.263986 TX Bit4 (974~993) 20 983, Bit12 (965~983) 19 974,
1117 11:32:57.270715 TX Bit5 (970~987) 18 978, Bit13 (965~982) 18 973,
1118 11:32:57.274143 TX Bit6 (971~988) 18 979, Bit14 (965~983) 19 974,
1119 11:32:57.277638 TX Bit7 (975~990) 16 982, Bit15 (968~984) 17 976,
1120 11:32:57.278055
1121 11:32:57.280870 Write Rank0 MR14 =0x6
1122 11:32:57.289902
1123 11:32:57.290359 CH=0, VrefRange= 0, VrefLevel = 6
1124 11:32:57.296468 TX Bit0 (976~994) 19 985, Bit8 (962~983) 22 972,
1125 11:32:57.300120 TX Bit1 (976~992) 17 984, Bit9 (965~983) 19 974,
1126 11:32:57.306435 TX Bit2 (975~992) 18 983, Bit10 (968~989) 22 978,
1127 11:32:57.309773 TX Bit3 (969~986) 18 977, Bit11 (962~982) 21 972,
1128 11:32:57.313427 TX Bit4 (974~993) 20 983, Bit12 (965~983) 19 974,
1129 11:32:57.320150 TX Bit5 (970~987) 18 978, Bit13 (964~982) 19 973,
1130 11:32:57.323203 TX Bit6 (971~988) 18 979, Bit14 (965~984) 20 974,
1131 11:32:57.326403 TX Bit7 (975~991) 17 983, Bit15 (967~984) 18 975,
1132 11:32:57.327009
1133 11:32:57.329805 Write Rank0 MR14 =0x8
1134 11:32:57.338559
1135 11:32:57.338841 CH=0, VrefRange= 0, VrefLevel = 8
1136 11:32:57.345204 TX Bit0 (976~994) 19 985, Bit8 (962~983) 22 972,
1137 11:32:57.348701 TX Bit1 (976~993) 18 984, Bit9 (965~983) 19 974,
1138 11:32:57.355168 TX Bit2 (975~993) 19 984, Bit10 (968~989) 22 978,
1139 11:32:57.358253 TX Bit3 (968~986) 19 977, Bit11 (962~983) 22 972,
1140 11:32:57.361843 TX Bit4 (974~993) 20 983, Bit12 (964~984) 21 974,
1141 11:32:57.368673 TX Bit5 (970~987) 18 978, Bit13 (963~983) 21 973,
1142 11:32:57.419950 TX Bit6 (970~989) 20 979, Bit14 (965~984) 20 974,
1143 11:32:57.420426 TX Bit7 (974~991) 18 982, Bit15 (967~984) 18 975,
1144 11:32:57.420828
1145 11:32:57.421320 Write Rank0 MR14 =0xa
1146 11:32:57.421689
1147 11:32:57.422363 CH=0, VrefRange= 0, VrefLevel = 10
1148 11:32:57.422691 TX Bit0 (975~994) 20 984, Bit8 (962~984) 23 973,
1149 11:32:57.423050 TX Bit1 (975~993) 19 984, Bit9 (964~984) 21 974,
1150 11:32:57.423396 TX Bit2 (975~993) 19 984, Bit10 (967~989) 23 978,
1151 11:32:57.423837 TX Bit3 (968~987) 20 977, Bit11 (962~983) 22 972,
1152 11:32:57.424174 TX Bit4 (973~993) 21 983, Bit12 (964~984) 21 974,
1153 11:32:57.424607 TX Bit5 (969~988) 20 978, Bit13 (963~983) 21 973,
1154 11:32:57.424947 TX Bit6 (970~990) 21 980, Bit14 (965~985) 21 975,
1155 11:32:57.454509 TX Bit7 (973~991) 19 982, Bit15 (967~985) 19 976,
1156 11:32:57.454994
1157 11:32:57.455642 Write Rank0 MR14 =0xc
1158 11:32:57.455982
1159 11:32:57.456272 CH=0, VrefRange= 0, VrefLevel = 12
1160 11:32:57.456539 TX Bit0 (975~995) 21 985, Bit8 (961~984) 24 972,
1161 11:32:57.456797 TX Bit1 (975~994) 20 984, Bit9 (963~984) 22 973,
1162 11:32:57.457101 TX Bit2 (974~993) 20 983, Bit10 (967~990) 24 978,
1163 11:32:57.457414 TX Bit3 (968~987) 20 977, Bit11 (962~983) 22 972,
1164 11:32:57.461927 TX Bit4 (972~994) 23 983, Bit12 (963~984) 22 973,
1165 11:32:57.465434 TX Bit5 (969~989) 21 979, Bit13 (962~983) 22 972,
1166 11:32:57.468820 TX Bit6 (970~990) 21 980, Bit14 (964~985) 22 974,
1167 11:32:57.475170 TX Bit7 (973~992) 20 982, Bit15 (966~985) 20 975,
1168 11:32:57.475584
1169 11:32:57.475882 Write Rank0 MR14 =0xe
1170 11:32:57.485715
1171 11:32:57.488946 CH=0, VrefRange= 0, VrefLevel = 14
1172 11:32:57.492286 TX Bit0 (975~995) 21 985, Bit8 (961~985) 25 973,
1173 11:32:57.495527 TX Bit1 (975~994) 20 984, Bit9 (963~985) 23 974,
1174 11:32:57.502542 TX Bit2 (974~993) 20 983, Bit10 (967~990) 24 978,
1175 11:32:57.505802 TX Bit3 (968~988) 21 978, Bit11 (961~983) 23 972,
1176 11:32:57.508800 TX Bit4 (972~994) 23 983, Bit12 (963~985) 23 974,
1177 11:32:57.515452 TX Bit5 (969~990) 22 979, Bit13 (962~984) 23 973,
1178 11:32:57.518865 TX Bit6 (969~991) 23 980, Bit14 (963~986) 24 974,
1179 11:32:57.522512 TX Bit7 (972~992) 21 982, Bit15 (966~986) 21 976,
1180 11:32:57.522895
1181 11:32:57.525678 Write Rank0 MR14 =0x10
1182 11:32:57.534947
1183 11:32:57.535364 CH=0, VrefRange= 0, VrefLevel = 16
1184 11:32:57.541899 TX Bit0 (975~995) 21 985, Bit8 (961~985) 25 973,
1185 11:32:57.545221 TX Bit1 (974~994) 21 984, Bit9 (963~985) 23 974,
1186 11:32:57.551685 TX Bit2 (974~994) 21 984, Bit10 (967~990) 24 978,
1187 11:32:57.555204 TX Bit3 (968~988) 21 978, Bit11 (961~984) 24 972,
1188 11:32:57.559052 TX Bit4 (972~994) 23 983, Bit12 (963~985) 23 974,
1189 11:32:57.564954 TX Bit5 (969~990) 22 979, Bit13 (962~984) 23 973,
1190 11:32:57.568719 TX Bit6 (969~991) 23 980, Bit14 (963~986) 24 974,
1191 11:32:57.571966 TX Bit7 (972~992) 21 982, Bit15 (966~987) 22 976,
1192 11:32:57.572437
1193 11:32:57.575007 Write Rank0 MR14 =0x12
1194 11:32:57.584169
1195 11:32:57.587648 CH=0, VrefRange= 0, VrefLevel = 18
1196 11:32:57.590944 TX Bit0 (974~996) 23 985, Bit8 (961~986) 26 973,
1197 11:32:57.594652 TX Bit1 (974~994) 21 984, Bit9 (962~985) 24 973,
1198 11:32:57.601471 TX Bit2 (973~994) 22 983, Bit10 (967~990) 24 978,
1199 11:32:57.604191 TX Bit3 (967~989) 23 978, Bit11 (961~984) 24 972,
1200 11:32:57.607647 TX Bit4 (971~995) 25 983, Bit12 (962~985) 24 973,
1201 11:32:57.614677 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1202 11:32:57.617729 TX Bit6 (969~991) 23 980, Bit14 (963~987) 25 975,
1203 11:32:57.620917 TX Bit7 (971~993) 23 982, Bit15 (966~987) 22 976,
1204 11:32:57.621363
1205 11:32:57.624265 Write Rank0 MR14 =0x14
1206 11:32:57.633831
1207 11:32:57.636908 CH=0, VrefRange= 0, VrefLevel = 20
1208 11:32:57.640405 TX Bit0 (974~997) 24 985, Bit8 (961~986) 26 973,
1209 11:32:57.644111 TX Bit1 (974~994) 21 984, Bit9 (962~986) 25 974,
1210 11:32:57.650452 TX Bit2 (973~994) 22 983, Bit10 (966~991) 26 978,
1211 11:32:57.654026 TX Bit3 (967~990) 24 978, Bit11 (961~985) 25 973,
1212 11:32:57.657323 TX Bit4 (971~995) 25 983, Bit12 (962~986) 25 974,
1213 11:32:57.663753 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1214 11:32:57.667436 TX Bit6 (969~992) 24 980, Bit14 (962~987) 26 974,
1215 11:32:57.670818 TX Bit7 (971~993) 23 982, Bit15 (966~988) 23 977,
1216 11:32:57.671281
1217 11:32:57.674063 Write Rank0 MR14 =0x16
1218 11:32:57.683254
1219 11:32:57.686641 CH=0, VrefRange= 0, VrefLevel = 22
1220 11:32:57.690120 TX Bit0 (974~997) 24 985, Bit8 (961~986) 26 973,
1221 11:32:57.693258 TX Bit1 (972~996) 25 984, Bit9 (962~986) 25 974,
1222 11:32:57.700079 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1223 11:32:57.703275 TX Bit3 (967~991) 25 979, Bit11 (961~985) 25 973,
1224 11:32:57.706515 TX Bit4 (971~996) 26 983, Bit12 (961~986) 26 973,
1225 11:32:57.713648 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1226 11:32:57.716779 TX Bit6 (969~992) 24 980, Bit14 (962~986) 25 974,
1227 11:32:57.720375 TX Bit7 (970~993) 24 981, Bit15 (965~989) 25 977,
1228 11:32:57.720827
1229 11:32:57.726825 wait MRW command Rank0 MR14 =0x18 fired (1)
1230 11:32:57.727202 Write Rank0 MR14 =0x18
1231 11:32:57.736802
1232 11:32:57.739979 CH=0, VrefRange= 0, VrefLevel = 24
1233 11:32:57.744068 TX Bit0 (974~997) 24 985, Bit8 (961~986) 26 973,
1234 11:32:57.747497 TX Bit1 (972~996) 25 984, Bit9 (962~986) 25 974,
1235 11:32:57.753719 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1236 11:32:57.756694 TX Bit3 (967~991) 25 979, Bit11 (961~985) 25 973,
1237 11:32:57.760421 TX Bit4 (971~996) 26 983, Bit12 (961~986) 26 973,
1238 11:32:57.766893 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1239 11:32:57.770210 TX Bit6 (969~992) 24 980, Bit14 (962~986) 25 974,
1240 11:32:57.773636 TX Bit7 (970~993) 24 981, Bit15 (965~989) 25 977,
1241 11:32:57.774017
1242 11:32:57.777310 Write Rank0 MR14 =0x1a
1243 11:32:57.786944
1244 11:32:57.789676 CH=0, VrefRange= 0, VrefLevel = 26
1245 11:32:57.793622 TX Bit0 (974~997) 24 985, Bit8 (961~986) 26 973,
1246 11:32:57.796467 TX Bit1 (972~996) 25 984, Bit9 (962~986) 25 974,
1247 11:32:57.802954 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1248 11:32:57.806413 TX Bit3 (967~991) 25 979, Bit11 (961~985) 25 973,
1249 11:32:57.809826 TX Bit4 (971~996) 26 983, Bit12 (961~986) 26 973,
1250 11:32:57.816303 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1251 11:32:57.819708 TX Bit6 (969~992) 24 980, Bit14 (962~986) 25 974,
1252 11:32:57.823204 TX Bit7 (970~993) 24 981, Bit15 (965~989) 25 977,
1253 11:32:57.823594
1254 11:32:57.826397 Write Rank0 MR14 =0x1c
1255 11:32:57.835674
1256 11:32:57.839274 CH=0, VrefRange= 0, VrefLevel = 28
1257 11:32:57.842451 TX Bit0 (974~997) 24 985, Bit8 (961~986) 26 973,
1258 11:32:57.845981 TX Bit1 (972~996) 25 984, Bit9 (962~986) 25 974,
1259 11:32:57.852488 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1260 11:32:57.856272 TX Bit3 (967~991) 25 979, Bit11 (961~985) 25 973,
1261 11:32:57.859423 TX Bit4 (971~996) 26 983, Bit12 (961~986) 26 973,
1262 11:32:57.865587 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1263 11:32:57.869538 TX Bit6 (969~992) 24 980, Bit14 (962~986) 25 974,
1264 11:32:57.872461 TX Bit7 (970~993) 24 981, Bit15 (965~989) 25 977,
1265 11:32:57.872854
1266 11:32:57.875818 Write Rank0 MR14 =0x1e
1267 11:32:57.885708
1268 11:32:57.888606 CH=0, VrefRange= 0, VrefLevel = 30
1269 11:32:57.891949 TX Bit0 (974~997) 24 985, Bit8 (961~986) 26 973,
1270 11:32:57.895629 TX Bit1 (972~996) 25 984, Bit9 (962~986) 25 974,
1271 11:32:57.901916 TX Bit2 (972~995) 24 983, Bit10 (966~990) 25 978,
1272 11:32:57.905396 TX Bit3 (967~991) 25 979, Bit11 (961~985) 25 973,
1273 11:32:57.908844 TX Bit4 (971~996) 26 983, Bit12 (961~986) 26 973,
1274 11:32:57.914965 TX Bit5 (968~991) 24 979, Bit13 (961~985) 25 973,
1275 11:32:57.918564 TX Bit6 (969~992) 24 980, Bit14 (962~986) 25 974,
1276 11:32:57.921820 TX Bit7 (970~993) 24 981, Bit15 (965~989) 25 977,
1277 11:32:57.922042
1278 11:32:57.922205
1279 11:32:57.925222 TX Vref found, early break! 371< 378
1280 11:32:57.931680 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
1281 11:32:57.935575 u1DelayCellOfst[0]=7 cells (6 PI)
1282 11:32:57.938665 u1DelayCellOfst[1]=6 cells (5 PI)
1283 11:32:57.942077 u1DelayCellOfst[2]=5 cells (4 PI)
1284 11:32:57.942287 u1DelayCellOfst[3]=0 cells (0 PI)
1285 11:32:57.945615 u1DelayCellOfst[4]=5 cells (4 PI)
1286 11:32:57.948797 u1DelayCellOfst[5]=0 cells (0 PI)
1287 11:32:57.952307 u1DelayCellOfst[6]=1 cells (1 PI)
1288 11:32:57.955499 u1DelayCellOfst[7]=2 cells (2 PI)
1289 11:32:57.958833 Byte0, DQ PI dly=979, DQM PI dly= 982
1290 11:32:57.962656 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1291 11:32:57.963118
1292 11:32:57.969042 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1293 11:32:57.969533
1294 11:32:57.971870 u1DelayCellOfst[8]=0 cells (0 PI)
1295 11:32:57.975757 u1DelayCellOfst[9]=1 cells (1 PI)
1296 11:32:57.976151 u1DelayCellOfst[10]=6 cells (5 PI)
1297 11:32:57.979093 u1DelayCellOfst[11]=0 cells (0 PI)
1298 11:32:57.981922 u1DelayCellOfst[12]=0 cells (0 PI)
1299 11:32:57.985263 u1DelayCellOfst[13]=0 cells (0 PI)
1300 11:32:57.988887 u1DelayCellOfst[14]=1 cells (1 PI)
1301 11:32:57.992407 u1DelayCellOfst[15]=5 cells (4 PI)
1302 11:32:57.996016 Byte1, DQ PI dly=973, DQM PI dly= 975
1303 11:32:57.999204 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 13)
1304 11:32:57.999704
1305 11:32:58.005679 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 13)
1306 11:32:58.006215
1307 11:32:58.006693 Write Rank0 MR14 =0x16
1308 11:32:58.007024
1309 11:32:58.009242 Final TX Range 0 Vref 22
1310 11:32:58.009770
1311 11:32:58.015803 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1312 11:32:58.016234
1313 11:32:58.022649 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1314 11:32:58.029543 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1315 11:32:58.036219 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1316 11:32:58.039131 Write Rank0 MR3 =0xb0
1317 11:32:58.039648 DramC Write-DBI on
1318 11:32:58.039959 ==
1319 11:32:58.045986 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1320 11:32:58.049243 fsp= 1, odt_onoff= 1, Byte mode= 0
1321 11:32:58.049665 ==
1322 11:32:58.052542 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1323 11:32:58.052924
1324 11:32:58.056618 Begin, DQ Scan Range 695~759
1325 11:32:58.056999
1326 11:32:58.057350
1327 11:32:58.059492 TX Vref Scan disable
1328 11:32:58.063135 695 |2 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1329 11:32:58.066176 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1330 11:32:58.069467 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1331 11:32:58.073060 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1332 11:32:58.075835 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1333 11:32:58.079320 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1334 11:32:58.082865 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1335 11:32:58.086045 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1336 11:32:58.089641 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1337 11:32:58.093003 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1338 11:32:58.096031 705 |2 6 1|[0] xxxxxxxx oooooooo [MSB]
1339 11:32:58.099316 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1340 11:32:58.102890 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1341 11:32:58.106058 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1342 11:32:58.109395 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1343 11:32:58.112579 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1344 11:32:58.119308 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1345 11:32:58.122589 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1346 11:32:58.125892 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1347 11:32:58.130380 732 |2 6 28|[0] oooooooo xxxxxxxx [MSB]
1348 11:32:58.136047 733 |2 6 29|[0] oooooooo xxxxxxxx [MSB]
1349 11:32:58.139353 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1350 11:32:58.142653 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1351 11:32:58.146112 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1352 11:32:58.149802 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1353 11:32:58.152999 738 |2 6 34|[0] xxxxxxxx xxxxxxxx [MSB]
1354 11:32:58.156006 Byte0, DQ PI dly=725, DQM PI dly= 725
1355 11:32:58.159748 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
1356 11:32:58.160136
1357 11:32:58.163387 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
1358 11:32:58.163778
1359 11:32:58.166306 Byte1, DQ PI dly=718, DQM PI dly= 718
1360 11:32:58.172778 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 14)
1361 11:32:58.173276
1362 11:32:58.176737 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 14)
1363 11:32:58.177188
1364 11:32:58.183112 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1365 11:32:58.190125 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1366 11:32:58.196462 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1367 11:32:58.199523 Write Rank0 MR3 =0x30
1368 11:32:58.199731 DramC Write-DBI off
1369 11:32:58.199890
1370 11:32:58.203026 [DATLAT]
1371 11:32:58.206329 Freq=1600, CH0 RK0, use_rxtx_scan=0
1372 11:32:58.206477
1373 11:32:58.206589 DATLAT Default: 0xf
1374 11:32:58.209479 7, 0xFFFF, sum=0
1375 11:32:58.209623 8, 0xFFFF, sum=0
1376 11:32:58.212946 9, 0xFFFF, sum=0
1377 11:32:58.213120 10, 0xFFFF, sum=0
1378 11:32:58.216439 11, 0xFFFF, sum=0
1379 11:32:58.216578 12, 0xFFFF, sum=0
1380 11:32:58.219389 13, 0xFFFF, sum=0
1381 11:32:58.219485 14, 0x0, sum=1
1382 11:32:58.219563 15, 0x0, sum=2
1383 11:32:58.223411 16, 0x0, sum=3
1384 11:32:58.223519 17, 0x0, sum=4
1385 11:32:58.230071 pattern=2 first_step=14 total pass=5 best_step=16
1386 11:32:58.230177 ==
1387 11:32:58.233042 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1388 11:32:58.236333 fsp= 1, odt_onoff= 1, Byte mode= 0
1389 11:32:58.236438 ==
1390 11:32:58.239436 Start DQ dly to find pass range UseTestEngine =1
1391 11:32:58.246291 x-axis: bit #, y-axis: DQ dly (-127~63)
1392 11:32:58.246398 RX Vref Scan = 1
1393 11:32:58.361185
1394 11:32:58.361448 RX Vref found, early break!
1395 11:32:58.361616
1396 11:32:58.368445 Final RX Vref 13, apply to both rank0 and 1
1397 11:32:58.368871 ==
1398 11:32:58.371374 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1399 11:32:58.375010 fsp= 1, odt_onoff= 1, Byte mode= 0
1400 11:32:58.375424 ==
1401 11:32:58.375817 DQS Delay:
1402 11:32:58.377910 DQS0 = 0, DQS1 = 0
1403 11:32:58.378466 DQM Delay:
1404 11:32:58.381575 DQM0 = 20, DQM1 = 18
1405 11:32:58.382067 DQ Delay:
1406 11:32:58.384712 DQ0 =25, DQ1 =24, DQ2 =24, DQ3 =15
1407 11:32:58.387805 DQ4 =23, DQ5 =16, DQ6 =17, DQ7 =19
1408 11:32:58.391943 DQ8 =18, DQ9 =20, DQ10 =23, DQ11 =16
1409 11:32:58.395056 DQ12 =19, DQ13 =17, DQ14 =18, DQ15 =20
1410 11:32:58.395451
1411 11:32:58.395747
1412 11:32:58.396018
1413 11:32:58.398166 [DramC_TX_OE_Calibration] TA2
1414 11:32:58.401754 Original DQ_B0 (3 6) =30, OEN = 27
1415 11:32:58.404879 Original DQ_B1 (3 6) =30, OEN = 27
1416 11:32:58.407944 23, 0x0, End_B0=23 End_B1=23
1417 11:32:58.408337 24, 0x0, End_B0=24 End_B1=24
1418 11:32:58.411876 25, 0x0, End_B0=25 End_B1=25
1419 11:32:58.414642 26, 0x0, End_B0=26 End_B1=26
1420 11:32:58.418125 27, 0x0, End_B0=27 End_B1=27
1421 11:32:58.418649 28, 0x0, End_B0=28 End_B1=28
1422 11:32:58.421537 29, 0x0, End_B0=29 End_B1=29
1423 11:32:58.425288 30, 0x0, End_B0=30 End_B1=30
1424 11:32:58.428277 31, 0xFFFF, End_B0=30 End_B1=30
1425 11:32:58.431755 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1426 11:32:58.438357 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1427 11:32:58.438870
1428 11:32:58.439179
1429 11:32:58.441895 Write Rank0 MR23 =0x3f
1430 11:32:58.442387 [DQSOSC]
1431 11:32:58.448564 [DQSOSCAuto] RK0, (LSB)MR18= 0xa8, (MSB)MR19= 0x3, tDQSOscB0 = 336 ps tDQSOscB1 = 0 ps
1432 11:32:58.454942 CH0_RK0: MR19=0x3, MR18=0xA8, DQSOSC=336, MR23=63, INC=21, DEC=32
1433 11:32:58.458424 Write Rank0 MR23 =0x3f
1434 11:32:58.458810 [DQSOSC]
1435 11:32:58.465184 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9, (MSB)MR19= 0x3, tDQSOscB0 = 336 ps tDQSOscB1 = 0 ps
1436 11:32:58.468810 CH0 RK0: MR19=3, MR18=A9
1437 11:32:58.471906 [RankSwap] Rank num 2, (Multi 1), Rank 1
1438 11:32:58.475305 Write Rank0 MR2 =0xad
1439 11:32:58.475690 [Write Leveling]
1440 11:32:58.477974 delay byte0 byte1 byte2 byte3
1441 11:32:58.478248
1442 11:32:58.478460 10 0 0
1443 11:32:58.481432 11 0 0
1444 11:32:58.481643 12 0 0
1445 11:32:58.484941 13 0 0
1446 11:32:58.485169 14 0 0
1447 11:32:58.485339 15 0 0
1448 11:32:58.488317 16 0 0
1449 11:32:58.488486 17 0 0
1450 11:32:58.491552 18 0 0
1451 11:32:58.491721 19 0 0
1452 11:32:58.494901 20 0 0
1453 11:32:58.495070 21 0 0
1454 11:32:58.495207 22 0 0
1455 11:32:58.498436 23 0 0
1456 11:32:58.498605 24 0 0
1457 11:32:58.501343 25 0 0
1458 11:32:58.501514 26 0 0
1459 11:32:58.501646 27 0 0
1460 11:32:58.505461 28 0 ff
1461 11:32:58.505684 29 0 ff
1462 11:32:58.508374 30 0 ff
1463 11:32:58.508577 31 0 ff
1464 11:32:58.511761 32 0 ff
1465 11:32:58.511951 33 0 ff
1466 11:32:58.512150 34 0 ff
1467 11:32:58.515066 35 ff ff
1468 11:32:58.515295 36 ff ff
1469 11:32:58.518538 37 ff ff
1470 11:32:58.518707 38 ff ff
1471 11:32:58.521777 39 ff ff
1472 11:32:58.521957 40 ff ff
1473 11:32:58.525104 41 ff ff
1474 11:32:58.528857 pass bytecount = 0xff (0xff: all bytes pass)
1475 11:32:58.529055
1476 11:32:58.529231 DQS0 dly: 35
1477 11:32:58.532024 DQS1 dly: 28
1478 11:32:58.532554 Write Rank0 MR2 =0x2d
1479 11:32:58.535188 [RankSwap] Rank num 2, (Multi 1), Rank 0
1480 11:32:58.539049 Write Rank1 MR1 =0xd6
1481 11:32:58.539433 [Gating]
1482 11:32:58.539730 ==
1483 11:32:58.545676 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1484 11:32:58.548453 fsp= 1, odt_onoff= 1, Byte mode= 0
1485 11:32:58.548838 ==
1486 11:32:58.552100 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1487 11:32:58.555654 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1488 11:32:58.562283 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1489 11:32:58.565716 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1490 11:32:58.568885 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1491 11:32:58.575595 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1492 11:32:58.578908 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1493 11:32:58.582268 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1494 11:32:58.589026 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1495 11:32:58.592173 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1496 11:32:58.595270 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1497 11:32:58.599084 3 2 12 |2a2a 2c2c |(11 11)(11 0) |(0 0)(0 0)| 0
1498 11:32:58.605384 3 2 16 |3534 303 |(11 11)(11 11) |(0 0)(0 0)| 0
1499 11:32:58.608535 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1500 11:32:58.612045 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1501 11:32:58.618862 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1502 11:32:58.622577 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1503 11:32:58.625629 3 3 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1504 11:32:58.628929 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1505 11:32:58.636183 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1506 11:32:58.639111 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1507 11:32:58.642945 [Byte 0] Lead/lag Transition tap number (1)
1508 11:32:58.646058 [Byte 1] Lead/lag falling Transition (3, 3, 16)
1509 11:32:58.652336 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1510 11:32:58.655874 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1511 11:32:58.659303 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1512 11:32:58.665966 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1513 11:32:58.669358 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1514 11:32:58.673156 3 4 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1515 11:32:58.679075 3 4 12 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1516 11:32:58.682617 3 4 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1517 11:32:58.685748 3 4 20 |3d3d 2121 |(11 11)(11 11) |(1 1)(1 1)| 0
1518 11:32:58.692544 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1519 11:32:58.695840 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1520 11:32:58.699333 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1521 11:32:58.702571 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1522 11:32:58.709462 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1523 11:32:58.712713 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1524 11:32:58.716739 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1525 11:32:58.722732 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1526 11:32:58.726104 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1527 11:32:58.729410 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1528 11:32:58.736479 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1529 11:32:58.739616 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1530 11:32:58.743040 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1531 11:32:58.746384 [Byte 0] Lead/lag Transition tap number (2)
1532 11:32:58.749799 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1533 11:32:58.756674 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1534 11:32:58.759957 [Byte 1] Lead/lag Transition tap number (2)
1535 11:32:58.763099 3 6 12 |202 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1536 11:32:58.766547 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1537 11:32:58.769673 [Byte 0]First pass (3, 6, 16)
1538 11:32:58.772973 3 6 20 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
1539 11:32:58.779942 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1540 11:32:58.780378 [Byte 1]First pass (3, 6, 24)
1541 11:32:58.786080 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1542 11:32:58.789611 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1543 11:32:58.792786 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1544 11:32:58.796129 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1545 11:32:58.799763 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1546 11:32:58.806301 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1547 11:32:58.809833 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1548 11:32:58.813119 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1549 11:32:58.816554 All bytes gating window > 1UI, Early break!
1550 11:32:58.816674
1551 11:32:58.820007 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1552 11:32:58.820115
1553 11:32:58.823399 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1554 11:32:58.823811
1555 11:32:58.826493
1556 11:32:58.826875
1557 11:32:58.830289 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1558 11:32:58.830819
1559 11:32:58.833926 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1560 11:32:58.834324
1561 11:32:58.834685
1562 11:32:58.836976 Write Rank1 MR1 =0x56
1563 11:32:58.837481
1564 11:32:58.840131 best RODT dly(2T, 0.5T) = (2, 3)
1565 11:32:58.840635
1566 11:32:58.840940 best RODT dly(2T, 0.5T) = (2, 3)
1567 11:32:58.843329 ==
1568 11:32:58.846504 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1569 11:32:58.850098 fsp= 1, odt_onoff= 1, Byte mode= 0
1570 11:32:58.850478 ==
1571 11:32:58.853383 Start DQ dly to find pass range UseTestEngine =0
1572 11:32:58.856686 x-axis: bit #, y-axis: DQ dly (-127~63)
1573 11:32:58.860024 RX Vref Scan = 0
1574 11:32:58.863523 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1575 11:32:58.867131 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1576 11:32:58.867522 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1577 11:32:58.870283 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1578 11:32:58.873738 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1579 11:32:58.876591 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1580 11:32:58.880301 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1581 11:32:58.883800 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1582 11:32:58.887281 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1583 11:32:58.890091 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1584 11:32:58.890302 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1585 11:32:58.893619 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1586 11:32:58.897014 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1587 11:32:58.900289 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1588 11:32:58.903684 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1589 11:32:58.906951 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1590 11:32:58.910311 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1591 11:32:58.913506 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1592 11:32:58.913715 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1593 11:32:58.916910 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1594 11:32:58.920108 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1595 11:32:58.923899 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1596 11:32:58.926825 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1597 11:32:58.930624 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1598 11:32:58.933998 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1599 11:32:58.934329 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1600 11:32:58.937119 0, [0] xxxoxxxx xxxoxoxx [MSB]
1601 11:32:58.940661 1, [0] xxxoxoxx ooxoooox [MSB]
1602 11:32:58.943935 2, [0] xxxoxoxx ooxoooox [MSB]
1603 11:32:58.947344 3, [0] xxxoxooo ooxooooo [MSB]
1604 11:32:58.947742 4, [0] xxxoxooo ooxooooo [MSB]
1605 11:32:58.950979 5, [0] xxxoxooo ooxooooo [MSB]
1606 11:32:58.954298 6, [0] xxxooooo oooooooo [MSB]
1607 11:32:58.957128 7, [0] xooooooo oooooooo [MSB]
1608 11:32:58.960919 8, [0] xooooooo oooooooo [MSB]
1609 11:32:58.963995 34, [0] oooooooo oooooooo [MSB]
1610 11:32:58.964271 35, [0] oooxoooo oooxoxoo [MSB]
1611 11:32:58.966961 36, [0] oooxoxoo oooxoxxo [MSB]
1612 11:32:58.970825 37, [0] oooxoxxx xooxoxxo [MSB]
1613 11:32:58.974227 38, [0] oooxoxxx xxoxxxxo [MSB]
1614 11:32:58.977861 39, [0] oooxoxxx xxoxxxxx [MSB]
1615 11:32:58.980636 40, [0] oooxoxxx xxoxxxxx [MSB]
1616 11:32:58.983917 41, [0] oooxoxxx xxoxxxxx [MSB]
1617 11:32:58.984091 42, [0] oooxxxxx xxoxxxxx [MSB]
1618 11:32:58.987529 43, [0] xoxxxxxx xxxxxxxx [MSB]
1619 11:32:58.990546 44, [0] xxxxxxxx xxxxxxxx [MSB]
1620 11:32:58.994131 iDelay=44, Bit 0, Center 25 (9 ~ 42) 34
1621 11:32:58.997695 iDelay=44, Bit 1, Center 25 (7 ~ 43) 37
1622 11:32:59.000610 iDelay=44, Bit 2, Center 24 (7 ~ 42) 36
1623 11:32:59.004099 iDelay=44, Bit 3, Center 17 (0 ~ 34) 35
1624 11:32:59.007516 iDelay=44, Bit 4, Center 23 (6 ~ 41) 36
1625 11:32:59.010654 iDelay=44, Bit 5, Center 18 (1 ~ 35) 35
1626 11:32:59.017734 iDelay=44, Bit 6, Center 19 (3 ~ 36) 34
1627 11:32:59.021448 iDelay=44, Bit 7, Center 19 (3 ~ 36) 34
1628 11:32:59.024266 iDelay=44, Bit 8, Center 18 (1 ~ 36) 36
1629 11:32:59.027403 iDelay=44, Bit 9, Center 19 (1 ~ 37) 37
1630 11:32:59.031149 iDelay=44, Bit 10, Center 24 (6 ~ 42) 37
1631 11:32:59.034319 iDelay=44, Bit 11, Center 17 (0 ~ 34) 35
1632 11:32:59.038040 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
1633 11:32:59.041077 iDelay=44, Bit 13, Center 17 (0 ~ 34) 35
1634 11:32:59.044069 iDelay=44, Bit 14, Center 18 (1 ~ 35) 35
1635 11:32:59.047559 iDelay=44, Bit 15, Center 20 (3 ~ 38) 36
1636 11:32:59.047832 ==
1637 11:32:59.054374 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1638 11:32:59.057796 fsp= 1, odt_onoff= 1, Byte mode= 0
1639 11:32:59.058070 ==
1640 11:32:59.058295 DQS Delay:
1641 11:32:59.060776 DQS0 = 0, DQS1 = 0
1642 11:32:59.061048 DQM Delay:
1643 11:32:59.061309 DQM0 = 21, DQM1 = 19
1644 11:32:59.064275 DQ Delay:
1645 11:32:59.067831 DQ0 =25, DQ1 =25, DQ2 =24, DQ3 =17
1646 11:32:59.071237 DQ4 =23, DQ5 =18, DQ6 =19, DQ7 =19
1647 11:32:59.074351 DQ8 =18, DQ9 =19, DQ10 =24, DQ11 =17
1648 11:32:59.078068 DQ12 =19, DQ13 =17, DQ14 =18, DQ15 =20
1649 11:32:59.078365
1650 11:32:59.078621
1651 11:32:59.078821 DramC Write-DBI off
1652 11:32:59.079115 ==
1653 11:32:59.084747 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1654 11:32:59.088095 fsp= 1, odt_onoff= 1, Byte mode= 0
1655 11:32:59.088484 ==
1656 11:32:59.091082 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1657 11:32:59.091468
1658 11:32:59.094697 Begin, DQ Scan Range 924~1180
1659 11:32:59.095082
1660 11:32:59.095382
1661 11:32:59.098035 TX Vref Scan disable
1662 11:32:59.101380 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1663 11:32:59.104776 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1664 11:32:59.108094 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1665 11:32:59.111536 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1666 11:32:59.114552 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1667 11:32:59.118145 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1668 11:32:59.121408 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1669 11:32:59.124947 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1670 11:32:59.128375 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1671 11:32:59.131813 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1672 11:32:59.134764 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1673 11:32:59.137905 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1674 11:32:59.141406 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1675 11:32:59.145224 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1676 11:32:59.148360 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1677 11:32:59.154656 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1678 11:32:59.158187 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1679 11:32:59.161541 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1680 11:32:59.164666 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1681 11:32:59.168115 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1682 11:32:59.171545 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1683 11:32:59.174721 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1684 11:32:59.178445 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1685 11:32:59.182051 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1686 11:32:59.184748 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1687 11:32:59.187851 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1688 11:32:59.191568 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1689 11:32:59.194675 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1690 11:32:59.197955 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1691 11:32:59.201803 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1692 11:32:59.205172 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1693 11:32:59.208130 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1694 11:32:59.215300 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1695 11:32:59.218238 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1696 11:32:59.221483 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1697 11:32:59.224984 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1698 11:32:59.228496 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1699 11:32:59.231752 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1700 11:32:59.234832 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1701 11:32:59.238748 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1702 11:32:59.241637 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1703 11:32:59.245197 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1704 11:32:59.248283 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1705 11:32:59.251672 967 |3 6 7|[0] xxxxxxxx xxxoxoxx [MSB]
1706 11:32:59.255517 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1707 11:32:59.258539 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB]
1708 11:32:59.262061 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
1709 11:32:59.265433 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1710 11:32:59.268335 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1711 11:32:59.271982 973 |3 6 13|[0] xxxoxxxx oooooooo [MSB]
1712 11:32:59.275116 974 |3 6 14|[0] xxxoxoox oooooooo [MSB]
1713 11:32:59.278690 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1714 11:32:59.282057 976 |3 6 16|[0] xxxoxooo oooooooo [MSB]
1715 11:32:59.285426 977 |3 6 17|[0] xxxoxooo oooooooo [MSB]
1716 11:32:59.288670 978 |3 6 18|[0] xooooooo oooooooo [MSB]
1717 11:32:59.296565 988 |3 6 28|[0] oooooooo oooooxoo [MSB]
1718 11:32:59.299967 989 |3 6 29|[0] oooooooo xooxoxoo [MSB]
1719 11:32:59.303267 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1720 11:32:59.306851 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1721 11:32:59.309985 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1722 11:32:59.313313 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1723 11:32:59.316631 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1724 11:32:59.320165 995 |3 6 35|[0] oooooxoo xxxxxxxx [MSB]
1725 11:32:59.323394 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1726 11:32:59.326608 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1727 11:32:59.330119 998 |3 6 38|[0] oooxoxxo xxxxxxxx [MSB]
1728 11:32:59.333596 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1729 11:32:59.336632 Byte0, DQ PI dly=986, DQM PI dly= 986
1730 11:32:59.340009 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1731 11:32:59.343167
1732 11:32:59.346645 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1733 11:32:59.346816
1734 11:32:59.350129 Byte1, DQ PI dly=978, DQM PI dly= 978
1735 11:32:59.353407 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1736 11:32:59.353647
1737 11:32:59.356865 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1738 11:32:59.360442
1739 11:32:59.360645 ==
1740 11:32:59.363449 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1741 11:32:59.366603 fsp= 1, odt_onoff= 1, Byte mode= 0
1742 11:32:59.366852 ==
1743 11:32:59.370506 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1744 11:32:59.370705
1745 11:32:59.373825 Begin, DQ Scan Range 954~1018
1746 11:32:59.377206 wait MRW command Rank1 MR14 =0x0 fired (1)
1747 11:32:59.380405 Write Rank1 MR14 =0x0
1748 11:32:59.389208
1749 11:32:59.389603 CH=0, VrefRange= 0, VrefLevel = 0
1750 11:32:59.396397 TX Bit0 (981~999) 19 990, Bit8 (969~984) 16 976,
1751 11:32:59.399240 TX Bit1 (979~998) 20 988, Bit9 (969~984) 16 976,
1752 11:32:59.402540 TX Bit2 (980~997) 18 988, Bit10 (975~989) 15 982,
1753 11:32:59.409221 TX Bit3 (974~991) 18 982, Bit11 (968~984) 17 976,
1754 11:32:59.412575 TX Bit4 (979~998) 20 988, Bit12 (969~984) 16 976,
1755 11:32:59.419391 TX Bit5 (977~991) 15 984, Bit13 (969~983) 15 976,
1756 11:32:59.422639 TX Bit6 (977~992) 16 984, Bit14 (969~984) 16 976,
1757 11:32:59.425992 TX Bit7 (978~994) 17 986, Bit15 (973~987) 15 980,
1758 11:32:59.426233
1759 11:32:59.429526 Write Rank1 MR14 =0x2
1760 11:32:59.438149
1761 11:32:59.438359 CH=0, VrefRange= 0, VrefLevel = 2
1762 11:32:59.444459 TX Bit0 (981~999) 19 990, Bit8 (969~985) 17 977,
1763 11:32:59.448408 TX Bit1 (979~998) 20 988, Bit9 (969~984) 16 976,
1764 11:32:59.454685 TX Bit2 (979~998) 20 988, Bit10 (974~990) 17 982,
1765 11:32:59.458058 TX Bit3 (974~992) 19 983, Bit11 (968~984) 17 976,
1766 11:32:59.461503 TX Bit4 (979~998) 20 988, Bit12 (969~985) 17 977,
1767 11:32:59.468355 TX Bit5 (976~991) 16 983, Bit13 (968~984) 17 976,
1768 11:32:59.471711 TX Bit6 (977~993) 17 985, Bit14 (969~984) 16 976,
1769 11:32:59.475405 TX Bit7 (978~994) 17 986, Bit15 (972~988) 17 980,
1770 11:32:59.475974
1771 11:32:59.478372 Write Rank1 MR14 =0x4
1772 11:32:59.487455
1773 11:32:59.487846 CH=0, VrefRange= 0, VrefLevel = 4
1774 11:32:59.515415 TX Bit0 (980~999) 20 989, Bit8 (968~985) 18 976,
1775 11:32:59.515944 TX Bit1 (978~998) 21 988, Bit9 (969~986) 18 977,
1776 11:32:59.516362 TX Bit2 (979~998) 20 988, Bit10 (973~990) 18 981,
1777 11:32:59.516742 TX Bit3 (974~992) 19 983, Bit11 (968~985) 18 976,
1778 11:32:59.517306 TX Bit4 (979~998) 20 988, Bit12 (968~986) 19 977,
1779 11:32:59.518008 TX Bit5 (976~991) 16 983, Bit13 (968~984) 17 976,
1780 11:32:59.521046 TX Bit6 (976~993) 18 984, Bit14 (969~985) 17 977,
1781 11:32:59.524210 TX Bit7 (978~995) 18 986, Bit15 (971~989) 19 980,
1782 11:32:59.524596
1783 11:32:59.527598 Write Rank1 MR14 =0x6
1784 11:32:59.537190
1785 11:32:59.537745 CH=0, VrefRange= 0, VrefLevel = 6
1786 11:32:59.543520 TX Bit0 (979~1000) 22 989, Bit8 (968~986) 19 977,
1787 11:32:59.547123 TX Bit1 (978~999) 22 988, Bit9 (969~987) 19 978,
1788 11:32:59.553648 TX Bit2 (978~998) 21 988, Bit10 (974~990) 17 982,
1789 11:32:59.556988 TX Bit3 (973~993) 21 983, Bit11 (968~985) 18 976,
1790 11:32:59.560542 TX Bit4 (979~999) 21 989, Bit12 (969~986) 18 977,
1791 11:32:59.566646 TX Bit5 (976~992) 17 984, Bit13 (968~984) 17 976,
1792 11:32:59.569812 TX Bit6 (976~994) 19 985, Bit14 (969~986) 18 977,
1793 11:32:59.573254 TX Bit7 (978~996) 19 987, Bit15 (971~989) 19 980,
1794 11:32:59.573395
1795 11:32:59.576799 Write Rank1 MR14 =0x8
1796 11:32:59.586345
1797 11:32:59.586732 CH=0, VrefRange= 0, VrefLevel = 8
1798 11:32:59.592623 TX Bit0 (979~1000) 22 989, Bit8 (968~986) 19 977,
1799 11:32:59.596141 TX Bit1 (978~999) 22 988, Bit9 (968~987) 20 977,
1800 11:32:59.603122 TX Bit2 (978~999) 22 988, Bit10 (972~990) 19 981,
1801 11:32:59.606682 TX Bit3 (973~993) 21 983, Bit11 (968~986) 19 977,
1802 11:32:59.610236 TX Bit4 (978~999) 22 988, Bit12 (968~987) 20 977,
1803 11:32:59.616532 TX Bit5 (976~992) 17 984, Bit13 (968~985) 18 976,
1804 11:32:59.620070 TX Bit6 (975~994) 20 984, Bit14 (968~986) 19 977,
1805 11:32:59.623163 TX Bit7 (977~997) 21 987, Bit15 (971~989) 19 980,
1806 11:32:59.623574
1807 11:32:59.626534 Write Rank1 MR14 =0xa
1808 11:32:59.635124
1809 11:32:59.638585 CH=0, VrefRange= 0, VrefLevel = 10
1810 11:32:59.642093 TX Bit0 (979~1000) 22 989, Bit8 (968~987) 20 977,
1811 11:32:59.645399 TX Bit1 (978~999) 22 988, Bit9 (968~987) 20 977,
1812 11:32:59.651816 TX Bit2 (978~999) 22 988, Bit10 (971~990) 20 980,
1813 11:32:59.655301 TX Bit3 (972~994) 23 983, Bit11 (967~986) 20 976,
1814 11:32:59.658797 TX Bit4 (978~999) 22 988, Bit12 (968~988) 21 978,
1815 11:32:59.665377 TX Bit5 (975~993) 19 984, Bit13 (968~986) 19 977,
1816 11:32:59.668855 TX Bit6 (975~995) 21 985, Bit14 (968~987) 20 977,
1817 11:32:59.671903 TX Bit7 (977~997) 21 987, Bit15 (970~989) 20 979,
1818 11:32:59.672205
1819 11:32:59.675587 Write Rank1 MR14 =0xc
1820 11:32:59.684921
1821 11:32:59.688529 CH=0, VrefRange= 0, VrefLevel = 12
1822 11:32:59.691680 TX Bit0 (978~1001) 24 989, Bit8 (967~987) 21 977,
1823 11:32:59.695000 TX Bit1 (978~999) 22 988, Bit9 (968~988) 21 978,
1824 11:32:59.701623 TX Bit2 (978~999) 22 988, Bit10 (971~991) 21 981,
1825 11:32:59.705233 TX Bit3 (971~994) 24 982, Bit11 (967~987) 21 977,
1826 11:32:59.708469 TX Bit4 (978~999) 22 988, Bit12 (968~988) 21 978,
1827 11:32:59.715467 TX Bit5 (975~993) 19 984, Bit13 (967~986) 20 976,
1828 11:32:59.718671 TX Bit6 (975~996) 22 985, Bit14 (968~988) 21 978,
1829 11:32:59.721654 TX Bit7 (977~998) 22 987, Bit15 (970~990) 21 980,
1830 11:32:59.722051
1831 11:32:59.724836 Write Rank1 MR14 =0xe
1832 11:32:59.734320
1833 11:32:59.737745 CH=0, VrefRange= 0, VrefLevel = 14
1834 11:32:59.741396 TX Bit0 (978~1001) 24 989, Bit8 (968~988) 21 978,
1835 11:32:59.744961 TX Bit1 (977~1000) 24 988, Bit9 (968~989) 22 978,
1836 11:32:59.751114 TX Bit2 (978~999) 22 988, Bit10 (971~991) 21 981,
1837 11:32:59.754699 TX Bit3 (971~995) 25 983, Bit11 (967~988) 22 977,
1838 11:32:59.757960 TX Bit4 (978~1000) 23 989, Bit12 (968~988) 21 978,
1839 11:32:59.764448 TX Bit5 (975~994) 20 984, Bit13 (967~987) 21 977,
1840 11:32:59.767912 TX Bit6 (975~997) 23 986, Bit14 (968~988) 21 978,
1841 11:32:59.771480 TX Bit7 (977~998) 22 987, Bit15 (970~990) 21 980,
1842 11:32:59.771866
1843 11:32:59.774405 Write Rank1 MR14 =0x10
1844 11:32:59.784394
1845 11:32:59.787919 CH=0, VrefRange= 0, VrefLevel = 16
1846 11:32:59.791409 TX Bit0 (978~1002) 25 990, Bit8 (967~988) 22 977,
1847 11:32:59.794749 TX Bit1 (978~1000) 23 989, Bit9 (968~989) 22 978,
1848 11:32:59.800998 TX Bit2 (978~1000) 23 989, Bit10 (970~991) 22 980,
1849 11:32:59.804578 TX Bit3 (971~995) 25 983, Bit11 (967~988) 22 977,
1850 11:32:59.807985 TX Bit4 (977~1000) 24 988, Bit12 (968~989) 22 978,
1851 11:32:59.814961 TX Bit5 (974~994) 21 984, Bit13 (967~987) 21 977,
1852 11:32:59.818229 TX Bit6 (974~997) 24 985, Bit14 (968~989) 22 978,
1853 11:32:59.821365 TX Bit7 (976~998) 23 987, Bit15 (969~990) 22 979,
1854 11:32:59.824637
1855 11:32:59.825028 Write Rank1 MR14 =0x12
1856 11:32:59.834768
1857 11:32:59.837913 CH=0, VrefRange= 0, VrefLevel = 18
1858 11:32:59.841420 TX Bit0 (978~1002) 25 990, Bit8 (967~989) 23 978,
1859 11:32:59.844350 TX Bit1 (977~1000) 24 988, Bit9 (968~989) 22 978,
1860 11:32:59.851115 TX Bit2 (978~1000) 23 989, Bit10 (971~992) 22 981,
1861 11:32:59.854886 TX Bit3 (971~996) 26 983, Bit11 (967~989) 23 978,
1862 11:32:59.857967 TX Bit4 (977~1000) 24 988, Bit12 (968~989) 22 978,
1863 11:32:59.864971 TX Bit5 (973~995) 23 984, Bit13 (967~988) 22 977,
1864 11:32:59.868093 TX Bit6 (974~998) 25 986, Bit14 (968~989) 22 978,
1865 11:32:59.871738 TX Bit7 (976~998) 23 987, Bit15 (969~990) 22 979,
1866 11:32:59.874773
1867 11:32:59.875164 Write Rank1 MR14 =0x14
1868 11:32:59.884709
1869 11:32:59.887993 CH=0, VrefRange= 0, VrefLevel = 20
1870 11:32:59.891507 TX Bit0 (978~1002) 25 990, Bit8 (967~989) 23 978,
1871 11:32:59.894817 TX Bit1 (978~1000) 23 989, Bit9 (968~989) 22 978,
1872 11:32:59.901667 TX Bit2 (977~1000) 24 988, Bit10 (970~992) 23 981,
1873 11:32:59.904801 TX Bit3 (970~996) 27 983, Bit11 (966~989) 24 977,
1874 11:32:59.908047 TX Bit4 (977~1001) 25 989, Bit12 (967~989) 23 978,
1875 11:32:59.914781 TX Bit5 (972~995) 24 983, Bit13 (966~988) 23 977,
1876 11:32:59.918691 TX Bit6 (973~998) 26 985, Bit14 (968~989) 22 978,
1877 11:32:59.922013 TX Bit7 (976~999) 24 987, Bit15 (969~991) 23 980,
1878 11:32:59.922423
1879 11:32:59.924789 Write Rank1 MR14 =0x16
1880 11:32:59.934885
1881 11:32:59.938074 CH=0, VrefRange= 0, VrefLevel = 22
1882 11:32:59.941805 TX Bit0 (978~1003) 26 990, Bit8 (967~989) 23 978,
1883 11:32:59.945464 TX Bit1 (977~1001) 25 989, Bit9 (967~990) 24 978,
1884 11:32:59.951860 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
1885 11:32:59.955253 TX Bit3 (970~996) 27 983, Bit11 (966~989) 24 977,
1886 11:32:59.958685 TX Bit4 (977~1001) 25 989, Bit12 (967~989) 23 978,
1887 11:32:59.965185 TX Bit5 (972~996) 25 984, Bit13 (966~988) 23 977,
1888 11:32:59.968810 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1889 11:32:59.971989 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1890 11:32:59.975031
1891 11:32:59.975420 Write Rank1 MR14 =0x18
1892 11:32:59.985256
1893 11:32:59.989057 CH=0, VrefRange= 0, VrefLevel = 24
1894 11:32:59.992197 TX Bit0 (978~1003) 26 990, Bit8 (967~989) 23 978,
1895 11:32:59.995557 TX Bit1 (977~1001) 25 989, Bit9 (967~990) 24 978,
1896 11:33:00.001948 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
1897 11:33:00.005449 TX Bit3 (970~996) 27 983, Bit11 (966~989) 24 977,
1898 11:33:00.009058 TX Bit4 (977~1001) 25 989, Bit12 (967~989) 23 978,
1899 11:33:00.015955 TX Bit5 (972~996) 25 984, Bit13 (966~988) 23 977,
1900 11:33:00.018679 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1901 11:33:00.022301 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1902 11:33:00.025716
1903 11:33:00.026093 Write Rank1 MR14 =0x1a
1904 11:33:00.035563
1905 11:33:00.038610 CH=0, VrefRange= 0, VrefLevel = 26
1906 11:33:00.042161 TX Bit0 (978~1003) 26 990, Bit8 (967~989) 23 978,
1907 11:33:00.045674 TX Bit1 (977~1001) 25 989, Bit9 (967~990) 24 978,
1908 11:33:00.052363 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
1909 11:33:00.055594 TX Bit3 (970~996) 27 983, Bit11 (966~989) 24 977,
1910 11:33:00.059505 TX Bit4 (977~1001) 25 989, Bit12 (967~989) 23 978,
1911 11:33:00.066171 TX Bit5 (972~996) 25 984, Bit13 (966~988) 23 977,
1912 11:33:00.069097 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1913 11:33:00.072660 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1914 11:33:00.073082
1915 11:33:00.075704 Write Rank1 MR14 =0x1c
1916 11:33:00.085373
1917 11:33:00.085756 CH=0, VrefRange= 0, VrefLevel = 28
1918 11:33:00.092026 TX Bit0 (978~1003) 26 990, Bit8 (967~989) 23 978,
1919 11:33:00.095445 TX Bit1 (977~1001) 25 989, Bit9 (967~990) 24 978,
1920 11:33:00.102410 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
1921 11:33:00.105534 TX Bit3 (970~996) 27 983, Bit11 (966~989) 24 977,
1922 11:33:00.108977 TX Bit4 (977~1001) 25 989, Bit12 (967~989) 23 978,
1923 11:33:00.115761 TX Bit5 (972~996) 25 984, Bit13 (966~988) 23 977,
1924 11:33:00.119287 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1925 11:33:00.122597 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1926 11:33:00.125764
1927 11:33:00.126144 Write Rank1 MR14 =0x1e
1928 11:33:00.135746
1929 11:33:00.139012 CH=0, VrefRange= 0, VrefLevel = 30
1930 11:33:00.142211 TX Bit0 (978~1003) 26 990, Bit8 (967~989) 23 978,
1931 11:33:00.145528 TX Bit1 (977~1001) 25 989, Bit9 (967~990) 24 978,
1932 11:33:00.152170 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
1933 11:33:00.155474 TX Bit3 (970~996) 27 983, Bit11 (966~989) 24 977,
1934 11:33:00.158577 TX Bit4 (977~1001) 25 989, Bit12 (967~989) 23 978,
1935 11:33:00.165587 TX Bit5 (972~996) 25 984, Bit13 (966~988) 23 977,
1936 11:33:00.168655 TX Bit6 (972~998) 27 985, Bit14 (967~989) 23 978,
1937 11:33:00.172321 TX Bit7 (975~999) 25 987, Bit15 (969~990) 22 979,
1938 11:33:00.176016
1939 11:33:00.176218
1940 11:33:00.178587 TX Vref found, early break! 364< 370
1941 11:33:00.182072 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
1942 11:33:00.185441 u1DelayCellOfst[0]=8 cells (7 PI)
1943 11:33:00.188690 u1DelayCellOfst[1]=7 cells (6 PI)
1944 11:33:00.192633 u1DelayCellOfst[2]=6 cells (5 PI)
1945 11:33:00.195578 u1DelayCellOfst[3]=0 cells (0 PI)
1946 11:33:00.195829 u1DelayCellOfst[4]=7 cells (6 PI)
1947 11:33:00.199149 u1DelayCellOfst[5]=1 cells (1 PI)
1948 11:33:00.202795 u1DelayCellOfst[6]=2 cells (2 PI)
1949 11:33:00.205689 u1DelayCellOfst[7]=5 cells (4 PI)
1950 11:33:00.208844 Byte0, DQ PI dly=983, DQM PI dly= 986
1951 11:33:00.215795 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1952 11:33:00.216088
1953 11:33:00.219365 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1954 11:33:00.219700
1955 11:33:00.222273 u1DelayCellOfst[8]=1 cells (1 PI)
1956 11:33:00.225840 u1DelayCellOfst[9]=1 cells (1 PI)
1957 11:33:00.229299 u1DelayCellOfst[10]=3 cells (3 PI)
1958 11:33:00.232219 u1DelayCellOfst[11]=0 cells (0 PI)
1959 11:33:00.232546 u1DelayCellOfst[12]=1 cells (1 PI)
1960 11:33:00.235716 u1DelayCellOfst[13]=0 cells (0 PI)
1961 11:33:00.239157 u1DelayCellOfst[14]=1 cells (1 PI)
1962 11:33:00.242257 u1DelayCellOfst[15]=2 cells (2 PI)
1963 11:33:00.246133 Byte1, DQ PI dly=977, DQM PI dly= 978
1964 11:33:00.252602 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1965 11:33:00.252860
1966 11:33:00.255918 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1967 11:33:00.256172
1968 11:33:00.259936 Write Rank1 MR14 =0x16
1969 11:33:00.260184
1970 11:33:00.260378 Final TX Range 0 Vref 22
1971 11:33:00.260619
1972 11:33:00.265987 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1973 11:33:00.266238
1974 11:33:00.272929 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1975 11:33:00.279758 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1976 11:33:00.286604 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1977 11:33:00.289391 Write Rank1 MR3 =0xb0
1978 11:33:00.292984 DramC Write-DBI on
1979 11:33:00.293407 ==
1980 11:33:00.296271 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1981 11:33:00.299207 fsp= 1, odt_onoff= 1, Byte mode= 0
1982 11:33:00.299645 ==
1983 11:33:00.302679 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1984 11:33:00.303082
1985 11:33:00.306330 Begin, DQ Scan Range 698~762
1986 11:33:00.306706
1987 11:33:00.306996
1988 11:33:00.309947 TX Vref Scan disable
1989 11:33:00.312702 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1990 11:33:00.316322 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1991 11:33:00.319191 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1992 11:33:00.322700 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1993 11:33:00.325817 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1994 11:33:00.329403 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1995 11:33:00.332567 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1996 11:33:00.336107 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1997 11:33:00.339626 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1998 11:33:00.342537 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1999 11:33:00.346089 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
2000 11:33:00.349261 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
2001 11:33:00.352750 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2002 11:33:00.355831 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2003 11:33:00.362850 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2004 11:33:00.366331 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2005 11:33:00.369867 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2006 11:33:00.372977 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2007 11:33:00.376340 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2008 11:33:00.379292 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2009 11:33:00.386426 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
2010 11:33:00.389801 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2011 11:33:00.393188 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2012 11:33:00.396455 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2013 11:33:00.400307 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2014 11:33:00.403230 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2015 11:33:00.407030 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2016 11:33:00.410017 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2017 11:33:00.413434 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2018 11:33:00.416410 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2019 11:33:00.419875 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2020 11:33:00.423606 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
2021 11:33:00.426599 Byte0, DQ PI dly=731, DQM PI dly= 731
2022 11:33:00.430303 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
2023 11:33:00.433243
2024 11:33:00.437317 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
2025 11:33:00.437707
2026 11:33:00.440259 Byte1, DQ PI dly=720, DQM PI dly= 720
2027 11:33:00.443593 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 16)
2028 11:33:00.444105
2029 11:33:00.446896 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 16)
2030 11:33:00.450340
2031 11:33:00.453352 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2032 11:33:00.463940 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2033 11:33:00.470322 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2034 11:33:00.470748 Write Rank1 MR3 =0x30
2035 11:33:00.473689 DramC Write-DBI off
2036 11:33:00.474076
2037 11:33:00.474416 [DATLAT]
2038 11:33:00.476997 Freq=1600, CH0 RK1, use_rxtx_scan=0
2039 11:33:00.477449
2040 11:33:00.480261 DATLAT Default: 0x10
2041 11:33:00.480651 7, 0xFFFF, sum=0
2042 11:33:00.483772 8, 0xFFFF, sum=0
2043 11:33:00.484291 9, 0xFFFF, sum=0
2044 11:33:00.487101 10, 0xFFFF, sum=0
2045 11:33:00.487761 11, 0xFFFF, sum=0
2046 11:33:00.490609 12, 0xFFFF, sum=0
2047 11:33:00.491005 13, 0xFFFF, sum=0
2048 11:33:00.491310 14, 0x0, sum=1
2049 11:33:00.494008 15, 0x0, sum=2
2050 11:33:00.494414 16, 0x0, sum=3
2051 11:33:00.496828 17, 0x0, sum=4
2052 11:33:00.500262 pattern=2 first_step=14 total pass=5 best_step=16
2053 11:33:00.500661 ==
2054 11:33:00.504403 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2055 11:33:00.507365 fsp= 1, odt_onoff= 1, Byte mode= 0
2056 11:33:00.510819 ==
2057 11:33:00.513822 Start DQ dly to find pass range UseTestEngine =1
2058 11:33:00.517478 x-axis: bit #, y-axis: DQ dly (-127~63)
2059 11:33:00.517862 RX Vref Scan = 0
2060 11:33:00.520483 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2061 11:33:00.524429 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2062 11:33:00.527060 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2063 11:33:00.530787 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2064 11:33:00.533952 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2065 11:33:00.537483 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2066 11:33:00.537774 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2067 11:33:00.540721 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2068 11:33:00.543744 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2069 11:33:00.546892 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2070 11:33:00.550210 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2071 11:33:00.554269 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2072 11:33:00.557540 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2073 11:33:00.560395 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2074 11:33:00.560538 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2075 11:33:00.563700 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2076 11:33:00.567212 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2077 11:33:00.570341 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2078 11:33:00.573986 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2079 11:33:00.577594 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2080 11:33:00.580847 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2081 11:33:00.580924 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2082 11:33:00.583632 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2083 11:33:00.587214 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2084 11:33:00.590471 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2085 11:33:00.593790 -1, [0] xxxoxxxx xxxxxoxx [MSB]
2086 11:33:00.597115 0, [0] xxxoxxxx oxxxxoxx [MSB]
2087 11:33:00.597236 1, [0] xxxoxoxx ooxoooox [MSB]
2088 11:33:00.600843 2, [0] xxxoxooo ooxoooox [MSB]
2089 11:33:00.604318 3, [0] xxxoxooo ooxooooo [MSB]
2090 11:33:00.607580 4, [0] xxxoxooo ooxooooo [MSB]
2091 11:33:00.611119 5, [0] xxxooooo ooxooooo [MSB]
2092 11:33:00.614082 6, [0] xxxooooo oooooooo [MSB]
2093 11:33:00.614163 7, [0] xooooooo oooooooo [MSB]
2094 11:33:00.617372 8, [0] xooooooo oooooooo [MSB]
2095 11:33:00.622311 34, [0] oooxoooo oooxoooo [MSB]
2096 11:33:00.625249 35, [0] oooxoxoo oooxoxoo [MSB]
2097 11:33:00.629099 36, [0] oooxoxxo oooxoxoo [MSB]
2098 11:33:00.632096 37, [0] oooxoxxx xooxxxxo [MSB]
2099 11:33:00.635474 38, [0] oooxoxxx xooxxxxo [MSB]
2100 11:33:00.638937 39, [0] oooxoxxx xxoxxxxx [MSB]
2101 11:33:00.639072 40, [0] oooxoxxx xxoxxxxx [MSB]
2102 11:33:00.642238 41, [0] oooxxxxx xxoxxxxx [MSB]
2103 11:33:00.645928 42, [0] oooxxxxx xxxxxxxx [MSB]
2104 11:33:00.649356 43, [0] oxxxxxxx xxxxxxxx [MSB]
2105 11:33:00.652877 44, [0] xxxxxxxx xxxxxxxx [MSB]
2106 11:33:00.655818 iDelay=44, Bit 0, Center 26 (9 ~ 43) 35
2107 11:33:00.658875 iDelay=44, Bit 1, Center 24 (7 ~ 42) 36
2108 11:33:00.662248 iDelay=44, Bit 2, Center 24 (7 ~ 42) 36
2109 11:33:00.665775 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2110 11:33:00.669547 iDelay=44, Bit 4, Center 22 (5 ~ 40) 36
2111 11:33:00.672911 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2112 11:33:00.676349 iDelay=44, Bit 6, Center 18 (2 ~ 35) 34
2113 11:33:00.679387 iDelay=44, Bit 7, Center 19 (2 ~ 36) 35
2114 11:33:00.683126 iDelay=44, Bit 8, Center 18 (0 ~ 36) 37
2115 11:33:00.686612 iDelay=44, Bit 9, Center 19 (1 ~ 38) 38
2116 11:33:00.689654 iDelay=44, Bit 10, Center 23 (6 ~ 41) 36
2117 11:33:00.692787 iDelay=44, Bit 11, Center 17 (1 ~ 33) 33
2118 11:33:00.699975 iDelay=44, Bit 12, Center 18 (1 ~ 36) 36
2119 11:33:00.703402 iDelay=44, Bit 13, Center 16 (-1 ~ 34) 36
2120 11:33:00.706295 iDelay=44, Bit 14, Center 18 (1 ~ 36) 36
2121 11:33:00.709908 iDelay=44, Bit 15, Center 20 (3 ~ 38) 36
2122 11:33:00.710181 ==
2123 11:33:00.712870 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2124 11:33:00.716538 fsp= 1, odt_onoff= 1, Byte mode= 0
2125 11:33:00.716999 ==
2126 11:33:00.719545 DQS Delay:
2127 11:33:00.719972 DQS0 = 0, DQS1 = 0
2128 11:33:00.723963 DQM Delay:
2129 11:33:00.724343 DQM0 = 20, DQM1 = 18
2130 11:33:00.724645 DQ Delay:
2131 11:33:00.726520 DQ0 =26, DQ1 =24, DQ2 =24, DQ3 =15
2132 11:33:00.730073 DQ4 =22, DQ5 =17, DQ6 =18, DQ7 =19
2133 11:33:00.733499 DQ8 =18, DQ9 =19, DQ10 =23, DQ11 =17
2134 11:33:00.737084 DQ12 =18, DQ13 =16, DQ14 =18, DQ15 =20
2135 11:33:00.737645
2136 11:33:00.737962
2137 11:33:00.738254
2138 11:33:00.740094 [DramC_TX_OE_Calibration] TA2
2139 11:33:00.743497 Original DQ_B0 (3 6) =30, OEN = 27
2140 11:33:00.746418 Original DQ_B1 (3 6) =30, OEN = 27
2141 11:33:00.750419 23, 0x0, End_B0=23 End_B1=23
2142 11:33:00.753591 24, 0x0, End_B0=24 End_B1=24
2143 11:33:00.753979 25, 0x0, End_B0=25 End_B1=25
2144 11:33:00.756968 26, 0x0, End_B0=26 End_B1=26
2145 11:33:00.760481 27, 0x0, End_B0=27 End_B1=27
2146 11:33:00.763514 28, 0x0, End_B0=28 End_B1=28
2147 11:33:00.763902 29, 0x0, End_B0=29 End_B1=29
2148 11:33:00.766868 30, 0x0, End_B0=30 End_B1=30
2149 11:33:00.770358 31, 0xFFFE, End_B0=30 End_B1=30
2150 11:33:00.777065 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2151 11:33:00.780768 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2152 11:33:00.781193
2153 11:33:00.781500
2154 11:33:00.783821 Write Rank1 MR23 =0x3f
2155 11:33:00.784198 [DQSOSC]
2156 11:33:00.791096 [DQSOSCAuto] RK1, (LSB)MR18= 0x77, (MSB)MR19= 0x3, tDQSOscB0 = 355 ps tDQSOscB1 = 0 ps
2157 11:33:00.797025 CH0_RK1: MR19=0x3, MR18=0x77, DQSOSC=355, MR23=63, INC=19, DEC=29
2158 11:33:00.800652 Write Rank1 MR23 =0x3f
2159 11:33:00.801176 [DQSOSC]
2160 11:33:00.807142 [DQSOSCAuto] RK1, (LSB)MR18= 0x77, (MSB)MR19= 0x3, tDQSOscB0 = 355 ps tDQSOscB1 = 0 ps
2161 11:33:00.810677 CH0 RK1: MR19=3, MR18=77
2162 11:33:00.814247 [RxdqsGatingPostProcess] freq 1600
2163 11:33:00.820602 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2164 11:33:00.820996 Rank: 0
2165 11:33:00.824464 best DQS0 dly(2T, 0.5T) = (2, 5)
2166 11:33:00.827315 best DQS1 dly(2T, 0.5T) = (2, 5)
2167 11:33:00.831070 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2168 11:33:00.831443 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2169 11:33:00.834371 Rank: 1
2170 11:33:00.837586 best DQS0 dly(2T, 0.5T) = (2, 6)
2171 11:33:00.837976 best DQS1 dly(2T, 0.5T) = (2, 6)
2172 11:33:00.840736 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2173 11:33:00.844604 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2174 11:33:00.850782 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2175 11:33:00.854150 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2176 11:33:00.857490 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2177 11:33:00.861307 Write Rank0 MR13 =0x59
2178 11:33:00.861697 ==
2179 11:33:00.864712 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2180 11:33:00.868144 fsp= 1, odt_onoff= 1, Byte mode= 0
2181 11:33:00.868534 ==
2182 11:33:00.871111 === u2Vref_new: 0x56 --> 0x3a
2183 11:33:00.874863 === u2Vref_new: 0x58 --> 0x58
2184 11:33:00.877811 === u2Vref_new: 0x5a --> 0x5a
2185 11:33:00.882071 === u2Vref_new: 0x5c --> 0x78
2186 11:33:00.884394 === u2Vref_new: 0x5e --> 0x7a
2187 11:33:00.887734 === u2Vref_new: 0x60 --> 0x90
2188 11:33:00.891131 [CA 0] Center 36 (9~63) winsize 55
2189 11:33:00.894870 [CA 1] Center 35 (7~63) winsize 57
2190 11:33:00.897871 [CA 2] Center 32 (4~61) winsize 58
2191 11:33:00.901408 [CA 3] Center 33 (3~63) winsize 61
2192 11:33:00.904785 [CA 4] Center 33 (4~63) winsize 60
2193 11:33:00.905221 [CA 5] Center 26 (-1~53) winsize 55
2194 11:33:00.907767
2195 11:33:00.910965 [CATrainingPosCal] consider 1 rank data
2196 11:33:00.911346 u2DelayCellTimex100 = 762/100 ps
2197 11:33:00.918180 CA0 delay=36 (9~63),Diff = 10 PI (12 cell)
2198 11:33:00.921082 CA1 delay=35 (7~63),Diff = 9 PI (11 cell)
2199 11:33:00.924520 CA2 delay=32 (4~61),Diff = 6 PI (7 cell)
2200 11:33:00.928127 CA3 delay=33 (3~63),Diff = 7 PI (8 cell)
2201 11:33:00.931401 CA4 delay=33 (4~63),Diff = 7 PI (8 cell)
2202 11:33:00.934711 CA5 delay=26 (-1~53),Diff = 0 PI (0 cell)
2203 11:33:00.935095
2204 11:33:00.938460 CA PerBit enable=1, Macro0, CA PI delay=26
2205 11:33:00.941682 === u2Vref_new: 0x58 --> 0x58
2206 11:33:00.942064
2207 11:33:00.944774 Vref(ca) range 1: 24
2208 11:33:00.945177
2209 11:33:00.945481 CS Dly= 10 (41-0-32)
2210 11:33:00.947975 Write Rank0 MR13 =0xd8
2211 11:33:00.951398 Write Rank0 MR13 =0xd8
2212 11:33:00.951674 Write Rank0 MR12 =0x58
2213 11:33:00.954624 Write Rank1 MR13 =0x59
2214 11:33:00.954899 ==
2215 11:33:00.958273 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2216 11:33:00.961437 fsp= 1, odt_onoff= 1, Byte mode= 0
2217 11:33:00.961605 ==
2218 11:33:00.964587 === u2Vref_new: 0x56 --> 0x3a
2219 11:33:00.967771 === u2Vref_new: 0x58 --> 0x58
2220 11:33:00.971122 === u2Vref_new: 0x5a --> 0x5a
2221 11:33:00.974991 === u2Vref_new: 0x5c --> 0x78
2222 11:33:00.978016 === u2Vref_new: 0x5e --> 0x7a
2223 11:33:00.981230 === u2Vref_new: 0x60 --> 0x90
2224 11:33:00.984990 [CA 0] Center 36 (10~63) winsize 54
2225 11:33:00.988487 [CA 1] Center 35 (7~63) winsize 57
2226 11:33:00.991609 [CA 2] Center 33 (4~62) winsize 59
2227 11:33:00.995017 [CA 3] Center 33 (3~63) winsize 61
2228 11:33:00.998315 [CA 4] Center 33 (4~63) winsize 60
2229 11:33:00.998512 [CA 5] Center 26 (-1~53) winsize 55
2230 11:33:01.002072
2231 11:33:01.005188 [CATrainingPosCal] consider 2 rank data
2232 11:33:01.005426 u2DelayCellTimex100 = 762/100 ps
2233 11:33:01.011777 CA0 delay=36 (10~63),Diff = 10 PI (12 cell)
2234 11:33:01.015120 CA1 delay=35 (7~63),Diff = 9 PI (11 cell)
2235 11:33:01.018682 CA2 delay=32 (4~61),Diff = 6 PI (7 cell)
2236 11:33:01.021669 CA3 delay=33 (3~63),Diff = 7 PI (8 cell)
2237 11:33:01.024871 CA4 delay=33 (4~63),Diff = 7 PI (8 cell)
2238 11:33:01.028253 CA5 delay=26 (-1~53),Diff = 0 PI (0 cell)
2239 11:33:01.028657
2240 11:33:01.031666 CA PerBit enable=1, Macro0, CA PI delay=26
2241 11:33:01.035212 === u2Vref_new: 0x58 --> 0x58
2242 11:33:01.035639
2243 11:33:01.038813 Vref(ca) range 1: 24
2244 11:33:01.039198
2245 11:33:01.039570 CS Dly= 11 (42-0-32)
2246 11:33:01.041853 Write Rank1 MR13 =0xd8
2247 11:33:01.045394 Write Rank1 MR13 =0xd8
2248 11:33:01.045777 Write Rank1 MR12 =0x58
2249 11:33:01.049036 [RankSwap] Rank num 2, (Multi 1), Rank 0
2250 11:33:01.051934 Write Rank0 MR2 =0xad
2251 11:33:01.052313 [Write Leveling]
2252 11:33:01.054896 delay byte0 byte1 byte2 byte3
2253 11:33:01.055274
2254 11:33:01.058236 10 0 0
2255 11:33:01.058629 11 0 0
2256 11:33:01.061769 12 0 0
2257 11:33:01.062162 13 0 0
2258 11:33:01.062665 14 0 0
2259 11:33:01.064817 15 0 0
2260 11:33:01.065235 16 0 0
2261 11:33:01.068389 17 0 0
2262 11:33:01.068784 18 0 0
2263 11:33:01.069091 19 0 0
2264 11:33:01.071724 20 0 0
2265 11:33:01.072157 21 0 0
2266 11:33:01.075228 22 0 0
2267 11:33:01.075697 23 0 0
2268 11:33:01.078755 24 0 0
2269 11:33:01.079224 25 0 0
2270 11:33:01.079538 26 0 0
2271 11:33:01.082150 27 0 0
2272 11:33:01.082546 28 0 0
2273 11:33:01.084992 29 0 0
2274 11:33:01.085447 30 0 0
2275 11:33:01.085758 31 0 ff
2276 11:33:01.088366 32 0 ff
2277 11:33:01.088762 33 0 ff
2278 11:33:01.091639 34 0 ff
2279 11:33:01.091919 35 0 ff
2280 11:33:01.095424 36 ff ff
2281 11:33:01.095706 37 ff ff
2282 11:33:01.098338 38 ff ff
2283 11:33:01.098688 39 ff ff
2284 11:33:01.098927 40 ff ff
2285 11:33:01.102111 41 ff ff
2286 11:33:01.102387 42 ff ff
2287 11:33:01.108656 pass bytecount = 0xff (0xff: all bytes pass)
2288 11:33:01.108929
2289 11:33:01.109167 DQS0 dly: 36
2290 11:33:01.109377 DQS1 dly: 31
2291 11:33:01.112277 Write Rank0 MR2 =0x2d
2292 11:33:01.115222 [RankSwap] Rank num 2, (Multi 1), Rank 0
2293 11:33:01.118735 Write Rank0 MR1 =0xd6
2294 11:33:01.119070 [Gating]
2295 11:33:01.119289 ==
2296 11:33:01.122131 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2297 11:33:01.125412 fsp= 1, odt_onoff= 1, Byte mode= 0
2298 11:33:01.128945 ==
2299 11:33:01.132609 3 1 0 |302f 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2300 11:33:01.135405 3 1 4 |a09 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2301 11:33:01.139048 3 1 8 |1515 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2302 11:33:01.145847 3 1 12 |1a19 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2303 11:33:01.149055 3 1 16 |1d1c 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2304 11:33:01.152246 3 1 20 |2a29 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2305 11:33:01.158992 3 1 24 |2e2e 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2306 11:33:01.163096 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2307 11:33:01.166047 3 2 0 |3938 504 |(11 11)(11 11) |(0 0)(1 1)| 0
2308 11:33:01.169021 3 2 4 |3736 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2309 11:33:01.175653 3 2 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2310 11:33:01.179383 3 2 12 |3636 3d3d |(0 0)(11 11) |(1 1)(1 1)| 0
2311 11:33:01.182405 3 2 16 |e0d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2312 11:33:01.185831 [Byte 0] Lead/lag Transition tap number (1)
2313 11:33:01.192608 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2314 11:33:01.195937 3 2 24 |3636 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2315 11:33:01.199934 3 2 28 |b0a 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2316 11:33:01.205817 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 1)(1 1)| 0
2317 11:33:01.209176 3 3 4 |3534 909 |(11 11)(11 11) |(0 1)(1 1)| 0
2318 11:33:01.212713 3 3 8 |3534 1a19 |(11 11)(11 11) |(0 1)(1 1)| 0
2319 11:33:01.215813 [Byte 1] Lead/lag falling Transition (3, 3, 8)
2320 11:33:01.222552 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2321 11:33:01.225759 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2322 11:33:01.229705 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2323 11:33:01.235734 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2324 11:33:01.239495 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2325 11:33:01.242448 3 4 0 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2326 11:33:01.246070 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2327 11:33:01.252498 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2328 11:33:01.256228 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2329 11:33:01.259166 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2330 11:33:01.265836 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2331 11:33:01.269658 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2332 11:33:01.272749 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2333 11:33:01.279883 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2334 11:33:01.282961 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2335 11:33:01.286488 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2336 11:33:01.289951 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2337 11:33:01.296167 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2338 11:33:01.299832 [Byte 0] Lead/lag falling Transition (3, 5, 16)
2339 11:33:01.302832 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2340 11:33:01.306397 [Byte 0] Lead/lag Transition tap number (2)
2341 11:33:01.313093 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2342 11:33:01.316232 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2343 11:33:01.319792 3 5 28 |403 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2344 11:33:01.323479 [Byte 1] Lead/lag Transition tap number (2)
2345 11:33:01.329826 3 6 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2346 11:33:01.330174 [Byte 0]First pass (3, 6, 0)
2347 11:33:01.336659 3 6 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2348 11:33:01.337090 [Byte 1]First pass (3, 6, 4)
2349 11:33:01.343319 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2350 11:33:01.346754 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2351 11:33:01.350666 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2352 11:33:01.353899 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2353 11:33:01.357389 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2354 11:33:01.364072 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2355 11:33:01.367161 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2356 11:33:01.370359 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2357 11:33:01.373512 All bytes gating window > 1UI, Early break!
2358 11:33:01.373900
2359 11:33:01.377124 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
2360 11:33:01.377556
2361 11:33:01.380033 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
2362 11:33:01.380419
2363 11:33:01.383587
2364 11:33:01.383967
2365 11:33:01.387032 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
2366 11:33:01.387420
2367 11:33:01.390209 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
2368 11:33:01.390593
2369 11:33:01.390887
2370 11:33:01.393803 Write Rank0 MR1 =0x56
2371 11:33:01.394182
2372 11:33:01.397093 best RODT dly(2T, 0.5T) = (2, 2)
2373 11:33:01.397505
2374 11:33:01.397806 best RODT dly(2T, 0.5T) = (2, 2)
2375 11:33:01.400368 ==
2376 11:33:01.403650 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2377 11:33:01.407201 fsp= 1, odt_onoff= 1, Byte mode= 0
2378 11:33:01.407617 ==
2379 11:33:01.410453 Start DQ dly to find pass range UseTestEngine =0
2380 11:33:01.414125 x-axis: bit #, y-axis: DQ dly (-127~63)
2381 11:33:01.417032 RX Vref Scan = 0
2382 11:33:01.420540 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2383 11:33:01.424061 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2384 11:33:01.426988 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2385 11:33:01.427563 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2386 11:33:01.430389 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2387 11:33:01.434088 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2388 11:33:01.437429 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2389 11:33:01.440300 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2390 11:33:01.443925 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2391 11:33:01.447418 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2392 11:33:01.450931 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2393 11:33:01.451342 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2394 11:33:01.453818 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2395 11:33:01.457601 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2396 11:33:01.460569 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2397 11:33:01.464025 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2398 11:33:01.467472 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2399 11:33:01.470653 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2400 11:33:01.471045 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2401 11:33:01.474211 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2402 11:33:01.477356 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2403 11:33:01.480742 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2404 11:33:01.484320 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2405 11:33:01.487825 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2406 11:33:01.490854 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2407 11:33:01.491244 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2408 11:33:01.494456 0, [0] xxxoxxxx xxxxxxxx [MSB]
2409 11:33:01.497456 1, [0] xxxoxxxx xxxxxxxo [MSB]
2410 11:33:01.501231 2, [0] xxooxxxo xxxxxxxo [MSB]
2411 11:33:01.504640 3, [0] xxoooxxo xxxxxoxo [MSB]
2412 11:33:01.507495 4, [0] xxoooxxo oooooooo [MSB]
2413 11:33:01.507880 5, [0] xxoooxxo oooooooo [MSB]
2414 11:33:01.510842 6, [0] xooooxxo oooooooo [MSB]
2415 11:33:01.514139 7, [0] xoooooxo oooooooo [MSB]
2416 11:33:01.517758 8, [0] xoooooxo oooooooo [MSB]
2417 11:33:01.520754 32, [0] ooxxoooo oooooooo [MSB]
2418 11:33:01.524417 33, [0] ooxxoooo ooooooox [MSB]
2419 11:33:01.524808 34, [0] ooxxoooo ooooooox [MSB]
2420 11:33:01.527607 35, [0] ooxxoooo ooxoooox [MSB]
2421 11:33:01.530930 36, [0] ooxxxoox xoxoooox [MSB]
2422 11:33:01.534104 37, [0] ooxxxoox xxxxoxxx [MSB]
2423 11:33:01.537838 38, [0] ooxxxoox xxxxoxxx [MSB]
2424 11:33:01.540539 39, [0] ooxxxoox xxxxxxxx [MSB]
2425 11:33:01.544055 40, [0] oxxxxoox xxxxxxxx [MSB]
2426 11:33:01.544505 41, [0] xxxxxxxx xxxxxxxx [MSB]
2427 11:33:01.547802 iDelay=41, Bit 0, Center 24 (9 ~ 40) 32
2428 11:33:01.551207 iDelay=41, Bit 1, Center 22 (6 ~ 39) 34
2429 11:33:01.557664 iDelay=41, Bit 2, Center 16 (2 ~ 31) 30
2430 11:33:01.560883 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
2431 11:33:01.564421 iDelay=41, Bit 4, Center 19 (3 ~ 35) 33
2432 11:33:01.567629 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2433 11:33:01.571001 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
2434 11:33:01.574775 iDelay=41, Bit 7, Center 18 (2 ~ 35) 34
2435 11:33:01.577566 iDelay=41, Bit 8, Center 19 (4 ~ 35) 32
2436 11:33:01.581086 iDelay=41, Bit 9, Center 20 (4 ~ 36) 33
2437 11:33:01.584301 iDelay=41, Bit 10, Center 19 (4 ~ 34) 31
2438 11:33:01.587891 iDelay=41, Bit 11, Center 20 (4 ~ 36) 33
2439 11:33:01.590870 iDelay=41, Bit 12, Center 21 (4 ~ 38) 35
2440 11:33:01.594465 iDelay=41, Bit 13, Center 19 (3 ~ 36) 34
2441 11:33:01.597411 iDelay=41, Bit 14, Center 20 (4 ~ 36) 33
2442 11:33:01.601182 iDelay=41, Bit 15, Center 16 (1 ~ 32) 32
2443 11:33:01.604240 ==
2444 11:33:01.607546 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2445 11:33:01.611471 fsp= 1, odt_onoff= 1, Byte mode= 0
2446 11:33:01.611786 ==
2447 11:33:01.612094 DQS Delay:
2448 11:33:01.614193 DQS0 = 0, DQS1 = 0
2449 11:33:01.614502 DQM Delay:
2450 11:33:01.617745 DQM0 = 20, DQM1 = 19
2451 11:33:01.618054 DQ Delay:
2452 11:33:01.620778 DQ0 =24, DQ1 =22, DQ2 =16, DQ3 =15
2453 11:33:01.624297 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =18
2454 11:33:01.627568 DQ8 =19, DQ9 =20, DQ10 =19, DQ11 =20
2455 11:33:01.631271 DQ12 =21, DQ13 =19, DQ14 =20, DQ15 =16
2456 11:33:01.631564
2457 11:33:01.631792
2458 11:33:01.634696 DramC Write-DBI off
2459 11:33:01.634988 ==
2460 11:33:01.637874 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2461 11:33:01.641061 fsp= 1, odt_onoff= 1, Byte mode= 0
2462 11:33:01.641397 ==
2463 11:33:01.644407 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2464 11:33:01.647826
2465 11:33:01.648117 Begin, DQ Scan Range 927~1183
2466 11:33:01.648346
2467 11:33:01.648553
2468 11:33:01.650818 TX Vref Scan disable
2469 11:33:01.654211 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2470 11:33:01.657848 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2471 11:33:01.660857 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2472 11:33:01.663866 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2473 11:33:01.667114 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2474 11:33:01.670521 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2475 11:33:01.674097 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2476 11:33:01.680869 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2477 11:33:01.683843 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2478 11:33:01.687290 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2479 11:33:01.690473 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2480 11:33:01.694098 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2481 11:33:01.697458 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2482 11:33:01.700923 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2483 11:33:01.704539 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2484 11:33:01.707331 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2485 11:33:01.710755 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2486 11:33:01.714637 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2487 11:33:01.717807 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2488 11:33:01.721128 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2489 11:33:01.723911 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2490 11:33:01.727255 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2491 11:33:01.730926 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2492 11:33:01.737485 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2493 11:33:01.740859 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2494 11:33:01.743883 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2495 11:33:01.747492 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2496 11:33:01.750931 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2497 11:33:01.754254 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2498 11:33:01.757415 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2499 11:33:01.761094 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2500 11:33:01.764059 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2501 11:33:01.767555 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2502 11:33:01.770633 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2503 11:33:01.774034 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2504 11:33:01.777538 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2505 11:33:01.781282 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2506 11:33:01.784349 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2507 11:33:01.787584 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB]
2508 11:33:01.790595 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB]
2509 11:33:01.794550 967 |3 6 7|[0] xxxxxxxx ooxxxxxo [MSB]
2510 11:33:01.797385 968 |3 6 8|[0] xxxxxxxx oooxxxoo [MSB]
2511 11:33:01.800670 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB]
2512 11:33:01.804337 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
2513 11:33:01.807741 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
2514 11:33:01.814018 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
2515 11:33:01.817369 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
2516 11:33:01.821095 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2517 11:33:01.824141 975 |3 6 15|[0] xxooxxxx oooooooo [MSB]
2518 11:33:01.827862 976 |3 6 16|[0] xooooxxo oooooooo [MSB]
2519 11:33:01.830813 977 |3 6 17|[0] ooooooxo oooooooo [MSB]
2520 11:33:01.834513 989 |3 6 29|[0] oooooooo ooooooox [MSB]
2521 11:33:01.840777 990 |3 6 30|[0] oooooooo oxooooox [MSB]
2522 11:33:01.843854 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2523 11:33:01.847186 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2524 11:33:01.850466 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2525 11:33:01.853876 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
2526 11:33:01.857442 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
2527 11:33:01.860709 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
2528 11:33:01.864331 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
2529 11:33:01.867191 998 |3 6 38|[0] ooxxooox xxxxxxxx [MSB]
2530 11:33:01.870630 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2531 11:33:01.873899 Byte0, DQ PI dly=986, DQM PI dly= 986
2532 11:33:01.877215 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2533 11:33:01.877608
2534 11:33:01.883685 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2535 11:33:01.884076
2536 11:33:01.887260 Byte1, DQ PI dly=977, DQM PI dly= 977
2537 11:33:01.890866 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2538 11:33:01.891260
2539 11:33:01.893872 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2540 11:33:01.897531
2541 11:33:01.897918 ==
2542 11:33:01.900330 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2543 11:33:01.903922 fsp= 1, odt_onoff= 1, Byte mode= 0
2544 11:33:01.904313 ==
2545 11:33:01.907282 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2546 11:33:01.907674
2547 11:33:01.910732 Begin, DQ Scan Range 953~1017
2548 11:33:01.913723 Write Rank0 MR14 =0x0
2549 11:33:01.922174
2550 11:33:01.922464 CH=1, VrefRange= 0, VrefLevel = 0
2551 11:33:01.928501 TX Bit0 (979~998) 20 988, Bit8 (969~985) 17 977,
2552 11:33:01.931933 TX Bit1 (978~996) 19 987, Bit9 (969~985) 17 977,
2553 11:33:01.939260 TX Bit2 (977~992) 16 984, Bit10 (970~985) 16 977,
2554 11:33:01.942267 TX Bit3 (976~990) 15 983, Bit11 (972~988) 17 980,
2555 11:33:01.945283 TX Bit4 (977~993) 17 985, Bit12 (970~988) 19 979,
2556 11:33:01.951941 TX Bit5 (978~997) 20 987, Bit13 (971~988) 18 979,
2557 11:33:01.955357 TX Bit6 (980~997) 18 988, Bit14 (970~986) 17 978,
2558 11:33:01.958399 TX Bit7 (978~992) 15 985, Bit15 (967~985) 19 976,
2559 11:33:01.958566
2560 11:33:01.962115 Write Rank0 MR14 =0x2
2561 11:33:01.971392
2562 11:33:01.971777 CH=1, VrefRange= 0, VrefLevel = 2
2563 11:33:01.978390 TX Bit0 (979~998) 20 988, Bit8 (969~985) 17 977,
2564 11:33:01.981543 TX Bit1 (978~997) 20 987, Bit9 (969~985) 17 977,
2565 11:33:01.988398 TX Bit2 (977~992) 16 984, Bit10 (970~986) 17 978,
2566 11:33:01.991761 TX Bit3 (975~990) 16 982, Bit11 (971~988) 18 979,
2567 11:33:01.994449 TX Bit4 (977~994) 18 985, Bit12 (970~989) 20 979,
2568 11:33:02.001257 TX Bit5 (978~998) 21 988, Bit13 (972~988) 17 980,
2569 11:33:02.004786 TX Bit6 (979~998) 20 988, Bit14 (970~986) 17 978,
2570 11:33:02.008155 TX Bit7 (977~992) 16 984, Bit15 (967~985) 19 976,
2571 11:33:02.008538
2572 11:33:02.010948 Write Rank0 MR14 =0x4
2573 11:33:02.020562
2574 11:33:02.020850 CH=1, VrefRange= 0, VrefLevel = 4
2575 11:33:02.027433 TX Bit0 (978~999) 22 988, Bit8 (968~986) 19 977,
2576 11:33:02.030267 TX Bit1 (977~997) 21 987, Bit9 (968~986) 19 977,
2577 11:33:02.037354 TX Bit2 (977~992) 16 984, Bit10 (969~986) 18 977,
2578 11:33:02.040188 TX Bit3 (975~991) 17 983, Bit11 (971~989) 19 980,
2579 11:33:02.043907 TX Bit4 (977~994) 18 985, Bit12 (970~989) 20 979,
2580 11:33:02.051027 TX Bit5 (978~998) 21 988, Bit13 (971~989) 19 980,
2581 11:33:02.053883 TX Bit6 (979~998) 20 988, Bit14 (970~987) 18 978,
2582 11:33:02.057520 TX Bit7 (977~993) 17 985, Bit15 (966~985) 20 975,
2583 11:33:02.057883
2584 11:33:02.060307 Write Rank0 MR14 =0x6
2585 11:33:02.069713
2586 11:33:02.070162 CH=1, VrefRange= 0, VrefLevel = 6
2587 11:33:02.076290 TX Bit0 (978~999) 22 988, Bit8 (968~986) 19 977,
2588 11:33:02.079508 TX Bit1 (977~997) 21 987, Bit9 (968~986) 19 977,
2589 11:33:02.086540 TX Bit2 (976~993) 18 984, Bit10 (969~987) 19 978,
2590 11:33:02.089714 TX Bit3 (975~991) 17 983, Bit11 (970~990) 21 980,
2591 11:33:02.093491 TX Bit4 (977~995) 19 986, Bit12 (970~990) 21 980,
2592 11:33:02.099768 TX Bit5 (978~998) 21 988, Bit13 (970~990) 21 980,
2593 11:33:02.102901 TX Bit6 (979~998) 20 988, Bit14 (970~988) 19 979,
2594 11:33:02.106493 TX Bit7 (977~994) 18 985, Bit15 (966~986) 21 976,
2595 11:33:02.106888
2596 11:33:02.109415 Write Rank0 MR14 =0x8
2597 11:33:02.118801
2598 11:33:02.119072 CH=1, VrefRange= 0, VrefLevel = 8
2599 11:33:02.125299 TX Bit0 (978~999) 22 988, Bit8 (968~987) 20 977,
2600 11:33:02.128793 TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977,
2601 11:33:02.135413 TX Bit2 (976~993) 18 984, Bit10 (969~988) 20 978,
2602 11:33:02.138681 TX Bit3 (974~991) 18 982, Bit11 (970~990) 21 980,
2603 11:33:02.142002 TX Bit4 (977~996) 20 986, Bit12 (969~990) 22 979,
2604 11:33:02.148671 TX Bit5 (978~999) 22 988, Bit13 (970~990) 21 980,
2605 11:33:02.151870 TX Bit6 (978~999) 22 988, Bit14 (970~988) 19 979,
2606 11:33:02.155350 TX Bit7 (977~994) 18 985, Bit15 (966~986) 21 976,
2607 11:33:02.155742
2608 11:33:02.158523 Write Rank0 MR14 =0xa
2609 11:33:02.168162
2610 11:33:02.171502 CH=1, VrefRange= 0, VrefLevel = 10
2611 11:33:02.174728 TX Bit0 (978~999) 22 988, Bit8 (968~988) 21 978,
2612 11:33:02.177983 TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977,
2613 11:33:02.184474 TX Bit2 (976~994) 19 985, Bit10 (969~988) 20 978,
2614 11:33:02.187920 TX Bit3 (974~992) 19 983, Bit11 (970~991) 22 980,
2615 11:33:02.191525 TX Bit4 (977~997) 21 987, Bit12 (969~991) 23 980,
2616 11:33:02.197881 TX Bit5 (978~999) 22 988, Bit13 (970~990) 21 980,
2617 11:33:02.201502 TX Bit6 (978~999) 22 988, Bit14 (969~989) 21 979,
2618 11:33:02.204463 TX Bit7 (976~995) 20 985, Bit15 (966~986) 21 976,
2619 11:33:02.208219
2620 11:33:02.208607 Write Rank0 MR14 =0xc
2621 11:33:02.217844
2622 11:33:02.220726 CH=1, VrefRange= 0, VrefLevel = 12
2623 11:33:02.224063 TX Bit0 (978~999) 22 988, Bit8 (968~989) 22 978,
2624 11:33:02.227269 TX Bit1 (977~998) 22 987, Bit9 (968~988) 21 978,
2625 11:33:02.233966 TX Bit2 (976~995) 20 985, Bit10 (969~989) 21 979,
2626 11:33:02.238225 TX Bit3 (974~993) 20 983, Bit11 (970~991) 22 980,
2627 11:33:02.241057 TX Bit4 (976~997) 22 986, Bit12 (969~991) 23 980,
2628 11:33:02.247899 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
2629 11:33:02.250795 TX Bit6 (979~999) 21 989, Bit14 (969~990) 22 979,
2630 11:33:02.254258 TX Bit7 (977~996) 20 986, Bit15 (966~987) 22 976,
2631 11:33:02.254648
2632 11:33:02.257280 Write Rank0 MR14 =0xe
2633 11:33:02.266709
2634 11:33:02.270269 CH=1, VrefRange= 0, VrefLevel = 14
2635 11:33:02.273751 TX Bit0 (978~1000) 23 989, Bit8 (967~989) 23 978,
2636 11:33:02.276837 TX Bit1 (976~999) 24 987, Bit9 (968~989) 22 978,
2637 11:33:02.283485 TX Bit2 (975~996) 22 985, Bit10 (968~989) 22 978,
2638 11:33:02.286761 TX Bit3 (973~993) 21 983, Bit11 (969~991) 23 980,
2639 11:33:02.290429 TX Bit4 (976~998) 23 987, Bit12 (969~991) 23 980,
2640 11:33:02.296885 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
2641 11:33:02.300238 TX Bit6 (978~1000) 23 989, Bit14 (969~990) 22 979,
2642 11:33:02.303817 TX Bit7 (976~996) 21 986, Bit15 (965~988) 24 976,
2643 11:33:02.304471
2644 11:33:02.306795 Write Rank0 MR14 =0x10
2645 11:33:02.316522
2646 11:33:02.319713 CH=1, VrefRange= 0, VrefLevel = 16
2647 11:33:02.323367 TX Bit0 (977~1000) 24 988, Bit8 (967~990) 24 978,
2648 11:33:02.326188 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
2649 11:33:02.333066 TX Bit2 (975~996) 22 985, Bit10 (969~990) 22 979,
2650 11:33:02.336517 TX Bit3 (972~994) 23 983, Bit11 (969~991) 23 980,
2651 11:33:02.339576 TX Bit4 (976~998) 23 987, Bit12 (969~991) 23 980,
2652 11:33:02.346963 TX Bit5 (977~1000) 24 988, Bit13 (969~991) 23 980,
2653 11:33:02.349605 TX Bit6 (978~1000) 23 989, Bit14 (968~991) 24 979,
2654 11:33:02.353097 TX Bit7 (976~997) 22 986, Bit15 (965~988) 24 976,
2655 11:33:02.356196
2656 11:33:02.356579 Write Rank0 MR14 =0x12
2657 11:33:02.366727
2658 11:33:02.369584 CH=1, VrefRange= 0, VrefLevel = 18
2659 11:33:02.373082 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978,
2660 11:33:02.376502 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
2661 11:33:02.383253 TX Bit2 (975~997) 23 986, Bit10 (968~991) 24 979,
2662 11:33:02.386570 TX Bit3 (972~994) 23 983, Bit11 (969~992) 24 980,
2663 11:33:02.389901 TX Bit4 (976~998) 23 987, Bit12 (968~992) 25 980,
2664 11:33:02.396834 TX Bit5 (977~1000) 24 988, Bit13 (969~991) 23 980,
2665 11:33:02.400170 TX Bit6 (978~1000) 23 989, Bit14 (969~991) 23 980,
2666 11:33:02.406425 TX Bit7 (976~997) 22 986, Bit15 (964~989) 26 976,
2667 11:33:02.406885
2668 11:33:02.407187 Write Rank0 MR14 =0x14
2669 11:33:02.416716
2670 11:33:02.419646 CH=1, VrefRange= 0, VrefLevel = 20
2671 11:33:02.423429 TX Bit0 (977~1001) 25 989, Bit8 (967~991) 25 979,
2672 11:33:02.426631 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
2673 11:33:02.432945 TX Bit2 (974~997) 24 985, Bit10 (967~991) 25 979,
2674 11:33:02.436471 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2675 11:33:02.439519 TX Bit4 (976~999) 24 987, Bit12 (968~992) 25 980,
2676 11:33:02.446427 TX Bit5 (977~1000) 24 988, Bit13 (969~991) 23 980,
2677 11:33:02.449592 TX Bit6 (978~1001) 24 989, Bit14 (968~991) 24 979,
2678 11:33:02.456350 TX Bit7 (976~998) 23 987, Bit15 (964~989) 26 976,
2679 11:33:02.456738
2680 11:33:02.457084 Write Rank0 MR14 =0x16
2681 11:33:02.466376
2682 11:33:02.469435 CH=1, VrefRange= 0, VrefLevel = 22
2683 11:33:02.473000 TX Bit0 (977~1001) 25 989, Bit8 (967~991) 25 979,
2684 11:33:02.476159 TX Bit1 (976~999) 24 987, Bit9 (966~991) 26 978,
2685 11:33:02.483374 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
2686 11:33:02.486651 TX Bit3 (971~996) 26 983, Bit11 (969~992) 24 980,
2687 11:33:02.489782 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2688 11:33:02.496236 TX Bit5 (977~1001) 25 989, Bit13 (969~991) 23 980,
2689 11:33:02.499585 TX Bit6 (977~1001) 25 989, Bit14 (968~991) 24 979,
2690 11:33:02.503098 TX Bit7 (975~998) 24 986, Bit15 (964~988) 25 976,
2691 11:33:02.506597
2692 11:33:02.506981 Write Rank0 MR14 =0x18
2693 11:33:02.516335
2694 11:33:02.520052 CH=1, VrefRange= 0, VrefLevel = 24
2695 11:33:02.523608 TX Bit0 (977~1002) 26 989, Bit8 (967~991) 25 979,
2696 11:33:02.526405 TX Bit1 (976~1000) 25 988, Bit9 (966~990) 25 978,
2697 11:33:02.532946 TX Bit2 (974~997) 24 985, Bit10 (968~991) 24 979,
2698 11:33:02.536358 TX Bit3 (971~996) 26 983, Bit11 (968~992) 25 980,
2699 11:33:02.539895 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2700 11:33:02.546496 TX Bit5 (976~1001) 26 988, Bit13 (969~991) 23 980,
2701 11:33:02.549633 TX Bit6 (977~1002) 26 989, Bit14 (967~991) 25 979,
2702 11:33:02.556456 TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975,
2703 11:33:02.556871
2704 11:33:02.557213 Write Rank0 MR14 =0x1a
2705 11:33:02.566758
2706 11:33:02.570135 CH=1, VrefRange= 0, VrefLevel = 26
2707 11:33:02.573353 TX Bit0 (977~1002) 26 989, Bit8 (967~991) 25 979,
2708 11:33:02.576256 TX Bit1 (976~1000) 25 988, Bit9 (966~990) 25 978,
2709 11:33:02.583296 TX Bit2 (974~997) 24 985, Bit10 (968~991) 24 979,
2710 11:33:02.586562 TX Bit3 (971~996) 26 983, Bit11 (968~992) 25 980,
2711 11:33:02.589637 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2712 11:33:02.596888 TX Bit5 (976~1001) 26 988, Bit13 (969~991) 23 980,
2713 11:33:02.599472 TX Bit6 (977~1002) 26 989, Bit14 (967~991) 25 979,
2714 11:33:02.606613 TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975,
2715 11:33:02.607285
2716 11:33:02.607630 Write Rank0 MR14 =0x1c
2717 11:33:02.616640
2718 11:33:02.620691 CH=1, VrefRange= 0, VrefLevel = 28
2719 11:33:02.623403 TX Bit0 (977~1002) 26 989, Bit8 (967~991) 25 979,
2720 11:33:02.626587 TX Bit1 (976~1000) 25 988, Bit9 (966~990) 25 978,
2721 11:33:02.633567 TX Bit2 (974~997) 24 985, Bit10 (968~991) 24 979,
2722 11:33:02.636920 TX Bit3 (971~996) 26 983, Bit11 (968~992) 25 980,
2723 11:33:02.639859 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2724 11:33:02.646659 TX Bit5 (976~1001) 26 988, Bit13 (969~991) 23 980,
2725 11:33:02.650171 TX Bit6 (977~1002) 26 989, Bit14 (967~991) 25 979,
2726 11:33:02.656957 TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975,
2727 11:33:02.657472
2728 11:33:02.657776 Write Rank0 MR14 =0x1e
2729 11:33:02.666612
2730 11:33:02.670057 CH=1, VrefRange= 0, VrefLevel = 30
2731 11:33:02.673360 TX Bit0 (977~1002) 26 989, Bit8 (967~991) 25 979,
2732 11:33:02.676561 TX Bit1 (976~1000) 25 988, Bit9 (966~990) 25 978,
2733 11:33:02.683114 TX Bit2 (974~997) 24 985, Bit10 (968~991) 24 979,
2734 11:33:02.686766 TX Bit3 (971~996) 26 983, Bit11 (968~992) 25 980,
2735 11:33:02.689806 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2736 11:33:02.696461 TX Bit5 (976~1001) 26 988, Bit13 (969~991) 23 980,
2737 11:33:02.699992 TX Bit6 (977~1002) 26 989, Bit14 (967~991) 25 979,
2738 11:33:02.706484 TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975,
2739 11:33:02.706875
2740 11:33:02.707199 Write Rank0 MR14 =0x20
2741 11:33:02.716798
2742 11:33:02.719873 CH=1, VrefRange= 0, VrefLevel = 32
2743 11:33:02.723594 TX Bit0 (977~1002) 26 989, Bit8 (967~991) 25 979,
2744 11:33:02.726375 TX Bit1 (976~1000) 25 988, Bit9 (966~990) 25 978,
2745 11:33:02.733415 TX Bit2 (974~997) 24 985, Bit10 (968~991) 24 979,
2746 11:33:02.736923 TX Bit3 (971~996) 26 983, Bit11 (968~992) 25 980,
2747 11:33:02.740008 TX Bit4 (975~999) 25 987, Bit12 (968~992) 25 980,
2748 11:33:02.746626 TX Bit5 (976~1001) 26 988, Bit13 (969~991) 23 980,
2749 11:33:02.750165 TX Bit6 (977~1002) 26 989, Bit14 (967~991) 25 979,
2750 11:33:02.756797 TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975,
2751 11:33:02.757173
2752 11:33:02.757414
2753 11:33:02.760059 TX Vref found, early break! 371< 379
2754 11:33:02.763343 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
2755 11:33:02.766910 u1DelayCellOfst[0]=7 cells (6 PI)
2756 11:33:02.770569 u1DelayCellOfst[1]=6 cells (5 PI)
2757 11:33:02.773399 u1DelayCellOfst[2]=2 cells (2 PI)
2758 11:33:02.776954 u1DelayCellOfst[3]=0 cells (0 PI)
2759 11:33:02.780350 u1DelayCellOfst[4]=5 cells (4 PI)
2760 11:33:02.780733 u1DelayCellOfst[5]=6 cells (5 PI)
2761 11:33:02.783831 u1DelayCellOfst[6]=7 cells (6 PI)
2762 11:33:02.787060 u1DelayCellOfst[7]=3 cells (3 PI)
2763 11:33:02.790268 Byte0, DQ PI dly=983, DQM PI dly= 986
2764 11:33:02.796852 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
2765 11:33:02.797375
2766 11:33:02.799876 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
2767 11:33:02.800391
2768 11:33:02.803533 u1DelayCellOfst[8]=5 cells (4 PI)
2769 11:33:02.806723 u1DelayCellOfst[9]=3 cells (3 PI)
2770 11:33:02.810478 u1DelayCellOfst[10]=5 cells (4 PI)
2771 11:33:02.813267 u1DelayCellOfst[11]=6 cells (5 PI)
2772 11:33:02.816924 u1DelayCellOfst[12]=6 cells (5 PI)
2773 11:33:02.817344 u1DelayCellOfst[13]=6 cells (5 PI)
2774 11:33:02.820241 u1DelayCellOfst[14]=5 cells (4 PI)
2775 11:33:02.823448 u1DelayCellOfst[15]=0 cells (0 PI)
2776 11:33:02.826595 Byte1, DQ PI dly=975, DQM PI dly= 977
2777 11:33:02.833725 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
2778 11:33:02.834133
2779 11:33:02.836646 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
2780 11:33:02.837037
2781 11:33:02.840381 Write Rank0 MR14 =0x18
2782 11:33:02.840764
2783 11:33:02.841064 Final TX Range 0 Vref 24
2784 11:33:02.841374
2785 11:33:02.846820 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2786 11:33:02.847213
2787 11:33:02.853429 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2788 11:33:02.860047 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2789 11:33:02.870288 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2790 11:33:02.870701 Write Rank0 MR3 =0xb0
2791 11:33:02.873478 DramC Write-DBI on
2792 11:33:02.873891 ==
2793 11:33:02.876784 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2794 11:33:02.880631 fsp= 1, odt_onoff= 1, Byte mode= 0
2795 11:33:02.881104 ==
2796 11:33:02.887097 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2797 11:33:02.887505
2798 11:33:02.887807 Begin, DQ Scan Range 697~761
2799 11:33:02.888086
2800 11:33:02.888347
2801 11:33:02.889833 TX Vref Scan disable
2802 11:33:02.893453 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2803 11:33:02.896867 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2804 11:33:02.900226 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2805 11:33:02.903478 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2806 11:33:02.906998 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2807 11:33:02.910186 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2808 11:33:02.916816 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2809 11:33:02.920057 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2810 11:33:02.923278 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2811 11:33:02.926612 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2812 11:33:02.930345 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
2813 11:33:02.933334 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
2814 11:33:02.936781 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
2815 11:33:02.940472 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2816 11:33:02.944362 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2817 11:33:02.947009 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2818 11:33:02.949963 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2819 11:33:02.953562 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2820 11:33:02.956840 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2821 11:33:02.959996 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2822 11:33:02.963541 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2823 11:33:02.971814 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2824 11:33:02.974825 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2825 11:33:02.978013 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2826 11:33:02.981431 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2827 11:33:02.984813 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2828 11:33:02.988612 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2829 11:33:02.991553 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2830 11:33:02.994614 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2831 11:33:02.997971 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2832 11:33:03.001563 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
2833 11:33:03.004508 Byte0, DQ PI dly=731, DQM PI dly= 731
2834 11:33:03.008278 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
2835 11:33:03.008445
2836 11:33:03.014474 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
2837 11:33:03.014642
2838 11:33:03.018015 Byte1, DQ PI dly=721, DQM PI dly= 721
2839 11:33:03.021175 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
2840 11:33:03.021343
2841 11:33:03.024452 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
2842 11:33:03.024618
2843 11:33:03.031712 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2844 11:33:03.041868 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2845 11:33:03.048308 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2846 11:33:03.048701 Write Rank0 MR3 =0x30
2847 11:33:03.051633 DramC Write-DBI off
2848 11:33:03.052174
2849 11:33:03.052604 [DATLAT]
2850 11:33:03.054654 Freq=1600, CH1 RK0, use_rxtx_scan=0
2851 11:33:03.055035
2852 11:33:03.058143 DATLAT Default: 0xf
2853 11:33:03.058525 7, 0xFFFF, sum=0
2854 11:33:03.061719 8, 0xFFFF, sum=0
2855 11:33:03.062107 9, 0xFFFF, sum=0
2856 11:33:03.064534 10, 0xFFFF, sum=0
2857 11:33:03.064921 11, 0xFFFF, sum=0
2858 11:33:03.068167 12, 0xFFFF, sum=0
2859 11:33:03.068554 13, 0xFFFF, sum=0
2860 11:33:03.068857 14, 0x0, sum=1
2861 11:33:03.071522 15, 0x0, sum=2
2862 11:33:03.071910 16, 0x0, sum=3
2863 11:33:03.074772 17, 0x0, sum=4
2864 11:33:03.078154 pattern=2 first_step=14 total pass=5 best_step=16
2865 11:33:03.078427 ==
2866 11:33:03.084521 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2867 11:33:03.087873 fsp= 1, odt_onoff= 1, Byte mode= 0
2868 11:33:03.088038 ==
2869 11:33:03.090987 Start DQ dly to find pass range UseTestEngine =1
2870 11:33:03.094599 x-axis: bit #, y-axis: DQ dly (-127~63)
2871 11:33:03.094764 RX Vref Scan = 1
2872 11:33:03.210970
2873 11:33:03.211503 RX Vref found, early break!
2874 11:33:03.211950
2875 11:33:03.214266 Final RX Vref 13, apply to both rank0 and 1
2876 11:33:03.217948 ==
2877 11:33:03.221464 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2878 11:33:03.224784 fsp= 1, odt_onoff= 1, Byte mode= 0
2879 11:33:03.225200 ==
2880 11:33:03.225511 DQS Delay:
2881 11:33:03.228062 DQS0 = 0, DQS1 = 0
2882 11:33:03.228449 DQM Delay:
2883 11:33:03.231117 DQM0 = 20, DQM1 = 18
2884 11:33:03.231503 DQ Delay:
2885 11:33:03.234369 DQ0 =24, DQ1 =22, DQ2 =16, DQ3 =15
2886 11:33:03.238011 DQ4 =18, DQ5 =24, DQ6 =25, DQ7 =19
2887 11:33:03.241109 DQ8 =19, DQ9 =19, DQ10 =18, DQ11 =19
2888 11:33:03.244370 DQ12 =20, DQ13 =19, DQ14 =18, DQ15 =17
2889 11:33:03.244758
2890 11:33:03.245085
2891 11:33:03.245435
2892 11:33:03.247699 [DramC_TX_OE_Calibration] TA2
2893 11:33:03.251256 Original DQ_B0 (3 6) =30, OEN = 27
2894 11:33:03.254242 Original DQ_B1 (3 6) =30, OEN = 27
2895 11:33:03.258143 23, 0x0, End_B0=23 End_B1=23
2896 11:33:03.258535 24, 0x0, End_B0=24 End_B1=24
2897 11:33:03.261277 25, 0x0, End_B0=25 End_B1=25
2898 11:33:03.264520 26, 0x0, End_B0=26 End_B1=26
2899 11:33:03.267902 27, 0x0, End_B0=27 End_B1=27
2900 11:33:03.268343 28, 0x0, End_B0=28 End_B1=28
2901 11:33:03.271295 29, 0x0, End_B0=29 End_B1=29
2902 11:33:03.274477 30, 0x0, End_B0=30 End_B1=30
2903 11:33:03.277668 31, 0xFFFF, End_B0=30 End_B1=30
2904 11:33:03.281111 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2905 11:33:03.287979 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2906 11:33:03.288371
2907 11:33:03.288669
2908 11:33:03.292405 Write Rank0 MR23 =0x3f
2909 11:33:03.292678 [DQSOSC]
2910 11:33:03.298189 [DQSOSCAuto] RK0, (LSB)MR18= 0xbd, (MSB)MR19= 0x3, tDQSOscB0 = 329 ps tDQSOscB1 = 0 ps
2911 11:33:03.304029 CH1_RK0: MR19=0x3, MR18=0xBD, DQSOSC=329, MR23=63, INC=22, DEC=34
2912 11:33:03.307816 Write Rank0 MR23 =0x3f
2913 11:33:03.308047 [DQSOSC]
2914 11:33:03.314479 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe, (MSB)MR19= 0x3, tDQSOscB0 = 328 ps tDQSOscB1 = 0 ps
2915 11:33:03.317963 CH1 RK0: MR19=3, MR18=BE
2916 11:33:03.320940 [RankSwap] Rank num 2, (Multi 1), Rank 1
2917 11:33:03.324375 Write Rank0 MR2 =0xad
2918 11:33:03.324580 [Write Leveling]
2919 11:33:03.327787 delay byte0 byte1 byte2 byte3
2920 11:33:03.328002
2921 11:33:03.331368 10 0 0
2922 11:33:03.331633 11 0 0
2923 11:33:03.331795 12 0 0
2924 11:33:03.334363 13 0 0
2925 11:33:03.334562 14 0 0
2926 11:33:03.337504 15 0 0
2927 11:33:03.337742 16 0 0
2928 11:33:03.337925 17 0 0
2929 11:33:03.341276 18 0 0
2930 11:33:03.341577 19 0 0
2931 11:33:03.343968 20 0 0
2932 11:33:03.344270 21 0 0
2933 11:33:03.347629 22 0 0
2934 11:33:03.348145 23 0 0
2935 11:33:03.348567 24 0 0
2936 11:33:03.350648 25 0 0
2937 11:33:03.351045 26 0 0
2938 11:33:03.353878 27 0 0
2939 11:33:03.354272 28 0 0
2940 11:33:03.354577 29 0 0
2941 11:33:03.357241 30 0 0
2942 11:33:03.357667 31 0 0
2943 11:33:03.360770 32 0 ff
2944 11:33:03.361216 33 0 ff
2945 11:33:03.363991 34 ff ff
2946 11:33:03.364383 35 ff ff
2947 11:33:03.367413 36 ff ff
2948 11:33:03.367820 37 ff ff
2949 11:33:03.370746 38 ff ff
2950 11:33:03.371138 39 ff ff
2951 11:33:03.371463 40 ff ff
2952 11:33:03.377065 pass bytecount = 0xff (0xff: all bytes pass)
2953 11:33:03.377489
2954 11:33:03.377787 DQS0 dly: 34
2955 11:33:03.378057 DQS1 dly: 32
2956 11:33:03.380636 Write Rank0 MR2 =0x2d
2957 11:33:03.384017 [RankSwap] Rank num 2, (Multi 1), Rank 0
2958 11:33:03.387707 Write Rank1 MR1 =0xd6
2959 11:33:03.388086 [Gating]
2960 11:33:03.388379 ==
2961 11:33:03.394180 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2962 11:33:03.394580 fsp= 1, odt_onoff= 1, Byte mode= 0
2963 11:33:03.397187 ==
2964 11:33:03.400683 3 1 0 |1212 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2965 11:33:03.403955 3 1 4 |1919 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2966 11:33:03.407555 3 1 8 |3131 3534 |(0 0)(11 11) |(0 1)(0 1)| 0
2967 11:33:03.414262 3 1 12 |1e1e 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2968 11:33:03.417214 3 1 16 |2f2e 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2969 11:33:03.420911 3 1 20 |2f2f 3534 |(0 0)(11 11) |(0 1)(0 1)| 0
2970 11:33:03.427329 3 1 24 |3231 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2971 11:33:03.431004 3 1 28 |909 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2972 11:33:03.434107 3 2 0 |2221 504 |(11 11)(11 11) |(1 1)(1 1)| 0
2973 11:33:03.440769 3 2 4 |3a39 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2974 11:33:03.444325 3 2 8 |2626 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2975 11:33:03.447130 3 2 12 |2221 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2976 11:33:03.450714 3 2 16 |3938 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2977 11:33:03.457692 3 2 20 |2928 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2978 11:33:03.460692 3 2 24 |1111 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2979 11:33:03.463908 3 2 28 |909 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2980 11:33:03.470533 3 3 0 |2322 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2981 11:33:03.473873 [Byte 0] Lead/lag falling Transition (3, 3, 0)
2982 11:33:03.479300 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 1)(1 1)| 0
2983 11:33:03.480817 3 3 8 |3534 3231 |(11 11)(11 11) |(0 1)(1 1)| 0
2984 11:33:03.487546 [Byte 1] Lead/lag falling Transition (3, 3, 8)
2985 11:33:03.490594 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2986 11:33:03.494016 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2987 11:33:03.501415 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2988 11:33:03.504067 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2989 11:33:03.507541 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2990 11:33:03.513977 3 4 0 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
2991 11:33:03.517659 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2992 11:33:03.520887 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2993 11:33:03.524176 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2994 11:33:03.530729 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2995 11:33:03.533896 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2996 11:33:03.537482 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2997 11:33:03.543780 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2998 11:33:03.547267 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2999 11:33:03.550696 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3000 11:33:03.557674 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3001 11:33:03.560756 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3002 11:33:03.563952 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3003 11:33:03.570527 [Byte 0] Lead/lag falling Transition (3, 5, 16)
3004 11:33:03.573649 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3005 11:33:03.577121 [Byte 0] Lead/lag Transition tap number (2)
3006 11:33:03.580471 3 5 24 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3007 11:33:03.587417 [Byte 1] Lead/lag falling Transition (3, 5, 24)
3008 11:33:03.590521 3 5 28 |403 3e3d |(11 11)(11 11) |(0 0)(1 0)| 0
3009 11:33:03.593798 [Byte 1] Lead/lag Transition tap number (2)
3010 11:33:03.597479 3 6 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3011 11:33:03.600498 [Byte 0]First pass (3, 6, 0)
3012 11:33:03.603936 3 6 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3013 11:33:03.607772 [Byte 1]First pass (3, 6, 4)
3014 11:33:03.610862 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3015 11:33:03.614416 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3016 11:33:03.621262 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3017 11:33:03.624392 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3018 11:33:03.627811 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3019 11:33:03.630700 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3020 11:33:03.633938 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3021 11:33:03.640541 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3022 11:33:03.644035 All bytes gating window > 1UI, Early break!
3023 11:33:03.644482
3024 11:33:03.647285 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
3025 11:33:03.647679
3026 11:33:03.650895 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
3027 11:33:03.651314
3028 11:33:03.651620
3029 11:33:03.651979
3030 11:33:03.654149 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
3031 11:33:03.654569
3032 11:33:03.660892 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
3033 11:33:03.661346
3034 11:33:03.661710
3035 11:33:03.662005 Write Rank1 MR1 =0x56
3036 11:33:03.662280
3037 11:33:03.663836 best RODT dly(2T, 0.5T) = (2, 2)
3038 11:33:03.664302
3039 11:33:03.667077 best RODT dly(2T, 0.5T) = (2, 2)
3040 11:33:03.667478 ==
3041 11:33:03.674296 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3042 11:33:03.677207 fsp= 1, odt_onoff= 1, Byte mode= 0
3043 11:33:03.677639 ==
3044 11:33:03.680773 Start DQ dly to find pass range UseTestEngine =0
3045 11:33:03.683759 x-axis: bit #, y-axis: DQ dly (-127~63)
3046 11:33:03.687384 RX Vref Scan = 0
3047 11:33:03.687857 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3048 11:33:03.690983 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3049 11:33:03.694252 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3050 11:33:03.697283 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3051 11:33:03.700505 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3052 11:33:03.703853 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3053 11:33:03.707350 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3054 11:33:03.710895 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3055 11:33:03.714021 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3056 11:33:03.714549 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3057 11:33:03.717174 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3058 11:33:03.720303 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3059 11:33:03.723618 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3060 11:33:03.727170 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3061 11:33:03.730418 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3062 11:33:03.733560 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3063 11:33:03.736991 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3064 11:33:03.737469 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3065 11:33:03.740308 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3066 11:33:03.743640 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3067 11:33:03.747284 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3068 11:33:03.750349 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3069 11:33:03.753967 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3070 11:33:03.757267 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3071 11:33:03.757688 -2, [0] xxxoxxxx xxxxxxxx [MSB]
3072 11:33:03.760436 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3073 11:33:03.763921 0, [0] xxooxxxx xxxxxxxo [MSB]
3074 11:33:03.766933 1, [0] xxoooxxo xxxxxxxo [MSB]
3075 11:33:03.770333 2, [0] xxoooxxo oooxxxoo [MSB]
3076 11:33:03.773453 3, [0] xxoooxxo ooooxooo [MSB]
3077 11:33:03.773906 4, [0] xxoooxxo ooooxooo [MSB]
3078 11:33:03.776981 5, [0] xoooooxo oooooooo [MSB]
3079 11:33:03.780581 6, [0] xooooooo oooooooo [MSB]
3080 11:33:03.783935 34, [0] oooxoooo oooooooo [MSB]
3081 11:33:03.786806 35, [0] ooxxoooo ooooooox [MSB]
3082 11:33:03.790176 36, [0] ooxxoooo ooooooox [MSB]
3083 11:33:03.793841 37, [0] ooxxxooo ooxoooox [MSB]
3084 11:33:03.794230 38, [0] ooxxxooo xoxooxox [MSB]
3085 11:33:03.797073 39, [0] ooxxxoox xxxxoxxx [MSB]
3086 11:33:03.800266 40, [0] ooxxxoox xxxxoxxx [MSB]
3087 11:33:03.803781 41, [0] ooxxxoox xxxxxxxx [MSB]
3088 11:33:03.807061 42, [0] xxxxxxxx xxxxxxxx [MSB]
3089 11:33:03.810557 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
3090 11:33:03.813620 iDelay=42, Bit 1, Center 23 (5 ~ 41) 37
3091 11:33:03.817093 iDelay=42, Bit 2, Center 17 (0 ~ 34) 35
3092 11:33:03.820308 iDelay=42, Bit 3, Center 15 (-2 ~ 33) 36
3093 11:33:03.823948 iDelay=42, Bit 4, Center 18 (1 ~ 36) 36
3094 11:33:03.827189 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
3095 11:33:03.830454 iDelay=42, Bit 6, Center 23 (6 ~ 41) 36
3096 11:33:03.833888 iDelay=42, Bit 7, Center 19 (1 ~ 38) 38
3097 11:33:03.837166 iDelay=42, Bit 8, Center 19 (2 ~ 37) 36
3098 11:33:03.840432 iDelay=42, Bit 9, Center 20 (2 ~ 38) 37
3099 11:33:03.847194 iDelay=42, Bit 10, Center 19 (2 ~ 36) 35
3100 11:33:03.850694 iDelay=42, Bit 11, Center 20 (3 ~ 38) 36
3101 11:33:03.853661 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
3102 11:33:03.856814 iDelay=42, Bit 13, Center 20 (3 ~ 37) 35
3103 11:33:03.860094 iDelay=42, Bit 14, Center 20 (2 ~ 38) 37
3104 11:33:03.863732 iDelay=42, Bit 15, Center 16 (-1 ~ 34) 36
3105 11:33:03.864141 ==
3106 11:33:03.870543 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3107 11:33:03.870948 fsp= 1, odt_onoff= 1, Byte mode= 0
3108 11:33:03.873469 ==
3109 11:33:03.873994 DQS Delay:
3110 11:33:03.874351 DQS0 = 0, DQS1 = 0
3111 11:33:03.876953 DQM Delay:
3112 11:33:03.877430 DQM0 = 20, DQM1 = 19
3113 11:33:03.880032 DQ Delay:
3114 11:33:03.883619 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =15
3115 11:33:03.884148 DQ4 =18, DQ5 =23, DQ6 =23, DQ7 =19
3116 11:33:03.886716 DQ8 =19, DQ9 =20, DQ10 =19, DQ11 =20
3117 11:33:03.890477 DQ12 =22, DQ13 =20, DQ14 =20, DQ15 =16
3118 11:33:03.893263
3119 11:33:03.893736
3120 11:33:03.894169 DramC Write-DBI off
3121 11:33:03.894466 ==
3122 11:33:03.899912 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3123 11:33:03.903768 fsp= 1, odt_onoff= 1, Byte mode= 0
3124 11:33:03.904137 ==
3125 11:33:03.906988 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3126 11:33:03.907508
3127 11:33:03.910348 Begin, DQ Scan Range 928~1184
3128 11:33:03.910718
3129 11:33:03.911009
3130 11:33:03.913257 TX Vref Scan disable
3131 11:33:03.916523 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3132 11:33:03.919910 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3133 11:33:03.923762 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3134 11:33:03.926798 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3135 11:33:03.930249 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3136 11:33:03.933295 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3137 11:33:03.936823 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3138 11:33:03.939911 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3139 11:33:03.943808 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3140 11:33:03.947414 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3141 11:33:03.949924 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3142 11:33:03.953214 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3143 11:33:03.956507 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3144 11:33:03.960247 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3145 11:33:03.966693 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3146 11:33:03.970113 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3147 11:33:03.973344 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3148 11:33:03.976372 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3149 11:33:03.980121 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3150 11:33:03.983535 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3151 11:33:03.986558 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3152 11:33:03.990105 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3153 11:33:03.993241 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3154 11:33:03.997018 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3155 11:33:04.000048 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3156 11:33:04.003444 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3157 11:33:04.006430 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3158 11:33:04.009917 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3159 11:33:04.013324 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3160 11:33:04.016441 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3161 11:33:04.019632 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3162 11:33:04.026547 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3163 11:33:04.029763 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3164 11:33:04.033114 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3165 11:33:04.036301 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3166 11:33:04.039859 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3167 11:33:04.043350 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3168 11:33:04.047141 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3169 11:33:04.050071 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3170 11:33:04.053623 967 |3 6 7|[0] xxxxxxxx xxxxxxxo [MSB]
3171 11:33:04.056423 968 |3 6 8|[0] xxxxxxxx xoxxxxxo [MSB]
3172 11:33:04.059709 969 |3 6 9|[0] xxxxxxxx oooxxxxo [MSB]
3173 11:33:04.063391 970 |3 6 10|[0] xxxxxxxx oooooxoo [MSB]
3174 11:33:04.067195 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3175 11:33:04.069992 972 |3 6 12|[0] xxxoxxxx oooooooo [MSB]
3176 11:33:04.073386 973 |3 6 13|[0] xxooxxxx oooooooo [MSB]
3177 11:33:04.076670 974 |3 6 14|[0] xxoooxxx oooooooo [MSB]
3178 11:33:04.079999 975 |3 6 15|[0] xxoooxxo oooooooo [MSB]
3179 11:33:04.083666 976 |3 6 16|[0] xooooooo oooooooo [MSB]
3180 11:33:04.091508 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3181 11:33:04.094896 990 |3 6 30|[0] oooooooo ooooooox [MSB]
3182 11:33:04.097684 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3183 11:33:04.101309 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3184 11:33:04.104442 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3185 11:33:04.107966 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
3186 11:33:04.111085 995 |3 6 35|[0] ooxxoooo xxxxxxxx [MSB]
3187 11:33:04.114530 996 |3 6 36|[0] ooxxooox xxxxxxxx [MSB]
3188 11:33:04.117603 997 |3 6 37|[0] ooxxxoox xxxxxxxx [MSB]
3189 11:33:04.121028 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
3190 11:33:04.124287 Byte0, DQ PI dly=984, DQM PI dly= 984
3191 11:33:04.127761 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
3192 11:33:04.130816
3193 11:33:04.134274 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
3194 11:33:04.134553
3195 11:33:04.137336 Byte1, DQ PI dly=978, DQM PI dly= 978
3196 11:33:04.140644 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
3197 11:33:04.141047
3198 11:33:04.147473 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
3199 11:33:04.147752
3200 11:33:04.147964 ==
3201 11:33:04.151082 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3202 11:33:04.154417 fsp= 1, odt_onoff= 1, Byte mode= 0
3203 11:33:04.154690 ==
3204 11:33:04.158115 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3205 11:33:04.158621
3206 11:33:04.160863 Begin, DQ Scan Range 954~1018
3207 11:33:04.164362 Write Rank1 MR14 =0x0
3208 11:33:04.172485
3209 11:33:04.172872 CH=1, VrefRange= 0, VrefLevel = 0
3210 11:33:04.179145 TX Bit0 (978~997) 20 987, Bit8 (971~986) 16 978,
3211 11:33:04.183130 TX Bit1 (978~994) 17 986, Bit9 (970~986) 17 978,
3212 11:33:04.189575 TX Bit2 (975~991) 17 983, Bit10 (972~986) 15 979,
3213 11:33:04.192162 TX Bit3 (974~990) 17 982, Bit11 (974~991) 18 982,
3214 11:33:04.195754 TX Bit4 (976~992) 17 984, Bit12 (972~988) 17 980,
3215 11:33:04.202350 TX Bit5 (977~995) 19 986, Bit13 (975~986) 12 980,
3216 11:33:04.205893 TX Bit6 (978~997) 20 987, Bit14 (971~988) 18 979,
3217 11:33:04.209247 TX Bit7 (977~991) 15 984, Bit15 (968~985) 18 976,
3218 11:33:04.209651
3219 11:33:04.212456 Write Rank1 MR14 =0x2
3220 11:33:04.221797
3221 11:33:04.222196 CH=1, VrefRange= 0, VrefLevel = 2
3222 11:33:04.228309 TX Bit0 (978~998) 21 988, Bit8 (971~987) 17 979,
3223 11:33:04.231894 TX Bit1 (978~994) 17 986, Bit9 (970~987) 18 978,
3224 11:33:04.238269 TX Bit2 (975~991) 17 983, Bit10 (972~987) 16 979,
3225 11:33:04.241891 TX Bit3 (974~991) 18 982, Bit11 (973~991) 19 982,
3226 11:33:04.244785 TX Bit4 (976~992) 17 984, Bit12 (972~988) 17 980,
3227 11:33:04.251684 TX Bit5 (977~996) 20 986, Bit13 (974~987) 14 980,
3228 11:33:04.255101 TX Bit6 (977~997) 21 987, Bit14 (972~988) 17 980,
3229 11:33:04.258265 TX Bit7 (977~991) 15 984, Bit15 (968~985) 18 976,
3230 11:33:04.258761
3231 11:33:04.261478 Write Rank1 MR14 =0x4
3232 11:33:04.270544
3233 11:33:04.271127 CH=1, VrefRange= 0, VrefLevel = 4
3234 11:33:04.277014 TX Bit0 (978~998) 21 988, Bit8 (970~987) 18 978,
3235 11:33:04.280430 TX Bit1 (977~995) 19 986, Bit9 (970~986) 17 978,
3236 11:33:04.287038 TX Bit2 (974~991) 18 982, Bit10 (971~987) 17 979,
3237 11:33:04.290285 TX Bit3 (973~991) 19 982, Bit11 (973~991) 19 982,
3238 11:33:04.293592 TX Bit4 (976~992) 17 984, Bit12 (972~989) 18 980,
3239 11:33:04.300270 TX Bit5 (977~997) 21 987, Bit13 (974~987) 14 980,
3240 11:33:04.303665 TX Bit6 (978~997) 20 987, Bit14 (972~989) 18 980,
3241 11:33:04.307220 TX Bit7 (977~992) 16 984, Bit15 (968~985) 18 976,
3242 11:33:04.307611
3243 11:33:04.310520 Write Rank1 MR14 =0x6
3244 11:33:04.319310
3245 11:33:04.319769 CH=1, VrefRange= 0, VrefLevel = 6
3246 11:33:04.326462 TX Bit0 (977~998) 22 987, Bit8 (970~988) 19 979,
3247 11:33:04.329338 TX Bit1 (977~996) 20 986, Bit9 (970~987) 18 978,
3248 11:33:04.335981 TX Bit2 (974~992) 19 983, Bit10 (970~988) 19 979,
3249 11:33:04.339744 TX Bit3 (972~991) 20 981, Bit11 (973~991) 19 982,
3250 11:33:04.343040 TX Bit4 (975~993) 19 984, Bit12 (971~990) 20 980,
3251 11:33:04.349429 TX Bit5 (977~997) 21 987, Bit13 (973~988) 16 980,
3252 11:33:04.352806 TX Bit6 (978~998) 21 988, Bit14 (972~990) 19 981,
3253 11:33:04.356617 TX Bit7 (976~992) 17 984, Bit15 (968~986) 19 977,
3254 11:33:04.357006
3255 11:33:04.359557 Write Rank1 MR14 =0x8
3256 11:33:04.368374
3257 11:33:04.368584 CH=1, VrefRange= 0, VrefLevel = 8
3258 11:33:04.375340 TX Bit0 (977~999) 23 988, Bit8 (970~989) 20 979,
3259 11:33:04.378217 TX Bit1 (977~997) 21 987, Bit9 (969~988) 20 978,
3260 11:33:04.385179 TX Bit2 (974~992) 19 983, Bit10 (970~988) 19 979,
3261 11:33:04.388455 TX Bit3 (972~991) 20 981, Bit11 (973~992) 20 982,
3262 11:33:04.391445 TX Bit4 (975~993) 19 984, Bit12 (971~990) 20 980,
3263 11:33:04.398629 TX Bit5 (977~997) 21 987, Bit13 (972~990) 19 981,
3264 11:33:04.402119 TX Bit6 (977~998) 22 987, Bit14 (971~990) 20 980,
3265 11:33:04.405155 TX Bit7 (976~993) 18 984, Bit15 (967~986) 20 976,
3266 11:33:04.405415
3267 11:33:04.408402 Write Rank1 MR14 =0xa
3268 11:33:04.417670
3269 11:33:04.421237 CH=1, VrefRange= 0, VrefLevel = 10
3270 11:33:04.424737 TX Bit0 (977~999) 23 988, Bit8 (970~990) 21 980,
3271 11:33:04.427455 TX Bit1 (977~997) 21 987, Bit9 (969~989) 21 979,
3272 11:33:04.434352 TX Bit2 (974~992) 19 983, Bit10 (970~990) 21 980,
3273 11:33:04.437690 TX Bit3 (971~992) 22 981, Bit11 (971~992) 22 981,
3274 11:33:04.440880 TX Bit4 (975~994) 20 984, Bit12 (971~991) 21 981,
3275 11:33:04.447269 TX Bit5 (977~998) 22 987, Bit13 (972~990) 19 981,
3276 11:33:04.450716 TX Bit6 (977~998) 22 987, Bit14 (971~991) 21 981,
3277 11:33:04.453679 TX Bit7 (976~994) 19 985, Bit15 (967~986) 20 976,
3278 11:33:04.453757
3279 11:33:04.457192 Write Rank1 MR14 =0xc
3280 11:33:04.466477
3281 11:33:04.466582 CH=1, VrefRange= 0, VrefLevel = 12
3282 11:33:04.473111 TX Bit0 (977~999) 23 988, Bit8 (969~990) 22 979,
3283 11:33:04.476755 TX Bit1 (977~998) 22 987, Bit9 (969~990) 22 979,
3284 11:33:04.483047 TX Bit2 (973~993) 21 983, Bit10 (970~990) 21 980,
3285 11:33:04.486620 TX Bit3 (971~992) 22 981, Bit11 (971~992) 22 981,
3286 11:33:04.490272 TX Bit4 (975~994) 20 984, Bit12 (970~991) 22 980,
3287 11:33:04.496844 TX Bit5 (977~998) 22 987, Bit13 (972~991) 20 981,
3288 11:33:04.499984 TX Bit6 (977~999) 23 988, Bit14 (971~991) 21 981,
3289 11:33:04.503169 TX Bit7 (976~994) 19 985, Bit15 (967~987) 21 977,
3290 11:33:04.503245
3291 11:33:04.506318 Write Rank1 MR14 =0xe
3292 11:33:04.515810
3293 11:33:04.519284 CH=1, VrefRange= 0, VrefLevel = 14
3294 11:33:04.522242 TX Bit0 (977~999) 23 988, Bit8 (969~990) 22 979,
3295 11:33:04.525989 TX Bit1 (976~998) 23 987, Bit9 (969~990) 22 979,
3296 11:33:04.532327 TX Bit2 (973~993) 21 983, Bit10 (969~990) 22 979,
3297 11:33:04.535982 TX Bit3 (971~993) 23 982, Bit11 (971~992) 22 981,
3298 11:33:04.539483 TX Bit4 (974~995) 22 984, Bit12 (970~991) 22 980,
3299 11:33:04.545575 TX Bit5 (977~998) 22 987, Bit13 (971~991) 21 981,
3300 11:33:04.548916 TX Bit6 (977~999) 23 988, Bit14 (970~991) 22 980,
3301 11:33:04.552573 TX Bit7 (976~994) 19 985, Bit15 (967~987) 21 977,
3302 11:33:04.552649
3303 11:33:04.559324 wait MRW command Rank1 MR14 =0x10 fired (1)
3304 11:33:04.559400 Write Rank1 MR14 =0x10
3305 11:33:04.569115
3306 11:33:04.572783 CH=1, VrefRange= 0, VrefLevel = 16
3307 11:33:04.575774 TX Bit0 (977~1000) 24 988, Bit8 (969~991) 23 980,
3308 11:33:04.578880 TX Bit1 (977~998) 22 987, Bit9 (969~990) 22 979,
3309 11:33:04.585539 TX Bit2 (973~994) 22 983, Bit10 (970~991) 22 980,
3310 11:33:04.589524 TX Bit3 (970~993) 24 981, Bit11 (971~992) 22 981,
3311 11:33:04.592297 TX Bit4 (974~996) 23 985, Bit12 (970~992) 23 981,
3312 11:33:04.599067 TX Bit5 (976~998) 23 987, Bit13 (971~991) 21 981,
3313 11:33:04.602402 TX Bit6 (976~999) 24 987, Bit14 (969~991) 23 980,
3314 11:33:04.605831 TX Bit7 (976~995) 20 985, Bit15 (967~987) 21 977,
3315 11:33:04.608805
3316 11:33:04.608879 Write Rank1 MR14 =0x12
3317 11:33:04.618860
3318 11:33:04.622145 CH=1, VrefRange= 0, VrefLevel = 18
3319 11:33:04.625327 TX Bit0 (977~1000) 24 988, Bit8 (969~991) 23 980,
3320 11:33:04.628950 TX Bit1 (976~998) 23 987, Bit9 (968~991) 24 979,
3321 11:33:04.635145 TX Bit2 (972~994) 23 983, Bit10 (969~991) 23 980,
3322 11:33:04.638587 TX Bit3 (970~993) 24 981, Bit11 (970~993) 24 981,
3323 11:33:04.642218 TX Bit4 (974~997) 24 985, Bit12 (970~992) 23 981,
3324 11:33:04.648985 TX Bit5 (976~998) 23 987, Bit13 (971~992) 22 981,
3325 11:33:04.651874 TX Bit6 (977~999) 23 988, Bit14 (970~992) 23 981,
3326 11:33:04.655389 TX Bit7 (975~995) 21 985, Bit15 (967~988) 22 977,
3327 11:33:04.655465
3328 11:33:04.658390 Write Rank1 MR14 =0x14
3329 11:33:04.668678
3330 11:33:04.671268 CH=1, VrefRange= 0, VrefLevel = 20
3331 11:33:04.674813 TX Bit0 (977~1000) 24 988, Bit8 (969~992) 24 980,
3332 11:33:04.677801 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3333 11:33:04.685241 TX Bit2 (972~994) 23 983, Bit10 (968~991) 24 979,
3334 11:33:04.688047 TX Bit3 (969~994) 26 981, Bit11 (970~993) 24 981,
3335 11:33:04.691721 TX Bit4 (973~997) 25 985, Bit12 (970~992) 23 981,
3336 11:33:04.698325 TX Bit5 (976~999) 24 987, Bit13 (971~992) 22 981,
3337 11:33:04.701265 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3338 11:33:04.704766 TX Bit7 (975~996) 22 985, Bit15 (967~988) 22 977,
3339 11:33:04.704866
3340 11:33:04.708395 Write Rank1 MR14 =0x16
3341 11:33:04.717487
3342 11:33:04.720927 CH=1, VrefRange= 0, VrefLevel = 22
3343 11:33:04.724713 TX Bit0 (976~1001) 26 988, Bit8 (969~991) 23 980,
3344 11:33:04.727851 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3345 11:33:04.734825 TX Bit2 (971~995) 25 983, Bit10 (969~991) 23 980,
3346 11:33:04.737740 TX Bit3 (969~994) 26 981, Bit11 (969~993) 25 981,
3347 11:33:04.741290 TX Bit4 (973~997) 25 985, Bit12 (969~992) 24 980,
3348 11:33:04.748148 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
3349 11:33:04.751198 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3350 11:33:04.754676 TX Bit7 (974~997) 24 985, Bit15 (966~989) 24 977,
3351 11:33:04.757884
3352 11:33:04.758054 Write Rank1 MR14 =0x18
3353 11:33:04.767644
3354 11:33:04.770755 CH=1, VrefRange= 0, VrefLevel = 24
3355 11:33:04.774125 TX Bit0 (976~1001) 26 988, Bit8 (969~991) 23 980,
3356 11:33:04.777667 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3357 11:33:04.784157 TX Bit2 (971~995) 25 983, Bit10 (969~991) 23 980,
3358 11:33:04.787629 TX Bit3 (969~994) 26 981, Bit11 (969~993) 25 981,
3359 11:33:04.790580 TX Bit4 (973~997) 25 985, Bit12 (969~992) 24 980,
3360 11:33:04.797270 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
3361 11:33:04.800918 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3362 11:33:04.807816 TX Bit7 (974~997) 24 985, Bit15 (966~989) 24 977,
3363 11:33:04.807924
3364 11:33:04.808029 Write Rank1 MR14 =0x1a
3365 11:33:04.817377
3366 11:33:04.820949 CH=1, VrefRange= 0, VrefLevel = 26
3367 11:33:04.824443 TX Bit0 (976~1001) 26 988, Bit8 (969~991) 23 980,
3368 11:33:04.827602 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3369 11:33:04.834114 TX Bit2 (971~995) 25 983, Bit10 (969~991) 23 980,
3370 11:33:04.837126 TX Bit3 (969~994) 26 981, Bit11 (969~993) 25 981,
3371 11:33:04.840692 TX Bit4 (973~997) 25 985, Bit12 (969~992) 24 980,
3372 11:33:04.847570 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
3373 11:33:04.850768 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3374 11:33:04.857041 TX Bit7 (974~997) 24 985, Bit15 (966~989) 24 977,
3375 11:33:04.857133
3376 11:33:04.857213 Write Rank1 MR14 =0x1c
3377 11:33:04.867403
3378 11:33:04.870789 CH=1, VrefRange= 0, VrefLevel = 28
3379 11:33:04.873838 TX Bit0 (976~1001) 26 988, Bit8 (969~991) 23 980,
3380 11:33:04.877833 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3381 11:33:04.884606 TX Bit2 (971~995) 25 983, Bit10 (969~991) 23 980,
3382 11:33:04.887614 TX Bit3 (969~994) 26 981, Bit11 (969~993) 25 981,
3383 11:33:04.890791 TX Bit4 (973~997) 25 985, Bit12 (969~992) 24 980,
3384 11:33:04.897682 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
3385 11:33:04.901061 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3386 11:33:04.904136 TX Bit7 (974~997) 24 985, Bit15 (966~989) 24 977,
3387 11:33:04.907635
3388 11:33:04.908023 Write Rank1 MR14 =0x1e
3389 11:33:04.917511
3390 11:33:04.920370 CH=1, VrefRange= 0, VrefLevel = 30
3391 11:33:04.923812 TX Bit0 (976~1001) 26 988, Bit8 (969~991) 23 980,
3392 11:33:04.927561 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3393 11:33:04.933772 TX Bit2 (971~995) 25 983, Bit10 (969~991) 23 980,
3394 11:33:04.937358 TX Bit3 (969~994) 26 981, Bit11 (969~993) 25 981,
3395 11:33:04.940472 TX Bit4 (973~997) 25 985, Bit12 (969~992) 24 980,
3396 11:33:04.946963 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
3397 11:33:04.950813 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3398 11:33:04.953669 TX Bit7 (974~997) 24 985, Bit15 (966~989) 24 977,
3399 11:33:04.957078
3400 11:33:04.957514 Write Rank1 MR14 =0x20
3401 11:33:04.966626
3402 11:33:04.967027 CH=1, VrefRange= 0, VrefLevel = 32
3403 11:33:04.973489 TX Bit0 (976~1001) 26 988, Bit8 (969~991) 23 980,
3404 11:33:04.976945 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3405 11:33:04.983358 TX Bit2 (971~995) 25 983, Bit10 (969~991) 23 980,
3406 11:33:04.986736 TX Bit3 (969~994) 26 981, Bit11 (969~993) 25 981,
3407 11:33:04.990184 TX Bit4 (973~997) 25 985, Bit12 (969~992) 24 980,
3408 11:33:04.996572 TX Bit5 (976~999) 24 987, Bit13 (970~992) 23 981,
3409 11:33:05.000285 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3410 11:33:05.003262 TX Bit7 (974~997) 24 985, Bit15 (966~989) 24 977,
3411 11:33:05.006831
3412 11:33:05.007103
3413 11:33:05.009927 TX Vref found, early break! 361< 369
3414 11:33:05.013787 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps
3415 11:33:05.016388 u1DelayCellOfst[0]=8 cells (7 PI)
3416 11:33:05.019702 u1DelayCellOfst[1]=7 cells (6 PI)
3417 11:33:05.023086 u1DelayCellOfst[2]=2 cells (2 PI)
3418 11:33:05.027334 u1DelayCellOfst[3]=0 cells (0 PI)
3419 11:33:05.027645 u1DelayCellOfst[4]=5 cells (4 PI)
3420 11:33:05.030302 u1DelayCellOfst[5]=7 cells (6 PI)
3421 11:33:05.033438 u1DelayCellOfst[6]=8 cells (7 PI)
3422 11:33:05.036896 u1DelayCellOfst[7]=5 cells (4 PI)
3423 11:33:05.040237 Byte0, DQ PI dly=981, DQM PI dly= 984
3424 11:33:05.046890 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
3425 11:33:05.047229
3426 11:33:05.049987 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
3427 11:33:05.050255
3428 11:33:05.053179 u1DelayCellOfst[8]=3 cells (3 PI)
3429 11:33:05.056681 u1DelayCellOfst[9]=2 cells (2 PI)
3430 11:33:05.060786 u1DelayCellOfst[10]=3 cells (3 PI)
3431 11:33:05.063458 u1DelayCellOfst[11]=5 cells (4 PI)
3432 11:33:05.063810 u1DelayCellOfst[12]=3 cells (3 PI)
3433 11:33:05.066547 u1DelayCellOfst[13]=5 cells (4 PI)
3434 11:33:05.069714 u1DelayCellOfst[14]=3 cells (3 PI)
3435 11:33:05.073190 u1DelayCellOfst[15]=0 cells (0 PI)
3436 11:33:05.076778 Byte1, DQ PI dly=977, DQM PI dly= 979
3437 11:33:05.083522 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3438 11:33:05.083827
3439 11:33:05.086523 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3440 11:33:05.086795
3441 11:33:05.089933 Write Rank1 MR14 =0x16
3442 11:33:05.090234
3443 11:33:05.090592 Final TX Range 0 Vref 22
3444 11:33:05.090937
3445 11:33:05.096466 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3446 11:33:05.096869
3447 11:33:05.103471 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3448 11:33:05.110202 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3449 11:33:05.120250 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3450 11:33:05.120529 Write Rank1 MR3 =0xb0
3451 11:33:05.123205 DramC Write-DBI on
3452 11:33:05.123553 ==
3453 11:33:05.126496 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3454 11:33:05.130165 fsp= 1, odt_onoff= 1, Byte mode= 0
3455 11:33:05.130546 ==
3456 11:33:05.136706 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3457 11:33:05.137109
3458 11:33:05.137409 Begin, DQ Scan Range 699~763
3459 11:33:05.137694
3460 11:33:05.137897
3461 11:33:05.139790 TX Vref Scan disable
3462 11:33:05.143124 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3463 11:33:05.146545 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3464 11:33:05.149390 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3465 11:33:05.152874 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3466 11:33:05.156513 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3467 11:33:05.159512 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3468 11:33:05.163282 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3469 11:33:05.166871 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3470 11:33:05.173224 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3471 11:33:05.176246 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3472 11:33:05.179729 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3473 11:33:05.183598 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3474 11:33:05.186240 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3475 11:33:05.190067 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3476 11:33:05.193306 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3477 11:33:05.196545 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3478 11:33:05.199498 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3479 11:33:05.202671 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3480 11:33:05.210857 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3481 11:33:05.213812 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3482 11:33:05.217303 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3483 11:33:05.220439 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3484 11:33:05.223926 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3485 11:33:05.227018 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3486 11:33:05.230869 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3487 11:33:05.234122 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3488 11:33:05.237053 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
3489 11:33:05.240678 Byte0, DQ PI dly=730, DQM PI dly= 730
3490 11:33:05.244272 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3491 11:33:05.244347
3492 11:33:05.250546 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3493 11:33:05.250622
3494 11:33:05.254071 Byte1, DQ PI dly=723, DQM PI dly= 723
3495 11:33:05.257281 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3496 11:33:05.257356
3497 11:33:05.260288 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3498 11:33:05.260356
3499 11:33:05.267101 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3500 11:33:05.276912 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3501 11:33:05.283605 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3502 11:33:05.283700 Write Rank1 MR3 =0x30
3503 11:33:05.287257 DramC Write-DBI off
3504 11:33:05.287352
3505 11:33:05.287437 [DATLAT]
3506 11:33:05.290893 Freq=1600, CH1 RK1, use_rxtx_scan=0
3507 11:33:05.291023
3508 11:33:05.293511 DATLAT Default: 0x10
3509 11:33:05.293603 7, 0xFFFF, sum=0
3510 11:33:05.296995 8, 0xFFFF, sum=0
3511 11:33:05.297093 9, 0xFFFF, sum=0
3512 11:33:05.300277 10, 0xFFFF, sum=0
3513 11:33:05.300345 11, 0xFFFF, sum=0
3514 11:33:05.303947 12, 0xFFFF, sum=0
3515 11:33:05.304041 13, 0xFFFF, sum=0
3516 11:33:05.304125 14, 0x0, sum=1
3517 11:33:05.307303 15, 0x0, sum=2
3518 11:33:05.307397 16, 0x0, sum=3
3519 11:33:05.310963 17, 0x0, sum=4
3520 11:33:05.313564 pattern=2 first_step=14 total pass=5 best_step=16
3521 11:33:05.313672 ==
3522 11:33:05.320132 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3523 11:33:05.323055 fsp= 1, odt_onoff= 1, Byte mode= 0
3524 11:33:05.323153 ==
3525 11:33:05.326694 Start DQ dly to find pass range UseTestEngine =1
3526 11:33:05.330211 x-axis: bit #, y-axis: DQ dly (-127~63)
3527 11:33:05.333606 RX Vref Scan = 0
3528 11:33:05.333681 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3529 11:33:05.336516 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3530 11:33:05.339773 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3531 11:33:05.343117 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3532 11:33:05.346612 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3533 11:33:05.350173 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3534 11:33:05.353450 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3535 11:33:05.356287 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3536 11:33:05.356382 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3537 11:33:05.359798 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3538 11:33:05.363411 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3539 11:33:05.366744 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3540 11:33:05.370556 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3541 11:33:05.373361 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3542 11:33:05.376923 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3543 11:33:05.379805 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3544 11:33:05.379896 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3545 11:33:05.383472 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3546 11:33:05.386575 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3547 11:33:05.390224 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3548 11:33:05.393601 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3549 11:33:05.396486 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3550 11:33:05.400660 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3551 11:33:05.400757 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3552 11:33:05.403187 -2, [0] xxxoxxxx xxxxxxxx [MSB]
3553 11:33:05.406842 -1, [0] xxxoxxxx xxxxxxxx [MSB]
3554 11:33:05.410200 0, [0] xxooxxxx xxxxxxxo [MSB]
3555 11:33:05.413757 1, [0] xxooxxxo xxxxxxxo [MSB]
3556 11:33:05.416586 2, [0] xxoooxxo oooxxxxo [MSB]
3557 11:33:05.416684 3, [0] xxoooxxo ooooxooo [MSB]
3558 11:33:05.419763 4, [0] xxoooxxo oooooooo [MSB]
3559 11:33:05.423148 5, [0] xoooooxo oooooooo [MSB]
3560 11:33:05.426580 6, [0] xoooooxo oooooooo [MSB]
3561 11:33:05.430589 34, [0] oooxoooo oooooooo [MSB]
3562 11:33:05.433930 35, [0] oooxoooo ooooooox [MSB]
3563 11:33:05.437477 36, [0] ooxxoooo ooooooox [MSB]
3564 11:33:05.440624 37, [0] ooxxxoox ooxooxxx [MSB]
3565 11:33:05.444786 38, [0] ooxxxoox xxxooxxx [MSB]
3566 11:33:05.447083 39, [0] ooxxxoox xxxxoxxx [MSB]
3567 11:33:05.447184 40, [0] ooxxxoox xxxxxxxx [MSB]
3568 11:33:05.450541 41, [0] oxxxxoox xxxxxxxx [MSB]
3569 11:33:05.453602 42, [0] oxxxxxox xxxxxxxx [MSB]
3570 11:33:05.456944 43, [0] xxxxxxxx xxxxxxxx [MSB]
3571 11:33:05.460348 iDelay=43, Bit 0, Center 24 (7 ~ 42) 36
3572 11:33:05.463925 iDelay=43, Bit 1, Center 22 (5 ~ 40) 36
3573 11:33:05.467343 iDelay=43, Bit 2, Center 17 (0 ~ 35) 36
3574 11:33:05.470542 iDelay=43, Bit 3, Center 15 (-2 ~ 33) 36
3575 11:33:05.474330 iDelay=43, Bit 4, Center 19 (2 ~ 36) 35
3576 11:33:05.477468 iDelay=43, Bit 5, Center 23 (5 ~ 41) 37
3577 11:33:05.480854 iDelay=43, Bit 6, Center 24 (7 ~ 42) 36
3578 11:33:05.487373 iDelay=43, Bit 7, Center 18 (1 ~ 36) 36
3579 11:33:05.490858 iDelay=43, Bit 8, Center 19 (2 ~ 37) 36
3580 11:33:05.494139 iDelay=43, Bit 9, Center 19 (2 ~ 37) 36
3581 11:33:05.497443 iDelay=43, Bit 10, Center 19 (2 ~ 36) 35
3582 11:33:05.500797 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36
3583 11:33:05.503998 iDelay=43, Bit 12, Center 21 (4 ~ 39) 36
3584 11:33:05.507323 iDelay=43, Bit 13, Center 19 (3 ~ 36) 34
3585 11:33:05.510796 iDelay=43, Bit 14, Center 19 (3 ~ 36) 34
3586 11:33:05.513897 iDelay=43, Bit 15, Center 17 (0 ~ 34) 35
3587 11:33:05.513986 ==
3588 11:33:05.520695 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3589 11:33:05.523971 fsp= 1, odt_onoff= 1, Byte mode= 0
3590 11:33:05.524091 ==
3591 11:33:05.524149 DQS Delay:
3592 11:33:05.527763 DQS0 = 0, DQS1 = 0
3593 11:33:05.527837 DQM Delay:
3594 11:33:05.527894 DQM0 = 20, DQM1 = 19
3595 11:33:05.530619 DQ Delay:
3596 11:33:05.534040 DQ0 =24, DQ1 =22, DQ2 =17, DQ3 =15
3597 11:33:05.537376 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =18
3598 11:33:05.540985 DQ8 =19, DQ9 =19, DQ10 =19, DQ11 =20
3599 11:33:05.544124 DQ12 =21, DQ13 =19, DQ14 =19, DQ15 =17
3600 11:33:05.544198
3601 11:33:05.544255
3602 11:33:05.544308
3603 11:33:05.547592 [DramC_TX_OE_Calibration] TA2
3604 11:33:05.547666 Original DQ_B0 (3 6) =30, OEN = 27
3605 11:33:05.550680 Original DQ_B1 (3 6) =30, OEN = 27
3606 11:33:05.554154 23, 0x0, End_B0=23 End_B1=23
3607 11:33:05.557549 24, 0x0, End_B0=24 End_B1=24
3608 11:33:05.560787 25, 0x0, End_B0=25 End_B1=25
3609 11:33:05.560862 26, 0x0, End_B0=26 End_B1=26
3610 11:33:05.564238 27, 0x0, End_B0=27 End_B1=27
3611 11:33:05.567359 28, 0x0, End_B0=28 End_B1=28
3612 11:33:05.570702 29, 0x0, End_B0=29 End_B1=29
3613 11:33:05.574464 30, 0x0, End_B0=30 End_B1=30
3614 11:33:05.574540 31, 0xFFFF, End_B0=30 End_B1=30
3615 11:33:05.581266 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3616 11:33:05.587536 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3617 11:33:05.587610
3618 11:33:05.587667
3619 11:33:05.587720 Write Rank1 MR23 =0x3f
3620 11:33:05.591250 [DQSOSC]
3621 11:33:05.597622 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2, (MSB)MR19= 0x3, tDQSOscB0 = 332 ps tDQSOscB1 = 0 ps
3622 11:33:05.604093 CH1_RK1: MR19=0x3, MR18=0xB2, DQSOSC=332, MR23=63, INC=22, DEC=33
3623 11:33:05.604195 Write Rank1 MR23 =0x3f
3624 11:33:05.607522 [DQSOSC]
3625 11:33:05.614204 [DQSOSCAuto] RK1, (LSB)MR18= 0xae, (MSB)MR19= 0x3, tDQSOscB0 = 334 ps tDQSOscB1 = 0 ps
3626 11:33:05.614279 CH1 RK1: MR19=3, MR18=AE
3627 11:33:05.617511 [RxdqsGatingPostProcess] freq 1600
3628 11:33:05.624017 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3629 11:33:05.624092 Rank: 0
3630 11:33:05.627754 best DQS0 dly(2T, 0.5T) = (2, 5)
3631 11:33:05.630890 best DQS1 dly(2T, 0.5T) = (2, 5)
3632 11:33:05.633993 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3633 11:33:05.637424 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3634 11:33:05.637499 Rank: 1
3635 11:33:05.641004 best DQS0 dly(2T, 0.5T) = (2, 5)
3636 11:33:05.644462 best DQS1 dly(2T, 0.5T) = (2, 5)
3637 11:33:05.647367 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3638 11:33:05.651010 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3639 11:33:05.654424 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3640 11:33:05.657443 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3641 11:33:05.663898 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3642 11:33:05.663973
3643 11:33:05.664030
3644 11:33:05.667411 [Calibration Summary] Freqency 1600
3645 11:33:05.667485 CH 0, Rank 0
3646 11:33:05.670525 All Pass.
3647 11:33:05.670598
3648 11:33:05.670655 CH 0, Rank 1
3649 11:33:05.670708 All Pass.
3650 11:33:05.670758
3651 11:33:05.674221 CH 1, Rank 0
3652 11:33:05.674295 All Pass.
3653 11:33:05.674360
3654 11:33:05.674413 CH 1, Rank 1
3655 11:33:05.677615 All Pass.
3656 11:33:05.677689
3657 11:33:05.684122 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3658 11:33:05.690889 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3659 11:33:05.697413 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3660 11:33:05.697508 Write Rank0 MR3 =0xb0
3661 11:33:05.703816 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3662 11:33:05.714226 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3663 11:33:05.720458 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3664 11:33:05.720534 Write Rank1 MR3 =0xb0
3665 11:33:05.727221 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3666 11:33:05.734238 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3667 11:33:05.740357 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3668 11:33:05.743877 Write Rank0 MR3 =0xb0
3669 11:33:05.750530 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3670 11:33:05.757119 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3671 11:33:05.764123 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3672 11:33:05.767047 Write Rank1 MR3 =0xb0
3673 11:33:05.767121 DramC Write-DBI on
3674 11:33:05.770581 [GetDramInforAfterCalByMRR] Vendor 1.
3675 11:33:05.774319 [GetDramInforAfterCalByMRR] Revision 7.
3676 11:33:05.777060 MR8 12
3677 11:33:05.780918 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3678 11:33:05.780992 MR8 12
3679 11:33:05.787067 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3680 11:33:05.787165 MR8 12
3681 11:33:05.790853 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3682 11:33:05.790947 MR8 12
3683 11:33:05.797374 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3684 11:33:05.807096 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3685 11:33:05.807196 Write Rank0 MR13 =0xd0
3686 11:33:05.810804 Write Rank1 MR13 =0xd0
3687 11:33:05.810895 Write Rank0 MR13 =0xd0
3688 11:33:05.814159 Write Rank1 MR13 =0xd0
3689 11:33:05.817362 Save calibration result to emmc
3690 11:33:05.817451
3691 11:33:05.817531
3692 11:33:05.820452 [DramcModeReg_Check] Freq_1600, FSP_1
3693 11:33:05.823903 FSP_1, CH_0, RK0
3694 11:33:05.824005 Write Rank0 MR13 =0xd8
3695 11:33:05.827045 MR12 = 0x56 (global = 0x56) match
3696 11:33:05.830850 MR14 = 0x16 (global = 0x16) match
3697 11:33:05.834146 FSP_1, CH_0, RK1
3698 11:33:05.834235 Write Rank1 MR13 =0xd8
3699 11:33:05.837475 MR12 = 0x56 (global = 0x56) match
3700 11:33:05.840432 MR14 = 0x16 (global = 0x16) match
3701 11:33:05.844048 FSP_1, CH_1, RK0
3702 11:33:05.844146 Write Rank0 MR13 =0xd8
3703 11:33:05.847113 MR12 = 0x58 (global = 0x58) match
3704 11:33:05.851029 MR14 = 0x18 (global = 0x18) match
3705 11:33:05.854663 FSP_1, CH_1, RK1
3706 11:33:05.854757 Write Rank1 MR13 =0xd8
3707 11:33:05.857393 MR12 = 0x58 (global = 0x58) match
3708 11:33:05.860501 MR14 = 0x16 (global = 0x16) match
3709 11:33:05.860598
3710 11:33:05.863976 [MEM_TEST] 02: After DFS, before run time config
3711 11:33:05.875815 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3712 11:33:05.875918
3713 11:33:05.876004 [TA2_TEST]
3714 11:33:05.876084 === TA2 HW
3715 11:33:05.879385 TA2 PAT: XTALK
3716 11:33:05.882435 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3717 11:33:05.889814 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3718 11:33:05.892870 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3719 11:33:05.895980 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3720 11:33:05.899234
3721 11:33:05.899309
3722 11:33:05.899367 Settings after calibration
3723 11:33:05.899448
3724 11:33:05.902590 [DramcRunTimeConfig]
3725 11:33:05.906179 TransferPLLToSPMControl - MODE SW PHYPLL
3726 11:33:05.906255 TX_TRACKING: ON
3727 11:33:05.909113 RX_TRACKING: ON
3728 11:33:05.909226 HW_GATING: ON
3729 11:33:05.912961 HW_GATING DBG: OFF
3730 11:33:05.913036 ddr_geometry:1
3731 11:33:05.916344 ddr_geometry:1
3732 11:33:05.916419 ddr_geometry:1
3733 11:33:05.916478 ddr_geometry:1
3734 11:33:05.919471 ddr_geometry:1
3735 11:33:05.919545 ddr_geometry:1
3736 11:33:05.922397 ddr_geometry:1
3737 11:33:05.922472 ddr_geometry:1
3738 11:33:05.925806 High Freq DUMMY_READ_FOR_TRACKING: ON
3739 11:33:05.929435 ZQCS_ENABLE_LP4: OFF
3740 11:33:05.932668 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3741 11:33:05.935767 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3742 11:33:05.935836 SPM_CONTROL_AFTERK: ON
3743 11:33:05.939322 IMPEDANCE_TRACKING: ON
3744 11:33:05.939427 TEMP_SENSOR: ON
3745 11:33:05.942470 PER_BANK_REFRESH: ON
3746 11:33:05.942535 HW_SAVE_FOR_SR: ON
3747 11:33:05.945709 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3748 11:33:05.949486 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3749 11:33:05.952215 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3750 11:33:05.955769 Read ODT Tracking: ON
3751 11:33:05.959019 =========================
3752 11:33:05.959129
3753 11:33:05.959226 [TA2_TEST]
3754 11:33:05.959305 === TA2 HW
3755 11:33:05.966373 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3756 11:33:05.968955 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3757 11:33:05.976017 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3758 11:33:05.978987 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3759 11:33:05.979079
3760 11:33:05.982331 [MEM_TEST] 03: After run time config
3761 11:33:05.994347 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3762 11:33:05.997395 [complex_mem_test] start addr:0x40024000, len:131072
3763 11:33:06.201981 1st complex R/W mem test pass
3764 11:33:06.208584 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3765 11:33:06.211676 sync preloader write leveling
3766 11:33:06.214738 sync preloader cbt_mr12
3767 11:33:06.218380 sync preloader cbt_clk_dly
3768 11:33:06.218876 sync preloader cbt_cmd_dly
3769 11:33:06.221988 sync preloader cbt_cs
3770 11:33:06.224787 sync preloader cbt_ca_perbit_delay
3771 11:33:06.225308 sync preloader clk_delay
3772 11:33:06.228552 sync preloader dqs_delay
3773 11:33:06.231717 sync preloader u1Gating2T_Save
3774 11:33:06.235146 sync preloader u1Gating05T_Save
3775 11:33:06.238197 sync preloader u1Gatingfine_tune_Save
3776 11:33:06.241422 sync preloader u1Gatingucpass_count_Save
3777 11:33:06.245233 sync preloader u1TxWindowPerbitVref_Save
3778 11:33:06.248227 sync preloader u1TxCenter_min_Save
3779 11:33:06.251827 sync preloader u1TxCenter_max_Save
3780 11:33:06.255318 sync preloader u1Txwin_center_Save
3781 11:33:06.258404 sync preloader u1Txfirst_pass_Save
3782 11:33:06.262169 sync preloader u1Txlast_pass_Save
3783 11:33:06.262694 sync preloader u1RxDatlat_Save
3784 11:33:06.264856 sync preloader u1RxWinPerbitVref_Save
3785 11:33:06.271789 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3786 11:33:06.275209 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3787 11:33:06.278559 sync preloader delay_cell_unit
3788 11:33:06.285193 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3789 11:33:06.288242 sync preloader write leveling
3790 11:33:06.288754 sync preloader cbt_mr12
3791 11:33:06.291850 sync preloader cbt_clk_dly
3792 11:33:06.295282 sync preloader cbt_cmd_dly
3793 11:33:06.295773 sync preloader cbt_cs
3794 11:33:06.298914 sync preloader cbt_ca_perbit_delay
3795 11:33:06.301678 sync preloader clk_delay
3796 11:33:06.304853 sync preloader dqs_delay
3797 11:33:06.305249 sync preloader u1Gating2T_Save
3798 11:33:06.308190 sync preloader u1Gating05T_Save
3799 11:33:06.311734 sync preloader u1Gatingfine_tune_Save
3800 11:33:06.314710 sync preloader u1Gatingucpass_count_Save
3801 11:33:06.318179 sync preloader u1TxWindowPerbitVref_Save
3802 11:33:06.321820 sync preloader u1TxCenter_min_Save
3803 11:33:06.325235 sync preloader u1TxCenter_max_Save
3804 11:33:06.328351 sync preloader u1Txwin_center_Save
3805 11:33:06.331408 sync preloader u1Txfirst_pass_Save
3806 11:33:06.335031 sync preloader u1Txlast_pass_Save
3807 11:33:06.338030 sync preloader u1RxDatlat_Save
3808 11:33:06.341806 sync preloader u1RxWinPerbitVref_Save
3809 11:33:06.345189 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3810 11:33:06.348809 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3811 11:33:06.351735 sync preloader delay_cell_unit
3812 11:33:06.358520 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3813 11:33:06.361747 sync preloader write leveling
3814 11:33:06.365108 sync preloader cbt_mr12
3815 11:33:06.365562 sync preloader cbt_clk_dly
3816 11:33:06.368264 sync preloader cbt_cmd_dly
3817 11:33:06.371420 sync preloader cbt_cs
3818 11:33:06.374785 sync preloader cbt_ca_perbit_delay
3819 11:33:06.375152 sync preloader clk_delay
3820 11:33:06.378455 sync preloader dqs_delay
3821 11:33:06.381416 sync preloader u1Gating2T_Save
3822 11:33:06.384812 sync preloader u1Gating05T_Save
3823 11:33:06.388624 sync preloader u1Gatingfine_tune_Save
3824 11:33:06.391377 sync preloader u1Gatingucpass_count_Save
3825 11:33:06.395064 sync preloader u1TxWindowPerbitVref_Save
3826 11:33:06.398165 sync preloader u1TxCenter_min_Save
3827 11:33:06.401458 sync preloader u1TxCenter_max_Save
3828 11:33:06.405245 sync preloader u1Txwin_center_Save
3829 11:33:06.408147 sync preloader u1Txfirst_pass_Save
3830 11:33:06.408609 sync preloader u1Txlast_pass_Save
3831 11:33:06.411351 sync preloader u1RxDatlat_Save
3832 11:33:06.415048 sync preloader u1RxWinPerbitVref_Save
3833 11:33:06.421766 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3834 11:33:06.424886 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3835 11:33:06.427860 sync preloader delay_cell_unit
3836 11:33:06.431557 just_for_test_dump_coreboot_params dump all params
3837 11:33:06.431905 dump source = 0x0
3838 11:33:06.434686 dump params frequency:1600
3839 11:33:06.438319 dump params rank number:2
3840 11:33:06.438668
3841 11:33:06.441401 dump params write leveling
3842 11:33:06.444922 write leveling[0][0][0] = 0x20
3843 11:33:06.445359 write leveling[0][0][1] = 0x19
3844 11:33:06.448241 write leveling[0][1][0] = 0x23
3845 11:33:06.451357 write leveling[0][1][1] = 0x1c
3846 11:33:06.455095 write leveling[1][0][0] = 0x24
3847 11:33:06.457922 write leveling[1][0][1] = 0x1f
3848 11:33:06.461457 write leveling[1][1][0] = 0x22
3849 11:33:06.461932 write leveling[1][1][1] = 0x20
3850 11:33:06.464635 dump params cbt_cs
3851 11:33:06.464982 cbt_cs[0][0] = 0xa
3852 11:33:06.467847 cbt_cs[0][1] = 0xa
3853 11:33:06.468233 cbt_cs[1][0] = 0xa
3854 11:33:06.471613 cbt_cs[1][1] = 0xa
3855 11:33:06.474910 dump params cbt_mr12
3856 11:33:06.475296 cbt_mr12[0][0] = 0x16
3857 11:33:06.478554 cbt_mr12[0][1] = 0x16
3858 11:33:06.478937 cbt_mr12[1][0] = 0x18
3859 11:33:06.481740 cbt_mr12[1][1] = 0x18
3860 11:33:06.482089 dump params tx window
3861 11:33:06.484719 tx_center_min[0][0][0] = 979
3862 11:33:06.488180 tx_center_max[0][0][0] = 985
3863 11:33:06.491892 tx_center_min[0][0][1] = 973
3864 11:33:06.494768 tx_center_max[0][0][1] = 978
3865 11:33:06.495153 tx_center_min[0][1][0] = 983
3866 11:33:06.498345 tx_center_max[0][1][0] = 990
3867 11:33:06.501501 tx_center_min[0][1][1] = 977
3868 11:33:06.505378 tx_center_max[0][1][1] = 980
3869 11:33:06.508164 tx_center_min[1][0][0] = 983
3870 11:33:06.508531 tx_center_max[1][0][0] = 989
3871 11:33:06.511837 tx_center_min[1][0][1] = 975
3872 11:33:06.514910 tx_center_max[1][0][1] = 980
3873 11:33:06.518345 tx_center_min[1][1][0] = 981
3874 11:33:06.521625 tx_center_max[1][1][0] = 988
3875 11:33:06.521980 tx_center_min[1][1][1] = 977
3876 11:33:06.524621 tx_center_max[1][1][1] = 981
3877 11:33:06.527913 dump params tx window
3878 11:33:06.528376 tx_win_center[0][0][0] = 985
3879 11:33:06.531210 tx_first_pass[0][0][0] = 974
3880 11:33:06.534645 tx_last_pass[0][0][0] = 997
3881 11:33:06.538348 tx_win_center[0][0][1] = 984
3882 11:33:06.541316 tx_first_pass[0][0][1] = 972
3883 11:33:06.541709 tx_last_pass[0][0][1] = 996
3884 11:33:06.544621 tx_win_center[0][0][2] = 983
3885 11:33:06.548060 tx_first_pass[0][0][2] = 972
3886 11:33:06.551468 tx_last_pass[0][0][2] = 995
3887 11:33:06.551821 tx_win_center[0][0][3] = 979
3888 11:33:06.554736 tx_first_pass[0][0][3] = 967
3889 11:33:06.557903 tx_last_pass[0][0][3] = 991
3890 11:33:06.561455 tx_win_center[0][0][4] = 983
3891 11:33:06.564557 tx_first_pass[0][0][4] = 971
3892 11:33:06.564943 tx_last_pass[0][0][4] = 996
3893 11:33:06.567839 tx_win_center[0][0][5] = 979
3894 11:33:06.571401 tx_first_pass[0][0][5] = 968
3895 11:33:06.574302 tx_last_pass[0][0][5] = 991
3896 11:33:06.574687 tx_win_center[0][0][6] = 980
3897 11:33:06.578220 tx_first_pass[0][0][6] = 969
3898 11:33:06.581367 tx_last_pass[0][0][6] = 992
3899 11:33:06.584538 tx_win_center[0][0][7] = 981
3900 11:33:06.588153 tx_first_pass[0][0][7] = 970
3901 11:33:06.588630 tx_last_pass[0][0][7] = 993
3902 11:33:06.591073 tx_win_center[0][0][8] = 973
3903 11:33:06.594802 tx_first_pass[0][0][8] = 961
3904 11:33:06.597783 tx_last_pass[0][0][8] = 986
3905 11:33:06.598169 tx_win_center[0][0][9] = 974
3906 11:33:06.601543 tx_first_pass[0][0][9] = 962
3907 11:33:06.604369 tx_last_pass[0][0][9] = 986
3908 11:33:06.607972 tx_win_center[0][0][10] = 978
3909 11:33:06.611371 tx_first_pass[0][0][10] = 966
3910 11:33:06.611759 tx_last_pass[0][0][10] = 990
3911 11:33:06.614206 tx_win_center[0][0][11] = 973
3912 11:33:06.617832 tx_first_pass[0][0][11] = 961
3913 11:33:06.620951 tx_last_pass[0][0][11] = 985
3914 11:33:06.624367 tx_win_center[0][0][12] = 973
3915 11:33:06.624756 tx_first_pass[0][0][12] = 961
3916 11:33:06.628026 tx_last_pass[0][0][12] = 986
3917 11:33:06.631168 tx_win_center[0][0][13] = 973
3918 11:33:06.634489 tx_first_pass[0][0][13] = 961
3919 11:33:06.637768 tx_last_pass[0][0][13] = 985
3920 11:33:06.638100 tx_win_center[0][0][14] = 974
3921 11:33:06.640955 tx_first_pass[0][0][14] = 962
3922 11:33:06.644352 tx_last_pass[0][0][14] = 986
3923 11:33:06.647914 tx_win_center[0][0][15] = 977
3924 11:33:06.651416 tx_first_pass[0][0][15] = 965
3925 11:33:06.654053 tx_last_pass[0][0][15] = 989
3926 11:33:06.654437 tx_win_center[0][1][0] = 990
3927 11:33:06.657748 tx_first_pass[0][1][0] = 978
3928 11:33:06.661229 tx_last_pass[0][1][0] = 1003
3929 11:33:06.664122 tx_win_center[0][1][1] = 989
3930 11:33:06.664505 tx_first_pass[0][1][1] = 977
3931 11:33:06.667557 tx_last_pass[0][1][1] = 1001
3932 11:33:06.671212 tx_win_center[0][1][2] = 988
3933 11:33:06.674440 tx_first_pass[0][1][2] = 977
3934 11:33:06.677912 tx_last_pass[0][1][2] = 1000
3935 11:33:06.678296 tx_win_center[0][1][3] = 983
3936 11:33:06.680787 tx_first_pass[0][1][3] = 970
3937 11:33:06.684133 tx_last_pass[0][1][3] = 996
3938 11:33:06.687748 tx_win_center[0][1][4] = 989
3939 11:33:06.688298 tx_first_pass[0][1][4] = 977
3940 11:33:06.691553 tx_last_pass[0][1][4] = 1001
3941 11:33:06.694706 tx_win_center[0][1][5] = 984
3942 11:33:06.698084 tx_first_pass[0][1][5] = 972
3943 11:33:06.701463 tx_last_pass[0][1][5] = 996
3944 11:33:06.701844 tx_win_center[0][1][6] = 985
3945 11:33:06.704914 tx_first_pass[0][1][6] = 972
3946 11:33:06.708060 tx_last_pass[0][1][6] = 998
3947 11:33:06.711359 tx_win_center[0][1][7] = 987
3948 11:33:06.711740 tx_first_pass[0][1][7] = 975
3949 11:33:06.715134 tx_last_pass[0][1][7] = 999
3950 11:33:06.718156 tx_win_center[0][1][8] = 978
3951 11:33:06.721307 tx_first_pass[0][1][8] = 967
3952 11:33:06.721715 tx_last_pass[0][1][8] = 989
3953 11:33:06.724647 tx_win_center[0][1][9] = 978
3954 11:33:06.728382 tx_first_pass[0][1][9] = 967
3955 11:33:06.731302 tx_last_pass[0][1][9] = 990
3956 11:33:06.734894 tx_win_center[0][1][10] = 980
3957 11:33:06.735351 tx_first_pass[0][1][10] = 969
3958 11:33:06.738379 tx_last_pass[0][1][10] = 992
3959 11:33:06.741630 tx_win_center[0][1][11] = 977
3960 11:33:06.744335 tx_first_pass[0][1][11] = 966
3961 11:33:06.748162 tx_last_pass[0][1][11] = 989
3962 11:33:06.748599 tx_win_center[0][1][12] = 978
3963 11:33:06.751250 tx_first_pass[0][1][12] = 967
3964 11:33:06.754607 tx_last_pass[0][1][12] = 989
3965 11:33:06.757906 tx_win_center[0][1][13] = 977
3966 11:33:06.761542 tx_first_pass[0][1][13] = 966
3967 11:33:06.761965 tx_last_pass[0][1][13] = 988
3968 11:33:06.764762 tx_win_center[0][1][14] = 978
3969 11:33:06.767979 tx_first_pass[0][1][14] = 967
3970 11:33:06.771275 tx_last_pass[0][1][14] = 989
3971 11:33:06.774320 tx_win_center[0][1][15] = 979
3972 11:33:06.774679 tx_first_pass[0][1][15] = 969
3973 11:33:06.777654 tx_last_pass[0][1][15] = 990
3974 11:33:06.781108 tx_win_center[1][0][0] = 989
3975 11:33:06.784679 tx_first_pass[1][0][0] = 977
3976 11:33:06.787778 tx_last_pass[1][0][0] = 1002
3977 11:33:06.788164 tx_win_center[1][0][1] = 988
3978 11:33:06.791176 tx_first_pass[1][0][1] = 976
3979 11:33:06.794412 tx_last_pass[1][0][1] = 1000
3980 11:33:06.797868 tx_win_center[1][0][2] = 985
3981 11:33:06.801592 tx_first_pass[1][0][2] = 974
3982 11:33:06.801982 tx_last_pass[1][0][2] = 997
3983 11:33:06.804577 tx_win_center[1][0][3] = 983
3984 11:33:06.807928 tx_first_pass[1][0][3] = 971
3985 11:33:06.810870 tx_last_pass[1][0][3] = 996
3986 11:33:06.811237 tx_win_center[1][0][4] = 987
3987 11:33:06.814485 tx_first_pass[1][0][4] = 975
3988 11:33:06.817923 tx_last_pass[1][0][4] = 999
3989 11:33:06.821133 tx_win_center[1][0][5] = 988
3990 11:33:06.821550 tx_first_pass[1][0][5] = 976
3991 11:33:06.824923 tx_last_pass[1][0][5] = 1001
3992 11:33:06.828029 tx_win_center[1][0][6] = 989
3993 11:33:06.831091 tx_first_pass[1][0][6] = 977
3994 11:33:06.834565 tx_last_pass[1][0][6] = 1002
3995 11:33:06.834955 tx_win_center[1][0][7] = 986
3996 11:33:06.838145 tx_first_pass[1][0][7] = 975
3997 11:33:06.841838 tx_last_pass[1][0][7] = 998
3998 11:33:06.844524 tx_win_center[1][0][8] = 979
3999 11:33:06.847780 tx_first_pass[1][0][8] = 967
4000 11:33:06.848172 tx_last_pass[1][0][8] = 991
4001 11:33:06.851327 tx_win_center[1][0][9] = 978
4002 11:33:06.854664 tx_first_pass[1][0][9] = 966
4003 11:33:06.857733 tx_last_pass[1][0][9] = 990
4004 11:33:06.858122 tx_win_center[1][0][10] = 979
4005 11:33:06.861548 tx_first_pass[1][0][10] = 968
4006 11:33:06.864776 tx_last_pass[1][0][10] = 991
4007 11:33:06.868246 tx_win_center[1][0][11] = 980
4008 11:33:06.871644 tx_first_pass[1][0][11] = 968
4009 11:33:06.872027 tx_last_pass[1][0][11] = 992
4010 11:33:06.874471 tx_win_center[1][0][12] = 980
4011 11:33:06.878177 tx_first_pass[1][0][12] = 968
4012 11:33:06.881515 tx_last_pass[1][0][12] = 992
4013 11:33:06.884393 tx_win_center[1][0][13] = 980
4014 11:33:06.884774 tx_first_pass[1][0][13] = 969
4015 11:33:06.888122 tx_last_pass[1][0][13] = 991
4016 11:33:06.891310 tx_win_center[1][0][14] = 979
4017 11:33:06.894777 tx_first_pass[1][0][14] = 967
4018 11:33:06.897935 tx_last_pass[1][0][14] = 991
4019 11:33:06.898274 tx_win_center[1][0][15] = 975
4020 11:33:06.901172 tx_first_pass[1][0][15] = 963
4021 11:33:06.904550 tx_last_pass[1][0][15] = 987
4022 11:33:06.907814 tx_win_center[1][1][0] = 988
4023 11:33:06.910919 tx_first_pass[1][1][0] = 976
4024 11:33:06.911241 tx_last_pass[1][1][0] = 1001
4025 11:33:06.914868 tx_win_center[1][1][1] = 987
4026 11:33:06.917834 tx_first_pass[1][1][1] = 976
4027 11:33:06.921353 tx_last_pass[1][1][1] = 999
4028 11:33:06.921747 tx_win_center[1][1][2] = 983
4029 11:33:06.924655 tx_first_pass[1][1][2] = 971
4030 11:33:06.928238 tx_last_pass[1][1][2] = 995
4031 11:33:06.931176 tx_win_center[1][1][3] = 981
4032 11:33:06.934832 tx_first_pass[1][1][3] = 969
4033 11:33:06.935236 tx_last_pass[1][1][3] = 994
4034 11:33:06.937636 tx_win_center[1][1][4] = 985
4035 11:33:06.941326 tx_first_pass[1][1][4] = 973
4036 11:33:06.944265 tx_last_pass[1][1][4] = 997
4037 11:33:06.944694 tx_win_center[1][1][5] = 987
4038 11:33:06.947942 tx_first_pass[1][1][5] = 976
4039 11:33:06.951496 tx_last_pass[1][1][5] = 999
4040 11:33:06.954527 tx_win_center[1][1][6] = 988
4041 11:33:06.957942 tx_first_pass[1][1][6] = 976
4042 11:33:06.958286 tx_last_pass[1][1][6] = 1000
4043 11:33:06.961455 tx_win_center[1][1][7] = 985
4044 11:33:06.964419 tx_first_pass[1][1][7] = 974
4045 11:33:06.967939 tx_last_pass[1][1][7] = 997
4046 11:33:06.971093 tx_win_center[1][1][8] = 980
4047 11:33:06.971449 tx_first_pass[1][1][8] = 969
4048 11:33:06.974194 tx_last_pass[1][1][8] = 991
4049 11:33:06.977606 tx_win_center[1][1][9] = 979
4050 11:33:06.980857 tx_first_pass[1][1][9] = 968
4051 11:33:06.981293 tx_last_pass[1][1][9] = 991
4052 11:33:06.984834 tx_win_center[1][1][10] = 980
4053 11:33:06.988112 tx_first_pass[1][1][10] = 969
4054 11:33:06.991077 tx_last_pass[1][1][10] = 991
4055 11:33:06.994227 tx_win_center[1][1][11] = 981
4056 11:33:06.994617 tx_first_pass[1][1][11] = 969
4057 11:33:06.997761 tx_last_pass[1][1][11] = 993
4058 11:33:07.000853 tx_win_center[1][1][12] = 980
4059 11:33:07.004263 tx_first_pass[1][1][12] = 969
4060 11:33:07.007749 tx_last_pass[1][1][12] = 992
4061 11:33:07.007959 tx_win_center[1][1][13] = 981
4062 11:33:07.011030 tx_first_pass[1][1][13] = 970
4063 11:33:07.014275 tx_last_pass[1][1][13] = 992
4064 11:33:07.017203 tx_win_center[1][1][14] = 980
4065 11:33:07.020874 tx_first_pass[1][1][14] = 969
4066 11:33:07.021046 tx_last_pass[1][1][14] = 992
4067 11:33:07.024100 tx_win_center[1][1][15] = 977
4068 11:33:07.027219 tx_first_pass[1][1][15] = 966
4069 11:33:07.031080 tx_last_pass[1][1][15] = 989
4070 11:33:07.031221 dump params rx window
4071 11:33:07.033936 rx_firspass[0][0][0] = 9
4072 11:33:07.037470 rx_lastpass[0][0][0] = 42
4073 11:33:07.037611 rx_firspass[0][0][1] = 8
4074 11:33:07.041157 rx_lastpass[0][0][1] = 40
4075 11:33:07.044026 rx_firspass[0][0][2] = 9
4076 11:33:07.047737 rx_lastpass[0][0][2] = 40
4077 11:33:07.047898 rx_firspass[0][0][3] = -2
4078 11:33:07.051461 rx_lastpass[0][0][3] = 32
4079 11:33:07.054078 rx_firspass[0][0][4] = 7
4080 11:33:07.054264 rx_lastpass[0][0][4] = 40
4081 11:33:07.057409 rx_firspass[0][0][5] = 2
4082 11:33:07.061061 rx_lastpass[0][0][5] = 30
4083 11:33:07.061359 rx_firspass[0][0][6] = 1
4084 11:33:07.064494 rx_lastpass[0][0][6] = 34
4085 11:33:07.067503 rx_firspass[0][0][7] = 3
4086 11:33:07.070959 rx_lastpass[0][0][7] = 35
4087 11:33:07.071312 rx_firspass[0][0][8] = 2
4088 11:33:07.074474 rx_lastpass[0][0][8] = 35
4089 11:33:07.077521 rx_firspass[0][0][9] = 4
4090 11:33:07.077842 rx_lastpass[0][0][9] = 36
4091 11:33:07.080790 rx_firspass[0][0][10] = 9
4092 11:33:07.084256 rx_lastpass[0][0][10] = 39
4093 11:33:07.088213 rx_firspass[0][0][11] = 2
4094 11:33:07.088584 rx_lastpass[0][0][11] = 31
4095 11:33:07.090916 rx_firspass[0][0][12] = 4
4096 11:33:07.094270 rx_lastpass[0][0][12] = 35
4097 11:33:07.094624 rx_firspass[0][0][13] = 1
4098 11:33:07.098029 rx_lastpass[0][0][13] = 32
4099 11:33:07.100796 rx_firspass[0][0][14] = 2
4100 11:33:07.104088 rx_lastpass[0][0][14] = 34
4101 11:33:07.104417 rx_firspass[0][0][15] = 3
4102 11:33:07.107543 rx_lastpass[0][0][15] = 36
4103 11:33:07.111041 rx_firspass[0][1][0] = 9
4104 11:33:07.114527 rx_lastpass[0][1][0] = 43
4105 11:33:07.114888 rx_firspass[0][1][1] = 7
4106 11:33:07.117729 rx_lastpass[0][1][1] = 42
4107 11:33:07.121005 rx_firspass[0][1][2] = 7
4108 11:33:07.121367 rx_lastpass[0][1][2] = 42
4109 11:33:07.124284 rx_firspass[0][1][3] = -2
4110 11:33:07.127285 rx_lastpass[0][1][3] = 33
4111 11:33:07.127610 rx_firspass[0][1][4] = 5
4112 11:33:07.130923 rx_lastpass[0][1][4] = 40
4113 11:33:07.134220 rx_firspass[0][1][5] = 1
4114 11:33:07.137373 rx_lastpass[0][1][5] = 34
4115 11:33:07.137711 rx_firspass[0][1][6] = 2
4116 11:33:07.140788 rx_lastpass[0][1][6] = 35
4117 11:33:07.144342 rx_firspass[0][1][7] = 2
4118 11:33:07.144923 rx_lastpass[0][1][7] = 36
4119 11:33:07.147465 rx_firspass[0][1][8] = 0
4120 11:33:07.150823 rx_lastpass[0][1][8] = 36
4121 11:33:07.151211 rx_firspass[0][1][9] = 1
4122 11:33:07.153957 rx_lastpass[0][1][9] = 38
4123 11:33:07.157125 rx_firspass[0][1][10] = 6
4124 11:33:07.160980 rx_lastpass[0][1][10] = 41
4125 11:33:07.161413 rx_firspass[0][1][11] = 1
4126 11:33:07.163783 rx_lastpass[0][1][11] = 33
4127 11:33:07.167223 rx_firspass[0][1][12] = 1
4128 11:33:07.170927 rx_lastpass[0][1][12] = 36
4129 11:33:07.171324 rx_firspass[0][1][13] = -1
4130 11:33:07.173939 rx_lastpass[0][1][13] = 34
4131 11:33:07.177707 rx_firspass[0][1][14] = 1
4132 11:33:07.178063 rx_lastpass[0][1][14] = 36
4133 11:33:07.180483 rx_firspass[0][1][15] = 3
4134 11:33:07.184109 rx_lastpass[0][1][15] = 38
4135 11:33:07.187511 rx_firspass[1][0][0] = 7
4136 11:33:07.187839 rx_lastpass[1][0][0] = 42
4137 11:33:07.190485 rx_firspass[1][0][1] = 7
4138 11:33:07.194078 rx_lastpass[1][0][1] = 39
4139 11:33:07.194431 rx_firspass[1][0][2] = 0
4140 11:33:07.197059 rx_lastpass[1][0][2] = 33
4141 11:33:07.200716 rx_firspass[1][0][3] = -1
4142 11:33:07.203915 rx_lastpass[1][0][3] = 32
4143 11:33:07.204331 rx_firspass[1][0][4] = 3
4144 11:33:07.207405 rx_lastpass[1][0][4] = 34
4145 11:33:07.210596 rx_firspass[1][0][5] = 8
4146 11:33:07.210986 rx_lastpass[1][0][5] = 40
4147 11:33:07.214233 rx_firspass[1][0][6] = 9
4148 11:33:07.217622 rx_lastpass[1][0][6] = 41
4149 11:33:07.218014 rx_firspass[1][0][7] = 4
4150 11:33:07.220862 rx_lastpass[1][0][7] = 34
4151 11:33:07.224692 rx_firspass[1][0][8] = 2
4152 11:33:07.225089 rx_lastpass[1][0][8] = 36
4153 11:33:07.227520 rx_firspass[1][0][9] = 3
4154 11:33:07.230664 rx_lastpass[1][0][9] = 36
4155 11:33:07.233956 rx_firspass[1][0][10] = 1
4156 11:33:07.234345 rx_lastpass[1][0][10] = 35
4157 11:33:07.237369 rx_firspass[1][0][11] = 3
4158 11:33:07.240621 rx_lastpass[1][0][11] = 36
4159 11:33:07.241007 rx_firspass[1][0][12] = 4
4160 11:33:07.244139 rx_lastpass[1][0][12] = 36
4161 11:33:07.247488 rx_firspass[1][0][13] = 4
4162 11:33:07.250840 rx_lastpass[1][0][13] = 34
4163 11:33:07.251230 rx_firspass[1][0][14] = 3
4164 11:33:07.254503 rx_lastpass[1][0][14] = 35
4165 11:33:07.257941 rx_firspass[1][0][15] = 0
4166 11:33:07.258303 rx_lastpass[1][0][15] = 33
4167 11:33:07.260802 rx_firspass[1][1][0] = 7
4168 11:33:07.264218 rx_lastpass[1][1][0] = 42
4169 11:33:07.267787 rx_firspass[1][1][1] = 5
4170 11:33:07.268208 rx_lastpass[1][1][1] = 40
4171 11:33:07.271051 rx_firspass[1][1][2] = 0
4172 11:33:07.274011 rx_lastpass[1][1][2] = 35
4173 11:33:07.274395 rx_firspass[1][1][3] = -2
4174 11:33:07.277259 rx_lastpass[1][1][3] = 33
4175 11:33:07.281081 rx_firspass[1][1][4] = 2
4176 11:33:07.281499 rx_lastpass[1][1][4] = 36
4177 11:33:07.284661 rx_firspass[1][1][5] = 5
4178 11:33:07.287665 rx_lastpass[1][1][5] = 41
4179 11:33:07.291063 rx_firspass[1][1][6] = 7
4180 11:33:07.291593 rx_lastpass[1][1][6] = 42
4181 11:33:07.294098 rx_firspass[1][1][7] = 1
4182 11:33:07.297327 rx_lastpass[1][1][7] = 36
4183 11:33:07.297709 rx_firspass[1][1][8] = 2
4184 11:33:07.300719 rx_lastpass[1][1][8] = 37
4185 11:33:07.304362 rx_firspass[1][1][9] = 2
4186 11:33:07.304836 rx_lastpass[1][1][9] = 37
4187 11:33:07.307240 rx_firspass[1][1][10] = 2
4188 11:33:07.310998 rx_lastpass[1][1][10] = 36
4189 11:33:07.314386 rx_firspass[1][1][11] = 3
4190 11:33:07.314864 rx_lastpass[1][1][11] = 38
4191 11:33:07.317382 rx_firspass[1][1][12] = 4
4192 11:33:07.320746 rx_lastpass[1][1][12] = 39
4193 11:33:07.323918 rx_firspass[1][1][13] = 3
4194 11:33:07.324384 rx_lastpass[1][1][13] = 36
4195 11:33:07.327984 rx_firspass[1][1][14] = 3
4196 11:33:07.330991 rx_lastpass[1][1][14] = 36
4197 11:33:07.331464 rx_firspass[1][1][15] = 0
4198 11:33:07.334174 rx_lastpass[1][1][15] = 34
4199 11:33:07.337505 dump params clk_delay
4200 11:33:07.338033 clk_delay[0] = -1
4201 11:33:07.340955 clk_delay[1] = 0
4202 11:33:07.341388 dump params dqs_delay
4203 11:33:07.344508 dqs_delay[0][0] = 0
4204 11:33:07.344896 dqs_delay[0][1] = -1
4205 11:33:07.347680 dqs_delay[1][0] = -1
4206 11:33:07.351146 dqs_delay[1][1] = 0
4207 11:33:07.351655 dump params delay_cell_unit = 762
4208 11:33:07.354500 dump source = 0x0
4209 11:33:07.357667 dump params frequency:1200
4210 11:33:07.358050 dump params rank number:2
4211 11:33:07.358346
4212 11:33:07.361288 dump params write leveling
4213 11:33:07.364312 write leveling[0][0][0] = 0x0
4214 11:33:07.367329 write leveling[0][0][1] = 0x0
4215 11:33:07.370655 write leveling[0][1][0] = 0x0
4216 11:33:07.370987 write leveling[0][1][1] = 0x0
4217 11:33:07.374314 write leveling[1][0][0] = 0x0
4218 11:33:07.377584 write leveling[1][0][1] = 0x0
4219 11:33:07.381019 write leveling[1][1][0] = 0x0
4220 11:33:07.384081 write leveling[1][1][1] = 0x0
4221 11:33:07.384462 dump params cbt_cs
4222 11:33:07.387527 cbt_cs[0][0] = 0x0
4223 11:33:07.387913 cbt_cs[0][1] = 0x0
4224 11:33:07.391185 cbt_cs[1][0] = 0x0
4225 11:33:07.391569 cbt_cs[1][1] = 0x0
4226 11:33:07.394191 dump params cbt_mr12
4227 11:33:07.394571 cbt_mr12[0][0] = 0x0
4228 11:33:07.397590 cbt_mr12[0][1] = 0x0
4229 11:33:07.397971 cbt_mr12[1][0] = 0x0
4230 11:33:07.400689 cbt_mr12[1][1] = 0x0
4231 11:33:07.404094 dump params tx window
4232 11:33:07.404481 tx_center_min[0][0][0] = 0
4233 11:33:07.407741 tx_center_max[0][0][0] = 0
4234 11:33:07.411062 tx_center_min[0][0][1] = 0
4235 11:33:07.413915 tx_center_max[0][0][1] = 0
4236 11:33:07.414304 tx_center_min[0][1][0] = 0
4237 11:33:07.417332 tx_center_max[0][1][0] = 0
4238 11:33:07.420522 tx_center_min[0][1][1] = 0
4239 11:33:07.424128 tx_center_max[0][1][1] = 0
4240 11:33:07.424514 tx_center_min[1][0][0] = 0
4241 11:33:07.427473 tx_center_max[1][0][0] = 0
4242 11:33:07.430725 tx_center_min[1][0][1] = 0
4243 11:33:07.431109 tx_center_max[1][0][1] = 0
4244 11:33:07.434193 tx_center_min[1][1][0] = 0
4245 11:33:07.437529 tx_center_max[1][1][0] = 0
4246 11:33:07.440738 tx_center_min[1][1][1] = 0
4247 11:33:07.441123 tx_center_max[1][1][1] = 0
4248 11:33:07.443924 dump params tx window
4249 11:33:07.447345 tx_win_center[0][0][0] = 0
4250 11:33:07.447791 tx_first_pass[0][0][0] = 0
4251 11:33:07.450824 tx_last_pass[0][0][0] = 0
4252 11:33:07.454038 tx_win_center[0][0][1] = 0
4253 11:33:07.457764 tx_first_pass[0][0][1] = 0
4254 11:33:07.458147 tx_last_pass[0][0][1] = 0
4255 11:33:07.461238 tx_win_center[0][0][2] = 0
4256 11:33:07.464367 tx_first_pass[0][0][2] = 0
4257 11:33:07.464751 tx_last_pass[0][0][2] = 0
4258 11:33:07.467831 tx_win_center[0][0][3] = 0
4259 11:33:07.471130 tx_first_pass[0][0][3] = 0
4260 11:33:07.474025 tx_last_pass[0][0][3] = 0
4261 11:33:07.474412 tx_win_center[0][0][4] = 0
4262 11:33:07.477542 tx_first_pass[0][0][4] = 0
4263 11:33:07.481008 tx_last_pass[0][0][4] = 0
4264 11:33:07.483953 tx_win_center[0][0][5] = 0
4265 11:33:07.484281 tx_first_pass[0][0][5] = 0
4266 11:33:07.487758 tx_last_pass[0][0][5] = 0
4267 11:33:07.491085 tx_win_center[0][0][6] = 0
4268 11:33:07.491421 tx_first_pass[0][0][6] = 0
4269 11:33:07.494325 tx_last_pass[0][0][6] = 0
4270 11:33:07.497356 tx_win_center[0][0][7] = 0
4271 11:33:07.500816 tx_first_pass[0][0][7] = 0
4272 11:33:07.501189 tx_last_pass[0][0][7] = 0
4273 11:33:07.504266 tx_win_center[0][0][8] = 0
4274 11:33:07.507297 tx_first_pass[0][0][8] = 0
4275 11:33:07.510974 tx_last_pass[0][0][8] = 0
4276 11:33:07.511397 tx_win_center[0][0][9] = 0
4277 11:33:07.514466 tx_first_pass[0][0][9] = 0
4278 11:33:07.517690 tx_last_pass[0][0][9] = 0
4279 11:33:07.518157 tx_win_center[0][0][10] = 0
4280 11:33:07.520879 tx_first_pass[0][0][10] = 0
4281 11:33:07.524381 tx_last_pass[0][0][10] = 0
4282 11:33:07.527440 tx_win_center[0][0][11] = 0
4283 11:33:07.527879 tx_first_pass[0][0][11] = 0
4284 11:33:07.530932 tx_last_pass[0][0][11] = 0
4285 11:33:07.534201 tx_win_center[0][0][12] = 0
4286 11:33:07.537447 tx_first_pass[0][0][12] = 0
4287 11:33:07.537859 tx_last_pass[0][0][12] = 0
4288 11:33:07.541045 tx_win_center[0][0][13] = 0
4289 11:33:07.544466 tx_first_pass[0][0][13] = 0
4290 11:33:07.547296 tx_last_pass[0][0][13] = 0
4291 11:33:07.547682 tx_win_center[0][0][14] = 0
4292 11:33:07.550927 tx_first_pass[0][0][14] = 0
4293 11:33:07.554297 tx_last_pass[0][0][14] = 0
4294 11:33:07.557435 tx_win_center[0][0][15] = 0
4295 11:33:07.557849 tx_first_pass[0][0][15] = 0
4296 11:33:07.560731 tx_last_pass[0][0][15] = 0
4297 11:33:07.564450 tx_win_center[0][1][0] = 0
4298 11:33:07.567701 tx_first_pass[0][1][0] = 0
4299 11:33:07.568086 tx_last_pass[0][1][0] = 0
4300 11:33:07.571439 tx_win_center[0][1][1] = 0
4301 11:33:07.574481 tx_first_pass[0][1][1] = 0
4302 11:33:07.574877 tx_last_pass[0][1][1] = 0
4303 11:33:07.577589 tx_win_center[0][1][2] = 0
4304 11:33:07.580964 tx_first_pass[0][1][2] = 0
4305 11:33:07.583985 tx_last_pass[0][1][2] = 0
4306 11:33:07.584470 tx_win_center[0][1][3] = 0
4307 11:33:07.587659 tx_first_pass[0][1][3] = 0
4308 11:33:07.590690 tx_last_pass[0][1][3] = 0
4309 11:33:07.594066 tx_win_center[0][1][4] = 0
4310 11:33:07.594542 tx_first_pass[0][1][4] = 0
4311 11:33:07.597552 tx_last_pass[0][1][4] = 0
4312 11:33:07.600600 tx_win_center[0][1][5] = 0
4313 11:33:07.604017 tx_first_pass[0][1][5] = 0
4314 11:33:07.604232 tx_last_pass[0][1][5] = 0
4315 11:33:07.607045 tx_win_center[0][1][6] = 0
4316 11:33:07.610298 tx_first_pass[0][1][6] = 0
4317 11:33:07.610464 tx_last_pass[0][1][6] = 0
4318 11:33:07.613583 tx_win_center[0][1][7] = 0
4319 11:33:07.617274 tx_first_pass[0][1][7] = 0
4320 11:33:07.620275 tx_last_pass[0][1][7] = 0
4321 11:33:07.620438 tx_win_center[0][1][8] = 0
4322 11:33:07.623676 tx_first_pass[0][1][8] = 0
4323 11:33:07.627247 tx_last_pass[0][1][8] = 0
4324 11:33:07.627411 tx_win_center[0][1][9] = 0
4325 11:33:07.630229 tx_first_pass[0][1][9] = 0
4326 11:33:07.633875 tx_last_pass[0][1][9] = 0
4327 11:33:07.637357 tx_win_center[0][1][10] = 0
4328 11:33:07.637526 tx_first_pass[0][1][10] = 0
4329 11:33:07.640469 tx_last_pass[0][1][10] = 0
4330 11:33:07.643831 tx_win_center[0][1][11] = 0
4331 11:33:07.647545 tx_first_pass[0][1][11] = 0
4332 11:33:07.647791 tx_last_pass[0][1][11] = 0
4333 11:33:07.650514 tx_win_center[0][1][12] = 0
4334 11:33:07.653767 tx_first_pass[0][1][12] = 0
4335 11:33:07.657406 tx_last_pass[0][1][12] = 0
4336 11:33:07.657787 tx_win_center[0][1][13] = 0
4337 11:33:07.660566 tx_first_pass[0][1][13] = 0
4338 11:33:07.664752 tx_last_pass[0][1][13] = 0
4339 11:33:07.667350 tx_win_center[0][1][14] = 0
4340 11:33:07.670616 tx_first_pass[0][1][14] = 0
4341 11:33:07.670997 tx_last_pass[0][1][14] = 0
4342 11:33:07.674261 tx_win_center[0][1][15] = 0
4343 11:33:07.677386 tx_first_pass[0][1][15] = 0
4344 11:33:07.677820 tx_last_pass[0][1][15] = 0
4345 11:33:07.680768 tx_win_center[1][0][0] = 0
4346 11:33:07.684067 tx_first_pass[1][0][0] = 0
4347 11:33:07.686755 tx_last_pass[1][0][0] = 0
4348 11:33:07.687157 tx_win_center[1][0][1] = 0
4349 11:33:07.690370 tx_first_pass[1][0][1] = 0
4350 11:33:07.693838 tx_last_pass[1][0][1] = 0
4351 11:33:07.697553 tx_win_center[1][0][2] = 0
4352 11:33:07.697937 tx_first_pass[1][0][2] = 0
4353 11:33:07.700392 tx_last_pass[1][0][2] = 0
4354 11:33:07.703373 tx_win_center[1][0][3] = 0
4355 11:33:07.706932 tx_first_pass[1][0][3] = 0
4356 11:33:07.707311 tx_last_pass[1][0][3] = 0
4357 11:33:07.709930 tx_win_center[1][0][4] = 0
4358 11:33:07.713399 tx_first_pass[1][0][4] = 0
4359 11:33:07.713870 tx_last_pass[1][0][4] = 0
4360 11:33:07.716842 tx_win_center[1][0][5] = 0
4361 11:33:07.720144 tx_first_pass[1][0][5] = 0
4362 11:33:07.723507 tx_last_pass[1][0][5] = 0
4363 11:33:07.723915 tx_win_center[1][0][6] = 0
4364 11:33:07.726585 tx_first_pass[1][0][6] = 0
4365 11:33:07.730032 tx_last_pass[1][0][6] = 0
4366 11:33:07.733500 tx_win_center[1][0][7] = 0
4367 11:33:07.733897 tx_first_pass[1][0][7] = 0
4368 11:33:07.736549 tx_last_pass[1][0][7] = 0
4369 11:33:07.740232 tx_win_center[1][0][8] = 0
4370 11:33:07.740617 tx_first_pass[1][0][8] = 0
4371 11:33:07.743172 tx_last_pass[1][0][8] = 0
4372 11:33:07.746450 tx_win_center[1][0][9] = 0
4373 11:33:07.750140 tx_first_pass[1][0][9] = 0
4374 11:33:07.750375 tx_last_pass[1][0][9] = 0
4375 11:33:07.752948 tx_win_center[1][0][10] = 0
4376 11:33:07.756542 tx_first_pass[1][0][10] = 0
4377 11:33:07.760089 tx_last_pass[1][0][10] = 0
4378 11:33:07.760253 tx_win_center[1][0][11] = 0
4379 11:33:07.762986 tx_first_pass[1][0][11] = 0
4380 11:33:07.766231 tx_last_pass[1][0][11] = 0
4381 11:33:07.769657 tx_win_center[1][0][12] = 0
4382 11:33:07.769787 tx_first_pass[1][0][12] = 0
4383 11:33:07.773172 tx_last_pass[1][0][12] = 0
4384 11:33:07.776361 tx_win_center[1][0][13] = 0
4385 11:33:07.779611 tx_first_pass[1][0][13] = 0
4386 11:33:07.779708 tx_last_pass[1][0][13] = 0
4387 11:33:07.783324 tx_win_center[1][0][14] = 0
4388 11:33:07.786157 tx_first_pass[1][0][14] = 0
4389 11:33:07.790223 tx_last_pass[1][0][14] = 0
4390 11:33:07.790300 tx_win_center[1][0][15] = 0
4391 11:33:07.793163 tx_first_pass[1][0][15] = 0
4392 11:33:07.796492 tx_last_pass[1][0][15] = 0
4393 11:33:07.799443 tx_win_center[1][1][0] = 0
4394 11:33:07.799520 tx_first_pass[1][1][0] = 0
4395 11:33:07.802803 tx_last_pass[1][1][0] = 0
4396 11:33:07.806334 tx_win_center[1][1][1] = 0
4397 11:33:07.806411 tx_first_pass[1][1][1] = 0
4398 11:33:07.809478 tx_last_pass[1][1][1] = 0
4399 11:33:07.812843 tx_win_center[1][1][2] = 0
4400 11:33:07.816281 tx_first_pass[1][1][2] = 0
4401 11:33:07.816365 tx_last_pass[1][1][2] = 0
4402 11:33:07.819609 tx_win_center[1][1][3] = 0
4403 11:33:07.823092 tx_first_pass[1][1][3] = 0
4404 11:33:07.826409 tx_last_pass[1][1][3] = 0
4405 11:33:07.826515 tx_win_center[1][1][4] = 0
4406 11:33:07.829856 tx_first_pass[1][1][4] = 0
4407 11:33:07.832975 tx_last_pass[1][1][4] = 0
4408 11:33:07.833144 tx_win_center[1][1][5] = 0
4409 11:33:07.836392 tx_first_pass[1][1][5] = 0
4410 11:33:07.839489 tx_last_pass[1][1][5] = 0
4411 11:33:07.842934 tx_win_center[1][1][6] = 0
4412 11:33:07.843079 tx_first_pass[1][1][6] = 0
4413 11:33:07.846055 tx_last_pass[1][1][6] = 0
4414 11:33:07.849362 tx_win_center[1][1][7] = 0
4415 11:33:07.853120 tx_first_pass[1][1][7] = 0
4416 11:33:07.853336 tx_last_pass[1][1][7] = 0
4417 11:33:07.856192 tx_win_center[1][1][8] = 0
4418 11:33:07.859776 tx_first_pass[1][1][8] = 0
4419 11:33:07.860011 tx_last_pass[1][1][8] = 0
4420 11:33:07.863046 tx_win_center[1][1][9] = 0
4421 11:33:07.867017 tx_first_pass[1][1][9] = 0
4422 11:33:07.869792 tx_last_pass[1][1][9] = 0
4423 11:33:07.870177 tx_win_center[1][1][10] = 0
4424 11:33:07.873099 tx_first_pass[1][1][10] = 0
4425 11:33:07.876418 tx_last_pass[1][1][10] = 0
4426 11:33:07.879889 tx_win_center[1][1][11] = 0
4427 11:33:07.880278 tx_first_pass[1][1][11] = 0
4428 11:33:07.883524 tx_last_pass[1][1][11] = 0
4429 11:33:07.886430 tx_win_center[1][1][12] = 0
4430 11:33:07.890149 tx_first_pass[1][1][12] = 0
4431 11:33:07.890535 tx_last_pass[1][1][12] = 0
4432 11:33:07.892975 tx_win_center[1][1][13] = 0
4433 11:33:07.896641 tx_first_pass[1][1][13] = 0
4434 11:33:07.899659 tx_last_pass[1][1][13] = 0
4435 11:33:07.900044 tx_win_center[1][1][14] = 0
4436 11:33:07.903450 tx_first_pass[1][1][14] = 0
4437 11:33:07.906746 tx_last_pass[1][1][14] = 0
4438 11:33:07.910060 tx_win_center[1][1][15] = 0
4439 11:33:07.910447 tx_first_pass[1][1][15] = 0
4440 11:33:07.913528 tx_last_pass[1][1][15] = 0
4441 11:33:07.916490 dump params rx window
4442 11:33:07.916873 rx_firspass[0][0][0] = 0
4443 11:33:07.919672 rx_lastpass[0][0][0] = 0
4444 11:33:07.923372 rx_firspass[0][0][1] = 0
4445 11:33:07.923755 rx_lastpass[0][0][1] = 0
4446 11:33:07.926487 rx_firspass[0][0][2] = 0
4447 11:33:07.929538 rx_lastpass[0][0][2] = 0
4448 11:33:07.930028 rx_firspass[0][0][3] = 0
4449 11:33:07.933012 rx_lastpass[0][0][3] = 0
4450 11:33:07.936534 rx_firspass[0][0][4] = 0
4451 11:33:07.939680 rx_lastpass[0][0][4] = 0
4452 11:33:07.940064 rx_firspass[0][0][5] = 0
4453 11:33:07.943381 rx_lastpass[0][0][5] = 0
4454 11:33:07.946277 rx_firspass[0][0][6] = 0
4455 11:33:07.946662 rx_lastpass[0][0][6] = 0
4456 11:33:07.949763 rx_firspass[0][0][7] = 0
4457 11:33:07.952952 rx_lastpass[0][0][7] = 0
4458 11:33:07.953387 rx_firspass[0][0][8] = 0
4459 11:33:07.956609 rx_lastpass[0][0][8] = 0
4460 11:33:07.960036 rx_firspass[0][0][9] = 0
4461 11:33:07.960422 rx_lastpass[0][0][9] = 0
4462 11:33:07.963212 rx_firspass[0][0][10] = 0
4463 11:33:07.966034 rx_lastpass[0][0][10] = 0
4464 11:33:07.969601 rx_firspass[0][0][11] = 0
4465 11:33:07.969988 rx_lastpass[0][0][11] = 0
4466 11:33:07.973111 rx_firspass[0][0][12] = 0
4467 11:33:07.976239 rx_lastpass[0][0][12] = 0
4468 11:33:07.976645 rx_firspass[0][0][13] = 0
4469 11:33:07.979738 rx_lastpass[0][0][13] = 0
4470 11:33:07.982967 rx_firspass[0][0][14] = 0
4471 11:33:07.986177 rx_lastpass[0][0][14] = 0
4472 11:33:07.986569 rx_firspass[0][0][15] = 0
4473 11:33:07.989624 rx_lastpass[0][0][15] = 0
4474 11:33:07.993104 rx_firspass[0][1][0] = 0
4475 11:33:07.993533 rx_lastpass[0][1][0] = 0
4476 11:33:07.996030 rx_firspass[0][1][1] = 0
4477 11:33:07.999680 rx_lastpass[0][1][1] = 0
4478 11:33:08.000074 rx_firspass[0][1][2] = 0
4479 11:33:08.002710 rx_lastpass[0][1][2] = 0
4480 11:33:08.006129 rx_firspass[0][1][3] = 0
4481 11:33:08.006532 rx_lastpass[0][1][3] = 0
4482 11:33:08.009713 rx_firspass[0][1][4] = 0
4483 11:33:08.013020 rx_lastpass[0][1][4] = 0
4484 11:33:08.016314 rx_firspass[0][1][5] = 0
4485 11:33:08.016707 rx_lastpass[0][1][5] = 0
4486 11:33:08.019671 rx_firspass[0][1][6] = 0
4487 11:33:08.022970 rx_lastpass[0][1][6] = 0
4488 11:33:08.023451 rx_firspass[0][1][7] = 0
4489 11:33:08.026050 rx_lastpass[0][1][7] = 0
4490 11:33:08.029542 rx_firspass[0][1][8] = 0
4491 11:33:08.029933 rx_lastpass[0][1][8] = 0
4492 11:33:08.032558 rx_firspass[0][1][9] = 0
4493 11:33:08.035934 rx_lastpass[0][1][9] = 0
4494 11:33:08.036328 rx_firspass[0][1][10] = 0
4495 11:33:08.039305 rx_lastpass[0][1][10] = 0
4496 11:33:08.042494 rx_firspass[0][1][11] = 0
4497 11:33:08.045943 rx_lastpass[0][1][11] = 0
4498 11:33:08.046355 rx_firspass[0][1][12] = 0
4499 11:33:08.049603 rx_lastpass[0][1][12] = 0
4500 11:33:08.052845 rx_firspass[0][1][13] = 0
4501 11:33:08.053272 rx_lastpass[0][1][13] = 0
4502 11:33:08.056180 rx_firspass[0][1][14] = 0
4503 11:33:08.059479 rx_lastpass[0][1][14] = 0
4504 11:33:08.062841 rx_firspass[0][1][15] = 0
4505 11:33:08.063232 rx_lastpass[0][1][15] = 0
4506 11:33:08.066480 rx_firspass[1][0][0] = 0
4507 11:33:08.069405 rx_lastpass[1][0][0] = 0
4508 11:33:08.069795 rx_firspass[1][0][1] = 0
4509 11:33:08.073033 rx_lastpass[1][0][1] = 0
4510 11:33:08.076725 rx_firspass[1][0][2] = 0
4511 11:33:08.077113 rx_lastpass[1][0][2] = 0
4512 11:33:08.079741 rx_firspass[1][0][3] = 0
4513 11:33:08.082879 rx_lastpass[1][0][3] = 0
4514 11:33:08.083313 rx_firspass[1][0][4] = 0
4515 11:33:08.086350 rx_lastpass[1][0][4] = 0
4516 11:33:08.089733 rx_firspass[1][0][5] = 0
4517 11:33:08.090124 rx_lastpass[1][0][5] = 0
4518 11:33:08.092966 rx_firspass[1][0][6] = 0
4519 11:33:08.096219 rx_lastpass[1][0][6] = 0
4520 11:33:08.099510 rx_firspass[1][0][7] = 0
4521 11:33:08.099903 rx_lastpass[1][0][7] = 0
4522 11:33:08.103085 rx_firspass[1][0][8] = 0
4523 11:33:08.106226 rx_lastpass[1][0][8] = 0
4524 11:33:08.106674 rx_firspass[1][0][9] = 0
4525 11:33:08.109699 rx_lastpass[1][0][9] = 0
4526 11:33:08.112766 rx_firspass[1][0][10] = 0
4527 11:33:08.113186 rx_lastpass[1][0][10] = 0
4528 11:33:08.115902 rx_firspass[1][0][11] = 0
4529 11:33:08.119438 rx_lastpass[1][0][11] = 0
4530 11:33:08.119831 rx_firspass[1][0][12] = 0
4531 11:33:08.122550 rx_lastpass[1][0][12] = 0
4532 11:33:08.126752 rx_firspass[1][0][13] = 0
4533 11:33:08.129869 rx_lastpass[1][0][13] = 0
4534 11:33:08.130297 rx_firspass[1][0][14] = 0
4535 11:33:08.132948 rx_lastpass[1][0][14] = 0
4536 11:33:08.136122 rx_firspass[1][0][15] = 0
4537 11:33:08.136509 rx_lastpass[1][0][15] = 0
4538 11:33:08.139637 rx_firspass[1][1][0] = 0
4539 11:33:08.142708 rx_lastpass[1][1][0] = 0
4540 11:33:08.146520 rx_firspass[1][1][1] = 0
4541 11:33:08.146899 rx_lastpass[1][1][1] = 0
4542 11:33:08.149319 rx_firspass[1][1][2] = 0
4543 11:33:08.153416 rx_lastpass[1][1][2] = 0
4544 11:33:08.153825 rx_firspass[1][1][3] = 0
4545 11:33:08.156318 rx_lastpass[1][1][3] = 0
4546 11:33:08.162245 rx_firspass[1][1][4] = 0
4547 11:33:08.162802 rx_lastpass[1][1][4] = 0
4548 11:33:08.163424 rx_firspass[1][1][5] = 0
4549 11:33:08.166106 rx_lastpass[1][1][5] = 0
4550 11:33:08.166491 rx_firspass[1][1][6] = 0
4551 11:33:08.169424 rx_lastpass[1][1][6] = 0
4552 11:33:08.172781 rx_firspass[1][1][7] = 0
4553 11:33:08.173342 rx_lastpass[1][1][7] = 0
4554 11:33:08.176185 rx_firspass[1][1][8] = 0
4555 11:33:08.179686 rx_lastpass[1][1][8] = 0
4556 11:33:08.180111 rx_firspass[1][1][9] = 0
4557 11:33:08.182688 rx_lastpass[1][1][9] = 0
4558 11:33:08.186244 rx_firspass[1][1][10] = 0
4559 11:33:08.189729 rx_lastpass[1][1][10] = 0
4560 11:33:08.190157 rx_firspass[1][1][11] = 0
4561 11:33:08.192745 rx_lastpass[1][1][11] = 0
4562 11:33:08.196380 rx_firspass[1][1][12] = 0
4563 11:33:08.196951 rx_lastpass[1][1][12] = 0
4564 11:33:08.199670 rx_firspass[1][1][13] = 0
4565 11:33:08.202420 rx_lastpass[1][1][13] = 0
4566 11:33:08.205855 rx_firspass[1][1][14] = 0
4567 11:33:08.206350 rx_lastpass[1][1][14] = 0
4568 11:33:08.209118 rx_firspass[1][1][15] = 0
4569 11:33:08.212568 rx_lastpass[1][1][15] = 0
4570 11:33:08.213120 dump params clk_delay
4571 11:33:08.215960 clk_delay[0] = 0
4572 11:33:08.216407 clk_delay[1] = 0
4573 11:33:08.219684 dump params dqs_delay
4574 11:33:08.220207 dqs_delay[0][0] = 0
4575 11:33:08.222563 dqs_delay[0][1] = 0
4576 11:33:08.222959 dqs_delay[1][0] = 0
4577 11:33:08.225826 dqs_delay[1][1] = 0
4578 11:33:08.229617 dump params delay_cell_unit = 762
4579 11:33:08.230021 dump source = 0x0
4580 11:33:08.232791 dump params frequency:800
4581 11:33:08.235764 dump params rank number:2
4582 11:33:08.236223
4583 11:33:08.239232 dump params write leveling
4584 11:33:08.239719 write leveling[0][0][0] = 0x0
4585 11:33:08.242743 write leveling[0][0][1] = 0x0
4586 11:33:08.247628 write leveling[0][1][0] = 0x0
4587 11:33:08.249232 write leveling[0][1][1] = 0x0
4588 11:33:08.252881 write leveling[1][0][0] = 0x0
4589 11:33:08.253472 write leveling[1][0][1] = 0x0
4590 11:33:08.256026 write leveling[1][1][0] = 0x0
4591 11:33:08.259215 write leveling[1][1][1] = 0x0
4592 11:33:08.262787 dump params cbt_cs
4593 11:33:08.263267 cbt_cs[0][0] = 0x0
4594 11:33:08.265991 cbt_cs[0][1] = 0x0
4595 11:33:08.266418 cbt_cs[1][0] = 0x0
4596 11:33:08.269233 cbt_cs[1][1] = 0x0
4597 11:33:08.269814 dump params cbt_mr12
4598 11:33:08.272969 cbt_mr12[0][0] = 0x0
4599 11:33:08.273419 cbt_mr12[0][1] = 0x0
4600 11:33:08.276170 cbt_mr12[1][0] = 0x0
4601 11:33:08.276587 cbt_mr12[1][1] = 0x0
4602 11:33:08.279772 dump params tx window
4603 11:33:08.282710 tx_center_min[0][0][0] = 0
4604 11:33:08.283131 tx_center_max[0][0][0] = 0
4605 11:33:08.286178 tx_center_min[0][0][1] = 0
4606 11:33:08.289251 tx_center_max[0][0][1] = 0
4607 11:33:08.292664 tx_center_min[0][1][0] = 0
4608 11:33:08.293252 tx_center_max[0][1][0] = 0
4609 11:33:08.296166 tx_center_min[0][1][1] = 0
4610 11:33:08.299404 tx_center_max[0][1][1] = 0
4611 11:33:08.302789 tx_center_min[1][0][0] = 0
4612 11:33:08.303174 tx_center_max[1][0][0] = 0
4613 11:33:08.306337 tx_center_min[1][0][1] = 0
4614 11:33:08.309800 tx_center_max[1][0][1] = 0
4615 11:33:08.312673 tx_center_min[1][1][0] = 0
4616 11:33:08.313239 tx_center_max[1][1][0] = 0
4617 11:33:08.316097 tx_center_min[1][1][1] = 0
4618 11:33:08.319279 tx_center_max[1][1][1] = 0
4619 11:33:08.319824 dump params tx window
4620 11:33:08.323194 tx_win_center[0][0][0] = 0
4621 11:33:08.326110 tx_first_pass[0][0][0] = 0
4622 11:33:08.329695 tx_last_pass[0][0][0] = 0
4623 11:33:08.330145 tx_win_center[0][0][1] = 0
4624 11:33:08.332663 tx_first_pass[0][0][1] = 0
4625 11:33:08.335829 tx_last_pass[0][0][1] = 0
4626 11:33:08.336379 tx_win_center[0][0][2] = 0
4627 11:33:08.339521 tx_first_pass[0][0][2] = 0
4628 11:33:08.342927 tx_last_pass[0][0][2] = 0
4629 11:33:08.346130 tx_win_center[0][0][3] = 0
4630 11:33:08.346611 tx_first_pass[0][0][3] = 0
4631 11:33:08.349733 tx_last_pass[0][0][3] = 0
4632 11:33:08.352324 tx_win_center[0][0][4] = 0
4633 11:33:08.355693 tx_first_pass[0][0][4] = 0
4634 11:33:08.355794 tx_last_pass[0][0][4] = 0
4635 11:33:08.358961 tx_win_center[0][0][5] = 0
4636 11:33:08.362243 tx_first_pass[0][0][5] = 0
4637 11:33:08.362313 tx_last_pass[0][0][5] = 0
4638 11:33:08.365676 tx_win_center[0][0][6] = 0
4639 11:33:08.368875 tx_first_pass[0][0][6] = 0
4640 11:33:08.372464 tx_last_pass[0][0][6] = 0
4641 11:33:08.372536 tx_win_center[0][0][7] = 0
4642 11:33:08.375570 tx_first_pass[0][0][7] = 0
4643 11:33:08.379042 tx_last_pass[0][0][7] = 0
4644 11:33:08.379115 tx_win_center[0][0][8] = 0
4645 11:33:08.382380 tx_first_pass[0][0][8] = 0
4646 11:33:08.385579 tx_last_pass[0][0][8] = 0
4647 11:33:08.389365 tx_win_center[0][0][9] = 0
4648 11:33:08.389431 tx_first_pass[0][0][9] = 0
4649 11:33:08.392377 tx_last_pass[0][0][9] = 0
4650 11:33:08.396034 tx_win_center[0][0][10] = 0
4651 11:33:08.399008 tx_first_pass[0][0][10] = 0
4652 11:33:08.399074 tx_last_pass[0][0][10] = 0
4653 11:33:08.402251 tx_win_center[0][0][11] = 0
4654 11:33:08.405542 tx_first_pass[0][0][11] = 0
4655 11:33:08.409043 tx_last_pass[0][0][11] = 0
4656 11:33:08.409118 tx_win_center[0][0][12] = 0
4657 11:33:08.412650 tx_first_pass[0][0][12] = 0
4658 11:33:08.415674 tx_last_pass[0][0][12] = 0
4659 11:33:08.419174 tx_win_center[0][0][13] = 0
4660 11:33:08.419249 tx_first_pass[0][0][13] = 0
4661 11:33:08.422687 tx_last_pass[0][0][13] = 0
4662 11:33:08.425839 tx_win_center[0][0][14] = 0
4663 11:33:08.429290 tx_first_pass[0][0][14] = 0
4664 11:33:08.429365 tx_last_pass[0][0][14] = 0
4665 11:33:08.432841 tx_win_center[0][0][15] = 0
4666 11:33:08.435811 tx_first_pass[0][0][15] = 0
4667 11:33:08.439327 tx_last_pass[0][0][15] = 0
4668 11:33:08.439402 tx_win_center[0][1][0] = 0
4669 11:33:08.442881 tx_first_pass[0][1][0] = 0
4670 11:33:08.445759 tx_last_pass[0][1][0] = 0
4671 11:33:08.445834 tx_win_center[0][1][1] = 0
4672 11:33:08.449454 tx_first_pass[0][1][1] = 0
4673 11:33:08.452870 tx_last_pass[0][1][1] = 0
4674 11:33:08.455770 tx_win_center[0][1][2] = 0
4675 11:33:08.455841 tx_first_pass[0][1][2] = 0
4676 11:33:08.459370 tx_last_pass[0][1][2] = 0
4677 11:33:08.462596 tx_win_center[0][1][3] = 0
4678 11:33:08.466125 tx_first_pass[0][1][3] = 0
4679 11:33:08.466195 tx_last_pass[0][1][3] = 0
4680 11:33:08.469578 tx_win_center[0][1][4] = 0
4681 11:33:08.472480 tx_first_pass[0][1][4] = 0
4682 11:33:08.472555 tx_last_pass[0][1][4] = 0
4683 11:33:08.475559 tx_win_center[0][1][5] = 0
4684 11:33:08.479025 tx_first_pass[0][1][5] = 0
4685 11:33:08.482533 tx_last_pass[0][1][5] = 0
4686 11:33:08.482607 tx_win_center[0][1][6] = 0
4687 11:33:08.485675 tx_first_pass[0][1][6] = 0
4688 11:33:08.489299 tx_last_pass[0][1][6] = 0
4689 11:33:08.489374 tx_win_center[0][1][7] = 0
4690 11:33:08.492741 tx_first_pass[0][1][7] = 0
4691 11:33:08.495884 tx_last_pass[0][1][7] = 0
4692 11:33:08.498965 tx_win_center[0][1][8] = 0
4693 11:33:08.499040 tx_first_pass[0][1][8] = 0
4694 11:33:08.503127 tx_last_pass[0][1][8] = 0
4695 11:33:08.505819 tx_win_center[0][1][9] = 0
4696 11:33:08.509402 tx_first_pass[0][1][9] = 0
4697 11:33:08.509477 tx_last_pass[0][1][9] = 0
4698 11:33:08.512443 tx_win_center[0][1][10] = 0
4699 11:33:08.515848 tx_first_pass[0][1][10] = 0
4700 11:33:08.515937 tx_last_pass[0][1][10] = 0
4701 11:33:08.519357 tx_win_center[0][1][11] = 0
4702 11:33:08.522852 tx_first_pass[0][1][11] = 0
4703 11:33:08.526264 tx_last_pass[0][1][11] = 0
4704 11:33:08.528969 tx_win_center[0][1][12] = 0
4705 11:33:08.529044 tx_first_pass[0][1][12] = 0
4706 11:33:08.532475 tx_last_pass[0][1][12] = 0
4707 11:33:08.535733 tx_win_center[0][1][13] = 0
4708 11:33:08.539336 tx_first_pass[0][1][13] = 0
4709 11:33:08.539411 tx_last_pass[0][1][13] = 0
4710 11:33:08.542274 tx_win_center[0][1][14] = 0
4711 11:33:08.545833 tx_first_pass[0][1][14] = 0
4712 11:33:08.549183 tx_last_pass[0][1][14] = 0
4713 11:33:08.549273 tx_win_center[0][1][15] = 0
4714 11:33:08.552231 tx_first_pass[0][1][15] = 0
4715 11:33:08.555783 tx_last_pass[0][1][15] = 0
4716 11:33:08.559215 tx_win_center[1][0][0] = 0
4717 11:33:08.559291 tx_first_pass[1][0][0] = 0
4718 11:33:08.562303 tx_last_pass[1][0][0] = 0
4719 11:33:08.565585 tx_win_center[1][0][1] = 0
4720 11:33:08.565676 tx_first_pass[1][0][1] = 0
4721 11:33:08.569025 tx_last_pass[1][0][1] = 0
4722 11:33:08.572170 tx_win_center[1][0][2] = 0
4723 11:33:08.575425 tx_first_pass[1][0][2] = 0
4724 11:33:08.575500 tx_last_pass[1][0][2] = 0
4725 11:33:08.578833 tx_win_center[1][0][3] = 0
4726 11:33:08.582434 tx_first_pass[1][0][3] = 0
4727 11:33:08.585840 tx_last_pass[1][0][3] = 0
4728 11:33:08.585915 tx_win_center[1][0][4] = 0
4729 11:33:08.588672 tx_first_pass[1][0][4] = 0
4730 11:33:08.592257 tx_last_pass[1][0][4] = 0
4731 11:33:08.592332 tx_win_center[1][0][5] = 0
4732 11:33:08.595300 tx_first_pass[1][0][5] = 0
4733 11:33:08.598886 tx_last_pass[1][0][5] = 0
4734 11:33:08.602032 tx_win_center[1][0][6] = 0
4735 11:33:08.602107 tx_first_pass[1][0][6] = 0
4736 11:33:08.605262 tx_last_pass[1][0][6] = 0
4737 11:33:08.608731 tx_win_center[1][0][7] = 0
4738 11:33:08.611878 tx_first_pass[1][0][7] = 0
4739 11:33:08.611968 tx_last_pass[1][0][7] = 0
4740 11:33:08.615149 tx_win_center[1][0][8] = 0
4741 11:33:08.618967 tx_first_pass[1][0][8] = 0
4742 11:33:08.619035 tx_last_pass[1][0][8] = 0
4743 11:33:08.621844 tx_win_center[1][0][9] = 0
4744 11:33:08.625418 tx_first_pass[1][0][9] = 0
4745 11:33:08.628855 tx_last_pass[1][0][9] = 0
4746 11:33:08.628945 tx_win_center[1][0][10] = 0
4747 11:33:08.631878 tx_first_pass[1][0][10] = 0
4748 11:33:08.635356 tx_last_pass[1][0][10] = 0
4749 11:33:08.638901 tx_win_center[1][0][11] = 0
4750 11:33:08.638967 tx_first_pass[1][0][11] = 0
4751 11:33:08.642026 tx_last_pass[1][0][11] = 0
4752 11:33:08.645477 tx_win_center[1][0][12] = 0
4753 11:33:08.649052 tx_first_pass[1][0][12] = 0
4754 11:33:08.649178 tx_last_pass[1][0][12] = 0
4755 11:33:08.651935 tx_win_center[1][0][13] = 0
4756 11:33:08.655402 tx_first_pass[1][0][13] = 0
4757 11:33:08.658872 tx_last_pass[1][0][13] = 0
4758 11:33:08.658963 tx_win_center[1][0][14] = 0
4759 11:33:08.662230 tx_first_pass[1][0][14] = 0
4760 11:33:08.665326 tx_last_pass[1][0][14] = 0
4761 11:33:08.668892 tx_win_center[1][0][15] = 0
4762 11:33:08.668967 tx_first_pass[1][0][15] = 0
4763 11:33:08.672462 tx_last_pass[1][0][15] = 0
4764 11:33:08.675633 tx_win_center[1][1][0] = 0
4765 11:33:08.678898 tx_first_pass[1][1][0] = 0
4766 11:33:08.678974 tx_last_pass[1][1][0] = 0
4767 11:33:08.681933 tx_win_center[1][1][1] = 0
4768 11:33:08.685399 tx_first_pass[1][1][1] = 0
4769 11:33:08.685516 tx_last_pass[1][1][1] = 0
4770 11:33:08.688976 tx_win_center[1][1][2] = 0
4771 11:33:08.691688 tx_first_pass[1][1][2] = 0
4772 11:33:08.695321 tx_last_pass[1][1][2] = 0
4773 11:33:08.695392 tx_win_center[1][1][3] = 0
4774 11:33:08.699048 tx_first_pass[1][1][3] = 0
4775 11:33:08.702092 tx_last_pass[1][1][3] = 0
4776 11:33:08.702166 tx_win_center[1][1][4] = 0
4777 11:33:08.705307 tx_first_pass[1][1][4] = 0
4778 11:33:08.708419 tx_last_pass[1][1][4] = 0
4779 11:33:08.712140 tx_win_center[1][1][5] = 0
4780 11:33:08.712209 tx_first_pass[1][1][5] = 0
4781 11:33:08.715684 tx_last_pass[1][1][5] = 0
4782 11:33:08.718834 tx_win_center[1][1][6] = 0
4783 11:33:08.721926 tx_first_pass[1][1][6] = 0
4784 11:33:08.721993 tx_last_pass[1][1][6] = 0
4785 11:33:08.725554 tx_win_center[1][1][7] = 0
4786 11:33:08.728895 tx_first_pass[1][1][7] = 0
4787 11:33:08.728961 tx_last_pass[1][1][7] = 0
4788 11:33:08.732183 tx_win_center[1][1][8] = 0
4789 11:33:08.735638 tx_first_pass[1][1][8] = 0
4790 11:33:08.739177 tx_last_pass[1][1][8] = 0
4791 11:33:08.739255 tx_win_center[1][1][9] = 0
4792 11:33:08.742242 tx_first_pass[1][1][9] = 0
4793 11:33:08.745717 tx_last_pass[1][1][9] = 0
4794 11:33:08.748918 tx_win_center[1][1][10] = 0
4795 11:33:08.749018 tx_first_pass[1][1][10] = 0
4796 11:33:08.752433 tx_last_pass[1][1][10] = 0
4797 11:33:08.755643 tx_win_center[1][1][11] = 0
4798 11:33:08.758580 tx_first_pass[1][1][11] = 0
4799 11:33:08.758665 tx_last_pass[1][1][11] = 0
4800 11:33:08.762477 tx_win_center[1][1][12] = 0
4801 11:33:08.765184 tx_first_pass[1][1][12] = 0
4802 11:33:08.768507 tx_last_pass[1][1][12] = 0
4803 11:33:08.768590 tx_win_center[1][1][13] = 0
4804 11:33:08.772514 tx_first_pass[1][1][13] = 0
4805 11:33:08.775500 tx_last_pass[1][1][13] = 0
4806 11:33:08.779110 tx_win_center[1][1][14] = 0
4807 11:33:08.779178 tx_first_pass[1][1][14] = 0
4808 11:33:08.782017 tx_last_pass[1][1][14] = 0
4809 11:33:08.785546 tx_win_center[1][1][15] = 0
4810 11:33:08.788534 tx_first_pass[1][1][15] = 0
4811 11:33:08.788605 tx_last_pass[1][1][15] = 0
4812 11:33:08.792217 dump params rx window
4813 11:33:08.795179 rx_firspass[0][0][0] = 0
4814 11:33:08.795247 rx_lastpass[0][0][0] = 0
4815 11:33:08.798588 rx_firspass[0][0][1] = 0
4816 11:33:08.802331 rx_lastpass[0][0][1] = 0
4817 11:33:08.802400 rx_firspass[0][0][2] = 0
4818 11:33:08.805301 rx_lastpass[0][0][2] = 0
4819 11:33:08.809008 rx_firspass[0][0][3] = 0
4820 11:33:08.809107 rx_lastpass[0][0][3] = 0
4821 11:33:08.811820 rx_firspass[0][0][4] = 0
4822 11:33:08.815253 rx_lastpass[0][0][4] = 0
4823 11:33:08.815321 rx_firspass[0][0][5] = 0
4824 11:33:08.818724 rx_lastpass[0][0][5] = 0
4825 11:33:08.822367 rx_firspass[0][0][6] = 0
4826 11:33:08.822436 rx_lastpass[0][0][6] = 0
4827 11:33:08.825237 rx_firspass[0][0][7] = 0
4828 11:33:08.828512 rx_lastpass[0][0][7] = 0
4829 11:33:08.831865 rx_firspass[0][0][8] = 0
4830 11:33:08.831932 rx_lastpass[0][0][8] = 0
4831 11:33:08.835613 rx_firspass[0][0][9] = 0
4832 11:33:08.839024 rx_lastpass[0][0][9] = 0
4833 11:33:08.839094 rx_firspass[0][0][10] = 0
4834 11:33:08.842406 rx_lastpass[0][0][10] = 0
4835 11:33:08.845294 rx_firspass[0][0][11] = 0
4836 11:33:08.845396 rx_lastpass[0][0][11] = 0
4837 11:33:08.849003 rx_firspass[0][0][12] = 0
4838 11:33:08.852024 rx_lastpass[0][0][12] = 0
4839 11:33:08.856005 rx_firspass[0][0][13] = 0
4840 11:33:08.856109 rx_lastpass[0][0][13] = 0
4841 11:33:08.858896 rx_firspass[0][0][14] = 0
4842 11:33:08.862230 rx_lastpass[0][0][14] = 0
4843 11:33:08.862306 rx_firspass[0][0][15] = 0
4844 11:33:08.865588 rx_lastpass[0][0][15] = 0
4845 11:33:08.869026 rx_firspass[0][1][0] = 0
4846 11:33:08.869141 rx_lastpass[0][1][0] = 0
4847 11:33:08.872320 rx_firspass[0][1][1] = 0
4848 11:33:08.875362 rx_lastpass[0][1][1] = 0
4849 11:33:08.875439 rx_firspass[0][1][2] = 0
4850 11:33:08.879147 rx_lastpass[0][1][2] = 0
4851 11:33:08.882544 rx_firspass[0][1][3] = 0
4852 11:33:08.885567 rx_lastpass[0][1][3] = 0
4853 11:33:08.885643 rx_firspass[0][1][4] = 0
4854 11:33:08.888990 rx_lastpass[0][1][4] = 0
4855 11:33:08.892389 rx_firspass[0][1][5] = 0
4856 11:33:08.892484 rx_lastpass[0][1][5] = 0
4857 11:33:08.895244 rx_firspass[0][1][6] = 0
4858 11:33:08.898711 rx_lastpass[0][1][6] = 0
4859 11:33:08.898795 rx_firspass[0][1][7] = 0
4860 11:33:08.902099 rx_lastpass[0][1][7] = 0
4861 11:33:08.905710 rx_firspass[0][1][8] = 0
4862 11:33:08.905785 rx_lastpass[0][1][8] = 0
4863 11:33:08.909025 rx_firspass[0][1][9] = 0
4864 11:33:08.912429 rx_lastpass[0][1][9] = 0
4865 11:33:08.912507 rx_firspass[0][1][10] = 0
4866 11:33:08.915515 rx_lastpass[0][1][10] = 0
4867 11:33:08.918670 rx_firspass[0][1][11] = 0
4868 11:33:08.922314 rx_lastpass[0][1][11] = 0
4869 11:33:08.922389 rx_firspass[0][1][12] = 0
4870 11:33:08.925526 rx_lastpass[0][1][12] = 0
4871 11:33:08.929085 rx_firspass[0][1][13] = 0
4872 11:33:08.929194 rx_lastpass[0][1][13] = 0
4873 11:33:08.932074 rx_firspass[0][1][14] = 0
4874 11:33:08.935283 rx_lastpass[0][1][14] = 0
4875 11:33:08.938781 rx_firspass[0][1][15] = 0
4876 11:33:08.938856 rx_lastpass[0][1][15] = 0
4877 11:33:08.941869 rx_firspass[1][0][0] = 0
4878 11:33:08.945282 rx_lastpass[1][0][0] = 0
4879 11:33:08.945370 rx_firspass[1][0][1] = 0
4880 11:33:08.948566 rx_lastpass[1][0][1] = 0
4881 11:33:08.952212 rx_firspass[1][0][2] = 0
4882 11:33:08.952296 rx_lastpass[1][0][2] = 0
4883 11:33:08.955832 rx_firspass[1][0][3] = 0
4884 11:33:08.958569 rx_lastpass[1][0][3] = 0
4885 11:33:08.958682 rx_firspass[1][0][4] = 0
4886 11:33:08.962502 rx_lastpass[1][0][4] = 0
4887 11:33:08.965400 rx_firspass[1][0][5] = 0
4888 11:33:08.968991 rx_lastpass[1][0][5] = 0
4889 11:33:08.969067 rx_firspass[1][0][6] = 0
4890 11:33:08.971877 rx_lastpass[1][0][6] = 0
4891 11:33:08.975698 rx_firspass[1][0][7] = 0
4892 11:33:08.975773 rx_lastpass[1][0][7] = 0
4893 11:33:08.979217 rx_firspass[1][0][8] = 0
4894 11:33:08.982231 rx_lastpass[1][0][8] = 0
4895 11:33:08.982305 rx_firspass[1][0][9] = 0
4896 11:33:08.985684 rx_lastpass[1][0][9] = 0
4897 11:33:08.988426 rx_firspass[1][0][10] = 0
4898 11:33:08.988500 rx_lastpass[1][0][10] = 0
4899 11:33:08.992241 rx_firspass[1][0][11] = 0
4900 11:33:08.995122 rx_lastpass[1][0][11] = 0
4901 11:33:08.999037 rx_firspass[1][0][12] = 0
4902 11:33:08.999112 rx_lastpass[1][0][12] = 0
4903 11:33:09.002245 rx_firspass[1][0][13] = 0
4904 11:33:09.005091 rx_lastpass[1][0][13] = 0
4905 11:33:09.005189 rx_firspass[1][0][14] = 0
4906 11:33:09.008767 rx_lastpass[1][0][14] = 0
4907 11:33:09.011747 rx_firspass[1][0][15] = 0
4908 11:33:09.015526 rx_lastpass[1][0][15] = 0
4909 11:33:09.015601 rx_firspass[1][1][0] = 0
4910 11:33:09.018826 rx_lastpass[1][1][0] = 0
4911 11:33:09.022485 rx_firspass[1][1][1] = 0
4912 11:33:09.022591 rx_lastpass[1][1][1] = 0
4913 11:33:09.025084 rx_firspass[1][1][2] = 0
4914 11:33:09.028998 rx_lastpass[1][1][2] = 0
4915 11:33:09.029072 rx_firspass[1][1][3] = 0
4916 11:33:09.032156 rx_lastpass[1][1][3] = 0
4917 11:33:09.035686 rx_firspass[1][1][4] = 0
4918 11:33:09.035761 rx_lastpass[1][1][4] = 0
4919 11:33:09.038584 rx_firspass[1][1][5] = 0
4920 11:33:09.042262 rx_lastpass[1][1][5] = 0
4921 11:33:09.042337 rx_firspass[1][1][6] = 0
4922 11:33:09.045183 rx_lastpass[1][1][6] = 0
4923 11:33:09.048758 rx_firspass[1][1][7] = 0
4924 11:33:09.051834 rx_lastpass[1][1][7] = 0
4925 11:33:09.051910 rx_firspass[1][1][8] = 0
4926 11:33:09.055161 rx_lastpass[1][1][8] = 0
4927 11:33:09.058613 rx_firspass[1][1][9] = 0
4928 11:33:09.058687 rx_lastpass[1][1][9] = 0
4929 11:33:09.062175 rx_firspass[1][1][10] = 0
4930 11:33:09.065422 rx_lastpass[1][1][10] = 0
4931 11:33:09.065496 rx_firspass[1][1][11] = 0
4932 11:33:09.068909 rx_lastpass[1][1][11] = 0
4933 11:33:09.071930 rx_firspass[1][1][12] = 0
4934 11:33:09.075590 rx_lastpass[1][1][12] = 0
4935 11:33:09.075664 rx_firspass[1][1][13] = 0
4936 11:33:09.079027 rx_lastpass[1][1][13] = 0
4937 11:33:09.081935 rx_firspass[1][1][14] = 0
4938 11:33:09.082009 rx_lastpass[1][1][14] = 0
4939 11:33:09.085292 rx_firspass[1][1][15] = 0
4940 11:33:09.088978 rx_lastpass[1][1][15] = 0
4941 11:33:09.089053 dump params clk_delay
4942 11:33:09.091950 clk_delay[0] = 0
4943 11:33:09.092033 clk_delay[1] = 0
4944 11:33:09.095325 dump params dqs_delay
4945 11:33:09.098347 dqs_delay[0][0] = 0
4946 11:33:09.098421 dqs_delay[0][1] = 0
4947 11:33:09.102085 dqs_delay[1][0] = 0
4948 11:33:09.102181 dqs_delay[1][1] = 0
4949 11:33:09.105326 dump params delay_cell_unit = 762
4950 11:33:09.108651 mt_set_emi_preloader end
4951 11:33:09.111758 [mt_mem_init] dram size: 0x100000000, rank number: 2
4952 11:33:09.118326 [complex_mem_test] start addr:0x40000000, len:20480
4953 11:33:09.153627 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
4954 11:33:09.160234 [complex_mem_test] start addr:0x80000000, len:20480
4955 11:33:09.195862 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
4956 11:33:09.202567 [complex_mem_test] start addr:0xc0000000, len:20480
4957 11:33:09.238198 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
4958 11:33:09.244810 [complex_mem_test] start addr:0x56000000, len:8192
4959 11:33:09.261424 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
4960 11:33:09.261505 ddr_geometry:1
4961 11:33:09.267977 [complex_mem_test] start addr:0x80000000, len:8192
4962 11:33:09.285613 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
4963 11:33:09.288798 dram_init: dram init end (result: 0)
4964 11:33:09.295168 Successfully loaded DRAM blobs and ran DRAM calibration
4965 11:33:09.304946 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
4966 11:33:09.305028 CBMEM:
4967 11:33:09.308444 IMD: root @ 00000000fffff000 254 entries.
4968 11:33:09.312138 IMD: root @ 00000000ffffec00 62 entries.
4969 11:33:09.318963 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
4970 11:33:09.325161 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
4971 11:33:09.328290 in-header: 03 a1 00 00 08 00 00 00
4972 11:33:09.331642 in-data: 84 60 60 10 00 00 00 00
4973 11:33:09.335344 Chrome EC: clear events_b mask to 0x0000000020004000
4974 11:33:09.342041 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
4975 11:33:09.345731 in-header: 03 fd 00 00 00 00 00 00
4976 11:33:09.345827 in-data:
4977 11:33:09.352053 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
4978 11:33:09.352125 CBFS @ 21000 size 3d4000
4979 11:33:09.358641 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
4980 11:33:09.362019 CBFS: Locating 'fallback/ramstage'
4981 11:33:09.365670 CBFS: Found @ offset 10d40 size d563
4982 11:33:09.387070 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
4983 11:33:09.399369 Accumulated console time in romstage 12860 ms
4984 11:33:09.399448
4985 11:33:09.399539
4986 11:33:09.409307 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
4987 11:33:09.412695 ARM64: Exception handlers installed.
4988 11:33:09.412769 ARM64: Testing exception
4989 11:33:09.415760 ARM64: Done test exception
4990 11:33:09.419473 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
4991 11:33:09.422880 Manufacturer: ef
4992 11:33:09.425744 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
4993 11:33:09.432325 WARNING: RO_VPD is uninitialized or empty.
4994 11:33:09.435971 FMAP: area RW_VPD found @ 550000 (16384 bytes)
4995 11:33:09.438804 FMAP: area RW_VPD found @ 550000 (16384 bytes)
4996 11:33:09.449092 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
4997 11:33:09.452410 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
4998 11:33:09.458938 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
4999 11:33:09.459013 Enumerating buses...
5000 11:33:09.465855 Show all devs... Before device enumeration.
5001 11:33:09.465930 Root Device: enabled 1
5002 11:33:09.468830 CPU_CLUSTER: 0: enabled 1
5003 11:33:09.468905 CPU: 00: enabled 1
5004 11:33:09.472007 Compare with tree...
5005 11:33:09.475653 Root Device: enabled 1
5006 11:33:09.475777 CPU_CLUSTER: 0: enabled 1
5007 11:33:09.478678 CPU: 00: enabled 1
5008 11:33:09.482171 Root Device scanning...
5009 11:33:09.482245 root_dev_scan_bus for Root Device
5010 11:33:09.485672 CPU_CLUSTER: 0 enabled
5011 11:33:09.489328 root_dev_scan_bus for Root Device done
5012 11:33:09.495711 scan_bus: scanning of bus Root Device took 10690 usecs
5013 11:33:09.495786 done
5014 11:33:09.499121 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5015 11:33:09.502498 Allocating resources...
5016 11:33:09.502573 Reading resources...
5017 11:33:09.505553 Root Device read_resources bus 0 link: 0
5018 11:33:09.512277 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5019 11:33:09.512380 CPU: 00 missing read_resources
5020 11:33:09.518653 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5021 11:33:09.522236 Root Device read_resources bus 0 link: 0 done
5022 11:33:09.525705 Done reading resources.
5023 11:33:09.529094 Show resources in subtree (Root Device)...After reading.
5024 11:33:09.532702 Root Device child on link 0 CPU_CLUSTER: 0
5025 11:33:09.535598 CPU_CLUSTER: 0 child on link 0 CPU: 00
5026 11:33:09.545525 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5027 11:33:09.545657 CPU: 00
5028 11:33:09.549228 Setting resources...
5029 11:33:09.552452 Root Device assign_resources, bus 0 link: 0
5030 11:33:09.555557 CPU_CLUSTER: 0 missing set_resources
5031 11:33:09.559008 Root Device assign_resources, bus 0 link: 0
5032 11:33:09.562470 Done setting resources.
5033 11:33:09.565448 Show resources in subtree (Root Device)...After assigning values.
5034 11:33:09.572293 Root Device child on link 0 CPU_CLUSTER: 0
5035 11:33:09.575775 CPU_CLUSTER: 0 child on link 0 CPU: 00
5036 11:33:09.582230 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5037 11:33:09.585378 CPU: 00
5038 11:33:09.585477 Done allocating resources.
5039 11:33:09.592597 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5040 11:33:09.592694 Enabling resources...
5041 11:33:09.595569 done.
5042 11:33:09.598898 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5043 11:33:09.602561 Initializing devices...
5044 11:33:09.602638 Root Device init ...
5045 11:33:09.605561 mainboard_init: Starting display init.
5046 11:33:09.609066 ADC[4]: Raw value=76494 ID=0
5047 11:33:09.631766 anx7625_power_on_init: Init interface.
5048 11:33:09.635069 anx7625_disable_pd_protocol: Disabled PD feature.
5049 11:33:09.641793 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5050 11:33:09.688561 anx7625_start_dp_work: Secure OCM version=00
5051 11:33:09.691381 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5052 11:33:09.709166 sp_tx_get_edid_block: EDID Block = 1
5053 11:33:09.825939 Extracted contents:
5054 11:33:09.829143 header: 00 ff ff ff ff ff ff 00
5055 11:33:09.832684 serial number: 06 af 5c 14 00 00 00 00 00 1a
5056 11:33:09.836164 version: 01 04
5057 11:33:09.839186 basic params: 95 1a 0e 78 02
5058 11:33:09.842692 chroma info: 99 85 95 55 56 92 28 22 50 54
5059 11:33:09.846177 established: 00 00 00
5060 11:33:09.852944 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5061 11:33:09.856274 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5062 11:33:09.862936 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5063 11:33:09.869608 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5064 11:33:09.875993 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5065 11:33:09.879256 extensions: 00
5066 11:33:09.879331 checksum: ae
5067 11:33:09.879389
5068 11:33:09.882346 Manufacturer: AUO Model 145c Serial Number 0
5069 11:33:09.885899 Made week 0 of 2016
5070 11:33:09.885974 EDID version: 1.4
5071 11:33:09.889066 Digital display
5072 11:33:09.892178 6 bits per primary color channel
5073 11:33:09.892250 DisplayPort interface
5074 11:33:09.895866 Maximum image size: 26 cm x 14 cm
5075 11:33:09.898909 Gamma: 220%
5076 11:33:09.898983 Check DPMS levels
5077 11:33:09.902178 Supported color formats: RGB 4:4:4
5078 11:33:09.906312 First detailed timing is preferred timing
5079 11:33:09.908994 Established timings supported:
5080 11:33:09.912581 Standard timings supported:
5081 11:33:09.912649 Detailed timings
5082 11:33:09.919338 Hex of detail: ce1d56ea50001a3030204600009010000018
5083 11:33:09.922543 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5084 11:33:09.925939 0556 0586 05a6 0640 hborder 0
5085 11:33:09.929202 0300 0304 030a 031a vborder 0
5086 11:33:09.932518 -hsync -vsync
5087 11:33:09.936089 Did detailed timing
5088 11:33:09.939407 Hex of detail: 0000000f0000000000000000000000000020
5089 11:33:09.942546 Manufacturer-specified data, tag 15
5090 11:33:09.946098 Hex of detail: 000000fe0041554f0a202020202020202020
5091 11:33:09.949252 ASCII string: AUO
5092 11:33:09.952279 Hex of detail: 000000fe004231313658414230312e34200a
5093 11:33:09.955764 ASCII string: B116XAB01.4
5094 11:33:09.955839 Checksum
5095 11:33:09.959171 Checksum: 0xae (valid)
5096 11:33:09.965574 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5097 11:33:09.965650 DSI data_rate: 457800000 bps
5098 11:33:09.972926 anx7625_parse_edid: set default k value to 0x3d for panel
5099 11:33:09.976452 anx7625_parse_edid: pixelclock(76300).
5100 11:33:09.979315 hactive(1366), hsync(32), hfp(48), hbp(154)
5101 11:33:09.983156 vactive(768), vsync(6), vfp(4), vbp(16)
5102 11:33:09.985932 anx7625_dsi_config: config dsi.
5103 11:33:09.993986 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5104 11:33:10.015216 anx7625_dsi_config: success to config DSI
5105 11:33:10.018843 anx7625_dp_start: MIPI phy setup OK.
5106 11:33:10.021976 [SSUSB] Setting up USB HOST controller...
5107 11:33:10.025161 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5108 11:33:10.028349 [SSUSB] phy power-on done.
5109 11:33:10.032568 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5110 11:33:10.035653 in-header: 03 fc 01 00 00 00 00 00
5111 11:33:10.035759 in-data:
5112 11:33:10.042187 handle_proto3_response: EC response with error code: 1
5113 11:33:10.042263 SPM: pcm index = 1
5114 11:33:10.045689 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5115 11:33:10.049147 CBFS @ 21000 size 3d4000
5116 11:33:10.055798 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5117 11:33:10.058843 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5118 11:33:10.061910 CBFS: Found @ offset 1e7c0 size 1026
5119 11:33:10.069041 read SPI 0x3f808 0x1026: 1272 us, 3250 KB/s, 26.000 Mbps
5120 11:33:10.072448 SPM: binary array size = 2988
5121 11:33:10.075268 SPM: version = pcm_allinone_v1.17.2_20180829
5122 11:33:10.078983 SPM binary loaded in 32 msecs
5123 11:33:10.086654 spm_kick_im_to_fetch: ptr = 000000004021eec2
5124 11:33:10.089737 spm_kick_im_to_fetch: len = 2988
5125 11:33:10.089813 SPM: spm_kick_pcm_to_run
5126 11:33:10.093167 SPM: spm_kick_pcm_to_run done
5127 11:33:10.096210 SPM: spm_init done in 52 msecs
5128 11:33:10.100101 Root Device init finished in 494994 usecs
5129 11:33:10.103000 CPU_CLUSTER: 0 init ...
5130 11:33:10.112925 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5131 11:33:10.116673 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5132 11:33:10.119599 CBFS @ 21000 size 3d4000
5133 11:33:10.122976 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5134 11:33:10.126065 CBFS: Locating 'sspm.bin'
5135 11:33:10.129834 CBFS: Found @ offset 208c0 size 41cb
5136 11:33:10.139779 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5137 11:33:10.147896 CPU_CLUSTER: 0 init finished in 42799 usecs
5138 11:33:10.147971 Devices initialized
5139 11:33:10.150852 Show all devs... After init.
5140 11:33:10.154196 Root Device: enabled 1
5141 11:33:10.154267 CPU_CLUSTER: 0: enabled 1
5142 11:33:10.157354 CPU: 00: enabled 1
5143 11:33:10.160952 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5144 11:33:10.164171 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5145 11:33:10.167379 ELOG: NV offset 0x558000 size 0x1000
5146 11:33:10.175343 read SPI 0x558000 0x1000: 1263 us, 3243 KB/s, 25.944 Mbps
5147 11:33:10.181809 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5148 11:33:10.184807 ELOG: Event(17) added with size 13 at 2024-07-17 11:33:09 UTC
5149 11:33:10.188921 out: cmd=0x121: 03 db 21 01 00 00 00 00
5150 11:33:10.191849 in-header: 03 7a 00 00 2c 00 00 00
5151 11:33:10.204992 in-data: 3a 48 00 00 00 00 00 00 02 10 00 00 06 80 00 00 4c 00 02 00 06 80 00 00 ae 1e 0e 00 06 80 00 00 cf c7 07 00 06 80 00 00 18 99 35 00
5152 11:33:10.208658 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5153 11:33:10.211680 in-header: 03 19 00 00 08 00 00 00
5154 11:33:10.215267 in-data: a2 e0 47 00 13 00 00 00
5155 11:33:10.218506 Chrome EC: UHEPI supported
5156 11:33:10.225279 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5157 11:33:10.228295 in-header: 03 e1 00 00 08 00 00 00
5158 11:33:10.231704 in-data: 84 20 60 10 00 00 00 00
5159 11:33:10.235149 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5160 11:33:10.241516 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5161 11:33:10.245237 in-header: 03 e1 00 00 08 00 00 00
5162 11:33:10.248043 in-data: 84 20 60 10 00 00 00 00
5163 11:33:10.255191 ELOG: Event(A1) added with size 10 at 2024-07-17 11:33:09 UTC
5164 11:33:10.261855 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5165 11:33:10.265202 ELOG: Event(A0) added with size 9 at 2024-07-17 11:33:10 UTC
5166 11:33:10.271584 elog_add_boot_reason: Logged dev mode boot
5167 11:33:10.271659 Finalize devices...
5168 11:33:10.274884 Devices finalized
5169 11:33:10.278496 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5170 11:33:10.281806 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5171 11:33:10.288426 ELOG: Event(91) added with size 10 at 2024-07-17 11:33:10 UTC
5172 11:33:10.291637 Writing coreboot table at 0xffeda000
5173 11:33:10.295286 0. 0000000000114000-000000000011efff: RAMSTAGE
5174 11:33:10.301625 1. 0000000040000000-000000004023cfff: RAMSTAGE
5175 11:33:10.305053 2. 000000004023d000-00000000545fffff: RAM
5176 11:33:10.308353 3. 0000000054600000-000000005465ffff: BL31
5177 11:33:10.311989 4. 0000000054660000-00000000ffed9fff: RAM
5178 11:33:10.318476 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5179 11:33:10.321910 6. 0000000100000000-000000013fffffff: RAM
5180 11:33:10.321980 Passing 5 GPIOs to payload:
5181 11:33:10.328530 NAME | PORT | POLARITY | VALUE
5182 11:33:10.331774 write protect | 0x00000096 | low | high
5183 11:33:10.338832 EC in RW | 0x000000b1 | high | undefined
5184 11:33:10.341959 EC interrupt | 0x00000097 | low | undefined
5185 11:33:10.345187 TPM interrupt | 0x00000099 | high | undefined
5186 11:33:10.351641 speaker enable | 0x000000af | high | undefined
5187 11:33:10.355297 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5188 11:33:10.358633 in-header: 03 f7 00 00 02 00 00 00
5189 11:33:10.358706 in-data: 04 00
5190 11:33:10.362260 Board ID: 4
5191 11:33:10.362327 ADC[3]: Raw value=1034629 ID=8
5192 11:33:10.364982 RAM code: 8
5193 11:33:10.365047 SKU ID: 16
5194 11:33:10.368713 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5195 11:33:10.372349 CBFS @ 21000 size 3d4000
5196 11:33:10.378314 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5197 11:33:10.385431 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 3ae3
5198 11:33:10.385502 coreboot table: 940 bytes.
5199 11:33:10.388558 IMD ROOT 0. 00000000fffff000 00001000
5200 11:33:10.391953 IMD SMALL 1. 00000000ffffe000 00001000
5201 11:33:10.398251 CONSOLE 2. 00000000fffde000 00020000
5202 11:33:10.401487 FMAP 3. 00000000fffdd000 0000047c
5203 11:33:10.405284 TIME STAMP 4. 00000000fffdc000 00000910
5204 11:33:10.408198 RAMOOPS 5. 00000000ffedc000 00100000
5205 11:33:10.411798 COREBOOT 6. 00000000ffeda000 00002000
5206 11:33:10.411879 IMD small region:
5207 11:33:10.418168 IMD ROOT 0. 00000000ffffec00 00000400
5208 11:33:10.421561 VBOOT WORK 1. 00000000ffffeb00 00000100
5209 11:33:10.424806 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5210 11:33:10.428356 VPD 3. 00000000ffffea60 0000006c
5211 11:33:10.432311 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5212 11:33:10.438389 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5213 11:33:10.441721 in-header: 03 e1 00 00 08 00 00 00
5214 11:33:10.445077 in-data: 84 20 60 10 00 00 00 00
5215 11:33:10.451704 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5216 11:33:10.451777 CBFS @ 21000 size 3d4000
5217 11:33:10.458188 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5218 11:33:10.461727 CBFS: Locating 'fallback/payload'
5219 11:33:10.469403 CBFS: Found @ offset dc040 size 439a0
5220 11:33:10.557373 read SPI 0xfd078 0x439a0: 84380 us, 3281 KB/s, 26.248 Mbps
5221 11:33:10.560747 Checking segment from ROM address 0x0000000040003a00
5222 11:33:10.566987 Checking segment from ROM address 0x0000000040003a1c
5223 11:33:10.570271 Loading segment from ROM address 0x0000000040003a00
5224 11:33:10.573556 code (compression=0)
5225 11:33:10.583980 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5226 11:33:10.590349 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5227 11:33:10.593935 it's not compressed!
5228 11:33:10.596783 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5229 11:33:10.603516 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5230 11:33:10.611141 Loading segment from ROM address 0x0000000040003a1c
5231 11:33:10.614818 Entry Point 0x0000000080000000
5232 11:33:10.614887 Loaded segments
5233 11:33:10.621461 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5234 11:33:10.624960 Jumping to boot code at 0000000080000000(00000000ffeda000)
5235 11:33:10.634500 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5236 11:33:10.637790 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5237 11:33:10.641099 CBFS @ 21000 size 3d4000
5238 11:33:10.648279 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5239 11:33:10.651725 CBFS: Locating 'fallback/bl31'
5240 11:33:10.654344 CBFS: Found @ offset 36dc0 size 5820
5241 11:33:10.665397 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5242 11:33:10.668609 Checking segment from ROM address 0x0000000040003a00
5243 11:33:10.674968 Checking segment from ROM address 0x0000000040003a1c
5244 11:33:10.678436 Loading segment from ROM address 0x0000000040003a00
5245 11:33:10.682053 code (compression=1)
5246 11:33:10.688749 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5247 11:33:10.698508 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5248 11:33:10.698593 using LZMA
5249 11:33:10.707160 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5250 11:33:10.714260 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5251 11:33:10.717328 Loading segment from ROM address 0x0000000040003a1c
5252 11:33:10.720960 Entry Point 0x0000000054601000
5253 11:33:10.721052 Loaded segments
5254 11:33:10.723997 NOTICE: MT8183 bl31_setup
5255 11:33:10.731079 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5256 11:33:10.734307 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5257 11:33:10.737346 INFO: [DEVAPC] dump DEVAPC registers:
5258 11:33:10.747695 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5259 11:33:10.754144 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5260 11:33:10.764759 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5261 11:33:10.770876 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5262 11:33:10.780889 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5263 11:33:10.787362 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5264 11:33:10.797384 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5265 11:33:10.804086 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5266 11:33:10.811022 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5267 11:33:10.820908 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5268 11:33:10.827846 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5269 11:33:10.837300 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5270 11:33:10.844465 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5271 11:33:10.850722 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5272 11:33:10.860673 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5273 11:33:10.867160 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5274 11:33:10.874101 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5275 11:33:10.880997 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5276 11:33:10.887496 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5277 11:33:10.897350 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5278 11:33:10.904280 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5279 11:33:10.910862 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5280 11:33:10.914222 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5281 11:33:10.917347 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5282 11:33:10.920859 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5283 11:33:10.924372 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5284 11:33:10.927478 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5285 11:33:10.934420 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5286 11:33:10.937176 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5287 11:33:10.940609 WARNING: region 0:
5288 11:33:10.944000 WARNING: apc:0x168, sa:0x0, ea:0xfff
5289 11:33:10.944113 WARNING: region 1:
5290 11:33:10.950601 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5291 11:33:10.950690 WARNING: region 2:
5292 11:33:10.954023 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5293 11:33:10.957287 WARNING: region 3:
5294 11:33:10.960556 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5295 11:33:10.960662 WARNING: region 4:
5296 11:33:10.964316 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5297 11:33:10.967030 WARNING: region 5:
5298 11:33:10.970825 WARNING: apc:0x0, sa:0x0, ea:0x0
5299 11:33:10.970894 WARNING: region 6:
5300 11:33:10.974021 WARNING: apc:0x0, sa:0x0, ea:0x0
5301 11:33:10.977316 WARNING: region 7:
5302 11:33:10.980723 WARNING: apc:0x0, sa:0x0, ea:0x0
5303 11:33:10.987078 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5304 11:33:10.990232 INFO: SPM: enable SPMC mode
5305 11:33:10.993746 NOTICE: spm_boot_init() start
5306 11:33:10.993827 NOTICE: spm_boot_init() end
5307 11:33:11.000295 INFO: BL31: Initializing runtime services
5308 11:33:11.003549 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5309 11:33:11.010413 INFO: BL31: Preparing for EL3 exit to normal world
5310 11:33:11.013475 INFO: Entry point address = 0x80000000
5311 11:33:11.013552 INFO: SPSR = 0x8
5312 11:33:11.037438
5313 11:33:11.037518
5314 11:33:11.037576
5315 11:33:11.037630 Starting depthcharge on Juniper...
5316 11:33:11.038083 end: 2.2.3 depthcharge-start (duration 00:00:22) [common]
5317 11:33:11.038183 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5318 11:33:11.038256 Setting prompt string to ['jacuzzi:']
5319 11:33:11.038319 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5320 11:33:11.040440
5321 11:33:11.043782 vboot_handoff: creating legacy vboot_handoff structure
5322 11:33:11.043848
5323 11:33:11.047081 ec_init(0): CrosEC protocol v3 supported (544, 544)
5324 11:33:11.047151
5325 11:33:11.050536 Wipe memory regions:
5326 11:33:11.050601
5327 11:33:11.054066 [0x00000040000000, 0x00000054600000)
5328 11:33:11.096587
5329 11:33:11.096665 [0x00000054660000, 0x00000080000000)
5330 11:33:11.188267
5331 11:33:11.188383 [0x000000811994a0, 0x000000ffeda000)
5332 11:33:11.447945
5333 11:33:11.448059 [0x00000100000000, 0x00000140000000)
5334 11:33:11.580346
5335 11:33:11.583899 Initializing XHCI USB controller at 0x11200000.
5336 11:33:11.607318
5337 11:33:11.610224 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5338 11:33:11.610324
5339 11:33:11.610413
5340 11:33:11.610720 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5341 11:33:11.610816 Sending line: 'tftpboot 192.168.201.1 14864604/tftp-deploy-5u8il0ve/kernel/image.itb 14864604/tftp-deploy-5u8il0ve/kernel/cmdline '
5343 11:33:11.711214 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5344 11:33:11.711298 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:28)
5345 11:33:11.716146 jacuzzi: tftpboot 192.168.201.1 14864604/tftp-deploy-5u8il0ve/kernel/image.itbtp-deploy-5u8il0ve/kernel/cmdline
5346 11:33:11.716244
5347 11:33:11.716338 Waiting for link
5348 11:33:12.120846
5349 11:33:12.120979 R8152: Initializing
5350 11:33:12.121071
5351 11:33:12.124028 Version 9 (ocp_data = 6010)
5352 11:33:12.124112
5353 11:33:12.127232 R8152: Done initializing
5354 11:33:12.127299
5355 11:33:12.127357 Adding net device
5356 11:33:12.512987
5357 11:33:12.513118 done.
5358 11:33:12.513203
5359 11:33:12.513260 MAC: 00:e0:4c:71:a7:1f
5360 11:33:12.513314
5361 11:33:12.516342 Sending DHCP discover... done.
5362 11:33:12.516464
5363 11:33:12.519581 Waiting for reply... done.
5364 11:33:12.519659
5365 11:33:12.522899 Sending DHCP request... done.
5366 11:33:12.522970
5367 11:33:12.523030 Waiting for reply... done.
5368 11:33:12.523085
5369 11:33:12.526289 My ip is 192.168.201.23
5370 11:33:12.526362
5371 11:33:12.529645 The DHCP server ip is 192.168.201.1
5372 11:33:12.529714
5373 11:33:12.532949 TFTP server IP predefined by user: 192.168.201.1
5374 11:33:12.533054
5375 11:33:12.539522 Bootfile predefined by user: 14864604/tftp-deploy-5u8il0ve/kernel/image.itb
5376 11:33:12.539601
5377 11:33:12.542668 Sending tftp read request... done.
5378 11:33:12.542769
5379 11:33:12.546087 Waiting for the transfer...
5380 11:33:12.546168
5381 11:33:12.803382 00000000 ################################################################
5382 11:33:12.803498
5383 11:33:13.055859 00080000 ################################################################
5384 11:33:13.055975
5385 11:33:13.307326 00100000 ################################################################
5386 11:33:13.307438
5387 11:33:13.562128 00180000 ################################################################
5388 11:33:13.562246
5389 11:33:13.819562 00200000 ################################################################
5390 11:33:13.819683
5391 11:33:14.077899 00280000 ################################################################
5392 11:33:14.078012
5393 11:33:14.327862 00300000 ################################################################
5394 11:33:14.328029
5395 11:33:14.579158 00380000 ################################################################
5396 11:33:14.579275
5397 11:33:14.833822 00400000 ################################################################
5398 11:33:14.833949
5399 11:33:15.089226 00480000 ################################################################
5400 11:33:15.089343
5401 11:33:15.344167 00500000 ################################################################
5402 11:33:15.344283
5403 11:33:15.597072 00580000 ################################################################
5404 11:33:15.597211
5405 11:33:15.850054 00600000 ################################################################
5406 11:33:15.850169
5407 11:33:16.100648 00680000 ################################################################
5408 11:33:16.100775
5409 11:33:16.355832 00700000 ################################################################
5410 11:33:16.355972
5411 11:33:16.611278 00780000 ################################################################
5412 11:33:16.611394
5413 11:33:16.862760 00800000 ################################################################
5414 11:33:16.862877
5415 11:33:17.117388 00880000 ################################################################
5416 11:33:17.117516
5417 11:33:17.370983 00900000 ################################################################
5418 11:33:17.371103
5419 11:33:17.625043 00980000 ################################################################
5420 11:33:17.625193
5421 11:33:17.882102 00a00000 ################################################################
5422 11:33:17.882238
5423 11:33:18.143751 00a80000 ################################################################
5424 11:33:18.143858
5425 11:33:18.398893 00b00000 ################################################################
5426 11:33:18.399005
5427 11:33:18.650782 00b80000 ################################################################
5428 11:33:18.650893
5429 11:33:18.912534 00c00000 ################################################################
5430 11:33:18.912669
5431 11:33:19.167562 00c80000 ################################################################
5432 11:33:19.167675
5433 11:33:19.423916 00d00000 ################################################################
5434 11:33:19.424033
5435 11:33:19.672821 00d80000 ################################################################
5436 11:33:19.672931
5437 11:33:19.924057 00e00000 ################################################################
5438 11:33:19.924195
5439 11:33:20.182230 00e80000 ################################################################
5440 11:33:20.182352
5441 11:33:20.435035 00f00000 ################################################################
5442 11:33:20.435176
5443 11:33:20.693037 00f80000 ################################################################
5444 11:33:20.693156
5445 11:33:20.945076 01000000 ################################################################
5446 11:33:20.945213
5447 11:33:21.198738 01080000 ################################################################
5448 11:33:21.198879
5449 11:33:21.453481 01100000 ################################################################
5450 11:33:21.453619
5451 11:33:21.708350 01180000 ################################################################
5452 11:33:21.708494
5453 11:33:21.965919 01200000 ################################################################
5454 11:33:21.966041
5455 11:33:22.220676 01280000 ################################################################
5456 11:33:22.220803
5457 11:33:22.481502 01300000 ################################################################
5458 11:33:22.481620
5459 11:33:22.738311 01380000 ################################################################
5460 11:33:22.738427
5461 11:33:22.993994 01400000 ################################################################
5462 11:33:22.994139
5463 11:33:23.247000 01480000 ################################################################
5464 11:33:23.247113
5465 11:33:23.502168 01500000 ################################################################
5466 11:33:23.502305
5467 11:33:23.759269 01580000 ################################################################
5468 11:33:23.759390
5469 11:33:24.012001 01600000 ################################################################
5470 11:33:24.012114
5471 11:33:24.278697 01680000 ################################################################
5472 11:33:24.278813
5473 11:33:24.541886 01700000 ################################################################
5474 11:33:24.542005
5475 11:33:24.802068 01780000 ################################################################
5476 11:33:24.802203
5477 11:33:25.058040 01800000 ################################################################
5478 11:33:25.058149
5479 11:33:25.312984 01880000 ################################################################
5480 11:33:25.313119
5481 11:33:25.587133 01900000 ################################################################
5482 11:33:25.587246
5483 11:33:25.866141 01980000 ################################################################
5484 11:33:25.866255
5485 11:33:26.139754 01a00000 ################################################################
5486 11:33:26.139868
5487 11:33:26.421047 01a80000 ################################################################
5488 11:33:26.421190
5489 11:33:26.680795 01b00000 ################################################################
5490 11:33:26.680908
5491 11:33:26.940839 01b80000 ################################################################
5492 11:33:26.940953
5493 11:33:27.202417 01c00000 ################################################################
5494 11:33:27.202532
5495 11:33:27.465350 01c80000 ################################################################
5496 11:33:27.465463
5497 11:33:27.757866 01d00000 ################################################################
5498 11:33:27.757980
5499 11:33:28.020763 01d80000 ################################################################
5500 11:33:28.020881
5501 11:33:28.283275 01e00000 ################################################################
5502 11:33:28.283422
5503 11:33:28.540000 01e80000 ################################################################
5504 11:33:28.540133
5505 11:33:28.806231 01f00000 ################################################################
5506 11:33:28.806347
5507 11:33:29.072695 01f80000 ################################################################
5508 11:33:29.072810
5509 11:33:29.351759 02000000 ################################################################
5510 11:33:29.351872
5511 11:33:29.596418 02080000 ######################################################## done.
5512 11:33:29.596534
5513 11:33:29.599902 The bootfile was 34533958 bytes long.
5514 11:33:29.599980
5515 11:33:29.603669 Sending tftp read request... done.
5516 11:33:29.603747
5517 11:33:29.606461 Waiting for the transfer...
5518 11:33:29.606537
5519 11:33:29.610102 00000000 # done.
5520 11:33:29.610179
5521 11:33:29.616951 Command line loaded dynamically from TFTP file: 14864604/tftp-deploy-5u8il0ve/kernel/cmdline
5522 11:33:29.617028
5523 11:33:29.633317 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5524 11:33:29.633400
5525 11:33:29.636544 Loading FIT.
5526 11:33:29.636623
5527 11:33:29.636681 Image ramdisk-1 has 21355925 bytes.
5528 11:33:29.639872
5529 11:33:29.639939 Image fdt-1 has 57695 bytes.
5530 11:33:29.639995
5531 11:33:29.642946 Image kernel-1 has 13118294 bytes.
5532 11:33:29.643017
5533 11:33:29.652978 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5534 11:33:29.653104
5535 11:33:29.663282 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5536 11:33:29.663354
5537 11:33:29.670110 Choosing best match conf-1 for compat google,juniper-sku16.
5538 11:33:29.674018
5539 11:33:29.679093 Connected to device vid:did:rid of 1ae0:0028:00
5540 11:33:29.686714
5541 11:33:29.690446 tpm_get_response: command 0x17b, return code 0x0
5542 11:33:29.690514
5543 11:33:29.693368 tpm_cleanup: add release locality here.
5544 11:33:29.693438
5545 11:33:29.696836 Shutting down all USB controllers.
5546 11:33:29.696901
5547 11:33:29.700600 Removing current net device
5548 11:33:29.700664
5549 11:33:29.703473 Exiting depthcharge with code 4 at timestamp: 35078705
5550 11:33:29.703552
5551 11:33:29.707144 LZMA decompressing kernel-1 to 0x80193568
5552 11:33:29.707230
5553 11:33:29.713926 LZMA decompressing kernel-1 to 0x40000000
5554 11:33:31.576264
5555 11:33:31.576739 jumping to kernel
5556 11:33:31.578427 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5557 11:33:31.578886 start: 2.2.5 auto-login-action (timeout 00:04:08) [common]
5558 11:33:31.579258 Setting prompt string to ['Linux version [0-9]']
5559 11:33:31.579576 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5560 11:33:31.579959 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5561 11:33:31.650853
5562 11:33:31.654273 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5563 11:33:31.657747 start: 2.2.5.1 login-action (timeout 00:04:08) [common]
5564 11:33:31.657841 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5565 11:33:31.657916 Setting prompt string to []
5566 11:33:31.657992 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5567 11:33:31.658055 Using line separator: #'\n'#
5568 11:33:31.658107 No login prompt set.
5569 11:33:31.658162 Parsing kernel messages
5570 11:33:31.658213 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5571 11:33:31.658306 [login-action] Waiting for messages, (timeout 00:04:08)
5572 11:33:31.658366 Waiting using forced prompt support (timeout 00:02:04)
5573 11:33:31.677123 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
5574 11:33:31.680496 [ 0.000000] random: crng init done
5575 11:33:31.683713 [ 0.000000] Machine model: Google juniper sku16 board
5576 11:33:31.687140 [ 0.000000] efi: UEFI not found.
5577 11:33:31.697109 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5578 11:33:31.703736 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5579 11:33:31.710109 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5580 11:33:31.716990 [ 0.000000] printk: bootconsole [mtk8250] enabled
5581 11:33:31.725116 [ 0.000000] NUMA: No NUMA configuration found
5582 11:33:31.731356 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5583 11:33:31.738613 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5584 11:33:31.738682 [ 0.000000] Zone ranges:
5585 11:33:31.744610 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5586 11:33:31.747909 [ 0.000000] DMA32 empty
5587 11:33:31.754893 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5588 11:33:31.758088 [ 0.000000] Movable zone start for each node
5589 11:33:31.761134 [ 0.000000] Early memory node ranges
5590 11:33:31.767899 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5591 11:33:31.774618 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5592 11:33:31.781244 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5593 11:33:31.787852 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5594 11:33:31.794850 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5595 11:33:31.801342 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5596 11:33:31.821053 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5597 11:33:31.828070 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5598 11:33:31.834526 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5599 11:33:31.837941 [ 0.000000] psci: probing for conduit method from DT.
5600 11:33:31.844433 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5601 11:33:31.848139 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5602 11:33:31.854643 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5603 11:33:31.858152 [ 0.000000] psci: SMC Calling Convention v1.1
5604 11:33:31.864847 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5605 11:33:31.867856 [ 0.000000] Detected VIPT I-cache on CPU0
5606 11:33:31.874847 [ 0.000000] CPU features: detected: GIC system register CPU interface
5607 11:33:31.881868 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5608 11:33:31.888036 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5609 11:33:31.891264 [ 0.000000] CPU features: detected: ARM erratum 845719
5610 11:33:31.898082 [ 0.000000] alternatives: applying boot alternatives
5611 11:33:31.901290 [ 0.000000] Fallback order for Node 0: 0
5612 11:33:31.908116 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5613 11:33:31.911321 [ 0.000000] Policy zone: Normal
5614 11:33:31.931417 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5615 11:33:31.944506 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5616 11:33:31.951075 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5617 11:33:31.961414 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5618 11:33:31.968062 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5619 11:33:31.971182 <6>[ 0.000000] software IO TLB: area num 8.
5620 11:33:31.996870 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5621 11:33:32.055095 <6>[ 0.000000] Memory: 3894220K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 264244K reserved, 32768K cma-reserved)
5622 11:33:32.061544 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5623 11:33:32.068320 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5624 11:33:32.071942 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5625 11:33:32.078082 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5626 11:33:32.084870 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5627 11:33:32.088417 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5628 11:33:32.098294 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5629 11:33:32.104803 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5630 11:33:32.108427 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5631 11:33:32.119851 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5632 11:33:32.126633 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5633 11:33:32.130256 <6>[ 0.000000] GICv3: 640 SPIs implemented
5634 11:33:32.133624 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5635 11:33:32.136844 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5636 11:33:32.143878 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5637 11:33:32.149905 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5638 11:33:32.160345 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5639 11:33:32.173408 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5640 11:33:32.180581 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5641 11:33:32.191737 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5642 11:33:32.205020 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5643 11:33:32.212130 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5644 11:33:32.218459 <6>[ 0.009471] Console: colour dummy device 80x25
5645 11:33:32.222235 <6>[ 0.014507] printk: console [tty1] enabled
5646 11:33:32.231832 <6>[ 0.018900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5647 11:33:32.238975 <6>[ 0.029364] pid_max: default: 32768 minimum: 301
5648 11:33:32.242011 <6>[ 0.034244] LSM: Security Framework initializing
5649 11:33:32.252036 <6>[ 0.039159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5650 11:33:32.258626 <6>[ 0.046781] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5651 11:33:32.264940 <4>[ 0.055661] cacheinfo: Unable to detect cache hierarchy for CPU 0
5652 11:33:32.275434 <6>[ 0.062290] cblist_init_generic: Setting adjustable number of callback queues.
5653 11:33:32.281784 <6>[ 0.069736] cblist_init_generic: Setting shift to 3 and lim to 1.
5654 11:33:32.288475 <6>[ 0.076088] cblist_init_generic: Setting adjustable number of callback queues.
5655 11:33:32.295091 <6>[ 0.083533] cblist_init_generic: Setting shift to 3 and lim to 1.
5656 11:33:32.298212 <6>[ 0.089932] rcu: Hierarchical SRCU implementation.
5657 11:33:32.305204 <6>[ 0.094958] rcu: Max phase no-delay instances is 1000.
5658 11:33:32.312209 <6>[ 0.102874] EFI services will not be available.
5659 11:33:32.315217 <6>[ 0.107824] smp: Bringing up secondary CPUs ...
5660 11:33:32.325764 <6>[ 0.113061] Detected VIPT I-cache on CPU1
5661 11:33:32.332793 <4>[ 0.113109] cacheinfo: Unable to detect cache hierarchy for CPU 1
5662 11:33:32.339289 <6>[ 0.113116] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5663 11:33:32.345939 <6>[ 0.113147] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5664 11:33:32.349293 <6>[ 0.113630] Detected VIPT I-cache on CPU2
5665 11:33:32.355496 <4>[ 0.113665] cacheinfo: Unable to detect cache hierarchy for CPU 2
5666 11:33:32.362233 <6>[ 0.113669] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5667 11:33:32.369059 <6>[ 0.113681] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5668 11:33:32.372740 <6>[ 0.114125] Detected VIPT I-cache on CPU3
5669 11:33:32.378660 <4>[ 0.114155] cacheinfo: Unable to detect cache hierarchy for CPU 3
5670 11:33:32.385754 <6>[ 0.114160] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5671 11:33:32.392285 <6>[ 0.114171] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5672 11:33:32.398804 <6>[ 0.114746] CPU features: detected: Spectre-v2
5673 11:33:32.401970 <6>[ 0.114756] CPU features: detected: Spectre-BHB
5674 11:33:32.408963 <6>[ 0.114759] CPU features: detected: ARM erratum 858921
5675 11:33:32.412441 <6>[ 0.114765] Detected VIPT I-cache on CPU4
5676 11:33:32.418917 <4>[ 0.114812] cacheinfo: Unable to detect cache hierarchy for CPU 4
5677 11:33:32.425524 <6>[ 0.114819] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5678 11:33:32.431958 <6>[ 0.114827] arch_timer: Enabling local workaround for ARM erratum 858921
5679 11:33:32.438835 <6>[ 0.114838] arch_timer: CPU4: Trapping CNTVCT access
5680 11:33:32.445115 <6>[ 0.114846] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5681 11:33:32.448790 <6>[ 0.115333] Detected VIPT I-cache on CPU5
5682 11:33:32.455202 <4>[ 0.115373] cacheinfo: Unable to detect cache hierarchy for CPU 5
5683 11:33:32.462140 <6>[ 0.115378] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5684 11:33:32.468901 <6>[ 0.115385] arch_timer: Enabling local workaround for ARM erratum 858921
5685 11:33:32.475725 <6>[ 0.115391] arch_timer: CPU5: Trapping CNTVCT access
5686 11:33:32.482092 <6>[ 0.115396] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5687 11:33:32.485440 <6>[ 0.115933] Detected VIPT I-cache on CPU6
5688 11:33:32.492296 <4>[ 0.115979] cacheinfo: Unable to detect cache hierarchy for CPU 6
5689 11:33:32.499400 <6>[ 0.115985] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5690 11:33:32.505706 <6>[ 0.115992] arch_timer: Enabling local workaround for ARM erratum 858921
5691 11:33:32.512537 <6>[ 0.115998] arch_timer: CPU6: Trapping CNTVCT access
5692 11:33:32.518995 <6>[ 0.116003] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5693 11:33:32.522390 <6>[ 0.116533] Detected VIPT I-cache on CPU7
5694 11:33:32.528693 <4>[ 0.116577] cacheinfo: Unable to detect cache hierarchy for CPU 7
5695 11:33:32.535712 <6>[ 0.116584] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5696 11:33:32.542264 <6>[ 0.116591] arch_timer: Enabling local workaround for ARM erratum 858921
5697 11:33:32.548704 <6>[ 0.116597] arch_timer: CPU7: Trapping CNTVCT access
5698 11:33:32.555377 <6>[ 0.116602] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5699 11:33:32.558538 <6>[ 0.116650] smp: Brought up 1 node, 8 CPUs
5700 11:33:32.565300 <6>[ 0.355523] SMP: Total of 8 processors activated.
5701 11:33:32.568943 <6>[ 0.360459] CPU features: detected: 32-bit EL0 Support
5702 11:33:32.575429 <6>[ 0.365830] CPU features: detected: 32-bit EL1 Support
5703 11:33:32.582226 <6>[ 0.371195] CPU features: detected: CRC32 instructions
5704 11:33:32.585211 <6>[ 0.376621] CPU: All CPU(s) started at EL2
5705 11:33:32.591838 <6>[ 0.380959] alternatives: applying system-wide alternatives
5706 11:33:32.595353 <6>[ 0.389116] devtmpfs: initialized
5707 11:33:32.610367 <6>[ 0.398038] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5708 11:33:32.620669 <6>[ 0.407987] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5709 11:33:32.623644 <6>[ 0.415709] pinctrl core: initialized pinctrl subsystem
5710 11:33:32.632264 <6>[ 0.422829] DMI not present or invalid.
5711 11:33:32.638663 <6>[ 0.427196] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5712 11:33:32.645467 <6>[ 0.434091] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5713 11:33:32.652182 <6>[ 0.441622] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5714 11:33:32.662460 <6>[ 0.449874] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5715 11:33:32.668649 <6>[ 0.458053] audit: initializing netlink subsys (disabled)
5716 11:33:32.675556 <5>[ 0.463759] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5717 11:33:32.682297 <6>[ 0.464736] thermal_sys: Registered thermal governor 'step_wise'
5718 11:33:32.688860 <6>[ 0.471726] thermal_sys: Registered thermal governor 'power_allocator'
5719 11:33:32.692459 <6>[ 0.478024] cpuidle: using governor menu
5720 11:33:32.698417 <6>[ 0.488989] NET: Registered PF_QIPCRTR protocol family
5721 11:33:32.705129 <6>[ 0.494475] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5722 11:33:32.712050 <6>[ 0.501571] ASID allocator initialised with 32768 entries
5723 11:33:32.715125 <6>[ 0.508347] Serial: AMBA PL011 UART driver
5724 11:33:32.728778 <4>[ 0.519702] Trying to register duplicate clock ID: 113
5725 11:33:32.788789 <6>[ 0.576204] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5726 11:33:32.803479 <6>[ 0.590616] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5727 11:33:32.806159 <6>[ 0.600390] KASLR enabled
5728 11:33:32.820861 <6>[ 0.608332] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5729 11:33:32.827335 <6>[ 0.615333] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5730 11:33:32.833885 <6>[ 0.621811] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5731 11:33:32.840498 <6>[ 0.628803] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5732 11:33:32.847648 <6>[ 0.635278] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5733 11:33:32.854074 <6>[ 0.642269] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5734 11:33:32.860562 <6>[ 0.648744] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5735 11:33:32.867325 <6>[ 0.655734] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5736 11:33:32.870756 <6>[ 0.663271] ACPI: Interpreter disabled.
5737 11:33:32.880181 <6>[ 0.671283] iommu: Default domain type: Translated
5738 11:33:32.887108 <6>[ 0.676443] iommu: DMA domain TLB invalidation policy: strict mode
5739 11:33:32.890585 <5>[ 0.683066] SCSI subsystem initialized
5740 11:33:32.897228 <6>[ 0.687515] usbcore: registered new interface driver usbfs
5741 11:33:32.903694 <6>[ 0.693245] usbcore: registered new interface driver hub
5742 11:33:32.907099 <6>[ 0.698788] usbcore: registered new device driver usb
5743 11:33:32.914280 <6>[ 0.705113] pps_core: LinuxPPS API ver. 1 registered
5744 11:33:32.924407 <6>[ 0.710298] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5745 11:33:32.927608 <6>[ 0.719623] PTP clock support registered
5746 11:33:32.931249 <6>[ 0.723876] EDAC MC: Ver: 3.0.0
5747 11:33:32.938761 <6>[ 0.729533] FPGA manager framework
5748 11:33:32.942276 <6>[ 0.733214] Advanced Linux Sound Architecture Driver Initialized.
5749 11:33:32.945836 <6>[ 0.739955] vgaarb: loaded
5750 11:33:32.952415 <6>[ 0.743080] clocksource: Switched to clocksource arch_sys_counter
5751 11:33:32.958957 <5>[ 0.749513] VFS: Disk quotas dquot_6.6.0
5752 11:33:32.966109 <6>[ 0.753687] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5753 11:33:32.968943 <6>[ 0.760861] pnp: PnP ACPI: disabled
5754 11:33:32.976812 <6>[ 0.767724] NET: Registered PF_INET protocol family
5755 11:33:32.983331 <6>[ 0.772947] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5756 11:33:32.995421 <6>[ 0.782858] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5757 11:33:33.002381 <6>[ 0.791611] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5758 11:33:33.012177 <6>[ 0.799560] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5759 11:33:33.018693 <6>[ 0.807792] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5760 11:33:33.024940 <6>[ 0.815886] TCP: Hash tables configured (established 32768 bind 32768)
5761 11:33:33.035274 <6>[ 0.822712] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5762 11:33:33.041867 <6>[ 0.829688] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5763 11:33:33.048700 <6>[ 0.837168] NET: Registered PF_UNIX/PF_LOCAL protocol family
5764 11:33:33.052263 <6>[ 0.843290] RPC: Registered named UNIX socket transport module.
5765 11:33:33.058624 <6>[ 0.849435] RPC: Registered udp transport module.
5766 11:33:33.061597 <6>[ 0.854360] RPC: Registered tcp transport module.
5767 11:33:33.068539 <6>[ 0.859283] RPC: Registered tcp NFSv4.1 backchannel transport module.
5768 11:33:33.075193 <6>[ 0.865936] PCI: CLS 0 bytes, default 64
5769 11:33:33.078788 <6>[ 0.870209] Unpacking initramfs...
5770 11:33:33.088444 <6>[ 0.874390] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5771 11:33:33.095365 <6>[ 0.883015] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5772 11:33:33.101748 <6>[ 0.891863] kvm [1]: IPA Size Limit: 40 bits
5773 11:33:33.105495 <6>[ 0.898182] kvm [1]: vgic-v2@c420000
5774 11:33:33.111970 <6>[ 0.902000] kvm [1]: GIC system register CPU interface enabled
5775 11:33:33.115124 <6>[ 0.908174] kvm [1]: vgic interrupt IRQ18
5776 11:33:33.121679 <6>[ 0.912521] kvm [1]: Hyp mode initialized successfully
5777 11:33:33.128372 <5>[ 0.918803] Initialise system trusted keyrings
5778 11:33:33.134633 <6>[ 0.923641] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5779 11:33:33.142843 <6>[ 0.933514] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5780 11:33:33.149685 <5>[ 0.940022] NFS: Registering the id_resolver key type
5781 11:33:33.152529 <5>[ 0.945333] Key type id_resolver registered
5782 11:33:33.159099 <5>[ 0.949747] Key type id_legacy registered
5783 11:33:33.166126 <6>[ 0.954052] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5784 11:33:33.172927 <6>[ 0.960973] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5785 11:33:33.179356 <6>[ 0.968741] 9p: Installing v9fs 9p2000 file system support
5786 11:33:33.206052 <5>[ 0.997046] Key type asymmetric registered
5787 11:33:33.209600 <5>[ 1.001394] Asymmetric key parser 'x509' registered
5788 11:33:33.219312 <6>[ 1.006555] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5789 11:33:33.223013 <6>[ 1.014170] io scheduler mq-deadline registered
5790 11:33:33.226289 <6>[ 1.018930] io scheduler kyber registered
5791 11:33:33.248556 <6>[ 1.039731] EINJ: ACPI disabled.
5792 11:33:33.255348 <4>[ 1.043498] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5793 11:33:33.293464 <6>[ 1.084487] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5794 11:33:33.302218 <6>[ 1.092972] printk: console [ttyS0] disabled
5795 11:33:33.330290 <6>[ 1.117625] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5796 11:33:33.336477 <6>[ 1.127110] printk: console [ttyS0] enabled
5797 11:33:33.340032 <6>[ 1.127110] printk: console [ttyS0] enabled
5798 11:33:33.346598 <6>[ 1.136025] printk: bootconsole [mtk8250] disabled
5799 11:33:33.350297 <6>[ 1.136025] printk: bootconsole [mtk8250] disabled
5800 11:33:33.359999 <3>[ 1.146565] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5801 11:33:33.366335 <3>[ 1.154951] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5802 11:33:33.395511 <6>[ 1.183376] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5803 11:33:33.402319 <6>[ 1.193040] serial serial0: tty port ttyS1 registered
5804 11:33:33.409212 <6>[ 1.199631] SuperH (H)SCI(F) driver initialized
5805 11:33:33.412328 <6>[ 1.205152] msm_serial: driver initialized
5806 11:33:33.428240 <6>[ 1.215560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5807 11:33:33.438566 <6>[ 1.224157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5808 11:33:33.444931 <6>[ 1.232736] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5809 11:33:33.454966 <6>[ 1.241302] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5810 11:33:33.461417 <6>[ 1.249955] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5811 11:33:33.471644 <6>[ 1.258617] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5812 11:33:33.481352 <6>[ 1.267356] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5813 11:33:33.487649 <6>[ 1.276096] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5814 11:33:33.497687 <6>[ 1.284661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5815 11:33:33.507639 <6>[ 1.293458] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5816 11:33:33.515008 <4>[ 1.305878] cacheinfo: Unable to detect cache hierarchy for CPU 0
5817 11:33:33.524018 <6>[ 1.315243] loop: module loaded
5818 11:33:33.536273 <6>[ 1.327230] vsim1: Bringing 1800000uV into 2700000-2700000uV
5819 11:33:33.554497 <6>[ 1.345321] megasas: 07.719.03.00-rc1
5820 11:33:33.563163 <6>[ 1.354239] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5821 11:33:33.571842 <6>[ 1.362486] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5822 11:33:33.588278 <6>[ 1.379343] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5823 11:33:33.645284 <6>[ 1.429588] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d
5824 11:33:33.783657 <6>[ 1.574724] Freeing initrd memory: 20852K
5825 11:33:33.803019 <4>[ 1.590547] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5826 11:33:33.809624 <4>[ 1.599775] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
5827 11:33:33.816786 <4>[ 1.606473] Hardware name: Google juniper sku16 board (DT)
5828 11:33:33.819794 <4>[ 1.612212] Call trace:
5829 11:33:33.823301 <4>[ 1.614912] dump_backtrace.part.0+0xe0/0xf0
5830 11:33:33.826670 <4>[ 1.619450] show_stack+0x18/0x30
5831 11:33:33.829676 <4>[ 1.623024] dump_stack_lvl+0x64/0x80
5832 11:33:33.832998 <4>[ 1.626944] dump_stack+0x18/0x34
5833 11:33:33.840433 <4>[ 1.630513] sysfs_warn_dup+0x64/0x80
5834 11:33:33.843572 <4>[ 1.634435] sysfs_do_create_link_sd+0xf0/0x100
5835 11:33:33.846822 <4>[ 1.639222] sysfs_create_link+0x20/0x40
5836 11:33:33.853269 <4>[ 1.643401] bus_add_device+0x64/0x120
5837 11:33:33.856953 <4>[ 1.647407] device_add+0x354/0x7ec
5838 11:33:33.859739 <4>[ 1.651152] of_device_add+0x44/0x60
5839 11:33:33.863203 <4>[ 1.654986] of_platform_device_create_pdata+0x90/0x124
5840 11:33:33.869737 <4>[ 1.660467] of_platform_bus_create+0x154/0x380
5841 11:33:33.873074 <4>[ 1.665253] of_platform_populate+0x50/0xfc
5842 11:33:33.879589 <4>[ 1.669692] parse_mtd_partitions+0x1d8/0x4e0
5843 11:33:33.884105 <4>[ 1.674309] mtd_device_parse_register+0xec/0x2e0
5844 11:33:33.886409 <4>[ 1.679269] spi_nor_probe+0x280/0x2f4
5845 11:33:33.889853 <4>[ 1.683274] spi_mem_probe+0x6c/0xc0
5846 11:33:33.893329 <4>[ 1.687106] spi_probe+0x84/0xe4
5847 11:33:33.899999 <4>[ 1.690591] really_probe+0xbc/0x2dc
5848 11:33:33.903619 <4>[ 1.694422] __driver_probe_device+0x78/0x114
5849 11:33:33.906689 <4>[ 1.699034] driver_probe_device+0xd8/0x15c
5850 11:33:33.913121 <4>[ 1.703472] __device_attach_driver+0xb8/0x134
5851 11:33:33.916311 <4>[ 1.708170] bus_for_each_drv+0x7c/0xd4
5852 11:33:33.920050 <4>[ 1.712262] __device_attach+0x9c/0x1a0
5853 11:33:33.926430 <4>[ 1.716353] device_initial_probe+0x14/0x20
5854 11:33:33.929440 <4>[ 1.720791] bus_probe_device+0x98/0xa0
5855 11:33:33.932989 <4>[ 1.724881] device_add+0x3c0/0x7ec
5856 11:33:33.936241 <4>[ 1.728626] __spi_add_device+0x78/0x120
5857 11:33:33.939473 <4>[ 1.732803] spi_add_device+0x44/0x80
5858 11:33:33.946347 <4>[ 1.736720] spi_register_controller+0x704/0xb20
5859 11:33:33.949892 <4>[ 1.741593] devm_spi_register_controller+0x4c/0xac
5860 11:33:33.956339 <4>[ 1.746726] mtk_spi_probe+0x4f4/0x684
5861 11:33:33.959593 <4>[ 1.750731] platform_probe+0x68/0xc0
5862 11:33:33.963160 <4>[ 1.754649] really_probe+0xbc/0x2dc
5863 11:33:33.966486 <4>[ 1.758480] __driver_probe_device+0x78/0x114
5864 11:33:33.973413 <4>[ 1.763091] driver_probe_device+0xd8/0x15c
5865 11:33:33.976687 <4>[ 1.767528] __driver_attach+0x94/0x19c
5866 11:33:33.979904 <4>[ 1.771619] bus_for_each_dev+0x74/0xd0
5867 11:33:33.983114 <4>[ 1.775711] driver_attach+0x24/0x30
5868 11:33:33.987084 <4>[ 1.779541] bus_add_driver+0x154/0x20c
5869 11:33:33.993187 <4>[ 1.783631] driver_register+0x78/0x130
5870 11:33:33.996651 <4>[ 1.787721] __platform_driver_register+0x28/0x34
5871 11:33:34.000006 <4>[ 1.792681] mtk_spi_driver_init+0x1c/0x28
5872 11:33:34.006425 <4>[ 1.797037] do_one_initcall+0x64/0x1dc
5873 11:33:34.010333 <4>[ 1.801128] kernel_init_freeable+0x218/0x284
5874 11:33:34.013172 <4>[ 1.805742] kernel_init+0x24/0x12c
5875 11:33:34.016751 <4>[ 1.809488] ret_from_fork+0x10/0x20
5876 11:33:34.027335 <6>[ 1.818349] tun: Universal TUN/TAP device driver, 1.6
5877 11:33:34.031107 <6>[ 1.824649] thunder_xcv, ver 1.0
5878 11:33:34.034431 <6>[ 1.828167] thunder_bgx, ver 1.0
5879 11:33:34.037858 <6>[ 1.831671] nicpf, ver 1.0
5880 11:33:34.048502 <6>[ 1.836058] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5881 11:33:34.051941 <6>[ 1.843544] hns3: Copyright (c) 2017 Huawei Corporation.
5882 11:33:34.055142 <6>[ 1.849143] hclge is initializing
5883 11:33:34.062160 <6>[ 1.852728] e1000: Intel(R) PRO/1000 Network Driver
5884 11:33:34.068611 <6>[ 1.857864] e1000: Copyright (c) 1999-2006 Intel Corporation.
5885 11:33:34.071863 <6>[ 1.863884] e1000e: Intel(R) PRO/1000 Network Driver
5886 11:33:34.078967 <6>[ 1.869105] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5887 11:33:34.085225 <6>[ 1.875299] igb: Intel(R) Gigabit Ethernet Network Driver
5888 11:33:34.092241 <6>[ 1.880955] igb: Copyright (c) 2007-2014 Intel Corporation.
5889 11:33:34.098820 <6>[ 1.886800] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5890 11:33:34.102474 <6>[ 1.893323] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5891 11:33:34.108937 <6>[ 1.899885] sky2: driver version 1.30
5892 11:33:34.116061 <6>[ 1.905146] usbcore: registered new device driver r8152-cfgselector
5893 11:33:34.122530 <6>[ 1.911688] usbcore: registered new interface driver r8152
5894 11:33:34.125559 <6>[ 1.917516] VFIO - User Level meta-driver version: 0.3
5895 11:33:34.134479 <6>[ 1.925343] mtu3 11201000.usb: uwk - reg:0x420, version:101
5896 11:33:34.141077 <4>[ 1.931217] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5897 11:33:34.148158 <6>[ 1.938498] mtu3 11201000.usb: dr_mode: 1, drd: auto
5898 11:33:34.154630 <6>[ 1.943727] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5899 11:33:34.158281 <6>[ 1.949911] mtu3 11201000.usb: usb3-drd: 0
5900 11:33:34.168131 <6>[ 1.955465] mtu3 11201000.usb: xHCI platform device register success...
5901 11:33:34.175033 <4>[ 1.964156] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5902 11:33:34.181496 <6>[ 1.972110] xhci-mtk 11200000.usb: xHCI Host Controller
5903 11:33:34.188256 <6>[ 1.977625] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5904 11:33:34.194444 <6>[ 1.985347] xhci-mtk 11200000.usb: USB3 root hub has no ports
5905 11:33:34.204441 <6>[ 1.991356] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5906 11:33:34.211146 <6>[ 2.000783] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5907 11:33:34.217732 <6>[ 2.006864] xhci-mtk 11200000.usb: xHCI Host Controller
5908 11:33:34.224308 <6>[ 2.012352] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5909 11:33:34.231765 <6>[ 2.020010] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
5910 11:33:34.234783 <6>[ 2.026842] hub 1-0:1.0: USB hub found
5911 11:33:34.238145 <6>[ 2.030870] hub 1-0:1.0: 1 port detected
5912 11:33:34.248633 <6>[ 2.036225] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
5913 11:33:34.251945 <6>[ 2.044852] hub 2-0:1.0: USB hub found
5914 11:33:34.262326 <3>[ 2.048879] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
5915 11:33:34.268679 <6>[ 2.056756] usbcore: registered new interface driver usb-storage
5916 11:33:34.275292 <6>[ 2.063370] usbcore: registered new device driver onboard-usb-hub
5917 11:33:34.291428 <4>[ 2.079181] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
5918 11:33:34.300884 <6>[ 2.091500] mt6397-rtc mt6358-rtc: registered as rtc0
5919 11:33:34.310799 <6>[ 2.096983] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-17T11:33:34 UTC (1721216014)
5920 11:33:34.313786 <6>[ 2.106885] i2c_dev: i2c /dev entries driver
5921 11:33:34.325736 <6>[ 2.113314] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5922 11:33:34.335638 <6>[ 2.121634] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5923 11:33:34.339171 <6>[ 2.130539] i2c 4-0058: Fixed dependency cycle(s) with /panel
5924 11:33:34.349133 <6>[ 2.136571] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
5925 11:33:34.365655 <6>[ 2.156020] cpu cpu0: EM: created perf domain
5926 11:33:34.375018 <6>[ 2.161507] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
5927 11:33:34.381857 <6>[ 2.172790] cpu cpu4: EM: created perf domain
5928 11:33:34.389360 <6>[ 2.179887] sdhci: Secure Digital Host Controller Interface driver
5929 11:33:34.395735 <6>[ 2.186342] sdhci: Copyright(c) Pierre Ossman
5930 11:33:34.402716 <6>[ 2.191777] Synopsys Designware Multimedia Card Interface Driver
5931 11:33:34.408735 <6>[ 2.192276] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
5932 11:33:34.412387 <6>[ 2.198885] sdhci-pltfm: SDHCI platform and OF driver helper
5933 11:33:34.421818 <6>[ 2.212579] ledtrig-cpu: registered to indicate activity on CPUs
5934 11:33:34.429825 <6>[ 2.220369] usbcore: registered new interface driver usbhid
5935 11:33:34.433182 <6>[ 2.226219] usbhid: USB HID core driver
5936 11:33:34.443807 <6>[ 2.230553] spi_master spi2: will run message pump with realtime priority
5937 11:33:34.447244 <4>[ 2.230892] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
5938 11:33:34.454532 <4>[ 2.244908] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
5939 11:33:34.467867 <6>[ 2.251052] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
5940 11:33:34.487286 <6>[ 2.267988] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
5941 11:33:34.494152 <4>[ 2.277303] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
5942 11:33:34.496831 <6>[ 2.282684] cros-ec-spi spi2.0: Chrome EC device registered
5943 11:33:34.511231 <4>[ 2.298774] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
5944 11:33:34.514631 <6>[ 2.300409] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
5945 11:33:34.525039 <4>[ 2.311051] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
5946 11:33:34.527954 <6>[ 2.313265] mmc0: new HS400 MMC card at address 0001
5947 11:33:34.534825 <4>[ 2.320964] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
5948 11:33:34.541606 <6>[ 2.326214] mmcblk0: mmc0:0001 TB2932 29.2 GiB
5949 11:33:34.551075 <6>[ 2.341949] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
5950 11:33:34.560006 <6>[ 2.350956] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
5951 11:33:34.566601 <6>[ 2.356506] mmc1: new ultra high speed SDR104 SDIO card at address 0001
5952 11:33:34.573215 <6>[ 2.357454] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
5953 11:33:34.580057 <6>[ 2.361256] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
5954 11:33:34.593599 <6>[ 2.364378] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5955 11:33:34.600415 <6>[ 2.369545] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
5956 11:33:34.604006 <6>[ 2.378469] NET: Registered PF_PACKET protocol family
5957 11:33:34.617068 <6>[ 2.391246] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
5958 11:33:34.619965 <6>[ 2.394789] 9pnet: Installing 9P2000 support
5959 11:33:34.630367 <6>[ 2.400399] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
5960 11:33:34.636912 <5>[ 2.412093] Key type dns_resolver registered
5961 11:33:34.640368 <6>[ 2.431384] registered taskstats version 1
5962 11:33:34.643716 <5>[ 2.435751] Loading compiled-in X.509 certificates
5963 11:33:34.664044 <6>[ 2.451214] usb 1-1: new high-speed USB device number 2 using xhci-mtk
5964 11:33:34.696439 <3>[ 2.483780] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
5965 11:33:34.728568 <6>[ 2.512939] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5966 11:33:34.740031 <6>[ 2.527197] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
5967 11:33:34.749755 <6>[ 2.535771] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
5968 11:33:34.756639 <6>[ 2.544432] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
5969 11:33:34.766943 <6>[ 2.553102] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
5970 11:33:34.773129 <6>[ 2.561708] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
5971 11:33:34.782799 <6>[ 2.570256] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
5972 11:33:34.793197 <6>[ 2.578843] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
5973 11:33:34.799621 <6>[ 2.588328] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
5974 11:33:34.805952 <6>[ 2.595920] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
5975 11:33:34.812545 <6>[ 2.603235] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
5976 11:33:34.819562 <6>[ 2.606515] hub 1-1:1.0: USB hub found
5977 11:33:34.826097 <6>[ 2.610545] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
5978 11:33:34.829522 <6>[ 2.614212] hub 1-1:1.0: 3 ports detected
5979 11:33:34.836232 <6>[ 2.621223] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
5980 11:33:34.842793 <6>[ 2.633183] panfrost 13040000.gpu: clock rate = 511999970
5981 11:33:34.852542 <6>[ 2.638877] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
5982 11:33:34.862627 <6>[ 2.648880] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
5983 11:33:34.869361 <6>[ 2.656895] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
5984 11:33:34.882841 <6>[ 2.665328] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
5985 11:33:34.888964 <6>[ 2.677406] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
5986 11:33:34.901501 <6>[ 2.688985] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
5987 11:33:34.911755 <6>[ 2.698288] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
5988 11:33:34.921411 <6>[ 2.707460] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
5989 11:33:34.931329 <6>[ 2.716592] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
5990 11:33:34.937997 <6>[ 2.725720] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
5991 11:33:34.948306 <6>[ 2.735022] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
5992 11:33:34.958115 <6>[ 2.744325] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
5993 11:33:34.967845 <6>[ 2.753802] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
5994 11:33:34.977803 <6>[ 2.763279] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
5995 11:33:34.984464 <6>[ 2.772407] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
5996 11:33:35.059263 <6>[ 2.846906] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
5997 11:33:35.069822 <6>[ 2.855834] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
5998 11:33:35.079896 <6>[ 2.867419] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
5999 11:33:35.127649 <6>[ 2.915116] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6000 11:33:35.769702 <6>[ 3.107345] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6001 11:33:35.779343 <4>[ 3.216509] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6002 11:33:35.786406 <4>[ 3.216529] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6003 11:33:35.792884 <6>[ 3.253337] r8152 1-1.2:1.0 eth0: v1.12.13
6004 11:33:35.799551 <6>[ 3.335111] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6005 11:33:35.805940 <6>[ 3.540605] Console: switching to colour frame buffer device 170x48
6006 11:33:35.812910 <6>[ 3.601268] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6007 11:33:35.833258 <6>[ 3.617233] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6008 11:33:35.850386 <6>[ 3.634292] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6009 11:33:35.856859 <6>[ 3.646465] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6010 11:33:35.867615 <6>[ 3.655046] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6011 11:33:35.877427 <6>[ 3.659512] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6012 11:33:35.895452 <6>[ 3.679389] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6013 11:33:37.056812 <6>[ 4.848003] r8152 1-1.2:1.0 eth0: carrier on
6014 11:33:39.328394 <5>[ 4.871119] Sending DHCP requests .., OK
6015 11:33:39.334911 <6>[ 7.123569] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.23
6016 11:33:39.338531 <6>[ 7.132007] IP-Config: Complete:
6017 11:33:39.351589 <6>[ 7.135574] device=eth0, hwaddr=00:e0:4c:71:a7:1f, ipaddr=192.168.201.23, mask=255.255.255.0, gw=192.168.201.1
6018 11:33:39.361461 <6>[ 7.146473] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3, domain=lava-rack, nis-domain=(none)
6019 11:33:39.373769 <6>[ 7.160836] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6020 11:33:39.381815 <6>[ 7.160846] nameserver0=192.168.201.1
6021 11:33:39.389900 <6>[ 7.180711] clk: Disabling unused clocks
6022 11:33:39.394729 <6>[ 7.188727] ALSA device list:
6023 11:33:39.404653 <6>[ 7.194820] No soundcards found.
6024 11:33:39.413053 <6>[ 7.203747] Freeing unused kernel memory: 8512K
6025 11:33:39.420334 <6>[ 7.210908] Run /init as init process
6026 11:33:39.458021 Starting syslogd: OK
6027 11:33:39.461082 Starting klogd: OK
6028 11:33:39.471294 Running sysctl: OK
6029 11:33:39.481327 Populating /dev using udev: <30>[ 7.270760] udevd[208]: starting version 3.2.9
6030 11:33:39.489453 <27>[ 7.279458] udevd[208]: specified user 'tss' unknown
6031 11:33:39.495219 <27>[ 7.285765] udevd[208]: specified group 'tss' unknown
6032 11:33:39.502289 <30>[ 7.292877] udevd[209]: starting eudev-3.2.9
6033 11:33:39.527635 <27>[ 7.318286] udevd[209]: specified user 'tss' unknown
6034 11:33:39.535014 <27>[ 7.324572] udevd[209]: specified group 'tss' unknown
6035 11:33:39.629339 <3>[ 7.419702] mtk-scp 10500000.scp: invalid resource
6036 11:33:39.639903 <6>[ 7.426659] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6037 11:33:39.646069 <6>[ 7.431430] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6038 11:33:39.652633 <6>[ 7.435752] remoteproc remoteproc0: scp is available
6039 11:33:39.656340 <3>[ 7.437947] thermal_sys: Failed to find 'trips' node
6040 11:33:39.665970 <3>[ 7.437956] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6041 11:33:39.672274 <3>[ 7.437964] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6042 11:33:39.678987 <4>[ 7.437968] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6043 11:33:39.686132 <3>[ 7.440715] thermal_sys: Failed to find 'trips' node
6044 11:33:39.692756 <3>[ 7.440724] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6045 11:33:39.702723 <3>[ 7.440732] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6046 11:33:39.709004 <4>[ 7.440737] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6047 11:33:39.718835 <4>[ 7.444454] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6048 11:33:39.728798 <4>[ 7.447575] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6049 11:33:39.732396 <6>[ 7.448337] Bluetooth: Core ver 2.22
6050 11:33:39.738808 <6>[ 7.448384] NET: Registered PF_BLUETOOTH protocol family
6051 11:33:39.745377 <6>[ 7.448386] Bluetooth: HCI device and connection manager initialized
6052 11:33:39.749358 <6>[ 7.448403] Bluetooth: HCI socket layer initialized
6053 11:33:39.753111 <6>[ 7.448409] Bluetooth: L2CAP socket layer initialized
6054 11:33:39.759623 <6>[ 7.448418] Bluetooth: SCO socket layer initialized
6055 11:33:39.769417 <6>[ 7.459532] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6056 11:33:39.776193 <6>[ 7.460116] remoteproc remoteproc0: powering up scp
6057 11:33:39.786275 <3>[ 7.461739] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6058 11:33:39.792700 <3>[ 7.461746] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6059 11:33:39.805817 <3>[ 7.461750] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6060 11:33:39.812659 <3>[ 7.461756] elan_i2c 2-0015: Error applying setting, reverse things back
6061 11:33:39.818840 <4>[ 7.463828] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6062 11:33:39.829027 <4>[ 7.463942] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6063 11:33:39.839274 <6>[ 7.471951] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6064 11:33:39.849640 <4>[ 7.476208] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6065 11:33:39.852617 <6>[ 7.482306] mc: Linux media interface: v0.10
6066 11:33:39.865595 <3>[ 7.488185] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6067 11:33:39.872285 <3>[ 7.489157] remoteproc remoteproc0: request_firmware failed: -2
6068 11:33:39.879218 <3>[ 7.489257] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6069 11:33:39.889428 <3>[ 7.489286] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6070 11:33:39.896143 <3>[ 7.489307] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6071 11:33:39.905746 <3>[ 7.492649] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6072 11:33:39.915843 <3>[ 7.492661] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6073 11:33:39.925785 <3>[ 7.492666] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6074 11:33:39.935478 <3>[ 7.492673] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6075 11:33:39.941784 <3>[ 7.492677] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6076 11:33:39.952143 <3>[ 7.492702] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6077 11:33:39.959059 <6>[ 7.498225] cs_system_cfg: CoreSight Configuration manager initialised
6078 11:33:39.965040 <5>[ 7.499628] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6079 11:33:39.975131 <6>[ 7.505304] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6080 11:33:39.981844 <6>[ 7.523489] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6081 11:33:39.988918 <5>[ 7.523841] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6082 11:33:39.998688 <5>[ 7.524265] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6083 11:33:40.005698 <6>[ 7.527917] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6084 11:33:40.015367 <4>[ 7.533396] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6085 11:33:40.025292 <6>[ 7.540233] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6086 11:33:40.028611 <6>[ 7.545042] cfg80211: failed to load regulatory.db
6087 11:33:40.039014 <6>[ 7.550430] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6088 11:33:40.048628 <6>[ 7.611064] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6089 11:33:40.055429 <6>[ 7.616601] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6090 11:33:40.062538 <6>[ 7.635925] videodev: Linux video capture interface: v2.00
6091 11:33:40.072649 <6>[ 7.643995] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6092 11:33:40.082276 <3>[ 7.644373] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6093 11:33:40.093107 <3>[ 7.645109] debugfs: File 'Playback' in directory 'dapm' already present!
6094 11:33:40.099645 <3>[ 7.645116] debugfs: File 'Capture' in directory 'dapm' already present!
6095 11:33:40.102866 <6>[ 7.653415] Bluetooth: HCI UART driver ver 2.3
6096 11:33:40.116355 <6>[ 7.653543] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6097 11:33:40.128058 <6>[ 7.661254] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6098 11:33:40.136683 <6>[ 7.667282] Bluetooth: HCI UART protocol H4 registered
6099 11:33:40.148009 <6>[ 7.675733] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6100 11:33:40.156653 <6>[ 7.684428] Bluetooth: HCI UART protocol LL registered
6101 11:33:40.165080 <6>[ 7.713072] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6102 11:33:40.173740 <6>[ 7.721620] Bluetooth: HCI UART protocol Three-wire (H5) registered
6103 11:33:40.183524 <6>[ 7.739398] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6104 11:33:40.190234 <6>[ 7.747902] Bluetooth: HCI UART protocol Broadcom registered
6105 11:33:40.199197 <6>[ 7.754831] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6106 11:33:40.208812 <6>[ 7.754918] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6107 11:33:40.220031 <6>[ 7.754923] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6108 11:33:40.233552 <6>[ 7.755016] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6109 11:33:40.243647 <6>[ 7.756527] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6110 11:33:40.249936 <6>[ 7.762634] Bluetooth: HCI UART protocol QCA registered
6111 11:33:40.263534 <6>[ 7.762698] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6112 11:33:40.270331 <6>[ 7.762874] usbcore: registered new interface driver uvcvideo
6113 11:33:40.277432 <6>[ 7.763770] Bluetooth: hci0: setting up ROME/QCA6390
6114 11:33:40.287928 <6>[ 7.770639] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video3 (81,3)
6115 11:33:40.294236 <6>[ 7.778266] Bluetooth: HCI UART protocol Marvell registered
6116 11:33:40.305498 <4>[ 7.897394] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6117 11:33:40.311553 <4>[ 7.897394] Fallback method does not support PEC.
6118 11:33:40.318388 <6>[ 7.971431] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6119 11:33:40.329826 <3>[ 7.975797] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6120 11:33:40.336614 <3>[ 7.989892] Bluetooth: hci0: Frame reassembly failed (-84)
6121 11:33:40.423544 <3>[ 8.210286] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6122 11:33:40.442982 done
6123 11:33:40.452629 Saving random seed: OK
6124 11:33:40.462939 Starting network: ip: RTNETLINK answers: File exists
6125 11:33:40.466098 FAIL
6126 11:33:40.476554 <6>[ 8.267487] Bluetooth: hci0: QCA Product ID :0x00000008
6127 11:33:40.483135 Starting dropbea<6>[ 8.274365] Bluetooth: hci0: QCA SOC Version :0x00000044
6128 11:33:40.489953 r sshd: <6>[ 8.281396] Bluetooth: hci0: QCA ROM Version :0x00000302
6129 11:33:40.497565 <6>[ 8.288186] Bluetooth: hci0: QCA Patch Version:0x00000111
6130 11:33:40.504332 <6>[ 8.294950] Bluetooth: hci0: QCA controller version 0x00440302
6131 11:33:40.515265 <6>[ 8.302651] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6132 11:33:40.518824 <6>[ 8.304209] NET: Registered PF_INET6 protocol family
6133 11:33:40.528559 <4>[ 8.309503] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6134 11:33:40.531680 <6>[ 8.316674] Segment Routing with IPv6
6135 11:33:40.541610 <3>[ 8.323966] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6136 11:33:40.545647 <3>[ 8.323969] Bluetooth: hci0: QCA Failed to download patch (-2)
6137 11:33:40.552243 <6>[ 8.328151] In-situ OAM (IOAM) with IPv6
6138 11:33:40.560965 OK
6139 11:33:40.573238 /bin/sh: can't access tty; job control turned off
6140 11:33:40.574556 Matched prompt #10: / #
6142 11:33:40.576072 Setting prompt string to ['/ #']
6143 11:33:40.576679 end: 2.2.5.1 login-action (duration 00:00:09) [common]
6145 11:33:40.577921 end: 2.2.5 auto-login-action (duration 00:00:09) [common]
6146 11:33:40.578403 start: 2.2.6 expect-shell-connection (timeout 00:03:59) [common]
6147 11:33:40.578783 Setting prompt string to ['/ #']
6148 11:33:40.579059 Forcing a shell prompt, looking for ['/ #']
6149 11:33:40.579406 Sending line: ''
6151 11:33:40.630552 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6152 11:33:40.631017 Waiting using forced prompt support (timeout 00:02:30)
6153 11:33:40.631501 / # <6>[ 8.372931] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6154 11:33:40.636596
6155 11:33:40.637410 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6156 11:33:40.638043 start: 2.2.7 export-device-env (timeout 00:03:59) [common]
6157 11:33:40.638673 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6158 11:33:40.639294 end: 2.2 depthcharge-retry (duration 00:01:01) [common]
6159 11:33:40.639858 end: 2 depthcharge-action (duration 00:01:01) [common]
6160 11:33:40.640516 start: 3 lava-test-retry (timeout 00:01:00) [common]
6161 11:33:40.641227 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
6162 11:33:40.641771 Using namespace: common
6163 11:33:40.642135 Sending line: '#'
6165 11:33:40.743059 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
6166 11:33:40.743260 / # <4>[ 8.455855] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6167 11:33:40.743417 <4>[ 8.475019] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6168 11:33:40.743542 <4>[ 8.490219] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6169 11:33:40.743659 #<4>[ 8.501919] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6170 11:33:40.748363
6171 11:33:40.748735 Using /lava-14864604
6172 11:33:40.748817 Sending line: 'export SHELL=/bin/sh'
6174 11:33:40.853510 / # export SHELL=/bin/sh
6175 11:33:40.853779 Sending line: '. /lava-14864604/environment'
6177 11:33:40.960165 / # . /lava-14864604/environment
6178 11:33:40.960963 Sending line: '/lava-14864604/bin/lava-test-runner /lava-14864604/0'
6180 11:33:41.062324 Test shell timeout: 10s (minimum of the action and connection timeout)
6181 11:33:41.067764 / # /lava-14864604/bin/lava-test-runner /lava-14864604/0
6182 11:33:41.094139 + export 'TESTRUN_ID=0_dmesg'
6183 11:33:41.100198 +<8>[ 8.889953] <LAVA_SIGNAL_STARTRUN 0_dmesg 14864604_1.5.2.3.1>
6184 11:33:41.100935 Received signal: <STARTRUN> 0_dmesg 14864604_1.5.2.3.1
6185 11:33:41.101347 Starting test lava.0_dmesg (14864604_1.5.2.3.1)
6186 11:33:41.101730 Skipping test definition patterns.
6187 11:33:41.103763 cd /lava-14864604/0/tests/0_dmesg
6188 11:33:41.107241 + cat uuid
6189 11:33:41.107626 + UUID=14864604_1.5.2.3.1
6190 11:33:41.111110 + set +x
6191 11:33:41.113452 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
6192 11:33:41.127275 <8>[ 8.914859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
6193 11:33:41.127921 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
6195 11:33:41.151012 <8>[ 8.938626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
6196 11:33:41.151671 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
6198 11:33:41.177437 <8>[ 8.964972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
6199 11:33:41.178062 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
6201 11:33:41.182329 + set +x
6202 11:33:41.185750 <8>[ 8.976520] <LAVA_SIGNAL_ENDRUN 0_dmesg 14864604_1.5.2.3.1>
6203 11:33:41.186366 Received signal: <ENDRUN> 0_dmesg 14864604_1.5.2.3.1
6204 11:33:41.186735 Ending use of test pattern.
6205 11:33:41.187046 Ending test lava.0_dmesg (14864604_1.5.2.3.1), duration 0.09
6207 11:33:41.194102 <LAVA_TEST_RUNNER EXIT>
6208 11:33:41.194710 ok: lava_test_shell seems to have completed
6209 11:33:41.195175 crit: pass
alert: pass
emerg: pass
6210 11:33:41.195548 end: 3.1 lava-test-shell (duration 00:00:01) [common]
6211 11:33:41.195919 end: 3 lava-test-retry (duration 00:00:01) [common]
6212 11:33:41.196298 start: 4 finalize (timeout 00:08:37) [common]
6213 11:33:41.196691 start: 4.1 power-off (timeout 00:00:30) [common]
6214 11:33:41.197345 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3', '--port=1', '--command=off']
6215 11:33:43.321975 >> Command sent successfully.
6216 11:33:43.336180 Returned 0 in 2 seconds
6217 11:33:43.336895 end: 4.1 power-off (duration 00:00:02) [common]
6219 11:33:43.338081 start: 4.2 read-feedback (timeout 00:08:35) [common]
6220 11:33:43.338758 Listened to connection for namespace 'common' for up to 1s
6221 11:33:44.339805 Finalising connection for namespace 'common'
6222 11:33:44.340299 Disconnecting from shell: Finalise
6223 11:33:44.340645 / #
6224 11:33:44.441401 end: 4.2 read-feedback (duration 00:00:01) [common]
6225 11:33:44.441915 end: 4 finalize (duration 00:00:03) [common]
6226 11:33:44.442415 Cleaning after the job
6227 11:33:44.442862 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/ramdisk
6228 11:33:44.453118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/kernel
6229 11:33:44.480018 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/dtb
6230 11:33:44.480464 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864604/tftp-deploy-5u8il0ve/modules
6231 11:33:44.490985 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864604
6232 11:33:44.535316 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864604
6233 11:33:44.535463 Job finished correctly