Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:31:22.473367 lava-dispatcher, installed at version: 2024.05
2 11:31:22.473581 start: 0 validate
3 11:31:22.473712 Start time: 2024-07-17 11:31:22.473702+00:00 (UTC)
4 11:31:22.473845 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:31:22.473981 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:31:22.738743 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:31:22.739455 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:32:17.545711 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:32:17.546528 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:32:17.807402 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:32:17.807599 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:32:18.325518 validate duration: 55.85
14 11:32:18.325813 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:32:18.325923 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:32:18.326005 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:32:18.326150 Not decompressing ramdisk as can be used compressed.
18 11:32:18.326232 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 11:32:18.326292 saving as /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/ramdisk/rootfs.cpio.gz
20 11:32:18.326350 total size: 47897469 (45 MB)
21 11:32:18.584128 progress 0 % (0 MB)
22 11:32:18.628228 progress 5 % (2 MB)
23 11:32:18.645419 progress 10 % (4 MB)
24 11:32:18.658182 progress 15 % (6 MB)
25 11:32:18.670750 progress 20 % (9 MB)
26 11:32:18.683847 progress 25 % (11 MB)
27 11:32:18.696756 progress 30 % (13 MB)
28 11:32:18.709746 progress 35 % (16 MB)
29 11:32:18.721865 progress 40 % (18 MB)
30 11:32:18.734160 progress 45 % (20 MB)
31 11:32:18.746432 progress 50 % (22 MB)
32 11:32:18.758659 progress 55 % (25 MB)
33 11:32:18.771077 progress 60 % (27 MB)
34 11:32:18.783709 progress 65 % (29 MB)
35 11:32:18.796077 progress 70 % (32 MB)
36 11:32:18.808476 progress 75 % (34 MB)
37 11:32:18.820689 progress 80 % (36 MB)
38 11:32:18.832858 progress 85 % (38 MB)
39 11:32:18.845089 progress 90 % (41 MB)
40 11:32:18.857249 progress 95 % (43 MB)
41 11:32:18.869228 progress 100 % (45 MB)
42 11:32:18.869472 45 MB downloaded in 0.54 s (84.10 MB/s)
43 11:32:18.869632 end: 1.1.1 http-download (duration 00:00:01) [common]
45 11:32:18.869855 end: 1.1 download-retry (duration 00:00:01) [common]
46 11:32:18.869936 start: 1.2 download-retry (timeout 00:09:59) [common]
47 11:32:18.870013 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 11:32:18.870147 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:32:18.870209 saving as /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/kernel/Image
50 11:32:18.870263 total size: 54813184 (52 MB)
51 11:32:18.870318 No compression specified
52 11:32:18.871350 progress 0 % (0 MB)
53 11:32:18.885257 progress 5 % (2 MB)
54 11:32:18.899316 progress 10 % (5 MB)
55 11:32:18.913712 progress 15 % (7 MB)
56 11:32:18.928092 progress 20 % (10 MB)
57 11:32:18.942132 progress 25 % (13 MB)
58 11:32:18.956275 progress 30 % (15 MB)
59 11:32:18.972315 progress 35 % (18 MB)
60 11:32:18.988323 progress 40 % (20 MB)
61 11:32:19.003459 progress 45 % (23 MB)
62 11:32:19.017520 progress 50 % (26 MB)
63 11:32:19.032001 progress 55 % (28 MB)
64 11:32:19.046288 progress 60 % (31 MB)
65 11:32:19.060320 progress 65 % (34 MB)
66 11:32:19.074289 progress 70 % (36 MB)
67 11:32:19.088551 progress 75 % (39 MB)
68 11:32:19.102944 progress 80 % (41 MB)
69 11:32:19.116859 progress 85 % (44 MB)
70 11:32:19.130781 progress 90 % (47 MB)
71 11:32:19.144721 progress 95 % (49 MB)
72 11:32:19.158901 progress 100 % (52 MB)
73 11:32:19.159151 52 MB downloaded in 0.29 s (180.95 MB/s)
74 11:32:19.159303 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:32:19.159513 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:32:19.159595 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:32:19.159672 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:32:19.159803 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:32:19.159868 saving as /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/dtb/mt8192-asurada-spherion-r0.dtb
81 11:32:19.159923 total size: 47258 (0 MB)
82 11:32:19.159977 No compression specified
83 11:32:19.161017 progress 69 % (0 MB)
84 11:32:19.161291 progress 100 % (0 MB)
85 11:32:19.161448 0 MB downloaded in 0.00 s (29.60 MB/s)
86 11:32:19.161565 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:32:19.161767 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:32:19.161844 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:32:19.161920 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:32:19.162034 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:32:19.162097 saving as /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/modules/modules.tar
93 11:32:19.162151 total size: 8610184 (8 MB)
94 11:32:19.162206 Using unxz to decompress xz
95 11:32:19.163763 progress 0 % (0 MB)
96 11:32:19.185700 progress 5 % (0 MB)
97 11:32:19.211878 progress 10 % (0 MB)
98 11:32:19.237488 progress 15 % (1 MB)
99 11:32:19.263353 progress 20 % (1 MB)
100 11:32:19.288477 progress 25 % (2 MB)
101 11:32:19.313537 progress 30 % (2 MB)
102 11:32:19.337677 progress 35 % (2 MB)
103 11:32:19.365497 progress 40 % (3 MB)
104 11:32:19.391069 progress 45 % (3 MB)
105 11:32:19.416916 progress 50 % (4 MB)
106 11:32:19.443703 progress 55 % (4 MB)
107 11:32:19.469639 progress 60 % (4 MB)
108 11:32:19.494617 progress 65 % (5 MB)
109 11:32:19.521669 progress 70 % (5 MB)
110 11:32:19.550556 progress 75 % (6 MB)
111 11:32:19.579658 progress 80 % (6 MB)
112 11:32:19.604725 progress 85 % (7 MB)
113 11:32:19.629375 progress 90 % (7 MB)
114 11:32:19.654612 progress 95 % (7 MB)
115 11:32:19.678751 progress 100 % (8 MB)
116 11:32:19.684474 8 MB downloaded in 0.52 s (15.72 MB/s)
117 11:32:19.684660 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:32:19.684876 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:32:19.684957 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:32:19.685036 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:32:19.685110 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:32:19.685197 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:32:19.685369 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y
125 11:32:19.685488 makedir: /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin
126 11:32:19.685579 makedir: /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/tests
127 11:32:19.685668 makedir: /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/results
128 11:32:19.685757 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-add-keys
129 11:32:19.685890 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-add-sources
130 11:32:19.686012 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-background-process-start
131 11:32:19.686133 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-background-process-stop
132 11:32:19.686264 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-common-functions
133 11:32:19.686384 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-echo-ipv4
134 11:32:19.686502 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-install-packages
135 11:32:19.686619 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-installed-packages
136 11:32:19.686735 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-os-build
137 11:32:19.686851 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-probe-channel
138 11:32:19.686966 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-probe-ip
139 11:32:19.687081 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-target-ip
140 11:32:19.687198 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-target-mac
141 11:32:19.687312 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-target-storage
142 11:32:19.687430 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-case
143 11:32:19.687561 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-event
144 11:32:19.687677 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-feedback
145 11:32:19.687793 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-raise
146 11:32:19.687907 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-reference
147 11:32:19.688022 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-runner
148 11:32:19.688138 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-set
149 11:32:19.688252 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-test-shell
150 11:32:19.688368 Updating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-install-packages (oe)
151 11:32:19.688511 Updating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/bin/lava-installed-packages (oe)
152 11:32:19.688632 Creating /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/environment
153 11:32:19.688728 LAVA metadata
154 11:32:19.688794 - LAVA_JOB_ID=14864586
155 11:32:19.688850 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:32:19.688943 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:32:19.689004 skipped lava-vland-overlay
158 11:32:19.689071 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:32:19.689150 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:32:19.689206 skipped lava-multinode-overlay
161 11:32:19.689271 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:32:19.689342 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:32:19.689407 Loading test definitions
164 11:32:19.689482 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:32:19.689542 Using /lava-14864586 at stage 0
166 11:32:19.689838 uuid=14864586_1.5.2.3.1 testdef=None
167 11:32:19.689920 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:32:19.689996 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:32:19.690436 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:32:19.690637 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:32:19.691214 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:32:19.691423 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:32:19.691978 runner path: /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/0/tests/0_igt-kms-mediatek test_uuid 14864586_1.5.2.3.1
176 11:32:19.692131 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:32:19.692323 Creating lava-test-runner.conf files
179 11:32:19.692381 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864586/lava-overlay-h3d0bo7y/lava-14864586/0 for stage 0
180 11:32:19.692463 - 0_igt-kms-mediatek
181 11:32:19.692555 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:32:19.692631 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:32:19.698749 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:32:19.698865 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:32:19.698950 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:32:19.699029 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:32:19.699106 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:32:21.460508 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:32:21.460646 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:32:21.460754 extracting modules file /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864586/extract-overlay-ramdisk-zhjmqzgl/ramdisk
191 11:32:21.703557 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:32:21.703735 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:32:21.703816 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864586/compress-overlay-hbiy62kx/overlay-1.5.2.4.tar.gz to ramdisk
194 11:32:21.703878 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864586/compress-overlay-hbiy62kx/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864586/extract-overlay-ramdisk-zhjmqzgl/ramdisk
195 11:32:21.710324 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:32:21.710429 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:32:21.710512 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:32:21.710590 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:32:21.710656 Building ramdisk /var/lib/lava/dispatcher/tmp/14864586/extract-overlay-ramdisk-zhjmqzgl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864586/extract-overlay-ramdisk-zhjmqzgl/ramdisk
200 11:32:23.165967 >> 465549 blocks
201 11:32:29.857678 rename /var/lib/lava/dispatcher/tmp/14864586/extract-overlay-ramdisk-zhjmqzgl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/ramdisk/ramdisk.cpio.gz
202 11:32:29.857887 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 11:32:29.858010 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 11:32:29.858125 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 11:32:29.858230 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/kernel/Image']
206 11:32:45.736542 Returned 0 in 15 seconds
207 11:32:45.736740 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/kernel/image.itb
208 11:32:47.076254 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:32:47.076381 output: Created: Wed Jul 17 12:32:46 2024
210 11:32:47.076444 output: Image 0 (kernel-1)
211 11:32:47.076529 output: Description:
212 11:32:47.076617 output: Created: Wed Jul 17 12:32:46 2024
213 11:32:47.076703 output: Type: Kernel Image
214 11:32:47.076781 output: Compression: lzma compressed
215 11:32:47.076865 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:32:47.076944 output: Architecture: AArch64
217 11:32:47.077023 output: OS: Linux
218 11:32:47.077100 output: Load Address: 0x00000000
219 11:32:47.077188 output: Entry Point: 0x00000000
220 11:32:47.077265 output: Hash algo: crc32
221 11:32:47.077344 output: Hash value: 83448d17
222 11:32:47.077421 output: Image 1 (fdt-1)
223 11:32:47.077499 output: Description: mt8192-asurada-spherion-r0
224 11:32:47.077577 output: Created: Wed Jul 17 12:32:46 2024
225 11:32:47.077656 output: Type: Flat Device Tree
226 11:32:47.077734 output: Compression: uncompressed
227 11:32:47.077811 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:32:47.077891 output: Architecture: AArch64
229 11:32:47.077968 output: Hash algo: crc32
230 11:32:47.078048 output: Hash value: 0f8e4d2e
231 11:32:47.078124 output: Image 2 (ramdisk-1)
232 11:32:47.078202 output: Description: unavailable
233 11:32:47.078277 output: Created: Wed Jul 17 12:32:46 2024
234 11:32:47.078356 output: Type: RAMDisk Image
235 11:32:47.078432 output: Compression: uncompressed
236 11:32:47.078509 output: Data Size: 60986419 Bytes = 59557.05 KiB = 58.16 MiB
237 11:32:47.078594 output: Architecture: AArch64
238 11:32:47.078671 output: OS: Linux
239 11:32:47.078736 output: Load Address: unavailable
240 11:32:47.078785 output: Entry Point: unavailable
241 11:32:47.078858 output: Hash algo: crc32
242 11:32:47.078935 output: Hash value: e3d0586d
243 11:32:47.079016 output: Default Configuration: 'conf-1'
244 11:32:47.079092 output: Configuration 0 (conf-1)
245 11:32:47.079170 output: Description: mt8192-asurada-spherion-r0
246 11:32:47.079255 output: Kernel: kernel-1
247 11:32:47.079338 output: Init Ramdisk: ramdisk-1
248 11:32:47.079393 output: FDT: fdt-1
249 11:32:47.079443 output: Loadables: kernel-1
250 11:32:47.079505 output:
251 11:32:47.079647 end: 1.5.8.1 prepare-fit (duration 00:00:17) [common]
252 11:32:47.079765 end: 1.5.8 prepare-kernel (duration 00:00:17) [common]
253 11:32:47.079887 end: 1.5 prepare-tftp-overlay (duration 00:00:27) [common]
254 11:32:47.080000 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
255 11:32:47.080085 No LXC device requested
256 11:32:47.080184 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:32:47.080289 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
258 11:32:47.080361 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:32:47.080416 Checking files for TFTP limit of 4294967296 bytes.
260 11:32:47.080776 end: 1 tftp-deploy (duration 00:00:29) [common]
261 11:32:47.080863 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:32:47.080939 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:32:47.081024 substitutions:
264 11:32:47.081083 - {DTB}: 14864586/tftp-deploy-tnkxt4xu/dtb/mt8192-asurada-spherion-r0.dtb
265 11:32:47.081144 - {INITRD}: 14864586/tftp-deploy-tnkxt4xu/ramdisk/ramdisk.cpio.gz
266 11:32:47.081200 - {KERNEL}: 14864586/tftp-deploy-tnkxt4xu/kernel/Image
267 11:32:47.081251 - {LAVA_MAC}: None
268 11:32:47.081302 - {PRESEED_CONFIG}: None
269 11:32:47.081351 - {PRESEED_LOCAL}: None
270 11:32:47.081400 - {RAMDISK}: 14864586/tftp-deploy-tnkxt4xu/ramdisk/ramdisk.cpio.gz
271 11:32:47.081459 - {ROOT_PART}: None
272 11:32:47.081510 - {ROOT}: None
273 11:32:47.081558 - {SERVER_IP}: 192.168.201.1
274 11:32:47.081606 - {TEE}: None
275 11:32:47.081654 Parsed boot commands:
276 11:32:47.081700 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:32:47.081840 Parsed boot commands: tftpboot 192.168.201.1 14864586/tftp-deploy-tnkxt4xu/kernel/image.itb 14864586/tftp-deploy-tnkxt4xu/kernel/cmdline
278 11:32:47.081920 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:32:47.081992 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:32:47.082062 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:32:47.082131 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:32:47.082185 Not connected, no need to disconnect.
283 11:32:47.082250 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:32:47.082317 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:32:47.082370 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 11:32:47.085349 Setting prompt string to ['lava-test: # ']
287 11:32:47.085697 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:32:47.085817 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:32:47.085946 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:32:47.086056 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:32:47.086339 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=reboot']
292 11:32:56.308596 >> Command sent successfully.
293 11:32:56.325793 Returned 0 in 9 seconds
294 11:32:56.326610 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:32:56.328042 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:32:56.328523 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:32:56.329103 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:32:56.329557 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:32:56.329913 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:32:56.331473 [Enter `^Ec?' for help]
302 11:32:57.791222
303 11:32:57.791663
304 11:32:57.791961 F0: 102B 0000
305 11:32:57.792257
306 11:32:57.792525 F3: 1001 0000 [0200]
307 11:32:57.792793
308 11:32:57.795305 F3: 1001 0000
309 11:32:57.795692
310 11:32:57.795988 F7: 102D 0000
311 11:32:57.796278
312 11:32:57.796542 F1: 0000 0000
313 11:32:57.798537
314 11:32:57.798854 V0: 0000 0000 [0001]
315 11:32:57.799121
316 11:32:57.799378 00: 0007 8000
317 11:32:57.799642
318 11:32:57.802492 01: 0000 0000
319 11:32:57.802882
320 11:32:57.803180 BP: 0C00 0209 [0000]
321 11:32:57.803456
322 11:32:57.806172 G0: 1182 0000
323 11:32:57.806552
324 11:32:57.806844 EC: 0000 0021 [4000]
325 11:32:57.807123
326 11:32:57.809425 S7: 0000 0000 [0000]
327 11:32:57.809807
328 11:32:57.810101 CC: 0000 0000 [0001]
329 11:32:57.810378
330 11:32:57.813036 T0: 0000 0040 [010F]
331 11:32:57.813465
332 11:32:57.813765 Jump to BL
333 11:32:57.814040
334 11:32:57.838620
335 11:32:57.839033
336 11:32:57.845849 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:32:57.849429 ARM64: Exception handlers installed.
338 11:32:57.853598 ARM64: Testing exception
339 11:32:57.853982 ARM64: Done test exception
340 11:32:57.861255 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:32:57.872160 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:32:57.879057 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:32:57.889071 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:32:57.895251 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:32:57.905753 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:32:57.915485 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:32:57.921948 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:32:57.940759 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:32:57.944283 WDT: Last reset was cold boot
350 11:32:57.947213 SPI1(PAD0) initialized at 2873684 Hz
351 11:32:57.950748 SPI5(PAD0) initialized at 992727 Hz
352 11:32:57.953929 VBOOT: Loading verstage.
353 11:32:57.961118 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:32:57.964105 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:32:57.967747 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:32:57.970529 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:32:57.978179 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:32:57.985225 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:32:57.996016 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 11:32:57.996546
361 11:32:57.997017
362 11:32:58.005912 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:32:58.008929 ARM64: Exception handlers installed.
364 11:32:58.012538 ARM64: Testing exception
365 11:32:58.012965 ARM64: Done test exception
366 11:32:58.018945 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:32:58.022315 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:32:58.036576 Probing TPM: . done!
369 11:32:58.037114 TPM ready after 0 ms
370 11:32:58.043789 Connected to device vid:did:rid of 1ae0:0028:00
371 11:32:58.053452 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
372 11:32:58.089538 Initialized TPM device CR50 revision 0
373 11:32:58.101166 tlcl_send_startup: Startup return code is 0
374 11:32:58.101726 TPM: setup succeeded
375 11:32:58.112900 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:32:58.121300 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:32:58.131454 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:32:58.140572 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:32:58.143800 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:32:58.147506 in-header: 03 07 00 00 08 00 00 00
381 11:32:58.150840 in-data: aa e4 47 04 13 02 00 00
382 11:32:58.154501 Chrome EC: UHEPI supported
383 11:32:58.160567 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:32:58.164203 in-header: 03 a9 00 00 08 00 00 00
385 11:32:58.167742 in-data: 84 60 60 08 00 00 00 00
386 11:32:58.168129 Phase 1
387 11:32:58.174546 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:32:58.177131 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:32:58.184077 VB2:vb2_check_recovery() Recovery was requested manually
390 11:32:58.190424 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:32:58.190921 Recovery requested (1009000e)
392 11:32:58.199239 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:32:58.204571 tlcl_extend: response is 0
394 11:32:58.212647 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:32:58.218012 tlcl_extend: response is 0
396 11:32:58.224662 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:32:58.245423 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:32:58.251792 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:32:58.251921
400 11:32:58.252036
401 11:32:58.262024 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:32:58.265494 ARM64: Exception handlers installed.
403 11:32:58.268900 ARM64: Testing exception
404 11:32:58.269368 ARM64: Done test exception
405 11:32:58.291243 pmic_efuse_setting: Set efuses in 11 msecs
406 11:32:58.294394 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:32:58.301176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:32:58.304201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:32:58.311018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:32:58.314480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:32:58.320837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:32:58.324451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:32:58.327354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:32:58.334093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:32:58.337675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:32:58.344003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:32:58.347633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:32:58.350859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:32:58.357421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:32:58.364601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:32:58.367643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:32:58.374379 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:32:58.381355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:32:58.387173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:32:58.391238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:32:58.397432 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:32:58.404299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:32:58.407126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:32:58.414421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:32:58.420788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:32:58.424994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:32:58.432004 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:32:58.435655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:32:58.438741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:32:58.445935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:32:58.448849 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:32:58.455847 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:32:58.459935 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:32:58.466090 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:32:58.469588 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:32:58.475992 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:32:58.479356 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:32:58.486032 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:32:58.489002 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:32:58.492914 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:32:58.499627 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:32:58.502852 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:32:58.506120 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:32:58.513398 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:32:58.516494 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:32:58.519858 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:32:58.526550 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:32:58.529849 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:32:58.533036 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:32:58.536385 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:32:58.543026 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:32:58.546505 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:32:58.552994 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:32:58.563317 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:32:58.566426 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:32:58.576239 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:32:58.582541 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:32:58.589648 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:32:58.592479 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:32:58.595606 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:32:58.604167 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2
467 11:32:58.610674 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:32:58.613437 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 11:32:58.620442 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:32:58.628206 [RTC]rtc_get_frequency_meter,154: input=15, output=854
471 11:32:58.637691 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 11:32:58.647430 [RTC]rtc_get_frequency_meter,154: input=11, output=788
473 11:32:58.656958 [RTC]rtc_get_frequency_meter,154: input=13, output=821
474 11:32:58.666248 [RTC]rtc_get_frequency_meter,154: input=12, output=806
475 11:32:58.675860 [RTC]rtc_get_frequency_meter,154: input=11, output=790
476 11:32:58.685234 [RTC]rtc_get_frequency_meter,154: input=12, output=805
477 11:32:58.688077 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 11:32:58.695890 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 11:32:58.699157 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:32:58.702566 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 11:32:58.708832 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:32:58.712692 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 11:32:58.715885 ADC[4]: Raw value=904064 ID=7
484 11:32:58.716274 ADC[3]: Raw value=213916 ID=1
485 11:32:58.718809 RAM Code: 0x71
486 11:32:58.722629 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:32:58.728682 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:32:58.735630 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:32:58.742277 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:32:58.745562 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:32:58.749553 in-header: 03 07 00 00 08 00 00 00
492 11:32:58.752932 in-data: aa e4 47 04 13 02 00 00
493 11:32:58.756389 Chrome EC: UHEPI supported
494 11:32:58.762544 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:32:58.766684 in-header: 03 a9 00 00 08 00 00 00
496 11:32:58.769513 in-data: 84 60 60 08 00 00 00 00
497 11:32:58.772639 MRC: failed to locate region type 0.
498 11:32:58.779580 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:32:58.782432 DRAM-K: Running full calibration
500 11:32:58.788911 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:32:58.789124 header.status = 0x0
502 11:32:58.792271 header.version = 0x6 (expected: 0x6)
503 11:32:58.795899 header.size = 0xd00 (expected: 0xd00)
504 11:32:58.799096 header.flags = 0x0
505 11:32:58.805331 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:32:58.822880 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 11:32:58.829974 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:32:58.832682 dram_init: ddr_geometry: 2
509 11:32:58.836216 [EMI] MDL number = 2
510 11:32:58.836604 [EMI] Get MDL freq = 0
511 11:32:58.839442 dram_init: ddr_type: 0
512 11:32:58.839827 is_discrete_lpddr4: 1
513 11:32:58.842603 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:32:58.842989
515 11:32:58.843312
516 11:32:58.845873 [Bian_co] ETT version 0.0.0.1
517 11:32:58.852615 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:32:58.853167
519 11:32:58.855902 dramc_set_vcore_voltage set vcore to 650000
520 11:32:58.859269 Read voltage for 800, 4
521 11:32:58.859656 Vio18 = 0
522 11:32:58.859955 Vcore = 650000
523 11:32:58.862802 Vdram = 0
524 11:32:58.863186 Vddq = 0
525 11:32:58.863512 Vmddr = 0
526 11:32:58.866182 dram_init: config_dvfs: 1
527 11:32:58.869293 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:32:58.875792 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:32:58.878753 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:32:58.882164 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:32:58.885680 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:32:58.888724 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:32:58.892242 MEM_TYPE=3, freq_sel=18
534 11:32:58.895614 sv_algorithm_assistance_LP4_1600
535 11:32:58.899246 ============ PULL DRAM RESETB DOWN ============
536 11:32:58.905465 ========== PULL DRAM RESETB DOWN end =========
537 11:32:58.908952 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:32:58.912149 ===================================
539 11:32:58.915387 LPDDR4 DRAM CONFIGURATION
540 11:32:58.918714 ===================================
541 11:32:58.918931 EX_ROW_EN[0] = 0x0
542 11:32:58.922307 EX_ROW_EN[1] = 0x0
543 11:32:58.922521 LP4Y_EN = 0x0
544 11:32:58.925330 WORK_FSP = 0x0
545 11:32:58.925545 WL = 0x2
546 11:32:58.929005 RL = 0x2
547 11:32:58.929290 BL = 0x2
548 11:32:58.932121 RPST = 0x0
549 11:32:58.932460 RD_PRE = 0x0
550 11:32:58.935594 WR_PRE = 0x1
551 11:32:58.939220 WR_PST = 0x0
552 11:32:58.939622 DBI_WR = 0x0
553 11:32:58.942601 DBI_RD = 0x0
554 11:32:58.943012 OTF = 0x1
555 11:32:58.945444 ===================================
556 11:32:58.949211 ===================================
557 11:32:58.949612 ANA top config
558 11:32:58.952389 ===================================
559 11:32:58.955663 DLL_ASYNC_EN = 0
560 11:32:58.958994 ALL_SLAVE_EN = 1
561 11:32:58.962101 NEW_RANK_MODE = 1
562 11:32:58.965399 DLL_IDLE_MODE = 1
563 11:32:58.965678 LP45_APHY_COMB_EN = 1
564 11:32:58.968463 TX_ODT_DIS = 1
565 11:32:58.972039 NEW_8X_MODE = 1
566 11:32:58.975469 ===================================
567 11:32:58.978501 ===================================
568 11:32:58.982150 data_rate = 1600
569 11:32:58.985559 CKR = 1
570 11:32:58.985728 DQ_P2S_RATIO = 8
571 11:32:58.988534 ===================================
572 11:32:58.992150 CA_P2S_RATIO = 8
573 11:32:58.995560 DQ_CA_OPEN = 0
574 11:32:58.998531 DQ_SEMI_OPEN = 0
575 11:32:59.002046 CA_SEMI_OPEN = 0
576 11:32:59.004841 CA_FULL_RATE = 0
577 11:32:59.005007 DQ_CKDIV4_EN = 1
578 11:32:59.008570 CA_CKDIV4_EN = 1
579 11:32:59.012126 CA_PREDIV_EN = 0
580 11:32:59.015055 PH8_DLY = 0
581 11:32:59.018664 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:32:59.021565 DQ_AAMCK_DIV = 4
583 11:32:59.022047 CA_AAMCK_DIV = 4
584 11:32:59.025274 CA_ADMCK_DIV = 4
585 11:32:59.028522 DQ_TRACK_CA_EN = 0
586 11:32:59.031645 CA_PICK = 800
587 11:32:59.035000 CA_MCKIO = 800
588 11:32:59.038542 MCKIO_SEMI = 0
589 11:32:59.042058 PLL_FREQ = 3068
590 11:32:59.042457 DQ_UI_PI_RATIO = 32
591 11:32:59.045049 CA_UI_PI_RATIO = 0
592 11:32:59.048377 ===================================
593 11:32:59.051391 ===================================
594 11:32:59.054797 memory_type:LPDDR4
595 11:32:59.058336 GP_NUM : 10
596 11:32:59.058670 SRAM_EN : 1
597 11:32:59.061579 MD32_EN : 0
598 11:32:59.065121 ===================================
599 11:32:59.068124 [ANA_INIT] >>>>>>>>>>>>>>
600 11:32:59.068419 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:32:59.071204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:32:59.074794 ===================================
603 11:32:59.077841 data_rate = 1600,PCW = 0X7600
604 11:32:59.081632 ===================================
605 11:32:59.084914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:32:59.092055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:32:59.095515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:32:59.102859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:32:59.106720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:32:59.107110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:32:59.110830 [ANA_INIT] flow start
612 11:32:59.114403 [ANA_INIT] PLL >>>>>>>>
613 11:32:59.114933 [ANA_INIT] PLL <<<<<<<<
614 11:32:59.117813 [ANA_INIT] MIDPI >>>>>>>>
615 11:32:59.118326 [ANA_INIT] MIDPI <<<<<<<<
616 11:32:59.121747 [ANA_INIT] DLL >>>>>>>>
617 11:32:59.124624 [ANA_INIT] flow end
618 11:32:59.128071 ============ LP4 DIFF to SE enter ============
619 11:32:59.131472 ============ LP4 DIFF to SE exit ============
620 11:32:59.134823 [ANA_INIT] <<<<<<<<<<<<<
621 11:32:59.138449 [Flow] Enable top DCM control >>>>>
622 11:32:59.141407 [Flow] Enable top DCM control <<<<<
623 11:32:59.144968 Enable DLL master slave shuffle
624 11:32:59.148360 ==============================================================
625 11:32:59.151480 Gating Mode config
626 11:32:59.157966 ==============================================================
627 11:32:59.158495 Config description:
628 11:32:59.168101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:32:59.174709 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:32:59.178070 SELPH_MODE 0: By rank 1: By Phase
631 11:32:59.184315 ==============================================================
632 11:32:59.187843 GAT_TRACK_EN = 1
633 11:32:59.190901 RX_GATING_MODE = 2
634 11:32:59.194609 RX_GATING_TRACK_MODE = 2
635 11:32:59.197883 SELPH_MODE = 1
636 11:32:59.201455 PICG_EARLY_EN = 1
637 11:32:59.204695 VALID_LAT_VALUE = 1
638 11:32:59.207650 ==============================================================
639 11:32:59.211319 Enter into Gating configuration >>>>
640 11:32:59.214407 Exit from Gating configuration <<<<
641 11:32:59.217855 Enter into DVFS_PRE_config >>>>>
642 11:32:59.231202 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:32:59.231612 Exit from DVFS_PRE_config <<<<<
644 11:32:59.234560 Enter into PICG configuration >>>>
645 11:32:59.237796 Exit from PICG configuration <<<<
646 11:32:59.240915 [RX_INPUT] configuration >>>>>
647 11:32:59.244344 [RX_INPUT] configuration <<<<<
648 11:32:59.251331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:32:59.254591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:32:59.261126 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:32:59.267458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:32:59.274338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:32:59.280661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:32:59.284071 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:32:59.287115 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:32:59.290799 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:32:59.297508 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:32:59.300703 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:32:59.303593 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:32:59.307279 ===================================
661 11:32:59.310335 LPDDR4 DRAM CONFIGURATION
662 11:32:59.314130 ===================================
663 11:32:59.316857 EX_ROW_EN[0] = 0x0
664 11:32:59.317253 EX_ROW_EN[1] = 0x0
665 11:32:59.320853 LP4Y_EN = 0x0
666 11:32:59.321063 WORK_FSP = 0x0
667 11:32:59.323503 WL = 0x2
668 11:32:59.323770 RL = 0x2
669 11:32:59.326608 BL = 0x2
670 11:32:59.326838 RPST = 0x0
671 11:32:59.330265 RD_PRE = 0x0
672 11:32:59.330490 WR_PRE = 0x1
673 11:32:59.333291 WR_PST = 0x0
674 11:32:59.333472 DBI_WR = 0x0
675 11:32:59.336874 DBI_RD = 0x0
676 11:32:59.337087 OTF = 0x1
677 11:32:59.340383 ===================================
678 11:32:59.343836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:32:59.350248 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:32:59.353267 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:32:59.357005 ===================================
682 11:32:59.360146 LPDDR4 DRAM CONFIGURATION
683 11:32:59.363167 ===================================
684 11:32:59.363382 EX_ROW_EN[0] = 0x10
685 11:32:59.366724 EX_ROW_EN[1] = 0x0
686 11:32:59.369757 LP4Y_EN = 0x0
687 11:32:59.369953 WORK_FSP = 0x0
688 11:32:59.373550 WL = 0x2
689 11:32:59.373882 RL = 0x2
690 11:32:59.376662 BL = 0x2
691 11:32:59.377260 RPST = 0x0
692 11:32:59.380617 RD_PRE = 0x0
693 11:32:59.381165 WR_PRE = 0x1
694 11:32:59.383346 WR_PST = 0x0
695 11:32:59.383732 DBI_WR = 0x0
696 11:32:59.386596 DBI_RD = 0x0
697 11:32:59.386984 OTF = 0x1
698 11:32:59.390033 ===================================
699 11:32:59.396435 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:32:59.401206 nWR fixed to 40
701 11:32:59.404912 [ModeRegInit_LP4] CH0 RK0
702 11:32:59.405342 [ModeRegInit_LP4] CH0 RK1
703 11:32:59.407812 [ModeRegInit_LP4] CH1 RK0
704 11:32:59.411116 [ModeRegInit_LP4] CH1 RK1
705 11:32:59.411386 match AC timing 13
706 11:32:59.417701 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:32:59.420896 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:32:59.424328 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:32:59.431002 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:32:59.434091 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:32:59.437355 [EMI DOE] emi_dcm 0
712 11:32:59.440537 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:32:59.440743 ==
714 11:32:59.443893 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:32:59.447599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:32:59.447892 ==
717 11:32:59.453787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:32:59.460508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:32:59.468698 [CA 0] Center 37 (7~68) winsize 62
720 11:32:59.472123 [CA 1] Center 37 (7~68) winsize 62
721 11:32:59.475847 [CA 2] Center 34 (4~65) winsize 62
722 11:32:59.478444 [CA 3] Center 35 (4~66) winsize 63
723 11:32:59.481749 [CA 4] Center 33 (3~64) winsize 62
724 11:32:59.485387 [CA 5] Center 33 (3~64) winsize 62
725 11:32:59.485785
726 11:32:59.488895 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:32:59.489441
728 11:32:59.515432 [CATrainingPosCal] consider 1 rank data
729 11:32:59.515951 u2DelayCellTimex100 = 270/100 ps
730 11:32:59.516286 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:32:59.516576 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 11:32:59.516893 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:32:59.517354 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 11:32:59.518045 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 11:32:59.519016 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:32:59.519443
737 11:32:59.522000 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:32:59.522383
739 11:32:59.525575 [CBTSetCACLKResult] CA Dly = 33
740 11:32:59.525960 CS Dly: 5 (0~36)
741 11:32:59.526258 ==
742 11:32:59.528936 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:32:59.535227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:32:59.535621 ==
745 11:32:59.538660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:32:59.545088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:32:59.555167 [CA 0] Center 38 (7~69) winsize 63
748 11:32:59.557925 [CA 1] Center 37 (7~68) winsize 62
749 11:32:59.561563 [CA 2] Center 35 (4~66) winsize 63
750 11:32:59.564578 [CA 3] Center 35 (4~66) winsize 63
751 11:32:59.568029 [CA 4] Center 34 (3~65) winsize 63
752 11:32:59.571136 [CA 5] Center 33 (3~64) winsize 62
753 11:32:59.571321
754 11:32:59.574575 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:32:59.574714
756 11:32:59.578311 [CATrainingPosCal] consider 2 rank data
757 11:32:59.581317 u2DelayCellTimex100 = 270/100 ps
758 11:32:59.584814 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:32:59.588307 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:32:59.594874 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 11:32:59.598244 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 11:32:59.601702 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:32:59.605010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:32:59.605439
765 11:32:59.607969 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:32:59.608464
767 11:32:59.611482 [CBTSetCACLKResult] CA Dly = 33
768 11:32:59.611982 CS Dly: 6 (0~38)
769 11:32:59.614698
770 11:32:59.618243 ----->DramcWriteLeveling(PI) begin...
771 11:32:59.618615 ==
772 11:32:59.621125 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:32:59.625087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:32:59.625548 ==
775 11:32:59.628146 Write leveling (Byte 0): 34 => 34
776 11:32:59.631759 Write leveling (Byte 1): 29 => 29
777 11:32:59.634899 DramcWriteLeveling(PI) end<-----
778 11:32:59.635335
779 11:32:59.635642 ==
780 11:32:59.638393 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:32:59.641228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:32:59.641657 ==
783 11:32:59.644823 [Gating] SW mode calibration
784 11:32:59.651367 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:32:59.658004 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:32:59.661508 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:32:59.664396 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:32:59.667936 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 11:32:59.674792 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:32:59.678099 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:32:59.681465 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:32:59.687967 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:32:59.691546 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:32:59.694863 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:32:59.701557 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:32:59.704884 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:32:59.708300 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:32:59.714555 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:32:59.718052 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:32:59.721271 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:32:59.728349 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:32:59.731285 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:32:59.734499 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:32:59.741112 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 11:32:59.744432 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 11:32:59.747860 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:32:59.754698 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:32:59.758348 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:32:59.761319 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:32:59.764821 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:32:59.771168 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:32:59.774854 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
813 11:32:59.777906 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
814 11:32:59.784438 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:32:59.787618 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:32:59.791162 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:32:59.798126 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:32:59.800868 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:32:59.804197 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
820 11:32:59.811407 0 10 8 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
821 11:32:59.814434 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
822 11:32:59.818008 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:32:59.824392 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:32:59.827815 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:32:59.831173 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:32:59.837497 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:32:59.841202 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
828 11:32:59.844101 0 11 8 | B1->B0 | 2828 4242 | 1 0 | (0 0) (0 0)
829 11:32:59.850855 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
830 11:32:59.854339 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:32:59.857672 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:32:59.864407 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:32:59.867722 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:32:59.870789 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:32:59.877713 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:32:59.880714 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 11:32:59.884190 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:32:59.890618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:32:59.894065 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:32:59.897231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:32:59.904093 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:32:59.907744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:32:59.910853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:32:59.917834 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:32:59.920568 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:32:59.924025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:32:59.927470 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:32:59.933707 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:32:59.937008 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:32:59.940289 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:32:59.947404 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:32:59.950677 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 11:32:59.953922 Total UI for P1: 0, mck2ui 16
854 11:32:59.957127 best dqsien dly found for B0: ( 0, 14, 6)
855 11:32:59.960230 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:32:59.963807 Total UI for P1: 0, mck2ui 16
857 11:32:59.967142 best dqsien dly found for B1: ( 0, 14, 8)
858 11:32:59.970508 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 11:32:59.974125 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:32:59.976874
861 11:32:59.980195 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 11:32:59.983827 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:32:59.987144 [Gating] SW calibration Done
864 11:32:59.987529 ==
865 11:32:59.990049 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:32:59.993743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:32:59.994134 ==
868 11:32:59.994694 RX Vref Scan: 0
869 11:32:59.995060
870 11:32:59.997111 RX Vref 0 -> 0, step: 1
871 11:32:59.997538
872 11:33:00.000033 RX Delay -130 -> 252, step: 16
873 11:33:00.003619 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:33:00.007118 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 11:33:00.014101 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:33:00.017040 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:33:00.020063 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 11:33:00.023637 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 11:33:00.026963 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:33:00.033986 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:33:00.037020 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 11:33:00.039974 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 11:33:00.043801 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 11:33:00.046660 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:33:00.053598 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:33:00.056654 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 11:33:00.060159 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:33:00.063556 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:33:00.063938 ==
890 11:33:00.066299 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:33:00.073022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:33:00.073553 ==
893 11:33:00.074011 DQS Delay:
894 11:33:00.076091 DQS0 = 0, DQS1 = 0
895 11:33:00.076581 DQM Delay:
896 11:33:00.076884 DQM0 = 88, DQM1 = 74
897 11:33:00.079686 DQ Delay:
898 11:33:00.083307 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:33:00.086196 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 11:33:00.089801 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
901 11:33:00.092904 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 11:33:00.093323
903 11:33:00.093624
904 11:33:00.093899 ==
905 11:33:00.096412 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:33:00.099472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:33:00.099858 ==
908 11:33:00.100153
909 11:33:00.100438
910 11:33:00.103307 TX Vref Scan disable
911 11:33:00.106264 == TX Byte 0 ==
912 11:33:00.109322 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
913 11:33:00.112449 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
914 11:33:00.116204 == TX Byte 1 ==
915 11:33:00.119496 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 11:33:00.122631 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 11:33:00.123069 ==
918 11:33:00.126255 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:33:00.129483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:33:00.132277 ==
921 11:33:00.144402 TX Vref=22, minBit 0, minWin=27, winSum=443
922 11:33:00.147723 TX Vref=24, minBit 1, minWin=27, winSum=448
923 11:33:00.150980 TX Vref=26, minBit 5, minWin=27, winSum=450
924 11:33:00.154917 TX Vref=28, minBit 5, minWin=27, winSum=454
925 11:33:00.157439 TX Vref=30, minBit 5, minWin=27, winSum=450
926 11:33:00.164086 TX Vref=32, minBit 5, minWin=27, winSum=453
927 11:33:00.167701 [TxChooseVref] Worse bit 5, Min win 27, Win sum 454, Final Vref 28
928 11:33:00.167910
929 11:33:00.170959 Final TX Range 1 Vref 28
930 11:33:00.171173
931 11:33:00.171349 ==
932 11:33:00.173752 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:33:00.177430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:33:00.177638 ==
935 11:33:00.180616
936 11:33:00.180820
937 11:33:00.180978 TX Vref Scan disable
938 11:33:00.184076 == TX Byte 0 ==
939 11:33:00.187754 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
940 11:33:00.194347 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
941 11:33:00.194599 == TX Byte 1 ==
942 11:33:00.197231 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 11:33:00.204343 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 11:33:00.204656
945 11:33:00.204902 [DATLAT]
946 11:33:00.205199 Freq=800, CH0 RK0
947 11:33:00.205405
948 11:33:00.207327 DATLAT Default: 0xa
949 11:33:00.207582 0, 0xFFFF, sum = 0
950 11:33:00.210981 1, 0xFFFF, sum = 0
951 11:33:00.211338 2, 0xFFFF, sum = 0
952 11:33:00.213968 3, 0xFFFF, sum = 0
953 11:33:00.217252 4, 0xFFFF, sum = 0
954 11:33:00.217513 5, 0xFFFF, sum = 0
955 11:33:00.220763 6, 0xFFFF, sum = 0
956 11:33:00.221026 7, 0xFFFF, sum = 0
957 11:33:00.224522 8, 0xFFFF, sum = 0
958 11:33:00.224780 9, 0x0, sum = 1
959 11:33:00.227440 10, 0x0, sum = 2
960 11:33:00.227697 11, 0x0, sum = 3
961 11:33:00.227899 12, 0x0, sum = 4
962 11:33:00.231019 best_step = 10
963 11:33:00.231273
964 11:33:00.231471 ==
965 11:33:00.234224 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:33:00.237202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:33:00.237476 ==
968 11:33:00.241164 RX Vref Scan: 1
969 11:33:00.241418
970 11:33:00.241627 Set Vref Range= 32 -> 127
971 11:33:00.244251
972 11:33:00.244501 RX Vref 32 -> 127, step: 1
973 11:33:00.244715
974 11:33:00.247939 RX Delay -111 -> 252, step: 8
975 11:33:00.248193
976 11:33:00.250910 Set Vref, RX VrefLevel [Byte0]: 32
977 11:33:00.254069 [Byte1]: 32
978 11:33:00.254320
979 11:33:00.257199 Set Vref, RX VrefLevel [Byte0]: 33
980 11:33:00.260641 [Byte1]: 33
981 11:33:00.265183
982 11:33:00.265447 Set Vref, RX VrefLevel [Byte0]: 34
983 11:33:00.268161 [Byte1]: 34
984 11:33:00.272528
985 11:33:00.272854 Set Vref, RX VrefLevel [Byte0]: 35
986 11:33:00.275659 [Byte1]: 35
987 11:33:00.280242
988 11:33:00.280650 Set Vref, RX VrefLevel [Byte0]: 36
989 11:33:00.283420 [Byte1]: 36
990 11:33:00.287926
991 11:33:00.288314 Set Vref, RX VrefLevel [Byte0]: 37
992 11:33:00.291533 [Byte1]: 37
993 11:33:00.295294
994 11:33:00.295713 Set Vref, RX VrefLevel [Byte0]: 38
995 11:33:00.298773 [Byte1]: 38
996 11:33:00.302913
997 11:33:00.303378 Set Vref, RX VrefLevel [Byte0]: 39
998 11:33:00.306653 [Byte1]: 39
999 11:33:00.310725
1000 11:33:00.311123 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:33:00.313820 [Byte1]: 40
1002 11:33:00.318885
1003 11:33:00.319339 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:33:00.321647 [Byte1]: 41
1005 11:33:00.326134
1006 11:33:00.326310 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:33:00.328999 [Byte1]: 42
1008 11:33:00.333926
1009 11:33:00.334070 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:33:00.336587 [Byte1]: 43
1011 11:33:00.341168
1012 11:33:00.341290 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:33:00.344191 [Byte1]: 44
1014 11:33:00.348715
1015 11:33:00.348834 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:33:00.351960 [Byte1]: 45
1017 11:33:00.356146
1018 11:33:00.356266 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:33:00.359716 [Byte1]: 46
1020 11:33:00.363983
1021 11:33:00.364103 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:33:00.367124 [Byte1]: 47
1023 11:33:00.371604
1024 11:33:00.371737 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:33:00.374939 [Byte1]: 48
1026 11:33:00.379262
1027 11:33:00.379413 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:33:00.382732 [Byte1]: 49
1029 11:33:00.386948
1030 11:33:00.387359 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:33:00.390541 [Byte1]: 50
1032 11:33:00.395497
1033 11:33:00.395884 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:33:00.398451 [Byte1]: 51
1035 11:33:00.402495
1036 11:33:00.402880 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:33:00.406144 [Byte1]: 52
1038 11:33:00.410143
1039 11:33:00.410529 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:33:00.413441 [Byte1]: 53
1041 11:33:00.418072
1042 11:33:00.418456 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:33:00.421031 [Byte1]: 54
1044 11:33:00.425706
1045 11:33:00.426093 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:33:00.431783 [Byte1]: 55
1047 11:33:00.432171
1048 11:33:00.435724 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:33:00.438920 [Byte1]: 56
1050 11:33:00.439323
1051 11:33:00.441761 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:33:00.445112 [Byte1]: 57
1053 11:33:00.448664
1054 11:33:00.449049 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:33:00.451855 [Byte1]: 58
1056 11:33:00.455780
1057 11:33:00.455995 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:33:00.459324 [Byte1]: 59
1059 11:33:00.463559
1060 11:33:00.463960 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:33:00.467117 [Byte1]: 60
1062 11:33:00.471536
1063 11:33:00.471991 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:33:00.474626 [Byte1]: 61
1065 11:33:00.479087
1066 11:33:00.479616 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:33:00.482272 [Byte1]: 62
1068 11:33:00.487113
1069 11:33:00.487496 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:33:00.490261 [Byte1]: 63
1071 11:33:00.494020
1072 11:33:00.497851 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:33:00.498241 [Byte1]: 64
1074 11:33:00.501975
1075 11:33:00.502368 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:33:00.505240 [Byte1]: 65
1077 11:33:00.509388
1078 11:33:00.509999 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:33:00.512942 [Byte1]: 66
1080 11:33:00.517533
1081 11:33:00.517920 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:33:00.520415 [Byte1]: 67
1083 11:33:00.525441
1084 11:33:00.525859 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:33:00.528233 [Byte1]: 68
1086 11:33:00.532607
1087 11:33:00.533019 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:33:00.536033 [Byte1]: 69
1089 11:33:00.540088
1090 11:33:00.540391 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:33:00.543523 [Byte1]: 70
1092 11:33:00.547624
1093 11:33:00.547819 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:33:00.550990 [Byte1]: 71
1095 11:33:00.555020
1096 11:33:00.555188 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:33:00.558466 [Byte1]: 72
1098 11:33:00.562621
1099 11:33:00.562755 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:33:00.566376 [Byte1]: 73
1101 11:33:00.570198
1102 11:33:00.570323 Final RX Vref Byte 0 = 55 to rank0
1103 11:33:00.573915 Final RX Vref Byte 1 = 60 to rank0
1104 11:33:00.577483 Final RX Vref Byte 0 = 55 to rank1
1105 11:33:00.580073 Final RX Vref Byte 1 = 60 to rank1==
1106 11:33:00.583453 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 11:33:00.590507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 11:33:00.590588 ==
1109 11:33:00.590664 DQS Delay:
1110 11:33:00.590737 DQS0 = 0, DQS1 = 0
1111 11:33:00.593483 DQM Delay:
1112 11:33:00.593582 DQM0 = 87, DQM1 = 76
1113 11:33:00.597033 DQ Delay:
1114 11:33:00.600693 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1115 11:33:00.600771 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1116 11:33:00.603544 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1117 11:33:00.610260 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1118 11:33:00.610338
1119 11:33:00.610415
1120 11:33:00.616619 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1121 11:33:00.619980 CH0 RK0: MR19=606, MR18=2F29
1122 11:33:00.627002 CH0_RK0: MR19=0x606, MR18=0x2F29, DQSOSC=397, MR23=63, INC=93, DEC=62
1123 11:33:00.627154
1124 11:33:00.630070 ----->DramcWriteLeveling(PI) begin...
1125 11:33:00.630178 ==
1126 11:33:00.633573 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 11:33:00.637056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 11:33:00.637241 ==
1129 11:33:00.640017 Write leveling (Byte 0): 31 => 31
1130 11:33:00.643700 Write leveling (Byte 1): 27 => 27
1131 11:33:00.646573 DramcWriteLeveling(PI) end<-----
1132 11:33:00.646730
1133 11:33:00.646851 ==
1134 11:33:00.650155 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 11:33:00.653694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 11:33:00.653878 ==
1137 11:33:00.657243 [Gating] SW mode calibration
1138 11:33:00.663423 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 11:33:00.670395 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 11:33:00.673759 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1141 11:33:00.677098 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1142 11:33:00.683800 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1143 11:33:00.686866 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 11:33:00.690302 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 11:33:00.696824 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 11:33:00.700168 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 11:33:00.744086 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:33:00.744835 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:33:00.745352 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:33:00.745745 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:33:00.746126 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:33:00.746414 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:33:00.746710 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:33:00.746970 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:33:00.747223 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:33:00.747525 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1157 11:33:00.758055 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1158 11:33:00.758783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1159 11:33:00.761285 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:33:00.761672 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:33:00.767729 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:33:00.771200 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:33:00.774542 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:33:00.781066 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:33:00.784400 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1166 11:33:00.787735 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1167 11:33:00.794012 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 11:33:00.797533 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 11:33:00.801064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 11:33:00.804463 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 11:33:00.811182 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 11:33:00.814824 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 11:33:00.817589 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1174 11:33:00.824180 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1175 11:33:00.827620 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1176 11:33:00.830761 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:33:00.837442 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:33:00.840845 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:33:00.844433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:33:00.850541 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:33:00.854227 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1182 11:33:00.857383 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
1183 11:33:00.864049 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1184 11:33:00.867360 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 11:33:00.870779 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 11:33:00.877457 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 11:33:00.880677 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 11:33:00.884207 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:33:00.890946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1190 11:33:00.894045 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1191 11:33:00.897574 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 11:33:00.904028 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 11:33:00.907569 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 11:33:00.910401 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:33:00.917234 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:33:00.921057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:33:00.923793 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:33:00.930875 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:33:00.933739 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:33:00.937368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:33:00.943766 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:33:00.947243 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:33:00.950664 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:33:00.954042 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:33:00.960471 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1206 11:33:00.963213 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 11:33:00.966486 Total UI for P1: 0, mck2ui 16
1208 11:33:00.969799 best dqsien dly found for B0: ( 0, 14, 4)
1209 11:33:00.973535 Total UI for P1: 0, mck2ui 16
1210 11:33:00.976644 best dqsien dly found for B1: ( 0, 14, 4)
1211 11:33:00.979884 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1212 11:33:00.983425 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1213 11:33:00.983604
1214 11:33:00.986475 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1215 11:33:00.990238 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1216 11:33:00.993434 [Gating] SW calibration Done
1217 11:33:00.993603 ==
1218 11:33:00.996403 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 11:33:01.003508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1220 11:33:01.003748 ==
1221 11:33:01.003948 RX Vref Scan: 0
1222 11:33:01.004232
1223 11:33:01.006696 RX Vref 0 -> 0, step: 1
1224 11:33:01.006996
1225 11:33:01.010200 RX Delay -130 -> 252, step: 16
1226 11:33:01.013842 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1227 11:33:01.016756 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1228 11:33:01.020242 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1229 11:33:01.023276 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1230 11:33:01.030388 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1231 11:33:01.034391 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1232 11:33:01.036903 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1233 11:33:01.039953 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1234 11:33:01.043295 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1235 11:33:01.050466 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1236 11:33:01.053358 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1237 11:33:01.056900 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1238 11:33:01.059820 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1239 11:33:01.063879 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1240 11:33:01.070142 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1241 11:33:01.073282 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1242 11:33:01.073672 ==
1243 11:33:01.076573 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 11:33:01.079946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 11:33:01.080404 ==
1246 11:33:01.083031 DQS Delay:
1247 11:33:01.083461 DQS0 = 0, DQS1 = 0
1248 11:33:01.083758 DQM Delay:
1249 11:33:01.086441 DQM0 = 85, DQM1 = 76
1250 11:33:01.086829 DQ Delay:
1251 11:33:01.089433 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1252 11:33:01.092918 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1253 11:33:01.096178 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1254 11:33:01.099604 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 11:33:01.099879
1256 11:33:01.100092
1257 11:33:01.100288 ==
1258 11:33:01.103187 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 11:33:01.109407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 11:33:01.109683 ==
1261 11:33:01.109899
1262 11:33:01.110096
1263 11:33:01.110285 TX Vref Scan disable
1264 11:33:01.113132 == TX Byte 0 ==
1265 11:33:01.116562 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1266 11:33:01.123106 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1267 11:33:01.123409 == TX Byte 1 ==
1268 11:33:01.126795 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1269 11:33:01.133467 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1270 11:33:01.133742 ==
1271 11:33:01.136421 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 11:33:01.139950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 11:33:01.140314 ==
1274 11:33:01.152536 TX Vref=22, minBit 2, minWin=27, winSum=442
1275 11:33:01.155943 TX Vref=24, minBit 0, minWin=27, winSum=445
1276 11:33:01.159599 TX Vref=26, minBit 1, minWin=27, winSum=449
1277 11:33:01.162868 TX Vref=28, minBit 2, minWin=27, winSum=451
1278 11:33:01.166301 TX Vref=30, minBit 1, minWin=27, winSum=451
1279 11:33:01.172720 TX Vref=32, minBit 1, minWin=27, winSum=451
1280 11:33:01.175784 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1281 11:33:01.176145
1282 11:33:01.179028 Final TX Range 1 Vref 28
1283 11:33:01.179483
1284 11:33:01.179873 ==
1285 11:33:01.182754 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 11:33:01.185974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 11:33:01.189236 ==
1288 11:33:01.189607
1289 11:33:01.189880
1290 11:33:01.190136 TX Vref Scan disable
1291 11:33:01.192855 == TX Byte 0 ==
1292 11:33:01.195940 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1293 11:33:01.202605 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1294 11:33:01.202962 == TX Byte 1 ==
1295 11:33:01.206017 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1296 11:33:01.212520 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1297 11:33:01.212881
1298 11:33:01.213199 [DATLAT]
1299 11:33:01.213474 Freq=800, CH0 RK1
1300 11:33:01.213725
1301 11:33:01.215801 DATLAT Default: 0xa
1302 11:33:01.216165 0, 0xFFFF, sum = 0
1303 11:33:01.219358 1, 0xFFFF, sum = 0
1304 11:33:01.219744 2, 0xFFFF, sum = 0
1305 11:33:01.222757 3, 0xFFFF, sum = 0
1306 11:33:01.226197 4, 0xFFFF, sum = 0
1307 11:33:01.226640 5, 0xFFFF, sum = 0
1308 11:33:01.229580 6, 0xFFFF, sum = 0
1309 11:33:01.230083 7, 0xFFFF, sum = 0
1310 11:33:01.232566 8, 0xFFFF, sum = 0
1311 11:33:01.233084 9, 0x0, sum = 1
1312 11:33:01.233551 10, 0x0, sum = 2
1313 11:33:01.236068 11, 0x0, sum = 3
1314 11:33:01.236488 12, 0x0, sum = 4
1315 11:33:01.239246 best_step = 10
1316 11:33:01.239593
1317 11:33:01.239873 ==
1318 11:33:01.242178 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 11:33:01.245689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 11:33:01.245918 ==
1321 11:33:01.249134 RX Vref Scan: 0
1322 11:33:01.249343
1323 11:33:01.249494 RX Vref 0 -> 0, step: 1
1324 11:33:01.252342
1325 11:33:01.252611 RX Delay -95 -> 252, step: 8
1326 11:33:01.259427 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1327 11:33:01.262330 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1328 11:33:01.265889 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1329 11:33:01.269237 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1330 11:33:01.272444 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1331 11:33:01.278971 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1332 11:33:01.282144 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1333 11:33:01.285911 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1334 11:33:01.289007 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1335 11:33:01.292139 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1336 11:33:01.298825 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1337 11:33:01.302560 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1338 11:33:01.305524 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1339 11:33:01.309063 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1340 11:33:01.315309 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1341 11:33:01.318764 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1342 11:33:01.319058 ==
1343 11:33:01.322161 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 11:33:01.325390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 11:33:01.325694 ==
1346 11:33:01.328853 DQS Delay:
1347 11:33:01.329277 DQS0 = 0, DQS1 = 0
1348 11:33:01.329560 DQM Delay:
1349 11:33:01.332365 DQM0 = 86, DQM1 = 76
1350 11:33:01.332656 DQ Delay:
1351 11:33:01.335828 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1352 11:33:01.339138 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1353 11:33:01.342101 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1354 11:33:01.345537 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1355 11:33:01.345917
1356 11:33:01.346218
1357 11:33:01.355235 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1358 11:33:01.358778 CH0 RK1: MR19=606, MR18=2C29
1359 11:33:01.361812 CH0_RK1: MR19=0x606, MR18=0x2C29, DQSOSC=398, MR23=63, INC=93, DEC=62
1360 11:33:01.365382 [RxdqsGatingPostProcess] freq 800
1361 11:33:01.372041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1362 11:33:01.374972 Pre-setting of DQS Precalculation
1363 11:33:01.378665 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1364 11:33:01.379045 ==
1365 11:33:01.381615 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 11:33:01.388630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 11:33:01.389029 ==
1368 11:33:01.392055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1369 11:33:01.398911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1370 11:33:01.407556 [CA 0] Center 37 (6~68) winsize 63
1371 11:33:01.410896 [CA 1] Center 36 (6~67) winsize 62
1372 11:33:01.414464 [CA 2] Center 35 (5~66) winsize 62
1373 11:33:01.417898 [CA 3] Center 34 (4~65) winsize 62
1374 11:33:01.421025 [CA 4] Center 34 (4~65) winsize 62
1375 11:33:01.424399 [CA 5] Center 34 (4~65) winsize 62
1376 11:33:01.424806
1377 11:33:01.427865 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1378 11:33:01.428254
1379 11:33:01.430977 [CATrainingPosCal] consider 1 rank data
1380 11:33:01.434700 u2DelayCellTimex100 = 270/100 ps
1381 11:33:01.437618 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1382 11:33:01.444247 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1383 11:33:01.447698 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1384 11:33:01.450930 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1385 11:33:01.454610 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1386 11:33:01.457762 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1387 11:33:01.458151
1388 11:33:01.460804 CA PerBit enable=1, Macro0, CA PI delay=34
1389 11:33:01.461236
1390 11:33:01.464463 [CBTSetCACLKResult] CA Dly = 34
1391 11:33:01.464849 CS Dly: 4 (0~35)
1392 11:33:01.467474 ==
1393 11:33:01.467856 Dram Type= 6, Freq= 0, CH_1, rank 1
1394 11:33:01.474486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 11:33:01.474932 ==
1396 11:33:01.477378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 11:33:01.484325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 11:33:01.493860 [CA 0] Center 36 (6~67) winsize 62
1399 11:33:01.497459 [CA 1] Center 36 (6~67) winsize 62
1400 11:33:01.500753 [CA 2] Center 35 (4~66) winsize 63
1401 11:33:01.503948 [CA 3] Center 34 (4~65) winsize 62
1402 11:33:01.507257 [CA 4] Center 34 (4~65) winsize 62
1403 11:33:01.510475 [CA 5] Center 34 (4~65) winsize 62
1404 11:33:01.510930
1405 11:33:01.513904 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1406 11:33:01.514316
1407 11:33:01.517381 [CATrainingPosCal] consider 2 rank data
1408 11:33:01.521079 u2DelayCellTimex100 = 270/100 ps
1409 11:33:01.523775 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1410 11:33:01.527155 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 11:33:01.533698 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1412 11:33:01.537416 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 11:33:01.540287 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 11:33:01.543932 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 11:33:01.544320
1416 11:33:01.546891 CA PerBit enable=1, Macro0, CA PI delay=34
1417 11:33:01.547278
1418 11:33:01.550620 [CBTSetCACLKResult] CA Dly = 34
1419 11:33:01.551108 CS Dly: 5 (0~37)
1420 11:33:01.551416
1421 11:33:01.553857 ----->DramcWriteLeveling(PI) begin...
1422 11:33:01.556884 ==
1423 11:33:01.560769 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 11:33:01.563583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 11:33:01.564016 ==
1426 11:33:01.567105 Write leveling (Byte 0): 24 => 24
1427 11:33:01.570132 Write leveling (Byte 1): 25 => 25
1428 11:33:01.573749 DramcWriteLeveling(PI) end<-----
1429 11:33:01.574162
1430 11:33:01.574705 ==
1431 11:33:01.577205 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 11:33:01.580014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 11:33:01.580644 ==
1434 11:33:01.583495 [Gating] SW mode calibration
1435 11:33:01.589702 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1436 11:33:01.596468 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1437 11:33:01.600131 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1438 11:33:01.603995 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1439 11:33:01.609800 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 11:33:01.613345 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 11:33:01.616645 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 11:33:01.620316 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 11:33:01.626749 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 11:33:01.630246 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:33:01.633779 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:33:01.640530 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:33:01.643542 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:33:01.646539 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:33:01.653354 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:33:01.656298 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:33:01.659926 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:33:01.666229 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:33:01.669729 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:33:01.673339 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1455 11:33:01.679479 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:33:01.682527 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:33:01.686471 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:33:01.692822 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:33:01.696549 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:33:01.699479 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:33:01.706831 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:33:01.709590 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1463 11:33:01.713218 0 9 8 | B1->B0 | 2c2c 3131 | 0 1 | (0 0) (1 1)
1464 11:33:01.719688 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 11:33:01.723029 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 11:33:01.726268 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 11:33:01.732828 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 11:33:01.736178 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 11:33:01.739522 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1470 11:33:01.746060 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 1)
1471 11:33:01.749497 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1472 11:33:01.752931 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:33:01.758861 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:33:01.762737 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:33:01.766296 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:33:01.772616 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:33:01.776004 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:33:01.779120 0 11 4 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
1479 11:33:01.786164 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1480 11:33:01.789284 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 11:33:01.792504 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 11:33:01.795574 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 11:33:01.802491 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 11:33:01.805893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:33:01.809388 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:33:01.815797 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1487 11:33:01.819240 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1488 11:33:01.822611 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 11:33:01.828902 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 11:33:01.832356 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 11:33:01.835331 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 11:33:01.842130 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 11:33:01.845184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:33:01.848304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:33:01.854700 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:33:01.858674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:33:01.862236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:33:01.868662 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:33:01.872199 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:33:01.875321 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:33:01.882485 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:33:01.885478 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1503 11:33:01.888161 Total UI for P1: 0, mck2ui 16
1504 11:33:01.891999 best dqsien dly found for B0: ( 0, 14, 2)
1505 11:33:01.895360 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1506 11:33:01.901767 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 11:33:01.902408 Total UI for P1: 0, mck2ui 16
1508 11:33:01.908032 best dqsien dly found for B1: ( 0, 14, 6)
1509 11:33:01.911487 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1510 11:33:01.915071 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1511 11:33:01.915685
1512 11:33:01.918177 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1513 11:33:01.921841 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1514 11:33:01.924835 [Gating] SW calibration Done
1515 11:33:01.925270 ==
1516 11:33:01.928248 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 11:33:01.931029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 11:33:01.931251 ==
1519 11:33:01.934508 RX Vref Scan: 0
1520 11:33:01.934724
1521 11:33:01.934918 RX Vref 0 -> 0, step: 1
1522 11:33:01.935099
1523 11:33:01.937899 RX Delay -130 -> 252, step: 16
1524 11:33:01.941448 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1525 11:33:01.947732 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1526 11:33:01.951144 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1527 11:33:01.954800 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1528 11:33:01.958078 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1529 11:33:01.961378 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1530 11:33:01.968326 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1531 11:33:01.971257 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1532 11:33:01.974773 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1533 11:33:01.978045 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1534 11:33:01.981428 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1535 11:33:01.987785 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1536 11:33:01.992050 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1537 11:33:01.994417 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1538 11:33:01.997958 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1539 11:33:02.004476 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1540 11:33:02.005080 ==
1541 11:33:02.007991 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 11:33:02.011252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 11:33:02.011870 ==
1544 11:33:02.012463 DQS Delay:
1545 11:33:02.014699 DQS0 = 0, DQS1 = 0
1546 11:33:02.015105 DQM Delay:
1547 11:33:02.017615 DQM0 = 88, DQM1 = 82
1548 11:33:02.017886 DQ Delay:
1549 11:33:02.020795 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1550 11:33:02.024334 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1551 11:33:02.027563 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1552 11:33:02.030826 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1553 11:33:02.031107
1554 11:33:02.031317
1555 11:33:02.031510 ==
1556 11:33:02.034161 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 11:33:02.037595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 11:33:02.037871 ==
1559 11:33:02.038083
1560 11:33:02.040964
1561 11:33:02.041313 TX Vref Scan disable
1562 11:33:02.044346 == TX Byte 0 ==
1563 11:33:02.047552 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1564 11:33:02.051125 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1565 11:33:02.054362 == TX Byte 1 ==
1566 11:33:02.058032 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1567 11:33:02.061218 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1568 11:33:02.061620 ==
1569 11:33:02.065134 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:33:02.071256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:33:02.071804 ==
1572 11:33:02.082811 TX Vref=22, minBit 5, minWin=26, winSum=441
1573 11:33:02.086353 TX Vref=24, minBit 1, minWin=27, winSum=445
1574 11:33:02.089375 TX Vref=26, minBit 1, minWin=27, winSum=448
1575 11:33:02.092787 TX Vref=28, minBit 7, minWin=27, winSum=455
1576 11:33:02.096068 TX Vref=30, minBit 3, minWin=27, winSum=455
1577 11:33:02.102753 TX Vref=32, minBit 1, minWin=27, winSum=451
1578 11:33:02.105756 [TxChooseVref] Worse bit 7, Min win 27, Win sum 455, Final Vref 28
1579 11:33:02.106407
1580 11:33:02.109308 Final TX Range 1 Vref 28
1581 11:33:02.109907
1582 11:33:02.110439 ==
1583 11:33:02.112584 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 11:33:02.116140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 11:33:02.116554 ==
1586 11:33:02.119390
1587 11:33:02.119790
1588 11:33:02.120153 TX Vref Scan disable
1589 11:33:02.122786 == TX Byte 0 ==
1590 11:33:02.126143 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1591 11:33:02.132223 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1592 11:33:02.132498 == TX Byte 1 ==
1593 11:33:02.135751 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1594 11:33:02.143101 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1595 11:33:02.143609
1596 11:33:02.144052 [DATLAT]
1597 11:33:02.144471 Freq=800, CH1 RK0
1598 11:33:02.144903
1599 11:33:02.145986 DATLAT Default: 0xa
1600 11:33:02.146371 0, 0xFFFF, sum = 0
1601 11:33:02.149501 1, 0xFFFF, sum = 0
1602 11:33:02.149893 2, 0xFFFF, sum = 0
1603 11:33:02.152224 3, 0xFFFF, sum = 0
1604 11:33:02.156110 4, 0xFFFF, sum = 0
1605 11:33:02.156637 5, 0xFFFF, sum = 0
1606 11:33:02.159346 6, 0xFFFF, sum = 0
1607 11:33:02.159870 7, 0xFFFF, sum = 0
1608 11:33:02.162409 8, 0xFFFF, sum = 0
1609 11:33:02.162795 9, 0x0, sum = 1
1610 11:33:02.165714 10, 0x0, sum = 2
1611 11:33:02.166104 11, 0x0, sum = 3
1612 11:33:02.166407 12, 0x0, sum = 4
1613 11:33:02.169368 best_step = 10
1614 11:33:02.169783
1615 11:33:02.170082 ==
1616 11:33:02.172429 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 11:33:02.176011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 11:33:02.176565 ==
1619 11:33:02.179320 RX Vref Scan: 1
1620 11:33:02.179726
1621 11:33:02.182393 Set Vref Range= 32 -> 127
1622 11:33:02.182773
1623 11:33:02.183071 RX Vref 32 -> 127, step: 1
1624 11:33:02.183351
1625 11:33:02.186211 RX Delay -95 -> 252, step: 8
1626 11:33:02.186596
1627 11:33:02.188779 Set Vref, RX VrefLevel [Byte0]: 32
1628 11:33:02.192354 [Byte1]: 32
1629 11:33:02.192738
1630 11:33:02.195918 Set Vref, RX VrefLevel [Byte0]: 33
1631 11:33:02.198775 [Byte1]: 33
1632 11:33:02.202983
1633 11:33:02.203366 Set Vref, RX VrefLevel [Byte0]: 34
1634 11:33:02.206605 [Byte1]: 34
1635 11:33:02.210897
1636 11:33:02.211277 Set Vref, RX VrefLevel [Byte0]: 35
1637 11:33:02.214170 [Byte1]: 35
1638 11:33:02.218135
1639 11:33:02.218598 Set Vref, RX VrefLevel [Byte0]: 36
1640 11:33:02.221661 [Byte1]: 36
1641 11:33:02.225985
1642 11:33:02.226368 Set Vref, RX VrefLevel [Byte0]: 37
1643 11:33:02.229191 [Byte1]: 37
1644 11:33:02.233934
1645 11:33:02.234317 Set Vref, RX VrefLevel [Byte0]: 38
1646 11:33:02.236570 [Byte1]: 38
1647 11:33:02.240802
1648 11:33:02.241223 Set Vref, RX VrefLevel [Byte0]: 39
1649 11:33:02.244121 [Byte1]: 39
1650 11:33:02.248732
1651 11:33:02.249121 Set Vref, RX VrefLevel [Byte0]: 40
1652 11:33:02.251632 [Byte1]: 40
1653 11:33:02.256173
1654 11:33:02.256555 Set Vref, RX VrefLevel [Byte0]: 41
1655 11:33:02.259735 [Byte1]: 41
1656 11:33:02.263840
1657 11:33:02.264222 Set Vref, RX VrefLevel [Byte0]: 42
1658 11:33:02.267005 [Byte1]: 42
1659 11:33:02.271178
1660 11:33:02.274437 Set Vref, RX VrefLevel [Byte0]: 43
1661 11:33:02.277773 [Byte1]: 43
1662 11:33:02.278156
1663 11:33:02.281189 Set Vref, RX VrefLevel [Byte0]: 44
1664 11:33:02.284468 [Byte1]: 44
1665 11:33:02.284849
1666 11:33:02.287907 Set Vref, RX VrefLevel [Byte0]: 45
1667 11:33:02.291046 [Byte1]: 45
1668 11:33:02.294357
1669 11:33:02.294740 Set Vref, RX VrefLevel [Byte0]: 46
1670 11:33:02.297948 [Byte1]: 46
1671 11:33:02.301735
1672 11:33:02.302223 Set Vref, RX VrefLevel [Byte0]: 47
1673 11:33:02.305560 [Byte1]: 47
1674 11:33:02.309580
1675 11:33:02.310184 Set Vref, RX VrefLevel [Byte0]: 48
1676 11:33:02.312501 [Byte1]: 48
1677 11:33:02.316944
1678 11:33:02.317456 Set Vref, RX VrefLevel [Byte0]: 49
1679 11:33:02.320184 [Byte1]: 49
1680 11:33:02.324494
1681 11:33:02.324881 Set Vref, RX VrefLevel [Byte0]: 50
1682 11:33:02.327935 [Byte1]: 50
1683 11:33:02.331952
1684 11:33:02.332249 Set Vref, RX VrefLevel [Byte0]: 51
1685 11:33:02.335179 [Byte1]: 51
1686 11:33:02.339679
1687 11:33:02.339976 Set Vref, RX VrefLevel [Byte0]: 52
1688 11:33:02.342781 [Byte1]: 52
1689 11:33:02.347170
1690 11:33:02.347467 Set Vref, RX VrefLevel [Byte0]: 53
1691 11:33:02.350571 [Byte1]: 53
1692 11:33:02.355202
1693 11:33:02.355499 Set Vref, RX VrefLevel [Byte0]: 54
1694 11:33:02.358625 [Byte1]: 54
1695 11:33:02.362744
1696 11:33:02.363041 Set Vref, RX VrefLevel [Byte0]: 55
1697 11:33:02.365695 [Byte1]: 55
1698 11:33:02.369830
1699 11:33:02.373517 Set Vref, RX VrefLevel [Byte0]: 56
1700 11:33:02.377011 [Byte1]: 56
1701 11:33:02.377439
1702 11:33:02.380026 Set Vref, RX VrefLevel [Byte0]: 57
1703 11:33:02.383115 [Byte1]: 57
1704 11:33:02.383504
1705 11:33:02.386482 Set Vref, RX VrefLevel [Byte0]: 58
1706 11:33:02.390273 [Byte1]: 58
1707 11:33:02.390660
1708 11:33:02.393575 Set Vref, RX VrefLevel [Byte0]: 59
1709 11:33:02.396463 [Byte1]: 59
1710 11:33:02.400419
1711 11:33:02.400898 Set Vref, RX VrefLevel [Byte0]: 60
1712 11:33:02.404164 [Byte1]: 60
1713 11:33:02.408410
1714 11:33:02.408843 Set Vref, RX VrefLevel [Byte0]: 61
1715 11:33:02.411341 [Byte1]: 61
1716 11:33:02.415913
1717 11:33:02.416299 Set Vref, RX VrefLevel [Byte0]: 62
1718 11:33:02.419235 [Byte1]: 62
1719 11:33:02.423460
1720 11:33:02.423848 Set Vref, RX VrefLevel [Byte0]: 63
1721 11:33:02.426832 [Byte1]: 63
1722 11:33:02.431065
1723 11:33:02.431339 Set Vref, RX VrefLevel [Byte0]: 64
1724 11:33:02.433844 [Byte1]: 64
1725 11:33:02.438506
1726 11:33:02.438713 Set Vref, RX VrefLevel [Byte0]: 65
1727 11:33:02.441678 [Byte1]: 65
1728 11:33:02.446393
1729 11:33:02.446688 Set Vref, RX VrefLevel [Byte0]: 66
1730 11:33:02.449438 [Byte1]: 66
1731 11:33:02.453981
1732 11:33:02.454290 Set Vref, RX VrefLevel [Byte0]: 67
1733 11:33:02.456984 [Byte1]: 67
1734 11:33:02.461330
1735 11:33:02.461710 Set Vref, RX VrefLevel [Byte0]: 68
1736 11:33:02.464532 [Byte1]: 68
1737 11:33:02.468767
1738 11:33:02.472223 Set Vref, RX VrefLevel [Byte0]: 69
1739 11:33:02.472612 [Byte1]: 69
1740 11:33:02.476468
1741 11:33:02.476941 Set Vref, RX VrefLevel [Byte0]: 70
1742 11:33:02.479969 [Byte1]: 70
1743 11:33:02.484212
1744 11:33:02.484595 Set Vref, RX VrefLevel [Byte0]: 71
1745 11:33:02.487693 [Byte1]: 71
1746 11:33:02.492129
1747 11:33:02.492514 Final RX Vref Byte 0 = 60 to rank0
1748 11:33:02.494865 Final RX Vref Byte 1 = 58 to rank0
1749 11:33:02.498419 Final RX Vref Byte 0 = 60 to rank1
1750 11:33:02.501644 Final RX Vref Byte 1 = 58 to rank1==
1751 11:33:02.504775 Dram Type= 6, Freq= 0, CH_1, rank 0
1752 11:33:02.511406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1753 11:33:02.511795 ==
1754 11:33:02.512098 DQS Delay:
1755 11:33:02.515201 DQS0 = 0, DQS1 = 0
1756 11:33:02.515666 DQM Delay:
1757 11:33:02.515965 DQM0 = 87, DQM1 = 81
1758 11:33:02.517925 DQ Delay:
1759 11:33:02.521697 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1760 11:33:02.524990 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1761 11:33:02.528079 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1762 11:33:02.531323 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1763 11:33:02.531779
1764 11:33:02.532080
1765 11:33:02.537819 [DQSOSCAuto] RK0, (LSB)MR18= 0x2235, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
1766 11:33:02.541457 CH1 RK0: MR19=606, MR18=2235
1767 11:33:02.547965 CH1_RK0: MR19=0x606, MR18=0x2235, DQSOSC=396, MR23=63, INC=94, DEC=62
1768 11:33:02.548409
1769 11:33:02.551542 ----->DramcWriteLeveling(PI) begin...
1770 11:33:02.551939 ==
1771 11:33:02.554416 Dram Type= 6, Freq= 0, CH_1, rank 1
1772 11:33:02.557716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 11:33:02.558107 ==
1774 11:33:02.561596 Write leveling (Byte 0): 28 => 28
1775 11:33:02.564401 Write leveling (Byte 1): 29 => 29
1776 11:33:02.567929 DramcWriteLeveling(PI) end<-----
1777 11:33:02.568315
1778 11:33:02.568705 ==
1779 11:33:02.570821 Dram Type= 6, Freq= 0, CH_1, rank 1
1780 11:33:02.574872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 11:33:02.575264 ==
1782 11:33:02.577984 [Gating] SW mode calibration
1783 11:33:02.584148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1784 11:33:02.591008 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1785 11:33:02.593991 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1786 11:33:02.601181 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1787 11:33:02.604237 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1788 11:33:02.607473 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1789 11:33:02.614483 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1790 11:33:02.617585 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1791 11:33:02.621274 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1792 11:33:02.624701 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1793 11:33:02.631598 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1794 11:33:02.633927 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1795 11:33:02.637238 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 11:33:02.644191 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 11:33:02.647994 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 11:33:02.651147 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 11:33:02.657808 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 11:33:02.660861 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 11:33:02.664166 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1802 11:33:02.670976 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1803 11:33:02.674282 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1804 11:33:02.677408 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:33:02.683908 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:33:02.687395 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:33:02.690782 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:33:02.697428 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:33:02.700877 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:33:02.703892 0 9 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1811 11:33:02.710737 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1812 11:33:02.714254 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1813 11:33:02.717297 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1814 11:33:02.723846 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1815 11:33:02.727378 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1816 11:33:02.730339 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1817 11:33:02.737109 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1818 11:33:02.740412 0 10 4 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
1819 11:33:02.744066 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1820 11:33:02.747544 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:33:02.754469 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:33:02.757276 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:33:02.760492 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:33:02.767432 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:33:02.770730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:33:02.773980 0 11 4 | B1->B0 | 2828 3636 | 0 0 | (1 1) (0 0)
1827 11:33:02.780177 0 11 8 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1828 11:33:02.783548 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1829 11:33:02.787088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1830 11:33:02.793288 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1831 11:33:02.797068 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1832 11:33:02.800068 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1833 11:33:02.807063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1834 11:33:02.810106 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1835 11:33:02.813658 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1836 11:33:02.819908 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1837 11:33:02.823266 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1838 11:33:02.826745 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1839 11:33:02.833605 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1840 11:33:02.836894 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1841 11:33:02.840402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1842 11:33:02.847199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1843 11:33:02.849983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1844 11:33:02.853426 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 11:33:02.860453 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 11:33:02.863424 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 11:33:02.866958 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 11:33:02.873604 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 11:33:02.876696 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1850 11:33:02.880399 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1851 11:33:02.883368 Total UI for P1: 0, mck2ui 16
1852 11:33:02.886339 best dqsien dly found for B0: ( 0, 14, 0)
1853 11:33:02.893016 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:33:02.893480 Total UI for P1: 0, mck2ui 16
1855 11:33:02.896530 best dqsien dly found for B1: ( 0, 14, 4)
1856 11:33:02.903050 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1857 11:33:02.906740 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1858 11:33:02.907124
1859 11:33:02.909809 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1860 11:33:02.913394 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1861 11:33:02.916195 [Gating] SW calibration Done
1862 11:33:02.916577 ==
1863 11:33:02.919629 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 11:33:02.922892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 11:33:02.923278 ==
1866 11:33:02.925977 RX Vref Scan: 0
1867 11:33:02.926369
1868 11:33:02.926667 RX Vref 0 -> 0, step: 1
1869 11:33:02.926943
1870 11:33:02.929555 RX Delay -130 -> 252, step: 16
1871 11:33:02.932970 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1872 11:33:02.939589 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1873 11:33:02.942478 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1874 11:33:02.946119 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1875 11:33:02.949187 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1876 11:33:02.952694 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1877 11:33:02.959310 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1878 11:33:02.963083 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1879 11:33:02.966289 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1880 11:33:02.969685 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1881 11:33:02.972865 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1882 11:33:02.979548 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1883 11:33:02.982896 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1884 11:33:02.986254 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1885 11:33:02.989491 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1886 11:33:02.992404 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1887 11:33:02.995867 ==
1888 11:33:02.996036 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 11:33:03.002168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 11:33:03.002338 ==
1891 11:33:03.002470 DQS Delay:
1892 11:33:03.005592 DQS0 = 0, DQS1 = 0
1893 11:33:03.005761 DQM Delay:
1894 11:33:03.009084 DQM0 = 85, DQM1 = 81
1895 11:33:03.009317 DQ Delay:
1896 11:33:03.012465 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1897 11:33:03.015762 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1898 11:33:03.019287 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1899 11:33:03.022556 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1900 11:33:03.022752
1901 11:33:03.022895
1902 11:33:03.023082 ==
1903 11:33:03.025409 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 11:33:03.028942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 11:33:03.029204 ==
1906 11:33:03.029364
1907 11:33:03.029509
1908 11:33:03.033110 TX Vref Scan disable
1909 11:33:03.035523 == TX Byte 0 ==
1910 11:33:03.038795 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1911 11:33:03.042214 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1912 11:33:03.045948 == TX Byte 1 ==
1913 11:33:03.049110 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1914 11:33:03.052458 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1915 11:33:03.052914 ==
1916 11:33:03.056109 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 11:33:03.059126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 11:33:03.062622 ==
1919 11:33:03.073562 TX Vref=22, minBit 1, minWin=27, winSum=444
1920 11:33:03.076643 TX Vref=24, minBit 0, minWin=27, winSum=446
1921 11:33:03.080383 TX Vref=26, minBit 2, minWin=27, winSum=452
1922 11:33:03.083165 TX Vref=28, minBit 1, minWin=27, winSum=454
1923 11:33:03.086389 TX Vref=30, minBit 5, minWin=27, winSum=455
1924 11:33:03.093205 TX Vref=32, minBit 1, minWin=27, winSum=451
1925 11:33:03.096667 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 30
1926 11:33:03.096888
1927 11:33:03.099645 Final TX Range 1 Vref 30
1928 11:33:03.099810
1929 11:33:03.099938 ==
1930 11:33:03.102960 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 11:33:03.106561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 11:33:03.106735 ==
1933 11:33:03.109530
1934 11:33:03.109717
1935 11:33:03.109890 TX Vref Scan disable
1936 11:33:03.113541 == TX Byte 0 ==
1937 11:33:03.116499 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1938 11:33:03.123252 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1939 11:33:03.123485 == TX Byte 1 ==
1940 11:33:03.126414 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1941 11:33:03.133229 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1942 11:33:03.133466
1943 11:33:03.133644 [DATLAT]
1944 11:33:03.133806 Freq=800, CH1 RK1
1945 11:33:03.133962
1946 11:33:03.136178 DATLAT Default: 0xa
1947 11:33:03.136355 0, 0xFFFF, sum = 0
1948 11:33:03.139698 1, 0xFFFF, sum = 0
1949 11:33:03.143016 2, 0xFFFF, sum = 0
1950 11:33:03.143181 3, 0xFFFF, sum = 0
1951 11:33:03.146298 4, 0xFFFF, sum = 0
1952 11:33:03.146447 5, 0xFFFF, sum = 0
1953 11:33:03.149514 6, 0xFFFF, sum = 0
1954 11:33:03.149660 7, 0xFFFF, sum = 0
1955 11:33:03.152733 8, 0xFFFF, sum = 0
1956 11:33:03.152874 9, 0x0, sum = 1
1957 11:33:03.156038 10, 0x0, sum = 2
1958 11:33:03.156127 11, 0x0, sum = 3
1959 11:33:03.156194 12, 0x0, sum = 4
1960 11:33:03.159059 best_step = 10
1961 11:33:03.159173
1962 11:33:03.159242 ==
1963 11:33:03.162693 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 11:33:03.165550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 11:33:03.165626 ==
1966 11:33:03.169504 RX Vref Scan: 0
1967 11:33:03.169581
1968 11:33:03.172805 RX Vref 0 -> 0, step: 1
1969 11:33:03.173229
1970 11:33:03.173538 RX Delay -95 -> 252, step: 8
1971 11:33:03.179784 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1972 11:33:03.183612 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1973 11:33:03.187085 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1974 11:33:03.190389 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1975 11:33:03.193420 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1976 11:33:03.200127 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1977 11:33:03.203628 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1978 11:33:03.207101 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1979 11:33:03.210511 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1980 11:33:03.213542 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1981 11:33:03.219930 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1982 11:33:03.222922 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1983 11:33:03.226575 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1984 11:33:03.230550 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1985 11:33:03.236440 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1986 11:33:03.239849 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1987 11:33:03.240274 ==
1988 11:33:03.243275 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 11:33:03.246238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 11:33:03.246644 ==
1991 11:33:03.247012 DQS Delay:
1992 11:33:03.249569 DQS0 = 0, DQS1 = 0
1993 11:33:03.249952 DQM Delay:
1994 11:33:03.253168 DQM0 = 86, DQM1 = 83
1995 11:33:03.253557 DQ Delay:
1996 11:33:03.256045 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
1997 11:33:03.259414 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1998 11:33:03.263091 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =76
1999 11:33:03.266811 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2000 11:33:03.267292
2001 11:33:03.267615
2002 11:33:03.276369 [DQSOSCAuto] RK1, (LSB)MR18= 0x2541, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2003 11:33:03.276758 CH1 RK1: MR19=606, MR18=2541
2004 11:33:03.283364 CH1_RK1: MR19=0x606, MR18=0x2541, DQSOSC=393, MR23=63, INC=95, DEC=63
2005 11:33:03.286254 [RxdqsGatingPostProcess] freq 800
2006 11:33:03.292555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2007 11:33:03.296069 Pre-setting of DQS Precalculation
2008 11:33:03.299224 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2009 11:33:03.305898 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2010 11:33:03.315937 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2011 11:33:03.316155
2012 11:33:03.316293
2013 11:33:03.318885 [Calibration Summary] 1600 Mbps
2014 11:33:03.319053 CH 0, Rank 0
2015 11:33:03.322366 SW Impedance : PASS
2016 11:33:03.322583 DUTY Scan : NO K
2017 11:33:03.325871 ZQ Calibration : PASS
2018 11:33:03.329315 Jitter Meter : NO K
2019 11:33:03.329525 CBT Training : PASS
2020 11:33:03.332461 Write leveling : PASS
2021 11:33:03.332698 RX DQS gating : PASS
2022 11:33:03.335929 RX DQ/DQS(RDDQC) : PASS
2023 11:33:03.339018 TX DQ/DQS : PASS
2024 11:33:03.339258 RX DATLAT : PASS
2025 11:33:03.342700 RX DQ/DQS(Engine): PASS
2026 11:33:03.345975 TX OE : NO K
2027 11:33:03.346372 All Pass.
2028 11:33:03.346764
2029 11:33:03.347128 CH 0, Rank 1
2030 11:33:03.349297 SW Impedance : PASS
2031 11:33:03.352524 DUTY Scan : NO K
2032 11:33:03.352919 ZQ Calibration : PASS
2033 11:33:03.356050 Jitter Meter : NO K
2034 11:33:03.358828 CBT Training : PASS
2035 11:33:03.359212 Write leveling : PASS
2036 11:33:03.362631 RX DQS gating : PASS
2037 11:33:03.366045 RX DQ/DQS(RDDQC) : PASS
2038 11:33:03.366428 TX DQ/DQS : PASS
2039 11:33:03.369435 RX DATLAT : PASS
2040 11:33:03.372463 RX DQ/DQS(Engine): PASS
2041 11:33:03.372846 TX OE : NO K
2042 11:33:03.373176 All Pass.
2043 11:33:03.375758
2044 11:33:03.376144 CH 1, Rank 0
2045 11:33:03.378890 SW Impedance : PASS
2046 11:33:03.379276 DUTY Scan : NO K
2047 11:33:03.382140 ZQ Calibration : PASS
2048 11:33:03.382527 Jitter Meter : NO K
2049 11:33:03.385601 CBT Training : PASS
2050 11:33:03.389233 Write leveling : PASS
2051 11:33:03.389622 RX DQS gating : PASS
2052 11:33:03.392169 RX DQ/DQS(RDDQC) : PASS
2053 11:33:03.395980 TX DQ/DQS : PASS
2054 11:33:03.396367 RX DATLAT : PASS
2055 11:33:03.398851 RX DQ/DQS(Engine): PASS
2056 11:33:03.402103 TX OE : NO K
2057 11:33:03.402490 All Pass.
2058 11:33:03.402791
2059 11:33:03.403066 CH 1, Rank 1
2060 11:33:03.405605 SW Impedance : PASS
2061 11:33:03.409481 DUTY Scan : NO K
2062 11:33:03.409866 ZQ Calibration : PASS
2063 11:33:03.412145 Jitter Meter : NO K
2064 11:33:03.415375 CBT Training : PASS
2065 11:33:03.415760 Write leveling : PASS
2066 11:33:03.418996 RX DQS gating : PASS
2067 11:33:03.422143 RX DQ/DQS(RDDQC) : PASS
2068 11:33:03.422530 TX DQ/DQS : PASS
2069 11:33:03.425106 RX DATLAT : PASS
2070 11:33:03.429077 RX DQ/DQS(Engine): PASS
2071 11:33:03.429500 TX OE : NO K
2072 11:33:03.429804 All Pass.
2073 11:33:03.431933
2074 11:33:03.432359 DramC Write-DBI off
2075 11:33:03.435167 PER_BANK_REFRESH: Hybrid Mode
2076 11:33:03.435551 TX_TRACKING: ON
2077 11:33:03.438584 [GetDramInforAfterCalByMRR] Vendor 6.
2078 11:33:03.442289 [GetDramInforAfterCalByMRR] Revision 606.
2079 11:33:03.448672 [GetDramInforAfterCalByMRR] Revision 2 0.
2080 11:33:03.449097 MR0 0x3b3b
2081 11:33:03.449452 MR8 0x5151
2082 11:33:03.451983 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2083 11:33:03.452368
2084 11:33:03.455197 MR0 0x3b3b
2085 11:33:03.455580 MR8 0x5151
2086 11:33:03.458419 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2087 11:33:03.458802
2088 11:33:03.468446 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2089 11:33:03.472063 [FAST_K] Save calibration result to emmc
2090 11:33:03.479271 [FAST_K] Save calibration result to emmc
2091 11:33:03.480220 dram_init: config_dvfs: 1
2092 11:33:03.482090 dramc_set_vcore_voltage set vcore to 662500
2093 11:33:03.485585 Read voltage for 1200, 2
2094 11:33:03.485965 Vio18 = 0
2095 11:33:03.486262 Vcore = 662500
2096 11:33:03.488517 Vdram = 0
2097 11:33:03.489051 Vddq = 0
2098 11:33:03.489644 Vmddr = 0
2099 11:33:03.494898 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2100 11:33:03.498633 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2101 11:33:03.501483 MEM_TYPE=3, freq_sel=15
2102 11:33:03.504925 sv_algorithm_assistance_LP4_1600
2103 11:33:03.508691 ============ PULL DRAM RESETB DOWN ============
2104 11:33:03.512323 ========== PULL DRAM RESETB DOWN end =========
2105 11:33:03.518397 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2106 11:33:03.522054 ===================================
2107 11:33:03.522669 LPDDR4 DRAM CONFIGURATION
2108 11:33:03.525562 ===================================
2109 11:33:03.528392 EX_ROW_EN[0] = 0x0
2110 11:33:03.531836 EX_ROW_EN[1] = 0x0
2111 11:33:03.532100 LP4Y_EN = 0x0
2112 11:33:03.535145 WORK_FSP = 0x0
2113 11:33:03.535365 WL = 0x4
2114 11:33:03.538161 RL = 0x4
2115 11:33:03.538337 BL = 0x2
2116 11:33:03.541400 RPST = 0x0
2117 11:33:03.541615 RD_PRE = 0x0
2118 11:33:03.544774 WR_PRE = 0x1
2119 11:33:03.544978 WR_PST = 0x0
2120 11:33:03.548212 DBI_WR = 0x0
2121 11:33:03.548460 DBI_RD = 0x0
2122 11:33:03.551832 OTF = 0x1
2123 11:33:03.554660 ===================================
2124 11:33:03.558924 ===================================
2125 11:33:03.559309 ANA top config
2126 11:33:03.561683 ===================================
2127 11:33:03.564684 DLL_ASYNC_EN = 0
2128 11:33:03.568534 ALL_SLAVE_EN = 0
2129 11:33:03.568922 NEW_RANK_MODE = 1
2130 11:33:03.571851 DLL_IDLE_MODE = 1
2131 11:33:03.574880 LP45_APHY_COMB_EN = 1
2132 11:33:03.578441 TX_ODT_DIS = 1
2133 11:33:03.581482 NEW_8X_MODE = 1
2134 11:33:03.585007 ===================================
2135 11:33:03.588168 ===================================
2136 11:33:03.588557 data_rate = 2400
2137 11:33:03.591648 CKR = 1
2138 11:33:03.594851 DQ_P2S_RATIO = 8
2139 11:33:03.598187 ===================================
2140 11:33:03.601415 CA_P2S_RATIO = 8
2141 11:33:03.604379 DQ_CA_OPEN = 0
2142 11:33:03.608220 DQ_SEMI_OPEN = 0
2143 11:33:03.608605 CA_SEMI_OPEN = 0
2144 11:33:03.611192 CA_FULL_RATE = 0
2145 11:33:03.614410 DQ_CKDIV4_EN = 0
2146 11:33:03.617684 CA_CKDIV4_EN = 0
2147 11:33:03.621390 CA_PREDIV_EN = 0
2148 11:33:03.624643 PH8_DLY = 17
2149 11:33:03.625065 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2150 11:33:03.628324 DQ_AAMCK_DIV = 4
2151 11:33:03.631541 CA_AAMCK_DIV = 4
2152 11:33:03.634827 CA_ADMCK_DIV = 4
2153 11:33:03.637697 DQ_TRACK_CA_EN = 0
2154 11:33:03.642079 CA_PICK = 1200
2155 11:33:03.644422 CA_MCKIO = 1200
2156 11:33:03.644900 MCKIO_SEMI = 0
2157 11:33:03.647578 PLL_FREQ = 2366
2158 11:33:03.651291 DQ_UI_PI_RATIO = 32
2159 11:33:03.654605 CA_UI_PI_RATIO = 0
2160 11:33:03.657639 ===================================
2161 11:33:03.661100 ===================================
2162 11:33:03.664204 memory_type:LPDDR4
2163 11:33:03.664687 GP_NUM : 10
2164 11:33:03.667522 SRAM_EN : 1
2165 11:33:03.670727 MD32_EN : 0
2166 11:33:03.674398 ===================================
2167 11:33:03.674822 [ANA_INIT] >>>>>>>>>>>>>>
2168 11:33:03.677480 <<<<<< [CONFIGURE PHASE]: ANA_TX
2169 11:33:03.680934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2170 11:33:03.683985 ===================================
2171 11:33:03.687702 data_rate = 2400,PCW = 0X5b00
2172 11:33:03.690900 ===================================
2173 11:33:03.693882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2174 11:33:03.700948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2175 11:33:03.704480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2176 11:33:03.711055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2177 11:33:03.713807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2178 11:33:03.717167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2179 11:33:03.717702 [ANA_INIT] flow start
2180 11:33:03.720625 [ANA_INIT] PLL >>>>>>>>
2181 11:33:03.723871 [ANA_INIT] PLL <<<<<<<<
2182 11:33:03.727567 [ANA_INIT] MIDPI >>>>>>>>
2183 11:33:03.728015 [ANA_INIT] MIDPI <<<<<<<<
2184 11:33:03.730979 [ANA_INIT] DLL >>>>>>>>
2185 11:33:03.733819 [ANA_INIT] DLL <<<<<<<<
2186 11:33:03.734354 [ANA_INIT] flow end
2187 11:33:03.737385 ============ LP4 DIFF to SE enter ============
2188 11:33:03.743958 ============ LP4 DIFF to SE exit ============
2189 11:33:03.744511 [ANA_INIT] <<<<<<<<<<<<<
2190 11:33:03.747083 [Flow] Enable top DCM control >>>>>
2191 11:33:03.750717 [Flow] Enable top DCM control <<<<<
2192 11:33:03.754180 Enable DLL master slave shuffle
2193 11:33:03.760647 ==============================================================
2194 11:33:03.761187 Gating Mode config
2195 11:33:03.767249 ==============================================================
2196 11:33:03.770204 Config description:
2197 11:33:03.780387 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2198 11:33:03.787246 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2199 11:33:03.790407 SELPH_MODE 0: By rank 1: By Phase
2200 11:33:03.796856 ==============================================================
2201 11:33:03.799953 GAT_TRACK_EN = 1
2202 11:33:03.803556 RX_GATING_MODE = 2
2203 11:33:03.803959 RX_GATING_TRACK_MODE = 2
2204 11:33:03.806954 SELPH_MODE = 1
2205 11:33:03.810371 PICG_EARLY_EN = 1
2206 11:33:03.813403 VALID_LAT_VALUE = 1
2207 11:33:03.820604 ==============================================================
2208 11:33:03.823514 Enter into Gating configuration >>>>
2209 11:33:03.826727 Exit from Gating configuration <<<<
2210 11:33:03.830219 Enter into DVFS_PRE_config >>>>>
2211 11:33:03.840299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2212 11:33:03.843221 Exit from DVFS_PRE_config <<<<<
2213 11:33:03.846840 Enter into PICG configuration >>>>
2214 11:33:03.849970 Exit from PICG configuration <<<<
2215 11:33:03.853658 [RX_INPUT] configuration >>>>>
2216 11:33:03.856492 [RX_INPUT] configuration <<<<<
2217 11:33:03.859973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2218 11:33:03.866711 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2219 11:33:03.873177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2220 11:33:03.879715 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2221 11:33:03.883376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2222 11:33:03.890160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2223 11:33:03.893104 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2224 11:33:03.899609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2225 11:33:03.903001 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2226 11:33:03.906676 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2227 11:33:03.909584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2228 11:33:03.916523 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2229 11:33:03.919575 ===================================
2230 11:33:03.920108 LPDDR4 DRAM CONFIGURATION
2231 11:33:03.922791 ===================================
2232 11:33:03.926242 EX_ROW_EN[0] = 0x0
2233 11:33:03.930249 EX_ROW_EN[1] = 0x0
2234 11:33:03.930782 LP4Y_EN = 0x0
2235 11:33:03.933040 WORK_FSP = 0x0
2236 11:33:03.933617 WL = 0x4
2237 11:33:03.936366 RL = 0x4
2238 11:33:03.936885 BL = 0x2
2239 11:33:03.939567 RPST = 0x0
2240 11:33:03.940055 RD_PRE = 0x0
2241 11:33:03.943492 WR_PRE = 0x1
2242 11:33:03.944004 WR_PST = 0x0
2243 11:33:03.946674 DBI_WR = 0x0
2244 11:33:03.947091 DBI_RD = 0x0
2245 11:33:03.949607 OTF = 0x1
2246 11:33:03.953500 ===================================
2247 11:33:03.956251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2248 11:33:03.959897 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2249 11:33:03.966389 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 11:33:03.969787 ===================================
2251 11:33:03.970294 LPDDR4 DRAM CONFIGURATION
2252 11:33:03.973017 ===================================
2253 11:33:03.976841 EX_ROW_EN[0] = 0x10
2254 11:33:03.979704 EX_ROW_EN[1] = 0x0
2255 11:33:03.980087 LP4Y_EN = 0x0
2256 11:33:03.983060 WORK_FSP = 0x0
2257 11:33:03.983453 WL = 0x4
2258 11:33:03.986239 RL = 0x4
2259 11:33:03.986643 BL = 0x2
2260 11:33:03.989861 RPST = 0x0
2261 11:33:03.990269 RD_PRE = 0x0
2262 11:33:03.993345 WR_PRE = 0x1
2263 11:33:03.993742 WR_PST = 0x0
2264 11:33:03.996148 DBI_WR = 0x0
2265 11:33:03.996553 DBI_RD = 0x0
2266 11:33:04.000100 OTF = 0x1
2267 11:33:04.003241 ===================================
2268 11:33:04.009620 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2269 11:33:04.010026 ==
2270 11:33:04.012989 Dram Type= 6, Freq= 0, CH_0, rank 0
2271 11:33:04.016155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2272 11:33:04.016610 ==
2273 11:33:04.019632 [Duty_Offset_Calibration]
2274 11:33:04.020046 B0:2 B1:0 CA:4
2275 11:33:04.020345
2276 11:33:04.023116 [DutyScan_Calibration_Flow] k_type=0
2277 11:33:04.032206
2278 11:33:04.032585 ==CLK 0==
2279 11:33:04.035081 Final CLK duty delay cell = -4
2280 11:33:04.038339 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2281 11:33:04.042102 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2282 11:33:04.045522 [-4] AVG Duty = 4937%(X100)
2283 11:33:04.045965
2284 11:33:04.049129 CH0 CLK Duty spec in!! Max-Min= 187%
2285 11:33:04.052173 [DutyScan_Calibration_Flow] ====Done====
2286 11:33:04.052555
2287 11:33:04.055249 [DutyScan_Calibration_Flow] k_type=1
2288 11:33:04.072366
2289 11:33:04.072748 ==DQS 0 ==
2290 11:33:04.075082 Final DQS duty delay cell = 0
2291 11:33:04.077928 [0] MAX Duty = 5156%(X100), DQS PI = 18
2292 11:33:04.081510 [0] MIN Duty = 5093%(X100), DQS PI = 0
2293 11:33:04.084498 [0] AVG Duty = 5124%(X100)
2294 11:33:04.084879
2295 11:33:04.085203 ==DQS 1 ==
2296 11:33:04.088261 Final DQS duty delay cell = 0
2297 11:33:04.091080 [0] MAX Duty = 5125%(X100), DQS PI = 4
2298 11:33:04.094503 [0] MIN Duty = 5000%(X100), DQS PI = 0
2299 11:33:04.097903 [0] AVG Duty = 5062%(X100)
2300 11:33:04.098297
2301 11:33:04.100939 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2302 11:33:04.101413
2303 11:33:04.104776 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2304 11:33:04.108052 [DutyScan_Calibration_Flow] ====Done====
2305 11:33:04.108433
2306 11:33:04.111039 [DutyScan_Calibration_Flow] k_type=3
2307 11:33:04.127492
2308 11:33:04.127806 ==DQM 0 ==
2309 11:33:04.130795 Final DQM duty delay cell = 0
2310 11:33:04.134091 [0] MAX Duty = 5093%(X100), DQS PI = 20
2311 11:33:04.137590 [0] MIN Duty = 4844%(X100), DQS PI = 50
2312 11:33:04.140810 [0] AVG Duty = 4968%(X100)
2313 11:33:04.141109
2314 11:33:04.141389 ==DQM 1 ==
2315 11:33:04.144070 Final DQM duty delay cell = 0
2316 11:33:04.147612 [0] MAX Duty = 4969%(X100), DQS PI = 2
2317 11:33:04.151080 [0] MIN Duty = 4875%(X100), DQS PI = 20
2318 11:33:04.151318 [0] AVG Duty = 4922%(X100)
2319 11:33:04.154397
2320 11:33:04.158191 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2321 11:33:04.158631
2322 11:33:04.160873 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2323 11:33:04.164581 [DutyScan_Calibration_Flow] ====Done====
2324 11:33:04.165065
2325 11:33:04.167685 [DutyScan_Calibration_Flow] k_type=2
2326 11:33:04.184136
2327 11:33:04.184608 ==DQ 0 ==
2328 11:33:04.187521 Final DQ duty delay cell = 0
2329 11:33:04.191452 [0] MAX Duty = 5125%(X100), DQS PI = 18
2330 11:33:04.194406 [0] MIN Duty = 4969%(X100), DQS PI = 58
2331 11:33:04.194864 [0] AVG Duty = 5047%(X100)
2332 11:33:04.197614
2333 11:33:04.197941 ==DQ 1 ==
2334 11:33:04.200909 Final DQ duty delay cell = 0
2335 11:33:04.204013 [0] MAX Duty = 5156%(X100), DQS PI = 6
2336 11:33:04.207740 [0] MIN Duty = 4938%(X100), DQS PI = 14
2337 11:33:04.208184 [0] AVG Duty = 5047%(X100)
2338 11:33:04.208511
2339 11:33:04.211133 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2340 11:33:04.214081
2341 11:33:04.217257 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2342 11:33:04.221033 [DutyScan_Calibration_Flow] ====Done====
2343 11:33:04.221501 ==
2344 11:33:04.223952 Dram Type= 6, Freq= 0, CH_1, rank 0
2345 11:33:04.227445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 11:33:04.227929 ==
2347 11:33:04.230540 [Duty_Offset_Calibration]
2348 11:33:04.230932 B0:0 B1:-1 CA:3
2349 11:33:04.231255
2350 11:33:04.233927 [DutyScan_Calibration_Flow] k_type=0
2351 11:33:04.243753
2352 11:33:04.244181 ==CLK 0==
2353 11:33:04.247276 Final CLK duty delay cell = -4
2354 11:33:04.250466 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2355 11:33:04.253179 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2356 11:33:04.256745 [-4] AVG Duty = 4938%(X100)
2357 11:33:04.257360
2358 11:33:04.260224 CH1 CLK Duty spec in!! Max-Min= 124%
2359 11:33:04.263571 [DutyScan_Calibration_Flow] ====Done====
2360 11:33:04.263946
2361 11:33:04.266890 [DutyScan_Calibration_Flow] k_type=1
2362 11:33:04.282818
2363 11:33:04.283201 ==DQS 0 ==
2364 11:33:04.286835 Final DQS duty delay cell = 0
2365 11:33:04.289429 [0] MAX Duty = 5156%(X100), DQS PI = 18
2366 11:33:04.292890 [0] MIN Duty = 4907%(X100), DQS PI = 38
2367 11:33:04.296080 [0] AVG Duty = 5031%(X100)
2368 11:33:04.296485
2369 11:33:04.296782 ==DQS 1 ==
2370 11:33:04.299660 Final DQS duty delay cell = 0
2371 11:33:04.302816 [0] MAX Duty = 5156%(X100), DQS PI = 8
2372 11:33:04.306249 [0] MIN Duty = 5031%(X100), DQS PI = 24
2373 11:33:04.306637 [0] AVG Duty = 5093%(X100)
2374 11:33:04.309521
2375 11:33:04.313419 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2376 11:33:04.313808
2377 11:33:04.316109 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2378 11:33:04.319407 [DutyScan_Calibration_Flow] ====Done====
2379 11:33:04.319806
2380 11:33:04.322790 [DutyScan_Calibration_Flow] k_type=3
2381 11:33:04.339400
2382 11:33:04.339913 ==DQM 0 ==
2383 11:33:04.342734 Final DQM duty delay cell = 0
2384 11:33:04.346328 [0] MAX Duty = 5031%(X100), DQS PI = 26
2385 11:33:04.349556 [0] MIN Duty = 4813%(X100), DQS PI = 38
2386 11:33:04.352798 [0] AVG Duty = 4922%(X100)
2387 11:33:04.353315
2388 11:33:04.353633 ==DQM 1 ==
2389 11:33:04.355790 Final DQM duty delay cell = 0
2390 11:33:04.359530 [0] MAX Duty = 5000%(X100), DQS PI = 34
2391 11:33:04.362386 [0] MIN Duty = 4844%(X100), DQS PI = 0
2392 11:33:04.365521 [0] AVG Duty = 4922%(X100)
2393 11:33:04.365805
2394 11:33:04.369087 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2395 11:33:04.369301
2396 11:33:04.372149 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2397 11:33:04.375625 [DutyScan_Calibration_Flow] ====Done====
2398 11:33:04.375832
2399 11:33:04.378571 [DutyScan_Calibration_Flow] k_type=2
2400 11:33:04.395234
2401 11:33:04.395442 ==DQ 0 ==
2402 11:33:04.398333 Final DQ duty delay cell = -4
2403 11:33:04.401813 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2404 11:33:04.404689 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2405 11:33:04.408408 [-4] AVG Duty = 4937%(X100)
2406 11:33:04.408665
2407 11:33:04.408909 ==DQ 1 ==
2408 11:33:04.411443 Final DQ duty delay cell = 0
2409 11:33:04.414909 [0] MAX Duty = 5031%(X100), DQS PI = 32
2410 11:33:04.418609 [0] MIN Duty = 4844%(X100), DQS PI = 0
2411 11:33:04.418949 [0] AVG Duty = 4937%(X100)
2412 11:33:04.421955
2413 11:33:04.422370 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2414 11:33:04.424899
2415 11:33:04.428774 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2416 11:33:04.431761 [DutyScan_Calibration_Flow] ====Done====
2417 11:33:04.435201 nWR fixed to 30
2418 11:33:04.435592 [ModeRegInit_LP4] CH0 RK0
2419 11:33:04.438519 [ModeRegInit_LP4] CH0 RK1
2420 11:33:04.441124 [ModeRegInit_LP4] CH1 RK0
2421 11:33:04.444951 [ModeRegInit_LP4] CH1 RK1
2422 11:33:04.445064 match AC timing 7
2423 11:33:04.447946 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2424 11:33:04.454620 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2425 11:33:04.458023 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2426 11:33:04.464549 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2427 11:33:04.467985 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2428 11:33:04.468054 ==
2429 11:33:04.471563 Dram Type= 6, Freq= 0, CH_0, rank 0
2430 11:33:04.474547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2431 11:33:04.474625 ==
2432 11:33:04.481266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2433 11:33:04.488092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2434 11:33:04.494976 [CA 0] Center 39 (9~70) winsize 62
2435 11:33:04.498408 [CA 1] Center 39 (9~70) winsize 62
2436 11:33:04.501948 [CA 2] Center 35 (5~66) winsize 62
2437 11:33:04.505163 [CA 3] Center 35 (5~66) winsize 62
2438 11:33:04.508253 [CA 4] Center 33 (3~64) winsize 62
2439 11:33:04.511941 [CA 5] Center 33 (3~64) winsize 62
2440 11:33:04.512018
2441 11:33:04.515017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2442 11:33:04.515093
2443 11:33:04.518666 [CATrainingPosCal] consider 1 rank data
2444 11:33:04.521439 u2DelayCellTimex100 = 270/100 ps
2445 11:33:04.524925 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2446 11:33:04.531315 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2447 11:33:04.534417 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2448 11:33:04.537868 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2449 11:33:04.541490 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2450 11:33:04.544646 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2451 11:33:04.544722
2452 11:33:04.548322 CA PerBit enable=1, Macro0, CA PI delay=33
2453 11:33:04.548397
2454 11:33:04.551274 [CBTSetCACLKResult] CA Dly = 33
2455 11:33:04.551349 CS Dly: 7 (0~38)
2456 11:33:04.555195 ==
2457 11:33:04.557816 Dram Type= 6, Freq= 0, CH_0, rank 1
2458 11:33:04.561223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 11:33:04.561301 ==
2460 11:33:04.565145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 11:33:04.571613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 11:33:04.580914 [CA 0] Center 39 (9~70) winsize 62
2463 11:33:04.584148 [CA 1] Center 39 (9~70) winsize 62
2464 11:33:04.587629 [CA 2] Center 35 (5~66) winsize 62
2465 11:33:04.591049 [CA 3] Center 35 (5~66) winsize 62
2466 11:33:04.594250 [CA 4] Center 34 (3~65) winsize 63
2467 11:33:04.597092 [CA 5] Center 33 (3~63) winsize 61
2468 11:33:04.597219
2469 11:33:04.600429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2470 11:33:04.600504
2471 11:33:04.603715 [CATrainingPosCal] consider 2 rank data
2472 11:33:04.607136 u2DelayCellTimex100 = 270/100 ps
2473 11:33:04.610827 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2474 11:33:04.617308 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 11:33:04.620289 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 11:33:04.623849 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 11:33:04.627378 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2478 11:33:04.630731 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 11:33:04.630807
2480 11:33:04.633665 CA PerBit enable=1, Macro0, CA PI delay=33
2481 11:33:04.633741
2482 11:33:04.637197 [CBTSetCACLKResult] CA Dly = 33
2483 11:33:04.637276 CS Dly: 8 (0~41)
2484 11:33:04.640590
2485 11:33:04.643737 ----->DramcWriteLeveling(PI) begin...
2486 11:33:04.643813 ==
2487 11:33:04.647298 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 11:33:04.650315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 11:33:04.650414 ==
2490 11:33:04.653962 Write leveling (Byte 0): 33 => 33
2491 11:33:04.656919 Write leveling (Byte 1): 27 => 27
2492 11:33:04.660563 DramcWriteLeveling(PI) end<-----
2493 11:33:04.660639
2494 11:33:04.660698 ==
2495 11:33:04.663486 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 11:33:04.667087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 11:33:04.667164 ==
2498 11:33:04.670477 [Gating] SW mode calibration
2499 11:33:04.676931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2500 11:33:04.684340 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2501 11:33:04.686910 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2502 11:33:04.690521 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
2503 11:33:04.696758 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2504 11:33:04.699996 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2505 11:33:04.703380 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2506 11:33:04.710165 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2507 11:33:04.713872 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2508 11:33:04.716707 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2509 11:33:04.723698 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
2510 11:33:04.727090 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2511 11:33:04.730161 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2512 11:33:04.733345 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2513 11:33:04.739680 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2514 11:33:04.743566 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2515 11:33:04.746345 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2516 11:33:04.753255 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2517 11:33:04.756773 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (1 1) (0 0)
2518 11:33:04.759782 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2519 11:33:04.766299 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2520 11:33:04.769767 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2521 11:33:04.773541 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2522 11:33:04.779685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2523 11:33:04.783348 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2524 11:33:04.786488 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2525 11:33:04.792991 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2526 11:33:04.796598 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2527 11:33:04.799513 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2528 11:33:04.806301 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2529 11:33:04.809665 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2530 11:33:04.813168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2531 11:33:04.819362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2532 11:33:04.822856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2533 11:33:04.826409 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2534 11:33:04.833118 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 11:33:04.836300 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 11:33:04.839772 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 11:33:04.846032 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 11:33:04.849382 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 11:33:04.852993 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 11:33:04.859385 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2541 11:33:04.859457 Total UI for P1: 0, mck2ui 16
2542 11:33:04.865809 best dqsien dly found for B0: ( 1, 3, 26)
2543 11:33:04.869343 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2544 11:33:04.872430 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:33:04.876347 Total UI for P1: 0, mck2ui 16
2546 11:33:04.879640 best dqsien dly found for B1: ( 1, 4, 0)
2547 11:33:04.882581 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2548 11:33:04.886151 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2549 11:33:04.886540
2550 11:33:04.889749 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2551 11:33:04.896327 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2552 11:33:04.896719 [Gating] SW calibration Done
2553 11:33:04.897025 ==
2554 11:33:04.899393 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 11:33:04.905774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 11:33:04.906165 ==
2557 11:33:04.906473 RX Vref Scan: 0
2558 11:33:04.906754
2559 11:33:04.909231 RX Vref 0 -> 0, step: 1
2560 11:33:04.909626
2561 11:33:04.912648 RX Delay -40 -> 252, step: 8
2562 11:33:04.915798 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2563 11:33:04.919460 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2564 11:33:04.922448 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2565 11:33:04.929414 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2566 11:33:04.932540 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2567 11:33:04.935801 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2568 11:33:04.938965 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2569 11:33:04.942393 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2570 11:33:04.949029 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2571 11:33:04.952135 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2572 11:33:04.955547 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2573 11:33:04.959088 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2574 11:33:04.961995 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2575 11:33:04.968804 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2576 11:33:04.972126 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2577 11:33:04.975628 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2578 11:33:04.976122 ==
2579 11:33:04.978960 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 11:33:04.982190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 11:33:04.982641 ==
2582 11:33:04.985917 DQS Delay:
2583 11:33:04.986340 DQS0 = 0, DQS1 = 0
2584 11:33:04.988896 DQM Delay:
2585 11:33:04.989334 DQM0 = 117, DQM1 = 107
2586 11:33:04.991788 DQ Delay:
2587 11:33:04.995384 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2588 11:33:04.998661 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2589 11:33:05.001797 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2590 11:33:05.004792 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2591 11:33:05.005066
2592 11:33:05.005374
2593 11:33:05.005583 ==
2594 11:33:05.008165 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 11:33:05.011824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 11:33:05.012128 ==
2597 11:33:05.012376
2598 11:33:05.012577
2599 11:33:05.015436 TX Vref Scan disable
2600 11:33:05.018074 == TX Byte 0 ==
2601 11:33:05.021766 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2602 11:33:05.024679 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2603 11:33:05.028516 == TX Byte 1 ==
2604 11:33:05.031458 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2605 11:33:05.034809 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2606 11:33:05.035089 ==
2607 11:33:05.038453 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 11:33:05.044677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 11:33:05.044956 ==
2610 11:33:05.055921 TX Vref=22, minBit 4, minWin=24, winSum=411
2611 11:33:05.058975 TX Vref=24, minBit 10, minWin=25, winSum=422
2612 11:33:05.062215 TX Vref=26, minBit 4, minWin=25, winSum=422
2613 11:33:05.065575 TX Vref=28, minBit 4, minWin=26, winSum=433
2614 11:33:05.069202 TX Vref=30, minBit 4, minWin=26, winSum=430
2615 11:33:05.075860 TX Vref=32, minBit 10, minWin=26, winSum=431
2616 11:33:05.078954 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 28
2617 11:33:05.079240
2618 11:33:05.082226 Final TX Range 1 Vref 28
2619 11:33:05.082524
2620 11:33:05.082804 ==
2621 11:33:05.085802 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 11:33:05.088937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 11:33:05.092021 ==
2624 11:33:05.092381
2625 11:33:05.092665
2626 11:33:05.092929 TX Vref Scan disable
2627 11:33:05.095541 == TX Byte 0 ==
2628 11:33:05.098677 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2629 11:33:05.102327 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2630 11:33:05.105254 == TX Byte 1 ==
2631 11:33:05.108750 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2632 11:33:05.112293 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2633 11:33:05.115442
2634 11:33:05.115726 [DATLAT]
2635 11:33:05.116065 Freq=1200, CH0 RK0
2636 11:33:05.116366
2637 11:33:05.118838 DATLAT Default: 0xd
2638 11:33:05.119238 0, 0xFFFF, sum = 0
2639 11:33:05.122269 1, 0xFFFF, sum = 0
2640 11:33:05.122551 2, 0xFFFF, sum = 0
2641 11:33:05.125765 3, 0xFFFF, sum = 0
2642 11:33:05.128593 4, 0xFFFF, sum = 0
2643 11:33:05.128884 5, 0xFFFF, sum = 0
2644 11:33:05.131889 6, 0xFFFF, sum = 0
2645 11:33:05.132170 7, 0xFFFF, sum = 0
2646 11:33:05.135964 8, 0xFFFF, sum = 0
2647 11:33:05.136348 9, 0xFFFF, sum = 0
2648 11:33:05.138472 10, 0xFFFF, sum = 0
2649 11:33:05.138777 11, 0xFFFF, sum = 0
2650 11:33:05.141605 12, 0x0, sum = 1
2651 11:33:05.141700 13, 0x0, sum = 2
2652 11:33:05.145021 14, 0x0, sum = 3
2653 11:33:05.145127 15, 0x0, sum = 4
2654 11:33:05.148604 best_step = 13
2655 11:33:05.148679
2656 11:33:05.148737 ==
2657 11:33:05.151616 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 11:33:05.155174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 11:33:05.155251 ==
2660 11:33:05.155309 RX Vref Scan: 1
2661 11:33:05.155364
2662 11:33:05.158522 Set Vref Range= 32 -> 127
2663 11:33:05.158598
2664 11:33:05.161788 RX Vref 32 -> 127, step: 1
2665 11:33:05.161863
2666 11:33:05.165243 RX Delay -21 -> 252, step: 4
2667 11:33:05.165319
2668 11:33:05.168752 Set Vref, RX VrefLevel [Byte0]: 32
2669 11:33:05.171840 [Byte1]: 32
2670 11:33:05.171938
2671 11:33:05.174958 Set Vref, RX VrefLevel [Byte0]: 33
2672 11:33:05.178353 [Byte1]: 33
2673 11:33:05.181855
2674 11:33:05.181930 Set Vref, RX VrefLevel [Byte0]: 34
2675 11:33:05.185295 [Byte1]: 34
2676 11:33:05.189393
2677 11:33:05.189463 Set Vref, RX VrefLevel [Byte0]: 35
2678 11:33:05.193874 [Byte1]: 35
2679 11:33:05.197456
2680 11:33:05.197523 Set Vref, RX VrefLevel [Byte0]: 36
2681 11:33:05.201083 [Byte1]: 36
2682 11:33:05.205417
2683 11:33:05.205499 Set Vref, RX VrefLevel [Byte0]: 37
2684 11:33:05.208829 [Byte1]: 37
2685 11:33:05.213486
2686 11:33:05.213584 Set Vref, RX VrefLevel [Byte0]: 38
2687 11:33:05.217074 [Byte1]: 38
2688 11:33:05.221353
2689 11:33:05.221469 Set Vref, RX VrefLevel [Byte0]: 39
2690 11:33:05.225000 [Byte1]: 39
2691 11:33:05.229287
2692 11:33:05.229363 Set Vref, RX VrefLevel [Byte0]: 40
2693 11:33:05.232635 [Byte1]: 40
2694 11:33:05.237053
2695 11:33:05.237131 Set Vref, RX VrefLevel [Byte0]: 41
2696 11:33:05.240454 [Byte1]: 41
2697 11:33:05.245103
2698 11:33:05.245242 Set Vref, RX VrefLevel [Byte0]: 42
2699 11:33:05.248588 [Byte1]: 42
2700 11:33:05.252997
2701 11:33:05.253118 Set Vref, RX VrefLevel [Byte0]: 43
2702 11:33:05.256691 [Byte1]: 43
2703 11:33:05.260867
2704 11:33:05.260943 Set Vref, RX VrefLevel [Byte0]: 44
2705 11:33:05.264557 [Byte1]: 44
2706 11:33:05.269116
2707 11:33:05.269231 Set Vref, RX VrefLevel [Byte0]: 45
2708 11:33:05.272541 [Byte1]: 45
2709 11:33:05.276723
2710 11:33:05.276798 Set Vref, RX VrefLevel [Byte0]: 46
2711 11:33:05.280191 [Byte1]: 46
2712 11:33:05.285440
2713 11:33:05.285581 Set Vref, RX VrefLevel [Byte0]: 47
2714 11:33:05.287992 [Byte1]: 47
2715 11:33:05.292647
2716 11:33:05.292746 Set Vref, RX VrefLevel [Byte0]: 48
2717 11:33:05.296249 [Byte1]: 48
2718 11:33:05.300875
2719 11:33:05.300979 Set Vref, RX VrefLevel [Byte0]: 49
2720 11:33:05.303919 [Byte1]: 49
2721 11:33:05.309315
2722 11:33:05.309390 Set Vref, RX VrefLevel [Byte0]: 50
2723 11:33:05.311911 [Byte1]: 50
2724 11:33:05.316615
2725 11:33:05.316714 Set Vref, RX VrefLevel [Byte0]: 51
2726 11:33:05.320088 [Byte1]: 51
2727 11:33:05.324550
2728 11:33:05.324631 Set Vref, RX VrefLevel [Byte0]: 52
2729 11:33:05.328000 [Byte1]: 52
2730 11:33:05.332406
2731 11:33:05.332483 Set Vref, RX VrefLevel [Byte0]: 53
2732 11:33:05.335408 [Byte1]: 53
2733 11:33:05.341117
2734 11:33:05.341218 Set Vref, RX VrefLevel [Byte0]: 54
2735 11:33:05.343368 [Byte1]: 54
2736 11:33:05.348041
2737 11:33:05.348118 Set Vref, RX VrefLevel [Byte0]: 55
2738 11:33:05.351324 [Byte1]: 55
2739 11:33:05.356158
2740 11:33:05.356236 Set Vref, RX VrefLevel [Byte0]: 56
2741 11:33:05.359462 [Byte1]: 56
2742 11:33:05.363867
2743 11:33:05.363967 Set Vref, RX VrefLevel [Byte0]: 57
2744 11:33:05.367108 [Byte1]: 57
2745 11:33:05.372232
2746 11:33:05.372315 Set Vref, RX VrefLevel [Byte0]: 58
2747 11:33:05.375735 [Byte1]: 58
2748 11:33:05.379899
2749 11:33:05.379976 Set Vref, RX VrefLevel [Byte0]: 59
2750 11:33:05.383267 [Byte1]: 59
2751 11:33:05.387604
2752 11:33:05.387681 Set Vref, RX VrefLevel [Byte0]: 60
2753 11:33:05.391110 [Byte1]: 60
2754 11:33:05.395658
2755 11:33:05.398917 Set Vref, RX VrefLevel [Byte0]: 61
2756 11:33:05.401994 [Byte1]: 61
2757 11:33:05.402072
2758 11:33:05.405660 Set Vref, RX VrefLevel [Byte0]: 62
2759 11:33:05.409043 [Byte1]: 62
2760 11:33:05.409163
2761 11:33:05.412047 Set Vref, RX VrefLevel [Byte0]: 63
2762 11:33:05.415434 [Byte1]: 63
2763 11:33:05.419437
2764 11:33:05.419512 Set Vref, RX VrefLevel [Byte0]: 64
2765 11:33:05.423020 [Byte1]: 64
2766 11:33:05.427588
2767 11:33:05.427663 Set Vref, RX VrefLevel [Byte0]: 65
2768 11:33:05.430873 [Byte1]: 65
2769 11:33:05.435580
2770 11:33:05.435655 Set Vref, RX VrefLevel [Byte0]: 66
2771 11:33:05.439036 [Byte1]: 66
2772 11:33:05.443429
2773 11:33:05.443526 Set Vref, RX VrefLevel [Byte0]: 67
2774 11:33:05.446838 [Byte1]: 67
2775 11:33:05.451310
2776 11:33:05.451387 Set Vref, RX VrefLevel [Byte0]: 68
2777 11:33:05.454528 [Byte1]: 68
2778 11:33:05.459104
2779 11:33:05.459181 Final RX Vref Byte 0 = 51 to rank0
2780 11:33:05.462802 Final RX Vref Byte 1 = 59 to rank0
2781 11:33:05.465550 Final RX Vref Byte 0 = 51 to rank1
2782 11:33:05.469305 Final RX Vref Byte 1 = 59 to rank1==
2783 11:33:05.472960 Dram Type= 6, Freq= 0, CH_0, rank 0
2784 11:33:05.478784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2785 11:33:05.478863 ==
2786 11:33:05.478941 DQS Delay:
2787 11:33:05.479014 DQS0 = 0, DQS1 = 0
2788 11:33:05.482279 DQM Delay:
2789 11:33:05.482356 DQM0 = 117, DQM1 = 105
2790 11:33:05.485958 DQ Delay:
2791 11:33:05.488907 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2792 11:33:05.492240 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2793 11:33:05.495998 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2794 11:33:05.499112 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2795 11:33:05.499203
2796 11:33:05.499280
2797 11:33:05.506028 [DQSOSCAuto] RK0, (LSB)MR18= 0x702, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2798 11:33:05.509145 CH0 RK0: MR19=404, MR18=702
2799 11:33:05.515797 CH0_RK0: MR19=0x404, MR18=0x702, DQSOSC=407, MR23=63, INC=39, DEC=26
2800 11:33:05.515882
2801 11:33:05.519171 ----->DramcWriteLeveling(PI) begin...
2802 11:33:05.519250 ==
2803 11:33:05.522539 Dram Type= 6, Freq= 0, CH_0, rank 1
2804 11:33:05.525815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 11:33:05.525892 ==
2806 11:33:05.529478 Write leveling (Byte 0): 32 => 32
2807 11:33:05.532779 Write leveling (Byte 1): 26 => 26
2808 11:33:05.535732 DramcWriteLeveling(PI) end<-----
2809 11:33:05.535810
2810 11:33:05.535869 ==
2811 11:33:05.539275 Dram Type= 6, Freq= 0, CH_0, rank 1
2812 11:33:05.542702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 11:33:05.546006 ==
2814 11:33:05.546105 [Gating] SW mode calibration
2815 11:33:05.555719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2816 11:33:05.558882 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2817 11:33:05.562613 0 15 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2818 11:33:05.569026 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2819 11:33:05.572280 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2820 11:33:05.575843 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2821 11:33:05.582557 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2822 11:33:05.585770 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2823 11:33:05.588634 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2824 11:33:05.595453 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2825 11:33:05.598692 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2826 11:33:05.602025 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2827 11:33:05.608380 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2828 11:33:05.612159 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2829 11:33:05.615578 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2830 11:33:05.622122 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2831 11:33:05.625509 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2832 11:33:05.628619 1 0 28 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
2833 11:33:05.635031 1 1 0 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2834 11:33:05.638399 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2835 11:33:05.641681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2836 11:33:05.648743 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2837 11:33:05.651666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2838 11:33:05.655461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2839 11:33:05.662231 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2840 11:33:05.665065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2841 11:33:05.668620 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2842 11:33:05.674940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2843 11:33:05.678508 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2844 11:33:05.682234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2845 11:33:05.688344 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2846 11:33:05.691879 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2847 11:33:05.695413 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2848 11:33:05.701955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2849 11:33:05.704692 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2850 11:33:05.708401 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 11:33:05.711808 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 11:33:05.718461 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 11:33:05.721504 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 11:33:05.724696 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 11:33:05.731823 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2856 11:33:05.734714 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2857 11:33:05.738406 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2858 11:33:05.742011 Total UI for P1: 0, mck2ui 16
2859 11:33:05.744581 best dqsien dly found for B0: ( 1, 3, 26)
2860 11:33:05.751332 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 11:33:05.751407 Total UI for P1: 0, mck2ui 16
2862 11:33:05.758497 best dqsien dly found for B1: ( 1, 3, 30)
2863 11:33:05.761060 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2864 11:33:05.764941 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2865 11:33:05.765016
2866 11:33:05.768436 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2867 11:33:05.771131 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2868 11:33:05.775230 [Gating] SW calibration Done
2869 11:33:05.775304 ==
2870 11:33:05.778439 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 11:33:05.781145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 11:33:05.781261 ==
2873 11:33:05.784439 RX Vref Scan: 0
2874 11:33:05.784513
2875 11:33:05.784572 RX Vref 0 -> 0, step: 1
2876 11:33:05.784627
2877 11:33:05.787804 RX Delay -40 -> 252, step: 8
2878 11:33:05.791078 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2879 11:33:05.797913 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2880 11:33:05.801336 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2881 11:33:05.804530 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2882 11:33:05.807889 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2883 11:33:05.811179 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2884 11:33:05.817771 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2885 11:33:05.821284 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2886 11:33:05.824836 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2887 11:33:05.827784 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2888 11:33:05.831349 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2889 11:33:05.837914 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2890 11:33:05.841328 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2891 11:33:05.844315 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2892 11:33:05.848386 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2893 11:33:05.854308 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2894 11:33:05.854388 ==
2895 11:33:05.857561 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 11:33:05.860894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 11:33:05.860984 ==
2898 11:33:05.861044 DQS Delay:
2899 11:33:05.864169 DQS0 = 0, DQS1 = 0
2900 11:33:05.864271 DQM Delay:
2901 11:33:05.867402 DQM0 = 115, DQM1 = 109
2902 11:33:05.867479 DQ Delay:
2903 11:33:05.871182 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2904 11:33:05.874234 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2905 11:33:05.877454 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2906 11:33:05.881006 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2907 11:33:05.881097
2908 11:33:05.881212
2909 11:33:05.881274 ==
2910 11:33:05.884043 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 11:33:05.890727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 11:33:05.890810 ==
2913 11:33:05.890868
2914 11:33:05.890922
2915 11:33:05.890981 TX Vref Scan disable
2916 11:33:05.894303 == TX Byte 0 ==
2917 11:33:05.897967 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2918 11:33:05.901212 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2919 11:33:05.904641 == TX Byte 1 ==
2920 11:33:05.907691 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2921 11:33:05.914146 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2922 11:33:05.914222 ==
2923 11:33:05.917993 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 11:33:05.920822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 11:33:05.920897 ==
2926 11:33:05.932673 TX Vref=22, minBit 13, minWin=25, winSum=418
2927 11:33:05.936181 TX Vref=24, minBit 3, minWin=26, winSum=426
2928 11:33:05.939175 TX Vref=26, minBit 2, minWin=25, winSum=422
2929 11:33:05.942854 TX Vref=28, minBit 2, minWin=26, winSum=428
2930 11:33:05.945935 TX Vref=30, minBit 5, minWin=26, winSum=427
2931 11:33:05.952491 TX Vref=32, minBit 0, minWin=26, winSum=426
2932 11:33:05.956109 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 28
2933 11:33:05.956184
2934 11:33:05.959197 Final TX Range 1 Vref 28
2935 11:33:05.959301
2936 11:33:05.959389 ==
2937 11:33:05.962896 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 11:33:05.965892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 11:33:05.965967 ==
2940 11:33:05.969050
2941 11:33:05.969188
2942 11:33:05.969249 TX Vref Scan disable
2943 11:33:05.972387 == TX Byte 0 ==
2944 11:33:05.975748 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2945 11:33:05.982573 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2946 11:33:05.982719 == TX Byte 1 ==
2947 11:33:05.985810 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2948 11:33:05.992823 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2949 11:33:05.992899
2950 11:33:05.992959 [DATLAT]
2951 11:33:05.993015 Freq=1200, CH0 RK1
2952 11:33:05.993068
2953 11:33:05.995540 DATLAT Default: 0xd
2954 11:33:05.995647 0, 0xFFFF, sum = 0
2955 11:33:05.999331 1, 0xFFFF, sum = 0
2956 11:33:06.002770 2, 0xFFFF, sum = 0
2957 11:33:06.002836 3, 0xFFFF, sum = 0
2958 11:33:06.005578 4, 0xFFFF, sum = 0
2959 11:33:06.005654 5, 0xFFFF, sum = 0
2960 11:33:06.009149 6, 0xFFFF, sum = 0
2961 11:33:06.009239 7, 0xFFFF, sum = 0
2962 11:33:06.012665 8, 0xFFFF, sum = 0
2963 11:33:06.012741 9, 0xFFFF, sum = 0
2964 11:33:06.015889 10, 0xFFFF, sum = 0
2965 11:33:06.015965 11, 0xFFFF, sum = 0
2966 11:33:06.018946 12, 0x0, sum = 1
2967 11:33:06.019022 13, 0x0, sum = 2
2968 11:33:06.022221 14, 0x0, sum = 3
2969 11:33:06.022297 15, 0x0, sum = 4
2970 11:33:06.026002 best_step = 13
2971 11:33:06.026100
2972 11:33:06.026184 ==
2973 11:33:06.028880 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 11:33:06.031905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 11:33:06.031997 ==
2976 11:33:06.035434 RX Vref Scan: 0
2977 11:33:06.035504
2978 11:33:06.035561 RX Vref 0 -> 0, step: 1
2979 11:33:06.035614
2980 11:33:06.038555 RX Delay -21 -> 252, step: 4
2981 11:33:06.045542 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2982 11:33:06.048500 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2983 11:33:06.051672 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
2984 11:33:06.055141 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
2985 11:33:06.058134 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
2986 11:33:06.064837 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
2987 11:33:06.068335 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2988 11:33:06.071381 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
2989 11:33:06.075400 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
2990 11:33:06.078149 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
2991 11:33:06.084825 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2992 11:33:06.088192 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
2993 11:33:06.091517 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2994 11:33:06.094899 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
2995 11:33:06.097773 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2996 11:33:06.104756 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
2997 11:33:06.104837 ==
2998 11:33:06.107922 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 11:33:06.111285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 11:33:06.111361 ==
3001 11:33:06.111419 DQS Delay:
3002 11:33:06.114865 DQS0 = 0, DQS1 = 0
3003 11:33:06.114938 DQM Delay:
3004 11:33:06.117488 DQM0 = 115, DQM1 = 106
3005 11:33:06.117556 DQ Delay:
3006 11:33:06.121394 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3007 11:33:06.124444 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3008 11:33:06.127739 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3009 11:33:06.131338 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3010 11:33:06.134046
3011 11:33:06.134115
3012 11:33:06.141013 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3013 11:33:06.144544 CH0 RK1: MR19=303, MR18=FEFD
3014 11:33:06.151118 CH0_RK1: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3015 11:33:06.154197 [RxdqsGatingPostProcess] freq 1200
3016 11:33:06.157636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3017 11:33:06.160706 best DQS0 dly(2T, 0.5T) = (0, 11)
3018 11:33:06.164261 best DQS1 dly(2T, 0.5T) = (0, 12)
3019 11:33:06.167799 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3020 11:33:06.170696 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3021 11:33:06.174166 best DQS0 dly(2T, 0.5T) = (0, 11)
3022 11:33:06.177132 best DQS1 dly(2T, 0.5T) = (0, 11)
3023 11:33:06.180723 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3024 11:33:06.184214 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3025 11:33:06.187403 Pre-setting of DQS Precalculation
3026 11:33:06.190797 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3027 11:33:06.190974 ==
3028 11:33:06.193670 Dram Type= 6, Freq= 0, CH_1, rank 0
3029 11:33:06.200467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 11:33:06.200634 ==
3031 11:33:06.203908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3032 11:33:06.210208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3033 11:33:06.219136 [CA 0] Center 38 (8~68) winsize 61
3034 11:33:06.222735 [CA 1] Center 37 (7~68) winsize 62
3035 11:33:06.225550 [CA 2] Center 35 (6~65) winsize 60
3036 11:33:06.229212 [CA 3] Center 34 (4~64) winsize 61
3037 11:33:06.232390 [CA 4] Center 34 (4~64) winsize 61
3038 11:33:06.235583 [CA 5] Center 33 (3~63) winsize 61
3039 11:33:06.235937
3040 11:33:06.238914 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3041 11:33:06.239274
3042 11:33:06.242139 [CATrainingPosCal] consider 1 rank data
3043 11:33:06.245459 u2DelayCellTimex100 = 270/100 ps
3044 11:33:06.248679 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3045 11:33:06.255491 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3046 11:33:06.258523 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3047 11:33:06.262067 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3048 11:33:06.265237 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3049 11:33:06.268383 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3050 11:33:06.268735
3051 11:33:06.271952 CA PerBit enable=1, Macro0, CA PI delay=33
3052 11:33:06.272309
3053 11:33:06.275117 [CBTSetCACLKResult] CA Dly = 33
3054 11:33:06.279150 CS Dly: 4 (0~35)
3055 11:33:06.279525 ==
3056 11:33:06.282048 Dram Type= 6, Freq= 0, CH_1, rank 1
3057 11:33:06.284907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 11:33:06.285312 ==
3059 11:33:06.291894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3060 11:33:06.294954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3061 11:33:06.305235 [CA 0] Center 38 (8~68) winsize 61
3062 11:33:06.308523 [CA 1] Center 38 (7~69) winsize 63
3063 11:33:06.311394 [CA 2] Center 35 (5~65) winsize 61
3064 11:33:06.315090 [CA 3] Center 34 (4~64) winsize 61
3065 11:33:06.317910 [CA 4] Center 34 (4~64) winsize 61
3066 11:33:06.321306 [CA 5] Center 33 (3~63) winsize 61
3067 11:33:06.321749
3068 11:33:06.324379 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3069 11:33:06.324735
3070 11:33:06.328135 [CATrainingPosCal] consider 2 rank data
3071 11:33:06.331240 u2DelayCellTimex100 = 270/100 ps
3072 11:33:06.334691 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3073 11:33:06.341102 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 11:33:06.344766 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3075 11:33:06.347382 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3076 11:33:06.350826 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3077 11:33:06.354684 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3078 11:33:06.355041
3079 11:33:06.357702 CA PerBit enable=1, Macro0, CA PI delay=33
3080 11:33:06.358059
3081 11:33:06.361174 [CBTSetCACLKResult] CA Dly = 33
3082 11:33:06.364287 CS Dly: 6 (0~39)
3083 11:33:06.364642
3084 11:33:06.367673 ----->DramcWriteLeveling(PI) begin...
3085 11:33:06.368033 ==
3086 11:33:06.370672 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 11:33:06.374094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 11:33:06.374455 ==
3089 11:33:06.377668 Write leveling (Byte 0): 27 => 27
3090 11:33:06.380591 Write leveling (Byte 1): 27 => 27
3091 11:33:06.384503 DramcWriteLeveling(PI) end<-----
3092 11:33:06.384859
3093 11:33:06.385163 ==
3094 11:33:06.387189 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 11:33:06.390789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 11:33:06.391149 ==
3097 11:33:06.394528 [Gating] SW mode calibration
3098 11:33:06.400563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3099 11:33:06.406796 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3100 11:33:06.410288 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3101 11:33:06.416808 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3102 11:33:06.419908 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3103 11:33:06.423346 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3104 11:33:06.430345 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3105 11:33:06.433094 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3106 11:33:06.436420 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3107 11:33:06.442780 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
3108 11:33:06.446511 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3109 11:33:06.449558 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3110 11:33:06.456249 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3111 11:33:06.459493 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3112 11:33:06.462678 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3113 11:33:06.469166 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3114 11:33:06.472409 1 0 24 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
3115 11:33:06.475701 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3116 11:33:06.482716 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3117 11:33:06.485700 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3118 11:33:06.489065 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3119 11:33:06.495749 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3120 11:33:06.498673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3121 11:33:06.502162 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3122 11:33:06.508488 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3123 11:33:06.512181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3124 11:33:06.515157 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3125 11:33:06.521713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3126 11:33:06.525779 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3127 11:33:06.528888 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3128 11:33:06.535058 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3129 11:33:06.538579 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3130 11:33:06.541916 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3131 11:33:06.548336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3132 11:33:06.552130 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3133 11:33:06.554726 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 11:33:06.561620 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 11:33:06.564461 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 11:33:06.568113 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 11:33:06.574613 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 11:33:06.577836 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3139 11:33:06.580992 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3140 11:33:06.587777 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:33:06.588170 Total UI for P1: 0, mck2ui 16
3142 11:33:06.594474 best dqsien dly found for B0: ( 1, 3, 26)
3143 11:33:06.594888 Total UI for P1: 0, mck2ui 16
3144 11:33:06.600909 best dqsien dly found for B1: ( 1, 3, 26)
3145 11:33:06.604004 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3146 11:33:06.607638 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3147 11:33:06.608026
3148 11:33:06.611013 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3149 11:33:06.614216 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3150 11:33:06.617319 [Gating] SW calibration Done
3151 11:33:06.617707 ==
3152 11:33:06.620611 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 11:33:06.624524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 11:33:06.624991 ==
3155 11:33:06.627201 RX Vref Scan: 0
3156 11:33:06.627589
3157 11:33:06.627913 RX Vref 0 -> 0, step: 1
3158 11:33:06.628221
3159 11:33:06.631102 RX Delay -40 -> 252, step: 8
3160 11:33:06.637271 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3161 11:33:06.640407 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3162 11:33:06.643759 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3163 11:33:06.647142 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3164 11:33:06.650808 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3165 11:33:06.656812 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3166 11:33:06.660345 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3167 11:33:06.663435 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3168 11:33:06.666777 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3169 11:33:06.670025 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3170 11:33:06.677038 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3171 11:33:06.680019 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3172 11:33:06.683607 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3173 11:33:06.686885 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3174 11:33:06.692842 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3175 11:33:06.696222 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3176 11:33:06.696683 ==
3177 11:33:06.699495 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 11:33:06.702892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 11:33:06.703354 ==
3180 11:33:06.706348 DQS Delay:
3181 11:33:06.706750 DQS0 = 0, DQS1 = 0
3182 11:33:06.707052 DQM Delay:
3183 11:33:06.709497 DQM0 = 116, DQM1 = 112
3184 11:33:06.709879 DQ Delay:
3185 11:33:06.712706 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3186 11:33:06.716287 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3187 11:33:06.719045 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3188 11:33:06.725703 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3189 11:33:06.726088
3190 11:33:06.726385
3191 11:33:06.726659 ==
3192 11:33:06.729229 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 11:33:06.733377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 11:33:06.733828 ==
3195 11:33:06.734132
3196 11:33:06.734413
3197 11:33:06.735732 TX Vref Scan disable
3198 11:33:06.736116 == TX Byte 0 ==
3199 11:33:06.742395 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3200 11:33:06.745808 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3201 11:33:06.746271 == TX Byte 1 ==
3202 11:33:06.752529 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3203 11:33:06.755392 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3204 11:33:06.755843 ==
3205 11:33:06.758862 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 11:33:06.762089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 11:33:06.762493 ==
3208 11:33:06.774931 TX Vref=22, minBit 9, minWin=24, winSum=411
3209 11:33:06.778059 TX Vref=24, minBit 11, minWin=24, winSum=417
3210 11:33:06.781436 TX Vref=26, minBit 9, minWin=25, winSum=422
3211 11:33:06.785208 TX Vref=28, minBit 11, minWin=24, winSum=420
3212 11:33:06.788120 TX Vref=30, minBit 9, minWin=25, winSum=426
3213 11:33:06.794739 TX Vref=32, minBit 9, minWin=24, winSum=424
3214 11:33:06.797803 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 30
3215 11:33:06.798300
3216 11:33:06.801621 Final TX Range 1 Vref 30
3217 11:33:06.802076
3218 11:33:06.802410 ==
3219 11:33:06.804456 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 11:33:06.807937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 11:33:06.811180 ==
3222 11:33:06.811640
3223 11:33:06.811997
3224 11:33:06.812304 TX Vref Scan disable
3225 11:33:06.815071 == TX Byte 0 ==
3226 11:33:06.817965 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3227 11:33:06.824696 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3228 11:33:06.825098 == TX Byte 1 ==
3229 11:33:06.828301 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3230 11:33:06.834405 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3231 11:33:06.834822
3232 11:33:06.835168 [DATLAT]
3233 11:33:06.835494 Freq=1200, CH1 RK0
3234 11:33:06.835801
3235 11:33:06.838018 DATLAT Default: 0xd
3236 11:33:06.841361 0, 0xFFFF, sum = 0
3237 11:33:06.841834 1, 0xFFFF, sum = 0
3238 11:33:06.844223 2, 0xFFFF, sum = 0
3239 11:33:06.844643 3, 0xFFFF, sum = 0
3240 11:33:06.847617 4, 0xFFFF, sum = 0
3241 11:33:06.848032 5, 0xFFFF, sum = 0
3242 11:33:06.851093 6, 0xFFFF, sum = 0
3243 11:33:06.851489 7, 0xFFFF, sum = 0
3244 11:33:06.854525 8, 0xFFFF, sum = 0
3245 11:33:06.854933 9, 0xFFFF, sum = 0
3246 11:33:06.857713 10, 0xFFFF, sum = 0
3247 11:33:06.858110 11, 0xFFFF, sum = 0
3248 11:33:06.860923 12, 0x0, sum = 1
3249 11:33:06.861435 13, 0x0, sum = 2
3250 11:33:06.864370 14, 0x0, sum = 3
3251 11:33:06.864767 15, 0x0, sum = 4
3252 11:33:06.867372 best_step = 13
3253 11:33:06.867754
3254 11:33:06.868133 ==
3255 11:33:06.871080 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 11:33:06.874307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 11:33:06.874778 ==
3258 11:33:06.877295 RX Vref Scan: 1
3259 11:33:06.877684
3260 11:33:06.878080 Set Vref Range= 32 -> 127
3261 11:33:06.878374
3262 11:33:06.880889 RX Vref 32 -> 127, step: 1
3263 11:33:06.881358
3264 11:33:06.883727 RX Delay -13 -> 252, step: 4
3265 11:33:06.884200
3266 11:33:06.887189 Set Vref, RX VrefLevel [Byte0]: 32
3267 11:33:06.890420 [Byte1]: 32
3268 11:33:06.890887
3269 11:33:06.894102 Set Vref, RX VrefLevel [Byte0]: 33
3270 11:33:06.896992 [Byte1]: 33
3271 11:33:06.901028
3272 11:33:06.901513 Set Vref, RX VrefLevel [Byte0]: 34
3273 11:33:06.904424 [Byte1]: 34
3274 11:33:06.909123
3275 11:33:06.912188 Set Vref, RX VrefLevel [Byte0]: 35
3276 11:33:06.915517 [Byte1]: 35
3277 11:33:06.915919
3278 11:33:06.918617 Set Vref, RX VrefLevel [Byte0]: 36
3279 11:33:06.922431 [Byte1]: 36
3280 11:33:06.922872
3281 11:33:06.925585 Set Vref, RX VrefLevel [Byte0]: 37
3282 11:33:06.928443 [Byte1]: 37
3283 11:33:06.932754
3284 11:33:06.933304 Set Vref, RX VrefLevel [Byte0]: 38
3285 11:33:06.936214 [Byte1]: 38
3286 11:33:06.940449
3287 11:33:06.940837 Set Vref, RX VrefLevel [Byte0]: 39
3288 11:33:06.943967 [Byte1]: 39
3289 11:33:06.948847
3290 11:33:06.949277 Set Vref, RX VrefLevel [Byte0]: 40
3291 11:33:06.951855 [Byte1]: 40
3292 11:33:06.956589
3293 11:33:06.957042 Set Vref, RX VrefLevel [Byte0]: 41
3294 11:33:06.959408 [Byte1]: 41
3295 11:33:06.964806
3296 11:33:06.965240 Set Vref, RX VrefLevel [Byte0]: 42
3297 11:33:06.967862 [Byte1]: 42
3298 11:33:06.972287
3299 11:33:06.972675 Set Vref, RX VrefLevel [Byte0]: 43
3300 11:33:06.975751 [Byte1]: 43
3301 11:33:06.980381
3302 11:33:06.980789 Set Vref, RX VrefLevel [Byte0]: 44
3303 11:33:06.983423 [Byte1]: 44
3304 11:33:06.987767
3305 11:33:06.988149 Set Vref, RX VrefLevel [Byte0]: 45
3306 11:33:06.991263 [Byte1]: 45
3307 11:33:06.995807
3308 11:33:06.996236 Set Vref, RX VrefLevel [Byte0]: 46
3309 11:33:06.999331 [Byte1]: 46
3310 11:33:07.003284
3311 11:33:07.003557 Set Vref, RX VrefLevel [Byte0]: 47
3312 11:33:07.006723 [Byte1]: 47
3313 11:33:07.011301
3314 11:33:07.011466 Set Vref, RX VrefLevel [Byte0]: 48
3315 11:33:07.014732 [Byte1]: 48
3316 11:33:07.019220
3317 11:33:07.019357 Set Vref, RX VrefLevel [Byte0]: 49
3318 11:33:07.022202 [Byte1]: 49
3319 11:33:07.026987
3320 11:33:07.027130 Set Vref, RX VrefLevel [Byte0]: 50
3321 11:33:07.030184 [Byte1]: 50
3322 11:33:07.034838
3323 11:33:07.034975 Set Vref, RX VrefLevel [Byte0]: 51
3324 11:33:07.038414 [Byte1]: 51
3325 11:33:07.042654
3326 11:33:07.042794 Set Vref, RX VrefLevel [Byte0]: 52
3327 11:33:07.046189 [Byte1]: 52
3328 11:33:07.050385
3329 11:33:07.050548 Set Vref, RX VrefLevel [Byte0]: 53
3330 11:33:07.053890 [Byte1]: 53
3331 11:33:07.058510
3332 11:33:07.058727 Set Vref, RX VrefLevel [Byte0]: 54
3333 11:33:07.062130 [Byte1]: 54
3334 11:33:07.066612
3335 11:33:07.067035 Set Vref, RX VrefLevel [Byte0]: 55
3336 11:33:07.070236 [Byte1]: 55
3337 11:33:07.074933
3338 11:33:07.075310 Set Vref, RX VrefLevel [Byte0]: 56
3339 11:33:07.077866 [Byte1]: 56
3340 11:33:07.082556
3341 11:33:07.082934 Set Vref, RX VrefLevel [Byte0]: 57
3342 11:33:07.085864 [Byte1]: 57
3343 11:33:07.090195
3344 11:33:07.090609 Set Vref, RX VrefLevel [Byte0]: 58
3345 11:33:07.093742 [Byte1]: 58
3346 11:33:07.098239
3347 11:33:07.098614 Set Vref, RX VrefLevel [Byte0]: 59
3348 11:33:07.101503 [Byte1]: 59
3349 11:33:07.106030
3350 11:33:07.106410 Set Vref, RX VrefLevel [Byte0]: 60
3351 11:33:07.109615 [Byte1]: 60
3352 11:33:07.114067
3353 11:33:07.114442 Set Vref, RX VrefLevel [Byte0]: 61
3354 11:33:07.117508 [Byte1]: 61
3355 11:33:07.121812
3356 11:33:07.122188 Set Vref, RX VrefLevel [Byte0]: 62
3357 11:33:07.125224 [Byte1]: 62
3358 11:33:07.129631
3359 11:33:07.130024 Set Vref, RX VrefLevel [Byte0]: 63
3360 11:33:07.132811 [Byte1]: 63
3361 11:33:07.137439
3362 11:33:07.137935 Set Vref, RX VrefLevel [Byte0]: 64
3363 11:33:07.140932 [Byte1]: 64
3364 11:33:07.145456
3365 11:33:07.145837 Set Vref, RX VrefLevel [Byte0]: 65
3366 11:33:07.148915 [Byte1]: 65
3367 11:33:07.153768
3368 11:33:07.154149 Final RX Vref Byte 0 = 53 to rank0
3369 11:33:07.156576 Final RX Vref Byte 1 = 52 to rank0
3370 11:33:07.160131 Final RX Vref Byte 0 = 53 to rank1
3371 11:33:07.162992 Final RX Vref Byte 1 = 52 to rank1==
3372 11:33:07.166560 Dram Type= 6, Freq= 0, CH_1, rank 0
3373 11:33:07.173017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3374 11:33:07.173444 ==
3375 11:33:07.173748 DQS Delay:
3376 11:33:07.176538 DQS0 = 0, DQS1 = 0
3377 11:33:07.176919 DQM Delay:
3378 11:33:07.179620 DQM0 = 115, DQM1 = 112
3379 11:33:07.180005 DQ Delay:
3380 11:33:07.182533 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =116
3381 11:33:07.186158 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3382 11:33:07.189729 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3383 11:33:07.193023 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3384 11:33:07.193461
3385 11:33:07.193763
3386 11:33:07.202623 [DQSOSCAuto] RK0, (LSB)MR18= 0xf602, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3387 11:33:07.205604 CH1 RK0: MR19=304, MR18=F602
3388 11:33:07.209227 CH1_RK0: MR19=0x304, MR18=0xF602, DQSOSC=409, MR23=63, INC=39, DEC=26
3389 11:33:07.209615
3390 11:33:07.212486 ----->DramcWriteLeveling(PI) begin...
3391 11:33:07.215915 ==
3392 11:33:07.218843 Dram Type= 6, Freq= 0, CH_1, rank 1
3393 11:33:07.222761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 11:33:07.223155 ==
3395 11:33:07.225572 Write leveling (Byte 0): 24 => 24
3396 11:33:07.228518 Write leveling (Byte 1): 27 => 27
3397 11:33:07.232153 DramcWriteLeveling(PI) end<-----
3398 11:33:07.232577
3399 11:33:07.232948 ==
3400 11:33:07.235724 Dram Type= 6, Freq= 0, CH_1, rank 1
3401 11:33:07.238381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 11:33:07.238782 ==
3403 11:33:07.241715 [Gating] SW mode calibration
3404 11:33:07.248866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3405 11:33:07.255385 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3406 11:33:07.258805 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3407 11:33:07.261791 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3408 11:33:07.268374 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3409 11:33:07.271447 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3410 11:33:07.274993 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3411 11:33:07.281955 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3412 11:33:07.284847 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
3413 11:33:07.288198 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
3414 11:33:07.294978 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3415 11:33:07.298148 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3416 11:33:07.301059 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3417 11:33:07.308157 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3418 11:33:07.311205 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3419 11:33:07.314783 1 0 20 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
3420 11:33:07.321035 1 0 24 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
3421 11:33:07.324257 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3422 11:33:07.327984 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3423 11:33:07.334144 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3424 11:33:07.337505 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3425 11:33:07.340889 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3426 11:33:07.347356 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3427 11:33:07.350934 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3428 11:33:07.354220 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3429 11:33:07.361013 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3430 11:33:07.364088 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3431 11:33:07.367651 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3432 11:33:07.373994 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3433 11:33:07.377269 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3434 11:33:07.380357 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3435 11:33:07.387363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3436 11:33:07.390286 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3437 11:33:07.393963 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3438 11:33:07.400649 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3439 11:33:07.403833 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3440 11:33:07.406869 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 11:33:07.413788 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 11:33:07.416592 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 11:33:07.420127 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3444 11:33:07.426729 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3445 11:33:07.429607 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3446 11:33:07.433544 Total UI for P1: 0, mck2ui 16
3447 11:33:07.436246 best dqsien dly found for B0: ( 1, 3, 22)
3448 11:33:07.439494 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 11:33:07.442695 Total UI for P1: 0, mck2ui 16
3450 11:33:07.446520 best dqsien dly found for B1: ( 1, 3, 28)
3451 11:33:07.449589 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3452 11:33:07.452756 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3453 11:33:07.453183
3454 11:33:07.459049 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3455 11:33:07.462698 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3456 11:33:07.465749 [Gating] SW calibration Done
3457 11:33:07.466144 ==
3458 11:33:07.469350 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 11:33:07.472691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 11:33:07.473094 ==
3461 11:33:07.473537 RX Vref Scan: 0
3462 11:33:07.473912
3463 11:33:07.475487 RX Vref 0 -> 0, step: 1
3464 11:33:07.475898
3465 11:33:07.479006 RX Delay -40 -> 252, step: 8
3466 11:33:07.482641 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3467 11:33:07.485957 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3468 11:33:07.492384 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3469 11:33:07.495404 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3470 11:33:07.498953 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3471 11:33:07.502339 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3472 11:33:07.505377 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3473 11:33:07.512328 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3474 11:33:07.515424 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3475 11:33:07.518528 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3476 11:33:07.522092 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3477 11:33:07.525435 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3478 11:33:07.532249 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3479 11:33:07.535159 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3480 11:33:07.538488 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3481 11:33:07.541258 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3482 11:33:07.544782 ==
3483 11:33:07.545213 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 11:33:07.551193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 11:33:07.551602 ==
3486 11:33:07.551998 DQS Delay:
3487 11:33:07.554617 DQS0 = 0, DQS1 = 0
3488 11:33:07.555016 DQM Delay:
3489 11:33:07.558051 DQM0 = 114, DQM1 = 111
3490 11:33:07.558452 DQ Delay:
3491 11:33:07.561046 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3492 11:33:07.564296 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3493 11:33:07.567729 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3494 11:33:07.571452 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3495 11:33:07.571852
3496 11:33:07.572255
3497 11:33:07.572625 ==
3498 11:33:07.574182 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 11:33:07.580994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 11:33:07.581442 ==
3501 11:33:07.581844
3502 11:33:07.582217
3503 11:33:07.584004 TX Vref Scan disable
3504 11:33:07.584402 == TX Byte 0 ==
3505 11:33:07.587104 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3506 11:33:07.594016 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3507 11:33:07.594419 == TX Byte 1 ==
3508 11:33:07.597559 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3509 11:33:07.603837 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3510 11:33:07.604066 ==
3511 11:33:07.607195 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 11:33:07.610290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 11:33:07.610464 ==
3514 11:33:07.622388 TX Vref=22, minBit 9, minWin=24, winSum=418
3515 11:33:07.625252 TX Vref=24, minBit 9, minWin=24, winSum=419
3516 11:33:07.628807 TX Vref=26, minBit 9, minWin=25, winSum=423
3517 11:33:07.632404 TX Vref=28, minBit 9, minWin=25, winSum=426
3518 11:33:07.635453 TX Vref=30, minBit 9, minWin=25, winSum=426
3519 11:33:07.641987 TX Vref=32, minBit 9, minWin=25, winSum=430
3520 11:33:07.645340 [TxChooseVref] Worse bit 9, Min win 25, Win sum 430, Final Vref 32
3521 11:33:07.645536
3522 11:33:07.648837 Final TX Range 1 Vref 32
3523 11:33:07.649080
3524 11:33:07.649315 ==
3525 11:33:07.652059 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 11:33:07.655552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 11:33:07.658369 ==
3528 11:33:07.658752
3529 11:33:07.659052
3530 11:33:07.659329 TX Vref Scan disable
3531 11:33:07.662323 == TX Byte 0 ==
3532 11:33:07.666066 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3533 11:33:07.669190 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3534 11:33:07.671891 == TX Byte 1 ==
3535 11:33:07.675563 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3536 11:33:07.682008 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3537 11:33:07.682399
3538 11:33:07.682701 [DATLAT]
3539 11:33:07.682979 Freq=1200, CH1 RK1
3540 11:33:07.683244
3541 11:33:07.685163 DATLAT Default: 0xd
3542 11:33:07.688662 0, 0xFFFF, sum = 0
3543 11:33:07.689070 1, 0xFFFF, sum = 0
3544 11:33:07.692070 2, 0xFFFF, sum = 0
3545 11:33:07.692607 3, 0xFFFF, sum = 0
3546 11:33:07.695138 4, 0xFFFF, sum = 0
3547 11:33:07.695544 5, 0xFFFF, sum = 0
3548 11:33:07.698379 6, 0xFFFF, sum = 0
3549 11:33:07.698786 7, 0xFFFF, sum = 0
3550 11:33:07.701984 8, 0xFFFF, sum = 0
3551 11:33:07.702390 9, 0xFFFF, sum = 0
3552 11:33:07.705578 10, 0xFFFF, sum = 0
3553 11:33:07.705983 11, 0xFFFF, sum = 0
3554 11:33:07.708472 12, 0x0, sum = 1
3555 11:33:07.708877 13, 0x0, sum = 2
3556 11:33:07.711891 14, 0x0, sum = 3
3557 11:33:07.712439 15, 0x0, sum = 4
3558 11:33:07.715608 best_step = 13
3559 11:33:07.716006
3560 11:33:07.716403 ==
3561 11:33:07.718846 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 11:33:07.722216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 11:33:07.722620 ==
3564 11:33:07.723014 RX Vref Scan: 0
3565 11:33:07.723402
3566 11:33:07.725683 RX Vref 0 -> 0, step: 1
3567 11:33:07.726087
3568 11:33:07.728684 RX Delay -13 -> 252, step: 4
3569 11:33:07.732054 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3570 11:33:07.739208 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3571 11:33:07.742285 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3572 11:33:07.745975 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3573 11:33:07.748624 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3574 11:33:07.752148 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3575 11:33:07.758112 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3576 11:33:07.762071 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3577 11:33:07.764984 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3578 11:33:07.768197 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3579 11:33:07.771686 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3580 11:33:07.778030 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3581 11:33:07.781725 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3582 11:33:07.785476 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3583 11:33:07.788117 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3584 11:33:07.795258 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3585 11:33:07.795340 ==
3586 11:33:07.797830 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:33:07.801010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:33:07.801114 ==
3589 11:33:07.801197 DQS Delay:
3590 11:33:07.804730 DQS0 = 0, DQS1 = 0
3591 11:33:07.804809 DQM Delay:
3592 11:33:07.807662 DQM0 = 114, DQM1 = 111
3593 11:33:07.807742 DQ Delay:
3594 11:33:07.811005 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3595 11:33:07.814466 DQ4 =112, DQ5 =122, DQ6 =120, DQ7 =112
3596 11:33:07.818086 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3597 11:33:07.821013 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3598 11:33:07.821148
3599 11:33:07.821248
3600 11:33:07.830971 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd0e, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
3601 11:33:07.834398 CH1 RK1: MR19=304, MR18=FD0E
3602 11:33:07.841275 CH1_RK1: MR19=0x304, MR18=0xFD0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3603 11:33:07.843963 [RxdqsGatingPostProcess] freq 1200
3604 11:33:07.847497 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3605 11:33:07.850358 best DQS0 dly(2T, 0.5T) = (0, 11)
3606 11:33:07.854357 best DQS1 dly(2T, 0.5T) = (0, 11)
3607 11:33:07.857154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3608 11:33:07.860661 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3609 11:33:07.863841 best DQS0 dly(2T, 0.5T) = (0, 11)
3610 11:33:07.867283 best DQS1 dly(2T, 0.5T) = (0, 11)
3611 11:33:07.870706 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3612 11:33:07.873990 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3613 11:33:07.877233 Pre-setting of DQS Precalculation
3614 11:33:07.880655 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3615 11:33:07.887767 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3616 11:33:07.897208 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3617 11:33:07.897617
3618 11:33:07.898023
3619 11:33:07.901240 [Calibration Summary] 2400 Mbps
3620 11:33:07.901643 CH 0, Rank 0
3621 11:33:07.904233 SW Impedance : PASS
3622 11:33:07.904637 DUTY Scan : NO K
3623 11:33:07.907192 ZQ Calibration : PASS
3624 11:33:07.910784 Jitter Meter : NO K
3625 11:33:07.911198 CBT Training : PASS
3626 11:33:07.913785 Write leveling : PASS
3627 11:33:07.914187 RX DQS gating : PASS
3628 11:33:07.917129 RX DQ/DQS(RDDQC) : PASS
3629 11:33:07.920508 TX DQ/DQS : PASS
3630 11:33:07.920914 RX DATLAT : PASS
3631 11:33:07.923565 RX DQ/DQS(Engine): PASS
3632 11:33:07.926791 TX OE : NO K
3633 11:33:07.927237 All Pass.
3634 11:33:07.927631
3635 11:33:07.928004 CH 0, Rank 1
3636 11:33:07.930133 SW Impedance : PASS
3637 11:33:07.933816 DUTY Scan : NO K
3638 11:33:07.934216 ZQ Calibration : PASS
3639 11:33:07.936810 Jitter Meter : NO K
3640 11:33:07.940328 CBT Training : PASS
3641 11:33:07.940728 Write leveling : PASS
3642 11:33:07.943631 RX DQS gating : PASS
3643 11:33:07.946808 RX DQ/DQS(RDDQC) : PASS
3644 11:33:07.947212 TX DQ/DQS : PASS
3645 11:33:07.950102 RX DATLAT : PASS
3646 11:33:07.953305 RX DQ/DQS(Engine): PASS
3647 11:33:07.953706 TX OE : NO K
3648 11:33:07.956983 All Pass.
3649 11:33:07.957420
3650 11:33:07.957818 CH 1, Rank 0
3651 11:33:07.959816 SW Impedance : PASS
3652 11:33:07.960216 DUTY Scan : NO K
3653 11:33:07.963245 ZQ Calibration : PASS
3654 11:33:07.966850 Jitter Meter : NO K
3655 11:33:07.967250 CBT Training : PASS
3656 11:33:07.969833 Write leveling : PASS
3657 11:33:07.973665 RX DQS gating : PASS
3658 11:33:07.974182 RX DQ/DQS(RDDQC) : PASS
3659 11:33:07.976499 TX DQ/DQS : PASS
3660 11:33:07.980025 RX DATLAT : PASS
3661 11:33:07.980424 RX DQ/DQS(Engine): PASS
3662 11:33:07.983234 TX OE : NO K
3663 11:33:07.983672 All Pass.
3664 11:33:07.984010
3665 11:33:07.986437 CH 1, Rank 1
3666 11:33:07.986897 SW Impedance : PASS
3667 11:33:07.989444 DUTY Scan : NO K
3668 11:33:07.992787 ZQ Calibration : PASS
3669 11:33:07.993221 Jitter Meter : NO K
3670 11:33:07.996537 CBT Training : PASS
3671 11:33:07.996935 Write leveling : PASS
3672 11:33:07.999310 RX DQS gating : PASS
3673 11:33:08.002859 RX DQ/DQS(RDDQC) : PASS
3674 11:33:08.003258 TX DQ/DQS : PASS
3675 11:33:08.006160 RX DATLAT : PASS
3676 11:33:08.009162 RX DQ/DQS(Engine): PASS
3677 11:33:08.009670 TX OE : NO K
3678 11:33:08.013016 All Pass.
3679 11:33:08.013456
3680 11:33:08.013851 DramC Write-DBI off
3681 11:33:08.015946 PER_BANK_REFRESH: Hybrid Mode
3682 11:33:08.019499 TX_TRACKING: ON
3683 11:33:08.025740 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3684 11:33:08.029162 [FAST_K] Save calibration result to emmc
3685 11:33:08.032566 dramc_set_vcore_voltage set vcore to 650000
3686 11:33:08.035916 Read voltage for 600, 5
3687 11:33:08.036315 Vio18 = 0
3688 11:33:08.039048 Vcore = 650000
3689 11:33:08.039447 Vdram = 0
3690 11:33:08.039840 Vddq = 0
3691 11:33:08.042338 Vmddr = 0
3692 11:33:08.045866 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3693 11:33:08.052628 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3694 11:33:08.053038 MEM_TYPE=3, freq_sel=19
3695 11:33:08.055994 sv_algorithm_assistance_LP4_1600
3696 11:33:08.062150 ============ PULL DRAM RESETB DOWN ============
3697 11:33:08.065911 ========== PULL DRAM RESETB DOWN end =========
3698 11:33:08.069038 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3699 11:33:08.072145 ===================================
3700 11:33:08.075704 LPDDR4 DRAM CONFIGURATION
3701 11:33:08.078787 ===================================
3702 11:33:08.082368 EX_ROW_EN[0] = 0x0
3703 11:33:08.082766 EX_ROW_EN[1] = 0x0
3704 11:33:08.085381 LP4Y_EN = 0x0
3705 11:33:08.085782 WORK_FSP = 0x0
3706 11:33:08.088930 WL = 0x2
3707 11:33:08.089389 RL = 0x2
3708 11:33:08.092285 BL = 0x2
3709 11:33:08.092682 RPST = 0x0
3710 11:33:08.095310 RD_PRE = 0x0
3711 11:33:08.095711 WR_PRE = 0x1
3712 11:33:08.098761 WR_PST = 0x0
3713 11:33:08.099159 DBI_WR = 0x0
3714 11:33:08.101827 DBI_RD = 0x0
3715 11:33:08.102224 OTF = 0x1
3716 11:33:08.105265 ===================================
3717 11:33:08.108457 ===================================
3718 11:33:08.111967 ANA top config
3719 11:33:08.114904 ===================================
3720 11:33:08.118691 DLL_ASYNC_EN = 0
3721 11:33:08.119092 ALL_SLAVE_EN = 1
3722 11:33:08.121267 NEW_RANK_MODE = 1
3723 11:33:08.124969 DLL_IDLE_MODE = 1
3724 11:33:08.128101 LP45_APHY_COMB_EN = 1
3725 11:33:08.131455 TX_ODT_DIS = 1
3726 11:33:08.131867 NEW_8X_MODE = 1
3727 11:33:08.135077 ===================================
3728 11:33:08.138245 ===================================
3729 11:33:08.141306 data_rate = 1200
3730 11:33:08.144458 CKR = 1
3731 11:33:08.147898 DQ_P2S_RATIO = 8
3732 11:33:08.151356 ===================================
3733 11:33:08.154433 CA_P2S_RATIO = 8
3734 11:33:08.157923 DQ_CA_OPEN = 0
3735 11:33:08.158382 DQ_SEMI_OPEN = 0
3736 11:33:08.162188 CA_SEMI_OPEN = 0
3737 11:33:08.164341 CA_FULL_RATE = 0
3738 11:33:08.169528 DQ_CKDIV4_EN = 1
3739 11:33:08.171575 CA_CKDIV4_EN = 1
3740 11:33:08.174992 CA_PREDIV_EN = 0
3741 11:33:08.175523 PH8_DLY = 0
3742 11:33:08.177613 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3743 11:33:08.180493 DQ_AAMCK_DIV = 4
3744 11:33:08.184160 CA_AAMCK_DIV = 4
3745 11:33:08.187251 CA_ADMCK_DIV = 4
3746 11:33:08.190396 DQ_TRACK_CA_EN = 0
3747 11:33:08.193723 CA_PICK = 600
3748 11:33:08.194103 CA_MCKIO = 600
3749 11:33:08.197341 MCKIO_SEMI = 0
3750 11:33:08.200685 PLL_FREQ = 2288
3751 11:33:08.204037 DQ_UI_PI_RATIO = 32
3752 11:33:08.206707 CA_UI_PI_RATIO = 0
3753 11:33:08.210434 ===================================
3754 11:33:08.213426 ===================================
3755 11:33:08.216854 memory_type:LPDDR4
3756 11:33:08.217434 GP_NUM : 10
3757 11:33:08.220507 SRAM_EN : 1
3758 11:33:08.223435 MD32_EN : 0
3759 11:33:08.226840 ===================================
3760 11:33:08.227229 [ANA_INIT] >>>>>>>>>>>>>>
3761 11:33:08.229871 <<<<<< [CONFIGURE PHASE]: ANA_TX
3762 11:33:08.233228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3763 11:33:08.237123 ===================================
3764 11:33:08.240188 data_rate = 1200,PCW = 0X5800
3765 11:33:08.243198 ===================================
3766 11:33:08.246553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3767 11:33:08.253331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3768 11:33:08.256220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3769 11:33:08.263100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3770 11:33:08.266188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3771 11:33:08.269379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3772 11:33:08.272629 [ANA_INIT] flow start
3773 11:33:08.273033 [ANA_INIT] PLL >>>>>>>>
3774 11:33:08.275814 [ANA_INIT] PLL <<<<<<<<
3775 11:33:08.279341 [ANA_INIT] MIDPI >>>>>>>>
3776 11:33:08.279717 [ANA_INIT] MIDPI <<<<<<<<
3777 11:33:08.282717 [ANA_INIT] DLL >>>>>>>>
3778 11:33:08.286190 [ANA_INIT] flow end
3779 11:33:08.288868 ============ LP4 DIFF to SE enter ============
3780 11:33:08.292884 ============ LP4 DIFF to SE exit ============
3781 11:33:08.296275 [ANA_INIT] <<<<<<<<<<<<<
3782 11:33:08.299018 [Flow] Enable top DCM control >>>>>
3783 11:33:08.302857 [Flow] Enable top DCM control <<<<<
3784 11:33:08.305657 Enable DLL master slave shuffle
3785 11:33:08.308869 ==============================================================
3786 11:33:08.312673 Gating Mode config
3787 11:33:08.319279 ==============================================================
3788 11:33:08.319824 Config description:
3789 11:33:08.328594 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3790 11:33:08.335068 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3791 11:33:08.341613 SELPH_MODE 0: By rank 1: By Phase
3792 11:33:08.345182 ==============================================================
3793 11:33:08.348123 GAT_TRACK_EN = 1
3794 11:33:08.351759 RX_GATING_MODE = 2
3795 11:33:08.354374 RX_GATING_TRACK_MODE = 2
3796 11:33:08.357970 SELPH_MODE = 1
3797 11:33:08.361652 PICG_EARLY_EN = 1
3798 11:33:08.364207 VALID_LAT_VALUE = 1
3799 11:33:08.371269 ==============================================================
3800 11:33:08.374175 Enter into Gating configuration >>>>
3801 11:33:08.377697 Exit from Gating configuration <<<<
3802 11:33:08.377773 Enter into DVFS_PRE_config >>>>>
3803 11:33:08.390976 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3804 11:33:08.394030 Exit from DVFS_PRE_config <<<<<
3805 11:33:08.397610 Enter into PICG configuration >>>>
3806 11:33:08.400508 Exit from PICG configuration <<<<
3807 11:33:08.404189 [RX_INPUT] configuration >>>>>
3808 11:33:08.404283 [RX_INPUT] configuration <<<<<
3809 11:33:08.410505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3810 11:33:08.417189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3811 11:33:08.420907 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3812 11:33:08.427185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3813 11:33:08.433926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3814 11:33:08.440362 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3815 11:33:08.443780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3816 11:33:08.447007 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3817 11:33:08.453300 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3818 11:33:08.456999 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3819 11:33:08.459843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3820 11:33:08.466444 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3821 11:33:08.469952 ===================================
3822 11:33:08.470028 LPDDR4 DRAM CONFIGURATION
3823 11:33:08.473438 ===================================
3824 11:33:08.476881 EX_ROW_EN[0] = 0x0
3825 11:33:08.476956 EX_ROW_EN[1] = 0x0
3826 11:33:08.479980 LP4Y_EN = 0x0
3827 11:33:08.483295 WORK_FSP = 0x0
3828 11:33:08.483369 WL = 0x2
3829 11:33:08.486687 RL = 0x2
3830 11:33:08.486762 BL = 0x2
3831 11:33:08.489816 RPST = 0x0
3832 11:33:08.489890 RD_PRE = 0x0
3833 11:33:08.493426 WR_PRE = 0x1
3834 11:33:08.493500 WR_PST = 0x0
3835 11:33:08.496179 DBI_WR = 0x0
3836 11:33:08.496248 DBI_RD = 0x0
3837 11:33:08.499859 OTF = 0x1
3838 11:33:08.503271 ===================================
3839 11:33:08.505965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3840 11:33:08.509590 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3841 11:33:08.516164 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3842 11:33:08.519450 ===================================
3843 11:33:08.519519 LPDDR4 DRAM CONFIGURATION
3844 11:33:08.522848 ===================================
3845 11:33:08.525847 EX_ROW_EN[0] = 0x10
3846 11:33:08.529387 EX_ROW_EN[1] = 0x0
3847 11:33:08.529452 LP4Y_EN = 0x0
3848 11:33:08.532689 WORK_FSP = 0x0
3849 11:33:08.532751 WL = 0x2
3850 11:33:08.535567 RL = 0x2
3851 11:33:08.535638 BL = 0x2
3852 11:33:08.539199 RPST = 0x0
3853 11:33:08.539304 RD_PRE = 0x0
3854 11:33:08.542496 WR_PRE = 0x1
3855 11:33:08.542571 WR_PST = 0x0
3856 11:33:08.545668 DBI_WR = 0x0
3857 11:33:08.545768 DBI_RD = 0x0
3858 11:33:08.548844 OTF = 0x1
3859 11:33:08.552469 ===================================
3860 11:33:08.558840 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3861 11:33:08.562293 nWR fixed to 30
3862 11:33:08.562383 [ModeRegInit_LP4] CH0 RK0
3863 11:33:08.565870 [ModeRegInit_LP4] CH0 RK1
3864 11:33:08.568673 [ModeRegInit_LP4] CH1 RK0
3865 11:33:08.572344 [ModeRegInit_LP4] CH1 RK1
3866 11:33:08.572408 match AC timing 17
3867 11:33:08.579247 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3868 11:33:08.582184 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3869 11:33:08.585725 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3870 11:33:08.591969 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3871 11:33:08.595579 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3872 11:33:08.595659 ==
3873 11:33:08.598329 Dram Type= 6, Freq= 0, CH_0, rank 0
3874 11:33:08.601603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3875 11:33:08.601665 ==
3876 11:33:08.608199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3877 11:33:08.614900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3878 11:33:08.618194 [CA 0] Center 36 (6~67) winsize 62
3879 11:33:08.621485 [CA 1] Center 36 (6~67) winsize 62
3880 11:33:08.625259 [CA 2] Center 34 (4~65) winsize 62
3881 11:33:08.628190 [CA 3] Center 34 (3~65) winsize 63
3882 11:33:08.631572 [CA 4] Center 33 (3~64) winsize 62
3883 11:33:08.634650 [CA 5] Center 33 (3~64) winsize 62
3884 11:33:08.634740
3885 11:33:08.638092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3886 11:33:08.638167
3887 11:33:08.641285 [CATrainingPosCal] consider 1 rank data
3888 11:33:08.644527 u2DelayCellTimex100 = 270/100 ps
3889 11:33:08.648060 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3890 11:33:08.651296 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3891 11:33:08.654648 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3892 11:33:08.658340 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3893 11:33:08.661533 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3894 11:33:08.667927 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3895 11:33:08.668000
3896 11:33:08.670966 CA PerBit enable=1, Macro0, CA PI delay=33
3897 11:33:08.671046
3898 11:33:08.674837 [CBTSetCACLKResult] CA Dly = 33
3899 11:33:08.674905 CS Dly: 4 (0~35)
3900 11:33:08.674961 ==
3901 11:33:08.677489 Dram Type= 6, Freq= 0, CH_0, rank 1
3902 11:33:08.681373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 11:33:08.684521 ==
3904 11:33:08.687724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 11:33:08.694266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3906 11:33:08.697574 [CA 0] Center 36 (6~67) winsize 62
3907 11:33:08.701006 [CA 1] Center 36 (6~67) winsize 62
3908 11:33:08.704756 [CA 2] Center 34 (4~65) winsize 62
3909 11:33:08.707462 [CA 3] Center 34 (4~65) winsize 62
3910 11:33:08.710890 [CA 4] Center 34 (3~65) winsize 63
3911 11:33:08.713878 [CA 5] Center 33 (3~64) winsize 62
3912 11:33:08.713955
3913 11:33:08.717004 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3914 11:33:08.717081
3915 11:33:08.720835 [CATrainingPosCal] consider 2 rank data
3916 11:33:08.723782 u2DelayCellTimex100 = 270/100 ps
3917 11:33:08.727018 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3918 11:33:08.730285 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3919 11:33:08.737036 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3920 11:33:08.740109 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3921 11:33:08.743926 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3922 11:33:08.747139 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3923 11:33:08.747216
3924 11:33:08.750575 CA PerBit enable=1, Macro0, CA PI delay=33
3925 11:33:08.750652
3926 11:33:08.753615 [CBTSetCACLKResult] CA Dly = 33
3927 11:33:08.753697 CS Dly: 5 (0~37)
3928 11:33:08.753760
3929 11:33:08.760039 ----->DramcWriteLeveling(PI) begin...
3930 11:33:08.760120 ==
3931 11:33:08.763214 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 11:33:08.766767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 11:33:08.766842 ==
3934 11:33:08.769806 Write leveling (Byte 0): 34 => 34
3935 11:33:08.773648 Write leveling (Byte 1): 30 => 30
3936 11:33:08.776561 DramcWriteLeveling(PI) end<-----
3937 11:33:08.776630
3938 11:33:08.776693 ==
3939 11:33:08.779871 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 11:33:08.782887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 11:33:08.782990 ==
3942 11:33:08.786453 [Gating] SW mode calibration
3943 11:33:08.793375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3944 11:33:08.799593 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3945 11:33:08.802671 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3946 11:33:08.806221 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3947 11:33:08.812895 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3948 11:33:08.816158 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3949 11:33:08.819686 0 9 16 | B1->B0 | 2c2c 2626 | 1 0 | (1 1) (1 0)
3950 11:33:08.825927 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3951 11:33:08.829228 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3952 11:33:08.832399 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3953 11:33:08.839248 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3954 11:33:08.842704 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3955 11:33:08.845626 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3956 11:33:08.851997 0 10 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
3957 11:33:08.855770 0 10 16 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
3958 11:33:08.858633 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3959 11:33:08.865239 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3960 11:33:08.868711 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3961 11:33:08.871898 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3962 11:33:08.878646 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3963 11:33:08.882342 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3964 11:33:08.885274 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3965 11:33:08.892198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3966 11:33:08.895030 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3967 11:33:08.898400 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3968 11:33:08.905086 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3969 11:33:08.908521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3970 11:33:08.912131 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3971 11:33:08.918844 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3972 11:33:08.921665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3973 11:33:08.925225 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3974 11:33:08.931680 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 11:33:08.934975 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 11:33:08.938359 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 11:33:08.944900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 11:33:08.948242 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 11:33:08.951795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 11:33:08.958218 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3981 11:33:08.958342 Total UI for P1: 0, mck2ui 16
3982 11:33:08.964369 best dqsien dly found for B0: ( 0, 13, 10)
3983 11:33:08.968133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3984 11:33:08.971024 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3985 11:33:08.977967 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 11:33:08.978043 Total UI for P1: 0, mck2ui 16
3987 11:33:08.981249 best dqsien dly found for B1: ( 0, 13, 20)
3988 11:33:08.987649 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
3989 11:33:08.990900 best DQS1 dly(MCK, UI, PI) = (0, 13, 20)
3990 11:33:08.990998
3991 11:33:08.994521 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
3992 11:33:08.997495 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 20)
3993 11:33:09.000851 [Gating] SW calibration Done
3994 11:33:09.000951 ==
3995 11:33:09.004350 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 11:33:09.007158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 11:33:09.007234 ==
3998 11:33:09.010780 RX Vref Scan: 0
3999 11:33:09.010851
4000 11:33:09.010907 RX Vref 0 -> 0, step: 1
4001 11:33:09.010966
4002 11:33:09.013897 RX Delay -230 -> 252, step: 16
4003 11:33:09.020359 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4004 11:33:09.024242 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4005 11:33:09.027560 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4006 11:33:09.030552 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4007 11:33:09.037091 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4008 11:33:09.040513 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4009 11:33:09.043378 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4010 11:33:09.046723 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4011 11:33:09.049970 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4012 11:33:09.056640 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4013 11:33:09.059883 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4014 11:33:09.063047 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4015 11:33:09.066873 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4016 11:33:09.073252 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4017 11:33:09.076423 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4018 11:33:09.079906 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4019 11:33:09.080009 ==
4020 11:33:09.083039 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 11:33:09.089825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 11:33:09.089899 ==
4023 11:33:09.089958 DQS Delay:
4024 11:33:09.092715 DQS0 = 0, DQS1 = 0
4025 11:33:09.092811 DQM Delay:
4026 11:33:09.092892 DQM0 = 42, DQM1 = 35
4027 11:33:09.096316 DQ Delay:
4028 11:33:09.099412 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4029 11:33:09.102638 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4030 11:33:09.106123 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4031 11:33:09.109578 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4032 11:33:09.109653
4033 11:33:09.109714
4034 11:33:09.109768 ==
4035 11:33:09.112495 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 11:33:09.116172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 11:33:09.116244 ==
4038 11:33:09.116308
4039 11:33:09.116365
4040 11:33:09.119207 TX Vref Scan disable
4041 11:33:09.122814 == TX Byte 0 ==
4042 11:33:09.125875 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4043 11:33:09.129492 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4044 11:33:09.132472 == TX Byte 1 ==
4045 11:33:09.135732 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4046 11:33:09.138983 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4047 11:33:09.139056 ==
4048 11:33:09.142723 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 11:33:09.145368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 11:33:09.149317 ==
4051 11:33:09.149383
4052 11:33:09.149445
4053 11:33:09.149500 TX Vref Scan disable
4054 11:33:09.152859 == TX Byte 0 ==
4055 11:33:09.156083 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4056 11:33:09.163017 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4057 11:33:09.163089 == TX Byte 1 ==
4058 11:33:09.165769 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4059 11:33:09.172588 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4060 11:33:09.172666
4061 11:33:09.172728 [DATLAT]
4062 11:33:09.172787 Freq=600, CH0 RK0
4063 11:33:09.172840
4064 11:33:09.176344 DATLAT Default: 0x9
4065 11:33:09.179343 0, 0xFFFF, sum = 0
4066 11:33:09.179443 1, 0xFFFF, sum = 0
4067 11:33:09.182473 2, 0xFFFF, sum = 0
4068 11:33:09.182550 3, 0xFFFF, sum = 0
4069 11:33:09.186121 4, 0xFFFF, sum = 0
4070 11:33:09.186195 5, 0xFFFF, sum = 0
4071 11:33:09.188944 6, 0xFFFF, sum = 0
4072 11:33:09.189043 7, 0xFFFF, sum = 0
4073 11:33:09.192976 8, 0x0, sum = 1
4074 11:33:09.193072 9, 0x0, sum = 2
4075 11:33:09.196293 10, 0x0, sum = 3
4076 11:33:09.196368 11, 0x0, sum = 4
4077 11:33:09.196431 best_step = 9
4078 11:33:09.196488
4079 11:33:09.199277 ==
4080 11:33:09.202228 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 11:33:09.205926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 11:33:09.206017 ==
4083 11:33:09.206093 RX Vref Scan: 1
4084 11:33:09.206148
4085 11:33:09.209244 RX Vref 0 -> 0, step: 1
4086 11:33:09.209318
4087 11:33:09.212137 RX Delay -179 -> 252, step: 8
4088 11:33:09.212206
4089 11:33:09.215447 Set Vref, RX VrefLevel [Byte0]: 51
4090 11:33:09.218927 [Byte1]: 59
4091 11:33:09.218992
4092 11:33:09.222332 Final RX Vref Byte 0 = 51 to rank0
4093 11:33:09.225386 Final RX Vref Byte 1 = 59 to rank0
4094 11:33:09.228917 Final RX Vref Byte 0 = 51 to rank1
4095 11:33:09.232154 Final RX Vref Byte 1 = 59 to rank1==
4096 11:33:09.235038 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 11:33:09.238206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 11:33:09.241899 ==
4099 11:33:09.241973 DQS Delay:
4100 11:33:09.242031 DQS0 = 0, DQS1 = 0
4101 11:33:09.245017 DQM Delay:
4102 11:33:09.245093 DQM0 = 41, DQM1 = 33
4103 11:33:09.248185 DQ Delay:
4104 11:33:09.251590 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4105 11:33:09.255114 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4106 11:33:09.258313 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =32
4107 11:33:09.261426 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4108 11:33:09.261501
4109 11:33:09.261559
4110 11:33:09.268339 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4111 11:33:09.271168 CH0 RK0: MR19=808, MR18=4B43
4112 11:33:09.277994 CH0_RK0: MR19=0x808, MR18=0x4B43, DQSOSC=395, MR23=63, INC=168, DEC=112
4113 11:33:09.278070
4114 11:33:09.281362 ----->DramcWriteLeveling(PI) begin...
4115 11:33:09.281439 ==
4116 11:33:09.284702 Dram Type= 6, Freq= 0, CH_0, rank 1
4117 11:33:09.287668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 11:33:09.287767 ==
4119 11:33:09.290957 Write leveling (Byte 0): 33 => 33
4120 11:33:09.294911 Write leveling (Byte 1): 29 => 29
4121 11:33:09.297781 DramcWriteLeveling(PI) end<-----
4122 11:33:09.297858
4123 11:33:09.297918 ==
4124 11:33:09.301119 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 11:33:09.304153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 11:33:09.307869 ==
4127 11:33:09.307973 [Gating] SW mode calibration
4128 11:33:09.314126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4129 11:33:09.320919 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4130 11:33:09.323930 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4131 11:33:09.330882 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4132 11:33:09.333813 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4133 11:33:09.337132 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4134 11:33:09.343588 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4135 11:33:09.347197 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4136 11:33:09.350380 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4137 11:33:09.357250 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4138 11:33:09.360267 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4139 11:33:09.363844 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4140 11:33:09.370056 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4141 11:33:09.373400 0 10 12 | B1->B0 | 2626 3332 | 0 1 | (0 0) (0 0)
4142 11:33:09.377004 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4143 11:33:09.383443 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4144 11:33:09.386842 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4145 11:33:09.390071 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4146 11:33:09.396693 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4147 11:33:09.399699 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4148 11:33:09.403027 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4149 11:33:09.409500 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4150 11:33:09.413130 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4151 11:33:09.416540 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4152 11:33:09.423066 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4153 11:33:09.426028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4154 11:33:09.429530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4155 11:33:09.436336 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4156 11:33:09.439114 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4157 11:33:09.442526 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4158 11:33:09.449078 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4159 11:33:09.452779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 11:33:09.455651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 11:33:09.462513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 11:33:09.465528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 11:33:09.469190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 11:33:09.475383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 11:33:09.478911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4166 11:33:09.482581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 11:33:09.485450 Total UI for P1: 0, mck2ui 16
4168 11:33:09.489130 best dqsien dly found for B0: ( 0, 13, 12)
4169 11:33:09.491819 Total UI for P1: 0, mck2ui 16
4170 11:33:09.495334 best dqsien dly found for B1: ( 0, 13, 14)
4171 11:33:09.498715 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4172 11:33:09.502245 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4173 11:33:09.505235
4174 11:33:09.508345 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4175 11:33:09.512073 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4176 11:33:09.515049 [Gating] SW calibration Done
4177 11:33:09.515120 ==
4178 11:33:09.518314 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 11:33:09.521599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 11:33:09.521700 ==
4181 11:33:09.524843 RX Vref Scan: 0
4182 11:33:09.524958
4183 11:33:09.525051 RX Vref 0 -> 0, step: 1
4184 11:33:09.525133
4185 11:33:09.528150 RX Delay -230 -> 252, step: 16
4186 11:33:09.531316 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4187 11:33:09.538197 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4188 11:33:09.541089 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4189 11:33:09.544688 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4190 11:33:09.548079 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4191 11:33:09.554597 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4192 11:33:09.558147 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4193 11:33:09.561043 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4194 11:33:09.564741 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4195 11:33:09.567710 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4196 11:33:09.574287 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4197 11:33:09.577683 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4198 11:33:09.580979 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4199 11:33:09.584487 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4200 11:33:09.591078 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4201 11:33:09.594127 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4202 11:33:09.594196 ==
4203 11:33:09.597460 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 11:33:09.601040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 11:33:09.601111 ==
4206 11:33:09.604006 DQS Delay:
4207 11:33:09.604097 DQS0 = 0, DQS1 = 0
4208 11:33:09.607851 DQM Delay:
4209 11:33:09.607919 DQM0 = 43, DQM1 = 33
4210 11:33:09.607976 DQ Delay:
4211 11:33:09.610990 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4212 11:33:09.613829 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4213 11:33:09.617594 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4214 11:33:09.620756 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4215 11:33:09.620833
4216 11:33:09.620892
4217 11:33:09.623832 ==
4218 11:33:09.623909 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 11:33:09.630543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 11:33:09.630621 ==
4221 11:33:09.630681
4222 11:33:09.630736
4223 11:33:09.633626 TX Vref Scan disable
4224 11:33:09.633703 == TX Byte 0 ==
4225 11:33:09.640178 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4226 11:33:09.643349 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4227 11:33:09.643426 == TX Byte 1 ==
4228 11:33:09.650152 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4229 11:33:09.653570 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4230 11:33:09.653648 ==
4231 11:33:09.657161 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 11:33:09.660145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 11:33:09.660246 ==
4234 11:33:09.660333
4235 11:33:09.660414
4236 11:33:09.663643 TX Vref Scan disable
4237 11:33:09.666731 == TX Byte 0 ==
4238 11:33:09.670480 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4239 11:33:09.673404 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4240 11:33:09.676756 == TX Byte 1 ==
4241 11:33:09.679739 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4242 11:33:09.683122 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4243 11:33:09.686750
4244 11:33:09.686844 [DATLAT]
4245 11:33:09.686929 Freq=600, CH0 RK1
4246 11:33:09.687021
4247 11:33:09.690325 DATLAT Default: 0x9
4248 11:33:09.690414 0, 0xFFFF, sum = 0
4249 11:33:09.693418 1, 0xFFFF, sum = 0
4250 11:33:09.693509 2, 0xFFFF, sum = 0
4251 11:33:09.696504 3, 0xFFFF, sum = 0
4252 11:33:09.700001 4, 0xFFFF, sum = 0
4253 11:33:09.700093 5, 0xFFFF, sum = 0
4254 11:33:09.703167 6, 0xFFFF, sum = 0
4255 11:33:09.703258 7, 0xFFFF, sum = 0
4256 11:33:09.706363 8, 0x0, sum = 1
4257 11:33:09.706443 9, 0x0, sum = 2
4258 11:33:09.706499 10, 0x0, sum = 3
4259 11:33:09.709387 11, 0x0, sum = 4
4260 11:33:09.709491 best_step = 9
4261 11:33:09.709542
4262 11:33:09.709603 ==
4263 11:33:09.712858 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 11:33:09.719301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 11:33:09.719395 ==
4266 11:33:09.719484 RX Vref Scan: 0
4267 11:33:09.719564
4268 11:33:09.722845 RX Vref 0 -> 0, step: 1
4269 11:33:09.722930
4270 11:33:09.725768 RX Delay -195 -> 252, step: 8
4271 11:33:09.729321 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4272 11:33:09.735656 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4273 11:33:09.739181 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4274 11:33:09.742681 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4275 11:33:09.745765 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4276 11:33:09.752568 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4277 11:33:09.755547 iDelay=197, Bit 6, Center 52 (-91 ~ 196) 288
4278 11:33:09.758792 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4279 11:33:09.762000 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4280 11:33:09.768656 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4281 11:33:09.771799 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4282 11:33:09.775496 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4283 11:33:09.778338 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4284 11:33:09.784912 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4285 11:33:09.788378 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4286 11:33:09.791622 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4287 11:33:09.791721 ==
4288 11:33:09.795001 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 11:33:09.798706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 11:33:09.801619 ==
4291 11:33:09.801699 DQS Delay:
4292 11:33:09.801754 DQS0 = 0, DQS1 = 0
4293 11:33:09.804910 DQM Delay:
4294 11:33:09.804997 DQM0 = 41, DQM1 = 33
4295 11:33:09.808478 DQ Delay:
4296 11:33:09.811457 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4297 11:33:09.811522 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =48
4298 11:33:09.814685 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4299 11:33:09.821227 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4300 11:33:09.821317
4301 11:33:09.821397
4302 11:33:09.827682 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4303 11:33:09.831127 CH0 RK1: MR19=808, MR18=4C47
4304 11:33:09.837641 CH0_RK1: MR19=0x808, MR18=0x4C47, DQSOSC=395, MR23=63, INC=168, DEC=112
4305 11:33:09.840656 [RxdqsGatingPostProcess] freq 600
4306 11:33:09.844529 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4307 11:33:09.847699 Pre-setting of DQS Precalculation
4308 11:33:09.854241 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4309 11:33:09.854311 ==
4310 11:33:09.857282 Dram Type= 6, Freq= 0, CH_1, rank 0
4311 11:33:09.861059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 11:33:09.861189 ==
4313 11:33:09.867590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4314 11:33:09.874111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4315 11:33:09.877654 [CA 0] Center 36 (6~66) winsize 61
4316 11:33:09.880464 [CA 1] Center 35 (5~66) winsize 62
4317 11:33:09.883597 [CA 2] Center 34 (4~65) winsize 62
4318 11:33:09.887269 [CA 3] Center 34 (4~65) winsize 62
4319 11:33:09.890327 [CA 4] Center 34 (4~65) winsize 62
4320 11:33:09.893561 [CA 5] Center 34 (3~65) winsize 63
4321 11:33:09.893637
4322 11:33:09.897183 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4323 11:33:09.897259
4324 11:33:09.900358 [CATrainingPosCal] consider 1 rank data
4325 11:33:09.903539 u2DelayCellTimex100 = 270/100 ps
4326 11:33:09.907032 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4327 11:33:09.910020 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4328 11:33:09.913553 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4329 11:33:09.916549 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4330 11:33:09.919759 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4331 11:33:09.923546 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4332 11:33:09.923641
4333 11:33:09.929851 CA PerBit enable=1, Macro0, CA PI delay=34
4334 11:33:09.929928
4335 11:33:09.933289 [CBTSetCACLKResult] CA Dly = 34
4336 11:33:09.933355 CS Dly: 3 (0~34)
4337 11:33:09.933410 ==
4338 11:33:09.936459 Dram Type= 6, Freq= 0, CH_1, rank 1
4339 11:33:09.939654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 11:33:09.939734 ==
4341 11:33:09.946573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4342 11:33:09.953105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4343 11:33:09.956021 [CA 0] Center 36 (6~66) winsize 61
4344 11:33:09.959608 [CA 1] Center 35 (5~66) winsize 62
4345 11:33:09.962537 [CA 2] Center 34 (4~65) winsize 62
4346 11:33:09.965940 [CA 3] Center 34 (3~65) winsize 63
4347 11:33:09.969641 [CA 4] Center 34 (4~64) winsize 61
4348 11:33:09.972637 [CA 5] Center 33 (3~64) winsize 62
4349 11:33:09.972702
4350 11:33:09.976114 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4351 11:33:09.976190
4352 11:33:09.979042 [CATrainingPosCal] consider 2 rank data
4353 11:33:09.982739 u2DelayCellTimex100 = 270/100 ps
4354 11:33:09.985843 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4355 11:33:09.989369 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4356 11:33:09.992942 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 11:33:09.999012 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 11:33:10.002458 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4359 11:33:10.005884 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4360 11:33:10.005959
4361 11:33:10.008813 CA PerBit enable=1, Macro0, CA PI delay=33
4362 11:33:10.008899
4363 11:33:10.011932 [CBTSetCACLKResult] CA Dly = 33
4364 11:33:10.012008 CS Dly: 4 (0~37)
4365 11:33:10.012066
4366 11:33:10.015351 ----->DramcWriteLeveling(PI) begin...
4367 11:33:10.018526 ==
4368 11:33:10.018618 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 11:33:10.025421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 11:33:10.025514 ==
4371 11:33:10.028777 Write leveling (Byte 0): 28 => 28
4372 11:33:10.031834 Write leveling (Byte 1): 32 => 32
4373 11:33:10.035615 DramcWriteLeveling(PI) end<-----
4374 11:33:10.035719
4375 11:33:10.035780 ==
4376 11:33:10.038288 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 11:33:10.041937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 11:33:10.042015 ==
4379 11:33:10.044908 [Gating] SW mode calibration
4380 11:33:10.052055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4381 11:33:10.057898 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4382 11:33:10.061513 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4383 11:33:10.064804 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4384 11:33:10.071626 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4385 11:33:10.074483 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (0 1)
4386 11:33:10.078205 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4387 11:33:10.084729 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4388 11:33:10.088026 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4389 11:33:10.091238 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4390 11:33:10.097849 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4391 11:33:10.100947 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4392 11:33:10.104002 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4393 11:33:10.111028 0 10 12 | B1->B0 | 3333 3737 | 0 1 | (0 0) (0 0)
4394 11:33:10.113861 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4395 11:33:10.117452 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4396 11:33:10.123892 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4397 11:33:10.127612 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4398 11:33:10.130641 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4399 11:33:10.137265 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4400 11:33:10.140258 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4401 11:33:10.143914 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4402 11:33:10.150190 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4403 11:33:10.153717 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4404 11:33:10.156801 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4405 11:33:10.163450 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4406 11:33:10.166848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4407 11:33:10.169987 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4408 11:33:10.176675 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4409 11:33:10.179693 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4410 11:33:10.183144 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 11:33:10.190033 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 11:33:10.193387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 11:33:10.196258 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:33:10.202799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 11:33:10.206375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 11:33:10.209574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:33:10.216014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4418 11:33:10.219437 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 11:33:10.222568 Total UI for P1: 0, mck2ui 16
4420 11:33:10.226131 best dqsien dly found for B0: ( 0, 13, 12)
4421 11:33:10.229205 Total UI for P1: 0, mck2ui 16
4422 11:33:10.232633 best dqsien dly found for B1: ( 0, 13, 12)
4423 11:33:10.236376 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4424 11:33:10.239528 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4425 11:33:10.239597
4426 11:33:10.242509 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4427 11:33:10.245656 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4428 11:33:10.249018 [Gating] SW calibration Done
4429 11:33:10.249131 ==
4430 11:33:10.252477 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 11:33:10.258857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 11:33:10.258928 ==
4433 11:33:10.259001 RX Vref Scan: 0
4434 11:33:10.259090
4435 11:33:10.262262 RX Vref 0 -> 0, step: 1
4436 11:33:10.262332
4437 11:33:10.265229 RX Delay -230 -> 252, step: 16
4438 11:33:10.268819 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4439 11:33:10.271863 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4440 11:33:10.275334 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4441 11:33:10.281937 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4442 11:33:10.285272 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4443 11:33:10.288432 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4444 11:33:10.291559 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4445 11:33:10.298506 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4446 11:33:10.301380 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4447 11:33:10.304654 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4448 11:33:10.308190 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4449 11:33:10.314676 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4450 11:33:10.318236 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4451 11:33:10.321369 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4452 11:33:10.324671 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4453 11:33:10.331221 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4454 11:33:10.331291 ==
4455 11:33:10.334164 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 11:33:10.337816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 11:33:10.337885 ==
4458 11:33:10.337944 DQS Delay:
4459 11:33:10.341057 DQS0 = 0, DQS1 = 0
4460 11:33:10.341144 DQM Delay:
4461 11:33:10.344739 DQM0 = 43, DQM1 = 37
4462 11:33:10.344849 DQ Delay:
4463 11:33:10.347357 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4464 11:33:10.350905 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4465 11:33:10.354389 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4466 11:33:10.357338 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4467 11:33:10.357433
4468 11:33:10.357517
4469 11:33:10.357606 ==
4470 11:33:10.360832 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 11:33:10.363799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 11:33:10.367167 ==
4473 11:33:10.367262
4474 11:33:10.367349
4475 11:33:10.367429 TX Vref Scan disable
4476 11:33:10.370814 == TX Byte 0 ==
4477 11:33:10.373748 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4478 11:33:10.380681 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4479 11:33:10.380752 == TX Byte 1 ==
4480 11:33:10.383542 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4481 11:33:10.390829 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4482 11:33:10.390912 ==
4483 11:33:10.393419 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 11:33:10.397008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 11:33:10.397105 ==
4486 11:33:10.397226
4487 11:33:10.397322
4488 11:33:10.400170 TX Vref Scan disable
4489 11:33:10.403343 == TX Byte 0 ==
4490 11:33:10.406574 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4491 11:33:10.410464 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4492 11:33:10.413402 == TX Byte 1 ==
4493 11:33:10.416862 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4494 11:33:10.420039 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4495 11:33:10.420107
4496 11:33:10.423383 [DATLAT]
4497 11:33:10.423478 Freq=600, CH1 RK0
4498 11:33:10.423561
4499 11:33:10.426672 DATLAT Default: 0x9
4500 11:33:10.426741 0, 0xFFFF, sum = 0
4501 11:33:10.429730 1, 0xFFFF, sum = 0
4502 11:33:10.429888 2, 0xFFFF, sum = 0
4503 11:33:10.433444 3, 0xFFFF, sum = 0
4504 11:33:10.433546 4, 0xFFFF, sum = 0
4505 11:33:10.436330 5, 0xFFFF, sum = 0
4506 11:33:10.436438 6, 0xFFFF, sum = 0
4507 11:33:10.439493 7, 0xFFFF, sum = 0
4508 11:33:10.439575 8, 0x0, sum = 1
4509 11:33:10.442586 9, 0x0, sum = 2
4510 11:33:10.442663 10, 0x0, sum = 3
4511 11:33:10.446078 11, 0x0, sum = 4
4512 11:33:10.446154 best_step = 9
4513 11:33:10.446211
4514 11:33:10.446265 ==
4515 11:33:10.449538 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 11:33:10.452528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 11:33:10.456179 ==
4518 11:33:10.456254 RX Vref Scan: 1
4519 11:33:10.456312
4520 11:33:10.459074 RX Vref 0 -> 0, step: 1
4521 11:33:10.459148
4522 11:33:10.462645 RX Delay -179 -> 252, step: 8
4523 11:33:10.462718
4524 11:33:10.466247 Set Vref, RX VrefLevel [Byte0]: 53
4525 11:33:10.469061 [Byte1]: 52
4526 11:33:10.469159
4527 11:33:10.472223 Final RX Vref Byte 0 = 53 to rank0
4528 11:33:10.475871 Final RX Vref Byte 1 = 52 to rank0
4529 11:33:10.479053 Final RX Vref Byte 0 = 53 to rank1
4530 11:33:10.482265 Final RX Vref Byte 1 = 52 to rank1==
4531 11:33:10.485460 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 11:33:10.489039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 11:33:10.489116 ==
4534 11:33:10.491978 DQS Delay:
4535 11:33:10.492052 DQS0 = 0, DQS1 = 0
4536 11:33:10.492111 DQM Delay:
4537 11:33:10.495563 DQM0 = 41, DQM1 = 34
4538 11:33:10.495639 DQ Delay:
4539 11:33:10.498531 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4540 11:33:10.502038 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4541 11:33:10.505241 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4542 11:33:10.509022 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4543 11:33:10.509099
4544 11:33:10.509168
4545 11:33:10.518708 [DQSOSCAuto] RK0, (LSB)MR18= 0x304a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4546 11:33:10.521575 CH1 RK0: MR19=808, MR18=304A
4547 11:33:10.528582 CH1_RK0: MR19=0x808, MR18=0x304A, DQSOSC=395, MR23=63, INC=168, DEC=112
4548 11:33:10.528661
4549 11:33:10.531592 ----->DramcWriteLeveling(PI) begin...
4550 11:33:10.531670 ==
4551 11:33:10.535340 Dram Type= 6, Freq= 0, CH_1, rank 1
4552 11:33:10.538160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 11:33:10.538238 ==
4554 11:33:10.541661 Write leveling (Byte 0): 31 => 31
4555 11:33:10.545373 Write leveling (Byte 1): 32 => 32
4556 11:33:10.548439 DramcWriteLeveling(PI) end<-----
4557 11:33:10.548515
4558 11:33:10.548574 ==
4559 11:33:10.551816 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 11:33:10.554885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 11:33:10.554968 ==
4562 11:33:10.558065 [Gating] SW mode calibration
4563 11:33:10.564882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4564 11:33:10.571316 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4565 11:33:10.575185 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4566 11:33:10.577885 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4567 11:33:10.584567 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4568 11:33:10.587952 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
4569 11:33:10.591127 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4570 11:33:10.597934 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4571 11:33:10.600983 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4572 11:33:10.604470 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4573 11:33:10.611309 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4574 11:33:10.614497 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4575 11:33:10.617602 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
4576 11:33:10.624023 0 10 12 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
4577 11:33:10.627756 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4578 11:33:10.630588 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4579 11:33:10.637089 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4580 11:33:10.640507 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4581 11:33:10.644163 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4582 11:33:10.650568 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4583 11:33:10.654041 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4584 11:33:10.657040 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4585 11:33:10.664003 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4586 11:33:10.667368 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4587 11:33:10.670529 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4588 11:33:10.676664 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4589 11:33:10.680311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4590 11:33:10.683531 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4591 11:33:10.690562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4592 11:33:10.693254 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4593 11:33:10.696631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 11:33:10.703232 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 11:33:10.706356 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 11:33:10.709955 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 11:33:10.716153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 11:33:10.720275 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 11:33:10.723048 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 11:33:10.729576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4601 11:33:10.729647 Total UI for P1: 0, mck2ui 16
4602 11:33:10.736509 best dqsien dly found for B0: ( 0, 13, 10)
4603 11:33:10.739498 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 11:33:10.742945 Total UI for P1: 0, mck2ui 16
4605 11:33:10.746312 best dqsien dly found for B1: ( 0, 13, 12)
4606 11:33:10.749252 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4607 11:33:10.752928 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4608 11:33:10.753027
4609 11:33:10.755903 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4610 11:33:10.759158 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4611 11:33:10.762587 [Gating] SW calibration Done
4612 11:33:10.762688 ==
4613 11:33:10.765775 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 11:33:10.772659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 11:33:10.772742 ==
4616 11:33:10.772801 RX Vref Scan: 0
4617 11:33:10.772856
4618 11:33:10.775472 RX Vref 0 -> 0, step: 1
4619 11:33:10.775562
4620 11:33:10.778854 RX Delay -230 -> 252, step: 16
4621 11:33:10.782115 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4622 11:33:10.785498 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4623 11:33:10.788686 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4624 11:33:10.795359 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4625 11:33:10.798892 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4626 11:33:10.802021 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4627 11:33:10.805252 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4628 11:33:10.811870 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4629 11:33:10.815417 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4630 11:33:10.818543 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4631 11:33:10.821703 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4632 11:33:10.828505 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4633 11:33:10.831543 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4634 11:33:10.835339 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4635 11:33:10.838776 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4636 11:33:10.845070 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4637 11:33:10.845184 ==
4638 11:33:10.848197 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 11:33:10.851553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 11:33:10.851628 ==
4641 11:33:10.851686 DQS Delay:
4642 11:33:10.854918 DQS0 = 0, DQS1 = 0
4643 11:33:10.854993 DQM Delay:
4644 11:33:10.857964 DQM0 = 42, DQM1 = 38
4645 11:33:10.858038 DQ Delay:
4646 11:33:10.861175 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4647 11:33:10.864749 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4648 11:33:10.868322 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4649 11:33:10.871286 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4650 11:33:10.871361
4651 11:33:10.871418
4652 11:33:10.871471 ==
4653 11:33:10.875051 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 11:33:10.877616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 11:33:10.881030 ==
4656 11:33:10.881130
4657 11:33:10.881215
4658 11:33:10.881270 TX Vref Scan disable
4659 11:33:10.884470 == TX Byte 0 ==
4660 11:33:10.887785 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4661 11:33:10.891591 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4662 11:33:10.894278 == TX Byte 1 ==
4663 11:33:10.897771 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4664 11:33:10.901081 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4665 11:33:10.904025 ==
4666 11:33:10.907623 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 11:33:10.910840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 11:33:10.910920 ==
4669 11:33:10.910978
4670 11:33:10.911031
4671 11:33:10.913939 TX Vref Scan disable
4672 11:33:10.914018 == TX Byte 0 ==
4673 11:33:10.920551 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4674 11:33:10.924131 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4675 11:33:10.927079 == TX Byte 1 ==
4676 11:33:10.930148 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4677 11:33:10.933878 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4678 11:33:10.933952
4679 11:33:10.934010 [DATLAT]
4680 11:33:10.936891 Freq=600, CH1 RK1
4681 11:33:10.936965
4682 11:33:10.940361 DATLAT Default: 0x9
4683 11:33:10.940435 0, 0xFFFF, sum = 0
4684 11:33:10.943872 1, 0xFFFF, sum = 0
4685 11:33:10.943950 2, 0xFFFF, sum = 0
4686 11:33:10.946812 3, 0xFFFF, sum = 0
4687 11:33:10.946931 4, 0xFFFF, sum = 0
4688 11:33:10.950512 5, 0xFFFF, sum = 0
4689 11:33:10.950642 6, 0xFFFF, sum = 0
4690 11:33:10.953914 7, 0xFFFF, sum = 0
4691 11:33:10.954013 8, 0x0, sum = 1
4692 11:33:10.956573 9, 0x0, sum = 2
4693 11:33:10.956675 10, 0x0, sum = 3
4694 11:33:10.960614 11, 0x0, sum = 4
4695 11:33:10.960716 best_step = 9
4696 11:33:10.960805
4697 11:33:10.960903 ==
4698 11:33:10.963312 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 11:33:10.966894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 11:33:10.966972 ==
4701 11:33:10.970076 RX Vref Scan: 0
4702 11:33:10.970143
4703 11:33:10.973431 RX Vref 0 -> 0, step: 1
4704 11:33:10.973504
4705 11:33:10.973575 RX Delay -179 -> 252, step: 8
4706 11:33:10.981283 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4707 11:33:10.984226 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4708 11:33:10.988251 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4709 11:33:10.991179 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4710 11:33:10.997751 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4711 11:33:11.000676 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4712 11:33:11.004497 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4713 11:33:11.007379 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4714 11:33:11.010812 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4715 11:33:11.017440 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4716 11:33:11.020851 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4717 11:33:11.024265 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4718 11:33:11.027628 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4719 11:33:11.034310 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4720 11:33:11.037195 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4721 11:33:11.040500 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4722 11:33:11.040611 ==
4723 11:33:11.044203 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:33:11.050975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:33:11.051051 ==
4726 11:33:11.051130 DQS Delay:
4727 11:33:11.051213 DQS0 = 0, DQS1 = 0
4728 11:33:11.053710 DQM Delay:
4729 11:33:11.053775 DQM0 = 37, DQM1 = 35
4730 11:33:11.057021 DQ Delay:
4731 11:33:11.060252 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4732 11:33:11.063893 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4733 11:33:11.067092 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4734 11:33:11.070442 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4735 11:33:11.070510
4736 11:33:11.070566
4737 11:33:11.077021 [DQSOSCAuto] RK1, (LSB)MR18= 0x4064, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
4738 11:33:11.080418 CH1 RK1: MR19=808, MR18=4064
4739 11:33:11.086538 CH1_RK1: MR19=0x808, MR18=0x4064, DQSOSC=391, MR23=63, INC=171, DEC=114
4740 11:33:11.089947 [RxdqsGatingPostProcess] freq 600
4741 11:33:11.093460 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4742 11:33:11.096347 Pre-setting of DQS Precalculation
4743 11:33:11.102909 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4744 11:33:11.109631 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4745 11:33:11.116607 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4746 11:33:11.116714
4747 11:33:11.116798
4748 11:33:11.119470 [Calibration Summary] 1200 Mbps
4749 11:33:11.122772 CH 0, Rank 0
4750 11:33:11.122862 SW Impedance : PASS
4751 11:33:11.125983 DUTY Scan : NO K
4752 11:33:11.129417 ZQ Calibration : PASS
4753 11:33:11.129487 Jitter Meter : NO K
4754 11:33:11.132504 CBT Training : PASS
4755 11:33:11.132618 Write leveling : PASS
4756 11:33:11.136082 RX DQS gating : PASS
4757 11:33:11.139336 RX DQ/DQS(RDDQC) : PASS
4758 11:33:11.139412 TX DQ/DQS : PASS
4759 11:33:11.142857 RX DATLAT : PASS
4760 11:33:11.145836 RX DQ/DQS(Engine): PASS
4761 11:33:11.145899 TX OE : NO K
4762 11:33:11.149363 All Pass.
4763 11:33:11.149435
4764 11:33:11.149512 CH 0, Rank 1
4765 11:33:11.152718 SW Impedance : PASS
4766 11:33:11.152786 DUTY Scan : NO K
4767 11:33:11.155860 ZQ Calibration : PASS
4768 11:33:11.158915 Jitter Meter : NO K
4769 11:33:11.159052 CBT Training : PASS
4770 11:33:11.162501 Write leveling : PASS
4771 11:33:11.165598 RX DQS gating : PASS
4772 11:33:11.165666 RX DQ/DQS(RDDQC) : PASS
4773 11:33:11.168995 TX DQ/DQS : PASS
4774 11:33:11.172345 RX DATLAT : PASS
4775 11:33:11.172408 RX DQ/DQS(Engine): PASS
4776 11:33:11.175562 TX OE : NO K
4777 11:33:11.175624 All Pass.
4778 11:33:11.175683
4779 11:33:11.178987 CH 1, Rank 0
4780 11:33:11.179078 SW Impedance : PASS
4781 11:33:11.181847 DUTY Scan : NO K
4782 11:33:11.185365 ZQ Calibration : PASS
4783 11:33:11.185434 Jitter Meter : NO K
4784 11:33:11.188392 CBT Training : PASS
4785 11:33:11.192141 Write leveling : PASS
4786 11:33:11.192214 RX DQS gating : PASS
4787 11:33:11.195554 RX DQ/DQS(RDDQC) : PASS
4788 11:33:11.198668 TX DQ/DQS : PASS
4789 11:33:11.198798 RX DATLAT : PASS
4790 11:33:11.201733 RX DQ/DQS(Engine): PASS
4791 11:33:11.205079 TX OE : NO K
4792 11:33:11.205206 All Pass.
4793 11:33:11.205263
4794 11:33:11.205324 CH 1, Rank 1
4795 11:33:11.208256 SW Impedance : PASS
4796 11:33:11.211767 DUTY Scan : NO K
4797 11:33:11.211842 ZQ Calibration : PASS
4798 11:33:11.215062 Jitter Meter : NO K
4799 11:33:11.218260 CBT Training : PASS
4800 11:33:11.218330 Write leveling : PASS
4801 11:33:11.221452 RX DQS gating : PASS
4802 11:33:11.224563 RX DQ/DQS(RDDQC) : PASS
4803 11:33:11.224632 TX DQ/DQS : PASS
4804 11:33:11.227887 RX DATLAT : PASS
4805 11:33:11.227978 RX DQ/DQS(Engine): PASS
4806 11:33:11.231346 TX OE : NO K
4807 11:33:11.231413 All Pass.
4808 11:33:11.231466
4809 11:33:11.234457 DramC Write-DBI off
4810 11:33:11.238257 PER_BANK_REFRESH: Hybrid Mode
4811 11:33:11.238332 TX_TRACKING: ON
4812 11:33:11.247726 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4813 11:33:11.250967 [FAST_K] Save calibration result to emmc
4814 11:33:11.254648 dramc_set_vcore_voltage set vcore to 662500
4815 11:33:11.257604 Read voltage for 933, 3
4816 11:33:11.257679 Vio18 = 0
4817 11:33:11.260945 Vcore = 662500
4818 11:33:11.261014 Vdram = 0
4819 11:33:11.261075 Vddq = 0
4820 11:33:11.261128 Vmddr = 0
4821 11:33:11.267793 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4822 11:33:11.274476 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4823 11:33:11.274553 MEM_TYPE=3, freq_sel=17
4824 11:33:11.277285 sv_algorithm_assistance_LP4_1600
4825 11:33:11.280778 ============ PULL DRAM RESETB DOWN ============
4826 11:33:11.287447 ========== PULL DRAM RESETB DOWN end =========
4827 11:33:11.290437 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4828 11:33:11.294090 ===================================
4829 11:33:11.297026 LPDDR4 DRAM CONFIGURATION
4830 11:33:11.300251 ===================================
4831 11:33:11.300326 EX_ROW_EN[0] = 0x0
4832 11:33:11.303883 EX_ROW_EN[1] = 0x0
4833 11:33:11.307426 LP4Y_EN = 0x0
4834 11:33:11.307496 WORK_FSP = 0x0
4835 11:33:11.310496 WL = 0x3
4836 11:33:11.310571 RL = 0x3
4837 11:33:11.313423 BL = 0x2
4838 11:33:11.313490 RPST = 0x0
4839 11:33:11.317093 RD_PRE = 0x0
4840 11:33:11.317216 WR_PRE = 0x1
4841 11:33:11.320080 WR_PST = 0x0
4842 11:33:11.320154 DBI_WR = 0x0
4843 11:33:11.323652 DBI_RD = 0x0
4844 11:33:11.323719 OTF = 0x1
4845 11:33:11.326820 ===================================
4846 11:33:11.330044 ===================================
4847 11:33:11.333373 ANA top config
4848 11:33:11.336693 ===================================
4849 11:33:11.336785 DLL_ASYNC_EN = 0
4850 11:33:11.340128 ALL_SLAVE_EN = 1
4851 11:33:11.343009 NEW_RANK_MODE = 1
4852 11:33:11.346697 DLL_IDLE_MODE = 1
4853 11:33:11.350178 LP45_APHY_COMB_EN = 1
4854 11:33:11.350248 TX_ODT_DIS = 1
4855 11:33:11.353259 NEW_8X_MODE = 1
4856 11:33:11.356651 ===================================
4857 11:33:11.359524 ===================================
4858 11:33:11.363076 data_rate = 1866
4859 11:33:11.366690 CKR = 1
4860 11:33:11.369631 DQ_P2S_RATIO = 8
4861 11:33:11.372907 ===================================
4862 11:33:11.375946 CA_P2S_RATIO = 8
4863 11:33:11.376015 DQ_CA_OPEN = 0
4864 11:33:11.379391 DQ_SEMI_OPEN = 0
4865 11:33:11.382703 CA_SEMI_OPEN = 0
4866 11:33:11.385911 CA_FULL_RATE = 0
4867 11:33:11.389532 DQ_CKDIV4_EN = 1
4868 11:33:11.392641 CA_CKDIV4_EN = 1
4869 11:33:11.392743 CA_PREDIV_EN = 0
4870 11:33:11.396174 PH8_DLY = 0
4871 11:33:11.398945 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4872 11:33:11.402597 DQ_AAMCK_DIV = 4
4873 11:33:11.405983 CA_AAMCK_DIV = 4
4874 11:33:11.408963 CA_ADMCK_DIV = 4
4875 11:33:11.412458 DQ_TRACK_CA_EN = 0
4876 11:33:11.412535 CA_PICK = 933
4877 11:33:11.415379 CA_MCKIO = 933
4878 11:33:11.419100 MCKIO_SEMI = 0
4879 11:33:11.422156 PLL_FREQ = 3732
4880 11:33:11.425491 DQ_UI_PI_RATIO = 32
4881 11:33:11.429227 CA_UI_PI_RATIO = 0
4882 11:33:11.432242 ===================================
4883 11:33:11.435603 ===================================
4884 11:33:11.435680 memory_type:LPDDR4
4885 11:33:11.438675 GP_NUM : 10
4886 11:33:11.442279 SRAM_EN : 1
4887 11:33:11.442355 MD32_EN : 0
4888 11:33:11.445287 ===================================
4889 11:33:11.448306 [ANA_INIT] >>>>>>>>>>>>>>
4890 11:33:11.451915 <<<<<< [CONFIGURE PHASE]: ANA_TX
4891 11:33:11.455588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4892 11:33:11.458161 ===================================
4893 11:33:11.461506 data_rate = 1866,PCW = 0X8f00
4894 11:33:11.464781 ===================================
4895 11:33:11.468264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4896 11:33:11.474881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4897 11:33:11.478118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4898 11:33:11.484418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4899 11:33:11.487908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4900 11:33:11.491304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4901 11:33:11.491380 [ANA_INIT] flow start
4902 11:33:11.494220 [ANA_INIT] PLL >>>>>>>>
4903 11:33:11.497745 [ANA_INIT] PLL <<<<<<<<
4904 11:33:11.497820 [ANA_INIT] MIDPI >>>>>>>>
4905 11:33:11.501133 [ANA_INIT] MIDPI <<<<<<<<
4906 11:33:11.504550 [ANA_INIT] DLL >>>>>>>>
4907 11:33:11.504653 [ANA_INIT] flow end
4908 11:33:11.510969 ============ LP4 DIFF to SE enter ============
4909 11:33:11.514685 ============ LP4 DIFF to SE exit ============
4910 11:33:11.517571 [ANA_INIT] <<<<<<<<<<<<<
4911 11:33:11.520667 [Flow] Enable top DCM control >>>>>
4912 11:33:11.524483 [Flow] Enable top DCM control <<<<<
4913 11:33:11.524553 Enable DLL master slave shuffle
4914 11:33:11.530988 ==============================================================
4915 11:33:11.533993 Gating Mode config
4916 11:33:11.537794 ==============================================================
4917 11:33:11.540314 Config description:
4918 11:33:11.550395 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4919 11:33:11.556942 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4920 11:33:11.560520 SELPH_MODE 0: By rank 1: By Phase
4921 11:33:11.567231 ==============================================================
4922 11:33:11.570194 GAT_TRACK_EN = 1
4923 11:33:11.573792 RX_GATING_MODE = 2
4924 11:33:11.576744 RX_GATING_TRACK_MODE = 2
4925 11:33:11.580102 SELPH_MODE = 1
4926 11:33:11.583551 PICG_EARLY_EN = 1
4927 11:33:11.586937 VALID_LAT_VALUE = 1
4928 11:33:11.590177 ==============================================================
4929 11:33:11.593365 Enter into Gating configuration >>>>
4930 11:33:11.596696 Exit from Gating configuration <<<<
4931 11:33:11.600048 Enter into DVFS_PRE_config >>>>>
4932 11:33:11.612967 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4933 11:33:11.613068 Exit from DVFS_PRE_config <<<<<
4934 11:33:11.616463 Enter into PICG configuration >>>>
4935 11:33:11.619600 Exit from PICG configuration <<<<
4936 11:33:11.623033 [RX_INPUT] configuration >>>>>
4937 11:33:11.626026 [RX_INPUT] configuration <<<<<
4938 11:33:11.632638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4939 11:33:11.635666 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4940 11:33:11.642212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4941 11:33:11.649165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4942 11:33:11.655645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4943 11:33:11.662521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4944 11:33:11.665561 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4945 11:33:11.668635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4946 11:33:11.675174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4947 11:33:11.678647 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4948 11:33:11.682210 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4949 11:33:11.685553 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4950 11:33:11.688362 ===================================
4951 11:33:11.692086 LPDDR4 DRAM CONFIGURATION
4952 11:33:11.695327 ===================================
4953 11:33:11.698593 EX_ROW_EN[0] = 0x0
4954 11:33:11.698692 EX_ROW_EN[1] = 0x0
4955 11:33:11.701643 LP4Y_EN = 0x0
4956 11:33:11.701733 WORK_FSP = 0x0
4957 11:33:11.705254 WL = 0x3
4958 11:33:11.705330 RL = 0x3
4959 11:33:11.708196 BL = 0x2
4960 11:33:11.708291 RPST = 0x0
4961 11:33:11.711469 RD_PRE = 0x0
4962 11:33:11.715195 WR_PRE = 0x1
4963 11:33:11.715271 WR_PST = 0x0
4964 11:33:11.718115 DBI_WR = 0x0
4965 11:33:11.718191 DBI_RD = 0x0
4966 11:33:11.721863 OTF = 0x1
4967 11:33:11.725342 ===================================
4968 11:33:11.728296 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4969 11:33:11.731518 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4970 11:33:11.735014 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4971 11:33:11.738071 ===================================
4972 11:33:11.741512 LPDDR4 DRAM CONFIGURATION
4973 11:33:11.744413 ===================================
4974 11:33:11.747951 EX_ROW_EN[0] = 0x10
4975 11:33:11.748027 EX_ROW_EN[1] = 0x0
4976 11:33:11.751319 LP4Y_EN = 0x0
4977 11:33:11.751418 WORK_FSP = 0x0
4978 11:33:11.754500 WL = 0x3
4979 11:33:11.754576 RL = 0x3
4980 11:33:11.757763 BL = 0x2
4981 11:33:11.761283 RPST = 0x0
4982 11:33:11.761358 RD_PRE = 0x0
4983 11:33:11.764111 WR_PRE = 0x1
4984 11:33:11.764187 WR_PST = 0x0
4985 11:33:11.767416 DBI_WR = 0x0
4986 11:33:11.767492 DBI_RD = 0x0
4987 11:33:11.771010 OTF = 0x1
4988 11:33:11.773984 ===================================
4989 11:33:11.780834 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4990 11:33:11.784144 nWR fixed to 30
4991 11:33:11.784216 [ModeRegInit_LP4] CH0 RK0
4992 11:33:11.787038 [ModeRegInit_LP4] CH0 RK1
4993 11:33:11.790377 [ModeRegInit_LP4] CH1 RK0
4994 11:33:11.793913 [ModeRegInit_LP4] CH1 RK1
4995 11:33:11.793979 match AC timing 9
4996 11:33:11.797417 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
4997 11:33:11.803512 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4998 11:33:11.807059 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4999 11:33:11.813696 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5000 11:33:11.816672 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5001 11:33:11.816748 ==
5002 11:33:11.820113 Dram Type= 6, Freq= 0, CH_0, rank 0
5003 11:33:11.823397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5004 11:33:11.823474 ==
5005 11:33:11.830128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5006 11:33:11.836613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5007 11:33:11.840344 [CA 0] Center 37 (7~68) winsize 62
5008 11:33:11.843522 [CA 1] Center 37 (7~68) winsize 62
5009 11:33:11.846887 [CA 2] Center 34 (4~65) winsize 62
5010 11:33:11.849810 [CA 3] Center 34 (4~65) winsize 62
5011 11:33:11.853048 [CA 4] Center 32 (2~63) winsize 62
5012 11:33:11.856703 [CA 5] Center 32 (2~63) winsize 62
5013 11:33:11.856779
5014 11:33:11.860429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5015 11:33:11.860505
5016 11:33:11.863319 [CATrainingPosCal] consider 1 rank data
5017 11:33:11.866256 u2DelayCellTimex100 = 270/100 ps
5018 11:33:11.869953 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5019 11:33:11.872839 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5020 11:33:11.876378 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5021 11:33:11.879336 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5022 11:33:11.882627 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5023 11:33:11.885956 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5024 11:33:11.889532
5025 11:33:11.892840 CA PerBit enable=1, Macro0, CA PI delay=32
5026 11:33:11.892915
5027 11:33:11.896127 [CBTSetCACLKResult] CA Dly = 32
5028 11:33:11.896203 CS Dly: 5 (0~36)
5029 11:33:11.896262 ==
5030 11:33:11.899102 Dram Type= 6, Freq= 0, CH_0, rank 1
5031 11:33:11.902806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5032 11:33:11.902883 ==
5033 11:33:11.909227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5034 11:33:11.915864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5035 11:33:11.919498 [CA 0] Center 38 (7~69) winsize 63
5036 11:33:11.922325 [CA 1] Center 37 (7~68) winsize 62
5037 11:33:11.925846 [CA 2] Center 34 (4~65) winsize 62
5038 11:33:11.929202 [CA 3] Center 34 (4~65) winsize 62
5039 11:33:11.932572 [CA 4] Center 33 (2~64) winsize 63
5040 11:33:11.935706 [CA 5] Center 32 (2~63) winsize 62
5041 11:33:11.935801
5042 11:33:11.938944 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5043 11:33:11.939020
5044 11:33:11.942080 [CATrainingPosCal] consider 2 rank data
5045 11:33:11.945963 u2DelayCellTimex100 = 270/100 ps
5046 11:33:11.948550 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 11:33:11.952066 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5048 11:33:11.955368 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5049 11:33:11.961887 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5050 11:33:11.965096 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5051 11:33:11.968787 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5052 11:33:11.968860
5053 11:33:11.971664 CA PerBit enable=1, Macro0, CA PI delay=32
5054 11:33:11.971748
5055 11:33:11.975188 [CBTSetCACLKResult] CA Dly = 32
5056 11:33:11.975256 CS Dly: 6 (0~39)
5057 11:33:11.975356
5058 11:33:11.978572 ----->DramcWriteLeveling(PI) begin...
5059 11:33:11.981666 ==
5060 11:33:11.985209 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 11:33:11.988438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 11:33:11.988504 ==
5063 11:33:11.991625 Write leveling (Byte 0): 33 => 33
5064 11:33:11.995068 Write leveling (Byte 1): 26 => 26
5065 11:33:11.998290 DramcWriteLeveling(PI) end<-----
5066 11:33:11.998356
5067 11:33:11.998416 ==
5068 11:33:12.001423 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 11:33:12.004860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 11:33:12.004960 ==
5071 11:33:12.007918 [Gating] SW mode calibration
5072 11:33:12.014468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5073 11:33:12.021088 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5074 11:33:12.024401 0 14 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
5075 11:33:12.027547 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5076 11:33:12.034417 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5077 11:33:12.037830 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5078 11:33:12.041228 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5079 11:33:12.047593 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5080 11:33:12.051384 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5081 11:33:12.053926 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (1 1)
5082 11:33:12.060476 0 15 0 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
5083 11:33:12.063673 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5084 11:33:12.067274 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5085 11:33:12.073685 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5086 11:33:12.076977 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5087 11:33:12.080534 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5088 11:33:12.087134 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5089 11:33:12.090632 0 15 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
5090 11:33:12.094165 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5091 11:33:12.100552 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5092 11:33:12.103255 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5093 11:33:12.106584 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5094 11:33:12.113218 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5095 11:33:12.116407 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5096 11:33:12.119876 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5097 11:33:12.126414 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5098 11:33:12.129498 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5099 11:33:12.133336 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5100 11:33:12.139583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5101 11:33:12.142614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5102 11:33:12.146023 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5103 11:33:12.152899 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5104 11:33:12.156258 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5105 11:33:12.159352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5106 11:33:12.166416 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5107 11:33:12.169565 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 11:33:12.172771 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 11:33:12.179504 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 11:33:12.182646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 11:33:12.185924 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 11:33:12.192804 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5113 11:33:12.195951 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5114 11:33:12.199378 Total UI for P1: 0, mck2ui 16
5115 11:33:12.202364 best dqsien dly found for B0: ( 1, 2, 24)
5116 11:33:12.206042 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5117 11:33:12.212379 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 11:33:12.212485 Total UI for P1: 0, mck2ui 16
5119 11:33:12.218614 best dqsien dly found for B1: ( 1, 2, 30)
5120 11:33:12.222050 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5121 11:33:12.225511 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5122 11:33:12.225587
5123 11:33:12.228610 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5124 11:33:12.232143 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5125 11:33:12.235268 [Gating] SW calibration Done
5126 11:33:12.235344 ==
5127 11:33:12.239122 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 11:33:12.241768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 11:33:12.241849 ==
5130 11:33:12.245345 RX Vref Scan: 0
5131 11:33:12.245416
5132 11:33:12.245475 RX Vref 0 -> 0, step: 1
5133 11:33:12.245533
5134 11:33:12.248530 RX Delay -80 -> 252, step: 8
5135 11:33:12.255218 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5136 11:33:12.258305 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5137 11:33:12.261920 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5138 11:33:12.265360 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5139 11:33:12.268359 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5140 11:33:12.271362 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5141 11:33:12.278248 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5142 11:33:12.281250 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5143 11:33:12.284488 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5144 11:33:12.288378 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5145 11:33:12.291525 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5146 11:33:12.294874 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5147 11:33:12.300987 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5148 11:33:12.304549 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5149 11:33:12.308123 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5150 11:33:12.310860 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5151 11:33:12.310939 ==
5152 11:33:12.314087 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 11:33:12.320864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 11:33:12.320967 ==
5155 11:33:12.321072 DQS Delay:
5156 11:33:12.324132 DQS0 = 0, DQS1 = 0
5157 11:33:12.324206 DQM Delay:
5158 11:33:12.324277 DQM0 = 100, DQM1 = 88
5159 11:33:12.327393 DQ Delay:
5160 11:33:12.330746 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5161 11:33:12.334070 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5162 11:33:12.337085 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5163 11:33:12.340590 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5164 11:33:12.340676
5165 11:33:12.340772
5166 11:33:12.340862 ==
5167 11:33:12.343669 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 11:33:12.347141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 11:33:12.347217 ==
5170 11:33:12.347288
5171 11:33:12.347359
5172 11:33:12.350696 TX Vref Scan disable
5173 11:33:12.353554 == TX Byte 0 ==
5174 11:33:12.357026 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5175 11:33:12.360646 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5176 11:33:12.363781 == TX Byte 1 ==
5177 11:33:12.366817 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5178 11:33:12.369853 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5179 11:33:12.369928 ==
5180 11:33:12.373680 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 11:33:12.379677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 11:33:12.379754 ==
5183 11:33:12.379814
5184 11:33:12.379868
5185 11:33:12.379920 TX Vref Scan disable
5186 11:33:12.384384 == TX Byte 0 ==
5187 11:33:12.387664 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5188 11:33:12.394059 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5189 11:33:12.394135 == TX Byte 1 ==
5190 11:33:12.397634 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5191 11:33:12.403940 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5192 11:33:12.404030
5193 11:33:12.404089 [DATLAT]
5194 11:33:12.404143 Freq=933, CH0 RK0
5195 11:33:12.404219
5196 11:33:12.407207 DATLAT Default: 0xd
5197 11:33:12.410398 0, 0xFFFF, sum = 0
5198 11:33:12.410490 1, 0xFFFF, sum = 0
5199 11:33:12.413960 2, 0xFFFF, sum = 0
5200 11:33:12.414071 3, 0xFFFF, sum = 0
5201 11:33:12.417115 4, 0xFFFF, sum = 0
5202 11:33:12.417230 5, 0xFFFF, sum = 0
5203 11:33:12.420318 6, 0xFFFF, sum = 0
5204 11:33:12.420394 7, 0xFFFF, sum = 0
5205 11:33:12.423645 8, 0xFFFF, sum = 0
5206 11:33:12.423721 9, 0xFFFF, sum = 0
5207 11:33:12.427142 10, 0x0, sum = 1
5208 11:33:12.427218 11, 0x0, sum = 2
5209 11:33:12.430295 12, 0x0, sum = 3
5210 11:33:12.430375 13, 0x0, sum = 4
5211 11:33:12.433326 best_step = 11
5212 11:33:12.433402
5213 11:33:12.433462 ==
5214 11:33:12.436836 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 11:33:12.439967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 11:33:12.440077 ==
5217 11:33:12.440153 RX Vref Scan: 1
5218 11:33:12.443394
5219 11:33:12.443468 RX Vref 0 -> 0, step: 1
5220 11:33:12.443527
5221 11:33:12.446855 RX Delay -61 -> 252, step: 4
5222 11:33:12.446922
5223 11:33:12.449701 Set Vref, RX VrefLevel [Byte0]: 51
5224 11:33:12.452855 [Byte1]: 59
5225 11:33:12.456861
5226 11:33:12.456928 Final RX Vref Byte 0 = 51 to rank0
5227 11:33:12.459923 Final RX Vref Byte 1 = 59 to rank0
5228 11:33:12.463128 Final RX Vref Byte 0 = 51 to rank1
5229 11:33:12.467053 Final RX Vref Byte 1 = 59 to rank1==
5230 11:33:12.470026 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 11:33:12.477122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 11:33:12.477213 ==
5233 11:33:12.477269 DQS Delay:
5234 11:33:12.480167 DQS0 = 0, DQS1 = 0
5235 11:33:12.480226 DQM Delay:
5236 11:33:12.480277 DQM0 = 99, DQM1 = 89
5237 11:33:12.483147 DQ Delay:
5238 11:33:12.486745 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5239 11:33:12.489631 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5240 11:33:12.493363 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =84
5241 11:33:12.496926 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =94
5242 11:33:12.497001
5243 11:33:12.497060
5244 11:33:12.503227 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5245 11:33:12.506095 CH0 RK0: MR19=505, MR18=1B16
5246 11:33:12.512966 CH0_RK0: MR19=0x505, MR18=0x1B16, DQSOSC=413, MR23=63, INC=63, DEC=42
5247 11:33:12.513069
5248 11:33:12.516285 ----->DramcWriteLeveling(PI) begin...
5249 11:33:12.516364 ==
5250 11:33:12.519647 Dram Type= 6, Freq= 0, CH_0, rank 1
5251 11:33:12.522689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 11:33:12.522769 ==
5253 11:33:12.525962 Write leveling (Byte 0): 33 => 33
5254 11:33:12.529409 Write leveling (Byte 1): 26 => 26
5255 11:33:12.532731 DramcWriteLeveling(PI) end<-----
5256 11:33:12.532808
5257 11:33:12.532867 ==
5258 11:33:12.535496 Dram Type= 6, Freq= 0, CH_0, rank 1
5259 11:33:12.542463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 11:33:12.542545 ==
5261 11:33:12.545851 [Gating] SW mode calibration
5262 11:33:12.552333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5263 11:33:12.555472 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5264 11:33:12.561884 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5265 11:33:12.565612 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5266 11:33:12.568814 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5267 11:33:12.575489 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5268 11:33:12.578541 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5269 11:33:12.582392 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5270 11:33:12.588764 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5271 11:33:12.592247 0 14 28 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5272 11:33:12.595094 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5273 11:33:12.601865 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5274 11:33:12.605107 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5275 11:33:12.608854 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5276 11:33:12.615140 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5277 11:33:12.618470 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5278 11:33:12.622167 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5279 11:33:12.628705 0 15 28 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
5280 11:33:12.631637 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5281 11:33:12.634781 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5282 11:33:12.641400 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5283 11:33:12.644839 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5284 11:33:12.647899 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5285 11:33:12.654799 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5286 11:33:12.657989 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5287 11:33:12.661264 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5288 11:33:12.667512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5289 11:33:12.671090 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5290 11:33:12.674652 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5291 11:33:12.680634 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5292 11:33:12.684290 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5293 11:33:12.687942 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5294 11:33:12.690669 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5295 11:33:12.697696 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5296 11:33:12.700627 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5297 11:33:12.703937 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 11:33:12.710500 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 11:33:12.713691 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 11:33:12.717095 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 11:33:12.723952 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 11:33:12.726899 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5303 11:33:12.730506 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5304 11:33:12.733901 Total UI for P1: 0, mck2ui 16
5305 11:33:12.737134 best dqsien dly found for B0: ( 1, 2, 24)
5306 11:33:12.743356 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 11:33:12.746842 Total UI for P1: 0, mck2ui 16
5308 11:33:12.749961 best dqsien dly found for B1: ( 1, 2, 28)
5309 11:33:12.753463 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5310 11:33:12.757075 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5311 11:33:12.757172
5312 11:33:12.759900 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5313 11:33:12.763351 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5314 11:33:12.766834 [Gating] SW calibration Done
5315 11:33:12.766912 ==
5316 11:33:12.770026 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 11:33:12.773437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 11:33:12.773513 ==
5319 11:33:12.776997 RX Vref Scan: 0
5320 11:33:12.777099
5321 11:33:12.780236 RX Vref 0 -> 0, step: 1
5322 11:33:12.780314
5323 11:33:12.780373 RX Delay -80 -> 252, step: 8
5324 11:33:12.786633 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5325 11:33:12.789973 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5326 11:33:12.793009 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5327 11:33:12.796357 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5328 11:33:12.799637 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5329 11:33:12.802986 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5330 11:33:12.809318 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5331 11:33:12.812739 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5332 11:33:12.815937 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5333 11:33:12.819384 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5334 11:33:12.823026 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5335 11:33:12.829405 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5336 11:33:12.832692 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5337 11:33:12.835821 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5338 11:33:12.839353 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5339 11:33:12.842790 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5340 11:33:12.842859 ==
5341 11:33:12.845882 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 11:33:12.852129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 11:33:12.852201 ==
5344 11:33:12.852258 DQS Delay:
5345 11:33:12.855517 DQS0 = 0, DQS1 = 0
5346 11:33:12.855583 DQM Delay:
5347 11:33:12.855637 DQM0 = 98, DQM1 = 88
5348 11:33:12.858995 DQ Delay:
5349 11:33:12.862466 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5350 11:33:12.865724 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5351 11:33:12.868647 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5352 11:33:12.872419 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5353 11:33:12.872498
5354 11:33:12.872555
5355 11:33:12.872608 ==
5356 11:33:12.875047 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 11:33:12.878484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 11:33:12.878575 ==
5359 11:33:12.878657
5360 11:33:12.878736
5361 11:33:12.881940 TX Vref Scan disable
5362 11:33:12.885215 == TX Byte 0 ==
5363 11:33:12.888885 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5364 11:33:12.891877 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5365 11:33:12.895483 == TX Byte 1 ==
5366 11:33:12.898457 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5367 11:33:12.901437 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5368 11:33:12.901504 ==
5369 11:33:12.905117 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 11:33:12.911617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 11:33:12.911696 ==
5372 11:33:12.911757
5373 11:33:12.911813
5374 11:33:12.911884 TX Vref Scan disable
5375 11:33:12.916059 == TX Byte 0 ==
5376 11:33:12.919141 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5377 11:33:12.925376 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5378 11:33:12.925478 == TX Byte 1 ==
5379 11:33:12.928842 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5380 11:33:12.935449 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5381 11:33:12.935544
5382 11:33:12.935628 [DATLAT]
5383 11:33:12.935715 Freq=933, CH0 RK1
5384 11:33:12.935799
5385 11:33:12.938895 DATLAT Default: 0xb
5386 11:33:12.938961 0, 0xFFFF, sum = 0
5387 11:33:12.942606 1, 0xFFFF, sum = 0
5388 11:33:12.942679 2, 0xFFFF, sum = 0
5389 11:33:12.945587 3, 0xFFFF, sum = 0
5390 11:33:12.948908 4, 0xFFFF, sum = 0
5391 11:33:12.948977 5, 0xFFFF, sum = 0
5392 11:33:12.951987 6, 0xFFFF, sum = 0
5393 11:33:12.952087 7, 0xFFFF, sum = 0
5394 11:33:12.955551 8, 0xFFFF, sum = 0
5395 11:33:12.955645 9, 0xFFFF, sum = 0
5396 11:33:12.959006 10, 0x0, sum = 1
5397 11:33:12.959103 11, 0x0, sum = 2
5398 11:33:12.961863 12, 0x0, sum = 3
5399 11:33:12.961958 13, 0x0, sum = 4
5400 11:33:12.962043 best_step = 11
5401 11:33:12.962123
5402 11:33:12.965103 ==
5403 11:33:12.968861 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 11:33:12.971867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 11:33:12.971938 ==
5406 11:33:12.971996 RX Vref Scan: 0
5407 11:33:12.972051
5408 11:33:12.975815 RX Vref 0 -> 0, step: 1
5409 11:33:12.975895
5410 11:33:12.978604 RX Delay -53 -> 252, step: 4
5411 11:33:12.985097 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5412 11:33:12.988340 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5413 11:33:12.991553 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5414 11:33:12.994963 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5415 11:33:12.998351 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5416 11:33:13.001949 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5417 11:33:13.008593 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5418 11:33:13.011522 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5419 11:33:13.014740 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5420 11:33:13.018215 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5421 11:33:13.021685 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5422 11:33:13.028272 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5423 11:33:13.031236 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5424 11:33:13.034745 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5425 11:33:13.037802 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5426 11:33:13.041600 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5427 11:33:13.041670 ==
5428 11:33:13.044451 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 11:33:13.051371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 11:33:13.051451 ==
5431 11:33:13.051512 DQS Delay:
5432 11:33:13.054423 DQS0 = 0, DQS1 = 0
5433 11:33:13.054499 DQM Delay:
5434 11:33:13.054559 DQM0 = 97, DQM1 = 88
5435 11:33:13.057775 DQ Delay:
5436 11:33:13.061085 DQ0 =96, DQ1 =100, DQ2 =92, DQ3 =98
5437 11:33:13.064309 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =104
5438 11:33:13.067436 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5439 11:33:13.071163 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5440 11:33:13.071241
5441 11:33:13.071302
5442 11:33:13.077606 [DQSOSCAuto] RK1, (LSB)MR18= 0x1915, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5443 11:33:13.081004 CH0 RK1: MR19=505, MR18=1915
5444 11:33:13.087437 CH0_RK1: MR19=0x505, MR18=0x1915, DQSOSC=413, MR23=63, INC=63, DEC=42
5445 11:33:13.090545 [RxdqsGatingPostProcess] freq 933
5446 11:33:13.097481 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5447 11:33:13.100682 best DQS0 dly(2T, 0.5T) = (0, 10)
5448 11:33:13.100783 best DQS1 dly(2T, 0.5T) = (0, 10)
5449 11:33:13.104024 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5450 11:33:13.106799 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5451 11:33:13.110414 best DQS0 dly(2T, 0.5T) = (0, 10)
5452 11:33:13.113543 best DQS1 dly(2T, 0.5T) = (0, 10)
5453 11:33:13.117101 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5454 11:33:13.120463 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5455 11:33:13.123555 Pre-setting of DQS Precalculation
5456 11:33:13.130220 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5457 11:33:13.130294 ==
5458 11:33:13.133355 Dram Type= 6, Freq= 0, CH_1, rank 0
5459 11:33:13.136819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 11:33:13.136888 ==
5461 11:33:13.143258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5462 11:33:13.150190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5463 11:33:13.153687 [CA 0] Center 36 (6~67) winsize 62
5464 11:33:13.156616 [CA 1] Center 36 (6~67) winsize 62
5465 11:33:13.160020 [CA 2] Center 35 (5~66) winsize 62
5466 11:33:13.162886 [CA 3] Center 34 (4~64) winsize 61
5467 11:33:13.166471 [CA 4] Center 34 (4~65) winsize 62
5468 11:33:13.169883 [CA 5] Center 33 (3~64) winsize 62
5469 11:33:13.169968
5470 11:33:13.173095 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5471 11:33:13.173186
5472 11:33:13.176829 [CATrainingPosCal] consider 1 rank data
5473 11:33:13.179655 u2DelayCellTimex100 = 270/100 ps
5474 11:33:13.182881 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5475 11:33:13.185882 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5476 11:33:13.189296 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5477 11:33:13.192924 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5478 11:33:13.195869 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5479 11:33:13.199177 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5480 11:33:13.199248
5481 11:33:13.205900 CA PerBit enable=1, Macro0, CA PI delay=33
5482 11:33:13.205981
5483 11:33:13.206053 [CBTSetCACLKResult] CA Dly = 33
5484 11:33:13.209245 CS Dly: 5 (0~36)
5485 11:33:13.209321 ==
5486 11:33:13.212796 Dram Type= 6, Freq= 0, CH_1, rank 1
5487 11:33:13.215864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:33:13.215942 ==
5489 11:33:13.222165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 11:33:13.228820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5491 11:33:13.231922 [CA 0] Center 36 (6~66) winsize 61
5492 11:33:13.235419 [CA 1] Center 36 (6~67) winsize 62
5493 11:33:13.238940 [CA 2] Center 34 (4~65) winsize 62
5494 11:33:13.242572 [CA 3] Center 33 (3~64) winsize 62
5495 11:33:13.245371 [CA 4] Center 34 (4~64) winsize 61
5496 11:33:13.248544 [CA 5] Center 33 (3~64) winsize 62
5497 11:33:13.248622
5498 11:33:13.251570 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5499 11:33:13.251661
5500 11:33:13.255089 [CATrainingPosCal] consider 2 rank data
5501 11:33:13.258051 u2DelayCellTimex100 = 270/100 ps
5502 11:33:13.261613 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5503 11:33:13.264675 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 11:33:13.268317 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5505 11:33:13.274781 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5506 11:33:13.278706 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5507 11:33:13.281283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 11:33:13.281360
5509 11:33:13.284796 CA PerBit enable=1, Macro0, CA PI delay=33
5510 11:33:13.284872
5511 11:33:13.288088 [CBTSetCACLKResult] CA Dly = 33
5512 11:33:13.288165 CS Dly: 6 (0~39)
5513 11:33:13.288224
5514 11:33:13.291278 ----->DramcWriteLeveling(PI) begin...
5515 11:33:13.294380 ==
5516 11:33:13.297576 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 11:33:13.301043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 11:33:13.301122 ==
5519 11:33:13.304280 Write leveling (Byte 0): 26 => 26
5520 11:33:13.307592 Write leveling (Byte 1): 27 => 27
5521 11:33:13.311770 DramcWriteLeveling(PI) end<-----
5522 11:33:13.311847
5523 11:33:13.311907 ==
5524 11:33:13.314155 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 11:33:13.317708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 11:33:13.317794 ==
5527 11:33:13.320931 [Gating] SW mode calibration
5528 11:33:13.327281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5529 11:33:13.333934 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5530 11:33:13.337667 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5531 11:33:13.340711 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5532 11:33:13.347740 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5533 11:33:13.350551 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5534 11:33:13.353859 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5535 11:33:13.360387 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5536 11:33:13.363817 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 0)
5537 11:33:13.366976 0 14 28 | B1->B0 | 2929 2626 | 0 0 | (0 0) (1 0)
5538 11:33:13.373785 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5539 11:33:13.376897 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 11:33:13.380546 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 11:33:13.387043 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 11:33:13.390491 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 11:33:13.393277 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 11:33:13.400271 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5545 11:33:13.403316 0 15 28 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
5546 11:33:13.406589 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5547 11:33:13.413230 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 11:33:13.416783 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 11:33:13.419469 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 11:33:13.426496 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 11:33:13.429891 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 11:33:13.433347 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5553 11:33:13.439484 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5554 11:33:13.442563 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 11:33:13.446136 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 11:33:13.452604 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 11:33:13.455568 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 11:33:13.459707 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 11:33:13.466316 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 11:33:13.469515 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 11:33:13.472418 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 11:33:13.478993 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:33:13.482351 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:33:13.485476 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:33:13.492390 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:33:13.496009 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 11:33:13.498765 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 11:33:13.505774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5569 11:33:13.508977 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 11:33:13.512443 Total UI for P1: 0, mck2ui 16
5571 11:33:13.515552 best dqsien dly found for B0: ( 1, 2, 24)
5572 11:33:13.519039 Total UI for P1: 0, mck2ui 16
5573 11:33:13.522317 best dqsien dly found for B1: ( 1, 2, 24)
5574 11:33:13.525227 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5575 11:33:13.528240 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5576 11:33:13.528317
5577 11:33:13.531513 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5578 11:33:13.535128 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5579 11:33:13.538697 [Gating] SW calibration Done
5580 11:33:13.538792 ==
5581 11:33:13.541767 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 11:33:13.544639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 11:33:13.548130 ==
5584 11:33:13.548206 RX Vref Scan: 0
5585 11:33:13.548265
5586 11:33:13.551662 RX Vref 0 -> 0, step: 1
5587 11:33:13.551738
5588 11:33:13.554770 RX Delay -80 -> 252, step: 8
5589 11:33:13.558418 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5590 11:33:13.561772 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5591 11:33:13.564956 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5592 11:33:13.567838 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5593 11:33:13.571630 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5594 11:33:13.577671 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5595 11:33:13.580950 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5596 11:33:13.584452 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5597 11:33:13.587883 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5598 11:33:13.591024 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5599 11:33:13.597971 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5600 11:33:13.601211 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5601 11:33:13.603988 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5602 11:33:13.607669 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5603 11:33:13.610708 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5604 11:33:13.617109 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5605 11:33:13.617198 ==
5606 11:33:13.620812 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 11:33:13.624060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 11:33:13.624126 ==
5609 11:33:13.624182 DQS Delay:
5610 11:33:13.627346 DQS0 = 0, DQS1 = 0
5611 11:33:13.627458 DQM Delay:
5612 11:33:13.630300 DQM0 = 97, DQM1 = 94
5613 11:33:13.630373 DQ Delay:
5614 11:33:13.633729 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5615 11:33:13.637670 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5616 11:33:13.640447 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5617 11:33:13.643911 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5618 11:33:13.643983
5619 11:33:13.644055
5620 11:33:13.644114 ==
5621 11:33:13.646944 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 11:33:13.653469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 11:33:13.653566 ==
5624 11:33:13.653625
5625 11:33:13.653685
5626 11:33:13.653738 TX Vref Scan disable
5627 11:33:13.657112 == TX Byte 0 ==
5628 11:33:13.660401 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5629 11:33:13.667159 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5630 11:33:13.667238 == TX Byte 1 ==
5631 11:33:13.670371 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5632 11:33:13.677048 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5633 11:33:13.677124 ==
5634 11:33:13.680454 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:33:13.683600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:33:13.683694 ==
5637 11:33:13.683787
5638 11:33:13.683874
5639 11:33:13.686728 TX Vref Scan disable
5640 11:33:13.686797 == TX Byte 0 ==
5641 11:33:13.693427 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5642 11:33:13.696856 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5643 11:33:13.696930 == TX Byte 1 ==
5644 11:33:13.703053 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5645 11:33:13.706569 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5646 11:33:13.706642
5647 11:33:13.706705 [DATLAT]
5648 11:33:13.710191 Freq=933, CH1 RK0
5649 11:33:13.710259
5650 11:33:13.710336 DATLAT Default: 0xd
5651 11:33:13.713102 0, 0xFFFF, sum = 0
5652 11:33:13.713213 1, 0xFFFF, sum = 0
5653 11:33:13.716458 2, 0xFFFF, sum = 0
5654 11:33:13.719784 3, 0xFFFF, sum = 0
5655 11:33:13.719891 4, 0xFFFF, sum = 0
5656 11:33:13.722833 5, 0xFFFF, sum = 0
5657 11:33:13.722901 6, 0xFFFF, sum = 0
5658 11:33:13.726074 7, 0xFFFF, sum = 0
5659 11:33:13.726141 8, 0xFFFF, sum = 0
5660 11:33:13.729487 9, 0xFFFF, sum = 0
5661 11:33:13.729558 10, 0x0, sum = 1
5662 11:33:13.732822 11, 0x0, sum = 2
5663 11:33:13.732916 12, 0x0, sum = 3
5664 11:33:13.736112 13, 0x0, sum = 4
5665 11:33:13.736194 best_step = 11
5666 11:33:13.736255
5667 11:33:13.736311 ==
5668 11:33:13.740137 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 11:33:13.742822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 11:33:13.742890 ==
5671 11:33:13.746236 RX Vref Scan: 1
5672 11:33:13.746313
5673 11:33:13.749163 RX Vref 0 -> 0, step: 1
5674 11:33:13.749259
5675 11:33:13.749346 RX Delay -61 -> 252, step: 4
5676 11:33:13.749439
5677 11:33:13.752883 Set Vref, RX VrefLevel [Byte0]: 53
5678 11:33:13.755854 [Byte1]: 52
5679 11:33:13.760642
5680 11:33:13.760714 Final RX Vref Byte 0 = 53 to rank0
5681 11:33:13.764210 Final RX Vref Byte 1 = 52 to rank0
5682 11:33:13.767282 Final RX Vref Byte 0 = 53 to rank1
5683 11:33:13.770676 Final RX Vref Byte 1 = 52 to rank1==
5684 11:33:13.773854 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 11:33:13.780773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 11:33:13.780851 ==
5687 11:33:13.780909 DQS Delay:
5688 11:33:13.784073 DQS0 = 0, DQS1 = 0
5689 11:33:13.784144 DQM Delay:
5690 11:33:13.784217 DQM0 = 96, DQM1 = 93
5691 11:33:13.787324 DQ Delay:
5692 11:33:13.790343 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =96
5693 11:33:13.793685 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5694 11:33:13.797004 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =86
5695 11:33:13.800455 DQ12 =106, DQ13 =102, DQ14 =98, DQ15 =102
5696 11:33:13.800555
5697 11:33:13.800645
5698 11:33:13.806826 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
5699 11:33:13.810265 CH1 RK0: MR19=505, MR18=F1F
5700 11:33:13.816828 CH1_RK0: MR19=0x505, MR18=0xF1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5701 11:33:13.816938
5702 11:33:13.820346 ----->DramcWriteLeveling(PI) begin...
5703 11:33:13.820418 ==
5704 11:33:13.823511 Dram Type= 6, Freq= 0, CH_1, rank 1
5705 11:33:13.827135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 11:33:13.827233 ==
5707 11:33:13.830591 Write leveling (Byte 0): 28 => 28
5708 11:33:13.833348 Write leveling (Byte 1): 29 => 29
5709 11:33:13.836554 DramcWriteLeveling(PI) end<-----
5710 11:33:13.836623
5711 11:33:13.836681 ==
5712 11:33:13.839960 Dram Type= 6, Freq= 0, CH_1, rank 1
5713 11:33:13.843213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:33:13.846766 ==
5715 11:33:13.846843 [Gating] SW mode calibration
5716 11:33:13.856582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5717 11:33:13.859421 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5718 11:33:13.863222 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5719 11:33:13.869454 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5720 11:33:13.872922 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5721 11:33:13.876466 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5722 11:33:13.882883 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5723 11:33:13.885909 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5724 11:33:13.889152 0 14 24 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5725 11:33:13.895925 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5726 11:33:13.899147 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5727 11:33:13.902471 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5728 11:33:13.908950 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5729 11:33:13.912758 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5730 11:33:13.915993 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5731 11:33:13.922391 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5732 11:33:13.925904 0 15 24 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (1 1)
5733 11:33:13.929231 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5734 11:33:13.935975 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5735 11:33:13.939110 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5736 11:33:13.942564 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5737 11:33:13.948992 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5738 11:33:13.952101 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5739 11:33:13.955142 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5740 11:33:13.961735 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5741 11:33:13.965466 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5742 11:33:13.968347 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5743 11:33:13.975013 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5744 11:33:13.978673 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5745 11:33:13.981448 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5746 11:33:13.988334 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5747 11:33:13.991569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5748 11:33:13.995199 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5749 11:33:14.001409 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5750 11:33:14.004855 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5751 11:33:14.007830 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5752 11:33:14.014731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 11:33:14.017863 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 11:33:14.021101 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 11:33:14.027854 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 11:33:14.031403 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5757 11:33:14.034326 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5758 11:33:14.037887 Total UI for P1: 0, mck2ui 16
5759 11:33:14.040857 best dqsien dly found for B0: ( 1, 2, 24)
5760 11:33:14.047837 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 11:33:14.051170 Total UI for P1: 0, mck2ui 16
5762 11:33:14.054270 best dqsien dly found for B1: ( 1, 2, 26)
5763 11:33:14.057447 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5764 11:33:14.060743 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5765 11:33:14.060845
5766 11:33:14.064361 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5767 11:33:14.067329 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5768 11:33:14.071117 [Gating] SW calibration Done
5769 11:33:14.071185 ==
5770 11:33:14.074041 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 11:33:14.077273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 11:33:14.077345 ==
5773 11:33:14.080539 RX Vref Scan: 0
5774 11:33:14.080610
5775 11:33:14.083928 RX Vref 0 -> 0, step: 1
5776 11:33:14.083998
5777 11:33:14.084060 RX Delay -80 -> 252, step: 8
5778 11:33:14.090643 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5779 11:33:14.093576 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5780 11:33:14.097200 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5781 11:33:14.100089 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5782 11:33:14.103777 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5783 11:33:14.110255 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5784 11:33:14.113349 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5785 11:33:14.116473 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5786 11:33:14.120010 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5787 11:33:14.123593 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5788 11:33:14.126631 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5789 11:33:14.133410 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5790 11:33:14.136197 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5791 11:33:14.139779 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5792 11:33:14.143236 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5793 11:33:14.146264 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5794 11:33:14.146340 ==
5795 11:33:14.149594 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 11:33:14.156239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 11:33:14.156320 ==
5798 11:33:14.156383 DQS Delay:
5799 11:33:14.159331 DQS0 = 0, DQS1 = 0
5800 11:33:14.159398 DQM Delay:
5801 11:33:14.162669 DQM0 = 96, DQM1 = 91
5802 11:33:14.162747 DQ Delay:
5803 11:33:14.166061 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5804 11:33:14.169695 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5805 11:33:14.172655 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5806 11:33:14.176163 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5807 11:33:14.176240
5808 11:33:14.176300
5809 11:33:14.176354 ==
5810 11:33:14.179230 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 11:33:14.182856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 11:33:14.182935 ==
5813 11:33:14.182995
5814 11:33:14.183051
5815 11:33:14.185755 TX Vref Scan disable
5816 11:33:14.189259 == TX Byte 0 ==
5817 11:33:14.192859 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5818 11:33:14.195864 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5819 11:33:14.198940 == TX Byte 1 ==
5820 11:33:14.202485 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5821 11:33:14.205527 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5822 11:33:14.205604 ==
5823 11:33:14.209017 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 11:33:14.215444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 11:33:14.215522 ==
5826 11:33:14.215582
5827 11:33:14.215637
5828 11:33:14.215690 TX Vref Scan disable
5829 11:33:14.219570 == TX Byte 0 ==
5830 11:33:14.223249 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5831 11:33:14.229614 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5832 11:33:14.229691 == TX Byte 1 ==
5833 11:33:14.232453 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5834 11:33:14.239664 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5835 11:33:14.239746
5836 11:33:14.239806 [DATLAT]
5837 11:33:14.239862 Freq=933, CH1 RK1
5838 11:33:14.239915
5839 11:33:14.242467 DATLAT Default: 0xb
5840 11:33:14.246134 0, 0xFFFF, sum = 0
5841 11:33:14.246213 1, 0xFFFF, sum = 0
5842 11:33:14.249396 2, 0xFFFF, sum = 0
5843 11:33:14.249475 3, 0xFFFF, sum = 0
5844 11:33:14.252566 4, 0xFFFF, sum = 0
5845 11:33:14.252643 5, 0xFFFF, sum = 0
5846 11:33:14.255625 6, 0xFFFF, sum = 0
5847 11:33:14.255709 7, 0xFFFF, sum = 0
5848 11:33:14.259148 8, 0xFFFF, sum = 0
5849 11:33:14.259227 9, 0xFFFF, sum = 0
5850 11:33:14.262382 10, 0x0, sum = 1
5851 11:33:14.262461 11, 0x0, sum = 2
5852 11:33:14.265753 12, 0x0, sum = 3
5853 11:33:14.265831 13, 0x0, sum = 4
5854 11:33:14.268953 best_step = 11
5855 11:33:14.269054
5856 11:33:14.269147 ==
5857 11:33:14.272636 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 11:33:14.275621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 11:33:14.275699 ==
5860 11:33:14.275760 RX Vref Scan: 0
5861 11:33:14.278720
5862 11:33:14.278796 RX Vref 0 -> 0, step: 1
5863 11:33:14.278856
5864 11:33:14.282128 RX Delay -61 -> 252, step: 4
5865 11:33:14.288887 iDelay=199, Bit 0, Center 100 (7 ~ 194) 188
5866 11:33:14.291926 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5867 11:33:14.295529 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5868 11:33:14.298869 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5869 11:33:14.301794 iDelay=199, Bit 4, Center 96 (-1 ~ 194) 196
5870 11:33:14.308462 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5871 11:33:14.312410 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5872 11:33:14.314984 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5873 11:33:14.318623 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5874 11:33:14.321699 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5875 11:33:14.324875 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5876 11:33:14.331693 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5877 11:33:14.335426 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5878 11:33:14.337924 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5879 11:33:14.341562 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5880 11:33:14.348346 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5881 11:33:14.348422 ==
5882 11:33:14.351604 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 11:33:14.355023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 11:33:14.355101 ==
5885 11:33:14.355160 DQS Delay:
5886 11:33:14.358409 DQS0 = 0, DQS1 = 0
5887 11:33:14.358484 DQM Delay:
5888 11:33:14.361416 DQM0 = 96, DQM1 = 93
5889 11:33:14.361492 DQ Delay:
5890 11:33:14.364991 DQ0 =100, DQ1 =94, DQ2 =84, DQ3 =92
5891 11:33:14.368206 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =94
5892 11:33:14.371165 DQ8 =82, DQ9 =84, DQ10 =90, DQ11 =86
5893 11:33:14.374521 DQ12 =104, DQ13 =100, DQ14 =98, DQ15 =100
5894 11:33:14.374597
5895 11:33:14.374656
5896 11:33:14.384657 [DQSOSCAuto] RK1, (LSB)MR18= 0xc23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 418 ps
5897 11:33:14.384734 CH1 RK1: MR19=505, MR18=C23
5898 11:33:14.391144 CH1_RK1: MR19=0x505, MR18=0xC23, DQSOSC=410, MR23=63, INC=64, DEC=42
5899 11:33:14.393971 [RxdqsGatingPostProcess] freq 933
5900 11:33:14.400999 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5901 11:33:14.403932 best DQS0 dly(2T, 0.5T) = (0, 10)
5902 11:33:14.407524 best DQS1 dly(2T, 0.5T) = (0, 10)
5903 11:33:14.410810 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5904 11:33:14.414066 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5905 11:33:14.414141 best DQS0 dly(2T, 0.5T) = (0, 10)
5906 11:33:14.417789 best DQS1 dly(2T, 0.5T) = (0, 10)
5907 11:33:14.420602 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5908 11:33:14.423830 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5909 11:33:14.427411 Pre-setting of DQS Precalculation
5910 11:33:14.433802 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5911 11:33:14.440352 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5912 11:33:14.447017 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5913 11:33:14.447094
5914 11:33:14.447153
5915 11:33:14.450402 [Calibration Summary] 1866 Mbps
5916 11:33:14.453789 CH 0, Rank 0
5917 11:33:14.453865 SW Impedance : PASS
5918 11:33:14.457029 DUTY Scan : NO K
5919 11:33:14.457106 ZQ Calibration : PASS
5920 11:33:14.460361 Jitter Meter : NO K
5921 11:33:14.463911 CBT Training : PASS
5922 11:33:14.463987 Write leveling : PASS
5923 11:33:14.467235 RX DQS gating : PASS
5924 11:33:14.470309 RX DQ/DQS(RDDQC) : PASS
5925 11:33:14.470385 TX DQ/DQS : PASS
5926 11:33:14.473621 RX DATLAT : PASS
5927 11:33:14.477052 RX DQ/DQS(Engine): PASS
5928 11:33:14.477129 TX OE : NO K
5929 11:33:14.480287 All Pass.
5930 11:33:14.480362
5931 11:33:14.480421 CH 0, Rank 1
5932 11:33:14.483662 SW Impedance : PASS
5933 11:33:14.483737 DUTY Scan : NO K
5934 11:33:14.486642 ZQ Calibration : PASS
5935 11:33:14.490214 Jitter Meter : NO K
5936 11:33:14.490302 CBT Training : PASS
5937 11:33:14.493532 Write leveling : PASS
5938 11:33:14.496447 RX DQS gating : PASS
5939 11:33:14.496558 RX DQ/DQS(RDDQC) : PASS
5940 11:33:14.500006 TX DQ/DQS : PASS
5941 11:33:14.503388 RX DATLAT : PASS
5942 11:33:14.503464 RX DQ/DQS(Engine): PASS
5943 11:33:14.506644 TX OE : NO K
5944 11:33:14.506720 All Pass.
5945 11:33:14.506779
5946 11:33:14.509655 CH 1, Rank 0
5947 11:33:14.509730 SW Impedance : PASS
5948 11:33:14.513338 DUTY Scan : NO K
5949 11:33:14.517071 ZQ Calibration : PASS
5950 11:33:14.517209 Jitter Meter : NO K
5951 11:33:14.519724 CBT Training : PASS
5952 11:33:14.519792 Write leveling : PASS
5953 11:33:14.522950 RX DQS gating : PASS
5954 11:33:14.526414 RX DQ/DQS(RDDQC) : PASS
5955 11:33:14.526487 TX DQ/DQS : PASS
5956 11:33:14.529317 RX DATLAT : PASS
5957 11:33:14.533062 RX DQ/DQS(Engine): PASS
5958 11:33:14.533181 TX OE : NO K
5959 11:33:14.536279 All Pass.
5960 11:33:14.536387
5961 11:33:14.536474 CH 1, Rank 1
5962 11:33:14.539241 SW Impedance : PASS
5963 11:33:14.539306 DUTY Scan : NO K
5964 11:33:14.542583 ZQ Calibration : PASS
5965 11:33:14.546142 Jitter Meter : NO K
5966 11:33:14.546208 CBT Training : PASS
5967 11:33:14.549256 Write leveling : PASS
5968 11:33:14.552737 RX DQS gating : PASS
5969 11:33:14.552832 RX DQ/DQS(RDDQC) : PASS
5970 11:33:14.556325 TX DQ/DQS : PASS
5971 11:33:14.559085 RX DATLAT : PASS
5972 11:33:14.559150 RX DQ/DQS(Engine): PASS
5973 11:33:14.562461 TX OE : NO K
5974 11:33:14.562540 All Pass.
5975 11:33:14.562603
5976 11:33:14.566222 DramC Write-DBI off
5977 11:33:14.569133 PER_BANK_REFRESH: Hybrid Mode
5978 11:33:14.569239 TX_TRACKING: ON
5979 11:33:14.579044 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5980 11:33:14.582452 [FAST_K] Save calibration result to emmc
5981 11:33:14.585643 dramc_set_vcore_voltage set vcore to 650000
5982 11:33:14.588708 Read voltage for 400, 6
5983 11:33:14.588784 Vio18 = 0
5984 11:33:14.588842 Vcore = 650000
5985 11:33:14.592382 Vdram = 0
5986 11:33:14.592458 Vddq = 0
5987 11:33:14.592518 Vmddr = 0
5988 11:33:14.598780 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5989 11:33:14.602102 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5990 11:33:14.605038 MEM_TYPE=3, freq_sel=20
5991 11:33:14.608820 sv_algorithm_assistance_LP4_800
5992 11:33:14.612047 ============ PULL DRAM RESETB DOWN ============
5993 11:33:14.618421 ========== PULL DRAM RESETB DOWN end =========
5994 11:33:14.622043 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5995 11:33:14.625075 ===================================
5996 11:33:14.628712 LPDDR4 DRAM CONFIGURATION
5997 11:33:14.631530 ===================================
5998 11:33:14.631607 EX_ROW_EN[0] = 0x0
5999 11:33:14.635363 EX_ROW_EN[1] = 0x0
6000 11:33:14.635439 LP4Y_EN = 0x0
6001 11:33:14.638161 WORK_FSP = 0x0
6002 11:33:14.638263 WL = 0x2
6003 11:33:14.641602 RL = 0x2
6004 11:33:14.641695 BL = 0x2
6005 11:33:14.645037 RPST = 0x0
6006 11:33:14.645130 RD_PRE = 0x0
6007 11:33:14.648249 WR_PRE = 0x1
6008 11:33:14.651375 WR_PST = 0x0
6009 11:33:14.651471 DBI_WR = 0x0
6010 11:33:14.654897 DBI_RD = 0x0
6011 11:33:14.654980 OTF = 0x1
6012 11:33:14.657799 ===================================
6013 11:33:14.661494 ===================================
6014 11:33:14.664913 ANA top config
6015 11:33:14.665011 ===================================
6016 11:33:14.668612 DLL_ASYNC_EN = 0
6017 11:33:14.671159 ALL_SLAVE_EN = 1
6018 11:33:14.674626 NEW_RANK_MODE = 1
6019 11:33:14.677787 DLL_IDLE_MODE = 1
6020 11:33:14.677861 LP45_APHY_COMB_EN = 1
6021 11:33:14.681208 TX_ODT_DIS = 1
6022 11:33:14.684762 NEW_8X_MODE = 1
6023 11:33:14.687412 ===================================
6024 11:33:14.691247 ===================================
6025 11:33:14.694364 data_rate = 800
6026 11:33:14.697946 CKR = 1
6027 11:33:14.700610 DQ_P2S_RATIO = 4
6028 11:33:14.704419 ===================================
6029 11:33:14.704515 CA_P2S_RATIO = 4
6030 11:33:14.707556 DQ_CA_OPEN = 0
6031 11:33:14.711226 DQ_SEMI_OPEN = 1
6032 11:33:14.714566 CA_SEMI_OPEN = 1
6033 11:33:14.717387 CA_FULL_RATE = 0
6034 11:33:14.720803 DQ_CKDIV4_EN = 0
6035 11:33:14.720871 CA_CKDIV4_EN = 1
6036 11:33:14.724103 CA_PREDIV_EN = 0
6037 11:33:14.727559 PH8_DLY = 0
6038 11:33:14.730308 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6039 11:33:14.733861 DQ_AAMCK_DIV = 0
6040 11:33:14.737093 CA_AAMCK_DIV = 0
6041 11:33:14.737232 CA_ADMCK_DIV = 4
6042 11:33:14.740569 DQ_TRACK_CA_EN = 0
6043 11:33:14.743854 CA_PICK = 800
6044 11:33:14.746867 CA_MCKIO = 400
6045 11:33:14.750530 MCKIO_SEMI = 400
6046 11:33:14.754164 PLL_FREQ = 3016
6047 11:33:14.756632 DQ_UI_PI_RATIO = 32
6048 11:33:14.760401 CA_UI_PI_RATIO = 32
6049 11:33:14.763574 ===================================
6050 11:33:14.767276 ===================================
6051 11:33:14.767353 memory_type:LPDDR4
6052 11:33:14.770251 GP_NUM : 10
6053 11:33:14.773320 SRAM_EN : 1
6054 11:33:14.773395 MD32_EN : 0
6055 11:33:14.776725 ===================================
6056 11:33:14.779639 [ANA_INIT] >>>>>>>>>>>>>>
6057 11:33:14.783140 <<<<<< [CONFIGURE PHASE]: ANA_TX
6058 11:33:14.786106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6059 11:33:14.789543 ===================================
6060 11:33:14.793365 data_rate = 800,PCW = 0X7400
6061 11:33:14.796103 ===================================
6062 11:33:14.799699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6063 11:33:14.803147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6064 11:33:14.816219 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6065 11:33:14.819587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6066 11:33:14.822515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6067 11:33:14.825819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6068 11:33:14.829091 [ANA_INIT] flow start
6069 11:33:14.832373 [ANA_INIT] PLL >>>>>>>>
6070 11:33:14.832448 [ANA_INIT] PLL <<<<<<<<
6071 11:33:14.835898 [ANA_INIT] MIDPI >>>>>>>>
6072 11:33:14.839477 [ANA_INIT] MIDPI <<<<<<<<
6073 11:33:14.839553 [ANA_INIT] DLL >>>>>>>>
6074 11:33:14.842503 [ANA_INIT] flow end
6075 11:33:14.845966 ============ LP4 DIFF to SE enter ============
6076 11:33:14.852430 ============ LP4 DIFF to SE exit ============
6077 11:33:14.852507 [ANA_INIT] <<<<<<<<<<<<<
6078 11:33:14.855838 [Flow] Enable top DCM control >>>>>
6079 11:33:14.858728 [Flow] Enable top DCM control <<<<<
6080 11:33:14.862423 Enable DLL master slave shuffle
6081 11:33:14.868744 ==============================================================
6082 11:33:14.868827 Gating Mode config
6083 11:33:14.875355 ==============================================================
6084 11:33:14.878886 Config description:
6085 11:33:14.885380 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6086 11:33:14.895458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6087 11:33:14.898595 SELPH_MODE 0: By rank 1: By Phase
6088 11:33:14.905160 ==============================================================
6089 11:33:14.908040 GAT_TRACK_EN = 0
6090 11:33:14.911627 RX_GATING_MODE = 2
6091 11:33:14.911692 RX_GATING_TRACK_MODE = 2
6092 11:33:14.914955 SELPH_MODE = 1
6093 11:33:14.918022 PICG_EARLY_EN = 1
6094 11:33:14.921177 VALID_LAT_VALUE = 1
6095 11:33:14.928355 ==============================================================
6096 11:33:14.931114 Enter into Gating configuration >>>>
6097 11:33:14.934544 Exit from Gating configuration <<<<
6098 11:33:14.937698 Enter into DVFS_PRE_config >>>>>
6099 11:33:14.948378 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6100 11:33:14.951015 Exit from DVFS_PRE_config <<<<<
6101 11:33:14.954593 Enter into PICG configuration >>>>
6102 11:33:14.957835 Exit from PICG configuration <<<<
6103 11:33:14.961642 [RX_INPUT] configuration >>>>>
6104 11:33:14.964132 [RX_INPUT] configuration <<<<<
6105 11:33:14.967827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6106 11:33:14.974149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6107 11:33:14.980679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6108 11:33:14.987160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6109 11:33:14.993984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6110 11:33:14.997368 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6111 11:33:15.003612 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6112 11:33:15.007462 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6113 11:33:15.010450 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6114 11:33:15.013407 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6115 11:33:15.020500 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6116 11:33:15.023756 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6117 11:33:15.026663 ===================================
6118 11:33:15.030350 LPDDR4 DRAM CONFIGURATION
6119 11:33:15.033485 ===================================
6120 11:33:15.033581 EX_ROW_EN[0] = 0x0
6121 11:33:15.036800 EX_ROW_EN[1] = 0x0
6122 11:33:15.036867 LP4Y_EN = 0x0
6123 11:33:15.040038 WORK_FSP = 0x0
6124 11:33:15.043278 WL = 0x2
6125 11:33:15.043376 RL = 0x2
6126 11:33:15.046732 BL = 0x2
6127 11:33:15.046831 RPST = 0x0
6128 11:33:15.049814 RD_PRE = 0x0
6129 11:33:15.049883 WR_PRE = 0x1
6130 11:33:15.052923 WR_PST = 0x0
6131 11:33:15.053014 DBI_WR = 0x0
6132 11:33:15.056317 DBI_RD = 0x0
6133 11:33:15.056407 OTF = 0x1
6134 11:33:15.059814 ===================================
6135 11:33:15.063313 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6136 11:33:15.069677 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6137 11:33:15.073154 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6138 11:33:15.076148 ===================================
6139 11:33:15.079347 LPDDR4 DRAM CONFIGURATION
6140 11:33:15.082817 ===================================
6141 11:33:15.082889 EX_ROW_EN[0] = 0x10
6142 11:33:15.085966 EX_ROW_EN[1] = 0x0
6143 11:33:15.086040 LP4Y_EN = 0x0
6144 11:33:15.089640 WORK_FSP = 0x0
6145 11:33:15.092773 WL = 0x2
6146 11:33:15.092843 RL = 0x2
6147 11:33:15.095981 BL = 0x2
6148 11:33:15.096048 RPST = 0x0
6149 11:33:15.099504 RD_PRE = 0x0
6150 11:33:15.099571 WR_PRE = 0x1
6151 11:33:15.102565 WR_PST = 0x0
6152 11:33:15.102629 DBI_WR = 0x0
6153 11:33:15.106048 DBI_RD = 0x0
6154 11:33:15.106118 OTF = 0x1
6155 11:33:15.109204 ===================================
6156 11:33:15.115706 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6157 11:33:15.119942 nWR fixed to 30
6158 11:33:15.123195 [ModeRegInit_LP4] CH0 RK0
6159 11:33:15.123271 [ModeRegInit_LP4] CH0 RK1
6160 11:33:15.126324 [ModeRegInit_LP4] CH1 RK0
6161 11:33:15.129834 [ModeRegInit_LP4] CH1 RK1
6162 11:33:15.129918 match AC timing 19
6163 11:33:15.136849 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6164 11:33:15.139976 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6165 11:33:15.143594 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6166 11:33:15.149499 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6167 11:33:15.153249 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6168 11:33:15.153322 ==
6169 11:33:15.156346 Dram Type= 6, Freq= 0, CH_0, rank 0
6170 11:33:15.159552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6171 11:33:15.159645 ==
6172 11:33:15.166171 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6173 11:33:15.172758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6174 11:33:15.176206 [CA 0] Center 36 (8~64) winsize 57
6175 11:33:15.179268 [CA 1] Center 36 (8~64) winsize 57
6176 11:33:15.182917 [CA 2] Center 36 (8~64) winsize 57
6177 11:33:15.185944 [CA 3] Center 36 (8~64) winsize 57
6178 11:33:15.188955 [CA 4] Center 36 (8~64) winsize 57
6179 11:33:15.192792 [CA 5] Center 36 (8~64) winsize 57
6180 11:33:15.192884
6181 11:33:15.195533 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6182 11:33:15.195621
6183 11:33:15.198980 [CATrainingPosCal] consider 1 rank data
6184 11:33:15.202396 u2DelayCellTimex100 = 270/100 ps
6185 11:33:15.205496 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6186 11:33:15.208964 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6187 11:33:15.212318 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6188 11:33:15.215626 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6189 11:33:15.219455 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6190 11:33:15.222293 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6191 11:33:15.222362
6192 11:33:15.225782 CA PerBit enable=1, Macro0, CA PI delay=36
6193 11:33:15.229092
6194 11:33:15.229225 [CBTSetCACLKResult] CA Dly = 36
6195 11:33:15.232227 CS Dly: 1 (0~32)
6196 11:33:15.232316 ==
6197 11:33:15.235273 Dram Type= 6, Freq= 0, CH_0, rank 1
6198 11:33:15.238681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6199 11:33:15.238752 ==
6200 11:33:15.245219 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6201 11:33:15.251710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6202 11:33:15.254945 [CA 0] Center 36 (8~64) winsize 57
6203 11:33:15.258307 [CA 1] Center 36 (8~64) winsize 57
6204 11:33:15.261512 [CA 2] Center 36 (8~64) winsize 57
6205 11:33:15.265233 [CA 3] Center 36 (8~64) winsize 57
6206 11:33:15.265329 [CA 4] Center 36 (8~64) winsize 57
6207 11:33:15.267961 [CA 5] Center 36 (8~64) winsize 57
6208 11:33:15.268052
6209 11:33:15.274567 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6210 11:33:15.274661
6211 11:33:15.278082 [CATrainingPosCal] consider 2 rank data
6212 11:33:15.281358 u2DelayCellTimex100 = 270/100 ps
6213 11:33:15.284723 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:33:15.287742 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:33:15.291405 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:33:15.294474 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:33:15.298069 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:33:15.301414 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 11:33:15.301508
6220 11:33:15.304273 CA PerBit enable=1, Macro0, CA PI delay=36
6221 11:33:15.304367
6222 11:33:15.307757 [CBTSetCACLKResult] CA Dly = 36
6223 11:33:15.310846 CS Dly: 1 (0~32)
6224 11:33:15.310937
6225 11:33:15.314239 ----->DramcWriteLeveling(PI) begin...
6226 11:33:15.314333 ==
6227 11:33:15.317627 Dram Type= 6, Freq= 0, CH_0, rank 0
6228 11:33:15.321029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 11:33:15.321126 ==
6230 11:33:15.324317 Write leveling (Byte 0): 40 => 8
6231 11:33:15.327436 Write leveling (Byte 1): 40 => 8
6232 11:33:15.330852 DramcWriteLeveling(PI) end<-----
6233 11:33:15.330931
6234 11:33:15.330987 ==
6235 11:33:15.334530 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 11:33:15.337632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 11:33:15.337711 ==
6238 11:33:15.340582 [Gating] SW mode calibration
6239 11:33:15.346867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6240 11:33:15.354119 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6241 11:33:15.357098 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6242 11:33:15.363585 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6243 11:33:15.367239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6244 11:33:15.370461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6245 11:33:15.377027 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6246 11:33:15.380408 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6247 11:33:15.383267 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6248 11:33:15.389849 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6249 11:33:15.393322 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6250 11:33:15.396867 Total UI for P1: 0, mck2ui 16
6251 11:33:15.399843 best dqsien dly found for B0: ( 0, 14, 24)
6252 11:33:15.402845 Total UI for P1: 0, mck2ui 16
6253 11:33:15.406184 best dqsien dly found for B1: ( 0, 14, 24)
6254 11:33:15.409541 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6255 11:33:15.413149 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6256 11:33:15.413233
6257 11:33:15.416679 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6258 11:33:15.423235 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6259 11:33:15.423312 [Gating] SW calibration Done
6260 11:33:15.423371 ==
6261 11:33:15.426393 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 11:33:15.432963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 11:33:15.433065 ==
6264 11:33:15.433160 RX Vref Scan: 0
6265 11:33:15.433231
6266 11:33:15.435831 RX Vref 0 -> 0, step: 1
6267 11:33:15.435906
6268 11:33:15.439389 RX Delay -410 -> 252, step: 16
6269 11:33:15.442507 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6270 11:33:15.445926 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6271 11:33:15.453050 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6272 11:33:15.455830 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6273 11:33:15.459132 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6274 11:33:15.462293 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6275 11:33:15.468976 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6276 11:33:15.472112 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6277 11:33:15.475374 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6278 11:33:15.478958 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6279 11:33:15.485497 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6280 11:33:15.488516 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6281 11:33:15.492116 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6282 11:33:15.498192 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6283 11:33:15.501791 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6284 11:33:15.504966 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6285 11:33:15.505042 ==
6286 11:33:15.508430 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 11:33:15.511880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 11:33:15.514880 ==
6289 11:33:15.514955 DQS Delay:
6290 11:33:15.515013 DQS0 = 35, DQS1 = 59
6291 11:33:15.518253 DQM Delay:
6292 11:33:15.518340 DQM0 = 4, DQM1 = 18
6293 11:33:15.521333 DQ Delay:
6294 11:33:15.521407 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6295 11:33:15.524865 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6296 11:33:15.527841 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6297 11:33:15.531421 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6298 11:33:15.531496
6299 11:33:15.531554
6300 11:33:15.534623 ==
6301 11:33:15.537847 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 11:33:15.541723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 11:33:15.541814 ==
6304 11:33:15.541872
6305 11:33:15.541924
6306 11:33:15.544885 TX Vref Scan disable
6307 11:33:15.544959 == TX Byte 0 ==
6308 11:33:15.547716 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6309 11:33:15.554237 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6310 11:33:15.554313 == TX Byte 1 ==
6311 11:33:15.557789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6312 11:33:15.564380 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6313 11:33:15.564476 ==
6314 11:33:15.567546 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 11:33:15.570788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 11:33:15.570876 ==
6317 11:33:15.570934
6318 11:33:15.571018
6319 11:33:15.574211 TX Vref Scan disable
6320 11:33:15.574300 == TX Byte 0 ==
6321 11:33:15.577437 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6322 11:33:15.584234 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6323 11:33:15.584310 == TX Byte 1 ==
6324 11:33:15.587231 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6325 11:33:15.593692 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6326 11:33:15.593781
6327 11:33:15.593853 [DATLAT]
6328 11:33:15.597274 Freq=400, CH0 RK0
6329 11:33:15.597352
6330 11:33:15.597413 DATLAT Default: 0xf
6331 11:33:15.600311 0, 0xFFFF, sum = 0
6332 11:33:15.600378 1, 0xFFFF, sum = 0
6333 11:33:15.603736 2, 0xFFFF, sum = 0
6334 11:33:15.603815 3, 0xFFFF, sum = 0
6335 11:33:15.606994 4, 0xFFFF, sum = 0
6336 11:33:15.607101 5, 0xFFFF, sum = 0
6337 11:33:15.610305 6, 0xFFFF, sum = 0
6338 11:33:15.610395 7, 0xFFFF, sum = 0
6339 11:33:15.613699 8, 0xFFFF, sum = 0
6340 11:33:15.613804 9, 0xFFFF, sum = 0
6341 11:33:15.616782 10, 0xFFFF, sum = 0
6342 11:33:15.620117 11, 0xFFFF, sum = 0
6343 11:33:15.620193 12, 0xFFFF, sum = 0
6344 11:33:15.623312 13, 0x0, sum = 1
6345 11:33:15.623389 14, 0x0, sum = 2
6346 11:33:15.623448 15, 0x0, sum = 3
6347 11:33:15.626432 16, 0x0, sum = 4
6348 11:33:15.626509 best_step = 14
6349 11:33:15.626568
6350 11:33:15.630026 ==
6351 11:33:15.630101 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 11:33:15.636280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 11:33:15.636355 ==
6354 11:33:15.636414 RX Vref Scan: 1
6355 11:33:15.636467
6356 11:33:15.640154 RX Vref 0 -> 0, step: 1
6357 11:33:15.640229
6358 11:33:15.642849 RX Delay -359 -> 252, step: 8
6359 11:33:15.642941
6360 11:33:15.646538 Set Vref, RX VrefLevel [Byte0]: 51
6361 11:33:15.649913 [Byte1]: 59
6362 11:33:15.653484
6363 11:33:15.653573 Final RX Vref Byte 0 = 51 to rank0
6364 11:33:15.657304 Final RX Vref Byte 1 = 59 to rank0
6365 11:33:15.660192 Final RX Vref Byte 0 = 51 to rank1
6366 11:33:15.663288 Final RX Vref Byte 1 = 59 to rank1==
6367 11:33:15.666332 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 11:33:15.672888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 11:33:15.672982 ==
6370 11:33:15.673098 DQS Delay:
6371 11:33:15.676483 DQS0 = 44, DQS1 = 60
6372 11:33:15.676572 DQM Delay:
6373 11:33:15.676629 DQM0 = 10, DQM1 = 16
6374 11:33:15.680066 DQ Delay:
6375 11:33:15.682818 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6376 11:33:15.686411 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6377 11:33:15.686485 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6378 11:33:15.693184 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6379 11:33:15.693260
6380 11:33:15.693319
6381 11:33:15.699294 [DQSOSCAuto] RK0, (LSB)MR18= 0x9589, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6382 11:33:15.703321 CH0 RK0: MR19=C0C, MR18=9589
6383 11:33:15.709714 CH0_RK0: MR19=0xC0C, MR18=0x9589, DQSOSC=391, MR23=63, INC=386, DEC=257
6384 11:33:15.709791 ==
6385 11:33:15.712990 Dram Type= 6, Freq= 0, CH_0, rank 1
6386 11:33:15.715824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 11:33:15.715900 ==
6388 11:33:15.719001 [Gating] SW mode calibration
6389 11:33:15.725466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6390 11:33:15.731968 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6391 11:33:15.735513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6392 11:33:15.739067 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6393 11:33:15.745387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6394 11:33:15.748913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6395 11:33:15.751649 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6396 11:33:15.758784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6397 11:33:15.762041 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6398 11:33:15.765202 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6399 11:33:15.772065 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6400 11:33:15.774825 Total UI for P1: 0, mck2ui 16
6401 11:33:15.778330 best dqsien dly found for B0: ( 0, 14, 24)
6402 11:33:15.781347 Total UI for P1: 0, mck2ui 16
6403 11:33:15.784905 best dqsien dly found for B1: ( 0, 14, 24)
6404 11:33:15.788320 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6405 11:33:15.791709 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6406 11:33:15.791785
6407 11:33:15.794702 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6408 11:33:15.797914 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6409 11:33:15.801302 [Gating] SW calibration Done
6410 11:33:15.801414 ==
6411 11:33:15.805088 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 11:33:15.808053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 11:33:15.811107 ==
6414 11:33:15.811208 RX Vref Scan: 0
6415 11:33:15.811293
6416 11:33:15.814612 RX Vref 0 -> 0, step: 1
6417 11:33:15.814723
6418 11:33:15.817572 RX Delay -410 -> 252, step: 16
6419 11:33:15.821193 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6420 11:33:15.824204 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6421 11:33:15.827531 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6422 11:33:15.834407 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6423 11:33:15.837833 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6424 11:33:15.840543 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6425 11:33:15.844200 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6426 11:33:15.850370 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6427 11:33:15.854271 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6428 11:33:15.856951 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6429 11:33:15.863549 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6430 11:33:15.866940 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6431 11:33:15.870687 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6432 11:33:15.873568 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6433 11:33:15.880126 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6434 11:33:15.883617 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6435 11:33:15.883718 ==
6436 11:33:15.886569 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 11:33:15.890435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 11:33:15.890558 ==
6439 11:33:15.893391 DQS Delay:
6440 11:33:15.893468 DQS0 = 35, DQS1 = 59
6441 11:33:15.896664 DQM Delay:
6442 11:33:15.896768 DQM0 = 8, DQM1 = 16
6443 11:33:15.896856 DQ Delay:
6444 11:33:15.899835 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6445 11:33:15.903234 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6446 11:33:15.906647 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6447 11:33:15.909745 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6448 11:33:15.909831
6449 11:33:15.909889
6450 11:33:15.909942 ==
6451 11:33:15.913263 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 11:33:15.919778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 11:33:15.919901 ==
6454 11:33:15.919986
6455 11:33:15.920081
6456 11:33:15.920162 TX Vref Scan disable
6457 11:33:15.922762 == TX Byte 0 ==
6458 11:33:15.926356 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6459 11:33:15.929633 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6460 11:33:15.932653 == TX Byte 1 ==
6461 11:33:15.935968 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6462 11:33:15.939337 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6463 11:33:15.939444 ==
6464 11:33:15.942632 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 11:33:15.949603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 11:33:15.949698 ==
6467 11:33:15.949772
6468 11:33:15.949845
6469 11:33:15.949902 TX Vref Scan disable
6470 11:33:15.952560 == TX Byte 0 ==
6471 11:33:15.956208 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6472 11:33:15.959071 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6473 11:33:15.962753 == TX Byte 1 ==
6474 11:33:15.965907 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6475 11:33:15.968787 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6476 11:33:15.972322
6477 11:33:15.972431 [DATLAT]
6478 11:33:15.972514 Freq=400, CH0 RK1
6479 11:33:15.972593
6480 11:33:15.975809 DATLAT Default: 0xe
6481 11:33:15.975918 0, 0xFFFF, sum = 0
6482 11:33:15.978800 1, 0xFFFF, sum = 0
6483 11:33:15.978910 2, 0xFFFF, sum = 0
6484 11:33:15.982312 3, 0xFFFF, sum = 0
6485 11:33:15.985517 4, 0xFFFF, sum = 0
6486 11:33:15.985601 5, 0xFFFF, sum = 0
6487 11:33:15.988766 6, 0xFFFF, sum = 0
6488 11:33:15.988828 7, 0xFFFF, sum = 0
6489 11:33:15.992349 8, 0xFFFF, sum = 0
6490 11:33:15.992426 9, 0xFFFF, sum = 0
6491 11:33:15.995508 10, 0xFFFF, sum = 0
6492 11:33:15.995587 11, 0xFFFF, sum = 0
6493 11:33:15.998749 12, 0xFFFF, sum = 0
6494 11:33:15.998827 13, 0x0, sum = 1
6495 11:33:16.002256 14, 0x0, sum = 2
6496 11:33:16.002359 15, 0x0, sum = 3
6497 11:33:16.005112 16, 0x0, sum = 4
6498 11:33:16.005212 best_step = 14
6499 11:33:16.005298
6500 11:33:16.005357 ==
6501 11:33:16.008262 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 11:33:16.011635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 11:33:16.015159 ==
6504 11:33:16.015237 RX Vref Scan: 0
6505 11:33:16.015297
6506 11:33:16.018231 RX Vref 0 -> 0, step: 1
6507 11:33:16.018308
6508 11:33:16.021477 RX Delay -359 -> 252, step: 8
6509 11:33:16.028481 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6510 11:33:16.031503 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6511 11:33:16.035023 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6512 11:33:16.038392 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6513 11:33:16.044868 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6514 11:33:16.047816 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6515 11:33:16.051461 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6516 11:33:16.054851 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6517 11:33:16.061470 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6518 11:33:16.064693 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6519 11:33:16.067909 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6520 11:33:16.070896 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6521 11:33:16.077433 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6522 11:33:16.081054 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6523 11:33:16.084177 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6524 11:33:16.090717 iDelay=209, Bit 15, Center -40 (-287 ~ 208) 496
6525 11:33:16.090795 ==
6526 11:33:16.094339 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 11:33:16.097356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 11:33:16.097434 ==
6529 11:33:16.097495 DQS Delay:
6530 11:33:16.100860 DQS0 = 44, DQS1 = 60
6531 11:33:16.100937 DQM Delay:
6532 11:33:16.103903 DQM0 = 9, DQM1 = 15
6533 11:33:16.103980 DQ Delay:
6534 11:33:16.107367 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6535 11:33:16.110941 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6536 11:33:16.114061 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6537 11:33:16.117333 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6538 11:33:16.117410
6539 11:33:16.117471
6540 11:33:16.123829 [DQSOSCAuto] RK1, (LSB)MR18= 0x8b83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6541 11:33:16.127038 CH0 RK1: MR19=C0C, MR18=8B83
6542 11:33:16.133641 CH0_RK1: MR19=0xC0C, MR18=0x8B83, DQSOSC=392, MR23=63, INC=384, DEC=256
6543 11:33:16.137336 [RxdqsGatingPostProcess] freq 400
6544 11:33:16.143597 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6545 11:33:16.146616 best DQS0 dly(2T, 0.5T) = (0, 10)
6546 11:33:16.146693 best DQS1 dly(2T, 0.5T) = (0, 10)
6547 11:33:16.150055 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6548 11:33:16.153731 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6549 11:33:16.156660 best DQS0 dly(2T, 0.5T) = (0, 10)
6550 11:33:16.160391 best DQS1 dly(2T, 0.5T) = (0, 10)
6551 11:33:16.163239 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6552 11:33:16.166689 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6553 11:33:16.170052 Pre-setting of DQS Precalculation
6554 11:33:16.176954 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6555 11:33:16.177033 ==
6556 11:33:16.179834 Dram Type= 6, Freq= 0, CH_1, rank 0
6557 11:33:16.183388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 11:33:16.183468 ==
6559 11:33:16.189982 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6560 11:33:16.196776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6561 11:33:16.196881 [CA 0] Center 36 (8~64) winsize 57
6562 11:33:16.199514 [CA 1] Center 36 (8~64) winsize 57
6563 11:33:16.203077 [CA 2] Center 36 (8~64) winsize 57
6564 11:33:16.206122 [CA 3] Center 36 (8~64) winsize 57
6565 11:33:16.209569 [CA 4] Center 36 (8~64) winsize 57
6566 11:33:16.212539 [CA 5] Center 36 (8~64) winsize 57
6567 11:33:16.212630
6568 11:33:16.216123 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6569 11:33:16.216224
6570 11:33:16.219104 [CATrainingPosCal] consider 1 rank data
6571 11:33:16.222759 u2DelayCellTimex100 = 270/100 ps
6572 11:33:16.226217 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6573 11:33:16.232437 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6574 11:33:16.235463 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6575 11:33:16.238745 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6576 11:33:16.242286 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6577 11:33:16.245851 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6578 11:33:16.245944
6579 11:33:16.249021 CA PerBit enable=1, Macro0, CA PI delay=36
6580 11:33:16.249114
6581 11:33:16.252491 [CBTSetCACLKResult] CA Dly = 36
6582 11:33:16.255342 CS Dly: 1 (0~32)
6583 11:33:16.255419 ==
6584 11:33:16.258994 Dram Type= 6, Freq= 0, CH_1, rank 1
6585 11:33:16.261971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 11:33:16.262047 ==
6587 11:33:16.268491 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6588 11:33:16.272247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6589 11:33:16.275621 [CA 0] Center 36 (8~64) winsize 57
6590 11:33:16.278379 [CA 1] Center 36 (8~64) winsize 57
6591 11:33:16.282144 [CA 2] Center 36 (8~64) winsize 57
6592 11:33:16.285330 [CA 3] Center 36 (8~64) winsize 57
6593 11:33:16.288356 [CA 4] Center 36 (8~64) winsize 57
6594 11:33:16.291982 [CA 5] Center 36 (8~64) winsize 57
6595 11:33:16.292058
6596 11:33:16.294847 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6597 11:33:16.294923
6598 11:33:16.298647 [CATrainingPosCal] consider 2 rank data
6599 11:33:16.301776 u2DelayCellTimex100 = 270/100 ps
6600 11:33:16.304930 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:33:16.308059 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:33:16.314667 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:33:16.318250 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:33:16.321316 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:33:16.324863 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 11:33:16.324954
6607 11:33:16.327930 CA PerBit enable=1, Macro0, CA PI delay=36
6608 11:33:16.328021
6609 11:33:16.331645 [CBTSetCACLKResult] CA Dly = 36
6610 11:33:16.331720 CS Dly: 1 (0~32)
6611 11:33:16.334553
6612 11:33:16.338226 ----->DramcWriteLeveling(PI) begin...
6613 11:33:16.338336 ==
6614 11:33:16.341098 Dram Type= 6, Freq= 0, CH_1, rank 0
6615 11:33:16.344585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 11:33:16.344662 ==
6617 11:33:16.347768 Write leveling (Byte 0): 40 => 8
6618 11:33:16.351018 Write leveling (Byte 1): 40 => 8
6619 11:33:16.354299 DramcWriteLeveling(PI) end<-----
6620 11:33:16.354417
6621 11:33:16.354505 ==
6622 11:33:16.357697 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 11:33:16.360775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 11:33:16.360851 ==
6625 11:33:16.364442 [Gating] SW mode calibration
6626 11:33:16.371249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6627 11:33:16.377390 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6628 11:33:16.380755 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6629 11:33:16.384008 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6630 11:33:16.390609 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6631 11:33:16.393885 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6632 11:33:16.396872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6633 11:33:16.403741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6634 11:33:16.407084 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6635 11:33:16.410551 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6636 11:33:16.416988 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6637 11:33:16.420196 Total UI for P1: 0, mck2ui 16
6638 11:33:16.423295 best dqsien dly found for B0: ( 0, 14, 24)
6639 11:33:16.423388 Total UI for P1: 0, mck2ui 16
6640 11:33:16.429738 best dqsien dly found for B1: ( 0, 14, 24)
6641 11:33:16.433583 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6642 11:33:16.436530 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6643 11:33:16.436607
6644 11:33:16.440047 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6645 11:33:16.443757 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6646 11:33:16.446864 [Gating] SW calibration Done
6647 11:33:16.446940 ==
6648 11:33:16.449781 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 11:33:16.453242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 11:33:16.453319 ==
6651 11:33:16.456609 RX Vref Scan: 0
6652 11:33:16.456685
6653 11:33:16.456759 RX Vref 0 -> 0, step: 1
6654 11:33:16.459630
6655 11:33:16.459705 RX Delay -410 -> 252, step: 16
6656 11:33:16.466231 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6657 11:33:16.469500 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6658 11:33:16.473101 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6659 11:33:16.479716 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6660 11:33:16.483253 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6661 11:33:16.486072 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6662 11:33:16.489520 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6663 11:33:16.496224 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6664 11:33:16.499514 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6665 11:33:16.502535 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6666 11:33:16.505874 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6667 11:33:16.512249 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6668 11:33:16.515722 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6669 11:33:16.519195 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6670 11:33:16.522150 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6671 11:33:16.529233 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6672 11:33:16.529341 ==
6673 11:33:16.532298 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 11:33:16.535824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 11:33:16.535901 ==
6676 11:33:16.535960 DQS Delay:
6677 11:33:16.538927 DQS0 = 35, DQS1 = 51
6678 11:33:16.539003 DQM Delay:
6679 11:33:16.542256 DQM0 = 6, DQM1 = 16
6680 11:33:16.542331 DQ Delay:
6681 11:33:16.545194 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6682 11:33:16.548697 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6683 11:33:16.552239 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6684 11:33:16.555012 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6685 11:33:16.555087
6686 11:33:16.555146
6687 11:33:16.555200 ==
6688 11:33:16.558619 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 11:33:16.561880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 11:33:16.561956 ==
6691 11:33:16.564876
6692 11:33:16.564950
6693 11:33:16.565008 TX Vref Scan disable
6694 11:33:16.568387 == TX Byte 0 ==
6695 11:33:16.571664 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6696 11:33:16.574954 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6697 11:33:16.578460 == TX Byte 1 ==
6698 11:33:16.581270 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6699 11:33:16.585317 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6700 11:33:16.585393 ==
6701 11:33:16.588268 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 11:33:16.591291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 11:33:16.594758 ==
6704 11:33:16.594832
6705 11:33:16.594891
6706 11:33:16.594945 TX Vref Scan disable
6707 11:33:16.598209 == TX Byte 0 ==
6708 11:33:16.601761 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6709 11:33:16.604952 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6710 11:33:16.607944 == TX Byte 1 ==
6711 11:33:16.611948 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6712 11:33:16.614626 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6713 11:33:16.614716
6714 11:33:16.617957 [DATLAT]
6715 11:33:16.618072 Freq=400, CH1 RK0
6716 11:33:16.618149
6717 11:33:16.621002 DATLAT Default: 0xf
6718 11:33:16.621084 0, 0xFFFF, sum = 0
6719 11:33:16.624627 1, 0xFFFF, sum = 0
6720 11:33:16.624704 2, 0xFFFF, sum = 0
6721 11:33:16.627704 3, 0xFFFF, sum = 0
6722 11:33:16.627781 4, 0xFFFF, sum = 0
6723 11:33:16.631229 5, 0xFFFF, sum = 0
6724 11:33:16.631306 6, 0xFFFF, sum = 0
6725 11:33:16.634281 7, 0xFFFF, sum = 0
6726 11:33:16.634384 8, 0xFFFF, sum = 0
6727 11:33:16.637671 9, 0xFFFF, sum = 0
6728 11:33:16.637748 10, 0xFFFF, sum = 0
6729 11:33:16.640760 11, 0xFFFF, sum = 0
6730 11:33:16.644148 12, 0xFFFF, sum = 0
6731 11:33:16.644225 13, 0x0, sum = 1
6732 11:33:16.647173 14, 0x0, sum = 2
6733 11:33:16.647249 15, 0x0, sum = 3
6734 11:33:16.647309 16, 0x0, sum = 4
6735 11:33:16.650557 best_step = 14
6736 11:33:16.650648
6737 11:33:16.650741 ==
6738 11:33:16.653836 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 11:33:16.657405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 11:33:16.657477 ==
6741 11:33:16.660254 RX Vref Scan: 1
6742 11:33:16.660347
6743 11:33:16.663871 RX Vref 0 -> 0, step: 1
6744 11:33:16.663963
6745 11:33:16.664047 RX Delay -343 -> 252, step: 8
6746 11:33:16.664127
6747 11:33:16.667524 Set Vref, RX VrefLevel [Byte0]: 53
6748 11:33:16.670108 [Byte1]: 52
6749 11:33:16.675691
6750 11:33:16.675785 Final RX Vref Byte 0 = 53 to rank0
6751 11:33:16.678887 Final RX Vref Byte 1 = 52 to rank0
6752 11:33:16.682294 Final RX Vref Byte 0 = 53 to rank1
6753 11:33:16.685470 Final RX Vref Byte 1 = 52 to rank1==
6754 11:33:16.688986 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 11:33:16.695431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 11:33:16.695525 ==
6757 11:33:16.695612 DQS Delay:
6758 11:33:16.698491 DQS0 = 44, DQS1 = 52
6759 11:33:16.698589 DQM Delay:
6760 11:33:16.701770 DQM0 = 11, DQM1 = 10
6761 11:33:16.701868 DQ Delay:
6762 11:33:16.705105 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6763 11:33:16.708877 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6764 11:33:16.708971 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6765 11:33:16.712076 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6766 11:33:16.715332
6767 11:33:16.715423
6768 11:33:16.721857 [DQSOSCAuto] RK0, (LSB)MR18= 0x739a, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6769 11:33:16.725306 CH1 RK0: MR19=C0C, MR18=739A
6770 11:33:16.731492 CH1_RK0: MR19=0xC0C, MR18=0x739A, DQSOSC=390, MR23=63, INC=388, DEC=258
6771 11:33:16.731588 ==
6772 11:33:16.734756 Dram Type= 6, Freq= 0, CH_1, rank 1
6773 11:33:16.738591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 11:33:16.738689 ==
6775 11:33:16.742078 [Gating] SW mode calibration
6776 11:33:16.748476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6777 11:33:16.754800 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6778 11:33:16.758197 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6779 11:33:16.761396 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6780 11:33:16.768071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6781 11:33:16.771405 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6782 11:33:16.774351 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6783 11:33:16.780968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6784 11:33:16.784742 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6785 11:33:16.787687 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6786 11:33:16.794082 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6787 11:33:16.797738 Total UI for P1: 0, mck2ui 16
6788 11:33:16.800469 best dqsien dly found for B0: ( 0, 14, 24)
6789 11:33:16.803916 Total UI for P1: 0, mck2ui 16
6790 11:33:16.807277 best dqsien dly found for B1: ( 0, 14, 24)
6791 11:33:16.810561 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6792 11:33:16.814097 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6793 11:33:16.814193
6794 11:33:16.816989 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6795 11:33:16.820340 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6796 11:33:16.823850 [Gating] SW calibration Done
6797 11:33:16.823946 ==
6798 11:33:16.827505 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 11:33:16.830394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 11:33:16.830491 ==
6801 11:33:16.834037 RX Vref Scan: 0
6802 11:33:16.834132
6803 11:33:16.837240 RX Vref 0 -> 0, step: 1
6804 11:33:16.837336
6805 11:33:16.837422 RX Delay -410 -> 252, step: 16
6806 11:33:16.843649 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6807 11:33:16.847046 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6808 11:33:16.850362 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6809 11:33:16.856952 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6810 11:33:16.860176 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6811 11:33:16.863634 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6812 11:33:16.867023 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6813 11:33:16.874000 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6814 11:33:16.877420 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6815 11:33:16.880034 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6816 11:33:16.883284 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6817 11:33:16.889846 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6818 11:33:16.893497 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6819 11:33:16.896811 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6820 11:33:16.899731 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6821 11:33:16.906844 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6822 11:33:16.906945 ==
6823 11:33:16.909772 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 11:33:16.913185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 11:33:16.913279 ==
6826 11:33:16.913366 DQS Delay:
6827 11:33:16.916290 DQS0 = 43, DQS1 = 51
6828 11:33:16.916382 DQM Delay:
6829 11:33:16.919810 DQM0 = 10, DQM1 = 15
6830 11:33:16.919902 DQ Delay:
6831 11:33:16.923144 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6832 11:33:16.926125 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6833 11:33:16.930266 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6834 11:33:16.932730 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6835 11:33:16.932825
6836 11:33:16.932910
6837 11:33:16.932992 ==
6838 11:33:16.936221 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 11:33:16.939797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 11:33:16.939893 ==
6841 11:33:16.943305
6842 11:33:16.943399
6843 11:33:16.943483 TX Vref Scan disable
6844 11:33:16.946423 == TX Byte 0 ==
6845 11:33:16.949670 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6846 11:33:16.952391 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6847 11:33:16.956026 == TX Byte 1 ==
6848 11:33:16.959474 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6849 11:33:16.962379 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6850 11:33:16.962453 ==
6851 11:33:16.965893 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 11:33:16.969562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 11:33:16.972881 ==
6854 11:33:16.972952
6855 11:33:16.973010
6856 11:33:16.973066 TX Vref Scan disable
6857 11:33:16.975587 == TX Byte 0 ==
6858 11:33:16.979271 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6859 11:33:16.982049 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6860 11:33:16.985619 == TX Byte 1 ==
6861 11:33:16.988590 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6862 11:33:16.992261 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6863 11:33:16.992333
6864 11:33:16.995728 [DATLAT]
6865 11:33:16.995796 Freq=400, CH1 RK1
6866 11:33:16.995859
6867 11:33:16.998643 DATLAT Default: 0xe
6868 11:33:16.998712 0, 0xFFFF, sum = 0
6869 11:33:17.002162 1, 0xFFFF, sum = 0
6870 11:33:17.002233 2, 0xFFFF, sum = 0
6871 11:33:17.005823 3, 0xFFFF, sum = 0
6872 11:33:17.005896 4, 0xFFFF, sum = 0
6873 11:33:17.008783 5, 0xFFFF, sum = 0
6874 11:33:17.008879 6, 0xFFFF, sum = 0
6875 11:33:17.011846 7, 0xFFFF, sum = 0
6876 11:33:17.011937 8, 0xFFFF, sum = 0
6877 11:33:17.015009 9, 0xFFFF, sum = 0
6878 11:33:17.015079 10, 0xFFFF, sum = 0
6879 11:33:17.018495 11, 0xFFFF, sum = 0
6880 11:33:17.021955 12, 0xFFFF, sum = 0
6881 11:33:17.022028 13, 0x0, sum = 1
6882 11:33:17.025006 14, 0x0, sum = 2
6883 11:33:17.025103 15, 0x0, sum = 3
6884 11:33:17.025182 16, 0x0, sum = 4
6885 11:33:17.028160 best_step = 14
6886 11:33:17.028231
6887 11:33:17.028285 ==
6888 11:33:17.031860 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 11:33:17.034799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 11:33:17.034891 ==
6891 11:33:17.038164 RX Vref Scan: 0
6892 11:33:17.038255
6893 11:33:17.038338 RX Vref 0 -> 0, step: 1
6894 11:33:17.041519
6895 11:33:17.041590 RX Delay -343 -> 252, step: 8
6896 11:33:17.050242 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6897 11:33:17.053463 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6898 11:33:17.056855 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6899 11:33:17.063564 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6900 11:33:17.066312 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6901 11:33:17.069613 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6902 11:33:17.073272 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6903 11:33:17.079416 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6904 11:33:17.083020 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6905 11:33:17.086248 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6906 11:33:17.089738 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6907 11:33:17.096367 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6908 11:33:17.099384 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6909 11:33:17.102997 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6910 11:33:17.105976 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6911 11:33:17.112478 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6912 11:33:17.112551 ==
6913 11:33:17.116051 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 11:33:17.119024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 11:33:17.119115 ==
6916 11:33:17.119226 DQS Delay:
6917 11:33:17.122468 DQS0 = 48, DQS1 = 52
6918 11:33:17.122559 DQM Delay:
6919 11:33:17.125498 DQM0 = 12, DQM1 = 10
6920 11:33:17.125566 DQ Delay:
6921 11:33:17.129054 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6922 11:33:17.132105 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6923 11:33:17.135650 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6924 11:33:17.138617 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6925 11:33:17.138692
6926 11:33:17.138750
6927 11:33:17.148712 [DQSOSCAuto] RK1, (LSB)MR18= 0x80b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6928 11:33:17.148803 CH1 RK1: MR19=C0C, MR18=80B7
6929 11:33:17.155542 CH1_RK1: MR19=0xC0C, MR18=0x80B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6930 11:33:17.158945 [RxdqsGatingPostProcess] freq 400
6931 11:33:17.165679 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6932 11:33:17.168433 best DQS0 dly(2T, 0.5T) = (0, 10)
6933 11:33:17.172311 best DQS1 dly(2T, 0.5T) = (0, 10)
6934 11:33:17.175434 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6935 11:33:17.178797 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6936 11:33:17.181788 best DQS0 dly(2T, 0.5T) = (0, 10)
6937 11:33:17.185266 best DQS1 dly(2T, 0.5T) = (0, 10)
6938 11:33:17.188335 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6939 11:33:17.191607 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6940 11:33:17.191682 Pre-setting of DQS Precalculation
6941 11:33:17.198354 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6942 11:33:17.204911 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6943 11:33:17.211481 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6944 11:33:17.211557
6945 11:33:17.211615
6946 11:33:17.214959 [Calibration Summary] 800 Mbps
6947 11:33:17.217887 CH 0, Rank 0
6948 11:33:17.217962 SW Impedance : PASS
6949 11:33:17.221404 DUTY Scan : NO K
6950 11:33:17.224550 ZQ Calibration : PASS
6951 11:33:17.224625 Jitter Meter : NO K
6952 11:33:17.228009 CBT Training : PASS
6953 11:33:17.230985 Write leveling : PASS
6954 11:33:17.231060 RX DQS gating : PASS
6955 11:33:17.234672 RX DQ/DQS(RDDQC) : PASS
6956 11:33:17.237393 TX DQ/DQS : PASS
6957 11:33:17.237468 RX DATLAT : PASS
6958 11:33:17.241082 RX DQ/DQS(Engine): PASS
6959 11:33:17.244145 TX OE : NO K
6960 11:33:17.244222 All Pass.
6961 11:33:17.244281
6962 11:33:17.244335 CH 0, Rank 1
6963 11:33:17.247611 SW Impedance : PASS
6964 11:33:17.250903 DUTY Scan : NO K
6965 11:33:17.250982 ZQ Calibration : PASS
6966 11:33:17.254246 Jitter Meter : NO K
6967 11:33:17.254339 CBT Training : PASS
6968 11:33:17.257367 Write leveling : NO K
6969 11:33:17.260930 RX DQS gating : PASS
6970 11:33:17.261022 RX DQ/DQS(RDDQC) : PASS
6971 11:33:17.263839 TX DQ/DQS : PASS
6972 11:33:17.267420 RX DATLAT : PASS
6973 11:33:17.267514 RX DQ/DQS(Engine): PASS
6974 11:33:17.270312 TX OE : NO K
6975 11:33:17.270407 All Pass.
6976 11:33:17.270506
6977 11:33:17.274205 CH 1, Rank 0
6978 11:33:17.274292 SW Impedance : PASS
6979 11:33:17.277228 DUTY Scan : NO K
6980 11:33:17.280457 ZQ Calibration : PASS
6981 11:33:17.280546 Jitter Meter : NO K
6982 11:33:17.284080 CBT Training : PASS
6983 11:33:17.286774 Write leveling : PASS
6984 11:33:17.286867 RX DQS gating : PASS
6985 11:33:17.290235 RX DQ/DQS(RDDQC) : PASS
6986 11:33:17.293428 TX DQ/DQS : PASS
6987 11:33:17.293496 RX DATLAT : PASS
6988 11:33:17.296954 RX DQ/DQS(Engine): PASS
6989 11:33:17.300163 TX OE : NO K
6990 11:33:17.300244 All Pass.
6991 11:33:17.300330
6992 11:33:17.300413 CH 1, Rank 1
6993 11:33:17.303387 SW Impedance : PASS
6994 11:33:17.306426 DUTY Scan : NO K
6995 11:33:17.306493 ZQ Calibration : PASS
6996 11:33:17.310108 Jitter Meter : NO K
6997 11:33:17.313482 CBT Training : PASS
6998 11:33:17.313554 Write leveling : NO K
6999 11:33:17.316385 RX DQS gating : PASS
7000 11:33:17.320045 RX DQ/DQS(RDDQC) : PASS
7001 11:33:17.320141 TX DQ/DQS : PASS
7002 11:33:17.322947 RX DATLAT : PASS
7003 11:33:17.326737 RX DQ/DQS(Engine): PASS
7004 11:33:17.326835 TX OE : NO K
7005 11:33:17.326921 All Pass.
7006 11:33:17.330266
7007 11:33:17.330359 DramC Write-DBI off
7008 11:33:17.333078 PER_BANK_REFRESH: Hybrid Mode
7009 11:33:17.333168 TX_TRACKING: ON
7010 11:33:17.342668 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7011 11:33:17.346223 [FAST_K] Save calibration result to emmc
7012 11:33:17.349862 dramc_set_vcore_voltage set vcore to 725000
7013 11:33:17.352848 Read voltage for 1600, 0
7014 11:33:17.352941 Vio18 = 0
7015 11:33:17.356337 Vcore = 725000
7016 11:33:17.356429 Vdram = 0
7017 11:33:17.356515 Vddq = 0
7018 11:33:17.359559 Vmddr = 0
7019 11:33:17.362615 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7020 11:33:17.369183 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7021 11:33:17.369280 MEM_TYPE=3, freq_sel=13
7022 11:33:17.372232 sv_algorithm_assistance_LP4_3733
7023 11:33:17.378827 ============ PULL DRAM RESETB DOWN ============
7024 11:33:17.382291 ========== PULL DRAM RESETB DOWN end =========
7025 11:33:17.385546 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7026 11:33:17.389532 ===================================
7027 11:33:17.392147 LPDDR4 DRAM CONFIGURATION
7028 11:33:17.395560 ===================================
7029 11:33:17.399165 EX_ROW_EN[0] = 0x0
7030 11:33:17.399261 EX_ROW_EN[1] = 0x0
7031 11:33:17.402267 LP4Y_EN = 0x0
7032 11:33:17.402363 WORK_FSP = 0x1
7033 11:33:17.405644 WL = 0x5
7034 11:33:17.405731 RL = 0x5
7035 11:33:17.408776 BL = 0x2
7036 11:33:17.408873 RPST = 0x0
7037 11:33:17.411805 RD_PRE = 0x0
7038 11:33:17.411896 WR_PRE = 0x1
7039 11:33:17.415022 WR_PST = 0x1
7040 11:33:17.415100 DBI_WR = 0x0
7041 11:33:17.419033 DBI_RD = 0x0
7042 11:33:17.419099 OTF = 0x1
7043 11:33:17.422014 ===================================
7044 11:33:17.425355 ===================================
7045 11:33:17.428168 ANA top config
7046 11:33:17.431765 ===================================
7047 11:33:17.435283 DLL_ASYNC_EN = 0
7048 11:33:17.435373 ALL_SLAVE_EN = 0
7049 11:33:17.438433 NEW_RANK_MODE = 1
7050 11:33:17.441400 DLL_IDLE_MODE = 1
7051 11:33:17.445231 LP45_APHY_COMB_EN = 1
7052 11:33:17.447894 TX_ODT_DIS = 0
7053 11:33:17.447989 NEW_8X_MODE = 1
7054 11:33:17.451636 ===================================
7055 11:33:17.454530 ===================================
7056 11:33:17.457970 data_rate = 3200
7057 11:33:17.461379 CKR = 1
7058 11:33:17.464341 DQ_P2S_RATIO = 8
7059 11:33:17.467723 ===================================
7060 11:33:17.471259 CA_P2S_RATIO = 8
7061 11:33:17.474197 DQ_CA_OPEN = 0
7062 11:33:17.474263 DQ_SEMI_OPEN = 0
7063 11:33:17.477666 CA_SEMI_OPEN = 0
7064 11:33:17.481116 CA_FULL_RATE = 0
7065 11:33:17.484145 DQ_CKDIV4_EN = 0
7066 11:33:17.487684 CA_CKDIV4_EN = 0
7067 11:33:17.491187 CA_PREDIV_EN = 0
7068 11:33:17.491279 PH8_DLY = 12
7069 11:33:17.494175 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7070 11:33:17.497782 DQ_AAMCK_DIV = 4
7071 11:33:17.500822 CA_AAMCK_DIV = 4
7072 11:33:17.504020 CA_ADMCK_DIV = 4
7073 11:33:17.507419 DQ_TRACK_CA_EN = 0
7074 11:33:17.510857 CA_PICK = 1600
7075 11:33:17.514028 CA_MCKIO = 1600
7076 11:33:17.514126 MCKIO_SEMI = 0
7077 11:33:17.517125 PLL_FREQ = 3068
7078 11:33:17.520558 DQ_UI_PI_RATIO = 32
7079 11:33:17.523864 CA_UI_PI_RATIO = 0
7080 11:33:17.527009 ===================================
7081 11:33:17.530608 ===================================
7082 11:33:17.533902 memory_type:LPDDR4
7083 11:33:17.533999 GP_NUM : 10
7084 11:33:17.537362 SRAM_EN : 1
7085 11:33:17.537432 MD32_EN : 0
7086 11:33:17.541015 ===================================
7087 11:33:17.543709 [ANA_INIT] >>>>>>>>>>>>>>
7088 11:33:17.547257 <<<<<< [CONFIGURE PHASE]: ANA_TX
7089 11:33:17.550229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7090 11:33:17.553487 ===================================
7091 11:33:17.557092 data_rate = 3200,PCW = 0X7600
7092 11:33:17.560175 ===================================
7093 11:33:17.563838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7094 11:33:17.570153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7095 11:33:17.573816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7096 11:33:17.580475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7097 11:33:17.583453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7098 11:33:17.586957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7099 11:33:17.587026 [ANA_INIT] flow start
7100 11:33:17.589792 [ANA_INIT] PLL >>>>>>>>
7101 11:33:17.593052 [ANA_INIT] PLL <<<<<<<<
7102 11:33:17.596673 [ANA_INIT] MIDPI >>>>>>>>
7103 11:33:17.596766 [ANA_INIT] MIDPI <<<<<<<<
7104 11:33:17.599905 [ANA_INIT] DLL >>>>>>>>
7105 11:33:17.603483 [ANA_INIT] DLL <<<<<<<<
7106 11:33:17.603576 [ANA_INIT] flow end
7107 11:33:17.606384 ============ LP4 DIFF to SE enter ============
7108 11:33:17.612847 ============ LP4 DIFF to SE exit ============
7109 11:33:17.612931 [ANA_INIT] <<<<<<<<<<<<<
7110 11:33:17.616230 [Flow] Enable top DCM control >>>>>
7111 11:33:17.619440 [Flow] Enable top DCM control <<<<<
7112 11:33:17.622970 Enable DLL master slave shuffle
7113 11:33:17.629672 ==============================================================
7114 11:33:17.629749 Gating Mode config
7115 11:33:17.636128 ==============================================================
7116 11:33:17.639550 Config description:
7117 11:33:17.649339 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7118 11:33:17.655926 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7119 11:33:17.659346 SELPH_MODE 0: By rank 1: By Phase
7120 11:33:17.665650 ==============================================================
7121 11:33:17.669042 GAT_TRACK_EN = 1
7122 11:33:17.671993 RX_GATING_MODE = 2
7123 11:33:17.675497 RX_GATING_TRACK_MODE = 2
7124 11:33:17.678661 SELPH_MODE = 1
7125 11:33:17.678730 PICG_EARLY_EN = 1
7126 11:33:17.682032 VALID_LAT_VALUE = 1
7127 11:33:17.688512 ==============================================================
7128 11:33:17.692183 Enter into Gating configuration >>>>
7129 11:33:17.695821 Exit from Gating configuration <<<<
7130 11:33:17.698498 Enter into DVFS_PRE_config >>>>>
7131 11:33:17.708683 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7132 11:33:17.711871 Exit from DVFS_PRE_config <<<<<
7133 11:33:17.715019 Enter into PICG configuration >>>>
7134 11:33:17.718545 Exit from PICG configuration <<<<
7135 11:33:17.721598 [RX_INPUT] configuration >>>>>
7136 11:33:17.725099 [RX_INPUT] configuration <<<<<
7137 11:33:17.732036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7138 11:33:17.734477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7139 11:33:17.741557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7140 11:33:17.748088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7141 11:33:17.754548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7142 11:33:17.761044 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7143 11:33:17.764285 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7144 11:33:17.767883 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7145 11:33:17.770635 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7146 11:33:17.777578 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7147 11:33:17.780619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7148 11:33:17.784464 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7149 11:33:17.787235 ===================================
7150 11:33:17.790861 LPDDR4 DRAM CONFIGURATION
7151 11:33:17.794185 ===================================
7152 11:33:17.796987 EX_ROW_EN[0] = 0x0
7153 11:33:17.797076 EX_ROW_EN[1] = 0x0
7154 11:33:17.800478 LP4Y_EN = 0x0
7155 11:33:17.800575 WORK_FSP = 0x1
7156 11:33:17.804029 WL = 0x5
7157 11:33:17.804121 RL = 0x5
7158 11:33:17.807029 BL = 0x2
7159 11:33:17.807122 RPST = 0x0
7160 11:33:17.810362 RD_PRE = 0x0
7161 11:33:17.810435 WR_PRE = 0x1
7162 11:33:17.813646 WR_PST = 0x1
7163 11:33:17.813738 DBI_WR = 0x0
7164 11:33:17.817351 DBI_RD = 0x0
7165 11:33:17.817422 OTF = 0x1
7166 11:33:17.820608 ===================================
7167 11:33:17.827102 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7168 11:33:17.830059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7169 11:33:17.833670 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7170 11:33:17.836607 ===================================
7171 11:33:17.840216 LPDDR4 DRAM CONFIGURATION
7172 11:33:17.843647 ===================================
7173 11:33:17.846627 EX_ROW_EN[0] = 0x10
7174 11:33:17.846697 EX_ROW_EN[1] = 0x0
7175 11:33:17.849942 LP4Y_EN = 0x0
7176 11:33:17.850015 WORK_FSP = 0x1
7177 11:33:17.853445 WL = 0x5
7178 11:33:17.853538 RL = 0x5
7179 11:33:17.856451 BL = 0x2
7180 11:33:17.856545 RPST = 0x0
7181 11:33:17.859760 RD_PRE = 0x0
7182 11:33:17.859830 WR_PRE = 0x1
7183 11:33:17.863035 WR_PST = 0x1
7184 11:33:17.863129 DBI_WR = 0x0
7185 11:33:17.866438 DBI_RD = 0x0
7186 11:33:17.866533 OTF = 0x1
7187 11:33:17.869738 ===================================
7188 11:33:17.876506 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7189 11:33:17.876609 ==
7190 11:33:17.879606 Dram Type= 6, Freq= 0, CH_0, rank 0
7191 11:33:17.886503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7192 11:33:17.886583 ==
7193 11:33:17.886642 [Duty_Offset_Calibration]
7194 11:33:17.889526 B0:2 B1:0 CA:4
7195 11:33:17.889595
7196 11:33:17.893273 [DutyScan_Calibration_Flow] k_type=0
7197 11:33:17.901600
7198 11:33:17.901675 ==CLK 0==
7199 11:33:17.904662 Final CLK duty delay cell = -4
7200 11:33:17.908191 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7201 11:33:17.911251 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7202 11:33:17.914961 [-4] AVG Duty = 4922%(X100)
7203 11:33:17.915037
7204 11:33:17.917999 CH0 CLK Duty spec in!! Max-Min= 218%
7205 11:33:17.921150 [DutyScan_Calibration_Flow] ====Done====
7206 11:33:17.921217
7207 11:33:17.924363 [DutyScan_Calibration_Flow] k_type=1
7208 11:33:17.941684
7209 11:33:17.941780 ==DQS 0 ==
7210 11:33:17.944989 Final DQS duty delay cell = 0
7211 11:33:17.948633 [0] MAX Duty = 5218%(X100), DQS PI = 38
7212 11:33:17.951756 [0] MIN Duty = 5093%(X100), DQS PI = 12
7213 11:33:17.954763 [0] AVG Duty = 5155%(X100)
7214 11:33:17.954853
7215 11:33:17.954935 ==DQS 1 ==
7216 11:33:17.958457 Final DQS duty delay cell = 0
7217 11:33:17.961180 [0] MAX Duty = 5156%(X100), DQS PI = 2
7218 11:33:17.964743 [0] MIN Duty = 4969%(X100), DQS PI = 10
7219 11:33:17.967834 [0] AVG Duty = 5062%(X100)
7220 11:33:17.967924
7221 11:33:17.970970 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7222 11:33:17.971058
7223 11:33:17.974917 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7224 11:33:17.977881 [DutyScan_Calibration_Flow] ====Done====
7225 11:33:17.977986
7226 11:33:17.980840 [DutyScan_Calibration_Flow] k_type=3
7227 11:33:17.998794
7228 11:33:17.998872 ==DQM 0 ==
7229 11:33:18.002293 Final DQM duty delay cell = 0
7230 11:33:18.005329 [0] MAX Duty = 5124%(X100), DQS PI = 20
7231 11:33:18.008834 [0] MIN Duty = 4844%(X100), DQS PI = 56
7232 11:33:18.012807 [0] AVG Duty = 4984%(X100)
7233 11:33:18.012896
7234 11:33:18.012979 ==DQM 1 ==
7235 11:33:18.015303 Final DQM duty delay cell = 0
7236 11:33:18.018912 [0] MAX Duty = 5000%(X100), DQS PI = 2
7237 11:33:18.021896 [0] MIN Duty = 4844%(X100), DQS PI = 14
7238 11:33:18.025404 [0] AVG Duty = 4922%(X100)
7239 11:33:18.025497
7240 11:33:18.028737 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7241 11:33:18.028804
7242 11:33:18.032125 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7243 11:33:18.035245 [DutyScan_Calibration_Flow] ====Done====
7244 11:33:18.035333
7245 11:33:18.038335 [DutyScan_Calibration_Flow] k_type=2
7246 11:33:18.056385
7247 11:33:18.056478 ==DQ 0 ==
7248 11:33:18.059128 Final DQ duty delay cell = 0
7249 11:33:18.062444 [0] MAX Duty = 5156%(X100), DQS PI = 26
7250 11:33:18.065762 [0] MIN Duty = 4938%(X100), DQS PI = 10
7251 11:33:18.065855 [0] AVG Duty = 5047%(X100)
7252 11:33:18.069429
7253 11:33:18.069493 ==DQ 1 ==
7254 11:33:18.072704 Final DQ duty delay cell = 0
7255 11:33:18.075745 [0] MAX Duty = 5187%(X100), DQS PI = 2
7256 11:33:18.078933 [0] MIN Duty = 4907%(X100), DQS PI = 16
7257 11:33:18.079001 [0] AVG Duty = 5047%(X100)
7258 11:33:18.082871
7259 11:33:18.085522 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7260 11:33:18.085610
7261 11:33:18.088800 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7262 11:33:18.092203 [DutyScan_Calibration_Flow] ====Done====
7263 11:33:18.092269 ==
7264 11:33:18.095868 Dram Type= 6, Freq= 0, CH_1, rank 0
7265 11:33:18.098881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7266 11:33:18.098972 ==
7267 11:33:18.102604 [Duty_Offset_Calibration]
7268 11:33:18.102668 B0:0 B1:-1 CA:3
7269 11:33:18.102724
7270 11:33:18.105854 [DutyScan_Calibration_Flow] k_type=0
7271 11:33:18.116451
7272 11:33:18.116524 ==CLK 0==
7273 11:33:18.119425 Final CLK duty delay cell = 0
7274 11:33:18.123008 [0] MAX Duty = 5187%(X100), DQS PI = 6
7275 11:33:18.126063 [0] MIN Duty = 5000%(X100), DQS PI = 38
7276 11:33:18.129718 [0] AVG Duty = 5093%(X100)
7277 11:33:18.129787
7278 11:33:18.132648 CH1 CLK Duty spec in!! Max-Min= 187%
7279 11:33:18.136212 [DutyScan_Calibration_Flow] ====Done====
7280 11:33:18.136281
7281 11:33:18.139095 [DutyScan_Calibration_Flow] k_type=1
7282 11:33:18.155394
7283 11:33:18.155494 ==DQS 0 ==
7284 11:33:18.158259 Final DQS duty delay cell = 0
7285 11:33:18.161944 [0] MAX Duty = 5218%(X100), DQS PI = 28
7286 11:33:18.165210 [0] MIN Duty = 4907%(X100), DQS PI = 60
7287 11:33:18.168531 [0] AVG Duty = 5062%(X100)
7288 11:33:18.168609
7289 11:33:18.168669 ==DQS 1 ==
7290 11:33:18.171647 Final DQS duty delay cell = -4
7291 11:33:18.175225 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7292 11:33:18.177986 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7293 11:33:18.181499 [-4] AVG Duty = 4906%(X100)
7294 11:33:18.181589
7295 11:33:18.184409 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7296 11:33:18.184499
7297 11:33:18.188407 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7298 11:33:18.191542 [DutyScan_Calibration_Flow] ====Done====
7299 11:33:18.191616
7300 11:33:18.194496 [DutyScan_Calibration_Flow] k_type=3
7301 11:33:18.212171
7302 11:33:18.212246 ==DQM 0 ==
7303 11:33:18.215635 Final DQM duty delay cell = 0
7304 11:33:18.218864 [0] MAX Duty = 5031%(X100), DQS PI = 30
7305 11:33:18.222368 [0] MIN Duty = 4750%(X100), DQS PI = 40
7306 11:33:18.225284 [0] AVG Duty = 4890%(X100)
7307 11:33:18.225358
7308 11:33:18.225415 ==DQM 1 ==
7309 11:33:18.228606 Final DQM duty delay cell = 0
7310 11:33:18.231942 [0] MAX Duty = 4969%(X100), DQS PI = 30
7311 11:33:18.235554 [0] MIN Duty = 4813%(X100), DQS PI = 60
7312 11:33:18.238857 [0] AVG Duty = 4891%(X100)
7313 11:33:18.238931
7314 11:33:18.242128 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7315 11:33:18.242202
7316 11:33:18.245378 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7317 11:33:18.248929 [DutyScan_Calibration_Flow] ====Done====
7318 11:33:18.249032
7319 11:33:18.251542 [DutyScan_Calibration_Flow] k_type=2
7320 11:33:18.268892
7321 11:33:18.268978 ==DQ 0 ==
7322 11:33:18.272120 Final DQ duty delay cell = -4
7323 11:33:18.275217 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7324 11:33:18.278484 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7325 11:33:18.281498 [-4] AVG Duty = 4875%(X100)
7326 11:33:18.281573
7327 11:33:18.281631 ==DQ 1 ==
7328 11:33:18.285473 Final DQ duty delay cell = 0
7329 11:33:18.288093 [0] MAX Duty = 5031%(X100), DQS PI = 30
7330 11:33:18.291681 [0] MIN Duty = 4844%(X100), DQS PI = 60
7331 11:33:18.294929 [0] AVG Duty = 4937%(X100)
7332 11:33:18.295003
7333 11:33:18.298253 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7334 11:33:18.298354
7335 11:33:18.301673 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7336 11:33:18.304831 [DutyScan_Calibration_Flow] ====Done====
7337 11:33:18.308056 nWR fixed to 30
7338 11:33:18.311985 [ModeRegInit_LP4] CH0 RK0
7339 11:33:18.312073 [ModeRegInit_LP4] CH0 RK1
7340 11:33:18.314522 [ModeRegInit_LP4] CH1 RK0
7341 11:33:18.317860 [ModeRegInit_LP4] CH1 RK1
7342 11:33:18.317957 match AC timing 5
7343 11:33:18.324581 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7344 11:33:18.327820 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7345 11:33:18.330855 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7346 11:33:18.337345 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7347 11:33:18.340805 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7348 11:33:18.343795 [MiockJmeterHQA]
7349 11:33:18.343870
7350 11:33:18.347221 [DramcMiockJmeter] u1RxGatingPI = 0
7351 11:33:18.347296 0 : 4255, 4026
7352 11:33:18.347357 4 : 4253, 4026
7353 11:33:18.350762 8 : 4255, 4029
7354 11:33:18.350839 12 : 4252, 4026
7355 11:33:18.354810 16 : 4252, 4027
7356 11:33:18.354887 20 : 4252, 4027
7357 11:33:18.357257 24 : 4252, 4027
7358 11:33:18.357334 28 : 4363, 4137
7359 11:33:18.357395 32 : 4252, 4027
7360 11:33:18.360806 36 : 4252, 4027
7361 11:33:18.360883 40 : 4253, 4026
7362 11:33:18.363765 44 : 4258, 4032
7363 11:33:18.363842 48 : 4252, 4027
7364 11:33:18.367460 52 : 4361, 4137
7365 11:33:18.367537 56 : 4360, 4138
7366 11:33:18.370702 60 : 4253, 4026
7367 11:33:18.370780 64 : 4250, 4026
7368 11:33:18.370840 68 : 4249, 4027
7369 11:33:18.373789 72 : 4250, 4026
7370 11:33:18.373868 76 : 4250, 4027
7371 11:33:18.377153 80 : 4360, 4137
7372 11:33:18.377231 84 : 4250, 4027
7373 11:33:18.380499 88 : 4249, 4027
7374 11:33:18.380612 92 : 4250, 4026
7375 11:33:18.383558 96 : 4250, 2834
7376 11:33:18.383635 100 : 4249, 0
7377 11:33:18.383703 104 : 4250, 0
7378 11:33:18.386993 108 : 4255, 0
7379 11:33:18.387075 112 : 4360, 0
7380 11:33:18.390269 116 : 4360, 0
7381 11:33:18.390372 120 : 4250, 0
7382 11:33:18.390460 124 : 4250, 0
7383 11:33:18.393432 128 : 4249, 0
7384 11:33:18.393510 132 : 4250, 0
7385 11:33:18.396932 136 : 4250, 0
7386 11:33:18.397010 140 : 4249, 0
7387 11:33:18.397070 144 : 4250, 0
7388 11:33:18.400007 148 : 4250, 0
7389 11:33:18.400085 152 : 4249, 0
7390 11:33:18.400145 156 : 4250, 0
7391 11:33:18.403878 160 : 4361, 0
7392 11:33:18.403985 164 : 4360, 0
7393 11:33:18.406957 168 : 4361, 0
7394 11:33:18.407060 172 : 4250, 0
7395 11:33:18.407148 176 : 4250, 0
7396 11:33:18.410268 180 : 4363, 0
7397 11:33:18.410346 184 : 4250, 0
7398 11:33:18.413107 188 : 4250, 0
7399 11:33:18.413192 192 : 4249, 0
7400 11:33:18.413254 196 : 4252, 0
7401 11:33:18.416431 200 : 4250, 0
7402 11:33:18.416508 204 : 4250, 0
7403 11:33:18.420150 208 : 4250, 0
7404 11:33:18.420232 212 : 4361, 0
7405 11:33:18.420297 216 : 4360, 0
7406 11:33:18.423140 220 : 4360, 563
7407 11:33:18.423217 224 : 4250, 4020
7408 11:33:18.426281 228 : 4361, 4137
7409 11:33:18.426359 232 : 4250, 4026
7410 11:33:18.429715 236 : 4249, 4027
7411 11:33:18.429792 240 : 4360, 4137
7412 11:33:18.432810 244 : 4250, 4026
7413 11:33:18.432887 248 : 4250, 4026
7414 11:33:18.436273 252 : 4361, 4138
7415 11:33:18.436351 256 : 4249, 4027
7416 11:33:18.439307 260 : 4250, 4026
7417 11:33:18.439385 264 : 4250, 4027
7418 11:33:18.439445 268 : 4250, 4027
7419 11:33:18.442986 272 : 4249, 4027
7420 11:33:18.443064 276 : 4250, 4026
7421 11:33:18.445992 280 : 4361, 4137
7422 11:33:18.446071 284 : 4250, 4027
7423 11:33:18.449319 288 : 4249, 4027
7424 11:33:18.449396 292 : 4360, 4137
7425 11:33:18.452980 296 : 4250, 4027
7426 11:33:18.453057 300 : 4250, 4026
7427 11:33:18.455978 304 : 4360, 4138
7428 11:33:18.456082 308 : 4249, 4027
7429 11:33:18.459303 312 : 4250, 4027
7430 11:33:18.459381 316 : 4250, 4026
7431 11:33:18.462325 320 : 4250, 4027
7432 11:33:18.462403 324 : 4249, 4027
7433 11:33:18.465841 328 : 4250, 4027
7434 11:33:18.465918 332 : 4361, 4072
7435 11:33:18.468878 336 : 4250, 1434
7436 11:33:18.468955
7437 11:33:18.469015 MIOCK jitter meter ch=0
7438 11:33:18.469070
7439 11:33:18.472381 1T = (336-100) = 236 dly cells
7440 11:33:18.478958 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7441 11:33:18.479034 ==
7442 11:33:18.482289 Dram Type= 6, Freq= 0, CH_0, rank 0
7443 11:33:18.485537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7444 11:33:18.485614 ==
7445 11:33:18.492460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7446 11:33:18.495607 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7447 11:33:18.498641 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7448 11:33:18.505243 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7449 11:33:18.514845 [CA 0] Center 43 (13~73) winsize 61
7450 11:33:18.518517 [CA 1] Center 42 (12~73) winsize 62
7451 11:33:18.521965 [CA 2] Center 37 (8~67) winsize 60
7452 11:33:18.525062 [CA 3] Center 37 (8~67) winsize 60
7453 11:33:18.528665 [CA 4] Center 36 (6~66) winsize 61
7454 11:33:18.531461 [CA 5] Center 35 (5~66) winsize 62
7455 11:33:18.531538
7456 11:33:18.535024 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7457 11:33:18.535100
7458 11:33:18.541260 [CATrainingPosCal] consider 1 rank data
7459 11:33:18.541336 u2DelayCellTimex100 = 275/100 ps
7460 11:33:18.548071 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7461 11:33:18.551069 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7462 11:33:18.554656 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7463 11:33:18.557979 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7464 11:33:18.560992 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7465 11:33:18.564475 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7466 11:33:18.564552
7467 11:33:18.567683 CA PerBit enable=1, Macro0, CA PI delay=35
7468 11:33:18.567760
7469 11:33:18.571226 [CBTSetCACLKResult] CA Dly = 35
7470 11:33:18.573944 CS Dly: 10 (0~41)
7471 11:33:18.577475 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7472 11:33:18.580509 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7473 11:33:18.580616 ==
7474 11:33:18.584112 Dram Type= 6, Freq= 0, CH_0, rank 1
7475 11:33:18.590827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7476 11:33:18.590905 ==
7477 11:33:18.593788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7478 11:33:18.600783 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7479 11:33:18.603609 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7480 11:33:18.609929 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7481 11:33:18.618930 [CA 0] Center 44 (14~75) winsize 62
7482 11:33:18.621941 [CA 1] Center 44 (14~74) winsize 61
7483 11:33:18.624835 [CA 2] Center 39 (10~69) winsize 60
7484 11:33:18.628193 [CA 3] Center 39 (10~68) winsize 59
7485 11:33:18.631872 [CA 4] Center 37 (7~67) winsize 61
7486 11:33:18.634915 [CA 5] Center 36 (7~66) winsize 60
7487 11:33:18.634992
7488 11:33:18.638397 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7489 11:33:18.638473
7490 11:33:18.644826 [CATrainingPosCal] consider 2 rank data
7491 11:33:18.644903 u2DelayCellTimex100 = 275/100 ps
7492 11:33:18.651250 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7493 11:33:18.654779 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7494 11:33:18.658048 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7495 11:33:18.661131 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7496 11:33:18.664271 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7497 11:33:18.667869 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7498 11:33:18.667982
7499 11:33:18.670782 CA PerBit enable=1, Macro0, CA PI delay=36
7500 11:33:18.670858
7501 11:33:18.674232 [CBTSetCACLKResult] CA Dly = 36
7502 11:33:18.677927 CS Dly: 11 (0~44)
7503 11:33:18.680912 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7504 11:33:18.684175 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7505 11:33:18.684252
7506 11:33:18.687555 ----->DramcWriteLeveling(PI) begin...
7507 11:33:18.690600 ==
7508 11:33:18.694100 Dram Type= 6, Freq= 0, CH_0, rank 0
7509 11:33:18.697160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7510 11:33:18.697236 ==
7511 11:33:18.701079 Write leveling (Byte 0): 33 => 33
7512 11:33:18.703945 Write leveling (Byte 1): 26 => 26
7513 11:33:18.707354 DramcWriteLeveling(PI) end<-----
7514 11:33:18.707430
7515 11:33:18.707489 ==
7516 11:33:18.710912 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 11:33:18.713868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 11:33:18.713945 ==
7519 11:33:18.717439 [Gating] SW mode calibration
7520 11:33:18.723954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7521 11:33:18.730456 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7522 11:33:18.734036 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7523 11:33:18.736829 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7524 11:33:18.743376 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7525 11:33:18.746631 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7526 11:33:18.750349 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7527 11:33:18.756806 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7528 11:33:18.759581 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7529 11:33:18.763223 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7530 11:33:18.769551 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7531 11:33:18.772931 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7532 11:33:18.776573 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7533 11:33:18.783091 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
7534 11:33:18.786019 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7535 11:33:18.789681 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7536 11:33:18.796223 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7537 11:33:18.799245 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7538 11:33:18.802649 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 11:33:18.809220 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7540 11:33:18.812757 1 6 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7541 11:33:18.815805 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7542 11:33:18.823174 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7543 11:33:18.825762 1 6 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7544 11:33:18.829306 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7545 11:33:18.835518 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7546 11:33:18.838835 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7547 11:33:18.842651 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7548 11:33:18.848870 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7549 11:33:18.852790 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7550 11:33:18.855264 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7551 11:33:18.862379 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7552 11:33:18.865958 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7553 11:33:18.868694 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7554 11:33:18.875500 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7555 11:33:18.878802 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7556 11:33:18.881700 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7557 11:33:18.888492 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7558 11:33:18.891903 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7559 11:33:18.895518 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7560 11:33:18.901654 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7561 11:33:18.904820 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7562 11:33:18.908143 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 11:33:18.914786 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7564 11:33:18.918303 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7565 11:33:18.921239 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7566 11:33:18.924873 Total UI for P1: 0, mck2ui 16
7567 11:33:18.927808 best dqsien dly found for B0: ( 1, 9, 6)
7568 11:33:18.934431 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7569 11:33:18.937901 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7570 11:33:18.941405 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 11:33:18.944383 Total UI for P1: 0, mck2ui 16
7572 11:33:18.947942 best dqsien dly found for B1: ( 1, 9, 20)
7573 11:33:18.951135 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
7574 11:33:18.954336 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7575 11:33:18.954404
7576 11:33:18.960842 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
7577 11:33:18.964070 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7578 11:33:18.967668 [Gating] SW calibration Done
7579 11:33:18.967745 ==
7580 11:33:18.971085 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 11:33:18.974419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 11:33:18.974530 ==
7583 11:33:18.974617 RX Vref Scan: 0
7584 11:33:18.974704
7585 11:33:18.977545 RX Vref 0 -> 0, step: 1
7586 11:33:18.977650
7587 11:33:18.980464 RX Delay 0 -> 252, step: 8
7588 11:33:18.983779 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7589 11:33:18.986988 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7590 11:33:18.993927 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7591 11:33:18.996877 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7592 11:33:19.000674 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7593 11:33:19.003436 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7594 11:33:19.007082 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7595 11:33:19.013445 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7596 11:33:19.016929 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7597 11:33:19.020091 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7598 11:33:19.023603 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7599 11:33:19.026577 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7600 11:33:19.033238 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7601 11:33:19.036929 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7602 11:33:19.040272 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7603 11:33:19.043148 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7604 11:33:19.043240 ==
7605 11:33:19.046317 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 11:33:19.053673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 11:33:19.053750 ==
7608 11:33:19.053811 DQS Delay:
7609 11:33:19.056099 DQS0 = 0, DQS1 = 0
7610 11:33:19.056175 DQM Delay:
7611 11:33:19.059427 DQM0 = 131, DQM1 = 126
7612 11:33:19.059527 DQ Delay:
7613 11:33:19.062634 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7614 11:33:19.066013 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7615 11:33:19.069481 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7616 11:33:19.072647 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7617 11:33:19.072723
7618 11:33:19.072782
7619 11:33:19.072838 ==
7620 11:33:19.076023 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 11:33:19.082711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 11:33:19.082788 ==
7623 11:33:19.082847
7624 11:33:19.082901
7625 11:33:19.082957 TX Vref Scan disable
7626 11:33:19.086235 == TX Byte 0 ==
7627 11:33:19.089872 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7628 11:33:19.096169 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7629 11:33:19.096246 == TX Byte 1 ==
7630 11:33:19.099679 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7631 11:33:19.105958 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7632 11:33:19.106035 ==
7633 11:33:19.109398 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 11:33:19.112382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 11:33:19.112459 ==
7636 11:33:19.126045
7637 11:33:19.129157 TX Vref early break, caculate TX vref
7638 11:33:19.132532 TX Vref=16, minBit 1, minWin=22, winSum=372
7639 11:33:19.135583 TX Vref=18, minBit 8, minWin=22, winSum=382
7640 11:33:19.139109 TX Vref=20, minBit 8, minWin=23, winSum=389
7641 11:33:19.142782 TX Vref=22, minBit 8, minWin=24, winSum=403
7642 11:33:19.146214 TX Vref=24, minBit 7, minWin=24, winSum=410
7643 11:33:19.152109 TX Vref=26, minBit 1, minWin=25, winSum=418
7644 11:33:19.155604 TX Vref=28, minBit 1, minWin=25, winSum=418
7645 11:33:19.158686 TX Vref=30, minBit 6, minWin=25, winSum=418
7646 11:33:19.162202 TX Vref=32, minBit 0, minWin=25, winSum=407
7647 11:33:19.165565 TX Vref=34, minBit 2, minWin=23, winSum=396
7648 11:33:19.172057 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 26
7649 11:33:19.172157
7650 11:33:19.175124 Final TX Range 0 Vref 26
7651 11:33:19.175203
7652 11:33:19.175262 ==
7653 11:33:19.178523 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 11:33:19.182056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 11:33:19.182135 ==
7656 11:33:19.182194
7657 11:33:19.182249
7658 11:33:19.185037 TX Vref Scan disable
7659 11:33:19.191563 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7660 11:33:19.191665 == TX Byte 0 ==
7661 11:33:19.195127 u2DelayCellOfst[0]=14 cells (4 PI)
7662 11:33:19.198142 u2DelayCellOfst[1]=17 cells (5 PI)
7663 11:33:19.201868 u2DelayCellOfst[2]=14 cells (4 PI)
7664 11:33:19.205323 u2DelayCellOfst[3]=14 cells (4 PI)
7665 11:33:19.208497 u2DelayCellOfst[4]=7 cells (2 PI)
7666 11:33:19.211342 u2DelayCellOfst[5]=0 cells (0 PI)
7667 11:33:19.214613 u2DelayCellOfst[6]=17 cells (5 PI)
7668 11:33:19.217991 u2DelayCellOfst[7]=17 cells (5 PI)
7669 11:33:19.221170 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7670 11:33:19.224446 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7671 11:33:19.228020 == TX Byte 1 ==
7672 11:33:19.230862 u2DelayCellOfst[8]=0 cells (0 PI)
7673 11:33:19.234139 u2DelayCellOfst[9]=0 cells (0 PI)
7674 11:33:19.237879 u2DelayCellOfst[10]=3 cells (1 PI)
7675 11:33:19.240753 u2DelayCellOfst[11]=0 cells (0 PI)
7676 11:33:19.240853 u2DelayCellOfst[12]=10 cells (3 PI)
7677 11:33:19.244241 u2DelayCellOfst[13]=10 cells (3 PI)
7678 11:33:19.247252 u2DelayCellOfst[14]=14 cells (4 PI)
7679 11:33:19.250660 u2DelayCellOfst[15]=10 cells (3 PI)
7680 11:33:19.257116 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7681 11:33:19.260784 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7682 11:33:19.264224 DramC Write-DBI on
7683 11:33:19.264316 ==
7684 11:33:19.267237 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 11:33:19.270198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 11:33:19.270283 ==
7687 11:33:19.270342
7688 11:33:19.270395
7689 11:33:19.273869 TX Vref Scan disable
7690 11:33:19.273932 == TX Byte 0 ==
7691 11:33:19.280133 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7692 11:33:19.280200 == TX Byte 1 ==
7693 11:33:19.287002 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7694 11:33:19.287110 DramC Write-DBI off
7695 11:33:19.287212
7696 11:33:19.287303 [DATLAT]
7697 11:33:19.290144 Freq=1600, CH0 RK0
7698 11:33:19.290230
7699 11:33:19.293257 DATLAT Default: 0xf
7700 11:33:19.293349 0, 0xFFFF, sum = 0
7701 11:33:19.296766 1, 0xFFFF, sum = 0
7702 11:33:19.296868 2, 0xFFFF, sum = 0
7703 11:33:19.299732 3, 0xFFFF, sum = 0
7704 11:33:19.299828 4, 0xFFFF, sum = 0
7705 11:33:19.303569 5, 0xFFFF, sum = 0
7706 11:33:19.303640 6, 0xFFFF, sum = 0
7707 11:33:19.306537 7, 0xFFFF, sum = 0
7708 11:33:19.306603 8, 0xFFFF, sum = 0
7709 11:33:19.309784 9, 0xFFFF, sum = 0
7710 11:33:19.309861 10, 0xFFFF, sum = 0
7711 11:33:19.312992 11, 0xFFFF, sum = 0
7712 11:33:19.313095 12, 0xFFFF, sum = 0
7713 11:33:19.316613 13, 0xFFFF, sum = 0
7714 11:33:19.316683 14, 0x0, sum = 1
7715 11:33:19.319770 15, 0x0, sum = 2
7716 11:33:19.319840 16, 0x0, sum = 3
7717 11:33:19.322903 17, 0x0, sum = 4
7718 11:33:19.322974 best_step = 15
7719 11:33:19.323032
7720 11:33:19.323101 ==
7721 11:33:19.326162 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 11:33:19.332684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 11:33:19.332762 ==
7724 11:33:19.332820 RX Vref Scan: 1
7725 11:33:19.332875
7726 11:33:19.336156 Set Vref Range= 24 -> 127
7727 11:33:19.336249
7728 11:33:19.339471 RX Vref 24 -> 127, step: 1
7729 11:33:19.339579
7730 11:33:19.342263 RX Delay 11 -> 252, step: 4
7731 11:33:19.342361
7732 11:33:19.345679 Set Vref, RX VrefLevel [Byte0]: 24
7733 11:33:19.349083 [Byte1]: 24
7734 11:33:19.349173
7735 11:33:19.352839 Set Vref, RX VrefLevel [Byte0]: 25
7736 11:33:19.355457 [Byte1]: 25
7737 11:33:19.355549
7738 11:33:19.359114 Set Vref, RX VrefLevel [Byte0]: 26
7739 11:33:19.361995 [Byte1]: 26
7740 11:33:19.365812
7741 11:33:19.365880 Set Vref, RX VrefLevel [Byte0]: 27
7742 11:33:19.369571 [Byte1]: 27
7743 11:33:19.373457
7744 11:33:19.373542 Set Vref, RX VrefLevel [Byte0]: 28
7745 11:33:19.376476 [Byte1]: 28
7746 11:33:19.381131
7747 11:33:19.381207 Set Vref, RX VrefLevel [Byte0]: 29
7748 11:33:19.384156 [Byte1]: 29
7749 11:33:19.388657
7750 11:33:19.388751 Set Vref, RX VrefLevel [Byte0]: 30
7751 11:33:19.391746 [Byte1]: 30
7752 11:33:19.396042
7753 11:33:19.396121 Set Vref, RX VrefLevel [Byte0]: 31
7754 11:33:19.399239 [Byte1]: 31
7755 11:33:19.403857
7756 11:33:19.403938 Set Vref, RX VrefLevel [Byte0]: 32
7757 11:33:19.407256 [Byte1]: 32
7758 11:33:19.411317
7759 11:33:19.411418 Set Vref, RX VrefLevel [Byte0]: 33
7760 11:33:19.414798 [Byte1]: 33
7761 11:33:19.418980
7762 11:33:19.419084 Set Vref, RX VrefLevel [Byte0]: 34
7763 11:33:19.422506 [Byte1]: 34
7764 11:33:19.426394
7765 11:33:19.426465 Set Vref, RX VrefLevel [Byte0]: 35
7766 11:33:19.429688 [Byte1]: 35
7767 11:33:19.434009
7768 11:33:19.434079 Set Vref, RX VrefLevel [Byte0]: 36
7769 11:33:19.437532 [Byte1]: 36
7770 11:33:19.441651
7771 11:33:19.441751 Set Vref, RX VrefLevel [Byte0]: 37
7772 11:33:19.445299 [Byte1]: 37
7773 11:33:19.449449
7774 11:33:19.449553 Set Vref, RX VrefLevel [Byte0]: 38
7775 11:33:19.453185 [Byte1]: 38
7776 11:33:19.456828
7777 11:33:19.456925 Set Vref, RX VrefLevel [Byte0]: 39
7778 11:33:19.460086 [Byte1]: 39
7779 11:33:19.464421
7780 11:33:19.464521 Set Vref, RX VrefLevel [Byte0]: 40
7781 11:33:19.467650 [Byte1]: 40
7782 11:33:19.472095
7783 11:33:19.472197 Set Vref, RX VrefLevel [Byte0]: 41
7784 11:33:19.475451 [Byte1]: 41
7785 11:33:19.479803
7786 11:33:19.479906 Set Vref, RX VrefLevel [Byte0]: 42
7787 11:33:19.483366 [Byte1]: 42
7788 11:33:19.487504
7789 11:33:19.487598 Set Vref, RX VrefLevel [Byte0]: 43
7790 11:33:19.490895 [Byte1]: 43
7791 11:33:19.494876
7792 11:33:19.494970 Set Vref, RX VrefLevel [Byte0]: 44
7793 11:33:19.498181 [Byte1]: 44
7794 11:33:19.502360
7795 11:33:19.502456 Set Vref, RX VrefLevel [Byte0]: 45
7796 11:33:19.506452 [Byte1]: 45
7797 11:33:19.510491
7798 11:33:19.510562 Set Vref, RX VrefLevel [Byte0]: 46
7799 11:33:19.513785 [Byte1]: 46
7800 11:33:19.517891
7801 11:33:19.517983 Set Vref, RX VrefLevel [Byte0]: 47
7802 11:33:19.521150 [Byte1]: 47
7803 11:33:19.525710
7804 11:33:19.525802 Set Vref, RX VrefLevel [Byte0]: 48
7805 11:33:19.528915 [Byte1]: 48
7806 11:33:19.533151
7807 11:33:19.533218 Set Vref, RX VrefLevel [Byte0]: 49
7808 11:33:19.536286 [Byte1]: 49
7809 11:33:19.540439
7810 11:33:19.540540 Set Vref, RX VrefLevel [Byte0]: 50
7811 11:33:19.543962 [Byte1]: 50
7812 11:33:19.548515
7813 11:33:19.548613 Set Vref, RX VrefLevel [Byte0]: 51
7814 11:33:19.552025 [Byte1]: 51
7815 11:33:19.556399
7816 11:33:19.556497 Set Vref, RX VrefLevel [Byte0]: 52
7817 11:33:19.559100 [Byte1]: 52
7818 11:33:19.563534
7819 11:33:19.563622 Set Vref, RX VrefLevel [Byte0]: 53
7820 11:33:19.566806 [Byte1]: 53
7821 11:33:19.571418
7822 11:33:19.571512 Set Vref, RX VrefLevel [Byte0]: 54
7823 11:33:19.574545 [Byte1]: 54
7824 11:33:19.579161
7825 11:33:19.579255 Set Vref, RX VrefLevel [Byte0]: 55
7826 11:33:19.582028 [Byte1]: 55
7827 11:33:19.586134
7828 11:33:19.586203 Set Vref, RX VrefLevel [Byte0]: 56
7829 11:33:19.589896 [Byte1]: 56
7830 11:33:19.594312
7831 11:33:19.594379 Set Vref, RX VrefLevel [Byte0]: 57
7832 11:33:19.597204 [Byte1]: 57
7833 11:33:19.601338
7834 11:33:19.601417 Set Vref, RX VrefLevel [Byte0]: 58
7835 11:33:19.604896 [Byte1]: 58
7836 11:33:19.609183
7837 11:33:19.609251 Set Vref, RX VrefLevel [Byte0]: 59
7838 11:33:19.612479 [Byte1]: 59
7839 11:33:19.616567
7840 11:33:19.616664 Set Vref, RX VrefLevel [Byte0]: 60
7841 11:33:19.620143 [Byte1]: 60
7842 11:33:19.625096
7843 11:33:19.625200 Set Vref, RX VrefLevel [Byte0]: 61
7844 11:33:19.627909 [Byte1]: 61
7845 11:33:19.632254
7846 11:33:19.632345 Set Vref, RX VrefLevel [Byte0]: 62
7847 11:33:19.635136 [Byte1]: 62
7848 11:33:19.639700
7849 11:33:19.639792 Set Vref, RX VrefLevel [Byte0]: 63
7850 11:33:19.643284 [Byte1]: 63
7851 11:33:19.647176
7852 11:33:19.647248 Set Vref, RX VrefLevel [Byte0]: 64
7853 11:33:19.650849 [Byte1]: 64
7854 11:33:19.655021
7855 11:33:19.655100 Set Vref, RX VrefLevel [Byte0]: 65
7856 11:33:19.658357 [Byte1]: 65
7857 11:33:19.662611
7858 11:33:19.662702 Set Vref, RX VrefLevel [Byte0]: 66
7859 11:33:19.666115 [Byte1]: 66
7860 11:33:19.670404
7861 11:33:19.670476 Set Vref, RX VrefLevel [Byte0]: 67
7862 11:33:19.673652 [Byte1]: 67
7863 11:33:19.677946
7864 11:33:19.678017 Set Vref, RX VrefLevel [Byte0]: 68
7865 11:33:19.684155 [Byte1]: 68
7866 11:33:19.684242
7867 11:33:19.687577 Set Vref, RX VrefLevel [Byte0]: 69
7868 11:33:19.691136 [Byte1]: 69
7869 11:33:19.691207
7870 11:33:19.693954 Set Vref, RX VrefLevel [Byte0]: 70
7871 11:33:19.697472 [Byte1]: 70
7872 11:33:19.700839
7873 11:33:19.700910 Set Vref, RX VrefLevel [Byte0]: 71
7874 11:33:19.704080 [Byte1]: 71
7875 11:33:19.708305
7876 11:33:19.708376 Set Vref, RX VrefLevel [Byte0]: 72
7877 11:33:19.711420 [Byte1]: 72
7878 11:33:19.716249
7879 11:33:19.716323 Set Vref, RX VrefLevel [Byte0]: 73
7880 11:33:19.719063 [Byte1]: 73
7881 11:33:19.723570
7882 11:33:19.723663 Set Vref, RX VrefLevel [Byte0]: 74
7883 11:33:19.726542 [Byte1]: 74
7884 11:33:19.731183
7885 11:33:19.731254 Set Vref, RX VrefLevel [Byte0]: 75
7886 11:33:19.734011 [Byte1]: 75
7887 11:33:19.738794
7888 11:33:19.738891 Set Vref, RX VrefLevel [Byte0]: 76
7889 11:33:19.741954 [Byte1]: 76
7890 11:33:19.746391
7891 11:33:19.746491 Set Vref, RX VrefLevel [Byte0]: 77
7892 11:33:19.749534 [Byte1]: 77
7893 11:33:19.754189
7894 11:33:19.754278 Set Vref, RX VrefLevel [Byte0]: 78
7895 11:33:19.756902 [Byte1]: 78
7896 11:33:19.761183
7897 11:33:19.761274 Final RX Vref Byte 0 = 56 to rank0
7898 11:33:19.764772 Final RX Vref Byte 1 = 56 to rank0
7899 11:33:19.768217 Final RX Vref Byte 0 = 56 to rank1
7900 11:33:19.771180 Final RX Vref Byte 1 = 56 to rank1==
7901 11:33:19.774659 Dram Type= 6, Freq= 0, CH_0, rank 0
7902 11:33:19.781609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7903 11:33:19.781707 ==
7904 11:33:19.781767 DQS Delay:
7905 11:33:19.784422 DQS0 = 0, DQS1 = 0
7906 11:33:19.784514 DQM Delay:
7907 11:33:19.784596 DQM0 = 128, DQM1 = 124
7908 11:33:19.788020 DQ Delay:
7909 11:33:19.790980 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7910 11:33:19.794384 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7911 11:33:19.797612 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7912 11:33:19.801173 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7913 11:33:19.801241
7914 11:33:19.801300
7915 11:33:19.801358
7916 11:33:19.804200 [DramC_TX_OE_Calibration] TA2
7917 11:33:19.807675 Original DQ_B0 (3 6) =30, OEN = 27
7918 11:33:19.810848 Original DQ_B1 (3 6) =30, OEN = 27
7919 11:33:19.814138 24, 0x0, End_B0=24 End_B1=24
7920 11:33:19.817658 25, 0x0, End_B0=25 End_B1=25
7921 11:33:19.817752 26, 0x0, End_B0=26 End_B1=26
7922 11:33:19.820685 27, 0x0, End_B0=27 End_B1=27
7923 11:33:19.824163 28, 0x0, End_B0=28 End_B1=28
7924 11:33:19.827673 29, 0x0, End_B0=29 End_B1=29
7925 11:33:19.827770 30, 0x0, End_B0=30 End_B1=30
7926 11:33:19.830479 31, 0x4141, End_B0=30 End_B1=30
7927 11:33:19.834106 Byte0 end_step=30 best_step=27
7928 11:33:19.837268 Byte1 end_step=30 best_step=27
7929 11:33:19.840302 Byte0 TX OE(2T, 0.5T) = (3, 3)
7930 11:33:19.843955 Byte1 TX OE(2T, 0.5T) = (3, 3)
7931 11:33:19.844049
7932 11:33:19.844138
7933 11:33:19.850314 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7934 11:33:19.853860 CH0 RK0: MR19=303, MR18=1714
7935 11:33:19.860304 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7936 11:33:19.860406
7937 11:33:19.863606 ----->DramcWriteLeveling(PI) begin...
7938 11:33:19.863707 ==
7939 11:33:19.866844 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 11:33:19.870063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 11:33:19.870158 ==
7942 11:33:19.873750 Write leveling (Byte 0): 34 => 34
7943 11:33:19.876799 Write leveling (Byte 1): 29 => 29
7944 11:33:19.880243 DramcWriteLeveling(PI) end<-----
7945 11:33:19.880320
7946 11:33:19.880388 ==
7947 11:33:19.883575 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 11:33:19.886514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 11:33:19.890034 ==
7950 11:33:19.890102 [Gating] SW mode calibration
7951 11:33:19.899590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7952 11:33:19.903365 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7953 11:33:19.906170 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7954 11:33:19.913057 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7955 11:33:19.916386 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7956 11:33:19.919349 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7957 11:33:19.926304 1 4 16 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7958 11:33:19.929654 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7959 11:33:19.932765 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7960 11:33:19.939488 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 11:33:19.942571 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7962 11:33:19.949258 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7963 11:33:19.952792 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7964 11:33:19.955737 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7965 11:33:19.962362 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7966 11:33:19.965795 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7967 11:33:19.968796 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 11:33:19.975394 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 11:33:19.978394 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 11:33:19.981764 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7971 11:33:19.988214 1 6 8 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
7972 11:33:19.992012 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7973 11:33:19.994871 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7974 11:33:20.001714 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7975 11:33:20.005084 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 11:33:20.008406 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 11:33:20.015086 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 11:33:20.018215 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 11:33:20.021829 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7980 11:33:20.027928 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7981 11:33:20.031493 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7982 11:33:20.034546 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 11:33:20.041022 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 11:33:20.044350 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 11:33:20.047977 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 11:33:20.054139 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 11:33:20.057680 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 11:33:20.061103 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 11:33:20.067573 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 11:33:20.071389 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 11:33:20.074047 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 11:33:20.080614 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 11:33:20.084349 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 11:33:20.087464 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 11:33:20.094048 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7996 11:33:20.097727 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7997 11:33:20.100350 Total UI for P1: 0, mck2ui 16
7998 11:33:20.103953 best dqsien dly found for B0: ( 1, 9, 8)
7999 11:33:20.106892 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8000 11:33:20.113335 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8001 11:33:20.116660 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 11:33:20.120446 Total UI for P1: 0, mck2ui 16
8003 11:33:20.123473 best dqsien dly found for B1: ( 1, 9, 20)
8004 11:33:20.126759 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8005 11:33:20.130365 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8006 11:33:20.130437
8007 11:33:20.133301 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8008 11:33:20.136983 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8009 11:33:20.140006 [Gating] SW calibration Done
8010 11:33:20.140076 ==
8011 11:33:20.143402 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 11:33:20.146510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 11:33:20.149988 ==
8014 11:33:20.150059 RX Vref Scan: 0
8015 11:33:20.150118
8016 11:33:20.153444 RX Vref 0 -> 0, step: 1
8017 11:33:20.153509
8018 11:33:20.156685 RX Delay 0 -> 252, step: 8
8019 11:33:20.159709 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8020 11:33:20.162816 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8021 11:33:20.166368 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8022 11:33:20.169636 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8023 11:33:20.176331 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8024 11:33:20.179426 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8025 11:33:20.183023 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8026 11:33:20.186097 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8027 11:33:20.189493 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8028 11:33:20.196119 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8029 11:33:20.198956 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8030 11:33:20.202570 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8031 11:33:20.205822 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8032 11:33:20.212552 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8033 11:33:20.215489 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8034 11:33:20.218869 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8035 11:33:20.218943 ==
8036 11:33:20.221967 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 11:33:20.225596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 11:33:20.225670 ==
8039 11:33:20.228834 DQS Delay:
8040 11:33:20.228901 DQS0 = 0, DQS1 = 0
8041 11:33:20.231836 DQM Delay:
8042 11:33:20.231910 DQM0 = 132, DQM1 = 124
8043 11:33:20.235423 DQ Delay:
8044 11:33:20.238341 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8045 11:33:20.242004 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8046 11:33:20.245387 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8047 11:33:20.248645 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8048 11:33:20.248715
8049 11:33:20.248774
8050 11:33:20.248829 ==
8051 11:33:20.251862 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 11:33:20.254845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 11:33:20.254938 ==
8054 11:33:20.255034
8055 11:33:20.258189
8056 11:33:20.258284 TX Vref Scan disable
8057 11:33:20.261765 == TX Byte 0 ==
8058 11:33:20.264751 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8059 11:33:20.268333 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8060 11:33:20.271453 == TX Byte 1 ==
8061 11:33:20.274932 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8062 11:33:20.278074 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8063 11:33:20.278142 ==
8064 11:33:20.281389 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:33:20.287577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:33:20.287656 ==
8067 11:33:20.300041
8068 11:33:20.303250 TX Vref early break, caculate TX vref
8069 11:33:20.306620 TX Vref=16, minBit 9, minWin=22, winSum=382
8070 11:33:20.310294 TX Vref=18, minBit 6, minWin=23, winSum=388
8071 11:33:20.313290 TX Vref=20, minBit 2, minWin=24, winSum=396
8072 11:33:20.316567 TX Vref=22, minBit 10, minWin=24, winSum=405
8073 11:33:20.319786 TX Vref=24, minBit 1, minWin=25, winSum=411
8074 11:33:20.326556 TX Vref=26, minBit 4, minWin=25, winSum=423
8075 11:33:20.329768 TX Vref=28, minBit 4, minWin=25, winSum=424
8076 11:33:20.332958 TX Vref=30, minBit 0, minWin=25, winSum=412
8077 11:33:20.336016 TX Vref=32, minBit 3, minWin=24, winSum=403
8078 11:33:20.339374 TX Vref=34, minBit 1, minWin=24, winSum=401
8079 11:33:20.346009 [TxChooseVref] Worse bit 4, Min win 25, Win sum 424, Final Vref 28
8080 11:33:20.346121
8081 11:33:20.349298 Final TX Range 0 Vref 28
8082 11:33:20.349368
8083 11:33:20.349427 ==
8084 11:33:20.352642 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 11:33:20.355989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 11:33:20.356082 ==
8087 11:33:20.356175
8088 11:33:20.356233
8089 11:33:20.359368 TX Vref Scan disable
8090 11:33:20.365577 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8091 11:33:20.365652 == TX Byte 0 ==
8092 11:33:20.369263 u2DelayCellOfst[0]=10 cells (3 PI)
8093 11:33:20.372389 u2DelayCellOfst[1]=14 cells (4 PI)
8094 11:33:20.375620 u2DelayCellOfst[2]=7 cells (2 PI)
8095 11:33:20.379054 u2DelayCellOfst[3]=7 cells (2 PI)
8096 11:33:20.382825 u2DelayCellOfst[4]=7 cells (2 PI)
8097 11:33:20.385522 u2DelayCellOfst[5]=0 cells (0 PI)
8098 11:33:20.389280 u2DelayCellOfst[6]=14 cells (4 PI)
8099 11:33:20.392566 u2DelayCellOfst[7]=14 cells (4 PI)
8100 11:33:20.395558 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8101 11:33:20.398565 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8102 11:33:20.402150 == TX Byte 1 ==
8103 11:33:20.405385 u2DelayCellOfst[8]=0 cells (0 PI)
8104 11:33:20.408695 u2DelayCellOfst[9]=0 cells (0 PI)
8105 11:33:20.412062 u2DelayCellOfst[10]=3 cells (1 PI)
8106 11:33:20.415358 u2DelayCellOfst[11]=3 cells (1 PI)
8107 11:33:20.415431 u2DelayCellOfst[12]=10 cells (3 PI)
8108 11:33:20.418263 u2DelayCellOfst[13]=10 cells (3 PI)
8109 11:33:20.421893 u2DelayCellOfst[14]=14 cells (4 PI)
8110 11:33:20.424961 u2DelayCellOfst[15]=10 cells (3 PI)
8111 11:33:20.431442 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8112 11:33:20.435219 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8113 11:33:20.435286 DramC Write-DBI on
8114 11:33:20.438153 ==
8115 11:33:20.442173 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 11:33:20.444780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 11:33:20.444869 ==
8118 11:33:20.444950
8119 11:33:20.445042
8120 11:33:20.448194 TX Vref Scan disable
8121 11:33:20.448258 == TX Byte 0 ==
8122 11:33:20.454836 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8123 11:33:20.454910 == TX Byte 1 ==
8124 11:33:20.457632 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8125 11:33:20.461114 DramC Write-DBI off
8126 11:33:20.461243
8127 11:33:20.461332 [DATLAT]
8128 11:33:20.464380 Freq=1600, CH0 RK1
8129 11:33:20.464473
8130 11:33:20.464527 DATLAT Default: 0xf
8131 11:33:20.467738 0, 0xFFFF, sum = 0
8132 11:33:20.467838 1, 0xFFFF, sum = 0
8133 11:33:20.470753 2, 0xFFFF, sum = 0
8134 11:33:20.474536 3, 0xFFFF, sum = 0
8135 11:33:20.474615 4, 0xFFFF, sum = 0
8136 11:33:20.477926 5, 0xFFFF, sum = 0
8137 11:33:20.478011 6, 0xFFFF, sum = 0
8138 11:33:20.481073 7, 0xFFFF, sum = 0
8139 11:33:20.481185 8, 0xFFFF, sum = 0
8140 11:33:20.484319 9, 0xFFFF, sum = 0
8141 11:33:20.484391 10, 0xFFFF, sum = 0
8142 11:33:20.487471 11, 0xFFFF, sum = 0
8143 11:33:20.487539 12, 0xFFFF, sum = 0
8144 11:33:20.491041 13, 0xFFFF, sum = 0
8145 11:33:20.491109 14, 0x0, sum = 1
8146 11:33:20.493896 15, 0x0, sum = 2
8147 11:33:20.493977 16, 0x0, sum = 3
8148 11:33:20.497240 17, 0x0, sum = 4
8149 11:33:20.497313 best_step = 15
8150 11:33:20.497370
8151 11:33:20.497442 ==
8152 11:33:20.500691 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 11:33:20.507389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 11:33:20.507464 ==
8155 11:33:20.507523 RX Vref Scan: 0
8156 11:33:20.507597
8157 11:33:20.510434 RX Vref 0 -> 0, step: 1
8158 11:33:20.510530
8159 11:33:20.514100 RX Delay 11 -> 252, step: 4
8160 11:33:20.517159 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8161 11:33:20.520534 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8162 11:33:20.523662 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8163 11:33:20.530169 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8164 11:33:20.533322 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8165 11:33:20.536874 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8166 11:33:20.539868 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8167 11:33:20.546886 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8168 11:33:20.549674 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8169 11:33:20.552965 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8170 11:33:20.556418 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8171 11:33:20.559536 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8172 11:33:20.566264 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8173 11:33:20.569518 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8174 11:33:20.572821 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8175 11:33:20.576071 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8176 11:33:20.576144 ==
8177 11:33:20.579775 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 11:33:20.586354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 11:33:20.586430 ==
8180 11:33:20.586492 DQS Delay:
8181 11:33:20.589678 DQS0 = 0, DQS1 = 0
8182 11:33:20.589744 DQM Delay:
8183 11:33:20.589799 DQM0 = 129, DQM1 = 123
8184 11:33:20.592926 DQ Delay:
8185 11:33:20.595935 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8186 11:33:20.599233 DQ4 =132, DQ5 =120, DQ6 =140, DQ7 =134
8187 11:33:20.602314 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8188 11:33:20.606173 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8189 11:33:20.606235
8190 11:33:20.606289
8191 11:33:20.606364
8192 11:33:20.609556 [DramC_TX_OE_Calibration] TA2
8193 11:33:20.612507 Original DQ_B0 (3 6) =30, OEN = 27
8194 11:33:20.616032 Original DQ_B1 (3 6) =30, OEN = 27
8195 11:33:20.618920 24, 0x0, End_B0=24 End_B1=24
8196 11:33:20.622418 25, 0x0, End_B0=25 End_B1=25
8197 11:33:20.622491 26, 0x0, End_B0=26 End_B1=26
8198 11:33:20.625413 27, 0x0, End_B0=27 End_B1=27
8199 11:33:20.628975 28, 0x0, End_B0=28 End_B1=28
8200 11:33:20.632005 29, 0x0, End_B0=29 End_B1=29
8201 11:33:20.635530 30, 0x0, End_B0=30 End_B1=30
8202 11:33:20.635601 31, 0x4141, End_B0=30 End_B1=30
8203 11:33:20.638589 Byte0 end_step=30 best_step=27
8204 11:33:20.642142 Byte1 end_step=30 best_step=27
8205 11:33:20.645733 Byte0 TX OE(2T, 0.5T) = (3, 3)
8206 11:33:20.648598 Byte1 TX OE(2T, 0.5T) = (3, 3)
8207 11:33:20.648669
8208 11:33:20.648725
8209 11:33:20.655076 [DQSOSCAuto] RK1, (LSB)MR18= 0x1715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8210 11:33:20.658702 CH0 RK1: MR19=303, MR18=1715
8211 11:33:20.664832 CH0_RK1: MR19=0x303, MR18=0x1715, DQSOSC=398, MR23=63, INC=23, DEC=15
8212 11:33:20.668776 [RxdqsGatingPostProcess] freq 1600
8213 11:33:20.674881 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8214 11:33:20.674955 best DQS0 dly(2T, 0.5T) = (1, 1)
8215 11:33:20.678525 best DQS1 dly(2T, 0.5T) = (1, 1)
8216 11:33:20.681495 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8217 11:33:20.684735 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8218 11:33:20.688646 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 11:33:20.691254 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 11:33:20.694963 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 11:33:20.697867 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 11:33:20.701363 Pre-setting of DQS Precalculation
8223 11:33:20.704449 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8224 11:33:20.708071 ==
8225 11:33:20.711069 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 11:33:20.714705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 11:33:20.714773 ==
8228 11:33:20.717889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8229 11:33:20.724331 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8230 11:33:20.727849 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8231 11:33:20.734173 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8232 11:33:20.742292 [CA 0] Center 42 (13~72) winsize 60
8233 11:33:20.745883 [CA 1] Center 42 (12~73) winsize 62
8234 11:33:20.749539 [CA 2] Center 39 (9~69) winsize 61
8235 11:33:20.752196 [CA 3] Center 38 (8~68) winsize 61
8236 11:33:20.755762 [CA 4] Center 38 (8~69) winsize 62
8237 11:33:20.758636 [CA 5] Center 37 (7~67) winsize 61
8238 11:33:20.758703
8239 11:33:20.762699 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8240 11:33:20.762765
8241 11:33:20.769170 [CATrainingPosCal] consider 1 rank data
8242 11:33:20.769240 u2DelayCellTimex100 = 275/100 ps
8243 11:33:20.775952 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8244 11:33:20.778482 CA1 delay=42 (12~73),Diff = 5 PI (17 cell)
8245 11:33:20.782007 CA2 delay=39 (9~69),Diff = 2 PI (7 cell)
8246 11:33:20.785756 CA3 delay=38 (8~68),Diff = 1 PI (3 cell)
8247 11:33:20.788514 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8248 11:33:20.792216 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8249 11:33:20.792288
8250 11:33:20.795192 CA PerBit enable=1, Macro0, CA PI delay=37
8251 11:33:20.795263
8252 11:33:20.798580 [CBTSetCACLKResult] CA Dly = 37
8253 11:33:20.802120 CS Dly: 8 (0~39)
8254 11:33:20.804926 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8255 11:33:20.808553 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8256 11:33:20.808638 ==
8257 11:33:20.811986 Dram Type= 6, Freq= 0, CH_1, rank 1
8258 11:33:20.818751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 11:33:20.818829 ==
8260 11:33:20.821468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8261 11:33:20.828027 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8262 11:33:20.831548 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8263 11:33:20.838352 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8264 11:33:20.845761 [CA 0] Center 42 (13~72) winsize 60
8265 11:33:20.849510 [CA 1] Center 43 (14~72) winsize 59
8266 11:33:20.852623 [CA 2] Center 38 (8~68) winsize 61
8267 11:33:20.855431 [CA 3] Center 37 (7~67) winsize 61
8268 11:33:20.859025 [CA 4] Center 37 (8~67) winsize 60
8269 11:33:20.862263 [CA 5] Center 37 (8~67) winsize 60
8270 11:33:20.862355
8271 11:33:20.865800 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8272 11:33:20.865895
8273 11:33:20.868895 [CATrainingPosCal] consider 2 rank data
8274 11:33:20.872056 u2DelayCellTimex100 = 275/100 ps
8275 11:33:20.878841 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8276 11:33:20.881835 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8277 11:33:20.885503 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8278 11:33:20.888635 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8279 11:33:20.891554 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8280 11:33:20.895064 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8281 11:33:20.895157
8282 11:33:20.898169 CA PerBit enable=1, Macro0, CA PI delay=37
8283 11:33:20.898264
8284 11:33:20.901747 [CBTSetCACLKResult] CA Dly = 37
8285 11:33:20.905054 CS Dly: 10 (0~43)
8286 11:33:20.908232 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8287 11:33:20.911560 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8288 11:33:20.911659
8289 11:33:20.914985 ----->DramcWriteLeveling(PI) begin...
8290 11:33:20.915082 ==
8291 11:33:20.917839 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 11:33:20.925043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 11:33:20.925163 ==
8294 11:33:20.927913 Write leveling (Byte 0): 25 => 25
8295 11:33:20.931680 Write leveling (Byte 1): 26 => 26
8296 11:33:20.931778 DramcWriteLeveling(PI) end<-----
8297 11:33:20.935004
8298 11:33:20.935106 ==
8299 11:33:20.937961 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 11:33:20.941521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 11:33:20.941624 ==
8302 11:33:20.944924 [Gating] SW mode calibration
8303 11:33:20.951029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8304 11:33:20.954756 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8305 11:33:20.961215 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 11:33:20.964235 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 11:33:20.967668 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 11:33:20.974045 1 4 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8309 11:33:20.977516 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 11:33:20.981050 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 11:33:20.987336 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 11:33:20.991013 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 11:33:20.993864 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 11:33:21.000788 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 11:33:21.004148 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8316 11:33:21.006902 1 5 12 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
8317 11:33:21.013456 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 11:33:21.016819 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 11:33:21.023608 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 11:33:21.027018 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 11:33:21.029885 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 11:33:21.036634 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 11:33:21.040206 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 11:33:21.043241 1 6 12 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
8325 11:33:21.050261 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 11:33:21.053564 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 11:33:21.056179 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 11:33:21.063269 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 11:33:21.066451 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 11:33:21.069303 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 11:33:21.076255 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8332 11:33:21.079392 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8333 11:33:21.082867 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8334 11:33:21.089086 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 11:33:21.092607 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 11:33:21.096058 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 11:33:21.102637 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 11:33:21.106125 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 11:33:21.109061 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 11:33:21.115320 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 11:33:21.119159 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 11:33:21.122699 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 11:33:21.128652 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 11:33:21.132228 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 11:33:21.135537 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 11:33:21.142221 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 11:33:21.144963 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8348 11:33:21.149023 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8349 11:33:21.152001 Total UI for P1: 0, mck2ui 16
8350 11:33:21.154962 best dqsien dly found for B0: ( 1, 9, 8)
8351 11:33:21.161818 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8352 11:33:21.165120 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 11:33:21.168232 Total UI for P1: 0, mck2ui 16
8354 11:33:21.171451 best dqsien dly found for B1: ( 1, 9, 12)
8355 11:33:21.175044 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8356 11:33:21.178801 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8357 11:33:21.178925
8358 11:33:21.181421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8359 11:33:21.184928 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8360 11:33:21.188103 [Gating] SW calibration Done
8361 11:33:21.188228 ==
8362 11:33:21.191773 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 11:33:21.194754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 11:33:21.197948 ==
8365 11:33:21.198023 RX Vref Scan: 0
8366 11:33:21.198084
8367 11:33:21.201203 RX Vref 0 -> 0, step: 1
8368 11:33:21.201272
8369 11:33:21.201327 RX Delay 0 -> 252, step: 8
8370 11:33:21.207737 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8371 11:33:21.211575 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8372 11:33:21.214755 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8373 11:33:21.217737 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8374 11:33:21.224242 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8375 11:33:21.227986 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8376 11:33:21.231230 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8377 11:33:21.234800 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8378 11:33:21.237955 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8379 11:33:21.243946 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8380 11:33:21.247244 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8381 11:33:21.250580 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8382 11:33:21.253695 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8383 11:33:21.256994 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8384 11:33:21.263975 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8385 11:33:21.267008 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8386 11:33:21.267102 ==
8387 11:33:21.270595 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 11:33:21.273515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 11:33:21.273608 ==
8390 11:33:21.277064 DQS Delay:
8391 11:33:21.277166 DQS0 = 0, DQS1 = 0
8392 11:33:21.280334 DQM Delay:
8393 11:33:21.280434 DQM0 = 135, DQM1 = 130
8394 11:33:21.280518 DQ Delay:
8395 11:33:21.287005 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8396 11:33:21.290111 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8397 11:33:21.293297 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8398 11:33:21.296851 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8399 11:33:21.296931
8400 11:33:21.296989
8401 11:33:21.297043 ==
8402 11:33:21.299742 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 11:33:21.303413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 11:33:21.303482 ==
8405 11:33:21.303538
8406 11:33:21.303591
8407 11:33:21.306775 TX Vref Scan disable
8408 11:33:21.309782 == TX Byte 0 ==
8409 11:33:21.313566 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8410 11:33:21.316204 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8411 11:33:21.319721 == TX Byte 1 ==
8412 11:33:21.322736 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8413 11:33:21.326302 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8414 11:33:21.326377 ==
8415 11:33:21.329722 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 11:33:21.335986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 11:33:21.336065 ==
8418 11:33:21.348717
8419 11:33:21.351863 TX Vref early break, caculate TX vref
8420 11:33:21.355205 TX Vref=16, minBit 8, minWin=21, winSum=365
8421 11:33:21.358594 TX Vref=18, minBit 8, minWin=22, winSum=375
8422 11:33:21.361436 TX Vref=20, minBit 9, minWin=22, winSum=386
8423 11:33:21.364965 TX Vref=22, minBit 8, minWin=23, winSum=399
8424 11:33:21.368055 TX Vref=24, minBit 9, minWin=24, winSum=408
8425 11:33:21.374718 TX Vref=26, minBit 3, minWin=25, winSum=413
8426 11:33:21.378210 TX Vref=28, minBit 15, minWin=25, winSum=417
8427 11:33:21.381369 TX Vref=30, minBit 9, minWin=24, winSum=409
8428 11:33:21.384441 TX Vref=32, minBit 0, minWin=24, winSum=406
8429 11:33:21.388214 TX Vref=34, minBit 0, minWin=24, winSum=397
8430 11:33:21.394405 TX Vref=36, minBit 0, minWin=23, winSum=387
8431 11:33:21.397854 [TxChooseVref] Worse bit 15, Min win 25, Win sum 417, Final Vref 28
8432 11:33:21.397937
8433 11:33:21.400941 Final TX Range 0 Vref 28
8434 11:33:21.401043
8435 11:33:21.401133 ==
8436 11:33:21.404672 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 11:33:21.407636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 11:33:21.411163 ==
8439 11:33:21.411237
8440 11:33:21.411300
8441 11:33:21.411355 TX Vref Scan disable
8442 11:33:21.417869 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8443 11:33:21.417949 == TX Byte 0 ==
8444 11:33:21.421280 u2DelayCellOfst[0]=14 cells (4 PI)
8445 11:33:21.424622 u2DelayCellOfst[1]=10 cells (3 PI)
8446 11:33:21.427472 u2DelayCellOfst[2]=0 cells (0 PI)
8447 11:33:21.431000 u2DelayCellOfst[3]=7 cells (2 PI)
8448 11:33:21.434951 u2DelayCellOfst[4]=10 cells (3 PI)
8449 11:33:21.437554 u2DelayCellOfst[5]=17 cells (5 PI)
8450 11:33:21.440876 u2DelayCellOfst[6]=14 cells (4 PI)
8451 11:33:21.444271 u2DelayCellOfst[7]=7 cells (2 PI)
8452 11:33:21.447429 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8453 11:33:21.450762 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8454 11:33:21.454074 == TX Byte 1 ==
8455 11:33:21.457725 u2DelayCellOfst[8]=0 cells (0 PI)
8456 11:33:21.460640 u2DelayCellOfst[9]=3 cells (1 PI)
8457 11:33:21.463780 u2DelayCellOfst[10]=10 cells (3 PI)
8458 11:33:21.467462 u2DelayCellOfst[11]=3 cells (1 PI)
8459 11:33:21.470252 u2DelayCellOfst[12]=14 cells (4 PI)
8460 11:33:21.473745 u2DelayCellOfst[13]=14 cells (4 PI)
8461 11:33:21.476757 u2DelayCellOfst[14]=17 cells (5 PI)
8462 11:33:21.480587 u2DelayCellOfst[15]=17 cells (5 PI)
8463 11:33:21.483863 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8464 11:33:21.486910 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8465 11:33:21.490443 DramC Write-DBI on
8466 11:33:21.490516 ==
8467 11:33:21.493288 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 11:33:21.496951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 11:33:21.497020 ==
8470 11:33:21.497077
8471 11:33:21.497130
8472 11:33:21.500045 TX Vref Scan disable
8473 11:33:21.500121 == TX Byte 0 ==
8474 11:33:21.506623 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8475 11:33:21.506700 == TX Byte 1 ==
8476 11:33:21.513129 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8477 11:33:21.513214 DramC Write-DBI off
8478 11:33:21.513274
8479 11:33:21.513331 [DATLAT]
8480 11:33:21.516866 Freq=1600, CH1 RK0
8481 11:33:21.516966
8482 11:33:21.519828 DATLAT Default: 0xf
8483 11:33:21.519904 0, 0xFFFF, sum = 0
8484 11:33:21.523438 1, 0xFFFF, sum = 0
8485 11:33:21.523516 2, 0xFFFF, sum = 0
8486 11:33:21.526423 3, 0xFFFF, sum = 0
8487 11:33:21.526501 4, 0xFFFF, sum = 0
8488 11:33:21.530330 5, 0xFFFF, sum = 0
8489 11:33:21.530407 6, 0xFFFF, sum = 0
8490 11:33:21.533238 7, 0xFFFF, sum = 0
8491 11:33:21.533315 8, 0xFFFF, sum = 0
8492 11:33:21.536646 9, 0xFFFF, sum = 0
8493 11:33:21.536724 10, 0xFFFF, sum = 0
8494 11:33:21.539530 11, 0xFFFF, sum = 0
8495 11:33:21.539607 12, 0xFFFF, sum = 0
8496 11:33:21.543281 13, 0xFFFF, sum = 0
8497 11:33:21.543358 14, 0x0, sum = 1
8498 11:33:21.546111 15, 0x0, sum = 2
8499 11:33:21.546189 16, 0x0, sum = 3
8500 11:33:21.549747 17, 0x0, sum = 4
8501 11:33:21.549824 best_step = 15
8502 11:33:21.549883
8503 11:33:21.549938 ==
8504 11:33:21.553033 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 11:33:21.559575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 11:33:21.559651 ==
8507 11:33:21.559712 RX Vref Scan: 1
8508 11:33:21.559768
8509 11:33:21.562593 Set Vref Range= 24 -> 127
8510 11:33:21.562669
8511 11:33:21.566353 RX Vref 24 -> 127, step: 1
8512 11:33:21.566429
8513 11:33:21.569152 RX Delay 19 -> 252, step: 4
8514 11:33:21.569234
8515 11:33:21.572585 Set Vref, RX VrefLevel [Byte0]: 24
8516 11:33:21.575925 [Byte1]: 24
8517 11:33:21.576001
8518 11:33:21.579307 Set Vref, RX VrefLevel [Byte0]: 25
8519 11:33:21.582463 [Byte1]: 25
8520 11:33:21.582538
8521 11:33:21.585886 Set Vref, RX VrefLevel [Byte0]: 26
8522 11:33:21.589258 [Byte1]: 26
8523 11:33:21.589334
8524 11:33:21.592520 Set Vref, RX VrefLevel [Byte0]: 27
8525 11:33:21.595739 [Byte1]: 27
8526 11:33:21.599652
8527 11:33:21.599727 Set Vref, RX VrefLevel [Byte0]: 28
8528 11:33:21.603567 [Byte1]: 28
8529 11:33:21.607593
8530 11:33:21.607669 Set Vref, RX VrefLevel [Byte0]: 29
8531 11:33:21.610316 [Byte1]: 29
8532 11:33:21.615072
8533 11:33:21.615157 Set Vref, RX VrefLevel [Byte0]: 30
8534 11:33:21.618260 [Byte1]: 30
8535 11:33:21.622601
8536 11:33:21.622677 Set Vref, RX VrefLevel [Byte0]: 31
8537 11:33:21.625430 [Byte1]: 31
8538 11:33:21.629702
8539 11:33:21.629785 Set Vref, RX VrefLevel [Byte0]: 32
8540 11:33:21.633202 [Byte1]: 32
8541 11:33:21.637594
8542 11:33:21.637693 Set Vref, RX VrefLevel [Byte0]: 33
8543 11:33:21.641047 [Byte1]: 33
8544 11:33:21.645442
8545 11:33:21.645517 Set Vref, RX VrefLevel [Byte0]: 34
8546 11:33:21.648621 [Byte1]: 34
8547 11:33:21.652656
8548 11:33:21.652754 Set Vref, RX VrefLevel [Byte0]: 35
8549 11:33:21.656205 [Byte1]: 35
8550 11:33:21.660499
8551 11:33:21.660614 Set Vref, RX VrefLevel [Byte0]: 36
8552 11:33:21.663335 [Byte1]: 36
8553 11:33:21.667765
8554 11:33:21.667844 Set Vref, RX VrefLevel [Byte0]: 37
8555 11:33:21.671021 [Byte1]: 37
8556 11:33:21.675392
8557 11:33:21.675468 Set Vref, RX VrefLevel [Byte0]: 38
8558 11:33:21.678550 [Byte1]: 38
8559 11:33:21.683148
8560 11:33:21.683250 Set Vref, RX VrefLevel [Byte0]: 39
8561 11:33:21.686234 [Byte1]: 39
8562 11:33:21.690809
8563 11:33:21.690885 Set Vref, RX VrefLevel [Byte0]: 40
8564 11:33:21.693676 [Byte1]: 40
8565 11:33:21.698389
8566 11:33:21.698469 Set Vref, RX VrefLevel [Byte0]: 41
8567 11:33:21.701315 [Byte1]: 41
8568 11:33:21.705794
8569 11:33:21.705872 Set Vref, RX VrefLevel [Byte0]: 42
8570 11:33:21.709330 [Byte1]: 42
8571 11:33:21.713613
8572 11:33:21.713690 Set Vref, RX VrefLevel [Byte0]: 43
8573 11:33:21.717012 [Byte1]: 43
8574 11:33:21.721214
8575 11:33:21.721290 Set Vref, RX VrefLevel [Byte0]: 44
8576 11:33:21.724456 [Byte1]: 44
8577 11:33:21.728316
8578 11:33:21.728392 Set Vref, RX VrefLevel [Byte0]: 45
8579 11:33:21.732094 [Byte1]: 45
8580 11:33:21.735995
8581 11:33:21.736080 Set Vref, RX VrefLevel [Byte0]: 46
8582 11:33:21.739051 [Byte1]: 46
8583 11:33:21.743844
8584 11:33:21.743920 Set Vref, RX VrefLevel [Byte0]: 47
8585 11:33:21.746714 [Byte1]: 47
8586 11:33:21.751014
8587 11:33:21.751091 Set Vref, RX VrefLevel [Byte0]: 48
8588 11:33:21.754579 [Byte1]: 48
8589 11:33:21.758563
8590 11:33:21.758639 Set Vref, RX VrefLevel [Byte0]: 49
8591 11:33:21.762064 [Byte1]: 49
8592 11:33:21.766546
8593 11:33:21.766622 Set Vref, RX VrefLevel [Byte0]: 50
8594 11:33:21.769370 [Byte1]: 50
8595 11:33:21.774021
8596 11:33:21.774097 Set Vref, RX VrefLevel [Byte0]: 51
8597 11:33:21.780372 [Byte1]: 51
8598 11:33:21.780448
8599 11:33:21.783912 Set Vref, RX VrefLevel [Byte0]: 52
8600 11:33:21.786795 [Byte1]: 52
8601 11:33:21.786872
8602 11:33:21.789909 Set Vref, RX VrefLevel [Byte0]: 53
8603 11:33:21.793462 [Byte1]: 53
8604 11:33:21.793539
8605 11:33:21.796933 Set Vref, RX VrefLevel [Byte0]: 54
8606 11:33:21.799864 [Byte1]: 54
8607 11:33:21.804755
8608 11:33:21.804840 Set Vref, RX VrefLevel [Byte0]: 55
8609 11:33:21.807636 [Byte1]: 55
8610 11:33:21.811708
8611 11:33:21.811784 Set Vref, RX VrefLevel [Byte0]: 56
8612 11:33:21.814770 [Byte1]: 56
8613 11:33:21.819336
8614 11:33:21.819413 Set Vref, RX VrefLevel [Byte0]: 57
8615 11:33:21.822785 [Byte1]: 57
8616 11:33:21.827179
8617 11:33:21.827254 Set Vref, RX VrefLevel [Byte0]: 58
8618 11:33:21.830531 [Byte1]: 58
8619 11:33:21.834475
8620 11:33:21.834551 Set Vref, RX VrefLevel [Byte0]: 59
8621 11:33:21.837903 [Byte1]: 59
8622 11:33:21.841990
8623 11:33:21.842066 Set Vref, RX VrefLevel [Byte0]: 60
8624 11:33:21.845151 [Byte1]: 60
8625 11:33:21.850133
8626 11:33:21.850208 Set Vref, RX VrefLevel [Byte0]: 61
8627 11:33:21.852632 [Byte1]: 61
8628 11:33:21.856866
8629 11:33:21.856942 Set Vref, RX VrefLevel [Byte0]: 62
8630 11:33:21.860407 [Byte1]: 62
8631 11:33:21.864590
8632 11:33:21.864666 Set Vref, RX VrefLevel [Byte0]: 63
8633 11:33:21.868117 [Byte1]: 63
8634 11:33:21.872203
8635 11:33:21.872279 Set Vref, RX VrefLevel [Byte0]: 64
8636 11:33:21.875314 [Byte1]: 64
8637 11:33:21.879997
8638 11:33:21.880072 Set Vref, RX VrefLevel [Byte0]: 65
8639 11:33:21.883003 [Byte1]: 65
8640 11:33:21.887615
8641 11:33:21.887714 Set Vref, RX VrefLevel [Byte0]: 66
8642 11:33:21.890764 [Byte1]: 66
8643 11:33:21.894870
8644 11:33:21.894970 Set Vref, RX VrefLevel [Byte0]: 67
8645 11:33:21.898275 [Byte1]: 67
8646 11:33:21.902797
8647 11:33:21.902873 Set Vref, RX VrefLevel [Byte0]: 68
8648 11:33:21.906360 [Byte1]: 68
8649 11:33:21.910122
8650 11:33:21.910198 Set Vref, RX VrefLevel [Byte0]: 69
8651 11:33:21.913520 [Byte1]: 69
8652 11:33:21.917897
8653 11:33:21.917974 Set Vref, RX VrefLevel [Byte0]: 70
8654 11:33:21.921018 [Byte1]: 70
8655 11:33:21.925150
8656 11:33:21.925244 Set Vref, RX VrefLevel [Byte0]: 71
8657 11:33:21.928605 [Byte1]: 71
8658 11:33:21.932821
8659 11:33:21.932926 Set Vref, RX VrefLevel [Byte0]: 72
8660 11:33:21.935971 [Byte1]: 72
8661 11:33:21.940725
8662 11:33:21.940795 Final RX Vref Byte 0 = 61 to rank0
8663 11:33:21.943906 Final RX Vref Byte 1 = 60 to rank0
8664 11:33:21.947021 Final RX Vref Byte 0 = 61 to rank1
8665 11:33:21.950604 Final RX Vref Byte 1 = 60 to rank1==
8666 11:33:21.953581 Dram Type= 6, Freq= 0, CH_1, rank 0
8667 11:33:21.960271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8668 11:33:21.960353 ==
8669 11:33:21.960413 DQS Delay:
8670 11:33:21.963587 DQS0 = 0, DQS1 = 0
8671 11:33:21.963664 DQM Delay:
8672 11:33:21.963723 DQM0 = 132, DQM1 = 127
8673 11:33:21.967129 DQ Delay:
8674 11:33:21.970120 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8675 11:33:21.973245 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8676 11:33:21.976788 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8677 11:33:21.979782 DQ12 =138, DQ13 =138, DQ14 =134, DQ15 =136
8678 11:33:21.979858
8679 11:33:21.979917
8680 11:33:21.979972
8681 11:33:21.983523 [DramC_TX_OE_Calibration] TA2
8682 11:33:21.987042 Original DQ_B0 (3 6) =30, OEN = 27
8683 11:33:21.990172 Original DQ_B1 (3 6) =30, OEN = 27
8684 11:33:21.993151 24, 0x0, End_B0=24 End_B1=24
8685 11:33:21.996477 25, 0x0, End_B0=25 End_B1=25
8686 11:33:21.996553 26, 0x0, End_B0=26 End_B1=26
8687 11:33:21.999809 27, 0x0, End_B0=27 End_B1=27
8688 11:33:22.002937 28, 0x0, End_B0=28 End_B1=28
8689 11:33:22.006399 29, 0x0, End_B0=29 End_B1=29
8690 11:33:22.006475 30, 0x0, End_B0=30 End_B1=30
8691 11:33:22.010057 31, 0x4141, End_B0=30 End_B1=30
8692 11:33:22.012841 Byte0 end_step=30 best_step=27
8693 11:33:22.016004 Byte1 end_step=30 best_step=27
8694 11:33:22.019800 Byte0 TX OE(2T, 0.5T) = (3, 3)
8695 11:33:22.023012 Byte1 TX OE(2T, 0.5T) = (3, 3)
8696 11:33:22.023111
8697 11:33:22.023168
8698 11:33:22.029391 [DQSOSCAuto] RK0, (LSB)MR18= 0xc15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 403 ps
8699 11:33:22.032942 CH1 RK0: MR19=303, MR18=C15
8700 11:33:22.039506 CH1_RK0: MR19=0x303, MR18=0xC15, DQSOSC=399, MR23=63, INC=23, DEC=15
8701 11:33:22.039581
8702 11:33:22.042700 ----->DramcWriteLeveling(PI) begin...
8703 11:33:22.042790 ==
8704 11:33:22.045964 Dram Type= 6, Freq= 0, CH_1, rank 1
8705 11:33:22.049503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8706 11:33:22.049579 ==
8707 11:33:22.052439 Write leveling (Byte 0): 24 => 24
8708 11:33:22.056109 Write leveling (Byte 1): 24 => 24
8709 11:33:22.059137 DramcWriteLeveling(PI) end<-----
8710 11:33:22.059205
8711 11:33:22.059262 ==
8712 11:33:22.062574 Dram Type= 6, Freq= 0, CH_1, rank 1
8713 11:33:22.065788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8714 11:33:22.065877 ==
8715 11:33:22.069106 [Gating] SW mode calibration
8716 11:33:22.075603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8717 11:33:22.082168 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8718 11:33:22.085665 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8719 11:33:22.092146 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8720 11:33:22.095797 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8721 11:33:22.098652 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8722 11:33:22.105663 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8723 11:33:22.108418 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8724 11:33:22.112276 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8725 11:33:22.118230 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8726 11:33:22.122110 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 11:33:22.125074 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8728 11:33:22.131389 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8729 11:33:22.134816 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8730 11:33:22.138806 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 11:33:22.144725 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 11:33:22.148168 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 11:33:22.151239 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 11:33:22.158329 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 11:33:22.161101 1 6 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8736 11:33:22.164568 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8737 11:33:22.170843 1 6 12 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
8738 11:33:22.174162 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8739 11:33:22.177820 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8740 11:33:22.184021 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 11:33:22.187192 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8742 11:33:22.190661 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 11:33:22.197406 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8744 11:33:22.200496 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8745 11:33:22.203878 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8746 11:33:22.210446 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 11:33:22.213871 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 11:33:22.217348 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 11:33:22.223321 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 11:33:22.226875 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 11:33:22.230395 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 11:33:22.236562 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 11:33:22.239896 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 11:33:22.243199 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 11:33:22.249904 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 11:33:22.253338 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 11:33:22.256819 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 11:33:22.263055 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 11:33:22.266600 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8760 11:33:22.270206 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8761 11:33:22.276655 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8762 11:33:22.279642 Total UI for P1: 0, mck2ui 16
8763 11:33:22.283025 best dqsien dly found for B0: ( 1, 9, 6)
8764 11:33:22.286172 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 11:33:22.289628 Total UI for P1: 0, mck2ui 16
8766 11:33:22.292978 best dqsien dly found for B1: ( 1, 9, 12)
8767 11:33:22.295912 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8768 11:33:22.299400 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8769 11:33:22.299477
8770 11:33:22.302928 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8771 11:33:22.309242 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8772 11:33:22.309318 [Gating] SW calibration Done
8773 11:33:22.309378 ==
8774 11:33:22.312509 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 11:33:22.319318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 11:33:22.319395 ==
8777 11:33:22.319455 RX Vref Scan: 0
8778 11:33:22.319510
8779 11:33:22.322589 RX Vref 0 -> 0, step: 1
8780 11:33:22.322665
8781 11:33:22.325647 RX Delay 0 -> 252, step: 8
8782 11:33:22.329368 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8783 11:33:22.333001 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8784 11:33:22.335575 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8785 11:33:22.342647 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8786 11:33:22.346019 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8787 11:33:22.349035 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8788 11:33:22.352147 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8789 11:33:22.355409 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8790 11:33:22.362355 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8791 11:33:22.365494 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8792 11:33:22.368555 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8793 11:33:22.372077 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8794 11:33:22.375072 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8795 11:33:22.381989 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8796 11:33:22.385362 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8797 11:33:22.388327 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8798 11:33:22.388403 ==
8799 11:33:22.391869 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 11:33:22.395003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 11:33:22.398356 ==
8802 11:33:22.398432 DQS Delay:
8803 11:33:22.398491 DQS0 = 0, DQS1 = 0
8804 11:33:22.401332 DQM Delay:
8805 11:33:22.401408 DQM0 = 132, DQM1 = 131
8806 11:33:22.404814 DQ Delay:
8807 11:33:22.408196 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8808 11:33:22.411599 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8809 11:33:22.414864 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8810 11:33:22.417990 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8811 11:33:22.418066
8812 11:33:22.418125
8813 11:33:22.418179 ==
8814 11:33:22.421034 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 11:33:22.424582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 11:33:22.427892 ==
8817 11:33:22.427968
8818 11:33:22.428026
8819 11:33:22.428081 TX Vref Scan disable
8820 11:33:22.430841 == TX Byte 0 ==
8821 11:33:22.434594 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8822 11:33:22.437883 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8823 11:33:22.440997 == TX Byte 1 ==
8824 11:33:22.444311 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8825 11:33:22.447246 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8826 11:33:22.450955 ==
8827 11:33:22.453889 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 11:33:22.457686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 11:33:22.457764 ==
8830 11:33:22.470311
8831 11:33:22.473987 TX Vref early break, caculate TX vref
8832 11:33:22.476777 TX Vref=16, minBit 9, minWin=22, winSum=377
8833 11:33:22.479953 TX Vref=18, minBit 1, minWin=23, winSum=385
8834 11:33:22.483160 TX Vref=20, minBit 9, minWin=23, winSum=398
8835 11:33:22.486904 TX Vref=22, minBit 9, minWin=23, winSum=401
8836 11:33:22.490385 TX Vref=24, minBit 1, minWin=25, winSum=411
8837 11:33:22.496325 TX Vref=26, minBit 9, minWin=25, winSum=421
8838 11:33:22.499892 TX Vref=28, minBit 0, minWin=26, winSum=424
8839 11:33:22.502957 TX Vref=30, minBit 5, minWin=25, winSum=419
8840 11:33:22.506371 TX Vref=32, minBit 0, minWin=25, winSum=417
8841 11:33:22.509820 TX Vref=34, minBit 0, minWin=24, winSum=402
8842 11:33:22.516174 TX Vref=36, minBit 9, minWin=23, winSum=401
8843 11:33:22.519411 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8844 11:33:22.519489
8845 11:33:22.522843 Final TX Range 0 Vref 28
8846 11:33:22.522919
8847 11:33:22.522978 ==
8848 11:33:22.526234 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 11:33:22.529842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 11:33:22.532527 ==
8851 11:33:22.532619
8852 11:33:22.532706
8853 11:33:22.532791 TX Vref Scan disable
8854 11:33:22.539499 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8855 11:33:22.539577 == TX Byte 0 ==
8856 11:33:22.543134 u2DelayCellOfst[0]=14 cells (4 PI)
8857 11:33:22.546000 u2DelayCellOfst[1]=10 cells (3 PI)
8858 11:33:22.549622 u2DelayCellOfst[2]=0 cells (0 PI)
8859 11:33:22.553017 u2DelayCellOfst[3]=3 cells (1 PI)
8860 11:33:22.556067 u2DelayCellOfst[4]=7 cells (2 PI)
8861 11:33:22.559060 u2DelayCellOfst[5]=14 cells (4 PI)
8862 11:33:22.562662 u2DelayCellOfst[6]=14 cells (4 PI)
8863 11:33:22.565685 u2DelayCellOfst[7]=7 cells (2 PI)
8864 11:33:22.569114 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8865 11:33:22.572603 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8866 11:33:22.576029 == TX Byte 1 ==
8867 11:33:22.578915 u2DelayCellOfst[8]=0 cells (0 PI)
8868 11:33:22.582346 u2DelayCellOfst[9]=0 cells (0 PI)
8869 11:33:22.585740 u2DelayCellOfst[10]=10 cells (3 PI)
8870 11:33:22.588915 u2DelayCellOfst[11]=3 cells (1 PI)
8871 11:33:22.592074 u2DelayCellOfst[12]=10 cells (3 PI)
8872 11:33:22.595537 u2DelayCellOfst[13]=14 cells (4 PI)
8873 11:33:22.598904 u2DelayCellOfst[14]=17 cells (5 PI)
8874 11:33:22.601808 u2DelayCellOfst[15]=17 cells (5 PI)
8875 11:33:22.605235 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8876 11:33:22.608531 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8877 11:33:22.611791 DramC Write-DBI on
8878 11:33:22.611867 ==
8879 11:33:22.615307 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 11:33:22.618710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 11:33:22.618787 ==
8882 11:33:22.618846
8883 11:33:22.618901
8884 11:33:22.621542 TX Vref Scan disable
8885 11:33:22.621618 == TX Byte 0 ==
8886 11:33:22.628408 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8887 11:33:22.628485 == TX Byte 1 ==
8888 11:33:22.634849 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8889 11:33:22.634927 DramC Write-DBI off
8890 11:33:22.634986
8891 11:33:22.635041 [DATLAT]
8892 11:33:22.637990 Freq=1600, CH1 RK1
8893 11:33:22.638067
8894 11:33:22.641457 DATLAT Default: 0xf
8895 11:33:22.641533 0, 0xFFFF, sum = 0
8896 11:33:22.644610 1, 0xFFFF, sum = 0
8897 11:33:22.644687 2, 0xFFFF, sum = 0
8898 11:33:22.648071 3, 0xFFFF, sum = 0
8899 11:33:22.648148 4, 0xFFFF, sum = 0
8900 11:33:22.651514 5, 0xFFFF, sum = 0
8901 11:33:22.651592 6, 0xFFFF, sum = 0
8902 11:33:22.654567 7, 0xFFFF, sum = 0
8903 11:33:22.654644 8, 0xFFFF, sum = 0
8904 11:33:22.657904 9, 0xFFFF, sum = 0
8905 11:33:22.657981 10, 0xFFFF, sum = 0
8906 11:33:22.660871 11, 0xFFFF, sum = 0
8907 11:33:22.660971 12, 0xFFFF, sum = 0
8908 11:33:22.664531 13, 0xFFFF, sum = 0
8909 11:33:22.664635 14, 0x0, sum = 1
8910 11:33:22.667609 15, 0x0, sum = 2
8911 11:33:22.667686 16, 0x0, sum = 3
8912 11:33:22.670956 17, 0x0, sum = 4
8913 11:33:22.671034 best_step = 15
8914 11:33:22.671093
8915 11:33:22.671148 ==
8916 11:33:22.674343 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 11:33:22.681077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 11:33:22.681179 ==
8919 11:33:22.681240 RX Vref Scan: 0
8920 11:33:22.681295
8921 11:33:22.684097 RX Vref 0 -> 0, step: 1
8922 11:33:22.684174
8923 11:33:22.687641 RX Delay 11 -> 252, step: 4
8924 11:33:22.690690 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8925 11:33:22.694774 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8926 11:33:22.700546 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8927 11:33:22.703823 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8928 11:33:22.707043 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8929 11:33:22.710899 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8930 11:33:22.714152 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8931 11:33:22.720611 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8932 11:33:22.723852 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8933 11:33:22.726827 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8934 11:33:22.730033 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8935 11:33:22.733528 iDelay=195, Bit 11, Center 122 (71 ~ 174) 104
8936 11:33:22.739782 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8937 11:33:22.743564 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8938 11:33:22.746530 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8939 11:33:22.750068 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8940 11:33:22.750144 ==
8941 11:33:22.753355 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 11:33:22.760150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 11:33:22.760228 ==
8944 11:33:22.760288 DQS Delay:
8945 11:33:22.763012 DQS0 = 0, DQS1 = 0
8946 11:33:22.763089 DQM Delay:
8947 11:33:22.766409 DQM0 = 130, DQM1 = 129
8948 11:33:22.766485 DQ Delay:
8949 11:33:22.769413 DQ0 =136, DQ1 =128, DQ2 =118, DQ3 =128
8950 11:33:22.772752 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =126
8951 11:33:22.775842 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8952 11:33:22.779321 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138
8953 11:33:22.779397
8954 11:33:22.779456
8955 11:33:22.779512
8956 11:33:22.782875 [DramC_TX_OE_Calibration] TA2
8957 11:33:22.785748 Original DQ_B0 (3 6) =30, OEN = 27
8958 11:33:22.789423 Original DQ_B1 (3 6) =30, OEN = 27
8959 11:33:22.792502 24, 0x0, End_B0=24 End_B1=24
8960 11:33:22.796012 25, 0x0, End_B0=25 End_B1=25
8961 11:33:22.799077 26, 0x0, End_B0=26 End_B1=26
8962 11:33:22.799155 27, 0x0, End_B0=27 End_B1=27
8963 11:33:22.802305 28, 0x0, End_B0=28 End_B1=28
8964 11:33:22.805457 29, 0x0, End_B0=29 End_B1=29
8965 11:33:22.809086 30, 0x0, End_B0=30 End_B1=30
8966 11:33:22.809184 31, 0x4141, End_B0=30 End_B1=30
8967 11:33:22.812175 Byte0 end_step=30 best_step=27
8968 11:33:22.815741 Byte1 end_step=30 best_step=27
8969 11:33:22.818764 Byte0 TX OE(2T, 0.5T) = (3, 3)
8970 11:33:22.822317 Byte1 TX OE(2T, 0.5T) = (3, 3)
8971 11:33:22.822393
8972 11:33:22.822451
8973 11:33:22.828587 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8974 11:33:22.832428 CH1 RK1: MR19=303, MR18=101E
8975 11:33:22.838880 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
8976 11:33:22.842162 [RxdqsGatingPostProcess] freq 1600
8977 11:33:22.848584 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8978 11:33:22.852419 best DQS0 dly(2T, 0.5T) = (1, 1)
8979 11:33:22.854999 best DQS1 dly(2T, 0.5T) = (1, 1)
8980 11:33:22.858421 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8981 11:33:22.858498 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8982 11:33:22.861561 best DQS0 dly(2T, 0.5T) = (1, 1)
8983 11:33:22.864734 best DQS1 dly(2T, 0.5T) = (1, 1)
8984 11:33:22.867955 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8985 11:33:22.871612 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8986 11:33:22.874567 Pre-setting of DQS Precalculation
8987 11:33:22.881524 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8988 11:33:22.887927 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8989 11:33:22.894365 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8990 11:33:22.894442
8991 11:33:22.894501
8992 11:33:22.898057 [Calibration Summary] 3200 Mbps
8993 11:33:22.898132 CH 0, Rank 0
8994 11:33:22.901044 SW Impedance : PASS
8995 11:33:22.904416 DUTY Scan : NO K
8996 11:33:22.904490 ZQ Calibration : PASS
8997 11:33:22.907409 Jitter Meter : NO K
8998 11:33:22.910973 CBT Training : PASS
8999 11:33:22.911048 Write leveling : PASS
9000 11:33:22.914100 RX DQS gating : PASS
9001 11:33:22.917538 RX DQ/DQS(RDDQC) : PASS
9002 11:33:22.917613 TX DQ/DQS : PASS
9003 11:33:22.921116 RX DATLAT : PASS
9004 11:33:22.924186 RX DQ/DQS(Engine): PASS
9005 11:33:22.924260 TX OE : PASS
9006 11:33:22.927228 All Pass.
9007 11:33:22.927302
9008 11:33:22.927359 CH 0, Rank 1
9009 11:33:22.930725 SW Impedance : PASS
9010 11:33:22.930800 DUTY Scan : NO K
9011 11:33:22.934149 ZQ Calibration : PASS
9012 11:33:22.937004 Jitter Meter : NO K
9013 11:33:22.937102 CBT Training : PASS
9014 11:33:22.940459 Write leveling : PASS
9015 11:33:22.943846 RX DQS gating : PASS
9016 11:33:22.943921 RX DQ/DQS(RDDQC) : PASS
9017 11:33:22.947579 TX DQ/DQS : PASS
9018 11:33:22.947654 RX DATLAT : PASS
9019 11:33:22.950629 RX DQ/DQS(Engine): PASS
9020 11:33:22.953531 TX OE : PASS
9021 11:33:22.953606 All Pass.
9022 11:33:22.953664
9023 11:33:22.953734 CH 1, Rank 0
9024 11:33:22.957000 SW Impedance : PASS
9025 11:33:22.960509 DUTY Scan : NO K
9026 11:33:22.960584 ZQ Calibration : PASS
9027 11:33:22.963608 Jitter Meter : NO K
9028 11:33:22.966904 CBT Training : PASS
9029 11:33:22.966979 Write leveling : PASS
9030 11:33:22.970299 RX DQS gating : PASS
9031 11:33:22.973344 RX DQ/DQS(RDDQC) : PASS
9032 11:33:22.973418 TX DQ/DQS : PASS
9033 11:33:22.976536 RX DATLAT : PASS
9034 11:33:22.980038 RX DQ/DQS(Engine): PASS
9035 11:33:22.980113 TX OE : PASS
9036 11:33:22.983536 All Pass.
9037 11:33:22.983610
9038 11:33:22.983667 CH 1, Rank 1
9039 11:33:22.986598 SW Impedance : PASS
9040 11:33:22.986673 DUTY Scan : NO K
9041 11:33:22.990015 ZQ Calibration : PASS
9042 11:33:22.993340 Jitter Meter : NO K
9043 11:33:22.993415 CBT Training : PASS
9044 11:33:22.996611 Write leveling : PASS
9045 11:33:22.999643 RX DQS gating : PASS
9046 11:33:22.999718 RX DQ/DQS(RDDQC) : PASS
9047 11:33:23.003014 TX DQ/DQS : PASS
9048 11:33:23.006526 RX DATLAT : PASS
9049 11:33:23.006601 RX DQ/DQS(Engine): PASS
9050 11:33:23.009578 TX OE : PASS
9051 11:33:23.009654 All Pass.
9052 11:33:23.009713
9053 11:33:23.013116 DramC Write-DBI on
9054 11:33:23.016215 PER_BANK_REFRESH: Hybrid Mode
9055 11:33:23.016289 TX_TRACKING: ON
9056 11:33:23.026422 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9057 11:33:23.032549 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9058 11:33:23.039323 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 11:33:23.045852 [FAST_K] Save calibration result to emmc
9060 11:33:23.045928 sync common calibartion params.
9061 11:33:23.049320 sync cbt_mode0:1, 1:1
9062 11:33:23.052606 dram_init: ddr_geometry: 2
9063 11:33:23.052681 dram_init: ddr_geometry: 2
9064 11:33:23.056172 dram_init: ddr_geometry: 2
9065 11:33:23.058667 0:dram_rank_size:100000000
9066 11:33:23.062420 1:dram_rank_size:100000000
9067 11:33:23.065744 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9068 11:33:23.068894 DFS_SHUFFLE_HW_MODE: ON
9069 11:33:23.072322 dramc_set_vcore_voltage set vcore to 725000
9070 11:33:23.075677 Read voltage for 1600, 0
9071 11:33:23.075751 Vio18 = 0
9072 11:33:23.079228 Vcore = 725000
9073 11:33:23.079302 Vdram = 0
9074 11:33:23.079360 Vddq = 0
9075 11:33:23.079414 Vmddr = 0
9076 11:33:23.082148 switch to 3200 Mbps bootup
9077 11:33:23.085321 [DramcRunTimeConfig]
9078 11:33:23.085395 PHYPLL
9079 11:33:23.088972 DPM_CONTROL_AFTERK: ON
9080 11:33:23.089047 PER_BANK_REFRESH: ON
9081 11:33:23.091766 REFRESH_OVERHEAD_REDUCTION: ON
9082 11:33:23.095279 CMD_PICG_NEW_MODE: OFF
9083 11:33:23.095354 XRTWTW_NEW_MODE: ON
9084 11:33:23.098581 XRTRTR_NEW_MODE: ON
9085 11:33:23.098656 TX_TRACKING: ON
9086 11:33:23.101957 RDSEL_TRACKING: OFF
9087 11:33:23.104836 DQS Precalculation for DVFS: ON
9088 11:33:23.104974 RX_TRACKING: OFF
9089 11:33:23.108136 HW_GATING DBG: ON
9090 11:33:23.108211 ZQCS_ENABLE_LP4: ON
9091 11:33:23.111628 RX_PICG_NEW_MODE: ON
9092 11:33:23.111716 TX_PICG_NEW_MODE: ON
9093 11:33:23.115050 ENABLE_RX_DCM_DPHY: ON
9094 11:33:23.118259 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9095 11:33:23.121814 DUMMY_READ_FOR_TRACKING: OFF
9096 11:33:23.121888 !!! SPM_CONTROL_AFTERK: OFF
9097 11:33:23.125104 !!! SPM could not control APHY
9098 11:33:23.127861 IMPEDANCE_TRACKING: ON
9099 11:33:23.127935 TEMP_SENSOR: ON
9100 11:33:23.131765 HW_SAVE_FOR_SR: OFF
9101 11:33:23.134442 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9102 11:33:23.138109 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9103 11:33:23.138183 Read ODT Tracking: ON
9104 11:33:23.141078 Refresh Rate DeBounce: ON
9105 11:33:23.144576 DFS_NO_QUEUE_FLUSH: ON
9106 11:33:23.148074 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9107 11:33:23.148176 ENABLE_DFS_RUNTIME_MRW: OFF
9108 11:33:23.151417 DDR_RESERVE_NEW_MODE: ON
9109 11:33:23.154350 MR_CBT_SWITCH_FREQ: ON
9110 11:33:23.157665 =========================
9111 11:33:23.174706 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9112 11:33:23.178636 dram_init: ddr_geometry: 2
9113 11:33:23.196303 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9114 11:33:23.199856 dram_init: dram init end (result: 0)
9115 11:33:23.206550 DRAM-K: Full calibration passed in 24412 msecs
9116 11:33:23.209400 MRC: failed to locate region type 0.
9117 11:33:23.209476 DRAM rank0 size:0x100000000,
9118 11:33:23.212956 DRAM rank1 size=0x100000000
9119 11:33:23.222850 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9120 11:33:23.229767 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9121 11:33:23.236074 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9122 11:33:23.246312 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9123 11:33:23.246388 DRAM rank0 size:0x100000000,
9124 11:33:23.249044 DRAM rank1 size=0x100000000
9125 11:33:23.249162 CBMEM:
9126 11:33:23.252915 IMD: root @ 0xfffff000 254 entries.
9127 11:33:23.255835 IMD: root @ 0xffffec00 62 entries.
9128 11:33:23.259252 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9129 11:33:23.265716 WARNING: RO_VPD is uninitialized or empty.
9130 11:33:23.268991 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9131 11:33:23.276445 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9132 11:33:23.289197 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9133 11:33:23.300655 BS: romstage times (exec / console): total (unknown) / 23942 ms
9134 11:33:23.300778
9135 11:33:23.300838
9136 11:33:23.310709 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9137 11:33:23.314109 ARM64: Exception handlers installed.
9138 11:33:23.317031 ARM64: Testing exception
9139 11:33:23.320524 ARM64: Done test exception
9140 11:33:23.320641 Enumerating buses...
9141 11:33:23.324004 Show all devs... Before device enumeration.
9142 11:33:23.326894 Root Device: enabled 1
9143 11:33:23.330464 CPU_CLUSTER: 0: enabled 1
9144 11:33:23.330576 CPU: 00: enabled 1
9145 11:33:23.333680 Compare with tree...
9146 11:33:23.333754 Root Device: enabled 1
9147 11:33:23.336796 CPU_CLUSTER: 0: enabled 1
9148 11:33:23.340480 CPU: 00: enabled 1
9149 11:33:23.340574 Root Device scanning...
9150 11:33:23.343474 scan_static_bus for Root Device
9151 11:33:23.347137 CPU_CLUSTER: 0 enabled
9152 11:33:23.350334 scan_static_bus for Root Device done
9153 11:33:23.353124 scan_bus: bus Root Device finished in 8 msecs
9154 11:33:23.353222 done
9155 11:33:23.360120 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9156 11:33:23.363118 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9157 11:33:23.370215 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9158 11:33:23.376700 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9159 11:33:23.376776 Allocating resources...
9160 11:33:23.380106 Reading resources...
9161 11:33:23.383046 Root Device read_resources bus 0 link: 0
9162 11:33:23.386655 DRAM rank0 size:0x100000000,
9163 11:33:23.386744 DRAM rank1 size=0x100000000
9164 11:33:23.392851 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9165 11:33:23.392926 CPU: 00 missing read_resources
9166 11:33:23.399473 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9167 11:33:23.403012 Root Device read_resources bus 0 link: 0 done
9168 11:33:23.405914 Done reading resources.
9169 11:33:23.409245 Show resources in subtree (Root Device)...After reading.
9170 11:33:23.412602 Root Device child on link 0 CPU_CLUSTER: 0
9171 11:33:23.416299 CPU_CLUSTER: 0 child on link 0 CPU: 00
9172 11:33:23.426211 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9173 11:33:23.426287 CPU: 00
9174 11:33:23.432443 Root Device assign_resources, bus 0 link: 0
9175 11:33:23.435980 CPU_CLUSTER: 0 missing set_resources
9176 11:33:23.438900 Root Device assign_resources, bus 0 link: 0 done
9177 11:33:23.438989 Done setting resources.
9178 11:33:23.445910 Show resources in subtree (Root Device)...After assigning values.
9179 11:33:23.449033 Root Device child on link 0 CPU_CLUSTER: 0
9180 11:33:23.455404 CPU_CLUSTER: 0 child on link 0 CPU: 00
9181 11:33:23.461866 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9182 11:33:23.465025 CPU: 00
9183 11:33:23.465145 Done allocating resources.
9184 11:33:23.471690 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9185 11:33:23.471766 Enabling resources...
9186 11:33:23.475251 done.
9187 11:33:23.479026 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9188 11:33:23.481639 Initializing devices...
9189 11:33:23.481742 Root Device init
9190 11:33:23.485040 init hardware done!
9191 11:33:23.485147 0x00000018: ctrlr->caps
9192 11:33:23.488223 52.000 MHz: ctrlr->f_max
9193 11:33:23.491343 0.400 MHz: ctrlr->f_min
9194 11:33:23.495265 0x40ff8080: ctrlr->voltages
9195 11:33:23.495368 sclk: 390625
9196 11:33:23.495455 Bus Width = 1
9197 11:33:23.498277 sclk: 390625
9198 11:33:23.498375 Bus Width = 1
9199 11:33:23.501257 Early init status = 3
9200 11:33:23.504834 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9201 11:33:23.508139 in-header: 03 fc 00 00 01 00 00 00
9202 11:33:23.511864 in-data: 00
9203 11:33:23.514876 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9204 11:33:23.519485 in-header: 03 fd 00 00 00 00 00 00
9205 11:33:23.522592 in-data:
9206 11:33:23.526035 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9207 11:33:23.529494 in-header: 03 fc 00 00 01 00 00 00
9208 11:33:23.532761 in-data: 00
9209 11:33:23.536206 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9210 11:33:23.540757 in-header: 03 fd 00 00 00 00 00 00
9211 11:33:23.543862 in-data:
9212 11:33:23.547755 [SSUSB] Setting up USB HOST controller...
9213 11:33:23.550376 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9214 11:33:23.553597 [SSUSB] phy power-on done.
9215 11:33:23.557036 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9216 11:33:23.563802 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9217 11:33:23.567140 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9218 11:33:23.573876 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9219 11:33:23.580356 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9220 11:33:23.587284 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9221 11:33:23.593121 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9222 11:33:23.599716 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9223 11:33:23.603398 SPM: binary array size = 0x9dc
9224 11:33:23.606345 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9225 11:33:23.613351 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9226 11:33:23.619816 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9227 11:33:23.625988 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9228 11:33:23.629311 configure_display: Starting display init
9229 11:33:23.664331 anx7625_power_on_init: Init interface.
9230 11:33:23.667236 anx7625_disable_pd_protocol: Disabled PD feature.
9231 11:33:23.670411 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9232 11:33:23.698201 anx7625_start_dp_work: Secure OCM version=00
9233 11:33:23.701577 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9234 11:33:23.716183 sp_tx_get_edid_block: EDID Block = 1
9235 11:33:23.819283 Extracted contents:
9236 11:33:23.822214 header: 00 ff ff ff ff ff ff 00
9237 11:33:23.825371 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9238 11:33:23.829050 version: 01 04
9239 11:33:23.831894 basic params: 95 1f 11 78 0a
9240 11:33:23.835538 chroma info: 76 90 94 55 54 90 27 21 50 54
9241 11:33:23.838511 established: 00 00 00
9242 11:33:23.845388 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9243 11:33:23.848482 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9244 11:33:23.855426 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9245 11:33:23.862035 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9246 11:33:23.868408 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9247 11:33:23.871654 extensions: 00
9248 11:33:23.871758 checksum: fb
9249 11:33:23.871847
9250 11:33:23.874881 Manufacturer: IVO Model 57d Serial Number 0
9251 11:33:23.878392 Made week 0 of 2020
9252 11:33:23.881676 EDID version: 1.4
9253 11:33:23.881765 Digital display
9254 11:33:23.884986 6 bits per primary color channel
9255 11:33:23.885083 DisplayPort interface
9256 11:33:23.888520 Maximum image size: 31 cm x 17 cm
9257 11:33:23.891511 Gamma: 220%
9258 11:33:23.891586 Check DPMS levels
9259 11:33:23.894789 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9260 11:33:23.901470 First detailed timing is preferred timing
9261 11:33:23.901547 Established timings supported:
9262 11:33:23.905296 Standard timings supported:
9263 11:33:23.908526 Detailed timings
9264 11:33:23.911628 Hex of detail: 383680a07038204018303c0035ae10000019
9265 11:33:23.918201 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9266 11:33:23.921233 0780 0798 07c8 0820 hborder 0
9267 11:33:23.925319 0438 043b 0447 0458 vborder 0
9268 11:33:23.928052 -hsync -vsync
9269 11:33:23.928152 Did detailed timing
9270 11:33:23.934467 Hex of detail: 000000000000000000000000000000000000
9271 11:33:23.937847 Manufacturer-specified data, tag 0
9272 11:33:23.941636 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9273 11:33:23.944506 ASCII string: InfoVision
9274 11:33:23.948475 Hex of detail: 000000fe00523134304e574635205248200a
9275 11:33:23.951219 ASCII string: R140NWF5 RH
9276 11:33:23.951316 Checksum
9277 11:33:23.954272 Checksum: 0xfb (valid)
9278 11:33:23.957771 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9279 11:33:23.960941 DSI data_rate: 832800000 bps
9280 11:33:23.967946 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9281 11:33:23.971084 anx7625_parse_edid: pixelclock(138800).
9282 11:33:23.974364 hactive(1920), hsync(48), hfp(24), hbp(88)
9283 11:33:23.977822 vactive(1080), vsync(12), vfp(3), vbp(17)
9284 11:33:23.981071 anx7625_dsi_config: config dsi.
9285 11:33:23.987429 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9286 11:33:24.001035 anx7625_dsi_config: success to config DSI
9287 11:33:24.004527 anx7625_dp_start: MIPI phy setup OK.
9288 11:33:24.007633 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9289 11:33:24.011112 mtk_ddp_mode_set invalid vrefresh 60
9290 11:33:24.014165 main_disp_path_setup
9291 11:33:24.014269 ovl_layer_smi_id_en
9292 11:33:24.017356 ovl_layer_smi_id_en
9293 11:33:24.017419 ccorr_config
9294 11:33:24.017473 aal_config
9295 11:33:24.020537 gamma_config
9296 11:33:24.020621 postmask_config
9297 11:33:24.024154 dither_config
9298 11:33:24.027600 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9299 11:33:24.033857 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9300 11:33:24.037309 Root Device init finished in 551 msecs
9301 11:33:24.040712 CPU_CLUSTER: 0 init
9302 11:33:24.047142 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9303 11:33:24.054073 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9304 11:33:24.054170 APU_MBOX 0x190000b0 = 0x10001
9305 11:33:24.056949 APU_MBOX 0x190001b0 = 0x10001
9306 11:33:24.060453 APU_MBOX 0x190005b0 = 0x10001
9307 11:33:24.063569 APU_MBOX 0x190006b0 = 0x10001
9308 11:33:24.070002 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9309 11:33:24.079787 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9310 11:33:24.092302 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9311 11:33:24.098841 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9312 11:33:24.110852 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9313 11:33:24.119981 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9314 11:33:24.123121 CPU_CLUSTER: 0 init finished in 81 msecs
9315 11:33:24.126198 Devices initialized
9316 11:33:24.129679 Show all devs... After init.
9317 11:33:24.129751 Root Device: enabled 1
9318 11:33:24.133088 CPU_CLUSTER: 0: enabled 1
9319 11:33:24.136252 CPU: 00: enabled 1
9320 11:33:24.139629 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9321 11:33:24.143023 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9322 11:33:24.145779 ELOG: NV offset 0x57f000 size 0x1000
9323 11:33:24.153395 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9324 11:33:24.159474 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9325 11:33:24.162945 ELOG: Event(17) added with size 13 at 2024-07-17 11:33:24 UTC
9326 11:33:24.169613 out: cmd=0x121: 03 db 21 01 00 00 00 00
9327 11:33:24.172518 in-header: 03 8d 00 00 2c 00 00 00
9328 11:33:24.182376 in-data: b1 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9329 11:33:24.189133 ELOG: Event(A1) added with size 10 at 2024-07-17 11:33:24 UTC
9330 11:33:24.195563 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9331 11:33:24.202539 ELOG: Event(A0) added with size 9 at 2024-07-17 11:33:24 UTC
9332 11:33:24.205799 elog_add_boot_reason: Logged dev mode boot
9333 11:33:24.211963 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9334 11:33:24.212063 Finalize devices...
9335 11:33:24.215558 Devices finalized
9336 11:33:24.218741 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9337 11:33:24.221798 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9338 11:33:24.225142 in-header: 03 07 00 00 08 00 00 00
9339 11:33:24.228473 in-data: aa e4 47 04 13 02 00 00
9340 11:33:24.232175 Chrome EC: UHEPI supported
9341 11:33:24.238315 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9342 11:33:24.241924 in-header: 03 a9 00 00 08 00 00 00
9343 11:33:24.245569 in-data: 84 60 60 08 00 00 00 00
9344 11:33:24.251595 ELOG: Event(91) added with size 10 at 2024-07-17 11:33:24 UTC
9345 11:33:24.254971 Chrome EC: clear events_b mask to 0x0000000020004000
9346 11:33:24.261680 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9347 11:33:24.265550 in-header: 03 fd 00 00 00 00 00 00
9348 11:33:24.268749 in-data:
9349 11:33:24.272065 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9350 11:33:24.275622 Writing coreboot table at 0xffe64000
9351 11:33:24.281932 0. 000000000010a000-0000000000113fff: RAMSTAGE
9352 11:33:24.285347 1. 0000000040000000-00000000400fffff: RAM
9353 11:33:24.288534 2. 0000000040100000-000000004032afff: RAMSTAGE
9354 11:33:24.291961 3. 000000004032b000-00000000545fffff: RAM
9355 11:33:24.295624 4. 0000000054600000-000000005465ffff: BL31
9356 11:33:24.298766 5. 0000000054660000-00000000ffe63fff: RAM
9357 11:33:24.304955 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9358 11:33:24.308591 7. 0000000100000000-000000023fffffff: RAM
9359 11:33:24.311698 Passing 5 GPIOs to payload:
9360 11:33:24.315124 NAME | PORT | POLARITY | VALUE
9361 11:33:24.321869 EC in RW | 0x000000aa | low | undefined
9362 11:33:24.324850 EC interrupt | 0x00000005 | low | undefined
9363 11:33:24.331671 TPM interrupt | 0x000000ab | high | undefined
9364 11:33:24.335008 SD card detect | 0x00000011 | high | undefined
9365 11:33:24.338167 speaker enable | 0x00000093 | high | undefined
9366 11:33:24.341574 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9367 11:33:24.345241 in-header: 03 f9 00 00 02 00 00 00
9368 11:33:24.348446 in-data: 02 00
9369 11:33:24.352140 ADC[4]: Raw value=901847 ID=7
9370 11:33:24.354989 ADC[3]: Raw value=213916 ID=1
9371 11:33:24.355068 RAM Code: 0x71
9372 11:33:24.358383 ADC[6]: Raw value=74630 ID=0
9373 11:33:24.361597 ADC[5]: Raw value=213546 ID=1
9374 11:33:24.361686 SKU Code: 0x1
9375 11:33:24.368013 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 812f
9376 11:33:24.368119 coreboot table: 964 bytes.
9377 11:33:24.371585 IMD ROOT 0. 0xfffff000 0x00001000
9378 11:33:24.374786 IMD SMALL 1. 0xffffe000 0x00001000
9379 11:33:24.377757 RO MCACHE 2. 0xffffc000 0x00001104
9380 11:33:24.381408 CONSOLE 3. 0xfff7c000 0x00080000
9381 11:33:24.384929 FMAP 4. 0xfff7b000 0x00000452
9382 11:33:24.387737 TIME STAMP 5. 0xfff7a000 0x00000910
9383 11:33:24.391366 VBOOT WORK 6. 0xfff66000 0x00014000
9384 11:33:24.394443 RAMOOPS 7. 0xffe66000 0x00100000
9385 11:33:24.398109 COREBOOT 8. 0xffe64000 0x00002000
9386 11:33:24.400971 IMD small region:
9387 11:33:24.404455 IMD ROOT 0. 0xffffec00 0x00000400
9388 11:33:24.407432 VPD 1. 0xffffeb80 0x0000006c
9389 11:33:24.411093 MMC STATUS 2. 0xffffeb60 0x00000004
9390 11:33:24.417573 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9391 11:33:24.424226 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9392 11:33:24.462509 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9393 11:33:24.466083 Checking segment from ROM address 0x40100000
9394 11:33:24.469183 Checking segment from ROM address 0x4010001c
9395 11:33:24.475791 Loading segment from ROM address 0x40100000
9396 11:33:24.475866 code (compression=0)
9397 11:33:24.485984 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9398 11:33:24.492203 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9399 11:33:24.492294 it's not compressed!
9400 11:33:24.498659 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9401 11:33:24.505214 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9402 11:33:24.523074 Loading segment from ROM address 0x4010001c
9403 11:33:24.523151 Entry Point 0x80000000
9404 11:33:24.526246 Loaded segments
9405 11:33:24.529794 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9406 11:33:24.536277 Jumping to boot code at 0x80000000(0xffe64000)
9407 11:33:24.542762 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9408 11:33:24.549110 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9409 11:33:24.557600 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9410 11:33:24.561034 Checking segment from ROM address 0x40100000
9411 11:33:24.564184 Checking segment from ROM address 0x4010001c
9412 11:33:24.570490 Loading segment from ROM address 0x40100000
9413 11:33:24.570582 code (compression=1)
9414 11:33:24.577002 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9415 11:33:24.587110 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9416 11:33:24.587243 using LZMA
9417 11:33:24.595753 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9418 11:33:24.602401 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9419 11:33:24.605966 Loading segment from ROM address 0x4010001c
9420 11:33:24.606043 Entry Point 0x54601000
9421 11:33:24.609176 Loaded segments
9422 11:33:24.611958 NOTICE: MT8192 bl31_setup
9423 11:33:24.619590 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9424 11:33:24.622528 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9425 11:33:24.625940 WARNING: region 0:
9426 11:33:24.629412 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9427 11:33:24.629525 WARNING: region 1:
9428 11:33:24.635492 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9429 11:33:24.639153 WARNING: region 2:
9430 11:33:24.642089 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9431 11:33:24.645748 WARNING: region 3:
9432 11:33:24.652034 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9433 11:33:24.652135 WARNING: region 4:
9434 11:33:24.659030 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9435 11:33:24.659110 WARNING: region 5:
9436 11:33:24.662069 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 11:33:24.665878 WARNING: region 6:
9438 11:33:24.668487 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 11:33:24.671915 WARNING: region 7:
9440 11:33:24.675344 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 11:33:24.681688 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9442 11:33:24.685310 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9443 11:33:24.691734 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9444 11:33:24.695307 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9445 11:33:24.698250 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9446 11:33:24.704794 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9447 11:33:24.708175 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9448 11:33:24.711801 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9449 11:33:24.717927 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9450 11:33:24.721191 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9451 11:33:24.727725 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9452 11:33:24.730970 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9453 11:33:24.734671 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9454 11:33:24.741252 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9455 11:33:24.744495 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9456 11:33:24.750983 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9457 11:33:24.754004 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9458 11:33:24.757338 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9459 11:33:24.763928 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9460 11:33:24.768047 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9461 11:33:24.774490 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9462 11:33:24.777567 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9463 11:33:24.780871 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9464 11:33:24.787460 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9465 11:33:24.790857 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9466 11:33:24.797251 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9467 11:33:24.800179 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9468 11:33:24.803516 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9469 11:33:24.810207 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9470 11:33:24.813358 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9471 11:33:24.820394 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9472 11:33:24.823488 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9473 11:33:24.826363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9474 11:33:24.833321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9475 11:33:24.836804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9476 11:33:24.839731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9477 11:33:24.843299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9478 11:33:24.849643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9479 11:33:24.853087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9480 11:33:24.856229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9481 11:33:24.859611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9482 11:33:24.865913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9483 11:33:24.869570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9484 11:33:24.872776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9485 11:33:24.879419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9486 11:33:24.882302 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9487 11:33:24.885850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9488 11:33:24.889065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9489 11:33:24.896027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9490 11:33:24.898861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9491 11:33:24.905594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9492 11:33:24.908793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9493 11:33:24.915245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9494 11:33:24.918509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9495 11:33:24.921917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9496 11:33:24.928490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9497 11:33:24.931961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9498 11:33:24.938949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9499 11:33:24.941980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9500 11:33:24.948804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9501 11:33:24.952286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9502 11:33:24.958173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9503 11:33:24.961634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9504 11:33:24.968092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9505 11:33:24.971301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9506 11:33:24.975324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9507 11:33:24.981107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9508 11:33:24.984825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9509 11:33:24.991421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9510 11:33:24.994319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9511 11:33:25.001126 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9512 11:33:25.004689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9513 11:33:25.011571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9514 11:33:25.014632 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9515 11:33:25.017572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9516 11:33:25.024395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9517 11:33:25.027595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9518 11:33:25.033972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9519 11:33:25.037518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9520 11:33:25.044168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9521 11:33:25.047001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9522 11:33:25.054117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9523 11:33:25.057230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9524 11:33:25.060258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9525 11:33:25.067316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9526 11:33:25.070293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9527 11:33:25.076807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9528 11:33:25.080263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9529 11:33:25.086711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9530 11:33:25.090166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9531 11:33:25.096888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9532 11:33:25.099828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9533 11:33:25.103293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9534 11:33:25.110198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9535 11:33:25.113560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9536 11:33:25.120144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9537 11:33:25.123074 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9538 11:33:25.126640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9539 11:33:25.132974 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9540 11:33:25.136821 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9541 11:33:25.139608 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9542 11:33:25.146831 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9543 11:33:25.149393 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9544 11:33:25.152890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9545 11:33:25.159524 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9546 11:33:25.163093 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9547 11:33:25.169726 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9548 11:33:25.172713 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9549 11:33:25.176268 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9550 11:33:25.182589 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9551 11:33:25.185662 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9552 11:33:25.193046 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9553 11:33:25.195587 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9554 11:33:25.202505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9555 11:33:25.205623 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9556 11:33:25.209048 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9557 11:33:25.212036 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9558 11:33:25.218624 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9559 11:33:25.221938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9560 11:33:25.225362 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9561 11:33:25.231764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9562 11:33:25.235409 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9563 11:33:25.239056 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9564 11:33:25.245257 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9565 11:33:25.248658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9566 11:33:25.252017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9567 11:33:25.258467 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9568 11:33:25.261671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9569 11:33:25.268627 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9570 11:33:25.271564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9571 11:33:25.275104 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9572 11:33:25.281754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9573 11:33:25.284593 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9574 11:33:25.291133 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9575 11:33:25.294455 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9576 11:33:25.297884 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9577 11:33:25.304398 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9578 11:33:25.307951 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9579 11:33:25.314434 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9580 11:33:25.317720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9581 11:33:25.320918 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9582 11:33:25.327723 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9583 11:33:25.330641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9584 11:33:25.337550 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9585 11:33:25.340633 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9586 11:33:25.344189 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9587 11:33:25.350448 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9588 11:33:25.354049 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9589 11:33:25.360560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9590 11:33:25.364067 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9591 11:33:25.367445 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9592 11:33:25.373676 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9593 11:33:25.376992 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9594 11:33:25.383941 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9595 11:33:25.387072 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9596 11:33:25.390982 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9597 11:33:25.396691 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9598 11:33:25.400116 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9599 11:33:25.406968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9600 11:33:25.410154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9601 11:33:25.413104 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9602 11:33:25.419692 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9603 11:33:25.423437 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9604 11:33:25.429695 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9605 11:33:25.433381 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9606 11:33:25.436447 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9607 11:33:25.442683 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9608 11:33:25.446196 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9609 11:33:25.453265 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9610 11:33:25.456258 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9611 11:33:25.459119 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9612 11:33:25.465661 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9613 11:33:25.469250 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9614 11:33:25.475677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9615 11:33:25.478836 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9616 11:33:25.482145 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9617 11:33:25.488957 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9618 11:33:25.492096 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9619 11:33:25.499277 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9620 11:33:25.501989 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9621 11:33:25.505565 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9622 11:33:25.512162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9623 11:33:25.515162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9624 11:33:25.521789 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9625 11:33:25.525209 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9626 11:33:25.528665 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9627 11:33:25.535203 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9628 11:33:25.538194 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9629 11:33:25.544789 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9630 11:33:25.548589 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9631 11:33:25.554662 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9632 11:33:25.558002 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9633 11:33:25.561645 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9634 11:33:25.567915 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9635 11:33:25.571644 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9636 11:33:25.577945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9637 11:33:25.581150 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9638 11:33:25.587946 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9639 11:33:25.590917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9640 11:33:25.594675 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9641 11:33:25.600999 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9642 11:33:25.604228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9643 11:33:25.610772 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9644 11:33:25.614055 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9645 11:33:25.620484 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9646 11:33:25.624201 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9647 11:33:25.627603 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9648 11:33:25.634174 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9649 11:33:25.637053 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9650 11:33:25.643799 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9651 11:33:25.647336 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9652 11:33:25.650378 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9653 11:33:25.657007 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9654 11:33:25.660207 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9655 11:33:25.666925 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9656 11:33:25.670480 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9657 11:33:25.676752 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9658 11:33:25.680190 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9659 11:33:25.683359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9660 11:33:25.690389 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9661 11:33:25.693266 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9662 11:33:25.699693 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9663 11:33:25.703064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9664 11:33:25.710026 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9665 11:33:25.713382 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9666 11:33:25.716695 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9667 11:33:25.722807 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9668 11:33:25.726252 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9669 11:33:25.733133 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9670 11:33:25.736192 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9671 11:33:25.739976 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9672 11:33:25.743220 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9673 11:33:25.749513 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9674 11:33:25.752936 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9675 11:33:25.756069 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9676 11:33:25.763102 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9677 11:33:25.766075 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9678 11:33:25.769429 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9679 11:33:25.775986 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9680 11:33:25.779095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9681 11:33:25.785590 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9682 11:33:25.789454 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9683 11:33:25.793020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9684 11:33:25.799045 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9685 11:33:25.802347 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9686 11:33:25.805453 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9687 11:33:25.812432 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9688 11:33:25.815455 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9689 11:33:25.818846 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9690 11:33:25.825026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9691 11:33:25.828912 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9692 11:33:25.835036 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9693 11:33:25.838040 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9694 11:33:25.841593 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9695 11:33:25.848468 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9696 11:33:25.851785 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9697 11:33:25.858393 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9698 11:33:25.861249 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9699 11:33:25.864782 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9700 11:33:25.871311 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9701 11:33:25.874843 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9702 11:33:25.877839 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9703 11:33:25.884780 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9704 11:33:25.887652 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9705 11:33:25.894043 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9706 11:33:25.897593 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9707 11:33:25.901012 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9708 11:33:25.907468 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9709 11:33:25.910492 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9710 11:33:25.913992 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9711 11:33:25.917495 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9712 11:33:25.923944 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9713 11:33:25.927562 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9714 11:33:25.930565 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9715 11:33:25.933652 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9716 11:33:25.940814 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9717 11:33:25.943902 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9718 11:33:25.947439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9719 11:33:25.950297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9720 11:33:25.956918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9721 11:33:25.960238 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9722 11:33:25.963621 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9723 11:33:25.970208 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9724 11:33:25.973231 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9725 11:33:25.979834 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9726 11:33:25.983369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9727 11:33:25.990128 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9728 11:33:25.993322 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9729 11:33:25.996301 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9730 11:33:26.003254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9731 11:33:26.006844 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9732 11:33:26.013123 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9733 11:33:26.016813 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9734 11:33:26.019829 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9735 11:33:26.026111 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9736 11:33:26.029437 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9737 11:33:26.035872 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9738 11:33:26.039971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9739 11:33:26.042510 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9740 11:33:26.049534 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9741 11:33:26.052895 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9742 11:33:26.058803 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9743 11:33:26.062480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9744 11:33:26.069063 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9745 11:33:26.072706 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9746 11:33:26.075470 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9747 11:33:26.082173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9748 11:33:26.085989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9749 11:33:26.092095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9750 11:33:26.095591 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9751 11:33:26.102041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9752 11:33:26.105009 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9753 11:33:26.108217 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9754 11:33:26.114869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9755 11:33:26.118410 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9756 11:33:26.124810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9757 11:33:26.128201 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9758 11:33:26.131559 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9759 11:33:26.137818 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9760 11:33:26.141757 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9761 11:33:26.147723 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9762 11:33:26.151520 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9763 11:33:26.157856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9764 11:33:26.161445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9765 11:33:26.164672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9766 11:33:26.171433 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9767 11:33:26.174069 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9768 11:33:26.181041 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9769 11:33:26.184086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9770 11:33:26.187613 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9771 11:33:26.194511 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9772 11:33:26.197667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9773 11:33:26.203776 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9774 11:33:26.207057 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9775 11:33:26.213767 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9776 11:33:26.217025 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9777 11:33:26.220357 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9778 11:33:26.226976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9779 11:33:26.230524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9780 11:33:26.236986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9781 11:33:26.240150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9782 11:33:26.247028 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9783 11:33:26.250370 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9784 11:33:26.253712 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9785 11:33:26.260438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9786 11:33:26.263297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9787 11:33:26.270038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9788 11:33:26.273142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9789 11:33:26.276797 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9790 11:33:26.283426 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9791 11:33:26.286759 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9792 11:33:26.293055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9793 11:33:26.296706 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9794 11:33:26.299683 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9795 11:33:26.306109 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9796 11:33:26.310142 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9797 11:33:26.316016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9798 11:33:26.319838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9799 11:33:26.326711 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9800 11:33:26.329507 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9801 11:33:26.336122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9802 11:33:26.339098 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9803 11:33:26.342545 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9804 11:33:26.349002 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9805 11:33:26.352514 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9806 11:33:26.359172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9807 11:33:26.362200 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9808 11:33:26.369091 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9809 11:33:26.372310 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9810 11:33:26.379131 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9811 11:33:26.382033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9812 11:33:26.385539 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9813 11:33:26.391760 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9814 11:33:26.395271 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9815 11:33:26.402077 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9816 11:33:26.405677 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9817 11:33:26.411912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9818 11:33:26.414924 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9819 11:33:26.421954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9820 11:33:26.425320 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9821 11:33:26.428352 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9822 11:33:26.434933 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9823 11:33:26.438270 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9824 11:33:26.444769 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9825 11:33:26.447849 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9826 11:33:26.454779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9827 11:33:26.458243 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9828 11:33:26.464471 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9829 11:33:26.468147 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9830 11:33:26.471048 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9831 11:33:26.477649 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9832 11:33:26.481201 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9833 11:33:26.487657 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9834 11:33:26.491161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9835 11:33:26.497822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9836 11:33:26.501072 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9837 11:33:26.507776 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9838 11:33:26.510764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9839 11:33:26.513769 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9840 11:33:26.520574 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9841 11:33:26.524224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9842 11:33:26.530373 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9843 11:33:26.533816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9844 11:33:26.537314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9845 11:33:26.544102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9846 11:33:26.546756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9847 11:33:26.553535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9848 11:33:26.557086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9849 11:33:26.563695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9850 11:33:26.566862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9851 11:33:26.573381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9852 11:33:26.576988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9853 11:33:26.583659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9854 11:33:26.587002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9855 11:33:26.593164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9856 11:33:26.596562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9857 11:33:26.603241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9858 11:33:26.606280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9859 11:33:26.613259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9860 11:33:26.616250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9861 11:33:26.622881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9862 11:33:26.626377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9863 11:33:26.632992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9864 11:33:26.636181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9865 11:33:26.642848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9866 11:33:26.646531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9867 11:33:26.652893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9868 11:33:26.656132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9869 11:33:26.662553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9870 11:33:26.666047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9871 11:33:26.672686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9872 11:33:26.675748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9873 11:33:26.682640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9874 11:33:26.685962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9875 11:33:26.692612 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9876 11:33:26.692692 INFO: [APUAPC] vio 0
9877 11:33:26.699417 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9878 11:33:26.702687 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9879 11:33:26.706010 INFO: [APUAPC] D0_APC_0: 0x400510
9880 11:33:26.709061 INFO: [APUAPC] D0_APC_1: 0x0
9881 11:33:26.712442 INFO: [APUAPC] D0_APC_2: 0x1540
9882 11:33:26.716064 INFO: [APUAPC] D0_APC_3: 0x0
9883 11:33:26.719093 INFO: [APUAPC] D1_APC_0: 0xffffffff
9884 11:33:26.722046 INFO: [APUAPC] D1_APC_1: 0xffffffff
9885 11:33:26.725470 INFO: [APUAPC] D1_APC_2: 0x3fffff
9886 11:33:26.728894 INFO: [APUAPC] D1_APC_3: 0x0
9887 11:33:26.731878 INFO: [APUAPC] D2_APC_0: 0xffffffff
9888 11:33:26.735526 INFO: [APUAPC] D2_APC_1: 0xffffffff
9889 11:33:26.738453 INFO: [APUAPC] D2_APC_2: 0x3fffff
9890 11:33:26.741976 INFO: [APUAPC] D2_APC_3: 0x0
9891 11:33:26.745260 INFO: [APUAPC] D3_APC_0: 0xffffffff
9892 11:33:26.748420 INFO: [APUAPC] D3_APC_1: 0xffffffff
9893 11:33:26.752359 INFO: [APUAPC] D3_APC_2: 0x3fffff
9894 11:33:26.755268 INFO: [APUAPC] D3_APC_3: 0x0
9895 11:33:26.758474 INFO: [APUAPC] D4_APC_0: 0xffffffff
9896 11:33:26.762340 INFO: [APUAPC] D4_APC_1: 0xffffffff
9897 11:33:26.765824 INFO: [APUAPC] D4_APC_2: 0x3fffff
9898 11:33:26.768298 INFO: [APUAPC] D4_APC_3: 0x0
9899 11:33:26.771768 INFO: [APUAPC] D5_APC_0: 0xffffffff
9900 11:33:26.774662 INFO: [APUAPC] D5_APC_1: 0xffffffff
9901 11:33:26.778156 INFO: [APUAPC] D5_APC_2: 0x3fffff
9902 11:33:26.781065 INFO: [APUAPC] D5_APC_3: 0x0
9903 11:33:26.784445 INFO: [APUAPC] D6_APC_0: 0xffffffff
9904 11:33:26.787824 INFO: [APUAPC] D6_APC_1: 0xffffffff
9905 11:33:26.791281 INFO: [APUAPC] D6_APC_2: 0x3fffff
9906 11:33:26.794681 INFO: [APUAPC] D6_APC_3: 0x0
9907 11:33:26.797533 INFO: [APUAPC] D7_APC_0: 0xffffffff
9908 11:33:26.801202 INFO: [APUAPC] D7_APC_1: 0xffffffff
9909 11:33:26.804743 INFO: [APUAPC] D7_APC_2: 0x3fffff
9910 11:33:26.808152 INFO: [APUAPC] D7_APC_3: 0x0
9911 11:33:26.811083 INFO: [APUAPC] D8_APC_0: 0xffffffff
9912 11:33:26.814371 INFO: [APUAPC] D8_APC_1: 0xffffffff
9913 11:33:26.817776 INFO: [APUAPC] D8_APC_2: 0x3fffff
9914 11:33:26.817851 INFO: [APUAPC] D8_APC_3: 0x0
9915 11:33:26.823889 INFO: [APUAPC] D9_APC_0: 0xffffffff
9916 11:33:26.827126 INFO: [APUAPC] D9_APC_1: 0xffffffff
9917 11:33:26.830526 INFO: [APUAPC] D9_APC_2: 0x3fffff
9918 11:33:26.830629 INFO: [APUAPC] D9_APC_3: 0x0
9919 11:33:26.837203 INFO: [APUAPC] D10_APC_0: 0xffffffff
9920 11:33:26.840763 INFO: [APUAPC] D10_APC_1: 0xffffffff
9921 11:33:26.843700 INFO: [APUAPC] D10_APC_2: 0x3fffff
9922 11:33:26.843775 INFO: [APUAPC] D10_APC_3: 0x0
9923 11:33:26.850475 INFO: [APUAPC] D11_APC_0: 0xffffffff
9924 11:33:26.853821 INFO: [APUAPC] D11_APC_1: 0xffffffff
9925 11:33:26.857106 INFO: [APUAPC] D11_APC_2: 0x3fffff
9926 11:33:26.860564 INFO: [APUAPC] D11_APC_3: 0x0
9927 11:33:26.863670 INFO: [APUAPC] D12_APC_0: 0xffffffff
9928 11:33:26.866939 INFO: [APUAPC] D12_APC_1: 0xffffffff
9929 11:33:26.870284 INFO: [APUAPC] D12_APC_2: 0x3fffff
9930 11:33:26.873945 INFO: [APUAPC] D12_APC_3: 0x0
9931 11:33:26.876865 INFO: [APUAPC] D13_APC_0: 0xffffffff
9932 11:33:26.880519 INFO: [APUAPC] D13_APC_1: 0xffffffff
9933 11:33:26.883635 INFO: [APUAPC] D13_APC_2: 0x3fffff
9934 11:33:26.886930 INFO: [APUAPC] D13_APC_3: 0x0
9935 11:33:26.890263 INFO: [APUAPC] D14_APC_0: 0xffffffff
9936 11:33:26.893813 INFO: [APUAPC] D14_APC_1: 0xffffffff
9937 11:33:26.896651 INFO: [APUAPC] D14_APC_2: 0x3fffff
9938 11:33:26.899909 INFO: [APUAPC] D14_APC_3: 0x0
9939 11:33:26.903273 INFO: [APUAPC] D15_APC_0: 0xffffffff
9940 11:33:26.906910 INFO: [APUAPC] D15_APC_1: 0xffffffff
9941 11:33:26.910370 INFO: [APUAPC] D15_APC_2: 0x3fffff
9942 11:33:26.913080 INFO: [APUAPC] D15_APC_3: 0x0
9943 11:33:26.916366 INFO: [APUAPC] APC_CON: 0x4
9944 11:33:26.916444 INFO: [NOCDAPC] D0_APC_0: 0x0
9945 11:33:26.919819 INFO: [NOCDAPC] D0_APC_1: 0x0
9946 11:33:26.923232 INFO: [NOCDAPC] D1_APC_0: 0x0
9947 11:33:26.926473 INFO: [NOCDAPC] D1_APC_1: 0xfff
9948 11:33:26.929886 INFO: [NOCDAPC] D2_APC_0: 0x0
9949 11:33:26.933383 INFO: [NOCDAPC] D2_APC_1: 0xfff
9950 11:33:26.936508 INFO: [NOCDAPC] D3_APC_0: 0x0
9951 11:33:26.939904 INFO: [NOCDAPC] D3_APC_1: 0xfff
9952 11:33:26.943463 INFO: [NOCDAPC] D4_APC_0: 0x0
9953 11:33:26.946554 INFO: [NOCDAPC] D4_APC_1: 0xfff
9954 11:33:26.946633 INFO: [NOCDAPC] D5_APC_0: 0x0
9955 11:33:26.950006 INFO: [NOCDAPC] D5_APC_1: 0xfff
9956 11:33:26.953016 INFO: [NOCDAPC] D6_APC_0: 0x0
9957 11:33:26.956430 INFO: [NOCDAPC] D6_APC_1: 0xfff
9958 11:33:26.959760 INFO: [NOCDAPC] D7_APC_0: 0x0
9959 11:33:26.963005 INFO: [NOCDAPC] D7_APC_1: 0xfff
9960 11:33:26.966145 INFO: [NOCDAPC] D8_APC_0: 0x0
9961 11:33:26.969524 INFO: [NOCDAPC] D8_APC_1: 0xfff
9962 11:33:26.972574 INFO: [NOCDAPC] D9_APC_0: 0x0
9963 11:33:26.976476 INFO: [NOCDAPC] D9_APC_1: 0xfff
9964 11:33:26.979365 INFO: [NOCDAPC] D10_APC_0: 0x0
9965 11:33:26.983021 INFO: [NOCDAPC] D10_APC_1: 0xfff
9966 11:33:26.985965 INFO: [NOCDAPC] D11_APC_0: 0x0
9967 11:33:26.989421 INFO: [NOCDAPC] D11_APC_1: 0xfff
9968 11:33:26.989499 INFO: [NOCDAPC] D12_APC_0: 0x0
9969 11:33:26.992427 INFO: [NOCDAPC] D12_APC_1: 0xfff
9970 11:33:26.995881 INFO: [NOCDAPC] D13_APC_0: 0x0
9971 11:33:26.999307 INFO: [NOCDAPC] D13_APC_1: 0xfff
9972 11:33:27.002550 INFO: [NOCDAPC] D14_APC_0: 0x0
9973 11:33:27.005598 INFO: [NOCDAPC] D14_APC_1: 0xfff
9974 11:33:27.008837 INFO: [NOCDAPC] D15_APC_0: 0x0
9975 11:33:27.012084 INFO: [NOCDAPC] D15_APC_1: 0xfff
9976 11:33:27.015675 INFO: [NOCDAPC] APC_CON: 0x4
9977 11:33:27.018731 INFO: [APUAPC] set_apusys_apc done
9978 11:33:27.022446 INFO: [DEVAPC] devapc_init done
9979 11:33:27.025575 INFO: GICv3 without legacy support detected.
9980 11:33:27.028923 INFO: ARM GICv3 driver initialized in EL3
9981 11:33:27.032171 INFO: Maximum SPI INTID supported: 639
9982 11:33:27.038687 INFO: BL31: Initializing runtime services
9983 11:33:27.042177 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9984 11:33:27.045177 INFO: SPM: enable CPC mode
9985 11:33:27.051688 INFO: mcdi ready for mcusys-off-idle and system suspend
9986 11:33:27.055304 INFO: BL31: Preparing for EL3 exit to normal world
9987 11:33:27.058153 INFO: Entry point address = 0x80000000
9988 11:33:27.061179 INFO: SPSR = 0x8
9989 11:33:27.067101
9990 11:33:27.067178
9991 11:33:27.067256
9992 11:33:27.070468 Starting depthcharge on Spherion...
9993 11:33:27.070545
9994 11:33:27.070622 Wipe memory regions:
9995 11:33:27.070695
9996 11:33:27.071333 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
9997 11:33:27.071468 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
9998 11:33:27.071598 Setting prompt string to ['asurada:']
9999 11:33:27.071712 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10000 11:33:27.073773 [0x00000040000000, 0x00000054600000)
10001 11:33:27.196125
10002 11:33:27.196226 [0x00000054660000, 0x00000080000000)
10003 11:33:27.456981
10004 11:33:27.457096 [0x000000821a7280, 0x000000ffe64000)
10005 11:33:28.201967
10006 11:33:28.202119 [0x00000100000000, 0x00000240000000)
10007 11:33:30.092479
10008 11:33:30.095388 Initializing XHCI USB controller at 0x11200000.
10009 11:33:31.134247
10010 11:33:31.137183 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10011 11:33:31.137699
10012 11:33:31.138124
10013 11:33:31.139034 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10014 11:33:31.139599 Sending line: 'tftpboot 192.168.201.1 14864586/tftp-deploy-tnkxt4xu/kernel/image.itb 14864586/tftp-deploy-tnkxt4xu/kernel/cmdline '
10016 11:33:31.240421 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10017 11:33:31.240497 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10018 11:33:31.244631 asurada: tftpboot 192.168.201.1 14864586/tftp-deploy-tnkxt4xu/kernel/image.itp-deploy-tnkxt4xu/kernel/cmdline
10019 11:33:31.244715
10020 11:33:31.244773 Waiting for link
10021 11:33:31.403414
10022 11:33:31.403824 R8152: Initializing
10023 11:33:31.404123
10024 11:33:31.406918 Version 6 (ocp_data = 5c30)
10025 11:33:31.407303
10026 11:33:31.410123 R8152: Done initializing
10027 11:33:31.410506
10028 11:33:31.410806 Adding net device
10029 11:33:33.375344
10030 11:33:33.375765 done.
10031 11:33:33.376065
10032 11:33:33.376342 MAC: 00:24:32:30:7c:7b
10033 11:33:33.376612
10034 11:33:33.378917 Sending DHCP discover... done.
10035 11:33:33.379298
10036 11:33:33.381757 Waiting for reply... done.
10037 11:33:33.382141
10038 11:33:33.385240 Sending DHCP request... done.
10039 11:33:33.385631
10040 11:33:33.385932 Waiting for reply... done.
10041 11:33:33.386214
10042 11:33:33.388679 My ip is 192.168.201.14
10043 11:33:33.389211
10044 11:33:33.391680 The DHCP server ip is 192.168.201.1
10045 11:33:33.392064
10046 11:33:33.394850 TFTP server IP predefined by user: 192.168.201.1
10047 11:33:33.395249
10048 11:33:33.401590 Bootfile predefined by user: 14864586/tftp-deploy-tnkxt4xu/kernel/image.itb
10049 11:33:33.401990
10050 11:33:33.405275 Sending tftp read request... done.
10051 11:33:33.405678
10052 11:33:33.414880 Waiting for the transfer...
10053 11:33:33.415284
10054 11:33:34.092149 00000000 ################################################################
10055 11:33:34.092603
10056 11:33:34.770588 00080000 ################################################################
10057 11:33:34.771050
10058 11:33:35.441294 00100000 ################################################################
10059 11:33:35.441750
10060 11:33:36.109467 00180000 ################################################################
10061 11:33:36.109941
10062 11:33:36.742666 00200000 ################################################################
10063 11:33:36.742792
10064 11:33:37.351657 00280000 ################################################################
10065 11:33:37.351783
10066 11:33:37.951641 00300000 ################################################################
10067 11:33:37.951762
10068 11:33:38.596620 00380000 ################################################################
10069 11:33:38.596746
10070 11:33:39.301996 00400000 ################################################################
10071 11:33:39.302481
10072 11:33:39.998129 00480000 ################################################################
10073 11:33:39.998571
10074 11:33:40.690305 00500000 ################################################################
10075 11:33:40.690769
10076 11:33:41.333468 00580000 ################################################################
10077 11:33:41.333689
10078 11:33:41.985486 00600000 ################################################################
10079 11:33:41.986100
10080 11:33:42.674841 00680000 ################################################################
10081 11:33:42.675305
10082 11:33:43.331798 00700000 ################################################################
10083 11:33:43.332240
10084 11:33:43.955887 00780000 ################################################################
10085 11:33:43.956243
10086 11:33:44.606344 00800000 ################################################################
10087 11:33:44.606542
10088 11:33:45.286468 00880000 ################################################################
10089 11:33:45.286923
10090 11:33:45.991898 00900000 ################################################################
10091 11:33:45.992421
10092 11:33:46.705341 00980000 ################################################################
10093 11:33:46.705788
10094 11:33:47.300923 00a00000 ################################################################
10095 11:33:47.301051
10096 11:33:47.886007 00a80000 ################################################################
10097 11:33:47.886133
10098 11:33:48.554316 00b00000 ################################################################
10099 11:33:48.554466
10100 11:33:49.248185 00b80000 ################################################################
10101 11:33:49.248657
10102 11:33:49.954303 00c00000 ################################################################
10103 11:33:49.954835
10104 11:33:50.616171 00c80000 ################################################################
10105 11:33:50.616287
10106 11:33:51.277432 00d00000 ################################################################
10107 11:33:51.278033
10108 11:33:52.015136 00d80000 ################################################################
10109 11:33:52.015262
10110 11:33:52.716143 00e00000 ################################################################
10111 11:33:52.716259
10112 11:33:53.312854 00e80000 ################################################################
10113 11:33:53.312996
10114 11:33:53.887708 00f00000 ################################################################
10115 11:33:53.887822
10116 11:33:54.490723 00f80000 ################################################################
10117 11:33:54.490839
10118 11:33:55.119147 01000000 ################################################################
10119 11:33:55.119586
10120 11:33:55.714329 01080000 ################################################################
10121 11:33:55.714823
10122 11:33:56.393168 01100000 ################################################################
10123 11:33:56.393284
10124 11:33:56.963737 01180000 ################################################################
10125 11:33:56.963874
10126 11:33:57.520505 01200000 ################################################################
10127 11:33:57.520641
10128 11:33:58.113898 01280000 ################################################################
10129 11:33:58.114428
10130 11:33:58.779956 01300000 ################################################################
10131 11:33:58.780474
10132 11:33:59.454099 01380000 ################################################################
10133 11:33:59.454596
10134 11:34:00.013770 01400000 ################################################################
10135 11:34:00.013920
10136 11:34:00.564481 01480000 ################################################################
10137 11:34:00.564597
10138 11:34:01.150109 01500000 ################################################################
10139 11:34:01.150230
10140 11:34:01.812948 01580000 ################################################################
10141 11:34:01.813437
10142 11:34:02.509638 01600000 ################################################################
10143 11:34:02.510122
10144 11:34:03.217918 01680000 ################################################################
10145 11:34:03.218477
10146 11:34:03.870626 01700000 ################################################################
10147 11:34:03.871128
10148 11:34:04.497565 01780000 ################################################################
10149 11:34:04.498052
10150 11:34:05.174906 01800000 ################################################################
10151 11:34:05.175373
10152 11:34:05.862231 01880000 ################################################################
10153 11:34:05.862689
10154 11:34:06.562823 01900000 ################################################################
10155 11:34:06.563484
10156 11:34:07.254034 01980000 ################################################################
10157 11:34:07.254146
10158 11:34:07.850033 01a00000 ################################################################
10159 11:34:07.850618
10160 11:34:08.551747 01a80000 ################################################################
10161 11:34:08.552212
10162 11:34:09.253966 01b00000 ################################################################
10163 11:34:09.254444
10164 11:34:09.961590 01b80000 ################################################################
10165 11:34:09.962070
10166 11:34:10.671767 01c00000 ################################################################
10167 11:34:10.672254
10168 11:34:11.371978 01c80000 ################################################################
10169 11:34:11.372501
10170 11:34:12.086137 01d00000 ################################################################
10171 11:34:12.086622
10172 11:34:12.798725 01d80000 ################################################################
10173 11:34:12.799193
10174 11:34:13.512120 01e00000 ################################################################
10175 11:34:13.512694
10176 11:34:14.223348 01e80000 ################################################################
10177 11:34:14.223851
10178 11:34:14.928484 01f00000 ################################################################
10179 11:34:14.928993
10180 11:34:15.643079 01f80000 ################################################################
10181 11:34:15.643564
10182 11:34:16.342580 02000000 ################################################################
10183 11:34:16.343083
10184 11:34:17.060706 02080000 ################################################################
10185 11:34:17.061210
10186 11:34:17.770533 02100000 ################################################################
10187 11:34:17.771004
10188 11:34:18.478035 02180000 ################################################################
10189 11:34:18.478537
10190 11:34:19.184460 02200000 ################################################################
10191 11:34:19.185009
10192 11:34:19.874566 02280000 ################################################################
10193 11:34:19.875126
10194 11:34:20.582058 02300000 ################################################################
10195 11:34:20.582531
10196 11:34:21.276767 02380000 ################################################################
10197 11:34:21.277314
10198 11:34:21.977226 02400000 ################################################################
10199 11:34:21.977707
10200 11:34:22.632305 02480000 ################################################################
10201 11:34:22.632800
10202 11:34:23.321094 02500000 ################################################################
10203 11:34:23.321671
10204 11:34:23.953063 02580000 ################################################################
10205 11:34:23.953228
10206 11:34:24.537578 02600000 ################################################################
10207 11:34:24.537709
10208 11:34:25.125192 02680000 ################################################################
10209 11:34:25.125323
10210 11:34:25.708219 02700000 ################################################################
10211 11:34:25.708366
10212 11:34:26.284110 02780000 ################################################################
10213 11:34:26.284241
10214 11:34:26.852618 02800000 ################################################################
10215 11:34:26.852747
10216 11:34:27.417340 02880000 ################################################################
10217 11:34:27.417492
10218 11:34:27.997985 02900000 ################################################################
10219 11:34:27.998119
10220 11:34:28.578827 02980000 ################################################################
10221 11:34:28.578948
10222 11:34:29.151929 02a00000 ################################################################
10223 11:34:29.152063
10224 11:34:29.734713 02a80000 ################################################################
10225 11:34:29.734844
10226 11:34:30.317481 02b00000 ################################################################
10227 11:34:30.317615
10228 11:34:30.890327 02b80000 ################################################################
10229 11:34:30.890454
10230 11:34:31.465007 02c00000 ################################################################
10231 11:34:31.465140
10232 11:34:32.038059 02c80000 ################################################################
10233 11:34:32.038183
10234 11:34:32.615517 02d00000 ################################################################
10235 11:34:32.615642
10236 11:34:33.180892 02d80000 ################################################################
10237 11:34:33.181013
10238 11:34:33.759047 02e00000 ################################################################
10239 11:34:33.759177
10240 11:34:34.340254 02e80000 ################################################################
10241 11:34:34.340382
10242 11:34:35.003130 02f00000 ################################################################
10243 11:34:35.003258
10244 11:34:35.636428 02f80000 ################################################################
10245 11:34:35.636558
10246 11:34:36.256124 03000000 ################################################################
10247 11:34:36.256255
10248 11:34:36.894859 03080000 ################################################################
10249 11:34:36.894994
10250 11:34:37.499985 03100000 ################################################################
10251 11:34:37.500122
10252 11:34:38.092650 03180000 ################################################################
10253 11:34:38.092777
10254 11:34:38.681668 03200000 ################################################################
10255 11:34:38.681795
10256 11:34:39.274899 03280000 ################################################################
10257 11:34:39.275025
10258 11:34:39.870454 03300000 ################################################################
10259 11:34:39.870579
10260 11:34:40.455195 03380000 ################################################################
10261 11:34:40.455322
10262 11:34:41.053039 03400000 ################################################################
10263 11:34:41.053224
10264 11:34:41.646162 03480000 ################################################################
10265 11:34:41.646291
10266 11:34:42.230293 03500000 ################################################################
10267 11:34:42.230419
10268 11:34:42.823315 03580000 ################################################################
10269 11:34:42.823438
10270 11:34:43.409100 03600000 ################################################################
10271 11:34:43.409242
10272 11:34:43.974448 03680000 ################################################################
10273 11:34:43.974576
10274 11:34:44.542718 03700000 ################################################################
10275 11:34:44.542888
10276 11:34:45.109010 03780000 ################################################################
10277 11:34:45.109221
10278 11:34:45.680257 03800000 ################################################################
10279 11:34:45.680428
10280 11:34:46.257943 03880000 ################################################################
10281 11:34:46.258105
10282 11:34:46.827841 03900000 ################################################################
10283 11:34:46.827971
10284 11:34:47.404814 03980000 ################################################################
10285 11:34:47.404983
10286 11:34:47.984237 03a00000 ################################################################
10287 11:34:47.984386
10288 11:34:48.544648 03a80000 ################################################################
10289 11:34:48.544781
10290 11:34:49.089829 03b00000 ################################################################
10291 11:34:49.089987
10292 11:34:49.639751 03b80000 ################################################################
10293 11:34:49.639888
10294 11:34:50.188188 03c00000 ################################################################
10295 11:34:50.188320
10296 11:34:50.725895 03c80000 ################################################################
10297 11:34:50.726063
10298 11:34:51.284588 03d00000 ################################################################
10299 11:34:51.284753
10300 11:34:51.861546 03d80000 ################################################################
10301 11:34:51.861718
10302 11:34:52.434032 03e00000 ################################################################
10303 11:34:52.434230
10304 11:34:52.998789 03e80000 ################################################################
10305 11:34:52.998945
10306 11:34:53.564850 03f00000 ################################################################
10307 11:34:53.565005
10308 11:34:54.130128 03f80000 ################################################################
10309 11:34:54.130262
10310 11:34:54.675375 04000000 ################################################################
10311 11:34:54.675509
10312 11:34:55.220196 04080000 ################################################################
10313 11:34:55.220330
10314 11:34:55.763728 04100000 ################################################################
10315 11:34:55.763868
10316 11:34:56.301190 04180000 ################################################################
10317 11:34:56.301321
10318 11:34:56.837612 04200000 ################################################################
10319 11:34:56.837742
10320 11:34:57.385176 04280000 ################################################################
10321 11:34:57.385306
10322 11:34:57.950873 04300000 ################################################################
10323 11:34:57.951005
10324 11:34:58.513098 04380000 ################################################################
10325 11:34:58.513249
10326 11:34:59.068318 04400000 ################################################################
10327 11:34:59.068451
10328 11:34:59.611618 04480000 ################################################################
10329 11:34:59.611756
10330 11:35:00.157170 04500000 ################################################################
10331 11:35:00.157311
10332 11:35:00.704687 04580000 ################################################################
10333 11:35:00.704827
10334 11:35:01.256418 04600000 ################################################################
10335 11:35:01.256551
10336 11:35:01.490938 04680000 ############################# done.
10337 11:35:01.491067
10338 11:35:01.494680 The bootfile was 74153998 bytes long.
10339 11:35:01.494797
10340 11:35:01.497500 Sending tftp read request... done.
10341 11:35:01.497577
10342 11:35:01.497636 Waiting for the transfer...
10343 11:35:01.497690
10344 11:35:01.501147 00000000 # done.
10345 11:35:01.501230
10346 11:35:01.507582 Command line loaded dynamically from TFTP file: 14864586/tftp-deploy-tnkxt4xu/kernel/cmdline
10347 11:35:01.507664
10348 11:35:01.520815 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10349 11:35:01.520928
10350 11:35:01.524355 Loading FIT.
10351 11:35:01.524447
10352 11:35:01.527452 Image ramdisk-1 has 60986419 bytes.
10353 11:35:01.527543
10354 11:35:01.531120 Image fdt-1 has 47258 bytes.
10355 11:35:01.531213
10356 11:35:01.531303 Image kernel-1 has 13118294 bytes.
10357 11:35:01.531372
10358 11:35:01.541049 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10359 11:35:01.541182
10360 11:35:01.560650 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10361 11:35:01.560771
10362 11:35:01.563652 Choosing best match conf-1 for compat google,spherion-rev2.
10363 11:35:01.569100
10364 11:35:01.572578 Connected to device vid:did:rid of 1ae0:0028:00
10365 11:35:01.579584
10366 11:35:01.582995 tpm_get_response: command 0x17b, return code 0x0
10367 11:35:01.583111
10368 11:35:01.589650 ec_init: CrosEC protocol v3 supported (256, 248)
10369 11:35:01.589756
10370 11:35:01.593156 tpm_cleanup: add release locality here.
10371 11:35:01.593290
10372 11:35:01.596212 Shutting down all USB controllers.
10373 11:35:01.596321
10374 11:35:01.599752 Removing current net device
10375 11:35:01.599833
10376 11:35:01.603361 Exiting depthcharge with code 4 at timestamp: 123764129
10377 11:35:01.606711
10378 11:35:01.609614 LZMA decompressing kernel-1 to 0x821a6718
10379 11:35:01.609694
10380 11:35:01.612983 LZMA decompressing kernel-1 to 0x40000000
10381 11:35:03.228053
10382 11:35:03.228181 jumping to kernel
10383 11:35:03.228726 end: 2.2.4 bootloader-commands (duration 00:01:36) [common]
10384 11:35:03.228816 start: 2.2.5 auto-login-action (timeout 00:02:44) [common]
10385 11:35:03.228885 Setting prompt string to ['Linux version [0-9]']
10386 11:35:03.228947 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10387 11:35:03.229011 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10388 11:35:03.309728
10389 11:35:03.313373 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10390 11:35:03.316944 start: 2.2.5.1 login-action (timeout 00:02:44) [common]
10391 11:35:03.317072 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10392 11:35:03.317157 Setting prompt string to []
10393 11:35:03.317242 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10394 11:35:03.317339 Using line separator: #'\n'#
10395 11:35:03.317410 No login prompt set.
10396 11:35:03.317519 Parsing kernel messages
10397 11:35:03.317602 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10398 11:35:03.317777 [login-action] Waiting for messages, (timeout 00:02:44)
10399 11:35:03.317872 Waiting using forced prompt support (timeout 00:01:22)
10400 11:35:03.336272 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10401 11:35:03.339496 [ 0.000000] random: crng init done
10402 11:35:03.342629 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10403 11:35:03.346337 [ 0.000000] efi: UEFI not found.
10404 11:35:03.356353 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10405 11:35:03.362698 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10406 11:35:03.373383 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10407 11:35:03.382229 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10408 11:35:03.388969 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10409 11:35:03.392330 [ 0.000000] printk: bootconsole [mtk8250] enabled
10410 11:35:03.401074 [ 0.000000] NUMA: No NUMA configuration found
10411 11:35:03.407576 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10412 11:35:03.414317 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10413 11:35:03.414440 [ 0.000000] Zone ranges:
10414 11:35:03.420973 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10415 11:35:03.424065 [ 0.000000] DMA32 empty
10416 11:35:03.430586 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10417 11:35:03.433832 [ 0.000000] Movable zone start for each node
10418 11:35:03.437524 [ 0.000000] Early memory node ranges
10419 11:35:03.443998 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10420 11:35:03.450412 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10421 11:35:03.457456 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10422 11:35:03.463746 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10423 11:35:03.470221 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10424 11:35:03.476766 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10425 11:35:03.534608 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10426 11:35:03.541219 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10427 11:35:03.547605 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10428 11:35:03.551057 [ 0.000000] psci: probing for conduit method from DT.
10429 11:35:03.557704 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10430 11:35:03.561005 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10431 11:35:03.567831 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10432 11:35:03.570986 [ 0.000000] psci: SMC Calling Convention v1.2
10433 11:35:03.577500 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10434 11:35:03.580860 [ 0.000000] Detected VIPT I-cache on CPU0
10435 11:35:03.587572 [ 0.000000] CPU features: detected: GIC system register CPU interface
10436 11:35:03.594170 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10437 11:35:03.600589 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10438 11:35:03.607387 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10439 11:35:03.614136 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10440 11:35:03.620711 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10441 11:35:03.627534 [ 0.000000] alternatives: applying boot alternatives
10442 11:35:03.633793 [ 0.000000] Fallback order for Node 0: 0
10443 11:35:03.640332 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10444 11:35:03.640447 [ 0.000000] Policy zone: Normal
10445 11:35:03.657729 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10446 11:35:03.667024 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10447 11:35:03.678601 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10448 11:35:03.688579 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10449 11:35:03.695450 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10450 11:35:03.698330 <6>[ 0.000000] software IO TLB: area num 8.
10451 11:35:03.756779 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10452 11:35:03.906262 <6>[ 0.000000] Memory: 7904504K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 448264K reserved, 32768K cma-reserved)
10453 11:35:03.912396 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10454 11:35:03.918800 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10455 11:35:03.922172 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10456 11:35:03.929027 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10457 11:35:03.935857 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10458 11:35:03.938935 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10459 11:35:03.948630 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10460 11:35:03.955387 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10461 11:35:03.961951 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10462 11:35:03.968653 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10463 11:35:03.971740 <6>[ 0.000000] GICv3: 608 SPIs implemented
10464 11:35:03.975086 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10465 11:35:03.981832 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10466 11:35:03.985299 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10467 11:35:03.992082 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10468 11:35:04.004795 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10469 11:35:04.018047 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10470 11:35:04.025475 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10471 11:35:04.032281 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10472 11:35:04.045543 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10473 11:35:04.052097 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10474 11:35:04.059015 <6>[ 0.009177] Console: colour dummy device 80x25
10475 11:35:04.068925 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10476 11:35:04.072460 <6>[ 0.024417] pid_max: default: 32768 minimum: 301
10477 11:35:04.079097 <6>[ 0.029290] LSM: Security Framework initializing
10478 11:35:04.086451 <6>[ 0.034229] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10479 11:35:04.095667 <6>[ 0.042043] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10480 11:35:04.102216 <6>[ 0.051474] cblist_init_generic: Setting adjustable number of callback queues.
10481 11:35:04.109115 <6>[ 0.058915] cblist_init_generic: Setting shift to 3 and lim to 1.
10482 11:35:04.119081 <6>[ 0.065254] cblist_init_generic: Setting adjustable number of callback queues.
10483 11:35:04.122238 <6>[ 0.072681] cblist_init_generic: Setting shift to 3 and lim to 1.
10484 11:35:04.128526 <6>[ 0.079119] rcu: Hierarchical SRCU implementation.
10485 11:35:04.135382 <6>[ 0.084134] rcu: Max phase no-delay instances is 1000.
10486 11:35:04.142399 <6>[ 0.091150] EFI services will not be available.
10487 11:35:04.145640 <6>[ 0.096110] smp: Bringing up secondary CPUs ...
10488 11:35:04.153380 <6>[ 0.101165] Detected VIPT I-cache on CPU1
10489 11:35:04.159954 <6>[ 0.101236] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10490 11:35:04.166291 <6>[ 0.101267] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10491 11:35:04.169696 <6>[ 0.101609] Detected VIPT I-cache on CPU2
10492 11:35:04.176696 <6>[ 0.101664] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10493 11:35:04.183033 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10494 11:35:04.189967 <6>[ 0.101946] Detected VIPT I-cache on CPU3
10495 11:35:04.196394 <6>[ 0.101995] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10496 11:35:04.202885 <6>[ 0.102009] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10497 11:35:04.206438 <6>[ 0.102317] CPU features: detected: Spectre-v4
10498 11:35:04.212665 <6>[ 0.102323] CPU features: detected: Spectre-BHB
10499 11:35:04.216579 <6>[ 0.102329] Detected PIPT I-cache on CPU4
10500 11:35:04.223145 <6>[ 0.102392] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10501 11:35:04.229641 <6>[ 0.102409] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10502 11:35:04.236193 <6>[ 0.102702] Detected PIPT I-cache on CPU5
10503 11:35:04.242791 <6>[ 0.102766] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10504 11:35:04.249598 <6>[ 0.102782] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10505 11:35:04.252696 <6>[ 0.103063] Detected PIPT I-cache on CPU6
10506 11:35:04.259174 <6>[ 0.103131] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10507 11:35:04.266449 <6>[ 0.103146] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10508 11:35:04.272767 <6>[ 0.103447] Detected PIPT I-cache on CPU7
10509 11:35:04.279108 <6>[ 0.103516] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10510 11:35:04.285836 <6>[ 0.103532] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10511 11:35:04.289477 <6>[ 0.103580] smp: Brought up 1 node, 8 CPUs
10512 11:35:04.295608 <6>[ 0.245033] SMP: Total of 8 processors activated.
10513 11:35:04.299151 <6>[ 0.249984] CPU features: detected: 32-bit EL0 Support
10514 11:35:04.308945 <6>[ 0.255380] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10515 11:35:04.316112 <6>[ 0.264181] CPU features: detected: Common not Private translations
10516 11:35:04.319210 <6>[ 0.270657] CPU features: detected: CRC32 instructions
10517 11:35:04.325427 <6>[ 0.276009] CPU features: detected: RCpc load-acquire (LDAPR)
10518 11:35:04.332505 <6>[ 0.281969] CPU features: detected: LSE atomic instructions
10519 11:35:04.338831 <6>[ 0.287750] CPU features: detected: Privileged Access Never
10520 11:35:04.342304 <6>[ 0.293530] CPU features: detected: RAS Extension Support
10521 11:35:04.352664 <6>[ 0.299138] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10522 11:35:04.355431 <6>[ 0.306360] CPU: All CPU(s) started at EL2
10523 11:35:04.361979 <6>[ 0.310677] alternatives: applying system-wide alternatives
10524 11:35:04.370814 <6>[ 0.321552] devtmpfs: initialized
10525 11:35:04.383388 <6>[ 0.330443] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10526 11:35:04.393414 <6>[ 0.340402] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10527 11:35:04.400292 <6>[ 0.348654] pinctrl core: initialized pinctrl subsystem
10528 11:35:04.403257 <6>[ 0.355527] DMI not present or invalid.
10529 11:35:04.410501 <6>[ 0.359938] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10530 11:35:04.420016 <6>[ 0.366827] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10531 11:35:04.426620 <6>[ 0.374397] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10532 11:35:04.436490 <6>[ 0.382628] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10533 11:35:04.439625 <6>[ 0.390865] audit: initializing netlink subsys (disabled)
10534 11:35:04.449757 <5>[ 0.396558] audit: type=2000 audit(0.284:1): state=initialized audit_enabled=0 res=1
10535 11:35:04.456468 <6>[ 0.397310] thermal_sys: Registered thermal governor 'step_wise'
10536 11:35:04.463262 <6>[ 0.404527] thermal_sys: Registered thermal governor 'power_allocator'
10537 11:35:04.466259 <6>[ 0.410782] cpuidle: using governor menu
10538 11:35:04.473038 <6>[ 0.421740] NET: Registered PF_QIPCRTR protocol family
10539 11:35:04.480157 <6>[ 0.427232] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10540 11:35:04.486118 <6>[ 0.434335] ASID allocator initialised with 32768 entries
10541 11:35:04.489628 <6>[ 0.440958] Serial: AMBA PL011 UART driver
10542 11:35:04.501081 <4>[ 0.451030] Trying to register duplicate clock ID: 134
10543 11:35:04.561028 <6>[ 0.514511] KASLR enabled
10544 11:35:04.575258 <6>[ 0.522153] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10545 11:35:04.581792 <6>[ 0.529167] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10546 11:35:04.588429 <6>[ 0.535654] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10547 11:35:04.595466 <6>[ 0.542662] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10548 11:35:04.601587 <6>[ 0.549151] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10549 11:35:04.608085 <6>[ 0.556153] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10550 11:35:04.615113 <6>[ 0.562642] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10551 11:35:04.621855 <6>[ 0.569642] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10552 11:35:04.624633 <6>[ 0.577127] ACPI: Interpreter disabled.
10553 11:35:04.633416 <6>[ 0.583653] iommu: Default domain type: Translated
10554 11:35:04.639954 <6>[ 0.588768] iommu: DMA domain TLB invalidation policy: strict mode
10555 11:35:04.643718 <5>[ 0.595428] SCSI subsystem initialized
10556 11:35:04.649756 <6>[ 0.599672] usbcore: registered new interface driver usbfs
10557 11:35:04.656720 <6>[ 0.605403] usbcore: registered new interface driver hub
10558 11:35:04.659777 <6>[ 0.610956] usbcore: registered new device driver usb
10559 11:35:04.666981 <6>[ 0.617112] pps_core: LinuxPPS API ver. 1 registered
10560 11:35:04.676350 <6>[ 0.622305] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10561 11:35:04.679713 <6>[ 0.631643] PTP clock support registered
10562 11:35:04.683004 <6>[ 0.635887] EDAC MC: Ver: 3.0.0
10563 11:35:04.690537 <6>[ 0.641118] FPGA manager framework
10564 11:35:04.697290 <6>[ 0.644797] Advanced Linux Sound Architecture Driver Initialized.
10565 11:35:04.700221 <6>[ 0.651592] vgaarb: loaded
10566 11:35:04.707309 <6>[ 0.654751] clocksource: Switched to clocksource arch_sys_counter
10567 11:35:04.710535 <5>[ 0.661197] VFS: Disk quotas dquot_6.6.0
10568 11:35:04.717018 <6>[ 0.665384] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10569 11:35:04.720689 <6>[ 0.672574] pnp: PnP ACPI: disabled
10570 11:35:04.728785 <6>[ 0.679288] NET: Registered PF_INET protocol family
10571 11:35:04.738220 <6>[ 0.684885] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10572 11:35:04.749980 <6>[ 0.697163] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10573 11:35:04.759896 <6>[ 0.705981] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10574 11:35:04.767089 <6>[ 0.713950] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10575 11:35:04.776555 <6>[ 0.722647] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10576 11:35:04.783216 <6>[ 0.732402] TCP: Hash tables configured (established 65536 bind 65536)
10577 11:35:04.789569 <6>[ 0.739280] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10578 11:35:04.799389 <6>[ 0.746478] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10579 11:35:04.806063 <6>[ 0.754177] NET: Registered PF_UNIX/PF_LOCAL protocol family
10580 11:35:04.812628 <6>[ 0.760335] RPC: Registered named UNIX socket transport module.
10581 11:35:04.815602 <6>[ 0.766488] RPC: Registered udp transport module.
10582 11:35:04.822657 <6>[ 0.771419] RPC: Registered tcp transport module.
10583 11:35:04.829128 <6>[ 0.776350] RPC: Registered tcp NFSv4.1 backchannel transport module.
10584 11:35:04.832309 <6>[ 0.783013] PCI: CLS 0 bytes, default 64
10585 11:35:04.835427 <6>[ 0.787338] Unpacking initramfs...
10586 11:35:04.852120 <6>[ 0.799278] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10587 11:35:04.862388 <6>[ 0.807912] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10588 11:35:04.865640 <6>[ 0.816746] kvm [1]: IPA Size Limit: 40 bits
10589 11:35:04.872081 <6>[ 0.821277] kvm [1]: GICv3: no GICV resource entry
10590 11:35:04.875653 <6>[ 0.826297] kvm [1]: disabling GICv2 emulation
10591 11:35:04.881655 <6>[ 0.830977] kvm [1]: GIC system register CPU interface enabled
10592 11:35:04.888814 <6>[ 0.838797] kvm [1]: vgic interrupt IRQ18
10593 11:35:04.891835 <6>[ 0.843170] kvm [1]: VHE mode initialized successfully
10594 11:35:04.899391 <5>[ 0.849585] Initialise system trusted keyrings
10595 11:35:04.905508 <6>[ 0.854392] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10596 11:35:04.914316 <6>[ 0.864446] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10597 11:35:04.920595 <5>[ 0.870837] NFS: Registering the id_resolver key type
10598 11:35:04.924117 <5>[ 0.876135] Key type id_resolver registered
10599 11:35:04.930668 <5>[ 0.880549] Key type id_legacy registered
10600 11:35:04.937316 <6>[ 0.884827] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10601 11:35:04.944327 <6>[ 0.891750] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10602 11:35:04.950216 <6>[ 0.899464] 9p: Installing v9fs 9p2000 file system support
10603 11:35:04.987794 <5>[ 0.937816] Key type asymmetric registered
10604 11:35:04.990500 <5>[ 0.942152] Asymmetric key parser 'x509' registered
10605 11:35:05.001324 <6>[ 0.947301] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10606 11:35:05.003868 <6>[ 0.954916] io scheduler mq-deadline registered
10607 11:35:05.008038 <6>[ 0.959682] io scheduler kyber registered
10608 11:35:05.027225 <6>[ 0.977250] EINJ: ACPI disabled.
10609 11:35:05.059996 <4>[ 1.003984] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 11:35:05.070324 <4>[ 1.014626] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 11:35:05.085435 <6>[ 1.035956] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10612 11:35:05.093593 <6>[ 1.044010] printk: console [ttyS0] disabled
10613 11:35:05.121308 <6>[ 1.068640] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10614 11:35:05.128341 <6>[ 1.078110] printk: console [ttyS0] enabled
10615 11:35:05.131694 <6>[ 1.078110] printk: console [ttyS0] enabled
10616 11:35:05.138117 <6>[ 1.087005] printk: bootconsole [mtk8250] disabled
10617 11:35:05.141762 <6>[ 1.087005] printk: bootconsole [mtk8250] disabled
10618 11:35:05.148199 <6>[ 1.098271] SuperH (H)SCI(F) driver initialized
10619 11:35:05.151310 <6>[ 1.103556] msm_serial: driver initialized
10620 11:35:05.166045 <6>[ 1.112638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10621 11:35:05.175778 <6>[ 1.121186] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10622 11:35:05.181967 <6>[ 1.129729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10623 11:35:05.191974 <6>[ 1.138357] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10624 11:35:05.202026 <6>[ 1.147065] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10625 11:35:05.208576 <6>[ 1.155787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10626 11:35:05.218882 <6>[ 1.164327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10627 11:35:05.224969 <6>[ 1.173136] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10628 11:35:05.234856 <6>[ 1.181679] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10629 11:35:05.246606 <6>[ 1.197314] loop: module loaded
10630 11:35:05.253622 <6>[ 1.203324] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10631 11:35:05.276335 <4>[ 1.226935] mtk-pmic-keys: Failed to locate of_node [id: -1]
10632 11:35:05.283317 <6>[ 1.234045] megasas: 07.719.03.00-rc1
10633 11:35:05.293690 <6>[ 1.244132] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10634 11:35:05.303502 <6>[ 1.254150] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10635 11:35:05.320628 <6>[ 1.270940] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10636 11:35:05.377799 <6>[ 1.321453] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10637 11:35:07.545950 <6>[ 3.496749] Freeing initrd memory: 59552K
10638 11:35:07.557909 <6>[ 3.508505] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10639 11:35:07.569361 <6>[ 3.519646] tun: Universal TUN/TAP device driver, 1.6
10640 11:35:07.572286 <6>[ 3.525740] thunder_xcv, ver 1.0
10641 11:35:07.575805 <6>[ 3.529249] thunder_bgx, ver 1.0
10642 11:35:07.578638 <6>[ 3.532745] nicpf, ver 1.0
10643 11:35:07.589389 <6>[ 3.536792] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10644 11:35:07.592559 <6>[ 3.544269] hns3: Copyright (c) 2017 Huawei Corporation.
10645 11:35:07.599481 <6>[ 3.549861] hclge is initializing
10646 11:35:07.602328 <6>[ 3.553442] e1000: Intel(R) PRO/1000 Network Driver
10647 11:35:07.609275 <6>[ 3.558570] e1000: Copyright (c) 1999-2006 Intel Corporation.
10648 11:35:07.612590 <6>[ 3.564583] e1000e: Intel(R) PRO/1000 Network Driver
10649 11:35:07.619025 <6>[ 3.569798] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10650 11:35:07.625713 <6>[ 3.575987] igb: Intel(R) Gigabit Ethernet Network Driver
10651 11:35:07.632594 <6>[ 3.581637] igb: Copyright (c) 2007-2014 Intel Corporation.
10652 11:35:07.639649 <6>[ 3.587473] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10653 11:35:07.645579 <6>[ 3.593991] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10654 11:35:07.648718 <6>[ 3.600457] sky2: driver version 1.30
10655 11:35:07.655391 <6>[ 3.605422] usbcore: registered new device driver r8152-cfgselector
10656 11:35:07.662060 <6>[ 3.611958] usbcore: registered new interface driver r8152
10657 11:35:07.668625 <6>[ 3.617785] VFIO - User Level meta-driver version: 0.3
10658 11:35:07.675351 <6>[ 3.626087] usbcore: registered new interface driver usb-storage
10659 11:35:07.682073 <6>[ 3.632539] usbcore: registered new device driver onboard-usb-hub
10660 11:35:07.691086 <6>[ 3.641788] mt6397-rtc mt6359-rtc: registered as rtc0
10661 11:35:07.701323 <6>[ 3.647255] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:35:07 UTC (1721216107)
10662 11:35:07.704488 <6>[ 3.656842] i2c_dev: i2c /dev entries driver
10663 11:35:07.718864 <4>[ 3.669127] cpu cpu0: supply cpu not found, using dummy regulator
10664 11:35:07.725369 <4>[ 3.675546] cpu cpu1: supply cpu not found, using dummy regulator
10665 11:35:07.731442 <4>[ 3.681968] cpu cpu2: supply cpu not found, using dummy regulator
10666 11:35:07.738068 <4>[ 3.688372] cpu cpu3: supply cpu not found, using dummy regulator
10667 11:35:07.744781 <4>[ 3.694770] cpu cpu4: supply cpu not found, using dummy regulator
10668 11:35:07.751431 <4>[ 3.701168] cpu cpu5: supply cpu not found, using dummy regulator
10669 11:35:07.757961 <4>[ 3.707571] cpu cpu6: supply cpu not found, using dummy regulator
10670 11:35:07.765257 <4>[ 3.713986] cpu cpu7: supply cpu not found, using dummy regulator
10671 11:35:07.783841 <6>[ 3.734618] cpu cpu0: EM: created perf domain
10672 11:35:07.787271 <6>[ 3.739536] cpu cpu4: EM: created perf domain
10673 11:35:07.794202 <6>[ 3.745154] sdhci: Secure Digital Host Controller Interface driver
10674 11:35:07.800846 <6>[ 3.751587] sdhci: Copyright(c) Pierre Ossman
10675 11:35:07.807759 <6>[ 3.756548] Synopsys Designware Multimedia Card Interface Driver
10676 11:35:07.814187 <6>[ 3.763197] sdhci-pltfm: SDHCI platform and OF driver helper
10677 11:35:07.817594 <6>[ 3.763250] mmc0: CQHCI version 5.10
10678 11:35:07.823979 <6>[ 3.773558] ledtrig-cpu: registered to indicate activity on CPUs
10679 11:35:07.831418 <6>[ 3.780581] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10680 11:35:07.837432 <6>[ 3.787638] usbcore: registered new interface driver usbhid
10681 11:35:07.840929 <6>[ 3.793459] usbhid: USB HID core driver
10682 11:35:07.850692 <6>[ 3.797673] spi_master spi0: will run message pump with realtime priority
10683 11:35:07.897466 <6>[ 3.841659] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10684 11:35:07.917036 <6>[ 3.857566] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10685 11:35:07.920210 <6>[ 3.869508] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10686 11:35:07.927203 <6>[ 3.872346] cros-ec-spi spi0.0: Chrome EC device registered
10687 11:35:07.930300 <6>[ 3.882964] mmc0: Command Queue Engine enabled
10688 11:35:07.937040 <6>[ 3.887716] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10689 11:35:07.944397 <6>[ 3.895183] mmcblk0: mmc0:0001 DA4128 116 GiB
10690 11:35:07.954535 <6>[ 3.896835] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10691 11:35:07.960793 <6>[ 3.903581] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10692 11:35:07.964601 <6>[ 3.910135] NET: Registered PF_PACKET protocol family
10693 11:35:07.971519 <6>[ 3.916580] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10694 11:35:07.974163 <6>[ 3.920511] 9pnet: Installing 9P2000 support
10695 11:35:07.980717 <6>[ 3.926275] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10696 11:35:07.983902 <5>[ 3.930194] Key type dns_resolver registered
10697 11:35:07.990849 <6>[ 3.936048] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10698 11:35:07.994578 <6>[ 3.940469] registered taskstats version 1
10699 11:35:08.000200 <5>[ 3.950818] Loading compiled-in X.509 certificates
10700 11:35:08.027110 <4>[ 3.971514] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10701 11:35:08.037211 <4>[ 3.982227] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10702 11:35:08.052496 <6>[ 4.003037] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10703 11:35:08.059784 <6>[ 4.009924] xhci-mtk 11200000.usb: xHCI Host Controller
10704 11:35:08.068871 <6>[ 4.015543] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10705 11:35:08.075793 <6>[ 4.023482] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10706 11:35:08.082183 <6>[ 4.032921] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10707 11:35:08.088812 <6>[ 4.039010] xhci-mtk 11200000.usb: xHCI Host Controller
10708 11:35:08.095402 <6>[ 4.044493] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10709 11:35:08.105312 <6>[ 4.052147] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10710 11:35:08.108591 <6>[ 4.060065] hub 1-0:1.0: USB hub found
10711 11:35:08.112100 <6>[ 4.064108] hub 1-0:1.0: 1 port detected
10712 11:35:08.122075 <6>[ 4.068428] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10713 11:35:08.125008 <6>[ 4.077241] hub 2-0:1.0: USB hub found
10714 11:35:08.128318 <6>[ 4.081278] hub 2-0:1.0: 1 port detected
10715 11:35:08.139178 <6>[ 4.090011] mtk-msdc 11f70000.mmc: Got CD GPIO
10716 11:35:08.150754 <6>[ 4.098065] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10717 11:35:08.160998 <6>[ 4.106444] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10718 11:35:08.167379 <6>[ 4.114788] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10719 11:35:08.177048 <6>[ 4.123130] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10720 11:35:08.183653 <6>[ 4.131471] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10721 11:35:08.193650 <6>[ 4.139811] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10722 11:35:08.199975 <6>[ 4.148151] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10723 11:35:08.210166 <6>[ 4.156490] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10724 11:35:08.216517 <6>[ 4.164828] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10725 11:35:08.226425 <6>[ 4.173167] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10726 11:35:08.232974 <6>[ 4.181505] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10727 11:35:08.243331 <6>[ 4.189853] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10728 11:35:08.249461 <6>[ 4.198192] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10729 11:35:08.259706 <6>[ 4.206535] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10730 11:35:08.266000 <6>[ 4.214879] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10731 11:35:08.272663 <6>[ 4.223592] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10732 11:35:08.280426 <6>[ 4.230784] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10733 11:35:08.286988 <6>[ 4.237585] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10734 11:35:08.296806 <6>[ 4.244345] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10735 11:35:08.303242 <6>[ 4.251323] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10736 11:35:08.309946 <6>[ 4.258196] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10737 11:35:08.320144 <6>[ 4.267328] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10738 11:35:08.329939 <6>[ 4.276450] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10739 11:35:08.339822 <6>[ 4.285744] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10740 11:35:08.349812 <6>[ 4.295212] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10741 11:35:08.360559 <6>[ 4.304679] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10742 11:35:08.366039 <6>[ 4.313799] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10743 11:35:08.376174 <6>[ 4.323266] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10744 11:35:08.385903 <6>[ 4.332387] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10745 11:35:08.395976 <6>[ 4.341682] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10746 11:35:08.405400 <6>[ 4.351843] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10747 11:35:08.416317 <6>[ 4.363527] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10748 11:35:08.539129 <6>[ 4.486928] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10749 11:35:08.694251 <6>[ 4.645066] hub 1-1:1.0: USB hub found
10750 11:35:08.697413 <6>[ 4.649617] hub 1-1:1.0: 4 ports detected
10751 11:35:08.709645 <6>[ 4.660331] hub 1-1:1.0: USB hub found
10752 11:35:08.712718 <6>[ 4.664671] hub 1-1:1.0: 4 ports detected
10753 11:35:08.820271 <6>[ 4.767417] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10754 11:35:08.846462 <6>[ 4.797253] hub 2-1:1.0: USB hub found
10755 11:35:08.849675 <6>[ 4.801765] hub 2-1:1.0: 3 ports detected
10756 11:35:08.861428 <6>[ 4.812502] hub 2-1:1.0: USB hub found
10757 11:35:08.864743 <6>[ 4.816964] hub 2-1:1.0: 3 ports detected
10758 11:35:09.031779 <6>[ 4.979131] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10759 11:35:09.164482 <6>[ 5.115255] hub 1-1.4:1.0: USB hub found
10760 11:35:09.167801 <6>[ 5.119937] hub 1-1.4:1.0: 2 ports detected
10761 11:35:09.183290 <6>[ 5.134053] hub 1-1.4:1.0: USB hub found
10762 11:35:09.186485 <6>[ 5.138693] hub 1-1.4:1.0: 2 ports detected
10763 11:35:09.243540 <6>[ 5.191300] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10764 11:35:09.352230 <6>[ 5.299748] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10765 11:35:09.389323 <4>[ 5.336734] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10766 11:35:09.398807 <4>[ 5.345905] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10767 11:35:09.437963 <6>[ 5.388596] r8152 2-1.3:1.0 eth0: v1.12.13
10768 11:35:09.486911 <6>[ 5.434848] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10769 11:35:09.679046 <6>[ 5.626886] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10770 11:35:11.087233 <6>[ 7.038240] r8152 2-1.3:1.0 eth0: carrier on
10771 11:35:13.899638 <5>[ 7.067022] Sending DHCP requests .., OK
10772 11:35:13.906425 <6>[ 9.855231] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10773 11:35:13.909369 <6>[ 9.863557] IP-Config: Complete:
10774 11:35:13.922830 <6>[ 9.867051] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10775 11:35:13.929165 <6>[ 9.877765] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10776 11:35:13.935796 <6>[ 9.886383] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10777 11:35:13.942827 <6>[ 9.886393] nameserver0=192.168.201.1
10778 11:35:13.946061 <6>[ 9.898609] clk: Disabling unused clocks
10779 11:35:13.949431 <6>[ 9.904290] ALSA device list:
10780 11:35:13.956024 <6>[ 9.907585] No soundcards found.
10781 11:35:13.963960 <6>[ 9.915371] Freeing unused kernel memory: 8512K
10782 11:35:13.966986 <6>[ 9.920296] Run /init as init process
10783 11:35:13.998062 <6>[ 9.949512] NET: Registered PF_INET6 protocol family
10784 11:35:14.004885 <6>[ 9.956462] Segment Routing with IPv6
10785 11:35:14.008290 <6>[ 9.960424] In-situ OAM (IOAM) with IPv6
10786 11:35:14.051140 <30>[ 9.976359] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10787 11:35:14.057701 <30>[ 10.009435] systemd[1]: Detected architecture arm64.
10788 11:35:14.057827
10789 11:35:14.064290 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10790 11:35:14.064408
10791 11:35:14.079834 <30>[ 10.031123] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10792 11:35:14.209206 <30>[ 10.157629] systemd[1]: Queued start job for default target graphical.target.
10793 11:35:14.248459 <30>[ 10.196677] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10794 11:35:14.254841 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10795 11:35:14.275702 <30>[ 10.223639] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10796 11:35:14.284896 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10797 11:35:14.303887 <30>[ 10.251892] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10798 11:35:14.313505 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10799 11:35:14.332209 <30>[ 10.280309] systemd[1]: Created slice user.slice - User and Session Slice.
10800 11:35:14.339092 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10801 11:35:14.366841 <30>[ 10.311721] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10802 11:35:14.373734 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10803 11:35:14.398444 <30>[ 10.343459] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10804 11:35:14.405242 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10805 11:35:14.433124 <30>[ 10.371603] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10806 11:35:14.444042 <30>[ 10.391582] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10807 11:35:14.449720 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10808 11:35:14.467258 <30>[ 10.415488] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10809 11:35:14.477016 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10810 11:35:14.495453 <30>[ 10.443567] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10811 11:35:14.504940 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10812 11:35:14.520446 <30>[ 10.471609] systemd[1]: Reached target paths.target - Path Units.
10813 11:35:14.530342 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10814 11:35:14.547183 <30>[ 10.495477] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10815 11:35:14.553989 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10816 11:35:14.567817 <30>[ 10.519146] systemd[1]: Reached target slices.target - Slice Units.
10817 11:35:14.578059 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10818 11:35:14.592161 <30>[ 10.543570] systemd[1]: Reached target swap.target - Swaps.
10819 11:35:14.598599 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10820 11:35:14.619522 <30>[ 10.567627] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10821 11:35:14.629510 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10822 11:35:14.647741 <30>[ 10.596109] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10823 11:35:14.658037 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10824 11:35:14.676647 <30>[ 10.624765] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10825 11:35:14.686514 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10826 11:35:14.703806 <30>[ 10.651790] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10827 11:35:14.713565 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10828 11:35:14.731540 <30>[ 10.679745] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10829 11:35:14.738501 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10830 11:35:14.755928 <30>[ 10.703796] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10831 11:35:14.765133 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10832 11:35:14.783988 <30>[ 10.732323] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10833 11:35:14.794099 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10834 11:35:14.847270 <30>[ 10.795291] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10835 11:35:14.853731 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10836 11:35:14.867315 <30>[ 10.815412] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10837 11:35:14.873977 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10838 11:35:14.899997 <30>[ 10.848100] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10839 11:35:14.906594 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10840 11:35:14.933604 <30>[ 10.875577] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10841 11:35:14.967514 <30>[ 10.915316] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10842 11:35:14.976619 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10843 11:35:15.000610 <30>[ 10.948417] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10844 11:35:15.007346 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10845 11:35:15.032922 <30>[ 10.980817] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10846 11:35:15.045794 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.994576] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10847 11:35:15.048672 Module dm_mod...
10848 11:35:15.098919 <30>[ 11.047268] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10849 11:35:15.105611 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10850 11:35:15.126525 <30>[ 11.074944] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10851 11:35:15.136560 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10852 11:35:15.159763 <30>[ 11.108220] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10853 11:35:15.166527 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10854 11:35:15.196583 <30>[ 11.144639] systemd[1]: Starting systemd-journald.service - Journal Service...
10855 11:35:15.203029 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10856 11:35:15.221543 <30>[ 11.169671] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10857 11:35:15.228455 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10858 11:35:15.254430 <30>[ 11.199247] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10859 11:35:15.260888 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10860 11:35:15.285375 <30>[ 11.233689] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10861 11:35:15.295045 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10862 11:35:15.319800 <30>[ 11.267650] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10863 11:35:15.325778 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10864 11:35:15.351827 <30>[ 11.299521] systemd[1]: Started systemd-journald.service - Journal Service.
10865 11:35:15.358030 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10866 11:35:15.378673 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10867 11:35:15.399573 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10868 11:35:15.419855 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10869 11:35:15.443698 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10870 11:35:15.465825 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10871 11:35:15.489462 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10872 11:35:15.514667 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10873 11:35:15.531753 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10874 11:35:15.552448 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10875 11:35:15.572903 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10876 11:35:15.593328 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10877 11:35:15.618365 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10878 11:35:15.631578 See 'systemctl status systemd-remount-fs.service' for details.
10879 11:35:15.656754 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10880 11:35:15.681682 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10881 11:35:15.727526 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10882 11:35:15.747596 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10883 11:35:15.769777 <46>[ 11.717552] systemd-journald[183]: Received client request to flush runtime journal.
10884 11:35:15.775726 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10885 11:35:15.798409 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10886 11:35:15.824589 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10887 11:35:15.853439 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10888 11:35:15.876580 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10889 11:35:15.896330 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10890 11:35:15.916592 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10891 11:35:15.936120 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10892 11:35:15.978492 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10893 11:35:16.002219 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10894 11:35:16.019277 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10895 11:35:16.034929 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10896 11:35:16.099418 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10897 11:35:16.128025 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10898 11:35:16.154791 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10899 11:35:16.176040 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10900 11:35:16.212443 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10901 11:35:16.245118 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10902 11:35:16.298102 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10903 11:35:16.321890 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10904 11:35:16.341529 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10905 11:35:16.445495 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10906 11:35:16.463468 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10907 11:35:16.483503 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10908 11:35:16.504073 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10909 11:35:16.526707 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10910 11:35:16.546061 <3>[ 12.494379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 11:35:16.552607 <6>[ 12.496375] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10912 11:35:16.563164 <3>[ 12.502533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 11:35:16.569028 <6>[ 12.510780] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10914 11:35:16.579131 <3>[ 12.518250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 11:35:16.586101 <6>[ 12.521166] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10916 11:35:16.595817 <6>[ 12.527485] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10917 11:35:16.602106 <3>[ 12.531150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 11:35:16.612066 <3>[ 12.531172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10919 11:35:16.618689 <3>[ 12.531177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 11:35:16.628958 <3>[ 12.531183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 11:35:16.635335 <3>[ 12.531186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 11:35:16.645000 <3>[ 12.537778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 11:35:16.651687 <6>[ 12.539106] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10924 11:35:16.658827 <6>[ 12.539115] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10925 11:35:16.668319 <4>[ 12.539330] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10926 11:35:16.678407 <6>[ 12.539983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10927 11:35:16.684630 <6>[ 12.539988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10928 11:35:16.691198 <6>[ 12.542069] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10929 11:35:16.701101 <6>[ 12.547705] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10930 11:35:16.707817 <3>[ 12.571188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 11:35:16.714424 <6>[ 12.576213] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10932 11:35:16.724915 <3>[ 12.584292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 11:35:16.730957 <3>[ 12.584296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10934 11:35:16.741283 <6>[ 12.592379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10935 11:35:16.744137 <6>[ 12.601436] remoteproc remoteproc0: scp is available
10936 11:35:16.753890 <6>[ 12.608534] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10937 11:35:16.764144 <3>[ 12.612941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10938 11:35:16.770411 <3>[ 12.612965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10939 11:35:16.780444 <3>[ 12.612970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 11:35:16.787476 <3>[ 12.612976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 11:35:16.793753 <3>[ 12.612980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10942 11:35:16.800435 <6>[ 12.616500] remoteproc remoteproc0: powering up scp
10943 11:35:16.807044 <3>[ 12.634075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 11:35:16.816772 <6>[ 12.641444] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10945 11:35:16.823763 <6>[ 12.641482] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10946 11:35:16.829898 <6>[ 12.646435] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10947 11:35:16.833475 <6>[ 12.646783] mc: Linux media interface: v0.10
10948 11:35:16.843267 <4>[ 12.671543] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10949 11:35:16.849840 <6>[ 12.681132] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10950 11:35:16.853367 <6>[ 12.694003] videodev: Linux video capture interface: v2.00
10951 11:35:16.859576 <6>[ 12.697256] pci_bus 0000:00: root bus resource [bus 00-ff]
10952 11:35:16.869900 <4>[ 12.697310] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10953 11:35:16.872968 <4>[ 12.697310] Fallback method does not support PEC.
10954 11:35:16.882979 <4>[ 12.697354] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10955 11:35:16.889492 <6>[ 12.838430] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10956 11:35:16.896077 <6>[ 12.838429] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10957 11:35:16.906052 <6>[ 12.838468] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10958 11:35:16.915808 <6>[ 12.838571] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10959 11:35:16.919427 <6>[ 12.838586] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10960 11:35:16.928934 [[0;32m OK [<6>[ 12.838607] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10961 11:35:16.936091 0m] Listening on<6>[ 12.838682] pci 0000:00:00.0: supports D1 D2
10962 11:35:16.942739 <6>[ 12.838685] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10963 11:35:16.952880 [0;1;39mdbus.s<6>[ 12.839278] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10964 11:35:16.965464 ocket[…- D-Bu<6>[ 12.840009] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10965 11:35:16.975436 s System Message<6>[ 12.840410] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10966 11:35:16.978927 <6>[ 12.840534] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10967 11:35:16.981882 Bus Socket.
10968 11:35:16.988594 <6>[ 12.840565] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10969 11:35:16.995602 <6>[ 12.840589] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10970 11:35:17.005391 <6>[ 12.840607] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10971 11:35:17.008281 <6>[ 12.840726] pci 0000:01:00.0: supports D1 D2
10972 11:35:17.014910 <6>[ 12.840729] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10973 11:35:17.025070 <6>[ 12.842239] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10974 11:35:17.031458 <6>[ 12.855155] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10975 11:35:17.038209 <6>[ 12.863028] remoteproc remoteproc0: remote processor scp is now up
10976 11:35:17.044706 <6>[ 12.871376] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10977 11:35:17.051303 <6>[ 12.873642] Bluetooth: Core ver 2.22
10978 11:35:17.055340 <6>[ 12.873724] NET: Registered PF_BLUETOOTH protocol family
10979 11:35:17.061253 <6>[ 12.873727] Bluetooth: HCI device and connection manager initialized
10980 11:35:17.067847 <6>[ 12.873747] Bluetooth: HCI socket layer initialized
10981 11:35:17.071603 <6>[ 12.873752] Bluetooth: L2CAP socket layer initialized
10982 11:35:17.077699 <6>[ 12.873765] Bluetooth: SCO socket layer initialized
10983 11:35:17.084644 <6>[ 12.892438] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10984 11:35:17.094094 <6>[ 12.899256] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10985 11:35:17.101024 <6>[ 12.914764] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10986 11:35:17.111360 <6>[ 12.921280] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10987 11:35:17.117100 <6>[ 12.931352] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10988 11:35:17.124312 <6>[ 12.937049] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10989 11:35:17.130649 <6>[ 12.938311] usbcore: registered new interface driver btusb
10990 11:35:17.140691 <4>[ 12.940406] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10991 11:35:17.146849 <3>[ 12.940417] Bluetooth: hci0: Failed to load firmware file (-2)
10992 11:35:17.153898 <3>[ 12.940421] Bluetooth: hci0: Failed to set up firmware (-2)
10993 11:35:17.163520 <4>[ 12.940426] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10994 11:35:17.176501 <6>[ 12.946979] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10995 11:35:17.183303 <6>[ 12.953279] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10996 11:35:17.190125 <6>[ 12.960895] usbcore: registered new interface driver uvcvideo
10997 11:35:17.197063 <6>[ 12.961813] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10998 11:35:17.203185 <6>[ 12.965291] pci 0000:00:00.0: PCI bridge to [bus 01]
10999 11:35:17.209497 <6>[ 12.965301] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11000 11:35:17.216593 <6>[ 12.965510] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11001 11:35:17.222895 [[0;32m OK [<6>[ 13.174697] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11002 11:35:17.232831 0m] Reached targ<6>[ 13.181629] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11003 11:35:17.236049 et [0;1;39msockets.target[0m - Socket Units.
11004 11:35:17.252903 <3>[ 13.200607] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 11:35:17.262159 <3>[ 13.201372] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
11006 11:35:17.272284 [[0;32m OK [0m] Reached targ<5>[ 13.221540] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11007 11:35:17.275455 et [0;1;39mbasic.target[0m - Basic System.
11008 11:35:17.289800 <5>[ 13.241467] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11009 11:35:17.299872 <3>[ 13.244832] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 11:35:17.309822 <5>[ 13.249849] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11011 11:35:17.317071 <3>[ 13.254201] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
11012 11:35:17.327141 <3>[ 13.273443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 11:35:17.333699 <4>[ 13.273820] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11014 11:35:17.340549 <6>[ 13.291496] cfg80211: failed to load regulatory.db
11015 11:35:17.354633 <3>[ 13.302915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 11:35:17.364451 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11017 11:35:17.383698 <3>[ 13.331998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11018 11:35:17.406095 <6>[ 13.354221] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11019 11:35:17.412657 <6>[ 13.354434] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11020 11:35:17.419940 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11021 11:35:17.429589 <3>[ 13.377425] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 11:35:17.436182 <6>[ 13.386486] mt7921e 0000:01:00.0: ASIC revision: 79610010
11023 11:35:17.442648 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11024 11:35:17.460605 <3>[ 13.408566] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 11:35:17.471679 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11026 11:35:17.495263 <3>[ 13.443615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 11:35:17.507128 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11028 11:35:17.538630 <6>[ 13.486843] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11029 11:35:17.541632 <6>[ 13.486843]
11030 11:35:17.556701 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11031 11:35:17.579097 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11032 11:35:17.599054 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11033 11:35:17.635354 [[0;32m OK [0m] Listening on<46>[ 13.569107] systemd-journald[183]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11034 11:35:17.651535 [0;1;39msystem<46>[ 13.591155] systemd-journald[183]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11035 11:35:17.654740 d-rfkil…l Switch Status /dev/rfkill Watch.
11036 11:35:17.693657 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11037 11:35:17.744481 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11038 11:35:17.763188 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11039 11:35:17.778509 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11040 11:35:17.797817 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11041 11:35:17.809809 <6>[ 13.758274] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11042 11:35:17.842498 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11043 11:35:17.866464 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11044 11:35:17.893068 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11045 11:35:17.950962 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11046 11:35:17.971095 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11047 11:35:17.992792 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11048 11:35:18.030042
11049 11:35:18.033298 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11050 11:35:18.033379
11051 11:35:18.036138 debian-bookworm-arm64 login: root (automatic login)
11052 11:35:18.036215
11053 11:35:18.054179 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11054 11:35:18.054299
11055 11:35:18.060754 The programs included with the Debian GNU/Linux system are free software;
11056 11:35:18.067289 the exact distribution terms for each program are described in the
11057 11:35:18.071352 individual files in /usr/share/doc/*/copyright.
11058 11:35:18.071436
11059 11:35:18.077419 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11060 11:35:18.080397 permitted by applicable law.
11061 11:35:18.080776 Matched prompt #10: / #
11063 11:35:18.080963 Setting prompt string to ['/ #']
11064 11:35:18.081050 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11066 11:35:18.081266 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11067 11:35:18.081346 start: 2.2.6 expect-shell-connection (timeout 00:02:29) [common]
11068 11:35:18.081407 Setting prompt string to ['/ #']
11069 11:35:18.081462 Forcing a shell prompt, looking for ['/ #']
11070 11:35:18.081516 Sending line: ''
11072 11:35:18.131896 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11073 11:35:18.131984 Waiting using forced prompt support (timeout 00:02:30)
11074 11:35:18.136814 / #
11075 11:35:18.137104 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11076 11:35:18.137220 start: 2.2.7 export-device-env (timeout 00:02:29) [common]
11077 11:35:18.137306 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11078 11:35:18.137385 end: 2.2 depthcharge-retry (duration 00:02:31) [common]
11079 11:35:18.137460 end: 2 depthcharge-action (duration 00:02:31) [common]
11080 11:35:18.137572 start: 3 lava-test-retry (timeout 00:07:00) [common]
11081 11:35:18.137652 start: 3.1 lava-test-shell (timeout 00:07:00) [common]
11082 11:35:18.137722 Using namespace: common
11083 11:35:18.137785 Sending line: '#'
11085 11:35:18.238274 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11086 11:35:18.243015 / # #
11087 11:35:18.243280 Using /lava-14864586
11088 11:35:18.243395 Sending line: 'export SHELL=/bin/sh'
11090 11:35:18.348644 / # export SHELL=/bin/sh
11091 11:35:18.348903 Sending line: '. /lava-14864586/environment'
11093 11:35:18.454361 / # . /lava-14864586/environment
11094 11:35:18.454655 Sending line: '/lava-14864586/bin/lava-test-runner /lava-14864586/0'
11096 11:35:18.555158 Test shell timeout: 10s (minimum of the action and connection timeout)
11097 11:35:18.560322 / # /lava-14864586/bin/lava-test-runner /lava-14864586/0
11098 11:35:18.586111 + export TESTRUN_ID=0_igt-kms-medi<8>[ 14.536914] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14864586_1.5.2.3.1>
11099 11:35:18.586400 Received signal: <STARTRUN> 0_igt-kms-mediatek 14864586_1.5.2.3.1
11100 11:35:18.586468 Starting test lava.0_igt-kms-mediatek (14864586_1.5.2.3.1)
11101 11:35:18.586542 Skipping test definition patterns.
11102 11:35:18.589042 atek
11103 11:35:18.592420 + cd /lava-14864586/0/tests/0_igt-kms-mediatek
11104 11:35:18.592496 + cat uuid
11105 11:35:18.595484 + UUID=14864586_1.5.2.3.1
11106 11:35:18.595561 + set +x
11107 11:35:18.612560 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read<8>[ 14.563821] <LAVA_SIGNAL_TESTSET START core_auth>
11108 11:35:18.612828 Received signal: <TESTSET> START core_auth
11109 11:35:18.612897 Starting test_set core_auth
11110 11:35:18.622271 kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11111 11:35:18.632616 <14>[ 14.584240] [IGT] core_auth: executing
11112 11:35:18.638810 IGT-Version: 1.2<14>[ 14.590145] [IGT] core_auth: starting subtest getclient-simple
11113 11:35:18.648721 8-ga44ebfe (aarc<14>[ 14.597951] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11114 11:35:18.655196 h64) (Linux: 6.1<14>[ 14.605969] [IGT] core_auth: exiting, ret=0
11115 11:35:18.655274 .96-cip24 aarch64)
11116 11:35:18.668499 Using IGT_SRANDOM=1721216118 for randomisati<8>[ 14.616955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11117 11:35:18.668578 on
11118 11:35:18.668811 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11120 11:35:18.675062 Starting subtest: getclient-<6>[ 14.627195] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11121 11:35:18.678252 simple
11122 11:35:18.678328 Opened device: /dev/dri/card0
11123 11:35:18.688512 [1mSubtest getclient-simple: SUCCESS (0.<14>[ 14.639109] [IGT] core_auth: executing
11124 11:35:18.688588 000s)[0m
11125 11:35:18.694972 <14>[ 14.644739] [IGT] core_auth: starting subtest getclient-master-drop
11126 11:35:18.704411 IGT-Version: 1.2<14>[ 14.652390] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11127 11:35:18.711617 8-ga44ebfe (aarc<14>[ 14.660991] [IGT] core_auth: exiting, ret=0
11128 11:35:18.714769 h64) (Linux: 6.1.96-cip24 aarch64)
11129 11:35:18.724665 Using IGT_SRANDOM=1721216118<8>[ 14.671719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11130 11:35:18.724746 for randomisation
11131 11:35:18.724977 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11133 11:35:18.727573 Starting subtest: getclient-master-drop
11134 11:35:18.730867 Opened device: /dev/dri/card0
11135 11:35:18.737744 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11136 11:35:18.764331 <14>[ 14.716319] [IGT] core_auth: executing
11137 11:35:18.770888 IGT-Version: 1.2<14>[ 14.720993] [IGT] core_auth: starting subtest basic-auth
11138 11:35:18.777377 8-ga44ebfe (aarc<14>[ 14.728176] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11139 11:35:18.783796 h64) (Linux: 6.1<14>[ 14.735599] [IGT] core_auth: exiting, ret=0
11140 11:35:18.787443 .96-cip24 aarch64)
11141 11:35:18.797429 Using IGT_SRANDOM=1721216118 for randomisati<8>[ 14.747103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11142 11:35:18.797524 on
11143 11:35:18.797757 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11145 11:35:18.800784 Opened device: /dev/dri/card0
11146 11:35:18.804337 Starting subtest: basic-auth
11147 11:35:18.807270 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11148 11:35:18.816189 <14>[ 14.768152] [IGT] core_auth: executing
11149 11:35:18.823251 IGT-Version: 1.2<14>[ 14.772563] [IGT] core_auth: starting subtest many-magics
11150 11:35:18.825978 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11151 11:35:18.835820 Using IGT_SRANDOM=1721216118 for randomisati<14>[ 14.786569] [IGT] core_auth: finished subtest many-magics, SUCCESS
11152 11:35:18.842366 <14>[ 14.794469] [IGT] core_auth: exiting, ret=0
11153 11:35:18.842452 on
11154 11:35:18.846078 Opened device: /dev/dri/card0
11155 11:35:18.855540 Starting subtest: many-magics<8>[ 14.803488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11156 11:35:18.855631
11157 11:35:18.855863 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11159 11:35:18.862162 Reopening device failed after <8>[ 14.813067] <LAVA_SIGNAL_TESTSET STOP>
11160 11:35:18.862242 1020 opens
11161 11:35:18.862471 Received signal: <TESTSET> STOP
11162 11:35:18.862532 Closing test_set core_auth
11163 11:35:18.865163 [1mSubtest many-magics: SUCCESS (0.007s)[0m
11164 11:35:18.894063 <14>[ 14.845766] [IGT] core_getclient: executing
11165 11:35:18.900518 IGT-Version: 1.2<14>[ 14.850674] [IGT] core_getclient: exiting, ret=0
11166 11:35:18.903875 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11167 11:35:18.913718 Using IGT_SR<8>[ 14.861591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11168 11:35:18.913968 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11170 11:35:18.917250 ANDOM=1721216118 for randomisation
11171 11:35:18.917326 Opened device: /dev/dri/card0
11172 11:35:18.919960 SUCCESS (0.006s)
11173 11:35:18.944522 <14>[ 14.896704] [IGT] core_getstats: executing
11174 11:35:18.951138 IGT-Version: 1.2<14>[ 14.901543] [IGT] core_getstats: exiting, ret=0
11175 11:35:18.955264 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11176 11:35:18.964378 Using IGT_SRANDOM=1721216118 for randomisati<8>[ 14.914593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11177 11:35:18.964636 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11179 11:35:18.967654 on
11180 11:35:18.967729 Opened device: /dev/dri/card0
11181 11:35:18.971207 SUCCESS (0.006s)
11182 11:35:18.998979 <14>[ 14.951141] [IGT] core_getversion: executing
11183 11:35:19.005758 IGT-Version: 1.2<14>[ 14.956274] [IGT] core_getversion: exiting, ret=0
11184 11:35:19.008848 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11185 11:35:19.019062 Using IGT_SR<8>[ 14.967189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11186 11:35:19.019336 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11188 11:35:19.022282 ANDOM=1721216118 for randomisation
11189 11:35:19.025907 Opened device: /dev/dri/card0
11190 11:35:19.025986 SUCCESS (0.006s)
11191 11:35:19.049518 <14>[ 15.001759] [IGT] core_setmaster_vs_auth: executing
11192 11:35:19.056683 IGT-Version: 1.2<14>[ 15.007452] [IGT] core_setmaster_vs_auth: exiting, ret=0
11193 11:35:19.063021 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11194 11:35:19.070301 Using IGT_SR<8>[ 15.019125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11195 11:35:19.070589 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11197 11:35:19.073020 ANDOM=1721216118 for randomisation
11198 11:35:19.076358 Opened device: /dev/dri/card0
11199 11:35:19.079826 SUCCESS (0.007s)
11200 11:35:19.092091 <8>[ 15.043869] <LAVA_SIGNAL_TESTSET START drm_read>
11201 11:35:19.092369 Received signal: <TESTSET> START drm_read
11202 11:35:19.092463 Starting test_set drm_read
11203 11:35:19.109790 <14>[ 15.061931] [IGT] drm_read: executing
11204 11:35:19.117102 IGT-Version: 1.2<14>[ 15.066457] [IGT] drm_read: exiting, ret=77
11205 11:35:19.119952 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11206 11:35:19.126490 Using IGT_SR<8>[ 15.076756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11207 11:35:19.126764 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11209 11:35:19.129730 ANDOM=1721216118 for randomisation
11210 11:35:19.133134 Opened device: /dev/dri/card0
11211 11:35:19.139942 No KMS driver or no outputs, pipes: 16, outputs: 0
11212 11:35:19.146194 [1mSubtest invalid-buffer: SKIP (0.000s)<14>[ 15.098692] [IGT] drm_read: executing
11213 11:35:19.146310 [0m
11214 11:35:19.149511 <14>[ 15.103399] [IGT] drm_read: exiting, ret=77
11215 11:35:19.163313 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<8>[ 15.112632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11216 11:35:19.163406 4)
11217 11:35:19.163639 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11219 11:35:19.169400 Using IGT_SRANDOM=1721216118 for randomisation
11220 11:35:19.169479 Opened device: /dev/dri/card0
11221 11:35:19.176089 No KMS driver or no outputs, pipes: 16, outputs: 0
11222 11:35:19.183035 [1mSubtest fault-buffer:<14>[ 15.134490] [IGT] drm_read: executing
11223 11:35:19.186051 SKIP (0.000s)[<14>[ 15.139092] [IGT] drm_read: exiting, ret=77
11224 11:35:19.189358 0m
11225 11:35:19.199198 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aa<8>[ 15.149237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11226 11:35:19.199312 rch64)
11227 11:35:19.199572 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11229 11:35:19.206337 Using IGT_SRANDOM=1721216119 for randomisation
11230 11:35:19.209275 Opened device: /dev/dri/card0
11231 11:35:19.212400 No KMS driver or no outputs, pipes: 16, outputs: 0
11232 11:35:19.219327 [1mSubtest empty-blo<14>[ 15.171005] [IGT] drm_read: executing
11233 11:35:19.225768 ck: SKIP (0.000s<14>[ 15.176008] [IGT] drm_read: exiting, ret=77
11234 11:35:19.225853 )[0m
11235 11:35:19.235784 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24<8>[ 15.185825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11236 11:35:19.236049 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11238 11:35:19.238798 aarch64)
11239 11:35:19.241920 Using IGT_SRANDOM=1721216119 for randomisation
11240 11:35:19.245734 Opened device: /dev/dri/card0
11241 11:35:19.248981 No KMS driver or no outputs, pipes: 16, outputs: 0
11242 11:35:19.255232 [1mSubtest empty-<14>[ 15.207580] [IGT] drm_read: executing
11243 11:35:19.261962 nonblock: SKIP (<14>[ 15.212355] [IGT] drm_read: exiting, ret=77
11244 11:35:19.262054 0.000s)[0m
11245 11:35:19.274972 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96<8>[ 15.222458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11246 11:35:19.275069 -cip24 aarch64)
11247 11:35:19.275300 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11249 11:35:19.278419 Using IGT_SRANDOM=1721216119 for randomisation
11250 11:35:19.281771 Opened device: /dev/dri/card0
11251 11:35:19.288655 No KMS driver or no outputs, pipes: 16, outputs: 0
11252 11:35:19.292084 [1mSubtest <14>[ 15.244903] [IGT] drm_read: executing
11253 11:35:19.298757 short-buffer-blo<14>[ 15.249476] [IGT] drm_read: exiting, ret=77
11254 11:35:19.298837 ck: SKIP (0.000s)[0m
11255 11:35:19.311461 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 15.259644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11256 11:35:19.311721 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11258 11:35:19.314876 ux: 6.1.96-cip24 aarch64)
11259 11:35:19.318103 Using IGT_SRANDOM=1721216119 for randomisation
11260 11:35:19.321594 Opened device: /dev/dri/card0
11261 11:35:19.324705 No KMS driver or no outputs, pipes: 16, outputs: 0
11262 11:35:19.331438 [1mSubtest short-<14>[ 15.282794] [IGT] drm_read: executing
11263 11:35:19.337839 buffer-nonblock:<14>[ 15.288204] [IGT] drm_read: exiting, ret=77
11264 11:35:19.337929 SKIP (0.000s)[0m
11265 11:35:19.351639 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 15.298355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11266 11:35:19.351768 6.1.96-cip24 aarch64)
11267 11:35:19.352000 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11269 11:35:19.357719 Using IG<8>[ 15.308513] <LAVA_SIGNAL_TESTSET STOP>
11270 11:35:19.357967 Received signal: <TESTSET> STOP
11271 11:35:19.358030 Closing test_set drm_read
11272 11:35:19.361045 T_SRANDOM=1721216119 for randomisation
11273 11:35:19.364648 Opened device: /dev/dri/card0
11274 11:35:19.368154 No KMS driver or no outputs, pipes: 16, outputs: 0
11275 11:35:19.370975 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11276 11:35:19.378788 <8>[ 15.330294] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11277 11:35:19.379062 Received signal: <TESTSET> START kms_addfb_basic
11278 11:35:19.379129 Starting test_set kms_addfb_basic
11279 11:35:19.397009 <14>[ 15.349055] [IGT] kms_addfb_basic: executing
11280 11:35:19.410374 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch6<14>[ 15.358163] [IGT] kms_addfb_basic: starting subtest unused-handle
11281 11:35:19.410488 4)
11282 11:35:19.417407 Using IGT_SR<14>[ 15.366066] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11283 11:35:19.419987 ANDOM=1721216119 for randomisation
11284 11:35:19.423424 Opened device: /dev/dri/card0
11285 11:35:19.430233 Starting subtest: unused-hand<14>[ 15.382842] [IGT] kms_addfb_basic: exiting, ret=0
11286 11:35:19.430318 le
11287 11:35:19.436922 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11288 11:35:19.446138 Test requirement not met in<8>[ 15.393868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11289 11:35:19.446397 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11291 11:35:19.449659 function igt_require_intel, file ../lib/drmtest.c:880:
11292 11:35:19.452806 Test requirement: is_intel_device(fd)
11293 11:35:19.466165 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 15.416392] [IGT] kms_addfb_basic: executing
11294 11:35:19.466265 0:
11295 11:35:19.469285 Test requirement: is_intel_device(fd)
11296 11:35:19.475709 No KMS driver or no o<14>[ 15.426653] [IGT] kms_addfb_basic: starting subtest unused-pitches
11297 11:35:19.485862 utputs, pipes: 1<14>[ 15.434499] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11298 11:35:19.485949 6, outputs: 0
11299 11:35:19.492879 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11300 11:35:19.499148 Using IGT_SRA<14>[ 15.451260] [IGT] kms_addfb_basic: exiting, ret=0
11301 11:35:19.502235 NDOM=1721216119 for randomisation
11302 11:35:19.512423 Opened device: /dev/dri/card0<8>[ 15.462196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11303 11:35:19.512524
11304 11:35:19.512821 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11306 11:35:19.515520 Starting subtest: unused-pitches
11307 11:35:19.519309 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11308 11:35:19.532032 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 15.483374] [IGT] kms_addfb_basic: executing
11309 11:35:19.532149 t.c:880:
11310 11:35:19.535663 Test requirement: is_intel_device(fd)
11311 11:35:19.541894 Test requiremen<14>[ 15.492554] [IGT] kms_addfb_basic: starting subtest unused-offsets
11312 11:35:19.551759 t not met in fun<14>[ 15.500282] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11313 11:35:19.555161 ction igt_require_intel, file ../lib/drmtest.c:880:
11314 11:35:19.561502 Test requirement: is_intel_device(fd)
11315 11:35:19.564698 No K<14>[ 15.517125] [IGT] kms_addfb_basic: exiting, ret=0
11316 11:35:19.568154 MS driver or no outputs, pipes: 16, outputs: 0
11317 11:35:19.577910 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 15.528212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11318 11:35:19.578227 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11320 11:35:19.581835 h64) (Linux: 6.1.96-cip24 aarch64)
11321 11:35:19.588237 Using IGT_SRANDOM=1721216119 for randomisation
11322 11:35:19.591131 Opened device: /dev/dri/card0
11323 11:35:19.591233 Starting subtest: unused-offsets
11324 11:35:19.601444 [1mSubtest unused-offsets:<14>[ 15.550778] [IGT] kms_addfb_basic: executing
11325 11:35:19.601566 SUCCESS (0.000s)[0m
11326 11:35:19.611498 Test requirement not met in function igt_<14>[ 15.561192] [IGT] kms_addfb_basic: starting subtest unused-modifier
11327 11:35:19.620647 require_intel, f<14>[ 15.569009] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11328 11:35:19.623827 ile ../lib/drmtest.c:880:
11329 11:35:19.627102 Test requirement: is_intel_device(fd)
11330 11:35:19.633922 Test requirement not met in fu<14>[ 15.585681] [IGT] kms_addfb_basic: exiting, ret=0
11331 11:35:19.637624 nction igt_require_intel, file ../lib/drmtest.c:880:
11332 11:35:19.647237 Test requirement: is_intel<8>[ 15.597194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11333 11:35:19.647503 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11335 11:35:19.650951 _device(fd)
11336 11:35:19.654200 No KMS driver or no outputs, pipes: 16, outputs: 0
11337 11:35:19.660370 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11338 11:35:19.667058 Using IGT_SRANDOM=1721216119 for randomisat<14>[ 15.619473] [IGT] kms_addfb_basic: executing
11339 11:35:19.670331 ion
11340 11:35:19.670417 Opened device: /dev/dri/card0
11341 11:35:19.680049 Starting subtest: unused-mod<14>[ 15.629806] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11342 11:35:19.680152 ifier
11343 11:35:19.689939 [1mSubte<14>[ 15.638231] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11344 11:35:19.693510 st unused-modifier: SUCCESS (0.000s)[0m
11345 11:35:19.703507 Test requirement not met in function igt_require_intel<14>[ 15.655303] [IGT] kms_addfb_basic: exiting, ret=77
11346 11:35:19.706973 , file ../lib/drmtest.c:880:
11347 11:35:19.709937 Test requirement: is_intel_device(fd)
11348 11:35:19.716634 Test requir<8>[ 15.666422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11349 11:35:19.716921 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11351 11:35:19.723175 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11352 11:35:19.726565 Test requirement: is_intel_device(fd)
11353 11:35:19.733026 No KMS driver or no outputs, pipes: 16, outputs: 0
11354 11:35:19.740000 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11355 11:35:19.742802 Using IGT_SRANDOM=1721216119 for randomisation
11356 11:35:19.749554 Opened device: /dev/dri/<14>[ 15.700377] [IGT] kms_addfb_basic: executing
11357 11:35:19.749701 card0
11358 11:35:19.752969 Starting subtest: clobberred-modifier
11359 11:35:19.762781 Test requirement n<14>[ 15.711376] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11360 11:35:19.772983 ot met in functi<14>[ 15.719621] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11361 11:35:19.776046 on igt_require_i915, file ../lib/drmtest.c:885:
11362 11:35:19.779363 Test requirement: is_i915_device(fd)
11363 11:35:19.786102 [1mSubtest clobberred-mo<14>[ 15.738259] [IGT] kms_addfb_basic: exiting, ret=77
11364 11:35:19.789452 difier: SKIP (0.000s)[0m
11365 11:35:19.799033 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11367 11:35:19.802131 Test requirement not met in function <8>[ 15.749098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11368 11:35:19.805871 igt_require_intel, file ../lib/drmtest.c:880:
11369 11:35:19.809040 Test requirement: is_intel_device(fd)
11370 11:35:19.818743 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 15.771436] [IGT] kms_addfb_basic: executing
11371 11:35:19.818874 t.c:880:
11372 11:35:19.822153 Test requirement: is_intel_device(fd)
11373 11:35:19.832185 No KMS driver o<14>[ 15.781028] [IGT] kms_addfb_basic: starting subtest legacy-format
11374 11:35:19.835669 r no outputs, pipes: 16, outputs: 0
11375 11:35:19.845425 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 15.794774] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11376 11:35:19.848431 : 6.1.96-cip24 aarch64)
11377 11:35:19.852022 Using IGT_SRANDOM=1721216119 for randomisation
11378 11:35:19.858520 Opened device: /dev/dri<14>[ 15.811101] [IGT] kms_addfb_basic: exiting, ret=0
11379 11:35:19.858636 /card0
11380 11:35:19.865532 Starting subtest: invalid-smem-bo-on-discrete
11381 11:35:19.871777 Test requ<8>[ 15.821941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11382 11:35:19.872107 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11384 11:35:19.878051 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11385 11:35:19.881623 Test requirement: is_intel_device(fd)
11386 11:35:19.888445 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11387 11:35:19.891254 Te<14>[ 15.843224] [IGT] kms_addfb_basic: executing
11388 11:35:19.904693 st requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<14>[ 15.855985] [IGT] kms_addfb_basic: starting subtest no-handle
11389 11:35:19.904831
11390 11:35:19.914900 Test requireme<14>[ 15.862375] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11391 11:35:19.915060 nt: is_intel_device(fd)
11392 11:35:19.924616 Test requirement not met in function igt_require_intel,<14>[ 15.876686] [IGT] kms_addfb_basic: exiting, ret=0
11393 11:35:19.928180 file ../lib/drmtest.c:880:
11394 11:35:19.931054 Test requirement: is_intel_device(fd)
11395 11:35:19.938110 No KMS drive<8>[ 15.888645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11396 11:35:19.938438 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11398 11:35:19.944336 r or no outputs, pipes: 16, outputs: 0
11399 11:35:19.947590 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11400 11:35:19.954186 Using IGT_SRANDOM=1721216119 for randomisation
11401 11:35:19.961460 Opened device: /dev/<14>[ 15.910449] [IGT] kms_addfb_basic: executing
11402 11:35:19.961558 dri/card0
11403 11:35:19.964036 Starting subtest: legacy-format
11404 11:35:19.970848 Successfully fuzzed 10000 {bpp, dept<14>[ 15.923074] [IGT] kms_addfb_basic: starting subtest basic
11405 11:35:19.974402 h} variations
11406 11:35:19.980435 <14>[ 15.929497] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11407 11:35:19.984079 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11408 11:35:19.990713 Test requirement not met in func<14>[ 15.943285] [IGT] kms_addfb_basic: exiting, ret=0
11409 11:35:19.997505 tion igt_require_intel, file ../lib/drmtest.c:880:
11410 11:35:20.004166 Test requirement: is_intel_d<8>[ 15.955166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11411 11:35:20.004448 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11413 11:35:20.007267 evice(fd)
11414 11:35:20.014278 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11415 11:35:20.017292 Test requirement: is_intel_device(fd)
11416 11:35:20.023661 No KMS driver or no outputs, pipes: 16, ou<14>[ 15.976774] [IGT] kms_addfb_basic: executing
11417 11:35:20.027325 tputs: 0
11418 11:35:20.034100 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11419 11:35:20.037572 Us<14>[ 15.989197] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11420 11:35:20.047418 ing IGT_SRANDOM=<14>[ 15.996270] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11421 11:35:20.050375 1721216119 for randomisation
11422 11:35:20.054017 Opened device: /dev/dri/card0
11423 11:35:20.060394 Starting subtest: n<14>[ 16.010617] [IGT] kms_addfb_basic: exiting, ret=0
11424 11:35:20.060487 o-handle
11425 11:35:20.063528 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11426 11:35:20.073878 Test requirement not met <8>[ 16.022571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11427 11:35:20.074149 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11429 11:35:20.077303 in function igt_require_intel, file ../lib/drmtest.c:880:
11430 11:35:20.083671 Test requirement: is_intel_device(fd)
11431 11:35:20.093713 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 16.044767] [IGT] kms_addfb_basic: executing
11432 11:35:20.093808 880:
11433 11:35:20.096998 Test requirement: is_intel_device(fd)
11434 11:35:20.106734 No KMS driver or no outputs, pipes:<14>[ 16.057131] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11435 11:35:20.106834 16, outputs: 0
11436 11:35:20.116614 <14>[ 16.063996] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11437 11:35:20.116779
11438 11:35:20.120120 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11439 11:35:20.126699 Using IGT_S<14>[ 16.078546] [IGT] kms_addfb_basic: exiting, ret=0
11440 11:35:20.129805 RANDOM=1721216119 for randomisation
11441 11:35:20.133395 Opened device: /dev/dri/card0
11442 11:35:20.139916 Starting sub<8>[ 16.090320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11443 11:35:20.140188 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11445 11:35:20.143616 test: basic
11446 11:35:20.146706 [1mSubtest basic: SUCCESS (0.000s)[0m
11447 11:35:20.152755 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11448 11:35:20.156227 Test requirement: is_intel_device(fd)
11449 11:35:20.162903 <14>[ 16.112673] [IGT] kms_addfb_basic: executing
11450 11:35:20.162991
11451 11:35:20.176308 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 16.125157] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11452 11:35:20.176428 80:
11453 11:35:20.182776 Test requir<14>[ 16.132102] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11454 11:35:20.186506 ement: is_intel_device(fd)
11455 11:35:20.189525 No KMS driver or no outputs, pipes: 16, outputs: 0
11456 11:35:20.196329 <14>[ 16.146434] [IGT] kms_addfb_basic: exiting, ret=0
11457 11:35:20.202995 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11458 11:35:20.209074 Using IGT_SR<8>[ 16.158190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11459 11:35:20.209364 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11461 11:35:20.212359 ANDOM=1721216119 for randomisation
11462 11:35:20.216082 Opened device: /dev/dri/card0
11463 11:35:20.219441 Starting subtest: bad-pitch-0
11464 11:35:20.222618 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11465 11:35:20.229725 Test requirement not met in fun<14>[ 16.181027] [IGT] kms_addfb_basic: executing
11466 11:35:20.232840 ction igt_require_intel, file ../lib/drmtest.c:880:
11467 11:35:20.242121 Test requirement: is_intel_<14>[ 16.193113] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11468 11:35:20.242243 device(fd)
11469 11:35:20.252300 Test<14>[ 16.200112] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11470 11:35:20.258654 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11471 11:35:20.262090 <14>[ 16.214666] [IGT] kms_addfb_basic: exiting, ret=0
11472 11:35:20.265698 Test requirement: is_intel_device(fd)
11473 11:35:20.279038 No KMS driver or no outputs, pipes: 16, o<8>[ 16.226681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11474 11:35:20.279156 utputs: 0
11475 11:35:20.279415 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11477 11:35:20.285499 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11478 11:35:20.288618 Using IGT_SRANDOM=1721216119 for randomisation
11479 11:35:20.291570 Opened device: /dev/dri/card0
11480 11:35:20.298669 Starting subtest: <14>[ 16.248830] [IGT] kms_addfb_basic: executing
11481 11:35:20.298751 bad-pitch-32
11482 11:35:20.301726 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11483 11:35:20.311909 Test requirement n<14>[ 16.261345] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11484 11:35:20.317943 ot met in functi<14>[ 16.268530] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11485 11:35:20.324755 on igt_require_intel, file ../lib/drmtest.c:880:
11486 11:35:20.331590 Test requirement: is_intel_dev<14>[ 16.282907] [IGT] kms_addfb_basic: exiting, ret=0
11487 11:35:20.331698 ice(fd)
11488 11:35:20.344878 Test requirement not met in function igt_require_intel, file ../lib/drm<8>[ 16.294948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11489 11:35:20.345215 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11491 11:35:20.347790 test.c:880:
11492 11:35:20.351195 Test requirement: is_intel_device(fd)
11493 11:35:20.354566 No KMS driver or no outputs, pipes: 16, outputs: 0
11494 11:35:20.361243 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11495 11:35:20.364291 Usin<14>[ 16.317187] [IGT] kms_addfb_basic: executing
11496 11:35:20.371101 g IGT_SRANDOM=1721216120 for randomisation
11497 11:35:20.371203 Opened device: /dev/dri/card0
11498 11:35:20.380681 Start<14>[ 16.329718] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11499 11:35:20.387912 ing subtest: bad<14>[ 16.336815] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11500 11:35:20.390631 -pitch-63
11501 11:35:20.394399 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11502 11:35:20.401058 Test requirement not <14>[ 16.351303] [IGT] kms_addfb_basic: exiting, ret=0
11503 11:35:20.407262 met in function igt_require_intel, file ../lib/drmtest.c:880:
11504 11:35:20.414152 Test requirement:<8>[ 16.363178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11505 11:35:20.414429 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11507 11:35:20.417164 is_intel_device(fd)
11508 11:35:20.424002 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11509 11:35:20.427265 Test requirement: is_intel_device(fd)
11510 11:35:20.433837 No KMS driver or no outputs, pi<14>[ 16.385775] [IGT] kms_addfb_basic: executing
11511 11:35:20.437172 pes: 16, outputs: 0
11512 11:35:20.447036 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 a<14>[ 16.398246] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11513 11:35:20.450689 arch64)
11514 11:35:20.456776 Using I<14>[ 16.405296] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11515 11:35:20.460488 GT_SRANDOM=1721216120 for randomisation
11516 11:35:20.463475 Opened device: /dev/dri/card0
11517 11:35:20.470099 Starting<14>[ 16.419858] [IGT] kms_addfb_basic: exiting, ret=0
11518 11:35:20.470176 subtest: bad-pitch-128
11519 11:35:20.476571 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11520 11:35:20.483614 Test r<8>[ 16.431823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11521 11:35:20.483863 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11523 11:35:20.490049 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11524 11:35:20.493729 Test requirement: is_intel_device(fd)
11525 11:35:20.503452 Test requirement not met in function igt_require_intel, fil<14>[ 16.454138] [IGT] kms_addfb_basic: executing
11526 11:35:20.506558 e ../lib/drmtest.c:880:
11527 11:35:20.509828 Test requirement: is_intel_device(fd)
11528 11:35:20.516222 No KMS driver or<14>[ 16.466475] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11529 11:35:20.526308 no outputs, pip<14>[ 16.473826] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11530 11:35:20.526416 es: 16, outputs: 0
11531 11:35:20.536049 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aa<14>[ 16.488462] [IGT] kms_addfb_basic: exiting, ret=0
11532 11:35:20.539673 rch64)
11533 11:35:20.542784 Using IGT_SRANDOM=1721216120 for randomisation
11534 11:35:20.553073 Opened device: /dev/dri/<8>[ 16.500199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11535 11:35:20.553198 card0
11536 11:35:20.553451 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11538 11:35:20.556258 Starting subtest: bad-pitch-256
11539 11:35:20.559233 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11540 11:35:20.565951 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11541 11:35:20.572771 Tes<14>[ 16.522969] [IGT] kms_addfb_basic: executing
11542 11:35:20.575721 t requirement: is_intel_device(fd)
11543 11:35:20.588796 Test requirement not met in function igt_require_intel, file ../lib/drmtest.<14>[ 16.537345] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11544 11:35:20.588886 c:880:
11545 11:35:20.598682 Test req<14>[ 16.545925] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11546 11:35:20.602118 uirement: is_intel_device(fd)
11547 11:35:20.605260 No KMS driver or <14>[ 16.559095] [IGT] kms_addfb_basic: exiting, ret=0
11548 11:35:20.608692 no outputs, pipes: 16, outputs: 0
11549 11:35:20.622218 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <8>[ 16.570306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11550 11:35:20.622472 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11552 11:35:20.625553 6.1.96-cip24 aarch64)
11553 11:35:20.628953 Using IGT_SRANDOM=1721216120 for randomisation
11554 11:35:20.631716 Opened device: /dev/dri/card0
11555 11:35:20.635387 Starting subtest: bad-pitch-1024
11556 11:35:20.642331 [1mSubtest bad-pitch-1024: SUCCESS (0.0<14>[ 16.593090] [IGT] kms_addfb_basic: executing
11557 11:35:20.642429 00s)[0m
11558 11:35:20.648347 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11559 11:35:20.658326 Test requirement: <14>[ 16.607731] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11560 11:35:20.668789 is_intel_device(<14>[ 16.615548] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11561 11:35:20.668902 fd)
11562 11:35:20.674985 Test requirement not met in function igt_re<14>[ 16.628445] [IGT] kms_addfb_basic: exiting, ret=0
11563 11:35:20.681981 quire_intel, file ../lib/drmtest.c:880:
11564 11:35:20.685007 Test requirement: is_intel_device(fd)
11565 11:35:20.691819 <8>[ 16.639515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11566 11:35:20.692069 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11568 11:35:20.694877 No KMS driver or no outputs, pipes: 16, outputs: 0
11569 11:35:20.701325 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11570 11:35:20.704745 Using IGT_SRANDOM=1721216120 for randomisation
11571 11:35:20.711236 Opened d<14>[ 16.662133] [IGT] kms_addfb_basic: executing
11572 11:35:20.714705 evice: /dev/dri/card0
11573 11:35:20.714783 Starting subtest: bad-pitch-999
11574 11:35:20.721389 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11575 11:35:20.727986 Test re<14>[ 16.676552] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11576 11:35:20.737608 quirement not me<14>[ 16.685067] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11577 11:35:20.747356 t in function igt_require_intel, file ../lib/drm<14>[ 16.698304] [IGT] kms_addfb_basic: exiting, ret=0
11578 11:35:20.747440 test.c:880:
11579 11:35:20.750477 Test requirement: is_intel_device(fd)
11580 11:35:20.760326 Test requirement not met in <8>[ 16.709413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11581 11:35:20.760579 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11583 11:35:20.767154 function igt_require_intel, file ../lib/drmtest.c:880:
11584 11:35:20.770702 Test requirement: is_intel_device(fd)
11585 11:35:20.773954 No KMS driver or no outputs, pipes: 16, outputs: 0
11586 11:35:20.780360 IGT-Version: <14>[ 16.732096] [IGT] kms_addfb_basic: executing
11587 11:35:20.783571 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11588 11:35:20.787031 Using IGT_SRANDOM=1721216120 for randomisation
11589 11:35:20.796920 Opened de<14>[ 16.745524] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11590 11:35:20.803716 vice: /dev/dri/c<14>[ 16.753493] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11591 11:35:20.806850 ard0
11592 11:35:20.809898 Starting subtest: bad-pitch-65536
11593 11:35:20.813426 [1mSub<14>[ 16.766363] [IGT] kms_addfb_basic: exiting, ret=0
11594 11:35:20.816902 test bad-pitch-65536: SUCCESS (0.000s)[0m
11595 11:35:20.830061 Test requirement not met in function<8>[ 16.777487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11596 11:35:20.830317 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11598 11:35:20.833424 igt_require_intel, file ../lib/drmtest.c:880:
11599 11:35:20.836663 Test requirement: is_intel_device(fd)
11600 11:35:20.843083 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11601 11:35:20.849997 Test <14>[ 16.799877] [IGT] kms_addfb_basic: executing
11602 11:35:20.852807 requirement: is_intel_device(fd)
11603 11:35:20.856724 No KMS driver or no outputs, pipes: 16, outputs: 0
11604 11:35:20.866213 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<14>[ 16.816379] [IGT] kms_addfb_basic: starting subtest master-rmfb
11605 11:35:20.872857 x: 6.1.96-cip24 <14>[ 16.823428] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11606 11:35:20.876295 aarch64)
11607 11:35:20.883242 Using IGT_SRANDOM=1721<14>[ 16.834036] [IGT] kms_addfb_basic: exiting, ret=0
11608 11:35:20.886556 216120 for randomisation
11609 11:35:20.886656 Opened device: /dev/dri/card0
11610 11:35:20.896083 Starting subtest: inval<8>[ 16.845572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11611 11:35:20.896336 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11613 11:35:20.899353 id-get-prop-any
11614 11:35:20.902770 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11615 11:35:20.909636 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11616 11:35:20.915939 Test requirement: i<14>[ 16.867788] [IGT] kms_addfb_basic: executing
11617 11:35:20.919225 s_intel_device(fd)
11618 11:35:20.925691 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11619 11:35:20.929131 Test requirement: is_intel_device(fd)
11620 11:35:20.935661 N<14>[ 16.885922] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11621 11:35:20.945525 o KMS driver or <14>[ 16.893711] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11622 11:35:20.952314 no outputs, pipe<14>[ 16.903466] [IGT] kms_addfb_basic: exiting, ret=0
11623 11:35:20.955351 s: 16, outputs: 0
11624 11:35:20.965385 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <8>[ 16.914176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11625 11:35:20.965660 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11627 11:35:20.968653 6.1.96-cip24 aarch64)
11628 11:35:20.972110 Using IGT_SRANDOM=1721216120 for randomisation
11629 11:35:20.975064 Opened device: /dev/dri/card0
11630 11:35:20.978452 Starting subtest: invalid-get-prop
11631 11:35:20.985079 [1mSubtest invalid-ge<14>[ 16.936869] [IGT] kms_addfb_basic: executing
11632 11:35:20.988649 t-prop: SUCCESS (0.000s)[0m
11633 11:35:20.994981 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11634 11:35:21.004876 Test requirement: is_intel_dev<14>[ 16.954506] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11635 11:35:21.004985 ice(fd)
11636 11:35:21.011378 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11637 11:35:21.014834 Test requirement: is_intel_device(fd)
11638 11:35:21.021580 No KMS driver or no outputs, pipes: 16, outputs: 0
11639 11:35:21.024690 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11640 11:35:21.031453 Using IGT_SRANDOM=1721216120 for randomisation
11641 11:35:21.034970 Opened device: /dev/dri/card0
11642 11:35:21.038248 Starting subtest: invalid-set-prop-any
11643 11:35:21.041367 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11644 11:35:21.047916 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11645 11:35:21.051416 Test requirement: is_intel_device(fd)
11646 11:35:21.057765 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11647 11:35:21.065058 Test requirement: is_intel_device(fd)
11648 11:35:21.067931 No KMS driver or no outputs, pipes: 16, outputs: 0
11649 11:35:21.074080 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11650 11:35:21.077981 Using IGT_SRANDOM=1721216120 for randomisation
11651 11:35:21.081155 Opened device: /dev/dri/card0
11652 11:35:21.084516 Starting subtest: invalid-set-prop
11653 11:35:21.087357 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11654 11:35:21.094451 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11655 11:35:21.097128 Test requirement: is_intel_device(fd)
11656 11:35:21.107240 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11657 11:35:21.110342 Test requirement: is_intel_device(fd)
11658 11:35:21.113996 No KMS driver or no outputs, pipes: 16, outputs: 0
11659 11:35:21.120308 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11660 11:35:21.124208 Using IGT_SRANDOM=1721216120 for randomisation
11661 11:35:21.127205 Opened device: /dev/dri/card0
11662 11:35:21.130462 Starting subtest: master-rmfb
11663 11:35:21.133836 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11664 11:35:21.140083 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11665 11:35:21.143345 Test requirement: is_intel_device(fd)
11666 11:35:21.150343 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11667 11:35:21.153814 Test requirement: is_intel_device(fd)
11668 11:35:21.159997 No KMS driver or no outputs, pipes: 16, outputs: 0
11669 11:35:21.166597 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11670 11:35:21.169608 Using IGT_SRANDOM=1721216120 for randomisation
11671 11:35:21.173438 Opened device: /dev/dri/card0
11672 11:35:21.176920 Starting subtest: addfb25-modifier-no-flag
11673 11:35:21.179534 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11674 11:35:21.189890 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11675 11:35:21.193090 Test requirement: is_intel_device(fd)
11676 11:35:21.199653 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11677 11:35:21.202778 Test requirement: is_intel_device(fd)
11678 11:35:21.205809 No KMS driver or no outputs, pipes: 16, outputs: 0
11679 11:35:21.212880 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11680 11:35:21.215836 Using IGT_SRANDOM=1721216120 for randomisation
11681 11:35:21.219538 Opened device: /dev/dri/card0
11682 11:35:21.222437 Starting subtest: addfb25-bad-modifier
11683 11:35:21.232281 (kms_addfb_basic:432) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11684 11:35:21.252137 (kms_addfb_basic:432) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11685 11:35:21.255393 (kms_addfb_basic:432) CRITICAL: error: 0 != -1
11686 11:35:21.255475 Stack trace:
11687 11:35:21.261830 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11688 11:35:21.261909 #1 [<unknown>+0xe2c24358]
11689 11:35:21.265127 #2 [<unknown>+0xe2c25fbc]
11690 11:35:21.268525 #3 [<unknown>+0xe2c2156c]
11691 11:35:21.271750 #4 [__libc_init_first+0x80]
11692 11:35:21.275327 #5 [__libc_start_main+0x98]
11693 11:35:21.275404 #6 [<unknown>+0xe2c215b0]
11694 11:35:21.278502 Subtest addfb25-bad-modifier failed.
11695 11:35:21.281974 **** DEBUG ****
11696 11:35:21.288120 (kms_addfb_basic:432) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11697 11:35:21.298175 (kms_addfb_basic:432) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11698 11:35:21.318091 (kms_addfb_basic:432) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11699 11:35:21.321041 (kms_addfb_basic:432) CRITICAL: error: 0 != -1
11700 11:35:21.324614 (kms_addfb_basic:432) igt_core-INFO: Stack trace:
11701 11:35:21.334814 (kms_addfb_basic:432) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11702 11:35:21.337652 (kms_addfb_basic:432) igt_core-INFO: #1 [<unknown>+0xe2c24358]
11703 11:35:21.344351 (kms_addfb_basic:432) igt_core-INFO: #2 [<unknown>+0xe2c25fbc]
11704 11:35:21.351098 (<14>[ 17.300900] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11705 11:35:21.357365 kms_addfb_basic:<14>[ 17.309922] [IGT] kms_addfb_basic: exiting, ret=98
11706 11:35:21.364640 432) igt_core-INFO: #3 [<unknown>+0xe2c2156c]
11707 11:35:21.373700 (kms_addfb_basic:432) igt_core-<8>[ 17.322462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11708 11:35:21.373958 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11710 11:35:21.376977 INFO: #4 [__libc_init_first+0x80]
11711 11:35:21.384012 (kms_addfb_basic:432) igt_core-INFO: #5 [__libc_start_main+0x98]
11712 11:35:21.387252 (kms_addfb_basic:432) igt_core-INFO: #6 [<unknown>+0xe2c215b0]
11713 11:35:21.393688 **** <14>[ 17.345291] [IGT] kms_addfb_basic: executing
11714 11:35:21.393766 END ****
11715 11:35:21.400323 [1mSubtest addfb25-bad-modifier: FAIL (0.339s)[0m
11716 11:35:21.406941 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11717 11:35:21.413376 Test requir<14>[ 17.363671] [IGT] kms_addfb_basic: exiting, ret=77
11718 11:35:21.416774 ement: is_intel_device(fd)
11719 11:35:21.426695 Test requirement not met in function<8>[ 17.375215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11720 11:35:21.426956 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11722 11:35:21.429958 igt_require_intel, file ../lib/drmtest.c:880:
11723 11:35:21.432921 Test requirement: is_intel_device(fd)
11724 11:35:21.439641 No KMS driver or no outputs, pipes: 16, outputs: 0
11725 11:35:21.446171 IGT-Version: 1.28-ga4<14>[ 17.397807] [IGT] kms_addfb_basic: executing
11726 11:35:21.449609 4ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11727 11:35:21.452969 Using IGT_SRANDOM=1721216121 for randomisation
11728 11:35:21.456734 Opened device: /dev/dri/card0
11729 11:35:21.465887 Test requirement not met in functi<14>[ 17.415559] [IGT] kms_addfb_basic: exiting, ret=77
11730 11:35:21.469524 on igt_require_intel, file ../lib/drmtest.c:880:
11731 11:35:21.479470 Test requireme<8>[ 17.426941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11732 11:35:21.479565 nt: is_intel_device(fd)
11733 11:35:21.479799 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11735 11:35:21.486147 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11736 11:35:21.495810 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 17.448778] [IGT] kms_addfb_basic: executing
11737 11:35:21.499000 test.c:880:
11738 11:35:21.502562 Test requirement: is_intel_device(fd)
11739 11:35:21.505792 No KMS driver or no outputs, pipes: 16, outputs: 0
11740 11:35:21.515200 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip2<14>[ 17.466732] [IGT] kms_addfb_basic: exiting, ret=77
11741 11:35:21.515283 4 aarch64)
11742 11:35:21.521918 Using IGT_SRANDOM=1721216121 for randomisation
11743 11:35:21.528664 Open<8>[ 17.478014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11744 11:35:21.528931 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11746 11:35:21.531839 ed device: /dev/dri/card0
11747 11:35:21.538522 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11748 11:35:21.541754 Test requirement: is_intel_device(fd)
11749 11:35:21.551929 [1mSubtest addfb25-x-tiled-legacy: SKIP (<14>[ 17.503948] [IGT] kms_addfb_basic: executing
11750 11:35:21.552022 0.000s)[0m
11751 11:35:21.561568 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11752 11:35:21.565547 Test requirement: is_intel_device(fd)
11753 11:35:21.571408 No KMS driver or no outp<14>[ 17.521736] [IGT] kms_addfb_basic: exiting, ret=77
11754 11:35:21.574927 uts, pipes: 16, outputs: 0
11755 11:35:21.584690 IGT-Version: 1.28-ga44ebfe (aarch64)<8>[ 17.533240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11756 11:35:21.584950 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11758 11:35:21.593894 (Linux: 6.1.96-cip24 aarch64)
11759 11:35:21.593995 Using IGT_SRANDOM=1721216121 for randomisation
11760 11:35:21.594439 Opened device: /dev/dri/card0
11761 11:35:21.602354 Test requirement not met in function igt_require_<14>[ 17.555438] [IGT] kms_addfb_basic: executing
11762 11:35:21.604925 intel, file ../lib/drmtest.c:880:
11763 11:35:21.607754 Test requirement: is_intel_device(fd)
11764 11:35:21.614450 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11765 11:35:21.621240 Test<14>[ 17.572845] [IGT] kms_addfb_basic: exiting, ret=77
11766 11:35:21.634664 requirement not met in function igt_require_intel, file ../lib/<8>[ 17.582745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11767 11:35:21.634767 drmtest.c:880:
11768 11:35:21.634996 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11770 11:35:21.637875 Test requirement: is_intel_device(fd)
11771 11:35:21.644200 No KMS driver or no outputs, pipes: 16, outputs: 0
11772 11:35:21.654351 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-c<14>[ 17.605607] [IGT] kms_addfb_basic: executing
11773 11:35:21.654435 ip24 aarch64)
11774 11:35:21.657871 Using IGT_SRANDOM=1721216121 for randomisation
11775 11:35:21.661327 Opened device: /dev/dri/card0
11776 11:35:21.671047 Test requirement not met in function igt_require_intel, file ../li<14>[ 17.622938] [IGT] kms_addfb_basic: exiting, ret=77
11777 11:35:21.674026 b/drmtest.c:880:
11778 11:35:21.677534 Test requirement: is_intel_device(fd)
11779 11:35:21.683934 Test re<8>[ 17.634262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11780 11:35:21.684184 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11782 11:35:21.690627 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11783 11:35:21.694203 Test requirement: is_intel_device(fd)
11784 11:35:21.704194 [1mSubtest basic-x-tiled-legacy: SKIP (0.00<14>[ 17.656474] [IGT] kms_addfb_basic: executing
11785 11:35:21.704278 0s)[0m
11786 11:35:21.710634 No KMS driver or no outputs, pipes: 16, outputs: 0
11787 11:35:21.713750 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11788 11:35:21.724159 Using IGT_SRANDOM=1721216121 fo<14>[ 17.674013] [IGT] kms_addfb_basic: exiting, ret=77
11789 11:35:21.724246 r randomisation
11790 11:35:21.727466 Opened device: /dev/dri/card0
11791 11:35:21.736936 Test requirement<8>[ 17.685188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11792 11:35:21.737188 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11794 11:35:21.743589 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11795 11:35:21.746825 Test requirement: is_intel_device(fd)
11796 11:35:21.753305 Test requirement not met in function igt_require_inte<14>[ 17.707190] [IGT] kms_addfb_basic: executing
11797 11:35:21.756989 l, file ../lib/drmtest.c:880:
11798 11:35:21.760192 Test requirement: is_intel_device(fd)
11799 11:35:21.766907 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11800 11:35:21.772982 No KMS driver or no outputs, pip<14>[ 17.724757] [IGT] kms_addfb_basic: exiting, ret=77
11801 11:35:21.776632 es: 16, outputs: 0
11802 11:35:21.786487 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 17.736184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11803 11:35:21.786742 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11805 11:35:21.789444 6.1.96-cip24 aarch64)
11806 11:35:21.792942 Using IGT_SRANDOM=1721216121 for randomisation
11807 11:35:21.796332 Opened device: /dev/dri/card0
11808 11:35:21.806328 Test requirement not met in function igt_require_intel, f<14>[ 17.757327] [IGT] kms_addfb_basic: executing
11809 11:35:21.806414 ile ../lib/drmtest.c:880:
11810 11:35:21.809818 Test requirement: is_intel_device(fd)
11811 11:35:21.819566 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11812 11:35:21.822837 Test requi<14>[ 17.775037] [IGT] kms_addfb_basic: exiting, ret=77
11813 11:35:21.826225 rement: is_intel_device(fd)
11814 11:35:21.836362 [1mSubtest tile-pitch-mismatch: SK<8>[ 17.786074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11815 11:35:21.836618 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11817 11:35:21.839340 IP (0.000s)[0m
11818 11:35:21.843014 No KMS driver or no outputs, pipes: 16, outputs: 0
11819 11:35:21.849420 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11820 11:35:21.856024 Using IGT_SRANDOM=17212<14>[ 17.807002] [IGT] kms_addfb_basic: executing
11821 11:35:21.856109 16121 for randomisation
11822 11:35:21.859057 Opened device: /dev/dri/card0
11823 11:35:21.865594 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11824 11:35:21.872437 Test<14>[ 17.824624] [IGT] kms_addfb_basic: exiting, ret=77
11825 11:35:21.875623 requirement: is_intel_device(fd)
11826 11:35:21.885586 Test requirement not met in f<8>[ 17.834911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11827 11:35:21.885837 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11829 11:35:21.888803 unction igt_require_intel, file ../lib/drmtest.c:880:
11830 11:35:21.891970 Test requirement: is_intel_device(fd)
11831 11:35:21.899060 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11832 11:35:21.902060 No KMS driver<14>[ 17.855117] [IGT] kms_addfb_basic: executing
11833 11:35:21.905104 or no outputs, pipes: 16, outputs: 0
11834 11:35:21.911649 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11835 11:35:21.915267 Using IGT_SRANDOM=1721216121 for randomisation
11836 11:35:21.921851 Opene<14>[ 17.873467] [IGT] kms_addfb_basic: exiting, ret=77
11837 11:35:21.925477 d device: /dev/dri/card0
11838 11:35:21.935110 Test requirement not met in function i<8>[ 17.884583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11839 11:35:21.935360 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11841 11:35:21.938376 gt_require_intel, file ../lib/drmtest.c:880:
11842 11:35:21.941679 Test requirement: is_intel_device(fd)
11843 11:35:21.955156 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 17.906057] [IGT] kms_addfb_basic: executing
11844 11:35:21.955243 .c:880:
11845 11:35:21.958350 Test requirement: is_intel_device(fd)
11846 11:35:21.961192 No KMS driver or no outputs, pipes: 16, outputs: 0
11847 11:35:21.964662 [1mSubtest size-max: SKIP (0.000s)[0m
11848 11:35:21.971396 IGT<14>[ 17.923444] [IGT] kms_addfb_basic: exiting, ret=77
11849 11:35:21.978345 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11850 11:35:21.984630 <8>[ 17.933745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11851 11:35:21.984710
11852 11:35:21.984939 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11854 11:35:21.987811 Using IGT_SRANDOM=1721216121 for randomisation
11855 11:35:21.990991 Opened device: /dev/dri/card0
11856 11:35:22.001274 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 17.954057] [IGT] kms_addfb_basic: executing
11857 11:35:22.004544 0:
11858 11:35:22.007750 Test requirement: is_intel_device(fd)
11859 11:35:22.014420 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11860 11:35:22.020987 Test requirement: is_intel_device<14>[ 17.972626] [IGT] kms_addfb_basic: exiting, ret=77
11861 11:35:22.021072 (fd)
11862 11:35:22.028141 No KMS driver or no outputs, pipes: 16, outputs: 0
11863 11:35:22.033826 [1mSu<8>[ 17.983699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11864 11:35:22.034103 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11866 11:35:22.038187 btest too-wide: SKIP (0.000s)[0m
11867 11:35:22.044302 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11868 11:35:22.047791 Using IGT_SRANDOM=1721216121 for randomisation
11869 11:35:22.054185 Opened de<14>[ 18.006452] [IGT] kms_addfb_basic: executing
11870 11:35:22.057421 vice: /dev/dri/card0
11871 11:35:22.064143 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11872 11:35:22.067697 Test requirement: is_intel_device(fd)
11873 11:35:22.073782 Test requiremen<14>[ 18.024121] [IGT] kms_addfb_basic: exiting, ret=77
11874 11:35:22.087346 t not met in function igt_require_intel, file ../lib/drmtest.c:8<8>[ 18.035360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11875 11:35:22.087440 80:
11876 11:35:22.087671 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11878 11:35:22.090425 Test requirement: is_intel_device(fd)
11879 11:35:22.093666 No KMS driver or no outputs, pipes: 16, outputs: 0
11880 11:35:22.096840 [1mSubtest too-high: SKIP (0.000s)[0m
11881 11:35:22.103391 IGT-Version: 1.28-ga44e<14>[ 18.057650] [IGT] kms_addfb_basic: executing
11882 11:35:22.110433 bfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11883 11:35:22.113744 Using IGT_SRANDOM=1721216121 for randomisation
11884 11:35:22.116775 Opened device: /dev/dri/card0
11885 11:35:22.123389 Test requirement not met in function<14>[ 18.075386] [IGT] kms_addfb_basic: exiting, ret=77
11886 11:35:22.130208 igt_require_intel, file ../lib/drmtest.c:880:
11887 11:35:22.136801 Test requirement<8>[ 18.086492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11888 11:35:22.137068 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11890 11:35:22.140059 : is_intel_device(fd)
11891 11:35:22.146769 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11892 11:35:22.149877 Test requirement: is_intel_device(fd)
11893 11:35:22.156403 No KMS driver <14>[ 18.108921] [IGT] kms_addfb_basic: executing
11894 11:35:22.160198 or no outputs, pipes: 16, outputs: 0
11895 11:35:22.163637 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11896 11:35:22.170592 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11897 11:35:22.176316 Using IGT<14>[ 18.126919] [IGT] kms_addfb_basic: exiting, ret=77
11898 11:35:22.180139 _SRANDOM=1721216121 for randomisation
11899 11:35:22.189722 Opened device: /dev/dri/c<8>[ 18.137811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11900 11:35:22.189824 ard0
11901 11:35:22.190098 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11903 11:35:22.196045 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11904 11:35:22.199548 Test requirement: is_intel_device(fd)
11905 11:35:22.209357 Test requirement not met in fun<14>[ 18.160878] [IGT] kms_addfb_basic: executing
11906 11:35:22.212704 ction igt_require_intel, file ../lib/drmtest.c:880:
11907 11:35:22.216311 Test requirement: is_intel_device(fd)
11908 11:35:22.222874 No KMS driver or no outputs, pipes: 16, outputs: 0
11909 11:35:22.226123 [1mSubtest smal<14>[ 18.178567] [IGT] kms_addfb_basic: exiting, ret=77
11910 11:35:22.229362 l-bo: SKIP (0.000s)[0m
11911 11:35:22.239170 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 18.189821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11912 11:35:22.239452 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11914 11:35:22.242545 inux: 6.1.96-cip24 aarch64)
11915 11:35:22.245719 Usi<8>[ 18.199489] <LAVA_SIGNAL_TESTSET STOP>
11916 11:35:22.245980 Received signal: <TESTSET> STOP
11917 11:35:22.246069 Closing test_set kms_addfb_basic
11918 11:35:22.252177 ng IGT_SRANDOM=1721216121 for randomisation
11919 11:35:22.252277 Opened device: /dev/dri/card0
11920 11:35:22.262837 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11921 11:35:22.269025 Test requirement: is_intel_devic<8>[ 18.221471] <LAVA_SIGNAL_TESTSET START kms_atomic>
11922 11:35:22.269128 e(fd)
11923 11:35:22.269389 Received signal: <TESTSET> START kms_atomic
11924 11:35:22.269478 Starting test_set kms_atomic
11925 11:35:22.278527 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11926 11:35:22.282049 Test requirement: is_intel_device(fd)
11927 11:35:22.288691 No KMS driver or no outputs, p<14>[ 18.240123] [IGT] kms_atomic: executing
11928 11:35:22.292106 ipes: 16, output<14>[ 18.245385] [IGT] kms_atomic: exiting, ret=77
11929 11:35:22.295430 s: 0
11930 11:35:22.298687 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11931 11:35:22.305091 <8>[ 18.255613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11932 11:35:22.305404 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11934 11:35:22.308531
11935 11:35:22.311934 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11936 11:35:22.318935 Using IGT_SRANDOM=1721216121 for randomisation
11937 11:35:22.319033 Opened device: /dev/dri/card0
11938 11:35:22.325250 Test require<14>[ 18.278053] [IGT] kms_atomic: executing
11939 11:35:22.331794 ment not met in <14>[ 18.282882] [IGT] kms_atomic: exiting, ret=77
11940 11:35:22.335132 function igt_require_intel, file ../lib/drmtest.c:880:
11941 11:35:22.344860 Test req<8>[ 18.293445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11942 11:35:22.345134 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11944 11:35:22.348555 uirement: is_intel_device(fd)
11945 11:35:22.354972 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11946 11:35:22.358386 Test requirement: is_intel_device(fd)
11947 11:35:22.361496 No KMS<14>[ 18.315238] [IGT] kms_atomic: executing
11948 11:35:22.368088 driver or no ou<14>[ 18.320540] [IGT] kms_atomic: exiting, ret=77
11949 11:35:22.371393 tputs, pipes: 16, outputs: 0
11950 11:35:22.384495 [1mSubtest addfb25-y-tiled-legacy<8>[ 18.330910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11951 11:35:22.384607 : SKIP (0.000s)[0m
11952 11:35:22.384858 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11954 11:35:22.391122 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11955 11:35:22.394365 Using IGT_SRANDOM=1721216121 for randomisation
11956 11:35:22.401122 Opened device: /dev/dri<14>[ 18.354114] [IGT] kms_atomic: executing
11957 11:35:22.401269 /card0
11958 11:35:22.407376 Test req<14>[ 18.359433] [IGT] kms_atomic: exiting, ret=77
11959 11:35:22.420720 uirement not met in function igt_require_intel, file ../lib/drmt<8>[ 18.369928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11960 11:35:22.420831 est.c:880:
11961 11:35:22.421087 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11963 11:35:22.423935 Test requirement: is_intel_device(fd)
11964 11:35:22.434006 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11965 11:35:22.440314 Test requirement: is_inte<14>[ 18.392061] [IGT] kms_atomic: executing
11966 11:35:22.440413 l_device(fd)
11967 11:35:22.444169 No<14>[ 18.396964] [IGT] kms_atomic: exiting, ret=77
11968 11:35:22.450791 KMS driver or no outputs, pipes: 16, outputs: 0
11969 11:35:22.457045 [1mSubtest ad<8>[ 18.407611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11970 11:35:22.457340 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11972 11:35:22.460125 dfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11973 11:35:22.466973 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11974 11:35:22.470457 Using IGT_SRANDOM=1721216122 for randomisation
11975 11:35:22.476893 Op<14>[ 18.428226] [IGT] kms_atomic: executing
11976 11:35:22.483686 ened device: /de<14>[ 18.433586] [IGT] kms_atomic: exiting, ret=77
11977 11:35:22.483787 v/dri/card0
11978 11:35:22.493393 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11980 11:35:22.496964 Test requirement not met in function igt_require_in<8>[ 18.444183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11981 11:35:22.497057 tel, file ../lib/drmtest.c:880:
11982 11:35:22.500180 Test requirement: is_intel_device(fd)
11983 11:35:22.510025 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11984 11:35:22.513441 Test<14>[ 18.466064] [IGT] kms_atomic: executing
11985 11:35:22.520025 requirement: is<14>[ 18.471188] [IGT] kms_atomic: exiting, ret=77
11986 11:35:22.520129 _intel_device(fd)
11987 11:35:22.532904 No KMS driver or no outputs, pipes: 16, outpu<8>[ 18.481844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11988 11:35:22.533052 ts: 0
11989 11:35:22.533325 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11991 11:35:22.539306 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11992 11:35:22.545954 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11993 11:35:22.549421 Using IGT_SRANDOM=172121<14>[ 18.503274] [IGT] kms_atomic: executing
11994 11:35:22.555857 6122 for randomi<14>[ 18.508716] [IGT] kms_atomic: exiting, ret=77
11995 11:35:22.559405 sation
11996 11:35:22.559506 Opened device: /dev/dri/card0
11997 11:35:22.569308 Test requirement not met <8>[ 18.519174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11998 11:35:22.569590 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12000 11:35:22.575522 in function igt_require_intel, file ../lib/drmtest.c:880:
12001 11:35:22.578945 Test requirement: is_intel_device(fd)
12002 11:35:22.589236 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 18.542852] [IGT] kms_atomic: executing
12003 11:35:22.592524 880:
12004 11:35:22.596056 Test requi<14>[ 18.548257] [IGT] kms_atomic: exiting, ret=77
12005 11:35:22.598798 rement: is_intel_device(fd)
12006 11:35:22.608791 No KMS driver or no outputs, pipes:<8>[ 18.558992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12007 11:35:22.609061 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12009 11:35:22.612140 16, outputs: 0
12010 11:35:22.615743 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12011 11:35:22.621860 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12012 11:35:22.628591 Using IGT_SRANDOM=1721216122 for randomisat<14>[ 18.581053] [IGT] kms_atomic: executing
12013 11:35:22.628688 ion
12014 11:35:22.635417 Opened devi<14>[ 18.587090] [IGT] kms_atomic: exiting, ret=77
12015 11:35:22.638491 ce: /dev/dri/card0
12016 11:35:22.648403 No KMS driver or no outputs, pipes: 16, outp<8>[ 18.597535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12017 11:35:22.648508 uts: 0
12018 11:35:22.648763 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12020 11:35:22.654895 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12021 11:35:22.661863 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12022 11:35:22.667969 Using IGT_SRANDOM=1721216122 fo<14>[ 18.619759] [IGT] kms_atomic: executing
12023 11:35:22.668052 r randomisation
12024 11:35:22.675004 <14>[ 18.625177] [IGT] kms_atomic: exiting, ret=77
12025 11:35:22.675084
12026 11:35:22.675143 Opened device: /dev/dri/card0
12027 11:35:22.688324 No KMS driver or no outputs, pip<8>[ 18.635564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12028 11:35:22.688435 es: 16, outputs: 0
12029 11:35:22.688695 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12031 11:35:22.694518 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12032 11:35:22.697884 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12033 11:35:22.704668 Using IGT_SRANDOM=1<14>[ 18.657825] [IGT] kms_atomic: executing
12034 11:35:22.711659 721216122 for ra<14>[ 18.662842] [IGT] kms_atomic: exiting, ret=77
12035 11:35:22.711744 ndomisation
12036 11:35:22.714377 Opened device: /dev/dri/card0
12037 11:35:22.724039 No KMS driver or no <8>[ 18.673255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12038 11:35:22.724321 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12040 11:35:22.727289 outputs, pipes: 16, outputs: 0
12041 11:35:22.731102 <8>[ 18.683375] <LAVA_SIGNAL_TESTSET STOP>
12042 11:35:22.731381 Received signal: <TESTSET> STOP
12043 11:35:22.731476 Closing test_set kms_atomic
12044 11:35:22.737952 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12045 11:35:22.744288 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12046 11:35:22.747566 Using IGT_SRANDOM=1721216122 for randomisation
12047 11:35:22.754283 Opened device: /dev/dri/c<8>[ 18.705741] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12048 11:35:22.754533 Received signal: <TESTSET> START kms_flip_event_leak
12049 11:35:22.754598 Starting test_set kms_flip_event_leak
12050 11:35:22.757016 ard0
12051 11:35:22.760624 No KMS driver or no outputs, pipes: 16, outputs: 0
12052 11:35:22.763749 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12053 11:35:22.773840 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 18.725711] [IGT] kms_flip_event_leak: executing
12054 11:35:22.780168 96-cip24 aarch64<14>[ 18.732001] [IGT] kms_flip_event_leak: exiting, ret=77
12055 11:35:22.780277 )
12056 11:35:22.786880 Using IGT_SRANDOM=1721216122 for randomisation
12057 11:35:22.793509 Opened device<8>[ 18.743252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12058 11:35:22.793599 : /dev/dri/card0
12059 11:35:22.793828 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12061 11:35:22.800023 No KMS driver <8>[ 18.751808] <LAVA_SIGNAL_TESTSET STOP>
12062 11:35:22.800272 Received signal: <TESTSET> STOP
12063 11:35:22.800365 Closing test_set kms_flip_event_leak
12064 11:35:22.803500 or no outputs, pipes: 16, outputs: 0
12065 11:35:22.806449 [1mSubtest test-only: SKIP (0.000s)[0m
12066 11:35:22.813287 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12067 11:35:22.816885 Using IGT_SRANDOM=1721216122 for randomisation
12068 11:35:22.823791 Opened devic<8>[ 18.774084] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12069 11:35:22.824073 Received signal: <TESTSET> START kms_prop_blob
12070 11:35:22.824143 Starting test_set kms_prop_blob
12071 11:35:22.826870 e: /dev/dri/card0
12072 11:35:22.829926 No KMS driver or no outputs, pipes: 16, outputs: 0
12073 11:35:22.833622 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12074 11:35:22.839752 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12075 11:35:22.845890 Using IGT_SRANDOM<14>[ 18.798073] [IGT] kms_prop_blob: executing
12076 11:35:22.852561 =1721216122 for <14>[ 18.803643] [IGT] kms_prop_blob: starting subtest basic
12077 11:35:22.852665 randomisation
12078 11:35:22.859435 O<14>[ 18.810442] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12079 11:35:22.866539 pened device: /d<14>[ 18.818237] [IGT] kms_prop_blob: exiting, ret=0
12080 11:35:22.869065 ev/dri/card0
12081 11:35:22.879540 No KMS driver or no outputs, pipes: 16, outputs: 0<8>[ 18.828861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12082 11:35:22.879634
12083 11:35:22.879903 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12085 11:35:22.882509 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12086 11:35:22.889189 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12087 11:35:22.899282 Using IGT_SRANDOM=1721216122 for rand<14>[ 18.850362] [IGT] kms_prop_blob: executing
12088 11:35:22.899369 omisation
12089 11:35:22.905631 Opene<14>[ 18.855189] [IGT] kms_prop_blob: starting subtest blob-prop-core
12090 11:35:22.912238 d device: /dev/d<14>[ 18.862842] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12091 11:35:22.915453 ri/card0
12092 11:35:22.919129 No KMS<14>[ 18.871364] [IGT] kms_prop_blob: exiting, ret=0
12093 11:35:22.925607 driver or no outputs, pipes: 16, outputs: 0
12094 11:35:22.931813 [1mSubtest plane-<8>[ 18.882150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12095 11:35:22.932087 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12097 11:35:22.935474 invalid-params-fence: SKIP (0.000s)[0m
12098 11:35:22.941831 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12099 11:35:22.945056 Using IGT_SRANDOM=1721216122 for randomisation
12100 11:35:22.951937 Ope<14>[ 18.903535] [IGT] kms_prop_blob: executing
12101 11:35:22.958700 ned device: /dev<14>[ 18.909199] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12102 11:35:22.962055 /dri/card0
12103 11:35:22.968459 No K<14>[ 18.917142] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12104 11:35:22.975085 MS driver or no <14>[ 18.925908] [IGT] kms_prop_blob: exiting, ret=0
12105 11:35:22.978252 outputs, pipes: 16, outputs: 0
12106 11:35:22.987876 [1mSubtest crtc-invalid-params:<8>[ 18.936958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12107 11:35:22.987954 SKIP (0.000s)[0m
12108 11:35:22.988182 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12110 11:35:22.994585 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12111 11:35:23.001133 Using IGT_SRANDOM=1721216122 for randomisation
12112 11:35:23.004933 Opened device: /dev/dri/<14>[ 18.958730] [IGT] kms_prop_blob: executing
12113 11:35:23.007937 card0
12114 11:35:23.014683 No KMS dr<14>[ 18.964045] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12115 11:35:23.024477 iver or no outpu<14>[ 18.971995] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12116 11:35:23.031270 ts, pipes: 16, o<14>[ 18.980860] [IGT] kms_prop_blob: exiting, ret=0
12117 11:35:23.031403 utputs: 0
12118 11:35:23.041296 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12120 11:35:23.044405 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)<8>[ 18.991459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12121 11:35:23.044482 [0m
12122 11:35:23.047549 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12123 11:35:23.054319 Using IGT_SRANDOM=1721216122 for randomisation
12124 11:35:23.057759 Opened device: /dev/dri/card0
12125 11:35:23.060656 No KMS d<14>[ 19.013418] [IGT] kms_prop_blob: executing
12126 11:35:23.067845 river or no outp<14>[ 19.019116] [IGT] kms_prop_blob: starting subtest blob-multiple
12127 11:35:23.077468 uts, pipes: 16, <14>[ 19.026567] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12128 11:35:23.077546 outputs: 0
12129 11:35:23.084032 [1m<14>[ 19.034906] [IGT] kms_prop_blob: exiting, ret=0
12130 11:35:23.087372 Subtest atomic-invalid-params: SKIP (0.000s)[0m
12131 11:35:23.097329 IGT-Version: 1<8>[ 19.045630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12132 11:35:23.097575 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12134 11:35:23.100279 .28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12135 11:35:23.104080 Using IGT_SRANDOM=1721216122 for randomisation
12136 11:35:23.106966 Opened device: /dev/dri/card0
12137 11:35:23.113497 No KMS driver or no outputs<14>[ 19.067757] [IGT] kms_prop_blob: executing
12138 11:35:23.123806 , pipes: 16, out<14>[ 19.072642] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12139 11:35:23.123909 puts: 0
12140 11:35:23.133713 [1mSub<14>[ 19.080663] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12141 11:35:23.140372 test atomic-plan<14>[ 19.089805] [IGT] kms_prop_blob: exiting, ret=0
12142 11:35:23.140450 e-damage: SKIP (0.000s)[0m
12143 11:35:23.153102 IGT-Version: 1.28-ga44ebfe (aarch64<8>[ 19.100600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12144 11:35:23.153216 ) (Linux: 6.1.96-cip24 aarch64)
12145 11:35:23.153444 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12147 11:35:23.159616 Using IGT_SRANDOM=1721216122 for randomisation
12148 11:35:23.163186 Opened device: /dev/dri/card0
12149 11:35:23.169719 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 19.122808] [IGT] kms_prop_blob: executing
12150 11:35:23.169797 0
12151 11:35:23.180238 [1mSubtest <14>[ 19.128208] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12152 11:35:23.186276 basic: SKIP (0.0<14>[ 19.135830] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12153 11:35:23.189653 00s)[0m
12154 11:35:23.192632 IGT-Ve<14>[ 19.144733] [IGT] kms_prop_blob: exiting, ret=0
12155 11:35:23.199690 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12156 11:35:23.206054 Us<8>[ 19.155390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12157 11:35:23.206301 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12159 11:35:23.209017 ing IGT_SRANDOM=1721216122 for randomisation
12160 11:35:23.212404 Opened device: /dev/dri/card0
12161 11:35:23.216232 Starting subtest: basic
12162 11:35:23.218822 [1mSubtest basic: SUCCESS (0.000s)[0m
12163 11:35:23.225565 IGT-Version: 1.28<14>[ 19.177358] [IGT] kms_prop_blob: executing
12164 11:35:23.232040 -ga44ebfe (aarch<14>[ 19.182586] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12165 11:35:23.242102 <14>[ 19.190611] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12166 11:35:23.245456 64) (Linux: 6.1.<14>[ 19.198354] [IGT] kms_prop_blob: exiting, ret=0
12167 11:35:23.248920 96-cip24 aarch64)
12168 11:35:23.258689 Using IGT_SRANDOM=1721216122 for randomisatio<8>[ 19.209119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12169 11:35:23.258940 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12171 11:35:23.262375 n
12172 11:35:23.262451 Opened device: /dev/dri/card0
12173 11:35:23.265565 Starting subtest: blob-prop-core
12174 11:35:23.272136 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12175 11:35:23.278371 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<14>[ 19.230702] [IGT] kms_prop_blob: executing
12176 11:35:23.285248 x: 6.1.96-cip24 <14>[ 19.236784] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12177 11:35:23.295206 <14>[ 19.244404] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12178 11:35:23.295285 aarch64)
12179 11:35:23.302308 Using <14>[ 19.251916] [IGT] kms_prop_blob: exiting, ret=0
12180 11:35:23.305091 IGT_SRANDOM=1721216122 for randomisation
12181 11:35:23.311923 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12183 11:35:23.315226 Opened device: /dev/dr<8>[ 19.262486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12184 11:35:23.315324 i/card0
12185 11:35:23.321648 Starting subtest: blob-<8>[ 19.272427] <LAVA_SIGNAL_TESTSET STOP>
12186 11:35:23.321764 prop-validate
12187 11:35:23.322019 Received signal: <TESTSET> STOP
12188 11:35:23.322108 Closing test_set kms_prop_blob
12189 11:35:23.324800 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12190 11:35:23.331317 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12191 11:35:23.338205 Using IGT_SRANDOM=1721216122 for randomisation
12192 11:35:23.341358 Opened <8>[ 19.294295] <LAVA_SIGNAL_TESTSET START kms_setmode>
12193 11:35:23.341603 Received signal: <TESTSET> START kms_setmode
12194 11:35:23.341666 Starting test_set kms_setmode
12195 11:35:23.344670 device: /dev/dri/card0
12196 11:35:23.348101 Starting subtest: blob-prop-lifetime
12197 11:35:23.351041 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12198 11:35:23.361298 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 19.312755] [IGT] kms_setmode: executing
12199 11:35:23.368167 6.1.96-cip24 aa<14>[ 19.318480] [IGT] kms_setmode: starting subtest basic
12200 11:35:23.368299 rch64)
12201 11:35:23.374317 Using IG<14>[ 19.325067] [IGT] kms_setmode: finished subtest basic, SKIP
12202 11:35:23.381122 T_SRANDOM=172121<14>[ 19.332237] [IGT] kms_setmode: exiting, ret=77
12203 11:35:23.384163 6122 for randomisation
12204 11:35:23.384262 Opened device: /dev/dri/card0
12205 11:35:23.394606 Starting <8>[ 19.342954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12206 11:35:23.394701 subtest: blob-multiple
12207 11:35:23.394931 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12209 11:35:23.400500 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12210 11:35:23.403907 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12211 11:35:23.410685 Using IGT_SRANDOM=1<14>[ 19.363720] [IGT] kms_setmode: executing
12212 11:35:23.420619 721216123 for ra<14>[ 19.369159] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12213 11:35:23.420705 ndomisation
12214 11:35:23.427034 Ope<14>[ 19.377163] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12215 11:35:23.433813 ned device: /dev<14>[ 19.386239] [IGT] kms_setmode: exiting, ret=77
12216 11:35:23.437179 /dri/card0
12217 11:35:23.440346 Starting subtest: invalid-get-prop-any
12218 11:35:23.447006 [1mSubtest <8>[ 19.396886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12219 11:35:23.447257 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12221 11:35:23.453312 invalid-get-prop-any: SUCCESS (0.000s)[0m
12222 11:35:23.456850 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12223 11:35:23.463256 Using IGT_SRANDOM=1721216123 for randomisation
12224 11:35:23.467115 <14>[ 19.419175] [IGT] kms_setmode: executing
12225 11:35:23.476675 Opened device: /<14>[ 19.424450] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12226 11:35:23.483438 <14>[ 19.432694] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12227 11:35:23.483651 dev/dri/card0
12228 11:35:23.489769 S<14>[ 19.440429] [IGT] kms_setmode: exiting, ret=77
12229 11:35:23.493621 tarting subtest: invalid-get-prop
12230 11:35:23.503212 [1mSubtest invalid-get-prop:<8>[ 19.451192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12231 11:35:23.503735 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12233 11:35:23.506647 SUCCESS (0.000s)[0m
12234 11:35:23.509647 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12235 11:35:23.516344 Using IGT_SRANDOM=1721216123 for randomisation
12236 11:35:23.523017 Opened device: /dev/d<14>[ 19.473789] [IGT] kms_setmode: executing
12237 11:35:23.523323 ri/card0
12238 11:35:23.529874 Starti<14>[ 19.479264] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12239 11:35:23.539726 ng subtest: inva<14>[ 19.487601] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12240 11:35:23.546037 lid-set-prop-any<14>[ 19.496965] [IGT] kms_setmode: exiting, ret=77
12241 11:35:23.546334
12242 11:35:23.549253 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12243 11:35:23.559640 IGT-Ve<8>[ 19.507523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12244 11:35:23.560163 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12246 11:35:23.565767 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12247 11:35:23.569067 Using IGT_SRANDOM=1721216123 for randomisation
12248 11:35:23.572570 Opened device: /dev/dri/card0
12249 11:35:23.575682 Starting subtest: invalid-set-prop
12250 11:35:23.582390 [1mSubtest invalid-set-prop: S<14>[ 19.534955] [IGT] kms_setmode: executing
12251 11:35:23.589060 UCCESS (0.000s)<14>[ 19.539991] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12252 11:35:23.592360 [0m
12253 11:35:23.598782 IGT-Version<14>[ 19.547816] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12254 11:35:23.605502 : 1.28-ga44ebfe <14>[ 19.556371] [IGT] kms_setmode: exiting, ret=77
12255 11:35:23.608601 (aarch64) (Linux: 6.1.96-cip24 aarch64)
12256 11:35:23.618413 Using IGT_SRANDOM=17212<8>[ 19.567251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12257 11:35:23.619006 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12259 11:35:23.621685 16123 for randomisation
12260 11:35:23.622017 Opened device: /dev/dri/card0
12261 11:35:23.625402 Starting subtest: basic
12262 11:35:23.628707 No dynamic tests executed.
12263 11:35:23.631495 [1mSubtest basic: SKIP (0.000s)[0m
12264 11:35:23.638842 IGT-Version: <14>[ 19.589358] [IGT] kms_setmode: executing
12265 11:35:23.644868 1.28-ga44ebfe (a<14>[ 19.594541] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12266 11:35:23.654729 <14>[ 19.603543] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12267 11:35:23.661226 arch64) (Linux: <14>[ 19.612063] [IGT] kms_setmode: exiting, ret=77
12268 11:35:23.661466 6.1.96-cip24 aarch64)
12269 11:35:23.674428 Using IGT_SRANDOM=1721216123 for randomis<8>[ 19.622694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12270 11:35:23.674595 ation
12271 11:35:23.674962 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12273 11:35:23.680829 Opened device: /dev/dri/c<8>[ 19.634350] <LAVA_SIGNAL_TESTSET STOP>
12274 11:35:23.681115 Received signal: <TESTSET> STOP
12275 11:35:23.681252 Closing test_set kms_setmode
12276 11:35:23.684003 ard0
12277 11:35:23.687431 Starting subtest: basic-clone-single-crtc
12278 11:35:23.687518 No dynamic tests executed.
12279 11:35:23.694061 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12280 11:35:23.703890 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 a<8>[ 19.656283] <LAVA_SIGNAL_TESTSET START kms_vblank>
12281 11:35:23.703969 arch64)
12282 11:35:23.704198 Received signal: <TESTSET> START kms_vblank
12283 11:35:23.704258 Starting test_set kms_vblank
12284 11:35:23.707400 Using IGT_SRANDOM=1721216123 for randomisation
12285 11:35:23.710955 Opened device: /dev/dri/card0
12286 11:35:23.717468 Starting subtest: invalid-clone-single-crtc
12287 11:35:23.717543 No dynamic tests executed.
12288 11:35:23.723466 [1mSubtest inv<14>[ 19.675492] [IGT] kms_vblank: executing
12289 11:35:23.730229 alid-clone-singl<14>[ 19.681460] [IGT] kms_vblank: exiting, ret=77
12290 11:35:23.730307 e-crtc: SKIP (0.000s)[0m
12291 11:35:23.736934 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12292 11:35:23.743381 Using IGT_SRANDOM=1721216123 for randomisation
12293 11:35:23.743459 Opened device: /dev/dri/card0
12294 11:35:23.753354 Starting subtest: invalid-clone-ex<8>[ 19.704990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12295 11:35:23.753626 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12297 11:35:23.756507 clusive-crtc
12298 11:35:23.756606 No dynamic tests executed.
12299 11:35:23.763795 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12300 11:35:23.769865 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12301 11:35:23.773305 Using IGT_SRANDOM=1721216123 for randomisation
12302 11:35:23.776612 Opened device: /dev/dri/card0
12303 11:35:23.779688 Starting subtest: clone-exclusive-crtc
12304 11:35:23.783449 No dynamic tests executed.
12305 11:35:23.786466 [1mSubtest clone-<14>[ 19.740499] [IGT] kms_vblank: executing
12306 11:35:23.792708 exclusive-crtc: <14>[ 19.746065] [IGT] kms_vblank: exiting, ret=77
12307 11:35:23.796077 SKIP (0.000s)[0m
12308 11:35:23.806107 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aar<8>[ 19.756854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12309 11:35:23.806215 ch64)
12310 11:35:23.806471 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12312 11:35:23.812647 Using IGT_SRANDOM=1721216123 for randomisation
12313 11:35:23.816287 Opened device: /dev/dri/card0
12314 11:35:23.819347 Starting subtest: invalid-clone-single-crtc-stealing
12315 11:35:23.822875 No dynamic tests executed.
12316 11:35:23.826303 [1mSubt<14>[ 19.779350] [IGT] kms_vblank: executing
12317 11:35:23.832658 est invalid-clon<14>[ 19.784719] [IGT] kms_vblank: exiting, ret=77
12318 11:35:23.835797 e-single-crtc-stealing: SKIP (0.000s)[0m
12319 11:35:23.845631 IGT-Version: 1.28-ga4<8>[ 19.795852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12320 11:35:23.845909 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12322 11:35:23.849468 4ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12323 11:35:23.852352 Using IGT_SRANDOM=1721216123 for randomisation
12324 11:35:23.855845 Opened device: /dev/dri/card0
12325 11:35:23.862246 No KMS driver or no outputs, pipes: 16, outputs: 0
12326 11:35:23.865495 [1mSubtest invalid: SKIP (0.000s)[0m
12327 11:35:23.872333 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-ci<14>[ 19.826168] [IGT] kms_vblank: executing
12328 11:35:23.875781 p24 aarch64)
12329 11:35:23.879101 Us<14>[ 19.831681] [IGT] kms_vblank: exiting, ret=77
12330 11:35:23.882099 ing IGT_SRANDOM=1721216123 for randomisation
12331 11:35:23.885294 Opened device: /dev/dri/card0
12332 11:35:23.984354 No <8>[ 19.842557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12333 11:35:23.984741 KMS driver or no outputs, pipes: 16, outputs: 0
12334 11:35:23.985093 [1mSubtest crtc-id: SKIP (0.000s)[0m
12335 11:35:23.985425 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12336 11:35:23.985671 Using IGT_SRANDOM=1721216123 for ra<14>[ 19.867072] [IGT] kms_vblank: executing
12337 11:35:23.985904 ndomisation
12338 11:35:23.986128 Ope<14>[ 19.872039] [IGT] kms_vblank: exiting, ret=77
12339 11:35:23.986351 ned device: /dev/dri/card0
12340 11:35:23.986571 No KMS driver or no outputs, pipes: 16, outputs: 0
12341 11:35:23.986793 [1mSubtest accu<8>[ 19.885124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12342 11:35:23.987013 racy-idle: SKIP (0.000s)[0m
12343 11:35:23.987225 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12344 11:35:23.987438 Using IGT_SRANDOM=1721216123 for randomisation
12345 11:35:23.987654 Opened device:<14>[ 19.906862] [IGT] kms_vblank: executing
12346 11:35:23.987876 /dev/dri/card0
12347 11:35:23.988107 <14>[ 19.911942] [IGT] kms_vblank: exiting, ret=77
12348 11:35:23.988393
12349 11:35:23.988615 No KMS driver or no outputs, pipes: 16, outputs: 0
12350 11:35:23.988835 [1mSubtest<8>[ 19.923155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12351 11:35:23.989052 query-idle: SKIP (0.000s)[0m
12352 11:35:23.989294 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12353 11:35:23.989531 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12355 11:35:23.989701 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12357 11:35:23.989856 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12359 11:35:23.990016 Using IGT_SRANDOM=1721216123 for randomisation
12360 11:35:23.991871 Opened device: /dev/dri/card<14>[ 19.944109] [IGT] kms_vblank: executing
12361 11:35:23.991952 0
12362 11:35:23.998172 No KMS driver<14>[ 19.950437] [IGT] kms_vblank: exiting, ret=77
12363 11:35:24.001150 or no outputs, pipes: 16, outputs: 0
12364 11:35:24.011654 [1mSubtest query-idle-ha<8>[ 19.961115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12365 11:35:24.011911 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12367 11:35:24.014642 ng: SKIP (0.000s)[0m
12368 11:35:24.018210 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12369 11:35:24.024196 Using IGT_SRANDOM=1721216123 for randomisation
12370 11:35:24.027804 Opened device: /dev/d<14>[ 19.982594] [IGT] kms_vblank: executing
12371 11:35:24.031010 ri/card0
12372 11:35:24.034645 No KMS<14>[ 19.987387] [IGT] kms_vblank: exiting, ret=77
12373 11:35:24.041499 driver or no outputs, pipes: 16, outputs: 0
12374 11:35:24.047912 [1mSubtest query-<8>[ 19.998380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12375 11:35:24.048163 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12377 11:35:24.051423 forked: SKIP (0.000s)[0m
12378 11:35:24.057568 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12379 11:35:24.060760 Using IGT_SRANDOM=1721216123 for randomisation
12380 11:35:24.064086 Opened device: /dev/dri/card0
12381 11:35:24.067403 No KMS driver or n<14>[ 20.022146] [IGT] kms_vblank: executing
12382 11:35:24.073981 o outputs, pipes<14>[ 20.026845] [IGT] kms_vblank: exiting, ret=77
12383 11:35:24.077059 : 16, outputs: 0
12384 11:35:24.080841 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12385 11:35:24.090854 IGT-Version:<8>[ 20.038118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12386 11:35:24.091236 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12388 11:35:24.093544 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12389 11:35:24.096869 Using IGT_SRANDOM=1721216123 for randomisation
12390 11:35:24.100267 Opened device: /dev/dri/card0
12391 11:35:24.110647 No KMS driver or no outputs, pipes: 16, o<14>[ 20.061925] [IGT] kms_vblank: executing
12392 11:35:24.111041 utputs: 0
12393 11:35:24.114512 [1mS<14>[ 20.066835] [IGT] kms_vblank: exiting, ret=77
12394 11:35:24.117098 ubtest query-busy: SKIP (0.000s)[0m
12395 11:35:24.130486 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<8>[ 20.078114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12396 11:35:24.130844 x: 6.1.96-cip24 aarch64)
12397 11:35:24.131348 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12399 11:35:24.137061 Using IGT_SRANDOM=1721216123 for randomisation
12400 11:35:24.140356 Opened device: /dev/dri/card0
12401 11:35:24.143223 No KMS driver or no outputs, pipes: 16, outputs: 0
12402 11:35:24.150262 [1mSubtest query-b<14>[ 20.100751] [IGT] kms_vblank: executing
12403 11:35:24.156595 usy-hang: SKIP (<14>[ 20.106732] [IGT] kms_vblank: exiting, ret=77
12404 11:35:24.156962 0.000s)[0m
12405 11:35:24.163163 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12406 11:35:24.169796 <8>[ 20.118884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12407 11:35:24.170160
12408 11:35:24.170748 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12410 11:35:24.172842 Using IGT_SRANDOM=1721216124 for randomisation
12411 11:35:24.176676 Opened device: /dev/dri/card0
12412 11:35:24.183238 No KMS driver or no outputs, pipes: 16, outputs: 0
12413 11:35:24.186226 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12414 11:35:24.189709 IGT-Versio<14>[ 20.142708] [IGT] kms_vblank: executing
12415 11:35:24.196224 n: 1.28-ga44ebfe<14>[ 20.148663] [IGT] kms_vblank: exiting, ret=77
12416 11:35:24.199348 (aarch64) (Linux: 6.1.96-cip24 aarch64)
12417 11:35:24.209215 Using IGT_SRANDOM=1721<8>[ 20.159317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12418 11:35:24.209804 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12420 11:35:24.212386 216124 for randomisation
12421 11:35:24.216051 Opened device: /dev/dri/card0
12422 11:35:24.219179 No KMS driver or no outputs, pipes: 16, outputs: 0
12423 11:35:24.222717 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12424 11:35:24.228860 IGT-Version:<14>[ 20.181550] [IGT] kms_vblank: executing
12425 11:35:24.235607 1.28-ga44ebfe (<14>[ 20.186467] [IGT] kms_vblank: exiting, ret=77
12426 11:35:24.238589 aarch64) (Linux: 6.1.96-cip24 aarch64)
12427 11:35:24.248722 Using IGT_SRANDOM=1721216124 for randomi<8>[ 20.198014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12428 11:35:24.249077 sation
12429 11:35:24.249621 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12431 11:35:24.252154 Opened device: /dev/dri/card0
12432 11:35:24.255141 No KMS driver or no outputs, pipes: 16, outputs: 0
12433 11:35:24.261860 [1mSubtest wait-idle: SKIP (0.000s)[0m
12434 11:35:24.268267 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 20.220649] [IGT] kms_vblank: executing
12435 11:35:24.274734 : 6.1.96-cip24 a<14>[ 20.226264] [IGT] kms_vblank: exiting, ret=77
12436 11:35:24.275172 arch64)
12437 11:35:24.278276 Using IGT_SRANDOM=1721216124 for randomisation
12438 11:35:24.287790 Opened <8>[ 20.237337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12439 11:35:24.288143 device: /dev/dri/card0
12440 11:35:24.288649 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12442 11:35:24.294551 No KMS driver or no outputs, pipes: 16, outputs: 0
12443 11:35:24.297735 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12444 11:35:24.304536 IGT-Version: 1.28-ga44ebfe (aarch64) <14>[ 20.257936] [IGT] kms_vblank: executing
12445 11:35:24.311450 (Linux: 6.1.96-c<14>[ 20.263051] [IGT] kms_vblank: exiting, ret=77
12446 11:35:24.311806 ip24 aarch64)
12447 11:35:24.317784 Using IGT_SRANDOM=1721216124 for randomisation
12448 11:35:24.324382 O<8>[ 20.274204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12449 11:35:24.325008 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12451 11:35:24.327815 pened device: /dev/dri/card0
12452 11:35:24.330990 No KMS driver or no outputs, pipes: 16, outputs: 0
12453 11:35:24.334155 [1mSubtest wait-forked: SKIP (0.000s)[0m
12454 11:35:24.340710 IGT-Version: 1.28-ga44ebfe (aarch6<14>[ 20.295198] [IGT] kms_vblank: executing
12455 11:35:24.346927 4) (Linux: 6.1.9<14>[ 20.300209] [IGT] kms_vblank: exiting, ret=77
12456 11:35:24.350718 6-cip24 aarch64)
12457 11:35:24.354023 Using IGT_SRANDOM=1721216124 for randomisation
12458 11:35:24.360161 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12460 11:35:24.363541 Opened device:<8>[ 20.312517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12461 11:35:24.363646 /dev/dri/card0
12462 11:35:24.366718 No KMS driver or no outputs, pipes: 16, outputs: 0
12463 11:35:24.373899 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12464 11:35:24.376552 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12465 11:35:24.383522 Using <14>[ 20.335999] [IGT] kms_vblank: executing
12466 11:35:24.390258 IGT_SRANDOM=1721<14>[ 20.341058] [IGT] kms_vblank: exiting, ret=77
12467 11:35:24.390345 216124 for randomisation
12468 11:35:24.392919 Opened device: /dev/dri/card0
12469 11:35:24.402851 No KMS <8>[ 20.352055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12470 11:35:24.403131 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12472 11:35:24.406460 driver or no outputs, pipes: 16, outputs: 0
12473 11:35:24.410037 [1mSubtest wait-busy: SKIP (0.000s)[0m
12474 11:35:24.416492 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12475 11:35:24.419456 Using<14>[ 20.373254] [IGT] kms_vblank: executing
12476 11:35:24.426014 IGT_SRANDOM=172<14>[ 20.378044] [IGT] kms_vblank: exiting, ret=77
12477 11:35:24.429130 1216124 for randomisation
12478 11:35:24.429264 Opened device: /dev/dri/card0
12479 11:35:24.439304 No KMS driver or no ou<8>[ 20.389178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12480 11:35:24.439644 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12482 11:35:24.442703 tputs, pipes: 16, outputs: 0
12483 11:35:24.446588 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12484 11:35:24.452464 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12485 11:35:24.459183 Using IGT_SRAND<14>[ 20.411423] [IGT] kms_vblank: executing
12486 11:35:24.466041 OM=1721216124 fo<14>[ 20.416466] [IGT] kms_vblank: exiting, ret=77
12487 11:35:24.466162 r randomisation
12488 11:35:24.469042 Opened device: /dev/dri/card0
12489 11:35:24.479224 No KMS driver or<8>[ 20.427452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12490 11:35:24.479526 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12492 11:35:24.481876 no outputs, pipes: 16, outputs: 0
12493 11:35:24.485273 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12494 11:35:24.492037 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12495 11:35:24.495534 Using I<14>[ 20.449154] [IGT] kms_vblank: executing
12496 11:35:24.501973 GT_SRANDOM=17212<14>[ 20.454095] [IGT] kms_vblank: exiting, ret=77
12497 11:35:24.505090 16124 for randomisation
12498 11:35:24.508582 Opened device: /dev/dri/card0
12499 11:35:24.514891 No KMS driver or no outp<8>[ 20.466395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12500 11:35:24.515205 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12502 11:35:24.518523 uts, pipes: 16, outputs: 0
12503 11:35:24.525295 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12504 11:35:24.528272 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12505 11:35:24.534836 Using IGT_<14>[ 20.488308] [IGT] kms_vblank: executing
12506 11:35:24.541566 SRANDOM=17212161<14>[ 20.493442] [IGT] kms_vblank: exiting, ret=77
12507 11:35:24.541687 24 for randomisation
12508 11:35:24.544960 Opened device: /dev/dri/card0
12509 11:35:24.554832 No KMS driv<8>[ 20.504174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12510 11:35:24.555141 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12512 11:35:24.558072 er or no outputs, pipes: 16, outputs: 0
12513 11:35:24.564326 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12514 11:35:24.574504 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)<14>[ 20.525874] [IGT] kms_vblank: executing
12515 11:35:24.574636
12516 11:35:24.577639 Using IGT_SRAN<14>[ 20.531167] [IGT] kms_vblank: exiting, ret=77
12517 11:35:24.580916 DOM=1721216124 for randomisation
12518 11:35:24.584867 Opened device: /dev/dri/card0
12519 11:35:24.594291 <8>[ 20.542316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12520 11:35:24.594436
12521 11:35:24.594718 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12523 11:35:24.597366 No KMS driver or no outputs, pipes: 16, outputs: 0
12524 11:35:24.603905 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12525 11:35:24.610430 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 20.564192] [IGT] kms_vblank: executing
12526 11:35:24.616996 96-cip24 aarch64<14>[ 20.569115] [IGT] kms_vblank: exiting, ret=77
12527 11:35:24.617127 )
12528 11:35:24.620575 Using IGT_SRANDOM=1721216124 for randomisation
12529 11:35:24.633386 Opened device: /dev/dri/card0<8>[ 20.581293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12530 11:35:24.633471
12531 11:35:24.633700 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12533 11:35:24.637141 No KMS driver or no outputs, pipes: 16, outputs: 0
12534 11:35:24.644130 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12535 11:35:24.650096 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 20.603767] [IGT] kms_vblank: executing
12536 11:35:24.656763 96-cip24 aarch64<14>[ 20.608948] [IGT] kms_vblank: exiting, ret=77
12537 11:35:24.656846 )
12538 11:35:24.660338 Using IGT_SRANDOM=1721216124 for randomisation
12539 11:35:24.670352 Opened device: /dev/dri/card0<8>[ 20.621046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12540 11:35:24.670622 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12542 11:35:24.673387
12543 11:35:24.676548 No KMS driver or no outputs, pipes: 16, outputs: 0
12544 11:35:24.683635 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12545 11:35:24.690014 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <14>[ 20.643083] [IGT] kms_vblank: executing
12546 11:35:24.696449 6.1.96-cip24 aar<14>[ 20.648104] [IGT] kms_vblank: exiting, ret=77
12547 11:35:24.696643 ch64)
12548 11:35:24.699703 Using IGT_SRANDOM=1721216124 for randomisation
12549 11:35:24.709773 Opened de<8>[ 20.658969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12550 11:35:24.710273 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12552 11:35:24.713594 vice: /dev/dri/card0
12553 11:35:24.716722 No KMS driver or no outputs, pipes: 16, outputs: 0
12554 11:35:24.720256 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12555 11:35:24.726698 IGT-Version: 1.28-ga44ebfe (aa<14>[ 20.680532] [IGT] kms_vblank: executing
12556 11:35:24.733345 rch64) (Linux: 6<14>[ 20.685734] [IGT] kms_vblank: exiting, ret=77
12557 11:35:24.736108 .1.96-cip24 aarch64)
12558 11:35:24.739608 Using IGT_SRANDOM=1721216124 for randomisation
12559 11:35:24.749416 Opened dev<8>[ 20.696995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12560 11:35:24.750019 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12562 11:35:24.752951 ice: /dev/dri/card0
12563 11:35:24.756824 No KMS driver or no outputs, pipes: 16, outputs: 0
12564 11:35:24.759234 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12565 11:35:24.765836 IGT-Version: 1.28-ga44ebfe (aar<14>[ 20.720239] [IGT] kms_vblank: executing
12566 11:35:24.772388 ch64) (Linux: 6.<14>[ 20.725387] [IGT] kms_vblank: exiting, ret=77
12567 11:35:24.776014 1.96-cip24 aarch64)
12568 11:35:24.779244 Using IGT_SRANDOM=1721216124 for randomisation
12569 11:35:24.789183 Opened devi<8>[ 20.737066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12570 11:35:24.789371 ce: /dev/dri/card0
12571 11:35:24.789690 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12573 11:35:24.795729 No KMS drive<8>[ 20.748197] <LAVA_SIGNAL_TESTSET STOP>
12574 11:35:24.796087 Received signal: <TESTSET> STOP
12575 11:35:24.796212 Closing test_set kms_vblank
12576 11:35:24.802576 r or no outputs,<8>[ 20.753842] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14864586_1.5.2.3.1>
12577 11:35:24.802882 Received signal: <ENDRUN> 0_igt-kms-mediatek 14864586_1.5.2.3.1
12578 11:35:24.802990 Ending use of test pattern.
12579 11:35:24.803066 Ending test lava.0_igt-kms-mediatek (14864586_1.5.2.3.1), duration 6.22
12581 11:35:24.805470 pipes: 16, outputs: 0
12582 11:35:24.811991 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12583 11:35:24.818303 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
12584 11:35:24.821874 Using IGT_SRANDOM=1721216124 for randomisation
12585 11:35:24.824809 Opened device: /dev/dri/card0
12586 11:35:24.828502 No KMS driver or no outputs, pipes: 16, outputs: 0
12587 11:35:24.835231 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12588 11:35:24.835311 + set +x
12589 11:35:24.835372 <LAVA_TEST_RUNNER EXIT>
12590 11:35:24.835600 ok: lava_test_shell seems to have completed
12591 11:35:24.836969 getclient-simple:
set: core_auth
result: pass
getclient-master-drop:
set: core_auth
result: pass
basic-auth:
set: core_auth
result: pass
many-magics:
set: core_auth
result: pass
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
invalid-buffer:
set: drm_read
result: skip
fault-buffer:
set: drm_read
result: skip
empty-block:
set: drm_read
result: skip
empty-nonblock:
set: drm_read
result: skip
short-buffer-block:
set: drm_read
result: skip
short-buffer-nonblock:
set: drm_read
result: skip
short-buffer-wakeup:
set: drm_read
result: skip
unused-handle:
set: kms_addfb_basic
result: pass
unused-pitches:
set: kms_addfb_basic
result: pass
unused-offsets:
set: kms_addfb_basic
result: pass
unused-modifier:
set: kms_addfb_basic
result: pass
clobberred-modifier:
set: kms_addfb_basic
result: skip
invalid-smem-bo-on-discrete:
set: kms_addfb_basic
result: skip
legacy-format:
set: kms_addfb_basic
result: pass
no-handle:
set: kms_addfb_basic
result: pass
basic:
set: kms_setmode
result: skip
bad-pitch-0:
set: kms_addfb_basic
result: pass
bad-pitch-32:
set: kms_addfb_basic
result: pass
bad-pitch-63:
set: kms_addfb_basic
result: pass
bad-pitch-128:
set: kms_addfb_basic
result: pass
bad-pitch-256:
set: kms_addfb_basic
result: pass
bad-pitch-1024:
set: kms_addfb_basic
result: pass
bad-pitch-999:
set: kms_addfb_basic
result: pass
bad-pitch-65536:
set: kms_addfb_basic
result: pass
invalid-get-prop-any:
set: kms_prop_blob
result: pass
invalid-get-prop:
set: kms_prop_blob
result: pass
invalid-set-prop-any:
set: kms_prop_blob
result: pass
invalid-set-prop:
set: kms_prop_blob
result: pass
master-rmfb:
set: kms_addfb_basic
result: pass
addfb25-modifier-no-flag:
set: kms_addfb_basic
result: pass
addfb25-bad-modifier:
set: kms_addfb_basic
result: fail
addfb25-x-tiled-mismatch-legacy:
set: kms_addfb_basic
result: skip
addfb25-x-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-framebuffer-vs-set-tiling:
set: kms_addfb_basic
result: skip
basic-x-tiled-legacy:
set: kms_addfb_basic
result: skip
framebuffer-vs-set-tiling:
set: kms_addfb_basic
result: skip
tile-pitch-mismatch:
set: kms_addfb_basic
result: skip
basic-y-tiled-legacy:
set: kms_addfb_basic
result: skip
size-max:
set: kms_addfb_basic
result: skip
too-wide:
set: kms_addfb_basic
result: skip
too-high:
set: kms_addfb_basic
result: skip
bo-too-small:
set: kms_addfb_basic
result: skip
small-bo:
set: kms_addfb_basic
result: skip
bo-too-small-due-to-tiling:
set: kms_addfb_basic
result: skip
addfb25-y-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-yf-tiled-legacy:
set: kms_addfb_basic
result: skip
addfb25-y-tiled-small-legacy:
set: kms_addfb_basic
result: skip
addfb25-4-tiled:
set: kms_addfb_basic
result: skip
plane-overlay-legacy:
set: kms_atomic
result: skip
plane-primary-legacy:
set: kms_atomic
result: skip
plane-primary-overlay-mutable-zpos:
set: kms_atomic
result: skip
plane-immutable-zpos:
set: kms_atomic
result: skip
test-only:
set: kms_atomic
result: skip
plane-cursor-legacy:
set: kms_atomic
result: skip
plane-invalid-params:
set: kms_atomic
result: skip
plane-invalid-params-fence:
set: kms_atomic
result: skip
crtc-invalid-params:
set: kms_atomic
result: skip
crtc-invalid-params-fence:
set: kms_atomic
result: skip
atomic-invalid-params:
set: kms_atomic
result: skip
atomic-plane-damage:
set: kms_atomic
result: skip
blob-prop-core:
set: kms_prop_blob
result: pass
blob-prop-validate:
set: kms_prop_blob
result: pass
blob-prop-lifetime:
set: kms_prop_blob
result: pass
blob-multiple:
set: kms_prop_blob
result: pass
basic-clone-single-crtc:
set: kms_setmode
result: skip
invalid-clone-single-crtc:
set: kms_setmode
result: skip
invalid-clone-exclusive-crtc:
set: kms_setmode
result: skip
clone-exclusive-crtc:
set: kms_setmode
result: skip
invalid-clone-single-crtc-stealing:
set: kms_setmode
result: skip
invalid:
set: kms_vblank
result: skip
crtc-id:
set: kms_vblank
result: skip
accuracy-idle:
set: kms_vblank
result: skip
query-idle:
set: kms_vblank
result: skip
query-idle-hang:
set: kms_vblank
result: skip
query-forked:
set: kms_vblank
result: skip
query-forked-hang:
set: kms_vblank
result: skip
query-busy:
set: kms_vblank
result: skip
query-busy-hang:
set: kms_vblank
result: skip
query-forked-busy:
set: kms_vblank
result: skip
query-forked-busy-hang:
set: kms_vblank
result: skip
wait-idle:
set: kms_vblank
result: skip
wait-idle-hang:
set: kms_vblank
result: skip
wait-forked:
set: kms_vblank
result: skip
wait-forked-hang:
set: kms_vblank
result: skip
wait-busy:
set: kms_vblank
result: skip
wait-busy-hang:
set: kms_vblank
result: skip
wait-forked-busy:
set: kms_vblank
result: skip
wait-forked-busy-hang:
set: kms_vblank
result: skip
ts-continuation-idle:
set: kms_vblank
result: skip
ts-continuation-idle-hang:
set: kms_vblank
result: skip
ts-continuation-dpms-rpm:
set: kms_vblank
result: skip
ts-continuation-dpms-suspend:
set: kms_vblank
result: skip
ts-continuation-suspend:
set: kms_vblank
result: skip
ts-continuation-modeset:
set: kms_vblank
result: skip
ts-continuation-modeset-hang:
set: kms_vblank
result: skip
ts-continuation-modeset-rpm:
set: kms_vblank
result: skip
12592 11:35:24.837121 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12593 11:35:24.837252 end: 3 lava-test-retry (duration 00:00:07) [common]
12594 11:35:24.837333 start: 4 finalize (timeout 00:06:53) [common]
12595 11:35:24.837413 start: 4.1 power-off (timeout 00:00:30) [common]
12596 11:35:24.837539 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
12597 11:35:26.907545 >> Command sent successfully.
12598 11:35:26.910779 Returned 0 in 2 seconds
12599 11:35:26.910925 end: 4.1 power-off (duration 00:00:02) [common]
12601 11:35:26.911116 start: 4.2 read-feedback (timeout 00:06:51) [common]
12602 11:35:26.911252 Listened to connection for namespace 'common' for up to 1s
12603 11:35:26.911541 Listened to connection for namespace 'common' for up to 1s
12604 11:35:27.912393 Finalising connection for namespace 'common'
12605 11:35:27.913032 Disconnecting from shell: Finalise
12606 11:35:27.913561 / #
12607 11:35:28.014466 end: 4.2 read-feedback (duration 00:00:01) [common]
12608 11:35:28.015172 end: 4 finalize (duration 00:00:03) [common]
12609 11:35:28.015863 Cleaning after the job
12610 11:35:28.016461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/ramdisk
12611 11:35:28.045499 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/kernel
12612 11:35:28.071188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/dtb
12613 11:35:28.071419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864586/tftp-deploy-tnkxt4xu/modules
12614 11:35:28.077808 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864586
12615 11:35:28.183878 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864586
12616 11:35:28.184026 Job finished correctly