Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 90
1 11:34:23.332708 lava-dispatcher, installed at version: 2024.05
2 11:34:23.332910 start: 0 validate
3 11:34:23.333026 Start time: 2024-07-17 11:34:23.333020+00:00 (UTC)
4 11:34:23.333158 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:34:23.333305 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:34:23.586823 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:34:23.587562 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:34:23.853423 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:34:23.854276 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:34:24.107879 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:34:24.108495 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:34:24.374372 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:34:24.375042 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:34:24.644691 validate duration: 1.31
16 11:34:24.645833 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:34:24.646294 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:34:24.646714 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:34:24.647643 Not decompressing ramdisk as can be used compressed.
20 11:34:24.648105 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:34:24.648436 saving as /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/ramdisk/initrd.cpio.gz
22 11:34:24.648782 total size: 5628169 (5 MB)
23 11:34:24.653296 progress 0 % (0 MB)
24 11:34:24.661904 progress 5 % (0 MB)
25 11:34:24.668759 progress 10 % (0 MB)
26 11:34:24.672808 progress 15 % (0 MB)
27 11:34:24.676664 progress 20 % (1 MB)
28 11:34:24.679773 progress 25 % (1 MB)
29 11:34:24.682597 progress 30 % (1 MB)
30 11:34:24.685416 progress 35 % (1 MB)
31 11:34:24.687496 progress 40 % (2 MB)
32 11:34:24.689981 progress 45 % (2 MB)
33 11:34:24.691885 progress 50 % (2 MB)
34 11:34:24.693907 progress 55 % (2 MB)
35 11:34:24.695922 progress 60 % (3 MB)
36 11:34:24.697613 progress 65 % (3 MB)
37 11:34:24.699442 progress 70 % (3 MB)
38 11:34:24.700977 progress 75 % (4 MB)
39 11:34:24.702599 progress 80 % (4 MB)
40 11:34:24.704105 progress 85 % (4 MB)
41 11:34:24.705705 progress 90 % (4 MB)
42 11:34:24.707174 progress 95 % (5 MB)
43 11:34:24.708502 progress 100 % (5 MB)
44 11:34:24.708701 5 MB downloaded in 0.06 s (89.55 MB/s)
45 11:34:24.708845 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:34:24.709064 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:34:24.709151 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:34:24.709228 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:34:24.709356 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:34:24.709422 saving as /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/kernel/Image
52 11:34:24.709476 total size: 54813184 (52 MB)
53 11:34:24.709530 No compression specified
54 11:34:24.710721 progress 0 % (0 MB)
55 11:34:24.723781 progress 5 % (2 MB)
56 11:34:24.737044 progress 10 % (5 MB)
57 11:34:24.749974 progress 15 % (7 MB)
58 11:34:24.763056 progress 20 % (10 MB)
59 11:34:24.776243 progress 25 % (13 MB)
60 11:34:24.789204 progress 30 % (15 MB)
61 11:34:24.802458 progress 35 % (18 MB)
62 11:34:24.815887 progress 40 % (20 MB)
63 11:34:24.828807 progress 45 % (23 MB)
64 11:34:24.841914 progress 50 % (26 MB)
65 11:34:24.855155 progress 55 % (28 MB)
66 11:34:24.868116 progress 60 % (31 MB)
67 11:34:24.881316 progress 65 % (34 MB)
68 11:34:24.894430 progress 70 % (36 MB)
69 11:34:24.907619 progress 75 % (39 MB)
70 11:34:24.920805 progress 80 % (41 MB)
71 11:34:24.933862 progress 85 % (44 MB)
72 11:34:24.946986 progress 90 % (47 MB)
73 11:34:24.960065 progress 95 % (49 MB)
74 11:34:24.973016 progress 100 % (52 MB)
75 11:34:24.973264 52 MB downloaded in 0.26 s (198.17 MB/s)
76 11:34:24.973408 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:34:24.973614 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:34:24.973694 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:34:24.973769 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:34:24.973897 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 11:34:24.973964 saving as /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 11:34:24.974017 total size: 57695 (0 MB)
84 11:34:24.974069 No compression specified
85 11:34:24.975172 progress 56 % (0 MB)
86 11:34:24.975425 progress 100 % (0 MB)
87 11:34:24.975612 0 MB downloaded in 0.00 s (34.55 MB/s)
88 11:34:24.975721 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:34:24.975920 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:34:24.975994 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:34:24.976071 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:34:24.976175 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:34:24.976234 saving as /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/nfsrootfs/full.rootfs.tar
95 11:34:24.976286 total size: 120894716 (115 MB)
96 11:34:24.976339 Using unxz to decompress xz
97 11:34:24.977551 progress 0 % (0 MB)
98 11:34:25.306535 progress 5 % (5 MB)
99 11:34:25.638012 progress 10 % (11 MB)
100 11:34:25.974609 progress 15 % (17 MB)
101 11:34:26.289451 progress 20 % (23 MB)
102 11:34:26.588298 progress 25 % (28 MB)
103 11:34:26.930166 progress 30 % (34 MB)
104 11:34:27.240675 progress 35 % (40 MB)
105 11:34:27.407763 progress 40 % (46 MB)
106 11:34:27.587182 progress 45 % (51 MB)
107 11:34:27.879385 progress 50 % (57 MB)
108 11:34:28.236159 progress 55 % (63 MB)
109 11:34:28.563496 progress 60 % (69 MB)
110 11:34:28.894718 progress 65 % (74 MB)
111 11:34:29.227722 progress 70 % (80 MB)
112 11:34:29.571725 progress 75 % (86 MB)
113 11:34:29.908059 progress 80 % (92 MB)
114 11:34:30.243773 progress 85 % (98 MB)
115 11:34:30.583825 progress 90 % (103 MB)
116 11:34:30.895376 progress 95 % (109 MB)
117 11:34:31.248761 progress 100 % (115 MB)
118 11:34:31.254029 115 MB downloaded in 6.28 s (18.37 MB/s)
119 11:34:31.254183 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:34:31.254388 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:34:31.254464 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:34:31.254538 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:34:31.254665 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:34:31.254725 saving as /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/modules/modules.tar
126 11:34:31.254778 total size: 8610184 (8 MB)
127 11:34:31.254832 Using unxz to decompress xz
128 11:34:31.256114 progress 0 % (0 MB)
129 11:34:31.275978 progress 5 % (0 MB)
130 11:34:31.299512 progress 10 % (0 MB)
131 11:34:31.322701 progress 15 % (1 MB)
132 11:34:31.346059 progress 20 % (1 MB)
133 11:34:31.368789 progress 25 % (2 MB)
134 11:34:31.391396 progress 30 % (2 MB)
135 11:34:31.413160 progress 35 % (2 MB)
136 11:34:31.438412 progress 40 % (3 MB)
137 11:34:31.462356 progress 45 % (3 MB)
138 11:34:31.486755 progress 50 % (4 MB)
139 11:34:31.512072 progress 55 % (4 MB)
140 11:34:31.536588 progress 60 % (4 MB)
141 11:34:31.559085 progress 65 % (5 MB)
142 11:34:31.583514 progress 70 % (5 MB)
143 11:34:31.609378 progress 75 % (6 MB)
144 11:34:31.635926 progress 80 % (6 MB)
145 11:34:31.658704 progress 85 % (7 MB)
146 11:34:31.681054 progress 90 % (7 MB)
147 11:34:31.703457 progress 95 % (7 MB)
148 11:34:31.725312 progress 100 % (8 MB)
149 11:34:31.730605 8 MB downloaded in 0.48 s (17.26 MB/s)
150 11:34:31.730767 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:34:31.731002 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:34:31.731092 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:34:31.731181 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:34:35.205666 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s
156 11:34:35.205839 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:34:35.205928 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:34:35.206081 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt
159 11:34:35.206197 makedir: /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin
160 11:34:35.206286 makedir: /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/tests
161 11:34:35.206373 makedir: /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/results
162 11:34:35.206453 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-add-keys
163 11:34:35.206576 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-add-sources
164 11:34:35.206690 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-background-process-start
165 11:34:35.206803 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-background-process-stop
166 11:34:35.206923 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-common-functions
167 11:34:35.207036 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-echo-ipv4
168 11:34:35.207147 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-install-packages
169 11:34:35.207255 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-installed-packages
170 11:34:35.207363 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-os-build
171 11:34:35.207472 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-probe-channel
172 11:34:35.207581 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-probe-ip
173 11:34:35.207690 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-target-ip
174 11:34:35.207800 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-target-mac
175 11:34:35.207908 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-target-storage
176 11:34:35.208021 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-case
177 11:34:35.208129 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-event
178 11:34:35.208237 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-feedback
179 11:34:35.208345 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-raise
180 11:34:35.208451 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-reference
181 11:34:35.208559 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-runner
182 11:34:35.208667 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-set
183 11:34:35.208774 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-test-shell
184 11:34:35.208885 Updating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-add-keys (debian)
185 11:34:35.209017 Updating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-add-sources (debian)
186 11:34:35.209171 Updating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-install-packages (debian)
187 11:34:35.209324 Updating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-installed-packages (debian)
188 11:34:35.209457 Updating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/bin/lava-os-build (debian)
189 11:34:35.209563 Creating /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/environment
190 11:34:35.209646 LAVA metadata
191 11:34:35.209708 - LAVA_JOB_ID=14864608
192 11:34:35.209762 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:34:35.209849 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 11:34:35.209904 skipped lava-vland-overlay
195 11:34:35.209969 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:34:35.210038 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 11:34:35.210089 skipped lava-multinode-overlay
198 11:34:35.210150 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:34:35.210216 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 11:34:35.210289 Loading test definitions
201 11:34:35.210363 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 11:34:35.210419 Using /lava-14864608 at stage 0
203 11:34:35.210684 uuid=14864608_1.6.2.3.1 testdef=None
204 11:34:35.210762 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:34:35.210833 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 11:34:35.211214 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:34:35.211404 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 11:34:35.211900 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:34:35.212102 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 11:34:35.212611 runner path: /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/0/tests/0_timesync-off test_uuid 14864608_1.6.2.3.1
213 11:34:35.212750 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:34:35.212947 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 11:34:35.213009 Using /lava-14864608 at stage 0
217 11:34:35.213092 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:34:35.213193 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/0/tests/1_kselftest-alsa'
219 11:34:39.547387 Running '/usr/bin/git checkout kernelci.org
220 11:34:39.696427 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:34:39.696793 uuid=14864608_1.6.2.3.5 testdef=None
222 11:34:39.696892 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 11:34:39.697081 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 11:34:39.697756 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:34:39.697954 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 11:34:39.698815 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:34:39.699024 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 11:34:39.699863 runner path: /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/0/tests/1_kselftest-alsa test_uuid 14864608_1.6.2.3.5
232 11:34:39.699941 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 11:34:39.699997 BRANCH='cip-gitlab'
234 11:34:39.700049 SKIPFILE='/dev/null'
235 11:34:39.700099 SKIP_INSTALL='True'
236 11:34:39.700148 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:34:39.700199 TST_CASENAME=''
238 11:34:39.700248 TST_CMDFILES='alsa'
239 11:34:39.700376 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:34:39.700554 Creating lava-test-runner.conf files
242 11:34:39.700608 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864608/lava-overlay-trb2wpzt/lava-14864608/0 for stage 0
243 11:34:39.700686 - 0_timesync-off
244 11:34:39.700744 - 1_kselftest-alsa
245 11:34:39.700827 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 11:34:39.700901 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 11:34:46.817158 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:34:46.817328 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 11:34:46.817415 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:34:46.817495 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 11:34:46.817572 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 11:34:46.958465 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:34:46.958614 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 11:34:46.958688 extracting modules file /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s
255 11:34:47.179228 extracting modules file /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864608/extract-overlay-ramdisk-v9qfkkxl/ramdisk
256 11:34:47.405986 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:34:47.406126 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 11:34:47.406205 [common] Applying overlay to NFS
259 11:34:47.406262 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864608/compress-overlay-ki24amex/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s
260 11:34:48.221471 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:34:48.221607 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 11:34:48.221693 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:34:48.221770 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 11:34:48.221836 Building ramdisk /var/lib/lava/dispatcher/tmp/14864608/extract-overlay-ramdisk-v9qfkkxl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864608/extract-overlay-ramdisk-v9qfkkxl/ramdisk
265 11:34:48.490759 >> 129966 blocks
266 11:34:50.572660 rename /var/lib/lava/dispatcher/tmp/14864608/extract-overlay-ramdisk-v9qfkkxl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/ramdisk/ramdisk.cpio.gz
267 11:34:50.572861 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:34:50.572951 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:34:50.573054 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:34:50.573194 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/kernel/Image']
271 11:35:03.767894 Returned 0 in 13 seconds
272 11:35:03.768060 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/kernel/image.itb
273 11:35:04.119187 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:35:04.119327 output: Created: Wed Jul 17 12:35:04 2024
275 11:35:04.119391 output: Image 0 (kernel-1)
276 11:35:04.119480 output: Description:
277 11:35:04.119568 output: Created: Wed Jul 17 12:35:04 2024
278 11:35:04.119625 output: Type: Kernel Image
279 11:35:04.119678 output: Compression: lzma compressed
280 11:35:04.119731 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
281 11:35:04.119781 output: Architecture: AArch64
282 11:35:04.119831 output: OS: Linux
283 11:35:04.119878 output: Load Address: 0x00000000
284 11:35:04.119927 output: Entry Point: 0x00000000
285 11:35:04.119974 output: Hash algo: crc32
286 11:35:04.120022 output: Hash value: 83448d17
287 11:35:04.120069 output: Image 1 (fdt-1)
288 11:35:04.120117 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 11:35:04.120165 output: Created: Wed Jul 17 12:35:04 2024
290 11:35:04.120212 output: Type: Flat Device Tree
291 11:35:04.120259 output: Compression: uncompressed
292 11:35:04.120306 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 11:35:04.120354 output: Architecture: AArch64
294 11:35:04.120401 output: Hash algo: crc32
295 11:35:04.120448 output: Hash value: a9713552
296 11:35:04.120494 output: Image 2 (ramdisk-1)
297 11:35:04.120540 output: Description: unavailable
298 11:35:04.120588 output: Created: Wed Jul 17 12:35:04 2024
299 11:35:04.120635 output: Type: RAMDisk Image
300 11:35:04.120682 output: Compression: uncompressed
301 11:35:04.120728 output: Data Size: 18725597 Bytes = 18286.72 KiB = 17.86 MiB
302 11:35:04.120775 output: Architecture: AArch64
303 11:35:04.120821 output: OS: Linux
304 11:35:04.120868 output: Load Address: unavailable
305 11:35:04.120914 output: Entry Point: unavailable
306 11:35:04.120960 output: Hash algo: crc32
307 11:35:04.121007 output: Hash value: cb1a9a30
308 11:35:04.121054 output: Default Configuration: 'conf-1'
309 11:35:04.121101 output: Configuration 0 (conf-1)
310 11:35:04.121181 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 11:35:04.121242 output: Kernel: kernel-1
312 11:35:04.121289 output: Init Ramdisk: ramdisk-1
313 11:35:04.121335 output: FDT: fdt-1
314 11:35:04.121381 output: Loadables: kernel-1
315 11:35:04.121427 output:
316 11:35:04.121524 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:35:04.121595 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:35:04.121666 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:35:04.121738 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 11:35:04.121793 No LXC device requested
321 11:35:04.121857 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:35:04.121924 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 11:35:04.121989 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:35:04.122042 Checking files for TFTP limit of 4294967296 bytes.
325 11:35:04.122397 end: 1 tftp-deploy (duration 00:00:39) [common]
326 11:35:04.122483 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:35:04.122559 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:35:04.122646 substitutions:
329 11:35:04.122703 - {DTB}: 14864608/tftp-deploy-bhuaup7q/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 11:35:04.122756 - {INITRD}: 14864608/tftp-deploy-bhuaup7q/ramdisk/ramdisk.cpio.gz
331 11:35:04.122808 - {KERNEL}: 14864608/tftp-deploy-bhuaup7q/kernel/Image
332 11:35:04.122857 - {LAVA_MAC}: None
333 11:35:04.122906 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s
334 11:35:04.122954 - {NFS_SERVER_IP}: 192.168.201.1
335 11:35:04.123001 - {PRESEED_CONFIG}: None
336 11:35:04.123051 - {PRESEED_LOCAL}: None
337 11:35:04.123099 - {RAMDISK}: 14864608/tftp-deploy-bhuaup7q/ramdisk/ramdisk.cpio.gz
338 11:35:04.123147 - {ROOT_PART}: None
339 11:35:04.123193 - {ROOT}: None
340 11:35:04.123240 - {SERVER_IP}: 192.168.201.1
341 11:35:04.123286 - {TEE}: None
342 11:35:04.123332 Parsed boot commands:
343 11:35:04.123378 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:35:04.123510 Parsed boot commands: tftpboot 192.168.201.1 14864608/tftp-deploy-bhuaup7q/kernel/image.itb 14864608/tftp-deploy-bhuaup7q/kernel/cmdline
345 11:35:04.123586 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:35:04.123657 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:35:04.123728 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:35:04.123796 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:35:04.123850 Not connected, no need to disconnect.
350 11:35:04.123914 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:35:04.123980 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:35:04.124033 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-1'
353 11:35:04.127131 Setting prompt string to ['lava-test: # ']
354 11:35:04.127427 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:35:04.127521 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:35:04.127607 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:35:04.127686 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:35:04.127899 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1', '--port=1', '--command=reboot']
359 11:35:13.243025 >> Command sent successfully.
360 11:35:13.246551 Returned 0 in 9 seconds
361 11:35:13.246728 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:35:13.246928 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:35:13.247017 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:35:13.247088 Setting prompt string to 'Starting depthcharge on Juniper...'
366 11:35:13.247157 Changing prompt to 'Starting depthcharge on Juniper...'
367 11:35:13.247214 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
368 11:35:13.247536 [Enter `^Ec?' for help]
369 11:35:19.003990 [DL] 00000000 00000000 010701
370 11:35:19.009065
371 11:35:19.009214
372 11:35:19.009274 F0: 102B 0000
373 11:35:19.009335
374 11:35:19.009387 F3: 1006 0033 [0200]
375 11:35:19.012216
376 11:35:19.012295 F3: 4001 00E0 [0200]
377 11:35:19.012353
378 11:35:19.012409 F3: 0000 0000
379 11:35:19.015459
380 11:35:19.015538 V0: 0000 0000 [0001]
381 11:35:19.015597
382 11:35:19.015650 00: 1027 0002
383 11:35:19.015703
384 11:35:19.018936 01: 0000 0000
385 11:35:19.019015
386 11:35:19.019074 BP: 0C00 0251 [0000]
387 11:35:19.019128
388 11:35:19.022150 G0: 1182 0000
389 11:35:19.022228
390 11:35:19.022291 EC: 0004 0000 [0001]
391 11:35:19.022345
392 11:35:19.025487 S7: 0000 0000 [0000]
393 11:35:19.025588
394 11:35:19.028729 CC: 0000 0000 [0001]
395 11:35:19.028820
396 11:35:19.028904 T0: 0000 00DB [000F]
397 11:35:19.028984
398 11:35:19.029064 Jump to BL
399 11:35:19.029185
400 11:35:19.065049
401 11:35:19.065242
402 11:35:19.071269 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 11:35:19.074875 ARM64: Exception handlers installed.
404 11:35:19.077900 ARM64: Testing exception
405 11:35:19.081965 ARM64: Done test exception
406 11:35:19.085904 WDT: Last reset was cold boot
407 11:35:19.086012 SPI0(PAD0) initialized at 992727 Hz
408 11:35:19.092576 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 11:35:19.092693 Manufacturer: ef
410 11:35:19.099106 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 11:35:19.111938 Probing TPM: . done!
412 11:35:19.112059 TPM ready after 0 ms
413 11:35:19.118573 Connected to device vid:did:rid of 1ae0:0028:00
414 11:35:19.124961 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
415 11:35:19.128808 Initialized TPM device CR50 revision 0
416 11:35:19.174480 tlcl_send_startup: Startup return code is 0
417 11:35:19.174637 TPM: setup succeeded
418 11:35:19.182488 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 11:35:19.186393 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 11:35:19.189666 in-header: 03 19 00 00 08 00 00 00
421 11:35:19.193392 in-data: a2 e0 47 00 13 00 00 00
422 11:35:19.195826 Chrome EC: UHEPI supported
423 11:35:19.202764 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 11:35:19.206112 in-header: 03 a1 00 00 08 00 00 00
425 11:35:19.209687 in-data: 84 60 60 10 00 00 00 00
426 11:35:19.209777 Phase 1
427 11:35:19.212908 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 11:35:19.219686 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 11:35:19.226468 VB2:vb2_check_recovery() Recovery was requested manually
430 11:35:19.229897 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 11:35:19.235540 Recovery requested (1009000e)
432 11:35:19.244129 tlcl_extend: response is 0
433 11:35:19.250113 tlcl_extend: response is 0
434 11:35:19.275184
435 11:35:19.275312
436 11:35:19.281237 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 11:35:19.284886 ARM64: Exception handlers installed.
438 11:35:19.287852 ARM64: Testing exception
439 11:35:19.291501 ARM64: Done test exception
440 11:35:19.306896 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x826a, sec=0x2000
441 11:35:19.313347 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 11:35:19.316999 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 11:35:19.324983 [RTC]rtc_get_frequency_meter,134: input=0xf, output=875
444 11:35:19.332998 [RTC]rtc_get_frequency_meter,134: input=0x7, output=742
445 11:35:19.338608 [RTC]rtc_get_frequency_meter,134: input=0xb, output=810
446 11:35:19.345684 [RTC]rtc_get_frequency_meter,134: input=0x9, output=776
447 11:35:19.352493 [RTC]rtc_get_frequency_meter,134: input=0xa, output=792
448 11:35:19.356000 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x826a
449 11:35:19.362968 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
450 11:35:19.366591 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
451 11:35:19.369469 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
452 11:35:19.375934 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
453 11:35:19.379192 in-header: 03 19 00 00 08 00 00 00
454 11:35:19.379278 in-data: a2 e0 47 00 13 00 00 00
455 11:35:19.382758 Chrome EC: UHEPI supported
456 11:35:19.389398 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
457 11:35:19.392741 in-header: 03 a1 00 00 08 00 00 00
458 11:35:19.396360 in-data: 84 60 60 10 00 00 00 00
459 11:35:19.399270 Skip loading cached calibration data
460 11:35:19.405963 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
461 11:35:19.409290 in-header: 03 a1 00 00 08 00 00 00
462 11:35:19.413091 in-data: 84 60 60 10 00 00 00 00
463 11:35:19.419550 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
464 11:35:19.423223 in-header: 03 a1 00 00 08 00 00 00
465 11:35:19.426118 in-data: 84 60 60 10 00 00 00 00
466 11:35:19.429492 ADC[3]: Raw value=216781 ID=1
467 11:35:19.429573 Manufacturer: ef
468 11:35:19.436166 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
469 11:35:19.439329 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
470 11:35:19.442577 CBFS @ 21000 size 3d4000
471 11:35:19.445765 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
472 11:35:19.452956 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
473 11:35:19.455750 CBFS: Found @ offset 3c700 size 44
474 11:35:19.455836 DRAM-K: Full Calibration
475 11:35:19.462377 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
476 11:35:19.462464 CBFS @ 21000 size 3d4000
477 11:35:19.469749 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
478 11:35:19.472594 CBFS: Locating 'fallback/dram'
479 11:35:19.475857 CBFS: Found @ offset 24b00 size 12268
480 11:35:19.504174 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
481 11:35:19.507014 ddr_geometry: 1, config: 0x0
482 11:35:19.510613 header.status = 0x0
483 11:35:19.513686 header.magic = 0x44524d4b (expected: 0x44524d4b)
484 11:35:19.518164 header.version = 0x5 (expected: 0x5)
485 11:35:19.520446 header.size = 0x8f0 (expected: 0x8f0)
486 11:35:19.520528 header.config = 0x0
487 11:35:19.523581 header.flags = 0x0
488 11:35:19.523659 header.checksum = 0x0
489 11:35:19.530364 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
490 11:35:19.536889 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
491 11:35:19.540297 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
492 11:35:19.543779 ddr_geometry:1
493 11:35:19.547017 [EMI] new MDL number = 1
494 11:35:19.547100 dram_cbt_mode_extern: 0
495 11:35:19.550720 dram_cbt_mode [RK0]: 0, [RK1]: 0
496 11:35:19.557611 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
497 11:35:19.557710
498 11:35:19.557770
499 11:35:19.560517 [Bianco] ETT version 0.0.0.1
500 11:35:19.564175 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
501 11:35:19.564256
502 11:35:19.567268 vSetVcoreByFreq with vcore:762500, freq=1600
503 11:35:19.567345
504 11:35:19.571410 [DramcInit]
505 11:35:19.571489 AutoRefreshCKEOff AutoREF OFF
506 11:35:19.573813 DDRPhyPLLSetting-CKEOFF
507 11:35:19.577354 DDRPhyPLLSetting-CKEON
508 11:35:19.577431
509 11:35:19.577495 Enable WDQS
510 11:35:19.581111 [ModeRegInit_LP4] CH0 RK0
511 11:35:19.584522 Write Rank0 MR13 =0x18
512 11:35:19.584603 Write Rank0 MR12 =0x5d
513 11:35:19.587646 Write Rank0 MR1 =0x56
514 11:35:19.591318 Write Rank0 MR2 =0x1a
515 11:35:19.591402 Write Rank0 MR11 =0x0
516 11:35:19.594487 Write Rank0 MR22 =0x38
517 11:35:19.594567 Write Rank0 MR14 =0x5d
518 11:35:19.597872 Write Rank0 MR3 =0x30
519 11:35:19.601311 Write Rank0 MR13 =0x58
520 11:35:19.601390 Write Rank0 MR12 =0x5d
521 11:35:19.604430 Write Rank0 MR1 =0x56
522 11:35:19.604506 Write Rank0 MR2 =0x2d
523 11:35:19.608320 Write Rank0 MR11 =0x23
524 11:35:19.611271 Write Rank0 MR22 =0x34
525 11:35:19.611351 Write Rank0 MR14 =0x10
526 11:35:19.614140 Write Rank0 MR3 =0x30
527 11:35:19.617734 Write Rank0 MR13 =0xd8
528 11:35:19.617814 [ModeRegInit_LP4] CH0 RK1
529 11:35:19.621086 Write Rank1 MR13 =0x18
530 11:35:19.621186 Write Rank1 MR12 =0x5d
531 11:35:19.624513 Write Rank1 MR1 =0x56
532 11:35:19.628047 Write Rank1 MR2 =0x1a
533 11:35:19.628128 Write Rank1 MR11 =0x0
534 11:35:19.631504 Write Rank1 MR22 =0x38
535 11:35:19.631581 Write Rank1 MR14 =0x5d
536 11:35:19.634877 Write Rank1 MR3 =0x30
537 11:35:19.637799 Write Rank1 MR13 =0x58
538 11:35:19.637876 Write Rank1 MR12 =0x5d
539 11:35:19.641258 Write Rank1 MR1 =0x56
540 11:35:19.644657 Write Rank1 MR2 =0x2d
541 11:35:19.644740 Write Rank1 MR11 =0x23
542 11:35:19.647910 Write Rank1 MR22 =0x34
543 11:35:19.647988 Write Rank1 MR14 =0x10
544 11:35:19.651186 Write Rank1 MR3 =0x30
545 11:35:19.654609 Write Rank1 MR13 =0xd8
546 11:35:19.654690 [ModeRegInit_LP4] CH1 RK0
547 11:35:19.657546 Write Rank0 MR13 =0x18
548 11:35:19.661153 Write Rank0 MR12 =0x5d
549 11:35:19.661233 Write Rank0 MR1 =0x56
550 11:35:19.664627 Write Rank0 MR2 =0x1a
551 11:35:19.664706 Write Rank0 MR11 =0x0
552 11:35:19.668045 Write Rank0 MR22 =0x38
553 11:35:19.671127 Write Rank0 MR14 =0x5d
554 11:35:19.671205 Write Rank0 MR3 =0x30
555 11:35:19.674522 Write Rank0 MR13 =0x58
556 11:35:19.674600 Write Rank0 MR12 =0x5d
557 11:35:19.678137 Write Rank0 MR1 =0x56
558 11:35:19.680980 Write Rank0 MR2 =0x2d
559 11:35:19.681058 Write Rank0 MR11 =0x23
560 11:35:19.684844 Write Rank0 MR22 =0x34
561 11:35:19.684922 Write Rank0 MR14 =0x10
562 11:35:19.688379 Write Rank0 MR3 =0x30
563 11:35:19.691428 Write Rank0 MR13 =0xd8
564 11:35:19.691521 [ModeRegInit_LP4] CH1 RK1
565 11:35:19.695006 Write Rank1 MR13 =0x18
566 11:35:19.697953 Write Rank1 MR12 =0x5d
567 11:35:19.698031 Write Rank1 MR1 =0x56
568 11:35:19.700942 Write Rank1 MR2 =0x1a
569 11:35:19.701019 Write Rank1 MR11 =0x0
570 11:35:19.704360 Write Rank1 MR22 =0x38
571 11:35:19.707976 Write Rank1 MR14 =0x5d
572 11:35:19.708058 Write Rank1 MR3 =0x30
573 11:35:19.711708 Write Rank1 MR13 =0x58
574 11:35:19.711787 Write Rank1 MR12 =0x5d
575 11:35:19.714907 Write Rank1 MR1 =0x56
576 11:35:19.717711 Write Rank1 MR2 =0x2d
577 11:35:19.717789 Write Rank1 MR11 =0x23
578 11:35:19.721083 Write Rank1 MR22 =0x34
579 11:35:19.721169 Write Rank1 MR14 =0x10
580 11:35:19.724714 Write Rank1 MR3 =0x30
581 11:35:19.728105 Write Rank1 MR13 =0xd8
582 11:35:19.728184 match AC timing 3
583 11:35:19.737986 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
584 11:35:19.741304 [MiockJmeterHQA]
585 11:35:19.744446 vSetVcoreByFreq with vcore:762500, freq=1600
586 11:35:19.835236
587 11:35:19.835365 MIOCK jitter meter ch=0
588 11:35:19.835427
589 11:35:19.838673 1T = (88-13) = 75 dly cells
590 11:35:19.845328 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 833/100 ps
591 11:35:19.849111 vSetVcoreByFreq with vcore:725000, freq=1200
592 11:35:19.934334
593 11:35:19.934472 MIOCK jitter meter ch=0
594 11:35:19.934534
595 11:35:19.937779 1T = (83-13) = 70 dly cells
596 11:35:19.944355 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 892/100 ps
597 11:35:19.947678 vSetVcoreByFreq with vcore:725000, freq=800
598 11:35:20.034035
599 11:35:20.034162 MIOCK jitter meter ch=0
600 11:35:20.034224
601 11:35:20.036986 1T = (83-13) = 70 dly cells
602 11:35:20.043355 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 892/100 ps
603 11:35:20.047403 vSetVcoreByFreq with vcore:762500, freq=1600
604 11:35:20.050348 vSetVcoreByFreq with vcore:762500, freq=1600
605 11:35:20.050429
606 11:35:20.050505 K DRVP
607 11:35:20.054052 1. OCD DRVP=0 CALOUT=0
608 11:35:20.056726 1. OCD DRVP=1 CALOUT=0
609 11:35:20.056804 1. OCD DRVP=2 CALOUT=0
610 11:35:20.060668 1. OCD DRVP=3 CALOUT=0
611 11:35:20.060750 1. OCD DRVP=4 CALOUT=0
612 11:35:20.063876 1. OCD DRVP=5 CALOUT=0
613 11:35:20.067166 1. OCD DRVP=6 CALOUT=0
614 11:35:20.067245 1. OCD DRVP=7 CALOUT=0
615 11:35:20.070496 1. OCD DRVP=8 CALOUT=0
616 11:35:20.070574 1. OCD DRVP=9 CALOUT=1
617 11:35:20.073454
618 11:35:20.073554 1. OCD DRVP calibration OK! DRVP=9
619 11:35:20.076917
620 11:35:20.076995
621 11:35:20.077053
622 11:35:20.077108 K ODTN
623 11:35:20.077246 3. OCD ODTN=0 ,CALOUT=1
624 11:35:20.080459 3. OCD ODTN=1 ,CALOUT=1
625 11:35:20.083566 3. OCD ODTN=2 ,CALOUT=1
626 11:35:20.083647 3. OCD ODTN=3 ,CALOUT=1
627 11:35:20.087256 3. OCD ODTN=4 ,CALOUT=1
628 11:35:20.090526 3. OCD ODTN=5 ,CALOUT=1
629 11:35:20.090606 3. OCD ODTN=6 ,CALOUT=1
630 11:35:20.093650 3. OCD ODTN=7 ,CALOUT=1
631 11:35:20.097560 3. OCD ODTN=8 ,CALOUT=0
632 11:35:20.097669
633 11:35:20.100637 3. OCD ODTN calibration OK! ODTN=8
634 11:35:20.100738
635 11:35:20.104208 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=8
636 11:35:20.107984 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15
637 11:35:20.110832 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15 (After Adjust)
638 11:35:20.110934
639 11:35:20.114224 K DRVP
640 11:35:20.114324 1. OCD DRVP=0 CALOUT=0
641 11:35:20.117089 1. OCD DRVP=1 CALOUT=0
642 11:35:20.120744 1. OCD DRVP=2 CALOUT=0
643 11:35:20.120846 1. OCD DRVP=3 CALOUT=0
644 11:35:20.124181 1. OCD DRVP=4 CALOUT=0
645 11:35:20.124300 1. OCD DRVP=5 CALOUT=0
646 11:35:20.127213 1. OCD DRVP=6 CALOUT=0
647 11:35:20.130491 1. OCD DRVP=7 CALOUT=0
648 11:35:20.130576 1. OCD DRVP=8 CALOUT=0
649 11:35:20.133933 1. OCD DRVP=9 CALOUT=0
650 11:35:20.134017 1. OCD DRVP=10 CALOUT=1
651 11:35:20.137400
652 11:35:20.137478 1. OCD DRVP calibration OK! DRVP=10
653 11:35:20.140862
654 11:35:20.140941
655 11:35:20.140999
656 11:35:20.141053 K ODTN
657 11:35:20.141104 3. OCD ODTN=0 ,CALOUT=1
658 11:35:20.144235 3. OCD ODTN=1 ,CALOUT=1
659 11:35:20.147433 3. OCD ODTN=2 ,CALOUT=1
660 11:35:20.147513 3. OCD ODTN=3 ,CALOUT=1
661 11:35:20.150720 3. OCD ODTN=4 ,CALOUT=1
662 11:35:20.154165 3. OCD ODTN=5 ,CALOUT=1
663 11:35:20.154246 3. OCD ODTN=6 ,CALOUT=1
664 11:35:20.157514 3. OCD ODTN=7 ,CALOUT=1
665 11:35:20.161164 3. OCD ODTN=8 ,CALOUT=1
666 11:35:20.161246 3. OCD ODTN=9 ,CALOUT=1
667 11:35:20.164135 3. OCD ODTN=10 ,CALOUT=1
668 11:35:20.168184 3. OCD ODTN=11 ,CALOUT=1
669 11:35:20.168269 3. OCD ODTN=12 ,CALOUT=1
670 11:35:20.171072 3. OCD ODTN=13 ,CALOUT=1
671 11:35:20.174302 3. OCD ODTN=14 ,CALOUT=1
672 11:35:20.174382 3. OCD ODTN=15 ,CALOUT=0
673 11:35:20.174442
674 11:35:20.177757 3. OCD ODTN calibration OK! ODTN=15
675 11:35:20.177837
676 11:35:20.181250 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
677 11:35:20.187651 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
678 11:35:20.191074 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
679 11:35:20.191160
680 11:35:20.194330 [DramcInit]
681 11:35:20.194408 AutoRefreshCKEOff AutoREF OFF
682 11:35:20.197703 DDRPhyPLLSetting-CKEOFF
683 11:35:20.201055 DDRPhyPLLSetting-CKEON
684 11:35:20.201143
685 11:35:20.201203 Enable WDQS
686 11:35:20.201257 ==
687 11:35:20.207879 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
688 11:35:20.211135 fsp= 1, odt_onoff= 1, Byte mode= 0
689 11:35:20.211245 ==
690 11:35:20.211334 [Duty_Offset_Calibration]
691 11:35:20.211417
692 11:35:20.214356 ===========================
693 11:35:20.217548 B0:0 B1:0 CA:2
694 11:35:20.238227 ==
695 11:35:20.241107 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
696 11:35:20.244980 fsp= 1, odt_onoff= 1, Byte mode= 0
697 11:35:20.245066 ==
698 11:35:20.248488 [Duty_Offset_Calibration]
699 11:35:20.248570
700 11:35:20.251104 ===========================
701 11:35:20.251182 B0:0 B1:2 CA:1
702 11:35:20.284681 [ModeRegInit_LP4] CH0 RK0
703 11:35:20.287760 Write Rank0 MR13 =0x18
704 11:35:20.287843 Write Rank0 MR12 =0x5d
705 11:35:20.291165 Write Rank0 MR1 =0x56
706 11:35:20.294237 Write Rank0 MR2 =0x1a
707 11:35:20.294320 Write Rank0 MR11 =0x0
708 11:35:20.297939 Write Rank0 MR22 =0x38
709 11:35:20.298021 Write Rank0 MR14 =0x5d
710 11:35:20.301151 Write Rank0 MR3 =0x30
711 11:35:20.304423 Write Rank0 MR13 =0x58
712 11:35:20.304524 Write Rank0 MR12 =0x5d
713 11:35:20.308451 Write Rank0 MR1 =0x56
714 11:35:20.308535 Write Rank0 MR2 =0x2d
715 11:35:20.311078 Write Rank0 MR11 =0x23
716 11:35:20.314651 Write Rank0 MR22 =0x34
717 11:35:20.314735 Write Rank0 MR14 =0x10
718 11:35:20.317977 Write Rank0 MR3 =0x30
719 11:35:20.321048 Write Rank0 MR13 =0xd8
720 11:35:20.321154 [ModeRegInit_LP4] CH0 RK1
721 11:35:20.324899 Write Rank1 MR13 =0x18
722 11:35:20.327825 Write Rank1 MR12 =0x5d
723 11:35:20.327905 Write Rank1 MR1 =0x56
724 11:35:20.330939 Write Rank1 MR2 =0x1a
725 11:35:20.331018 Write Rank1 MR11 =0x0
726 11:35:20.335413 Write Rank1 MR22 =0x38
727 11:35:20.338303 Write Rank1 MR14 =0x5d
728 11:35:20.338382 Write Rank1 MR3 =0x30
729 11:35:20.341684 Write Rank1 MR13 =0x58
730 11:35:20.341764 Write Rank1 MR12 =0x5d
731 11:35:20.345003 Write Rank1 MR1 =0x56
732 11:35:20.347904 Write Rank1 MR2 =0x2d
733 11:35:20.347983 Write Rank1 MR11 =0x23
734 11:35:20.351209 Write Rank1 MR22 =0x34
735 11:35:20.351288 Write Rank1 MR14 =0x10
736 11:35:20.354397 Write Rank1 MR3 =0x30
737 11:35:20.357551 Write Rank1 MR13 =0xd8
738 11:35:20.357652 [ModeRegInit_LP4] CH1 RK0
739 11:35:20.361267 Write Rank0 MR13 =0x18
740 11:35:20.364282 Write Rank0 MR12 =0x5d
741 11:35:20.364382 Write Rank0 MR1 =0x56
742 11:35:20.367798 Write Rank0 MR2 =0x1a
743 11:35:20.367899 Write Rank0 MR11 =0x0
744 11:35:20.370961 Write Rank0 MR22 =0x38
745 11:35:20.375129 Write Rank0 MR14 =0x5d
746 11:35:20.375236 Write Rank0 MR3 =0x30
747 11:35:20.378078 Write Rank0 MR13 =0x58
748 11:35:20.378180 Write Rank0 MR12 =0x5d
749 11:35:20.381234 Write Rank0 MR1 =0x56
750 11:35:20.384639 Write Rank0 MR2 =0x2d
751 11:35:20.384743 Write Rank0 MR11 =0x23
752 11:35:20.388475 Write Rank0 MR22 =0x34
753 11:35:20.388574 Write Rank0 MR14 =0x10
754 11:35:20.390903 Write Rank0 MR3 =0x30
755 11:35:20.394704 Write Rank0 MR13 =0xd8
756 11:35:20.394807 [ModeRegInit_LP4] CH1 RK1
757 11:35:20.397778 Write Rank1 MR13 =0x18
758 11:35:20.401427 Write Rank1 MR12 =0x5d
759 11:35:20.401530 Write Rank1 MR1 =0x56
760 11:35:20.404647 Write Rank1 MR2 =0x1a
761 11:35:20.404746 Write Rank1 MR11 =0x0
762 11:35:20.407605 Write Rank1 MR22 =0x38
763 11:35:20.411331 Write Rank1 MR14 =0x5d
764 11:35:20.411443 Write Rank1 MR3 =0x30
765 11:35:20.414676 Write Rank1 MR13 =0x58
766 11:35:20.414776 Write Rank1 MR12 =0x5d
767 11:35:20.417700 Write Rank1 MR1 =0x56
768 11:35:20.421011 Write Rank1 MR2 =0x2d
769 11:35:20.421123 Write Rank1 MR11 =0x23
770 11:35:20.424441 Write Rank1 MR22 =0x34
771 11:35:20.427851 Write Rank1 MR14 =0x10
772 11:35:20.427956 Write Rank1 MR3 =0x30
773 11:35:20.431512 Write Rank1 MR13 =0xd8
774 11:35:20.431611 match AC timing 3
775 11:35:20.441112 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
776 11:35:20.444812 DramC Write-DBI off
777 11:35:20.444928 DramC Read-DBI off
778 11:35:20.447524 Write Rank0 MR13 =0x59
779 11:35:20.447624 ==
780 11:35:20.451319 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
781 11:35:20.454587 fsp= 1, odt_onoff= 1, Byte mode= 0
782 11:35:20.454690 ==
783 11:35:20.457857 === u2Vref_new: 0x56 --> 0x2d
784 11:35:20.461509 === u2Vref_new: 0x58 --> 0x38
785 11:35:20.465123 === u2Vref_new: 0x5a --> 0x39
786 11:35:20.467887 === u2Vref_new: 0x5c --> 0x3c
787 11:35:20.471069 === u2Vref_new: 0x5e --> 0x3d
788 11:35:20.474478 === u2Vref_new: 0x60 --> 0xa0
789 11:35:20.477667 [CA 0] Center 34 (6~63) winsize 58
790 11:35:20.480933 [CA 1] Center 36 (9~63) winsize 55
791 11:35:20.484377 [CA 2] Center 30 (2~59) winsize 58
792 11:35:20.487886 [CA 3] Center 26 (-2~54) winsize 57
793 11:35:20.491080 [CA 4] Center 26 (-2~54) winsize 57
794 11:35:20.494459 [CA 5] Center 31 (2~61) winsize 60
795 11:35:20.494561
796 11:35:20.498508 [CATrainingPosCal] consider 1 rank data
797 11:35:20.500969 u2DelayCellTimex100 = 833/100 ps
798 11:35:20.504815 CA0 delay=34 (6~63),Diff = 8 PI (9 cell)
799 11:35:20.507809 CA1 delay=36 (9~63),Diff = 10 PI (11 cell)
800 11:35:20.510993 CA2 delay=30 (2~59),Diff = 4 PI (4 cell)
801 11:35:20.514679 CA3 delay=26 (-2~54),Diff = 0 PI (0 cell)
802 11:35:20.517954 CA4 delay=26 (-2~54),Diff = 0 PI (0 cell)
803 11:35:20.521180 CA5 delay=31 (2~61),Diff = 5 PI (5 cell)
804 11:35:20.521258
805 11:35:20.524874 CA PerBit enable=1, Macro0, CA PI delay=26
806 11:35:20.528053 === u2Vref_new: 0x60 --> 0xa0
807 11:35:20.528130
808 11:35:20.531211 Vref(ca) range 1: 32
809 11:35:20.531287
810 11:35:20.531345 CS Dly= 10 (41-0-32)
811 11:35:20.535917 Write Rank0 MR13 =0xd8
812 11:35:20.538212 Write Rank0 MR13 =0xd8
813 11:35:20.538288 Write Rank0 MR12 =0x60
814 11:35:20.541276 Write Rank1 MR13 =0x59
815 11:35:20.541352 ==
816 11:35:20.544746 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
817 11:35:20.547815 fsp= 1, odt_onoff= 1, Byte mode= 0
818 11:35:20.551179 ==
819 11:35:20.551265 === u2Vref_new: 0x56 --> 0x2d
820 11:35:20.554419 === u2Vref_new: 0x58 --> 0x38
821 11:35:20.558010 === u2Vref_new: 0x5a --> 0x39
822 11:35:20.561512 === u2Vref_new: 0x5c --> 0x3c
823 11:35:20.564743 === u2Vref_new: 0x5e --> 0x3d
824 11:35:20.567963 === u2Vref_new: 0x60 --> 0xa0
825 11:35:20.571150 [CA 0] Center 36 (10~63) winsize 54
826 11:35:20.574727 [CA 1] Center 36 (10~63) winsize 54
827 11:35:20.577524 [CA 2] Center 31 (2~60) winsize 59
828 11:35:20.581528 [CA 3] Center 26 (-2~54) winsize 57
829 11:35:20.584204 [CA 4] Center 25 (-3~53) winsize 57
830 11:35:20.587581 [CA 5] Center 30 (1~60) winsize 60
831 11:35:20.587678
832 11:35:20.591181 [CATrainingPosCal] consider 2 rank data
833 11:35:20.594227 u2DelayCellTimex100 = 833/100 ps
834 11:35:20.597883 CA0 delay=36 (10~63),Diff = 11 PI (12 cell)
835 11:35:20.600853 CA1 delay=36 (10~63),Diff = 11 PI (12 cell)
836 11:35:20.604321 CA2 delay=30 (2~59),Diff = 5 PI (5 cell)
837 11:35:20.607911 CA3 delay=26 (-2~54),Diff = 1 PI (1 cell)
838 11:35:20.610909 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
839 11:35:20.617878 CA5 delay=31 (2~60),Diff = 6 PI (7 cell)
840 11:35:20.617978
841 11:35:20.621032 CA PerBit enable=1, Macro0, CA PI delay=25
842 11:35:20.625097 === u2Vref_new: 0x5c --> 0x3c
843 11:35:20.625229
844 11:35:20.625316 Vref(ca) range 1: 28
845 11:35:20.625399
846 11:35:20.627631 CS Dly= 6 (37-0-32)
847 11:35:20.627726 Write Rank1 MR13 =0xd8
848 11:35:20.631061 Write Rank1 MR13 =0xd8
849 11:35:20.634311 Write Rank1 MR12 =0x5c
850 11:35:20.637789 [RankSwap] Rank num 2, (Multi 1), Rank 0
851 11:35:20.637888 Write Rank0 MR2 =0xad
852 11:35:20.640721 [Write Leveling]
853 11:35:20.644374 delay byte0 byte1 byte2 byte3
854 11:35:20.644472
855 11:35:20.644559 10 0 0
856 11:35:20.647393 11 0 0
857 11:35:20.647496 12 0 0
858 11:35:20.647584 13 0 0
859 11:35:20.651713 14 0 0
860 11:35:20.651814 15 0 0
861 11:35:20.654851 16 0 0
862 11:35:20.654951 17 0 0
863 11:35:20.655037 18 0 0
864 11:35:20.658472 19 0 0
865 11:35:20.658570 20 0 0
866 11:35:20.661224 21 0 0
867 11:35:20.661322 22 0 0
868 11:35:20.664480 23 0 0
869 11:35:20.664578 24 0 0
870 11:35:20.664665 25 0 ff
871 11:35:20.667730 26 0 ff
872 11:35:20.667829 27 0 ff
873 11:35:20.670830 28 0 ff
874 11:35:20.670928 29 0 ff
875 11:35:20.674157 30 0 ff
876 11:35:20.674254 31 0 ff
877 11:35:20.674340 32 0 ff
878 11:35:20.677715 33 ff ff
879 11:35:20.677813 34 ff ff
880 11:35:20.681146 35 ff ff
881 11:35:20.681245 36 ff ff
882 11:35:20.684344 37 ff ff
883 11:35:20.684442 38 ff ff
884 11:35:20.687764 39 ff ff
885 11:35:20.691217 pass bytecount = 0xff (0xff: all bytes pass)
886 11:35:20.691314
887 11:35:20.691395 DQS0 dly: 33
888 11:35:20.694284 DQS1 dly: 25
889 11:35:20.694382 Write Rank0 MR2 =0x2d
890 11:35:20.697776 [RankSwap] Rank num 2, (Multi 1), Rank 0
891 11:35:20.701070 Write Rank0 MR1 =0xd6
892 11:35:20.701173 [Gating]
893 11:35:20.701256 ==
894 11:35:20.707638 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
895 11:35:20.711211 fsp= 1, odt_onoff= 1, Byte mode= 0
896 11:35:20.711309 ==
897 11:35:20.714600 3 1 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
898 11:35:20.717748 3 1 4 |3534 3635 |(11 11)(11 11) |(0 0)(0 0)| 0
899 11:35:20.724383 3 1 8 |3534 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
900 11:35:20.727598 3 1 12 |3534 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
901 11:35:20.731197 3 1 16 |3534 e0e |(11 11)(11 11) |(1 1)(1 1)| 0
902 11:35:20.737770 3 1 20 |3534 1414 |(11 11)(11 11) |(0 0)(1 1)| 0
903 11:35:20.741256 3 1 24 |3534 2626 |(11 11)(11 11) |(0 0)(0 0)| 0
904 11:35:20.744594 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
905 11:35:20.751264 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
906 11:35:20.754356 3 2 4 |3534 3131 |(11 11)(11 11) |(0 0)(0 0)| 0
907 11:35:20.757634 3 2 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
908 11:35:20.761512 3 2 12 |201 3635 |(11 11)(11 11) |(0 1)(0 1)| 0
909 11:35:20.768365 3 2 16 |1a1a a09 |(11 11)(11 11) |(1 1)(1 1)| 0
910 11:35:20.771206 3 2 20 |3d3d 605 |(11 11)(11 11) |(1 1)(1 1)| 0
911 11:35:20.774764 3 2 24 |3d3d 1e1e |(11 11)(11 11) |(1 1)(1 1)| 0
912 11:35:20.778123 [Byte 1] Lead/lag Transition tap number (1)
913 11:35:20.784392 3 2 28 |3d3d 1414 |(11 11)(11 11) |(1 1)(0 0)| 0
914 11:35:20.787666 3 3 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
915 11:35:20.791661 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
916 11:35:20.798092 3 3 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
917 11:35:20.801421 3 3 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
918 11:35:20.804534 3 3 16 |3d3d 3b3a |(11 11)(11 11) |(1 1)(1 1)| 0
919 11:35:20.810920 3 3 20 |3534 1615 |(11 11)(11 11) |(1 1)(1 1)| 0
920 11:35:20.814562 [Byte 0] Lead/lag Transition tap number (1)
921 11:35:20.818152 [Byte 1] Lead/lag Transition tap number (1)
922 11:35:20.821011 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
923 11:35:20.827907 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
924 11:35:20.831165 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
925 11:35:20.834624 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
926 11:35:20.838147 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
927 11:35:20.844449 3 4 12 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
928 11:35:20.848038 3 4 16 |e0d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
929 11:35:20.851257 3 4 20 |3d3d 4545 |(11 11)(11 11) |(1 1)(1 1)| 0
930 11:35:20.858006 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 11:35:20.861295 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 11:35:20.864970 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 11:35:20.867859 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 11:35:20.874942 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 11:35:20.878029 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 11:35:20.881558 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
937 11:35:20.888405 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
938 11:35:20.891364 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
939 11:35:20.894837 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
940 11:35:20.901240 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
941 11:35:20.905018 [Byte 0] Lead/lag falling Transition (3, 6, 0)
942 11:35:20.907819 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
943 11:35:20.911322 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
944 11:35:20.918198 [Byte 0] Lead/lag Transition tap number (3)
945 11:35:20.921149 [Byte 1] Lead/lag falling Transition (3, 6, 8)
946 11:35:20.924770 3 6 12 |202 3e3d |(11 11)(11 11) |(0 0)(1 0)| 0
947 11:35:20.928221 [Byte 1] Lead/lag Transition tap number (2)
948 11:35:20.935001 3 6 16 |202 403 |(1 1)(11 11) |(0 0)(0 0)| 0
949 11:35:20.937769 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 11:35:20.941787 [Byte 0]First pass (3, 6, 20)
951 11:35:20.941863 [Byte 1]First pass (3, 6, 20)
952 11:35:20.947923 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 11:35:20.951525 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 11:35:20.954902 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 11:35:20.958110 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 11:35:20.961692 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
957 11:35:20.967866 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
958 11:35:20.971571 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
959 11:35:20.975102 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
960 11:35:20.977987 All bytes gating window > 1UI, Early break!
961 11:35:20.978064
962 11:35:20.981431 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
963 11:35:20.981507
964 11:35:20.984460 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12)
965 11:35:20.984535
966 11:35:20.987943
967 11:35:20.988023
968 11:35:20.991341 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
969 11:35:20.991419
970 11:35:20.994721 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
971 11:35:20.994800
972 11:35:20.994877
973 11:35:20.998250 Write Rank0 MR1 =0x56
974 11:35:20.998328
975 11:35:21.001455 best RODT dly(2T, 0.5T) = (2, 3)
976 11:35:21.001533
977 11:35:21.001610 best RODT dly(2T, 0.5T) = (2, 3)
978 11:35:21.004606 ==
979 11:35:21.007785 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
980 11:35:21.011636 fsp= 1, odt_onoff= 1, Byte mode= 0
981 11:35:21.011715 ==
982 11:35:21.014359 Start DQ dly to find pass range UseTestEngine =0
983 11:35:21.017793 x-axis: bit #, y-axis: DQ dly (-127~63)
984 11:35:21.021681 RX Vref Scan = 0
985 11:35:21.024486 -26, [0] xxxxxxxx xxxxxxxx [MSB]
986 11:35:21.028773 -25, [0] xxxxxxxx xxxxxxxx [MSB]
987 11:35:21.031229 -24, [0] xxxxxxxx xxxxxxxx [MSB]
988 11:35:21.031328 -23, [0] xxxxxxxx xxxxxxxx [MSB]
989 11:35:21.034615 -22, [0] xxxxxxxx xxxxxxxx [MSB]
990 11:35:21.038354 -21, [0] xxxxxxxx xxxxxxxx [MSB]
991 11:35:21.041443 -20, [0] xxxxxxxx xxxxxxxx [MSB]
992 11:35:21.044683 -19, [0] xxxxxxxx xxxxxxxx [MSB]
993 11:35:21.048596 -18, [0] xxxxxxxx xxxxxxxx [MSB]
994 11:35:21.051436 -17, [0] xxxxxxxx xxxxxxxx [MSB]
995 11:35:21.054611 -16, [0] xxxxxxxx xxxxxxxx [MSB]
996 11:35:21.054713 -15, [0] xxxxxxxx xxxxxxxx [MSB]
997 11:35:21.058234 -14, [0] xxxxxxxx xxxxxxxx [MSB]
998 11:35:21.061453 -13, [0] xxxxxxxx xxxxxxxx [MSB]
999 11:35:21.065532 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1000 11:35:21.067939 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1001 11:35:21.071836 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1002 11:35:21.075689 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1003 11:35:21.078615 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1004 11:35:21.078717 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1005 11:35:21.082272 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1006 11:35:21.084695 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1007 11:35:21.088299 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1008 11:35:21.091456 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1009 11:35:21.094789 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1010 11:35:21.094898 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1011 11:35:21.098419 0, [0] xxxxxxxx xxxxxxxx [MSB]
1012 11:35:21.101398 1, [0] xxxxxxxx xxxxxxxx [MSB]
1013 11:35:21.104918 2, [0] xxxxxxxx oxxxxxxx [MSB]
1014 11:35:21.108446 3, [0] xxxoxxxx oxxoxxxx [MSB]
1015 11:35:21.111926 4, [0] xxxoxoxx ooxoxxxx [MSB]
1016 11:35:21.112033 5, [0] xxxoxoxx ooxoooox [MSB]
1017 11:35:21.115074 6, [0] xxxoxoxo ooxoooox [MSB]
1018 11:35:21.118040 7, [0] xxxoxooo ooxooooo [MSB]
1019 11:35:21.121651 8, [0] ooxoxooo ooxooooo [MSB]
1020 11:35:21.124955 9, [0] oooooooo ooxooooo [MSB]
1021 11:35:21.128072 31, [0] oooooooo oooooooo [MSB]
1022 11:35:21.128173 32, [0] oooxoooo oooooooo [MSB]
1023 11:35:21.131435 33, [0] oooxoooo xooooooo [MSB]
1024 11:35:21.134938 34, [0] oooxoooo xooooooo [MSB]
1025 11:35:21.138298 35, [0] oooxoooo xooxoooo [MSB]
1026 11:35:21.141738 36, [0] oooxoxxo xxoxxooo [MSB]
1027 11:35:21.145055 37, [0] oooxoxxo xxoxxoxo [MSB]
1028 11:35:21.148073 38, [0] oxoxoxxo xxoxxxxo [MSB]
1029 11:35:21.148172 39, [0] oxoxoxxx xxoxxxxo [MSB]
1030 11:35:21.151689 40, [0] xxoxxxxx xxoxxxxo [MSB]
1031 11:35:21.154728 41, [0] xxoxxxxx xxoxxxxx [MSB]
1032 11:35:21.157988 42, [0] xxxxxxxx xxxxxxxx [MSB]
1033 11:35:21.161727 iDelay=42, Bit 0, Center 23 (8 ~ 39) 32
1034 11:35:21.164606 iDelay=42, Bit 1, Center 22 (8 ~ 37) 30
1035 11:35:21.168163 iDelay=42, Bit 2, Center 25 (9 ~ 41) 33
1036 11:35:21.171435 iDelay=42, Bit 3, Center 17 (3 ~ 31) 29
1037 11:35:21.175792 iDelay=42, Bit 4, Center 24 (9 ~ 39) 31
1038 11:35:21.178092 iDelay=42, Bit 5, Center 19 (4 ~ 35) 32
1039 11:35:21.181942 iDelay=42, Bit 6, Center 21 (7 ~ 35) 29
1040 11:35:21.184759 iDelay=42, Bit 7, Center 22 (6 ~ 38) 33
1041 11:35:21.191854 iDelay=42, Bit 8, Center 17 (2 ~ 32) 31
1042 11:35:21.194645 iDelay=42, Bit 9, Center 19 (4 ~ 35) 32
1043 11:35:21.198050 iDelay=42, Bit 10, Center 25 (10 ~ 41) 32
1044 11:35:21.201473 iDelay=42, Bit 11, Center 18 (3 ~ 34) 32
1045 11:35:21.205018 iDelay=42, Bit 12, Center 20 (5 ~ 35) 31
1046 11:35:21.208659 iDelay=42, Bit 13, Center 21 (5 ~ 37) 33
1047 11:35:21.211593 iDelay=42, Bit 14, Center 20 (5 ~ 36) 32
1048 11:35:21.215279 iDelay=42, Bit 15, Center 23 (7 ~ 40) 34
1049 11:35:21.215381 ==
1050 11:35:21.222022 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1051 11:35:21.224763 fsp= 1, odt_onoff= 1, Byte mode= 0
1052 11:35:21.224863 ==
1053 11:35:21.224950 DQS Delay:
1054 11:35:21.228617 DQS0 = 0, DQS1 = 0
1055 11:35:21.228717 DQM Delay:
1056 11:35:21.228804 DQM0 = 21, DQM1 = 20
1057 11:35:21.232075 DQ Delay:
1058 11:35:21.235535 DQ0 =23, DQ1 =22, DQ2 =25, DQ3 =17
1059 11:35:21.238750 DQ4 =24, DQ5 =19, DQ6 =21, DQ7 =22
1060 11:35:21.241592 DQ8 =17, DQ9 =19, DQ10 =25, DQ11 =18
1061 11:35:21.244861 DQ12 =20, DQ13 =21, DQ14 =20, DQ15 =23
1062 11:35:21.244959
1063 11:35:21.245046
1064 11:35:21.245140 DramC Write-DBI off
1065 11:35:21.245225 ==
1066 11:35:21.251557 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1067 11:35:21.254929 fsp= 1, odt_onoff= 1, Byte mode= 0
1068 11:35:21.255012 ==
1069 11:35:21.258777 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1070 11:35:21.258854
1071 11:35:21.261942 Begin, DQ Scan Range 921~1177
1072 11:35:21.262018
1073 11:35:21.262076
1074 11:35:21.264896 TX Vref Scan disable
1075 11:35:21.268389 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1076 11:35:21.272230 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1077 11:35:21.274776 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1078 11:35:21.278984 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1079 11:35:21.281550 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1080 11:35:21.285273 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1081 11:35:21.288327 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1082 11:35:21.291444 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1083 11:35:21.295280 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1084 11:35:21.298883 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1085 11:35:21.301743 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1086 11:35:21.305393 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1087 11:35:21.308197 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1088 11:35:21.311836 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1089 11:35:21.318127 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1090 11:35:21.321557 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1091 11:35:21.325010 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1092 11:35:21.328751 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1093 11:35:21.331576 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1094 11:35:21.335116 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1095 11:35:21.338707 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1096 11:35:21.342173 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1097 11:35:21.344918 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1098 11:35:21.348653 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1099 11:35:21.351842 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1100 11:35:21.355652 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1101 11:35:21.358542 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1102 11:35:21.362122 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1103 11:35:21.365051 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1104 11:35:21.369060 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1105 11:35:21.372319 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1106 11:35:21.378505 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1107 11:35:21.383282 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1108 11:35:21.384987 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1109 11:35:21.388359 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1110 11:35:21.391887 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1111 11:35:21.395204 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1112 11:35:21.398678 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1113 11:35:21.401773 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1114 11:35:21.405333 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1115 11:35:21.409057 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1116 11:35:21.412375 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1117 11:35:21.415970 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1118 11:35:21.418341 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1119 11:35:21.421874 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1120 11:35:21.425870 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1121 11:35:21.428881 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1122 11:35:21.431823 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1123 11:35:21.435074 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1124 11:35:21.438747 970 |3 6 10|[0] xxxxxxxx ooxoooxx [MSB]
1125 11:35:21.441944 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1126 11:35:21.445583 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1127 11:35:21.448656 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1128 11:35:21.452037 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1129 11:35:21.458927 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1130 11:35:21.463226 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1131 11:35:21.465285 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1132 11:35:21.468967 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1133 11:35:21.471929 979 |3 6 19|[0] xxxoxxxx oooooooo [MSB]
1134 11:35:21.475441 980 |3 6 20|[0] xxxoooox oooooooo [MSB]
1135 11:35:21.479152 981 |3 6 21|[0] xxxooooo oooooooo [MSB]
1136 11:35:21.482135 982 |3 6 22|[0] xoxooooo oooooooo [MSB]
1137 11:35:21.485751 983 |3 6 23|[0] xooooooo oooooooo [MSB]
1138 11:35:21.488750 990 |3 6 30|[0] oooooooo xooxoooo [MSB]
1139 11:35:21.492309 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1140 11:35:21.495305 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1141 11:35:21.502224 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1142 11:35:21.505720 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1143 11:35:21.508731 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1144 11:35:21.512514 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1145 11:35:21.515460 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1146 11:35:21.519068 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1147 11:35:21.522660 999 |3 6 39|[0] oooxoxxo xxxxxxxx [MSB]
1148 11:35:21.525495 1000 |3 6 40|[0] oooxoxxo xxxxxxxx [MSB]
1149 11:35:21.529364 1001 |3 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
1150 11:35:21.532392 Byte0, DQ PI dly=989, DQM PI dly= 989
1151 11:35:21.535642 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
1152 11:35:21.535744
1153 11:35:21.542206 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
1154 11:35:21.542307
1155 11:35:21.545945 Byte1, DQ PI dly=980, DQM PI dly= 980
1156 11:35:21.549412 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1157 11:35:21.549510
1158 11:35:21.552216 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1159 11:35:21.552311
1160 11:35:21.555817 ==
1161 11:35:21.559177 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1162 11:35:21.562305 fsp= 1, odt_onoff= 1, Byte mode= 0
1163 11:35:21.562403 ==
1164 11:35:21.565411 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1165 11:35:21.565507
1166 11:35:21.569606 Begin, DQ Scan Range 956~1020
1167 11:35:21.572297 Write Rank0 MR14 =0x0
1168 11:35:21.579368
1169 11:35:21.579473 CH=0, VrefRange= 0, VrefLevel = 0
1170 11:35:21.587083 TX Bit0 (986~995) 10 990, Bit8 (971~983) 13 977,
1171 11:35:21.589481 TX Bit1 (984~996) 13 990, Bit9 (974~987) 14 980,
1172 11:35:21.596226 TX Bit2 (986~995) 10 990, Bit10 (979~989) 11 984,
1173 11:35:21.599569 TX Bit3 (979~991) 13 985, Bit11 (973~984) 12 978,
1174 11:35:21.603480 TX Bit4 (984~994) 11 989, Bit12 (973~987) 15 980,
1175 11:35:21.609970 TX Bit5 (984~992) 9 988, Bit13 (974~986) 13 980,
1176 11:35:21.612573 TX Bit6 (983~993) 11 988, Bit14 (975~988) 14 981,
1177 11:35:21.616253 TX Bit7 (983~994) 12 988, Bit15 (979~990) 12 984,
1178 11:35:21.616354
1179 11:35:21.619791 Write Rank0 MR14 =0x2
1180 11:35:21.628155
1181 11:35:21.628259 CH=0, VrefRange= 0, VrefLevel = 2
1182 11:35:21.634464 TX Bit0 (985~996) 12 990, Bit8 (970~984) 15 977,
1183 11:35:21.637741 TX Bit1 (984~996) 13 990, Bit9 (973~988) 16 980,
1184 11:35:21.644679 TX Bit2 (985~995) 11 990, Bit10 (978~990) 13 984,
1185 11:35:21.647632 TX Bit3 (979~992) 14 985, Bit11 (972~985) 14 978,
1186 11:35:21.651147 TX Bit4 (983~994) 12 988, Bit12 (973~987) 15 980,
1187 11:35:21.657995 TX Bit5 (983~993) 11 988, Bit13 (973~987) 15 980,
1188 11:35:21.660926 TX Bit6 (981~994) 14 987, Bit14 (975~989) 15 982,
1189 11:35:21.664704 TX Bit7 (983~994) 12 988, Bit15 (979~990) 12 984,
1190 11:35:21.664802
1191 11:35:21.667818 Write Rank0 MR14 =0x4
1192 11:35:21.676068
1193 11:35:21.676174 CH=0, VrefRange= 0, VrefLevel = 4
1194 11:35:21.683544 TX Bit0 (986~996) 11 991, Bit8 (970~985) 16 977,
1195 11:35:21.686479 TX Bit1 (983~997) 15 990, Bit9 (973~988) 16 980,
1196 11:35:21.692735 TX Bit2 (985~996) 12 990, Bit10 (978~990) 13 984,
1197 11:35:21.696310 TX Bit3 (979~992) 14 985, Bit11 (971~985) 15 978,
1198 11:35:21.699559 TX Bit4 (983~995) 13 989, Bit12 (972~988) 17 980,
1199 11:35:21.706345 TX Bit5 (982~993) 12 987, Bit13 (973~987) 15 980,
1200 11:35:21.709465 TX Bit6 (982~994) 13 988, Bit14 (975~989) 15 982,
1201 11:35:21.713283 TX Bit7 (983~995) 13 989, Bit15 (979~991) 13 985,
1202 11:35:21.713384
1203 11:35:21.716116 Write Rank0 MR14 =0x6
1204 11:35:21.725038
1205 11:35:21.725180 CH=0, VrefRange= 0, VrefLevel = 6
1206 11:35:21.731597 TX Bit0 (985~998) 14 991, Bit8 (970~985) 16 977,
1207 11:35:21.734969 TX Bit1 (984~997) 14 990, Bit9 (972~989) 18 980,
1208 11:35:21.741268 TX Bit2 (984~997) 14 990, Bit10 (977~991) 15 984,
1209 11:35:21.745094 TX Bit3 (979~993) 15 986, Bit11 (971~987) 17 979,
1210 11:35:21.748335 TX Bit4 (983~996) 14 989, Bit12 (972~989) 18 980,
1211 11:35:21.754532 TX Bit5 (982~993) 12 987, Bit13 (973~988) 16 980,
1212 11:35:21.758229 TX Bit6 (981~995) 15 988, Bit14 (974~990) 17 982,
1213 11:35:21.761595 TX Bit7 (982~995) 14 988, Bit15 (977~992) 16 984,
1214 11:35:21.761695
1215 11:35:21.764622 Write Rank0 MR14 =0x8
1216 11:35:21.773283
1217 11:35:21.773386 CH=0, VrefRange= 0, VrefLevel = 8
1218 11:35:21.780394 TX Bit0 (985~998) 14 991, Bit8 (970~986) 17 978,
1219 11:35:21.782997 TX Bit1 (982~998) 17 990, Bit9 (971~989) 19 980,
1220 11:35:21.818328 TX Bit2 (984~998) 15 991, Bit10 (977~991) 15 984,
1221 11:35:21.818696 TX Bit3 (979~993) 15 986, Bit11 (971~987) 17 979,
1222 11:35:21.819153 TX Bit4 (982~996) 15 989, Bit12 (971~989) 19 980,
1223 11:35:21.819558 TX Bit5 (981~994) 14 987, Bit13 (971~988) 18 979,
1224 11:35:21.819655 TX Bit6 (980~995) 16 987, Bit14 (973~990) 18 981,
1225 11:35:21.819939 TX Bit7 (982~996) 15 989, Bit15 (977~992) 16 984,
1226 11:35:21.820041
1227 11:35:21.824324 Write Rank0 MR14 =0xa
1228 11:35:21.824420
1229 11:35:21.824509 CH=0, VrefRange= 0, VrefLevel = 10
1230 11:35:21.827333 TX Bit0 (984~1000) 17 992, Bit8 (969~987) 19 978,
1231 11:35:21.834189 TX Bit1 (982~998) 17 990, Bit9 (971~990) 20 980,
1232 11:35:21.837708 TX Bit2 (984~998) 15 991, Bit10 (977~992) 16 984,
1233 11:35:21.841052 TX Bit3 (978~993) 16 985, Bit11 (970~988) 19 979,
1234 11:35:21.847266 TX Bit4 (982~997) 16 989, Bit12 (971~989) 19 980,
1235 11:35:21.850815 TX Bit5 (980~995) 16 987, Bit13 (971~989) 19 980,
1236 11:35:21.854622 TX Bit6 (980~996) 17 988, Bit14 (973~991) 19 982,
1237 11:35:21.861508 TX Bit7 (981~997) 17 989, Bit15 (977~994) 18 985,
1238 11:35:21.861612
1239 11:35:21.861699 Write Rank0 MR14 =0xc
1240 11:35:21.871162
1241 11:35:21.874664 CH=0, VrefRange= 0, VrefLevel = 12
1242 11:35:21.878548 TX Bit0 (984~1001) 18 992, Bit8 (969~988) 20 978,
1243 11:35:21.881665 TX Bit1 (982~1000) 19 991, Bit9 (970~990) 21 980,
1244 11:35:21.888164 TX Bit2 (984~1000) 17 992, Bit10 (976~993) 18 984,
1245 11:35:21.892081 TX Bit3 (978~994) 17 986, Bit11 (970~988) 19 979,
1246 11:35:21.894490 TX Bit4 (981~998) 18 989, Bit12 (971~990) 20 980,
1247 11:35:21.901554 TX Bit5 (980~995) 16 987, Bit13 (971~989) 19 980,
1248 11:35:21.904492 TX Bit6 (980~996) 17 988, Bit14 (972~991) 20 981,
1249 11:35:21.908028 TX Bit7 (981~998) 18 989, Bit15 (977~994) 18 985,
1250 11:35:21.911747
1251 11:35:21.911846 Write Rank0 MR14 =0xe
1252 11:35:21.920855
1253 11:35:21.920961 CH=0, VrefRange= 0, VrefLevel = 14
1254 11:35:21.927592 TX Bit0 (983~1001) 19 992, Bit8 (969~988) 20 978,
1255 11:35:21.930492 TX Bit1 (982~1000) 19 991, Bit9 (970~990) 21 980,
1256 11:35:21.937333 TX Bit2 (983~1000) 18 991, Bit10 (976~994) 19 985,
1257 11:35:21.941190 TX Bit3 (978~994) 17 986, Bit11 (969~989) 21 979,
1258 11:35:21.943908 TX Bit4 (980~998) 19 989, Bit12 (970~990) 21 980,
1259 11:35:21.951448 TX Bit5 (980~996) 17 988, Bit13 (970~990) 21 980,
1260 11:35:21.954185 TX Bit6 (980~997) 18 988, Bit14 (971~992) 22 981,
1261 11:35:21.957468 TX Bit7 (981~998) 18 989, Bit15 (977~995) 19 986,
1262 11:35:21.961196
1263 11:35:21.961295 Write Rank0 MR14 =0x10
1264 11:35:21.970209
1265 11:35:21.970309 CH=0, VrefRange= 0, VrefLevel = 16
1266 11:35:21.976633 TX Bit0 (983~1001) 19 992, Bit8 (968~989) 22 978,
1267 11:35:21.980149 TX Bit1 (981~1000) 20 990, Bit9 (970~991) 22 980,
1268 11:35:21.986845 TX Bit2 (983~1001) 19 992, Bit10 (976~995) 20 985,
1269 11:35:21.989898 TX Bit3 (978~994) 17 986, Bit11 (969~989) 21 979,
1270 11:35:21.993541 TX Bit4 (980~999) 20 989, Bit12 (970~990) 21 980,
1271 11:35:21.999872 TX Bit5 (980~996) 17 988, Bit13 (970~990) 21 980,
1272 11:35:22.003547 TX Bit6 (980~998) 19 989, Bit14 (972~992) 21 982,
1273 11:35:22.006733 TX Bit7 (980~999) 20 989, Bit15 (976~995) 20 985,
1274 11:35:22.010288
1275 11:35:22.010389 Write Rank0 MR14 =0x12
1276 11:35:22.019994
1277 11:35:22.023197 CH=0, VrefRange= 0, VrefLevel = 18
1278 11:35:22.026589 TX Bit0 (983~1002) 20 992, Bit8 (969~989) 21 979,
1279 11:35:22.030045 TX Bit1 (981~1001) 21 991, Bit9 (970~991) 22 980,
1280 11:35:22.036371 TX Bit2 (983~1001) 19 992, Bit10 (976~995) 20 985,
1281 11:35:22.039770 TX Bit3 (978~995) 18 986, Bit11 (969~990) 22 979,
1282 11:35:22.043266 TX Bit4 (980~1000) 21 990, Bit12 (970~990) 21 980,
1283 11:35:22.049733 TX Bit5 (980~996) 17 988, Bit13 (970~990) 21 980,
1284 11:35:22.053395 TX Bit6 (979~999) 21 989, Bit14 (971~993) 23 982,
1285 11:35:22.059855 TX Bit7 (980~1000) 21 990, Bit15 (975~996) 22 985,
1286 11:35:22.059959
1287 11:35:22.063051 wait MRW command Rank0 MR14 =0x14 fired (1)
1288 11:35:22.063147 Write Rank0 MR14 =0x14
1289 11:35:22.073774
1290 11:35:22.077277 CH=0, VrefRange= 0, VrefLevel = 20
1291 11:35:22.080543 TX Bit0 (984~1003) 20 993, Bit8 (968~989) 22 978,
1292 11:35:22.083761 TX Bit1 (981~1002) 22 991, Bit9 (969~992) 24 980,
1293 11:35:22.090781 TX Bit2 (982~1002) 21 992, Bit10 (975~996) 22 985,
1294 11:35:22.093546 TX Bit3 (977~995) 19 986, Bit11 (969~990) 22 979,
1295 11:35:22.097466 TX Bit4 (980~1000) 21 990, Bit12 (969~992) 24 980,
1296 11:35:22.103838 TX Bit5 (979~997) 19 988, Bit13 (969~991) 23 980,
1297 11:35:22.107052 TX Bit6 (980~999) 20 989, Bit14 (970~993) 24 981,
1298 11:35:22.113875 TX Bit7 (980~1000) 21 990, Bit15 (975~996) 22 985,
1299 11:35:22.113983
1300 11:35:22.114069 Write Rank0 MR14 =0x16
1301 11:35:22.123886
1302 11:35:22.126784 CH=0, VrefRange= 0, VrefLevel = 22
1303 11:35:22.130772 TX Bit0 (982~1003) 22 992, Bit8 (968~990) 23 979,
1304 11:35:22.134071 TX Bit1 (981~1002) 22 991, Bit9 (969~992) 24 980,
1305 11:35:22.140189 TX Bit2 (982~1002) 21 992, Bit10 (975~996) 22 985,
1306 11:35:22.143670 TX Bit3 (977~995) 19 986, Bit11 (969~990) 22 979,
1307 11:35:22.146781 TX Bit4 (980~1001) 22 990, Bit12 (969~992) 24 980,
1308 11:35:22.154107 TX Bit5 (979~998) 20 988, Bit13 (969~991) 23 980,
1309 11:35:22.156742 TX Bit6 (979~999) 21 989, Bit14 (970~994) 25 982,
1310 11:35:22.163666 TX Bit7 (981~1001) 21 991, Bit15 (975~997) 23 986,
1311 11:35:22.163797
1312 11:35:22.163970 Write Rank0 MR14 =0x18
1313 11:35:22.174084
1314 11:35:22.177058 CH=0, VrefRange= 0, VrefLevel = 24
1315 11:35:22.180517 TX Bit0 (982~1004) 23 993, Bit8 (968~990) 23 979,
1316 11:35:22.183444 TX Bit1 (980~1003) 24 991, Bit9 (969~992) 24 980,
1317 11:35:22.190394 TX Bit2 (982~1003) 22 992, Bit10 (974~996) 23 985,
1318 11:35:22.193841 TX Bit3 (977~996) 20 986, Bit11 (968~991) 24 979,
1319 11:35:22.197386 TX Bit4 (980~1001) 22 990, Bit12 (969~993) 25 981,
1320 11:35:22.203878 TX Bit5 (979~999) 21 989, Bit13 (969~992) 24 980,
1321 11:35:22.207333 TX Bit6 (979~1000) 22 989, Bit14 (970~995) 26 982,
1322 11:35:22.213471 TX Bit7 (980~1001) 22 990, Bit15 (974~996) 23 985,
1323 11:35:22.213609
1324 11:35:22.213730 Write Rank0 MR14 =0x1a
1325 11:35:22.224067
1326 11:35:22.227254 CH=0, VrefRange= 0, VrefLevel = 26
1327 11:35:22.230284 TX Bit0 (982~1004) 23 993, Bit8 (967~991) 25 979,
1328 11:35:22.233876 TX Bit1 (980~1003) 24 991, Bit9 (969~992) 24 980,
1329 11:35:22.241023 TX Bit2 (981~1003) 23 992, Bit10 (974~997) 24 985,
1330 11:35:22.244094 TX Bit3 (977~996) 20 986, Bit11 (968~991) 24 979,
1331 11:35:22.247034 TX Bit4 (979~1002) 24 990, Bit12 (969~993) 25 981,
1332 11:35:22.254576 TX Bit5 (979~999) 21 989, Bit13 (969~993) 25 981,
1333 11:35:22.257306 TX Bit6 (979~1001) 23 990, Bit14 (970~995) 26 982,
1334 11:35:22.264222 TX Bit7 (979~1002) 24 990, Bit15 (975~997) 23 986,
1335 11:35:22.264343
1336 11:35:22.264433 Write Rank0 MR14 =0x1c
1337 11:35:22.274803
1338 11:35:22.277863 CH=0, VrefRange= 0, VrefLevel = 28
1339 11:35:22.280840 TX Bit0 (983~1005) 23 994, Bit8 (967~990) 24 978,
1340 11:35:22.284017 TX Bit1 (980~1003) 24 991, Bit9 (969~992) 24 980,
1341 11:35:22.291259 TX Bit2 (981~1004) 24 992, Bit10 (974~997) 24 985,
1342 11:35:22.294743 TX Bit3 (977~997) 21 987, Bit11 (968~991) 24 979,
1343 11:35:22.297544 TX Bit4 (980~1003) 24 991, Bit12 (969~993) 25 981,
1344 11:35:22.305070 TX Bit5 (979~999) 21 989, Bit13 (969~993) 25 981,
1345 11:35:22.307803 TX Bit6 (979~1001) 23 990, Bit14 (969~995) 27 982,
1346 11:35:22.314368 TX Bit7 (979~1003) 25 991, Bit15 (975~997) 23 986,
1347 11:35:22.314456
1348 11:35:22.314558 Write Rank0 MR14 =0x1e
1349 11:35:22.324498
1350 11:35:22.328609 CH=0, VrefRange= 0, VrefLevel = 30
1351 11:35:22.332088 TX Bit0 (980~1005) 26 992, Bit8 (967~990) 24 978,
1352 11:35:22.334967 TX Bit1 (980~1003) 24 991, Bit9 (968~991) 24 979,
1353 11:35:22.341265 TX Bit2 (981~1005) 25 993, Bit10 (973~997) 25 985,
1354 11:35:22.344745 TX Bit3 (977~997) 21 987, Bit11 (968~991) 24 979,
1355 11:35:22.348413 TX Bit4 (980~1003) 24 991, Bit12 (969~993) 25 981,
1356 11:35:22.354796 TX Bit5 (979~1000) 22 989, Bit13 (969~993) 25 981,
1357 11:35:22.358077 TX Bit6 (979~1002) 24 990, Bit14 (969~994) 26 981,
1358 11:35:22.365155 TX Bit7 (979~1003) 25 991, Bit15 (974~997) 24 985,
1359 11:35:22.365253
1360 11:35:22.365312 Write Rank0 MR14 =0x20
1361 11:35:22.375016
1362 11:35:22.378190 CH=0, VrefRange= 0, VrefLevel = 32
1363 11:35:22.381662 TX Bit0 (980~1005) 26 992, Bit8 (967~990) 24 978,
1364 11:35:22.385175 TX Bit1 (980~1003) 24 991, Bit9 (968~991) 24 979,
1365 11:35:22.391878 TX Bit2 (981~1005) 25 993, Bit10 (973~997) 25 985,
1366 11:35:22.394923 TX Bit3 (977~997) 21 987, Bit11 (968~991) 24 979,
1367 11:35:22.398857 TX Bit4 (980~1003) 24 991, Bit12 (969~993) 25 981,
1368 11:35:22.405455 TX Bit5 (979~1000) 22 989, Bit13 (969~993) 25 981,
1369 11:35:22.408523 TX Bit6 (979~1002) 24 990, Bit14 (969~994) 26 981,
1370 11:35:22.415522 TX Bit7 (979~1003) 25 991, Bit15 (974~997) 24 985,
1371 11:35:22.415612
1372 11:35:22.415670 Write Rank0 MR14 =0x22
1373 11:35:22.425692
1374 11:35:22.429266 CH=0, VrefRange= 0, VrefLevel = 34
1375 11:35:22.431947 TX Bit0 (980~1005) 26 992, Bit8 (967~990) 24 978,
1376 11:35:22.435234 TX Bit1 (980~1003) 24 991, Bit9 (968~991) 24 979,
1377 11:35:22.442907 TX Bit2 (981~1005) 25 993, Bit10 (973~997) 25 985,
1378 11:35:22.445134 TX Bit3 (977~997) 21 987, Bit11 (968~991) 24 979,
1379 11:35:22.448619 TX Bit4 (980~1003) 24 991, Bit12 (969~993) 25 981,
1380 11:35:22.455650 TX Bit5 (979~1000) 22 989, Bit13 (969~993) 25 981,
1381 11:35:22.458445 TX Bit6 (979~1002) 24 990, Bit14 (969~994) 26 981,
1382 11:35:22.465137 TX Bit7 (979~1003) 25 991, Bit15 (974~997) 24 985,
1383 11:35:22.465213
1384 11:35:22.468848 wait MRW command Rank0 MR14 =0x24 fired (1)
1385 11:35:22.468923 Write Rank0 MR14 =0x24
1386 11:35:22.479393
1387 11:35:22.482778 CH=0, VrefRange= 0, VrefLevel = 36
1388 11:35:22.486768 TX Bit0 (980~1005) 26 992, Bit8 (967~990) 24 978,
1389 11:35:22.491281 TX Bit1 (980~1003) 24 991, Bit9 (968~991) 24 979,
1390 11:35:22.496243 TX Bit2 (981~1005) 25 993, Bit10 (973~997) 25 985,
1391 11:35:22.499566 TX Bit3 (977~997) 21 987, Bit11 (968~991) 24 979,
1392 11:35:22.503135 TX Bit4 (980~1003) 24 991, Bit12 (969~993) 25 981,
1393 11:35:22.509389 TX Bit5 (979~1000) 22 989, Bit13 (969~993) 25 981,
1394 11:35:22.512760 TX Bit6 (979~1002) 24 990, Bit14 (969~994) 26 981,
1395 11:35:22.519286 TX Bit7 (979~1003) 25 991, Bit15 (974~997) 24 985,
1396 11:35:22.519362
1397 11:35:22.519419
1398 11:35:22.522878 TX Vref found, early break! 364< 368
1399 11:35:22.526634 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
1400 11:35:22.529393 u1DelayCellOfst[0]=5 cells (5 PI)
1401 11:35:22.532832 u1DelayCellOfst[1]=4 cells (4 PI)
1402 11:35:22.536223 u1DelayCellOfst[2]=7 cells (6 PI)
1403 11:35:22.539702 u1DelayCellOfst[3]=0 cells (0 PI)
1404 11:35:22.542722 u1DelayCellOfst[4]=4 cells (4 PI)
1405 11:35:22.546127 u1DelayCellOfst[5]=2 cells (2 PI)
1406 11:35:22.546220 u1DelayCellOfst[6]=3 cells (3 PI)
1407 11:35:22.549425 u1DelayCellOfst[7]=4 cells (4 PI)
1408 11:35:22.552563 Byte0, DQ PI dly=987, DQM PI dly= 990
1409 11:35:22.560294 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1410 11:35:22.560386
1411 11:35:22.563524 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1412 11:35:22.563621
1413 11:35:22.566464 u1DelayCellOfst[8]=0 cells (0 PI)
1414 11:35:22.569227 u1DelayCellOfst[9]=1 cells (1 PI)
1415 11:35:22.572706 u1DelayCellOfst[10]=8 cells (7 PI)
1416 11:35:22.576760 u1DelayCellOfst[11]=1 cells (1 PI)
1417 11:35:22.579102 u1DelayCellOfst[12]=3 cells (3 PI)
1418 11:35:22.582892 u1DelayCellOfst[13]=3 cells (3 PI)
1419 11:35:22.586085 u1DelayCellOfst[14]=3 cells (3 PI)
1420 11:35:22.586161 u1DelayCellOfst[15]=8 cells (7 PI)
1421 11:35:22.590079 Byte1, DQ PI dly=978, DQM PI dly= 981
1422 11:35:22.596052 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1423 11:35:22.596128
1424 11:35:22.599960 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1425 11:35:22.600036
1426 11:35:22.603050 Write Rank0 MR14 =0x1e
1427 11:35:22.603125
1428 11:35:22.603183 Final TX Range 0 Vref 30
1429 11:35:22.606292
1430 11:35:22.609437 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1431 11:35:22.609514
1432 11:35:22.616078 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1433 11:35:22.622847 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1434 11:35:22.633582 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1435 11:35:22.633659 Write Rank0 MR3 =0xb0
1436 11:35:22.636283 DramC Write-DBI on
1437 11:35:22.636358 ==
1438 11:35:22.639494 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1439 11:35:22.643309 fsp= 1, odt_onoff= 1, Byte mode= 0
1440 11:35:22.643384 ==
1441 11:35:22.649500 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1442 11:35:22.649576
1443 11:35:22.649635 Begin, DQ Scan Range 701~765
1444 11:35:22.649690
1445 11:35:22.649741
1446 11:35:22.652980 TX Vref Scan disable
1447 11:35:22.656214 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1448 11:35:22.660442 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1449 11:35:22.663262 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1450 11:35:22.666329 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1451 11:35:22.669496 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1452 11:35:22.673270 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1453 11:35:22.676621 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1454 11:35:22.679835 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1455 11:35:22.686088 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1456 11:35:22.690505 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1457 11:35:22.693218 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1458 11:35:22.696612 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1459 11:35:22.700047 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1460 11:35:22.703190 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1461 11:35:22.706265 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1462 11:35:22.709733 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1463 11:35:22.713478 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1464 11:35:22.716562 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1465 11:35:22.719586 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1466 11:35:22.722775 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1467 11:35:22.727080 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
1468 11:35:22.729658 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
1469 11:35:22.737625 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1470 11:35:22.740903 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1471 11:35:22.744598 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1472 11:35:22.748161 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1473 11:35:22.750828 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1474 11:35:22.754499 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1475 11:35:22.757888 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1476 11:35:22.761058 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1477 11:35:22.764573 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
1478 11:35:22.767706 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
1479 11:35:22.771083 749 |2 6 45|[0] xxxxxxxx xxxxxxxx [MSB]
1480 11:35:22.774437 Byte0, DQ PI dly=735, DQM PI dly= 735
1481 11:35:22.777679 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
1482 11:35:22.781075
1483 11:35:22.784661 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
1484 11:35:22.784739
1485 11:35:22.787844 Byte1, DQ PI dly=725, DQM PI dly= 725
1486 11:35:22.791210 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
1487 11:35:22.791287
1488 11:35:22.794137 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
1489 11:35:22.797865
1490 11:35:22.801154 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1491 11:35:22.811201 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1492 11:35:22.817636 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1493 11:35:22.817720 Write Rank0 MR3 =0x30
1494 11:35:22.821517 DramC Write-DBI off
1495 11:35:22.821592
1496 11:35:22.821650 [DATLAT]
1497 11:35:22.824426 Freq=1600, CH0 RK0, use_rxtx_scan=0
1498 11:35:22.824501
1499 11:35:22.828359 DATLAT Default: 0xf
1500 11:35:22.828435 7, 0xFFFF, sum=0
1501 11:35:22.831184 8, 0xFFFF, sum=0
1502 11:35:22.831260 9, 0xFFFF, sum=0
1503 11:35:22.834632 10, 0xFFFF, sum=0
1504 11:35:22.834712 11, 0xFFFF, sum=0
1505 11:35:22.838806 12, 0xFFFF, sum=0
1506 11:35:22.838888 13, 0xFFFF, sum=0
1507 11:35:22.838967 14, 0x0, sum=1
1508 11:35:22.841405 15, 0x0, sum=2
1509 11:35:22.841483 16, 0x0, sum=3
1510 11:35:22.844846 17, 0x0, sum=4
1511 11:35:22.847689 pattern=2 first_step=14 total pass=5 best_step=16
1512 11:35:22.847770 ==
1513 11:35:22.854317 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1514 11:35:22.857696 fsp= 1, odt_onoff= 1, Byte mode= 0
1515 11:35:22.857775 ==
1516 11:35:22.860927 Start DQ dly to find pass range UseTestEngine =1
1517 11:35:22.864517 x-axis: bit #, y-axis: DQ dly (-127~63)
1518 11:35:22.864596 RX Vref Scan = 1
1519 11:35:22.981023
1520 11:35:22.981218 RX Vref found, early break!
1521 11:35:22.981308
1522 11:35:22.987504 Final RX Vref 12, apply to both rank0 and 1
1523 11:35:22.987640 ==
1524 11:35:22.990689 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1525 11:35:22.994016 fsp= 1, odt_onoff= 1, Byte mode= 0
1526 11:35:22.994107 ==
1527 11:35:22.994179 DQS Delay:
1528 11:35:22.997625 DQS0 = 0, DQS1 = 0
1529 11:35:22.997729 DQM Delay:
1530 11:35:23.001444 DQM0 = 21, DQM1 = 20
1531 11:35:23.001533 DQ Delay:
1532 11:35:23.004539 DQ0 =23, DQ1 =23, DQ2 =24, DQ3 =17
1533 11:35:23.007346 DQ4 =23, DQ5 =19, DQ6 =20, DQ7 =23
1534 11:35:23.010962 DQ8 =17, DQ9 =18, DQ10 =25, DQ11 =18
1535 11:35:23.014125 DQ12 =20, DQ13 =19, DQ14 =21, DQ15 =23
1536 11:35:23.014204
1537 11:35:23.014263
1538 11:35:23.014317
1539 11:35:23.017336 [DramC_TX_OE_Calibration] TA2
1540 11:35:23.020741 Original DQ_B0 (3 6) =30, OEN = 27
1541 11:35:23.024416 Original DQ_B1 (3 6) =30, OEN = 27
1542 11:35:23.027309 23, 0x0, End_B0=23 End_B1=23
1543 11:35:23.027386 24, 0x0, End_B0=24 End_B1=24
1544 11:35:23.030921 25, 0x0, End_B0=25 End_B1=25
1545 11:35:23.035062 26, 0x0, End_B0=26 End_B1=26
1546 11:35:23.037685 27, 0x0, End_B0=27 End_B1=27
1547 11:35:23.037778 28, 0x0, End_B0=28 End_B1=28
1548 11:35:23.040968 29, 0x0, End_B0=29 End_B1=29
1549 11:35:23.044330 30, 0x0, End_B0=30 End_B1=30
1550 11:35:23.047582 31, 0xFFFF, End_B0=30 End_B1=30
1551 11:35:23.051307 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1552 11:35:23.057831 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1553 11:35:23.057925
1554 11:35:23.057997
1555 11:35:23.061060 Write Rank0 MR23 =0x3f
1556 11:35:23.061143 [DQSOSC]
1557 11:35:23.071166 [DQSOSCAuto] RK0, (LSB)MR18= 0xcaca, (MSB)MR19= 0x202, tDQSOscB0 = 441 ps tDQSOscB1 = 441 ps
1558 11:35:23.074893 CH0_RK0: MR19=0x202, MR18=0xCACA, DQSOSC=441, MR23=63, INC=12, DEC=18
1559 11:35:23.077878 Write Rank0 MR23 =0x3f
1560 11:35:23.077970 [DQSOSC]
1561 11:35:23.088155 [DQSOSCAuto] RK0, (LSB)MR18= 0xcece, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
1562 11:35:23.088236 CH0 RK0: MR19=202, MR18=CECE
1563 11:35:23.094527 [RankSwap] Rank num 2, (Multi 1), Rank 1
1564 11:35:23.094605 Write Rank0 MR2 =0xad
1565 11:35:23.097820 [Write Leveling]
1566 11:35:23.097896 delay byte0 byte1 byte2 byte3
1567 11:35:23.101007
1568 11:35:23.101082 10 0 0
1569 11:35:23.101184 11 0 0
1570 11:35:23.104694 12 0 0
1571 11:35:23.104771 13 0 0
1572 11:35:23.108431 14 0 0
1573 11:35:23.108507 15 0 0
1574 11:35:23.108567 16 0 0
1575 11:35:23.111227 17 0 0
1576 11:35:23.111304 18 0 0
1577 11:35:23.114507 19 0 0
1578 11:35:23.114585 20 0 0
1579 11:35:23.114644 21 0 0
1580 11:35:23.117873 22 0 0
1581 11:35:23.117950 23 0 0
1582 11:35:23.121377 24 0 0
1583 11:35:23.121456 25 0 ff
1584 11:35:23.124493 26 0 ff
1585 11:35:23.124570 27 0 ff
1586 11:35:23.124629 28 0 ff
1587 11:35:23.128286 29 0 ff
1588 11:35:23.128364 30 0 ff
1589 11:35:23.131805 31 0 ff
1590 11:35:23.131881 32 0 ff
1591 11:35:23.134919 33 0 ff
1592 11:35:23.134996 34 ff ff
1593 11:35:23.138383 35 ff ff
1594 11:35:23.138461 36 ff ff
1595 11:35:23.140934 37 ff ff
1596 11:35:23.141011 38 ff ff
1597 11:35:23.141070 39 ff ff
1598 11:35:23.144921 40 ff ff
1599 11:35:23.147808 pass bytecount = 0xff (0xff: all bytes pass)
1600 11:35:23.147885
1601 11:35:23.151946 DQS0 dly: 34
1602 11:35:23.152022 DQS1 dly: 25
1603 11:35:23.152081 Write Rank0 MR2 =0x2d
1604 11:35:23.158147 [RankSwap] Rank num 2, (Multi 1), Rank 0
1605 11:35:23.158229 Write Rank1 MR1 =0xd6
1606 11:35:23.158288 [Gating]
1607 11:35:23.161014 ==
1608 11:35:23.164546 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1609 11:35:23.167994 fsp= 1, odt_onoff= 1, Byte mode= 0
1610 11:35:23.168070 ==
1611 11:35:23.170902 3 1 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1612 11:35:23.177930 3 1 4 |3534 3535 |(11 11)(11 11) |(0 0)(1 1)| 0
1613 11:35:23.181605 3 1 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1614 11:35:23.184433 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1615 11:35:23.191308 3 1 16 |3534 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
1616 11:35:23.194294 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1617 11:35:23.197979 [Byte 1] Lead/lag Transition tap number (1)
1618 11:35:23.201679 3 1 24 |3534 f0f |(11 11)(11 11) |(0 0)(0 0)| 0
1619 11:35:23.207663 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1620 11:35:23.212039 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1621 11:35:23.214784 3 2 4 |3534 3434 |(11 11)(11 11) |(0 0)(0 0)| 0
1622 11:35:23.220843 3 2 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
1623 11:35:23.224909 3 2 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1624 11:35:23.228016 3 2 16 |3534 1e1e |(11 11)(11 11) |(1 1)(0 1)| 0
1625 11:35:23.231047 3 2 20 |3d3d 3433 |(11 11)(11 11) |(1 1)(0 0)| 0
1626 11:35:23.238344 3 2 24 |3d3d 2625 |(11 11)(11 11) |(1 1)(1 1)| 0
1627 11:35:23.241683 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1628 11:35:23.244343 3 3 0 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1629 11:35:23.251173 3 3 4 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1630 11:35:23.254744 3 3 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1631 11:35:23.258393 3 3 12 |3d3d 2323 |(11 11)(11 11) |(1 1)(1 1)| 0
1632 11:35:23.264804 3 3 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1633 11:35:23.268083 3 3 20 |201 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1634 11:35:23.271195 3 3 24 |3534 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1635 11:35:23.274666 [Byte 0] Lead/lag Transition tap number (1)
1636 11:35:23.281825 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1637 11:35:23.284934 [Byte 1] Lead/lag Transition tap number (1)
1638 11:35:23.287840 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1639 11:35:23.291234 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1640 11:35:23.297946 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1641 11:35:23.301166 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
1642 11:35:23.304527 3 4 16 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1643 11:35:23.311638 3 4 20 |3d3d 201 |(11 11)(11 11) |(1 1)(0 1)| 0
1644 11:35:23.314628 3 4 24 |3d3d 100f |(11 11)(11 11) |(1 1)(1 1)| 0
1645 11:35:23.318535 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1646 11:35:23.321682 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1647 11:35:23.328262 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1648 11:35:23.331299 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1649 11:35:23.334889 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1650 11:35:23.341496 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1651 11:35:23.344750 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1652 11:35:23.347952 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1653 11:35:23.354685 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1654 11:35:23.357913 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1655 11:35:23.361084 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1656 11:35:23.365910 [Byte 0] Lead/lag falling Transition (3, 6, 4)
1657 11:35:23.371088 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1658 11:35:23.374691 [Byte 1] Lead/lag falling Transition (3, 6, 8)
1659 11:35:23.377746 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1660 11:35:23.381435 [Byte 0] Lead/lag Transition tap number (3)
1661 11:35:23.387864 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1662 11:35:23.391483 [Byte 1] Lead/lag Transition tap number (3)
1663 11:35:23.394626 3 6 20 |808 3d3d |(1 1)(11 11) |(0 0)(0 0)| 0
1664 11:35:23.397946 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1665 11:35:23.402427 [Byte 0]First pass (3, 6, 24)
1666 11:35:23.404709 [Byte 1]First pass (3, 6, 24)
1667 11:35:23.408648 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1668 11:35:23.411870 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1669 11:35:23.415344 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1670 11:35:23.421693 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1671 11:35:23.425000 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1672 11:35:23.428828 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1673 11:35:23.431419 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1674 11:35:23.435600 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1675 11:35:23.441551 All bytes gating window > 1UI, Early break!
1676 11:35:23.441631
1677 11:35:23.445063 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10)
1678 11:35:23.445167
1679 11:35:23.449027 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 14)
1680 11:35:23.449106
1681 11:35:23.449190
1682 11:35:23.449246
1683 11:35:23.451573 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
1684 11:35:23.451650
1685 11:35:23.455023 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
1686 11:35:23.458836
1687 11:35:23.458912
1688 11:35:23.458970 Write Rank1 MR1 =0x56
1689 11:35:23.459025
1690 11:35:23.462423 best RODT dly(2T, 0.5T) = (2, 3)
1691 11:35:23.462524
1692 11:35:23.466021 best RODT dly(2T, 0.5T) = (2, 3)
1693 11:35:23.466120 ==
1694 11:35:23.472053 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1695 11:35:23.472133 fsp= 1, odt_onoff= 1, Byte mode= 0
1696 11:35:23.475424 ==
1697 11:35:23.479059 Start DQ dly to find pass range UseTestEngine =0
1698 11:35:23.481745 x-axis: bit #, y-axis: DQ dly (-127~63)
1699 11:35:23.481821 RX Vref Scan = 0
1700 11:35:23.485312 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1701 11:35:23.488840 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1702 11:35:23.491806 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1703 11:35:23.495533 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1704 11:35:23.498694 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1705 11:35:23.502186 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1706 11:35:23.505226 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1707 11:35:23.505304 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1708 11:35:23.508456 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1709 11:35:23.512021 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1710 11:35:23.515198 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1711 11:35:23.519454 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1712 11:35:23.522041 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1713 11:35:23.526213 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1714 11:35:23.529594 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1715 11:35:23.529674 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1716 11:35:23.532801 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1717 11:35:23.535700 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1718 11:35:23.538700 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1719 11:35:23.542777 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1720 11:35:23.545563 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1721 11:35:23.549669 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1722 11:35:23.549746 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1723 11:35:23.552336 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1724 11:35:23.555874 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1725 11:35:23.558697 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1726 11:35:23.561903 0, [0] xxxxxxxx xxxxxxxx [MSB]
1727 11:35:23.565612 1, [0] xxxxxxxx xxxxxxxx [MSB]
1728 11:35:23.565689 2, [0] xxxoxxxx oxxxxxxx [MSB]
1729 11:35:23.568633 3, [0] xxxoxxxx oxxxxxxx [MSB]
1730 11:35:23.572381 4, [0] xxxoxoxx oxxoxxxx [MSB]
1731 11:35:23.575693 5, [0] xxxoxooo ooxoxxxx [MSB]
1732 11:35:23.578495 6, [0] xxxoxooo ooxoxxxx [MSB]
1733 11:35:23.582066 7, [0] xooooooo ooxoooox [MSB]
1734 11:35:23.582144 8, [0] oooooooo ooxoooox [MSB]
1735 11:35:23.585471 9, [0] oooooooo ooxooooo [MSB]
1736 11:35:23.589268 10, [0] oooooooo ooxooooo [MSB]
1737 11:35:23.591825 32, [0] oooooooo oooooooo [MSB]
1738 11:35:23.595275 33, [0] oooxoooo xooooooo [MSB]
1739 11:35:23.598754 34, [0] oooxoooo xooooooo [MSB]
1740 11:35:23.602454 35, [0] oooxoooo xooxoooo [MSB]
1741 11:35:23.602531 36, [0] oooxooxo xxoxxooo [MSB]
1742 11:35:23.605412 37, [0] oooxoxxo xxoxxxoo [MSB]
1743 11:35:23.608845 38, [0] oooxoxxo xxoxxxxo [MSB]
1744 11:35:23.612191 39, [0] oooxoxxx xxoxxxxo [MSB]
1745 11:35:23.615367 40, [0] oxoxxxxx xxoxxxxx [MSB]
1746 11:35:23.618931 41, [0] oxxxxxxx xxoxxxxx [MSB]
1747 11:35:23.619010 42, [0] xxxxxxxx xxoxxxxx [MSB]
1748 11:35:23.621898 43, [0] xxxxxxxx xxxxxxxx [MSB]
1749 11:35:23.625373 iDelay=43, Bit 0, Center 24 (8 ~ 41) 34
1750 11:35:23.628664 iDelay=43, Bit 1, Center 23 (7 ~ 39) 33
1751 11:35:23.635278 iDelay=43, Bit 2, Center 23 (7 ~ 40) 34
1752 11:35:23.638802 iDelay=43, Bit 3, Center 17 (2 ~ 32) 31
1753 11:35:23.641888 iDelay=43, Bit 4, Center 23 (7 ~ 39) 33
1754 11:35:23.645439 iDelay=43, Bit 5, Center 20 (4 ~ 36) 33
1755 11:35:23.649284 iDelay=43, Bit 6, Center 20 (5 ~ 35) 31
1756 11:35:23.652040 iDelay=43, Bit 7, Center 21 (5 ~ 38) 34
1757 11:35:23.655889 iDelay=43, Bit 8, Center 17 (2 ~ 32) 31
1758 11:35:23.659212 iDelay=43, Bit 9, Center 20 (5 ~ 35) 31
1759 11:35:23.662229 iDelay=43, Bit 10, Center 26 (11 ~ 42) 32
1760 11:35:23.665851 iDelay=43, Bit 11, Center 19 (4 ~ 34) 31
1761 11:35:23.668595 iDelay=43, Bit 12, Center 21 (7 ~ 35) 29
1762 11:35:23.672139 iDelay=43, Bit 13, Center 21 (7 ~ 36) 30
1763 11:35:23.675690 iDelay=43, Bit 14, Center 22 (7 ~ 37) 31
1764 11:35:23.679185 iDelay=43, Bit 15, Center 24 (9 ~ 39) 31
1765 11:35:23.682413 ==
1766 11:35:23.685596 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1767 11:35:23.688527 fsp= 1, odt_onoff= 1, Byte mode= 0
1768 11:35:23.688604 ==
1769 11:35:23.688662 DQS Delay:
1770 11:35:23.692211 DQS0 = 0, DQS1 = 0
1771 11:35:23.692287 DQM Delay:
1772 11:35:23.695642 DQM0 = 21, DQM1 = 21
1773 11:35:23.695718 DQ Delay:
1774 11:35:23.699162 DQ0 =24, DQ1 =23, DQ2 =23, DQ3 =17
1775 11:35:23.702231 DQ4 =23, DQ5 =20, DQ6 =20, DQ7 =21
1776 11:35:23.705714 DQ8 =17, DQ9 =20, DQ10 =26, DQ11 =19
1777 11:35:23.709076 DQ12 =21, DQ13 =21, DQ14 =22, DQ15 =24
1778 11:35:23.709193
1779 11:35:23.709252
1780 11:35:23.712187 DramC Write-DBI off
1781 11:35:23.712263 ==
1782 11:35:23.715557 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1783 11:35:23.718777 fsp= 1, odt_onoff= 1, Byte mode= 0
1784 11:35:23.718855 ==
1785 11:35:23.722139 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1786 11:35:23.726291
1787 11:35:23.726368 Begin, DQ Scan Range 921~1177
1788 11:35:23.726427
1789 11:35:23.726481
1790 11:35:23.729030 TX Vref Scan disable
1791 11:35:23.732393 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1792 11:35:23.735898 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1793 11:35:23.739195 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1794 11:35:23.742662 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1795 11:35:23.745808 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1796 11:35:23.748789 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1797 11:35:23.752646 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1798 11:35:23.755728 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1799 11:35:23.762365 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1800 11:35:23.765596 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1801 11:35:23.768816 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1802 11:35:23.772108 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1803 11:35:23.775326 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1804 11:35:23.779345 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1805 11:35:23.782221 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1806 11:35:23.785467 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1807 11:35:23.788974 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1808 11:35:23.792141 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1809 11:35:23.795562 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1810 11:35:23.799058 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1811 11:35:23.802213 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1812 11:35:23.805651 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1813 11:35:23.808698 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1814 11:35:23.812217 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1815 11:35:23.815867 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1816 11:35:23.822135 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1817 11:35:23.826417 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1818 11:35:23.828841 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1819 11:35:23.832171 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1820 11:35:23.835882 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1821 11:35:23.839082 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1822 11:35:23.842162 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1823 11:35:23.845572 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1824 11:35:23.848815 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1825 11:35:23.852205 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1826 11:35:23.856087 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1827 11:35:23.859149 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1828 11:35:23.862391 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1829 11:35:23.865764 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1830 11:35:23.869366 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1831 11:35:23.872682 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1832 11:35:23.875651 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1833 11:35:23.878912 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1834 11:35:23.882456 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1835 11:35:23.885746 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1836 11:35:23.892230 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1837 11:35:23.896921 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1838 11:35:23.900444 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1839 11:35:23.902238 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1840 11:35:23.906189 970 |3 6 10|[0] xxxxxxxx oxxoxxxx [MSB]
1841 11:35:23.910285 971 |3 6 11|[0] xxxxxxxx ooxoxxxx [MSB]
1842 11:35:23.912413 972 |3 6 12|[0] xxxxxxxx ooxooxxx [MSB]
1843 11:35:23.915927 973 |3 6 13|[0] xxxxxxxx ooxoooxx [MSB]
1844 11:35:23.919383 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1845 11:35:23.922598 975 |3 6 15|[0] xxxxxxxx ooxoooox [MSB]
1846 11:35:23.925709 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1847 11:35:23.929419 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1848 11:35:23.933171 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1849 11:35:23.935913 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
1850 11:35:23.938947 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
1851 11:35:23.942573 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
1852 11:35:23.946094 982 |3 6 22|[0] xxxoooox oooooooo [MSB]
1853 11:35:23.948916 983 |3 6 23|[0] xxxoooox oooooooo [MSB]
1854 11:35:23.952615 984 |3 6 24|[0] xoxooooo oooooooo [MSB]
1855 11:35:23.959782 990 |3 6 30|[0] oooooooo xooxoooo [MSB]
1856 11:35:23.963416 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1857 11:35:23.966684 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1858 11:35:23.969930 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1859 11:35:23.973211 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1860 11:35:23.976849 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
1861 11:35:23.979987 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1862 11:35:23.983290 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
1863 11:35:23.987104 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
1864 11:35:23.989792 999 |3 6 39|[0] oooxoxoo xxxxxxxx [MSB]
1865 11:35:23.993257 1000 |3 6 40|[0] oooxoxoo xxxxxxxx [MSB]
1866 11:35:23.996837 1001 |3 6 41|[0] oooxoxxo xxxxxxxx [MSB]
1867 11:35:24.000057 1002 |3 6 42|[0] xxxxoxxx xxxxxxxx [MSB]
1868 11:35:24.003120 1003 |3 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
1869 11:35:24.006823 Byte0, DQ PI dly=990, DQM PI dly= 990
1870 11:35:24.013189 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
1871 11:35:24.013277
1872 11:35:24.017069 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
1873 11:35:24.017174
1874 11:35:24.020846 Byte1, DQ PI dly=981, DQM PI dly= 981
1875 11:35:24.024293 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1876 11:35:24.024372
1877 11:35:24.030789 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1878 11:35:24.030874
1879 11:35:24.030934 ==
1880 11:35:24.033727 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1881 11:35:24.037240 fsp= 1, odt_onoff= 1, Byte mode= 0
1882 11:35:24.037318 ==
1883 11:35:24.043414 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1884 11:35:24.043494
1885 11:35:24.043553 Begin, DQ Scan Range 957~1021
1886 11:35:24.046767 Write Rank1 MR14 =0x0
1887 11:35:24.055410
1888 11:35:24.055491 CH=0, VrefRange= 0, VrefLevel = 0
1889 11:35:24.062144 TX Bit0 (987~999) 13 993, Bit8 (972~984) 13 978,
1890 11:35:24.065592 TX Bit1 (986~997) 12 991, Bit9 (974~988) 15 981,
1891 11:35:24.072569 TX Bit2 (987~997) 11 992, Bit10 (980~992) 13 986,
1892 11:35:24.075880 TX Bit3 (981~990) 10 985, Bit11 (973~984) 12 978,
1893 11:35:24.079165 TX Bit4 (986~997) 12 991, Bit12 (975~988) 14 981,
1894 11:35:24.085998 TX Bit5 (984~994) 11 989, Bit13 (976~988) 13 982,
1895 11:35:24.089770 TX Bit6 (983~995) 13 989, Bit14 (976~989) 14 982,
1896 11:35:24.092319 TX Bit7 (987~995) 9 991, Bit15 (980~991) 12 985,
1897 11:35:24.092396
1898 11:35:24.095543 Write Rank1 MR14 =0x2
1899 11:35:24.104316
1900 11:35:24.104394 CH=0, VrefRange= 0, VrefLevel = 2
1901 11:35:24.111253 TX Bit0 (987~1000) 14 993, Bit8 (972~985) 14 978,
1902 11:35:24.114731 TX Bit1 (985~998) 14 991, Bit9 (974~989) 16 981,
1903 11:35:24.121042 TX Bit2 (986~999) 14 992, Bit10 (979~993) 15 986,
1904 11:35:24.124811 TX Bit3 (980~992) 13 986, Bit11 (973~984) 12 978,
1905 11:35:24.128594 TX Bit4 (985~998) 14 991, Bit12 (975~988) 14 981,
1906 11:35:24.135820 TX Bit5 (983~994) 12 988, Bit13 (975~989) 15 982,
1907 11:35:24.137722 TX Bit6 (983~996) 14 989, Bit14 (975~990) 16 982,
1908 11:35:24.141252 TX Bit7 (986~996) 11 991, Bit15 (979~992) 14 985,
1909 11:35:24.141329
1910 11:35:24.144239 Write Rank1 MR14 =0x4
1911 11:35:24.153250
1912 11:35:24.153329 CH=0, VrefRange= 0, VrefLevel = 4
1913 11:35:24.160384 TX Bit0 (986~1001) 16 993, Bit8 (971~985) 15 978,
1914 11:35:24.164228 TX Bit1 (986~999) 14 992, Bit9 (974~989) 16 981,
1915 11:35:24.170773 TX Bit2 (986~999) 14 992, Bit10 (978~994) 17 986,
1916 11:35:24.173508 TX Bit3 (981~992) 12 986, Bit11 (973~985) 13 979,
1917 11:35:24.176811 TX Bit4 (985~999) 15 992, Bit12 (974~989) 16 981,
1918 11:35:24.183228 TX Bit5 (982~995) 14 988, Bit13 (975~989) 15 982,
1919 11:35:24.187301 TX Bit6 (983~996) 14 989, Bit14 (975~990) 16 982,
1920 11:35:24.190017 TX Bit7 (986~996) 11 991, Bit15 (978~993) 16 985,
1921 11:35:24.190096
1922 11:35:24.193774 Write Rank1 MR14 =0x6
1923 11:35:24.202875
1924 11:35:24.202957 CH=0, VrefRange= 0, VrefLevel = 6
1925 11:35:24.209101 TX Bit0 (986~1001) 16 993, Bit8 (971~986) 16 978,
1926 11:35:24.212227 TX Bit1 (986~999) 14 992, Bit9 (973~989) 17 981,
1927 11:35:24.219060 TX Bit2 (986~1000) 15 993, Bit10 (978~995) 18 986,
1928 11:35:24.222194 TX Bit3 (980~993) 14 986, Bit11 (972~986) 15 979,
1929 11:35:24.226124 TX Bit4 (984~1000) 17 992, Bit12 (974~989) 16 981,
1930 11:35:24.232609 TX Bit5 (982~995) 14 988, Bit13 (974~989) 16 981,
1931 11:35:24.235793 TX Bit6 (982~997) 16 989, Bit14 (975~991) 17 983,
1932 11:35:24.238942 TX Bit7 (986~997) 12 991, Bit15 (978~994) 17 986,
1933 11:35:24.239019
1934 11:35:24.242360 Write Rank1 MR14 =0x8
1935 11:35:24.251896
1936 11:35:24.251977 CH=0, VrefRange= 0, VrefLevel = 8
1937 11:35:24.258585 TX Bit0 (986~1002) 17 994, Bit8 (970~986) 17 978,
1938 11:35:24.262279 TX Bit1 (985~1000) 16 992, Bit9 (972~990) 19 981,
1939 11:35:24.268938 TX Bit2 (986~1001) 16 993, Bit10 (978~995) 18 986,
1940 11:35:24.271928 TX Bit3 (980~993) 14 986, Bit11 (972~987) 16 979,
1941 11:35:24.275662 TX Bit4 (984~1000) 17 992, Bit12 (974~989) 16 981,
1942 11:35:24.282458 TX Bit5 (981~996) 16 988, Bit13 (974~989) 16 981,
1943 11:35:24.284857 TX Bit6 (982~998) 17 990, Bit14 (975~992) 18 983,
1944 11:35:24.288500 TX Bit7 (986~998) 13 992, Bit15 (977~994) 18 985,
1945 11:35:24.291843
1946 11:35:24.291920 Write Rank1 MR14 =0xa
1947 11:35:24.301661
1948 11:35:24.304964 CH=0, VrefRange= 0, VrefLevel = 10
1949 11:35:24.308016 TX Bit0 (986~1003) 18 994, Bit8 (970~987) 18 978,
1950 11:35:24.311873 TX Bit1 (984~1000) 17 992, Bit9 (973~990) 18 981,
1951 11:35:24.318041 TX Bit2 (986~1002) 17 994, Bit10 (977~996) 20 986,
1952 11:35:24.321622 TX Bit3 (980~994) 15 987, Bit11 (971~988) 18 979,
1953 11:35:24.324681 TX Bit4 (983~1001) 19 992, Bit12 (974~990) 17 982,
1954 11:35:24.331112 TX Bit5 (981~996) 16 988, Bit13 (974~990) 17 982,
1955 11:35:24.334931 TX Bit6 (981~998) 18 989, Bit14 (975~992) 18 983,
1956 11:35:24.338529 TX Bit7 (985~998) 14 991, Bit15 (978~995) 18 986,
1957 11:35:24.341218
1958 11:35:24.341292 Write Rank1 MR14 =0xc
1959 11:35:24.350986
1960 11:35:24.354125 CH=0, VrefRange= 0, VrefLevel = 12
1961 11:35:24.358239 TX Bit0 (986~1003) 18 994, Bit8 (969~989) 21 979,
1962 11:35:24.360765 TX Bit1 (985~1001) 17 993, Bit9 (973~991) 19 982,
1963 11:35:24.368453 TX Bit2 (985~1002) 18 993, Bit10 (977~996) 20 986,
1964 11:35:24.370962 TX Bit3 (979~994) 16 986, Bit11 (971~988) 18 979,
1965 11:35:24.374785 TX Bit4 (983~1001) 19 992, Bit12 (973~990) 18 981,
1966 11:35:24.381125 TX Bit5 (981~997) 17 989, Bit13 (973~991) 19 982,
1967 11:35:24.384222 TX Bit6 (981~999) 19 990, Bit14 (974~993) 20 983,
1968 11:35:24.387939 TX Bit7 (984~999) 16 991, Bit15 (977~996) 20 986,
1969 11:35:24.390858
1970 11:35:24.390933 Write Rank1 MR14 =0xe
1971 11:35:24.400596
1972 11:35:24.404140 CH=0, VrefRange= 0, VrefLevel = 14
1973 11:35:24.407982 TX Bit0 (985~1004) 20 994, Bit8 (970~989) 20 979,
1974 11:35:24.410860 TX Bit1 (984~1002) 19 993, Bit9 (971~991) 21 981,
1975 11:35:24.417627 TX Bit2 (985~1003) 19 994, Bit10 (977~997) 21 987,
1976 11:35:24.420749 TX Bit3 (979~994) 16 986, Bit11 (970~988) 19 979,
1977 11:35:24.424464 TX Bit4 (983~1002) 20 992, Bit12 (973~991) 19 982,
1978 11:35:24.430875 TX Bit5 (981~997) 17 989, Bit13 (973~991) 19 982,
1979 11:35:24.434358 TX Bit6 (981~999) 19 990, Bit14 (974~993) 20 983,
1980 11:35:24.440893 TX Bit7 (984~1001) 18 992, Bit15 (977~996) 20 986,
1981 11:35:24.440970
1982 11:35:24.441045 Write Rank1 MR14 =0x10
1983 11:35:24.450971
1984 11:35:24.454149 CH=0, VrefRange= 0, VrefLevel = 16
1985 11:35:24.457745 TX Bit0 (985~1004) 20 994, Bit8 (969~989) 21 979,
1986 11:35:24.460793 TX Bit1 (984~1002) 19 993, Bit9 (971~992) 22 981,
1987 11:35:24.467188 TX Bit2 (985~1004) 20 994, Bit10 (977~997) 21 987,
1988 11:35:24.470998 TX Bit3 (979~995) 17 987, Bit11 (970~989) 20 979,
1989 11:35:24.474571 TX Bit4 (982~1002) 21 992, Bit12 (972~991) 20 981,
1990 11:35:24.480727 TX Bit5 (980~998) 19 989, Bit13 (973~992) 20 982,
1991 11:35:24.484206 TX Bit6 (980~1000) 21 990, Bit14 (973~994) 22 983,
1992 11:35:24.491127 TX Bit7 (984~1001) 18 992, Bit15 (976~996) 21 986,
1993 11:35:24.491205
1994 11:35:24.491263 Write Rank1 MR14 =0x12
1995 11:35:24.500962
1996 11:35:24.504490 CH=0, VrefRange= 0, VrefLevel = 18
1997 11:35:24.507478 TX Bit0 (985~1005) 21 995, Bit8 (969~990) 22 979,
1998 11:35:24.511231 TX Bit1 (983~1003) 21 993, Bit9 (970~992) 23 981,
1999 11:35:24.518260 TX Bit2 (985~1004) 20 994, Bit10 (976~997) 22 986,
2000 11:35:24.521303 TX Bit3 (979~995) 17 987, Bit11 (970~990) 21 980,
2001 11:35:24.524385 TX Bit4 (982~1003) 22 992, Bit12 (972~992) 21 982,
2002 11:35:24.531387 TX Bit5 (980~998) 19 989, Bit13 (972~992) 21 982,
2003 11:35:24.534271 TX Bit6 (980~1001) 22 990, Bit14 (973~994) 22 983,
2004 11:35:24.541479 TX Bit7 (983~1001) 19 992, Bit15 (976~997) 22 986,
2005 11:35:24.541563
2006 11:35:24.541654 Write Rank1 MR14 =0x14
2007 11:35:24.551638
2008 11:35:24.554958 CH=0, VrefRange= 0, VrefLevel = 20
2009 11:35:24.558609 TX Bit0 (985~1006) 22 995, Bit8 (969~990) 22 979,
2010 11:35:24.562199 TX Bit1 (983~1004) 22 993, Bit9 (971~993) 23 982,
2011 11:35:24.568001 TX Bit2 (984~1005) 22 994, Bit10 (976~997) 22 986,
2012 11:35:24.571544 TX Bit3 (979~996) 18 987, Bit11 (969~990) 22 979,
2013 11:35:24.574933 TX Bit4 (982~1004) 23 993, Bit12 (972~993) 22 982,
2014 11:35:24.581517 TX Bit5 (980~999) 20 989, Bit13 (972~993) 22 982,
2015 11:35:24.584670 TX Bit6 (980~1001) 22 990, Bit14 (972~995) 24 983,
2016 11:35:24.591323 TX Bit7 (983~1002) 20 992, Bit15 (976~997) 22 986,
2017 11:35:24.591402
2018 11:35:24.591462 Write Rank1 MR14 =0x16
2019 11:35:24.602183
2020 11:35:24.605083 CH=0, VrefRange= 0, VrefLevel = 22
2021 11:35:24.608381 TX Bit0 (984~1006) 23 995, Bit8 (968~991) 24 979,
2022 11:35:24.611739 TX Bit1 (982~1004) 23 993, Bit9 (970~994) 25 982,
2023 11:35:24.618535 TX Bit2 (984~1005) 22 994, Bit10 (975~997) 23 986,
2024 11:35:24.622105 TX Bit3 (979~996) 18 987, Bit11 (969~990) 22 979,
2025 11:35:24.625017 TX Bit4 (981~1004) 24 992, Bit12 (971~993) 23 982,
2026 11:35:24.631933 TX Bit5 (980~1000) 21 990, Bit13 (971~994) 24 982,
2027 11:35:24.635281 TX Bit6 (980~1002) 23 991, Bit14 (972~995) 24 983,
2028 11:35:24.641963 TX Bit7 (983~1002) 20 992, Bit15 (976~997) 22 986,
2029 11:35:24.642041
2030 11:35:24.642100 Write Rank1 MR14 =0x18
2031 11:35:24.652929
2032 11:35:24.655910 CH=0, VrefRange= 0, VrefLevel = 24
2033 11:35:24.659757 TX Bit0 (984~1007) 24 995, Bit8 (968~991) 24 979,
2034 11:35:24.662812 TX Bit1 (982~1005) 24 993, Bit9 (970~994) 25 982,
2035 11:35:24.669321 TX Bit2 (984~1006) 23 995, Bit10 (975~998) 24 986,
2036 11:35:24.672981 TX Bit3 (978~996) 19 987, Bit11 (969~991) 23 980,
2037 11:35:24.675992 TX Bit4 (981~1005) 25 993, Bit12 (971~994) 24 982,
2038 11:35:24.682607 TX Bit5 (980~1000) 21 990, Bit13 (971~994) 24 982,
2039 11:35:24.685610 TX Bit6 (980~1003) 24 991, Bit14 (971~996) 26 983,
2040 11:35:24.692410 TX Bit7 (982~1003) 22 992, Bit15 (976~997) 22 986,
2041 11:35:24.692487
2042 11:35:24.692545 Write Rank1 MR14 =0x1a
2043 11:35:24.703573
2044 11:35:24.706869 CH=0, VrefRange= 0, VrefLevel = 26
2045 11:35:24.710332 TX Bit0 (983~1008) 26 995, Bit8 (968~992) 25 980,
2046 11:35:24.713671 TX Bit1 (982~1005) 24 993, Bit9 (970~994) 25 982,
2047 11:35:24.720239 TX Bit2 (983~1007) 25 995, Bit10 (975~998) 24 986,
2048 11:35:24.723403 TX Bit3 (978~997) 20 987, Bit11 (969~991) 23 980,
2049 11:35:24.726901 TX Bit4 (981~1005) 25 993, Bit12 (970~994) 25 982,
2050 11:35:24.733417 TX Bit5 (979~1001) 23 990, Bit13 (970~995) 26 982,
2051 11:35:24.736753 TX Bit6 (980~1003) 24 991, Bit14 (971~996) 26 983,
2052 11:35:24.743199 TX Bit7 (982~1005) 24 993, Bit15 (975~997) 23 986,
2053 11:35:24.743277
2054 11:35:24.743336 Write Rank1 MR14 =0x1c
2055 11:35:24.754345
2056 11:35:24.757538 CH=0, VrefRange= 0, VrefLevel = 28
2057 11:35:24.761074 TX Bit0 (984~1008) 25 996, Bit8 (968~992) 25 980,
2058 11:35:24.764927 TX Bit1 (981~1006) 26 993, Bit9 (970~994) 25 982,
2059 11:35:24.770865 TX Bit2 (983~1007) 25 995, Bit10 (975~998) 24 986,
2060 11:35:24.774271 TX Bit3 (978~997) 20 987, Bit11 (969~992) 24 980,
2061 11:35:24.778212 TX Bit4 (981~1006) 26 993, Bit12 (970~995) 26 982,
2062 11:35:24.784242 TX Bit5 (979~1002) 24 990, Bit13 (970~994) 25 982,
2063 11:35:24.787513 TX Bit6 (980~1004) 25 992, Bit14 (970~996) 27 983,
2064 11:35:24.794422 TX Bit7 (982~1004) 23 993, Bit15 (975~998) 24 986,
2065 11:35:24.794499
2066 11:35:24.794558 Write Rank1 MR14 =0x1e
2067 11:35:24.804881
2068 11:35:24.808434 CH=0, VrefRange= 0, VrefLevel = 30
2069 11:35:24.811855 TX Bit0 (984~1008) 25 996, Bit8 (968~991) 24 979,
2070 11:35:24.814879 TX Bit1 (981~1005) 25 993, Bit9 (970~994) 25 982,
2071 11:35:24.822518 TX Bit2 (983~1007) 25 995, Bit10 (975~998) 24 986,
2072 11:35:24.825065 TX Bit3 (978~999) 22 988, Bit11 (969~992) 24 980,
2073 11:35:24.828604 TX Bit4 (982~1006) 25 994, Bit12 (970~995) 26 982,
2074 11:35:24.835270 TX Bit5 (979~1002) 24 990, Bit13 (970~994) 25 982,
2075 11:35:24.838554 TX Bit6 (980~1003) 24 991, Bit14 (970~996) 27 983,
2076 11:35:24.845435 TX Bit7 (982~1005) 24 993, Bit15 (974~998) 25 986,
2077 11:35:24.845511
2078 11:35:24.845571 Write Rank1 MR14 =0x20
2079 11:35:24.855655
2080 11:35:24.859002 CH=0, VrefRange= 0, VrefLevel = 32
2081 11:35:24.862366 TX Bit0 (984~1008) 25 996, Bit8 (968~991) 24 979,
2082 11:35:24.865548 TX Bit1 (981~1005) 25 993, Bit9 (970~994) 25 982,
2083 11:35:24.872191 TX Bit2 (983~1007) 25 995, Bit10 (975~998) 24 986,
2084 11:35:24.875785 TX Bit3 (978~999) 22 988, Bit11 (969~992) 24 980,
2085 11:35:24.879155 TX Bit4 (982~1006) 25 994, Bit12 (970~995) 26 982,
2086 11:35:24.885853 TX Bit5 (979~1002) 24 990, Bit13 (970~994) 25 982,
2087 11:35:24.888928 TX Bit6 (980~1003) 24 991, Bit14 (970~996) 27 983,
2088 11:35:24.895561 TX Bit7 (982~1005) 24 993, Bit15 (974~998) 25 986,
2089 11:35:24.895638
2090 11:35:24.895698 Write Rank1 MR14 =0x22
2091 11:35:24.906377
2092 11:35:24.909748 CH=0, VrefRange= 0, VrefLevel = 34
2093 11:35:24.913242 TX Bit0 (984~1008) 25 996, Bit8 (968~991) 24 979,
2094 11:35:24.916305 TX Bit1 (981~1005) 25 993, Bit9 (970~994) 25 982,
2095 11:35:24.923340 TX Bit2 (983~1007) 25 995, Bit10 (975~998) 24 986,
2096 11:35:24.926643 TX Bit3 (978~999) 22 988, Bit11 (969~992) 24 980,
2097 11:35:24.930369 TX Bit4 (982~1006) 25 994, Bit12 (970~995) 26 982,
2098 11:35:24.936489 TX Bit5 (979~1002) 24 990, Bit13 (970~994) 25 982,
2099 11:35:24.940087 TX Bit6 (980~1003) 24 991, Bit14 (970~996) 27 983,
2100 11:35:24.946501 TX Bit7 (982~1005) 24 993, Bit15 (974~998) 25 986,
2101 11:35:24.946580
2102 11:35:24.946639
2103 11:35:24.950192 TX Vref found, early break! 372< 374
2104 11:35:24.953738 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
2105 11:35:24.956733 u1DelayCellOfst[0]=9 cells (8 PI)
2106 11:35:24.959721 u1DelayCellOfst[1]=5 cells (5 PI)
2107 11:35:24.963956 u1DelayCellOfst[2]=8 cells (7 PI)
2108 11:35:24.966702 u1DelayCellOfst[3]=0 cells (0 PI)
2109 11:35:24.969781 u1DelayCellOfst[4]=7 cells (6 PI)
2110 11:35:24.969857 u1DelayCellOfst[5]=2 cells (2 PI)
2111 11:35:24.973059 u1DelayCellOfst[6]=3 cells (3 PI)
2112 11:35:24.976431 u1DelayCellOfst[7]=5 cells (5 PI)
2113 11:35:24.979814 Byte0, DQ PI dly=988, DQM PI dly= 992
2114 11:35:24.986888 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2115 11:35:24.986968
2116 11:35:24.991140 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2117 11:35:24.991217
2118 11:35:24.993395 u1DelayCellOfst[8]=0 cells (0 PI)
2119 11:35:24.996664 u1DelayCellOfst[9]=3 cells (3 PI)
2120 11:35:25.000439 u1DelayCellOfst[10]=8 cells (7 PI)
2121 11:35:25.003315 u1DelayCellOfst[11]=1 cells (1 PI)
2122 11:35:25.003391 u1DelayCellOfst[12]=3 cells (3 PI)
2123 11:35:25.007319 u1DelayCellOfst[13]=3 cells (3 PI)
2124 11:35:25.010812 u1DelayCellOfst[14]=4 cells (4 PI)
2125 11:35:25.013626 u1DelayCellOfst[15]=8 cells (7 PI)
2126 11:35:25.017131 Byte1, DQ PI dly=979, DQM PI dly= 982
2127 11:35:25.023221 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2128 11:35:25.023300
2129 11:35:25.026760 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2130 11:35:25.026837
2131 11:35:25.029898 Write Rank1 MR14 =0x1e
2132 11:35:25.029973
2133 11:35:25.030031 Final TX Range 0 Vref 30
2134 11:35:25.030086
2135 11:35:25.036652 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2136 11:35:25.036730
2137 11:35:25.043548 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2138 11:35:25.049967 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2139 11:35:25.060010 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2140 11:35:25.060089 Write Rank1 MR3 =0xb0
2141 11:35:25.063440 DramC Write-DBI on
2142 11:35:25.063516 ==
2143 11:35:25.067475 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2144 11:35:25.069943 fsp= 1, odt_onoff= 1, Byte mode= 0
2145 11:35:25.070019 ==
2146 11:35:25.077081 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2147 11:35:25.077197
2148 11:35:25.077256 Begin, DQ Scan Range 702~766
2149 11:35:25.077311
2150 11:35:25.077361
2151 11:35:25.079929 TX Vref Scan disable
2152 11:35:25.083349 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2153 11:35:25.086352 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2154 11:35:25.089642 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2155 11:35:25.093125 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2156 11:35:25.096504 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2157 11:35:25.099733 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2158 11:35:25.103935 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2159 11:35:25.106786 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2160 11:35:25.109874 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2161 11:35:25.113880 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2162 11:35:25.120006 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2163 11:35:25.123463 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2164 11:35:25.126386 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2165 11:35:25.129927 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2166 11:35:25.133329 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2167 11:35:25.136559 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2168 11:35:25.140250 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2169 11:35:25.143530 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2170 11:35:25.146687 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2171 11:35:25.150169 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2172 11:35:25.154148 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2173 11:35:25.156628 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
2174 11:35:25.160183 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
2175 11:35:25.168337 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2176 11:35:25.172018 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2177 11:35:25.174816 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2178 11:35:25.178026 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2179 11:35:25.181425 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2180 11:35:25.184711 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2181 11:35:25.188266 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2182 11:35:25.191421 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2183 11:35:25.194622 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2184 11:35:25.198144 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2185 11:35:25.202000 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
2186 11:35:25.204669 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
2187 11:35:25.207863 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
2188 11:35:25.211692 Byte0, DQ PI dly=738, DQM PI dly= 738
2189 11:35:25.218396 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 34)
2190 11:35:25.218475
2191 11:35:25.221541 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 34)
2192 11:35:25.221618
2193 11:35:25.224800 Byte1, DQ PI dly=727, DQM PI dly= 727
2194 11:35:25.228344 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 23)
2195 11:35:25.228419
2196 11:35:25.235420 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 23)
2197 11:35:25.235497
2198 11:35:25.242091 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2199 11:35:25.248252 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2200 11:35:25.255846 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2201 11:35:25.255925 Write Rank1 MR3 =0x30
2202 11:35:25.258431 DramC Write-DBI off
2203 11:35:25.258505
2204 11:35:25.258563 [DATLAT]
2205 11:35:25.261363 Freq=1600, CH0 RK1, use_rxtx_scan=0
2206 11:35:25.261438
2207 11:35:25.264717 DATLAT Default: 0x10
2208 11:35:25.264792 7, 0xFFFF, sum=0
2209 11:35:25.268333 8, 0xFFFF, sum=0
2210 11:35:25.268409 9, 0xFFFF, sum=0
2211 11:35:25.271904 10, 0xFFFF, sum=0
2212 11:35:25.271980 11, 0xFFFF, sum=0
2213 11:35:25.275197 12, 0xFFFF, sum=0
2214 11:35:25.275280 13, 0xFFFF, sum=0
2215 11:35:25.278225 14, 0x0, sum=1
2216 11:35:25.278302 15, 0x0, sum=2
2217 11:35:25.278362 16, 0x0, sum=3
2218 11:35:25.282222 17, 0x0, sum=4
2219 11:35:25.286872 pattern=2 first_step=14 total pass=5 best_step=16
2220 11:35:25.286969 ==
2221 11:35:25.290341 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2222 11:35:25.293771 fsp= 1, odt_onoff= 1, Byte mode= 0
2223 11:35:25.293846 ==
2224 11:35:25.297396 Start DQ dly to find pass range UseTestEngine =1
2225 11:35:25.300272 x-axis: bit #, y-axis: DQ dly (-127~63)
2226 11:35:25.303494 RX Vref Scan = 0
2227 11:35:25.307585 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2228 11:35:25.310024 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2229 11:35:25.313655 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2230 11:35:25.313733 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2231 11:35:25.316767 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2232 11:35:25.320014 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2233 11:35:25.323461 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2234 11:35:25.326950 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2235 11:35:25.330140 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2236 11:35:25.333492 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2237 11:35:25.336828 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2238 11:35:25.336946 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2239 11:35:25.340111 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2240 11:35:25.343596 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2241 11:35:25.346980 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2242 11:35:25.350222 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2243 11:35:25.353698 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2244 11:35:25.356714 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2245 11:35:25.360027 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2246 11:35:25.360105 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2247 11:35:25.363460 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2248 11:35:25.367317 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2249 11:35:25.372284 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2250 11:35:25.372370 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2251 11:35:25.376622 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2252 11:35:25.380909 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2253 11:35:25.381011 0, [0] xxxxxxxx xxxxxxxx [MSB]
2254 11:35:25.384966 1, [0] xxxoxxxx xxxxxxxx [MSB]
2255 11:35:25.388446 2, [0] xxxoxxxx oxxxxxxx [MSB]
2256 11:35:25.388524 3, [0] xxxoxoxx oxxoxxxx [MSB]
2257 11:35:25.392324 4, [0] xxxoxoox oxxoxxxx [MSB]
2258 11:35:25.395904 5, [0] xxxoxoox ooxoxxxx [MSB]
2259 11:35:25.398716 6, [0] xxxoxoox ooxooxxx [MSB]
2260 11:35:25.401353 7, [0] xoxoxooo ooxoooox [MSB]
2261 11:35:25.404830 8, [0] xoxoxooo ooxoooox [MSB]
2262 11:35:25.404924 9, [0] oooooooo ooxoooox [MSB]
2263 11:35:25.408273 10, [0] oooooooo ooxooooo [MSB]
2264 11:35:25.411457 11, [0] oooooooo ooxooooo [MSB]
2265 11:35:25.415716 33, [0] oooxoooo xooxoooo [MSB]
2266 11:35:25.418884 34, [0] oooxoooo xooxoooo [MSB]
2267 11:35:25.422489 35, [0] oooxoxoo xxoxoxoo [MSB]
2268 11:35:25.426189 36, [0] oooxoxxo xxoxxxoo [MSB]
2269 11:35:25.429085 37, [0] oooxoxxo xxoxxxoo [MSB]
2270 11:35:25.432413 38, [0] oooxxxxx xxoxxxxo [MSB]
2271 11:35:25.432491 39, [0] oooxxxxx xxoxxxxx [MSB]
2272 11:35:25.435673 40, [0] xxxxxxxx xxoxxxxx [MSB]
2273 11:35:25.438950 41, [0] xxxxxxxx xxoxxxxx [MSB]
2274 11:35:25.442704 42, [0] xxxxxxxx xxxxxxxx [MSB]
2275 11:35:25.445552 iDelay=42, Bit 0, Center 24 (9 ~ 39) 31
2276 11:35:25.449031 iDelay=42, Bit 1, Center 23 (7 ~ 39) 33
2277 11:35:25.453762 iDelay=42, Bit 2, Center 24 (9 ~ 39) 31
2278 11:35:25.457533 iDelay=42, Bit 3, Center 16 (1 ~ 32) 32
2279 11:35:25.460989 iDelay=42, Bit 4, Center 23 (9 ~ 37) 29
2280 11:35:25.464398 iDelay=42, Bit 5, Center 18 (3 ~ 34) 32
2281 11:35:25.467275 iDelay=42, Bit 6, Center 19 (4 ~ 35) 32
2282 11:35:25.471466 iDelay=42, Bit 7, Center 22 (7 ~ 37) 31
2283 11:35:25.474441 iDelay=42, Bit 8, Center 17 (2 ~ 32) 31
2284 11:35:25.478248 iDelay=42, Bit 9, Center 19 (5 ~ 34) 30
2285 11:35:25.481269 iDelay=42, Bit 10, Center 26 (12 ~ 41) 30
2286 11:35:25.484332 iDelay=42, Bit 11, Center 17 (3 ~ 32) 30
2287 11:35:25.488287 iDelay=42, Bit 12, Center 20 (6 ~ 35) 30
2288 11:35:25.491376 iDelay=42, Bit 13, Center 20 (7 ~ 34) 28
2289 11:35:25.494791 iDelay=42, Bit 14, Center 22 (7 ~ 37) 31
2290 11:35:25.498584 iDelay=42, Bit 15, Center 24 (10 ~ 38) 29
2291 11:35:25.501330 ==
2292 11:35:25.504397 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2293 11:35:25.507734 fsp= 1, odt_onoff= 1, Byte mode= 0
2294 11:35:25.507819 ==
2295 11:35:25.507881 DQS Delay:
2296 11:35:25.511234 DQS0 = 0, DQS1 = 0
2297 11:35:25.511357 DQM Delay:
2298 11:35:25.514806 DQM0 = 21, DQM1 = 20
2299 11:35:25.514925 DQ Delay:
2300 11:35:25.517926 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =16
2301 11:35:25.521855 DQ4 =23, DQ5 =18, DQ6 =19, DQ7 =22
2302 11:35:25.525426 DQ8 =17, DQ9 =19, DQ10 =26, DQ11 =17
2303 11:35:25.528142 DQ12 =20, DQ13 =20, DQ14 =22, DQ15 =24
2304 11:35:25.528254
2305 11:35:25.528316
2306 11:35:25.528370
2307 11:35:25.531211 [DramC_TX_OE_Calibration] TA2
2308 11:35:25.535040 Original DQ_B0 (3 6) =30, OEN = 27
2309 11:35:25.538800 Original DQ_B1 (3 6) =30, OEN = 27
2310 11:35:25.538888 23, 0x0, End_B0=23 End_B1=23
2311 11:35:25.541943 24, 0x0, End_B0=24 End_B1=24
2312 11:35:25.545037 25, 0x0, End_B0=25 End_B1=25
2313 11:35:25.548762 26, 0x0, End_B0=26 End_B1=26
2314 11:35:25.548840 27, 0x0, End_B0=27 End_B1=27
2315 11:35:25.551770 28, 0x0, End_B0=28 End_B1=28
2316 11:35:25.555211 29, 0x0, End_B0=29 End_B1=29
2317 11:35:25.558694 30, 0x0, End_B0=30 End_B1=30
2318 11:35:25.561945 31, 0xFFFF, End_B0=30 End_B1=30
2319 11:35:25.565324 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2320 11:35:25.572554 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2321 11:35:25.572632
2322 11:35:25.572690
2323 11:35:25.575242 Write Rank1 MR23 =0x3f
2324 11:35:25.575350 [DQSOSC]
2325 11:35:25.581934 [DQSOSCAuto] RK1, (LSB)MR18= 0xb8b8, (MSB)MR19= 0x202, tDQSOscB0 = 452 ps tDQSOscB1 = 452 ps
2326 11:35:25.589073 CH0_RK1: MR19=0x202, MR18=0xB8B8, DQSOSC=452, MR23=63, INC=12, DEC=18
2327 11:35:25.591936 Write Rank1 MR23 =0x3f
2328 11:35:25.592012 [DQSOSC]
2329 11:35:25.598517 [DQSOSCAuto] RK1, (LSB)MR18= 0xb9b9, (MSB)MR19= 0x202, tDQSOscB0 = 451 ps tDQSOscB1 = 451 ps
2330 11:35:25.602505 CH0 RK1: MR19=202, MR18=B9B9
2331 11:35:25.605014 [RxdqsGatingPostProcess] freq 1600
2332 11:35:25.611645 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2333 11:35:25.611723 Rank: 0
2334 11:35:25.614922 best DQS0 dly(2T, 0.5T) = (2, 6)
2335 11:35:25.618533 best DQS1 dly(2T, 0.5T) = (2, 6)
2336 11:35:25.621974 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2337 11:35:25.624966 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2338 11:35:25.625084 Rank: 1
2339 11:35:25.628552 best DQS0 dly(2T, 0.5T) = (2, 6)
2340 11:35:25.631890 best DQS1 dly(2T, 0.5T) = (2, 6)
2341 11:35:25.635328 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2342 11:35:25.638209 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2343 11:35:25.642153 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2344 11:35:25.645412 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2345 11:35:25.648538 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2346 11:35:25.652659 Write Rank0 MR13 =0x59
2347 11:35:25.652757 ==
2348 11:35:25.659307 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2349 11:35:25.661929 fsp= 1, odt_onoff= 1, Byte mode= 0
2350 11:35:25.662026 ==
2351 11:35:25.665148 === u2Vref_new: 0x56 --> 0x3a
2352 11:35:25.665263 === u2Vref_new: 0x58 --> 0x58
2353 11:35:25.669181 === u2Vref_new: 0x5a --> 0x5a
2354 11:35:25.672442 === u2Vref_new: 0x5c --> 0x78
2355 11:35:25.675469 === u2Vref_new: 0x5e --> 0x7a
2356 11:35:25.678852 === u2Vref_new: 0x60 --> 0x90
2357 11:35:25.682365 [CA 0] Center 38 (13~63) winsize 51
2358 11:35:25.685460 [CA 1] Center 37 (12~63) winsize 52
2359 11:35:25.688642 [CA 2] Center 35 (7~63) winsize 57
2360 11:35:25.692513 [CA 3] Center 34 (6~63) winsize 58
2361 11:35:25.696359 [CA 4] Center 34 (6~63) winsize 58
2362 11:35:25.699350 [CA 5] Center 29 (0~58) winsize 59
2363 11:35:25.699427
2364 11:35:25.702089 [CATrainingPosCal] consider 1 rank data
2365 11:35:25.705705 u2DelayCellTimex100 = 833/100 ps
2366 11:35:25.709337 CA0 delay=38 (13~63),Diff = 9 PI (10 cell)
2367 11:35:25.712187 CA1 delay=37 (12~63),Diff = 8 PI (9 cell)
2368 11:35:25.715655 CA2 delay=35 (7~63),Diff = 6 PI (7 cell)
2369 11:35:25.718831 CA3 delay=34 (6~63),Diff = 5 PI (5 cell)
2370 11:35:25.722139 CA4 delay=34 (6~63),Diff = 5 PI (5 cell)
2371 11:35:25.725755 CA5 delay=29 (0~58),Diff = 0 PI (0 cell)
2372 11:35:25.725832
2373 11:35:25.732339 CA PerBit enable=1, Macro0, CA PI delay=29
2374 11:35:25.732416 === u2Vref_new: 0x60 --> 0x90
2375 11:35:25.732475
2376 11:35:25.735496 Vref(ca) range 1: 32
2377 11:35:25.735572
2378 11:35:25.739273 CS Dly= 11 (42-0-32)
2379 11:35:25.739349 Write Rank0 MR13 =0xd8
2380 11:35:25.742273 Write Rank0 MR13 =0xd8
2381 11:35:25.742348 Write Rank0 MR12 =0x60
2382 11:35:25.746284 Write Rank1 MR13 =0x59
2383 11:35:25.746360 ==
2384 11:35:25.752683 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2385 11:35:25.755841 fsp= 1, odt_onoff= 1, Byte mode= 0
2386 11:35:25.755917 ==
2387 11:35:25.759046 === u2Vref_new: 0x56 --> 0x3a
2388 11:35:25.759123 === u2Vref_new: 0x58 --> 0x58
2389 11:35:25.762698 === u2Vref_new: 0x5a --> 0x5a
2390 11:35:25.765936 === u2Vref_new: 0x5c --> 0x78
2391 11:35:25.769555 === u2Vref_new: 0x5e --> 0x7a
2392 11:35:25.773366 === u2Vref_new: 0x60 --> 0x90
2393 11:35:25.776528 [CA 0] Center 36 (10~63) winsize 54
2394 11:35:25.779451 [CA 1] Center 37 (11~63) winsize 53
2395 11:35:25.782641 [CA 2] Center 34 (6~63) winsize 58
2396 11:35:25.786077 [CA 3] Center 34 (6~63) winsize 58
2397 11:35:25.789629 [CA 4] Center 34 (6~63) winsize 58
2398 11:35:25.794676 [CA 5] Center 28 (-1~57) winsize 59
2399 11:35:25.794750
2400 11:35:25.796892 [CATrainingPosCal] consider 2 rank data
2401 11:35:25.799283 u2DelayCellTimex100 = 833/100 ps
2402 11:35:25.803007 CA0 delay=38 (13~63),Diff = 10 PI (11 cell)
2403 11:35:25.806593 CA1 delay=37 (12~63),Diff = 9 PI (10 cell)
2404 11:35:25.809872 CA2 delay=35 (7~63),Diff = 7 PI (8 cell)
2405 11:35:25.812808 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2406 11:35:25.816245 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2407 11:35:25.819523 CA5 delay=28 (0~57),Diff = 0 PI (0 cell)
2408 11:35:25.822487
2409 11:35:25.826167 CA PerBit enable=1, Macro0, CA PI delay=28
2410 11:35:25.826245 === u2Vref_new: 0x60 --> 0x90
2411 11:35:25.829427
2412 11:35:25.829501 Vref(ca) range 1: 32
2413 11:35:25.829563
2414 11:35:25.832620 CS Dly= 11 (42-0-32)
2415 11:35:25.832694 Write Rank1 MR13 =0xd8
2416 11:35:25.835808 Write Rank1 MR13 =0xd8
2417 11:35:25.839509 Write Rank1 MR12 =0x60
2418 11:35:25.842744 [RankSwap] Rank num 2, (Multi 1), Rank 0
2419 11:35:25.842819 Write Rank0 MR2 =0xad
2420 11:35:25.846618 [Write Leveling]
2421 11:35:25.849440 delay byte0 byte1 byte2 byte3
2422 11:35:25.849516
2423 11:35:25.849574 10 0 0
2424 11:35:25.852630 11 0 0
2425 11:35:25.852706 12 0 0
2426 11:35:25.852766 13 0 0
2427 11:35:25.856376 14 0 0
2428 11:35:25.856453 15 0 0
2429 11:35:25.859294 16 0 0
2430 11:35:25.859371 17 0 0
2431 11:35:25.859430 18 0 0
2432 11:35:25.862878 19 0 0
2433 11:35:25.862954 20 0 0
2434 11:35:25.866392 21 0 0
2435 11:35:25.866469 22 0 0
2436 11:35:25.866528 23 0 0
2437 11:35:25.869652 24 0 0
2438 11:35:25.869729 25 0 0
2439 11:35:25.873647 26 0 0
2440 11:35:25.873723 27 0 0
2441 11:35:25.876082 28 0 0
2442 11:35:25.876173 29 0 0
2443 11:35:25.876233 30 0 0
2444 11:35:25.879532 31 0 0
2445 11:35:25.879608 32 0 ff
2446 11:35:25.883310 33 0 ff
2447 11:35:25.883387 34 ff ff
2448 11:35:25.886341 35 ff ff
2449 11:35:25.886417 36 ff ff
2450 11:35:25.886476 37 ff ff
2451 11:35:25.889556 38 ff ff
2452 11:35:25.889634 39 ff ff
2453 11:35:25.893488 40 ff ff
2454 11:35:25.897050 pass bytecount = 0xff (0xff: all bytes pass)
2455 11:35:25.897152
2456 11:35:25.897226 DQS0 dly: 34
2457 11:35:25.899671 DQS1 dly: 32
2458 11:35:25.899774 Write Rank0 MR2 =0x2d
2459 11:35:25.906184 [RankSwap] Rank num 2, (Multi 1), Rank 0
2460 11:35:25.906262 Write Rank0 MR1 =0xd6
2461 11:35:25.906321 [Gating]
2462 11:35:25.906375 ==
2463 11:35:25.913285 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2464 11:35:25.916250 fsp= 1, odt_onoff= 1, Byte mode= 0
2465 11:35:25.916327 ==
2466 11:35:25.919907 3 1 0 |3534 1110 |(11 11)(11 11) |(0 0)(0 0)| 0
2467 11:35:25.926358 3 1 4 |3534 1616 |(11 11)(11 11) |(0 0)(1 1)| 0
2468 11:35:25.930201 3 1 8 |3534 2e2e |(11 11)(11 11) |(0 0)(0 0)| 0
2469 11:35:25.933411 3 1 12 |3534 201f |(11 11)(11 11) |(0 0)(1 1)| 0
2470 11:35:25.936495 3 1 16 |3534 3231 |(11 11)(11 11) |(1 1)(1 1)| 0
2471 11:35:25.943277 3 1 20 |3534 2929 |(11 11)(11 11) |(1 1)(0 0)| 0
2472 11:35:25.946107 3 1 24 |3534 1b1a |(11 11)(11 11) |(0 1)(1 0)| 0
2473 11:35:25.949857 3 1 28 |3534 3535 |(11 11)(11 11) |(0 1)(1 1)| 0
2474 11:35:25.957096 3 2 0 |3534 808 |(11 11)(11 11) |(0 1)(1 0)| 0
2475 11:35:25.959368 3 2 4 |3534 2727 |(11 11)(11 11) |(0 1)(1 0)| 0
2476 11:35:25.963537 3 2 8 |3534 1312 |(11 11)(11 11) |(0 1)(0 1)| 0
2477 11:35:25.970091 3 2 12 |3534 2f2f |(11 11)(11 11) |(0 1)(0 1)| 0
2478 11:35:25.972875 3 2 16 |3534 2d2c |(11 11)(11 11) |(0 1)(1 0)| 0
2479 11:35:25.976196 3 2 20 |403 1d1c |(11 11)(11 11) |(1 1)(1 0)| 0
2480 11:35:25.982932 3 2 24 |201f 2e2e |(11 11)(0 0) |(1 1)(1 0)| 0
2481 11:35:25.986180 3 2 28 |3d3d 605 |(11 11)(11 11) |(1 1)(1 1)| 0
2482 11:35:25.989453 3 3 0 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
2483 11:35:25.992980 [Byte 1] Lead/lag Transition tap number (1)
2484 11:35:26.000023 3 3 4 |3d3d 3938 |(11 11)(11 11) |(1 1)(0 0)| 0
2485 11:35:26.002947 3 3 8 |3d3d 3737 |(11 11)(11 11) |(1 1)(1 1)| 0
2486 11:35:26.005995 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2487 11:35:26.009483 3 3 16 |3d3d 3636 |(11 11)(11 11) |(1 1)(1 1)| 0
2488 11:35:26.016213 3 3 20 |3d3d 706 |(11 11)(11 11) |(1 1)(1 1)| 0
2489 11:35:26.019116 3 3 24 |202 e0e |(11 11)(11 11) |(1 1)(1 1)| 0
2490 11:35:26.023094 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2491 11:35:26.028924 [Byte 0] Lead/lag falling Transition (3, 3, 28)
2492 11:35:26.032345 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2493 11:35:26.035962 [Byte 1] Lead/lag falling Transition (3, 4, 0)
2494 11:35:26.042791 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2495 11:35:26.045838 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2496 11:35:26.049337 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2497 11:35:26.055703 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2498 11:35:26.059294 3 4 20 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2499 11:35:26.062991 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2500 11:35:26.065726 3 4 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2501 11:35:26.071984 3 5 0 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2502 11:35:26.075866 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2503 11:35:26.078940 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2504 11:35:26.085538 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2505 11:35:26.088819 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2506 11:35:26.092174 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2507 11:35:26.098677 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2508 11:35:26.102316 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2509 11:35:26.105522 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2510 11:35:26.112204 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2511 11:35:26.115312 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2512 11:35:26.118692 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2513 11:35:26.122040 [Byte 0] Lead/lag falling Transition (3, 6, 12)
2514 11:35:26.128756 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2515 11:35:26.131856 [Byte 0] Lead/lag Transition tap number (2)
2516 11:35:26.135020 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2517 11:35:26.141706 3 6 20 |2525 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2518 11:35:26.145047 3 6 24 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2519 11:35:26.148625 [Byte 1] Lead/lag Transition tap number (3)
2520 11:35:26.152279 3 6 28 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2521 11:35:26.155293 [Byte 0]First pass (3, 6, 28)
2522 11:35:26.158255 3 7 0 |4646 404 |(0 0)(1 1) |(0 0)(0 0)| 0
2523 11:35:26.161673 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2524 11:35:26.164864 [Byte 1]First pass (3, 7, 4)
2525 11:35:26.168176 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2526 11:35:26.175250 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2527 11:35:26.178335 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2528 11:35:26.182245 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2529 11:35:26.185389 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2530 11:35:26.191680 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2531 11:35:26.194896 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2532 11:35:26.198177 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2533 11:35:26.201254 All bytes gating window > 1UI, Early break!
2534 11:35:26.201330
2535 11:35:26.204680 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 16)
2536 11:35:26.204757
2537 11:35:26.208569 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 22)
2538 11:35:26.208645
2539 11:35:26.211374
2540 11:35:26.211450
2541 11:35:26.214605 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
2542 11:35:26.214681
2543 11:35:26.218468 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 22)
2544 11:35:26.218545
2545 11:35:26.218603
2546 11:35:26.221884 Write Rank0 MR1 =0x56
2547 11:35:26.221960
2548 11:35:26.225175 best RODT dly(2T, 0.5T) = (2, 3)
2549 11:35:26.225252
2550 11:35:26.228516 best RODT dly(2T, 0.5T) = (2, 3)
2551 11:35:26.228591 ==
2552 11:35:26.231291 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2553 11:35:26.234644 fsp= 1, odt_onoff= 1, Byte mode= 0
2554 11:35:26.234721 ==
2555 11:35:26.238189 Start DQ dly to find pass range UseTestEngine =0
2556 11:35:26.241241 x-axis: bit #, y-axis: DQ dly (-127~63)
2557 11:35:26.244746 RX Vref Scan = 0
2558 11:35:26.248636 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2559 11:35:26.251244 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2560 11:35:26.254649 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2561 11:35:26.254727 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2562 11:35:26.258090 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2563 11:35:26.262018 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2564 11:35:26.264590 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2565 11:35:26.267743 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2566 11:35:26.271250 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2567 11:35:26.274541 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2568 11:35:26.277986 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2569 11:35:26.281821 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2570 11:35:26.281899 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2571 11:35:26.284603 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2572 11:35:26.287817 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2573 11:35:26.291137 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2574 11:35:26.294716 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2575 11:35:26.297761 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2576 11:35:26.301492 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2577 11:35:26.304586 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2578 11:35:26.304663 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2579 11:35:26.307740 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2580 11:35:26.310865 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2581 11:35:26.314301 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2582 11:35:26.317627 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2583 11:35:26.321237 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2584 11:35:26.324114 0, [0] xxxxxxxx xxxxxxxo [MSB]
2585 11:35:26.324214 1, [0] xxxxxxxx xxxxxxxo [MSB]
2586 11:35:26.327479 2, [0] xxxoxxxx xoxxxxxo [MSB]
2587 11:35:26.331446 3, [0] xxxoxxxx xoxxxxxo [MSB]
2588 11:35:26.334148 4, [0] xxxoxxxx ooxxxxxo [MSB]
2589 11:35:26.337604 5, [0] xoooxxxo ooxxxxxo [MSB]
2590 11:35:26.337704 6, [0] xoooxxxx ooxxxxxo [MSB]
2591 11:35:26.340841 7, [0] oooooxoo oooooooo [MSB]
2592 11:35:26.344526 8, [0] oooooxoo oooooooo [MSB]
2593 11:35:26.347407 31, [0] oooooooo ooooooox [MSB]
2594 11:35:26.350936 32, [0] oooooooo ooooooox [MSB]
2595 11:35:26.354258 33, [0] oooooooo ooooooox [MSB]
2596 11:35:26.357533 34, [0] oooooooo oxooooox [MSB]
2597 11:35:26.357633 35, [0] ooxxoooo xxooooox [MSB]
2598 11:35:26.361064 36, [0] ooxxoooo xxooooox [MSB]
2599 11:35:26.364496 37, [0] ooxxoooo xxxoooox [MSB]
2600 11:35:26.368310 38, [0] ooxxxooo xxxxoxox [MSB]
2601 11:35:26.371135 39, [0] oxxxxxox xxxxxxxx [MSB]
2602 11:35:26.373994 40, [0] oxxxxxox xxxxxxxx [MSB]
2603 11:35:26.377513 41, [0] xxxxxxxx xxxxxxxx [MSB]
2604 11:35:26.380916 iDelay=41, Bit 0, Center 23 (7 ~ 40) 34
2605 11:35:26.384381 iDelay=41, Bit 1, Center 21 (5 ~ 38) 34
2606 11:35:26.387396 iDelay=41, Bit 2, Center 19 (5 ~ 34) 30
2607 11:35:26.390716 iDelay=41, Bit 3, Center 18 (2 ~ 34) 33
2608 11:35:26.394175 iDelay=41, Bit 4, Center 22 (7 ~ 37) 31
2609 11:35:26.397471 iDelay=41, Bit 5, Center 23 (9 ~ 38) 30
2610 11:35:26.401240 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
2611 11:35:26.404492 iDelay=41, Bit 7, Center 22 (7 ~ 38) 32
2612 11:35:26.407377 iDelay=41, Bit 8, Center 19 (4 ~ 34) 31
2613 11:35:26.411146 iDelay=41, Bit 9, Center 17 (2 ~ 33) 32
2614 11:35:26.414265 iDelay=41, Bit 10, Center 21 (7 ~ 36) 30
2615 11:35:26.417584 iDelay=41, Bit 11, Center 22 (7 ~ 37) 31
2616 11:35:26.420826 iDelay=41, Bit 12, Center 22 (7 ~ 38) 32
2617 11:35:26.427622 iDelay=41, Bit 13, Center 22 (7 ~ 37) 31
2618 11:35:26.431351 iDelay=41, Bit 14, Center 22 (7 ~ 38) 32
2619 11:35:26.434073 iDelay=41, Bit 15, Center 15 (0 ~ 30) 31
2620 11:35:26.434170 ==
2621 11:35:26.437434 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2622 11:35:26.440834 fsp= 1, odt_onoff= 1, Byte mode= 0
2623 11:35:26.440931 ==
2624 11:35:26.444011 DQS Delay:
2625 11:35:26.444108 DQS0 = 0, DQS1 = 0
2626 11:35:26.444193 DQM Delay:
2627 11:35:26.447363 DQM0 = 21, DQM1 = 20
2628 11:35:26.447458 DQ Delay:
2629 11:35:26.451386 DQ0 =23, DQ1 =21, DQ2 =19, DQ3 =18
2630 11:35:26.454781 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =22
2631 11:35:26.457373 DQ8 =19, DQ9 =17, DQ10 =21, DQ11 =22
2632 11:35:26.460963 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =15
2633 11:35:26.461060
2634 11:35:26.461187
2635 11:35:26.464404 DramC Write-DBI off
2636 11:35:26.464500 ==
2637 11:35:26.467497 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2638 11:35:26.470919 fsp= 1, odt_onoff= 1, Byte mode= 0
2639 11:35:26.471017 ==
2640 11:35:26.477390 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2641 11:35:26.477490
2642 11:35:26.480468 Begin, DQ Scan Range 928~1184
2643 11:35:26.480564
2644 11:35:26.480648
2645 11:35:26.480729 TX Vref Scan disable
2646 11:35:26.483899 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2647 11:35:26.487834 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2648 11:35:26.490745 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2649 11:35:26.496894 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2650 11:35:26.500537 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2651 11:35:26.504220 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2652 11:35:26.507424 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2653 11:35:26.510687 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2654 11:35:26.514001 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2655 11:35:26.517085 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2656 11:35:26.520496 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2657 11:35:26.523662 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2658 11:35:26.526786 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2659 11:35:26.530390 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2660 11:35:26.533832 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2661 11:35:26.537085 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2662 11:35:26.540672 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2663 11:35:26.543976 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2664 11:35:26.546977 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2665 11:35:26.554246 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2666 11:35:26.557121 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2667 11:35:26.560262 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2668 11:35:26.564209 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2669 11:35:26.567047 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2670 11:35:26.570516 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2671 11:35:26.573620 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2672 11:35:26.577393 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2673 11:35:26.580141 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2674 11:35:26.583315 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2675 11:35:26.587163 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2676 11:35:26.589949 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2677 11:35:26.593541 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2678 11:35:26.596686 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2679 11:35:26.599964 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2680 11:35:26.606408 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2681 11:35:26.609753 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2682 11:35:26.613264 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2683 11:35:26.616812 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2684 11:35:26.619748 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2685 11:35:26.622829 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2686 11:35:26.626665 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2687 11:35:26.629721 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2688 11:35:26.632927 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2689 11:35:26.636581 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2690 11:35:26.639727 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2691 11:35:26.642979 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2692 11:35:26.646639 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2693 11:35:26.650109 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2694 11:35:26.653251 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2695 11:35:26.656971 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2696 11:35:26.659651 978 |3 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2697 11:35:26.663530 979 |3 6 19|[0] xxxxxxxx ooxxxxxo [MSB]
2698 11:35:26.666528 980 |3 6 20|[0] xxxxxxxx ooxxxxxo [MSB]
2699 11:35:26.672863 981 |3 6 21|[0] xxxxxxxx ooxxxxxo [MSB]
2700 11:35:26.676670 982 |3 6 22|[0] xxxxxxxx oooxxxoo [MSB]
2701 11:35:26.679583 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
2702 11:35:26.683050 984 |3 6 24|[0] xooooxoo oooooooo [MSB]
2703 11:35:26.686499 995 |3 6 35|[0] oooooooo ooooooox [MSB]
2704 11:35:26.689798 996 |3 6 36|[0] oooooooo ooooooox [MSB]
2705 11:35:26.692827 997 |3 6 37|[0] oooooooo ooooooox [MSB]
2706 11:35:26.696403 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2707 11:35:26.703124 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2708 11:35:26.706179 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
2709 11:35:26.709380 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2710 11:35:26.712947 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2711 11:35:26.716260 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2712 11:35:26.719271 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
2713 11:35:26.722737 1005 |3 6 45|[0] oxxxooox xxxxxxxx [MSB]
2714 11:35:26.725885 1006 |3 6 46|[0] oxxxxoox xxxxxxxx [MSB]
2715 11:35:26.729808 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2716 11:35:26.733125 Byte0, DQ PI dly=993, DQM PI dly= 993
2717 11:35:26.739306 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
2718 11:35:26.739407
2719 11:35:26.742591 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
2720 11:35:26.742670
2721 11:35:26.745626 Byte1, DQ PI dly=988, DQM PI dly= 988
2722 11:35:26.749063 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2723 11:35:26.749177
2724 11:35:26.755820 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2725 11:35:26.755897
2726 11:35:26.755956 ==
2727 11:35:26.759281 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2728 11:35:26.762571 fsp= 1, odt_onoff= 1, Byte mode= 0
2729 11:35:26.762648 ==
2730 11:35:26.769698 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2731 11:35:26.769774
2732 11:35:26.769833 Begin, DQ Scan Range 964~1028
2733 11:35:26.773017 Write Rank0 MR14 =0x0
2734 11:35:26.780141
2735 11:35:26.780217 CH=1, VrefRange= 0, VrefLevel = 0
2736 11:35:26.786921 TX Bit0 (986~1001) 16 993, Bit8 (982~993) 12 987,
2737 11:35:26.791252 TX Bit1 (985~999) 15 992, Bit9 (982~992) 11 987,
2738 11:35:26.796718 TX Bit2 (983~999) 17 991, Bit10 (984~994) 11 989,
2739 11:35:26.800297 TX Bit3 (982~994) 13 988, Bit11 (984~997) 14 990,
2740 11:35:26.803801 TX Bit4 (985~1000) 16 992, Bit12 (985~996) 12 990,
2741 11:35:26.810246 TX Bit5 (987~1000) 14 993, Bit13 (985~994) 10 989,
2742 11:35:26.813677 TX Bit6 (985~1000) 16 992, Bit14 (984~996) 13 990,
2743 11:35:26.819946 TX Bit7 (985~1000) 16 992, Bit15 (979~988) 10 983,
2744 11:35:26.820095
2745 11:35:26.820182 Write Rank0 MR14 =0x2
2746 11:35:26.828588
2747 11:35:26.828690 CH=1, VrefRange= 0, VrefLevel = 2
2748 11:35:26.835280 TX Bit0 (986~1002) 17 994, Bit8 (981~993) 13 987,
2749 11:35:26.838507 TX Bit1 (985~999) 15 992, Bit9 (982~993) 12 987,
2750 11:35:26.845260 TX Bit2 (983~999) 17 991, Bit10 (984~996) 13 990,
2751 11:35:26.848294 TX Bit3 (981~994) 14 987, Bit11 (984~998) 15 991,
2752 11:35:26.852526 TX Bit4 (985~1001) 17 993, Bit12 (984~996) 13 990,
2753 11:35:26.858666 TX Bit5 (986~1001) 16 993, Bit13 (985~995) 11 990,
2754 11:35:26.861710 TX Bit6 (985~1001) 17 993, Bit14 (984~996) 13 990,
2755 11:35:26.869056 TX Bit7 (985~1000) 16 992, Bit15 (977~990) 14 983,
2756 11:35:26.869188
2757 11:35:26.869248 Write Rank0 MR14 =0x4
2758 11:35:26.877432
2759 11:35:26.877508 CH=1, VrefRange= 0, VrefLevel = 4
2760 11:35:26.883970 TX Bit0 (986~1003) 18 994, Bit8 (981~994) 14 987,
2761 11:35:26.887321 TX Bit1 (985~1000) 16 992, Bit9 (981~993) 13 987,
2762 11:35:26.894187 TX Bit2 (983~1000) 18 991, Bit10 (984~996) 13 990,
2763 11:35:26.897218 TX Bit3 (981~995) 15 988, Bit11 (984~998) 15 991,
2764 11:35:26.900286 TX Bit4 (985~1002) 18 993, Bit12 (984~997) 14 990,
2765 11:35:26.907094 TX Bit5 (986~1001) 16 993, Bit13 (985~996) 12 990,
2766 11:35:26.910212 TX Bit6 (984~1002) 19 993, Bit14 (984~997) 14 990,
2767 11:35:26.916861 TX Bit7 (985~1001) 17 993, Bit15 (978~991) 14 984,
2768 11:35:26.916937
2769 11:35:26.916996 Write Rank0 MR14 =0x6
2770 11:35:26.925814
2771 11:35:26.925893 CH=1, VrefRange= 0, VrefLevel = 6
2772 11:35:26.932762 TX Bit0 (986~1003) 18 994, Bit8 (980~994) 15 987,
2773 11:35:26.935625 TX Bit1 (985~1001) 17 993, Bit9 (980~993) 14 986,
2774 11:35:26.943327 TX Bit2 (982~1001) 20 991, Bit10 (983~997) 15 990,
2775 11:35:26.946201 TX Bit3 (980~996) 17 988, Bit11 (984~999) 16 991,
2776 11:35:26.949628 TX Bit4 (984~1002) 19 993, Bit12 (984~998) 15 991,
2777 11:35:26.955874 TX Bit5 (986~1002) 17 994, Bit13 (985~997) 13 991,
2778 11:35:26.958999 TX Bit6 (984~1002) 19 993, Bit14 (983~998) 16 990,
2779 11:35:26.965675 TX Bit7 (985~1001) 17 993, Bit15 (977~991) 15 984,
2780 11:35:26.965773
2781 11:35:26.965857 Write Rank0 MR14 =0x8
2782 11:35:26.974821
2783 11:35:26.974922 CH=1, VrefRange= 0, VrefLevel = 8
2784 11:35:26.981990 TX Bit0 (986~1004) 19 995, Bit8 (980~995) 16 987,
2785 11:35:26.985333 TX Bit1 (984~1001) 18 992, Bit9 (981~994) 14 987,
2786 11:35:26.990985 TX Bit2 (982~1001) 20 991, Bit10 (983~998) 16 990,
2787 11:35:26.994505 TX Bit3 (980~997) 18 988, Bit11 (984~999) 16 991,
2788 11:35:26.997732 TX Bit4 (984~1002) 19 993, Bit12 (984~999) 16 991,
2789 11:35:27.004467 TX Bit5 (986~1003) 18 994, Bit13 (985~998) 14 991,
2790 11:35:27.008470 TX Bit6 (984~1003) 20 993, Bit14 (983~998) 16 990,
2791 11:35:27.014286 TX Bit7 (985~1002) 18 993, Bit15 (977~992) 16 984,
2792 11:35:27.014384
2793 11:35:27.014466 Write Rank0 MR14 =0xa
2794 11:35:27.023956
2795 11:35:27.027306 CH=1, VrefRange= 0, VrefLevel = 10
2796 11:35:27.030689 TX Bit0 (986~1005) 20 995, Bit8 (979~995) 17 987,
2797 11:35:27.033815 TX Bit1 (984~1002) 19 993, Bit9 (979~995) 17 987,
2798 11:35:27.040238 TX Bit2 (981~1001) 21 991, Bit10 (983~999) 17 991,
2799 11:35:27.044069 TX Bit3 (979~999) 21 989, Bit11 (983~999) 17 991,
2800 11:35:27.047137 TX Bit4 (984~1004) 21 994, Bit12 (983~999) 17 991,
2801 11:35:27.053387 TX Bit5 (986~1004) 19 995, Bit13 (984~998) 15 991,
2802 11:35:27.056626 TX Bit6 (984~1003) 20 993, Bit14 (983~999) 17 991,
2803 11:35:27.063726 TX Bit7 (984~1002) 19 993, Bit15 (977~992) 16 984,
2804 11:35:27.063830
2805 11:35:27.063914 Write Rank0 MR14 =0xc
2806 11:35:27.073052
2807 11:35:27.076047 CH=1, VrefRange= 0, VrefLevel = 12
2808 11:35:27.080163 TX Bit0 (985~1005) 21 995, Bit8 (978~996) 19 987,
2809 11:35:27.083047 TX Bit1 (984~1003) 20 993, Bit9 (979~996) 18 987,
2810 11:35:27.090108 TX Bit2 (981~1002) 22 991, Bit10 (983~999) 17 991,
2811 11:35:27.093107 TX Bit3 (979~999) 21 989, Bit11 (983~1000) 18 991,
2812 11:35:27.096448 TX Bit4 (983~1004) 22 993, Bit12 (983~999) 17 991,
2813 11:35:27.103302 TX Bit5 (985~1005) 21 995, Bit13 (984~999) 16 991,
2814 11:35:27.106212 TX Bit6 (983~1004) 22 993, Bit14 (982~999) 18 990,
2815 11:35:27.112718 TX Bit7 (984~1003) 20 993, Bit15 (975~993) 19 984,
2816 11:35:27.112864
2817 11:35:27.112924 Write Rank0 MR14 =0xe
2818 11:35:27.122204
2819 11:35:27.126208 CH=1, VrefRange= 0, VrefLevel = 14
2820 11:35:27.128930 TX Bit0 (985~1006) 22 995, Bit8 (978~997) 20 987,
2821 11:35:27.132774 TX Bit1 (983~1003) 21 993, Bit9 (979~997) 19 988,
2822 11:35:27.138703 TX Bit2 (981~1003) 23 992, Bit10 (982~999) 18 990,
2823 11:35:27.142324 TX Bit3 (979~1000) 22 989, Bit11 (983~1000) 18 991,
2824 11:35:27.148892 TX Bit4 (983~1005) 23 994, Bit12 (983~1000) 18 991,
2825 11:35:27.152178 TX Bit5 (985~1005) 21 995, Bit13 (983~999) 17 991,
2826 11:35:27.155598 TX Bit6 (983~1005) 23 994, Bit14 (982~1000) 19 991,
2827 11:35:27.162181 TX Bit7 (984~1004) 21 994, Bit15 (977~993) 17 985,
2828 11:35:27.162258
2829 11:35:27.162317 Write Rank0 MR14 =0x10
2830 11:35:27.172186
2831 11:35:27.172264 CH=1, VrefRange= 0, VrefLevel = 16
2832 11:35:27.179199 TX Bit0 (985~1006) 22 995, Bit8 (978~997) 20 987,
2833 11:35:27.182028 TX Bit1 (983~1003) 21 993, Bit9 (979~997) 19 988,
2834 11:35:27.188623 TX Bit2 (981~1003) 23 992, Bit10 (982~999) 18 990,
2835 11:35:27.192276 TX Bit3 (979~1000) 22 989, Bit11 (983~1000) 18 991,
2836 11:35:27.199285 TX Bit4 (983~1005) 23 994, Bit12 (983~1000) 18 991,
2837 11:35:27.202709 TX Bit5 (985~1005) 21 995, Bit13 (983~999) 17 991,
2838 11:35:27.205986 TX Bit6 (983~1005) 23 994, Bit14 (982~1000) 19 991,
2839 11:35:27.211679 TX Bit7 (984~1004) 21 994, Bit15 (977~993) 17 985,
2840 11:35:27.211755
2841 11:35:27.211814 Write Rank0 MR14 =0x12
2842 11:35:27.221402
2843 11:35:27.225035 CH=1, VrefRange= 0, VrefLevel = 18
2844 11:35:27.228394 TX Bit0 (985~1006) 22 995, Bit8 (978~998) 21 988,
2845 11:35:27.232103 TX Bit1 (983~1005) 23 994, Bit9 (977~998) 22 987,
2846 11:35:27.238570 TX Bit2 (980~1004) 25 992, Bit10 (982~1000) 19 991,
2847 11:35:27.241439 TX Bit3 (978~1001) 24 989, Bit11 (982~1001) 20 991,
2848 11:35:27.248109 TX Bit4 (983~1006) 24 994, Bit12 (982~1000) 19 991,
2849 11:35:27.251700 TX Bit5 (985~1006) 22 995, Bit13 (983~1000) 18 991,
2850 11:35:27.255180 TX Bit6 (982~1006) 25 994, Bit14 (982~1000) 19 991,
2851 11:35:27.262133 TX Bit7 (983~1005) 23 994, Bit15 (975~994) 20 984,
2852 11:35:27.262211
2853 11:35:27.262269 Write Rank0 MR14 =0x14
2854 11:35:27.271845
2855 11:35:27.274875 CH=1, VrefRange= 0, VrefLevel = 20
2856 11:35:27.277989 TX Bit0 (984~1007) 24 995, Bit8 (977~999) 23 988,
2857 11:35:27.281319 TX Bit1 (983~1005) 23 994, Bit9 (977~998) 22 987,
2858 11:35:27.288076 TX Bit2 (980~1005) 26 992, Bit10 (981~1000) 20 990,
2859 11:35:27.291875 TX Bit3 (978~1001) 24 989, Bit11 (982~1001) 20 991,
2860 11:35:27.298301 TX Bit4 (982~1006) 25 994, Bit12 (982~1001) 20 991,
2861 11:35:27.301623 TX Bit5 (985~1006) 22 995, Bit13 (983~1000) 18 991,
2862 11:35:27.304816 TX Bit6 (983~1006) 24 994, Bit14 (981~1001) 21 991,
2863 11:35:27.311594 TX Bit7 (982~1005) 24 993, Bit15 (974~994) 21 984,
2864 11:35:27.311671
2865 11:35:27.311728 Write Rank0 MR14 =0x16
2866 11:35:27.321791
2867 11:35:27.325093 CH=1, VrefRange= 0, VrefLevel = 22
2868 11:35:27.328307 TX Bit0 (984~1007) 24 995, Bit8 (977~999) 23 988,
2869 11:35:27.331805 TX Bit1 (983~1006) 24 994, Bit9 (976~999) 24 987,
2870 11:35:27.338456 TX Bit2 (979~1005) 27 992, Bit10 (981~1000) 20 990,
2871 11:35:27.341671 TX Bit3 (978~1002) 25 990, Bit11 (981~1001) 21 991,
2872 11:35:27.348133 TX Bit4 (981~1007) 27 994, Bit12 (981~1001) 21 991,
2873 11:35:27.351654 TX Bit5 (984~1007) 24 995, Bit13 (983~1000) 18 991,
2874 11:35:27.354800 TX Bit6 (982~1007) 26 994, Bit14 (982~1001) 20 991,
2875 11:35:27.361751 TX Bit7 (982~1006) 25 994, Bit15 (973~995) 23 984,
2876 11:35:27.361825
2877 11:35:27.361883 Write Rank0 MR14 =0x18
2878 11:35:27.371823
2879 11:35:27.374955 CH=1, VrefRange= 0, VrefLevel = 24
2880 11:35:27.378478 TX Bit0 (984~1007) 24 995, Bit8 (976~999) 24 987,
2881 11:35:27.382013 TX Bit1 (982~1006) 25 994, Bit9 (977~999) 23 988,
2882 11:35:27.388187 TX Bit2 (980~1006) 27 993, Bit10 (981~1001) 21 991,
2883 11:35:27.391427 TX Bit3 (978~1002) 25 990, Bit11 (981~1002) 22 991,
2884 11:35:27.398379 TX Bit4 (981~1007) 27 994, Bit12 (981~1001) 21 991,
2885 11:35:27.401553 TX Bit5 (984~1007) 24 995, Bit13 (983~1001) 19 992,
2886 11:35:27.404997 TX Bit6 (981~1007) 27 994, Bit14 (980~1001) 22 990,
2887 11:35:27.411188 TX Bit7 (982~1006) 25 994, Bit15 (973~996) 24 984,
2888 11:35:27.411265
2889 11:35:27.411324 Write Rank0 MR14 =0x1a
2890 11:35:27.421840
2891 11:35:27.425381 CH=1, VrefRange= 0, VrefLevel = 26
2892 11:35:27.428643 TX Bit0 (984~1007) 24 995, Bit8 (976~1000) 25 988,
2893 11:35:27.431543 TX Bit1 (982~1007) 26 994, Bit9 (976~999) 24 987,
2894 11:35:27.438341 TX Bit2 (980~1006) 27 993, Bit10 (980~1001) 22 990,
2895 11:35:27.441805 TX Bit3 (978~1002) 25 990, Bit11 (981~1002) 22 991,
2896 11:35:27.447846 TX Bit4 (981~1007) 27 994, Bit12 (981~1002) 22 991,
2897 11:35:27.451330 TX Bit5 (984~1007) 24 995, Bit13 (982~1001) 20 991,
2898 11:35:27.454579 TX Bit6 (981~1007) 27 994, Bit14 (980~1002) 23 991,
2899 11:35:27.461390 TX Bit7 (982~1007) 26 994, Bit15 (973~997) 25 985,
2900 11:35:27.461568
2901 11:35:27.464823 Write Rank0 MR14 =0x1c
2902 11:35:27.471954
2903 11:35:27.475338 CH=1, VrefRange= 0, VrefLevel = 28
2904 11:35:27.478419 TX Bit0 (983~1008) 26 995, Bit8 (976~999) 24 987,
2905 11:35:27.482116 TX Bit1 (981~1007) 27 994, Bit9 (976~999) 24 987,
2906 11:35:27.488800 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2907 11:35:27.491924 TX Bit3 (978~1003) 26 990, Bit11 (980~1002) 23 991,
2908 11:35:27.498632 TX Bit4 (981~1007) 27 994, Bit12 (981~1002) 22 991,
2909 11:35:27.502083 TX Bit5 (983~1007) 25 995, Bit13 (982~1002) 21 992,
2910 11:35:27.504976 TX Bit6 (981~1007) 27 994, Bit14 (979~1002) 24 990,
2911 11:35:27.511669 TX Bit7 (981~1007) 27 994, Bit15 (972~997) 26 984,
2912 11:35:27.511753
2913 11:35:27.511813 Write Rank0 MR14 =0x1e
2914 11:35:27.521812
2915 11:35:27.525179 CH=1, VrefRange= 0, VrefLevel = 30
2916 11:35:27.529244 TX Bit0 (983~1008) 26 995, Bit8 (976~999) 24 987,
2917 11:35:27.531845 TX Bit1 (981~1007) 27 994, Bit9 (976~999) 24 987,
2918 11:35:27.539329 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2919 11:35:27.542297 TX Bit3 (978~1003) 26 990, Bit11 (980~1002) 23 991,
2920 11:35:27.548883 TX Bit4 (981~1007) 27 994, Bit12 (981~1002) 22 991,
2921 11:35:27.552242 TX Bit5 (983~1007) 25 995, Bit13 (982~1002) 21 992,
2922 11:35:27.555335 TX Bit6 (981~1007) 27 994, Bit14 (979~1002) 24 990,
2923 11:35:27.562310 TX Bit7 (981~1007) 27 994, Bit15 (972~997) 26 984,
2924 11:35:27.562395
2925 11:35:27.562453 Write Rank0 MR14 =0x20
2926 11:35:27.571962
2927 11:35:27.575568 CH=1, VrefRange= 0, VrefLevel = 32
2928 11:35:27.578959 TX Bit0 (983~1008) 26 995, Bit8 (976~999) 24 987,
2929 11:35:27.582480 TX Bit1 (981~1007) 27 994, Bit9 (976~999) 24 987,
2930 11:35:27.588852 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2931 11:35:27.591964 TX Bit3 (978~1003) 26 990, Bit11 (980~1002) 23 991,
2932 11:35:27.595678 TX Bit4 (981~1007) 27 994, Bit12 (981~1002) 22 991,
2933 11:35:27.602195 TX Bit5 (983~1007) 25 995, Bit13 (982~1002) 21 992,
2934 11:35:27.605517 TX Bit6 (981~1007) 27 994, Bit14 (979~1002) 24 990,
2935 11:35:27.612130 TX Bit7 (981~1007) 27 994, Bit15 (972~997) 26 984,
2936 11:35:27.612223
2937 11:35:27.612282 Write Rank0 MR14 =0x22
2938 11:35:27.622678
2939 11:35:27.625586 CH=1, VrefRange= 0, VrefLevel = 34
2940 11:35:27.628934 TX Bit0 (983~1008) 26 995, Bit8 (976~999) 24 987,
2941 11:35:27.632599 TX Bit1 (981~1007) 27 994, Bit9 (976~999) 24 987,
2942 11:35:27.639285 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2943 11:35:27.643231 TX Bit3 (978~1003) 26 990, Bit11 (980~1002) 23 991,
2944 11:35:27.649757 TX Bit4 (981~1007) 27 994, Bit12 (981~1002) 22 991,
2945 11:35:27.652084 TX Bit5 (983~1007) 25 995, Bit13 (982~1002) 21 992,
2946 11:35:27.655899 TX Bit6 (981~1007) 27 994, Bit14 (979~1002) 24 990,
2947 11:35:27.662526 TX Bit7 (981~1007) 27 994, Bit15 (972~997) 26 984,
2948 11:35:27.662635
2949 11:35:27.662724 Write Rank0 MR14 =0x24
2950 11:35:27.672239
2951 11:35:27.675471 CH=1, VrefRange= 0, VrefLevel = 36
2952 11:35:27.679172 TX Bit0 (983~1008) 26 995, Bit8 (976~999) 24 987,
2953 11:35:27.682231 TX Bit1 (981~1007) 27 994, Bit9 (976~999) 24 987,
2954 11:35:27.688942 TX Bit2 (979~1006) 28 992, Bit10 (979~1002) 24 990,
2955 11:35:27.692628 TX Bit3 (978~1003) 26 990, Bit11 (980~1002) 23 991,
2956 11:35:27.699041 TX Bit4 (981~1007) 27 994, Bit12 (981~1002) 22 991,
2957 11:35:27.702721 TX Bit5 (983~1007) 25 995, Bit13 (982~1002) 21 992,
2958 11:35:27.705597 TX Bit6 (981~1007) 27 994, Bit14 (979~1002) 24 990,
2959 11:35:27.712611 TX Bit7 (981~1007) 27 994, Bit15 (972~997) 26 984,
2960 11:35:27.712947
2961 11:35:27.713239
2962 11:35:27.715819 TX Vref found, early break! 377< 380
2963 11:35:27.719385 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
2964 11:35:27.722573 u1DelayCellOfst[0]=5 cells (5 PI)
2965 11:35:27.725605 u1DelayCellOfst[1]=4 cells (4 PI)
2966 11:35:27.729385 u1DelayCellOfst[2]=2 cells (2 PI)
2967 11:35:27.732858 u1DelayCellOfst[3]=0 cells (0 PI)
2968 11:35:27.735939 u1DelayCellOfst[4]=4 cells (4 PI)
2969 11:35:27.739057 u1DelayCellOfst[5]=5 cells (5 PI)
2970 11:35:27.742526 u1DelayCellOfst[6]=4 cells (4 PI)
2971 11:35:27.746183 u1DelayCellOfst[7]=4 cells (4 PI)
2972 11:35:27.748776 Byte0, DQ PI dly=990, DQM PI dly= 992
2973 11:35:27.752818 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2974 11:35:27.753178
2975 11:35:27.755537 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2976 11:35:27.755868
2977 11:35:27.759125 u1DelayCellOfst[8]=3 cells (3 PI)
2978 11:35:27.762481 u1DelayCellOfst[9]=3 cells (3 PI)
2979 11:35:27.765731 u1DelayCellOfst[10]=7 cells (6 PI)
2980 11:35:27.768815 u1DelayCellOfst[11]=8 cells (7 PI)
2981 11:35:27.772089 u1DelayCellOfst[12]=8 cells (7 PI)
2982 11:35:27.775840 u1DelayCellOfst[13]=9 cells (8 PI)
2983 11:35:27.778842 u1DelayCellOfst[14]=7 cells (6 PI)
2984 11:35:27.782422 u1DelayCellOfst[15]=0 cells (0 PI)
2985 11:35:27.786016 Byte1, DQ PI dly=984, DQM PI dly= 988
2986 11:35:27.788856 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2987 11:35:27.789336
2988 11:35:27.792413 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2989 11:35:27.792709
2990 11:35:27.795557 Write Rank0 MR14 =0x1c
2991 11:35:27.795855
2992 11:35:27.798927 Final TX Range 0 Vref 28
2993 11:35:27.799149
2994 11:35:27.805769 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2995 11:35:27.805991
2996 11:35:27.812001 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2997 11:35:27.818656 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2998 11:35:27.825249 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2999 11:35:27.828793 Write Rank0 MR3 =0xb0
3000 11:35:27.828891 DramC Write-DBI on
3001 11:35:27.828985 ==
3002 11:35:27.835462 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3003 11:35:27.838312 fsp= 1, odt_onoff= 1, Byte mode= 0
3004 11:35:27.838412 ==
3005 11:35:27.841572 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3006 11:35:27.841670
3007 11:35:27.845203 Begin, DQ Scan Range 708~772
3008 11:35:27.845298
3009 11:35:27.845388
3010 11:35:27.848819 TX Vref Scan disable
3011 11:35:27.851600 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3012 11:35:27.855029 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3013 11:35:27.858538 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3014 11:35:27.861995 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3015 11:35:27.865411 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3016 11:35:27.868621 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3017 11:35:27.871749 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3018 11:35:27.875299 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3019 11:35:27.878429 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3020 11:35:27.882114 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3021 11:35:27.884948 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3022 11:35:27.888124 719 |2 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3023 11:35:27.891850 720 |2 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
3024 11:35:27.895078 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3025 11:35:27.898404 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3026 11:35:27.902075 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3027 11:35:27.905274 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3028 11:35:27.912033 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3029 11:35:27.915716 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3030 11:35:27.918504 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3031 11:35:27.921471 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3032 11:35:27.928208 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3033 11:35:27.931708 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3034 11:35:27.935157 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3035 11:35:27.938687 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3036 11:35:27.941820 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3037 11:35:27.944954 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3038 11:35:27.948080 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3039 11:35:27.951840 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3040 11:35:27.955404 753 |2 6 49|[0] xxxxxxxx xxxxxxxx [MSB]
3041 11:35:27.958376 Byte0, DQ PI dly=740, DQM PI dly= 740
3042 11:35:27.961231 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 36)
3043 11:35:27.961566
3044 11:35:27.967992 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 36)
3045 11:35:27.968324
3046 11:35:27.972077 Byte1, DQ PI dly=732, DQM PI dly= 732
3047 11:35:27.974690 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
3048 11:35:27.975025
3049 11:35:27.978004 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
3050 11:35:27.981950
3051 11:35:27.984417 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3052 11:35:27.994425 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3053 11:35:28.001042 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3054 11:35:28.001413 Write Rank0 MR3 =0x30
3055 11:35:28.004805 DramC Write-DBI off
3056 11:35:28.005170
3057 11:35:28.005437 [DATLAT]
3058 11:35:28.008090 Freq=1600, CH1 RK0, use_rxtx_scan=0
3059 11:35:28.008448
3060 11:35:28.011263 DATLAT Default: 0xf
3061 11:35:28.011621 7, 0xFFFF, sum=0
3062 11:35:28.015286 8, 0xFFFF, sum=0
3063 11:35:28.015649 9, 0xFFFF, sum=0
3064 11:35:28.018654 10, 0xFFFF, sum=0
3065 11:35:28.019019 11, 0xFFFF, sum=0
3066 11:35:28.021932 12, 0xFFFF, sum=0
3067 11:35:28.022338 13, 0xFFFF, sum=0
3068 11:35:28.022638 14, 0x0, sum=1
3069 11:35:28.024944 15, 0x0, sum=2
3070 11:35:28.025361 16, 0x0, sum=3
3071 11:35:28.028161 17, 0x0, sum=4
3072 11:35:28.031667 pattern=2 first_step=14 total pass=5 best_step=16
3073 11:35:28.032023 ==
3074 11:35:28.038124 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3075 11:35:28.038484 fsp= 1, odt_onoff= 1, Byte mode= 0
3076 11:35:28.041270 ==
3077 11:35:28.045189 Start DQ dly to find pass range UseTestEngine =1
3078 11:35:28.048089 x-axis: bit #, y-axis: DQ dly (-127~63)
3079 11:35:28.048447 RX Vref Scan = 1
3080 11:35:28.156789
3081 11:35:28.157216 RX Vref found, early break!
3082 11:35:28.157508
3083 11:35:28.163940 Final RX Vref 12, apply to both rank0 and 1
3084 11:35:28.164302 ==
3085 11:35:28.166766 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3086 11:35:28.169991 fsp= 1, odt_onoff= 1, Byte mode= 0
3087 11:35:28.170352 ==
3088 11:35:28.170630 DQS Delay:
3089 11:35:28.173650 DQS0 = 0, DQS1 = 0
3090 11:35:28.174006 DQM Delay:
3091 11:35:28.177076 DQM0 = 21, DQM1 = 19
3092 11:35:28.177559 DQ Delay:
3093 11:35:28.179894 DQ0 =23, DQ1 =21, DQ2 =20, DQ3 =19
3094 11:35:28.183805 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3095 11:35:28.186622 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3096 11:35:28.190022 DQ12 =22, DQ13 =22, DQ14 =21, DQ15 =16
3097 11:35:28.190377
3098 11:35:28.190651
3099 11:35:28.190903
3100 11:35:28.193589 [DramC_TX_OE_Calibration] TA2
3101 11:35:28.197154 Original DQ_B0 (3 6) =30, OEN = 27
3102 11:35:28.200229 Original DQ_B1 (3 6) =30, OEN = 27
3103 11:35:28.203090 23, 0x0, End_B0=23 End_B1=23
3104 11:35:28.203453 24, 0x0, End_B0=24 End_B1=24
3105 11:35:28.206737 25, 0x0, End_B0=25 End_B1=25
3106 11:35:28.209965 26, 0x0, End_B0=26 End_B1=26
3107 11:35:28.213285 27, 0x0, End_B0=27 End_B1=27
3108 11:35:28.216939 28, 0x0, End_B0=28 End_B1=28
3109 11:35:28.217343 29, 0x0, End_B0=29 End_B1=29
3110 11:35:28.220000 30, 0x0, End_B0=30 End_B1=30
3111 11:35:28.222920 31, 0xDBFF, End_B0=30 End_B1=30
3112 11:35:28.229474 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3113 11:35:28.233254 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3114 11:35:28.233616
3115 11:35:28.233894
3116 11:35:28.236611 Write Rank0 MR23 =0x3f
3117 11:35:28.236970 [DQSOSC]
3118 11:35:28.246147 [DQSOSCAuto] RK0, (LSB)MR18= 0xbcbc, (MSB)MR19= 0x202, tDQSOscB0 = 450 ps tDQSOscB1 = 450 ps
3119 11:35:28.253279 CH1_RK0: MR19=0x202, MR18=0xBCBC, DQSOSC=450, MR23=63, INC=12, DEC=18
3120 11:35:28.253639 Write Rank0 MR23 =0x3f
3121 11:35:28.253918 [DQSOSC]
3122 11:35:28.262864 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3123 11:35:28.266534 CH1 RK0: MR19=202, MR18=BFBF
3124 11:35:28.269360 [RankSwap] Rank num 2, (Multi 1), Rank 1
3125 11:35:28.269722 Write Rank0 MR2 =0xad
3126 11:35:28.273292 [Write Leveling]
3127 11:35:28.276214 delay byte0 byte1 byte2 byte3
3128 11:35:28.276572
3129 11:35:28.276847 10 0 0
3130 11:35:28.279727 11 0 0
3131 11:35:28.280093 12 0 0
3132 11:35:28.280377 13 0 0
3133 11:35:28.282899 14 0 0
3134 11:35:28.283261 15 0 0
3135 11:35:28.286276 16 0 0
3136 11:35:28.286652 17 0 0
3137 11:35:28.286935 18 0 0
3138 11:35:28.289882 19 0 0
3139 11:35:28.290260 20 0 0
3140 11:35:28.292863 21 0 0
3141 11:35:28.293264 22 0 0
3142 11:35:28.296423 23 0 0
3143 11:35:28.296785 24 0 0
3144 11:35:28.297064 25 0 0
3145 11:35:28.299735 26 0 0
3146 11:35:28.300095 27 0 0
3147 11:35:28.303047 28 0 0
3148 11:35:28.303409 29 0 0
3149 11:35:28.303691 30 0 0
3150 11:35:28.306686 31 0 0
3151 11:35:28.307049 32 0 ff
3152 11:35:28.309517 33 0 ff
3153 11:35:28.309881 34 0 ff
3154 11:35:28.312624 35 0 ff
3155 11:35:28.312986 36 0 ff
3156 11:35:28.315918 37 0 ff
3157 11:35:28.316278 38 ff ff
3158 11:35:28.316560 39 ff ff
3159 11:35:28.319136 40 ff ff
3160 11:35:28.319473 41 ff ff
3161 11:35:28.323048 42 ff ff
3162 11:35:28.323411 43 ff ff
3163 11:35:28.325886 44 ff ff
3164 11:35:28.329225 pass bytecount = 0xff (0xff: all bytes pass)
3165 11:35:28.329586
3166 11:35:28.329864 DQS0 dly: 38
3167 11:35:28.332977 DQS1 dly: 32
3168 11:35:28.333400 Write Rank0 MR2 =0x2d
3169 11:35:28.339762 [RankSwap] Rank num 2, (Multi 1), Rank 0
3170 11:35:28.340121 Write Rank1 MR1 =0xd6
3171 11:35:28.340401 [Gating]
3172 11:35:28.340655 ==
3173 11:35:28.346240 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3174 11:35:28.349601 fsp= 1, odt_onoff= 1, Byte mode= 0
3175 11:35:28.349959 ==
3176 11:35:28.352834 3 1 0 |3534 2e2d |(11 11)(11 11) |(0 0)(1 1)| 0
3177 11:35:28.359192 3 1 4 |3534 2e2d |(11 11)(11 11) |(0 0)(0 0)| 0
3178 11:35:28.362432 3 1 8 |3534 2d2d |(11 11)(11 11) |(1 1)(0 0)| 0
3179 11:35:28.365980 3 1 12 |3534 3130 |(11 11)(11 11) |(1 1)(0 0)| 0
3180 11:35:28.369143 3 1 16 |3534 303 |(11 11)(11 11) |(0 1)(1 1)| 0
3181 11:35:28.376449 3 1 20 |3534 2e2d |(11 11)(11 11) |(0 1)(1 0)| 0
3182 11:35:28.379465 3 1 24 |3534 201 |(11 11)(11 11) |(0 1)(0 1)| 0
3183 11:35:28.382417 3 1 28 |3534 504 |(11 11)(1 1) |(0 1)(1 1)| 0
3184 11:35:28.388999 3 2 0 |3534 2d2c |(11 11)(11 11) |(0 1)(0 1)| 0
3185 11:35:28.392422 3 2 4 |3534 2e2e |(11 11)(10 10) |(0 1)(1 0)| 0
3186 11:35:28.395931 3 2 8 |3534 2d2d |(11 11)(11 11) |(0 1)(0 1)| 0
3187 11:35:28.402688 3 2 12 |201 a09 |(11 11)(11 11) |(1 1)(0 1)| 0
3188 11:35:28.405653 3 2 16 |3d3d 2e2d |(11 11)(1 1) |(1 1)(1 0)| 0
3189 11:35:28.408679 3 2 20 |3d3d 303 |(11 11)(11 11) |(1 1)(1 1)| 0
3190 11:35:28.411891 3 2 24 |3d3d 1111 |(11 11)(11 11) |(1 1)(0 0)| 0
3191 11:35:28.419078 3 2 28 |3d3d 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
3192 11:35:28.422091 [Byte 1] Lead/lag Transition tap number (1)
3193 11:35:28.425730 3 3 0 |3d3d 3636 |(11 11)(0 0) |(1 1)(0 0)| 0
3194 11:35:28.428874 3 3 4 |3d3d 3837 |(11 11)(11 11) |(1 1)(1 1)| 0
3195 11:35:28.435811 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3196 11:35:28.438718 3 3 12 |3d3d 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
3197 11:35:28.442475 3 3 16 |201 b0b |(11 11)(11 11) |(1 1)(1 1)| 0
3198 11:35:28.448869 [Byte 0] Lead/lag falling Transition (3, 3, 16)
3199 11:35:28.451980 3 3 20 |3534 1a19 |(11 11)(11 11) |(0 1)(1 1)| 0
3200 11:35:28.455711 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3201 11:35:28.461899 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3202 11:35:28.465729 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3203 11:35:28.468506 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3204 11:35:28.475370 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3205 11:35:28.478915 3 4 12 |504 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3206 11:35:28.481971 3 4 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3207 11:35:28.485621 3 4 20 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3208 11:35:28.492658 3 4 24 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
3209 11:35:28.495051 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3210 11:35:28.498517 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3211 11:35:28.505191 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3212 11:35:28.508395 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3213 11:35:28.512097 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3214 11:35:28.518972 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3215 11:35:28.521696 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3216 11:35:28.524911 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3217 11:35:28.531741 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3218 11:35:28.535483 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3219 11:35:28.538691 [Byte 0] Lead/lag falling Transition (3, 6, 0)
3220 11:35:28.543526 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3221 11:35:28.548419 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3222 11:35:28.551714 [Byte 0] Lead/lag Transition tap number (3)
3223 11:35:28.555183 [Byte 1] Lead/lag falling Transition (3, 6, 8)
3224 11:35:28.558730 3 6 12 |1010 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3225 11:35:28.565403 3 6 16 |a0a 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3226 11:35:28.568670 [Byte 1] Lead/lag Transition tap number (3)
3227 11:35:28.571647 3 6 20 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
3228 11:35:28.574945 [Byte 0]First pass (3, 6, 20)
3229 11:35:28.578816 3 6 24 |4646 1010 |(0 0)(11 11) |(0 0)(0 0)| 0
3230 11:35:28.581768 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3231 11:35:28.584619 [Byte 1]First pass (3, 6, 28)
3232 11:35:28.588061 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3233 11:35:28.595444 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3234 11:35:28.598652 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3235 11:35:28.601762 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3236 11:35:28.604907 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3237 11:35:28.611818 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3238 11:35:28.615128 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3239 11:35:28.618114 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3240 11:35:28.621241 All bytes gating window > 1UI, Early break!
3241 11:35:28.621601
3242 11:35:28.624619 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
3243 11:35:28.624976
3244 11:35:28.628216 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 14)
3245 11:35:28.628580
3246 11:35:28.631202
3247 11:35:28.631554
3248 11:35:28.634680 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
3249 11:35:28.635204
3250 11:35:28.638692 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
3251 11:35:28.639053
3252 11:35:28.639329
3253 11:35:28.641199 Write Rank1 MR1 =0x56
3254 11:35:28.641559
3255 11:35:28.644391 best RODT dly(2T, 0.5T) = (2, 3)
3256 11:35:28.644792
3257 11:35:28.647901 best RODT dly(2T, 0.5T) = (2, 3)
3258 11:35:28.648406 ==
3259 11:35:28.651321 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3260 11:35:28.654363 fsp= 1, odt_onoff= 1, Byte mode= 0
3261 11:35:28.654752 ==
3262 11:35:28.657860 Start DQ dly to find pass range UseTestEngine =0
3263 11:35:28.661187 x-axis: bit #, y-axis: DQ dly (-127~63)
3264 11:35:28.664674 RX Vref Scan = 0
3265 11:35:28.668519 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3266 11:35:28.671557 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3267 11:35:28.674434 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3268 11:35:28.674799 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3269 11:35:28.678171 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3270 11:35:28.681368 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3271 11:35:28.684540 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3272 11:35:28.687523 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3273 11:35:28.690998 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3274 11:35:28.694125 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3275 11:35:28.697946 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3276 11:35:28.700848 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3277 11:35:28.701250 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3278 11:35:28.704580 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3279 11:35:28.708069 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3280 11:35:28.711372 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3281 11:35:28.714603 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3282 11:35:28.717706 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3283 11:35:28.721289 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3284 11:35:28.724691 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3285 11:35:28.725082 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3286 11:35:28.727845 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3287 11:35:28.730863 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3288 11:35:28.734066 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3289 11:35:28.737732 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3290 11:35:28.741218 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3291 11:35:28.741614 0, [0] xxxxxxxx xxxxxxxx [MSB]
3292 11:35:28.743964 1, [0] xxxoxxxx xoxxxxxo [MSB]
3293 11:35:28.747613 2, [0] xxxoxxxx ooxxxxxo [MSB]
3294 11:35:28.750752 3, [0] xxxoxxxx ooxxxxxo [MSB]
3295 11:35:28.754094 4, [0] xxooxxxx ooxxxxxo [MSB]
3296 11:35:28.757452 5, [0] xxooxxxx oooxoxxo [MSB]
3297 11:35:28.757846 6, [0] xxoooxxx oooooxoo [MSB]
3298 11:35:28.761311 7, [0] xooooxxo oooooooo [MSB]
3299 11:35:28.764153 31, [0] oooooooo ooooooox [MSB]
3300 11:35:28.767573 32, [0] oooooooo ooooooox [MSB]
3301 11:35:28.770946 33, [0] oooooooo ooooooox [MSB]
3302 11:35:28.774255 34, [0] oooooooo xxooooox [MSB]
3303 11:35:28.777602 35, [0] oooooooo xxooooox [MSB]
3304 11:35:28.777997 36, [0] ooxxoooo xxooooox [MSB]
3305 11:35:28.780892 37, [0] ooxxoooo xxooooox [MSB]
3306 11:35:28.784342 38, [0] ooxxxooo xxxoooox [MSB]
3307 11:35:28.787874 39, [0] ooxxxoox xxxxxxxx [MSB]
3308 11:35:28.790960 40, [0] oxxxxoox xxxxxxxx [MSB]
3309 11:35:28.794085 41, [0] xxxxxxox xxxxxxxx [MSB]
3310 11:35:28.797313 42, [0] xxxxxxxx xxxxxxxx [MSB]
3311 11:35:28.801051 iDelay=42, Bit 0, Center 24 (8 ~ 40) 33
3312 11:35:28.804225 iDelay=42, Bit 1, Center 23 (7 ~ 39) 33
3313 11:35:28.807338 iDelay=42, Bit 2, Center 19 (4 ~ 35) 32
3314 11:35:28.810965 iDelay=42, Bit 3, Center 18 (1 ~ 35) 35
3315 11:35:28.814289 iDelay=42, Bit 4, Center 21 (6 ~ 37) 32
3316 11:35:28.817193 iDelay=42, Bit 5, Center 24 (8 ~ 40) 33
3317 11:35:28.820478 iDelay=42, Bit 6, Center 24 (8 ~ 41) 34
3318 11:35:28.824163 iDelay=42, Bit 7, Center 22 (7 ~ 38) 32
3319 11:35:28.827503 iDelay=42, Bit 8, Center 17 (2 ~ 33) 32
3320 11:35:28.830512 iDelay=42, Bit 9, Center 17 (1 ~ 33) 33
3321 11:35:28.833818 iDelay=42, Bit 10, Center 21 (5 ~ 37) 33
3322 11:35:28.837292 iDelay=42, Bit 11, Center 22 (6 ~ 38) 33
3323 11:35:28.840425 iDelay=42, Bit 12, Center 21 (5 ~ 38) 34
3324 11:35:28.847453 iDelay=42, Bit 13, Center 22 (7 ~ 38) 32
3325 11:35:28.851059 iDelay=42, Bit 14, Center 22 (6 ~ 38) 33
3326 11:35:28.854232 iDelay=42, Bit 15, Center 15 (1 ~ 30) 30
3327 11:35:28.854703 ==
3328 11:35:28.857580 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3329 11:35:28.860641 fsp= 1, odt_onoff= 1, Byte mode= 0
3330 11:35:28.861030 ==
3331 11:35:28.864399 DQS Delay:
3332 11:35:28.864786 DQS0 = 0, DQS1 = 0
3333 11:35:28.865087 DQM Delay:
3334 11:35:28.867518 DQM0 = 21, DQM1 = 19
3335 11:35:28.867908 DQ Delay:
3336 11:35:28.870930 DQ0 =24, DQ1 =23, DQ2 =19, DQ3 =18
3337 11:35:28.874271 DQ4 =21, DQ5 =24, DQ6 =24, DQ7 =22
3338 11:35:28.877620 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22
3339 11:35:28.880413 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =15
3340 11:35:28.880769
3341 11:35:28.881048
3342 11:35:28.883978 DramC Write-DBI off
3343 11:35:28.884332 ==
3344 11:35:28.887125 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3345 11:35:28.890926 fsp= 1, odt_onoff= 1, Byte mode= 0
3346 11:35:28.894163 ==
3347 11:35:28.897091 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3348 11:35:28.897480
3349 11:35:28.900539 Begin, DQ Scan Range 928~1184
3350 11:35:28.900895
3351 11:35:28.901198
3352 11:35:28.901460 TX Vref Scan disable
3353 11:35:28.903926 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3354 11:35:28.906995 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3355 11:35:28.913617 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3356 11:35:28.916942 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3357 11:35:28.920534 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3358 11:35:28.924148 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3359 11:35:28.926819 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3360 11:35:28.930399 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3361 11:35:28.933604 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3362 11:35:28.936855 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3363 11:35:28.940386 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3364 11:35:28.944136 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3365 11:35:28.946996 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3366 11:35:28.950110 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3367 11:35:28.953554 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3368 11:35:28.956565 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3369 11:35:28.959734 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3370 11:35:28.966763 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3371 11:35:28.969891 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3372 11:35:28.973621 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3373 11:35:28.976811 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3374 11:35:28.980390 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3375 11:35:28.983767 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3376 11:35:28.986835 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3377 11:35:28.990070 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3378 11:35:28.993192 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3379 11:35:28.996503 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3380 11:35:29.000174 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3381 11:35:29.003625 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3382 11:35:29.006368 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3383 11:35:29.009722 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3384 11:35:29.013415 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3385 11:35:29.019789 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3386 11:35:29.022947 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3387 11:35:29.026264 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3388 11:35:29.029749 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3389 11:35:29.032991 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3390 11:35:29.036373 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3391 11:35:29.039730 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3392 11:35:29.043043 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3393 11:35:29.046156 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3394 11:35:29.049703 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3395 11:35:29.053169 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3396 11:35:29.057144 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3397 11:35:29.060344 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3398 11:35:29.062706 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3399 11:35:29.066648 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3400 11:35:29.069623 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3401 11:35:29.073384 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
3402 11:35:29.076545 977 |3 6 17|[0] xxxxxxxx ooxxxxxo [MSB]
3403 11:35:29.079495 978 |3 6 18|[0] xxxxxxxx ooxxxxxo [MSB]
3404 11:35:29.082935 979 |3 6 19|[0] xxxxxxxx oooxxxxo [MSB]
3405 11:35:29.089890 980 |3 6 20|[0] xxxxxxxx oooxxxoo [MSB]
3406 11:35:29.092665 981 |3 6 21|[0] xxxxxxxx oooooxoo [MSB]
3407 11:35:29.096042 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3408 11:35:29.099699 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3409 11:35:29.102646 984 |3 6 24|[0] xooooxoo oooooooo [MSB]
3410 11:35:29.106298 985 |3 6 25|[0] xooooooo oooooooo [MSB]
3411 11:35:29.109687 994 |3 6 34|[0] oooooooo ooooooox [MSB]
3412 11:35:29.113179 995 |3 6 35|[0] oooooooo oxooooox [MSB]
3413 11:35:29.115850 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3414 11:35:29.122515 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3415 11:35:29.126522 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3416 11:35:29.129491 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3417 11:35:29.132930 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
3418 11:35:29.136267 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
3419 11:35:29.139300 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
3420 11:35:29.142502 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
3421 11:35:29.145756 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
3422 11:35:29.148911 1005 |3 6 45|[0] ooxxoooo xxxxxxxx [MSB]
3423 11:35:29.152346 1006 |3 6 46|[0] oxxxooxx xxxxxxxx [MSB]
3424 11:35:29.156122 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3425 11:35:29.159192 Byte0, DQ PI dly=994, DQM PI dly= 994
3426 11:35:29.165714 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 34)
3427 11:35:29.166100
3428 11:35:29.169206 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 34)
3429 11:35:29.169594
3430 11:35:29.173398 Byte1, DQ PI dly=986, DQM PI dly= 986
3431 11:35:29.175759 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3432 11:35:29.176146
3433 11:35:29.183101 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3434 11:35:29.183491
3435 11:35:29.183791 ==
3436 11:35:29.185965 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3437 11:35:29.189213 fsp= 1, odt_onoff= 1, Byte mode= 0
3438 11:35:29.189600 ==
3439 11:35:29.195583 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3440 11:35:29.195971
3441 11:35:29.198904 Begin, DQ Scan Range 962~1026
3442 11:35:29.199292 Write Rank1 MR14 =0x0
3443 11:35:29.207379
3444 11:35:29.207761 CH=1, VrefRange= 0, VrefLevel = 0
3445 11:35:29.214101 TX Bit0 (987~1001) 15 994, Bit8 (981~991) 11 986,
3446 11:35:29.217252 TX Bit1 (986~999) 14 992, Bit9 (980~991) 12 985,
3447 11:35:29.224027 TX Bit2 (984~998) 15 991, Bit10 (983~993) 11 988,
3448 11:35:29.227003 TX Bit3 (982~995) 14 988, Bit11 (983~995) 13 989,
3449 11:35:29.231294 TX Bit4 (985~1001) 17 993, Bit12 (983~994) 12 988,
3450 11:35:29.237749 TX Bit5 (987~999) 13 993, Bit13 (984~993) 10 988,
3451 11:35:29.240942 TX Bit6 (986~1000) 15 993, Bit14 (983~994) 12 988,
3452 11:35:29.247671 TX Bit7 (986~1000) 15 993, Bit15 (976~987) 12 981,
3453 11:35:29.248105
3454 11:35:29.250103 wait MRW command Rank1 MR14 =0x2 fired (1)
3455 11:35:29.250489 Write Rank1 MR14 =0x2
3456 11:35:29.259876
3457 11:35:29.260271 CH=1, VrefRange= 0, VrefLevel = 2
3458 11:35:29.266375 TX Bit0 (987~1001) 15 994, Bit8 (979~992) 14 985,
3459 11:35:29.270007 TX Bit1 (986~1000) 15 993, Bit9 (980~991) 12 985,
3460 11:35:29.276199 TX Bit2 (984~999) 16 991, Bit10 (982~994) 13 988,
3461 11:35:29.279455 TX Bit3 (982~996) 15 989, Bit11 (983~996) 14 989,
3462 11:35:29.283048 TX Bit4 (985~1001) 17 993, Bit12 (983~995) 13 989,
3463 11:35:29.289879 TX Bit5 (987~1000) 14 993, Bit13 (984~994) 11 989,
3464 11:35:29.293395 TX Bit6 (986~1000) 15 993, Bit14 (983~994) 12 988,
3465 11:35:29.299675 TX Bit7 (986~1000) 15 993, Bit15 (976~988) 13 982,
3466 11:35:29.300064
3467 11:35:29.300364 Write Rank1 MR14 =0x4
3468 11:35:29.308431
3469 11:35:29.308814 CH=1, VrefRange= 0, VrefLevel = 4
3470 11:35:29.315212 TX Bit0 (987~1002) 16 994, Bit8 (979~992) 14 985,
3471 11:35:29.318190 TX Bit1 (986~1001) 16 993, Bit9 (979~991) 13 985,
3472 11:35:29.325169 TX Bit2 (984~999) 16 991, Bit10 (982~995) 14 988,
3473 11:35:29.328868 TX Bit3 (981~997) 17 989, Bit11 (982~997) 16 989,
3474 11:35:29.332253 TX Bit4 (985~1002) 18 993, Bit12 (983~994) 12 988,
3475 11:35:29.338341 TX Bit5 (987~1001) 15 994, Bit13 (984~995) 12 989,
3476 11:35:29.341575 TX Bit6 (985~1001) 17 993, Bit14 (982~994) 13 988,
3477 11:35:29.348074 TX Bit7 (985~1001) 17 993, Bit15 (975~990) 16 982,
3478 11:35:29.348465
3479 11:35:29.348767 Write Rank1 MR14 =0x6
3480 11:35:29.357804
3481 11:35:29.358187 CH=1, VrefRange= 0, VrefLevel = 6
3482 11:35:29.364429 TX Bit0 (987~1003) 17 995, Bit8 (978~993) 16 985,
3483 11:35:29.367259 TX Bit1 (985~1001) 17 993, Bit9 (978~992) 15 985,
3484 11:35:29.374272 TX Bit2 (984~1000) 17 992, Bit10 (982~995) 14 988,
3485 11:35:29.377426 TX Bit3 (981~998) 18 989, Bit11 (982~998) 17 990,
3486 11:35:29.380677 TX Bit4 (984~1003) 20 993, Bit12 (983~995) 13 989,
3487 11:35:29.387239 TX Bit5 (986~1002) 17 994, Bit13 (983~996) 14 989,
3488 11:35:29.390528 TX Bit6 (985~1002) 18 993, Bit14 (982~995) 14 988,
3489 11:35:29.397233 TX Bit7 (986~1002) 17 994, Bit15 (975~991) 17 983,
3490 11:35:29.397623
3491 11:35:29.397923 Write Rank1 MR14 =0x8
3492 11:35:29.406858
3493 11:35:29.407242 CH=1, VrefRange= 0, VrefLevel = 8
3494 11:35:29.413304 TX Bit0 (986~1004) 19 995, Bit8 (977~993) 17 985,
3495 11:35:29.416868 TX Bit1 (985~1002) 18 993, Bit9 (978~992) 15 985,
3496 11:35:29.423918 TX Bit2 (983~1001) 19 992, Bit10 (981~996) 16 988,
3497 11:35:29.426746 TX Bit3 (980~999) 20 989, Bit11 (982~998) 17 990,
3498 11:35:29.429869 TX Bit4 (984~1003) 20 993, Bit12 (983~997) 15 990,
3499 11:35:29.445641 TX Bit5 (986~1003) 18 994, Bit13 (983~996) 14 989,
3500 11:35:29.445731 TX Bit6 (985~1002) 18 993, Bit14 (981~996) 16 988,
3501 11:35:29.446320 TX Bit7 (985~1003) 19 994, Bit15 (974~991) 18 982,
3502 11:35:29.446395
3503 11:35:29.446454 Write Rank1 MR14 =0xa
3504 11:35:29.455828
3505 11:35:29.459150 CH=1, VrefRange= 0, VrefLevel = 10
3506 11:35:29.463176 TX Bit0 (986~1005) 20 995, Bit8 (977~993) 17 985,
3507 11:35:29.465876 TX Bit1 (985~1003) 19 994, Bit9 (978~992) 15 985,
3508 11:35:29.472628 TX Bit2 (982~1002) 21 992, Bit10 (981~997) 17 989,
3509 11:35:29.475584 TX Bit3 (980~999) 20 989, Bit11 (981~999) 19 990,
3510 11:35:29.479089 TX Bit4 (984~1004) 21 994, Bit12 (982~998) 17 990,
3511 11:35:29.485504 TX Bit5 (986~1004) 19 995, Bit13 (983~998) 16 990,
3512 11:35:29.488999 TX Bit6 (985~1003) 19 994, Bit14 (981~997) 17 989,
3513 11:35:29.495915 TX Bit7 (985~1003) 19 994, Bit15 (974~992) 19 983,
3514 11:35:29.495997
3515 11:35:29.496059 Write Rank1 MR14 =0xc
3516 11:35:29.505287
3517 11:35:29.508626 CH=1, VrefRange= 0, VrefLevel = 12
3518 11:35:29.511824 TX Bit0 (986~1005) 20 995, Bit8 (977~994) 18 985,
3519 11:35:29.515110 TX Bit1 (985~1005) 21 995, Bit9 (977~993) 17 985,
3520 11:35:29.521975 TX Bit2 (982~1002) 21 992, Bit10 (980~998) 19 989,
3521 11:35:29.525477 TX Bit3 (980~1000) 21 990, Bit11 (981~999) 19 990,
3522 11:35:29.528510 TX Bit4 (984~1005) 22 994, Bit12 (982~998) 17 990,
3523 11:35:29.535622 TX Bit5 (985~1005) 21 995, Bit13 (983~999) 17 991,
3524 11:35:29.538877 TX Bit6 (984~1004) 21 994, Bit14 (981~998) 18 989,
3525 11:35:29.545274 TX Bit7 (985~1004) 20 994, Bit15 (973~992) 20 982,
3526 11:35:29.545552
3527 11:35:29.545764 Write Rank1 MR14 =0xe
3528 11:35:29.555659
3529 11:35:29.558913 CH=1, VrefRange= 0, VrefLevel = 14
3530 11:35:29.562073 TX Bit0 (986~1006) 21 996, Bit8 (976~994) 19 985,
3531 11:35:29.565552 TX Bit1 (984~1005) 22 994, Bit9 (977~993) 17 985,
3532 11:35:29.571884 TX Bit2 (981~1003) 23 992, Bit10 (980~998) 19 989,
3533 11:35:29.575453 TX Bit3 (979~1000) 22 989, Bit11 (981~999) 19 990,
3534 11:35:29.578631 TX Bit4 (984~1005) 22 994, Bit12 (982~999) 18 990,
3535 11:35:29.585303 TX Bit5 (985~1006) 22 995, Bit13 (982~999) 18 990,
3536 11:35:29.588583 TX Bit6 (984~1005) 22 994, Bit14 (980~998) 19 989,
3537 11:35:29.595267 TX Bit7 (985~1005) 21 995, Bit15 (973~992) 20 982,
3538 11:35:29.595658
3539 11:35:29.595954 Write Rank1 MR14 =0x10
3540 11:35:29.605318
3541 11:35:29.608474 CH=1, VrefRange= 0, VrefLevel = 16
3542 11:35:29.611981 TX Bit0 (986~1006) 21 996, Bit8 (976~995) 20 985,
3543 11:35:29.615106 TX Bit1 (985~1005) 21 995, Bit9 (977~994) 18 985,
3544 11:35:29.622013 TX Bit2 (982~1003) 22 992, Bit10 (980~998) 19 989,
3545 11:35:29.625620 TX Bit3 (979~1001) 23 990, Bit11 (980~1000) 21 990,
3546 11:35:29.628899 TX Bit4 (983~1006) 24 994, Bit12 (981~999) 19 990,
3547 11:35:29.635505 TX Bit5 (985~1006) 22 995, Bit13 (982~999) 18 990,
3548 11:35:29.638776 TX Bit6 (984~1005) 22 994, Bit14 (980~999) 20 989,
3549 11:35:29.645016 TX Bit7 (984~1005) 22 994, Bit15 (973~993) 21 983,
3550 11:35:29.645431
3551 11:35:29.645730 Write Rank1 MR14 =0x12
3552 11:35:29.655228
3553 11:35:29.658860 CH=1, VrefRange= 0, VrefLevel = 18
3554 11:35:29.661797 TX Bit0 (985~1006) 22 995, Bit8 (976~996) 21 986,
3555 11:35:29.665396 TX Bit1 (984~1006) 23 995, Bit9 (976~994) 19 985,
3556 11:35:29.671701 TX Bit2 (981~1005) 25 993, Bit10 (979~999) 21 989,
3557 11:35:29.674964 TX Bit3 (979~1001) 23 990, Bit11 (980~1000) 21 990,
3558 11:35:29.681631 TX Bit4 (983~1006) 24 994, Bit12 (981~999) 19 990,
3559 11:35:29.685728 TX Bit5 (985~1006) 22 995, Bit13 (982~1000) 19 991,
3560 11:35:29.688110 TX Bit6 (983~1006) 24 994, Bit14 (979~999) 21 989,
3561 11:35:29.694861 TX Bit7 (984~1006) 23 995, Bit15 (972~993) 22 982,
3562 11:35:29.695254
3563 11:35:29.695552 Write Rank1 MR14 =0x14
3564 11:35:29.705345
3565 11:35:29.708807 CH=1, VrefRange= 0, VrefLevel = 20
3566 11:35:29.712248 TX Bit0 (985~1007) 23 996, Bit8 (975~996) 22 985,
3567 11:35:29.715514 TX Bit1 (984~1006) 23 995, Bit9 (976~995) 20 985,
3568 11:35:29.721799 TX Bit2 (981~1005) 25 993, Bit10 (978~999) 22 988,
3569 11:35:29.724960 TX Bit3 (979~1002) 24 990, Bit11 (980~1000) 21 990,
3570 11:35:29.728439 TX Bit4 (983~1006) 24 994, Bit12 (980~999) 20 989,
3571 11:35:29.735395 TX Bit5 (984~1006) 23 995, Bit13 (981~1000) 20 990,
3572 11:35:29.738303 TX Bit6 (984~1006) 23 995, Bit14 (979~999) 21 989,
3573 11:35:29.745681 TX Bit7 (984~1006) 23 995, Bit15 (971~994) 24 982,
3574 11:35:29.746069
3575 11:35:29.746367 Write Rank1 MR14 =0x16
3576 11:35:29.755395
3577 11:35:29.758553 CH=1, VrefRange= 0, VrefLevel = 22
3578 11:35:29.762235 TX Bit0 (985~1007) 23 996, Bit8 (975~997) 23 986,
3579 11:35:29.765942 TX Bit1 (984~1006) 23 995, Bit9 (976~995) 20 985,
3580 11:35:29.772447 TX Bit2 (980~1005) 26 992, Bit10 (978~1000) 23 989,
3581 11:35:29.775354 TX Bit3 (979~1002) 24 990, Bit11 (979~1001) 23 990,
3582 11:35:29.781847 TX Bit4 (982~1006) 25 994, Bit12 (979~1000) 22 989,
3583 11:35:29.785144 TX Bit5 (984~1006) 23 995, Bit13 (981~1000) 20 990,
3584 11:35:29.788971 TX Bit6 (983~1006) 24 994, Bit14 (979~999) 21 989,
3585 11:35:29.795472 TX Bit7 (984~1006) 23 995, Bit15 (971~994) 24 982,
3586 11:35:29.795863
3587 11:35:29.796162 Write Rank1 MR14 =0x18
3588 11:35:29.805434
3589 11:35:29.809095 CH=1, VrefRange= 0, VrefLevel = 24
3590 11:35:29.812362 TX Bit0 (985~1007) 23 996, Bit8 (975~998) 24 986,
3591 11:35:29.815387 TX Bit1 (983~1007) 25 995, Bit9 (975~996) 22 985,
3592 11:35:29.822389 TX Bit2 (980~1006) 27 993, Bit10 (978~1000) 23 989,
3593 11:35:29.826106 TX Bit3 (979~1002) 24 990, Bit11 (979~1001) 23 990,
3594 11:35:29.832037 TX Bit4 (982~1007) 26 994, Bit12 (979~1000) 22 989,
3595 11:35:29.835200 TX Bit5 (984~1007) 24 995, Bit13 (981~1000) 20 990,
3596 11:35:29.838976 TX Bit6 (982~1006) 25 994, Bit14 (978~1000) 23 989,
3597 11:35:29.845726 TX Bit7 (983~1006) 24 994, Bit15 (971~995) 25 983,
3598 11:35:29.846114
3599 11:35:29.846411 Write Rank1 MR14 =0x1a
3600 11:35:29.856244
3601 11:35:29.859201 CH=1, VrefRange= 0, VrefLevel = 26
3602 11:35:29.862692 TX Bit0 (984~1007) 24 995, Bit8 (975~998) 24 986,
3603 11:35:29.866088 TX Bit1 (983~1007) 25 995, Bit9 (975~997) 23 986,
3604 11:35:29.872725 TX Bit2 (980~1006) 27 993, Bit10 (977~1000) 24 988,
3605 11:35:29.875715 TX Bit3 (979~1003) 25 991, Bit11 (978~1001) 24 989,
3606 11:35:29.882885 TX Bit4 (982~1007) 26 994, Bit12 (979~1000) 22 989,
3607 11:35:29.885715 TX Bit5 (984~1007) 24 995, Bit13 (980~1001) 22 990,
3608 11:35:29.889214 TX Bit6 (982~1007) 26 994, Bit14 (978~1000) 23 989,
3609 11:35:29.896269 TX Bit7 (983~1007) 25 995, Bit15 (971~995) 25 983,
3610 11:35:29.896695
3611 11:35:29.897175 Write Rank1 MR14 =0x1c
3612 11:35:29.906321
3613 11:35:29.909831 CH=1, VrefRange= 0, VrefLevel = 28
3614 11:35:29.913294 TX Bit0 (984~1008) 25 996, Bit8 (974~998) 25 986,
3615 11:35:29.916480 TX Bit1 (984~1007) 24 995, Bit9 (975~998) 24 986,
3616 11:35:29.923252 TX Bit2 (980~1006) 27 993, Bit10 (977~1000) 24 988,
3617 11:35:29.926845 TX Bit3 (978~1004) 27 991, Bit11 (978~1001) 24 989,
3618 11:35:29.933285 TX Bit4 (982~1007) 26 994, Bit12 (979~1001) 23 990,
3619 11:35:29.936367 TX Bit5 (983~1007) 25 995, Bit13 (980~1001) 22 990,
3620 11:35:29.939591 TX Bit6 (982~1007) 26 994, Bit14 (977~1000) 24 988,
3621 11:35:29.946195 TX Bit7 (982~1007) 26 994, Bit15 (970~995) 26 982,
3622 11:35:29.946734
3623 11:35:29.947048 Write Rank1 MR14 =0x1e
3624 11:35:29.957238
3625 11:35:29.961051 CH=1, VrefRange= 0, VrefLevel = 30
3626 11:35:29.963988 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
3627 11:35:29.967341 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
3628 11:35:29.973762 TX Bit2 (980~1006) 27 993, Bit10 (977~1000) 24 988,
3629 11:35:29.976910 TX Bit3 (978~1004) 27 991, Bit11 (978~1001) 24 989,
3630 11:35:29.983595 TX Bit4 (983~1007) 25 995, Bit12 (978~1001) 24 989,
3631 11:35:29.987159 TX Bit5 (983~1007) 25 995, Bit13 (978~1001) 24 989,
3632 11:35:29.989985 TX Bit6 (982~1007) 26 994, Bit14 (977~1000) 24 988,
3633 11:35:29.996870 TX Bit7 (982~1007) 26 994, Bit15 (970~995) 26 982,
3634 11:35:29.997308
3635 11:35:30.000295 Write Rank1 MR14 =0x20
3636 11:35:30.008108
3637 11:35:30.010967 CH=1, VrefRange= 0, VrefLevel = 32
3638 11:35:30.014124 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
3639 11:35:30.017701 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
3640 11:35:30.023999 TX Bit2 (980~1006) 27 993, Bit10 (977~1000) 24 988,
3641 11:35:30.027757 TX Bit3 (978~1004) 27 991, Bit11 (978~1001) 24 989,
3642 11:35:30.034615 TX Bit4 (983~1007) 25 995, Bit12 (978~1001) 24 989,
3643 11:35:30.037388 TX Bit5 (983~1007) 25 995, Bit13 (978~1001) 24 989,
3644 11:35:30.041214 TX Bit6 (982~1007) 26 994, Bit14 (977~1000) 24 988,
3645 11:35:30.047659 TX Bit7 (982~1007) 26 994, Bit15 (970~995) 26 982,
3646 11:35:30.048099
3647 11:35:30.048402 Write Rank1 MR14 =0x22
3648 11:35:30.058084
3649 11:35:30.061279 CH=1, VrefRange= 0, VrefLevel = 34
3650 11:35:30.064913 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
3651 11:35:30.068096 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
3652 11:35:30.075361 TX Bit2 (980~1006) 27 993, Bit10 (977~1000) 24 988,
3653 11:35:30.078380 TX Bit3 (978~1004) 27 991, Bit11 (978~1001) 24 989,
3654 11:35:30.085045 TX Bit4 (983~1007) 25 995, Bit12 (978~1001) 24 989,
3655 11:35:30.088456 TX Bit5 (983~1007) 25 995, Bit13 (978~1001) 24 989,
3656 11:35:30.091503 TX Bit6 (982~1007) 26 994, Bit14 (977~1000) 24 988,
3657 11:35:30.098151 TX Bit7 (982~1007) 26 994, Bit15 (970~995) 26 982,
3658 11:35:30.098546
3659 11:35:30.098847 Write Rank1 MR14 =0x24
3660 11:35:30.108965
3661 11:35:30.111963 CH=1, VrefRange= 0, VrefLevel = 36
3662 11:35:30.115042 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
3663 11:35:30.118692 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
3664 11:35:30.125036 TX Bit2 (980~1006) 27 993, Bit10 (977~1000) 24 988,
3665 11:35:30.128517 TX Bit3 (978~1004) 27 991, Bit11 (978~1001) 24 989,
3666 11:35:30.135520 TX Bit4 (983~1007) 25 995, Bit12 (978~1001) 24 989,
3667 11:35:30.138919 TX Bit5 (983~1007) 25 995, Bit13 (978~1001) 24 989,
3668 11:35:30.141912 TX Bit6 (982~1007) 26 994, Bit14 (977~1000) 24 988,
3669 11:35:30.148276 TX Bit7 (982~1007) 26 994, Bit15 (970~995) 26 982,
3670 11:35:30.148680
3671 11:35:30.148983 Write Rank1 MR14 =0x26
3672 11:35:30.159372
3673 11:35:30.159760 CH=1, VrefRange= 0, VrefLevel = 38
3674 11:35:30.165779 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
3675 11:35:30.169228 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
3676 11:35:30.175469 TX Bit2 (980~1006) 27 993, Bit10 (977~1000) 24 988,
3677 11:35:30.178832 TX Bit3 (978~1004) 27 991, Bit11 (978~1001) 24 989,
3678 11:35:30.185551 TX Bit4 (983~1007) 25 995, Bit12 (978~1001) 24 989,
3679 11:35:30.188967 TX Bit5 (983~1007) 25 995, Bit13 (978~1001) 24 989,
3680 11:35:30.192665 TX Bit6 (982~1007) 26 994, Bit14 (977~1000) 24 988,
3681 11:35:30.198769 TX Bit7 (982~1007) 26 994, Bit15 (970~995) 26 982,
3682 11:35:30.199168
3683 11:35:30.199466
3684 11:35:30.202494 TX Vref found, early break! 369< 383
3685 11:35:30.205456 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =833/100 ps
3686 11:35:30.208809 u1DelayCellOfst[0]=5 cells (5 PI)
3687 11:35:30.212220 u1DelayCellOfst[1]=3 cells (3 PI)
3688 11:35:30.215254 u1DelayCellOfst[2]=2 cells (2 PI)
3689 11:35:30.219485 u1DelayCellOfst[3]=0 cells (0 PI)
3690 11:35:30.221858 u1DelayCellOfst[4]=4 cells (4 PI)
3691 11:35:30.225675 u1DelayCellOfst[5]=4 cells (4 PI)
3692 11:35:30.229082 u1DelayCellOfst[6]=3 cells (3 PI)
3693 11:35:30.232228 u1DelayCellOfst[7]=3 cells (3 PI)
3694 11:35:30.235233 Byte0, DQ PI dly=991, DQM PI dly= 993
3695 11:35:30.239300 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
3696 11:35:30.239790
3697 11:35:30.242091 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
3698 11:35:30.242592
3699 11:35:30.245609 u1DelayCellOfst[8]=4 cells (4 PI)
3700 11:35:30.248602 u1DelayCellOfst[9]=4 cells (4 PI)
3701 11:35:30.251782 u1DelayCellOfst[10]=7 cells (6 PI)
3702 11:35:30.255579 u1DelayCellOfst[11]=8 cells (7 PI)
3703 11:35:30.258440 u1DelayCellOfst[12]=8 cells (7 PI)
3704 11:35:30.261624 u1DelayCellOfst[13]=8 cells (7 PI)
3705 11:35:30.266294 u1DelayCellOfst[14]=7 cells (6 PI)
3706 11:35:30.268910 u1DelayCellOfst[15]=0 cells (0 PI)
3707 11:35:30.271883 Byte1, DQ PI dly=982, DQM PI dly= 985
3708 11:35:30.275467 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
3709 11:35:30.275954
3710 11:35:30.278777 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
3711 11:35:30.279180
3712 11:35:30.282369 Write Rank1 MR14 =0x1e
3713 11:35:30.282784
3714 11:35:30.285095 Final TX Range 0 Vref 30
3715 11:35:30.285528
3716 11:35:30.291988 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3717 11:35:30.292384
3718 11:35:30.298208 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3719 11:35:30.304896 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3720 11:35:30.312019 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3721 11:35:30.315647 wait MRW command Rank1 MR3 =0xb0 fired (1)
3722 11:35:30.318489 Write Rank1 MR3 =0xb0
3723 11:35:30.318879 DramC Write-DBI on
3724 11:35:30.319266 ==
3725 11:35:30.324994 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3726 11:35:30.327967 fsp= 1, odt_onoff= 1, Byte mode= 0
3727 11:35:30.328363 ==
3728 11:35:30.331328 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3729 11:35:30.331727
3730 11:35:30.335197 Begin, DQ Scan Range 705~769
3731 11:35:30.335577
3732 11:35:30.335870
3733 11:35:30.338445 TX Vref Scan disable
3734 11:35:30.341735 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3735 11:35:30.344795 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3736 11:35:30.348180 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3737 11:35:30.352119 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3738 11:35:30.355071 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3739 11:35:30.358343 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3740 11:35:30.361479 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3741 11:35:30.365108 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3742 11:35:30.368199 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3743 11:35:30.371248 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3744 11:35:30.375059 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3745 11:35:30.378302 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3746 11:35:30.381222 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3747 11:35:30.385170 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3748 11:35:30.387860 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3749 11:35:30.391942 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3750 11:35:30.397980 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3751 11:35:30.402263 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3752 11:35:30.404550 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3753 11:35:30.408241 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3754 11:35:30.411347 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3755 11:35:30.414605 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3756 11:35:30.417695 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3757 11:35:30.425218 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3758 11:35:30.428814 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3759 11:35:30.432063 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3760 11:35:30.435505 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3761 11:35:30.438935 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3762 11:35:30.442340 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3763 11:35:30.445181 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3764 11:35:30.448723 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3765 11:35:30.451675 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3766 11:35:30.455454 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
3767 11:35:30.458796 754 |2 6 50|[0] xxxxxxxx xxxxxxxx [MSB]
3768 11:35:30.461934 Byte0, DQ PI dly=740, DQM PI dly= 740
3769 11:35:30.468576 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 36)
3770 11:35:30.469092
3771 11:35:30.471992 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 36)
3772 11:35:30.472486
3773 11:35:30.475641 Byte1, DQ PI dly=730, DQM PI dly= 730
3774 11:35:30.478413 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3775 11:35:30.478890
3776 11:35:30.485812 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3777 11:35:30.486198
3778 11:35:30.491529 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3779 11:35:30.498118 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3780 11:35:30.504803 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3781 11:35:30.505228 Write Rank1 MR3 =0x30
3782 11:35:30.507901 DramC Write-DBI off
3783 11:35:30.508290
3784 11:35:30.508679 [DATLAT]
3785 11:35:30.511518 Freq=1600, CH1 RK1, use_rxtx_scan=0
3786 11:35:30.511951
3787 11:35:30.515592 DATLAT Default: 0x10
3788 11:35:30.516117 7, 0xFFFF, sum=0
3789 11:35:30.518194 8, 0xFFFF, sum=0
3790 11:35:30.518594 9, 0xFFFF, sum=0
3791 11:35:30.521638 10, 0xFFFF, sum=0
3792 11:35:30.522039 11, 0xFFFF, sum=0
3793 11:35:30.525582 12, 0xFFFF, sum=0
3794 11:35:30.525986 13, 0xFFFF, sum=0
3795 11:35:30.528196 14, 0x0, sum=1
3796 11:35:30.528595 15, 0x0, sum=2
3797 11:35:30.528994 16, 0x0, sum=3
3798 11:35:30.531587 17, 0x0, sum=4
3799 11:35:30.534687 pattern=2 first_step=14 total pass=5 best_step=16
3800 11:35:30.535172 ==
3801 11:35:30.541095 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3802 11:35:30.544183 fsp= 1, odt_onoff= 1, Byte mode= 0
3803 11:35:30.544661 ==
3804 11:35:30.547878 Start DQ dly to find pass range UseTestEngine =1
3805 11:35:30.551190 x-axis: bit #, y-axis: DQ dly (-127~63)
3806 11:35:30.554199 RX Vref Scan = 0
3807 11:35:30.557599 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3808 11:35:30.561042 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3809 11:35:30.561573 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3810 11:35:30.564180 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3811 11:35:30.567919 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3812 11:35:30.570800 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3813 11:35:30.574054 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3814 11:35:30.577536 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3815 11:35:30.580802 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3816 11:35:30.584014 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3817 11:35:30.584445 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3818 11:35:30.588128 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3819 11:35:30.590746 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3820 11:35:30.594105 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3821 11:35:30.597615 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3822 11:35:30.600682 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3823 11:35:30.604164 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3824 11:35:30.607644 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3825 11:35:30.608088 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3826 11:35:30.610561 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3827 11:35:30.614120 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3828 11:35:30.617684 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3829 11:35:30.620598 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3830 11:35:30.624213 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3831 11:35:30.627080 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3832 11:35:30.630647 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3833 11:35:30.631050 0, [0] xxxxxxxx xxxxxxxo [MSB]
3834 11:35:30.633985 1, [0] xxxxxxxx xxxxxxxo [MSB]
3835 11:35:30.637299 2, [0] xxxxxxxx xoxxxxxo [MSB]
3836 11:35:30.640746 3, [0] xxxoxxxx ooxxxxxo [MSB]
3837 11:35:30.643741 4, [0] xxxoxxxx ooxxxxxo [MSB]
3838 11:35:30.644239 5, [0] xxoooxxx ooxxxxxo [MSB]
3839 11:35:30.647100 6, [0] xxoooxxx oooxxxxo [MSB]
3840 11:35:30.650757 7, [0] oooooxxx oooooooo [MSB]
3841 11:35:30.654227 8, [0] ooooooxo oooooooo [MSB]
3842 11:35:30.657225 30, [0] oooooooo ooooooox [MSB]
3843 11:35:30.660644 31, [0] oooooooo ooooooox [MSB]
3844 11:35:30.663836 32, [0] oooooooo ooooooox [MSB]
3845 11:35:30.666920 33, [0] oooooooo oxooooox [MSB]
3846 11:35:30.670521 34, [0] oooooooo xxooooox [MSB]
3847 11:35:30.673771 35, [0] oooxoooo xxooooox [MSB]
3848 11:35:30.676889 36, [0] ooxxoooo xxooooox [MSB]
3849 11:35:30.677321 37, [0] ooxxooox xxxoxoxx [MSB]
3850 11:35:30.680966 38, [0] oxxxxoox xxxxxxxx [MSB]
3851 11:35:30.683609 39, [0] xxxxxoox xxxxxxxx [MSB]
3852 11:35:30.686979 40, [0] xxxxxxox xxxxxxxx [MSB]
3853 11:35:30.690312 41, [0] xxxxxxxx xxxxxxxx [MSB]
3854 11:35:30.693409 iDelay=41, Bit 0, Center 22 (7 ~ 38) 32
3855 11:35:30.697224 iDelay=41, Bit 1, Center 22 (7 ~ 37) 31
3856 11:35:30.700428 iDelay=41, Bit 2, Center 20 (5 ~ 35) 31
3857 11:35:30.703319 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
3858 11:35:30.706542 iDelay=41, Bit 4, Center 21 (5 ~ 37) 33
3859 11:35:30.710200 iDelay=41, Bit 5, Center 23 (8 ~ 39) 32
3860 11:35:30.713718 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
3861 11:35:30.716717 iDelay=41, Bit 7, Center 22 (8 ~ 36) 29
3862 11:35:30.720773 iDelay=41, Bit 8, Center 18 (3 ~ 33) 31
3863 11:35:30.723425 iDelay=41, Bit 9, Center 17 (2 ~ 32) 31
3864 11:35:30.729730 iDelay=41, Bit 10, Center 21 (6 ~ 36) 31
3865 11:35:30.733476 iDelay=41, Bit 11, Center 22 (7 ~ 37) 31
3866 11:35:30.736315 iDelay=41, Bit 12, Center 21 (7 ~ 36) 30
3867 11:35:30.739609 iDelay=41, Bit 13, Center 22 (7 ~ 37) 31
3868 11:35:30.743194 iDelay=41, Bit 14, Center 21 (7 ~ 36) 30
3869 11:35:30.746384 iDelay=41, Bit 15, Center 14 (0 ~ 29) 30
3870 11:35:30.746782 ==
3871 11:35:30.753265 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3872 11:35:30.756324 fsp= 1, odt_onoff= 1, Byte mode= 0
3873 11:35:30.756754 ==
3874 11:35:30.757062 DQS Delay:
3875 11:35:30.759857 DQS0 = 0, DQS1 = 0
3876 11:35:30.760241 DQM Delay:
3877 11:35:30.760538 DQM0 = 21, DQM1 = 19
3878 11:35:30.763017 DQ Delay:
3879 11:35:30.766094 DQ0 =22, DQ1 =22, DQ2 =20, DQ3 =18
3880 11:35:30.770345 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3881 11:35:30.772990 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3882 11:35:30.775950 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =14
3883 11:35:30.776337
3884 11:35:30.776638
3885 11:35:30.776947
3886 11:35:30.779756 [DramC_TX_OE_Calibration] TA2
3887 11:35:30.782787 Original DQ_B0 (3 6) =30, OEN = 27
3888 11:35:30.783177 Original DQ_B1 (3 6) =30, OEN = 27
3889 11:35:30.786089 23, 0x0, End_B0=23 End_B1=23
3890 11:35:30.789277 24, 0x0, End_B0=24 End_B1=24
3891 11:35:30.793485 25, 0x0, End_B0=25 End_B1=25
3892 11:35:30.796044 26, 0x0, End_B0=26 End_B1=26
3893 11:35:30.796447 27, 0x0, End_B0=27 End_B1=27
3894 11:35:30.799621 28, 0x0, End_B0=28 End_B1=28
3895 11:35:30.802824 29, 0x0, End_B0=29 End_B1=29
3896 11:35:30.806512 30, 0x0, End_B0=30 End_B1=30
3897 11:35:30.809413 31, 0xFFFF, End_B0=30 End_B1=30
3898 11:35:30.813037 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3899 11:35:30.819326 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3900 11:35:30.819775
3901 11:35:30.820071
3902 11:35:30.822625 Write Rank1 MR23 =0x3f
3903 11:35:30.823007 [DQSOSC]
3904 11:35:30.829466 [DQSOSCAuto] RK1, (LSB)MR18= 0xd5d5, (MSB)MR19= 0x202, tDQSOscB0 = 434 ps tDQSOscB1 = 434 ps
3905 11:35:30.835748 CH1_RK1: MR19=0x202, MR18=0xD5D5, DQSOSC=434, MR23=63, INC=13, DEC=19
3906 11:35:30.839432 Write Rank1 MR23 =0x3f
3907 11:35:30.839816 [DQSOSC]
3908 11:35:30.845742 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
3909 11:35:30.849607 CH1 RK1: MR19=202, MR18=D8D8
3910 11:35:30.852834 [RxdqsGatingPostProcess] freq 1600
3911 11:35:30.859341 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3912 11:35:30.859729 Rank: 0
3913 11:35:30.862844 best DQS0 dly(2T, 0.5T) = (2, 6)
3914 11:35:30.866290 best DQS1 dly(2T, 0.5T) = (2, 6)
3915 11:35:30.869464 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3916 11:35:30.872947 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3917 11:35:30.873377 Rank: 1
3918 11:35:30.876053 best DQS0 dly(2T, 0.5T) = (2, 6)
3919 11:35:30.878998 best DQS1 dly(2T, 0.5T) = (2, 6)
3920 11:35:30.883085 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3921 11:35:30.885643 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3922 11:35:30.889627 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3923 11:35:30.892790 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3924 11:35:30.899591 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3925 11:35:30.899990
3926 11:35:30.900285
3927 11:35:30.902232 [Calibration Summary] Freqency 1600
3928 11:35:30.902616 CH 0, Rank 0
3929 11:35:30.902916 All Pass.
3930 11:35:30.903189
3931 11:35:30.905650 CH 0, Rank 1
3932 11:35:30.906034 All Pass.
3933 11:35:30.906330
3934 11:35:30.906603 CH 1, Rank 0
3935 11:35:30.909411 All Pass.
3936 11:35:30.909794
3937 11:35:30.910089 CH 1, Rank 1
3938 11:35:30.910362 All Pass.
3939 11:35:30.910624
3940 11:35:30.915661 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3941 11:35:30.922635 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3942 11:35:30.932550 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3943 11:35:30.932945 Write Rank0 MR3 =0xb0
3944 11:35:30.939406 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3945 11:35:30.945914 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3946 11:35:30.952199 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3947 11:35:30.955688 Write Rank1 MR3 =0xb0
3948 11:35:30.962273 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3949 11:35:30.969220 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3950 11:35:30.975541 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3951 11:35:30.978974 Write Rank0 MR3 =0xb0
3952 11:35:30.985781 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3953 11:35:30.992094 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3954 11:35:30.998509 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3955 11:35:31.002180 Write Rank1 MR3 =0xb0
3956 11:35:31.002563 DramC Write-DBI on
3957 11:35:31.005520 [GetDramInforAfterCalByMRR] Vendor 6.
3958 11:35:31.008430 [GetDramInforAfterCalByMRR] Revision 505.
3959 11:35:31.008819 MR8 1111
3960 11:35:31.015400 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3961 11:35:31.015795 MR8 1111
3962 11:35:31.021855 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3963 11:35:31.022270 MR8 1111
3964 11:35:31.025178 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3965 11:35:31.028736 MR8 1111
3966 11:35:31.031677 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3967 11:35:31.042002 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3968 11:35:31.042390 Write Rank0 MR13 =0xd0
3969 11:35:31.045216 Write Rank1 MR13 =0xd0
3970 11:35:31.048684 Write Rank0 MR13 =0xd0
3971 11:35:31.049068 Write Rank1 MR13 =0xd0
3972 11:35:31.052268 Save calibration result to emmc
3973 11:35:31.052648
3974 11:35:31.052940
3975 11:35:31.054788 [DramcModeReg_Check] Freq_1600, FSP_1
3976 11:35:31.058029 FSP_1, CH_0, RK0
3977 11:35:31.058411 Write Rank0 MR13 =0xd8
3978 11:35:31.061453 MR12 = 0x60 (global = 0x60) match
3979 11:35:31.064822 MR14 = 0x1e (global = 0x1e) match
3980 11:35:31.068813 FSP_1, CH_0, RK1
3981 11:35:31.069235 Write Rank1 MR13 =0xd8
3982 11:35:31.071604 MR12 = 0x5c (global = 0x5c) match
3983 11:35:31.074639 MR14 = 0x1e (global = 0x1e) match
3984 11:35:31.078808 FSP_1, CH_1, RK0
3985 11:35:31.079191 Write Rank0 MR13 =0xd8
3986 11:35:31.081438 MR12 = 0x60 (global = 0x60) match
3987 11:35:31.084451 MR14 = 0x1c (global = 0x1c) match
3988 11:35:31.088197 FSP_1, CH_1, RK1
3989 11:35:31.088582 Write Rank1 MR13 =0xd8
3990 11:35:31.091498 MR12 = 0x60 (global = 0x60) match
3991 11:35:31.094494 MR14 = 0x1e (global = 0x1e) match
3992 11:35:31.094877
3993 11:35:31.101216 [MEM_TEST] 02: After DFS, before run time config
3994 11:35:31.108101 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3995 11:35:31.111415
3996 11:35:31.111794 [TA2_TEST]
3997 11:35:31.112090 === TA2 HW
3998 11:35:31.114432 TA2 PAT: XTALK
3999 11:35:31.117784 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
4000 11:35:31.121302 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
4001 11:35:31.128000 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
4002 11:35:31.131102 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
4003 11:35:31.131484
4004 11:35:31.131774
4005 11:35:31.134430 Settings after calibration
4006 11:35:31.134837
4007 11:35:31.137532 [DramcRunTimeConfig]
4008 11:35:31.141822 TransferPLLToSPMControl - MODE SW PHYPLL
4009 11:35:31.142205 TX_TRACKING: ON
4010 11:35:31.144406 RX_TRACKING: ON
4011 11:35:31.144852 HW_GATING: ON
4012 11:35:31.148066 HW_GATING DBG: OFF
4013 11:35:31.148447 ddr_geometry:1
4014 11:35:31.150701 ddr_geometry:1
4015 11:35:31.151078 ddr_geometry:1
4016 11:35:31.151374 ddr_geometry:1
4017 11:35:31.154324 ddr_geometry:1
4018 11:35:31.154746 ddr_geometry:1
4019 11:35:31.157831 ddr_geometry:1
4020 11:35:31.158211 ddr_geometry:1
4021 11:35:31.160870 High Freq DUMMY_READ_FOR_TRACKING: ON
4022 11:35:31.164514 ZQCS_ENABLE_LP4: OFF
4023 11:35:31.168120 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4024 11:35:31.171262 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4025 11:35:31.171644 SPM_CONTROL_AFTERK: ON
4026 11:35:31.174673 IMPEDANCE_TRACKING: ON
4027 11:35:31.175097 TEMP_SENSOR: ON
4028 11:35:31.177568 PER_BANK_REFRESH: ON
4029 11:35:31.177945 HW_SAVE_FOR_SR: ON
4030 11:35:31.181176 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4031 11:35:31.184386 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4032 11:35:31.187455 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4033 11:35:31.190881 Read ODT Tracking: ON
4034 11:35:31.194376 =========================
4035 11:35:31.194760
4036 11:35:31.195053 [TA2_TEST]
4037 11:35:31.195325 === TA2 HW
4038 11:35:31.201164 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4039 11:35:31.204012 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4040 11:35:31.211009 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4041 11:35:31.214604 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4042 11:35:31.215002
4043 11:35:31.217760 [MEM_TEST] 03: After run time config
4044 11:35:31.228895 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4045 11:35:31.231839 [complex_mem_test] start addr:0x40024000, len:131072
4046 11:35:31.436778 1st complex R/W mem test pass
4047 11:35:31.443250 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4048 11:35:31.446485 sync preloader write leveling
4049 11:35:31.449659 sync preloader cbt_mr12
4050 11:35:31.453423 sync preloader cbt_clk_dly
4051 11:35:31.453915 sync preloader cbt_cmd_dly
4052 11:35:31.456411 sync preloader cbt_cs
4053 11:35:31.460250 sync preloader cbt_ca_perbit_delay
4054 11:35:31.460639 sync preloader clk_delay
4055 11:35:31.462926 sync preloader dqs_delay
4056 11:35:31.466350 sync preloader u1Gating2T_Save
4057 11:35:31.469741 sync preloader u1Gating05T_Save
4058 11:35:31.473241 sync preloader u1Gatingfine_tune_Save
4059 11:35:31.476244 sync preloader u1Gatingucpass_count_Save
4060 11:35:31.480088 sync preloader u1TxWindowPerbitVref_Save
4061 11:35:31.482819 sync preloader u1TxCenter_min_Save
4062 11:35:31.486093 sync preloader u1TxCenter_max_Save
4063 11:35:31.489332 sync preloader u1Txwin_center_Save
4064 11:35:31.493097 sync preloader u1Txfirst_pass_Save
4065 11:35:31.496634 sync preloader u1Txlast_pass_Save
4066 11:35:31.497048 sync preloader u1RxDatlat_Save
4067 11:35:31.502927 sync preloader u1RxWinPerbitVref_Save
4068 11:35:31.506350 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4069 11:35:31.510483 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4070 11:35:31.512948 sync preloader delay_cell_unit
4071 11:35:31.519265 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4072 11:35:31.523131 sync preloader write leveling
4073 11:35:31.523512 sync preloader cbt_mr12
4074 11:35:31.526190 sync preloader cbt_clk_dly
4075 11:35:31.529835 sync preloader cbt_cmd_dly
4076 11:35:31.530216 sync preloader cbt_cs
4077 11:35:31.532574 sync preloader cbt_ca_perbit_delay
4078 11:35:31.535978 sync preloader clk_delay
4079 11:35:31.539446 sync preloader dqs_delay
4080 11:35:31.539967 sync preloader u1Gating2T_Save
4081 11:35:31.543375 sync preloader u1Gating05T_Save
4082 11:35:31.546106 sync preloader u1Gatingfine_tune_Save
4083 11:35:31.549344 sync preloader u1Gatingucpass_count_Save
4084 11:35:31.556244 sync preloader u1TxWindowPerbitVref_Save
4085 11:35:31.556743 sync preloader u1TxCenter_min_Save
4086 11:35:31.559091 sync preloader u1TxCenter_max_Save
4087 11:35:31.562834 sync preloader u1Txwin_center_Save
4088 11:35:31.566164 sync preloader u1Txfirst_pass_Save
4089 11:35:31.569307 sync preloader u1Txlast_pass_Save
4090 11:35:31.573064 sync preloader u1RxDatlat_Save
4091 11:35:31.576160 sync preloader u1RxWinPerbitVref_Save
4092 11:35:31.579128 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4093 11:35:31.586134 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4094 11:35:31.586680 sync preloader delay_cell_unit
4095 11:35:31.592645 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4096 11:35:31.595951 sync preloader write leveling
4097 11:35:31.599386 sync preloader cbt_mr12
4098 11:35:31.602595 sync preloader cbt_clk_dly
4099 11:35:31.602976 sync preloader cbt_cmd_dly
4100 11:35:31.605877 sync preloader cbt_cs
4101 11:35:31.609323 sync preloader cbt_ca_perbit_delay
4102 11:35:31.609703 sync preloader clk_delay
4103 11:35:31.612460 sync preloader dqs_delay
4104 11:35:31.616109 sync preloader u1Gating2T_Save
4105 11:35:31.619266 sync preloader u1Gating05T_Save
4106 11:35:31.622554 sync preloader u1Gatingfine_tune_Save
4107 11:35:31.626049 sync preloader u1Gatingucpass_count_Save
4108 11:35:31.629243 sync preloader u1TxWindowPerbitVref_Save
4109 11:35:31.632653 sync preloader u1TxCenter_min_Save
4110 11:35:31.635630 sync preloader u1TxCenter_max_Save
4111 11:35:31.638967 sync preloader u1Txwin_center_Save
4112 11:35:31.642500 sync preloader u1Txfirst_pass_Save
4113 11:35:31.645680 sync preloader u1Txlast_pass_Save
4114 11:35:31.649066 sync preloader u1RxDatlat_Save
4115 11:35:31.652617 sync preloader u1RxWinPerbitVref_Save
4116 11:35:31.655589 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4117 11:35:31.658935 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4118 11:35:31.662544 sync preloader delay_cell_unit
4119 11:35:31.666246 just_for_test_dump_coreboot_params dump all params
4120 11:35:31.668797 dump source = 0x0
4121 11:35:31.669206 dump params frequency:1600
4122 11:35:31.672349 dump params rank number:2
4123 11:35:31.672730
4124 11:35:31.675250 dump params write leveling
4125 11:35:31.679029 write leveling[0][0][0] = 0x21
4126 11:35:31.682166 write leveling[0][0][1] = 0x19
4127 11:35:31.682549 write leveling[0][1][0] = 0x22
4128 11:35:31.685353 write leveling[0][1][1] = 0x19
4129 11:35:31.689156 write leveling[1][0][0] = 0x22
4130 11:35:31.692340 write leveling[1][0][1] = 0x20
4131 11:35:31.695864 write leveling[1][1][0] = 0x26
4132 11:35:31.698584 write leveling[1][1][1] = 0x20
4133 11:35:31.698972 dump params cbt_cs
4134 11:35:31.702078 cbt_cs[0][0] = 0x8
4135 11:35:31.702460 cbt_cs[0][1] = 0x8
4136 11:35:31.705575 cbt_cs[1][0] = 0xb
4137 11:35:31.705954 cbt_cs[1][1] = 0xb
4138 11:35:31.708792 dump params cbt_mr12
4139 11:35:31.709234 cbt_mr12[0][0] = 0x20
4140 11:35:31.712307 cbt_mr12[0][1] = 0x1c
4141 11:35:31.715414 cbt_mr12[1][0] = 0x20
4142 11:35:31.715813 cbt_mr12[1][1] = 0x20
4143 11:35:31.718920 dump params tx window
4144 11:35:31.719300 tx_center_min[0][0][0] = 987
4145 11:35:31.722224 tx_center_max[0][0][0] = 993
4146 11:35:31.725611 tx_center_min[0][0][1] = 978
4147 11:35:31.728642 tx_center_max[0][0][1] = 985
4148 11:35:31.732355 tx_center_min[0][1][0] = 988
4149 11:35:31.732823 tx_center_max[0][1][0] = 996
4150 11:35:31.735574 tx_center_min[0][1][1] = 979
4151 11:35:31.738933 tx_center_max[0][1][1] = 986
4152 11:35:31.742337 tx_center_min[1][0][0] = 990
4153 11:35:31.745322 tx_center_max[1][0][0] = 995
4154 11:35:31.745707 tx_center_min[1][0][1] = 984
4155 11:35:31.748799 tx_center_max[1][0][1] = 992
4156 11:35:31.752122 tx_center_min[1][1][0] = 991
4157 11:35:31.755266 tx_center_max[1][1][0] = 996
4158 11:35:31.758793 tx_center_min[1][1][1] = 982
4159 11:35:31.759177 tx_center_max[1][1][1] = 989
4160 11:35:31.762206 dump params tx window
4161 11:35:31.765425 tx_win_center[0][0][0] = 992
4162 11:35:31.768810 tx_first_pass[0][0][0] = 980
4163 11:35:31.769221 tx_last_pass[0][0][0] = 1005
4164 11:35:31.772243 tx_win_center[0][0][1] = 991
4165 11:35:31.775204 tx_first_pass[0][0][1] = 980
4166 11:35:31.778235 tx_last_pass[0][0][1] = 1003
4167 11:35:31.781874 tx_win_center[0][0][2] = 993
4168 11:35:31.782263 tx_first_pass[0][0][2] = 981
4169 11:35:31.785158 tx_last_pass[0][0][2] = 1005
4170 11:35:31.788419 tx_win_center[0][0][3] = 987
4171 11:35:31.791929 tx_first_pass[0][0][3] = 977
4172 11:35:31.792310 tx_last_pass[0][0][3] = 997
4173 11:35:31.794943 tx_win_center[0][0][4] = 991
4174 11:35:31.798671 tx_first_pass[0][0][4] = 980
4175 11:35:31.802050 tx_last_pass[0][0][4] = 1003
4176 11:35:31.805627 tx_win_center[0][0][5] = 989
4177 11:35:31.806010 tx_first_pass[0][0][5] = 979
4178 11:35:31.808229 tx_last_pass[0][0][5] = 1000
4179 11:35:31.811966 tx_win_center[0][0][6] = 990
4180 11:35:31.814776 tx_first_pass[0][0][6] = 979
4181 11:35:31.818180 tx_last_pass[0][0][6] = 1002
4182 11:35:31.818565 tx_win_center[0][0][7] = 991
4183 11:35:31.821978 tx_first_pass[0][0][7] = 979
4184 11:35:31.824441 tx_last_pass[0][0][7] = 1003
4185 11:35:31.828194 tx_win_center[0][0][8] = 978
4186 11:35:31.831157 tx_first_pass[0][0][8] = 967
4187 11:35:31.831542 tx_last_pass[0][0][8] = 990
4188 11:35:31.834544 tx_win_center[0][0][9] = 979
4189 11:35:31.837954 tx_first_pass[0][0][9] = 968
4190 11:35:31.841204 tx_last_pass[0][0][9] = 991
4191 11:35:31.841593 tx_win_center[0][0][10] = 985
4192 11:35:31.844559 tx_first_pass[0][0][10] = 973
4193 11:35:31.847675 tx_last_pass[0][0][10] = 997
4194 11:35:31.851768 tx_win_center[0][0][11] = 979
4195 11:35:31.854104 tx_first_pass[0][0][11] = 968
4196 11:35:31.857669 tx_last_pass[0][0][11] = 991
4197 11:35:31.858189 tx_win_center[0][0][12] = 981
4198 11:35:31.860971 tx_first_pass[0][0][12] = 969
4199 11:35:31.864201 tx_last_pass[0][0][12] = 993
4200 11:35:31.867755 tx_win_center[0][0][13] = 981
4201 11:35:31.871264 tx_first_pass[0][0][13] = 969
4202 11:35:31.871657 tx_last_pass[0][0][13] = 993
4203 11:35:31.874104 tx_win_center[0][0][14] = 981
4204 11:35:31.877906 tx_first_pass[0][0][14] = 969
4205 11:35:31.881208 tx_last_pass[0][0][14] = 994
4206 11:35:31.884487 tx_win_center[0][0][15] = 985
4207 11:35:31.884880 tx_first_pass[0][0][15] = 974
4208 11:35:31.887787 tx_last_pass[0][0][15] = 997
4209 11:35:31.890861 tx_win_center[0][1][0] = 996
4210 11:35:31.894214 tx_first_pass[0][1][0] = 984
4211 11:35:31.894609 tx_last_pass[0][1][0] = 1008
4212 11:35:31.897489 tx_win_center[0][1][1] = 993
4213 11:35:31.901146 tx_first_pass[0][1][1] = 981
4214 11:35:31.903982 tx_last_pass[0][1][1] = 1005
4215 11:35:31.907342 tx_win_center[0][1][2] = 995
4216 11:35:31.907735 tx_first_pass[0][1][2] = 983
4217 11:35:31.910787 tx_last_pass[0][1][2] = 1007
4218 11:35:31.914114 tx_win_center[0][1][3] = 988
4219 11:35:31.917532 tx_first_pass[0][1][3] = 978
4220 11:35:31.920355 tx_last_pass[0][1][3] = 999
4221 11:35:31.920857 tx_win_center[0][1][4] = 994
4222 11:35:31.923826 tx_first_pass[0][1][4] = 982
4223 11:35:31.927372 tx_last_pass[0][1][4] = 1006
4224 11:35:31.930563 tx_win_center[0][1][5] = 990
4225 11:35:31.934237 tx_first_pass[0][1][5] = 979
4226 11:35:31.934738 tx_last_pass[0][1][5] = 1002
4227 11:35:31.937346 tx_win_center[0][1][6] = 991
4228 11:35:31.940678 tx_first_pass[0][1][6] = 980
4229 11:35:31.943736 tx_last_pass[0][1][6] = 1003
4230 11:35:31.944237 tx_win_center[0][1][7] = 993
4231 11:35:31.947362 tx_first_pass[0][1][7] = 982
4232 11:35:31.950900 tx_last_pass[0][1][7] = 1005
4233 11:35:31.954360 tx_win_center[0][1][8] = 979
4234 11:35:31.957210 tx_first_pass[0][1][8] = 968
4235 11:35:31.957743 tx_last_pass[0][1][8] = 991
4236 11:35:31.960720 tx_win_center[0][1][9] = 982
4237 11:35:31.963658 tx_first_pass[0][1][9] = 970
4238 11:35:31.967102 tx_last_pass[0][1][9] = 994
4239 11:35:31.967621 tx_win_center[0][1][10] = 986
4240 11:35:31.970379 tx_first_pass[0][1][10] = 975
4241 11:35:31.973765 tx_last_pass[0][1][10] = 998
4242 11:35:31.977481 tx_win_center[0][1][11] = 980
4243 11:35:31.980671 tx_first_pass[0][1][11] = 969
4244 11:35:31.983755 tx_last_pass[0][1][11] = 992
4245 11:35:31.984263 tx_win_center[0][1][12] = 982
4246 11:35:31.986772 tx_first_pass[0][1][12] = 970
4247 11:35:31.990612 tx_last_pass[0][1][12] = 995
4248 11:35:31.994584 tx_win_center[0][1][13] = 982
4249 11:35:31.997301 tx_first_pass[0][1][13] = 970
4250 11:35:31.997693 tx_last_pass[0][1][13] = 994
4251 11:35:32.001014 tx_win_center[0][1][14] = 983
4252 11:35:32.004149 tx_first_pass[0][1][14] = 970
4253 11:35:32.007445 tx_last_pass[0][1][14] = 996
4254 11:35:32.010729 tx_win_center[0][1][15] = 986
4255 11:35:32.011119 tx_first_pass[0][1][15] = 974
4256 11:35:32.013500 tx_last_pass[0][1][15] = 998
4257 11:35:32.016782 tx_win_center[1][0][0] = 995
4258 11:35:32.020678 tx_first_pass[1][0][0] = 983
4259 11:35:32.021214 tx_last_pass[1][0][0] = 1008
4260 11:35:32.023827 tx_win_center[1][0][1] = 994
4261 11:35:32.027377 tx_first_pass[1][0][1] = 981
4262 11:35:32.030369 tx_last_pass[1][0][1] = 1007
4263 11:35:32.033931 tx_win_center[1][0][2] = 992
4264 11:35:32.034426 tx_first_pass[1][0][2] = 979
4265 11:35:32.036846 tx_last_pass[1][0][2] = 1006
4266 11:35:32.040560 tx_win_center[1][0][3] = 990
4267 11:35:32.043795 tx_first_pass[1][0][3] = 978
4268 11:35:32.047156 tx_last_pass[1][0][3] = 1003
4269 11:35:32.047659 tx_win_center[1][0][4] = 994
4270 11:35:32.050216 tx_first_pass[1][0][4] = 981
4271 11:35:32.053561 tx_last_pass[1][0][4] = 1007
4272 11:35:32.057213 tx_win_center[1][0][5] = 995
4273 11:35:32.060472 tx_first_pass[1][0][5] = 983
4274 11:35:32.060852 tx_last_pass[1][0][5] = 1007
4275 11:35:32.063579 tx_win_center[1][0][6] = 994
4276 11:35:32.067246 tx_first_pass[1][0][6] = 981
4277 11:35:32.070595 tx_last_pass[1][0][6] = 1007
4278 11:35:32.070980 tx_win_center[1][0][7] = 994
4279 11:35:32.073650 tx_first_pass[1][0][7] = 981
4280 11:35:32.077433 tx_last_pass[1][0][7] = 1007
4281 11:35:32.080470 tx_win_center[1][0][8] = 987
4282 11:35:32.083633 tx_first_pass[1][0][8] = 976
4283 11:35:32.084017 tx_last_pass[1][0][8] = 999
4284 11:35:32.087008 tx_win_center[1][0][9] = 987
4285 11:35:32.089885 tx_first_pass[1][0][9] = 976
4286 11:35:32.093692 tx_last_pass[1][0][9] = 999
4287 11:35:32.096660 tx_win_center[1][0][10] = 990
4288 11:35:32.097042 tx_first_pass[1][0][10] = 979
4289 11:35:32.099980 tx_last_pass[1][0][10] = 1002
4290 11:35:32.103477 tx_win_center[1][0][11] = 991
4291 11:35:32.106449 tx_first_pass[1][0][11] = 980
4292 11:35:32.110402 tx_last_pass[1][0][11] = 1002
4293 11:35:32.110804 tx_win_center[1][0][12] = 991
4294 11:35:32.113171 tx_first_pass[1][0][12] = 981
4295 11:35:32.116960 tx_last_pass[1][0][12] = 1002
4296 11:35:32.119783 tx_win_center[1][0][13] = 992
4297 11:35:32.123307 tx_first_pass[1][0][13] = 982
4298 11:35:32.126329 tx_last_pass[1][0][13] = 1002
4299 11:35:32.126712 tx_win_center[1][0][14] = 990
4300 11:35:32.129750 tx_first_pass[1][0][14] = 979
4301 11:35:32.133055 tx_last_pass[1][0][14] = 1002
4302 11:35:32.136624 tx_win_center[1][0][15] = 984
4303 11:35:32.139571 tx_first_pass[1][0][15] = 972
4304 11:35:32.139968 tx_last_pass[1][0][15] = 997
4305 11:35:32.142741 tx_win_center[1][1][0] = 996
4306 11:35:32.146517 tx_first_pass[1][1][0] = 984
4307 11:35:32.149241 tx_last_pass[1][1][0] = 1008
4308 11:35:32.152622 tx_win_center[1][1][1] = 994
4309 11:35:32.153181 tx_first_pass[1][1][1] = 982
4310 11:35:32.155851 tx_last_pass[1][1][1] = 1007
4311 11:35:32.159854 tx_win_center[1][1][2] = 993
4312 11:35:32.162923 tx_first_pass[1][1][2] = 980
4313 11:35:32.165857 tx_last_pass[1][1][2] = 1006
4314 11:35:32.166360 tx_win_center[1][1][3] = 991
4315 11:35:32.169402 tx_first_pass[1][1][3] = 978
4316 11:35:32.172527 tx_last_pass[1][1][3] = 1004
4317 11:35:32.176180 tx_win_center[1][1][4] = 995
4318 11:35:32.176674 tx_first_pass[1][1][4] = 983
4319 11:35:32.179725 tx_last_pass[1][1][4] = 1007
4320 11:35:32.182789 tx_win_center[1][1][5] = 995
4321 11:35:32.185602 tx_first_pass[1][1][5] = 983
4322 11:35:32.189419 tx_last_pass[1][1][5] = 1007
4323 11:35:32.189918 tx_win_center[1][1][6] = 994
4324 11:35:32.192670 tx_first_pass[1][1][6] = 982
4325 11:35:32.196161 tx_last_pass[1][1][6] = 1007
4326 11:35:32.199232 tx_win_center[1][1][7] = 994
4327 11:35:32.202724 tx_first_pass[1][1][7] = 982
4328 11:35:32.203218 tx_last_pass[1][1][7] = 1007
4329 11:35:32.205987 tx_win_center[1][1][8] = 986
4330 11:35:32.208892 tx_first_pass[1][1][8] = 974
4331 11:35:32.213228 tx_last_pass[1][1][8] = 999
4332 11:35:32.213730 tx_win_center[1][1][9] = 986
4333 11:35:32.216005 tx_first_pass[1][1][9] = 974
4334 11:35:32.219154 tx_last_pass[1][1][9] = 998
4335 11:35:32.222439 tx_win_center[1][1][10] = 988
4336 11:35:32.226309 tx_first_pass[1][1][10] = 977
4337 11:35:32.226830 tx_last_pass[1][1][10] = 1000
4338 11:35:32.229165 tx_win_center[1][1][11] = 989
4339 11:35:32.232401 tx_first_pass[1][1][11] = 978
4340 11:35:32.235955 tx_last_pass[1][1][11] = 1001
4341 11:35:32.238984 tx_win_center[1][1][12] = 989
4342 11:35:32.242325 tx_first_pass[1][1][12] = 978
4343 11:35:32.242722 tx_last_pass[1][1][12] = 1001
4344 11:35:32.245735 tx_win_center[1][1][13] = 989
4345 11:35:32.248989 tx_first_pass[1][1][13] = 978
4346 11:35:32.252703 tx_last_pass[1][1][13] = 1001
4347 11:35:32.255545 tx_win_center[1][1][14] = 988
4348 11:35:32.255939 tx_first_pass[1][1][14] = 977
4349 11:35:32.259165 tx_last_pass[1][1][14] = 1000
4350 11:35:32.262214 tx_win_center[1][1][15] = 982
4351 11:35:32.265508 tx_first_pass[1][1][15] = 970
4352 11:35:32.269100 tx_last_pass[1][1][15] = 995
4353 11:35:32.269533 dump params rx window
4354 11:35:32.272378 rx_firspass[0][0][0] = 9
4355 11:35:32.275610 rx_lastpass[0][0][0] = 37
4356 11:35:32.276004 rx_firspass[0][0][1] = 9
4357 11:35:32.278868 rx_lastpass[0][0][1] = 36
4358 11:35:32.282140 rx_firspass[0][0][2] = 11
4359 11:35:32.282533 rx_lastpass[0][0][2] = 37
4360 11:35:32.285528 rx_firspass[0][0][3] = 3
4361 11:35:32.288882 rx_lastpass[0][0][3] = 32
4362 11:35:32.291960 rx_firspass[0][0][4] = 10
4363 11:35:32.292356 rx_lastpass[0][0][4] = 36
4364 11:35:32.296184 rx_firspass[0][0][5] = 6
4365 11:35:32.299285 rx_lastpass[0][0][5] = 32
4366 11:35:32.299679 rx_firspass[0][0][6] = 7
4367 11:35:32.302690 rx_lastpass[0][0][6] = 35
4368 11:35:32.305817 rx_firspass[0][0][7] = 11
4369 11:35:32.309628 rx_lastpass[0][0][7] = 35
4370 11:35:32.310137 rx_firspass[0][0][8] = 3
4371 11:35:32.312039 rx_lastpass[0][0][8] = 31
4372 11:35:32.315772 rx_firspass[0][0][9] = 6
4373 11:35:32.316332 rx_lastpass[0][0][9] = 32
4374 11:35:32.319468 rx_firspass[0][0][10] = 11
4375 11:35:32.322729 rx_lastpass[0][0][10] = 39
4376 11:35:32.323245 rx_firspass[0][0][11] = 4
4377 11:35:32.325220 rx_lastpass[0][0][11] = 31
4378 11:35:32.328517 rx_firspass[0][0][12] = 6
4379 11:35:32.332157 rx_lastpass[0][0][12] = 34
4380 11:35:32.332413 rx_firspass[0][0][13] = 7
4381 11:35:32.335390 rx_lastpass[0][0][13] = 32
4382 11:35:32.338627 rx_firspass[0][0][14] = 7
4383 11:35:32.341868 rx_lastpass[0][0][14] = 35
4384 11:35:32.342083 rx_firspass[0][0][15] = 9
4385 11:35:32.345367 rx_lastpass[0][0][15] = 36
4386 11:35:32.348357 rx_firspass[0][1][0] = 9
4387 11:35:32.348562 rx_lastpass[0][1][0] = 39
4388 11:35:32.351787 rx_firspass[0][1][1] = 7
4389 11:35:32.355310 rx_lastpass[0][1][1] = 39
4390 11:35:32.355522 rx_firspass[0][1][2] = 9
4391 11:35:32.358271 rx_lastpass[0][1][2] = 39
4392 11:35:32.361864 rx_firspass[0][1][3] = 1
4393 11:35:32.364969 rx_lastpass[0][1][3] = 32
4394 11:35:32.365187 rx_firspass[0][1][4] = 9
4395 11:35:32.368945 rx_lastpass[0][1][4] = 37
4396 11:35:32.372217 rx_firspass[0][1][5] = 3
4397 11:35:32.372467 rx_lastpass[0][1][5] = 34
4398 11:35:32.375367 rx_firspass[0][1][6] = 4
4399 11:35:32.378654 rx_lastpass[0][1][6] = 35
4400 11:35:32.379031 rx_firspass[0][1][7] = 7
4401 11:35:32.382310 rx_lastpass[0][1][7] = 37
4402 11:35:32.385457 rx_firspass[0][1][8] = 2
4403 11:35:32.388318 rx_lastpass[0][1][8] = 32
4404 11:35:32.388410 rx_firspass[0][1][9] = 5
4405 11:35:32.391665 rx_lastpass[0][1][9] = 34
4406 11:35:32.395273 rx_firspass[0][1][10] = 12
4407 11:35:32.395370 rx_lastpass[0][1][10] = 41
4408 11:35:32.398683 rx_firspass[0][1][11] = 3
4409 11:35:32.401594 rx_lastpass[0][1][11] = 32
4410 11:35:32.405035 rx_firspass[0][1][12] = 6
4411 11:35:32.405139 rx_lastpass[0][1][12] = 35
4412 11:35:32.408611 rx_firspass[0][1][13] = 7
4413 11:35:32.411988 rx_lastpass[0][1][13] = 34
4414 11:35:32.415167 rx_firspass[0][1][14] = 7
4415 11:35:32.415261 rx_lastpass[0][1][14] = 37
4416 11:35:32.418507 rx_firspass[0][1][15] = 10
4417 11:35:32.421536 rx_lastpass[0][1][15] = 38
4418 11:35:32.421636 rx_firspass[1][0][0] = 7
4419 11:35:32.424824 rx_lastpass[1][0][0] = 38
4420 11:35:32.428201 rx_firspass[1][0][1] = 6
4421 11:35:32.432183 rx_lastpass[1][0][1] = 36
4422 11:35:32.432350 rx_firspass[1][0][2] = 4
4423 11:35:32.434761 rx_lastpass[1][0][2] = 36
4424 11:35:32.438837 rx_firspass[1][0][3] = 5
4425 11:35:32.438996 rx_lastpass[1][0][3] = 33
4426 11:35:32.441640 rx_firspass[1][0][4] = 7
4427 11:35:32.444985 rx_lastpass[1][0][4] = 36
4428 11:35:32.445196 rx_firspass[1][0][5] = 8
4429 11:35:32.448238 rx_lastpass[1][0][5] = 38
4430 11:35:32.451538 rx_firspass[1][0][6] = 11
4431 11:35:32.454807 rx_lastpass[1][0][6] = 38
4432 11:35:32.455081 rx_firspass[1][0][7] = 9
4433 11:35:32.458482 rx_lastpass[1][0][7] = 36
4434 11:35:32.461633 rx_firspass[1][0][8] = 4
4435 11:35:32.462041 rx_lastpass[1][0][8] = 32
4436 11:35:32.465049 rx_firspass[1][0][9] = 3
4437 11:35:32.468411 rx_lastpass[1][0][9] = 31
4438 11:35:32.471578 rx_firspass[1][0][10] = 5
4439 11:35:32.471965 rx_lastpass[1][0][10] = 37
4440 11:35:32.474996 rx_firspass[1][0][11] = 7
4441 11:35:32.478645 rx_lastpass[1][0][11] = 36
4442 11:35:32.479036 rx_firspass[1][0][12] = 7
4443 11:35:32.481776 rx_lastpass[1][0][12] = 36
4444 11:35:32.484731 rx_firspass[1][0][13] = 8
4445 11:35:32.487938 rx_lastpass[1][0][13] = 36
4446 11:35:32.488326 rx_firspass[1][0][14] = 8
4447 11:35:32.491252 rx_lastpass[1][0][14] = 35
4448 11:35:32.494645 rx_firspass[1][0][15] = 3
4449 11:35:32.498382 rx_lastpass[1][0][15] = 28
4450 11:35:32.498771 rx_firspass[1][1][0] = 7
4451 11:35:32.502070 rx_lastpass[1][1][0] = 38
4452 11:35:32.504865 rx_firspass[1][1][1] = 7
4453 11:35:32.505298 rx_lastpass[1][1][1] = 37
4454 11:35:32.508598 rx_firspass[1][1][2] = 5
4455 11:35:32.511252 rx_lastpass[1][1][2] = 35
4456 11:35:32.511641 rx_firspass[1][1][3] = 3
4457 11:35:32.514899 rx_lastpass[1][1][3] = 34
4458 11:35:32.518044 rx_firspass[1][1][4] = 5
4459 11:35:32.521576 rx_lastpass[1][1][4] = 37
4460 11:35:32.521966 rx_firspass[1][1][5] = 8
4461 11:35:32.524445 rx_lastpass[1][1][5] = 39
4462 11:35:32.528124 rx_firspass[1][1][6] = 9
4463 11:35:32.528510 rx_lastpass[1][1][6] = 40
4464 11:35:32.531374 rx_firspass[1][1][7] = 8
4465 11:35:32.534521 rx_lastpass[1][1][7] = 36
4466 11:35:32.534911 rx_firspass[1][1][8] = 3
4467 11:35:32.538116 rx_lastpass[1][1][8] = 33
4468 11:35:32.541385 rx_firspass[1][1][9] = 2
4469 11:35:32.544959 rx_lastpass[1][1][9] = 32
4470 11:35:32.545383 rx_firspass[1][1][10] = 6
4471 11:35:32.548032 rx_lastpass[1][1][10] = 36
4472 11:35:32.551264 rx_firspass[1][1][11] = 7
4473 11:35:32.555059 rx_lastpass[1][1][11] = 37
4474 11:35:32.555490 rx_firspass[1][1][12] = 7
4475 11:35:32.558041 rx_lastpass[1][1][12] = 36
4476 11:35:32.561173 rx_firspass[1][1][13] = 7
4477 11:35:32.561567 rx_lastpass[1][1][13] = 37
4478 11:35:32.564559 rx_firspass[1][1][14] = 7
4479 11:35:32.567943 rx_lastpass[1][1][14] = 36
4480 11:35:32.571367 rx_firspass[1][1][15] = 0
4481 11:35:32.571758 rx_lastpass[1][1][15] = 29
4482 11:35:32.574364 dump params clk_delay
4483 11:35:32.574753 clk_delay[0] = 0
4484 11:35:32.577542 clk_delay[1] = 0
4485 11:35:32.577934 dump params dqs_delay
4486 11:35:32.581347 dqs_delay[0][0] = 0
4487 11:35:32.584264 dqs_delay[0][1] = 0
4488 11:35:32.584656 dqs_delay[1][0] = 0
4489 11:35:32.587623 dqs_delay[1][1] = 0
4490 11:35:32.591092 dump params delay_cell_unit = 833
4491 11:35:32.591510 dump source = 0x0
4492 11:35:32.594987 dump params frequency:1200
4493 11:35:32.597497 dump params rank number:2
4494 11:35:32.597887
4495 11:35:32.598281 dump params write leveling
4496 11:35:32.601184 write leveling[0][0][0] = 0x0
4497 11:35:32.604093 write leveling[0][0][1] = 0x0
4498 11:35:32.607346 write leveling[0][1][0] = 0x0
4499 11:35:32.610750 write leveling[0][1][1] = 0x0
4500 11:35:32.611143 write leveling[1][0][0] = 0x0
4501 11:35:32.614183 write leveling[1][0][1] = 0x0
4502 11:35:32.617442 write leveling[1][1][0] = 0x0
4503 11:35:32.621256 write leveling[1][1][1] = 0x0
4504 11:35:32.621653 dump params cbt_cs
4505 11:35:32.624150 cbt_cs[0][0] = 0x0
4506 11:35:32.624545 cbt_cs[0][1] = 0x0
4507 11:35:32.627448 cbt_cs[1][0] = 0x0
4508 11:35:32.627617 cbt_cs[1][1] = 0x0
4509 11:35:32.630574 dump params cbt_mr12
4510 11:35:32.630744 cbt_mr12[0][0] = 0x0
4511 11:35:32.634134 cbt_mr12[0][1] = 0x0
4512 11:35:32.637028 cbt_mr12[1][0] = 0x0
4513 11:35:32.637218 cbt_mr12[1][1] = 0x0
4514 11:35:32.640620 dump params tx window
4515 11:35:32.640789 tx_center_min[0][0][0] = 0
4516 11:35:32.644235 tx_center_max[0][0][0] = 0
4517 11:35:32.647274 tx_center_min[0][0][1] = 0
4518 11:35:32.651792 tx_center_max[0][0][1] = 0
4519 11:35:32.651990 tx_center_min[0][1][0] = 0
4520 11:35:32.654383 tx_center_max[0][1][0] = 0
4521 11:35:32.657425 tx_center_min[0][1][1] = 0
4522 11:35:32.660925 tx_center_max[0][1][1] = 0
4523 11:35:32.661219 tx_center_min[1][0][0] = 0
4524 11:35:32.663967 tx_center_max[1][0][0] = 0
4525 11:35:32.667440 tx_center_min[1][0][1] = 0
4526 11:35:32.670915 tx_center_max[1][0][1] = 0
4527 11:35:32.671416 tx_center_min[1][1][0] = 0
4528 11:35:32.674226 tx_center_max[1][1][0] = 0
4529 11:35:32.677622 tx_center_min[1][1][1] = 0
4530 11:35:32.680530 tx_center_max[1][1][1] = 0
4531 11:35:32.680927 dump params tx window
4532 11:35:32.684327 tx_win_center[0][0][0] = 0
4533 11:35:32.687598 tx_first_pass[0][0][0] = 0
4534 11:35:32.687990 tx_last_pass[0][0][0] = 0
4535 11:35:32.690537 tx_win_center[0][0][1] = 0
4536 11:35:32.694195 tx_first_pass[0][0][1] = 0
4537 11:35:32.694586 tx_last_pass[0][0][1] = 0
4538 11:35:32.697263 tx_win_center[0][0][2] = 0
4539 11:35:32.701199 tx_first_pass[0][0][2] = 0
4540 11:35:32.704496 tx_last_pass[0][0][2] = 0
4541 11:35:32.704887 tx_win_center[0][0][3] = 0
4542 11:35:32.707210 tx_first_pass[0][0][3] = 0
4543 11:35:32.710858 tx_last_pass[0][0][3] = 0
4544 11:35:32.714825 tx_win_center[0][0][4] = 0
4545 11:35:32.715220 tx_first_pass[0][0][4] = 0
4546 11:35:32.717520 tx_last_pass[0][0][4] = 0
4547 11:35:32.720602 tx_win_center[0][0][5] = 0
4548 11:35:32.721009 tx_first_pass[0][0][5] = 0
4549 11:35:32.724252 tx_last_pass[0][0][5] = 0
4550 11:35:32.727300 tx_win_center[0][0][6] = 0
4551 11:35:32.730794 tx_first_pass[0][0][6] = 0
4552 11:35:32.731189 tx_last_pass[0][0][6] = 0
4553 11:35:32.734403 tx_win_center[0][0][7] = 0
4554 11:35:32.737961 tx_first_pass[0][0][7] = 0
4555 11:35:32.740854 tx_last_pass[0][0][7] = 0
4556 11:35:32.741273 tx_win_center[0][0][8] = 0
4557 11:35:32.744375 tx_first_pass[0][0][8] = 0
4558 11:35:32.747453 tx_last_pass[0][0][8] = 0
4559 11:35:32.747837 tx_win_center[0][0][9] = 0
4560 11:35:32.750527 tx_first_pass[0][0][9] = 0
4561 11:35:32.754432 tx_last_pass[0][0][9] = 0
4562 11:35:32.757252 tx_win_center[0][0][10] = 0
4563 11:35:32.757645 tx_first_pass[0][0][10] = 0
4564 11:35:32.761028 tx_last_pass[0][0][10] = 0
4565 11:35:32.764354 tx_win_center[0][0][11] = 0
4566 11:35:32.767402 tx_first_pass[0][0][11] = 0
4567 11:35:32.767813 tx_last_pass[0][0][11] = 0
4568 11:35:32.770501 tx_win_center[0][0][12] = 0
4569 11:35:32.773913 tx_first_pass[0][0][12] = 0
4570 11:35:32.777467 tx_last_pass[0][0][12] = 0
4571 11:35:32.777849 tx_win_center[0][0][13] = 0
4572 11:35:32.780548 tx_first_pass[0][0][13] = 0
4573 11:35:32.783746 tx_last_pass[0][0][13] = 0
4574 11:35:32.787255 tx_win_center[0][0][14] = 0
4575 11:35:32.787639 tx_first_pass[0][0][14] = 0
4576 11:35:32.790266 tx_last_pass[0][0][14] = 0
4577 11:35:32.794150 tx_win_center[0][0][15] = 0
4578 11:35:32.796943 tx_first_pass[0][0][15] = 0
4579 11:35:32.797368 tx_last_pass[0][0][15] = 0
4580 11:35:32.800471 tx_win_center[0][1][0] = 0
4581 11:35:32.804025 tx_first_pass[0][1][0] = 0
4582 11:35:32.806961 tx_last_pass[0][1][0] = 0
4583 11:35:32.807341 tx_win_center[0][1][1] = 0
4584 11:35:32.810465 tx_first_pass[0][1][1] = 0
4585 11:35:32.813676 tx_last_pass[0][1][1] = 0
4586 11:35:32.816985 tx_win_center[0][1][2] = 0
4587 11:35:32.817396 tx_first_pass[0][1][2] = 0
4588 11:35:32.820782 tx_last_pass[0][1][2] = 0
4589 11:35:32.824307 tx_win_center[0][1][3] = 0
4590 11:35:32.824755 tx_first_pass[0][1][3] = 0
4591 11:35:32.827253 tx_last_pass[0][1][3] = 0
4592 11:35:32.830376 tx_win_center[0][1][4] = 0
4593 11:35:32.833476 tx_first_pass[0][1][4] = 0
4594 11:35:32.833862 tx_last_pass[0][1][4] = 0
4595 11:35:32.836994 tx_win_center[0][1][5] = 0
4596 11:35:32.840458 tx_first_pass[0][1][5] = 0
4597 11:35:32.843518 tx_last_pass[0][1][5] = 0
4598 11:35:32.843901 tx_win_center[0][1][6] = 0
4599 11:35:32.847227 tx_first_pass[0][1][6] = 0
4600 11:35:32.850086 tx_last_pass[0][1][6] = 0
4601 11:35:32.850469 tx_win_center[0][1][7] = 0
4602 11:35:32.854066 tx_first_pass[0][1][7] = 0
4603 11:35:32.857166 tx_last_pass[0][1][7] = 0
4604 11:35:32.860299 tx_win_center[0][1][8] = 0
4605 11:35:32.860679 tx_first_pass[0][1][8] = 0
4606 11:35:32.863482 tx_last_pass[0][1][8] = 0
4607 11:35:32.867283 tx_win_center[0][1][9] = 0
4608 11:35:32.870355 tx_first_pass[0][1][9] = 0
4609 11:35:32.870736 tx_last_pass[0][1][9] = 0
4610 11:35:32.873906 tx_win_center[0][1][10] = 0
4611 11:35:32.877370 tx_first_pass[0][1][10] = 0
4612 11:35:32.877752 tx_last_pass[0][1][10] = 0
4613 11:35:32.880289 tx_win_center[0][1][11] = 0
4614 11:35:32.883358 tx_first_pass[0][1][11] = 0
4615 11:35:32.886717 tx_last_pass[0][1][11] = 0
4616 11:35:32.890294 tx_win_center[0][1][12] = 0
4617 11:35:32.890678 tx_first_pass[0][1][12] = 0
4618 11:35:32.893881 tx_last_pass[0][1][12] = 0
4619 11:35:32.896655 tx_win_center[0][1][13] = 0
4620 11:35:32.900455 tx_first_pass[0][1][13] = 0
4621 11:35:32.900885 tx_last_pass[0][1][13] = 0
4622 11:35:32.903718 tx_win_center[0][1][14] = 0
4623 11:35:32.907135 tx_first_pass[0][1][14] = 0
4624 11:35:32.910327 tx_last_pass[0][1][14] = 0
4625 11:35:32.910712 tx_win_center[0][1][15] = 0
4626 11:35:32.913433 tx_first_pass[0][1][15] = 0
4627 11:35:32.916868 tx_last_pass[0][1][15] = 0
4628 11:35:32.917279 tx_win_center[1][0][0] = 0
4629 11:35:32.920176 tx_first_pass[1][0][0] = 0
4630 11:35:32.924441 tx_last_pass[1][0][0] = 0
4631 11:35:32.926859 tx_win_center[1][0][1] = 0
4632 11:35:32.927240 tx_first_pass[1][0][1] = 0
4633 11:35:32.930160 tx_last_pass[1][0][1] = 0
4634 11:35:32.933905 tx_win_center[1][0][2] = 0
4635 11:35:32.936752 tx_first_pass[1][0][2] = 0
4636 11:35:32.937170 tx_last_pass[1][0][2] = 0
4637 11:35:32.940565 tx_win_center[1][0][3] = 0
4638 11:35:32.943752 tx_first_pass[1][0][3] = 0
4639 11:35:32.944135 tx_last_pass[1][0][3] = 0
4640 11:35:32.947308 tx_win_center[1][0][4] = 0
4641 11:35:32.950114 tx_first_pass[1][0][4] = 0
4642 11:35:32.953671 tx_last_pass[1][0][4] = 0
4643 11:35:32.954207 tx_win_center[1][0][5] = 0
4644 11:35:32.956868 tx_first_pass[1][0][5] = 0
4645 11:35:32.959820 tx_last_pass[1][0][5] = 0
4646 11:35:32.963141 tx_win_center[1][0][6] = 0
4647 11:35:32.963216 tx_first_pass[1][0][6] = 0
4648 11:35:32.966272 tx_last_pass[1][0][6] = 0
4649 11:35:32.969667 tx_win_center[1][0][7] = 0
4650 11:35:32.969748 tx_first_pass[1][0][7] = 0
4651 11:35:32.973548 tx_last_pass[1][0][7] = 0
4652 11:35:32.976244 tx_win_center[1][0][8] = 0
4653 11:35:32.979604 tx_first_pass[1][0][8] = 0
4654 11:35:32.979697 tx_last_pass[1][0][8] = 0
4655 11:35:32.982461 tx_win_center[1][0][9] = 0
4656 11:35:32.985840 tx_first_pass[1][0][9] = 0
4657 11:35:32.989070 tx_last_pass[1][0][9] = 0
4658 11:35:32.989197 tx_win_center[1][0][10] = 0
4659 11:35:32.993044 tx_first_pass[1][0][10] = 0
4660 11:35:32.995915 tx_last_pass[1][0][10] = 0
4661 11:35:32.999201 tx_win_center[1][0][11] = 0
4662 11:35:32.999347 tx_first_pass[1][0][11] = 0
4663 11:35:33.002572 tx_last_pass[1][0][11] = 0
4664 11:35:33.006081 tx_win_center[1][0][12] = 0
4665 11:35:33.009832 tx_first_pass[1][0][12] = 0
4666 11:35:33.010016 tx_last_pass[1][0][12] = 0
4667 11:35:33.012272 tx_win_center[1][0][13] = 0
4668 11:35:33.015669 tx_first_pass[1][0][13] = 0
4669 11:35:33.018972 tx_last_pass[1][0][13] = 0
4670 11:35:33.019259 tx_win_center[1][0][14] = 0
4671 11:35:33.022551 tx_first_pass[1][0][14] = 0
4672 11:35:33.025588 tx_last_pass[1][0][14] = 0
4673 11:35:33.029417 tx_win_center[1][0][15] = 0
4674 11:35:33.029922 tx_first_pass[1][0][15] = 0
4675 11:35:33.032335 tx_last_pass[1][0][15] = 0
4676 11:35:33.036168 tx_win_center[1][1][0] = 0
4677 11:35:33.039024 tx_first_pass[1][1][0] = 0
4678 11:35:33.039408 tx_last_pass[1][1][0] = 0
4679 11:35:33.042265 tx_win_center[1][1][1] = 0
4680 11:35:33.045857 tx_first_pass[1][1][1] = 0
4681 11:35:33.049099 tx_last_pass[1][1][1] = 0
4682 11:35:33.049551 tx_win_center[1][1][2] = 0
4683 11:35:33.051928 tx_first_pass[1][1][2] = 0
4684 11:35:33.056014 tx_last_pass[1][1][2] = 0
4685 11:35:33.058644 tx_win_center[1][1][3] = 0
4686 11:35:33.059184 tx_first_pass[1][1][3] = 0
4687 11:35:33.062285 tx_last_pass[1][1][3] = 0
4688 11:35:33.065492 tx_win_center[1][1][4] = 0
4689 11:35:33.065876 tx_first_pass[1][1][4] = 0
4690 11:35:33.068881 tx_last_pass[1][1][4] = 0
4691 11:35:33.072548 tx_win_center[1][1][5] = 0
4692 11:35:33.075700 tx_first_pass[1][1][5] = 0
4693 11:35:33.076089 tx_last_pass[1][1][5] = 0
4694 11:35:33.078697 tx_win_center[1][1][6] = 0
4695 11:35:33.081878 tx_first_pass[1][1][6] = 0
4696 11:35:33.085465 tx_last_pass[1][1][6] = 0
4697 11:35:33.085852 tx_win_center[1][1][7] = 0
4698 11:35:33.088760 tx_first_pass[1][1][7] = 0
4699 11:35:33.092450 tx_last_pass[1][1][7] = 0
4700 11:35:33.095708 tx_win_center[1][1][8] = 0
4701 11:35:33.096096 tx_first_pass[1][1][8] = 0
4702 11:35:33.098544 tx_last_pass[1][1][8] = 0
4703 11:35:33.102096 tx_win_center[1][1][9] = 0
4704 11:35:33.102483 tx_first_pass[1][1][9] = 0
4705 11:35:33.105504 tx_last_pass[1][1][9] = 0
4706 11:35:33.108773 tx_win_center[1][1][10] = 0
4707 11:35:33.112460 tx_first_pass[1][1][10] = 0
4708 11:35:33.112841 tx_last_pass[1][1][10] = 0
4709 11:35:33.115269 tx_win_center[1][1][11] = 0
4710 11:35:33.118730 tx_first_pass[1][1][11] = 0
4711 11:35:33.121873 tx_last_pass[1][1][11] = 0
4712 11:35:33.122256 tx_win_center[1][1][12] = 0
4713 11:35:33.124919 tx_first_pass[1][1][12] = 0
4714 11:35:33.128382 tx_last_pass[1][1][12] = 0
4715 11:35:33.131948 tx_win_center[1][1][13] = 0
4716 11:35:33.132333 tx_first_pass[1][1][13] = 0
4717 11:35:33.135191 tx_last_pass[1][1][13] = 0
4718 11:35:33.138595 tx_win_center[1][1][14] = 0
4719 11:35:33.141793 tx_first_pass[1][1][14] = 0
4720 11:35:33.142177 tx_last_pass[1][1][14] = 0
4721 11:35:33.145081 tx_win_center[1][1][15] = 0
4722 11:35:33.148893 tx_first_pass[1][1][15] = 0
4723 11:35:33.151539 tx_last_pass[1][1][15] = 0
4724 11:35:33.151923 dump params rx window
4725 11:35:33.154893 rx_firspass[0][0][0] = 0
4726 11:35:33.158296 rx_lastpass[0][0][0] = 0
4727 11:35:33.158681 rx_firspass[0][0][1] = 0
4728 11:35:33.161470 rx_lastpass[0][0][1] = 0
4729 11:35:33.164817 rx_firspass[0][0][2] = 0
4730 11:35:33.165259 rx_lastpass[0][0][2] = 0
4731 11:35:33.168203 rx_firspass[0][0][3] = 0
4732 11:35:33.171539 rx_lastpass[0][0][3] = 0
4733 11:35:33.174510 rx_firspass[0][0][4] = 0
4734 11:35:33.174896 rx_lastpass[0][0][4] = 0
4735 11:35:33.178010 rx_firspass[0][0][5] = 0
4736 11:35:33.181264 rx_lastpass[0][0][5] = 0
4737 11:35:33.181650 rx_firspass[0][0][6] = 0
4738 11:35:33.184458 rx_lastpass[0][0][6] = 0
4739 11:35:33.188298 rx_firspass[0][0][7] = 0
4740 11:35:33.188686 rx_lastpass[0][0][7] = 0
4741 11:35:33.191394 rx_firspass[0][0][8] = 0
4742 11:35:33.194780 rx_lastpass[0][0][8] = 0
4743 11:35:33.195178 rx_firspass[0][0][9] = 0
4744 11:35:33.197872 rx_lastpass[0][0][9] = 0
4745 11:35:33.201153 rx_firspass[0][0][10] = 0
4746 11:35:33.205397 rx_lastpass[0][0][10] = 0
4747 11:35:33.205785 rx_firspass[0][0][11] = 0
4748 11:35:33.207579 rx_lastpass[0][0][11] = 0
4749 11:35:33.211019 rx_firspass[0][0][12] = 0
4750 11:35:33.211564 rx_lastpass[0][0][12] = 0
4751 11:35:33.214485 rx_firspass[0][0][13] = 0
4752 11:35:33.217749 rx_lastpass[0][0][13] = 0
4753 11:35:33.221464 rx_firspass[0][0][14] = 0
4754 11:35:33.221954 rx_lastpass[0][0][14] = 0
4755 11:35:33.224981 rx_firspass[0][0][15] = 0
4756 11:35:33.227392 rx_lastpass[0][0][15] = 0
4757 11:35:33.227795 rx_firspass[0][1][0] = 0
4758 11:35:33.230933 rx_lastpass[0][1][0] = 0
4759 11:35:33.234453 rx_firspass[0][1][1] = 0
4760 11:35:33.234837 rx_lastpass[0][1][1] = 0
4761 11:35:33.238148 rx_firspass[0][1][2] = 0
4762 11:35:33.240898 rx_lastpass[0][1][2] = 0
4763 11:35:33.243989 rx_firspass[0][1][3] = 0
4764 11:35:33.244510 rx_lastpass[0][1][3] = 0
4765 11:35:33.247408 rx_firspass[0][1][4] = 0
4766 11:35:33.250587 rx_lastpass[0][1][4] = 0
4767 11:35:33.250967 rx_firspass[0][1][5] = 0
4768 11:35:33.254388 rx_lastpass[0][1][5] = 0
4769 11:35:33.257314 rx_firspass[0][1][6] = 0
4770 11:35:33.257695 rx_lastpass[0][1][6] = 0
4771 11:35:33.260583 rx_firspass[0][1][7] = 0
4772 11:35:33.263980 rx_lastpass[0][1][7] = 0
4773 11:35:33.264363 rx_firspass[0][1][8] = 0
4774 11:35:33.267642 rx_lastpass[0][1][8] = 0
4775 11:35:33.270582 rx_firspass[0][1][9] = 0
4776 11:35:33.274243 rx_lastpass[0][1][9] = 0
4777 11:35:33.274625 rx_firspass[0][1][10] = 0
4778 11:35:33.277379 rx_lastpass[0][1][10] = 0
4779 11:35:33.280471 rx_firspass[0][1][11] = 0
4780 11:35:33.280852 rx_lastpass[0][1][11] = 0
4781 11:35:33.284206 rx_firspass[0][1][12] = 0
4782 11:35:33.287313 rx_lastpass[0][1][12] = 0
4783 11:35:33.287841 rx_firspass[0][1][13] = 0
4784 11:35:33.291097 rx_lastpass[0][1][13] = 0
4785 11:35:33.293710 rx_firspass[0][1][14] = 0
4786 11:35:33.297608 rx_lastpass[0][1][14] = 0
4787 11:35:33.298098 rx_firspass[0][1][15] = 0
4788 11:35:33.300680 rx_lastpass[0][1][15] = 0
4789 11:35:33.303784 rx_firspass[1][0][0] = 0
4790 11:35:33.304291 rx_lastpass[1][0][0] = 0
4791 11:35:33.307773 rx_firspass[1][0][1] = 0
4792 11:35:33.310334 rx_lastpass[1][0][1] = 0
4793 11:35:33.310809 rx_firspass[1][0][2] = 0
4794 11:35:33.313885 rx_lastpass[1][0][2] = 0
4795 11:35:33.317873 rx_firspass[1][0][3] = 0
4796 11:35:33.320442 rx_lastpass[1][0][3] = 0
4797 11:35:33.320931 rx_firspass[1][0][4] = 0
4798 11:35:33.324291 rx_lastpass[1][0][4] = 0
4799 11:35:33.327349 rx_firspass[1][0][5] = 0
4800 11:35:33.327816 rx_lastpass[1][0][5] = 0
4801 11:35:33.330612 rx_firspass[1][0][6] = 0
4802 11:35:33.333715 rx_lastpass[1][0][6] = 0
4803 11:35:33.334099 rx_firspass[1][0][7] = 0
4804 11:35:33.337105 rx_lastpass[1][0][7] = 0
4805 11:35:33.340707 rx_firspass[1][0][8] = 0
4806 11:35:33.341089 rx_lastpass[1][0][8] = 0
4807 11:35:33.343870 rx_firspass[1][0][9] = 0
4808 11:35:33.347368 rx_lastpass[1][0][9] = 0
4809 11:35:33.347749 rx_firspass[1][0][10] = 0
4810 11:35:33.350771 rx_lastpass[1][0][10] = 0
4811 11:35:33.354013 rx_firspass[1][0][11] = 0
4812 11:35:33.356859 rx_lastpass[1][0][11] = 0
4813 11:35:33.357270 rx_firspass[1][0][12] = 0
4814 11:35:33.360585 rx_lastpass[1][0][12] = 0
4815 11:35:33.363570 rx_firspass[1][0][13] = 0
4816 11:35:33.367494 rx_lastpass[1][0][13] = 0
4817 11:35:33.367876 rx_firspass[1][0][14] = 0
4818 11:35:33.370856 rx_lastpass[1][0][14] = 0
4819 11:35:33.373547 rx_firspass[1][0][15] = 0
4820 11:35:33.373946 rx_lastpass[1][0][15] = 0
4821 11:35:33.376764 rx_firspass[1][1][0] = 0
4822 11:35:33.380420 rx_lastpass[1][1][0] = 0
4823 11:35:33.380803 rx_firspass[1][1][1] = 0
4824 11:35:33.383667 rx_lastpass[1][1][1] = 0
4825 11:35:33.386849 rx_firspass[1][1][2] = 0
4826 11:35:33.390763 rx_lastpass[1][1][2] = 0
4827 11:35:33.391145 rx_firspass[1][1][3] = 0
4828 11:35:33.393491 rx_lastpass[1][1][3] = 0
4829 11:35:33.396616 rx_firspass[1][1][4] = 0
4830 11:35:33.396781 rx_lastpass[1][1][4] = 0
4831 11:35:33.400191 rx_firspass[1][1][5] = 0
4832 11:35:33.403297 rx_lastpass[1][1][5] = 0
4833 11:35:33.403461 rx_firspass[1][1][6] = 0
4834 11:35:33.407663 rx_lastpass[1][1][6] = 0
4835 11:35:33.410164 rx_firspass[1][1][7] = 0
4836 11:35:33.410358 rx_lastpass[1][1][7] = 0
4837 11:35:33.413330 rx_firspass[1][1][8] = 0
4838 11:35:33.416480 rx_lastpass[1][1][8] = 0
4839 11:35:33.416715 rx_firspass[1][1][9] = 0
4840 11:35:33.419991 rx_lastpass[1][1][9] = 0
4841 11:35:33.423484 rx_firspass[1][1][10] = 0
4842 11:35:33.426494 rx_lastpass[1][1][10] = 0
4843 11:35:33.426886 rx_firspass[1][1][11] = 0
4844 11:35:33.430380 rx_lastpass[1][1][11] = 0
4845 11:35:33.433154 rx_firspass[1][1][12] = 0
4846 11:35:33.433545 rx_lastpass[1][1][12] = 0
4847 11:35:33.437208 rx_firspass[1][1][13] = 0
4848 11:35:33.440239 rx_lastpass[1][1][13] = 0
4849 11:35:33.443691 rx_firspass[1][1][14] = 0
4850 11:35:33.444077 rx_lastpass[1][1][14] = 0
4851 11:35:33.446708 rx_firspass[1][1][15] = 0
4852 11:35:33.450797 rx_lastpass[1][1][15] = 0
4853 11:35:33.451180 dump params clk_delay
4854 11:35:33.453035 clk_delay[0] = 0
4855 11:35:33.453456 clk_delay[1] = 0
4856 11:35:33.456511 dump params dqs_delay
4857 11:35:33.456889 dqs_delay[0][0] = 0
4858 11:35:33.459801 dqs_delay[0][1] = 0
4859 11:35:33.460183 dqs_delay[1][0] = 0
4860 11:35:33.463698 dqs_delay[1][1] = 0
4861 11:35:33.466849 dump params delay_cell_unit = 833
4862 11:35:33.467230 dump source = 0x0
4863 11:35:33.470173 dump params frequency:800
4864 11:35:33.473361 dump params rank number:2
4865 11:35:33.473739
4866 11:35:33.476889 dump params write leveling
4867 11:35:33.477316 write leveling[0][0][0] = 0x0
4868 11:35:33.480271 write leveling[0][0][1] = 0x0
4869 11:35:33.483168 write leveling[0][1][0] = 0x0
4870 11:35:33.486715 write leveling[0][1][1] = 0x0
4871 11:35:33.489917 write leveling[1][0][0] = 0x0
4872 11:35:33.490307 write leveling[1][0][1] = 0x0
4873 11:35:33.493729 write leveling[1][1][0] = 0x0
4874 11:35:33.496559 write leveling[1][1][1] = 0x0
4875 11:35:33.499980 dump params cbt_cs
4876 11:35:33.500366 cbt_cs[0][0] = 0x0
4877 11:35:33.503187 cbt_cs[0][1] = 0x0
4878 11:35:33.503593 cbt_cs[1][0] = 0x0
4879 11:35:33.507165 cbt_cs[1][1] = 0x0
4880 11:35:33.507557 dump params cbt_mr12
4881 11:35:33.510078 cbt_mr12[0][0] = 0x0
4882 11:35:33.510603 cbt_mr12[0][1] = 0x0
4883 11:35:33.513574 cbt_mr12[1][0] = 0x0
4884 11:35:33.514082 cbt_mr12[1][1] = 0x0
4885 11:35:33.516865 dump params tx window
4886 11:35:33.519648 tx_center_min[0][0][0] = 0
4887 11:35:33.523299 tx_center_max[0][0][0] = 0
4888 11:35:33.523811 tx_center_min[0][0][1] = 0
4889 11:35:33.526514 tx_center_max[0][0][1] = 0
4890 11:35:33.529949 tx_center_min[0][1][0] = 0
4891 11:35:33.533170 tx_center_max[0][1][0] = 0
4892 11:35:33.533538 tx_center_min[0][1][1] = 0
4893 11:35:33.536141 tx_center_max[0][1][1] = 0
4894 11:35:33.539806 tx_center_min[1][0][0] = 0
4895 11:35:33.540243 tx_center_max[1][0][0] = 0
4896 11:35:33.542912 tx_center_min[1][0][1] = 0
4897 11:35:33.546662 tx_center_max[1][0][1] = 0
4898 11:35:33.550061 tx_center_min[1][1][0] = 0
4899 11:35:33.550596 tx_center_max[1][1][0] = 0
4900 11:35:33.552732 tx_center_min[1][1][1] = 0
4901 11:35:33.556266 tx_center_max[1][1][1] = 0
4902 11:35:33.556697 dump params tx window
4903 11:35:33.559740 tx_win_center[0][0][0] = 0
4904 11:35:33.563031 tx_first_pass[0][0][0] = 0
4905 11:35:33.566074 tx_last_pass[0][0][0] = 0
4906 11:35:33.566468 tx_win_center[0][0][1] = 0
4907 11:35:33.569507 tx_first_pass[0][0][1] = 0
4908 11:35:33.572943 tx_last_pass[0][0][1] = 0
4909 11:35:33.576852 tx_win_center[0][0][2] = 0
4910 11:35:33.577283 tx_first_pass[0][0][2] = 0
4911 11:35:33.579945 tx_last_pass[0][0][2] = 0
4912 11:35:33.583080 tx_win_center[0][0][3] = 0
4913 11:35:33.586308 tx_first_pass[0][0][3] = 0
4914 11:35:33.586701 tx_last_pass[0][0][3] = 0
4915 11:35:33.589433 tx_win_center[0][0][4] = 0
4916 11:35:33.592786 tx_first_pass[0][0][4] = 0
4917 11:35:33.593230 tx_last_pass[0][0][4] = 0
4918 11:35:33.596204 tx_win_center[0][0][5] = 0
4919 11:35:33.599655 tx_first_pass[0][0][5] = 0
4920 11:35:33.602756 tx_last_pass[0][0][5] = 0
4921 11:35:33.603143 tx_win_center[0][0][6] = 0
4922 11:35:33.605838 tx_first_pass[0][0][6] = 0
4923 11:35:33.609420 tx_last_pass[0][0][6] = 0
4924 11:35:33.609811 tx_win_center[0][0][7] = 0
4925 11:35:33.612554 tx_first_pass[0][0][7] = 0
4926 11:35:33.616092 tx_last_pass[0][0][7] = 0
4927 11:35:33.619528 tx_win_center[0][0][8] = 0
4928 11:35:33.619915 tx_first_pass[0][0][8] = 0
4929 11:35:33.622794 tx_last_pass[0][0][8] = 0
4930 11:35:33.626425 tx_win_center[0][0][9] = 0
4931 11:35:33.629410 tx_first_pass[0][0][9] = 0
4932 11:35:33.629797 tx_last_pass[0][0][9] = 0
4933 11:35:33.632690 tx_win_center[0][0][10] = 0
4934 11:35:33.635899 tx_first_pass[0][0][10] = 0
4935 11:35:33.639743 tx_last_pass[0][0][10] = 0
4936 11:35:33.640133 tx_win_center[0][0][11] = 0
4937 11:35:33.642685 tx_first_pass[0][0][11] = 0
4938 11:35:33.646283 tx_last_pass[0][0][11] = 0
4939 11:35:33.649175 tx_win_center[0][0][12] = 0
4940 11:35:33.649603 tx_first_pass[0][0][12] = 0
4941 11:35:33.653001 tx_last_pass[0][0][12] = 0
4942 11:35:33.656328 tx_win_center[0][0][13] = 0
4943 11:35:33.659452 tx_first_pass[0][0][13] = 0
4944 11:35:33.659841 tx_last_pass[0][0][13] = 0
4945 11:35:33.662615 tx_win_center[0][0][14] = 0
4946 11:35:33.666356 tx_first_pass[0][0][14] = 0
4947 11:35:33.669462 tx_last_pass[0][0][14] = 0
4948 11:35:33.669854 tx_win_center[0][0][15] = 0
4949 11:35:33.672734 tx_first_pass[0][0][15] = 0
4950 11:35:33.676410 tx_last_pass[0][0][15] = 0
4951 11:35:33.679311 tx_win_center[0][1][0] = 0
4952 11:35:33.679704 tx_first_pass[0][1][0] = 0
4953 11:35:33.682608 tx_last_pass[0][1][0] = 0
4954 11:35:33.685782 tx_win_center[0][1][1] = 0
4955 11:35:33.688949 tx_first_pass[0][1][1] = 0
4956 11:35:33.689372 tx_last_pass[0][1][1] = 0
4957 11:35:33.692612 tx_win_center[0][1][2] = 0
4958 11:35:33.695957 tx_first_pass[0][1][2] = 0
4959 11:35:33.696362 tx_last_pass[0][1][2] = 0
4960 11:35:33.699245 tx_win_center[0][1][3] = 0
4961 11:35:33.702213 tx_first_pass[0][1][3] = 0
4962 11:35:33.705867 tx_last_pass[0][1][3] = 0
4963 11:35:33.706260 tx_win_center[0][1][4] = 0
4964 11:35:33.709035 tx_first_pass[0][1][4] = 0
4965 11:35:33.712339 tx_last_pass[0][1][4] = 0
4966 11:35:33.712730 tx_win_center[0][1][5] = 0
4967 11:35:33.716360 tx_first_pass[0][1][5] = 0
4968 11:35:33.718981 tx_last_pass[0][1][5] = 0
4969 11:35:33.722596 tx_win_center[0][1][6] = 0
4970 11:35:33.722986 tx_first_pass[0][1][6] = 0
4971 11:35:33.725694 tx_last_pass[0][1][6] = 0
4972 11:35:33.728757 tx_win_center[0][1][7] = 0
4973 11:35:33.732745 tx_first_pass[0][1][7] = 0
4974 11:35:33.733159 tx_last_pass[0][1][7] = 0
4975 11:35:33.735741 tx_win_center[0][1][8] = 0
4976 11:35:33.739152 tx_first_pass[0][1][8] = 0
4977 11:35:33.739541 tx_last_pass[0][1][8] = 0
4978 11:35:33.742008 tx_win_center[0][1][9] = 0
4979 11:35:33.745685 tx_first_pass[0][1][9] = 0
4980 11:35:33.748987 tx_last_pass[0][1][9] = 0
4981 11:35:33.749425 tx_win_center[0][1][10] = 0
4982 11:35:33.752341 tx_first_pass[0][1][10] = 0
4983 11:35:33.755458 tx_last_pass[0][1][10] = 0
4984 11:35:33.758586 tx_win_center[0][1][11] = 0
4985 11:35:33.758976 tx_first_pass[0][1][11] = 0
4986 11:35:33.762255 tx_last_pass[0][1][11] = 0
4987 11:35:33.765677 tx_win_center[0][1][12] = 0
4988 11:35:33.768730 tx_first_pass[0][1][12] = 0
4989 11:35:33.769162 tx_last_pass[0][1][12] = 0
4990 11:35:33.772368 tx_win_center[0][1][13] = 0
4991 11:35:33.775188 tx_first_pass[0][1][13] = 0
4992 11:35:33.778421 tx_last_pass[0][1][13] = 0
4993 11:35:33.778811 tx_win_center[0][1][14] = 0
4994 11:35:33.782817 tx_first_pass[0][1][14] = 0
4995 11:35:33.787456 tx_last_pass[0][1][14] = 0
4996 11:35:33.788511 tx_win_center[0][1][15] = 0
4997 11:35:33.791707 tx_first_pass[0][1][15] = 0
4998 11:35:33.792097 tx_last_pass[0][1][15] = 0
4999 11:35:33.795404 tx_win_center[1][0][0] = 0
5000 11:35:33.798636 tx_first_pass[1][0][0] = 0
5001 11:35:33.799153 tx_last_pass[1][0][0] = 0
5002 11:35:33.801709 tx_win_center[1][0][1] = 0
5003 11:35:33.805713 tx_first_pass[1][0][1] = 0
5004 11:35:33.808949 tx_last_pass[1][0][1] = 0
5005 11:35:33.809470 tx_win_center[1][0][2] = 0
5006 11:35:33.812824 tx_first_pass[1][0][2] = 0
5007 11:35:33.815142 tx_last_pass[1][0][2] = 0
5008 11:35:33.815631 tx_win_center[1][0][3] = 0
5009 11:35:33.818788 tx_first_pass[1][0][3] = 0
5010 11:35:33.821841 tx_last_pass[1][0][3] = 0
5011 11:35:33.825686 tx_win_center[1][0][4] = 0
5012 11:35:33.826176 tx_first_pass[1][0][4] = 0
5013 11:35:33.828765 tx_last_pass[1][0][4] = 0
5014 11:35:33.832004 tx_win_center[1][0][5] = 0
5015 11:35:33.835285 tx_first_pass[1][0][5] = 0
5016 11:35:33.835764 tx_last_pass[1][0][5] = 0
5017 11:35:33.838531 tx_win_center[1][0][6] = 0
5018 11:35:33.842382 tx_first_pass[1][0][6] = 0
5019 11:35:33.842876 tx_last_pass[1][0][6] = 0
5020 11:35:33.845378 tx_win_center[1][0][7] = 0
5021 11:35:33.848598 tx_first_pass[1][0][7] = 0
5022 11:35:33.851742 tx_last_pass[1][0][7] = 0
5023 11:35:33.852234 tx_win_center[1][0][8] = 0
5024 11:35:33.855003 tx_first_pass[1][0][8] = 0
5025 11:35:33.858256 tx_last_pass[1][0][8] = 0
5026 11:35:33.862400 tx_win_center[1][0][9] = 0
5027 11:35:33.862893 tx_first_pass[1][0][9] = 0
5028 11:35:33.864993 tx_last_pass[1][0][9] = 0
5029 11:35:33.868804 tx_win_center[1][0][10] = 0
5030 11:35:33.871426 tx_first_pass[1][0][10] = 0
5031 11:35:33.871816 tx_last_pass[1][0][10] = 0
5032 11:35:33.875162 tx_win_center[1][0][11] = 0
5033 11:35:33.878413 tx_first_pass[1][0][11] = 0
5034 11:35:33.882135 tx_last_pass[1][0][11] = 0
5035 11:35:33.882528 tx_win_center[1][0][12] = 0
5036 11:35:33.885159 tx_first_pass[1][0][12] = 0
5037 11:35:33.888660 tx_last_pass[1][0][12] = 0
5038 11:35:33.892116 tx_win_center[1][0][13] = 0
5039 11:35:33.892504 tx_first_pass[1][0][13] = 0
5040 11:35:33.894725 tx_last_pass[1][0][13] = 0
5041 11:35:33.898351 tx_win_center[1][0][14] = 0
5042 11:35:33.901941 tx_first_pass[1][0][14] = 0
5043 11:35:33.902332 tx_last_pass[1][0][14] = 0
5044 11:35:33.904742 tx_win_center[1][0][15] = 0
5045 11:35:33.908704 tx_first_pass[1][0][15] = 0
5046 11:35:33.911447 tx_last_pass[1][0][15] = 0
5047 11:35:33.911970 tx_win_center[1][1][0] = 0
5048 11:35:33.914901 tx_first_pass[1][1][0] = 0
5049 11:35:33.918541 tx_last_pass[1][1][0] = 0
5050 11:35:33.918932 tx_win_center[1][1][1] = 0
5051 11:35:33.921728 tx_first_pass[1][1][1] = 0
5052 11:35:33.925020 tx_last_pass[1][1][1] = 0
5053 11:35:33.928270 tx_win_center[1][1][2] = 0
5054 11:35:33.928626 tx_first_pass[1][1][2] = 0
5055 11:35:33.931760 tx_last_pass[1][1][2] = 0
5056 11:35:33.935183 tx_win_center[1][1][3] = 0
5057 11:35:33.937878 tx_first_pass[1][1][3] = 0
5058 11:35:33.938393 tx_last_pass[1][1][3] = 0
5059 11:35:33.941477 tx_win_center[1][1][4] = 0
5060 11:35:33.944799 tx_first_pass[1][1][4] = 0
5061 11:35:33.945345 tx_last_pass[1][1][4] = 0
5062 11:35:33.947878 tx_win_center[1][1][5] = 0
5063 11:35:33.951832 tx_first_pass[1][1][5] = 0
5064 11:35:33.954666 tx_last_pass[1][1][5] = 0
5065 11:35:33.955188 tx_win_center[1][1][6] = 0
5066 11:35:33.958578 tx_first_pass[1][1][6] = 0
5067 11:35:33.961549 tx_last_pass[1][1][6] = 0
5068 11:35:33.964736 tx_win_center[1][1][7] = 0
5069 11:35:33.965165 tx_first_pass[1][1][7] = 0
5070 11:35:33.968680 tx_last_pass[1][1][7] = 0
5071 11:35:33.971533 tx_win_center[1][1][8] = 0
5072 11:35:33.971925 tx_first_pass[1][1][8] = 0
5073 11:35:33.975132 tx_last_pass[1][1][8] = 0
5074 11:35:33.977999 tx_win_center[1][1][9] = 0
5075 11:35:33.981600 tx_first_pass[1][1][9] = 0
5076 11:35:33.981992 tx_last_pass[1][1][9] = 0
5077 11:35:33.985212 tx_win_center[1][1][10] = 0
5078 11:35:33.988013 tx_first_pass[1][1][10] = 0
5079 11:35:33.991976 tx_last_pass[1][1][10] = 0
5080 11:35:33.992367 tx_win_center[1][1][11] = 0
5081 11:35:33.995044 tx_first_pass[1][1][11] = 0
5082 11:35:33.998150 tx_last_pass[1][1][11] = 0
5083 11:35:34.001469 tx_win_center[1][1][12] = 0
5084 11:35:34.001859 tx_first_pass[1][1][12] = 0
5085 11:35:34.005298 tx_last_pass[1][1][12] = 0
5086 11:35:34.008454 tx_win_center[1][1][13] = 0
5087 11:35:34.011370 tx_first_pass[1][1][13] = 0
5088 11:35:34.011758 tx_last_pass[1][1][13] = 0
5089 11:35:34.015213 tx_win_center[1][1][14] = 0
5090 11:35:34.017944 tx_first_pass[1][1][14] = 0
5091 11:35:34.021387 tx_last_pass[1][1][14] = 0
5092 11:35:34.021899 tx_win_center[1][1][15] = 0
5093 11:35:34.024814 tx_first_pass[1][1][15] = 0
5094 11:35:34.028544 tx_last_pass[1][1][15] = 0
5095 11:35:34.028932 dump params rx window
5096 11:35:34.031816 rx_firspass[0][0][0] = 0
5097 11:35:34.035231 rx_lastpass[0][0][0] = 0
5098 11:35:34.035620 rx_firspass[0][0][1] = 0
5099 11:35:34.038115 rx_lastpass[0][0][1] = 0
5100 11:35:34.041434 rx_firspass[0][0][2] = 0
5101 11:35:34.041821 rx_lastpass[0][0][2] = 0
5102 11:35:34.045183 rx_firspass[0][0][3] = 0
5103 11:35:34.048715 rx_lastpass[0][0][3] = 0
5104 11:35:34.052473 rx_firspass[0][0][4] = 0
5105 11:35:34.052879 rx_lastpass[0][0][4] = 0
5106 11:35:34.054800 rx_firspass[0][0][5] = 0
5107 11:35:34.058482 rx_lastpass[0][0][5] = 0
5108 11:35:34.058874 rx_firspass[0][0][6] = 0
5109 11:35:34.061614 rx_lastpass[0][0][6] = 0
5110 11:35:34.065224 rx_firspass[0][0][7] = 0
5111 11:35:34.065616 rx_lastpass[0][0][7] = 0
5112 11:35:34.068236 rx_firspass[0][0][8] = 0
5113 11:35:34.071207 rx_lastpass[0][0][8] = 0
5114 11:35:34.071598 rx_firspass[0][0][9] = 0
5115 11:35:34.074629 rx_lastpass[0][0][9] = 0
5116 11:35:34.078163 rx_firspass[0][0][10] = 0
5117 11:35:34.081178 rx_lastpass[0][0][10] = 0
5118 11:35:34.081582 rx_firspass[0][0][11] = 0
5119 11:35:34.084731 rx_lastpass[0][0][11] = 0
5120 11:35:34.088139 rx_firspass[0][0][12] = 0
5121 11:35:34.088531 rx_lastpass[0][0][12] = 0
5122 11:35:34.091579 rx_firspass[0][0][13] = 0
5123 11:35:34.094514 rx_lastpass[0][0][13] = 0
5124 11:35:34.095011 rx_firspass[0][0][14] = 0
5125 11:35:34.097588 rx_lastpass[0][0][14] = 0
5126 11:35:34.101229 rx_firspass[0][0][15] = 0
5127 11:35:34.105249 rx_lastpass[0][0][15] = 0
5128 11:35:34.105640 rx_firspass[0][1][0] = 0
5129 11:35:34.108445 rx_lastpass[0][1][0] = 0
5130 11:35:34.111516 rx_firspass[0][1][1] = 0
5131 11:35:34.111907 rx_lastpass[0][1][1] = 0
5132 11:35:34.114726 rx_firspass[0][1][2] = 0
5133 11:35:34.118216 rx_lastpass[0][1][2] = 0
5134 11:35:34.118609 rx_firspass[0][1][3] = 0
5135 11:35:34.121481 rx_lastpass[0][1][3] = 0
5136 11:35:34.124748 rx_firspass[0][1][4] = 0
5137 11:35:34.128351 rx_lastpass[0][1][4] = 0
5138 11:35:34.128781 rx_firspass[0][1][5] = 0
5139 11:35:34.131115 rx_lastpass[0][1][5] = 0
5140 11:35:34.134754 rx_firspass[0][1][6] = 0
5141 11:35:34.135143 rx_lastpass[0][1][6] = 0
5142 11:35:34.137871 rx_firspass[0][1][7] = 0
5143 11:35:34.141175 rx_lastpass[0][1][7] = 0
5144 11:35:34.141722 rx_firspass[0][1][8] = 0
5145 11:35:34.144204 rx_lastpass[0][1][8] = 0
5146 11:35:34.148218 rx_firspass[0][1][9] = 0
5147 11:35:34.148728 rx_lastpass[0][1][9] = 0
5148 11:35:34.151220 rx_firspass[0][1][10] = 0
5149 11:35:34.154272 rx_lastpass[0][1][10] = 0
5150 11:35:34.158383 rx_firspass[0][1][11] = 0
5151 11:35:34.158770 rx_lastpass[0][1][11] = 0
5152 11:35:34.161276 rx_firspass[0][1][12] = 0
5153 11:35:34.164384 rx_lastpass[0][1][12] = 0
5154 11:35:34.164783 rx_firspass[0][1][13] = 0
5155 11:35:34.167710 rx_lastpass[0][1][13] = 0
5156 11:35:34.171088 rx_firspass[0][1][14] = 0
5157 11:35:34.174392 rx_lastpass[0][1][14] = 0
5158 11:35:34.174929 rx_firspass[0][1][15] = 0
5159 11:35:34.177496 rx_lastpass[0][1][15] = 0
5160 11:35:34.181208 rx_firspass[1][0][0] = 0
5161 11:35:34.181715 rx_lastpass[1][0][0] = 0
5162 11:35:34.184446 rx_firspass[1][0][1] = 0
5163 11:35:34.187883 rx_lastpass[1][0][1] = 0
5164 11:35:34.188271 rx_firspass[1][0][2] = 0
5165 11:35:34.191423 rx_lastpass[1][0][2] = 0
5166 11:35:34.194669 rx_firspass[1][0][3] = 0
5167 11:35:34.195056 rx_lastpass[1][0][3] = 0
5168 11:35:34.197389 rx_firspass[1][0][4] = 0
5169 11:35:34.201441 rx_lastpass[1][0][4] = 0
5170 11:35:34.204578 rx_firspass[1][0][5] = 0
5171 11:35:34.204967 rx_lastpass[1][0][5] = 0
5172 11:35:34.208127 rx_firspass[1][0][6] = 0
5173 11:35:34.211041 rx_lastpass[1][0][6] = 0
5174 11:35:34.211432 rx_firspass[1][0][7] = 0
5175 11:35:34.214482 rx_lastpass[1][0][7] = 0
5176 11:35:34.217889 rx_firspass[1][0][8] = 0
5177 11:35:34.218277 rx_lastpass[1][0][8] = 0
5178 11:35:34.220836 rx_firspass[1][0][9] = 0
5179 11:35:34.224092 rx_lastpass[1][0][9] = 0
5180 11:35:34.224478 rx_firspass[1][0][10] = 0
5181 11:35:34.227750 rx_lastpass[1][0][10] = 0
5182 11:35:34.230771 rx_firspass[1][0][11] = 0
5183 11:35:34.234250 rx_lastpass[1][0][11] = 0
5184 11:35:34.234637 rx_firspass[1][0][12] = 0
5185 11:35:34.237408 rx_lastpass[1][0][12] = 0
5186 11:35:34.240957 rx_firspass[1][0][13] = 0
5187 11:35:34.241410 rx_lastpass[1][0][13] = 0
5188 11:35:34.244784 rx_firspass[1][0][14] = 0
5189 11:35:34.247487 rx_lastpass[1][0][14] = 0
5190 11:35:34.250830 rx_firspass[1][0][15] = 0
5191 11:35:34.251215 rx_lastpass[1][0][15] = 0
5192 11:35:34.254301 rx_firspass[1][1][0] = 0
5193 11:35:34.257211 rx_lastpass[1][1][0] = 0
5194 11:35:34.257601 rx_firspass[1][1][1] = 0
5195 11:35:34.260699 rx_lastpass[1][1][1] = 0
5196 11:35:34.263863 rx_firspass[1][1][2] = 0
5197 11:35:34.264249 rx_lastpass[1][1][2] = 0
5198 11:35:34.267758 rx_firspass[1][1][3] = 0
5199 11:35:34.270694 rx_lastpass[1][1][3] = 0
5200 11:35:34.271083 rx_firspass[1][1][4] = 0
5201 11:35:34.274267 rx_lastpass[1][1][4] = 0
5202 11:35:34.277584 rx_firspass[1][1][5] = 0
5203 11:35:34.280833 rx_lastpass[1][1][5] = 0
5204 11:35:34.281304 rx_firspass[1][1][6] = 0
5205 11:35:34.283728 rx_lastpass[1][1][6] = 0
5206 11:35:34.287838 rx_firspass[1][1][7] = 0
5207 11:35:34.288226 rx_lastpass[1][1][7] = 0
5208 11:35:34.290512 rx_firspass[1][1][8] = 0
5209 11:35:34.294535 rx_lastpass[1][1][8] = 0
5210 11:35:34.294930 rx_firspass[1][1][9] = 0
5211 11:35:34.297606 rx_lastpass[1][1][9] = 0
5212 11:35:34.300957 rx_firspass[1][1][10] = 0
5213 11:35:34.301411 rx_lastpass[1][1][10] = 0
5214 11:35:34.304302 rx_firspass[1][1][11] = 0
5215 11:35:34.308298 rx_lastpass[1][1][11] = 0
5216 11:35:34.310693 rx_firspass[1][1][12] = 0
5217 11:35:34.311082 rx_lastpass[1][1][12] = 0
5218 11:35:34.313840 rx_firspass[1][1][13] = 0
5219 11:35:34.317631 rx_lastpass[1][1][13] = 0
5220 11:35:34.318020 rx_firspass[1][1][14] = 0
5221 11:35:34.320857 rx_lastpass[1][1][14] = 0
5222 11:35:34.323859 rx_firspass[1][1][15] = 0
5223 11:35:34.327437 rx_lastpass[1][1][15] = 0
5224 11:35:34.327827 dump params clk_delay
5225 11:35:34.330772 clk_delay[0] = 0
5226 11:35:34.331161 clk_delay[1] = 0
5227 11:35:34.333929 dump params dqs_delay
5228 11:35:34.334320 dqs_delay[0][0] = 0
5229 11:35:34.337645 dqs_delay[0][1] = 0
5230 11:35:34.338032 dqs_delay[1][0] = 0
5231 11:35:34.340353 dqs_delay[1][1] = 0
5232 11:35:34.344087 dump params delay_cell_unit = 833
5233 11:35:34.344477 mt_set_emi_preloader end
5234 11:35:34.350495 [mt_mem_init] dram size: 0x100000000, rank number: 2
5235 11:35:34.353867 [complex_mem_test] start addr:0x40000000, len:20480
5236 11:35:34.391581 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5237 11:35:34.398126 [complex_mem_test] start addr:0x80000000, len:20480
5238 11:35:34.434007 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5239 11:35:34.440566 [complex_mem_test] start addr:0xc0000000, len:20480
5240 11:35:34.475949 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5241 11:35:34.482387 [complex_mem_test] start addr:0x56000000, len:8192
5242 11:35:34.499296 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5243 11:35:34.499688 ddr_geometry:1
5244 11:35:34.505804 [complex_mem_test] start addr:0x80000000, len:8192
5245 11:35:34.523422 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5246 11:35:34.526354 dram_init: dram init end (result: 0)
5247 11:35:34.533275 Successfully loaded DRAM blobs and ran DRAM calibration
5248 11:35:34.542859 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5249 11:35:34.543157 CBMEM:
5250 11:35:34.545926 IMD: root @ 00000000fffff000 254 entries.
5251 11:35:34.549740 IMD: root @ 00000000ffffec00 62 entries.
5252 11:35:34.556116 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5253 11:35:34.562756 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5254 11:35:34.566341 in-header: 03 a1 00 00 08 00 00 00
5255 11:35:34.569255 in-data: 84 60 60 10 00 00 00 00
5256 11:35:34.572315 Chrome EC: clear events_b mask to 0x0000000020004000
5257 11:35:34.580168 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5258 11:35:34.583060 in-header: 03 fd 00 00 00 00 00 00
5259 11:35:34.583268 in-data:
5260 11:35:34.590168 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5261 11:35:34.590377 CBFS @ 21000 size 3d4000
5262 11:35:34.596565 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5263 11:35:34.599569 CBFS: Locating 'fallback/ramstage'
5264 11:35:34.603395 CBFS: Found @ offset 10d40 size d563
5265 11:35:34.624664 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5266 11:35:34.637133 Accumulated console time in romstage 13660 ms
5267 11:35:34.637368
5268 11:35:34.637528
5269 11:35:34.646553 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5270 11:35:34.650322 ARM64: Exception handlers installed.
5271 11:35:34.650514 ARM64: Testing exception
5272 11:35:34.653355 ARM64: Done test exception
5273 11:35:34.656837 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5274 11:35:34.659944 Manufacturer: ef
5275 11:35:34.663344 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5276 11:35:34.669801 WARNING: RO_VPD is uninitialized or empty.
5277 11:35:34.673124 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5278 11:35:34.676435 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5279 11:35:34.686421 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5280 11:35:34.689945 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5281 11:35:34.696192 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5282 11:35:34.696273 Enumerating buses...
5283 11:35:34.703147 Show all devs... Before device enumeration.
5284 11:35:34.703227 Root Device: enabled 1
5285 11:35:34.706888 CPU_CLUSTER: 0: enabled 1
5286 11:35:34.706965 CPU: 00: enabled 1
5287 11:35:34.709940 Compare with tree...
5288 11:35:34.712905 Root Device: enabled 1
5289 11:35:34.712981 CPU_CLUSTER: 0: enabled 1
5290 11:35:34.716477 CPU: 00: enabled 1
5291 11:35:34.719703 Root Device scanning...
5292 11:35:34.719786 root_dev_scan_bus for Root Device
5293 11:35:34.723366 CPU_CLUSTER: 0 enabled
5294 11:35:34.726500 root_dev_scan_bus for Root Device done
5295 11:35:34.732768 scan_bus: scanning of bus Root Device took 10689 usecs
5296 11:35:34.732847 done
5297 11:35:34.736515 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5298 11:35:34.739445 Allocating resources...
5299 11:35:34.739561 Reading resources...
5300 11:35:34.743068 Root Device read_resources bus 0 link: 0
5301 11:35:34.749686 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5302 11:35:34.749765 CPU: 00 missing read_resources
5303 11:35:34.756449 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5304 11:35:34.760047 Root Device read_resources bus 0 link: 0 done
5305 11:35:34.763236 Done reading resources.
5306 11:35:34.766370 Show resources in subtree (Root Device)...After reading.
5307 11:35:34.769479 Root Device child on link 0 CPU_CLUSTER: 0
5308 11:35:34.772719 CPU_CLUSTER: 0 child on link 0 CPU: 00
5309 11:35:34.782911 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5310 11:35:34.783022 CPU: 00
5311 11:35:34.785957 Setting resources...
5312 11:35:34.789146 Root Device assign_resources, bus 0 link: 0
5313 11:35:34.792822 CPU_CLUSTER: 0 missing set_resources
5314 11:35:34.796582 Root Device assign_resources, bus 0 link: 0
5315 11:35:34.799219 Done setting resources.
5316 11:35:34.806085 Show resources in subtree (Root Device)...After assigning values.
5317 11:35:34.809392 Root Device child on link 0 CPU_CLUSTER: 0
5318 11:35:34.812854 CPU_CLUSTER: 0 child on link 0 CPU: 00
5319 11:35:34.819914 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5320 11:35:34.822463 CPU: 00
5321 11:35:34.826053 Done allocating resources.
5322 11:35:34.829550 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5323 11:35:34.832989 Enabling resources...
5324 11:35:34.833088 done.
5325 11:35:34.836207 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5326 11:35:34.839489 Initializing devices...
5327 11:35:34.839570 Root Device init ...
5328 11:35:34.842679 mainboard_init: Starting display init.
5329 11:35:34.846219 ADC[4]: Raw value=75944 ID=0
5330 11:35:34.869612 anx7625_power_on_init: Init interface.
5331 11:35:34.872330 anx7625_disable_pd_protocol: Disabled PD feature.
5332 11:35:34.879170 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5333 11:35:34.936570 anx7625_start_dp_work: Secure OCM version=00
5334 11:35:34.939751 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5335 11:35:34.956724 sp_tx_get_edid_block: EDID Block = 1
5336 11:35:35.074189 Extracted contents:
5337 11:35:35.078252 header: 00 ff ff ff ff ff ff 00
5338 11:35:35.081068 serial number: 06 af 5c 14 00 00 00 00 00 1a
5339 11:35:35.084409 version: 01 04
5340 11:35:35.087857 basic params: 95 1a 0e 78 02
5341 11:35:35.090825 chroma info: 99 85 95 55 56 92 28 22 50 54
5342 11:35:35.093645 established: 00 00 00
5343 11:35:35.100665 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5344 11:35:35.103739 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5345 11:35:35.110672 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5346 11:35:35.117235 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5347 11:35:35.124158 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5348 11:35:35.127136 extensions: 00
5349 11:35:35.127522 checksum: ae
5350 11:35:35.127823
5351 11:35:35.130543 Manufacturer: AUO Model 145c Serial Number 0
5352 11:35:35.133945 Made week 0 of 2016
5353 11:35:35.134331 EDID version: 1.4
5354 11:35:35.137231 Digital display
5355 11:35:35.140244 6 bits per primary color channel
5356 11:35:35.140634 DisplayPort interface
5357 11:35:35.143903 Maximum image size: 26 cm x 14 cm
5358 11:35:35.146853 Gamma: 220%
5359 11:35:35.147236 Check DPMS levels
5360 11:35:35.150602 Supported color formats: RGB 4:4:4
5361 11:35:35.153653 First detailed timing is preferred timing
5362 11:35:35.157302 Established timings supported:
5363 11:35:35.160385 Standard timings supported:
5364 11:35:35.160880 Detailed timings
5365 11:35:35.167397 Hex of detail: ce1d56ea50001a3030204600009010000018
5366 11:35:35.170971 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5367 11:35:35.173650 0556 0586 05a6 0640 hborder 0
5368 11:35:35.177009 0300 0304 030a 031a vborder 0
5369 11:35:35.180060 -hsync -vsync
5370 11:35:35.183903 Did detailed timing
5371 11:35:35.187172 Hex of detail: 0000000f0000000000000000000000000020
5372 11:35:35.190372 Manufacturer-specified data, tag 15
5373 11:35:35.193971 Hex of detail: 000000fe0041554f0a202020202020202020
5374 11:35:35.196900 ASCII string: AUO
5375 11:35:35.200678 Hex of detail: 000000fe004231313658414230312e34200a
5376 11:35:35.203543 ASCII string: B116XAB01.4
5377 11:35:35.203813 Checksum
5378 11:35:35.206901 Checksum: 0xae (valid)
5379 11:35:35.213779 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5380 11:35:35.214002 DSI data_rate: 457800000 bps
5381 11:35:35.221341 anx7625_parse_edid: set default k value to 0x3d for panel
5382 11:35:35.223860 anx7625_parse_edid: pixelclock(76300).
5383 11:35:35.227437 hactive(1366), hsync(32), hfp(48), hbp(154)
5384 11:35:35.231073 vactive(768), vsync(6), vfp(4), vbp(16)
5385 11:35:35.234494 anx7625_dsi_config: config dsi.
5386 11:35:35.242614 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5387 11:35:35.263261 anx7625_dsi_config: success to config DSI
5388 11:35:35.266496 anx7625_dp_start: MIPI phy setup OK.
5389 11:35:35.269936 [SSUSB] Setting up USB HOST controller...
5390 11:35:35.273774 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5391 11:35:35.274231 [SSUSB] phy power-on done.
5392 11:35:35.280592 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5393 11:35:35.283819 in-header: 03 fc 01 00 00 00 00 00
5394 11:35:35.284291 in-data:
5395 11:35:35.286875 handle_proto3_response: EC response with error code: 1
5396 11:35:35.290297 SPM: pcm index = 1
5397 11:35:35.293886 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5398 11:35:35.296922 CBFS @ 21000 size 3d4000
5399 11:35:35.303958 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5400 11:35:35.307543 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5401 11:35:35.310299 CBFS: Found @ offset 1e7c0 size 1026
5402 11:35:35.317245 read SPI 0x3f808 0x1026: 1270 us, 3255 KB/s, 26.040 Mbps
5403 11:35:35.320261 SPM: binary array size = 2988
5404 11:35:35.323849 SPM: version = pcm_allinone_v1.17.2_20180829
5405 11:35:35.327163 SPM binary loaded in 32 msecs
5406 11:35:35.334646 spm_kick_im_to_fetch: ptr = 000000004021eec2
5407 11:35:35.337669 spm_kick_im_to_fetch: len = 2988
5408 11:35:35.338052 SPM: spm_kick_pcm_to_run
5409 11:35:35.341779 SPM: spm_kick_pcm_to_run done
5410 11:35:35.344690 SPM: spm_init done in 52 msecs
5411 11:35:35.347975 Root Device init finished in 505263 usecs
5412 11:35:35.351564 CPU_CLUSTER: 0 init ...
5413 11:35:35.360702 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5414 11:35:35.364190 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5415 11:35:35.367701 CBFS @ 21000 size 3d4000
5416 11:35:35.371162 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5417 11:35:35.374119 CBFS: Locating 'sspm.bin'
5418 11:35:35.377371 CBFS: Found @ offset 208c0 size 41cb
5419 11:35:35.387606 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5420 11:35:35.395884 CPU_CLUSTER: 0 init finished in 42802 usecs
5421 11:35:35.396371 Devices initialized
5422 11:35:35.398969 Show all devs... After init.
5423 11:35:35.402046 Root Device: enabled 1
5424 11:35:35.402425 CPU_CLUSTER: 0: enabled 1
5425 11:35:35.405617 CPU: 00: enabled 1
5426 11:35:35.409196 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5427 11:35:35.412531 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5428 11:35:35.415966 ELOG: NV offset 0x558000 size 0x1000
5429 11:35:35.422943 read SPI 0x558000 0x1000: 1262 us, 3245 KB/s, 25.960 Mbps
5430 11:35:35.429703 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5431 11:35:35.432854 ELOG: Event(17) added with size 13 at 2024-07-17 11:35:35 UTC
5432 11:35:35.436771 out: cmd=0x121: 03 db 21 01 00 00 00 00
5433 11:35:35.440011 in-header: 03 2b 00 00 2c 00 00 00
5434 11:35:35.453033 in-data: 36 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 e7 36 08 00 06 80 00 00 1d ea 2f 00 06 80 00 00 34 2b 01 00 06 80 00 00 cb 73 02 00
5435 11:35:35.456673 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5436 11:35:35.460322 in-header: 03 19 00 00 08 00 00 00
5437 11:35:35.463699 in-data: a2 e0 47 00 13 00 00 00
5438 11:35:35.467028 Chrome EC: UHEPI supported
5439 11:35:35.473215 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5440 11:35:35.476214 in-header: 03 e1 00 00 08 00 00 00
5441 11:35:35.479804 in-data: 84 20 60 10 00 00 00 00
5442 11:35:35.483003 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5443 11:35:35.490880 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5444 11:35:35.493349 in-header: 03 e1 00 00 08 00 00 00
5445 11:35:35.497008 in-data: 84 20 60 10 00 00 00 00
5446 11:35:35.502920 ELOG: Event(A1) added with size 10 at 2024-07-17 11:35:35 UTC
5447 11:35:35.509830 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5448 11:35:35.512971 ELOG: Event(A0) added with size 9 at 2024-07-17 11:35:35 UTC
5449 11:35:35.519676 elog_add_boot_reason: Logged dev mode boot
5450 11:35:35.520076 Finalize devices...
5451 11:35:35.523046 Devices finalized
5452 11:35:35.526675 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5453 11:35:35.529757 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5454 11:35:35.536468 ELOG: Event(91) added with size 10 at 2024-07-17 11:35:35 UTC
5455 11:35:35.539782 Writing coreboot table at 0xffeda000
5456 11:35:35.543293 0. 0000000000114000-000000000011efff: RAMSTAGE
5457 11:35:35.549515 1. 0000000040000000-000000004023cfff: RAMSTAGE
5458 11:35:35.552967 2. 000000004023d000-00000000545fffff: RAM
5459 11:35:35.555945 3. 0000000054600000-000000005465ffff: BL31
5460 11:35:35.560396 4. 0000000054660000-00000000ffed9fff: RAM
5461 11:35:35.566102 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5462 11:35:35.569561 6. 0000000100000000-000000013fffffff: RAM
5463 11:35:35.572736 Passing 5 GPIOs to payload:
5464 11:35:35.576165 NAME | PORT | POLARITY | VALUE
5465 11:35:35.579327 write protect | 0x00000096 | low | low
5466 11:35:35.586551 EC in RW | 0x000000b1 | high | undefined
5467 11:35:35.589937 EC interrupt | 0x00000097 | low | undefined
5468 11:35:35.596373 TPM interrupt | 0x00000099 | high | undefined
5469 11:35:35.600014 speaker enable | 0x000000af | high | undefined
5470 11:35:35.603099 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5471 11:35:35.606294 in-header: 03 f7 00 00 02 00 00 00
5472 11:35:35.606676 in-data: 04 00
5473 11:35:35.609744 Board ID: 4
5474 11:35:35.612703 ADC[3]: Raw value=216068 ID=1
5475 11:35:35.613062 RAM code: 1
5476 11:35:35.613478 SKU ID: 16
5477 11:35:35.619858 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5478 11:35:35.620320 CBFS @ 21000 size 3d4000
5479 11:35:35.626663 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5480 11:35:35.632919 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 1fb5
5481 11:35:35.633349 coreboot table: 940 bytes.
5482 11:35:35.636332 IMD ROOT 0. 00000000fffff000 00001000
5483 11:35:35.642660 IMD SMALL 1. 00000000ffffe000 00001000
5484 11:35:35.646597 CONSOLE 2. 00000000fffde000 00020000
5485 11:35:35.649462 FMAP 3. 00000000fffdd000 0000047c
5486 11:35:35.653404 TIME STAMP 4. 00000000fffdc000 00000910
5487 11:35:35.656179 RAMOOPS 5. 00000000ffedc000 00100000
5488 11:35:35.659883 COREBOOT 6. 00000000ffeda000 00002000
5489 11:35:35.662894 IMD small region:
5490 11:35:35.666180 IMD ROOT 0. 00000000ffffec00 00000400
5491 11:35:35.669841 VBOOT WORK 1. 00000000ffffeb00 00000100
5492 11:35:35.672428 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5493 11:35:35.676162 VPD 3. 00000000ffffea60 0000006c
5494 11:35:35.682991 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5495 11:35:35.689292 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5496 11:35:35.692996 in-header: 03 e1 00 00 08 00 00 00
5497 11:35:35.693444 in-data: 84 20 60 10 00 00 00 00
5498 11:35:35.699219 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5499 11:35:35.699607 CBFS @ 21000 size 3d4000
5500 11:35:35.706349 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5501 11:35:35.709080 CBFS: Locating 'fallback/payload'
5502 11:35:35.718188 CBFS: Found @ offset dc040 size 439a0
5503 11:35:35.805275 read SPI 0xfd078 0x439a0: 84380 us, 3281 KB/s, 26.248 Mbps
5504 11:35:35.808355 Checking segment from ROM address 0x0000000040003a00
5505 11:35:35.815032 Checking segment from ROM address 0x0000000040003a1c
5506 11:35:35.818541 Loading segment from ROM address 0x0000000040003a00
5507 11:35:35.821629 code (compression=0)
5508 11:35:35.831380 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5509 11:35:35.838461 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5510 11:35:35.841868 it's not compressed!
5511 11:35:35.845545 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5512 11:35:35.851601 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5513 11:35:35.859749 Loading segment from ROM address 0x0000000040003a1c
5514 11:35:35.862890 Entry Point 0x0000000080000000
5515 11:35:35.863595 Loaded segments
5516 11:35:35.869844 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5517 11:35:35.872955 Jumping to boot code at 0000000080000000(00000000ffeda000)
5518 11:35:35.883304 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5519 11:35:35.886119 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5520 11:35:35.889260 CBFS @ 21000 size 3d4000
5521 11:35:35.896208 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5522 11:35:35.899827 CBFS: Locating 'fallback/bl31'
5523 11:35:35.902627 CBFS: Found @ offset 36dc0 size 5820
5524 11:35:35.913686 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5525 11:35:35.916718 Checking segment from ROM address 0x0000000040003a00
5526 11:35:35.923512 Checking segment from ROM address 0x0000000040003a1c
5527 11:35:35.927021 Loading segment from ROM address 0x0000000040003a00
5528 11:35:35.930083 code (compression=1)
5529 11:35:35.936848 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5530 11:35:35.946292 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5531 11:35:35.946691 using LZMA
5532 11:35:35.955160 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5533 11:35:35.962263 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5534 11:35:35.965201 Loading segment from ROM address 0x0000000040003a1c
5535 11:35:35.968615 Entry Point 0x0000000054601000
5536 11:35:35.969007 Loaded segments
5537 11:35:35.971897 NOTICE: MT8183 bl31_setup
5538 11:35:35.979358 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5539 11:35:35.982523 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5540 11:35:35.985672 INFO: [DEVAPC] dump DEVAPC registers:
5541 11:35:35.995989 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5542 11:35:36.002576 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5543 11:35:36.012197 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5544 11:35:36.019383 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5545 11:35:36.028688 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5546 11:35:36.035260 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5547 11:35:36.045515 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5548 11:35:36.052170 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5549 11:35:36.058681 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5550 11:35:36.068698 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5551 11:35:36.075187 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5552 11:35:36.085714 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5553 11:35:36.091898 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5554 11:35:36.102183 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5555 11:35:36.108772 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5556 11:35:36.115873 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5557 11:35:36.121911 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5558 11:35:36.128416 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5559 11:35:36.139098 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5560 11:35:36.144738 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5561 11:35:36.151366 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5562 11:35:36.157949 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5563 11:35:36.161792 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5564 11:35:36.165632 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5565 11:35:36.167943 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5566 11:35:36.171504 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5567 11:35:36.174760 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5568 11:35:36.181251 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5569 11:35:36.188201 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5570 11:35:36.188586 WARNING: region 0:
5571 11:35:36.191562 WARNING: apc:0x168, sa:0x0, ea:0xfff
5572 11:35:36.194441 WARNING: region 1:
5573 11:35:36.197775 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5574 11:35:36.198161 WARNING: region 2:
5575 11:35:36.201223 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5576 11:35:36.205016 WARNING: region 3:
5577 11:35:36.208240 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5578 11:35:36.211285 WARNING: region 4:
5579 11:35:36.214322 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5580 11:35:36.214706 WARNING: region 5:
5581 11:35:36.217703 WARNING: apc:0x0, sa:0x0, ea:0x0
5582 11:35:36.221529 WARNING: region 6:
5583 11:35:36.224592 WARNING: apc:0x0, sa:0x0, ea:0x0
5584 11:35:36.224976 WARNING: region 7:
5585 11:35:36.228124 WARNING: apc:0x0, sa:0x0, ea:0x0
5586 11:35:36.234163 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5587 11:35:36.237970 INFO: SPM: enable SPMC mode
5588 11:35:36.241463 NOTICE: spm_boot_init() start
5589 11:35:36.244199 NOTICE: spm_boot_init() end
5590 11:35:36.248407 INFO: BL31: Initializing runtime services
5591 11:35:36.254499 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5592 11:35:36.257954 INFO: BL31: Preparing for EL3 exit to normal world
5593 11:35:36.260859 INFO: Entry point address = 0x80000000
5594 11:35:36.264370 INFO: SPSR = 0x8
5595 11:35:36.285260
5596 11:35:36.285818
5597 11:35:36.286147
5598 11:35:36.287586 end: 2.2.3 depthcharge-start (duration 00:00:23) [common]
5599 11:35:36.288020 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5600 11:35:36.288378 Setting prompt string to ['jacuzzi:']
5601 11:35:36.288807 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5602 11:35:36.289486 Starting depthcharge on Juniper...
5603 11:35:36.289801
5604 11:35:36.292473 vboot_handoff: creating legacy vboot_handoff structure
5605 11:35:36.292909
5606 11:35:36.295537 ec_init(0): CrosEC protocol v3 supported (544, 544)
5607 11:35:36.296016
5608 11:35:36.299683 Wipe memory regions:
5609 11:35:36.300064
5610 11:35:36.302345 [0x00000040000000, 0x00000054600000)
5611 11:35:36.344913
5612 11:35:36.345347 [0x00000054660000, 0x00000080000000)
5613 11:35:36.436994
5614 11:35:36.437435 [0x000000811994a0, 0x000000ffeda000)
5615 11:35:36.696708
5616 11:35:36.697279 [0x00000100000000, 0x00000140000000)
5617 11:35:36.829980
5618 11:35:36.832809 Initializing XHCI USB controller at 0x11200000.
5619 11:35:36.855649
5620 11:35:36.858855 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5621 11:35:36.859316
5622 11:35:36.859862
5623 11:35:36.860598 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5624 11:35:36.861011 Sending line: 'tftpboot 192.168.201.1 14864608/tftp-deploy-bhuaup7q/kernel/image.itb 14864608/tftp-deploy-bhuaup7q/kernel/cmdline '
5626 11:35:36.962762 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5627 11:35:36.963244 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5628 11:35:36.967381 jacuzzi: tftpboot 192.168.201.1 14864608/tftp-deploy-bhuaup7q/kernel/image.ittp-deploy-bhuaup7q/kernel/cmdline
5629 11:35:36.967778
5630 11:35:36.968166 Waiting for link
5631 11:35:37.370091
5632 11:35:37.370608 R8152: Initializing
5633 11:35:37.371044
5634 11:35:37.372536 Version 9 (ocp_data = 6010)
5635 11:35:37.372969
5636 11:35:37.376060 R8152: Done initializing
5637 11:35:37.376495
5638 11:35:37.376936 Adding net device
5639 11:35:37.761373
5640 11:35:37.761841 done.
5641 11:35:37.762235
5642 11:35:37.762601 MAC: 00:e0:4c:72:3d:67
5643 11:35:37.762975
5644 11:35:37.764972 Sending DHCP discover... done.
5645 11:35:37.765407
5646 11:35:37.768074 Waiting for reply... done.
5647 11:35:37.768456
5648 11:35:37.771669 Sending DHCP request... done.
5649 11:35:37.771912
5650 11:35:37.776302 Waiting for reply... done.
5651 11:35:37.776470
5652 11:35:37.776640 My ip is 192.168.201.13
5653 11:35:37.776801
5654 11:35:37.779329 The DHCP server ip is 192.168.201.1
5655 11:35:37.779435
5656 11:35:37.785875 TFTP server IP predefined by user: 192.168.201.1
5657 11:35:37.785954
5658 11:35:37.792606 Bootfile predefined by user: 14864608/tftp-deploy-bhuaup7q/kernel/image.itb
5659 11:35:37.792685
5660 11:35:37.792761 Sending tftp read request... done.
5661 11:35:37.796304
5662 11:35:37.799375 Waiting for the transfer...
5663 11:35:37.799461
5664 11:35:38.078359 00000000 ################################################################
5665 11:35:38.078490
5666 11:35:38.346705 00080000 ################################################################
5667 11:35:38.346808
5668 11:35:38.613591 00100000 ################################################################
5669 11:35:38.613719
5670 11:35:38.891918 00180000 ################################################################
5671 11:35:38.892031
5672 11:35:39.159972 00200000 ################################################################
5673 11:35:39.160084
5674 11:35:39.438920 00280000 ################################################################
5675 11:35:39.439024
5676 11:35:39.713940 00300000 ################################################################
5677 11:35:39.714043
5678 11:35:40.006530 00380000 ################################################################
5679 11:35:40.006639
5680 11:35:40.301055 00400000 ################################################################
5681 11:35:40.301209
5682 11:35:40.594617 00480000 ################################################################
5683 11:35:40.594757
5684 11:35:40.892301 00500000 ################################################################
5685 11:35:40.892412
5686 11:35:41.180131 00580000 ################################################################
5687 11:35:41.180250
5688 11:35:41.471003 00600000 ################################################################
5689 11:35:41.471141
5690 11:35:41.754793 00680000 ################################################################
5691 11:35:41.754911
5692 11:35:42.111097 00700000 ################################################################
5693 11:35:42.111533
5694 11:35:42.504457 00780000 ################################################################
5695 11:35:42.505020
5696 11:35:42.892654 00800000 ################################################################
5697 11:35:42.892768
5698 11:35:43.173336 00880000 ################################################################
5699 11:35:43.173448
5700 11:35:43.413366 00900000 ################################################################
5701 11:35:43.413503
5702 11:35:43.691413 00980000 ################################################################
5703 11:35:43.691523
5704 11:35:43.985945 00a00000 ################################################################
5705 11:35:43.986053
5706 11:35:44.263355 00a80000 ################################################################
5707 11:35:44.263470
5708 11:35:44.545429 00b00000 ################################################################
5709 11:35:44.545539
5710 11:35:44.824326 00b80000 ################################################################
5711 11:35:44.824437
5712 11:35:45.078796 00c00000 ################################################################
5713 11:35:45.078907
5714 11:35:45.343111 00c80000 ################################################################
5715 11:35:45.343223
5716 11:35:45.604069 00d00000 ################################################################
5717 11:35:45.604180
5718 11:35:45.857973 00d80000 ################################################################
5719 11:35:45.858084
5720 11:35:46.161239 00e00000 ################################################################
5721 11:35:46.161350
5722 11:35:46.443529 00e80000 ################################################################
5723 11:35:46.443641
5724 11:35:46.710644 00f00000 ################################################################
5725 11:35:46.710757
5726 11:35:46.992838 00f80000 ################################################################
5727 11:35:46.992948
5728 11:35:47.271495 01000000 ################################################################
5729 11:35:47.271605
5730 11:35:47.558321 01080000 ################################################################
5731 11:35:47.558433
5732 11:35:47.840221 01100000 ################################################################
5733 11:35:47.840332
5734 11:35:48.107903 01180000 ################################################################
5735 11:35:48.108014
5736 11:35:48.400439 01200000 ################################################################
5737 11:35:48.400550
5738 11:35:48.686623 01280000 ################################################################
5739 11:35:48.686735
5740 11:35:48.941437 01300000 ################################################################
5741 11:35:48.941550
5742 11:35:49.196761 01380000 ################################################################
5743 11:35:49.196872
5744 11:35:49.464591 01400000 ################################################################
5745 11:35:49.464700
5746 11:35:49.753696 01480000 ################################################################
5747 11:35:49.753807
5748 11:35:50.027906 01500000 ################################################################
5749 11:35:50.028018
5750 11:35:50.287907 01580000 ################################################################
5751 11:35:50.288020
5752 11:35:50.583661 01600000 ################################################################
5753 11:35:50.583773
5754 11:35:50.847226 01680000 ################################################################
5755 11:35:50.847337
5756 11:35:51.124208 01700000 ################################################################
5757 11:35:51.124322
5758 11:35:51.392597 01780000 ################################################################
5759 11:35:51.392707
5760 11:35:51.661089 01800000 ################################################################
5761 11:35:51.661220
5762 11:35:51.942483 01880000 ################################################################
5763 11:35:51.942628
5764 11:35:52.213650 01900000 ################################################################
5765 11:35:52.213761
5766 11:35:52.513446 01980000 ################################################################
5767 11:35:52.513556
5768 11:35:52.803378 01a00000 ################################################################
5769 11:35:52.803489
5770 11:35:53.091505 01a80000 ################################################################
5771 11:35:53.091617
5772 11:35:53.421987 01b00000 ################################################################
5773 11:35:53.422097
5774 11:35:53.682436 01b80000 ################################################################
5775 11:35:53.682544
5776 11:35:53.954666 01c00000 ################################################################
5777 11:35:53.954775
5778 11:35:54.252994 01c80000 ################################################################
5779 11:35:54.253104
5780 11:35:54.521578 01d00000 ################################################################
5781 11:35:54.521719
5782 11:35:54.809463 01d80000 ################################################################
5783 11:35:54.809574
5784 11:35:55.052375 01e00000 ####################################################### done.
5785 11:35:55.052487
5786 11:35:55.055870 The bootfile was 31903630 bytes long.
5787 11:35:55.055978
5788 11:35:55.059310 Sending tftp read request... done.
5789 11:35:55.059388
5790 11:35:55.062718 Waiting for the transfer...
5791 11:35:55.062800
5792 11:35:55.062863 00000000 # done.
5793 11:35:55.062924
5794 11:35:55.072555 Command line loaded dynamically from TFTP file: 14864608/tftp-deploy-bhuaup7q/kernel/cmdline
5795 11:35:55.072658
5796 11:35:55.099150 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5797 11:35:55.099376
5798 11:35:55.099510 Loading FIT.
5799 11:35:55.099631
5800 11:35:55.103057 Image ramdisk-1 has 18725597 bytes.
5801 11:35:55.103311
5802 11:35:55.106035 Image fdt-1 has 57695 bytes.
5803 11:35:55.106230
5804 11:35:55.109225 Image kernel-1 has 13118294 bytes.
5805 11:35:55.109450
5806 11:35:55.116207 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5807 11:35:55.116532
5808 11:35:55.129693 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5809 11:35:55.130091
5810 11:35:55.132881 Choosing best match conf-1 for compat google,juniper-sku16.
5811 11:35:55.138570
5812 11:35:55.143679 Connected to device vid:did:rid of 1ae0:0028:00
5813 11:35:55.149843
5814 11:35:55.153495 tpm_get_response: command 0x17b, return code 0x0
5815 11:35:55.153967
5816 11:35:55.156408 tpm_cleanup: add release locality here.
5817 11:35:55.156798
5818 11:35:55.160409 Shutting down all USB controllers.
5819 11:35:55.161007
5820 11:35:55.163549 Removing current net device
5821 11:35:55.163972
5822 11:35:55.166329 Exiting depthcharge with code 4 at timestamp: 36124152
5823 11:35:55.166769
5824 11:35:55.169977 LZMA decompressing kernel-1 to 0x80193568
5825 11:35:55.170370
5826 11:35:55.176891 LZMA decompressing kernel-1 to 0x40000000
5827 11:35:57.039483
5828 11:35:57.039993 jumping to kernel
5829 11:35:57.041921 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5830 11:35:57.042539 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
5831 11:35:57.042917 Setting prompt string to ['Linux version [0-9]']
5832 11:35:57.043260 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5833 11:35:57.043629 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5834 11:35:57.114385
5835 11:35:57.117929 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5836 11:35:57.121967 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
5837 11:35:57.122461 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5838 11:35:57.122903 Setting prompt string to []
5839 11:35:57.123310 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5840 11:35:57.123679 Using line separator: #'\n'#
5841 11:35:57.123985 No login prompt set.
5842 11:35:57.124292 Parsing kernel messages
5843 11:35:57.124576 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5844 11:35:57.125107 [login-action] Waiting for messages, (timeout 00:04:07)
5845 11:35:57.125491 Waiting using forced prompt support (timeout 00:02:03)
5846 11:35:57.140860 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
5847 11:35:57.144361 [ 0.000000] random: crng init done
5848 11:35:57.147564 [ 0.000000] Machine model: Google juniper sku16 board
5849 11:35:57.151186 [ 0.000000] efi: UEFI not found.
5850 11:35:57.161268 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5851 11:35:57.167551 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5852 11:35:57.174612 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5853 11:35:57.180797 [ 0.000000] printk: bootconsole [mtk8250] enabled
5854 11:35:57.188664 [ 0.000000] NUMA: No NUMA configuration found
5855 11:35:57.195435 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5856 11:35:57.201818 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5857 11:35:57.202327 [ 0.000000] Zone ranges:
5858 11:35:57.208378 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5859 11:35:57.211304 [ 0.000000] DMA32 empty
5860 11:35:57.217842 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5861 11:35:57.221373 [ 0.000000] Movable zone start for each node
5862 11:35:57.224412 [ 0.000000] Early memory node ranges
5863 11:35:57.231091 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5864 11:35:57.237844 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5865 11:35:57.244588 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5866 11:35:57.250627 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5867 11:35:57.257788 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5868 11:35:57.264223 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5869 11:35:57.285351 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5870 11:35:57.291981 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5871 11:35:57.298504 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5872 11:35:57.301477 [ 0.000000] psci: probing for conduit method from DT.
5873 11:35:57.308706 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5874 11:35:57.312293 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5875 11:35:57.318244 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5876 11:35:57.321436 [ 0.000000] psci: SMC Calling Convention v1.1
5877 11:35:57.328096 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5878 11:35:57.331229 [ 0.000000] Detected VIPT I-cache on CPU0
5879 11:35:57.338352 [ 0.000000] CPU features: detected: GIC system register CPU interface
5880 11:35:57.344820 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5881 11:35:57.351371 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5882 11:35:57.358088 [ 0.000000] CPU features: detected: ARM erratum 845719
5883 11:35:57.361778 [ 0.000000] alternatives: applying boot alternatives
5884 11:35:57.364978 [ 0.000000] Fallback order for Node 0: 0
5885 11:35:57.371290 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5886 11:35:57.375024 [ 0.000000] Policy zone: Normal
5887 11:35:57.401509 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5888 11:35:57.414636 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5889 11:35:57.425515 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5890 11:35:57.431419 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5891 11:35:57.437406 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5892 11:35:57.444492 <6>[ 0.000000] software IO TLB: area num 8.
5893 11:35:57.469211 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5894 11:35:57.527161 <6>[ 0.000000] Memory: 3896784K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261680K reserved, 32768K cma-reserved)
5895 11:35:57.533652 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5896 11:35:57.540387 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5897 11:35:57.544253 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5898 11:35:57.550897 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5899 11:35:57.556787 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5900 11:35:57.559998 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5901 11:35:57.570382 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5902 11:35:57.577336 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5903 11:35:57.583183 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5904 11:35:57.593522 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5905 11:35:57.596973 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5906 11:35:57.599772 <6>[ 0.000000] GICv3: 640 SPIs implemented
5907 11:35:57.606762 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5908 11:35:57.609874 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5909 11:35:57.616415 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5910 11:35:57.623076 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5911 11:35:57.632762 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5912 11:35:57.646621 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5913 11:35:57.653178 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5914 11:35:57.664363 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5915 11:35:57.677246 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5916 11:35:57.684221 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5917 11:35:57.690483 <6>[ 0.009465] Console: colour dummy device 80x25
5918 11:35:57.694171 <6>[ 0.014502] printk: console [tty1] enabled
5919 11:35:57.704265 <6>[ 0.018893] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5920 11:35:57.710655 <6>[ 0.029358] pid_max: default: 32768 minimum: 301
5921 11:35:57.714154 <6>[ 0.034239] LSM: Security Framework initializing
5922 11:35:57.724088 <6>[ 0.039153] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5923 11:35:57.730482 <6>[ 0.046776] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5924 11:35:57.738119 <4>[ 0.055654] cacheinfo: Unable to detect cache hierarchy for CPU 0
5925 11:35:57.746935 <6>[ 0.062281] cblist_init_generic: Setting adjustable number of callback queues.
5926 11:35:57.753469 <6>[ 0.069727] cblist_init_generic: Setting shift to 3 and lim to 1.
5927 11:35:57.760590 <6>[ 0.076080] cblist_init_generic: Setting adjustable number of callback queues.
5928 11:35:57.767892 <6>[ 0.083524] cblist_init_generic: Setting shift to 3 and lim to 1.
5929 11:35:57.770740 <6>[ 0.089923] rcu: Hierarchical SRCU implementation.
5930 11:35:57.776559 <6>[ 0.094950] rcu: Max phase no-delay instances is 1000.
5931 11:35:57.783832 <6>[ 0.102860] EFI services will not be available.
5932 11:35:57.787164 <6>[ 0.107811] smp: Bringing up secondary CPUs ...
5933 11:35:57.797759 <6>[ 0.113054] Detected VIPT I-cache on CPU1
5934 11:35:57.803976 <4>[ 0.113102] cacheinfo: Unable to detect cache hierarchy for CPU 1
5935 11:35:57.810906 <6>[ 0.113110] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5936 11:35:57.817277 <6>[ 0.113142] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5937 11:35:57.821046 <6>[ 0.113623] Detected VIPT I-cache on CPU2
5938 11:35:57.827429 <4>[ 0.113656] cacheinfo: Unable to detect cache hierarchy for CPU 2
5939 11:35:57.833962 <6>[ 0.113660] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5940 11:35:57.840320 <6>[ 0.113673] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5941 11:35:57.848179 <6>[ 0.114119] Detected VIPT I-cache on CPU3
5942 11:35:57.850688 <4>[ 0.114150] cacheinfo: Unable to detect cache hierarchy for CPU 3
5943 11:35:57.861159 <6>[ 0.114155] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5944 11:35:57.867889 <6>[ 0.114166] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5945 11:35:57.871284 <6>[ 0.114739] CPU features: detected: Spectre-v2
5946 11:35:57.873894 <6>[ 0.114749] CPU features: detected: Spectre-BHB
5947 11:35:57.880248 <6>[ 0.114753] CPU features: detected: ARM erratum 858921
5948 11:35:57.884000 <6>[ 0.114758] Detected VIPT I-cache on CPU4
5949 11:35:57.890374 <4>[ 0.114806] cacheinfo: Unable to detect cache hierarchy for CPU 4
5950 11:35:57.897330 <6>[ 0.114814] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5951 11:35:57.906937 <6>[ 0.114822] arch_timer: Enabling local workaround for ARM erratum 858921
5952 11:35:57.910270 <6>[ 0.114832] arch_timer: CPU4: Trapping CNTVCT access
5953 11:35:57.916806 <6>[ 0.114840] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5954 11:35:57.919994 <6>[ 0.115326] Detected VIPT I-cache on CPU5
5955 11:35:57.926891 <4>[ 0.115365] cacheinfo: Unable to detect cache hierarchy for CPU 5
5956 11:35:57.936717 <6>[ 0.115371] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5957 11:35:57.943688 <6>[ 0.115378] arch_timer: Enabling local workaround for ARM erratum 858921
5958 11:35:57.946602 <6>[ 0.115384] arch_timer: CPU5: Trapping CNTVCT access
5959 11:35:57.953332 <6>[ 0.115389] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5960 11:35:57.960368 <6>[ 0.115827] Detected VIPT I-cache on CPU6
5961 11:35:57.963798 <4>[ 0.115873] cacheinfo: Unable to detect cache hierarchy for CPU 6
5962 11:35:57.973107 <6>[ 0.115879] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5963 11:35:57.979857 <6>[ 0.115885] arch_timer: Enabling local workaround for ARM erratum 858921
5964 11:35:57.983057 <6>[ 0.115892] arch_timer: CPU6: Trapping CNTVCT access
5965 11:35:57.990007 <6>[ 0.115897] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5966 11:35:57.996606 <6>[ 0.116427] Detected VIPT I-cache on CPU7
5967 11:35:57.999739 <4>[ 0.116469] cacheinfo: Unable to detect cache hierarchy for CPU 7
5968 11:35:58.010085 <6>[ 0.116475] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5969 11:35:58.016587 <6>[ 0.116482] arch_timer: Enabling local workaround for ARM erratum 858921
5970 11:35:58.020271 <6>[ 0.116489] arch_timer: CPU7: Trapping CNTVCT access
5971 11:35:58.026175 <6>[ 0.116494] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5972 11:35:58.032809 <6>[ 0.116541] smp: Brought up 1 node, 8 CPUs
5973 11:35:58.036280 <6>[ 0.355448] SMP: Total of 8 processors activated.
5974 11:35:58.042748 <6>[ 0.360383] CPU features: detected: 32-bit EL0 Support
5975 11:35:58.046025 <6>[ 0.365761] CPU features: detected: 32-bit EL1 Support
5976 11:35:58.052768 <6>[ 0.371129] CPU features: detected: CRC32 instructions
5977 11:35:58.056113 <6>[ 0.376552] CPU: All CPU(s) started at EL2
5978 11:35:58.062201 <6>[ 0.380890] alternatives: applying system-wide alternatives
5979 11:35:58.070313 <6>[ 0.388910] devtmpfs: initialized
5980 11:35:58.082480 <6>[ 0.397870] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5981 11:35:58.092304 <6>[ 0.407819] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5982 11:35:58.095646 <6>[ 0.415545] pinctrl core: initialized pinctrl subsystem
5983 11:35:58.103757 <6>[ 0.422651] DMI not present or invalid.
5984 11:35:58.110556 <6>[ 0.427023] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5985 11:35:58.117492 <6>[ 0.433925] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5986 11:35:58.127212 <6>[ 0.441438] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5987 11:35:58.134101 <6>[ 0.449608] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5988 11:35:58.141205 <6>[ 0.457754] audit: initializing netlink subsys (disabled)
5989 11:35:58.147284 <5>[ 0.463437] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
5990 11:35:58.153859 <6>[ 0.464397] thermal_sys: Registered thermal governor 'step_wise'
5991 11:35:58.160512 <6>[ 0.471388] thermal_sys: Registered thermal governor 'power_allocator'
5992 11:35:58.163963 <6>[ 0.477636] cpuidle: using governor menu
5993 11:35:58.170652 <6>[ 0.488585] NET: Registered PF_QIPCRTR protocol family
5994 11:35:58.177279 <6>[ 0.494072] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5995 11:35:58.183512 <6>[ 0.501167] ASID allocator initialised with 32768 entries
5996 11:35:58.187351 <6>[ 0.507945] Serial: AMBA PL011 UART driver
5997 11:35:58.200712 <4>[ 0.519280] Trying to register duplicate clock ID: 113
5998 11:35:58.260679 <6>[ 0.575758] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5999 11:35:58.275056 <6>[ 0.590150] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6000 11:35:58.278053 <6>[ 0.599933] KASLR enabled
6001 11:35:58.292425 <6>[ 0.607907] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
6002 11:35:58.299170 <6>[ 0.614911] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
6003 11:35:58.305615 <6>[ 0.621388] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
6004 11:35:58.312813 <6>[ 0.628380] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6005 11:35:58.319609 <6>[ 0.634854] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6006 11:35:58.325753 <6>[ 0.641845] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6007 11:35:58.332697 <6>[ 0.648320] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6008 11:35:58.339677 <6>[ 0.655309] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6009 11:35:58.342621 <6>[ 0.662880] ACPI: Interpreter disabled.
6010 11:35:58.352266 <6>[ 0.670843] iommu: Default domain type: Translated
6011 11:35:58.358629 <6>[ 0.675956] iommu: DMA domain TLB invalidation policy: strict mode
6012 11:35:58.362197 <5>[ 0.682588] SCSI subsystem initialized
6013 11:35:58.369247 <6>[ 0.687009] usbcore: registered new interface driver usbfs
6014 11:35:58.375488 <6>[ 0.692734] usbcore: registered new interface driver hub
6015 11:35:58.379044 <6>[ 0.698275] usbcore: registered new device driver usb
6016 11:35:58.386184 <6>[ 0.704575] pps_core: LinuxPPS API ver. 1 registered
6017 11:35:58.395747 <6>[ 0.709759] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6018 11:35:58.399659 <6>[ 0.719085] PTP clock support registered
6019 11:35:58.402384 <6>[ 0.723337] EDAC MC: Ver: 3.0.0
6020 11:35:58.410477 <6>[ 0.728982] FPGA manager framework
6021 11:35:58.416855 <6>[ 0.732667] Advanced Linux Sound Architecture Driver Initialized.
6022 11:35:58.420676 <6>[ 0.739422] vgaarb: loaded
6023 11:35:58.426894 <6>[ 0.742546] clocksource: Switched to clocksource arch_sys_counter
6024 11:35:58.430092 <5>[ 0.748976] VFS: Disk quotas dquot_6.6.0
6025 11:35:58.436539 <6>[ 0.753153] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6026 11:35:58.440148 <6>[ 0.760329] pnp: PnP ACPI: disabled
6027 11:35:58.448610 <6>[ 0.767230] NET: Registered PF_INET protocol family
6028 11:35:58.455306 <6>[ 0.772464] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6029 11:35:58.466966 <6>[ 0.782380] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6030 11:35:58.477083 <6>[ 0.791134] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6031 11:35:58.483546 <6>[ 0.799085] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6032 11:35:58.490193 <6>[ 0.807317] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6033 11:35:58.500930 <6>[ 0.815409] TCP: Hash tables configured (established 32768 bind 32768)
6034 11:35:58.506809 <6>[ 0.822238] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6035 11:35:58.513708 <6>[ 0.829214] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6036 11:35:58.519988 <6>[ 0.836695] NET: Registered PF_UNIX/PF_LOCAL protocol family
6037 11:35:58.526512 <6>[ 0.842834] RPC: Registered named UNIX socket transport module.
6038 11:35:58.530174 <6>[ 0.848980] RPC: Registered udp transport module.
6039 11:35:58.533302 <6>[ 0.853906] RPC: Registered tcp transport module.
6040 11:35:58.539942 <6>[ 0.858830] RPC: Registered tcp NFSv4.1 backchannel transport module.
6041 11:35:58.546850 <6>[ 0.865485] PCI: CLS 0 bytes, default 64
6042 11:35:58.549902 <6>[ 0.869773] Unpacking initramfs...
6043 11:35:58.575932 <6>[ 0.890666] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6044 11:35:58.585297 <6>[ 0.899311] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6045 11:35:58.588424 <6>[ 0.908165] kvm [1]: IPA Size Limit: 40 bits
6046 11:35:58.595918 <6>[ 0.914492] kvm [1]: vgic-v2@c420000
6047 11:35:58.599506 <6>[ 0.918309] kvm [1]: GIC system register CPU interface enabled
6048 11:35:58.605886 <6>[ 0.924478] kvm [1]: vgic interrupt IRQ18
6049 11:35:58.614549 <6>[ 0.930653] kvm [1]: Hyp mode initialized successfully
6050 11:35:58.619825 <5>[ 0.937034] Initialise system trusted keyrings
6051 11:35:58.625728 <6>[ 0.941890] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6052 11:35:58.632981 <6>[ 0.951826] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6053 11:35:58.640131 <5>[ 0.958260] NFS: Registering the id_resolver key type
6054 11:35:58.642883 <5>[ 0.963567] Key type id_resolver registered
6055 11:35:58.649944 <5>[ 0.967980] Key type id_legacy registered
6056 11:35:58.656632 <6>[ 0.972289] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6057 11:35:58.663584 <6>[ 0.979213] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6058 11:35:58.669434 <6>[ 0.986971] 9p: Installing v9fs 9p2000 file system support
6059 11:35:58.697850 <5>[ 1.016310] Key type asymmetric registered
6060 11:35:58.701459 <5>[ 1.020657] Asymmetric key parser 'x509' registered
6061 11:35:58.710818 <6>[ 1.025813] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6062 11:35:58.714390 <6>[ 1.033427] io scheduler mq-deadline registered
6063 11:35:58.717339 <6>[ 1.038184] io scheduler kyber registered
6064 11:35:58.740234 <6>[ 1.058900] EINJ: ACPI disabled.
6065 11:35:58.746700 <4>[ 1.062672] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6066 11:35:58.784682 <6>[ 1.103481] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6067 11:35:58.793579 <6>[ 1.112054] printk: console [ttyS0] disabled
6068 11:35:58.821466 <6>[ 1.136708] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6069 11:35:58.828273 <6>[ 1.146184] printk: console [ttyS0] enabled
6070 11:35:58.830984 <6>[ 1.146184] printk: console [ttyS0] enabled
6071 11:35:58.837742 <6>[ 1.155107] printk: bootconsole [mtk8250] disabled
6072 11:35:58.841248 <6>[ 1.155107] printk: bootconsole [mtk8250] disabled
6073 11:35:58.850888 <3>[ 1.165655] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6074 11:35:58.857507 <3>[ 1.174036] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6075 11:35:58.887299 <6>[ 1.202458] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6076 11:35:58.893616 <6>[ 1.212123] serial serial0: tty port ttyS1 registered
6077 11:35:58.900519 <6>[ 1.218749] SuperH (H)SCI(F) driver initialized
6078 11:35:58.903724 <6>[ 1.224252] msm_serial: driver initialized
6079 11:35:58.919332 <6>[ 1.234569] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6080 11:35:58.929075 <6>[ 1.243169] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6081 11:35:58.935589 <6>[ 1.251746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6082 11:35:58.945419 <6>[ 1.260321] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6083 11:35:58.952144 <6>[ 1.268976] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6084 11:35:58.962350 <6>[ 1.277642] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6085 11:35:58.972309 <6>[ 1.286382] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6086 11:35:58.978810 <6>[ 1.295124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6087 11:35:58.988595 <6>[ 1.303693] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6088 11:35:58.998929 <6>[ 1.312500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6089 11:35:59.006670 <4>[ 1.325006] cacheinfo: Unable to detect cache hierarchy for CPU 0
6090 11:35:59.015726 <6>[ 1.334372] loop: module loaded
6091 11:35:59.028219 <6>[ 1.346440] vsim1: Bringing 1800000uV into 2700000-2700000uV
6092 11:35:59.045510 <6>[ 1.364511] megasas: 07.719.03.00-rc1
6093 11:35:59.054762 <6>[ 1.373305] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6094 11:35:59.067376 <6>[ 1.385953] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6095 11:35:59.084099 <6>[ 1.402724] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6096 11:35:59.140901 <6>[ 1.453062] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6097 11:35:59.169017 <6>[ 1.487818] Freeing initrd memory: 18284K
6098 11:35:59.184587 <4>[ 1.499699] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6099 11:35:59.190847 <4>[ 1.508930] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6100 11:35:59.197615 <4>[ 1.515627] Hardware name: Google juniper sku16 board (DT)
6101 11:35:59.200699 <4>[ 1.521366] Call trace:
6102 11:35:59.204247 <4>[ 1.524066] dump_backtrace.part.0+0xe0/0xf0
6103 11:35:59.207966 <4>[ 1.528603] show_stack+0x18/0x30
6104 11:35:59.211248 <4>[ 1.532176] dump_stack_lvl+0x64/0x80
6105 11:35:59.217613 <4>[ 1.536096] dump_stack+0x18/0x34
6106 11:35:59.220892 <4>[ 1.539665] sysfs_warn_dup+0x64/0x80
6107 11:35:59.224330 <4>[ 1.543587] sysfs_do_create_link_sd+0xf0/0x100
6108 11:35:59.227813 <4>[ 1.548375] sysfs_create_link+0x20/0x40
6109 11:35:59.234232 <4>[ 1.552554] bus_add_device+0x64/0x120
6110 11:35:59.238077 <4>[ 1.556558] device_add+0x354/0x7ec
6111 11:35:59.241222 <4>[ 1.560304] of_device_add+0x44/0x60
6112 11:35:59.247324 <4>[ 1.564137] of_platform_device_create_pdata+0x90/0x124
6113 11:35:59.250985 <4>[ 1.569618] of_platform_bus_create+0x154/0x380
6114 11:35:59.254394 <4>[ 1.574405] of_platform_populate+0x50/0xfc
6115 11:35:59.260749 <4>[ 1.578843] parse_mtd_partitions+0x1d8/0x4e0
6116 11:35:59.264001 <4>[ 1.583460] mtd_device_parse_register+0xec/0x2e0
6117 11:35:59.267111 <4>[ 1.588421] spi_nor_probe+0x280/0x2f4
6118 11:35:59.273988 <4>[ 1.592426] spi_mem_probe+0x6c/0xc0
6119 11:35:59.277034 <4>[ 1.596259] spi_probe+0x84/0xe4
6120 11:35:59.280805 <4>[ 1.599744] really_probe+0xbc/0x2dc
6121 11:35:59.283990 <4>[ 1.603574] __driver_probe_device+0x78/0x114
6122 11:35:59.290397 <4>[ 1.608186] driver_probe_device+0xd8/0x15c
6123 11:35:59.294100 <4>[ 1.612623] __device_attach_driver+0xb8/0x134
6124 11:35:59.296959 <4>[ 1.617321] bus_for_each_drv+0x7c/0xd4
6125 11:35:59.300176 <4>[ 1.621414] __device_attach+0x9c/0x1a0
6126 11:35:59.307356 <4>[ 1.625504] device_initial_probe+0x14/0x20
6127 11:35:59.310597 <4>[ 1.629942] bus_probe_device+0x98/0xa0
6128 11:35:59.313698 <4>[ 1.634032] device_add+0x3c0/0x7ec
6129 11:35:59.316830 <4>[ 1.637777] __spi_add_device+0x78/0x120
6130 11:35:59.324563 <4>[ 1.641955] spi_add_device+0x44/0x80
6131 11:35:59.327267 <4>[ 1.645871] spi_register_controller+0x704/0xb20
6132 11:35:59.333638 <4>[ 1.650743] devm_spi_register_controller+0x4c/0xac
6133 11:35:59.336747 <4>[ 1.655876] mtk_spi_probe+0x4f4/0x684
6134 11:35:59.340638 <4>[ 1.659881] platform_probe+0x68/0xc0
6135 11:35:59.343452 <4>[ 1.663799] really_probe+0xbc/0x2dc
6136 11:35:59.350605 <4>[ 1.667629] __driver_probe_device+0x78/0x114
6137 11:35:59.353561 <4>[ 1.672241] driver_probe_device+0xd8/0x15c
6138 11:35:59.356900 <4>[ 1.676678] __driver_attach+0x94/0x19c
6139 11:35:59.360146 <4>[ 1.680769] bus_for_each_dev+0x74/0xd0
6140 11:35:59.363600 <4>[ 1.684861] driver_attach+0x24/0x30
6141 11:35:59.369957 <4>[ 1.688691] bus_add_driver+0x154/0x20c
6142 11:35:59.373593 <4>[ 1.692781] driver_register+0x78/0x130
6143 11:35:59.376808 <4>[ 1.696872] __platform_driver_register+0x28/0x34
6144 11:35:59.383511 <4>[ 1.701832] mtk_spi_driver_init+0x1c/0x28
6145 11:35:59.386775 <4>[ 1.706188] do_one_initcall+0x64/0x1dc
6146 11:35:59.390784 <4>[ 1.710279] kernel_init_freeable+0x218/0x284
6147 11:35:59.393597 <4>[ 1.714894] kernel_init+0x24/0x12c
6148 11:35:59.399907 <4>[ 1.718638] ret_from_fork+0x10/0x20
6149 11:35:59.408952 <6>[ 1.727519] tun: Universal TUN/TAP device driver, 1.6
6150 11:35:59.412104 <6>[ 1.733815] thunder_xcv, ver 1.0
6151 11:35:59.415323 <6>[ 1.737328] thunder_bgx, ver 1.0
6152 11:35:59.419058 <6>[ 1.740833] nicpf, ver 1.0
6153 11:35:59.430175 <6>[ 1.745198] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6154 11:35:59.433155 <6>[ 1.752684] hns3: Copyright (c) 2017 Huawei Corporation.
6155 11:35:59.436441 <6>[ 1.758290] hclge is initializing
6156 11:35:59.443448 <6>[ 1.761876] e1000: Intel(R) PRO/1000 Network Driver
6157 11:35:59.450101 <6>[ 1.767011] e1000: Copyright (c) 1999-2006 Intel Corporation.
6158 11:35:59.453248 <6>[ 1.773035] e1000e: Intel(R) PRO/1000 Network Driver
6159 11:35:59.460425 <6>[ 1.778255] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6160 11:35:59.466860 <6>[ 1.784449] igb: Intel(R) Gigabit Ethernet Network Driver
6161 11:35:59.473493 <6>[ 1.790106] igb: Copyright (c) 2007-2014 Intel Corporation.
6162 11:35:59.479850 <6>[ 1.795948] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6163 11:35:59.486323 <6>[ 1.802471] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6164 11:35:59.489496 <6>[ 1.809027] sky2: driver version 1.30
6165 11:35:59.496438 <6>[ 1.814273] usbcore: registered new device driver r8152-cfgselector
6166 11:35:59.503427 <6>[ 1.820818] usbcore: registered new interface driver r8152
6167 11:35:59.509708 <6>[ 1.826653] VFIO - User Level meta-driver version: 0.3
6168 11:35:59.516282 <6>[ 1.834436] mtu3 11201000.usb: uwk - reg:0x420, version:101
6169 11:35:59.522699 <4>[ 1.840311] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6170 11:35:59.529411 <6>[ 1.847580] mtu3 11201000.usb: dr_mode: 1, drd: auto
6171 11:35:59.536197 <6>[ 1.852805] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6172 11:35:59.539211 <6>[ 1.858993] mtu3 11201000.usb: usb3-drd: 0
6173 11:35:59.546446 <6>[ 1.864556] mtu3 11201000.usb: xHCI platform device register success...
6174 11:35:59.558820 <4>[ 1.873176] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6175 11:35:59.564718 <6>[ 1.881128] xhci-mtk 11200000.usb: xHCI Host Controller
6176 11:35:59.571172 <6>[ 1.886642] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6177 11:35:59.578345 <6>[ 1.894361] xhci-mtk 11200000.usb: USB3 root hub has no ports
6178 11:35:59.587913 <6>[ 1.900391] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6179 11:35:59.591137 <6>[ 1.909818] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6180 11:35:59.597725 <6>[ 1.915895] xhci-mtk 11200000.usb: xHCI Host Controller
6181 11:35:59.604485 <6>[ 1.921383] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6182 11:35:59.611768 <6>[ 1.929041] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6183 11:35:59.617766 <6>[ 1.935868] hub 1-0:1.0: USB hub found
6184 11:35:59.620969 <6>[ 1.939896] hub 1-0:1.0: 1 port detected
6185 11:35:59.631268 <6>[ 1.945264] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6186 11:35:59.634080 <6>[ 1.953879] hub 2-0:1.0: USB hub found
6187 11:35:59.641058 <3>[ 1.957907] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6188 11:35:59.647715 <6>[ 1.965784] usbcore: registered new interface driver usb-storage
6189 11:35:59.654167 <6>[ 1.972400] usbcore: registered new device driver onboard-usb-hub
6190 11:35:59.671202 <4>[ 1.986667] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6191 11:35:59.680359 <6>[ 1.998925] mt6397-rtc mt6358-rtc: registered as rtc0
6192 11:35:59.690530 <6>[ 2.004409] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-17T11:35:59 UTC (1721216159)
6193 11:35:59.693349 <6>[ 2.014282] i2c_dev: i2c /dev entries driver
6194 11:35:59.705415 <6>[ 2.020717] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6195 11:35:59.715224 <6>[ 2.029061] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6196 11:35:59.718622 <6>[ 2.037967] i2c 4-0058: Fixed dependency cycle(s) with /panel
6197 11:35:59.728843 <6>[ 2.043997] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6198 11:35:59.745191 <6>[ 2.063432] cpu cpu0: EM: created perf domain
6199 11:35:59.754930 <6>[ 2.068951] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6200 11:35:59.761851 <6>[ 2.080238] cpu cpu4: EM: created perf domain
6201 11:35:59.768660 <6>[ 2.086936] sdhci: Secure Digital Host Controller Interface driver
6202 11:35:59.774733 <6>[ 2.093390] sdhci: Copyright(c) Pierre Ossman
6203 11:35:59.781812 <6>[ 2.098796] Synopsys Designware Multimedia Card Interface Driver
6204 11:35:59.789231 <6>[ 2.099322] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6205 11:35:59.791829 <6>[ 2.105848] sdhci-pltfm: SDHCI platform and OF driver helper
6206 11:35:59.800104 <6>[ 2.118714] ledtrig-cpu: registered to indicate activity on CPUs
6207 11:35:59.808040 <6>[ 2.126452] usbcore: registered new interface driver usbhid
6208 11:35:59.811118 <6>[ 2.132296] usbhid: USB HID core driver
6209 11:35:59.821447 <6>[ 2.136633] spi_master spi2: will run message pump with realtime priority
6210 11:35:59.829075 <4>[ 2.136761] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6211 11:35:59.835775 <4>[ 2.151010] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6212 11:35:59.849338 <6>[ 2.156423] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6213 11:35:59.865476 <6>[ 2.174192] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6214 11:35:59.872971 <4>[ 2.182370] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6215 11:35:59.878710 <6>[ 2.195427] cros-ec-spi spi2.0: Chrome EC device registered
6216 11:35:59.885419 <4>[ 2.202714] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6217 11:35:59.899952 <4>[ 2.214675] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6218 11:35:59.905646 <4>[ 2.223854] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6219 11:35:59.919079 <6>[ 2.234046] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6220 11:35:59.925812 <6>[ 2.242745] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x12c14
6221 11:35:59.932300 <6>[ 2.250388] mmc0: new HS400 MMC card at address 0001
6222 11:35:59.938674 <6>[ 2.256667] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6223 11:35:59.948625 <6>[ 2.266885] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6224 11:35:59.956710 <6>[ 2.275487] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6225 11:35:59.963327 <6>[ 2.281918] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6226 11:35:59.970357 <6>[ 2.288165] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6227 11:35:59.980175 <6>[ 2.289742] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6228 11:35:59.995904 <6>[ 2.307728] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6229 11:36:00.005964 <6>[ 2.307972] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6230 11:36:00.015417 <6>[ 2.320002] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6231 11:36:00.022615 <6>[ 2.332317] NET: Registered PF_PACKET protocol family
6232 11:36:00.025803 <6>[ 2.346058] 9pnet: Installing 9P2000 support
6233 11:36:00.032482 <5>[ 2.350648] Key type dns_resolver registered
6234 11:36:00.035736 <6>[ 2.355846] registered taskstats version 1
6235 11:36:00.041861 <6>[ 2.358560] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6236 11:36:00.048561 <5>[ 2.360218] Loading compiled-in X.509 certificates
6237 11:36:00.087558 <3>[ 2.402362] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6238 11:36:00.119184 <6>[ 2.431026] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6239 11:36:00.129870 <6>[ 2.445344] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6240 11:36:00.139935 <6>[ 2.453963] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6241 11:36:00.147221 <6>[ 2.462552] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6242 11:36:00.156316 <6>[ 2.471087] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6243 11:36:00.163025 <6>[ 2.479610] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6244 11:36:00.173419 <6>[ 2.488132] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6245 11:36:00.179954 <6>[ 2.496650] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6246 11:36:00.187486 <6>[ 2.505822] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6247 11:36:00.194423 <6>[ 2.513154] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6248 11:36:00.200931 <6>[ 2.517074] hub 1-1:1.0: USB hub found
6249 11:36:00.207976 <6>[ 2.520331] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6250 11:36:00.211234 <6>[ 2.523974] hub 1-1:1.0: 3 ports detected
6251 11:36:00.217807 <6>[ 2.530847] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6252 11:36:00.224668 <6>[ 2.541838] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6253 11:36:00.231391 <6>[ 2.549936] panfrost 13040000.gpu: clock rate = 511999970
6254 11:36:00.241416 <6>[ 2.555622] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6255 11:36:00.251463 <6>[ 2.565508] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6256 11:36:00.258161 <6>[ 2.573521] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6257 11:36:00.271366 <6>[ 2.581953] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6258 11:36:00.277470 <6>[ 2.594029] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6259 11:36:00.290115 <6>[ 2.605184] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6260 11:36:00.299713 <6>[ 2.614195] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6261 11:36:00.309871 <6>[ 2.623346] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6262 11:36:00.317023 <6>[ 2.632477] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6263 11:36:00.326589 <6>[ 2.641604] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6264 11:36:00.336517 <6>[ 2.650905] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6265 11:36:00.347026 <6>[ 2.660207] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6266 11:36:00.356329 <6>[ 2.669683] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6267 11:36:00.365974 <6>[ 2.679158] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6268 11:36:00.372377 <6>[ 2.688285] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6269 11:36:00.444489 <6>[ 2.759595] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6270 11:36:00.454692 <6>[ 2.768503] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6271 11:36:00.465064 <6>[ 2.780549] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6272 11:36:00.511338 <6>[ 2.826584] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6273 11:36:01.168156 <6>[ 3.018951] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6274 11:36:01.178627 <4>[ 3.135767] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6275 11:36:01.184630 <4>[ 3.135785] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6276 11:36:01.191444 <6>[ 3.176559] r8152 1-1.2:1.0 eth0: v1.12.13
6277 11:36:01.197684 <6>[ 3.254577] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6278 11:36:01.204655 <6>[ 3.467068] Console: switching to colour frame buffer device 170x48
6279 11:36:01.210945 <6>[ 3.527715] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6280 11:36:01.232504 <6>[ 3.544821] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6281 11:36:01.253090 <6>[ 3.564256] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6282 11:36:01.259224 <6>[ 3.576797] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6283 11:36:01.269783 <6>[ 3.585033] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6284 11:36:01.280119 <6>[ 3.592944] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6285 11:36:01.300286 <6>[ 3.612079] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6286 11:36:02.439177 <6>[ 4.757744] r8152 1-1.2:1.0 eth0: carrier on
6287 11:36:04.813043 <5>[ 4.778583] Sending DHCP requests .., OK
6288 11:36:04.818872 <6>[ 7.134954] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6289 11:36:04.821873 <6>[ 7.143407] IP-Config: Complete:
6290 11:36:04.835287 <6>[ 7.146979] device=eth0, hwaddr=00:e0:4c:72:3d:67, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6291 11:36:04.845290 <6>[ 7.157881] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1, domain=lava-rack, nis-domain=(none)
6292 11:36:04.857220 <6>[ 7.172253] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6293 11:36:04.866281 <6>[ 7.172263] nameserver0=192.168.201.1
6294 11:36:04.873453 <6>[ 7.192230] clk: Disabling unused clocks
6295 11:36:04.878322 <6>[ 7.200247] ALSA device list:
6296 11:36:04.887559 <6>[ 7.206153] No soundcards found.
6297 11:36:04.896648 <6>[ 7.215098] Freeing unused kernel memory: 8512K
6298 11:36:04.904150 <6>[ 7.222267] Run /init as init process
6299 11:36:04.915630 Loading, please wait...
6300 11:36:04.952453 Starting systemd-udevd version 252.22-1~deb12u1
6301 11:36:05.262338 <6>[ 7.577787] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6302 11:36:05.269604 <3>[ 7.586727] mtk-scp 10500000.scp: invalid resource
6303 11:36:05.279735 <6>[ 7.594996] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6304 11:36:05.289629 <4>[ 7.595194] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6305 11:36:05.296526 <4>[ 7.607089] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6306 11:36:05.306503 <6>[ 7.617724] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6307 11:36:05.318434 <4>[ 7.632434] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6308 11:36:05.321947 <6>[ 7.632531] remoteproc remoteproc0: scp is available
6309 11:36:05.331550 <4>[ 7.632627] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6310 11:36:05.338594 <6>[ 7.632634] remoteproc remoteproc0: powering up scp
6311 11:36:05.349927 <4>[ 7.632650] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6312 11:36:05.355783 <3>[ 7.632653] remoteproc remoteproc0: request_firmware failed: -2
6313 11:36:05.365468 <6>[ 7.638879] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6314 11:36:05.376084 <3>[ 7.643051] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6315 11:36:05.386136 <5>[ 7.664449] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6316 11:36:05.392972 <3>[ 7.672573] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6317 11:36:05.402554 <3>[ 7.672587] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6318 11:36:05.412546 <3>[ 7.672594] elan_i2c 2-0015: Error applying setting, reverse things back
6319 11:36:05.416159 <6>[ 7.683978] mc: Linux media interface: v0.10
6320 11:36:05.422475 <5>[ 7.704892] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6321 11:36:05.433359 <3>[ 7.720773] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6322 11:36:05.439529 <5>[ 7.728195] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6323 11:36:05.449862 <3>[ 7.734710] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6324 11:36:05.459965 <6>[ 7.739072] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6325 11:36:05.466760 <4>[ 7.739285] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6326 11:36:05.480201 <3>[ 7.740359] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6327 11:36:05.487510 <6>[ 7.743454] videodev: Linux video capture interface: v2.00
6328 11:36:05.497432 <3>[ 7.746023] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6329 11:36:05.504547 <6>[ 7.750289] cs_system_cfg: CoreSight Configuration manager initialised
6330 11:36:05.507917 <6>[ 7.754563] cfg80211: failed to load regulatory.db
6331 11:36:05.517952 <6>[ 7.778721] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6332 11:36:05.527726 <3>[ 7.783233] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6333 11:36:05.534404 <6>[ 7.809428] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6334 11:36:05.544281 <3>[ 7.812095] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6335 11:36:05.550833 <6>[ 7.820956] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6336 11:36:05.560688 <3>[ 7.828198] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6337 11:36:05.564367 <6>[ 7.828329] Bluetooth: Core ver 2.22
6338 11:36:05.570727 <6>[ 7.828382] NET: Registered PF_BLUETOOTH protocol family
6339 11:36:05.577267 <6>[ 7.828385] Bluetooth: HCI device and connection manager initialized
6340 11:36:05.580548 <6>[ 7.828402] Bluetooth: HCI socket layer initialized
6341 11:36:05.587112 <6>[ 7.828408] Bluetooth: L2CAP socket layer initialized
6342 11:36:05.593631 <6>[ 7.828417] Bluetooth: SCO socket layer initialized
6343 11:36:05.600205 <6>[ 7.832924] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6344 11:36:05.607151 <6>[ 7.842478] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6345 11:36:05.616772 <3>[ 7.842564] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6346 11:36:05.623834 <3>[ 7.842574] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6347 11:36:05.633827 <3>[ 7.842613] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6348 11:36:05.640401 <6>[ 7.850872] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6349 11:36:05.646458 <6>[ 7.858812] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6350 11:36:05.656927 Begin: Loading essential drivers<6>[ 7.859342] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6351 11:36:05.659911 ... done.
6352 11:36:05.667446 Begin: Running /scri<6>[ 7.859495] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6353 11:36:05.670371 pts/init-premount ... done.
6354 11:36:05.680661 Beg<6>[ 7.859637] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video1 (81,1)
6355 11:36:05.687341 in: Mounting root file system ..<6>[ 7.875212] Bluetooth: HCI UART driver ver 2.3
6356 11:36:05.697050 . Begin: Running /scripts/nfs-to<6>[ 7.875841] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6357 11:36:05.700505 p ... done.
6358 11:36:05.706716 Begin: Running /scr<6>[ 7.884308] Bluetooth: HCI UART protocol H4 registered
6359 11:36:05.720037 ipts/nfs-premount ... Waiting up<6>[ 7.885697] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6360 11:36:05.730487 to 60 secs for any ethernet to <6>[ 7.885849] usbcore: registered new interface driver uvcvideo
6361 11:36:05.730877 become available
6362 11:36:05.739786 Device /sys/cl<6>[ 7.888151] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6363 11:36:05.740204 ass/net/eth0 found
6364 11:36:05.743228 done.
6365 11:36:05.753285 Begin<3>[ 7.888329] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6366 11:36:05.763188 : Waiting up to 180 secs for any<3>[ 7.888969] debugfs: File 'Playback' in directory 'dapm' already present!
6367 11:36:05.773057 network device to become availa<3>[ 7.888974] debugfs: File 'Capture' in directory 'dapm' already present!
6368 11:36:05.776620 ble ... done.
6369 11:36:05.786596 <6>[ 7.890222] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6370 11:36:05.793547 <3>[ 7.891574] thermal_sys: Failed to find 'trips' node
6371 11:36:05.801065 <3>[ 7.891581] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6372 11:36:05.811772 <3>[ 7.891588] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6373 11:36:05.821791 <4>[ 7.891591] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6374 11:36:05.829171 <3>[ 7.892847] thermal_sys: Failed to find 'trips' node
6375 11:36:05.836788 <3>[ 7.892850] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6376 11:36:05.842948 <3>[ 7.892856] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6377 11:36:05.854862 <4>[ 7.892858] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6378 11:36:05.860707 <6>[ 7.893636] Bluetooth: HCI UART protocol LL registered
6379 11:36:05.870747 <6>[ 7.900340] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6380 11:36:05.878024 <6>[ 7.905356] Bluetooth: HCI UART protocol Three-wire (H5) registered
6381 11:36:05.887179 <6>[ 7.915781] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6382 11:36:05.893993 <6>[ 7.916865] Bluetooth: HCI UART protocol Broadcom registered
6383 11:36:05.904145 <6>[ 7.928563] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6384 11:36:05.910559 <6>[ 7.931268] Bluetooth: HCI UART protocol QCA registered
6385 11:36:05.917315 <6>[ 7.932511] Bluetooth: hci0: setting up ROME/QCA6390
6386 11:36:05.927453 <6>[ 7.939788] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6387 11:36:05.933681 <6>[ 7.948305] Bluetooth: HCI UART protocol Marvell registered
6388 11:36:05.944169 <6>[ 7.957234] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6389 11:36:05.954611 <4>[ 8.116986] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6390 11:36:05.958075 <4>[ 8.116986] Fallback method does not support PEC.
6391 11:36:05.964687 <3>[ 8.149759] Bluetooth: hci0: Frame reassembly failed (-84)
6392 11:36:05.974679 IP-Config: eth0 <3>[ 8.155265] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6393 11:36:05.984352 hardware address<6>[ 8.266819] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6394 11:36:05.994585 00:e0:4c:72:3d:<3>[ 8.275076] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6395 11:36:05.995110 67 mtu 1500 DHCP
6396 11:36:05.997783 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6397 11:36:06.007574 address: 192.168.201.13 broadcast: 192.168.201.255 netmask: 255.255.255.0
6398 11:36:06.014092 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6399 11:36:06.021026 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-1
6400 11:36:06.027113 domain : lava-rack
6401 11:36:06.031109 rootserver: 192.168.201.1 rootpath:
6402 11:36:06.031494 filename :
6403 11:36:06.104567 <6>[ 8.423155] Bluetooth: hci0: QCA Product ID :0x00000008
6404 11:36:06.114930 <6>[ 8.433197] Bluetooth: hci0: QCA SOC Version :0x00000044
6405 11:36:06.115080 done.
6406 11:36:06.127458 Begin: Running /<6>[ 8.443961] Bluetooth: hci0: QCA ROM Version :0x00000302
6407 11:36:06.127624 scripts/nfs-bottom ... done.
6408 11:36:06.137099 Begin: Running /sc<6>[ 8.452826] Bluetooth: hci0: QCA Patch Version:0x00000111
6409 11:36:06.145090 ripts/init-bottom ... <6>[ 8.463781] Bluetooth: hci0: QCA controller version 0x00440302
6410 11:36:06.148777 done.
6411 11:36:06.154957 <6>[ 8.472870] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6412 11:36:06.168249 <4>[ 8.483578] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6413 11:36:06.179817 <3>[ 8.495326] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6414 11:36:06.187163 <3>[ 8.505655] Bluetooth: hci0: QCA Failed to download patch (-2)
6415 11:36:06.324944 <6>[ 8.639955] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6416 11:36:06.406664 <4>[ 8.721773] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6417 11:36:06.426447 <4>[ 8.741187] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6418 11:36:06.441725 <4>[ 8.756762] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6419 11:36:06.452290 <4>[ 8.770354] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6420 11:36:07.580039 <6>[ 9.898816] NET: Registered PF_INET6 protocol family
6421 11:36:07.592723 <6>[ 9.911206] Segment Routing with IPv6
6422 11:36:07.601032 <6>[ 9.919635] In-situ OAM (IOAM) with IPv6
6423 11:36:07.787103 <30>[ 10.078650] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6424 11:36:07.807503 <30>[ 10.125736] systemd[1]: Detected architecture arm64.
6425 11:36:07.820035
6426 11:36:07.823942 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6427 11:36:07.824450
6428 11:36:07.845671 <30>[ 10.164439] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6429 11:36:09.019294 <30>[ 11.334404] systemd[1]: Queued start job for default target graphical.target.
6430 11:36:09.064961 <30>[ 11.380214] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6431 11:36:09.078484 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6432 11:36:09.097790 <30>[ 11.412760] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6433 11:36:09.111605 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6434 11:36:09.129831 <30>[ 11.445019] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6435 11:36:09.144741 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6436 11:36:09.165573 <30>[ 11.480223] systemd[1]: Created slice user.slice - User and Session Slice.
6437 11:36:09.177804 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6438 11:36:09.199954 <30>[ 11.511146] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6439 11:36:09.213496 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6440 11:36:09.235176 <30>[ 11.546990] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6441 11:36:09.247637 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6442 11:36:09.273882 <30>[ 11.578924] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6443 11:36:09.293151 <30>[ 11.608418] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6444 11:36:09.301157 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6445 11:36:09.319893 <30>[ 11.634755] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6446 11:36:09.332993 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6447 11:36:09.351539 <30>[ 11.666786] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6448 11:36:09.366022 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6449 11:36:09.380867 <30>[ 11.698844] systemd[1]: Reached target paths.target - Path Units.
6450 11:36:09.395463 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6451 11:36:09.411657 <30>[ 11.726747] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6452 11:36:09.424573 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6453 11:36:09.436737 <30>[ 11.754719] systemd[1]: Reached target slices.target - Slice Units.
6454 11:36:09.450873 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6455 11:36:09.464650 <30>[ 11.782754] systemd[1]: Reached target swap.target - Swaps.
6456 11:36:09.475464 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6457 11:36:09.495489 <30>[ 11.810808] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6458 11:36:09.509456 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6459 11:36:09.528086 <30>[ 11.843163] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6460 11:36:09.543283 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6461 11:36:09.562796 <30>[ 11.877988] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6462 11:36:09.576584 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6463 11:36:09.597527 <30>[ 11.912425] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6464 11:36:09.611848 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6465 11:36:09.628471 <30>[ 11.943508] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6466 11:36:09.640888 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6467 11:36:09.661654 <30>[ 11.976539] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6468 11:36:09.675270 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6469 11:36:09.695964 <30>[ 12.010420] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6470 11:36:09.709095 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6471 11:36:09.728880 <30>[ 12.043377] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6472 11:36:09.741801 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6473 11:36:09.783776 <30>[ 12.098927] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6474 11:36:09.794921 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6475 11:36:09.816364 <30>[ 12.131581] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6476 11:36:09.829361 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6477 11:36:09.852816 <30>[ 12.168263] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6478 11:36:09.864959 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6479 11:36:09.890477 <30>[ 12.199179] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6480 11:36:09.936434 <30>[ 12.251506] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6481 11:36:09.949340 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6482 11:36:09.974446 <30>[ 12.289252] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6483 11:36:09.986033 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6484 11:36:10.010404 <30>[ 12.325052] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6485 11:36:10.020801 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6486 11:36:10.053489 <6>[ 12.368403] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6487 11:36:10.072851 <30>[ 12.388119] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6488 11:36:10.083480 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6489 11:36:10.105705 <30>[ 12.420937] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6490 11:36:10.117691 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6491 11:36:10.142840 <30>[ 12.457476] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6492 11:36:10.152976 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6493 11:36:10.176210 <30>[ 12.491139] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6494 11:36:10.185333 Startin<6>[ 12.504653] fuse: init (API version 7.37)
6495 11:36:10.191452 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6496 11:36:10.237282 <30>[ 12.551632] systemd[1]: Starting systemd-journald.service - Journal Service...
6497 11:36:10.247203 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6498 11:36:10.274798 <30>[ 12.590127] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6499 11:36:10.285182 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6500 11:36:10.337168 <30>[ 12.648491] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6501 11:36:10.348518 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6502 11:36:10.372979 <30>[ 12.688494] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6503 11:36:10.385965 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6504 11:36:10.424736 <30>[ 12.739401] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6505 11:36:10.439601 Starting [0;1;39msyste<3>[ 12.752471] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6506 11:36:10.442556 md-udev-trig…[0m - Coldplug All udev Devices...
6507 11:36:10.456431 <3>[ 12.771000] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6508 11:36:10.468613 <30>[ 12.786023] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6509 11:36:10.478692 <3>[ 12.790081] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6510 11:36:10.498250 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File S<3>[ 12.811662] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6511 11:36:10.498715 ystem.
6512 11:36:10.515320 <3>[ 12.830227] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6513 11:36:10.525979 <30>[ 12.839233] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6514 11:36:10.532948 <3>[ 12.846609] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6515 11:36:10.552721 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 12.866509] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6516 11:36:10.553152 File System.
6517 11:36:10.570412 <3>[ 12.884993] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6518 11:36:10.580303 <30>[ 12.894079] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6519 11:36:10.591345 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6520 11:36:10.608684 <30>[ 12.923375] systemd[1]: Started systemd-journald.service - Journal Service.
6521 11:36:10.618226 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6522 11:36:10.639008 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6523 11:36:10.662665 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6524 11:36:10.683569 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6525 11:36:10.705163 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6526 11:36:10.725312 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6527 11:36:10.749284 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6528 11:36:10.769253 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6529 11:36:10.792713 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6530 11:36:10.812585 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6531 11:36:10.832221 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6532 11:36:10.857638 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6533 11:36:10.904383 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6534 11:36:10.922490 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6535 11:36:10.929230 <4>[ 13.245473] power_supply_show_property: 2 callbacks suppressed
6536 11:36:10.936043 <3>[ 13.245483] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6537 11:36:10.953655 <4>[ 13.261188] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6538 11:36:10.962579 <3>[ 13.261377] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6539 11:36:10.976994 <3>[ 13.277520] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6540 11:36:10.999198 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage..<3>[ 13.312326] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6541 11:36:10.999663 .
6542 11:36:11.016096 <3>[ 13.330646] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6543 11:36:11.033274 <3>[ 13.347452] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6544 11:36:11.048598 <3>[ 13.363483] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6545 11:36:11.055896 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6546 11:36:11.066214 <3>[ 13.381131] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6547 11:36:11.083176 <3>[ 13.398271] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6548 11:36:11.101488 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<3>[ 13.414574] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6549 11:36:11.102030 .
6550 11:36:11.116563 <3>[ 13.431562] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6551 11:36:11.125361 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6552 11:36:11.139982 <46>[ 13.455161] systemd-journald[319]: Received client request to flush runtime journal.
6553 11:36:11.160094 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6554 11:36:11.180692 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6555 11:36:11.200232 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6556 11:36:11.222239 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6557 11:36:11.241747 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6558 11:36:12.239855 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6559 11:36:12.308861 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6560 11:36:12.590131 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6561 11:36:12.721493 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6562 11:36:12.740308 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6563 11:36:12.759827 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6564 11:36:12.808490 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6565 11:36:12.833832 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6566 11:36:13.114653 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6567 11:36:13.167604 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6568 11:36:13.209311 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6569 11:36:13.462800 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6570 11:36:13.481327 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6571 11:36:13.499212 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6572 11:36:13.547813 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6573 11:36:13.614335 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6574 11:36:13.657195 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6575 11:36:13.740122 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6576 11:36:13.756833 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6577 11:36:13.802061 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6578 11:36:13.889666 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6579 11:36:13.914859 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6580 11:36:13.936759 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6581 11:36:13.966090 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6582 11:36:13.985779 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6583 11:36:14.006552 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6584 11:36:14.027917 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6585 11:36:14.049969 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6586 11:36:14.073099 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6587 11:36:14.092916 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6588 11:36:14.113390 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6589 11:36:14.135391 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6590 11:36:14.158058 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6591 11:36:14.182637 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6592 11:36:14.201955 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6593 11:36:14.219951 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6594 11:36:14.238057 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6595 11:36:14.258238 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6596 11:36:14.275766 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6597 11:36:14.291883 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6598 11:36:14.309330 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6599 11:36:14.327566 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6600 11:36:14.344157 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6601 11:36:14.416523 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6602 11:36:14.434206 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6603 11:36:14.466317 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6604 11:36:14.524522 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6605 11:36:14.553488 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6606 11:36:14.569070 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6607 11:36:14.589933 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6608 11:36:14.762315 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6609 11:36:14.820866 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6610 11:36:14.880286 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6611 11:36:14.891196 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6612 11:36:14.913010 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6613 11:36:14.953342 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6614 11:36:14.978528 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6615 11:36:14.999525 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6616 11:36:15.017884 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6617 11:36:15.064476 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6618 11:36:15.160169 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6619 11:36:15.238979
6620 11:36:15.242368 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6621 11:36:15.242466
6622 11:36:15.245727 debian-bookworm-arm64 login: root (automatic login)
6623 11:36:15.245794
6624 11:36:15.527102 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
6625 11:36:15.527241
6626 11:36:15.533811 The programs included with the Debian GNU/Linux system are free software;
6627 11:36:15.540535 the exact distribution terms for each program are described in the
6628 11:36:15.543193 individual files in /usr/share/doc/*/copyright.
6629 11:36:15.543285
6630 11:36:15.549981 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6631 11:36:15.553420 permitted by applicable law.
6632 11:36:16.648924 Matched prompt #10: / #
6634 11:36:16.649216 Setting prompt string to ['/ #']
6635 11:36:16.649304 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6637 11:36:16.649483 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6638 11:36:16.649564 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6639 11:36:16.649626 Setting prompt string to ['/ #']
6640 11:36:16.649680 Forcing a shell prompt, looking for ['/ #']
6641 11:36:16.649733 Sending line: ''
6643 11:36:16.700134 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6644 11:36:16.700201 Waiting using forced prompt support (timeout 00:02:30)
6645 11:36:16.705438 / #
6646 11:36:16.705700 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6647 11:36:16.705787 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6648 11:36:16.705860 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s'"
6650 11:36:16.812434 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864608/extract-nfsrootfs-02f_h40s'
6651 11:36:16.813053 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6653 11:36:16.919396 / # export NFS_SERVER_IP='192.168.201.1'
6654 11:36:16.919758 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6655 11:36:16.919927 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6656 11:36:16.920084 end: 2 depthcharge-action (duration 00:01:13) [common]
6657 11:36:16.920231 start: 3 lava-test-retry (timeout 00:08:08) [common]
6658 11:36:16.920375 start: 3.1 lava-test-shell (timeout 00:08:08) [common]
6659 11:36:16.920502 Using namespace: common
6660 11:36:16.920618 Sending line: '#'
6662 11:36:17.021595 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6663 11:36:17.027189 / # #
6664 11:36:17.027854 Using /lava-14864608
6665 11:36:17.028227 Sending line: 'export SHELL=/bin/bash'
6667 11:36:17.135666 / # export SHELL=/bin/bash
6668 11:36:17.136273 Sending line: '. /lava-14864608/environment'
6670 11:36:17.243810 / # . /lava-14864608/environment
6671 11:36:17.249815 Sending line: '/lava-14864608/bin/lava-test-runner /lava-14864608/0'
6673 11:36:17.351079 Test shell timeout: 10s (minimum of the action and connection timeout)
6674 11:36:17.356650 / # /lava-14864608/bin/lava-test-runner /lava-14864608/0
6675 11:36:17.620197 + export TESTRUN_ID=0_timesync-off
6676 11:36:17.623367 + TESTRUN_ID=0_timesync-off
6677 11:36:17.626668 + cd /lava-14864608/0/tests/0_timesync-off
6678 11:36:17.630241 ++ cat uuid
6679 11:36:17.630310 + UUID=14864608_1.6.2.3.1
6680 11:36:17.633583 + set +x
6681 11:36:17.636639 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14864608_1.6.2.3.1>
6682 11:36:17.636921 Received signal: <STARTRUN> 0_timesync-off 14864608_1.6.2.3.1
6683 11:36:17.637014 Starting test lava.0_timesync-off (14864608_1.6.2.3.1)
6684 11:36:17.637151 Skipping test definition patterns.
6685 11:36:17.640336 + systemctl stop systemd-timesyncd
6686 11:36:17.680896 + set +x
6687 11:36:17.684635 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14864608_1.6.2.3.1>
6688 11:36:17.684879 Received signal: <ENDRUN> 0_timesync-off 14864608_1.6.2.3.1
6689 11:36:17.684953 Ending use of test pattern.
6690 11:36:17.685009 Ending test lava.0_timesync-off (14864608_1.6.2.3.1), duration 0.05
6692 11:36:17.739804 + export TESTRUN_ID=1_kselftest-alsa
6693 11:36:17.743101 + TESTRUN_ID=1_kselftest-alsa
6694 11:36:17.749478 + cd /lava-14864608/0/tests/1_kselftest-alsa
6695 11:36:17.749552 ++ cat uuid
6696 11:36:17.752948 + UUID=14864608_1.6.2.3.5
6697 11:36:17.753014 + set +x
6698 11:36:17.759458 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14864608_1.6.2.3.5>
6699 11:36:17.759695 Received signal: <STARTRUN> 1_kselftest-alsa 14864608_1.6.2.3.5
6700 11:36:17.759756 Starting test lava.1_kselftest-alsa (14864608_1.6.2.3.5)
6701 11:36:17.759826 Skipping test definition patterns.
6702 11:36:17.762792 + cd ./automated/linux/kselftest/
6703 11:36:17.792659 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
6704 11:36:17.822483 INFO: install_deps skipped
6705 11:36:18.317856 --2024-07-17 11:36:18-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
6706 11:36:18.324920 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6707 11:36:18.455378 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6708 11:36:18.584562 HTTP request sent, awaiting response... 200 OK
6709 11:36:18.587832 Length: 1920476 (1.8M) [application/octet-stream]
6710 11:36:18.591563 Saving to: 'kselftest_armhf.tar.gz'
6711 11:36:18.591983
6712 11:36:18.592290
6713 11:36:18.843879 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6714 11:36:19.102311 kselftest_armhf.tar 2%[ ] 50.15K 194KB/s
6715 11:36:19.412066 kselftest_armhf.tar 11%[=> ] 213.25K 412KB/s
6716 11:36:19.544713 kselftest_armhf.tar 44%[=======> ] 825.54K 999KB/s
6717 11:36:19.551376 kselftest_armhf.tar 100%[===================>] 1.83M 1.91MB/s in 1.0s
6718 11:36:19.551455
6719 11:36:19.720800 2024-07-17 11:36:19 (1.91 MB/s) - 'kselftest_armhf.tar.gz' saved [1920476/1920476]
6720 11:36:19.720922
6721 11:36:26.442918 skiplist:
6722 11:36:26.445982 ========================================
6723 11:36:26.449294 ========================================
6724 11:36:26.495359 alsa:mixer-test
6725 11:36:26.519607 ============== Tests to run ===============
6726 11:36:26.519689 alsa:mixer-test
6727 11:36:26.525502 ===========End Tests to run ===============
6728 11:36:26.525578 shardfile-alsa pass
6729 11:36:26.629066 <12>[ 28.947404] kselftest: Running tests in alsa
6730 11:36:26.639085 TAP version 13
6731 11:36:26.653702 1..1
6732 11:36:26.670827 # selftests: alsa: mixer-test
6733 11:36:26.778178 <6>[ 29.090129] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6734 11:36:26.791989 <6>[ 29.102497] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6735 11:36:26.805064 <6>[ 29.114766] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6736 11:36:26.815062 <6>[ 29.127017] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6737 11:36:26.827976 <6>[ 29.139233] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6738 11:36:26.838180 <6>[ 29.151503] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6739 11:36:26.851435 <6>[ 29.162883] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6740 11:36:26.860851 <6>[ 29.174231] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6741 11:36:26.874272 <6>[ 29.185570] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6742 11:36:26.884015 <6>[ 29.196907] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6743 11:36:26.897484 <6>[ 29.208247] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6744 11:36:26.907254 <6>[ 29.219582] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6745 11:36:26.917699 <6>[ 29.230913] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6746 11:36:26.930962 <6>[ 29.242241] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6747 11:36:26.940444 <6>[ 29.253578] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6748 11:36:26.953922 <6>[ 29.264917] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6749 11:36:26.964498 <6>[ 29.276255] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6750 11:36:26.977056 <6>[ 29.287589] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6751 11:36:26.986708 <6>[ 29.298933] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6752 11:36:26.997249 <6>[ 29.310272] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6753 11:36:27.010280 <6>[ 29.321613] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6754 11:36:27.019801 <6>[ 29.332968] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6755 11:36:27.033025 <6>[ 29.344347] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6756 11:36:27.043317 <6>[ 29.355728] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6757 11:36:27.056045 <6>[ 29.367111] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6758 11:36:27.065981 # TAP version 13<6>[ 29.378503] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6759 11:36:27.066058
6760 11:36:27.069617 # 1..658
6761 11:36:27.079572 # ok<6>[ 29.391137] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6762 11:36:27.093123 1 get_value.0.9<6>[ 29.403802] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6763 11:36:27.093202 3
6764 11:36:27.105852 # ok 2 name.0<6>[ 29.416496] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6765 11:36:27.105929 .93
6766 11:36:27.119250 # ok 3 writ<6>[ 29.429186] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6767 11:36:27.119327 e_default.0.93
6768 11:36:27.122839 # ok 4 write_valid.0.93
6769 11:36:27.125775 # ok 5 write_invalid.0.93
6770 11:36:27.125851 # ok 6 event_missing.0.93
6771 11:36:27.129040 # ok 7 event_spurious.0.93
6772 11:36:27.132659 # ok 8 get_value.0.92
6773 11:36:27.132734 # ok 9 name.0.92
6774 11:36:27.135840 # ok 10 write_default.0.92
6775 11:36:27.139322 # ok 11 write_valid.0.92
6776 11:36:27.139397 # ok 12 write_invalid.0.92
6777 11:36:27.142481 # ok 13 event_missing.0.92
6778 11:36:27.146072 # ok 14 event_spurious.0.92
6779 11:36:27.149111 # ok 15 get_value.0.91
6780 11:36:27.149193 # ok 16 name.0.91
6781 11:36:27.152187 # ok 17 write_default.0.91
6782 11:36:27.156121 # ok 18 write_valid.0.91
6783 11:36:27.156195 # ok 19 write_invalid.0.91
6784 11:36:27.159266 # ok 20 event_missing.0.91
6785 11:36:27.162524 # ok 21 event_spurious.0.91
6786 11:36:27.165533 # ok 22 get_value.0.90
6787 11:36:27.165609 # ok 23 name.0.90
6788 11:36:27.168847 # ok 24 write_default.0.90
6789 11:36:27.172264 # ok 25 write_valid.0.90
6790 11:36:27.175316 # ok 26 write_invalid.0.90
6791 11:36:27.175391 # ok 27 event_missing.0.90
6792 11:36:27.179098 # ok 28 event_spurious.0.90
6793 11:36:27.182906 # ok 29 get_value.0.89
6794 11:36:27.182982 # ok 30 name.0.89
6795 11:36:27.185936 # ok 31 write_default.0.89
6796 11:36:27.188993 # ok 32 write_valid.0.89
6797 11:36:27.192237 # ok 33 write_invalid.0.89
6798 11:36:27.195491 # ok 34 event_missing.0.89
6799 11:36:27.195580 # ok 35 event_spurious.0.89
6800 11:36:27.198752 # ok 36 get_value.0.88
6801 11:36:27.202375 # ok 37 name.0.88
6802 11:36:27.202448 # ok 38 write_default.0.88
6803 11:36:27.209270 # # Spurious event generated for AIF Out Mux
6804 11:36:27.212215 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6805 11:36:27.218827 # # Spurious event generated for AIF Out Mux
6806 11:36:27.222091 # not ok 39 write_valid.0.88
6807 11:36:27.222165 # ok 40 write_invalid.0.88
6808 11:36:27.225743 # ok 41 event_missing.0.88
6809 11:36:27.228564 # not ok 42 event_spurious.0.88
6810 11:36:27.231785 # ok 43 get_value.0.87
6811 11:36:27.231859 # ok 44 name.0.87
6812 11:36:27.235569 # ok 45 write_default.0.87
6813 11:36:27.238733 # ok 46 write_valid.0.87
6814 11:36:27.241921 # ok 47 write_invalid.0.87
6815 11:36:27.245641 # ok 48 event_missing.0.87
6816 11:36:27.245714 # ok 49 event_spurious.0.87
6817 11:36:27.248805 # ok 50 get_value.0.86
6818 11:36:27.251781 # ok 51 name.0.86
6819 11:36:27.251855 # ok 52 write_default.0.86
6820 11:36:27.258302 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6821 11:36:27.261306 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6822 11:36:27.268041 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6823 11:36:27.271934 # not ok 53 write_valid.0.86
6824 11:36:27.274927 # ok 54 write_invalid.0.86
6825 11:36:27.275015 # ok 55 event_missing.0.86
6826 11:36:27.278039 # ok 56 event_spurious.0.86
6827 11:36:27.281795 # ok 57 get_value.0.85
6828 11:36:27.284883 # ok 58 name.0.85
6829 11:36:27.284958 # ok 59 write_default.0.85
6830 11:36:27.291538 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6831 11:36:27.295263 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6832 11:36:27.301640 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6833 11:36:27.304535 # not ok 60 write_valid.0.85
6834 11:36:27.304633 # ok 61 write_invalid.0.85
6835 11:36:27.307999 # ok 62 event_missing.0.85
6836 11:36:27.311266 # ok 63 event_spurious.0.85
6837 11:36:27.314199 # ok 64 get_value.0.84
6838 11:36:27.314273 # ok 65 name.0.84
6839 11:36:27.318088 # ok 66 write_default.0.84
6840 11:36:27.320892 # ok 67 write_valid.0.84
6841 11:36:27.324495 # ok 68 write_invalid.0.84
6842 11:36:27.327430 # ok 69 event_missing.0.84
6843 11:36:27.327505 # ok 70 event_spurious.0.84
6844 11:36:27.330733 # ok 71 get_value.0.83
6845 11:36:27.334395 # ok 72 name.0.83
6846 11:36:27.334495 # ok 73 write_default.0.83
6847 11:36:27.337547 # ok 74 write_valid.0.83
6848 11:36:27.341026 # ok 75 write_invalid.0.83
6849 11:36:27.344166 # ok 76 event_missing.0.83
6850 11:36:27.347628 # ok 77 event_spurious.0.83
6851 11:36:27.347703 # ok 78 get_value.0.82
6852 11:36:27.350659 # ok 79 name.0.82
6853 11:36:27.353871 # # Headset Jack is not writeable
6854 11:36:27.357770 # ok 80 # SKIP write_default.0.82
6855 11:36:27.360792 # # Headset Jack is not writeable
6856 11:36:27.363873 # ok 81 # SKIP write_valid.0.82
6857 11:36:27.367355 # # Headset Jack is not writeable
6858 11:36:27.371425 # ok 82 # SKIP write_invalid.0.82
6859 11:36:27.374030 # ok 83 event_missing.0.82
6860 11:36:27.374104 # ok 84 event_spurious.0.82
6861 11:36:27.377717 # ok 85 get_value.0.81
6862 11:36:27.380876 # ok 86 name.0.81
6863 11:36:27.380951 # ok 87 write_default.0.81
6864 11:36:27.387961 # # No event generated for Wake-on-Voice Phase2 Switch
6865 11:36:27.394122 # # No event generated for Wake-on-Voice Phase2 Switch
6866 11:36:27.394195 # ok 88 write_valid.0.81
6867 11:36:27.400894 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6868 11:36:27.407359 # # No event generated for Wake-on-Voice Phase2 Switch
6869 11:36:27.410663 # not ok 89 write_invalid.0.81
6870 11:36:27.410737 # not ok 90 event_missing.0.81
6871 11:36:27.413974 # ok 91 event_spurious.0.81
6872 11:36:27.417090 # ok 92 get_value.0.80
6873 11:36:27.420873 # ok 93 name.0.80
6874 11:36:27.420962 # ok 94 write_default.0.80
6875 11:36:27.424179 # ok 95 write_valid.0.80
6876 11:36:27.427351 # ok 96 write_invalid.0.80
6877 11:36:27.430563 # ok 97 event_missing.0.80
6878 11:36:27.430655 # ok 98 event_spurious.0.80
6879 11:36:27.437729 # # Handset Volume.0 value -13 less than minimum 0
6880 11:36:27.437796 # not ok 99 get_value.0.79
6881 11:36:27.440500 # ok 100 name.0.79
6882 11:36:27.443810 # # snd_ctl_elem_write() failed: Invalid argument
6883 11:36:27.447366 # not ok 101 write_default.0.79
6884 11:36:27.453800 # # snd_ctl_elem_write() failed: Invalid argument
6885 11:36:27.453875 # not ok 102 write_valid.0.79
6886 11:36:27.460418 # # snd_ctl_elem_write() failed: Invalid argument
6887 11:36:27.463662 # not ok 103 write_invalid.0.79
6888 11:36:27.463736 # ok 104 event_missing.0.79
6889 11:36:27.466965 # ok 105 event_spurious.0.79
6890 11:36:27.473911 # # Lineout Volume.0 value -13 less than minimum 0
6891 11:36:27.477245 # # Lineout Volume.1 value -13 less than minimum 0
6892 11:36:27.480383 # not ok 106 get_value.0.78
6893 11:36:27.480457 # ok 107 name.0.78
6894 11:36:27.486734 # # snd_ctl_elem_write() failed: Invalid argument
6895 11:36:27.490553 # not ok 108 write_default.0.78
6896 11:36:27.493314 # # snd_ctl_elem_write() failed: Invalid argument
6897 11:36:27.497103 # not ok 109 write_valid.0.78
6898 11:36:27.499926 # # snd_ctl_elem_write() failed: Invalid argument
6899 11:36:27.503272 # not ok 110 write_invalid.0.78
6900 11:36:27.506754 # ok 111 event_missing.0.78
6901 11:36:27.509967 # ok 112 event_spurious.0.78
6902 11:36:27.513638 # # Headphone Volume.0 value -13 less than minimum 0
6903 11:36:27.519859 # # Headphone Volume.1 value -13 less than minimum 0
6904 11:36:27.519935 # not ok 113 get_value.0.77
6905 11:36:27.524007 # ok 114 name.0.77
6906 11:36:27.526560 # # snd_ctl_elem_write() failed: Invalid argument
6907 11:36:27.529776 # not ok 115 write_default.0.77
6908 11:36:27.536867 # # snd_ctl_elem_write() failed: Invalid argument
6909 11:36:27.539673 # not ok 116 write_valid.0.77
6910 11:36:27.542893 # # snd_ctl_elem_write() failed: Invalid argument
6911 11:36:27.546608 # not ok 117 write_invalid.0.77
6912 11:36:27.549675 # ok 118 event_missing.0.77
6913 11:36:27.549750 # ok 119 event_spurious.0.77
6914 11:36:27.553105 # ok 120 get_value.0.76
6915 11:36:27.559921 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6916 11:36:27.562949 # not ok 121 name.0.76
6917 11:36:27.566230 # ok 122 write_default.0.76
6918 11:36:27.566304 # ok 123 write_valid.0.76
6919 11:36:27.569250 # ok 124 write_invalid.0.76
6920 11:36:27.573015 # ok 125 event_missing.0.76
6921 11:36:27.576306 # ok 126 event_spurious.0.76
6922 11:36:27.576381 # ok 127 get_value.0.75
6923 11:36:27.583050 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6924 11:36:27.586516 # not ok 128 name.0.75
6925 11:36:27.589311 # ok 129 write_default.0.75
6926 11:36:27.592842 # ok 130 write_valid.0.75
6927 11:36:27.592917 # ok 131 write_invalid.0.75
6928 11:36:27.595943 # ok 132 event_missing.0.75
6929 11:36:27.599015 # ok 133 event_spurious.0.75
6930 11:36:27.602391 # ok 134 get_value.0.74
6931 11:36:27.609597 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6932 11:36:27.609673 # not ok 135 name.0.74
6933 11:36:27.612632 # ok 136 write_default.0.74
6934 11:36:27.616258 # ok 137 write_valid.0.74
6935 11:36:27.619083 # ok 138 write_invalid.0.74
6936 11:36:27.622545 # ok 139 event_missing.0.74
6937 11:36:27.622620 # ok 140 event_spurious.0.74
6938 11:36:27.625774 # ok 141 get_value.0.73
6939 11:36:27.632622 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6940 11:36:27.635478 # not ok 142 name.0.73
6941 11:36:27.639261 # ok 143 write_default.0.73
6942 11:36:27.639336 # ok 144 write_valid.0.73
6943 11:36:27.642811 # ok 145 write_invalid.0.73
6944 11:36:27.645991 # ok 146 event_missing.0.73
6945 11:36:27.649004 # ok 147 event_spurious.0.73
6946 11:36:27.649103 # ok 148 get_value.0.72
6947 11:36:27.655882 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6948 11:36:27.659418 # not ok 149 name.0.72
6949 11:36:27.662662 # ok 150 write_default.0.72
6950 11:36:27.662738 # ok 151 write_valid.0.72
6951 11:36:27.665975 # ok 152 write_invalid.0.72
6952 11:36:27.668947 # ok 153 event_missing.0.72
6953 11:36:27.672372 # ok 154 event_spurious.0.72
6954 11:36:27.675568 # ok 155 get_value.0.71
6955 11:36:27.682300 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6956 11:36:27.682376 # not ok 156 name.0.71
6957 11:36:27.685489 # ok 157 write_default.0.71
6958 11:36:27.688759 # ok 158 write_valid.0.71
6959 11:36:27.692132 # ok 159 write_invalid.0.71
6960 11:36:27.692235 # ok 160 event_missing.0.71
6961 11:36:27.695780 # ok 161 event_spurious.0.71
6962 11:36:27.698701 # ok 162 get_value.0.70
6963 11:36:27.705052 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6964 11:36:27.705149 # not ok 163 name.0.70
6965 11:36:27.709095 # ok 164 write_default.0.70
6966 11:36:27.711822 # ok 165 write_valid.0.70
6967 11:36:27.715266 # ok 166 write_invalid.0.70
6968 11:36:27.718649 # ok 167 event_missing.0.70
6969 11:36:27.718736 # ok 168 event_spurious.0.70
6970 11:36:27.721653 # ok 169 get_value.0.69
6971 11:36:27.729039 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6972 11:36:27.731864 # not ok 170 name.0.69
6973 11:36:27.731954 # ok 171 write_default.0.69
6974 11:36:27.734793 # ok 172 write_valid.0.69
6975 11:36:27.738266 # ok 173 write_invalid.0.69
6976 11:36:27.741330 # ok 174 event_missing.0.69
6977 11:36:27.744826 # ok 175 event_spurious.0.69
6978 11:36:27.744938 # ok 176 get_value.0.68
6979 11:36:27.751341 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6980 11:36:27.755001 # not ok 177 name.0.68
6981 11:36:27.758239 # ok 178 write_default.0.68
6982 11:36:27.758345 # ok 179 write_valid.0.68
6983 11:36:27.761148 # ok 180 write_invalid.0.68
6984 11:36:27.764374 # ok 181 event_missing.0.68
6985 11:36:27.767693 # ok 182 event_spurious.0.68
6986 11:36:27.767774 # ok 183 get_value.0.67
6987 11:36:27.774752 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6988 11:36:27.778495 # not ok 184 name.0.67
6989 11:36:27.781864 # ok 185 write_default.0.67
6990 11:36:27.781953 # ok 186 write_valid.0.67
6991 11:36:27.784526 # ok 187 write_invalid.0.67
6992 11:36:27.787749 # ok 188 event_missing.0.67
6993 11:36:27.791098 # ok 189 event_spurious.0.67
6994 11:36:27.791173 # ok 190 get_value.0.66
6995 11:36:27.797811 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6996 11:36:27.801447 # not ok 191 name.0.66
6997 11:36:27.804334 # ok 192 write_default.0.66
6998 11:36:27.808122 # ok 193 write_valid.0.66
6999 11:36:27.808197 # ok 194 write_invalid.0.66
7000 11:36:27.810929 # ok 195 event_missing.0.66
7001 11:36:27.814179 # ok 196 event_spurious.0.66
7002 11:36:27.817554 # ok 197 get_value.0.65
7003 11:36:27.821256 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
7004 11:36:27.824423 # not ok 198 name.0.65
7005 11:36:27.827266 # ok 199 write_default.0.65
7006 11:36:27.831226 # ok 200 write_valid.0.65
7007 11:36:27.831300 # ok 201 write_invalid.0.65
7008 11:36:27.834689 # ok 202 event_missing.0.65
7009 11:36:27.837699 # ok 203 event_spurious.0.65
7010 11:36:27.841184 # ok 204 get_value.0.64
7011 11:36:27.847246 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
7012 11:36:27.847323 # not ok 205 name.0.64
7013 11:36:27.850838 # ok 206 write_default.0.64
7014 11:36:27.853920 # ok 207 write_valid.0.64
7015 11:36:27.853995 # ok 208 write_invalid.0.64
7016 11:36:27.857263 # ok 209 event_missing.0.64
7017 11:36:27.860653 # ok 210 event_spurious.0.64
7018 11:36:27.864164 # ok 211 get_value.0.63
7019 11:36:27.870532 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
7020 11:36:27.870609 # not ok 212 name.0.63
7021 11:36:27.873951 # ok 213 write_default.0.63
7022 11:36:27.877073 # ok 214 write_valid.0.63
7023 11:36:27.877167 # ok 215 write_invalid.0.63
7024 11:36:27.880666 # ok 216 event_missing.0.63
7025 11:36:27.884383 # ok 217 event_spurious.0.63
7026 11:36:27.886874 # ok 218 get_value.0.62
7027 11:36:27.894085 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7028 11:36:27.894162 # not ok 219 name.0.62
7029 11:36:27.897281 # ok 220 write_default.0.62
7030 11:36:27.900169 # ok 221 write_valid.0.62
7031 11:36:27.900244 # ok 222 write_invalid.0.62
7032 11:36:27.903571 # ok 223 event_missing.0.62
7033 11:36:27.906686 # ok 224 event_spurious.0.62
7034 11:36:27.910223 # ok 225 get_value.0.61
7035 11:36:27.916981 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7036 11:36:27.917081 # not ok 226 name.0.61
7037 11:36:27.920013 # ok 227 write_default.0.61
7038 11:36:27.923488 # ok 228 write_valid.0.61
7039 11:36:27.923563 # ok 229 write_invalid.0.61
7040 11:36:27.926711 # ok 230 event_missing.0.61
7041 11:36:27.930223 # ok 231 event_spurious.0.61
7042 11:36:27.933372 # ok 232 get_value.0.60
7043 11:36:27.940349 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
7044 11:36:27.940425 # not ok 233 name.0.60
7045 11:36:27.943353 # ok 234 write_default.0.60
7046 11:36:27.946450 # ok 235 write_valid.0.60
7047 11:36:27.950031 # ok 236 write_invalid.0.60
7048 11:36:27.950106 # ok 237 event_missing.0.60
7049 11:36:27.953030 # ok 238 event_spurious.0.60
7050 11:36:27.956783 # ok 239 get_value.0.59
7051 11:36:27.963547 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
7052 11:36:27.963623 # not ok 240 name.0.59
7053 11:36:27.966568 # ok 241 write_default.0.59
7054 11:36:27.969905 # ok 242 write_valid.0.59
7055 11:36:27.972672 # ok 243 write_invalid.0.59
7056 11:36:27.976268 # ok 244 event_missing.0.59
7057 11:36:27.976343 # ok 245 event_spurious.0.59
7058 11:36:27.979424 # ok 246 get_value.0.58
7059 11:36:27.986697 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
7060 11:36:27.989836 # not ok 247 name.0.58
7061 11:36:27.989914 # ok 248 write_default.0.58
7062 11:36:27.993336 # ok 249 write_valid.0.58
7063 11:36:27.996241 # ok 250 write_invalid.0.58
7064 11:36:27.999435 # ok 251 event_missing.0.58
7065 11:36:28.003128 # ok 252 event_spurious.0.58
7066 11:36:28.003194 # ok 253 get_value.0.57
7067 11:36:28.009426 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
7068 11:36:28.012669 # not ok 254 name.0.57
7069 11:36:28.012737 # ok 255 write_default.0.57
7070 11:36:28.016320 # ok 256 write_valid.0.57
7071 11:36:28.019876 # ok 257 write_invalid.0.57
7072 11:36:28.023199 # ok 258 event_missing.0.57
7073 11:36:28.025803 # ok 259 event_spurious.0.57
7074 11:36:28.025866 # ok 260 get_value.0.56
7075 11:36:28.032767 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
7076 11:36:28.036203 # not ok 261 name.0.56
7077 11:36:28.039791 # ok 262 write_default.0.56
7078 11:36:28.039857 # ok 263 write_valid.0.56
7079 11:36:28.042477 # ok 264 write_invalid.0.56
7080 11:36:28.045736 # ok 265 event_missing.0.56
7081 11:36:28.049546 # ok 266 event_spurious.0.56
7082 11:36:28.049613 # ok 267 get_value.0.55
7083 11:36:28.056010 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
7084 11:36:28.059340 # not ok 268 name.0.55
7085 11:36:28.062264 # ok 269 write_default.0.55
7086 11:36:28.062333 # ok 270 write_valid.0.55
7087 11:36:28.065540 # ok 271 write_invalid.0.55
7088 11:36:28.069272 # ok 272 event_missing.0.55
7089 11:36:28.072128 # ok 273 event_spurious.0.55
7090 11:36:28.072192 # ok 274 get_value.0.54
7091 11:36:28.079104 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
7092 11:36:28.082990 # not ok 275 name.0.54
7093 11:36:28.085981 # ok 276 write_default.0.54
7094 11:36:28.086048 # ok 277 write_valid.0.54
7095 11:36:28.088694 # ok 278 write_invalid.0.54
7096 11:36:28.092041 # ok 279 event_missing.0.54
7097 11:36:28.096231 # ok 280 event_spurious.0.54
7098 11:36:28.096298 # ok 281 get_value.0.53
7099 11:36:28.101813 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
7100 11:36:28.105460 # not ok 282 name.0.53
7101 11:36:28.109153 # ok 283 write_default.0.53
7102 11:36:28.109215 # ok 284 write_valid.0.53
7103 11:36:28.112375 # ok 285 write_invalid.0.53
7104 11:36:28.115145 # ok 286 event_missing.0.53
7105 11:36:28.118720 # ok 287 event_spurious.0.53
7106 11:36:28.121925 # ok 288 get_value.0.52
7107 11:36:28.124930 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
7108 11:36:28.128285 # not ok 289 name.0.52
7109 11:36:28.131526 # ok 290 write_default.0.52
7110 11:36:28.135002 # ok 291 write_valid.0.52
7111 11:36:28.135081 # ok 292 write_invalid.0.52
7112 11:36:28.138533 # ok 293 event_missing.0.52
7113 11:36:28.141475 # ok 294 event_spurious.0.52
7114 11:36:28.145434 # ok 295 get_value.0.51
7115 11:36:28.148572 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
7116 11:36:28.151509 # not ok 296 name.0.51
7117 11:36:28.154814 # ok 297 write_default.0.51
7118 11:36:28.158483 # ok 298 write_valid.0.51
7119 11:36:28.158558 # ok 299 write_invalid.0.51
7120 11:36:28.161664 # ok 300 event_missing.0.51
7121 11:36:28.165323 # ok 301 event_spurious.0.51
7122 11:36:28.168758 # ok 302 get_value.0.50
7123 11:36:28.171710 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
7124 11:36:28.175267 # not ok 303 name.0.50
7125 11:36:28.178292 # ok 304 write_default.0.50
7126 11:36:28.181783 # ok 305 write_valid.0.50
7127 11:36:28.181858 # ok 306 write_invalid.0.50
7128 11:36:28.184932 # ok 307 event_missing.0.50
7129 11:36:28.188201 # ok 308 event_spurious.0.50
7130 11:36:28.191535 # ok 309 get_value.0.49
7131 11:36:28.194917 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
7132 11:36:28.198543 # not ok 310 name.0.49
7133 11:36:28.201622 # ok 311 write_default.0.49
7134 11:36:28.204988 # ok 312 write_valid.0.49
7135 11:36:28.205063 # ok 313 write_invalid.0.49
7136 11:36:28.208060 # ok 314 event_missing.0.49
7137 11:36:28.211564 # ok 315 event_spurious.0.49
7138 11:36:28.214621 # ok 316 get_value.0.48
7139 11:36:28.221069 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
7140 11:36:28.221152 # not ok 317 name.0.48
7141 11:36:28.224995 # ok 318 write_default.0.48
7142 11:36:28.228323 # ok 319 write_valid.0.48
7143 11:36:28.231028 # ok 320 write_invalid.0.48
7144 11:36:28.231118 # ok 321 event_missing.0.48
7145 11:36:28.234815 # ok 322 event_spurious.0.48
7146 11:36:28.237826 # ok 323 get_value.0.47
7147 11:36:28.244781 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
7148 11:36:28.244857 # not ok 324 name.0.47
7149 11:36:28.247841 # ok 325 write_default.0.47
7150 11:36:28.251305 # ok 326 write_valid.0.47
7151 11:36:28.254482 # ok 327 write_invalid.0.47
7152 11:36:28.254558 # ok 328 event_missing.0.47
7153 11:36:28.257596 # ok 329 event_spurious.0.47
7154 11:36:28.260790 # ok 330 get_value.0.46
7155 11:36:28.267706 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
7156 11:36:28.267781 # not ok 331 name.0.46
7157 11:36:28.271294 # ok 332 write_default.0.46
7158 11:36:28.274342 # ok 333 write_valid.0.46
7159 11:36:28.277986 # ok 334 write_invalid.0.46
7160 11:36:28.278062 # ok 335 event_missing.0.46
7161 11:36:28.280898 # ok 336 event_spurious.0.46
7162 11:36:28.284301 # ok 337 get_value.0.45
7163 11:36:28.290672 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
7164 11:36:28.290748 # not ok 338 name.0.45
7165 11:36:28.294501 # ok 339 write_default.0.45
7166 11:36:28.297559 # ok 340 write_valid.0.45
7167 11:36:28.300944 # ok 341 write_invalid.0.45
7168 11:36:28.301020 # ok 342 event_missing.0.45
7169 11:36:28.304481 # ok 343 event_spurious.0.45
7170 11:36:28.307862 # ok 344 get_value.0.44
7171 11:36:28.314544 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
7172 11:36:28.314620 # not ok 345 name.0.44
7173 11:36:28.317368 # ok 346 write_default.0.44
7174 11:36:28.320822 # ok 347 write_valid.0.44
7175 11:36:28.323999 # ok 348 write_invalid.0.44
7176 11:36:28.324075 # ok 349 event_missing.0.44
7177 11:36:28.327698 # ok 350 event_spurious.0.44
7178 11:36:28.330761 # ok 351 get_value.0.43
7179 11:36:28.337622 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
7180 11:36:28.337698 # not ok 352 name.0.43
7181 11:36:28.340600 # ok 353 write_default.0.43
7182 11:36:28.344244 # ok 354 write_valid.0.43
7183 11:36:28.347401 # ok 355 write_invalid.0.43
7184 11:36:28.350733 # ok 356 event_missing.0.43
7185 11:36:28.350808 # ok 357 event_spurious.0.43
7186 11:36:28.354019 # ok 358 get_value.0.42
7187 11:36:28.360499 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
7188 11:36:28.364240 # not ok 359 name.0.42
7189 11:36:28.364315 # ok 360 write_default.0.42
7190 11:36:28.367216 # ok 361 write_valid.0.42
7191 11:36:28.370612 # ok 362 write_invalid.0.42
7192 11:36:28.374229 # ok 363 event_missing.0.42
7193 11:36:28.374304 # ok 364 event_spurious.0.42
7194 11:36:28.377151 # ok 365 get_value.0.41
7195 11:36:28.383875 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
7196 11:36:28.387280 # not ok 366 name.0.41
7197 11:36:28.387354 # ok 367 write_default.0.41
7198 11:36:28.390075 # ok 368 write_valid.0.41
7199 11:36:28.393536 # ok 369 write_invalid.0.41
7200 11:36:28.396806 # ok 370 event_missing.0.41
7201 11:36:28.399916 # ok 371 event_spurious.0.41
7202 11:36:28.399990 # ok 372 get_value.0.40
7203 11:36:28.406731 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7204 11:36:28.410193 # not ok 373 name.0.40
7205 11:36:28.410268 # ok 374 write_default.0.40
7206 11:36:28.413674 # ok 375 write_valid.0.40
7207 11:36:28.416574 # ok 376 write_invalid.0.40
7208 11:36:28.420656 # ok 377 event_missing.0.40
7209 11:36:28.423912 # ok 378 event_spurious.0.40
7210 11:36:28.423985 # ok 379 get_value.0.39
7211 11:36:28.430391 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7212 11:36:28.433416 # not ok 380 name.0.39
7213 11:36:28.437015 # ok 381 write_default.0.39
7214 11:36:28.437090 # ok 382 write_valid.0.39
7215 11:36:28.440081 # ok 383 write_invalid.0.39
7216 11:36:28.443192 # ok 384 event_missing.0.39
7217 11:36:28.446642 # ok 385 event_spurious.0.39
7218 11:36:28.446716 # ok 386 get_value.0.38
7219 11:36:28.453302 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7220 11:36:28.456689 # not ok 387 name.0.38
7221 11:36:28.460420 # ok 388 write_default.0.38
7222 11:36:28.460494 # ok 389 write_valid.0.38
7223 11:36:28.463565 # ok 390 write_invalid.0.38
7224 11:36:28.466880 # ok 391 event_missing.0.38
7225 11:36:28.469978 # ok 392 event_spurious.0.38
7226 11:36:28.470052 # ok 393 get_value.0.37
7227 11:36:28.479751 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7228 11:36:28.479826 # not ok 394 name.0.37
7229 11:36:28.483304 # ok 395 write_default.0.37
7230 11:36:28.486965 # ok 396 write_valid.0.37
7231 11:36:28.487039 # ok 397 write_invalid.0.37
7232 11:36:28.489984 # ok 398 event_missing.0.37
7233 11:36:28.493713 # ok 399 event_spurious.0.37
7234 11:36:28.496621 # ok 400 get_value.0.36
7235 11:36:28.503347 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7236 11:36:28.503422 # not ok 401 name.0.36
7237 11:36:28.506804 # ok 402 write_default.0.36
7238 11:36:28.509556 # ok 403 write_valid.0.36
7239 11:36:28.513465 # ok 404 write_invalid.0.36
7240 11:36:28.513540 # ok 405 event_missing.0.36
7241 11:36:28.516602 # ok 406 event_spurious.0.36
7242 11:36:28.519889 # ok 407 get_value.0.35
7243 11:36:28.526353 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7244 11:36:28.529694 # not ok 408 name.0.35
7245 11:36:28.529768 # ok 409 write_default.0.35
7246 11:36:28.533092 # ok 410 write_valid.0.35
7247 11:36:28.536180 # ok 411 write_invalid.0.35
7248 11:36:28.539424 # ok 412 event_missing.0.35
7249 11:36:28.543092 # ok 413 event_spurious.0.35
7250 11:36:28.543166 # ok 414 get_value.0.34
7251 11:36:28.549518 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7252 11:36:28.552887 # not ok 415 name.0.34
7253 11:36:28.555796 # ok 416 write_default.0.34
7254 11:36:28.555899 # ok 417 write_valid.0.34
7255 11:36:28.559100 # ok 418 write_invalid.0.34
7256 11:36:28.562422 # ok 419 event_missing.0.34
7257 11:36:28.566229 # ok 420 event_spurious.0.34
7258 11:36:28.566302 # ok 421 get_value.0.33
7259 11:36:28.572552 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7260 11:36:28.575519 # not ok 422 name.0.33
7261 11:36:28.579302 # ok 423 write_default.0.33
7262 11:36:28.582544 # ok 424 write_valid.0.33
7263 11:36:28.582618 # ok 425 write_invalid.0.33
7264 11:36:28.586315 # ok 426 event_missing.0.33
7265 11:36:28.589262 # ok 427 event_spurious.0.33
7266 11:36:28.592835 # ok 428 get_value.0.32
7267 11:36:28.598756 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7268 11:36:28.598832 # not ok 429 name.0.32
7269 11:36:28.602026 # ok 430 write_default.0.32
7270 11:36:28.606227 # ok 431 write_valid.0.32
7271 11:36:28.609123 # ok 432 write_invalid.0.32
7272 11:36:28.609230 # ok 433 event_missing.0.32
7273 11:36:28.612529 # ok 434 event_spurious.0.32
7274 11:36:28.615439 # ok 435 get_value.0.31
7275 11:36:28.622454 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7276 11:36:28.622531 # not ok 436 name.0.31
7277 11:36:28.626172 # ok 437 write_default.0.31
7278 11:36:28.628768 # ok 438 write_valid.0.31
7279 11:36:28.632207 # ok 439 write_invalid.0.31
7280 11:36:28.635840 # ok 440 event_missing.0.31
7281 11:36:28.635915 # ok 441 event_spurious.0.31
7282 11:36:28.639401 # ok 442 get_value.0.30
7283 11:36:28.645374 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7284 11:36:28.649033 # not ok 443 name.0.30
7285 11:36:28.652099 # ok 444 write_default.0.30
7286 11:36:28.652174 # ok 445 write_valid.0.30
7287 11:36:28.655292 # ok 446 write_invalid.0.30
7288 11:36:28.658521 # ok 447 event_missing.0.30
7289 11:36:28.661799 # ok 448 event_spurious.0.30
7290 11:36:28.661875 # ok 449 get_value.0.29
7291 11:36:28.665519 # ok 450 name.0.29
7292 11:36:28.669008 # ok 451 write_default.0.29
7293 11:36:28.669083 # ok 452 write_valid.0.29
7294 11:36:28.671948 # ok 453 write_invalid.0.29
7295 11:36:28.675536 # ok 454 event_missing.0.29
7296 11:36:28.678607 # ok 455 event_spurious.0.29
7297 11:36:28.678681 # ok 456 get_value.0.28
7298 11:36:28.681975 # ok 457 name.0.28
7299 11:36:28.685007 # ok 458 write_default.0.28
7300 11:36:28.688549 # ok 459 write_valid.0.28
7301 11:36:28.688624 # ok 460 write_invalid.0.28
7302 11:36:28.691857 # ok 461 event_missing.0.28
7303 11:36:28.695157 # ok 462 event_spurious.0.28
7304 11:36:28.698598 # ok 463 get_value.0.27
7305 11:36:28.698673 # ok 464 name.0.27
7306 11:36:28.701663 # ok 465 write_default.0.27
7307 11:36:28.705162 # ok 466 write_valid.0.27
7308 11:36:28.705238 # ok 467 write_invalid.0.27
7309 11:36:28.708633 # ok 468 event_missing.0.27
7310 11:36:28.712004 # ok 469 event_spurious.0.27
7311 11:36:28.714764 # ok 470 get_value.0.26
7312 11:36:28.714839 # ok 471 name.0.26
7313 11:36:28.717938 # ok 472 write_default.0.26
7314 11:36:28.721385 # ok 473 write_valid.0.26
7315 11:36:28.724899 # ok 474 write_invalid.0.26
7316 11:36:28.724975 # ok 475 event_missing.0.26
7317 11:36:28.728323 # ok 476 event_spurious.0.26
7318 11:36:28.731420 # ok 477 get_value.0.25
7319 11:36:28.731496 # ok 478 name.0.25
7320 11:36:28.735044 # ok 479 write_default.0.25
7321 11:36:28.738192 # ok 480 write_valid.0.25
7322 11:36:28.741449 # ok 481 write_invalid.0.25
7323 11:36:28.741525 # ok 482 event_missing.0.25
7324 11:36:28.744548 # ok 483 event_spurious.0.25
7325 11:36:28.748493 # ok 484 get_value.0.24
7326 11:36:28.748569 # ok 485 name.0.24
7327 11:36:28.751709 # ok 486 write_default.0.24
7328 11:36:28.755054 # ok 487 write_valid.0.24
7329 11:36:28.758689 # ok 488 write_invalid.0.24
7330 11:36:28.761185 # ok 489 event_missing.0.24
7331 11:36:28.761260 # ok 490 event_spurious.0.24
7332 11:36:28.764570 # ok 491 get_value.0.23
7333 11:36:28.767902 # ok 492 name.0.23
7334 11:36:28.767978 # ok 493 write_default.0.23
7335 11:36:28.771462 # ok 494 write_valid.0.23
7336 11:36:28.774946 # ok 495 write_invalid.0.23
7337 11:36:28.777703 # ok 496 event_missing.0.23
7338 11:36:28.777778 # ok 497 event_spurious.0.23
7339 11:36:28.781460 # ok 498 get_value.0.22
7340 11:36:28.784683 # ok 499 name.0.22
7341 11:36:28.784770 # ok 500 write_default.0.22
7342 11:36:28.787763 # ok 501 write_valid.0.22
7343 11:36:28.790913 # ok 502 write_invalid.0.22
7344 11:36:28.794565 # ok 503 event_missing.0.22
7345 11:36:28.797567 # ok 504 event_spurious.0.22
7346 11:36:28.797642 # ok 505 get_value.0.21
7347 11:36:28.804578 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7348 11:36:28.807433 # not ok 506 name.0.21
7349 11:36:28.810776 # ok 507 write_default.0.21
7350 11:36:28.810850 # ok 508 write_valid.0.21
7351 11:36:28.814508 # ok 509 write_invalid.0.21
7352 11:36:28.817551 # ok 510 event_missing.0.21
7353 11:36:28.820830 # ok 511 event_spurious.0.21
7354 11:36:28.820904 # ok 512 get_value.0.20
7355 11:36:28.827572 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7356 11:36:28.830887 # not ok 513 name.0.20
7357 11:36:28.833826 # ok 514 write_default.0.20
7358 11:36:28.837405 # ok 515 write_valid.0.20
7359 11:36:28.837479 # ok 516 write_invalid.0.20
7360 11:36:28.840762 # ok 517 event_missing.0.20
7361 11:36:28.844273 # ok 518 event_spurious.0.20
7362 11:36:28.847471 # ok 519 get_value.0.19
7363 11:36:28.854182 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7364 11:36:28.854257 # not ok 520 name.0.19
7365 11:36:28.857129 # ok 521 write_default.0.19
7366 11:36:28.860932 # ok 522 write_valid.0.19
7367 11:36:28.861005 # ok 523 write_invalid.0.19
7368 11:36:28.863937 # ok 524 event_missing.0.19
7369 11:36:28.867230 # ok 525 event_spurious.0.19
7370 11:36:28.870633 # ok 526 get_value.0.18
7371 11:36:28.874003 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7372 11:36:28.876857 # not ok 527 name.0.18
7373 11:36:28.880158 # ok 528 write_default.0.18
7374 11:36:28.883906 # ok 529 write_valid.0.18
7375 11:36:28.883979 # ok 530 write_invalid.0.18
7376 11:36:28.887098 # ok 531 event_missing.0.18
7377 11:36:28.890303 # ok 532 event_spurious.0.18
7378 11:36:28.893380 # ok 533 get_value.0.17
7379 11:36:28.896921 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7380 11:36:28.899972 # not ok 534 name.0.17
7381 11:36:28.903734 # ok 535 write_default.0.17
7382 11:36:28.903809 # ok 536 write_valid.0.17
7383 11:36:28.907143 # ok 537 write_invalid.0.17
7384 11:36:28.910463 # ok 538 event_missing.0.17
7385 11:36:28.913252 # ok 539 event_spurious.0.17
7386 11:36:28.913328 # ok 540 get_value.0.16
7387 11:36:28.920164 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7388 11:36:28.923213 # not ok 541 name.0.16
7389 11:36:28.926879 # ok 542 write_default.0.16
7390 11:36:28.926963 # ok 543 write_valid.0.16
7391 11:36:28.929757 # ok 544 write_invalid.0.16
7392 11:36:28.933557 # ok 545 event_missing.0.16
7393 11:36:28.936418 # ok 546 event_spurious.0.16
7394 11:36:28.936506 # ok 547 get_value.0.15
7395 11:36:28.943609 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7396 11:36:28.946788 # not ok 548 name.0.15
7397 11:36:28.946864 # ok 549 write_default.0.15
7398 11:36:28.950445 # ok 550 write_valid.0.15
7399 11:36:28.953022 # ok 551 write_invalid.0.15
7400 11:36:28.956515 # ok 552 event_missing.0.15
7401 11:36:28.956591 # ok 553 event_spurious.0.15
7402 11:36:28.960022 # ok 554 get_value.0.14
7403 11:36:28.966536 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7404 11:36:28.970026 # not ok 555 name.0.14
7405 11:36:28.970132 # ok 556 write_default.0.14
7406 11:36:28.973238 # ok 557 write_valid.0.14
7407 11:36:28.976240 # ok 558 write_invalid.0.14
7408 11:36:28.979928 # ok 559 event_missing.0.14
7409 11:36:28.979995 # ok 560 event_spurious.0.14
7410 11:36:28.982563 # ok 561 get_value.0.13
7411 11:36:28.989778 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7412 11:36:28.989854 # not ok 562 name.0.13
7413 11:36:28.993285 # ok 563 write_default.0.13
7414 11:36:28.996096 # ok 564 write_valid.0.13
7415 11:36:28.999602 # ok 565 write_invalid.0.13
7416 11:36:28.999697 # ok 566 event_missing.0.13
7417 11:36:29.002580 # ok 567 event_spurious.0.13
7418 11:36:29.006135 # ok 568 get_value.0.12
7419 11:36:29.012733 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7420 11:36:29.012809 # not ok 569 name.0.12
7421 11:36:29.016119 # ok 570 write_default.0.12
7422 11:36:29.019850 # ok 571 write_valid.0.12
7423 11:36:29.022765 # ok 572 write_invalid.0.12
7424 11:36:29.022839 # ok 573 event_missing.0.12
7425 11:36:29.025832 # ok 574 event_spurious.0.12
7426 11:36:29.029410 # ok 575 get_value.0.11
7427 11:36:29.033057 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7428 11:36:29.036600 # not ok 576 name.0.11
7429 11:36:29.039259 # ok 577 write_default.0.11
7430 11:36:29.042534 # ok 578 write_valid.0.11
7431 11:36:29.042609 # ok 579 write_invalid.0.11
7432 11:36:29.046036 # ok 580 event_missing.0.11
7433 11:36:29.049442 # ok 581 event_spurious.0.11
7434 11:36:29.052756 # ok 582 get_value.0.10
7435 11:36:29.059389 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7436 11:36:29.059464 # not ok 583 name.0.10
7437 11:36:29.062343 # ok 584 write_default.0.10
7438 11:36:29.065754 # ok 585 write_valid.0.10
7439 11:36:29.065830 # ok 586 write_invalid.0.10
7440 11:36:29.069111 # ok 587 event_missing.0.10
7441 11:36:29.072373 # ok 588 event_spurious.0.10
7442 11:36:29.076350 # ok 589 get_value.0.9
7443 11:36:29.082240 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7444 11:36:29.082315 # not ok 590 name.0.9
7445 11:36:29.085899 # ok 591 write_default.0.9
7446 11:36:29.088959 # ok 592 write_valid.0.9
7447 11:36:29.089033 # ok 593 write_invalid.0.9
7448 11:36:29.092122 # ok 594 event_missing.0.9
7449 11:36:29.095725 # ok 595 event_spurious.0.9
7450 11:36:29.098768 # ok 596 get_value.0.8
7451 11:36:29.102089 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7452 11:36:29.105634 # not ok 597 name.0.8
7453 11:36:29.108788 # ok 598 write_default.0.8
7454 11:36:29.111875 # ok 599 write_valid.0.8
7455 11:36:29.111950 # ok 600 write_invalid.0.8
7456 11:36:29.115747 # ok 601 event_missing.0.8
7457 11:36:29.118762 # ok 602 event_spurious.0.8
7458 11:36:29.121887 # ok 603 get_value.0.7
7459 11:36:29.125552 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7460 11:36:29.128611 # not ok 604 name.0.7
7461 11:36:29.132411 # ok 605 write_default.0.7
7462 11:36:29.132486 # ok 606 write_valid.0.7
7463 11:36:29.135387 # ok 607 write_invalid.0.7
7464 11:36:29.138563 # ok 608 event_missing.0.7
7465 11:36:29.141725 # ok 609 event_spurious.0.7
7466 11:36:29.141800 # ok 610 get_value.0.6
7467 11:36:29.148613 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7468 11:36:29.151716 # not ok 611 name.0.6
7469 11:36:29.155292 # ok 612 write_default.0.6
7470 11:36:29.155367 # ok 613 write_valid.0.6
7471 11:36:29.158845 # ok 614 write_invalid.0.6
7472 11:36:29.162331 # ok 615 event_missing.0.6
7473 11:36:29.165495 # ok 616 event_spurious.0.6
7474 11:36:29.165570 # ok 617 get_value.0.5
7475 11:36:29.168512 # ok 618 name.0.5
7476 11:36:29.171700 # ok 619 write_default.0.5
7477 11:36:29.175492 # # No event generated for MTKAIF_DMIC
7478 11:36:29.179026 # # No event generated for MTKAIF_DMIC
7479 11:36:29.179101 # ok 620 write_valid.0.5
7480 11:36:29.181822 # ok 621 write_invalid.0.5
7481 11:36:29.184816 # not ok 622 event_missing.0.5
7482 11:36:29.188124 # ok 623 event_spurious.0.5
7483 11:36:29.191409 # ok 624 get_value.0.4
7484 11:36:29.191487 # ok 625 name.0.4
7485 11:36:29.194862 # ok 626 write_default.0.4
7486 11:36:29.198438 # # No event generated for I2S5_HD_Mux
7487 11:36:29.201456 # # No event generated for I2S5_HD_Mux
7488 11:36:29.205099 # ok 627 write_valid.0.4
7489 11:36:29.205214 # ok 628 write_invalid.0.4
7490 11:36:29.208207 # not ok 629 event_missing.0.4
7491 11:36:29.211446 # ok 630 event_spurious.0.4
7492 11:36:29.214606 # ok 631 get_value.0.3
7493 11:36:29.214701 # ok 632 name.0.3
7494 11:36:29.217890 # ok 633 write_default.0.3
7495 11:36:29.221679 # # No event generated for I2S3_HD_Mux
7496 11:36:29.224676 # # No event generated for I2S3_HD_Mux
7497 11:36:29.227997 # ok 634 write_valid.0.3
7498 11:36:29.228091 # ok 635 write_invalid.0.3
7499 11:36:29.231104 # not ok 636 event_missing.0.3
7500 11:36:29.234619 # ok 637 event_spurious.0.3
7501 11:36:29.238088 # ok 638 get_value.0.2
7502 11:36:29.238163 # ok 639 name.0.2
7503 11:36:29.241186 # ok 640 write_default.0.2
7504 11:36:29.244527 # # No event generated for I2S2_HD_Mux
7505 11:36:29.248117 # # No event generated for I2S2_HD_Mux
7506 11:36:29.251075 # ok 641 write_valid.0.2
7507 11:36:29.251174 # ok 642 write_invalid.0.2
7508 11:36:29.254578 # not ok 643 event_missing.0.2
7509 11:36:29.257461 # ok 644 event_spurious.0.2
7510 11:36:29.261726 # ok 645 get_value.0.1
7511 11:36:29.261816 # ok 646 name.0.1
7512 11:36:29.264250 # ok 647 write_default.0.1
7513 11:36:29.267485 # # No event generated for I2S1_HD_Mux
7514 11:36:29.271381 # # No event generated for I2S1_HD_Mux
7515 11:36:29.274643 # ok 648 write_valid.0.1
7516 11:36:29.274718 # ok 649 write_invalid.0.1
7517 11:36:29.277368 # not ok 650 event_missing.0.1
7518 11:36:29.280748 # ok 651 event_spurious.0.1
7519 11:36:29.284037 # ok 652 get_value.0.0
7520 11:36:29.284112 # ok 653 name.0.0
7521 11:36:29.287744 # ok 654 write_default.0.0
7522 11:36:29.290621 # # No event generated for I2S0_HD_Mux
7523 11:36:29.293862 # # No event generated for I2S0_HD_Mux
7524 11:36:29.297356 # ok 655 write_valid.0.0
7525 11:36:29.297431 # ok 656 write_invalid.0.0
7526 11:36:29.300546 # not ok 657 event_missing.0.0
7527 11:36:29.304003 # ok 658 event_spurious.0.0
7528 11:36:29.307642 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7529 11:36:29.310551 ok 1 selftests: alsa: mixer-test
7530 11:36:30.798272 alsa_mixer-test_get_value_0_93 pass
7531 11:36:30.801472 alsa_mixer-test_name_0_93 pass
7532 11:36:30.804789 alsa_mixer-test_write_default_0_93 pass
7533 11:36:30.808323 alsa_mixer-test_write_valid_0_93 pass
7534 11:36:30.811750 alsa_mixer-test_write_invalid_0_93 pass
7535 11:36:30.818485 alsa_mixer-test_event_missing_0_93 pass
7536 11:36:30.821101 alsa_mixer-test_event_spurious_0_93 pass
7537 11:36:30.824570 alsa_mixer-test_get_value_0_92 pass
7538 11:36:30.824643 alsa_mixer-test_name_0_92 pass
7539 11:36:30.831937 alsa_mixer-test_write_default_0_92 pass
7540 11:36:30.834511 alsa_mixer-test_write_valid_0_92 pass
7541 11:36:30.837967 alsa_mixer-test_write_invalid_0_92 pass
7542 11:36:30.840959 alsa_mixer-test_event_missing_0_92 pass
7543 11:36:30.844920 alsa_mixer-test_event_spurious_0_92 pass
7544 11:36:30.847789 alsa_mixer-test_get_value_0_91 pass
7545 11:36:30.851075 alsa_mixer-test_name_0_91 pass
7546 11:36:30.854558 alsa_mixer-test_write_default_0_91 pass
7547 11:36:30.858143 alsa_mixer-test_write_valid_0_91 pass
7548 11:36:30.860993 alsa_mixer-test_write_invalid_0_91 pass
7549 11:36:30.864222 alsa_mixer-test_event_missing_0_91 pass
7550 11:36:30.867367 alsa_mixer-test_event_spurious_0_91 pass
7551 11:36:30.870828 alsa_mixer-test_get_value_0_90 pass
7552 11:36:30.874357 alsa_mixer-test_name_0_90 pass
7553 11:36:30.877239 alsa_mixer-test_write_default_0_90 pass
7554 11:36:30.880944 alsa_mixer-test_write_valid_0_90 pass
7555 11:36:30.884310 alsa_mixer-test_write_invalid_0_90 pass
7556 11:36:30.887117 alsa_mixer-test_event_missing_0_90 pass
7557 11:36:30.890456 alsa_mixer-test_event_spurious_0_90 pass
7558 11:36:30.893973 alsa_mixer-test_get_value_0_89 pass
7559 11:36:30.897352 alsa_mixer-test_name_0_89 pass
7560 11:36:30.900606 alsa_mixer-test_write_default_0_89 pass
7561 11:36:30.907208 alsa_mixer-test_write_valid_0_89 pass
7562 11:36:30.910552 alsa_mixer-test_write_invalid_0_89 pass
7563 11:36:30.914168 alsa_mixer-test_event_missing_0_89 pass
7564 11:36:30.917351 alsa_mixer-test_event_spurious_0_89 pass
7565 11:36:30.920720 alsa_mixer-test_get_value_0_88 pass
7566 11:36:30.923932 alsa_mixer-test_name_0_88 pass
7567 11:36:30.927006 alsa_mixer-test_write_default_0_88 pass
7568 11:36:30.930487 alsa_mixer-test_write_valid_0_88 fail
7569 11:36:30.933841 alsa_mixer-test_write_invalid_0_88 pass
7570 11:36:30.936979 alsa_mixer-test_event_missing_0_88 pass
7571 11:36:30.940323 alsa_mixer-test_event_spurious_0_88 fail
7572 11:36:30.943855 alsa_mixer-test_get_value_0_87 pass
7573 11:36:30.946882 alsa_mixer-test_name_0_87 pass
7574 11:36:30.950421 alsa_mixer-test_write_default_0_87 pass
7575 11:36:30.953282 alsa_mixer-test_write_valid_0_87 pass
7576 11:36:30.957133 alsa_mixer-test_write_invalid_0_87 pass
7577 11:36:30.960204 alsa_mixer-test_event_missing_0_87 pass
7578 11:36:30.967526 alsa_mixer-test_event_spurious_0_87 pass
7579 11:36:30.970003 alsa_mixer-test_get_value_0_86 pass
7580 11:36:30.970080 alsa_mixer-test_name_0_86 pass
7581 11:36:30.976882 alsa_mixer-test_write_default_0_86 pass
7582 11:36:30.980236 alsa_mixer-test_write_valid_0_86 fail
7583 11:36:30.983218 alsa_mixer-test_write_invalid_0_86 pass
7584 11:36:30.987304 alsa_mixer-test_event_missing_0_86 pass
7585 11:36:30.989856 alsa_mixer-test_event_spurious_0_86 pass
7586 11:36:30.993244 alsa_mixer-test_get_value_0_85 pass
7587 11:36:30.996407 alsa_mixer-test_name_0_85 pass
7588 11:36:30.999932 alsa_mixer-test_write_default_0_85 pass
7589 11:36:31.003386 alsa_mixer-test_write_valid_0_85 fail
7590 11:36:31.006309 alsa_mixer-test_write_invalid_0_85 pass
7591 11:36:31.010434 alsa_mixer-test_event_missing_0_85 pass
7592 11:36:31.013421 alsa_mixer-test_event_spurious_0_85 pass
7593 11:36:31.016551 alsa_mixer-test_get_value_0_84 pass
7594 11:36:31.019916 alsa_mixer-test_name_0_84 pass
7595 11:36:31.023072 alsa_mixer-test_write_default_0_84 pass
7596 11:36:31.026683 alsa_mixer-test_write_valid_0_84 pass
7597 11:36:31.032803 alsa_mixer-test_write_invalid_0_84 pass
7598 11:36:31.036270 alsa_mixer-test_event_missing_0_84 pass
7599 11:36:31.039872 alsa_mixer-test_event_spurious_0_84 pass
7600 11:36:31.043099 alsa_mixer-test_get_value_0_83 pass
7601 11:36:31.046717 alsa_mixer-test_name_0_83 pass
7602 11:36:31.049480 alsa_mixer-test_write_default_0_83 pass
7603 11:36:31.053088 alsa_mixer-test_write_valid_0_83 pass
7604 11:36:31.056411 alsa_mixer-test_write_invalid_0_83 pass
7605 11:36:31.060052 alsa_mixer-test_event_missing_0_83 pass
7606 11:36:31.062684 alsa_mixer-test_event_spurious_0_83 pass
7607 11:36:31.066147 alsa_mixer-test_get_value_0_82 pass
7608 11:36:31.069493 alsa_mixer-test_name_0_82 pass
7609 11:36:31.072804 alsa_mixer-test_write_default_0_82 skip
7610 11:36:31.077092 alsa_mixer-test_write_valid_0_82 skip
7611 11:36:31.079866 alsa_mixer-test_write_invalid_0_82 skip
7612 11:36:31.083060 alsa_mixer-test_event_missing_0_82 pass
7613 11:36:31.085953 alsa_mixer-test_event_spurious_0_82 pass
7614 11:36:31.092939 alsa_mixer-test_get_value_0_81 pass
7615 11:36:31.093014 alsa_mixer-test_name_0_81 pass
7616 11:36:31.095751 alsa_mixer-test_write_default_0_81 pass
7617 11:36:31.102546 alsa_mixer-test_write_valid_0_81 pass
7618 11:36:31.106259 alsa_mixer-test_write_invalid_0_81 fail
7619 11:36:31.109400 alsa_mixer-test_event_missing_0_81 fail
7620 11:36:31.112738 alsa_mixer-test_event_spurious_0_81 pass
7621 11:36:31.115592 alsa_mixer-test_get_value_0_80 pass
7622 11:36:31.119684 alsa_mixer-test_name_0_80 pass
7623 11:36:31.122226 alsa_mixer-test_write_default_0_80 pass
7624 11:36:31.126048 alsa_mixer-test_write_valid_0_80 pass
7625 11:36:31.128867 alsa_mixer-test_write_invalid_0_80 pass
7626 11:36:31.132580 alsa_mixer-test_event_missing_0_80 pass
7627 11:36:31.135791 alsa_mixer-test_event_spurious_0_80 pass
7628 11:36:31.138919 alsa_mixer-test_get_value_0_79 fail
7629 11:36:31.142546 alsa_mixer-test_name_0_79 pass
7630 11:36:31.146195 alsa_mixer-test_write_default_0_79 fail
7631 11:36:31.149055 alsa_mixer-test_write_valid_0_79 fail
7632 11:36:31.152363 alsa_mixer-test_write_invalid_0_79 fail
7633 11:36:31.159390 alsa_mixer-test_event_missing_0_79 pass
7634 11:36:31.162043 alsa_mixer-test_event_spurious_0_79 pass
7635 11:36:31.165830 alsa_mixer-test_get_value_0_78 fail
7636 11:36:31.169239 alsa_mixer-test_name_0_78 pass
7637 11:36:31.172410 alsa_mixer-test_write_default_0_78 fail
7638 11:36:31.175643 alsa_mixer-test_write_valid_0_78 fail
7639 11:36:31.178628 alsa_mixer-test_write_invalid_0_78 fail
7640 11:36:31.182066 alsa_mixer-test_event_missing_0_78 pass
7641 11:36:31.185716 alsa_mixer-test_event_spurious_0_78 pass
7642 11:36:31.188711 alsa_mixer-test_get_value_0_77 fail
7643 11:36:31.191965 alsa_mixer-test_name_0_77 pass
7644 11:36:31.195737 alsa_mixer-test_write_default_0_77 fail
7645 11:36:31.199330 alsa_mixer-test_write_valid_0_77 fail
7646 11:36:31.201969 alsa_mixer-test_write_invalid_0_77 fail
7647 11:36:31.205555 alsa_mixer-test_event_missing_0_77 pass
7648 11:36:31.211796 alsa_mixer-test_event_spurious_0_77 pass
7649 11:36:31.216005 alsa_mixer-test_get_value_0_76 pass
7650 11:36:31.216079 alsa_mixer-test_name_0_76 fail
7651 11:36:31.218529 alsa_mixer-test_write_default_0_76 pass
7652 11:36:31.225299 alsa_mixer-test_write_valid_0_76 pass
7653 11:36:31.228352 alsa_mixer-test_write_invalid_0_76 pass
7654 11:36:31.231568 alsa_mixer-test_event_missing_0_76 pass
7655 11:36:31.235732 alsa_mixer-test_event_spurious_0_76 pass
7656 11:36:31.238708 alsa_mixer-test_get_value_0_75 pass
7657 11:36:31.241636 alsa_mixer-test_name_0_75 fail
7658 11:36:31.245420 alsa_mixer-test_write_default_0_75 pass
7659 11:36:31.248542 alsa_mixer-test_write_valid_0_75 pass
7660 11:36:31.251799 alsa_mixer-test_write_invalid_0_75 pass
7661 11:36:31.255396 alsa_mixer-test_event_missing_0_75 pass
7662 11:36:31.258698 alsa_mixer-test_event_spurious_0_75 pass
7663 11:36:31.261769 alsa_mixer-test_get_value_0_74 pass
7664 11:36:31.264742 alsa_mixer-test_name_0_74 fail
7665 11:36:31.268390 alsa_mixer-test_write_default_0_74 pass
7666 11:36:31.271727 alsa_mixer-test_write_valid_0_74 pass
7667 11:36:31.278332 alsa_mixer-test_write_invalid_0_74 pass
7668 11:36:31.281346 alsa_mixer-test_event_missing_0_74 pass
7669 11:36:31.284745 alsa_mixer-test_event_spurious_0_74 pass
7670 11:36:31.288255 alsa_mixer-test_get_value_0_73 pass
7671 11:36:31.291562 alsa_mixer-test_name_0_73 fail
7672 11:36:31.294963 alsa_mixer-test_write_default_0_73 pass
7673 11:36:31.298282 alsa_mixer-test_write_valid_0_73 pass
7674 11:36:31.301698 alsa_mixer-test_write_invalid_0_73 pass
7675 11:36:31.304832 alsa_mixer-test_event_missing_0_73 pass
7676 11:36:31.308291 alsa_mixer-test_event_spurious_0_73 pass
7677 11:36:31.311977 alsa_mixer-test_get_value_0_72 pass
7678 11:36:31.314909 alsa_mixer-test_name_0_72 fail
7679 11:36:31.318005 alsa_mixer-test_write_default_0_72 pass
7680 11:36:31.321110 alsa_mixer-test_write_valid_0_72 pass
7681 11:36:31.324818 alsa_mixer-test_write_invalid_0_72 pass
7682 11:36:31.328401 alsa_mixer-test_event_missing_0_72 pass
7683 11:36:31.335169 alsa_mixer-test_event_spurious_0_72 pass
7684 11:36:31.337768 alsa_mixer-test_get_value_0_71 pass
7685 11:36:31.337844 alsa_mixer-test_name_0_71 fail
7686 11:36:31.344806 alsa_mixer-test_write_default_0_71 pass
7687 11:36:31.348195 alsa_mixer-test_write_valid_0_71 pass
7688 11:36:31.350993 alsa_mixer-test_write_invalid_0_71 pass
7689 11:36:31.354835 alsa_mixer-test_event_missing_0_71 pass
7690 11:36:31.357556 alsa_mixer-test_event_spurious_0_71 pass
7691 11:36:31.361379 alsa_mixer-test_get_value_0_70 pass
7692 11:36:31.364328 alsa_mixer-test_name_0_70 fail
7693 11:36:31.367498 alsa_mixer-test_write_default_0_70 pass
7694 11:36:31.371300 alsa_mixer-test_write_valid_0_70 pass
7695 11:36:31.374026 alsa_mixer-test_write_invalid_0_70 pass
7696 11:36:31.378092 alsa_mixer-test_event_missing_0_70 pass
7697 11:36:31.381523 alsa_mixer-test_event_spurious_0_70 pass
7698 11:36:31.384362 alsa_mixer-test_get_value_0_69 pass
7699 11:36:31.387432 alsa_mixer-test_name_0_69 fail
7700 11:36:31.390789 alsa_mixer-test_write_default_0_69 pass
7701 11:36:31.393960 alsa_mixer-test_write_valid_0_69 pass
7702 11:36:31.400770 alsa_mixer-test_write_invalid_0_69 pass
7703 11:36:31.404462 alsa_mixer-test_event_missing_0_69 pass
7704 11:36:31.407741 alsa_mixer-test_event_spurious_0_69 pass
7705 11:36:31.410696 alsa_mixer-test_get_value_0_68 pass
7706 11:36:31.414209 alsa_mixer-test_name_0_68 fail
7707 11:36:31.417717 alsa_mixer-test_write_default_0_68 pass
7708 11:36:31.420666 alsa_mixer-test_write_valid_0_68 pass
7709 11:36:31.424586 alsa_mixer-test_write_invalid_0_68 pass
7710 11:36:31.427474 alsa_mixer-test_event_missing_0_68 pass
7711 11:36:31.430564 alsa_mixer-test_event_spurious_0_68 pass
7712 11:36:31.433962 alsa_mixer-test_get_value_0_67 pass
7713 11:36:31.436874 alsa_mixer-test_name_0_67 fail
7714 11:36:31.440701 alsa_mixer-test_write_default_0_67 pass
7715 11:36:31.444001 alsa_mixer-test_write_valid_0_67 pass
7716 11:36:31.447115 alsa_mixer-test_write_invalid_0_67 pass
7717 11:36:31.453586 alsa_mixer-test_event_missing_0_67 pass
7718 11:36:31.456764 alsa_mixer-test_event_spurious_0_67 pass
7719 11:36:31.460321 alsa_mixer-test_get_value_0_66 pass
7720 11:36:31.463357 alsa_mixer-test_name_0_66 fail
7721 11:36:31.466705 alsa_mixer-test_write_default_0_66 pass
7722 11:36:31.470216 alsa_mixer-test_write_valid_0_66 pass
7723 11:36:31.473798 alsa_mixer-test_write_invalid_0_66 pass
7724 11:36:31.476756 alsa_mixer-test_event_missing_0_66 pass
7725 11:36:31.480229 alsa_mixer-test_event_spurious_0_66 pass
7726 11:36:31.483606 alsa_mixer-test_get_value_0_65 pass
7727 11:36:31.486575 alsa_mixer-test_name_0_65 fail
7728 11:36:31.490270 alsa_mixer-test_write_default_0_65 pass
7729 11:36:31.493444 alsa_mixer-test_write_valid_0_65 pass
7730 11:36:31.497122 alsa_mixer-test_write_invalid_0_65 pass
7731 11:36:31.500217 alsa_mixer-test_event_missing_0_65 pass
7732 11:36:31.503184 alsa_mixer-test_event_spurious_0_65 pass
7733 11:36:31.506663 alsa_mixer-test_get_value_0_64 pass
7734 11:36:31.509966 alsa_mixer-test_name_0_64 fail
7735 11:36:31.512979 alsa_mixer-test_write_default_0_64 pass
7736 11:36:31.516792 alsa_mixer-test_write_valid_0_64 pass
7737 11:36:31.523224 alsa_mixer-test_write_invalid_0_64 pass
7738 11:36:31.526340 alsa_mixer-test_event_missing_0_64 pass
7739 11:36:31.529487 alsa_mixer-test_event_spurious_0_64 pass
7740 11:36:31.532947 alsa_mixer-test_get_value_0_63 pass
7741 11:36:31.536171 alsa_mixer-test_name_0_63 fail
7742 11:36:31.539723 alsa_mixer-test_write_default_0_63 pass
7743 11:36:31.543082 alsa_mixer-test_write_valid_0_63 pass
7744 11:36:31.546174 alsa_mixer-test_write_invalid_0_63 pass
7745 11:36:31.549358 alsa_mixer-test_event_missing_0_63 pass
7746 11:36:31.552722 alsa_mixer-test_event_spurious_0_63 pass
7747 11:36:31.556136 alsa_mixer-test_get_value_0_62 pass
7748 11:36:31.559478 alsa_mixer-test_name_0_62 fail
7749 11:36:31.562547 alsa_mixer-test_write_default_0_62 pass
7750 11:36:31.566250 alsa_mixer-test_write_valid_0_62 pass
7751 11:36:31.569127 alsa_mixer-test_write_invalid_0_62 pass
7752 11:36:31.572951 alsa_mixer-test_event_missing_0_62 pass
7753 11:36:31.579289 alsa_mixer-test_event_spurious_0_62 pass
7754 11:36:31.582493 alsa_mixer-test_get_value_0_61 pass
7755 11:36:31.582568 alsa_mixer-test_name_0_61 fail
7756 11:36:31.585886 alsa_mixer-test_write_default_0_61 pass
7757 11:36:31.592594 alsa_mixer-test_write_valid_0_61 pass
7758 11:36:31.596772 alsa_mixer-test_write_invalid_0_61 pass
7759 11:36:31.599017 alsa_mixer-test_event_missing_0_61 pass
7760 11:36:31.602261 alsa_mixer-test_event_spurious_0_61 pass
7761 11:36:31.605891 alsa_mixer-test_get_value_0_60 pass
7762 11:36:31.608823 alsa_mixer-test_name_0_60 fail
7763 11:36:31.612137 alsa_mixer-test_write_default_0_60 pass
7764 11:36:31.615707 alsa_mixer-test_write_valid_0_60 pass
7765 11:36:31.622293 alsa_mixer-test_write_invalid_0_60 pass
7766 11:36:31.625567 alsa_mixer-test_event_missing_0_60 pass
7767 11:36:31.628818 alsa_mixer-test_event_spurious_0_60 pass
7768 11:36:31.632105 alsa_mixer-test_get_value_0_59 pass
7769 11:36:31.635998 alsa_mixer-test_name_0_59 fail
7770 11:36:31.639039 alsa_mixer-test_write_default_0_59 pass
7771 11:36:31.642191 alsa_mixer-test_write_valid_0_59 pass
7772 11:36:31.645526 alsa_mixer-test_write_invalid_0_59 pass
7773 11:36:31.652394 alsa_mixer-test_event_missing_0_59 pass
7774 11:36:31.655355 alsa_mixer-test_event_spurious_0_59 pass
7775 11:36:31.658675 alsa_mixer-test_get_value_0_58 pass
7776 11:36:31.661841 alsa_mixer-test_name_0_58 fail
7777 11:36:31.665244 alsa_mixer-test_write_default_0_58 pass
7778 11:36:31.668900 alsa_mixer-test_write_valid_0_58 pass
7779 11:36:31.672112 alsa_mixer-test_write_invalid_0_58 pass
7780 11:36:31.675038 alsa_mixer-test_event_missing_0_58 pass
7781 11:36:31.681673 alsa_mixer-test_event_spurious_0_58 pass
7782 11:36:31.685007 alsa_mixer-test_get_value_0_57 pass
7783 11:36:31.688157 alsa_mixer-test_name_0_57 fail
7784 11:36:31.692143 alsa_mixer-test_write_default_0_57 pass
7785 11:36:31.695234 alsa_mixer-test_write_valid_0_57 pass
7786 11:36:31.698712 alsa_mixer-test_write_invalid_0_57 pass
7787 11:36:31.701845 alsa_mixer-test_event_missing_0_57 pass
7788 11:36:31.704997 alsa_mixer-test_event_spurious_0_57 pass
7789 11:36:31.711547 alsa_mixer-test_get_value_0_56 pass
7790 11:36:31.711623 alsa_mixer-test_name_0_56 fail
7791 11:36:31.718032 alsa_mixer-test_write_default_0_56 pass
7792 11:36:31.721994 alsa_mixer-test_write_valid_0_56 pass
7793 11:36:31.725375 alsa_mixer-test_write_invalid_0_56 pass
7794 11:36:31.728471 alsa_mixer-test_event_missing_0_56 pass
7795 11:36:31.731550 alsa_mixer-test_event_spurious_0_56 pass
7796 11:36:31.735383 alsa_mixer-test_get_value_0_55 pass
7797 11:36:31.738140 alsa_mixer-test_name_0_55 fail
7798 11:36:31.741907 alsa_mixer-test_write_default_0_55 pass
7799 11:36:31.748647 alsa_mixer-test_write_valid_0_55 pass
7800 11:36:31.751895 alsa_mixer-test_write_invalid_0_55 pass
7801 11:36:31.754843 alsa_mixer-test_event_missing_0_55 pass
7802 11:36:31.758286 alsa_mixer-test_event_spurious_0_55 pass
7803 11:36:31.761781 alsa_mixer-test_get_value_0_54 pass
7804 11:36:31.765073 alsa_mixer-test_name_0_54 fail
7805 11:36:31.768315 alsa_mixer-test_write_default_0_54 pass
7806 11:36:31.771536 alsa_mixer-test_write_valid_0_54 pass
7807 11:36:31.778240 alsa_mixer-test_write_invalid_0_54 pass
7808 11:36:31.781817 alsa_mixer-test_event_missing_0_54 pass
7809 11:36:31.785039 alsa_mixer-test_event_spurious_0_54 pass
7810 11:36:31.788726 alsa_mixer-test_get_value_0_53 pass
7811 11:36:31.791663 alsa_mixer-test_name_0_53 fail
7812 11:36:31.794987 alsa_mixer-test_write_default_0_53 pass
7813 11:36:31.798192 alsa_mixer-test_write_valid_0_53 pass
7814 11:36:31.801886 alsa_mixer-test_write_invalid_0_53 pass
7815 11:36:31.804968 alsa_mixer-test_event_missing_0_53 pass
7816 11:36:31.811662 alsa_mixer-test_event_spurious_0_53 pass
7817 11:36:31.815317 alsa_mixer-test_get_value_0_52 pass
7818 11:36:31.818323 alsa_mixer-test_name_0_52 fail
7819 11:36:31.821992 alsa_mixer-test_write_default_0_52 pass
7820 11:36:31.824877 alsa_mixer-test_write_valid_0_52 pass
7821 11:36:31.829199 alsa_mixer-test_write_invalid_0_52 pass
7822 11:36:31.831940 alsa_mixer-test_event_missing_0_52 pass
7823 11:36:31.835074 alsa_mixer-test_event_spurious_0_52 pass
7824 11:36:31.838084 alsa_mixer-test_get_value_0_51 pass
7825 11:36:31.841613 alsa_mixer-test_name_0_51 fail
7826 11:36:31.845259 alsa_mixer-test_write_default_0_51 pass
7827 11:36:31.848807 alsa_mixer-test_write_valid_0_51 pass
7828 11:36:31.854699 alsa_mixer-test_write_invalid_0_51 pass
7829 11:36:31.858486 alsa_mixer-test_event_missing_0_51 pass
7830 11:36:31.861634 alsa_mixer-test_event_spurious_0_51 pass
7831 11:36:31.865035 alsa_mixer-test_get_value_0_50 pass
7832 11:36:31.868213 alsa_mixer-test_name_0_50 fail
7833 11:36:31.872103 alsa_mixer-test_write_default_0_50 pass
7834 11:36:31.875489 alsa_mixer-test_write_valid_0_50 pass
7835 11:36:31.878218 alsa_mixer-test_write_invalid_0_50 pass
7836 11:36:31.881314 alsa_mixer-test_event_missing_0_50 pass
7837 11:36:31.884660 alsa_mixer-test_event_spurious_0_50 pass
7838 11:36:31.888369 alsa_mixer-test_get_value_0_49 pass
7839 11:36:31.891579 alsa_mixer-test_name_0_49 fail
7840 11:36:31.894735 alsa_mixer-test_write_default_0_49 pass
7841 11:36:31.898330 alsa_mixer-test_write_valid_0_49 pass
7842 11:36:31.901561 alsa_mixer-test_write_invalid_0_49 pass
7843 11:36:31.905026 alsa_mixer-test_event_missing_0_49 pass
7844 11:36:31.911842 alsa_mixer-test_event_spurious_0_49 pass
7845 11:36:31.911933 alsa_mixer-test_get_value_0_48 pass
7846 11:36:31.914946 alsa_mixer-test_name_0_48 fail
7847 11:36:31.918302 alsa_mixer-test_write_default_0_48 pass
7848 11:36:31.921508 alsa_mixer-test_write_valid_0_48 pass
7849 11:36:31.924736 alsa_mixer-test_write_invalid_0_48 pass
7850 11:36:31.931354 alsa_mixer-test_event_missing_0_48 pass
7851 11:36:31.934404 alsa_mixer-test_event_spurious_0_48 pass
7852 11:36:31.937771 alsa_mixer-test_get_value_0_47 pass
7853 11:36:31.937846 alsa_mixer-test_name_0_47 fail
7854 11:36:31.945535 alsa_mixer-test_write_default_0_47 pass
7855 11:36:31.948042 alsa_mixer-test_write_valid_0_47 pass
7856 11:36:31.951728 alsa_mixer-test_write_invalid_0_47 pass
7857 11:36:31.954442 alsa_mixer-test_event_missing_0_47 pass
7858 11:36:31.957668 alsa_mixer-test_event_spurious_0_47 pass
7859 11:36:31.961703 alsa_mixer-test_get_value_0_46 pass
7860 11:36:31.964806 alsa_mixer-test_name_0_46 fail
7861 11:36:31.968126 alsa_mixer-test_write_default_0_46 pass
7862 11:36:31.971496 alsa_mixer-test_write_valid_0_46 pass
7863 11:36:31.974454 alsa_mixer-test_write_invalid_0_46 pass
7864 11:36:31.977834 alsa_mixer-test_event_missing_0_46 pass
7865 11:36:31.981668 alsa_mixer-test_event_spurious_0_46 pass
7866 11:36:31.984725 alsa_mixer-test_get_value_0_45 pass
7867 11:36:31.987520 alsa_mixer-test_name_0_45 fail
7868 11:36:31.990796 alsa_mixer-test_write_default_0_45 pass
7869 11:36:31.993891 alsa_mixer-test_write_valid_0_45 pass
7870 11:36:31.997626 alsa_mixer-test_write_invalid_0_45 pass
7871 11:36:32.000995 alsa_mixer-test_event_missing_0_45 pass
7872 11:36:32.004092 alsa_mixer-test_event_spurious_0_45 pass
7873 11:36:32.007688 alsa_mixer-test_get_value_0_44 pass
7874 11:36:32.010596 alsa_mixer-test_name_0_44 fail
7875 11:36:32.014246 alsa_mixer-test_write_default_0_44 pass
7876 11:36:32.017707 alsa_mixer-test_write_valid_0_44 pass
7877 11:36:32.020719 alsa_mixer-test_write_invalid_0_44 pass
7878 11:36:32.024036 alsa_mixer-test_event_missing_0_44 pass
7879 11:36:32.027554 alsa_mixer-test_event_spurious_0_44 pass
7880 11:36:32.030674 alsa_mixer-test_get_value_0_43 pass
7881 11:36:32.033890 alsa_mixer-test_name_0_43 fail
7882 11:36:32.037150 alsa_mixer-test_write_default_0_43 pass
7883 11:36:32.040336 alsa_mixer-test_write_valid_0_43 pass
7884 11:36:32.043822 alsa_mixer-test_write_invalid_0_43 pass
7885 11:36:32.047017 alsa_mixer-test_event_missing_0_43 pass
7886 11:36:32.050198 alsa_mixer-test_event_spurious_0_43 pass
7887 11:36:32.053905 alsa_mixer-test_get_value_0_42 pass
7888 11:36:32.057830 alsa_mixer-test_name_0_42 fail
7889 11:36:32.060295 alsa_mixer-test_write_default_0_42 pass
7890 11:36:32.063820 alsa_mixer-test_write_valid_0_42 pass
7891 11:36:32.067574 alsa_mixer-test_write_invalid_0_42 pass
7892 11:36:32.073763 alsa_mixer-test_event_missing_0_42 pass
7893 11:36:32.076713 alsa_mixer-test_event_spurious_0_42 pass
7894 11:36:32.080181 alsa_mixer-test_get_value_0_41 pass
7895 11:36:32.080258 alsa_mixer-test_name_0_41 fail
7896 11:36:32.087291 alsa_mixer-test_write_default_0_41 pass
7897 11:36:32.090325 alsa_mixer-test_write_valid_0_41 pass
7898 11:36:32.093252 alsa_mixer-test_write_invalid_0_41 pass
7899 11:36:32.096890 alsa_mixer-test_event_missing_0_41 pass
7900 11:36:32.100033 alsa_mixer-test_event_spurious_0_41 pass
7901 11:36:32.103609 alsa_mixer-test_get_value_0_40 pass
7902 11:36:32.107038 alsa_mixer-test_name_0_40 fail
7903 11:36:32.109875 alsa_mixer-test_write_default_0_40 pass
7904 11:36:32.112984 alsa_mixer-test_write_valid_0_40 pass
7905 11:36:32.116848 alsa_mixer-test_write_invalid_0_40 pass
7906 11:36:32.119840 alsa_mixer-test_event_missing_0_40 pass
7907 11:36:32.123434 alsa_mixer-test_event_spurious_0_40 pass
7908 11:36:32.126306 alsa_mixer-test_get_value_0_39 pass
7909 11:36:32.129601 alsa_mixer-test_name_0_39 fail
7910 11:36:32.132980 alsa_mixer-test_write_default_0_39 pass
7911 11:36:32.136359 alsa_mixer-test_write_valid_0_39 pass
7912 11:36:32.139607 alsa_mixer-test_write_invalid_0_39 pass
7913 11:36:32.142876 alsa_mixer-test_event_missing_0_39 pass
7914 11:36:32.149907 alsa_mixer-test_event_spurious_0_39 pass
7915 11:36:32.152928 alsa_mixer-test_get_value_0_38 pass
7916 11:36:32.153004 alsa_mixer-test_name_0_38 fail
7917 11:36:32.159717 alsa_mixer-test_write_default_0_38 pass
7918 11:36:32.163038 alsa_mixer-test_write_valid_0_38 pass
7919 11:36:32.166850 alsa_mixer-test_write_invalid_0_38 pass
7920 11:36:32.169535 alsa_mixer-test_event_missing_0_38 pass
7921 11:36:32.173126 alsa_mixer-test_event_spurious_0_38 pass
7922 11:36:32.176269 alsa_mixer-test_get_value_0_37 pass
7923 11:36:32.179299 alsa_mixer-test_name_0_37 fail
7924 11:36:32.182406 alsa_mixer-test_write_default_0_37 pass
7925 11:36:32.185991 alsa_mixer-test_write_valid_0_37 pass
7926 11:36:32.189413 alsa_mixer-test_write_invalid_0_37 pass
7927 11:36:32.192521 alsa_mixer-test_event_missing_0_37 pass
7928 11:36:32.196209 alsa_mixer-test_event_spurious_0_37 pass
7929 11:36:32.199205 alsa_mixer-test_get_value_0_36 pass
7930 11:36:32.202512 alsa_mixer-test_name_0_36 fail
7931 11:36:32.205811 alsa_mixer-test_write_default_0_36 pass
7932 11:36:32.212619 alsa_mixer-test_write_valid_0_36 pass
7933 11:36:32.216066 alsa_mixer-test_write_invalid_0_36 pass
7934 11:36:32.219220 alsa_mixer-test_event_missing_0_36 pass
7935 11:36:32.222497 alsa_mixer-test_event_spurious_0_36 pass
7936 11:36:32.225531 alsa_mixer-test_get_value_0_35 pass
7937 11:36:32.229004 alsa_mixer-test_name_0_35 fail
7938 11:36:32.232388 alsa_mixer-test_write_default_0_35 pass
7939 11:36:32.236287 alsa_mixer-test_write_valid_0_35 pass
7940 11:36:32.238715 alsa_mixer-test_write_invalid_0_35 pass
7941 11:36:32.242911 alsa_mixer-test_event_missing_0_35 pass
7942 11:36:32.246016 alsa_mixer-test_event_spurious_0_35 pass
7943 11:36:32.249231 alsa_mixer-test_get_value_0_34 pass
7944 11:36:32.252286 alsa_mixer-test_name_0_34 fail
7945 11:36:32.255910 alsa_mixer-test_write_default_0_34 pass
7946 11:36:32.259127 alsa_mixer-test_write_valid_0_34 pass
7947 11:36:32.262119 alsa_mixer-test_write_invalid_0_34 pass
7948 11:36:32.268699 alsa_mixer-test_event_missing_0_34 pass
7949 11:36:32.272043 alsa_mixer-test_event_spurious_0_34 pass
7950 11:36:32.275424 alsa_mixer-test_get_value_0_33 pass
7951 11:36:32.279228 alsa_mixer-test_name_0_33 fail
7952 11:36:32.282421 alsa_mixer-test_write_default_0_33 pass
7953 11:36:32.285315 alsa_mixer-test_write_valid_0_33 pass
7954 11:36:32.288753 alsa_mixer-test_write_invalid_0_33 pass
7955 11:36:32.292093 alsa_mixer-test_event_missing_0_33 pass
7956 11:36:32.295564 alsa_mixer-test_event_spurious_0_33 pass
7957 11:36:32.298892 alsa_mixer-test_get_value_0_32 pass
7958 11:36:32.301966 alsa_mixer-test_name_0_32 fail
7959 11:36:32.305138 alsa_mixer-test_write_default_0_32 pass
7960 11:36:32.308814 alsa_mixer-test_write_valid_0_32 pass
7961 11:36:32.311853 alsa_mixer-test_write_invalid_0_32 pass
7962 11:36:32.315057 alsa_mixer-test_event_missing_0_32 pass
7963 11:36:32.318415 alsa_mixer-test_event_spurious_0_32 pass
7964 11:36:32.322718 alsa_mixer-test_get_value_0_31 pass
7965 11:36:32.325056 alsa_mixer-test_name_0_31 fail
7966 11:36:32.328812 alsa_mixer-test_write_default_0_31 pass
7967 11:36:32.331916 alsa_mixer-test_write_valid_0_31 pass
7968 11:36:32.338536 alsa_mixer-test_write_invalid_0_31 pass
7969 11:36:32.342149 alsa_mixer-test_event_missing_0_31 pass
7970 11:36:32.345698 alsa_mixer-test_event_spurious_0_31 pass
7971 11:36:32.348978 alsa_mixer-test_get_value_0_30 pass
7972 11:36:32.352734 alsa_mixer-test_name_0_30 fail
7973 11:36:32.355541 alsa_mixer-test_write_default_0_30 pass
7974 11:36:32.358501 alsa_mixer-test_write_valid_0_30 pass
7975 11:36:32.362300 alsa_mixer-test_write_invalid_0_30 pass
7976 11:36:32.365013 alsa_mixer-test_event_missing_0_30 pass
7977 11:36:32.368675 alsa_mixer-test_event_spurious_0_30 pass
7978 11:36:32.372221 alsa_mixer-test_get_value_0_29 pass
7979 11:36:32.375000 alsa_mixer-test_name_0_29 pass
7980 11:36:32.378936 alsa_mixer-test_write_default_0_29 pass
7981 11:36:32.382131 alsa_mixer-test_write_valid_0_29 pass
7982 11:36:32.384812 alsa_mixer-test_write_invalid_0_29 pass
7983 11:36:32.391416 alsa_mixer-test_event_missing_0_29 pass
7984 11:36:32.394809 alsa_mixer-test_event_spurious_0_29 pass
7985 11:36:32.398084 alsa_mixer-test_get_value_0_28 pass
7986 11:36:32.401925 alsa_mixer-test_name_0_28 pass
7987 11:36:32.404744 alsa_mixer-test_write_default_0_28 pass
7988 11:36:32.408668 alsa_mixer-test_write_valid_0_28 pass
7989 11:36:32.412076 alsa_mixer-test_write_invalid_0_28 pass
7990 11:36:32.415124 alsa_mixer-test_event_missing_0_28 pass
7991 11:36:32.418506 alsa_mixer-test_event_spurious_0_28 pass
7992 11:36:32.421798 alsa_mixer-test_get_value_0_27 pass
7993 11:36:32.425077 alsa_mixer-test_name_0_27 pass
7994 11:36:32.428241 alsa_mixer-test_write_default_0_27 pass
7995 11:36:32.431905 alsa_mixer-test_write_valid_0_27 pass
7996 11:36:32.435034 alsa_mixer-test_write_invalid_0_27 pass
7997 11:36:32.438482 alsa_mixer-test_event_missing_0_27 pass
7998 11:36:32.441523 alsa_mixer-test_event_spurious_0_27 pass
7999 11:36:32.445075 alsa_mixer-test_get_value_0_26 pass
8000 11:36:32.448026 alsa_mixer-test_name_0_26 pass
8001 11:36:32.451671 alsa_mixer-test_write_default_0_26 pass
8002 11:36:32.455239 alsa_mixer-test_write_valid_0_26 pass
8003 11:36:32.458250 alsa_mixer-test_write_invalid_0_26 pass
8004 11:36:32.462003 alsa_mixer-test_event_missing_0_26 pass
8005 11:36:32.464624 alsa_mixer-test_event_spurious_0_26 pass
8006 11:36:32.467895 alsa_mixer-test_get_value_0_25 pass
8007 11:36:32.471695 alsa_mixer-test_name_0_25 pass
8008 11:36:32.474517 alsa_mixer-test_write_default_0_25 pass
8009 11:36:32.478577 alsa_mixer-test_write_valid_0_25 pass
8010 11:36:32.481439 alsa_mixer-test_write_invalid_0_25 pass
8011 11:36:32.484635 alsa_mixer-test_event_missing_0_25 pass
8012 11:36:32.488397 alsa_mixer-test_event_spurious_0_25 pass
8013 11:36:32.491217 alsa_mixer-test_get_value_0_24 pass
8014 11:36:32.494986 alsa_mixer-test_name_0_24 pass
8015 11:36:32.498014 alsa_mixer-test_write_default_0_24 pass
8016 11:36:32.505389 alsa_mixer-test_write_valid_0_24 pass
8017 11:36:32.507753 alsa_mixer-test_write_invalid_0_24 pass
8018 11:36:32.511421 alsa_mixer-test_event_missing_0_24 pass
8019 11:36:32.514611 alsa_mixer-test_event_spurious_0_24 pass
8020 11:36:32.517772 alsa_mixer-test_get_value_0_23 pass
8021 11:36:32.521112 alsa_mixer-test_name_0_23 pass
8022 11:36:32.524319 alsa_mixer-test_write_default_0_23 pass
8023 11:36:32.527665 alsa_mixer-test_write_valid_0_23 pass
8024 11:36:32.531243 alsa_mixer-test_write_invalid_0_23 pass
8025 11:36:32.534055 alsa_mixer-test_event_missing_0_23 pass
8026 11:36:32.537810 alsa_mixer-test_event_spurious_0_23 pass
8027 11:36:32.541619 alsa_mixer-test_get_value_0_22 pass
8028 11:36:32.544511 alsa_mixer-test_name_0_22 pass
8029 11:36:32.547590 alsa_mixer-test_write_default_0_22 pass
8030 11:36:32.550695 alsa_mixer-test_write_valid_0_22 pass
8031 11:36:32.554467 alsa_mixer-test_write_invalid_0_22 pass
8032 11:36:32.560618 alsa_mixer-test_event_missing_0_22 pass
8033 11:36:32.563857 alsa_mixer-test_event_spurious_0_22 pass
8034 11:36:32.567493 alsa_mixer-test_get_value_0_21 pass
8035 11:36:32.570640 alsa_mixer-test_name_0_21 fail
8036 11:36:32.574187 alsa_mixer-test_write_default_0_21 pass
8037 11:36:32.577739 alsa_mixer-test_write_valid_0_21 pass
8038 11:36:32.580475 alsa_mixer-test_write_invalid_0_21 pass
8039 11:36:32.584119 alsa_mixer-test_event_missing_0_21 pass
8040 11:36:32.587286 alsa_mixer-test_event_spurious_0_21 pass
8041 11:36:32.590790 alsa_mixer-test_get_value_0_20 pass
8042 11:36:32.593753 alsa_mixer-test_name_0_20 fail
8043 11:36:32.597602 alsa_mixer-test_write_default_0_20 pass
8044 11:36:32.600682 alsa_mixer-test_write_valid_0_20 pass
8045 11:36:32.603581 alsa_mixer-test_write_invalid_0_20 pass
8046 11:36:32.607391 alsa_mixer-test_event_missing_0_20 pass
8047 11:36:32.611017 alsa_mixer-test_event_spurious_0_20 pass
8048 11:36:32.613945 alsa_mixer-test_get_value_0_19 pass
8049 11:36:32.617167 alsa_mixer-test_name_0_19 fail
8050 11:36:32.620250 alsa_mixer-test_write_default_0_19 pass
8051 11:36:32.623456 alsa_mixer-test_write_valid_0_19 pass
8052 11:36:32.627073 alsa_mixer-test_write_invalid_0_19 pass
8053 11:36:32.630101 alsa_mixer-test_event_missing_0_19 pass
8054 11:36:32.633404 alsa_mixer-test_event_spurious_0_19 pass
8055 11:36:32.637159 alsa_mixer-test_get_value_0_18 pass
8056 11:36:32.640282 alsa_mixer-test_name_0_18 fail
8057 11:36:32.643103 alsa_mixer-test_write_default_0_18 pass
8058 11:36:32.646478 alsa_mixer-test_write_valid_0_18 pass
8059 11:36:32.650178 alsa_mixer-test_write_invalid_0_18 pass
8060 11:36:32.653122 alsa_mixer-test_event_missing_0_18 pass
8061 11:36:32.660126 alsa_mixer-test_event_spurious_0_18 pass
8062 11:36:32.663115 alsa_mixer-test_get_value_0_17 pass
8063 11:36:32.663191 alsa_mixer-test_name_0_17 fail
8064 11:36:32.666250 alsa_mixer-test_write_default_0_17 pass
8065 11:36:32.669731 alsa_mixer-test_write_valid_0_17 pass
8066 11:36:32.676488 alsa_mixer-test_write_invalid_0_17 pass
8067 11:36:32.679634 alsa_mixer-test_event_missing_0_17 pass
8068 11:36:32.682965 alsa_mixer-test_event_spurious_0_17 pass
8069 11:36:32.686181 alsa_mixer-test_get_value_0_16 pass
8070 11:36:32.689470 alsa_mixer-test_name_0_16 fail
8071 11:36:32.692928 alsa_mixer-test_write_default_0_16 pass
8072 11:36:32.696387 alsa_mixer-test_write_valid_0_16 pass
8073 11:36:32.699284 alsa_mixer-test_write_invalid_0_16 pass
8074 11:36:32.703174 alsa_mixer-test_event_missing_0_16 pass
8075 11:36:32.706131 alsa_mixer-test_event_spurious_0_16 pass
8076 11:36:32.709199 alsa_mixer-test_get_value_0_15 pass
8077 11:36:32.712429 alsa_mixer-test_name_0_15 fail
8078 11:36:32.716080 alsa_mixer-test_write_default_0_15 pass
8079 11:36:32.719212 alsa_mixer-test_write_valid_0_15 pass
8080 11:36:32.722491 alsa_mixer-test_write_invalid_0_15 pass
8081 11:36:32.726188 alsa_mixer-test_event_missing_0_15 pass
8082 11:36:32.729055 alsa_mixer-test_event_spurious_0_15 pass
8083 11:36:32.732498 alsa_mixer-test_get_value_0_14 pass
8084 11:36:32.736369 alsa_mixer-test_name_0_14 fail
8085 11:36:32.739177 alsa_mixer-test_write_default_0_14 pass
8086 11:36:32.742750 alsa_mixer-test_write_valid_0_14 pass
8087 11:36:32.745940 alsa_mixer-test_write_invalid_0_14 pass
8088 11:36:32.749322 alsa_mixer-test_event_missing_0_14 pass
8089 11:36:32.752473 alsa_mixer-test_event_spurious_0_14 pass
8090 11:36:32.755341 alsa_mixer-test_get_value_0_13 pass
8091 11:36:32.759514 alsa_mixer-test_name_0_13 fail
8092 11:36:32.762334 alsa_mixer-test_write_default_0_13 pass
8093 11:36:32.765451 alsa_mixer-test_write_valid_0_13 pass
8094 11:36:32.768560 alsa_mixer-test_write_invalid_0_13 pass
8095 11:36:32.771813 alsa_mixer-test_event_missing_0_13 pass
8096 11:36:32.775443 alsa_mixer-test_event_spurious_0_13 pass
8097 11:36:32.778688 alsa_mixer-test_get_value_0_12 pass
8098 11:36:32.782674 alsa_mixer-test_name_0_12 fail
8099 11:36:32.785430 alsa_mixer-test_write_default_0_12 pass
8100 11:36:32.788404 alsa_mixer-test_write_valid_0_12 pass
8101 11:36:32.792144 alsa_mixer-test_write_invalid_0_12 pass
8102 11:36:32.795467 alsa_mixer-test_event_missing_0_12 pass
8103 11:36:32.802093 alsa_mixer-test_event_spurious_0_12 pass
8104 11:36:32.805142 alsa_mixer-test_get_value_0_11 pass
8105 11:36:32.805218 alsa_mixer-test_name_0_11 fail
8106 11:36:32.808294 alsa_mixer-test_write_default_0_11 pass
8107 11:36:32.811866 alsa_mixer-test_write_valid_0_11 pass
8108 11:36:32.818402 alsa_mixer-test_write_invalid_0_11 pass
8109 11:36:32.822042 alsa_mixer-test_event_missing_0_11 pass
8110 11:36:32.825434 alsa_mixer-test_event_spurious_0_11 pass
8111 11:36:32.828133 alsa_mixer-test_get_value_0_10 pass
8112 11:36:32.831702 alsa_mixer-test_name_0_10 fail
8113 11:36:32.835058 alsa_mixer-test_write_default_0_10 pass
8114 11:36:32.838263 alsa_mixer-test_write_valid_0_10 pass
8115 11:36:32.841385 alsa_mixer-test_write_invalid_0_10 pass
8116 11:36:32.844530 alsa_mixer-test_event_missing_0_10 pass
8117 11:36:32.848009 alsa_mixer-test_event_spurious_0_10 pass
8118 11:36:32.851549 alsa_mixer-test_get_value_0_9 pass
8119 11:36:32.855355 alsa_mixer-test_name_0_9 fail
8120 11:36:32.858465 alsa_mixer-test_write_default_0_9 pass
8121 11:36:32.861331 alsa_mixer-test_write_valid_0_9 pass
8122 11:36:32.864746 alsa_mixer-test_write_invalid_0_9 pass
8123 11:36:32.867851 alsa_mixer-test_event_missing_0_9 pass
8124 11:36:32.870964 alsa_mixer-test_event_spurious_0_9 pass
8125 11:36:32.874346 alsa_mixer-test_get_value_0_8 pass
8126 11:36:32.877874 alsa_mixer-test_name_0_8 fail
8127 11:36:32.880885 alsa_mixer-test_write_default_0_8 pass
8128 11:36:32.884097 alsa_mixer-test_write_valid_0_8 pass
8129 11:36:32.887782 alsa_mixer-test_write_invalid_0_8 pass
8130 11:36:32.890920 alsa_mixer-test_event_missing_0_8 pass
8131 11:36:32.894761 alsa_mixer-test_event_spurious_0_8 pass
8132 11:36:32.897449 alsa_mixer-test_get_value_0_7 pass
8133 11:36:32.900829 alsa_mixer-test_name_0_7 fail
8134 11:36:32.904171 alsa_mixer-test_write_default_0_7 pass
8135 11:36:32.907724 alsa_mixer-test_write_valid_0_7 pass
8136 11:36:32.910757 alsa_mixer-test_write_invalid_0_7 pass
8137 11:36:32.913928 alsa_mixer-test_event_missing_0_7 pass
8138 11:36:32.917452 alsa_mixer-test_event_spurious_0_7 pass
8139 11:36:32.921146 alsa_mixer-test_get_value_0_6 pass
8140 11:36:32.924514 alsa_mixer-test_name_0_6 fail
8141 11:36:32.927463 alsa_mixer-test_write_default_0_6 pass
8142 11:36:32.931294 alsa_mixer-test_write_valid_0_6 pass
8143 11:36:32.933960 alsa_mixer-test_write_invalid_0_6 pass
8144 11:36:32.937242 alsa_mixer-test_event_missing_0_6 pass
8145 11:36:32.940542 alsa_mixer-test_event_spurious_0_6 pass
8146 11:36:32.943957 alsa_mixer-test_get_value_0_5 pass
8147 11:36:32.946964 alsa_mixer-test_name_0_5 pass
8148 11:36:32.950384 alsa_mixer-test_write_default_0_5 pass
8149 11:36:32.953488 alsa_mixer-test_write_valid_0_5 pass
8150 11:36:32.956941 alsa_mixer-test_write_invalid_0_5 pass
8151 11:36:32.960560 alsa_mixer-test_event_missing_0_5 fail
8152 11:36:32.964143 alsa_mixer-test_event_spurious_0_5 pass
8153 11:36:32.967316 alsa_mixer-test_get_value_0_4 pass
8154 11:36:32.970497 alsa_mixer-test_name_0_4 pass
8155 11:36:32.974172 alsa_mixer-test_write_default_0_4 pass
8156 11:36:32.977028 alsa_mixer-test_write_valid_0_4 pass
8157 11:36:32.980106 alsa_mixer-test_write_invalid_0_4 pass
8158 11:36:32.983715 alsa_mixer-test_event_missing_0_4 fail
8159 11:36:32.986986 alsa_mixer-test_event_spurious_0_4 pass
8160 11:36:32.990148 alsa_mixer-test_get_value_0_3 pass
8161 11:36:32.993619 alsa_mixer-test_name_0_3 pass
8162 11:36:32.996912 alsa_mixer-test_write_default_0_3 pass
8163 11:36:33.000269 alsa_mixer-test_write_valid_0_3 pass
8164 11:36:33.003375 alsa_mixer-test_write_invalid_0_3 pass
8165 11:36:33.006891 alsa_mixer-test_event_missing_0_3 fail
8166 11:36:33.010304 alsa_mixer-test_event_spurious_0_3 pass
8167 11:36:33.013418 alsa_mixer-test_get_value_0_2 pass
8168 11:36:33.016428 alsa_mixer-test_name_0_2 pass
8169 11:36:33.019811 alsa_mixer-test_write_default_0_2 pass
8170 11:36:33.023467 alsa_mixer-test_write_valid_0_2 pass
8171 11:36:33.026493 alsa_mixer-test_write_invalid_0_2 pass
8172 11:36:33.029615 alsa_mixer-test_event_missing_0_2 fail
8173 11:36:33.033244 alsa_mixer-test_event_spurious_0_2 pass
8174 11:36:33.036209 alsa_mixer-test_get_value_0_1 pass
8175 11:36:33.040011 alsa_mixer-test_name_0_1 pass
8176 11:36:33.043263 alsa_mixer-test_write_default_0_1 pass
8177 11:36:33.046471 alsa_mixer-test_write_valid_0_1 pass
8178 11:36:33.049810 alsa_mixer-test_write_invalid_0_1 pass
8179 11:36:33.052887 alsa_mixer-test_event_missing_0_1 fail
8180 11:36:33.056369 alsa_mixer-test_event_spurious_0_1 pass
8181 11:36:33.059750 alsa_mixer-test_get_value_0_0 pass
8182 11:36:33.063333 alsa_mixer-test_name_0_0 pass
8183 11:36:33.066050 alsa_mixer-test_write_default_0_0 pass
8184 11:36:33.070184 alsa_mixer-test_write_valid_0_0 pass
8185 11:36:33.072679 alsa_mixer-test_write_invalid_0_0 pass
8186 11:36:33.075859 alsa_mixer-test_event_missing_0_0 fail
8187 11:36:33.079602 alsa_mixer-test_event_spurious_0_0 pass
8188 11:36:33.079682 alsa_mixer-test pass
8189 11:36:33.086124 + ../../utils/send-to-lava.sh ./output/result.txt
8190 11:36:33.089171 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
8192 11:36:33.092806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
8193 11:36:33.099244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
8194 11:36:33.099487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
8196 11:36:33.105878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
8197 11:36:33.106145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
8199 11:36:33.112484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
8200 11:36:33.112734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8202 11:36:33.118634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8203 11:36:33.118877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8205 11:36:33.132084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8206 11:36:33.132327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8208 11:36:33.174606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8209 11:36:33.174853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8211 11:36:33.218291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8212 11:36:33.218541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8214 11:36:33.257471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8215 11:36:33.257720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8217 11:36:33.295182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8218 11:36:33.295429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8220 11:36:33.338749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8221 11:36:33.338998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8223 11:36:33.377531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8224 11:36:33.377781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8226 11:36:33.413869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8227 11:36:33.414153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8229 11:36:33.452715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8230 11:36:33.452965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8232 11:36:33.493471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8233 11:36:33.493729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8235 11:36:33.535928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8236 11:36:33.536216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8238 11:36:33.570569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8239 11:36:33.570863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8241 11:36:33.613629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8242 11:36:33.613900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8244 11:36:33.654371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8245 11:36:33.654644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8247 11:36:33.697915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8248 11:36:33.698164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8250 11:36:33.741725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8251 11:36:33.742002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8253 11:36:33.779214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8254 11:36:33.779487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8256 11:36:33.820863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8257 11:36:33.821152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8259 11:36:33.853739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8260 11:36:33.853984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8262 11:36:33.896547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8263 11:36:33.896791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8265 11:36:33.943755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8266 11:36:33.944031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8268 11:36:33.986946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8269 11:36:33.987214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8271 11:36:34.030854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8272 11:36:34.031104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8274 11:36:34.077064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8275 11:36:34.077366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8277 11:36:34.116602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8278 11:36:34.116853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8280 11:36:34.154937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8281 11:36:34.155184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8283 11:36:34.197440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8284 11:36:34.197689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8286 11:36:34.238934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8287 11:36:34.239186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8289 11:36:34.282725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8290 11:36:34.283007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8292 11:36:34.322817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8293 11:36:34.323070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8295 11:36:34.360778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8296 11:36:34.361029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8298 11:36:34.399939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8299 11:36:34.400185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8301 11:36:34.441025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8302 11:36:34.441292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8304 11:36:34.488979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8305 11:36:34.489227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8307 11:36:34.528218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8308 11:36:34.528464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8310 11:36:34.567966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8311 11:36:34.568213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8313 11:36:34.605617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8314 11:36:34.605867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8316 11:36:34.649519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8317 11:36:34.649769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8319 11:36:34.687600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8320 11:36:34.687878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8322 11:36:34.722190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8323 11:36:34.722443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8325 11:36:34.763793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8326 11:36:34.764041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8328 11:36:34.800460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8329 11:36:34.800759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8331 11:36:34.843412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8332 11:36:34.843684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8334 11:36:34.881046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8335 11:36:34.881354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8337 11:36:34.924434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8338 11:36:34.924711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8340 11:36:34.963331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8341 11:36:34.963586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8343 11:36:34.999615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8344 11:36:34.999900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8346 11:36:35.043977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8347 11:36:35.044259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8349 11:36:35.083107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8350 11:36:35.083360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8352 11:36:35.125043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8353 11:36:35.125344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8355 11:36:35.165682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8356 11:36:35.165944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8358 11:36:35.212305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8359 11:36:35.212555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8361 11:36:35.253054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8362 11:36:35.253321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8364 11:36:35.287879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8365 11:36:35.288124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8367 11:36:35.329947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8368 11:36:35.330225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8370 11:36:35.373135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8371 11:36:35.373405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8373 11:36:35.412297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8374 11:36:35.412566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8376 11:36:35.455513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8377 11:36:35.455767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8379 11:36:35.499309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8380 11:36:35.499593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8382 11:36:35.538641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8383 11:36:35.538917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8385 11:36:35.575045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8386 11:36:35.575300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8388 11:36:35.620393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8389 11:36:35.620646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8391 11:36:35.656481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8392 11:36:35.656726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8394 11:36:35.669519 <6>[ 37.990997] vaux18: disabling
8395 11:36:35.672565 <6>[ 37.994448] vio28: disabling
8396 11:36:35.696116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8397 11:36:35.696359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8399 11:36:35.733282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8400 11:36:35.733530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8402 11:36:35.775014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8403 11:36:35.775286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8405 11:36:35.815522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8406 11:36:35.815773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8408 11:36:35.852798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8409 11:36:35.853081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8411 11:36:35.897034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8412 11:36:35.897298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8414 11:36:35.938917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8415 11:36:35.939166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8417 11:36:35.977312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8418 11:36:35.977562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8420 11:36:36.017861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8421 11:36:36.018109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8423 11:36:36.058454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8424 11:36:36.058707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8426 11:36:36.101437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8427 11:36:36.101689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8429 11:36:36.139921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8430 11:36:36.140168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8432 11:36:36.186965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8433 11:36:36.187214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8435 11:36:36.224303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8436 11:36:36.224549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8438 11:36:36.263605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8439 11:36:36.263849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8441 11:36:36.309807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8442 11:36:36.310054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8444 11:36:36.351001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8445 11:36:36.351251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8447 11:36:36.390485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8448 11:36:36.390732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8450 11:36:36.427276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8451 11:36:36.427525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8453 11:36:36.470469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8454 11:36:36.470714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8456 11:36:36.514169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8457 11:36:36.514415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8459 11:36:36.555849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8460 11:36:36.556096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8462 11:36:36.596312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8463 11:36:36.596559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8465 11:36:36.638943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8466 11:36:36.639190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8468 11:36:36.679899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8469 11:36:36.680147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8471 11:36:36.719505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8472 11:36:36.719751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8474 11:36:36.764468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8475 11:36:36.764716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8477 11:36:36.808094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8478 11:36:36.808341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8480 11:36:36.853492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8481 11:36:36.853738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8483 11:36:36.895715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8484 11:36:36.895981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8486 11:36:36.933938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8487 11:36:36.934217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8489 11:36:36.974767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8490 11:36:36.975061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8492 11:36:37.010881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8493 11:36:37.011135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8495 11:36:37.061902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8496 11:36:37.062168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8498 11:36:37.105102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8499 11:36:37.105407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8501 11:36:37.152495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8502 11:36:37.153259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8504 11:36:37.201828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8505 11:36:37.202477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8507 11:36:37.251560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8508 11:36:37.252196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8510 11:36:37.302272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8511 11:36:37.302906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8513 11:36:37.345312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8514 11:36:37.345936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8516 11:36:37.399945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8517 11:36:37.400587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8519 11:36:37.447483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8520 11:36:37.448108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8522 11:36:37.498224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8523 11:36:37.498852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8525 11:36:37.544945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8526 11:36:37.545643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8528 11:36:37.593687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8529 11:36:37.594314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8531 11:36:37.642289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8532 11:36:37.642930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8534 11:36:37.684277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8535 11:36:37.685010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8537 11:36:37.738021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8538 11:36:37.738651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8540 11:36:37.784710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8541 11:36:37.785360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8543 11:36:37.836254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8544 11:36:37.836935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8546 11:36:37.884196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8547 11:36:37.884817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8549 11:36:37.930840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8550 11:36:37.931465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8552 11:36:37.977943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8553 11:36:37.978581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8555 11:36:38.024214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8556 11:36:38.024916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8558 11:36:38.077901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8559 11:36:38.078528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8561 11:36:38.127440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8562 11:36:38.128156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8564 11:36:38.180371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8565 11:36:38.181241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8567 11:36:38.231490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8568 11:36:38.232172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8570 11:36:38.290165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8571 11:36:38.290948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8573 11:36:38.344272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8574 11:36:38.344905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8576 11:36:38.387652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8577 11:36:38.387905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8579 11:36:38.430158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8580 11:36:38.430410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8582 11:36:38.473603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8583 11:36:38.473847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8585 11:36:38.517607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8586 11:36:38.517855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8588 11:36:38.563882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8589 11:36:38.564133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8591 11:36:38.611906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8592 11:36:38.612194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8594 11:36:38.654397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8595 11:36:38.654646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8597 11:36:38.687769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8598 11:36:38.688013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8600 11:36:38.732230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8601 11:36:38.732499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8603 11:36:38.777196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8604 11:36:38.777470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8606 11:36:38.814689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8607 11:36:38.814942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8609 11:36:38.854009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8610 11:36:38.854258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8612 11:36:38.894901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8613 11:36:38.895147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8615 11:36:38.934829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8616 11:36:38.935081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8618 11:36:38.969400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8619 11:36:38.969649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8621 11:36:39.008993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8622 11:36:39.009269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8624 11:36:39.047427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8625 11:36:39.047707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8627 11:36:39.086761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8628 11:36:39.087035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8630 11:36:39.127934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8631 11:36:39.128203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8633 11:36:39.170485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8634 11:36:39.170761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8636 11:36:39.211124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8637 11:36:39.211416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8639 11:36:39.248865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8640 11:36:39.249127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8642 11:36:39.290500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8643 11:36:39.290918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8645 11:36:39.337511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8646 11:36:39.338279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8648 11:36:39.384528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8649 11:36:39.385231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8651 11:36:39.431433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8652 11:36:39.432100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8654 11:36:39.479982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8655 11:36:39.480798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8657 11:36:39.532901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8658 11:36:39.533607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8660 11:36:39.580522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8661 11:36:39.580770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8663 11:36:39.627073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8664 11:36:39.627325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8666 11:36:39.671724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8667 11:36:39.671972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8669 11:36:39.714984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8670 11:36:39.715237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8672 11:36:39.757417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8673 11:36:39.757664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8675 11:36:39.801333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8676 11:36:39.801602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8678 11:36:39.845619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8679 11:36:39.845874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8681 11:36:39.888242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8682 11:36:39.888492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8684 11:36:39.936809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8685 11:36:39.937064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8687 11:36:39.979716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8688 11:36:39.979969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8690 11:36:40.022451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8691 11:36:40.022701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8693 11:36:40.067054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8694 11:36:40.067307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8696 11:36:40.110044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8697 11:36:40.110293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8699 11:36:40.154099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8700 11:36:40.154351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8702 11:36:40.191877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8703 11:36:40.192127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8705 11:36:40.234281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8706 11:36:40.234544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8708 11:36:40.277802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8709 11:36:40.278058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8711 11:36:40.315715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8712 11:36:40.315985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8714 11:36:40.355417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8715 11:36:40.355664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8717 11:36:40.395925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8718 11:36:40.396199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8720 11:36:40.435704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8721 11:36:40.435962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8723 11:36:40.473895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8724 11:36:40.474147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8726 11:36:40.513904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8727 11:36:40.514165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8729 11:36:40.552585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8730 11:36:40.552840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8732 11:36:40.593035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8733 11:36:40.593298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8735 11:36:40.634823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8736 11:36:40.635076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8738 11:36:40.674559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8739 11:36:40.674809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8741 11:36:40.714429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8742 11:36:40.714702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8744 11:36:40.751594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8745 11:36:40.751843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8747 11:36:40.794760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8748 11:36:40.795011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8750 11:36:40.834520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8751 11:36:40.834782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8753 11:36:40.873090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8754 11:36:40.873360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8756 11:36:40.913612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8757 11:36:40.913860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8759 11:36:40.953471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8760 11:36:40.953722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8762 11:36:40.994768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8763 11:36:40.995016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8765 11:36:41.027495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8766 11:36:41.027740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8768 11:36:41.066586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8769 11:36:41.066831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8771 11:36:41.105260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8772 11:36:41.105507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8774 11:36:41.142959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8775 11:36:41.143206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8777 11:36:41.180367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8778 11:36:41.180613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8780 11:36:41.219188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8781 11:36:41.219434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8783 11:36:41.259544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8784 11:36:41.259822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8786 11:36:41.294613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8787 11:36:41.294875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8789 11:36:41.342976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8790 11:36:41.343232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8792 11:36:41.376990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8793 11:36:41.377261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8795 11:36:41.418796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8796 11:36:41.419045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8798 11:36:41.461024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8799 11:36:41.461305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8801 11:36:41.504259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8802 11:36:41.504511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8804 11:36:41.547992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8805 11:36:41.548245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8807 11:36:41.587402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8808 11:36:41.587656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8810 11:36:41.629166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8811 11:36:41.629417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8813 11:36:41.672988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8814 11:36:41.673241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8816 11:36:41.716093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8817 11:36:41.716353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8819 11:36:41.758402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8820 11:36:41.758654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8822 11:36:41.794825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8823 11:36:41.795071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8825 11:36:41.835466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8826 11:36:41.835717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8828 11:36:41.876428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8829 11:36:41.876675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8831 11:36:41.924123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8832 11:36:41.924371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8834 11:36:41.962496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8835 11:36:41.962745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8837 11:36:42.005781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8838 11:36:42.006033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8840 11:36:42.049892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8841 11:36:42.050145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8843 11:36:42.093330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8844 11:36:42.093580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8846 11:36:42.138138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8847 11:36:42.138387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8849 11:36:42.180425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8850 11:36:42.180670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8852 11:36:42.225431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8853 11:36:42.225680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8855 11:36:42.267627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8856 11:36:42.267876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8858 11:36:42.310764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8859 11:36:42.311021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8861 11:36:42.353305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8862 11:36:42.353561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8864 11:36:42.398737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8865 11:36:42.398992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8867 11:36:42.440806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8868 11:36:42.441077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8870 11:36:42.481743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8871 11:36:42.481991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8873 11:36:42.529378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8874 11:36:42.529628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8876 11:36:42.572262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8877 11:36:42.572514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8879 11:36:42.616101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8880 11:36:42.616373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8882 11:36:42.654844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8883 11:36:42.655092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8885 11:36:42.696516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8886 11:36:42.696769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8888 11:36:42.738239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8889 11:36:42.738495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8891 11:36:42.773594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8892 11:36:42.773850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8894 11:36:42.817869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8895 11:36:42.818126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8897 11:36:42.855988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8898 11:36:42.856238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8900 11:36:42.894215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8901 11:36:42.894463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8903 11:36:42.936100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8904 11:36:42.936349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8906 11:36:42.974492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8907 11:36:42.974744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8909 11:36:43.020142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8910 11:36:43.020397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8912 11:36:43.055314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8913 11:36:43.055565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8915 11:36:43.099214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8916 11:36:43.099468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8918 11:36:43.143711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8919 11:36:43.143963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8921 11:36:43.183414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8922 11:36:43.183664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8924 11:36:43.223720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8925 11:36:43.223973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8927 11:36:43.265513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8928 11:36:43.265795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8930 11:36:43.306038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8931 11:36:43.306289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8933 11:36:43.343915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8934 11:36:43.344167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8936 11:36:43.387752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8937 11:36:43.388020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8939 11:36:43.426543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8940 11:36:43.426794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8942 11:36:43.467614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8943 11:36:43.467865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8945 11:36:43.510849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8946 11:36:43.511103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8948 11:36:43.553103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8949 11:36:43.553394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8951 11:36:43.591865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8952 11:36:43.592138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8954 11:36:43.628625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8955 11:36:43.628878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8957 11:36:43.674409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8958 11:36:43.674659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8960 11:36:43.718830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8961 11:36:43.719082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8963 11:36:43.761895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8964 11:36:43.762146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8966 11:36:43.804525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8967 11:36:43.804775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8969 11:36:43.843717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8970 11:36:43.843970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8972 11:36:43.882942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8973 11:36:43.883195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8975 11:36:43.918889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8976 11:36:43.919142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8978 11:36:43.964379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8979 11:36:43.964644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8981 11:36:44.000240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8982 11:36:44.000493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8984 11:36:44.039614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8985 11:36:44.039867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8987 11:36:44.077534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8988 11:36:44.077791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8990 11:36:44.116265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8991 11:36:44.116519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8993 11:36:44.155503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8994 11:36:44.155758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8996 11:36:44.192152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8997 11:36:44.192398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8999 11:36:44.239069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
9000 11:36:44.239319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
9002 11:36:44.281161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
9003 11:36:44.281411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
9005 11:36:44.324243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
9006 11:36:44.324518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
9008 11:36:44.362308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
9009 11:36:44.362558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
9011 11:36:44.402557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
9012 11:36:44.402807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
9014 11:36:44.441859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
9015 11:36:44.442149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
9017 11:36:44.480128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
9018 11:36:44.480379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
9020 11:36:44.521054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
9021 11:36:44.521332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
9023 11:36:44.560133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
9024 11:36:44.560384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
9026 11:36:44.604109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
9027 11:36:44.604360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
9029 11:36:44.646264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
9030 11:36:44.646518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
9032 11:36:44.688460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
9033 11:36:44.688712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
9035 11:36:44.725942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
9036 11:36:44.726217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
9038 11:36:44.764402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
9039 11:36:44.764654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
9041 11:36:44.808639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
9042 11:36:44.808889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
9044 11:36:44.850205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
9045 11:36:44.850454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
9047 11:36:44.894981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
9048 11:36:44.895230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
9050 11:36:44.942833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
9051 11:36:44.943090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
9053 11:36:44.983847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
9054 11:36:44.984117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
9056 11:36:45.026697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
9057 11:36:45.026961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
9059 11:36:45.064782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
9060 11:36:45.065063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
9062 11:36:45.111615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
9063 11:36:45.111871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
9065 11:36:45.155620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
9066 11:36:45.155881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
9068 11:36:45.197324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
9069 11:36:45.197577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
9071 11:36:45.242223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
9072 11:36:45.242492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
9074 11:36:45.287012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
9075 11:36:45.287265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
9077 11:36:45.326590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
9078 11:36:45.326837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
9080 11:36:45.369668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
9081 11:36:45.369965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
9083 11:36:45.414660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
9084 11:36:45.414923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
9086 11:36:45.459675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
9087 11:36:45.459934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
9089 11:36:45.501537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
9090 11:36:45.501796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
9092 11:36:45.543361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
9093 11:36:45.543612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
9095 11:36:45.583973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
9096 11:36:45.584222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
9098 11:36:45.627606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
9099 11:36:45.627853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
9101 11:36:45.667364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
9102 11:36:45.667613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
9104 11:36:45.713922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
9105 11:36:45.714172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
9107 11:36:45.755038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
9108 11:36:45.755286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
9110 11:36:45.795586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
9111 11:36:45.795833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
9113 11:36:45.831644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
9114 11:36:45.831889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
9116 11:36:45.871347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
9117 11:36:45.871593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
9119 11:36:45.915475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
9120 11:36:45.915731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
9122 11:36:45.956397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
9123 11:36:45.956646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
9125 11:36:46.001226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
9126 11:36:46.001490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
9128 11:36:46.046253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
9129 11:36:46.046526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
9131 11:36:46.084815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
9132 11:36:46.085071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
9134 11:36:46.124392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
9135 11:36:46.124636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
9137 11:36:46.168131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
9138 11:36:46.168436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
9140 11:36:46.212987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
9141 11:36:46.213233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
9143 11:36:46.250154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
9144 11:36:46.250404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
9146 11:36:46.298405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
9147 11:36:46.298663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
9149 11:36:46.343252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
9150 11:36:46.343509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
9152 11:36:46.387331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
9153 11:36:46.387590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
9155 11:36:46.428853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
9156 11:36:46.429152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
9158 11:36:46.470076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
9159 11:36:46.470324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
9161 11:36:46.514223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
9162 11:36:46.514475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
9164 11:36:46.550472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
9165 11:36:46.550723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
9167 11:36:46.594138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
9168 11:36:46.594393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
9170 11:36:46.636356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
9171 11:36:46.636602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
9173 11:36:46.679230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
9174 11:36:46.679476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
9176 11:36:46.721104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
9177 11:36:46.721376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
9179 11:36:46.769043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
9180 11:36:46.769325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
9182 11:36:46.811521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
9183 11:36:46.811772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
9185 11:36:46.847904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
9186 11:36:46.848150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
9188 11:36:46.895653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
9189 11:36:46.895900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
9191 11:36:46.938498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
9192 11:36:46.938749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
9194 11:36:46.978243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
9195 11:36:46.978489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
9197 11:36:47.021955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
9198 11:36:47.022200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
9200 11:36:47.066042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9201 11:36:47.066289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9203 11:36:47.109030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9204 11:36:47.109252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9206 11:36:47.144296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9207 11:36:47.144571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9209 11:36:47.188634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9210 11:36:47.188876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9212 11:36:47.228381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9213 11:36:47.228626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9215 11:36:47.268902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9216 11:36:47.269166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9218 11:36:47.309299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9219 11:36:47.309545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9221 11:36:47.351456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9222 11:36:47.351702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9224 11:36:47.389743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9225 11:36:47.389993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9227 11:36:47.430140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9228 11:36:47.430435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9230 11:36:47.474692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9231 11:36:47.474975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9233 11:36:47.516302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9234 11:36:47.516559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9236 11:36:47.556504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9237 11:36:47.556772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9239 11:36:47.602090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9240 11:36:47.602350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9242 11:36:47.646189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9243 11:36:47.646439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9245 11:36:47.685856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9246 11:36:47.686101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9248 11:36:47.719296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9249 11:36:47.719544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9251 11:36:47.762111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9252 11:36:47.762363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9254 11:36:47.805591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9255 11:36:47.805842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9257 11:36:47.847766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9258 11:36:47.848029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9260 11:36:47.889613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9261 11:36:47.889858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9263 11:36:47.936157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9264 11:36:47.936406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9266 11:36:47.975764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9267 11:36:47.976016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9269 11:36:48.014582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9270 11:36:48.014825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9272 11:36:48.059634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9273 11:36:48.059880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9275 11:36:48.101917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9276 11:36:48.102164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9278 11:36:48.145425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9279 11:36:48.145672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9281 11:36:48.189812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9282 11:36:48.190060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9284 11:36:48.231420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9285 11:36:48.231670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9287 11:36:48.272459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9288 11:36:48.272706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9290 11:36:48.313674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9291 11:36:48.313921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9293 11:36:48.356819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9294 11:36:48.357065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9296 11:36:48.393664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9297 11:36:48.393934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9299 11:36:48.438371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9300 11:36:48.438619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9302 11:36:48.485609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9303 11:36:48.485855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9305 11:36:48.526655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9306 11:36:48.526909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9308 11:36:48.571424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9309 11:36:48.571684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9311 11:36:48.613899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9312 11:36:48.614158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9314 11:36:48.663263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9315 11:36:48.663527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9317 11:36:48.703831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9318 11:36:48.704078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9320 11:36:48.747324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9321 11:36:48.747572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9323 11:36:48.791345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9324 11:36:48.791594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9326 11:36:48.835515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9327 11:36:48.835762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9329 11:36:48.880003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9330 11:36:48.880256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9332 11:36:48.920120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9333 11:36:48.920384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9335 11:36:48.963867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9336 11:36:48.964121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9338 11:36:49.007356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9339 11:36:49.007600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9341 11:36:49.047101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9342 11:36:49.047350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9344 11:36:49.090069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9345 11:36:49.090314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9347 11:36:49.132432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9348 11:36:49.132684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9350 11:36:49.176531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9351 11:36:49.176782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9353 11:36:49.213791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9354 11:36:49.214041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9356 11:36:49.259388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9357 11:36:49.259639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9359 11:36:49.304525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9360 11:36:49.304770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9362 11:36:49.345476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9363 11:36:49.345722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9365 11:36:49.386267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9366 11:36:49.386513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9368 11:36:49.428749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9369 11:36:49.428998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9371 11:36:49.469085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9373 11:36:49.471594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9374 11:36:49.507546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9375 11:36:49.507792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9377 11:36:49.553878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9378 11:36:49.554121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9380 11:36:49.596326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9381 11:36:49.596596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9383 11:36:49.637576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9384 11:36:49.637821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9386 11:36:49.683438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9387 11:36:49.683718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9389 11:36:49.726123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9390 11:36:49.726859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9392 11:36:49.776418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9393 11:36:49.777057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9395 11:36:49.829651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9396 11:36:49.830309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9398 11:36:49.886394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9399 11:36:49.887064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9401 11:36:49.941585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9402 11:36:49.942266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9404 11:36:49.989669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9405 11:36:49.990311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9407 11:36:50.041781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9408 11:36:50.042432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9410 11:36:50.097580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9411 11:36:50.098210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9413 11:36:50.153212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9414 11:36:50.153864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9416 11:36:50.204700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9417 11:36:50.205401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9419 11:36:50.262645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9420 11:36:50.263372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9422 11:36:50.307865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9423 11:36:50.308127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9425 11:36:50.348107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9426 11:36:50.348354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9428 11:36:50.391994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9429 11:36:50.392248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9431 11:36:50.432045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9432 11:36:50.432291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9434 11:36:50.472384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9435 11:36:50.472660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9437 11:36:50.510751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9438 11:36:50.510997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9440 11:36:50.555488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9441 11:36:50.555739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9443 11:36:50.600412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9444 11:36:50.600658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9446 11:36:50.643776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9447 11:36:50.644040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9449 11:36:50.692314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9450 11:36:50.692705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9452 11:36:50.746272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9453 11:36:50.746913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9455 11:36:50.796231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9456 11:36:50.796507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9458 11:36:50.848337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9459 11:36:50.848633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9461 11:36:50.902914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9462 11:36:50.903570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9464 11:36:50.960215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9465 11:36:50.960880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9467 11:36:51.022778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9468 11:36:51.023572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9470 11:36:51.071762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9471 11:36:51.072022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9473 11:36:51.116606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9474 11:36:51.116854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9476 11:36:51.160538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9477 11:36:51.160802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9479 11:36:51.204718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9480 11:36:51.205333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9482 11:36:51.252431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9483 11:36:51.252678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9485 11:36:51.298844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9486 11:36:51.299530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9488 11:36:51.347308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9489 11:36:51.347615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9491 11:36:51.394985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9492 11:36:51.395560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9494 11:36:51.449098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9495 11:36:51.449807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9497 11:36:51.501818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9498 11:36:51.502465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9500 11:36:51.554754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9501 11:36:51.555421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9503 11:36:51.607522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9504 11:36:51.607772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9506 11:36:51.657862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9507 11:36:51.658317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9509 11:36:51.704622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9510 11:36:51.704958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9512 11:36:51.753343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9513 11:36:51.753915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9515 11:36:51.803511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9516 11:36:51.803779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9518 11:36:51.852692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9519 11:36:51.852985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9521 11:36:51.895104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9522 11:36:51.895448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9524 11:36:51.942940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9525 11:36:51.943606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9527 11:36:51.997025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9528 11:36:51.997786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9530 11:36:52.051886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9531 11:36:52.052583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9533 11:36:52.104274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9534 11:36:52.104986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9536 11:36:52.158448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9537 11:36:52.159258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9539 11:36:52.213220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9540 11:36:52.213864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9542 11:36:52.270112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9543 11:36:52.270761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9545 11:36:52.326456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9546 11:36:52.327103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9548 11:36:52.381854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9549 11:36:52.382553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9551 11:36:52.439064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9552 11:36:52.439785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9554 11:36:52.498059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9555 11:36:52.498717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9557 11:36:52.554284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9558 11:36:52.554983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9560 11:36:52.608623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9561 11:36:52.609006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9563 11:36:52.656043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9564 11:36:52.656353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9566 11:36:52.705206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9567 11:36:52.705468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9569 11:36:52.748643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9570 11:36:52.749346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9572 11:36:52.803101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9573 11:36:52.803808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9575 11:36:52.856138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9576 11:36:52.856464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9578 11:36:52.910047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9579 11:36:52.910586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9581 11:36:52.957440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9582 11:36:52.957710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9584 11:36:53.003941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9585 11:36:53.004280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9587 11:36:53.061050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9588 11:36:53.061729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9590 11:36:53.111687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9591 11:36:53.111947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9593 11:36:53.164295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9594 11:36:53.164643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9596 11:36:53.210652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9597 11:36:53.210901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9599 11:36:53.251987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9600 11:36:53.252236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9602 11:36:53.292798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9603 11:36:53.293081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9605 11:36:53.334713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9606 11:36:53.335141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9608 11:36:53.389109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9609 11:36:53.389790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9611 11:36:53.437384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9612 11:36:53.438015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9614 11:36:53.491881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9615 11:36:53.492515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9617 11:36:53.542920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9618 11:36:53.543557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9620 11:36:53.597177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9621 11:36:53.597822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9623 11:36:53.646804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9624 11:36:53.647431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9626 11:36:53.699846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9627 11:36:53.700539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9629 11:36:53.753083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9630 11:36:53.753752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9632 11:36:53.803131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9633 11:36:53.803890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9635 11:36:53.855140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9636 11:36:53.855869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9638 11:36:53.907716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9639 11:36:53.908427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9641 11:36:53.959454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9642 11:36:53.960103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9644 11:36:54.015016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9645 11:36:54.015811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9647 11:36:54.066620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9648 11:36:54.067375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9650 11:36:54.122172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9651 11:36:54.122846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9653 11:36:54.177263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9654 11:36:54.178031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9656 11:36:54.236065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9657 11:36:54.236790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9659 11:36:54.289989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9660 11:36:54.290652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9662 11:36:54.343420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9663 11:36:54.344126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9665 11:36:54.401087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9666 11:36:54.401805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9668 11:36:54.454769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9669 11:36:54.455405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9671 11:36:54.510349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9672 11:36:54.510989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9674 11:36:54.564866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9675 11:36:54.565695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9677 11:36:54.620610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9678 11:36:54.621224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9680 11:36:54.678204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9681 11:36:54.678940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9683 11:36:54.732062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9684 11:36:54.732819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9686 11:36:54.785439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9687 11:36:54.786239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9689 11:36:54.834838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9691 11:36:54.836644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9692 11:36:54.892867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9693 11:36:54.893700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9695 11:36:54.951595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9696 11:36:54.952400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9698 11:36:55.006480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9699 11:36:55.007136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9701 11:36:55.059835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9702 11:36:55.060573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9704 11:36:55.116313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9705 11:36:55.117070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9707 11:36:55.175088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9708 11:36:55.175879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9710 11:36:55.227061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9711 11:36:55.227866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9713 11:36:55.285467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9714 11:36:55.286110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9716 11:36:55.336658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9717 11:36:55.337495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9719 11:36:55.393673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9720 11:36:55.394340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9722 11:36:55.451713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9723 11:36:55.452494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9725 11:36:55.508374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9726 11:36:55.509046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9728 11:36:55.565235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9729 11:36:55.566069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9731 11:36:55.620229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9732 11:36:55.620903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9734 11:36:55.683703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9735 11:36:55.684499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9737 11:36:55.740539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9738 11:36:55.741407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9740 11:36:55.796333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9741 11:36:55.797106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9743 11:36:55.854634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9744 11:36:55.855352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9746 11:36:55.912708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9747 11:36:55.913340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9749 11:36:55.959195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9750 11:36:55.959556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9752 11:36:56.003616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9753 11:36:56.004257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9755 11:36:56.055508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9756 11:36:56.056135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9758 11:36:56.105330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9759 11:36:56.105958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9761 11:36:56.160625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9762 11:36:56.161214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9764 11:36:56.217425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9765 11:36:56.218067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9767 11:36:56.275379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9768 11:36:56.276009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9770 11:36:56.329474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9771 11:36:56.330124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9773 11:36:56.380153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9774 11:36:56.380794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9776 11:36:56.438874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9777 11:36:56.439546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9779 11:36:56.494611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9780 11:36:56.495251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9782 11:36:56.551467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9783 11:36:56.552228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9785 11:36:56.607412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9786 11:36:56.608185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9788 11:36:56.662842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9789 11:36:56.663510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9791 11:36:56.720727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9792 11:36:56.721531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9794 11:36:56.776278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9795 11:36:56.776984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9797 11:36:56.835370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9798 11:36:56.836009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9800 11:36:56.894024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9801 11:36:56.894756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9803 11:36:56.947463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9804 11:36:56.947787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9806 11:36:56.996810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9807 11:36:56.997134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9809 11:36:57.051829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9810 11:36:57.052117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9812 11:36:57.097963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9813 11:36:57.098294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9815 11:36:57.140516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9816 11:36:57.140771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9818 11:36:57.192119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9819 11:36:57.192803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9821 11:36:57.240808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9822 11:36:57.241148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9824 11:36:57.296063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9825 11:36:57.296743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9827 11:36:57.344945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9828 11:36:57.345207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9830 11:36:57.393328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9831 11:36:57.394100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9833 11:36:57.441851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9834 11:36:57.442114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9836 11:36:57.492699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9837 11:36:57.493286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9839 11:36:57.551922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9840 11:36:57.552550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9842 11:36:57.602091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9843 11:36:57.602449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9845 11:36:57.650383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9846 11:36:57.650675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9848 11:36:57.701825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9849 11:36:57.702508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9851 11:36:57.753323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9852 11:36:57.753949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9854 11:36:57.809560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9855 11:36:57.810367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9857 11:36:57.862562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9858 11:36:57.863339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9860 11:36:57.921748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9861 11:36:57.922541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9863 11:36:57.980618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9864 11:36:57.981340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9866 11:36:58.036807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9867 11:36:58.037487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9869 11:36:58.087996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9870 11:36:58.088707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9872 11:36:58.142682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9873 11:36:58.142958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9875 11:36:58.187910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9876 11:36:58.188196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9878 11:36:58.232951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9879 11:36:58.233238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9881 11:36:58.285220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9882 11:36:58.285869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9884 11:36:58.332459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9885 11:36:58.332723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9887 11:36:58.382882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9888 11:36:58.383440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9890 11:36:58.433344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9891 11:36:58.433966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9893 11:36:58.484588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9894 11:36:58.484835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9896 11:36:58.530931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9897 11:36:58.531177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9899 11:36:58.574446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9900 11:36:58.574773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9902 11:36:58.622976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9903 11:36:58.623507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9905 11:36:58.676389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9906 11:36:58.677015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9908 11:36:58.731075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9909 11:36:58.731323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9911 11:36:58.776775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9912 11:36:58.777018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9914 11:36:58.823276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9915 11:36:58.823910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9917 11:36:58.871975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9918 11:36:58.872297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9920 11:36:58.914602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9921 11:36:58.914874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9923 11:36:58.956840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9924 11:36:58.957093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9926 11:36:58.992686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9927 11:36:58.992941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9929 11:36:59.030206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9930 11:36:59.030461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9932 11:36:59.069915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9933 11:36:59.070591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9935 11:36:59.119106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9936 11:36:59.119927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9938 11:36:59.169035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9939 11:36:59.169359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9941 11:36:59.215345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9942 11:36:59.215986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9944 11:36:59.272441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9945 11:36:59.272858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9947 11:36:59.322017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9948 11:36:59.322340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9950 11:36:59.372083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9951 11:36:59.372786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9953 11:36:59.422035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9954 11:36:59.422357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9956 11:36:59.472281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9957 11:36:59.472608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9959 11:36:59.519285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9960 11:36:59.519546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9962 11:36:59.562979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9963 11:36:59.563311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9965 11:36:59.614094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9966 11:36:59.614396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9968 11:36:59.663121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9969 11:36:59.663745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9971 11:36:59.708216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9972 11:36:59.708840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9974 11:36:59.755931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9975 11:36:59.756205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9977 11:36:59.805152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9978 11:36:59.805779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9980 11:36:59.855996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9981 11:36:59.856619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9983 11:36:59.902031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9984 11:36:59.902855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9986 11:36:59.953643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9987 11:36:59.953891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9989 11:37:00.000867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9990 11:37:00.001634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9992 11:37:00.057778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9993 11:37:00.058485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9995 11:37:00.115540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9996 11:37:00.116252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9998 11:37:00.177037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9999 11:37:00.177863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
10001 11:37:00.229641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
10002 11:37:00.230487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
10004 11:37:00.285460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
10005 11:37:00.286146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
10007 11:37:00.345847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
10008 11:37:00.346584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
10010 11:37:00.405609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
10011 11:37:00.406296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
10013 11:37:00.464155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
10014 11:37:00.464780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
10016 11:37:00.521060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
10017 11:37:00.521728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
10019 11:37:00.574256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
10020 11:37:00.574894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
10022 11:37:00.633854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
10023 11:37:00.634539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
10025 11:37:00.691690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
10026 11:37:00.692388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
10028 11:37:00.750998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
10029 11:37:00.751698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
10031 11:37:00.808604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
10032 11:37:00.809483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
10034 11:37:00.862739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
10035 11:37:00.863369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
10037 11:37:00.916371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
10038 11:37:00.917028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
10040 11:37:00.969378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
10041 11:37:00.970013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
10043 11:37:01.023984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
10044 11:37:01.024613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
10046 11:37:01.075844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
10047 11:37:01.076465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
10049 11:37:01.133165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
10050 11:37:01.133798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
10052 11:37:01.184699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
10053 11:37:01.185323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
10055 11:37:01.240334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
10056 11:37:01.240974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
10058 11:37:01.289634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
10059 11:37:01.289910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
10061 11:37:01.336405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
10062 11:37:01.336671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
10064 11:37:01.381953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
10065 11:37:01.382217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
10067 11:37:01.421336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
10068 11:37:01.421594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
10070 11:37:01.469940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
10071 11:37:01.470212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
10073 11:37:01.513908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
10074 11:37:01.514210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
10076 11:37:01.562802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
10077 11:37:01.563107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
10079 11:37:01.612986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
10080 11:37:01.613386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
10082 11:37:01.665126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
10083 11:37:01.665384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
10085 11:37:01.708937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
10086 11:37:01.709155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
10088 11:37:01.750788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
10089 11:37:01.751418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
10091 11:37:01.803555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
10092 11:37:01.803851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
10094 11:37:01.847784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
10095 11:37:01.848069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
10097 11:37:01.896592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
10098 11:37:01.896889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
10100 11:37:01.944261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
10101 11:37:01.944942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
10103 11:37:01.991788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
10104 11:37:01.992058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
10106 11:37:02.035521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
10107 11:37:02.036154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
10109 11:37:02.079573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
10110 11:37:02.080294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
10112 11:37:02.132321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
10113 11:37:02.132575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
10115 11:37:02.179161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
10116 11:37:02.179407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
10118 11:37:02.223572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
10119 11:37:02.224200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
10121 11:37:02.277619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
10122 11:37:02.278254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
10124 11:37:02.328829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
10125 11:37:02.329102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
10127 11:37:02.365516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
10129 11:37:02.368026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
10130 11:37:02.402633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
10131 11:37:02.402878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
10133 11:37:02.445861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
10134 11:37:02.446108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
10136 11:37:02.484177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
10137 11:37:02.484458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
10139 11:37:02.526299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
10140 11:37:02.526666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
10142 11:37:02.565238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
10143 11:37:02.565513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
10145 11:37:02.610142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
10146 11:37:02.610414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
10148 11:37:02.654111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
10149 11:37:02.654384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
10151 11:37:02.693869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
10152 11:37:02.694111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
10154 11:37:02.743022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
10155 11:37:02.743298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
10157 11:37:02.786382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
10158 11:37:02.786648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
10160 11:37:02.833599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
10161 11:37:02.833866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
10163 11:37:02.876249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
10164 11:37:02.876522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
10166 11:37:02.920585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
10167 11:37:02.920861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
10169 11:37:02.959173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10170 11:37:02.959272 + set +x
10171 11:37:02.959525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10173 11:37:02.965856 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14864608_1.6.2.3.5>
10174 11:37:02.966116 Received signal: <ENDRUN> 1_kselftest-alsa 14864608_1.6.2.3.5
10175 11:37:02.966209 Ending use of test pattern.
10176 11:37:02.966290 Ending test lava.1_kselftest-alsa (14864608_1.6.2.3.5), duration 45.21
10178 11:37:02.969331 <LAVA_TEST_RUNNER EXIT>
10179 11:37:02.969567 ok: lava_test_shell seems to have completed
10180 11:37:02.972664 shardfile-alsa: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_valid_0_93: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test: pass
10181 11:37:02.973043 end: 3.1 lava-test-shell (duration 00:00:46) [common]
10182 11:37:02.973210 end: 3 lava-test-retry (duration 00:00:46) [common]
10183 11:37:02.973313 start: 4 finalize (timeout 00:07:22) [common]
10184 11:37:02.973394 start: 4.1 power-off (timeout 00:00:30) [common]
10185 11:37:02.973525 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1', '--port=1', '--command=off']
10186 11:37:05.068124 >> Command sent successfully.
10187 11:37:05.081742 Returned 0 in 2 seconds
10188 11:37:05.082297 end: 4.1 power-off (duration 00:00:02) [common]
10190 11:37:05.083228 start: 4.2 read-feedback (timeout 00:07:20) [common]
10191 11:37:05.083827 Listened to connection for namespace 'common' for up to 1s
10192 11:37:06.084858 Finalising connection for namespace 'common'
10193 11:37:06.085488 Disconnecting from shell: Finalise
10194 11:37:06.085969 / #
10195 11:37:06.186908 end: 4.2 read-feedback (duration 00:00:01) [common]
10196 11:37:06.187429 end: 4 finalize (duration 00:00:03) [common]
10197 11:37:06.187903 Cleaning after the job
10198 11:37:06.188456 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/ramdisk
10199 11:37:06.198675 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/kernel
10200 11:37:06.228908 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/dtb
10201 11:37:06.229427 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/nfsrootfs
10202 11:37:06.296442 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864608/tftp-deploy-bhuaup7q/modules
10203 11:37:06.302068 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864608
10204 11:37:06.894403 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864608
10205 11:37:06.894566 Job finished correctly