Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:31:24.797230 lava-dispatcher, installed at version: 2024.05
2 11:31:24.797460 start: 0 validate
3 11:31:24.797582 Start time: 2024-07-17 11:31:24.797577+00:00 (UTC)
4 11:31:24.797721 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:31:24.797866 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:31:25.058883 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:31:25.059592 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:31:52.331193 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:31:52.331951 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:31:52.585414 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:31:52.585996 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:31:53.090944 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:31:53.091525 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:31:56.101757 validate duration: 31.30
16 11:31:56.101999 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:31:56.102090 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:31:56.102168 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:31:56.102315 Not decompressing ramdisk as can be used compressed.
20 11:31:56.102395 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:31:56.102456 saving as /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/ramdisk/initrd.cpio.gz
22 11:31:56.102517 total size: 5628169 (5 MB)
23 11:31:56.360245 progress 0 % (0 MB)
24 11:31:56.361962 progress 5 % (0 MB)
25 11:31:56.363457 progress 10 % (0 MB)
26 11:31:56.364792 progress 15 % (0 MB)
27 11:31:56.366333 progress 20 % (1 MB)
28 11:31:56.367657 progress 25 % (1 MB)
29 11:31:56.369129 progress 30 % (1 MB)
30 11:31:56.370673 progress 35 % (1 MB)
31 11:31:56.371985 progress 40 % (2 MB)
32 11:31:56.373488 progress 45 % (2 MB)
33 11:31:56.374845 progress 50 % (2 MB)
34 11:31:56.376355 progress 55 % (2 MB)
35 11:31:56.377852 progress 60 % (3 MB)
36 11:31:56.379145 progress 65 % (3 MB)
37 11:31:56.380597 progress 70 % (3 MB)
38 11:31:56.381941 progress 75 % (4 MB)
39 11:31:56.383378 progress 80 % (4 MB)
40 11:31:56.384660 progress 85 % (4 MB)
41 11:31:56.386212 progress 90 % (4 MB)
42 11:31:56.387646 progress 95 % (5 MB)
43 11:31:56.388987 progress 100 % (5 MB)
44 11:31:56.389183 5 MB downloaded in 0.29 s (18.72 MB/s)
45 11:31:56.389369 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:31:56.389589 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:31:56.389667 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:31:56.389742 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:31:56.389859 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:31:56.389920 saving as /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/kernel/Image
52 11:31:56.389972 total size: 54813184 (52 MB)
53 11:31:56.390024 No compression specified
54 11:31:56.391005 progress 0 % (0 MB)
55 11:31:56.403912 progress 5 % (2 MB)
56 11:31:56.417021 progress 10 % (5 MB)
57 11:31:56.430144 progress 15 % (7 MB)
58 11:31:56.443113 progress 20 % (10 MB)
59 11:31:56.456776 progress 25 % (13 MB)
60 11:31:56.469805 progress 30 % (15 MB)
61 11:31:56.483296 progress 35 % (18 MB)
62 11:31:56.497503 progress 40 % (20 MB)
63 11:31:56.511143 progress 45 % (23 MB)
64 11:31:56.524651 progress 50 % (26 MB)
65 11:31:56.538587 progress 55 % (28 MB)
66 11:31:56.552231 progress 60 % (31 MB)
67 11:31:56.565678 progress 65 % (34 MB)
68 11:31:56.579129 progress 70 % (36 MB)
69 11:31:56.593015 progress 75 % (39 MB)
70 11:31:56.607497 progress 80 % (41 MB)
71 11:31:56.620829 progress 85 % (44 MB)
72 11:31:56.634087 progress 90 % (47 MB)
73 11:31:56.647467 progress 95 % (49 MB)
74 11:31:56.660480 progress 100 % (52 MB)
75 11:31:56.660738 52 MB downloaded in 0.27 s (193.06 MB/s)
76 11:31:56.660881 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:31:56.661088 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:31:56.661167 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:31:56.661267 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:31:56.661409 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:31:56.661472 saving as /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/dtb/mt8192-asurada-spherion-r0.dtb
83 11:31:56.661523 total size: 47258 (0 MB)
84 11:31:56.661575 No compression specified
85 11:31:56.662707 progress 69 % (0 MB)
86 11:31:56.662960 progress 100 % (0 MB)
87 11:31:56.663104 0 MB downloaded in 0.00 s (28.55 MB/s)
88 11:31:56.663213 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:31:56.663408 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:31:56.663481 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:31:56.663555 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:31:56.663658 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:31:56.663718 saving as /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/nfsrootfs/full.rootfs.tar
95 11:31:56.663769 total size: 120894716 (115 MB)
96 11:31:56.663823 Using unxz to decompress xz
97 11:31:56.665037 progress 0 % (0 MB)
98 11:31:57.003329 progress 5 % (5 MB)
99 11:31:57.352673 progress 10 % (11 MB)
100 11:31:57.695681 progress 15 % (17 MB)
101 11:31:58.017438 progress 20 % (23 MB)
102 11:31:58.320929 progress 25 % (28 MB)
103 11:31:58.669974 progress 30 % (34 MB)
104 11:31:58.994478 progress 35 % (40 MB)
105 11:31:59.165921 progress 40 % (46 MB)
106 11:31:59.347192 progress 45 % (51 MB)
107 11:31:59.641984 progress 50 % (57 MB)
108 11:31:59.998569 progress 55 % (63 MB)
109 11:32:00.341047 progress 60 % (69 MB)
110 11:32:00.676696 progress 65 % (74 MB)
111 11:32:01.015942 progress 70 % (80 MB)
112 11:32:01.373104 progress 75 % (86 MB)
113 11:32:01.701475 progress 80 % (92 MB)
114 11:32:02.047437 progress 85 % (98 MB)
115 11:32:02.393297 progress 90 % (103 MB)
116 11:32:02.721699 progress 95 % (109 MB)
117 11:32:03.082907 progress 100 % (115 MB)
118 11:32:03.088516 115 MB downloaded in 6.42 s (17.95 MB/s)
119 11:32:03.088704 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:32:03.088916 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:32:03.088992 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:32:03.089066 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:32:03.089193 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:32:03.089298 saving as /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/modules/modules.tar
126 11:32:03.089353 total size: 8610184 (8 MB)
127 11:32:03.089408 Using unxz to decompress xz
128 11:32:03.351393 progress 0 % (0 MB)
129 11:32:03.372646 progress 5 % (0 MB)
130 11:32:03.398925 progress 10 % (0 MB)
131 11:32:03.425385 progress 15 % (1 MB)
132 11:32:03.451217 progress 20 % (1 MB)
133 11:32:03.475412 progress 25 % (2 MB)
134 11:32:03.500420 progress 30 % (2 MB)
135 11:32:03.524197 progress 35 % (2 MB)
136 11:32:03.551858 progress 40 % (3 MB)
137 11:32:03.577556 progress 45 % (3 MB)
138 11:32:03.602148 progress 50 % (4 MB)
139 11:32:03.626769 progress 55 % (4 MB)
140 11:32:03.651641 progress 60 % (4 MB)
141 11:32:03.674775 progress 65 % (5 MB)
142 11:32:03.699762 progress 70 % (5 MB)
143 11:32:03.726316 progress 75 % (6 MB)
144 11:32:03.753261 progress 80 % (6 MB)
145 11:32:03.776869 progress 85 % (7 MB)
146 11:32:03.800748 progress 90 % (7 MB)
147 11:32:03.824108 progress 95 % (7 MB)
148 11:32:03.846775 progress 100 % (8 MB)
149 11:32:03.852218 8 MB downloaded in 0.76 s (10.76 MB/s)
150 11:32:03.852439 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:32:03.852767 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:32:03.852879 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 11:32:03.852990 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 11:32:07.814100 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip
156 11:32:07.814377 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:32:07.814503 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:32:07.814745 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm
159 11:32:07.814911 makedir: /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin
160 11:32:07.815039 makedir: /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/tests
161 11:32:07.815164 makedir: /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/results
162 11:32:07.815283 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-add-keys
163 11:32:07.815470 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-add-sources
164 11:32:07.815637 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-background-process-start
165 11:32:07.815800 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-background-process-stop
166 11:32:07.815931 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-common-functions
167 11:32:07.816047 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-echo-ipv4
168 11:32:07.816162 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-install-packages
169 11:32:07.816273 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-installed-packages
170 11:32:07.816384 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-os-build
171 11:32:07.816496 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-probe-channel
172 11:32:07.816607 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-probe-ip
173 11:32:07.816719 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-target-ip
174 11:32:07.816831 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-target-mac
175 11:32:07.816943 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-target-storage
176 11:32:07.817056 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-case
177 11:32:07.817168 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-event
178 11:32:07.817319 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-feedback
179 11:32:07.817459 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-raise
180 11:32:07.817572 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-reference
181 11:32:07.817700 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-runner
182 11:32:07.817811 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-set
183 11:32:07.817921 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-test-shell
184 11:32:07.818037 Updating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-add-keys (debian)
185 11:32:07.818182 Updating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-add-sources (debian)
186 11:32:07.818312 Updating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-install-packages (debian)
187 11:32:07.818438 Updating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-installed-packages (debian)
188 11:32:07.818564 Updating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/bin/lava-os-build (debian)
189 11:32:07.818673 Creating /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/environment
190 11:32:07.818758 LAVA metadata
191 11:32:07.818822 - LAVA_JOB_ID=14864597
192 11:32:07.818895 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:32:07.819024 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:32:07.819121 skipped lava-vland-overlay
195 11:32:07.819193 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:32:07.819264 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:32:07.819344 skipped lava-multinode-overlay
198 11:32:07.819410 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:32:07.819478 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:32:07.819543 Loading test definitions
201 11:32:07.819618 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:32:07.819675 Using /lava-14864597 at stage 0
203 11:32:07.820035 uuid=14864597_1.6.2.3.1 testdef=None
204 11:32:07.820115 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:32:07.820188 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:32:07.820584 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:32:07.820778 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:32:07.821381 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:32:07.821647 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:32:07.822153 runner path: /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/0/tests/0_timesync-off test_uuid 14864597_1.6.2.3.1
213 11:32:07.822295 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:32:07.822492 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:32:07.822556 Using /lava-14864597 at stage 0
217 11:32:07.822644 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:32:07.822718 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/0/tests/1_kselftest-alsa'
219 11:32:10.574162 Running '/usr/bin/git checkout kernelci.org
220 11:32:10.728260 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:32:10.728878 uuid=14864597_1.6.2.3.5 testdef=None
222 11:32:10.729027 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:32:10.729361 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 11:32:10.730339 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:32:10.730643 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 11:32:10.731997 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:32:10.732312 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 11:32:10.733658 runner path: /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/0/tests/1_kselftest-alsa test_uuid 14864597_1.6.2.3.5
232 11:32:10.733768 BOARD='mt8192-asurada-spherion-r0'
233 11:32:10.733852 BRANCH='cip-gitlab'
234 11:32:10.733970 SKIPFILE='/dev/null'
235 11:32:10.734047 SKIP_INSTALL='True'
236 11:32:10.734123 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:32:10.734203 TST_CASENAME=''
238 11:32:10.734280 TST_CMDFILES='alsa'
239 11:32:10.734466 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:32:10.734753 Creating lava-test-runner.conf files
242 11:32:10.734839 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864597/lava-overlay-hz5dlmmm/lava-14864597/0 for stage 0
243 11:32:10.734958 - 0_timesync-off
244 11:32:10.735047 - 1_kselftest-alsa
245 11:32:10.735169 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:32:10.735282 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 11:32:18.064326 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:32:18.064460 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 11:32:18.064547 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:32:18.064628 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 11:32:18.064706 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 11:32:18.210358 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:32:18.210501 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 11:32:18.210575 extracting modules file /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip
255 11:32:18.433787 extracting modules file /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864597/extract-overlay-ramdisk-tssr8jjn/ramdisk
256 11:32:18.665104 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:32:18.665276 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 11:32:18.665369 [common] Applying overlay to NFS
259 11:32:18.665427 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864597/compress-overlay-2fm7wdd2/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip
260 11:32:19.498458 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:32:19.498598 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 11:32:19.498687 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:32:19.498766 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 11:32:19.498834 Building ramdisk /var/lib/lava/dispatcher/tmp/14864597/extract-overlay-ramdisk-tssr8jjn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864597/extract-overlay-ramdisk-tssr8jjn/ramdisk
265 11:32:19.778082 >> 129966 blocks
266 11:32:21.897535 rename /var/lib/lava/dispatcher/tmp/14864597/extract-overlay-ramdisk-tssr8jjn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/ramdisk/ramdisk.cpio.gz
267 11:32:21.897700 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:32:21.897790 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:32:21.897867 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:32:21.897945 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/kernel/Image']
271 11:32:35.439807 Returned 0 in 13 seconds
272 11:32:35.439958 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/kernel/image.itb
273 11:32:35.788048 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:32:35.788164 output: Created: Wed Jul 17 12:32:35 2024
275 11:32:35.788224 output: Image 0 (kernel-1)
276 11:32:35.788277 output: Description:
277 11:32:35.788328 output: Created: Wed Jul 17 12:32:35 2024
278 11:32:35.788379 output: Type: Kernel Image
279 11:32:35.788429 output: Compression: lzma compressed
280 11:32:35.788481 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
281 11:32:35.788530 output: Architecture: AArch64
282 11:32:35.788577 output: OS: Linux
283 11:32:35.788624 output: Load Address: 0x00000000
284 11:32:35.788672 output: Entry Point: 0x00000000
285 11:32:35.788719 output: Hash algo: crc32
286 11:32:35.788766 output: Hash value: 83448d17
287 11:32:35.788813 output: Image 1 (fdt-1)
288 11:32:35.788860 output: Description: mt8192-asurada-spherion-r0
289 11:32:35.788908 output: Created: Wed Jul 17 12:32:35 2024
290 11:32:35.788956 output: Type: Flat Device Tree
291 11:32:35.789003 output: Compression: uncompressed
292 11:32:35.789050 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:32:35.789099 output: Architecture: AArch64
294 11:32:35.789147 output: Hash algo: crc32
295 11:32:35.789193 output: Hash value: 0f8e4d2e
296 11:32:35.789248 output: Image 2 (ramdisk-1)
297 11:32:35.789296 output: Description: unavailable
298 11:32:35.789342 output: Created: Wed Jul 17 12:32:35 2024
299 11:32:35.789389 output: Type: RAMDisk Image
300 11:32:35.789436 output: Compression: uncompressed
301 11:32:35.789483 output: Data Size: 18719884 Bytes = 18281.14 KiB = 17.85 MiB
302 11:32:35.789530 output: Architecture: AArch64
303 11:32:35.789576 output: OS: Linux
304 11:32:35.789622 output: Load Address: unavailable
305 11:32:35.789669 output: Entry Point: unavailable
306 11:32:35.789716 output: Hash algo: crc32
307 11:32:35.789762 output: Hash value: 10b5237e
308 11:32:35.789808 output: Default Configuration: 'conf-1'
309 11:32:35.789854 output: Configuration 0 (conf-1)
310 11:32:35.789900 output: Description: mt8192-asurada-spherion-r0
311 11:32:35.789946 output: Kernel: kernel-1
312 11:32:35.789993 output: Init Ramdisk: ramdisk-1
313 11:32:35.790040 output: FDT: fdt-1
314 11:32:35.790086 output: Loadables: kernel-1
315 11:32:35.790132 output:
316 11:32:35.790231 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:32:35.790303 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:32:35.790377 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:32:35.790451 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 11:32:35.790507 No LXC device requested
321 11:32:35.790571 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:32:35.790640 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 11:32:35.790704 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:32:35.790757 Checking files for TFTP limit of 4294967296 bytes.
325 11:32:35.791120 end: 1 tftp-deploy (duration 00:00:40) [common]
326 11:32:35.791206 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:32:35.791283 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:32:35.791373 substitutions:
329 11:32:35.791431 - {DTB}: 14864597/tftp-deploy-m32fafkl/dtb/mt8192-asurada-spherion-r0.dtb
330 11:32:35.791484 - {INITRD}: 14864597/tftp-deploy-m32fafkl/ramdisk/ramdisk.cpio.gz
331 11:32:35.791536 - {KERNEL}: 14864597/tftp-deploy-m32fafkl/kernel/Image
332 11:32:35.791586 - {LAVA_MAC}: None
333 11:32:35.791634 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip
334 11:32:35.791684 - {NFS_SERVER_IP}: 192.168.201.1
335 11:32:35.791732 - {PRESEED_CONFIG}: None
336 11:32:35.791783 - {PRESEED_LOCAL}: None
337 11:32:35.791831 - {RAMDISK}: 14864597/tftp-deploy-m32fafkl/ramdisk/ramdisk.cpio.gz
338 11:32:35.791878 - {ROOT_PART}: None
339 11:32:35.791925 - {ROOT}: None
340 11:32:35.791974 - {SERVER_IP}: 192.168.201.1
341 11:32:35.792020 - {TEE}: None
342 11:32:35.792067 Parsed boot commands:
343 11:32:35.792113 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:32:35.792247 Parsed boot commands: tftpboot 192.168.201.1 14864597/tftp-deploy-m32fafkl/kernel/image.itb 14864597/tftp-deploy-m32fafkl/kernel/cmdline
345 11:32:35.792324 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:32:35.792396 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:32:35.792468 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:32:35.792537 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:32:35.792591 Not connected, no need to disconnect.
350 11:32:35.792654 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:32:35.792721 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:32:35.792774 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 11:32:35.795777 Setting prompt string to ['lava-test: # ']
354 11:32:35.796076 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:32:35.796168 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:32:35.796254 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:32:35.796332 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:32:35.796499 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 11:32:44.932739 >> Command sent successfully.
360 11:32:44.935879 Returned 0 in 9 seconds
361 11:32:44.936014 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:32:44.936225 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:32:44.936408 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:32:44.936480 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:32:44.936534 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:32:44.936591 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:32:44.936919 [Enter `^Ec?' for help]
369 11:32:46.153111
370 11:32:46.153235
371 11:32:46.153299 F0: 102B 0000
372 11:32:46.153357
373 11:32:46.153412 F3: 1001 0000 [0200]
374 11:32:46.153468
375 11:32:46.157716 F3: 1001 0000
376 11:32:46.157796
377 11:32:46.157853 F7: 102D 0000
378 11:32:46.157926
379 11:32:46.158006 F1: 0000 0000
380 11:32:46.158087
381 11:32:46.160763 V0: 0000 0000 [0001]
382 11:32:46.160837
383 11:32:46.160894 00: 0007 8000
384 11:32:46.160948
385 11:32:46.164790 01: 0000 0000
386 11:32:46.164875
387 11:32:46.164996 BP: 0C00 0209 [0000]
388 11:32:46.165112
389 11:32:46.167667 G0: 1182 0000
390 11:32:46.167740
391 11:32:46.167796 EC: 0000 0021 [4000]
392 11:32:46.167849
393 11:32:46.170892 S7: 0000 0000 [0000]
394 11:32:46.170966
395 11:32:46.171023 CC: 0000 0000 [0001]
396 11:32:46.171076
397 11:32:46.174838 T0: 0000 0040 [010F]
398 11:32:46.174912
399 11:32:46.174969 Jump to BL
400 11:32:46.175022
401 11:32:46.200503
402 11:32:46.200580
403 11:32:46.207795 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:32:46.211247 ARM64: Exception handlers installed.
405 11:32:46.215232 ARM64: Testing exception
406 11:32:46.218742 ARM64: Done test exception
407 11:32:46.226084 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:32:46.234017 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:32:46.240680 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:32:46.251706 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:32:46.258450 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:32:46.266344 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:32:46.277927 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:32:46.284781 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:32:46.304005 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:32:46.307324 WDT: Last reset was cold boot
417 11:32:46.310971 SPI1(PAD0) initialized at 2873684 Hz
418 11:32:46.314896 SPI5(PAD0) initialized at 992727 Hz
419 11:32:46.318178 VBOOT: Loading verstage.
420 11:32:46.321634 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:32:46.325647 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:32:46.328755 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:32:46.333125 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:32:46.340846 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:32:46.347807 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:32:46.358291 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 11:32:46.358368
428 11:32:46.358427
429 11:32:46.368809 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:32:46.373177 ARM64: Exception handlers installed.
431 11:32:46.373303 ARM64: Testing exception
432 11:32:46.377300 ARM64: Done test exception
433 11:32:46.380551 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:32:46.387342 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:32:46.399983 Probing TPM: . done!
436 11:32:46.400058 TPM ready after 0 ms
437 11:32:46.406137 Connected to device vid:did:rid of 1ae0:0028:00
438 11:32:46.413658 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
439 11:32:46.471472 Initialized TPM device CR50 revision 0
440 11:32:46.476949 tlcl_send_startup: Startup return code is 0
441 11:32:46.486723 TPM: setup succeeded
442 11:32:46.497160 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:32:46.506431 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:32:46.517780 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:32:46.527968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:32:46.530665 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:32:46.534683 in-header: 03 07 00 00 08 00 00 00
448 11:32:46.538713 in-data: aa e4 47 04 13 02 00 00
449 11:32:46.538789 Chrome EC: UHEPI supported
450 11:32:46.546017 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:32:46.549796 in-header: 03 a9 00 00 08 00 00 00
452 11:32:46.553153 in-data: 84 60 60 08 00 00 00 00
453 11:32:46.553255 Phase 1
454 11:32:46.556291 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:32:46.563310 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:32:46.570005 VB2:vb2_check_recovery() Recovery was requested manually
457 11:32:46.572609 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:32:46.576596 Recovery requested (1009000e)
459 11:32:46.584680 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:32:46.590093 tlcl_extend: response is 0
461 11:32:46.598011 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:32:46.603711 tlcl_extend: response is 0
463 11:32:46.610703 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:32:46.630686 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:32:46.637322 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:32:46.637397
467 11:32:46.637456
468 11:32:46.648186 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:32:46.651182 ARM64: Exception handlers installed.
470 11:32:46.654305 ARM64: Testing exception
471 11:32:46.654380 ARM64: Done test exception
472 11:32:46.676989 pmic_efuse_setting: Set efuses in 11 msecs
473 11:32:46.679484 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:32:46.686564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:32:46.690503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:32:46.696124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:32:46.699580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:32:46.707206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:32:46.709585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:32:46.713245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:32:46.720122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:32:46.723518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:32:46.730175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:32:46.733311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:32:46.736356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:32:46.743087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:32:46.749896 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:32:46.752984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:32:46.760233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:32:46.766429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:32:46.773078 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:32:46.776132 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:32:46.782527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:32:46.789152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:32:46.793261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:32:46.799285 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:32:46.806111 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:32:46.809487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:32:46.816045 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:32:46.819913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:32:46.825775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:32:46.828875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:32:46.836212 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:32:46.839089 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:32:46.845787 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:32:46.849097 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:32:46.856294 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:32:46.859519 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:32:46.866940 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:32:46.869857 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:32:46.876787 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:32:46.879756 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:32:46.883514 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:32:46.891071 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:32:46.893406 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:32:46.896316 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:32:46.903402 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:32:46.906099 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:32:46.909342 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:32:46.912799 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:32:46.919914 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:32:46.923225 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:32:46.926239 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:32:46.929663 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:32:46.939541 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:32:46.946287 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:32:46.952898 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:32:46.960204 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:32:46.969946 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:32:46.972624 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:32:46.979358 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:32:46.982666 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:32:46.989607 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x30
534 11:32:46.996404 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:32:46.999721 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:32:47.003019 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:32:47.013796 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 11:32:47.023256 [RTC]rtc_get_frequency_meter,154: input=23, output=950
539 11:32:47.032992 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 11:32:47.042671 [RTC]rtc_get_frequency_meter,154: input=17, output=811
541 11:32:47.052856 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 11:32:47.061295 [RTC]rtc_get_frequency_meter,154: input=16, output=788
543 11:32:47.070982 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 11:32:47.073903 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 11:32:47.081199 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 11:32:47.085015 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:32:47.088659 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:32:47.094486 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:32:47.098444 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:32:47.100984 ADC[4]: Raw value=670800 ID=5
551 11:32:47.101073 ADC[3]: Raw value=212549 ID=1
552 11:32:47.104810 RAM Code: 0x51
553 11:32:47.108244 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:32:47.114847 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:32:47.121349 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 11:32:47.127844 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 11:32:47.131079 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:32:47.135660 in-header: 03 07 00 00 08 00 00 00
559 11:32:47.138318 in-data: aa e4 47 04 13 02 00 00
560 11:32:47.141191 Chrome EC: UHEPI supported
561 11:32:47.147812 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:32:47.151239 in-header: 03 a9 00 00 08 00 00 00
563 11:32:47.154618 in-data: 84 60 60 08 00 00 00 00
564 11:32:47.157996 MRC: failed to locate region type 0.
565 11:32:47.164572 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:32:47.167723 DRAM-K: Running full calibration
567 11:32:47.175076 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 11:32:47.175176 header.status = 0x0
569 11:32:47.178263 header.version = 0x6 (expected: 0x6)
570 11:32:47.181141 header.size = 0xd00 (expected: 0xd00)
571 11:32:47.184935 header.flags = 0x0
572 11:32:47.187775 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:32:47.207118 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:32:47.214236 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:32:47.216697 dram_init: ddr_geometry: 0
576 11:32:47.220611 [EMI] MDL number = 0
577 11:32:47.220700 [EMI] Get MDL freq = 0
578 11:32:47.223453 dram_init: ddr_type: 0
579 11:32:47.223564 is_discrete_lpddr4: 1
580 11:32:47.226754 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:32:47.226830
582 11:32:47.226888
583 11:32:47.230185 [Bian_co] ETT version 0.0.0.1
584 11:32:47.236727 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 11:32:47.236804
586 11:32:47.241206 dramc_set_vcore_voltage set vcore to 650000
587 11:32:47.243661 Read voltage for 800, 4
588 11:32:47.243737 Vio18 = 0
589 11:32:47.243796 Vcore = 650000
590 11:32:47.243850 Vdram = 0
591 11:32:47.247111 Vddq = 0
592 11:32:47.247186 Vmddr = 0
593 11:32:47.250264 dram_init: config_dvfs: 1
594 11:32:47.253964 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:32:47.260715 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:32:47.263615 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 11:32:47.266514 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 11:32:47.270323 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 11:32:47.273590 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 11:32:47.277193 MEM_TYPE=3, freq_sel=18
601 11:32:47.280405 sv_algorithm_assistance_LP4_1600
602 11:32:47.284668 ============ PULL DRAM RESETB DOWN ============
603 11:32:47.287513 ========== PULL DRAM RESETB DOWN end =========
604 11:32:47.293350 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:32:47.297618 ===================================
606 11:32:47.300183 LPDDR4 DRAM CONFIGURATION
607 11:32:47.303728 ===================================
608 11:32:47.303803 EX_ROW_EN[0] = 0x0
609 11:32:47.306860 EX_ROW_EN[1] = 0x0
610 11:32:47.306934 LP4Y_EN = 0x0
611 11:32:47.309832 WORK_FSP = 0x0
612 11:32:47.309907 WL = 0x2
613 11:32:47.313874 RL = 0x2
614 11:32:47.313948 BL = 0x2
615 11:32:47.316459 RPST = 0x0
616 11:32:47.316533 RD_PRE = 0x0
617 11:32:47.320319 WR_PRE = 0x1
618 11:32:47.320394 WR_PST = 0x0
619 11:32:47.323333 DBI_WR = 0x0
620 11:32:47.323408 DBI_RD = 0x0
621 11:32:47.327298 OTF = 0x1
622 11:32:47.330346 ===================================
623 11:32:47.333438 ===================================
624 11:32:47.333514 ANA top config
625 11:32:47.336821 ===================================
626 11:32:47.340109 DLL_ASYNC_EN = 0
627 11:32:47.343183 ALL_SLAVE_EN = 1
628 11:32:47.346802 NEW_RANK_MODE = 1
629 11:32:47.346879 DLL_IDLE_MODE = 1
630 11:32:47.350082 LP45_APHY_COMB_EN = 1
631 11:32:47.353172 TX_ODT_DIS = 1
632 11:32:47.356703 NEW_8X_MODE = 1
633 11:32:47.359815 ===================================
634 11:32:47.363695 ===================================
635 11:32:47.367211 data_rate = 1600
636 11:32:47.367313 CKR = 1
637 11:32:47.370363 DQ_P2S_RATIO = 8
638 11:32:47.373622 ===================================
639 11:32:47.376590 CA_P2S_RATIO = 8
640 11:32:47.380162 DQ_CA_OPEN = 0
641 11:32:47.383452 DQ_SEMI_OPEN = 0
642 11:32:47.386865 CA_SEMI_OPEN = 0
643 11:32:47.386941 CA_FULL_RATE = 0
644 11:32:47.390483 DQ_CKDIV4_EN = 1
645 11:32:47.393955 CA_CKDIV4_EN = 1
646 11:32:47.397079 CA_PREDIV_EN = 0
647 11:32:47.400614 PH8_DLY = 0
648 11:32:47.400690 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:32:47.404753 DQ_AAMCK_DIV = 4
650 11:32:47.406837 CA_AAMCK_DIV = 4
651 11:32:47.410521 CA_ADMCK_DIV = 4
652 11:32:47.413546 DQ_TRACK_CA_EN = 0
653 11:32:47.416910 CA_PICK = 800
654 11:32:47.416986 CA_MCKIO = 800
655 11:32:47.420377 MCKIO_SEMI = 0
656 11:32:47.424266 PLL_FREQ = 3068
657 11:32:47.427073 DQ_UI_PI_RATIO = 32
658 11:32:47.430589 CA_UI_PI_RATIO = 0
659 11:32:47.433944 ===================================
660 11:32:47.436796 ===================================
661 11:32:47.440131 memory_type:LPDDR4
662 11:32:47.440231 GP_NUM : 10
663 11:32:47.443749 SRAM_EN : 1
664 11:32:47.443849 MD32_EN : 0
665 11:32:47.446740 ===================================
666 11:32:47.450701 [ANA_INIT] >>>>>>>>>>>>>>
667 11:32:47.453563 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:32:47.457302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:32:47.460378 ===================================
670 11:32:47.463086 data_rate = 1600,PCW = 0X7600
671 11:32:47.467060 ===================================
672 11:32:47.471251 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:32:47.476400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:32:47.479969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:32:47.486388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:32:47.490017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:32:47.493624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:32:47.493716 [ANA_INIT] flow start
679 11:32:47.496532 [ANA_INIT] PLL >>>>>>>>
680 11:32:47.499906 [ANA_INIT] PLL <<<<<<<<
681 11:32:47.499978 [ANA_INIT] MIDPI >>>>>>>>
682 11:32:47.503322 [ANA_INIT] MIDPI <<<<<<<<
683 11:32:47.506887 [ANA_INIT] DLL >>>>>>>>
684 11:32:47.506975 [ANA_INIT] flow end
685 11:32:47.513565 ============ LP4 DIFF to SE enter ============
686 11:32:47.516763 ============ LP4 DIFF to SE exit ============
687 11:32:47.516852 [ANA_INIT] <<<<<<<<<<<<<
688 11:32:47.520342 [Flow] Enable top DCM control >>>>>
689 11:32:47.523148 [Flow] Enable top DCM control <<<<<
690 11:32:47.527010 Enable DLL master slave shuffle
691 11:32:47.533623 ==============================================================
692 11:32:47.536770 Gating Mode config
693 11:32:47.540418 ==============================================================
694 11:32:47.543038 Config description:
695 11:32:47.553091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:32:47.559870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:32:47.563425 SELPH_MODE 0: By rank 1: By Phase
698 11:32:47.570303 ==============================================================
699 11:32:47.573434 GAT_TRACK_EN = 1
700 11:32:47.576414 RX_GATING_MODE = 2
701 11:32:47.576490 RX_GATING_TRACK_MODE = 2
702 11:32:47.580327 SELPH_MODE = 1
703 11:32:47.583211 PICG_EARLY_EN = 1
704 11:32:47.586495 VALID_LAT_VALUE = 1
705 11:32:47.593364 ==============================================================
706 11:32:47.596519 Enter into Gating configuration >>>>
707 11:32:47.600260 Exit from Gating configuration <<<<
708 11:32:47.603284 Enter into DVFS_PRE_config >>>>>
709 11:32:47.613626 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:32:47.617186 Exit from DVFS_PRE_config <<<<<
711 11:32:47.619801 Enter into PICG configuration >>>>
712 11:32:47.623759 Exit from PICG configuration <<<<
713 11:32:47.627097 [RX_INPUT] configuration >>>>>
714 11:32:47.630037 [RX_INPUT] configuration <<<<<
715 11:32:47.633924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:32:47.640803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:32:47.646578 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:32:47.650172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:32:47.657423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:32:47.663941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:32:47.667483 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:32:47.671833 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:32:47.674972 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:32:47.681689 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:32:47.686203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:32:47.689983 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:32:47.693142 ===================================
728 11:32:47.693259 LPDDR4 DRAM CONFIGURATION
729 11:32:47.696926 ===================================
730 11:32:47.699743 EX_ROW_EN[0] = 0x0
731 11:32:47.703602 EX_ROW_EN[1] = 0x0
732 11:32:47.703673 LP4Y_EN = 0x0
733 11:32:47.706849 WORK_FSP = 0x0
734 11:32:47.706916 WL = 0x2
735 11:32:47.710440 RL = 0x2
736 11:32:47.710506 BL = 0x2
737 11:32:47.713955 RPST = 0x0
738 11:32:47.714030 RD_PRE = 0x0
739 11:32:47.716446 WR_PRE = 0x1
740 11:32:47.716521 WR_PST = 0x0
741 11:32:47.720033 DBI_WR = 0x0
742 11:32:47.720108 DBI_RD = 0x0
743 11:32:47.723830 OTF = 0x1
744 11:32:47.726889 ===================================
745 11:32:47.730072 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:32:47.733909 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:32:47.736468 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:32:47.740525 ===================================
749 11:32:47.743500 LPDDR4 DRAM CONFIGURATION
750 11:32:47.746873 ===================================
751 11:32:47.749738 EX_ROW_EN[0] = 0x10
752 11:32:47.749814 EX_ROW_EN[1] = 0x0
753 11:32:47.753907 LP4Y_EN = 0x0
754 11:32:47.753982 WORK_FSP = 0x0
755 11:32:47.756892 WL = 0x2
756 11:32:47.756967 RL = 0x2
757 11:32:47.759864 BL = 0x2
758 11:32:47.759939 RPST = 0x0
759 11:32:47.763847 RD_PRE = 0x0
760 11:32:47.763922 WR_PRE = 0x1
761 11:32:47.767083 WR_PST = 0x0
762 11:32:47.770174 DBI_WR = 0x0
763 11:32:47.770250 DBI_RD = 0x0
764 11:32:47.773344 OTF = 0x1
765 11:32:47.777170 ===================================
766 11:32:47.779915 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:32:47.785299 nWR fixed to 40
768 11:32:47.788621 [ModeRegInit_LP4] CH0 RK0
769 11:32:47.788696 [ModeRegInit_LP4] CH0 RK1
770 11:32:47.791644 [ModeRegInit_LP4] CH1 RK0
771 11:32:47.795922 [ModeRegInit_LP4] CH1 RK1
772 11:32:47.795997 match AC timing 12
773 11:32:47.802446 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 11:32:47.805386 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:32:47.808840 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:32:47.815247 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:32:47.818599 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:32:47.818674 [EMI DOE] emi_dcm 0
779 11:32:47.825406 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:32:47.825483 ==
781 11:32:47.828650 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:32:47.831980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 11:32:47.832057 ==
784 11:32:47.838617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:32:47.845431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:32:47.852642 [CA 0] Center 37 (7~68) winsize 62
787 11:32:47.855885 [CA 1] Center 37 (7~68) winsize 62
788 11:32:47.859169 [CA 2] Center 35 (5~66) winsize 62
789 11:32:47.862539 [CA 3] Center 35 (5~66) winsize 62
790 11:32:47.865770 [CA 4] Center 34 (3~65) winsize 63
791 11:32:47.869925 [CA 5] Center 33 (3~64) winsize 62
792 11:32:47.870001
793 11:32:47.873798 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:32:47.873874
795 11:32:47.876815 [CATrainingPosCal] consider 1 rank data
796 11:32:47.879975 u2DelayCellTimex100 = 270/100 ps
797 11:32:47.883434 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:32:47.886769 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 11:32:47.890143 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 11:32:47.893389 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
801 11:32:47.897068 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 11:32:47.903693 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:32:47.903769
804 11:32:47.906679 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:32:47.906755
806 11:32:47.909990 [CBTSetCACLKResult] CA Dly = 33
807 11:32:47.910066 CS Dly: 5 (0~36)
808 11:32:47.910125 ==
809 11:32:47.913355 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:32:47.916699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 11:32:47.919994 ==
812 11:32:47.923363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:32:47.930339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:32:47.938168 [CA 0] Center 37 (6~68) winsize 63
815 11:32:47.941768 [CA 1] Center 37 (6~68) winsize 63
816 11:32:47.945434 [CA 2] Center 35 (5~66) winsize 62
817 11:32:47.948459 [CA 3] Center 34 (4~65) winsize 62
818 11:32:47.951591 [CA 4] Center 33 (3~64) winsize 62
819 11:32:47.956050 [CA 5] Center 33 (3~64) winsize 62
820 11:32:47.956125
821 11:32:47.958411 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:32:47.958486
823 11:32:47.961904 [CATrainingPosCal] consider 2 rank data
824 11:32:47.965527 u2DelayCellTimex100 = 270/100 ps
825 11:32:47.968577 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:32:47.971823 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:32:47.979005 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 11:32:47.982841 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
829 11:32:47.985675 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:32:47.988839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:32:47.988914
832 11:32:47.991985 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:32:47.992061
834 11:32:47.995364 [CBTSetCACLKResult] CA Dly = 33
835 11:32:47.995440 CS Dly: 6 (0~38)
836 11:32:47.995499
837 11:32:47.999341 ----->DramcWriteLeveling(PI) begin...
838 11:32:48.002031 ==
839 11:32:48.005340 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:32:48.008860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 11:32:48.008937 ==
842 11:32:48.012292 Write leveling (Byte 0): 31 => 31
843 11:32:48.014878 Write leveling (Byte 1): 30 => 30
844 11:32:48.018783 DramcWriteLeveling(PI) end<-----
845 11:32:48.018858
846 11:32:48.018917 ==
847 11:32:48.021603 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:32:48.025179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 11:32:48.025297 ==
850 11:32:48.028228 [Gating] SW mode calibration
851 11:32:48.035509 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:32:48.041515 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:32:48.045270 0 6 0 | B1->B0 | 3232 3232 | 1 0 | (1 0) (0 0)
854 11:32:48.048308 0 6 4 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
855 11:32:48.052095 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:32:48.058337 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:32:48.061551 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:32:48.065376 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:32:48.071730 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:32:48.074705 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:32:48.078347 0 7 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
862 11:32:48.084793 0 7 4 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
863 11:32:48.088302 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 11:32:48.091171 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 11:32:48.098101 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 11:32:48.101330 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 11:32:48.104434 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:32:48.111310 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:32:48.114659 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 11:32:48.117990 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 11:32:48.124586 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 11:32:48.127976 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 11:32:48.131363 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 11:32:48.137691 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 11:32:48.141232 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:32:48.145159 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:32:48.151296 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:32:48.155007 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:32:48.158092 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:32:48.164538 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:32:48.167856 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:32:48.171442 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:32:48.174940 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:32:48.181387 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:32:48.184670 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 11:32:48.188429 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
887 11:32:48.191586 Total UI for P1: 0, mck2ui 16
888 11:32:48.194739 best dqsien dly found for B0: ( 0, 10, 0)
889 11:32:48.201441 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 11:32:48.205099 Total UI for P1: 0, mck2ui 16
891 11:32:48.207736 best dqsien dly found for B1: ( 0, 10, 2)
892 11:32:48.211257 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
893 11:32:48.214750 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
894 11:32:48.214813
895 11:32:48.219132 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 11:32:48.221739 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
897 11:32:48.225184 [Gating] SW calibration Done
898 11:32:48.225263 ==
899 11:32:48.227711 Dram Type= 6, Freq= 0, CH_0, rank 0
900 11:32:48.231550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 11:32:48.231626 ==
902 11:32:48.235265 RX Vref Scan: 0
903 11:32:48.235340
904 11:32:48.235398 RX Vref 0 -> 0, step: 1
905 11:32:48.235452
906 11:32:48.237945 RX Delay -130 -> 252, step: 16
907 11:32:48.245873 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
908 11:32:48.248528 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
909 11:32:48.252045 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
910 11:32:48.254795 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
911 11:32:48.258897 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
912 11:32:48.262508 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
913 11:32:48.265238 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
914 11:32:48.271529 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
915 11:32:48.275509 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
916 11:32:48.278825 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
917 11:32:48.281596 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
918 11:32:48.285074 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
919 11:32:48.291980 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
920 11:32:48.294978 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
921 11:32:48.298455 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
922 11:32:48.301665 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
923 11:32:48.301739 ==
924 11:32:48.305352 Dram Type= 6, Freq= 0, CH_0, rank 0
925 11:32:48.312747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
926 11:32:48.312848 ==
927 11:32:48.312939 DQS Delay:
928 11:32:48.315298 DQS0 = 0, DQS1 = 0
929 11:32:48.315376 DQM Delay:
930 11:32:48.315450 DQM0 = 83, DQM1 = 74
931 11:32:48.318701 DQ Delay:
932 11:32:48.321697 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
933 11:32:48.325819 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
934 11:32:48.328754 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
935 11:32:48.331941 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
936 11:32:48.332009
937 11:32:48.332107
938 11:32:48.332175 ==
939 11:32:48.335287 Dram Type= 6, Freq= 0, CH_0, rank 0
940 11:32:48.338685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
941 11:32:48.338752 ==
942 11:32:48.338823
943 11:32:48.338916
944 11:32:48.341903 TX Vref Scan disable
945 11:32:48.341969 == TX Byte 0 ==
946 11:32:48.348400 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
947 11:32:48.351838 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
948 11:32:48.351913 == TX Byte 1 ==
949 11:32:48.358918 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 11:32:48.361537 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 11:32:48.361613 ==
952 11:32:48.365070 Dram Type= 6, Freq= 0, CH_0, rank 0
953 11:32:48.368383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
954 11:32:48.368465 ==
955 11:32:48.383029 TX Vref=22, minBit 0, minWin=27, winSum=444
956 11:32:48.386142 TX Vref=24, minBit 3, minWin=27, winSum=450
957 11:32:48.389094 TX Vref=26, minBit 2, minWin=28, winSum=456
958 11:32:48.393748 TX Vref=28, minBit 4, minWin=28, winSum=458
959 11:32:48.396742 TX Vref=30, minBit 0, minWin=28, winSum=457
960 11:32:48.399153 TX Vref=32, minBit 5, minWin=27, winSum=455
961 11:32:48.405852 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
962 11:32:48.405923
963 11:32:48.409307 Final TX Range 1 Vref 28
964 11:32:48.409383
965 11:32:48.409440 ==
966 11:32:48.412855 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:32:48.415775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
968 11:32:48.415851 ==
969 11:32:48.415909
970 11:32:48.419300
971 11:32:48.419368 TX Vref Scan disable
972 11:32:48.422494 == TX Byte 0 ==
973 11:32:48.426521 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
974 11:32:48.428857 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
975 11:32:48.432821 == TX Byte 1 ==
976 11:32:48.436142 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 11:32:48.439373 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 11:32:48.442585
979 11:32:48.442658 [DATLAT]
980 11:32:48.442716 Freq=800, CH0 RK0
981 11:32:48.442771
982 11:32:48.445889 DATLAT Default: 0xa
983 11:32:48.445964 0, 0xFFFF, sum = 0
984 11:32:48.449291 1, 0xFFFF, sum = 0
985 11:32:48.449368 2, 0xFFFF, sum = 0
986 11:32:48.452437 3, 0xFFFF, sum = 0
987 11:32:48.452512 4, 0xFFFF, sum = 0
988 11:32:48.455939 5, 0xFFFF, sum = 0
989 11:32:48.459627 6, 0xFFFF, sum = 0
990 11:32:48.459703 7, 0xFFFF, sum = 0
991 11:32:48.459763 8, 0x0, sum = 1
992 11:32:48.462406 9, 0x0, sum = 2
993 11:32:48.462483 10, 0x0, sum = 3
994 11:32:48.466572 11, 0x0, sum = 4
995 11:32:48.466648 best_step = 9
996 11:32:48.466707
997 11:32:48.466759 ==
998 11:32:48.469811 Dram Type= 6, Freq= 0, CH_0, rank 0
999 11:32:48.475969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1000 11:32:48.476068 ==
1001 11:32:48.476159 RX Vref Scan: 1
1002 11:32:48.476251
1003 11:32:48.479436 Set Vref Range= 32 -> 127
1004 11:32:48.479533
1005 11:32:48.482430 RX Vref 32 -> 127, step: 1
1006 11:32:48.482499
1007 11:32:48.487050 RX Delay -111 -> 252, step: 8
1008 11:32:48.487118
1009 11:32:48.487192 Set Vref, RX VrefLevel [Byte0]: 32
1010 11:32:48.489598 [Byte1]: 32
1011 11:32:48.494322
1012 11:32:48.494397 Set Vref, RX VrefLevel [Byte0]: 33
1013 11:32:48.496688 [Byte1]: 33
1014 11:32:48.501162
1015 11:32:48.501290 Set Vref, RX VrefLevel [Byte0]: 34
1016 11:32:48.504309 [Byte1]: 34
1017 11:32:48.509381
1018 11:32:48.509457 Set Vref, RX VrefLevel [Byte0]: 35
1019 11:32:48.512120 [Byte1]: 35
1020 11:32:48.516638
1021 11:32:48.516738 Set Vref, RX VrefLevel [Byte0]: 36
1022 11:32:48.519856 [Byte1]: 36
1023 11:32:48.523913
1024 11:32:48.524005 Set Vref, RX VrefLevel [Byte0]: 37
1025 11:32:48.527463 [Byte1]: 37
1026 11:32:48.531934
1027 11:32:48.532069 Set Vref, RX VrefLevel [Byte0]: 38
1028 11:32:48.535133 [Byte1]: 38
1029 11:32:48.539603
1030 11:32:48.539702 Set Vref, RX VrefLevel [Byte0]: 39
1031 11:32:48.542500 [Byte1]: 39
1032 11:32:48.546933
1033 11:32:48.547029 Set Vref, RX VrefLevel [Byte0]: 40
1034 11:32:48.550790 [Byte1]: 40
1035 11:32:48.554427
1036 11:32:48.554498 Set Vref, RX VrefLevel [Byte0]: 41
1037 11:32:48.558220 [Byte1]: 41
1038 11:32:48.562952
1039 11:32:48.563023 Set Vref, RX VrefLevel [Byte0]: 42
1040 11:32:48.565496 [Byte1]: 42
1041 11:32:48.570431
1042 11:32:48.570500 Set Vref, RX VrefLevel [Byte0]: 43
1043 11:32:48.573046 [Byte1]: 43
1044 11:32:48.577674
1045 11:32:48.577742 Set Vref, RX VrefLevel [Byte0]: 44
1046 11:32:48.580939 [Byte1]: 44
1047 11:32:48.585265
1048 11:32:48.585333 Set Vref, RX VrefLevel [Byte0]: 45
1049 11:32:48.588723 [Byte1]: 45
1050 11:32:48.592618
1051 11:32:48.592685 Set Vref, RX VrefLevel [Byte0]: 46
1052 11:32:48.596093 [Byte1]: 46
1053 11:32:48.600287
1054 11:32:48.600350 Set Vref, RX VrefLevel [Byte0]: 47
1055 11:32:48.603808 [Byte1]: 47
1056 11:32:48.607995
1057 11:32:48.608063 Set Vref, RX VrefLevel [Byte0]: 48
1058 11:32:48.611219 [Byte1]: 48
1059 11:32:48.615775
1060 11:32:48.615844 Set Vref, RX VrefLevel [Byte0]: 49
1061 11:32:48.619661 [Byte1]: 49
1062 11:32:48.623788
1063 11:32:48.623854 Set Vref, RX VrefLevel [Byte0]: 50
1064 11:32:48.626779 [Byte1]: 50
1065 11:32:48.631676
1066 11:32:48.631739 Set Vref, RX VrefLevel [Byte0]: 51
1067 11:32:48.634461 [Byte1]: 51
1068 11:32:48.638944
1069 11:32:48.639032 Set Vref, RX VrefLevel [Byte0]: 52
1070 11:32:48.641736 [Byte1]: 52
1071 11:32:48.646567
1072 11:32:48.646654 Set Vref, RX VrefLevel [Byte0]: 53
1073 11:32:48.650557 [Byte1]: 53
1074 11:32:48.654132
1075 11:32:48.654197 Set Vref, RX VrefLevel [Byte0]: 54
1076 11:32:48.657316 [Byte1]: 54
1077 11:32:48.661649
1078 11:32:48.661717 Set Vref, RX VrefLevel [Byte0]: 55
1079 11:32:48.665458 [Byte1]: 55
1080 11:32:48.669374
1081 11:32:48.669434 Set Vref, RX VrefLevel [Byte0]: 56
1082 11:32:48.673102 [Byte1]: 56
1083 11:32:48.677063
1084 11:32:48.677149 Set Vref, RX VrefLevel [Byte0]: 57
1085 11:32:48.680133 [Byte1]: 57
1086 11:32:48.684541
1087 11:32:48.684601 Set Vref, RX VrefLevel [Byte0]: 58
1088 11:32:48.687941 [Byte1]: 58
1089 11:32:48.693135
1090 11:32:48.693220 Set Vref, RX VrefLevel [Byte0]: 59
1091 11:32:48.696163 [Byte1]: 59
1092 11:32:48.700216
1093 11:32:48.700277 Set Vref, RX VrefLevel [Byte0]: 60
1094 11:32:48.703889 [Byte1]: 60
1095 11:32:48.707859
1096 11:32:48.707922 Set Vref, RX VrefLevel [Byte0]: 61
1097 11:32:48.710899 [Byte1]: 61
1098 11:32:48.715585
1099 11:32:48.715650 Set Vref, RX VrefLevel [Byte0]: 62
1100 11:32:48.718484 [Byte1]: 62
1101 11:32:48.722478
1102 11:32:48.722538 Set Vref, RX VrefLevel [Byte0]: 63
1103 11:32:48.725845 [Byte1]: 63
1104 11:32:48.730560
1105 11:32:48.730621 Set Vref, RX VrefLevel [Byte0]: 64
1106 11:32:48.734043 [Byte1]: 64
1107 11:32:48.738352
1108 11:32:48.738438 Set Vref, RX VrefLevel [Byte0]: 65
1109 11:32:48.741982 [Byte1]: 65
1110 11:32:48.745462
1111 11:32:48.745531 Set Vref, RX VrefLevel [Byte0]: 66
1112 11:32:48.748846 [Byte1]: 66
1113 11:32:48.753251
1114 11:32:48.753322 Set Vref, RX VrefLevel [Byte0]: 67
1115 11:32:48.756657 [Byte1]: 67
1116 11:32:48.761053
1117 11:32:48.761144 Set Vref, RX VrefLevel [Byte0]: 68
1118 11:32:48.765099 [Byte1]: 68
1119 11:32:48.768859
1120 11:32:48.768925 Set Vref, RX VrefLevel [Byte0]: 69
1121 11:32:48.771804 [Byte1]: 69
1122 11:32:48.776628
1123 11:32:48.776691 Set Vref, RX VrefLevel [Byte0]: 70
1124 11:32:48.779739 [Byte1]: 70
1125 11:32:48.784100
1126 11:32:48.784159 Set Vref, RX VrefLevel [Byte0]: 71
1127 11:32:48.787077 [Byte1]: 71
1128 11:32:48.791410
1129 11:32:48.791469 Set Vref, RX VrefLevel [Byte0]: 72
1130 11:32:48.795040 [Byte1]: 72
1131 11:32:48.799572
1132 11:32:48.799631 Set Vref, RX VrefLevel [Byte0]: 73
1133 11:32:48.802663 [Byte1]: 73
1134 11:32:48.806741
1135 11:32:48.806799 Set Vref, RX VrefLevel [Byte0]: 74
1136 11:32:48.810489 [Byte1]: 74
1137 11:32:48.814355
1138 11:32:48.814418 Set Vref, RX VrefLevel [Byte0]: 75
1139 11:32:48.817925 [Byte1]: 75
1140 11:32:48.822004
1141 11:32:48.822065 Set Vref, RX VrefLevel [Byte0]: 76
1142 11:32:48.825770 [Byte1]: 76
1143 11:32:48.830389
1144 11:32:48.830473 Set Vref, RX VrefLevel [Byte0]: 77
1145 11:32:48.833151 [Byte1]: 77
1146 11:32:48.837458
1147 11:32:48.837520 Final RX Vref Byte 0 = 56 to rank0
1148 11:32:48.840922 Final RX Vref Byte 1 = 51 to rank0
1149 11:32:48.844227 Final RX Vref Byte 0 = 56 to rank1
1150 11:32:48.847516 Final RX Vref Byte 1 = 51 to rank1==
1151 11:32:48.850968 Dram Type= 6, Freq= 0, CH_0, rank 0
1152 11:32:48.857748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1153 11:32:48.857820 ==
1154 11:32:48.857877 DQS Delay:
1155 11:32:48.857929 DQS0 = 0, DQS1 = 0
1156 11:32:48.860567 DQM Delay:
1157 11:32:48.860627 DQM0 = 83, DQM1 = 73
1158 11:32:48.864083 DQ Delay:
1159 11:32:48.867126 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1160 11:32:48.870936 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1161 11:32:48.873775 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1162 11:32:48.877122 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1163 11:32:48.877209
1164 11:32:48.877305
1165 11:32:48.884115 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1166 11:32:48.887387 CH0 RK0: MR19=606, MR18=3636
1167 11:32:48.894476 CH0_RK0: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1168 11:32:48.894570
1169 11:32:48.897578 ----->DramcWriteLeveling(PI) begin...
1170 11:32:48.897642 ==
1171 11:32:48.900423 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 11:32:48.904629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1173 11:32:48.904691 ==
1174 11:32:48.907579 Write leveling (Byte 0): 30 => 30
1175 11:32:48.910620 Write leveling (Byte 1): 29 => 29
1176 11:32:48.913798 DramcWriteLeveling(PI) end<-----
1177 11:32:48.913861
1178 11:32:48.913915 ==
1179 11:32:48.917679 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 11:32:48.920901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1181 11:32:48.920962 ==
1182 11:32:48.924141 [Gating] SW mode calibration
1183 11:32:48.930482 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1184 11:32:48.937342 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1185 11:32:48.941288 0 6 0 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1186 11:32:48.943942 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:32:48.951066 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:32:48.953712 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:32:48.957101 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:32:48.964032 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:32:48.967325 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:32:48.971138 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:32:48.977668 0 7 0 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (0 0)
1194 11:32:48.981092 0 7 4 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
1195 11:32:48.983703 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:32:48.990566 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:32:48.994140 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:32:48.997389 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:32:49.004041 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:32:49.007121 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:32:49.010727 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:32:49.014206 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 11:32:49.021059 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:32:49.024008 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:32:49.027832 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:32:49.034216 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:32:49.037340 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:32:49.040773 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:32:49.047461 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:32:49.050529 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:32:49.053620 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:32:49.060318 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:32:49.063790 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:32:49.067428 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:32:49.073790 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:32:49.077257 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:32:49.121648 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 11:32:49.121903 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 11:32:49.121966 Total UI for P1: 0, mck2ui 16
1220 11:32:49.122568 best dqsien dly found for B0: ( 0, 10, 0)
1221 11:32:49.122630 Total UI for P1: 0, mck2ui 16
1222 11:32:49.122862 best dqsien dly found for B1: ( 0, 10, 2)
1223 11:32:49.123510 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1224 11:32:49.123567 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1225 11:32:49.123621
1226 11:32:49.123852 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1227 11:32:49.124206 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1228 11:32:49.124261 [Gating] SW calibration Done
1229 11:32:49.124313 ==
1230 11:32:49.124829 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 11:32:49.135129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1232 11:32:49.135192 ==
1233 11:32:49.135245 RX Vref Scan: 0
1234 11:32:49.135295
1235 11:32:49.135345 RX Vref 0 -> 0, step: 1
1236 11:32:49.135398
1237 11:32:49.135633 RX Delay -130 -> 252, step: 16
1238 11:32:49.137999 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1239 11:32:49.138057 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1240 11:32:49.141475 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1241 11:32:49.148517 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1242 11:32:49.151413 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1243 11:32:49.154840 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1244 11:32:49.158488 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1245 11:32:49.161548 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1246 11:32:49.168261 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1247 11:32:49.171607 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1248 11:32:49.175343 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 11:32:49.178138 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1250 11:32:49.181027 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1251 11:32:49.188170 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1252 11:32:49.191412 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1253 11:32:49.194941 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1254 11:32:49.195003 ==
1255 11:32:49.197930 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 11:32:49.201002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 11:32:49.201062 ==
1258 11:32:49.204544 DQS Delay:
1259 11:32:49.204607 DQS0 = 0, DQS1 = 0
1260 11:32:49.208167 DQM Delay:
1261 11:32:49.208232 DQM0 = 82, DQM1 = 72
1262 11:32:49.208286 DQ Delay:
1263 11:32:49.211132 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1264 11:32:49.214724 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1265 11:32:49.218378 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1266 11:32:49.221134 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1267 11:32:49.221194
1268 11:32:49.221287
1269 11:32:49.224762 ==
1270 11:32:49.224817 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 11:32:49.231683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1272 11:32:49.231745 ==
1273 11:32:49.231796
1274 11:32:49.231845
1275 11:32:49.234643 TX Vref Scan disable
1276 11:32:49.234703 == TX Byte 0 ==
1277 11:32:49.238101 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1278 11:32:49.244897 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1279 11:32:49.244957 == TX Byte 1 ==
1280 11:32:49.248680 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1281 11:32:49.254663 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1282 11:32:49.254730 ==
1283 11:32:49.258531 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 11:32:49.261495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1285 11:32:49.261559 ==
1286 11:32:49.275035 TX Vref=22, minBit 0, minWin=27, winSum=450
1287 11:32:49.278588 TX Vref=24, minBit 2, minWin=28, winSum=453
1288 11:32:49.281076 TX Vref=26, minBit 2, minWin=28, winSum=455
1289 11:32:49.284852 TX Vref=28, minBit 2, minWin=28, winSum=457
1290 11:32:49.288091 TX Vref=30, minBit 2, minWin=28, winSum=459
1291 11:32:49.291128 TX Vref=32, minBit 2, minWin=28, winSum=459
1292 11:32:49.297697 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1293 11:32:49.297766
1294 11:32:49.300999 Final TX Range 1 Vref 30
1295 11:32:49.301094
1296 11:32:49.301178 ==
1297 11:32:49.304078 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 11:32:49.307815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1299 11:32:49.307883 ==
1300 11:32:49.307936
1301 11:32:49.310765
1302 11:32:49.310828 TX Vref Scan disable
1303 11:32:49.314063 == TX Byte 0 ==
1304 11:32:49.317903 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1305 11:32:49.323898 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1306 11:32:49.323962 == TX Byte 1 ==
1307 11:32:49.327390 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1308 11:32:49.334206 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1309 11:32:49.334297
1310 11:32:49.334410 [DATLAT]
1311 11:32:49.334463 Freq=800, CH0 RK1
1312 11:32:49.334517
1313 11:32:49.337776 DATLAT Default: 0x9
1314 11:32:49.337833 0, 0xFFFF, sum = 0
1315 11:32:49.341223 1, 0xFFFF, sum = 0
1316 11:32:49.341319 2, 0xFFFF, sum = 0
1317 11:32:49.344974 3, 0xFFFF, sum = 0
1318 11:32:49.345033 4, 0xFFFF, sum = 0
1319 11:32:49.348350 5, 0xFFFF, sum = 0
1320 11:32:49.351358 6, 0xFFFF, sum = 0
1321 11:32:49.351429 7, 0xFFFF, sum = 0
1322 11:32:49.351489 8, 0x0, sum = 1
1323 11:32:49.355064 9, 0x0, sum = 2
1324 11:32:49.355127 10, 0x0, sum = 3
1325 11:32:49.358116 11, 0x0, sum = 4
1326 11:32:49.358177 best_step = 9
1327 11:32:49.358228
1328 11:32:49.358277 ==
1329 11:32:49.361509 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 11:32:49.367438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1331 11:32:49.367508 ==
1332 11:32:49.367564 RX Vref Scan: 0
1333 11:32:49.367616
1334 11:32:49.371438 RX Vref 0 -> 0, step: 1
1335 11:32:49.371500
1336 11:32:49.374062 RX Delay -111 -> 252, step: 8
1337 11:32:49.377297 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1338 11:32:49.380925 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1339 11:32:49.387561 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1340 11:32:49.390508 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1341 11:32:49.394565 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1342 11:32:49.397542 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1343 11:32:49.401112 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1344 11:32:49.407647 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1345 11:32:49.410644 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1346 11:32:49.413994 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1347 11:32:49.418225 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1348 11:32:49.420814 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1349 11:32:49.428611 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1350 11:32:49.430901 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1351 11:32:49.433923 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1352 11:32:49.437711 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1353 11:32:49.437786 ==
1354 11:32:49.440777 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 11:32:49.444581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1356 11:32:49.447696 ==
1357 11:32:49.447765 DQS Delay:
1358 11:32:49.447821 DQS0 = 0, DQS1 = 0
1359 11:32:49.451138 DQM Delay:
1360 11:32:49.451205 DQM0 = 87, DQM1 = 73
1361 11:32:49.454053 DQ Delay:
1362 11:32:49.458100 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1363 11:32:49.458170 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 11:32:49.460576 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =64
1365 11:32:49.464696 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1366 11:32:49.467366
1367 11:32:49.467430
1368 11:32:49.474339 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1369 11:32:49.477688 CH0 RK1: MR19=606, MR18=4D4D
1370 11:32:49.484212 CH0_RK1: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1371 11:32:49.487425 [RxdqsGatingPostProcess] freq 800
1372 11:32:49.490680 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 11:32:49.493693 Pre-setting of DQS Precalculation
1374 11:32:49.497083 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1375 11:32:49.501027 ==
1376 11:32:49.504003 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 11:32:49.507701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1378 11:32:49.507770 ==
1379 11:32:49.510723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 11:32:49.517355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 11:32:49.527504 [CA 0] Center 37 (6~68) winsize 63
1382 11:32:49.530424 [CA 1] Center 37 (6~68) winsize 63
1383 11:32:49.533829 [CA 2] Center 34 (4~65) winsize 62
1384 11:32:49.537824 [CA 3] Center 34 (4~65) winsize 62
1385 11:32:49.540865 [CA 4] Center 33 (3~64) winsize 62
1386 11:32:49.544341 [CA 5] Center 33 (3~64) winsize 62
1387 11:32:49.544410
1388 11:32:49.548719 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1389 11:32:49.548786
1390 11:32:49.550986 [CATrainingPosCal] consider 1 rank data
1391 11:32:49.553920 u2DelayCellTimex100 = 270/100 ps
1392 11:32:49.557975 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1393 11:32:49.560633 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1394 11:32:49.564328 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 11:32:49.570551 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 11:32:49.574505 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 11:32:49.577533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 11:32:49.577599
1399 11:32:49.580776 CA PerBit enable=1, Macro0, CA PI delay=33
1400 11:32:49.580868
1401 11:32:49.583826 [CBTSetCACLKResult] CA Dly = 33
1402 11:32:49.583890 CS Dly: 4 (0~35)
1403 11:32:49.583943 ==
1404 11:32:49.587299 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 11:32:49.594052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1406 11:32:49.594117 ==
1407 11:32:49.597047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 11:32:49.603449 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 11:32:49.612667 [CA 0] Center 37 (6~68) winsize 63
1410 11:32:49.616392 [CA 1] Center 37 (6~68) winsize 63
1411 11:32:49.619345 [CA 2] Center 34 (4~65) winsize 62
1412 11:32:49.623669 [CA 3] Center 34 (3~65) winsize 63
1413 11:32:49.627073 [CA 4] Center 33 (3~64) winsize 62
1414 11:32:49.629554 [CA 5] Center 33 (3~64) winsize 62
1415 11:32:49.629619
1416 11:32:49.632957 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 11:32:49.633019
1418 11:32:49.636737 [CATrainingPosCal] consider 2 rank data
1419 11:32:49.639514 u2DelayCellTimex100 = 270/100 ps
1420 11:32:49.642997 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1421 11:32:49.646132 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1422 11:32:49.652977 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 11:32:49.655970 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 11:32:49.659556 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 11:32:49.663256 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 11:32:49.663322
1427 11:32:49.666207 CA PerBit enable=1, Macro0, CA PI delay=33
1428 11:32:49.666273
1429 11:32:49.670253 [CBTSetCACLKResult] CA Dly = 33
1430 11:32:49.670315 CS Dly: 4 (0~36)
1431 11:32:49.670373
1432 11:32:49.673711 ----->DramcWriteLeveling(PI) begin...
1433 11:32:49.676990 ==
1434 11:32:49.679235 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 11:32:49.683104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1436 11:32:49.683177 ==
1437 11:32:49.685800 Write leveling (Byte 0): 25 => 25
1438 11:32:49.689047 Write leveling (Byte 1): 24 => 24
1439 11:32:49.692946 DramcWriteLeveling(PI) end<-----
1440 11:32:49.693040
1441 11:32:49.693123 ==
1442 11:32:49.696382 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:32:49.699391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1444 11:32:49.699461 ==
1445 11:32:49.702549 [Gating] SW mode calibration
1446 11:32:49.709035 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 11:32:49.716196 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 11:32:49.719353 0 6 0 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
1449 11:32:49.722357 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:32:49.725920 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:32:49.732113 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:32:49.735677 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:32:49.739231 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:32:49.746222 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:32:49.748723 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1456 11:32:49.752554 0 7 0 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (1 1)
1457 11:32:49.759906 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1458 11:32:49.762038 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1459 11:32:49.766030 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1460 11:32:49.772431 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1461 11:32:49.775484 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1462 11:32:49.778720 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1463 11:32:49.786000 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1464 11:32:49.788948 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1465 11:32:49.791952 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 11:32:49.799389 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 11:32:49.802013 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 11:32:49.805804 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 11:32:49.812028 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 11:32:49.815592 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 11:32:49.818831 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 11:32:49.825719 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1473 11:32:49.828560 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1474 11:32:49.832298 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1475 11:32:49.839379 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1476 11:32:49.842092 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1477 11:32:49.845807 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1478 11:32:49.849029 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1479 11:32:49.855405 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1480 11:32:49.858903 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1481 11:32:49.862804 Total UI for P1: 0, mck2ui 16
1482 11:32:49.866812 best dqsien dly found for B0: ( 0, 9, 28)
1483 11:32:49.868698 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 11:32:49.872460 Total UI for P1: 0, mck2ui 16
1485 11:32:49.875647 best dqsien dly found for B1: ( 0, 10, 0)
1486 11:32:49.878823 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1487 11:32:49.882712 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1488 11:32:49.882805
1489 11:32:49.889106 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1490 11:32:49.892276 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1491 11:32:49.895823 [Gating] SW calibration Done
1492 11:32:49.895896 ==
1493 11:32:49.898749 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 11:32:49.902756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1495 11:32:49.902832 ==
1496 11:32:49.902891 RX Vref Scan: 0
1497 11:32:49.902950
1498 11:32:49.906281 RX Vref 0 -> 0, step: 1
1499 11:32:49.906345
1500 11:32:49.908995 RX Delay -130 -> 252, step: 16
1501 11:32:49.912393 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1502 11:32:49.915439 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1503 11:32:49.922467 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1504 11:32:49.925303 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1505 11:32:49.928741 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1506 11:32:49.932340 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1507 11:32:49.935487 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1508 11:32:49.942088 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1509 11:32:49.945505 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1510 11:32:49.948752 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1511 11:32:49.952005 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1512 11:32:49.955841 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1513 11:32:49.962164 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1514 11:32:49.965340 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1515 11:32:49.969597 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1516 11:32:49.972091 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1517 11:32:49.972169 ==
1518 11:32:49.975663 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 11:32:49.982478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 11:32:49.982546 ==
1521 11:32:49.982609 DQS Delay:
1522 11:32:49.982662 DQS0 = 0, DQS1 = 0
1523 11:32:49.985169 DQM Delay:
1524 11:32:49.985259 DQM0 = 81, DQM1 = 72
1525 11:32:49.989163 DQ Delay:
1526 11:32:49.992229 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1527 11:32:49.992300 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1528 11:32:49.995566 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1529 11:32:50.001713 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1530 11:32:50.001779
1531 11:32:50.001840
1532 11:32:50.001892 ==
1533 11:32:50.005770 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 11:32:50.008535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1535 11:32:50.008598 ==
1536 11:32:50.008651
1537 11:32:50.008700
1538 11:32:50.012179 TX Vref Scan disable
1539 11:32:50.012246 == TX Byte 0 ==
1540 11:32:50.018653 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1541 11:32:50.021981 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1542 11:32:50.022070 == TX Byte 1 ==
1543 11:32:50.029117 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1544 11:32:50.032453 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1545 11:32:50.032520 ==
1546 11:32:50.035278 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 11:32:50.038819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1548 11:32:50.038889 ==
1549 11:32:50.052155 TX Vref=22, minBit 2, minWin=27, winSum=444
1550 11:32:50.055658 TX Vref=24, minBit 3, minWin=27, winSum=450
1551 11:32:50.058869 TX Vref=26, minBit 0, minWin=28, winSum=453
1552 11:32:50.062298 TX Vref=28, minBit 0, minWin=28, winSum=458
1553 11:32:50.065630 TX Vref=30, minBit 0, minWin=28, winSum=458
1554 11:32:50.069585 TX Vref=32, minBit 0, minWin=28, winSum=455
1555 11:32:50.075431 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1556 11:32:50.075502
1557 11:32:50.079232 Final TX Range 1 Vref 28
1558 11:32:50.079298
1559 11:32:50.079355 ==
1560 11:32:50.082793 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 11:32:50.085718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1562 11:32:50.085783 ==
1563 11:32:50.085843
1564 11:32:50.089138
1565 11:32:50.089236 TX Vref Scan disable
1566 11:32:50.092331 == TX Byte 0 ==
1567 11:32:50.095824 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1568 11:32:50.099219 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1569 11:32:50.102015 == TX Byte 1 ==
1570 11:32:50.105685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1571 11:32:50.108484 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1572 11:32:50.112305
1573 11:32:50.112375 [DATLAT]
1574 11:32:50.112430 Freq=800, CH1 RK0
1575 11:32:50.112482
1576 11:32:50.116089 DATLAT Default: 0xa
1577 11:32:50.116165 0, 0xFFFF, sum = 0
1578 11:32:50.118879 1, 0xFFFF, sum = 0
1579 11:32:50.118949 2, 0xFFFF, sum = 0
1580 11:32:50.122432 3, 0xFFFF, sum = 0
1581 11:32:50.122499 4, 0xFFFF, sum = 0
1582 11:32:50.125489 5, 0xFFFF, sum = 0
1583 11:32:50.125560 6, 0xFFFF, sum = 0
1584 11:32:50.128883 7, 0xFFFF, sum = 0
1585 11:32:50.128953 8, 0x0, sum = 1
1586 11:32:50.132335 9, 0x0, sum = 2
1587 11:32:50.132406 10, 0x0, sum = 3
1588 11:32:50.136091 11, 0x0, sum = 4
1589 11:32:50.136158 best_step = 9
1590 11:32:50.136228
1591 11:32:50.136297 ==
1592 11:32:50.138692 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 11:32:50.143812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1594 11:32:50.145459 ==
1595 11:32:50.145527 RX Vref Scan: 1
1596 11:32:50.145615
1597 11:32:50.149190 Set Vref Range= 32 -> 127
1598 11:32:50.149298
1599 11:32:50.152255 RX Vref 32 -> 127, step: 1
1600 11:32:50.152324
1601 11:32:50.152399 RX Delay -111 -> 252, step: 8
1602 11:32:50.152466
1603 11:32:50.155806 Set Vref, RX VrefLevel [Byte0]: 32
1604 11:32:50.159118 [Byte1]: 32
1605 11:32:50.163197
1606 11:32:50.163269 Set Vref, RX VrefLevel [Byte0]: 33
1607 11:32:50.166397 [Byte1]: 33
1608 11:32:50.170409
1609 11:32:50.170475 Set Vref, RX VrefLevel [Byte0]: 34
1610 11:32:50.174090 [Byte1]: 34
1611 11:32:50.178497
1612 11:32:50.178570 Set Vref, RX VrefLevel [Byte0]: 35
1613 11:32:50.182230 [Byte1]: 35
1614 11:32:50.186015
1615 11:32:50.186075 Set Vref, RX VrefLevel [Byte0]: 36
1616 11:32:50.189723 [Byte1]: 36
1617 11:32:50.193894
1618 11:32:50.193972 Set Vref, RX VrefLevel [Byte0]: 37
1619 11:32:50.198192 [Byte1]: 37
1620 11:32:50.201627
1621 11:32:50.201692 Set Vref, RX VrefLevel [Byte0]: 38
1622 11:32:50.204270 [Byte1]: 38
1623 11:32:50.209172
1624 11:32:50.209253 Set Vref, RX VrefLevel [Byte0]: 39
1625 11:32:50.212138 [Byte1]: 39
1626 11:32:50.216421
1627 11:32:50.216485 Set Vref, RX VrefLevel [Byte0]: 40
1628 11:32:50.220258 [Byte1]: 40
1629 11:32:50.224658
1630 11:32:50.224722 Set Vref, RX VrefLevel [Byte0]: 41
1631 11:32:50.227508 [Byte1]: 41
1632 11:32:50.232495
1633 11:32:50.232554 Set Vref, RX VrefLevel [Byte0]: 42
1634 11:32:50.235554 [Byte1]: 42
1635 11:32:50.239905
1636 11:32:50.239964 Set Vref, RX VrefLevel [Byte0]: 43
1637 11:32:50.242882 [Byte1]: 43
1638 11:32:50.247277
1639 11:32:50.247343 Set Vref, RX VrefLevel [Byte0]: 44
1640 11:32:50.250477 [Byte1]: 44
1641 11:32:50.255150
1642 11:32:50.255216 Set Vref, RX VrefLevel [Byte0]: 45
1643 11:32:50.261021 [Byte1]: 45
1644 11:32:50.261084
1645 11:32:50.265088 Set Vref, RX VrefLevel [Byte0]: 46
1646 11:32:50.267759 [Byte1]: 46
1647 11:32:50.267824
1648 11:32:50.271328 Set Vref, RX VrefLevel [Byte0]: 47
1649 11:32:50.274776 [Byte1]: 47
1650 11:32:50.274838
1651 11:32:50.278289 Set Vref, RX VrefLevel [Byte0]: 48
1652 11:32:50.281843 [Byte1]: 48
1653 11:32:50.286027
1654 11:32:50.286092 Set Vref, RX VrefLevel [Byte0]: 49
1655 11:32:50.288617 [Byte1]: 49
1656 11:32:50.293010
1657 11:32:50.293097 Set Vref, RX VrefLevel [Byte0]: 50
1658 11:32:50.296172 [Byte1]: 50
1659 11:32:50.301163
1660 11:32:50.301251 Set Vref, RX VrefLevel [Byte0]: 51
1661 11:32:50.303979 [Byte1]: 51
1662 11:32:50.308789
1663 11:32:50.308860 Set Vref, RX VrefLevel [Byte0]: 52
1664 11:32:50.311507 [Byte1]: 52
1665 11:32:50.316705
1666 11:32:50.316789 Set Vref, RX VrefLevel [Byte0]: 53
1667 11:32:50.321077 [Byte1]: 53
1668 11:32:50.323733
1669 11:32:50.323806 Set Vref, RX VrefLevel [Byte0]: 54
1670 11:32:50.327229 [Byte1]: 54
1671 11:32:50.331586
1672 11:32:50.331661 Set Vref, RX VrefLevel [Byte0]: 55
1673 11:32:50.334839 [Byte1]: 55
1674 11:32:50.338813
1675 11:32:50.338890 Set Vref, RX VrefLevel [Byte0]: 56
1676 11:32:50.342314 [Byte1]: 56
1677 11:32:50.346911
1678 11:32:50.346978 Set Vref, RX VrefLevel [Byte0]: 57
1679 11:32:50.349985 [Byte1]: 57
1680 11:32:50.354160
1681 11:32:50.354226 Set Vref, RX VrefLevel [Byte0]: 58
1682 11:32:50.357438 [Byte1]: 58
1683 11:32:50.361928
1684 11:32:50.361995 Set Vref, RX VrefLevel [Byte0]: 59
1685 11:32:50.365071 [Byte1]: 59
1686 11:32:50.369386
1687 11:32:50.369473 Set Vref, RX VrefLevel [Byte0]: 60
1688 11:32:50.372921 [Byte1]: 60
1689 11:32:50.377160
1690 11:32:50.377258 Set Vref, RX VrefLevel [Byte0]: 61
1691 11:32:50.380898 [Byte1]: 61
1692 11:32:50.384590
1693 11:32:50.384654 Set Vref, RX VrefLevel [Byte0]: 62
1694 11:32:50.388040 [Byte1]: 62
1695 11:32:50.392560
1696 11:32:50.392626 Set Vref, RX VrefLevel [Byte0]: 63
1697 11:32:50.395694 [Byte1]: 63
1698 11:32:50.399918
1699 11:32:50.399980 Set Vref, RX VrefLevel [Byte0]: 64
1700 11:32:50.403449 [Byte1]: 64
1701 11:32:50.408382
1702 11:32:50.408449 Set Vref, RX VrefLevel [Byte0]: 65
1703 11:32:50.411604 [Byte1]: 65
1704 11:32:50.415358
1705 11:32:50.415452 Set Vref, RX VrefLevel [Byte0]: 66
1706 11:32:50.418946 [Byte1]: 66
1707 11:32:50.423922
1708 11:32:50.423985 Set Vref, RX VrefLevel [Byte0]: 67
1709 11:32:50.426408 [Byte1]: 67
1710 11:32:50.432974
1711 11:32:50.433066 Set Vref, RX VrefLevel [Byte0]: 68
1712 11:32:50.435240 [Byte1]: 68
1713 11:32:50.438196
1714 11:32:50.438263 Set Vref, RX VrefLevel [Byte0]: 69
1715 11:32:50.441590 [Byte1]: 69
1716 11:32:50.445938
1717 11:32:50.446007 Set Vref, RX VrefLevel [Byte0]: 70
1718 11:32:50.449941 [Byte1]: 70
1719 11:32:50.453357
1720 11:32:50.453451 Set Vref, RX VrefLevel [Byte0]: 71
1721 11:32:50.457358 [Byte1]: 71
1722 11:32:50.461915
1723 11:32:50.461983 Set Vref, RX VrefLevel [Byte0]: 72
1724 11:32:50.464520 [Byte1]: 72
1725 11:32:50.469486
1726 11:32:50.469551 Set Vref, RX VrefLevel [Byte0]: 73
1727 11:32:50.472368 [Byte1]: 73
1728 11:32:50.476299
1729 11:32:50.476364 Set Vref, RX VrefLevel [Byte0]: 74
1730 11:32:50.479980 [Byte1]: 74
1731 11:32:50.484555
1732 11:32:50.484631 Set Vref, RX VrefLevel [Byte0]: 75
1733 11:32:50.488407 [Byte1]: 75
1734 11:32:50.491550
1735 11:32:50.491616 Set Vref, RX VrefLevel [Byte0]: 76
1736 11:32:50.495050 [Byte1]: 76
1737 11:32:50.499299
1738 11:32:50.499369 Set Vref, RX VrefLevel [Byte0]: 77
1739 11:32:50.502693 [Byte1]: 77
1740 11:32:50.507478
1741 11:32:50.507545 Set Vref, RX VrefLevel [Byte0]: 78
1742 11:32:50.510612 [Byte1]: 78
1743 11:32:50.514832
1744 11:32:50.514898 Final RX Vref Byte 0 = 60 to rank0
1745 11:32:50.517830 Final RX Vref Byte 1 = 56 to rank0
1746 11:32:50.521787 Final RX Vref Byte 0 = 60 to rank1
1747 11:32:50.524726 Final RX Vref Byte 1 = 56 to rank1==
1748 11:32:50.528128 Dram Type= 6, Freq= 0, CH_1, rank 0
1749 11:32:50.531303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1750 11:32:50.534915 ==
1751 11:32:50.534981 DQS Delay:
1752 11:32:50.535054 DQS0 = 0, DQS1 = 0
1753 11:32:50.538854 DQM Delay:
1754 11:32:50.538919 DQM0 = 81, DQM1 = 74
1755 11:32:50.542045 DQ Delay:
1756 11:32:50.544846 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1757 11:32:50.544918 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1758 11:32:50.549488 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1759 11:32:50.551861 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1760 11:32:50.554548
1761 11:32:50.554621
1762 11:32:50.562808 [DQSOSCAuto] RK0, (LSB)MR18= 0x5757, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1763 11:32:50.565261 CH1 RK0: MR19=606, MR18=5757
1764 11:32:50.571108 CH1_RK0: MR19=0x606, MR18=0x5757, DQSOSC=388, MR23=63, INC=98, DEC=65
1765 11:32:50.571203
1766 11:32:50.574763 ----->DramcWriteLeveling(PI) begin...
1767 11:32:50.574833 ==
1768 11:32:50.577858 Dram Type= 6, Freq= 0, CH_1, rank 1
1769 11:32:50.582059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1770 11:32:50.582127 ==
1771 11:32:50.584730 Write leveling (Byte 0): 23 => 23
1772 11:32:50.588350 Write leveling (Byte 1): 26 => 26
1773 11:32:50.591565 DramcWriteLeveling(PI) end<-----
1774 11:32:50.591635
1775 11:32:50.591727 ==
1776 11:32:50.594902 Dram Type= 6, Freq= 0, CH_1, rank 1
1777 11:32:50.597990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1778 11:32:50.598058 ==
1779 11:32:50.601466 [Gating] SW mode calibration
1780 11:32:50.609011 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1781 11:32:50.615021 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1782 11:32:50.618632 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1783 11:32:50.621925 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1784 11:32:50.628245 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1785 11:32:50.631348 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1786 11:32:50.635232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1787 11:32:50.641504 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1788 11:32:50.644780 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1789 11:32:50.648345 0 6 28 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1790 11:32:50.655865 0 7 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
1791 11:32:50.658757 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1792 11:32:50.661883 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1793 11:32:50.664737 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1794 11:32:50.671283 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1795 11:32:50.674866 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1796 11:32:50.678286 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1797 11:32:50.684853 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1798 11:32:50.687994 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1799 11:32:50.692028 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 11:32:50.697808 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 11:32:50.701062 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 11:32:50.704836 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 11:32:50.711597 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1804 11:32:50.714487 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1805 11:32:50.718191 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1806 11:32:50.724916 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1807 11:32:50.728088 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1808 11:32:50.731479 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1809 11:32:50.738275 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1810 11:32:50.741860 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1811 11:32:50.744591 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1812 11:32:50.751720 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1813 11:32:50.755004 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1814 11:32:50.757997 Total UI for P1: 0, mck2ui 16
1815 11:32:50.762890 best dqsien dly found for B0: ( 0, 9, 26)
1816 11:32:50.765461 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1817 11:32:50.767884 Total UI for P1: 0, mck2ui 16
1818 11:32:50.771298 best dqsien dly found for B1: ( 0, 9, 28)
1819 11:32:50.774811 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1820 11:32:50.777851 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1821 11:32:50.777920
1822 11:32:50.781696 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1823 11:32:50.788380 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1824 11:32:50.788450 [Gating] SW calibration Done
1825 11:32:50.788526 ==
1826 11:32:50.791080 Dram Type= 6, Freq= 0, CH_1, rank 1
1827 11:32:50.798387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1828 11:32:50.798461 ==
1829 11:32:50.798535 RX Vref Scan: 0
1830 11:32:50.798606
1831 11:32:50.801114 RX Vref 0 -> 0, step: 1
1832 11:32:50.801183
1833 11:32:50.804445 RX Delay -130 -> 252, step: 16
1834 11:32:50.807655 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1835 11:32:50.811497 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1836 11:32:50.814629 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1837 11:32:50.821610 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1838 11:32:50.824478 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1839 11:32:50.828098 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1840 11:32:50.832013 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1841 11:32:50.834518 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1842 11:32:50.841369 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1843 11:32:50.844914 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1844 11:32:50.848230 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1845 11:32:50.851234 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1846 11:32:50.854299 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1847 11:32:50.861205 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1848 11:32:50.865156 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1849 11:32:50.868141 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1850 11:32:50.868210 ==
1851 11:32:50.871937 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 11:32:50.874539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1853 11:32:50.874607 ==
1854 11:32:50.877899 DQS Delay:
1855 11:32:50.877967 DQS0 = 0, DQS1 = 0
1856 11:32:50.881182 DQM Delay:
1857 11:32:50.881295 DQM0 = 86, DQM1 = 75
1858 11:32:50.881365 DQ Delay:
1859 11:32:50.884877 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1860 11:32:50.887981 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1861 11:32:50.891401 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1862 11:32:50.894575 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1863 11:32:50.894641
1864 11:32:50.894714
1865 11:32:50.897811 ==
1866 11:32:50.897876 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 11:32:50.904406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1868 11:32:50.904473 ==
1869 11:32:50.904542
1870 11:32:50.904608
1871 11:32:50.908485 TX Vref Scan disable
1872 11:32:50.908551 == TX Byte 0 ==
1873 11:32:50.911261 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1874 11:32:50.918114 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1875 11:32:50.918186 == TX Byte 1 ==
1876 11:32:50.921432 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1877 11:32:50.928104 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1878 11:32:50.928174 ==
1879 11:32:50.932269 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 11:32:50.934357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1881 11:32:50.934424 ==
1882 11:32:50.948185 TX Vref=22, minBit 0, minWin=27, winSum=448
1883 11:32:50.951532 TX Vref=24, minBit 1, minWin=28, winSum=454
1884 11:32:50.955153 TX Vref=26, minBit 8, minWin=27, winSum=460
1885 11:32:50.958226 TX Vref=28, minBit 9, minWin=28, winSum=461
1886 11:32:50.961165 TX Vref=30, minBit 9, minWin=27, winSum=458
1887 11:32:50.964281 TX Vref=32, minBit 9, minWin=27, winSum=455
1888 11:32:50.971062 [TxChooseVref] Worse bit 9, Min win 28, Win sum 461, Final Vref 28
1889 11:32:50.971132
1890 11:32:50.976021 Final TX Range 1 Vref 28
1891 11:32:50.976091
1892 11:32:50.976163 ==
1893 11:32:50.978007 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 11:32:50.981213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1895 11:32:50.981284 ==
1896 11:32:50.981355
1897 11:32:50.984586
1898 11:32:50.984654 TX Vref Scan disable
1899 11:32:50.987637 == TX Byte 0 ==
1900 11:32:50.991660 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1901 11:32:50.997781 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1902 11:32:50.997850 == TX Byte 1 ==
1903 11:32:51.001483 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1904 11:32:51.008359 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1905 11:32:51.008427
1906 11:32:51.008499 [DATLAT]
1907 11:32:51.008570 Freq=800, CH1 RK1
1908 11:32:51.008639
1909 11:32:51.011155 DATLAT Default: 0x9
1910 11:32:51.011219 0, 0xFFFF, sum = 0
1911 11:32:51.014307 1, 0xFFFF, sum = 0
1912 11:32:51.014372 2, 0xFFFF, sum = 0
1913 11:32:51.017672 3, 0xFFFF, sum = 0
1914 11:32:51.017740 4, 0xFFFF, sum = 0
1915 11:32:51.021971 5, 0xFFFF, sum = 0
1916 11:32:51.022038 6, 0xFFFF, sum = 0
1917 11:32:51.024382 7, 0xFFFF, sum = 0
1918 11:32:51.024450 8, 0x0, sum = 1
1919 11:32:51.027981 9, 0x0, sum = 2
1920 11:32:51.028051 10, 0x0, sum = 3
1921 11:32:51.031348 11, 0x0, sum = 4
1922 11:32:51.031416 best_step = 9
1923 11:32:51.031487
1924 11:32:51.031556 ==
1925 11:32:51.034658 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 11:32:51.041347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1927 11:32:51.041418 ==
1928 11:32:51.041491 RX Vref Scan: 0
1929 11:32:51.041561
1930 11:32:51.044397 RX Vref 0 -> 0, step: 1
1931 11:32:51.044461
1932 11:32:51.047562 RX Delay -111 -> 252, step: 8
1933 11:32:51.051497 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1934 11:32:51.055342 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1935 11:32:51.061059 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1936 11:32:51.064975 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1937 11:32:51.067951 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1938 11:32:51.070996 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1939 11:32:51.074060 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1940 11:32:51.081348 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1941 11:32:51.084222 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1942 11:32:51.087929 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1943 11:32:51.091506 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1944 11:32:51.094646 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1945 11:32:51.101194 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1946 11:32:51.104142 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1947 11:32:51.107961 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1948 11:32:51.110897 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1949 11:32:51.110971 ==
1950 11:32:51.114595 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 11:32:51.121017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1952 11:32:51.121115 ==
1953 11:32:51.121198 DQS Delay:
1954 11:32:51.121319 DQS0 = 0, DQS1 = 0
1955 11:32:51.124273 DQM Delay:
1956 11:32:51.124360 DQM0 = 83, DQM1 = 74
1957 11:32:51.127578 DQ Delay:
1958 11:32:51.130904 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1959 11:32:51.134505 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1960 11:32:51.137707 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1961 11:32:51.140495 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1962 11:32:51.140561
1963 11:32:51.140623
1964 11:32:51.147293 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1965 11:32:51.150899 CH1 RK1: MR19=606, MR18=3F3F
1966 11:32:51.157416 CH1_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1967 11:32:51.160868 [RxdqsGatingPostProcess] freq 800
1968 11:32:51.164242 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1969 11:32:51.167341 Pre-setting of DQS Precalculation
1970 11:32:51.174264 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1971 11:32:51.180908 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1972 11:32:51.187213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1973 11:32:51.187285
1974 11:32:51.187350
1975 11:32:51.190867 [Calibration Summary] 1600 Mbps
1976 11:32:51.190936 CH 0, Rank 0
1977 11:32:51.194379 SW Impedance : PASS
1978 11:32:51.197685 DUTY Scan : NO K
1979 11:32:51.197758 ZQ Calibration : PASS
1980 11:32:51.200402 Jitter Meter : NO K
1981 11:32:51.204153 CBT Training : PASS
1982 11:32:51.204247 Write leveling : PASS
1983 11:32:51.206958 RX DQS gating : PASS
1984 11:32:51.207027 RX DQ/DQS(RDDQC) : PASS
1985 11:32:51.210567 TX DQ/DQS : PASS
1986 11:32:51.214226 RX DATLAT : PASS
1987 11:32:51.214294 RX DQ/DQS(Engine): PASS
1988 11:32:51.217683 TX OE : NO K
1989 11:32:51.217747 All Pass.
1990 11:32:51.217800
1991 11:32:51.220400 CH 0, Rank 1
1992 11:32:51.220460 SW Impedance : PASS
1993 11:32:51.223629 DUTY Scan : NO K
1994 11:32:51.227166 ZQ Calibration : PASS
1995 11:32:51.227228 Jitter Meter : NO K
1996 11:32:51.230640 CBT Training : PASS
1997 11:32:51.234150 Write leveling : PASS
1998 11:32:51.234220 RX DQS gating : PASS
1999 11:32:51.237307 RX DQ/DQS(RDDQC) : PASS
2000 11:32:51.240478 TX DQ/DQS : PASS
2001 11:32:51.240543 RX DATLAT : PASS
2002 11:32:51.243778 RX DQ/DQS(Engine): PASS
2003 11:32:51.247188 TX OE : NO K
2004 11:32:51.247259 All Pass.
2005 11:32:51.247313
2006 11:32:51.247364 CH 1, Rank 0
2007 11:32:51.250554 SW Impedance : PASS
2008 11:32:51.250639 DUTY Scan : NO K
2009 11:32:51.253720 ZQ Calibration : PASS
2010 11:32:51.257020 Jitter Meter : NO K
2011 11:32:51.257113 CBT Training : PASS
2012 11:32:51.260622 Write leveling : PASS
2013 11:32:51.263721 RX DQS gating : PASS
2014 11:32:51.263792 RX DQ/DQS(RDDQC) : PASS
2015 11:32:51.267358 TX DQ/DQS : PASS
2016 11:32:51.270214 RX DATLAT : PASS
2017 11:32:51.270277 RX DQ/DQS(Engine): PASS
2018 11:32:51.274057 TX OE : NO K
2019 11:32:51.274121 All Pass.
2020 11:32:51.274174
2021 11:32:51.276899 CH 1, Rank 1
2022 11:32:51.276982 SW Impedance : PASS
2023 11:32:51.280370 DUTY Scan : NO K
2024 11:32:51.284049 ZQ Calibration : PASS
2025 11:32:51.284114 Jitter Meter : NO K
2026 11:32:51.287175 CBT Training : PASS
2027 11:32:51.290786 Write leveling : PASS
2028 11:32:51.290853 RX DQS gating : PASS
2029 11:32:51.294148 RX DQ/DQS(RDDQC) : PASS
2030 11:32:51.294219 TX DQ/DQS : PASS
2031 11:32:51.296896 RX DATLAT : PASS
2032 11:32:51.300410 RX DQ/DQS(Engine): PASS
2033 11:32:51.300478 TX OE : NO K
2034 11:32:51.303813 All Pass.
2035 11:32:51.303880
2036 11:32:51.303933 DramC Write-DBI off
2037 11:32:51.307413 PER_BANK_REFRESH: Hybrid Mode
2038 11:32:51.310503 TX_TRACKING: ON
2039 11:32:51.314520 [GetDramInforAfterCalByMRR] Vendor 6.
2040 11:32:51.317004 [GetDramInforAfterCalByMRR] Revision 606.
2041 11:32:51.320504 [GetDramInforAfterCalByMRR] Revision 2 0.
2042 11:32:51.320569 MR0 0x3939
2043 11:32:51.320623 MR8 0x1111
2044 11:32:51.327015 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2045 11:32:51.327082
2046 11:32:51.327137 MR0 0x3939
2047 11:32:51.327189 MR8 0x1111
2048 11:32:51.330421 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2049 11:32:51.330482
2050 11:32:51.340886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2051 11:32:51.343689 [FAST_K] Save calibration result to emmc
2052 11:32:51.347018 [FAST_K] Save calibration result to emmc
2053 11:32:51.350221 dram_init: config_dvfs: 1
2054 11:32:51.354429 dramc_set_vcore_voltage set vcore to 662500
2055 11:32:51.357147 Read voltage for 1200, 2
2056 11:32:51.357221 Vio18 = 0
2057 11:32:51.357335 Vcore = 662500
2058 11:32:51.360258 Vdram = 0
2059 11:32:51.360326 Vddq = 0
2060 11:32:51.360400 Vmddr = 0
2061 11:32:51.367148 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2062 11:32:51.370529 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2063 11:32:51.373854 MEM_TYPE=3, freq_sel=15
2064 11:32:51.376955 sv_algorithm_assistance_LP4_1600
2065 11:32:51.380344 ============ PULL DRAM RESETB DOWN ============
2066 11:32:51.383696 ========== PULL DRAM RESETB DOWN end =========
2067 11:32:51.390346 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2068 11:32:51.394050 ===================================
2069 11:32:51.394125 LPDDR4 DRAM CONFIGURATION
2070 11:32:51.397108 ===================================
2071 11:32:51.400892 EX_ROW_EN[0] = 0x0
2072 11:32:51.403851 EX_ROW_EN[1] = 0x0
2073 11:32:51.403917 LP4Y_EN = 0x0
2074 11:32:51.406770 WORK_FSP = 0x0
2075 11:32:51.406835 WL = 0x4
2076 11:32:51.410337 RL = 0x4
2077 11:32:51.410406 BL = 0x2
2078 11:32:51.413591 RPST = 0x0
2079 11:32:51.413655 RD_PRE = 0x0
2080 11:32:51.417419 WR_PRE = 0x1
2081 11:32:51.417489 WR_PST = 0x0
2082 11:32:51.420714 DBI_WR = 0x0
2083 11:32:51.420782 DBI_RD = 0x0
2084 11:32:51.423511 OTF = 0x1
2085 11:32:51.427335 ===================================
2086 11:32:51.430842 ===================================
2087 11:32:51.430918 ANA top config
2088 11:32:51.433522 ===================================
2089 11:32:51.437147 DLL_ASYNC_EN = 0
2090 11:32:51.440828 ALL_SLAVE_EN = 0
2091 11:32:51.443575 NEW_RANK_MODE = 1
2092 11:32:51.443639 DLL_IDLE_MODE = 1
2093 11:32:51.447491 LP45_APHY_COMB_EN = 1
2094 11:32:51.450441 TX_ODT_DIS = 1
2095 11:32:51.453870 NEW_8X_MODE = 1
2096 11:32:51.457583 ===================================
2097 11:32:51.460086 ===================================
2098 11:32:51.463907 data_rate = 2400
2099 11:32:51.463977 CKR = 1
2100 11:32:51.466920 DQ_P2S_RATIO = 8
2101 11:32:51.470836 ===================================
2102 11:32:51.473417 CA_P2S_RATIO = 8
2103 11:32:51.477092 DQ_CA_OPEN = 0
2104 11:32:51.480621 DQ_SEMI_OPEN = 0
2105 11:32:51.483539 CA_SEMI_OPEN = 0
2106 11:32:51.483605 CA_FULL_RATE = 0
2107 11:32:51.486578 DQ_CKDIV4_EN = 0
2108 11:32:51.490634 CA_CKDIV4_EN = 0
2109 11:32:51.493476 CA_PREDIV_EN = 0
2110 11:32:51.496602 PH8_DLY = 17
2111 11:32:51.499939 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2112 11:32:51.500006 DQ_AAMCK_DIV = 4
2113 11:32:51.504149 CA_AAMCK_DIV = 4
2114 11:32:51.506697 CA_ADMCK_DIV = 4
2115 11:32:51.510275 DQ_TRACK_CA_EN = 0
2116 11:32:51.513681 CA_PICK = 1200
2117 11:32:51.516837 CA_MCKIO = 1200
2118 11:32:51.516903 MCKIO_SEMI = 0
2119 11:32:51.519991 PLL_FREQ = 2366
2120 11:32:51.523677 DQ_UI_PI_RATIO = 32
2121 11:32:51.526707 CA_UI_PI_RATIO = 0
2122 11:32:51.531055 ===================================
2123 11:32:51.534487 ===================================
2124 11:32:51.536853 memory_type:LPDDR4
2125 11:32:51.536951 GP_NUM : 10
2126 11:32:51.540012 SRAM_EN : 1
2127 11:32:51.543668 MD32_EN : 0
2128 11:32:51.546682 ===================================
2129 11:32:51.546751 [ANA_INIT] >>>>>>>>>>>>>>
2130 11:32:51.549877 <<<<<< [CONFIGURE PHASE]: ANA_TX
2131 11:32:51.553990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2132 11:32:51.557473 ===================================
2133 11:32:51.560222 data_rate = 2400,PCW = 0X5b00
2134 11:32:51.563266 ===================================
2135 11:32:51.567163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2136 11:32:51.573241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2137 11:32:51.576996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2138 11:32:51.583348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2139 11:32:51.586416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2140 11:32:51.590277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2141 11:32:51.590344 [ANA_INIT] flow start
2142 11:32:51.593832 [ANA_INIT] PLL >>>>>>>>
2143 11:32:51.596611 [ANA_INIT] PLL <<<<<<<<
2144 11:32:51.596686 [ANA_INIT] MIDPI >>>>>>>>
2145 11:32:51.599815 [ANA_INIT] MIDPI <<<<<<<<
2146 11:32:51.603944 [ANA_INIT] DLL >>>>>>>>
2147 11:32:51.607065 [ANA_INIT] DLL <<<<<<<<
2148 11:32:51.607139 [ANA_INIT] flow end
2149 11:32:51.610274 ============ LP4 DIFF to SE enter ============
2150 11:32:51.617821 ============ LP4 DIFF to SE exit ============
2151 11:32:51.617897 [ANA_INIT] <<<<<<<<<<<<<
2152 11:32:51.620275 [Flow] Enable top DCM control >>>>>
2153 11:32:51.623018 [Flow] Enable top DCM control <<<<<
2154 11:32:51.626708 Enable DLL master slave shuffle
2155 11:32:51.633448 ==============================================================
2156 11:32:51.633527 Gating Mode config
2157 11:32:51.640265 ==============================================================
2158 11:32:51.643166 Config description:
2159 11:32:51.649685 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2160 11:32:51.656454 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2161 11:32:51.662989 SELPH_MODE 0: By rank 1: By Phase
2162 11:32:51.669824 ==============================================================
2163 11:32:51.672990 GAT_TRACK_EN = 1
2164 11:32:51.673065 RX_GATING_MODE = 2
2165 11:32:51.676620 RX_GATING_TRACK_MODE = 2
2166 11:32:51.679726 SELPH_MODE = 1
2167 11:32:51.683514 PICG_EARLY_EN = 1
2168 11:32:51.687100 VALID_LAT_VALUE = 1
2169 11:32:51.693080 ==============================================================
2170 11:32:51.696521 Enter into Gating configuration >>>>
2171 11:32:51.700566 Exit from Gating configuration <<<<
2172 11:32:51.702985 Enter into DVFS_PRE_config >>>>>
2173 11:32:51.712986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2174 11:32:51.716768 Exit from DVFS_PRE_config <<<<<
2175 11:32:51.719768 Enter into PICG configuration >>>>
2176 11:32:51.723678 Exit from PICG configuration <<<<
2177 11:32:51.726335 [RX_INPUT] configuration >>>>>
2178 11:32:51.726410 [RX_INPUT] configuration <<<<<
2179 11:32:51.733400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2180 11:32:51.740619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2181 11:32:51.742973 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2182 11:32:51.749615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2183 11:32:51.756682 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2184 11:32:51.762938 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2185 11:32:51.766773 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2186 11:32:51.769777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2187 11:32:51.776435 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2188 11:32:51.779627 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2189 11:32:51.782798 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2190 11:32:51.789507 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2191 11:32:51.792937 ===================================
2192 11:32:51.793010 LPDDR4 DRAM CONFIGURATION
2193 11:32:51.796194 ===================================
2194 11:32:51.799575 EX_ROW_EN[0] = 0x0
2195 11:32:51.799641 EX_ROW_EN[1] = 0x0
2196 11:32:51.803609 LP4Y_EN = 0x0
2197 11:32:51.803682 WORK_FSP = 0x0
2198 11:32:51.806043 WL = 0x4
2199 11:32:51.806114 RL = 0x4
2200 11:32:51.809678 BL = 0x2
2201 11:32:51.809742 RPST = 0x0
2202 11:32:51.812810 RD_PRE = 0x0
2203 11:32:51.816656 WR_PRE = 0x1
2204 11:32:51.816721 WR_PST = 0x0
2205 11:32:51.819695 DBI_WR = 0x0
2206 11:32:51.819760 DBI_RD = 0x0
2207 11:32:51.823343 OTF = 0x1
2208 11:32:51.826278 ===================================
2209 11:32:51.829695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2210 11:32:51.832882 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2211 11:32:51.836119 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2212 11:32:51.840131 ===================================
2213 11:32:51.842765 LPDDR4 DRAM CONFIGURATION
2214 11:32:51.846690 ===================================
2215 11:32:51.849385 EX_ROW_EN[0] = 0x10
2216 11:32:51.849474 EX_ROW_EN[1] = 0x0
2217 11:32:51.853381 LP4Y_EN = 0x0
2218 11:32:51.853470 WORK_FSP = 0x0
2219 11:32:51.856669 WL = 0x4
2220 11:32:51.856759 RL = 0x4
2221 11:32:51.859355 BL = 0x2
2222 11:32:51.859420 RPST = 0x0
2223 11:32:51.863055 RD_PRE = 0x0
2224 11:32:51.863125 WR_PRE = 0x1
2225 11:32:51.866300 WR_PST = 0x0
2226 11:32:51.866370 DBI_WR = 0x0
2227 11:32:51.869887 DBI_RD = 0x0
2228 11:32:51.869960 OTF = 0x1
2229 11:32:51.872604 ===================================
2230 11:32:51.880213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2231 11:32:51.880298 ==
2232 11:32:51.882817 Dram Type= 6, Freq= 0, CH_0, rank 0
2233 11:32:51.889884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2234 11:32:51.889967 ==
2235 11:32:51.890025 [Duty_Offset_Calibration]
2236 11:32:51.892945 B0:0 B1:2 CA:1
2237 11:32:51.893032
2238 11:32:51.896514 [DutyScan_Calibration_Flow] k_type=0
2239 11:32:51.905534
2240 11:32:51.905604 ==CLK 0==
2241 11:32:51.909127 Final CLK duty delay cell = 0
2242 11:32:51.911653 [0] MAX Duty = 5093%(X100), DQS PI = 12
2243 11:32:51.915340 [0] MIN Duty = 4938%(X100), DQS PI = 52
2244 11:32:51.915414 [0] AVG Duty = 5015%(X100)
2245 11:32:51.918411
2246 11:32:51.922100 CH0 CLK Duty spec in!! Max-Min= 155%
2247 11:32:51.925325 [DutyScan_Calibration_Flow] ====Done====
2248 11:32:51.925391
2249 11:32:51.928219 [DutyScan_Calibration_Flow] k_type=1
2250 11:32:51.944370
2251 11:32:51.944483 ==DQS 0 ==
2252 11:32:51.948758 Final DQS duty delay cell = 0
2253 11:32:51.951623 [0] MAX Duty = 5125%(X100), DQS PI = 32
2254 11:32:51.954562 [0] MIN Duty = 5031%(X100), DQS PI = 4
2255 11:32:51.954651 [0] AVG Duty = 5078%(X100)
2256 11:32:51.958100
2257 11:32:51.958261 ==DQS 1 ==
2258 11:32:51.961076 Final DQS duty delay cell = 0
2259 11:32:51.965112 [0] MAX Duty = 5031%(X100), DQS PI = 52
2260 11:32:51.967821 [0] MIN Duty = 4906%(X100), DQS PI = 14
2261 11:32:51.967904 [0] AVG Duty = 4968%(X100)
2262 11:32:51.970872
2263 11:32:51.974200 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2264 11:32:51.974269
2265 11:32:51.978897 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2266 11:32:51.982066 [DutyScan_Calibration_Flow] ====Done====
2267 11:32:51.982143
2268 11:32:51.984621 [DutyScan_Calibration_Flow] k_type=3
2269 11:32:52.001429
2270 11:32:52.001508 ==DQM 0 ==
2271 11:32:52.005096 Final DQM duty delay cell = 0
2272 11:32:52.008328 [0] MAX Duty = 5124%(X100), DQS PI = 20
2273 11:32:52.011978 [0] MIN Duty = 4969%(X100), DQS PI = 40
2274 11:32:52.014983 [0] AVG Duty = 5046%(X100)
2275 11:32:52.015082
2276 11:32:52.015169 ==DQM 1 ==
2277 11:32:52.018201 Final DQM duty delay cell = 4
2278 11:32:52.021622 [4] MAX Duty = 5187%(X100), DQS PI = 54
2279 11:32:52.025198 [4] MIN Duty = 5000%(X100), DQS PI = 18
2280 11:32:52.028422 [4] AVG Duty = 5093%(X100)
2281 11:32:52.028504
2282 11:32:52.031474 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2283 11:32:52.031538
2284 11:32:52.035292 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2285 11:32:52.038659 [DutyScan_Calibration_Flow] ====Done====
2286 11:32:52.038725
2287 11:32:52.041614 [DutyScan_Calibration_Flow] k_type=2
2288 11:32:52.056935
2289 11:32:52.057015 ==DQ 0 ==
2290 11:32:52.059919 Final DQ duty delay cell = -4
2291 11:32:52.063455 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2292 11:32:52.066848 [-4] MIN Duty = 4813%(X100), DQS PI = 44
2293 11:32:52.069786 [-4] AVG Duty = 4937%(X100)
2294 11:32:52.069853
2295 11:32:52.069910 ==DQ 1 ==
2296 11:32:52.073858 Final DQ duty delay cell = -4
2297 11:32:52.076976 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2298 11:32:52.080037 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2299 11:32:52.083192 [-4] AVG Duty = 4984%(X100)
2300 11:32:52.083260
2301 11:32:52.087132 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2302 11:32:52.087231
2303 11:32:52.090766 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2304 11:32:52.093331 [DutyScan_Calibration_Flow] ====Done====
2305 11:32:52.093397 ==
2306 11:32:52.096740 Dram Type= 6, Freq= 0, CH_1, rank 0
2307 11:32:52.100764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2308 11:32:52.100857 ==
2309 11:32:52.104034 [Duty_Offset_Calibration]
2310 11:32:52.104095 B0:0 B1:5 CA:-5
2311 11:32:52.104148
2312 11:32:52.106903 [DutyScan_Calibration_Flow] k_type=0
2313 11:32:52.117623
2314 11:32:52.117696 ==CLK 0==
2315 11:32:52.120276 Final CLK duty delay cell = 0
2316 11:32:52.123514 [0] MAX Duty = 5094%(X100), DQS PI = 24
2317 11:32:52.127466 [0] MIN Duty = 4875%(X100), DQS PI = 46
2318 11:32:52.130725 [0] AVG Duty = 4984%(X100)
2319 11:32:52.130799
2320 11:32:52.134892 CH1 CLK Duty spec in!! Max-Min= 219%
2321 11:32:52.137024 [DutyScan_Calibration_Flow] ====Done====
2322 11:32:52.137135
2323 11:32:52.140158 [DutyScan_Calibration_Flow] k_type=1
2324 11:32:52.155485
2325 11:32:52.155566 ==DQS 0 ==
2326 11:32:52.158911 Final DQS duty delay cell = 0
2327 11:32:52.162460 [0] MAX Duty = 5125%(X100), DQS PI = 16
2328 11:32:52.165736 [0] MIN Duty = 4875%(X100), DQS PI = 40
2329 11:32:52.169546 [0] AVG Duty = 5000%(X100)
2330 11:32:52.169615
2331 11:32:52.169677 ==DQS 1 ==
2332 11:32:52.172795 Final DQS duty delay cell = -4
2333 11:32:52.175886 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2334 11:32:52.178999 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2335 11:32:52.182602 [-4] AVG Duty = 4953%(X100)
2336 11:32:52.182681
2337 11:32:52.185777 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2338 11:32:52.185849
2339 11:32:52.188891 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2340 11:32:52.192190 [DutyScan_Calibration_Flow] ====Done====
2341 11:32:52.192297
2342 11:32:52.195625 [DutyScan_Calibration_Flow] k_type=3
2343 11:32:52.211244
2344 11:32:52.211316 ==DQM 0 ==
2345 11:32:52.214215 Final DQM duty delay cell = -4
2346 11:32:52.217364 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2347 11:32:52.221433 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2348 11:32:52.224038 [-4] AVG Duty = 4968%(X100)
2349 11:32:52.224115
2350 11:32:52.224173 ==DQM 1 ==
2351 11:32:52.227993 Final DQM duty delay cell = -4
2352 11:32:52.231002 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2353 11:32:52.234693 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2354 11:32:52.238377 [-4] AVG Duty = 4968%(X100)
2355 11:32:52.238453
2356 11:32:52.241118 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2357 11:32:52.241199
2358 11:32:52.244071 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2359 11:32:52.247928 [DutyScan_Calibration_Flow] ====Done====
2360 11:32:52.248004
2361 11:32:52.250683 [DutyScan_Calibration_Flow] k_type=2
2362 11:32:52.268277
2363 11:32:52.268354 ==DQ 0 ==
2364 11:32:52.271392 Final DQ duty delay cell = 0
2365 11:32:52.275305 [0] MAX Duty = 5062%(X100), DQS PI = 0
2366 11:32:52.278452 [0] MIN Duty = 4969%(X100), DQS PI = 42
2367 11:32:52.278528 [0] AVG Duty = 5015%(X100)
2368 11:32:52.278587
2369 11:32:52.281195 ==DQ 1 ==
2370 11:32:52.284660 Final DQ duty delay cell = 0
2371 11:32:52.288171 [0] MAX Duty = 5031%(X100), DQS PI = 8
2372 11:32:52.291370 [0] MIN Duty = 4907%(X100), DQS PI = 0
2373 11:32:52.291468 [0] AVG Duty = 4969%(X100)
2374 11:32:52.291552
2375 11:32:52.294965 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2376 11:32:52.295039
2377 11:32:52.298739 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2378 11:32:52.304967 [DutyScan_Calibration_Flow] ====Done====
2379 11:32:52.307705 nWR fixed to 30
2380 11:32:52.307780 [ModeRegInit_LP4] CH0 RK0
2381 11:32:52.311047 [ModeRegInit_LP4] CH0 RK1
2382 11:32:52.315490 [ModeRegInit_LP4] CH1 RK0
2383 11:32:52.315565 [ModeRegInit_LP4] CH1 RK1
2384 11:32:52.319127 match AC timing 6
2385 11:32:52.321321 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2386 11:32:52.324846 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2387 11:32:52.331478 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2388 11:32:52.334765 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2389 11:32:52.341541 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2390 11:32:52.341609 ==
2391 11:32:52.344676 Dram Type= 6, Freq= 0, CH_0, rank 0
2392 11:32:52.347878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2393 11:32:52.347945 ==
2394 11:32:52.354514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2395 11:32:52.357780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2396 11:32:52.368816 [CA 0] Center 39 (9~70) winsize 62
2397 11:32:52.370945 [CA 1] Center 39 (8~70) winsize 63
2398 11:32:52.375045 [CA 2] Center 36 (5~67) winsize 63
2399 11:32:52.377781 [CA 3] Center 35 (4~66) winsize 63
2400 11:32:52.381415 [CA 4] Center 34 (3~65) winsize 63
2401 11:32:52.383975 [CA 5] Center 33 (3~64) winsize 62
2402 11:32:52.384040
2403 11:32:52.388312 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2404 11:32:52.388375
2405 11:32:52.390754 [CATrainingPosCal] consider 1 rank data
2406 11:32:52.394713 u2DelayCellTimex100 = 270/100 ps
2407 11:32:52.397668 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2408 11:32:52.401443 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2409 11:32:52.407919 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2410 11:32:52.410882 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2411 11:32:52.414491 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2412 11:32:52.417878 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2413 11:32:52.417943
2414 11:32:52.421003 CA PerBit enable=1, Macro0, CA PI delay=33
2415 11:32:52.421066
2416 11:32:52.424239 [CBTSetCACLKResult] CA Dly = 33
2417 11:32:52.424302 CS Dly: 7 (0~38)
2418 11:32:52.424355 ==
2419 11:32:52.427586 Dram Type= 6, Freq= 0, CH_0, rank 1
2420 11:32:52.434617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2421 11:32:52.434693 ==
2422 11:32:52.438376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2423 11:32:52.444408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2424 11:32:52.453001 [CA 0] Center 39 (8~70) winsize 63
2425 11:32:52.456849 [CA 1] Center 39 (8~70) winsize 63
2426 11:32:52.459598 [CA 2] Center 36 (5~67) winsize 63
2427 11:32:52.462888 [CA 3] Center 35 (4~66) winsize 63
2428 11:32:52.466982 [CA 4] Center 33 (3~64) winsize 62
2429 11:32:52.470397 [CA 5] Center 33 (3~64) winsize 62
2430 11:32:52.470472
2431 11:32:52.472823 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2432 11:32:52.472899
2433 11:32:52.476519 [CATrainingPosCal] consider 2 rank data
2434 11:32:52.480003 u2DelayCellTimex100 = 270/100 ps
2435 11:32:52.483078 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2436 11:32:52.487155 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2437 11:32:52.493760 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2438 11:32:52.496525 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2439 11:32:52.499840 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2440 11:32:52.503319 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2441 11:32:52.503395
2442 11:32:52.506308 CA PerBit enable=1, Macro0, CA PI delay=33
2443 11:32:52.506384
2444 11:32:52.509996 [CBTSetCACLKResult] CA Dly = 33
2445 11:32:52.510071 CS Dly: 7 (0~39)
2446 11:32:52.510130
2447 11:32:52.513240 ----->DramcWriteLeveling(PI) begin...
2448 11:32:52.516427 ==
2449 11:32:52.516502 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 11:32:52.522890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2451 11:32:52.522967 ==
2452 11:32:52.526260 Write leveling (Byte 0): 26 => 26
2453 11:32:52.529717 Write leveling (Byte 1): 27 => 27
2454 11:32:52.529792 DramcWriteLeveling(PI) end<-----
2455 11:32:52.533159
2456 11:32:52.533291 ==
2457 11:32:52.536872 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 11:32:52.540858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2459 11:32:52.540933 ==
2460 11:32:52.543437 [Gating] SW mode calibration
2461 11:32:52.549927 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2462 11:32:52.553860 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2463 11:32:52.559990 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2464 11:32:52.564033 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2465 11:32:52.566692 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2466 11:32:52.573897 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2467 11:32:52.577111 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2468 11:32:52.579940 0 11 20 | B1->B0 | 2d2d 2727 | 0 0 | (0 1) (0 1)
2469 11:32:52.586977 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2470 11:32:52.589849 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2471 11:32:52.594074 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2472 11:32:52.600018 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2473 11:32:52.603584 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2474 11:32:52.606788 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2475 11:32:52.614297 0 12 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2476 11:32:52.616355 0 12 20 | B1->B0 | 3a3a 4040 | 0 1 | (0 0) (0 0)
2477 11:32:52.620949 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2478 11:32:52.623952 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2479 11:32:52.630133 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2480 11:32:52.633381 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2481 11:32:52.636683 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2482 11:32:52.642976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2483 11:32:52.646898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2484 11:32:52.650272 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2485 11:32:52.656343 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 11:32:52.660467 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 11:32:52.663372 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 11:32:52.670573 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 11:32:52.673267 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2490 11:32:52.676625 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2491 11:32:52.683602 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2492 11:32:52.686662 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2493 11:32:52.690553 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2494 11:32:52.696838 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2495 11:32:52.700053 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2496 11:32:52.703509 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2497 11:32:52.710154 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2498 11:32:52.713053 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2499 11:32:52.716517 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2500 11:32:52.723350 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2501 11:32:52.723423 Total UI for P1: 0, mck2ui 16
2502 11:32:52.726933 best dqsien dly found for B0: ( 0, 15, 16)
2503 11:32:52.733504 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2504 11:32:52.736902 Total UI for P1: 0, mck2ui 16
2505 11:32:52.739653 best dqsien dly found for B1: ( 0, 15, 20)
2506 11:32:52.743272 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2507 11:32:52.746387 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2508 11:32:52.746450
2509 11:32:52.749978 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2510 11:32:52.752725 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2511 11:32:52.756730 [Gating] SW calibration Done
2512 11:32:52.756796 ==
2513 11:32:52.759587 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 11:32:52.763193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2515 11:32:52.763259 ==
2516 11:32:52.766410 RX Vref Scan: 0
2517 11:32:52.766478
2518 11:32:52.769702 RX Vref 0 -> 0, step: 1
2519 11:32:52.769767
2520 11:32:52.769828 RX Delay -40 -> 252, step: 8
2521 11:32:52.777000 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2522 11:32:52.779946 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2523 11:32:52.782765 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2524 11:32:52.786706 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2525 11:32:52.789407 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2526 11:32:52.796493 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2527 11:32:52.800079 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2528 11:32:52.802969 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2529 11:32:52.806394 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2530 11:32:52.809874 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2531 11:32:52.815975 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2532 11:32:52.819723 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2533 11:32:52.823087 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2534 11:32:52.826774 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2535 11:32:52.829760 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2536 11:32:52.836253 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2537 11:32:52.836326 ==
2538 11:32:52.839416 Dram Type= 6, Freq= 0, CH_0, rank 0
2539 11:32:52.842714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2540 11:32:52.842782 ==
2541 11:32:52.842836 DQS Delay:
2542 11:32:52.846350 DQS0 = 0, DQS1 = 0
2543 11:32:52.846426 DQM Delay:
2544 11:32:52.849344 DQM0 = 115, DQM1 = 106
2545 11:32:52.849418 DQ Delay:
2546 11:32:52.853062 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2547 11:32:52.856026 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2548 11:32:52.859749 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2549 11:32:52.862669 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2550 11:32:52.862744
2551 11:32:52.862801
2552 11:32:52.862855 ==
2553 11:32:52.866526 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 11:32:52.872966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2555 11:32:52.873043 ==
2556 11:32:52.873101
2557 11:32:52.873154
2558 11:32:52.873204 TX Vref Scan disable
2559 11:32:52.876680 == TX Byte 0 ==
2560 11:32:52.879760 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2561 11:32:52.887918 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2562 11:32:52.887993 == TX Byte 1 ==
2563 11:32:52.890128 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2564 11:32:52.896725 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2565 11:32:52.896800 ==
2566 11:32:52.900601 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 11:32:52.903273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2568 11:32:52.903348 ==
2569 11:32:52.914296 TX Vref=22, minBit 9, minWin=24, winSum=411
2570 11:32:52.917275 TX Vref=24, minBit 5, minWin=25, winSum=415
2571 11:32:52.921142 TX Vref=26, minBit 2, minWin=26, winSum=425
2572 11:32:52.924688 TX Vref=28, minBit 5, minWin=26, winSum=428
2573 11:32:52.927257 TX Vref=30, minBit 5, minWin=26, winSum=432
2574 11:32:52.930551 TX Vref=32, minBit 4, minWin=26, winSum=428
2575 11:32:52.938380 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2576 11:32:52.938455
2577 11:32:52.941920 Final TX Range 1 Vref 30
2578 11:32:52.941994
2579 11:32:52.942052 ==
2580 11:32:52.944252 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 11:32:52.947835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2582 11:32:52.947910 ==
2583 11:32:52.947967
2584 11:32:52.950928
2585 11:32:52.951002 TX Vref Scan disable
2586 11:32:52.954497 == TX Byte 0 ==
2587 11:32:52.957562 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2588 11:32:52.960714 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2589 11:32:52.964273 == TX Byte 1 ==
2590 11:32:52.967293 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2591 11:32:52.970962 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2592 11:32:52.971032
2593 11:32:52.974414 [DATLAT]
2594 11:32:52.974488 Freq=1200, CH0 RK0
2595 11:32:52.974547
2596 11:32:52.977603 DATLAT Default: 0xd
2597 11:32:52.977667 0, 0xFFFF, sum = 0
2598 11:32:52.981313 1, 0xFFFF, sum = 0
2599 11:32:52.981378 2, 0xFFFF, sum = 0
2600 11:32:52.984204 3, 0xFFFF, sum = 0
2601 11:32:52.984267 4, 0xFFFF, sum = 0
2602 11:32:52.987608 5, 0xFFFF, sum = 0
2603 11:32:52.987673 6, 0xFFFF, sum = 0
2604 11:32:52.991845 7, 0xFFFF, sum = 0
2605 11:32:52.991922 8, 0xFFFF, sum = 0
2606 11:32:52.994224 9, 0xFFFF, sum = 0
2607 11:32:52.994299 10, 0xFFFF, sum = 0
2608 11:32:52.998093 11, 0x0, sum = 1
2609 11:32:52.998168 12, 0x0, sum = 2
2610 11:32:53.000970 13, 0x0, sum = 3
2611 11:32:53.001046 14, 0x0, sum = 4
2612 11:32:53.004420 best_step = 12
2613 11:32:53.004496
2614 11:32:53.004554 ==
2615 11:32:53.008069 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 11:32:53.011180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2617 11:32:53.011255 ==
2618 11:32:53.014917 RX Vref Scan: 1
2619 11:32:53.014992
2620 11:32:53.015057 Set Vref Range= 32 -> 127
2621 11:32:53.015111
2622 11:32:53.017783 RX Vref 32 -> 127, step: 1
2623 11:32:53.017857
2624 11:32:53.020817 RX Delay -21 -> 252, step: 4
2625 11:32:53.020892
2626 11:32:53.024446 Set Vref, RX VrefLevel [Byte0]: 32
2627 11:32:53.027666 [Byte1]: 32
2628 11:32:53.027740
2629 11:32:53.031981 Set Vref, RX VrefLevel [Byte0]: 33
2630 11:32:53.034699 [Byte1]: 33
2631 11:32:53.038403
2632 11:32:53.038477 Set Vref, RX VrefLevel [Byte0]: 34
2633 11:32:53.041989 [Byte1]: 34
2634 11:32:53.046154
2635 11:32:53.046265 Set Vref, RX VrefLevel [Byte0]: 35
2636 11:32:53.049862 [Byte1]: 35
2637 11:32:53.054447
2638 11:32:53.054521 Set Vref, RX VrefLevel [Byte0]: 36
2639 11:32:53.057456 [Byte1]: 36
2640 11:32:53.062428
2641 11:32:53.062502 Set Vref, RX VrefLevel [Byte0]: 37
2642 11:32:53.065372 [Byte1]: 37
2643 11:32:53.070522
2644 11:32:53.070596 Set Vref, RX VrefLevel [Byte0]: 38
2645 11:32:53.074555 [Byte1]: 38
2646 11:32:53.078296
2647 11:32:53.078371 Set Vref, RX VrefLevel [Byte0]: 39
2648 11:32:53.081804 [Byte1]: 39
2649 11:32:53.086302
2650 11:32:53.086377 Set Vref, RX VrefLevel [Byte0]: 40
2651 11:32:53.089163 [Byte1]: 40
2652 11:32:53.093790
2653 11:32:53.093864 Set Vref, RX VrefLevel [Byte0]: 41
2654 11:32:53.097400 [Byte1]: 41
2655 11:32:53.103211
2656 11:32:53.103286 Set Vref, RX VrefLevel [Byte0]: 42
2657 11:32:53.105537 [Byte1]: 42
2658 11:32:53.109672
2659 11:32:53.109746 Set Vref, RX VrefLevel [Byte0]: 43
2660 11:32:53.113167 [Byte1]: 43
2661 11:32:53.117827
2662 11:32:53.117901 Set Vref, RX VrefLevel [Byte0]: 44
2663 11:32:53.120817 [Byte1]: 44
2664 11:32:53.125711
2665 11:32:53.125786 Set Vref, RX VrefLevel [Byte0]: 45
2666 11:32:53.129232 [Byte1]: 45
2667 11:32:53.133776
2668 11:32:53.133850 Set Vref, RX VrefLevel [Byte0]: 46
2669 11:32:53.137424 [Byte1]: 46
2670 11:32:53.141437
2671 11:32:53.141511 Set Vref, RX VrefLevel [Byte0]: 47
2672 11:32:53.144725 [Byte1]: 47
2673 11:32:53.149591
2674 11:32:53.149665 Set Vref, RX VrefLevel [Byte0]: 48
2675 11:32:53.153579 [Byte1]: 48
2676 11:32:53.158987
2677 11:32:53.159062 Set Vref, RX VrefLevel [Byte0]: 49
2678 11:32:53.161359 [Byte1]: 49
2679 11:32:53.165785
2680 11:32:53.165859 Set Vref, RX VrefLevel [Byte0]: 50
2681 11:32:53.168438 [Byte1]: 50
2682 11:32:53.173194
2683 11:32:53.173278 Set Vref, RX VrefLevel [Byte0]: 51
2684 11:32:53.177406 [Byte1]: 51
2685 11:32:53.181545
2686 11:32:53.181615 Set Vref, RX VrefLevel [Byte0]: 52
2687 11:32:53.184302 [Byte1]: 52
2688 11:32:53.189710
2689 11:32:53.189785 Set Vref, RX VrefLevel [Byte0]: 53
2690 11:32:53.192287 [Byte1]: 53
2691 11:32:53.197524
2692 11:32:53.197598 Set Vref, RX VrefLevel [Byte0]: 54
2693 11:32:53.200170 [Byte1]: 54
2694 11:32:53.205206
2695 11:32:53.205316 Set Vref, RX VrefLevel [Byte0]: 55
2696 11:32:53.208226 [Byte1]: 55
2697 11:32:53.212658
2698 11:32:53.212733 Set Vref, RX VrefLevel [Byte0]: 56
2699 11:32:53.215950 [Byte1]: 56
2700 11:32:53.220479
2701 11:32:53.220554 Set Vref, RX VrefLevel [Byte0]: 57
2702 11:32:53.224007 [Byte1]: 57
2703 11:32:53.228678
2704 11:32:53.228753 Set Vref, RX VrefLevel [Byte0]: 58
2705 11:32:53.232003 [Byte1]: 58
2706 11:32:53.236969
2707 11:32:53.237044 Set Vref, RX VrefLevel [Byte0]: 59
2708 11:32:53.239955 [Byte1]: 59
2709 11:32:53.245081
2710 11:32:53.245148 Set Vref, RX VrefLevel [Byte0]: 60
2711 11:32:53.248125 [Byte1]: 60
2712 11:32:53.252485
2713 11:32:53.252560 Set Vref, RX VrefLevel [Byte0]: 61
2714 11:32:53.255664 [Byte1]: 61
2715 11:32:53.260414
2716 11:32:53.260489 Set Vref, RX VrefLevel [Byte0]: 62
2717 11:32:53.264065 [Byte1]: 62
2718 11:32:53.267936
2719 11:32:53.268011 Set Vref, RX VrefLevel [Byte0]: 63
2720 11:32:53.271871 [Byte1]: 63
2721 11:32:53.276305
2722 11:32:53.276379 Set Vref, RX VrefLevel [Byte0]: 64
2723 11:32:53.279467 [Byte1]: 64
2724 11:32:53.285045
2725 11:32:53.285120 Set Vref, RX VrefLevel [Byte0]: 65
2726 11:32:53.287812 [Byte1]: 65
2727 11:32:53.291742
2728 11:32:53.291817 Set Vref, RX VrefLevel [Byte0]: 66
2729 11:32:53.295335 [Byte1]: 66
2730 11:32:53.299848
2731 11:32:53.299923 Set Vref, RX VrefLevel [Byte0]: 67
2732 11:32:53.303492 [Byte1]: 67
2733 11:32:53.307710
2734 11:32:53.307784 Final RX Vref Byte 0 = 51 to rank0
2735 11:32:53.311091 Final RX Vref Byte 1 = 51 to rank0
2736 11:32:53.315066 Final RX Vref Byte 0 = 51 to rank1
2737 11:32:53.318797 Final RX Vref Byte 1 = 51 to rank1==
2738 11:32:53.321144 Dram Type= 6, Freq= 0, CH_0, rank 0
2739 11:32:53.327548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2740 11:32:53.327627 ==
2741 11:32:53.327684 DQS Delay:
2742 11:32:53.327737 DQS0 = 0, DQS1 = 0
2743 11:32:53.331372 DQM Delay:
2744 11:32:53.331446 DQM0 = 114, DQM1 = 105
2745 11:32:53.335405 DQ Delay:
2746 11:32:53.337891 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =110
2747 11:32:53.341478 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2748 11:32:53.344435 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =98
2749 11:32:53.347426 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2750 11:32:53.347501
2751 11:32:53.347558
2752 11:32:53.354618 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2753 11:32:53.357830 CH0 RK0: MR19=404, MR18=808
2754 11:32:53.364685 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
2755 11:32:53.364760
2756 11:32:53.367849 ----->DramcWriteLeveling(PI) begin...
2757 11:32:53.367925 ==
2758 11:32:53.371417 Dram Type= 6, Freq= 0, CH_0, rank 1
2759 11:32:53.374270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2760 11:32:53.374346 ==
2761 11:32:53.377661 Write leveling (Byte 0): 28 => 28
2762 11:32:53.381221 Write leveling (Byte 1): 25 => 25
2763 11:32:53.384973 DramcWriteLeveling(PI) end<-----
2764 11:32:53.385048
2765 11:32:53.385106 ==
2766 11:32:53.387690 Dram Type= 6, Freq= 0, CH_0, rank 1
2767 11:32:53.394483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2768 11:32:53.394562 ==
2769 11:32:53.394621 [Gating] SW mode calibration
2770 11:32:53.404204 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2771 11:32:53.407356 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2772 11:32:53.410751 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2773 11:32:53.417543 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2774 11:32:53.420830 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2775 11:32:53.424055 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2776 11:32:53.431198 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2777 11:32:53.434173 0 11 20 | B1->B0 | 2c2c 2424 | 0 0 | (0 1) (1 0)
2778 11:32:53.437584 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2779 11:32:53.444342 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2780 11:32:53.448120 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2781 11:32:53.451621 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2782 11:32:53.457960 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2783 11:32:53.460985 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2784 11:32:53.464468 0 12 16 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2785 11:32:53.470999 0 12 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2786 11:32:53.474178 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2787 11:32:53.478934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2788 11:32:53.484662 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2789 11:32:53.488075 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2790 11:32:53.490812 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2791 11:32:53.494241 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2792 11:32:53.500580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2793 11:32:53.504043 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2794 11:32:53.507572 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 11:32:53.514274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 11:32:53.518372 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2797 11:32:53.520866 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2798 11:32:53.527437 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2799 11:32:53.530882 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2800 11:32:53.534181 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2801 11:32:53.541126 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2802 11:32:53.544809 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2803 11:32:53.547682 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2804 11:32:53.554007 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2805 11:32:53.558083 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2806 11:32:53.560969 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2807 11:32:53.567051 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2808 11:32:53.570717 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2809 11:32:53.574674 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2810 11:32:53.580956 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2811 11:32:53.581032 Total UI for P1: 0, mck2ui 16
2812 11:32:53.587398 best dqsien dly found for B0: ( 0, 15, 18)
2813 11:32:53.587474 Total UI for P1: 0, mck2ui 16
2814 11:32:53.590689 best dqsien dly found for B1: ( 0, 15, 18)
2815 11:32:53.597285 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2816 11:32:53.600644 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2817 11:32:53.600720
2818 11:32:53.604090 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2819 11:32:53.607717 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2820 11:32:53.611027 [Gating] SW calibration Done
2821 11:32:53.611102 ==
2822 11:32:53.614411 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 11:32:53.617430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2824 11:32:53.617506 ==
2825 11:32:53.620578 RX Vref Scan: 0
2826 11:32:53.620652
2827 11:32:53.620710 RX Vref 0 -> 0, step: 1
2828 11:32:53.620764
2829 11:32:53.623823 RX Delay -40 -> 252, step: 8
2830 11:32:53.627670 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2831 11:32:53.634774 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2832 11:32:53.637430 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2833 11:32:53.641181 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2834 11:32:53.643946 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2835 11:32:53.647312 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2836 11:32:53.654263 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2837 11:32:53.657363 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2838 11:32:53.660593 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2839 11:32:53.663910 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2840 11:32:53.667461 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2841 11:32:53.670974 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2842 11:32:53.677103 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2843 11:32:53.680935 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2844 11:32:53.683914 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2845 11:32:53.687371 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2846 11:32:53.687447 ==
2847 11:32:53.690802 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 11:32:53.697527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 11:32:53.697602 ==
2850 11:32:53.697660 DQS Delay:
2851 11:32:53.700478 DQS0 = 0, DQS1 = 0
2852 11:32:53.700552 DQM Delay:
2853 11:32:53.700610 DQM0 = 114, DQM1 = 106
2854 11:32:53.704580 DQ Delay:
2855 11:32:53.707232 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2856 11:32:53.710269 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2857 11:32:53.714053 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2858 11:32:53.717510 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2859 11:32:53.717585
2860 11:32:53.717644
2861 11:32:53.717697 ==
2862 11:32:53.720154 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 11:32:53.724112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2864 11:32:53.727121 ==
2865 11:32:53.727195
2866 11:32:53.727253
2867 11:32:53.727307 TX Vref Scan disable
2868 11:32:53.730397 == TX Byte 0 ==
2869 11:32:53.734090 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2870 11:32:53.737630 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2871 11:32:53.741185 == TX Byte 1 ==
2872 11:32:53.744468 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2873 11:32:53.746977 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2874 11:32:53.747051 ==
2875 11:32:53.750261 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 11:32:53.757584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2877 11:32:53.757660 ==
2878 11:32:53.768767 TX Vref=22, minBit 8, minWin=25, winSum=416
2879 11:32:53.772021 TX Vref=24, minBit 1, minWin=26, winSum=428
2880 11:32:53.775020 TX Vref=26, minBit 8, minWin=26, winSum=430
2881 11:32:53.778065 TX Vref=28, minBit 9, minWin=26, winSum=435
2882 11:32:53.781871 TX Vref=30, minBit 9, minWin=26, winSum=434
2883 11:32:53.784813 TX Vref=32, minBit 8, minWin=25, winSum=432
2884 11:32:53.790973 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
2885 11:32:53.791048
2886 11:32:53.795024 Final TX Range 1 Vref 28
2887 11:32:53.795099
2888 11:32:53.795157 ==
2889 11:32:53.797725 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 11:32:53.801637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2891 11:32:53.801741 ==
2892 11:32:53.801815
2893 11:32:53.804995
2894 11:32:53.805069 TX Vref Scan disable
2895 11:32:53.809069 == TX Byte 0 ==
2896 11:32:53.811281 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2897 11:32:53.814779 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2898 11:32:53.818183 == TX Byte 1 ==
2899 11:32:53.821467 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2900 11:32:53.824339 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2901 11:32:53.824414
2902 11:32:53.827682 [DATLAT]
2903 11:32:53.827757 Freq=1200, CH0 RK1
2904 11:32:53.827816
2905 11:32:53.831016 DATLAT Default: 0xc
2906 11:32:53.831126 0, 0xFFFF, sum = 0
2907 11:32:53.835116 1, 0xFFFF, sum = 0
2908 11:32:53.835192 2, 0xFFFF, sum = 0
2909 11:32:53.837937 3, 0xFFFF, sum = 0
2910 11:32:53.838013 4, 0xFFFF, sum = 0
2911 11:32:53.841284 5, 0xFFFF, sum = 0
2912 11:32:53.841386 6, 0xFFFF, sum = 0
2913 11:32:53.844937 7, 0xFFFF, sum = 0
2914 11:32:53.845013 8, 0xFFFF, sum = 0
2915 11:32:53.847722 9, 0xFFFF, sum = 0
2916 11:32:53.847798 10, 0xFFFF, sum = 0
2917 11:32:53.851584 11, 0x0, sum = 1
2918 11:32:53.851661 12, 0x0, sum = 2
2919 11:32:53.854925 13, 0x0, sum = 3
2920 11:32:53.855001 14, 0x0, sum = 4
2921 11:32:53.858080 best_step = 12
2922 11:32:53.858155
2923 11:32:53.858213 ==
2924 11:32:53.861751 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 11:32:53.864529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2926 11:32:53.864605 ==
2927 11:32:53.868478 RX Vref Scan: 0
2928 11:32:53.868568
2929 11:32:53.868627 RX Vref 0 -> 0, step: 1
2930 11:32:53.868681
2931 11:32:53.871840 RX Delay -21 -> 252, step: 4
2932 11:32:53.878485 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2933 11:32:53.881429 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2934 11:32:53.884677 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2935 11:32:53.889016 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2936 11:32:53.891300 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2937 11:32:53.898218 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2938 11:32:53.901358 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2939 11:32:53.905062 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2940 11:32:53.907750 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2941 11:32:53.911038 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2942 11:32:53.918571 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2943 11:32:53.921444 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2944 11:32:53.924909 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2945 11:32:53.928230 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2946 11:32:53.931327 iDelay=199, Bit 14, Center 114 (51 ~ 178) 128
2947 11:32:53.938257 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2948 11:32:53.938333 ==
2949 11:32:53.941176 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 11:32:53.944609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2951 11:32:53.944686 ==
2952 11:32:53.944744 DQS Delay:
2953 11:32:53.948545 DQS0 = 0, DQS1 = 0
2954 11:32:53.948620 DQM Delay:
2955 11:32:53.951306 DQM0 = 115, DQM1 = 105
2956 11:32:53.951381 DQ Delay:
2957 11:32:53.954461 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2958 11:32:53.959009 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =124
2959 11:32:53.961802 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2960 11:32:53.964873 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =114
2961 11:32:53.964963
2962 11:32:53.965022
2963 11:32:53.974497 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2964 11:32:53.977958 CH0 RK1: MR19=404, MR18=1010
2965 11:32:53.981451 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2966 11:32:53.984712 [RxdqsGatingPostProcess] freq 1200
2967 11:32:53.991369 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2968 11:32:53.994684 Pre-setting of DQS Precalculation
2969 11:32:53.998034 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2970 11:32:53.998109 ==
2971 11:32:54.001841 Dram Type= 6, Freq= 0, CH_1, rank 0
2972 11:32:54.008454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2973 11:32:54.008544 ==
2974 11:32:54.011738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2975 11:32:54.017710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2976 11:32:54.027511 [CA 0] Center 37 (7~68) winsize 62
2977 11:32:54.031295 [CA 1] Center 37 (7~68) winsize 62
2978 11:32:54.033152 [CA 2] Center 34 (4~65) winsize 62
2979 11:32:54.036701 [CA 3] Center 33 (3~64) winsize 62
2980 11:32:54.039865 [CA 4] Center 32 (2~63) winsize 62
2981 11:32:54.043042 [CA 5] Center 32 (2~63) winsize 62
2982 11:32:54.043110
2983 11:32:54.046371 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2984 11:32:54.046446
2985 11:32:54.049994 [CATrainingPosCal] consider 1 rank data
2986 11:32:54.053285 u2DelayCellTimex100 = 270/100 ps
2987 11:32:54.056770 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2988 11:32:54.060633 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2989 11:32:54.066958 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2990 11:32:54.070865 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2991 11:32:54.073498 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2992 11:32:54.076603 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2993 11:32:54.076693
2994 11:32:54.080381 CA PerBit enable=1, Macro0, CA PI delay=32
2995 11:32:54.080456
2996 11:32:54.083651 [CBTSetCACLKResult] CA Dly = 32
2997 11:32:54.083726 CS Dly: 5 (0~36)
2998 11:32:54.086563 ==
2999 11:32:54.086639 Dram Type= 6, Freq= 0, CH_1, rank 1
3000 11:32:54.093178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3001 11:32:54.093297 ==
3002 11:32:54.096229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3003 11:32:54.103698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3004 11:32:54.112390 [CA 0] Center 37 (7~68) winsize 62
3005 11:32:54.115521 [CA 1] Center 37 (7~68) winsize 62
3006 11:32:54.118953 [CA 2] Center 34 (3~65) winsize 63
3007 11:32:54.121937 [CA 3] Center 33 (3~64) winsize 62
3008 11:32:54.125645 [CA 4] Center 32 (2~63) winsize 62
3009 11:32:54.128484 [CA 5] Center 32 (2~63) winsize 62
3010 11:32:54.128559
3011 11:32:54.132486 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3012 11:32:54.132561
3013 11:32:54.135844 [CATrainingPosCal] consider 2 rank data
3014 11:32:54.138552 u2DelayCellTimex100 = 270/100 ps
3015 11:32:54.141842 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3016 11:32:54.145453 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3017 11:32:54.151699 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3018 11:32:54.155671 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3019 11:32:54.158983 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3020 11:32:54.161941 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3021 11:32:54.162017
3022 11:32:54.165405 CA PerBit enable=1, Macro0, CA PI delay=32
3023 11:32:54.165482
3024 11:32:54.169024 [CBTSetCACLKResult] CA Dly = 32
3025 11:32:54.169127 CS Dly: 6 (0~38)
3026 11:32:54.169221
3027 11:32:54.173493 ----->DramcWriteLeveling(PI) begin...
3028 11:32:54.175783 ==
3029 11:32:54.175859 Dram Type= 6, Freq= 0, CH_1, rank 0
3030 11:32:54.182608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3031 11:32:54.182679 ==
3032 11:32:54.185250 Write leveling (Byte 0): 21 => 21
3033 11:32:54.188810 Write leveling (Byte 1): 21 => 21
3034 11:32:54.191867 DramcWriteLeveling(PI) end<-----
3035 11:32:54.191942
3036 11:32:54.192000 ==
3037 11:32:54.195443 Dram Type= 6, Freq= 0, CH_1, rank 0
3038 11:32:54.198739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3039 11:32:54.198814 ==
3040 11:32:54.202023 [Gating] SW mode calibration
3041 11:32:54.209275 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3042 11:32:54.211919 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3043 11:32:54.218617 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3044 11:32:54.222428 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3045 11:32:54.225469 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3046 11:32:54.232288 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3047 11:32:54.235657 0 11 16 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 0)
3048 11:32:54.239020 0 11 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3049 11:32:54.245483 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3050 11:32:54.249562 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3051 11:32:54.251883 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3052 11:32:54.258963 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3053 11:32:54.262083 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3054 11:32:54.265299 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3055 11:32:54.272118 0 12 16 | B1->B0 | 2f2f 4444 | 1 0 | (0 0) (1 1)
3056 11:32:54.275462 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3057 11:32:54.279080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3058 11:32:54.285641 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3059 11:32:54.288623 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3060 11:32:54.291931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3061 11:32:54.295310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3062 11:32:54.302094 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3063 11:32:54.305385 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3064 11:32:54.309429 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3065 11:32:54.316175 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 11:32:54.318780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 11:32:54.322670 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3068 11:32:54.328530 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3069 11:32:54.332143 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3070 11:32:54.335932 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3071 11:32:54.341848 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3072 11:32:54.345757 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3073 11:32:54.348840 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3074 11:32:54.355372 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3075 11:32:54.358834 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3076 11:32:54.362377 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3077 11:32:54.368970 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3078 11:32:54.371948 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3079 11:32:54.375489 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3080 11:32:54.382429 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3081 11:32:54.382505 Total UI for P1: 0, mck2ui 16
3082 11:32:54.385815 best dqsien dly found for B0: ( 0, 15, 14)
3083 11:32:54.392261 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3084 11:32:54.395286 Total UI for P1: 0, mck2ui 16
3085 11:32:54.398352 best dqsien dly found for B1: ( 0, 15, 18)
3086 11:32:54.402108 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3087 11:32:54.404938 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3088 11:32:54.405012
3089 11:32:54.408854 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3090 11:32:54.411709 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3091 11:32:54.415022 [Gating] SW calibration Done
3092 11:32:54.415097 ==
3093 11:32:54.418319 Dram Type= 6, Freq= 0, CH_1, rank 0
3094 11:32:54.422296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3095 11:32:54.422371 ==
3096 11:32:54.425207 RX Vref Scan: 0
3097 11:32:54.425304
3098 11:32:54.428812 RX Vref 0 -> 0, step: 1
3099 11:32:54.428886
3100 11:32:54.428944 RX Delay -40 -> 252, step: 8
3101 11:32:54.435068 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3102 11:32:54.438447 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3103 11:32:54.441709 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3104 11:32:54.445070 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3105 11:32:54.448926 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3106 11:32:54.455090 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3107 11:32:54.458602 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3108 11:32:54.461721 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3109 11:32:54.465213 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3110 11:32:54.468968 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3111 11:32:54.475904 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3112 11:32:54.478419 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3113 11:32:54.481590 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3114 11:32:54.485025 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3115 11:32:54.488440 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3116 11:32:54.494866 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3117 11:32:54.494942 ==
3118 11:32:54.498439 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 11:32:54.501701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 11:32:54.501777 ==
3121 11:32:54.501836 DQS Delay:
3122 11:32:54.505107 DQS0 = 0, DQS1 = 0
3123 11:32:54.505182 DQM Delay:
3124 11:32:54.508957 DQM0 = 116, DQM1 = 108
3125 11:32:54.509032 DQ Delay:
3126 11:32:54.511788 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3127 11:32:54.515116 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3128 11:32:54.518471 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =95
3129 11:32:54.521553 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3130 11:32:54.521627
3131 11:32:54.521685
3132 11:32:54.525165 ==
3133 11:32:54.525262 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 11:32:54.531805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3135 11:32:54.531880 ==
3136 11:32:54.531938
3137 11:32:54.531992
3138 11:32:54.535085 TX Vref Scan disable
3139 11:32:54.535159 == TX Byte 0 ==
3140 11:32:54.538450 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3141 11:32:54.545033 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3142 11:32:54.545134 == TX Byte 1 ==
3143 11:32:54.548508 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3144 11:32:54.554915 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3145 11:32:54.554991 ==
3146 11:32:54.558392 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 11:32:54.561596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3148 11:32:54.561671 ==
3149 11:32:54.573327 TX Vref=22, minBit 9, minWin=25, winSum=417
3150 11:32:54.576395 TX Vref=24, minBit 8, minWin=25, winSum=419
3151 11:32:54.579825 TX Vref=26, minBit 9, minWin=25, winSum=425
3152 11:32:54.583949 TX Vref=28, minBit 0, minWin=26, winSum=430
3153 11:32:54.586613 TX Vref=30, minBit 9, minWin=26, winSum=431
3154 11:32:54.590538 TX Vref=32, minBit 0, minWin=26, winSum=429
3155 11:32:54.596604 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 30
3156 11:32:54.596680
3157 11:32:54.599772 Final TX Range 1 Vref 30
3158 11:32:54.599846
3159 11:32:54.599904 ==
3160 11:32:54.603382 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 11:32:54.606149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3162 11:32:54.606225 ==
3163 11:32:54.606283
3164 11:32:54.609381
3165 11:32:54.609456 TX Vref Scan disable
3166 11:32:54.612812 == TX Byte 0 ==
3167 11:32:54.616100 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3168 11:32:54.620521 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3169 11:32:54.622885 == TX Byte 1 ==
3170 11:32:54.626638 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3171 11:32:54.629764 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3172 11:32:54.632849
3173 11:32:54.632923 [DATLAT]
3174 11:32:54.632981 Freq=1200, CH1 RK0
3175 11:32:54.633036
3176 11:32:54.636097 DATLAT Default: 0xd
3177 11:32:54.636172 0, 0xFFFF, sum = 0
3178 11:32:54.640605 1, 0xFFFF, sum = 0
3179 11:32:54.640682 2, 0xFFFF, sum = 0
3180 11:32:54.643104 3, 0xFFFF, sum = 0
3181 11:32:54.643180 4, 0xFFFF, sum = 0
3182 11:32:54.646450 5, 0xFFFF, sum = 0
3183 11:32:54.649477 6, 0xFFFF, sum = 0
3184 11:32:54.649553 7, 0xFFFF, sum = 0
3185 11:32:54.652723 8, 0xFFFF, sum = 0
3186 11:32:54.652798 9, 0xFFFF, sum = 0
3187 11:32:54.656069 10, 0xFFFF, sum = 0
3188 11:32:54.656145 11, 0x0, sum = 1
3189 11:32:54.659132 12, 0x0, sum = 2
3190 11:32:54.659209 13, 0x0, sum = 3
3191 11:32:54.659268 14, 0x0, sum = 4
3192 11:32:54.662582 best_step = 12
3193 11:32:54.662657
3194 11:32:54.662715 ==
3195 11:32:54.666216 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 11:32:54.669406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3197 11:32:54.669481 ==
3198 11:32:54.672956 RX Vref Scan: 1
3199 11:32:54.673030
3200 11:32:54.676123 Set Vref Range= 32 -> 127
3201 11:32:54.676198
3202 11:32:54.676257 RX Vref 32 -> 127, step: 1
3203 11:32:54.676311
3204 11:32:54.679176 RX Delay -29 -> 252, step: 4
3205 11:32:54.679250
3206 11:32:54.682511 Set Vref, RX VrefLevel [Byte0]: 32
3207 11:32:54.685394 [Byte1]: 32
3208 11:32:54.690140
3209 11:32:54.690214 Set Vref, RX VrefLevel [Byte0]: 33
3210 11:32:54.692908 [Byte1]: 33
3211 11:32:54.697575
3212 11:32:54.697650 Set Vref, RX VrefLevel [Byte0]: 34
3213 11:32:54.701187 [Byte1]: 34
3214 11:32:54.705214
3215 11:32:54.705298 Set Vref, RX VrefLevel [Byte0]: 35
3216 11:32:54.708641 [Byte1]: 35
3217 11:32:54.713260
3218 11:32:54.713348 Set Vref, RX VrefLevel [Byte0]: 36
3219 11:32:54.716890 [Byte1]: 36
3220 11:32:54.721063
3221 11:32:54.721138 Set Vref, RX VrefLevel [Byte0]: 37
3222 11:32:54.725006 [Byte1]: 37
3223 11:32:54.729729
3224 11:32:54.729804 Set Vref, RX VrefLevel [Byte0]: 38
3225 11:32:54.732851 [Byte1]: 38
3226 11:32:54.736946
3227 11:32:54.737021 Set Vref, RX VrefLevel [Byte0]: 39
3228 11:32:54.740909 [Byte1]: 39
3229 11:32:54.745388
3230 11:32:54.745463 Set Vref, RX VrefLevel [Byte0]: 40
3231 11:32:54.748786 [Byte1]: 40
3232 11:32:54.753766
3233 11:32:54.753840 Set Vref, RX VrefLevel [Byte0]: 41
3234 11:32:54.757280 [Byte1]: 41
3235 11:32:54.761062
3236 11:32:54.761136 Set Vref, RX VrefLevel [Byte0]: 42
3237 11:32:54.765095 [Byte1]: 42
3238 11:32:54.769008
3239 11:32:54.769082 Set Vref, RX VrefLevel [Byte0]: 43
3240 11:32:54.772203 [Byte1]: 43
3241 11:32:54.776924
3242 11:32:54.776999 Set Vref, RX VrefLevel [Byte0]: 44
3243 11:32:54.780324 [Byte1]: 44
3244 11:32:54.784505
3245 11:32:54.788423 Set Vref, RX VrefLevel [Byte0]: 45
3246 11:32:54.791512 [Byte1]: 45
3247 11:32:54.791587
3248 11:32:54.794474 Set Vref, RX VrefLevel [Byte0]: 46
3249 11:32:54.798560 [Byte1]: 46
3250 11:32:54.798635
3251 11:32:54.801746 Set Vref, RX VrefLevel [Byte0]: 47
3252 11:32:54.804312 [Byte1]: 47
3253 11:32:54.808894
3254 11:32:54.808968 Set Vref, RX VrefLevel [Byte0]: 48
3255 11:32:54.811854 [Byte1]: 48
3256 11:32:54.817700
3257 11:32:54.817776 Set Vref, RX VrefLevel [Byte0]: 49
3258 11:32:54.820415 [Byte1]: 49
3259 11:32:54.824729
3260 11:32:54.824803 Set Vref, RX VrefLevel [Byte0]: 50
3261 11:32:54.828420 [Byte1]: 50
3262 11:32:54.832370
3263 11:32:54.832445 Set Vref, RX VrefLevel [Byte0]: 51
3264 11:32:54.836053 [Byte1]: 51
3265 11:32:54.840493
3266 11:32:54.840567 Set Vref, RX VrefLevel [Byte0]: 52
3267 11:32:54.843921 [Byte1]: 52
3268 11:32:54.848904
3269 11:32:54.848978 Set Vref, RX VrefLevel [Byte0]: 53
3270 11:32:54.852064 [Byte1]: 53
3271 11:32:54.856167
3272 11:32:54.856241 Set Vref, RX VrefLevel [Byte0]: 54
3273 11:32:54.859773 [Byte1]: 54
3274 11:32:54.864788
3275 11:32:54.864862 Set Vref, RX VrefLevel [Byte0]: 55
3276 11:32:54.867776 [Byte1]: 55
3277 11:32:54.872642
3278 11:32:54.872717 Set Vref, RX VrefLevel [Byte0]: 56
3279 11:32:54.875464 [Byte1]: 56
3280 11:32:54.880628
3281 11:32:54.880703 Set Vref, RX VrefLevel [Byte0]: 57
3282 11:32:54.883771 [Byte1]: 57
3283 11:32:54.888161
3284 11:32:54.888236 Set Vref, RX VrefLevel [Byte0]: 58
3285 11:32:54.892903 [Byte1]: 58
3286 11:32:54.896723
3287 11:32:54.896798 Set Vref, RX VrefLevel [Byte0]: 59
3288 11:32:54.900059 [Byte1]: 59
3289 11:32:54.904689
3290 11:32:54.904764 Set Vref, RX VrefLevel [Byte0]: 60
3291 11:32:54.907526 [Byte1]: 60
3292 11:32:54.913613
3293 11:32:54.913688 Set Vref, RX VrefLevel [Byte0]: 61
3294 11:32:54.915379 [Byte1]: 61
3295 11:32:54.920256
3296 11:32:54.920334 Set Vref, RX VrefLevel [Byte0]: 62
3297 11:32:54.923487 [Byte1]: 62
3298 11:32:54.928224
3299 11:32:54.928299 Set Vref, RX VrefLevel [Byte0]: 63
3300 11:32:54.931070 [Byte1]: 63
3301 11:32:54.936201
3302 11:32:54.936275 Set Vref, RX VrefLevel [Byte0]: 64
3303 11:32:54.939076 [Byte1]: 64
3304 11:32:54.944358
3305 11:32:54.944433 Set Vref, RX VrefLevel [Byte0]: 65
3306 11:32:54.947081 [Byte1]: 65
3307 11:32:54.952498
3308 11:32:54.952572 Set Vref, RX VrefLevel [Byte0]: 66
3309 11:32:54.955145 [Byte1]: 66
3310 11:32:54.960553
3311 11:32:54.960628 Final RX Vref Byte 0 = 52 to rank0
3312 11:32:54.963019 Final RX Vref Byte 1 = 52 to rank0
3313 11:32:54.967175 Final RX Vref Byte 0 = 52 to rank1
3314 11:32:54.970182 Final RX Vref Byte 1 = 52 to rank1==
3315 11:32:54.973218 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 11:32:54.979735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3317 11:32:54.979815 ==
3318 11:32:54.979874 DQS Delay:
3319 11:32:54.979928 DQS0 = 0, DQS1 = 0
3320 11:32:54.982927 DQM Delay:
3321 11:32:54.983002 DQM0 = 115, DQM1 = 105
3322 11:32:54.986082 DQ Delay:
3323 11:32:54.989473 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3324 11:32:54.993365 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3325 11:32:54.996692 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3326 11:32:54.999285 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3327 11:32:54.999360
3328 11:32:54.999418
3329 11:32:55.009950 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x404, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
3330 11:32:55.010030 CH1 RK0: MR19=404, MR18=1E1E
3331 11:32:55.017174 CH1_RK0: MR19=0x404, MR18=0x1E1E, DQSOSC=398, MR23=63, INC=41, DEC=27
3332 11:32:55.017300
3333 11:32:55.019692 ----->DramcWriteLeveling(PI) begin...
3334 11:32:55.019768 ==
3335 11:32:55.022510 Dram Type= 6, Freq= 0, CH_1, rank 1
3336 11:32:55.029374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3337 11:32:55.029449 ==
3338 11:32:55.033151 Write leveling (Byte 0): 21 => 21
3339 11:32:55.033283 Write leveling (Byte 1): 21 => 21
3340 11:32:55.036415 DramcWriteLeveling(PI) end<-----
3341 11:32:55.036489
3342 11:32:55.039342 ==
3343 11:32:55.039417 Dram Type= 6, Freq= 0, CH_1, rank 1
3344 11:32:55.045865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3345 11:32:55.045940 ==
3346 11:32:55.049271 [Gating] SW mode calibration
3347 11:32:55.055768 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3348 11:32:55.059086 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3349 11:32:55.065532 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3350 11:32:55.068901 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3351 11:32:55.072233 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3352 11:32:55.078793 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3353 11:32:55.082109 0 11 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
3354 11:32:55.085565 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3355 11:32:55.092291 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3356 11:32:55.095152 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3357 11:32:55.098639 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3358 11:32:55.105868 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3359 11:32:55.108407 0 12 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3360 11:32:55.112059 0 12 12 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
3361 11:32:55.118244 0 12 16 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
3362 11:32:55.122121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3363 11:32:55.125789 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3364 11:32:55.132561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3365 11:32:55.134808 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3366 11:32:55.138526 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3367 11:32:55.145535 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3368 11:32:55.148157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3369 11:32:55.152419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3370 11:32:55.158728 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3371 11:32:55.161907 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3372 11:32:55.165135 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3373 11:32:55.171256 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3374 11:32:55.174877 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3375 11:32:55.178017 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3376 11:32:55.184858 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3377 11:32:55.188143 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3378 11:32:55.191952 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3379 11:32:55.194955 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3380 11:32:55.201223 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3381 11:32:55.204779 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3382 11:32:55.208720 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3383 11:32:55.214962 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3384 11:32:55.217936 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3385 11:32:55.221169 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3386 11:32:55.228409 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3387 11:32:55.231359 Total UI for P1: 0, mck2ui 16
3388 11:32:55.234694 best dqsien dly found for B0: ( 0, 15, 14)
3389 11:32:55.237771 Total UI for P1: 0, mck2ui 16
3390 11:32:55.240912 best dqsien dly found for B1: ( 0, 15, 16)
3391 11:32:55.245028 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3392 11:32:55.247781 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3393 11:32:55.247879
3394 11:32:55.251299 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3395 11:32:55.254311 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3396 11:32:55.258053 [Gating] SW calibration Done
3397 11:32:55.258127 ==
3398 11:32:55.260965 Dram Type= 6, Freq= 0, CH_1, rank 1
3399 11:32:55.264260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3400 11:32:55.264335 ==
3401 11:32:55.268256 RX Vref Scan: 0
3402 11:32:55.268344
3403 11:32:55.271007 RX Vref 0 -> 0, step: 1
3404 11:32:55.271082
3405 11:32:55.271140 RX Delay -40 -> 252, step: 8
3406 11:32:55.277660 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3407 11:32:55.281015 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3408 11:32:55.284127 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3409 11:32:55.287604 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3410 11:32:55.290905 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3411 11:32:55.297627 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3412 11:32:55.301530 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3413 11:32:55.304205 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3414 11:32:55.308061 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3415 11:32:55.311078 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3416 11:32:55.317738 iDelay=200, Bit 10, Center 103 (24 ~ 183) 160
3417 11:32:55.321547 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3418 11:32:55.324397 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3419 11:32:55.327543 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3420 11:32:55.330542 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3421 11:32:55.337741 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3422 11:32:55.337818 ==
3423 11:32:55.341026 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 11:32:55.344496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 11:32:55.344572 ==
3426 11:32:55.344631 DQS Delay:
3427 11:32:55.347511 DQS0 = 0, DQS1 = 0
3428 11:32:55.347587 DQM Delay:
3429 11:32:55.350569 DQM0 = 115, DQM1 = 106
3430 11:32:55.350645 DQ Delay:
3431 11:32:55.353948 DQ0 =115, DQ1 =111, DQ2 =107, DQ3 =115
3432 11:32:55.357167 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3433 11:32:55.361353 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3434 11:32:55.364367 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3435 11:32:55.364466
3436 11:32:55.364556
3437 11:32:55.367047 ==
3438 11:32:55.370482 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 11:32:55.373784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3440 11:32:55.373860 ==
3441 11:32:55.373919
3442 11:32:55.373973
3443 11:32:55.377142 TX Vref Scan disable
3444 11:32:55.377217 == TX Byte 0 ==
3445 11:32:55.380717 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3446 11:32:55.387182 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3447 11:32:55.387259 == TX Byte 1 ==
3448 11:32:55.390512 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3449 11:32:55.397515 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3450 11:32:55.397591 ==
3451 11:32:55.400105 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 11:32:55.403949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3453 11:32:55.404025 ==
3454 11:32:55.415249 TX Vref=22, minBit 9, minWin=25, winSum=421
3455 11:32:55.419646 TX Vref=24, minBit 9, minWin=25, winSum=426
3456 11:32:55.421911 TX Vref=26, minBit 3, minWin=26, winSum=429
3457 11:32:55.425206 TX Vref=28, minBit 4, minWin=26, winSum=429
3458 11:32:55.428556 TX Vref=30, minBit 3, minWin=26, winSum=429
3459 11:32:55.432635 TX Vref=32, minBit 9, minWin=26, winSum=433
3460 11:32:55.438445 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3461 11:32:55.438522
3462 11:32:55.441836 Final TX Range 1 Vref 32
3463 11:32:55.441911
3464 11:32:55.441969 ==
3465 11:32:55.445406 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 11:32:55.448675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3467 11:32:55.452150 ==
3468 11:32:55.452225
3469 11:32:55.452283
3470 11:32:55.452336 TX Vref Scan disable
3471 11:32:55.454851 == TX Byte 0 ==
3472 11:32:55.458844 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3473 11:32:55.465092 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3474 11:32:55.465169 == TX Byte 1 ==
3475 11:32:55.468283 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3476 11:32:55.474718 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3477 11:32:55.474793
3478 11:32:55.474851 [DATLAT]
3479 11:32:55.474905 Freq=1200, CH1 RK1
3480 11:32:55.474956
3481 11:32:55.479890 DATLAT Default: 0xc
3482 11:32:55.479965 0, 0xFFFF, sum = 0
3483 11:32:55.481601 1, 0xFFFF, sum = 0
3484 11:32:55.484822 2, 0xFFFF, sum = 0
3485 11:32:55.484897 3, 0xFFFF, sum = 0
3486 11:32:55.487981 4, 0xFFFF, sum = 0
3487 11:32:55.488057 5, 0xFFFF, sum = 0
3488 11:32:55.491519 6, 0xFFFF, sum = 0
3489 11:32:55.491596 7, 0xFFFF, sum = 0
3490 11:32:55.494544 8, 0xFFFF, sum = 0
3491 11:32:55.494620 9, 0xFFFF, sum = 0
3492 11:32:55.498649 10, 0xFFFF, sum = 0
3493 11:32:55.498726 11, 0x0, sum = 1
3494 11:32:55.501123 12, 0x0, sum = 2
3495 11:32:55.501201 13, 0x0, sum = 3
3496 11:32:55.504495 14, 0x0, sum = 4
3497 11:32:55.504571 best_step = 12
3498 11:32:55.504629
3499 11:32:55.504683 ==
3500 11:32:55.508573 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 11:32:55.511070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3502 11:32:55.515578 ==
3503 11:32:55.515653 RX Vref Scan: 0
3504 11:32:55.515711
3505 11:32:55.517916 RX Vref 0 -> 0, step: 1
3506 11:32:55.517990
3507 11:32:55.518048 RX Delay -21 -> 252, step: 4
3508 11:32:55.525923 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3509 11:32:55.528923 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3510 11:32:55.532236 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3511 11:32:55.535762 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3512 11:32:55.538789 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3513 11:32:55.545657 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3514 11:32:55.548379 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3515 11:32:55.551693 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3516 11:32:55.555701 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3517 11:32:55.559027 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3518 11:32:55.565964 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3519 11:32:55.568559 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3520 11:32:55.572902 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3521 11:32:55.575624 iDelay=199, Bit 13, Center 112 (43 ~ 182) 140
3522 11:32:55.581626 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3523 11:32:55.585451 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3524 11:32:55.585527 ==
3525 11:32:55.588837 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 11:32:55.591641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3527 11:32:55.591717 ==
3528 11:32:55.591776 DQS Delay:
3529 11:32:55.595501 DQS0 = 0, DQS1 = 0
3530 11:32:55.595576 DQM Delay:
3531 11:32:55.598903 DQM0 = 114, DQM1 = 104
3532 11:32:55.598979 DQ Delay:
3533 11:32:55.601925 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3534 11:32:55.604892 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3535 11:32:55.608397 DQ8 =88, DQ9 =92, DQ10 =106, DQ11 =98
3536 11:32:55.611820 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =110
3537 11:32:55.614740
3538 11:32:55.614814
3539 11:32:55.621870 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3540 11:32:55.624765 CH1 RK1: MR19=404, MR18=D0D
3541 11:32:55.631452 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3542 11:32:55.631537 [RxdqsGatingPostProcess] freq 1200
3543 11:32:55.638174 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3544 11:32:55.641639 Pre-setting of DQS Precalculation
3545 11:32:55.648512 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3546 11:32:55.654917 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3547 11:32:55.661514 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3548 11:32:55.661590
3549 11:32:55.661649
3550 11:32:55.664664 [Calibration Summary] 2400 Mbps
3551 11:32:55.664739 CH 0, Rank 0
3552 11:32:55.667840 SW Impedance : PASS
3553 11:32:55.671262 DUTY Scan : NO K
3554 11:32:55.671338 ZQ Calibration : PASS
3555 11:32:55.674611 Jitter Meter : NO K
3556 11:32:55.677925 CBT Training : PASS
3557 11:32:55.678001 Write leveling : PASS
3558 11:32:55.681431 RX DQS gating : PASS
3559 11:32:55.681507 RX DQ/DQS(RDDQC) : PASS
3560 11:32:55.684291 TX DQ/DQS : PASS
3561 11:32:55.687912 RX DATLAT : PASS
3562 11:32:55.687987 RX DQ/DQS(Engine): PASS
3563 11:32:55.692161 TX OE : NO K
3564 11:32:55.692237 All Pass.
3565 11:32:55.692296
3566 11:32:55.694276 CH 0, Rank 1
3567 11:32:55.694352 SW Impedance : PASS
3568 11:32:55.697805 DUTY Scan : NO K
3569 11:32:55.701419 ZQ Calibration : PASS
3570 11:32:55.701494 Jitter Meter : NO K
3571 11:32:55.705027 CBT Training : PASS
3572 11:32:55.708455 Write leveling : PASS
3573 11:32:55.708530 RX DQS gating : PASS
3574 11:32:55.711151 RX DQ/DQS(RDDQC) : PASS
3575 11:32:55.714661 TX DQ/DQS : PASS
3576 11:32:55.714736 RX DATLAT : PASS
3577 11:32:55.717428 RX DQ/DQS(Engine): PASS
3578 11:32:55.721096 TX OE : NO K
3579 11:32:55.721171 All Pass.
3580 11:32:55.721239
3581 11:32:55.721295 CH 1, Rank 0
3582 11:32:55.724266 SW Impedance : PASS
3583 11:32:55.727511 DUTY Scan : NO K
3584 11:32:55.727586 ZQ Calibration : PASS
3585 11:32:55.730683 Jitter Meter : NO K
3586 11:32:55.734233 CBT Training : PASS
3587 11:32:55.734333 Write leveling : PASS
3588 11:32:55.737436 RX DQS gating : PASS
3589 11:32:55.737511 RX DQ/DQS(RDDQC) : PASS
3590 11:32:55.740881 TX DQ/DQS : PASS
3591 11:32:55.744409 RX DATLAT : PASS
3592 11:32:55.744484 RX DQ/DQS(Engine): PASS
3593 11:32:55.747756 TX OE : NO K
3594 11:32:55.747831 All Pass.
3595 11:32:55.747889
3596 11:32:55.750503 CH 1, Rank 1
3597 11:32:55.750579 SW Impedance : PASS
3598 11:32:55.754914 DUTY Scan : NO K
3599 11:32:55.757477 ZQ Calibration : PASS
3600 11:32:55.757556 Jitter Meter : NO K
3601 11:32:55.760768 CBT Training : PASS
3602 11:32:55.764135 Write leveling : PASS
3603 11:32:55.764211 RX DQS gating : PASS
3604 11:32:55.768216 RX DQ/DQS(RDDQC) : PASS
3605 11:32:55.770453 TX DQ/DQS : PASS
3606 11:32:55.770528 RX DATLAT : PASS
3607 11:32:55.774285 RX DQ/DQS(Engine): PASS
3608 11:32:55.777280 TX OE : NO K
3609 11:32:55.777355 All Pass.
3610 11:32:55.777413
3611 11:32:55.777467 DramC Write-DBI off
3612 11:32:55.781089 PER_BANK_REFRESH: Hybrid Mode
3613 11:32:55.784072 TX_TRACKING: ON
3614 11:32:55.790800 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3615 11:32:55.793730 [FAST_K] Save calibration result to emmc
3616 11:32:55.801789 dramc_set_vcore_voltage set vcore to 650000
3617 11:32:55.801864 Read voltage for 600, 5
3618 11:32:55.804493 Vio18 = 0
3619 11:32:55.804567 Vcore = 650000
3620 11:32:55.804625 Vdram = 0
3621 11:32:55.804679 Vddq = 0
3622 11:32:55.807178 Vmddr = 0
3623 11:32:55.810301 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3624 11:32:55.817522 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3625 11:32:55.820711 MEM_TYPE=3, freq_sel=19
3626 11:32:55.820786 sv_algorithm_assistance_LP4_1600
3627 11:32:55.826956 ============ PULL DRAM RESETB DOWN ============
3628 11:32:55.831080 ========== PULL DRAM RESETB DOWN end =========
3629 11:32:55.834049 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3630 11:32:55.837156 ===================================
3631 11:32:55.840017 LPDDR4 DRAM CONFIGURATION
3632 11:32:55.843571 ===================================
3633 11:32:55.846988 EX_ROW_EN[0] = 0x0
3634 11:32:55.847063 EX_ROW_EN[1] = 0x0
3635 11:32:55.850292 LP4Y_EN = 0x0
3636 11:32:55.850367 WORK_FSP = 0x0
3637 11:32:55.853857 WL = 0x2
3638 11:32:55.853931 RL = 0x2
3639 11:32:55.856937 BL = 0x2
3640 11:32:55.857012 RPST = 0x0
3641 11:32:55.859893 RD_PRE = 0x0
3642 11:32:55.859968 WR_PRE = 0x1
3643 11:32:55.863077 WR_PST = 0x0
3644 11:32:55.866907 DBI_WR = 0x0
3645 11:32:55.866982 DBI_RD = 0x0
3646 11:32:55.870568 OTF = 0x1
3647 11:32:55.873532 ===================================
3648 11:32:55.876578 ===================================
3649 11:32:55.876654 ANA top config
3650 11:32:55.879901 ===================================
3651 11:32:55.883733 DLL_ASYNC_EN = 0
3652 11:32:55.886957 ALL_SLAVE_EN = 1
3653 11:32:55.887032 NEW_RANK_MODE = 1
3654 11:32:55.889864 DLL_IDLE_MODE = 1
3655 11:32:55.893041 LP45_APHY_COMB_EN = 1
3656 11:32:55.896228 TX_ODT_DIS = 1
3657 11:32:55.896307 NEW_8X_MODE = 1
3658 11:32:55.899472 ===================================
3659 11:32:55.903522 ===================================
3660 11:32:55.906124 data_rate = 1200
3661 11:32:55.909388 CKR = 1
3662 11:32:55.913913 DQ_P2S_RATIO = 8
3663 11:32:55.916104 ===================================
3664 11:32:55.919592 CA_P2S_RATIO = 8
3665 11:32:55.922928 DQ_CA_OPEN = 0
3666 11:32:55.923002 DQ_SEMI_OPEN = 0
3667 11:32:55.926501 CA_SEMI_OPEN = 0
3668 11:32:55.929647 CA_FULL_RATE = 0
3669 11:32:55.933057 DQ_CKDIV4_EN = 1
3670 11:32:55.936301 CA_CKDIV4_EN = 1
3671 11:32:55.939481 CA_PREDIV_EN = 0
3672 11:32:55.939556 PH8_DLY = 0
3673 11:32:55.942691 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3674 11:32:55.946417 DQ_AAMCK_DIV = 4
3675 11:32:55.949670 CA_AAMCK_DIV = 4
3676 11:32:55.952725 CA_ADMCK_DIV = 4
3677 11:32:55.956374 DQ_TRACK_CA_EN = 0
3678 11:32:55.960106 CA_PICK = 600
3679 11:32:55.960181 CA_MCKIO = 600
3680 11:32:55.962974 MCKIO_SEMI = 0
3681 11:32:55.965687 PLL_FREQ = 2288
3682 11:32:55.969047 DQ_UI_PI_RATIO = 32
3683 11:32:55.973117 CA_UI_PI_RATIO = 0
3684 11:32:55.975850 ===================================
3685 11:32:55.978943 ===================================
3686 11:32:55.982971 memory_type:LPDDR4
3687 11:32:55.983046 GP_NUM : 10
3688 11:32:55.985751 SRAM_EN : 1
3689 11:32:55.985825 MD32_EN : 0
3690 11:32:55.989424 ===================================
3691 11:32:55.992456 [ANA_INIT] >>>>>>>>>>>>>>
3692 11:32:55.996127 <<<<<< [CONFIGURE PHASE]: ANA_TX
3693 11:32:55.999253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3694 11:32:56.002570 ===================================
3695 11:32:56.006217 data_rate = 1200,PCW = 0X5800
3696 11:32:56.009100 ===================================
3697 11:32:56.013027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3698 11:32:56.018762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3699 11:32:56.022280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3700 11:32:56.029272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3701 11:32:56.032473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3702 11:32:56.035706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3703 11:32:56.035781 [ANA_INIT] flow start
3704 11:32:56.039178 [ANA_INIT] PLL >>>>>>>>
3705 11:32:56.042520 [ANA_INIT] PLL <<<<<<<<
3706 11:32:56.042594 [ANA_INIT] MIDPI >>>>>>>>
3707 11:32:56.045394 [ANA_INIT] MIDPI <<<<<<<<
3708 11:32:56.049151 [ANA_INIT] DLL >>>>>>>>
3709 11:32:56.049231 [ANA_INIT] flow end
3710 11:32:56.055694 ============ LP4 DIFF to SE enter ============
3711 11:32:56.059122 ============ LP4 DIFF to SE exit ============
3712 11:32:56.059198 [ANA_INIT] <<<<<<<<<<<<<
3713 11:32:56.062937 [Flow] Enable top DCM control >>>>>
3714 11:32:56.066446 [Flow] Enable top DCM control <<<<<
3715 11:32:56.069286 Enable DLL master slave shuffle
3716 11:32:56.076238 ==============================================================
3717 11:32:56.076387 Gating Mode config
3718 11:32:56.082849 ==============================================================
3719 11:32:56.086200 Config description:
3720 11:32:56.095967 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3721 11:32:56.102690 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3722 11:32:56.105793 SELPH_MODE 0: By rank 1: By Phase
3723 11:32:56.112211 ==============================================================
3724 11:32:56.115706 GAT_TRACK_EN = 1
3725 11:32:56.119230 RX_GATING_MODE = 2
3726 11:32:56.119332 RX_GATING_TRACK_MODE = 2
3727 11:32:56.122111 SELPH_MODE = 1
3728 11:32:56.125648 PICG_EARLY_EN = 1
3729 11:32:56.128764 VALID_LAT_VALUE = 1
3730 11:32:56.136398 ==============================================================
3731 11:32:56.138518 Enter into Gating configuration >>>>
3732 11:32:56.142611 Exit from Gating configuration <<<<
3733 11:32:56.145216 Enter into DVFS_PRE_config >>>>>
3734 11:32:56.155396 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3735 11:32:56.158672 Exit from DVFS_PRE_config <<<<<
3736 11:32:56.161732 Enter into PICG configuration >>>>
3737 11:32:56.165345 Exit from PICG configuration <<<<
3738 11:32:56.168340 [RX_INPUT] configuration >>>>>
3739 11:32:56.172027 [RX_INPUT] configuration <<<<<
3740 11:32:56.175267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3741 11:32:56.182166 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3742 11:32:56.188712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3743 11:32:56.195151 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3744 11:32:56.198373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3745 11:32:56.204993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3746 11:32:56.208197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3747 11:32:56.214713 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3748 11:32:56.218143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3749 11:32:56.221741 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3750 11:32:56.225934 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3751 11:32:56.231225 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 11:32:56.234578 ===================================
3753 11:32:56.238805 LPDDR4 DRAM CONFIGURATION
3754 11:32:56.242212 ===================================
3755 11:32:56.242303 EX_ROW_EN[0] = 0x0
3756 11:32:56.244418 EX_ROW_EN[1] = 0x0
3757 11:32:56.244489 LP4Y_EN = 0x0
3758 11:32:56.248747 WORK_FSP = 0x0
3759 11:32:56.248823 WL = 0x2
3760 11:32:56.251144 RL = 0x2
3761 11:32:56.251219 BL = 0x2
3762 11:32:56.254714 RPST = 0x0
3763 11:32:56.254789 RD_PRE = 0x0
3764 11:32:56.257388 WR_PRE = 0x1
3765 11:32:56.257487 WR_PST = 0x0
3766 11:32:56.260871 DBI_WR = 0x0
3767 11:32:56.264719 DBI_RD = 0x0
3768 11:32:56.264794 OTF = 0x1
3769 11:32:56.267876 ===================================
3770 11:32:56.270755 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3771 11:32:56.274558 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3772 11:32:56.280656 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3773 11:32:56.284234 ===================================
3774 11:32:56.287314 LPDDR4 DRAM CONFIGURATION
3775 11:32:56.291558 ===================================
3776 11:32:56.291658 EX_ROW_EN[0] = 0x10
3777 11:32:56.294229 EX_ROW_EN[1] = 0x0
3778 11:32:56.294304 LP4Y_EN = 0x0
3779 11:32:56.297295 WORK_FSP = 0x0
3780 11:32:56.297370 WL = 0x2
3781 11:32:56.300698 RL = 0x2
3782 11:32:56.300772 BL = 0x2
3783 11:32:56.304429 RPST = 0x0
3784 11:32:56.304503 RD_PRE = 0x0
3785 11:32:56.307686 WR_PRE = 0x1
3786 11:32:56.307761 WR_PST = 0x0
3787 11:32:56.310918 DBI_WR = 0x0
3788 11:32:56.310993 DBI_RD = 0x0
3789 11:32:56.314161 OTF = 0x1
3790 11:32:56.317204 ===================================
3791 11:32:56.323867 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3792 11:32:56.327245 nWR fixed to 30
3793 11:32:56.330885 [ModeRegInit_LP4] CH0 RK0
3794 11:32:56.330960 [ModeRegInit_LP4] CH0 RK1
3795 11:32:56.333795 [ModeRegInit_LP4] CH1 RK0
3796 11:32:56.337316 [ModeRegInit_LP4] CH1 RK1
3797 11:32:56.337391 match AC timing 16
3798 11:32:56.343521 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3799 11:32:56.347426 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3800 11:32:56.350383 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3801 11:32:56.356925 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3802 11:32:56.360605 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3803 11:32:56.360680 ==
3804 11:32:56.363944 Dram Type= 6, Freq= 0, CH_0, rank 0
3805 11:32:56.366846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3806 11:32:56.366921 ==
3807 11:32:56.373743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3808 11:32:56.380257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3809 11:32:56.383030 [CA 0] Center 35 (5~66) winsize 62
3810 11:32:56.386676 [CA 1] Center 35 (5~66) winsize 62
3811 11:32:56.390670 [CA 2] Center 34 (4~65) winsize 62
3812 11:32:56.393260 [CA 3] Center 34 (4~65) winsize 62
3813 11:32:56.396719 [CA 4] Center 33 (3~64) winsize 62
3814 11:32:56.400985 [CA 5] Center 33 (3~64) winsize 62
3815 11:32:56.401060
3816 11:32:56.403423 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3817 11:32:56.403498
3818 11:32:56.406461 [CATrainingPosCal] consider 1 rank data
3819 11:32:56.409812 u2DelayCellTimex100 = 270/100 ps
3820 11:32:56.413527 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3821 11:32:56.416226 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3822 11:32:56.419825 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3823 11:32:56.423526 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3824 11:32:56.429645 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3825 11:32:56.433088 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3826 11:32:56.433163
3827 11:32:56.436349 CA PerBit enable=1, Macro0, CA PI delay=33
3828 11:32:56.436424
3829 11:32:56.439582 [CBTSetCACLKResult] CA Dly = 33
3830 11:32:56.439657 CS Dly: 5 (0~36)
3831 11:32:56.439715 ==
3832 11:32:56.443189 Dram Type= 6, Freq= 0, CH_0, rank 1
3833 11:32:56.450251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3834 11:32:56.450350 ==
3835 11:32:56.454201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3836 11:32:56.459865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3837 11:32:56.462923 [CA 0] Center 36 (6~66) winsize 61
3838 11:32:56.466748 [CA 1] Center 35 (5~66) winsize 62
3839 11:32:56.469493 [CA 2] Center 34 (4~65) winsize 62
3840 11:32:56.472765 [CA 3] Center 34 (4~65) winsize 62
3841 11:32:56.476944 [CA 4] Center 33 (3~64) winsize 62
3842 11:32:56.479681 [CA 5] Center 33 (3~64) winsize 62
3843 11:32:56.479755
3844 11:32:56.482711 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3845 11:32:56.482786
3846 11:32:56.486020 [CATrainingPosCal] consider 2 rank data
3847 11:32:56.489744 u2DelayCellTimex100 = 270/100 ps
3848 11:32:56.492602 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3849 11:32:56.496197 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3850 11:32:56.502579 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3851 11:32:56.505583 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3852 11:32:56.509109 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3853 11:32:56.512173 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3854 11:32:56.512248
3855 11:32:56.516293 CA PerBit enable=1, Macro0, CA PI delay=33
3856 11:32:56.516387
3857 11:32:56.519201 [CBTSetCACLKResult] CA Dly = 33
3858 11:32:56.519294 CS Dly: 5 (0~36)
3859 11:32:56.519380
3860 11:32:56.522639 ----->DramcWriteLeveling(PI) begin...
3861 11:32:56.525567 ==
3862 11:32:56.528969 Dram Type= 6, Freq= 0, CH_0, rank 0
3863 11:32:56.532225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3864 11:32:56.532300 ==
3865 11:32:56.535898 Write leveling (Byte 0): 30 => 30
3866 11:32:56.538862 Write leveling (Byte 1): 30 => 30
3867 11:32:56.542090 DramcWriteLeveling(PI) end<-----
3868 11:32:56.542165
3869 11:32:56.542226 ==
3870 11:32:56.545342 Dram Type= 6, Freq= 0, CH_0, rank 0
3871 11:32:56.548677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3872 11:32:56.548753 ==
3873 11:32:56.552184 [Gating] SW mode calibration
3874 11:32:56.558770 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3875 11:32:56.565569 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3876 11:32:56.568424 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3877 11:32:56.572331 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3878 11:32:56.579078 0 5 8 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (1 0)
3879 11:32:56.581744 0 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3880 11:32:56.586313 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3881 11:32:56.591918 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3882 11:32:56.595021 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3883 11:32:56.598947 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3884 11:32:56.605471 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3885 11:32:56.608401 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3886 11:32:56.611483 0 6 8 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
3887 11:32:56.618640 0 6 12 | B1->B0 | 4444 4444 | 1 0 | (0 0) (0 0)
3888 11:32:56.621391 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3889 11:32:56.625175 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3890 11:32:56.628489 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3891 11:32:56.634757 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3892 11:32:56.638114 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3893 11:32:56.644719 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3894 11:32:56.648140 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3895 11:32:56.651328 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 11:32:56.654781 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3897 11:32:56.661354 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3898 11:32:56.664668 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3899 11:32:56.671069 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3900 11:32:56.674479 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3901 11:32:56.677430 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3902 11:32:56.684438 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3903 11:32:56.687416 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3904 11:32:56.691005 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3905 11:32:56.697643 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3906 11:32:56.700171 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3907 11:32:56.703897 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3908 11:32:56.711311 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3909 11:32:56.714373 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3910 11:32:56.716864 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3911 11:32:56.720647 Total UI for P1: 0, mck2ui 16
3912 11:32:56.724363 best dqsien dly found for B0: ( 0, 9, 6)
3913 11:32:56.727434 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3914 11:32:56.733979 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3915 11:32:56.737240 Total UI for P1: 0, mck2ui 16
3916 11:32:56.739995 best dqsien dly found for B1: ( 0, 9, 10)
3917 11:32:56.743486 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3918 11:32:56.746775 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3919 11:32:56.746849
3920 11:32:56.749919 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3921 11:32:56.753396 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3922 11:32:56.756324 [Gating] SW calibration Done
3923 11:32:56.756398 ==
3924 11:32:56.759878 Dram Type= 6, Freq= 0, CH_0, rank 0
3925 11:32:56.763088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3926 11:32:56.763163 ==
3927 11:32:56.766821 RX Vref Scan: 0
3928 11:32:56.766896
3929 11:32:56.770870 RX Vref 0 -> 0, step: 1
3930 11:32:56.770945
3931 11:32:56.772944 RX Delay -230 -> 252, step: 16
3932 11:32:56.776201 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3933 11:32:56.779677 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3934 11:32:56.782812 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3935 11:32:56.786227 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3936 11:32:56.792721 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3937 11:32:56.796325 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3938 11:32:56.800347 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3939 11:32:56.802705 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3940 11:32:56.809589 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3941 11:32:56.813034 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3942 11:32:56.816219 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3943 11:32:56.819762 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3944 11:32:56.826414 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3945 11:32:56.829736 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3946 11:32:56.832658 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3947 11:32:56.836189 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3948 11:32:56.836289 ==
3949 11:32:56.839081 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 11:32:56.845817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3951 11:32:56.845907 ==
3952 11:32:56.845993 DQS Delay:
3953 11:32:56.849162 DQS0 = 0, DQS1 = 0
3954 11:32:56.849304 DQM Delay:
3955 11:32:56.849392 DQM0 = 37, DQM1 = 33
3956 11:32:56.852982 DQ Delay:
3957 11:32:56.855984 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3958 11:32:56.859402 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3959 11:32:56.862312 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3960 11:32:56.865711 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3961 11:32:56.865811
3962 11:32:56.865895
3963 11:32:56.865968 ==
3964 11:32:56.869317 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 11:32:56.871954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3966 11:32:56.872056 ==
3967 11:32:56.872140
3968 11:32:56.872220
3969 11:32:56.875972 TX Vref Scan disable
3970 11:32:56.878867 == TX Byte 0 ==
3971 11:32:56.882353 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3972 11:32:56.885696 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3973 11:32:56.889096 == TX Byte 1 ==
3974 11:32:56.893362 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3975 11:32:56.896111 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3976 11:32:56.896187 ==
3977 11:32:56.898933 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 11:32:56.901825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3979 11:32:56.905045 ==
3980 11:32:56.905119
3981 11:32:56.905177
3982 11:32:56.905240 TX Vref Scan disable
3983 11:32:56.909202 == TX Byte 0 ==
3984 11:32:56.912292 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3985 11:32:56.919198 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3986 11:32:56.919274 == TX Byte 1 ==
3987 11:32:56.922273 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3988 11:32:56.929219 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3989 11:32:56.929300
3990 11:32:56.929358 [DATLAT]
3991 11:32:56.929412 Freq=600, CH0 RK0
3992 11:32:56.929464
3993 11:32:56.932586 DATLAT Default: 0x9
3994 11:32:56.932684 0, 0xFFFF, sum = 0
3995 11:32:56.935519 1, 0xFFFF, sum = 0
3996 11:32:56.935595 2, 0xFFFF, sum = 0
3997 11:32:56.938882 3, 0xFFFF, sum = 0
3998 11:32:56.943251 4, 0xFFFF, sum = 0
3999 11:32:56.943328 5, 0xFFFF, sum = 0
4000 11:32:56.945609 6, 0xFFFF, sum = 0
4001 11:32:56.945685 7, 0x0, sum = 1
4002 11:32:56.945744 8, 0x0, sum = 2
4003 11:32:56.949085 9, 0x0, sum = 3
4004 11:32:56.949161 10, 0x0, sum = 4
4005 11:32:56.952806 best_step = 8
4006 11:32:56.952888
4007 11:32:56.952947 ==
4008 11:32:56.955882 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 11:32:56.959706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4010 11:32:56.959802 ==
4011 11:32:56.962224 RX Vref Scan: 1
4012 11:32:56.962299
4013 11:32:56.962357 RX Vref 0 -> 0, step: 1
4014 11:32:56.962411
4015 11:32:56.966625 RX Delay -195 -> 252, step: 8
4016 11:32:56.966724
4017 11:32:56.969201 Set Vref, RX VrefLevel [Byte0]: 51
4018 11:32:56.972333 [Byte1]: 51
4019 11:32:56.976607
4020 11:32:56.976682 Final RX Vref Byte 0 = 51 to rank0
4021 11:32:56.979825 Final RX Vref Byte 1 = 51 to rank0
4022 11:32:56.982779 Final RX Vref Byte 0 = 51 to rank1
4023 11:32:56.986373 Final RX Vref Byte 1 = 51 to rank1==
4024 11:32:56.990352 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 11:32:56.996999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4026 11:32:56.997075 ==
4027 11:32:56.997134 DQS Delay:
4028 11:32:56.997188 DQS0 = 0, DQS1 = 0
4029 11:32:56.999090 DQM Delay:
4030 11:32:56.999165 DQM0 = 40, DQM1 = 30
4031 11:32:57.002555 DQ Delay:
4032 11:32:57.005929 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
4033 11:32:57.009582 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4034 11:32:57.012562 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4035 11:32:57.016229 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4036 11:32:57.016306
4037 11:32:57.016383
4038 11:32:57.022578 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4039 11:32:57.026008 CH0 RK0: MR19=808, MR18=5C5C
4040 11:32:57.032423 CH0_RK0: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4041 11:32:57.032501
4042 11:32:57.036191 ----->DramcWriteLeveling(PI) begin...
4043 11:32:57.036291 ==
4044 11:32:57.039580 Dram Type= 6, Freq= 0, CH_0, rank 1
4045 11:32:57.042767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4046 11:32:57.042843 ==
4047 11:32:57.046686 Write leveling (Byte 0): 30 => 30
4048 11:32:57.049332 Write leveling (Byte 1): 30 => 30
4049 11:32:57.052938 DramcWriteLeveling(PI) end<-----
4050 11:32:57.053012
4051 11:32:57.053070 ==
4052 11:32:57.055722 Dram Type= 6, Freq= 0, CH_0, rank 1
4053 11:32:57.059378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4054 11:32:57.059454 ==
4055 11:32:57.062814 [Gating] SW mode calibration
4056 11:32:57.069236 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4057 11:32:57.075466 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4058 11:32:57.078819 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 11:32:57.085473 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 11:32:57.089433 0 5 8 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
4061 11:32:57.092709 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4062 11:32:57.098660 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 11:32:57.102625 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 11:32:57.105771 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 11:32:57.109020 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:32:57.115627 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:32:57.118664 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:32:57.122171 0 6 8 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
4069 11:32:57.128650 0 6 12 | B1->B0 | 4444 4343 | 1 0 | (0 0) (0 0)
4070 11:32:57.131843 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:32:57.135247 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:32:57.142113 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:32:57.145834 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:32:57.149096 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:32:57.156023 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:32:57.159024 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4077 11:32:57.161699 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4078 11:32:57.168599 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:32:57.171933 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:32:57.175106 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:32:57.181819 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:32:57.185695 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:32:57.188340 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:32:57.195304 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:32:57.198666 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:32:57.201502 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:32:57.209549 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:32:57.211768 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:32:57.215314 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:32:57.222144 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:32:57.224644 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:32:57.228410 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4093 11:32:57.231653 Total UI for P1: 0, mck2ui 16
4094 11:32:57.235016 best dqsien dly found for B0: ( 0, 9, 6)
4095 11:32:57.238944 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 11:32:57.242118 Total UI for P1: 0, mck2ui 16
4097 11:32:57.245123 best dqsien dly found for B1: ( 0, 9, 8)
4098 11:32:57.248109 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4099 11:32:57.255049 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4100 11:32:57.255124
4101 11:32:57.258627 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4102 11:32:57.261272 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4103 11:32:57.266115 [Gating] SW calibration Done
4104 11:32:57.266191 ==
4105 11:32:57.267889 Dram Type= 6, Freq= 0, CH_0, rank 1
4106 11:32:57.271348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4107 11:32:57.271424 ==
4108 11:32:57.274844 RX Vref Scan: 0
4109 11:32:57.274919
4110 11:32:57.274978 RX Vref 0 -> 0, step: 1
4111 11:32:57.275034
4112 11:32:57.278132 RX Delay -230 -> 252, step: 16
4113 11:32:57.281244 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4114 11:32:57.287755 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4115 11:32:57.291071 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4116 11:32:57.294444 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4117 11:32:57.297741 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4118 11:32:57.304553 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4119 11:32:57.307398 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4120 11:32:57.311082 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4121 11:32:57.314096 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4122 11:32:57.317500 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4123 11:32:57.324527 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4124 11:32:57.328023 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4125 11:32:57.330660 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4126 11:32:57.334290 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4127 11:32:57.341408 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4128 11:32:57.343872 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4129 11:32:57.343948 ==
4130 11:32:57.347406 Dram Type= 6, Freq= 0, CH_0, rank 1
4131 11:32:57.351168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4132 11:32:57.351245 ==
4133 11:32:57.354469 DQS Delay:
4134 11:32:57.354544 DQS0 = 0, DQS1 = 0
4135 11:32:57.354605 DQM Delay:
4136 11:32:57.357486 DQM0 = 40, DQM1 = 33
4137 11:32:57.357586 DQ Delay:
4138 11:32:57.360868 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4139 11:32:57.364148 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4140 11:32:57.368302 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4141 11:32:57.371078 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4142 11:32:57.371156
4143 11:32:57.371233
4144 11:32:57.371305 ==
4145 11:32:57.373982 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 11:32:57.380827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4147 11:32:57.380905 ==
4148 11:32:57.380998
4149 11:32:57.381089
4150 11:32:57.381181 TX Vref Scan disable
4151 11:32:57.384744 == TX Byte 0 ==
4152 11:32:57.388340 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4153 11:32:57.394367 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4154 11:32:57.394443 == TX Byte 1 ==
4155 11:32:57.398534 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4156 11:32:57.404580 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4157 11:32:57.404671 ==
4158 11:32:57.408172 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 11:32:57.410854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4160 11:32:57.410949 ==
4161 11:32:57.411008
4162 11:32:57.411062
4163 11:32:57.414067 TX Vref Scan disable
4164 11:32:57.417825 == TX Byte 0 ==
4165 11:32:57.421018 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4166 11:32:57.424137 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4167 11:32:57.427450 == TX Byte 1 ==
4168 11:32:57.431095 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4169 11:32:57.434222 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4170 11:32:57.434296
4171 11:32:57.434354 [DATLAT]
4172 11:32:57.437741 Freq=600, CH0 RK1
4173 11:32:57.437817
4174 11:32:57.441046 DATLAT Default: 0x8
4175 11:32:57.441121 0, 0xFFFF, sum = 0
4176 11:32:57.444293 1, 0xFFFF, sum = 0
4177 11:32:57.444369 2, 0xFFFF, sum = 0
4178 11:32:57.447159 3, 0xFFFF, sum = 0
4179 11:32:57.447234 4, 0xFFFF, sum = 0
4180 11:32:57.450434 5, 0xFFFF, sum = 0
4181 11:32:57.450510 6, 0xFFFF, sum = 0
4182 11:32:57.453717 7, 0x0, sum = 1
4183 11:32:57.453793 8, 0x0, sum = 2
4184 11:32:57.453852 9, 0x0, sum = 3
4185 11:32:57.457277 10, 0x0, sum = 4
4186 11:32:57.457366 best_step = 8
4187 11:32:57.457424
4188 11:32:57.457477 ==
4189 11:32:57.460643 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 11:32:57.467131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4191 11:32:57.467232 ==
4192 11:32:57.467323 RX Vref Scan: 0
4193 11:32:57.467402
4194 11:32:57.470437 RX Vref 0 -> 0, step: 1
4195 11:32:57.470532
4196 11:32:57.474086 RX Delay -195 -> 252, step: 8
4197 11:32:57.477426 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4198 11:32:57.483564 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4199 11:32:57.487244 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4200 11:32:57.490326 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4201 11:32:57.493746 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4202 11:32:57.501352 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4203 11:32:57.503799 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4204 11:32:57.507073 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4205 11:32:57.510807 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4206 11:32:57.517047 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4207 11:32:57.520453 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4208 11:32:57.523716 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4209 11:32:57.527391 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4210 11:32:57.533563 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4211 11:32:57.537005 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4212 11:32:57.540079 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4213 11:32:57.540155 ==
4214 11:32:57.543760 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 11:32:57.546603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 11:32:57.546703 ==
4217 11:32:57.549803 DQS Delay:
4218 11:32:57.549878 DQS0 = 0, DQS1 = 0
4219 11:32:57.553086 DQM Delay:
4220 11:32:57.553190 DQM0 = 41, DQM1 = 32
4221 11:32:57.553335 DQ Delay:
4222 11:32:57.556293 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4223 11:32:57.560136 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4224 11:32:57.563479 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4225 11:32:57.566266 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4226 11:32:57.566342
4227 11:32:57.566401
4228 11:32:57.576724 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a6a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4229 11:32:57.579693 CH0 RK1: MR19=808, MR18=6A6A
4230 11:32:57.586151 CH0_RK1: MR19=0x808, MR18=0x6A6A, DQSOSC=389, MR23=63, INC=173, DEC=115
4231 11:32:57.586227 [RxdqsGatingPostProcess] freq 600
4232 11:32:57.593455 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4233 11:32:57.597832 Pre-setting of DQS Precalculation
4234 11:32:57.599724 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4235 11:32:57.603065 ==
4236 11:32:57.603154 Dram Type= 6, Freq= 0, CH_1, rank 0
4237 11:32:57.609991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4238 11:32:57.610155 ==
4239 11:32:57.613457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4240 11:32:57.620089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4241 11:32:57.623401 [CA 0] Center 35 (5~66) winsize 62
4242 11:32:57.626559 [CA 1] Center 35 (5~66) winsize 62
4243 11:32:57.630511 [CA 2] Center 33 (3~64) winsize 62
4244 11:32:57.633480 [CA 3] Center 33 (3~64) winsize 62
4245 11:32:57.636720 [CA 4] Center 33 (2~64) winsize 63
4246 11:32:57.639974 [CA 5] Center 33 (2~64) winsize 63
4247 11:32:57.640066
4248 11:32:57.643096 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4249 11:32:57.643170
4250 11:32:57.646623 [CATrainingPosCal] consider 1 rank data
4251 11:32:57.650035 u2DelayCellTimex100 = 270/100 ps
4252 11:32:57.653164 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4253 11:32:57.659530 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4254 11:32:57.662820 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4255 11:32:57.666663 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4256 11:32:57.670456 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4257 11:32:57.673164 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4258 11:32:57.673295
4259 11:32:57.676012 CA PerBit enable=1, Macro0, CA PI delay=33
4260 11:32:57.676087
4261 11:32:57.679541 [CBTSetCACLKResult] CA Dly = 33
4262 11:32:57.679616 CS Dly: 4 (0~35)
4263 11:32:57.684112 ==
4264 11:32:57.685870 Dram Type= 6, Freq= 0, CH_1, rank 1
4265 11:32:57.689937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4266 11:32:57.690013 ==
4267 11:32:57.695705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4268 11:32:57.699497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4269 11:32:57.703147 [CA 0] Center 35 (4~66) winsize 63
4270 11:32:57.706777 [CA 1] Center 34 (4~65) winsize 62
4271 11:32:57.710245 [CA 2] Center 33 (3~64) winsize 62
4272 11:32:57.712847 [CA 3] Center 33 (3~64) winsize 62
4273 11:32:57.716892 [CA 4] Center 32 (2~63) winsize 62
4274 11:32:57.720473 [CA 5] Center 32 (2~63) winsize 62
4275 11:32:57.720548
4276 11:32:57.723339 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4277 11:32:57.723414
4278 11:32:57.726477 [CATrainingPosCal] consider 2 rank data
4279 11:32:57.730205 u2DelayCellTimex100 = 270/100 ps
4280 11:32:57.733223 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4281 11:32:57.739733 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4282 11:32:57.743061 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4283 11:32:57.746411 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4284 11:32:57.749864 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4285 11:32:57.752765 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4286 11:32:57.752840
4287 11:32:57.755966 CA PerBit enable=1, Macro0, CA PI delay=32
4288 11:32:57.756042
4289 11:32:57.759331 [CBTSetCACLKResult] CA Dly = 32
4290 11:32:57.762645 CS Dly: 4 (0~36)
4291 11:32:57.762718
4292 11:32:57.765874 ----->DramcWriteLeveling(PI) begin...
4293 11:32:57.765951 ==
4294 11:32:57.769421 Dram Type= 6, Freq= 0, CH_1, rank 0
4295 11:32:57.772797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4296 11:32:57.772872 ==
4297 11:32:57.775801 Write leveling (Byte 0): 29 => 29
4298 11:32:57.779107 Write leveling (Byte 1): 29 => 29
4299 11:32:57.782665 DramcWriteLeveling(PI) end<-----
4300 11:32:57.782746
4301 11:32:57.782823 ==
4302 11:32:57.785687 Dram Type= 6, Freq= 0, CH_1, rank 0
4303 11:32:57.788872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4304 11:32:57.788950 ==
4305 11:32:57.792290 [Gating] SW mode calibration
4306 11:32:57.799350 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4307 11:32:57.805489 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4308 11:32:57.809013 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4309 11:32:57.812575 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
4310 11:32:57.818862 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4311 11:32:57.822290 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4312 11:32:57.826815 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4313 11:32:57.833034 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4314 11:32:57.835351 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4315 11:32:57.839271 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4316 11:32:57.845737 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4317 11:32:57.849135 0 6 4 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
4318 11:32:57.852380 0 6 8 | B1->B0 | 3434 3f3f | 0 1 | (1 1) (0 0)
4319 11:32:57.859068 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4320 11:32:57.862169 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4321 11:32:57.865995 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4322 11:32:57.872249 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4323 11:32:57.875199 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4324 11:32:57.878890 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4325 11:32:57.885849 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4326 11:32:57.888727 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4327 11:32:57.892737 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4328 11:32:57.898514 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4329 11:32:57.902076 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4330 11:32:57.905367 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4331 11:32:57.911431 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4332 11:32:57.915141 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4333 11:32:57.918183 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4334 11:32:57.925150 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4335 11:32:57.928125 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4336 11:32:57.931380 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4337 11:32:57.938294 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4338 11:32:57.941414 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4339 11:32:57.945009 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4340 11:32:57.947847 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4341 11:32:57.954616 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4342 11:32:57.957968 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4343 11:32:57.961729 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4344 11:32:57.965118 Total UI for P1: 0, mck2ui 16
4345 11:32:57.968729 best dqsien dly found for B0: ( 0, 9, 6)
4346 11:32:57.971292 Total UI for P1: 0, mck2ui 16
4347 11:32:57.974263 best dqsien dly found for B1: ( 0, 9, 10)
4348 11:32:57.978354 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4349 11:32:57.984396 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4350 11:32:57.984477
4351 11:32:57.988074 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4352 11:32:57.991362 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4353 11:32:57.994385 [Gating] SW calibration Done
4354 11:32:57.994460 ==
4355 11:32:57.997520 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 11:32:58.001371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4357 11:32:58.001446 ==
4358 11:32:58.004659 RX Vref Scan: 0
4359 11:32:58.004733
4360 11:32:58.004791 RX Vref 0 -> 0, step: 1
4361 11:32:58.004845
4362 11:32:58.007865 RX Delay -230 -> 252, step: 16
4363 11:32:58.010770 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4364 11:32:58.017161 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4365 11:32:58.020827 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4366 11:32:58.024655 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4367 11:32:58.027494 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4368 11:32:58.033680 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4369 11:32:58.037099 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4370 11:32:58.040537 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4371 11:32:58.044435 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4372 11:32:58.047582 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4373 11:32:58.053670 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4374 11:32:58.057314 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4375 11:32:58.060286 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4376 11:32:58.063604 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4377 11:32:58.070369 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4378 11:32:58.074005 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4379 11:32:58.074080 ==
4380 11:32:58.077184 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 11:32:58.080688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4382 11:32:58.080763 ==
4383 11:32:58.083592 DQS Delay:
4384 11:32:58.083666 DQS0 = 0, DQS1 = 0
4385 11:32:58.083724 DQM Delay:
4386 11:32:58.087008 DQM0 = 38, DQM1 = 30
4387 11:32:58.087106 DQ Delay:
4388 11:32:58.091073 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4389 11:32:58.093488 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4390 11:32:58.097168 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4391 11:32:58.100560 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4392 11:32:58.100633
4393 11:32:58.100690
4394 11:32:58.100743 ==
4395 11:32:58.103684 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:32:58.110396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4397 11:32:58.110471 ==
4398 11:32:58.110528
4399 11:32:58.110581
4400 11:32:58.110631 TX Vref Scan disable
4401 11:32:58.114104 == TX Byte 0 ==
4402 11:32:58.117633 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4403 11:32:58.120770 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4404 11:32:58.123970 == TX Byte 1 ==
4405 11:32:58.127345 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4406 11:32:58.130634 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4407 11:32:58.134249 ==
4408 11:32:58.137269 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 11:32:58.141651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4410 11:32:58.141725 ==
4411 11:32:58.141783
4412 11:32:58.141837
4413 11:32:58.144408 TX Vref Scan disable
4414 11:32:58.144482 == TX Byte 0 ==
4415 11:32:58.150839 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4416 11:32:58.153832 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4417 11:32:58.153906 == TX Byte 1 ==
4418 11:32:58.160694 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4419 11:32:58.164001 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4420 11:32:58.164075
4421 11:32:58.164132 [DATLAT]
4422 11:32:58.166976 Freq=600, CH1 RK0
4423 11:32:58.167049
4424 11:32:58.167106 DATLAT Default: 0x9
4425 11:32:58.170105 0, 0xFFFF, sum = 0
4426 11:32:58.173789 1, 0xFFFF, sum = 0
4427 11:32:58.173873 2, 0xFFFF, sum = 0
4428 11:32:58.177092 3, 0xFFFF, sum = 0
4429 11:32:58.177168 4, 0xFFFF, sum = 0
4430 11:32:58.180179 5, 0xFFFF, sum = 0
4431 11:32:58.180254 6, 0xFFFF, sum = 0
4432 11:32:58.183465 7, 0x0, sum = 1
4433 11:32:58.183565 8, 0x0, sum = 2
4434 11:32:58.183652 9, 0x0, sum = 3
4435 11:32:58.186717 10, 0x0, sum = 4
4436 11:32:58.186792 best_step = 8
4437 11:32:58.186848
4438 11:32:58.186901 ==
4439 11:32:58.191262 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 11:32:58.196696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4441 11:32:58.196771 ==
4442 11:32:58.196830 RX Vref Scan: 1
4443 11:32:58.196884
4444 11:32:58.200190 RX Vref 0 -> 0, step: 1
4445 11:32:58.200264
4446 11:32:58.203578 RX Delay -195 -> 252, step: 8
4447 11:32:58.203653
4448 11:32:58.206617 Set Vref, RX VrefLevel [Byte0]: 52
4449 11:32:58.209694 [Byte1]: 52
4450 11:32:58.209769
4451 11:32:58.213015 Final RX Vref Byte 0 = 52 to rank0
4452 11:32:58.216638 Final RX Vref Byte 1 = 52 to rank0
4453 11:32:58.220335 Final RX Vref Byte 0 = 52 to rank1
4454 11:32:58.223241 Final RX Vref Byte 1 = 52 to rank1==
4455 11:32:58.226507 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 11:32:58.229579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4457 11:32:58.229654 ==
4458 11:32:58.233699 DQS Delay:
4459 11:32:58.233792 DQS0 = 0, DQS1 = 0
4460 11:32:58.236439 DQM Delay:
4461 11:32:58.236513 DQM0 = 37, DQM1 = 30
4462 11:32:58.236572 DQ Delay:
4463 11:32:58.239801 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4464 11:32:58.243109 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4465 11:32:58.246805 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4466 11:32:58.249805 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =40
4467 11:32:58.249890
4468 11:32:58.249949
4469 11:32:58.259763 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7f, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4470 11:32:58.262909 CH1 RK0: MR19=808, MR18=7F7F
4471 11:32:58.269396 CH1_RK0: MR19=0x808, MR18=0x7F7F, DQSOSC=386, MR23=63, INC=176, DEC=117
4472 11:32:58.269471
4473 11:32:58.273139 ----->DramcWriteLeveling(PI) begin...
4474 11:32:58.273235 ==
4475 11:32:58.276224 Dram Type= 6, Freq= 0, CH_1, rank 1
4476 11:32:58.279725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4477 11:32:58.279801 ==
4478 11:32:58.282452 Write leveling (Byte 0): 29 => 29
4479 11:32:58.286401 Write leveling (Byte 1): 27 => 27
4480 11:32:58.289927 DramcWriteLeveling(PI) end<-----
4481 11:32:58.290002
4482 11:32:58.290060 ==
4483 11:32:58.292643 Dram Type= 6, Freq= 0, CH_1, rank 1
4484 11:32:58.296070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4485 11:32:58.296145 ==
4486 11:32:58.299667 [Gating] SW mode calibration
4487 11:32:58.306154 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4488 11:32:58.312722 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4489 11:32:58.316392 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4490 11:32:58.319280 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4491 11:32:58.326191 0 5 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4492 11:32:58.328715 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 11:32:58.332265 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 11:32:58.338644 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 11:32:58.342238 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 11:32:58.346186 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 11:32:58.352199 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 11:32:58.355408 0 6 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
4499 11:32:58.359028 0 6 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4500 11:32:58.365664 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:32:58.368723 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 11:32:58.372327 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 11:32:58.378263 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:32:58.381968 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 11:32:58.384882 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 11:32:58.391313 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4507 11:32:58.395107 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4508 11:32:58.398567 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:32:58.404738 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:32:58.408165 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:32:58.411326 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:32:58.418176 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:32:58.421644 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:32:58.425098 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:32:58.431380 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:32:58.434440 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:32:58.438307 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:32:58.444748 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:32:58.447650 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:32:58.451016 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:32:58.457704 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:32:58.460878 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4523 11:32:58.464473 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 11:32:58.468335 Total UI for P1: 0, mck2ui 16
4525 11:32:58.470986 best dqsien dly found for B0: ( 0, 9, 4)
4526 11:32:58.474532 Total UI for P1: 0, mck2ui 16
4527 11:32:58.478278 best dqsien dly found for B1: ( 0, 9, 6)
4528 11:32:58.480645 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4529 11:32:58.484723 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4530 11:32:58.484798
4531 11:32:58.488317 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4532 11:32:58.494019 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4533 11:32:58.494094 [Gating] SW calibration Done
4534 11:32:58.497848 ==
4535 11:32:58.497945 Dram Type= 6, Freq= 0, CH_1, rank 1
4536 11:32:58.504250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4537 11:32:58.504326 ==
4538 11:32:58.504384 RX Vref Scan: 0
4539 11:32:58.504438
4540 11:32:58.507569 RX Vref 0 -> 0, step: 1
4541 11:32:58.507644
4542 11:32:58.511129 RX Delay -230 -> 252, step: 16
4543 11:32:58.514032 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4544 11:32:58.517295 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4545 11:32:58.524004 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4546 11:32:58.527422 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4547 11:32:58.531064 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4548 11:32:58.533915 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4549 11:32:58.540743 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4550 11:32:58.544550 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4551 11:32:58.547119 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4552 11:32:58.550749 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4553 11:32:58.553401 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4554 11:32:58.560512 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4555 11:32:58.564133 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4556 11:32:58.567361 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4557 11:32:58.570188 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4558 11:32:58.577521 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4559 11:32:58.577599 ==
4560 11:32:58.580183 Dram Type= 6, Freq= 0, CH_1, rank 1
4561 11:32:58.583543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4562 11:32:58.583620 ==
4563 11:32:58.583679 DQS Delay:
4564 11:32:58.586563 DQS0 = 0, DQS1 = 0
4565 11:32:58.586639 DQM Delay:
4566 11:32:58.589974 DQM0 = 39, DQM1 = 32
4567 11:32:58.590050 DQ Delay:
4568 11:32:58.593169 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4569 11:32:58.597102 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4570 11:32:58.600433 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4571 11:32:58.603235 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =33
4572 11:32:58.603310
4573 11:32:58.603369
4574 11:32:58.603423 ==
4575 11:32:58.606797 Dram Type= 6, Freq= 0, CH_1, rank 1
4576 11:32:58.610028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4577 11:32:58.613635 ==
4578 11:32:58.613710
4579 11:32:58.613769
4580 11:32:58.613823 TX Vref Scan disable
4581 11:32:58.617312 == TX Byte 0 ==
4582 11:32:58.620079 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4583 11:32:58.623653 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4584 11:32:58.626716 == TX Byte 1 ==
4585 11:32:58.629959 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4586 11:32:58.633394 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4587 11:32:58.636219 ==
4588 11:32:58.640076 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 11:32:58.643163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4590 11:32:58.643239 ==
4591 11:32:58.643298
4592 11:32:58.643351
4593 11:32:58.646535 TX Vref Scan disable
4594 11:32:58.649399 == TX Byte 0 ==
4595 11:32:58.652807 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 11:32:58.655920 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 11:32:58.660849 == TX Byte 1 ==
4598 11:32:58.663035 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4599 11:32:58.666316 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4600 11:32:58.666483
4601 11:32:58.666575 [DATLAT]
4602 11:32:58.669189 Freq=600, CH1 RK1
4603 11:32:58.669295
4604 11:32:58.673007 DATLAT Default: 0x8
4605 11:32:58.673107 0, 0xFFFF, sum = 0
4606 11:32:58.676224 1, 0xFFFF, sum = 0
4607 11:32:58.676303 2, 0xFFFF, sum = 0
4608 11:32:58.679337 3, 0xFFFF, sum = 0
4609 11:32:58.679417 4, 0xFFFF, sum = 0
4610 11:32:58.682940 5, 0xFFFF, sum = 0
4611 11:32:58.683018 6, 0xFFFF, sum = 0
4612 11:32:58.685837 7, 0x0, sum = 1
4613 11:32:58.685926 8, 0x0, sum = 2
4614 11:32:58.689030 9, 0x0, sum = 3
4615 11:32:58.689109 10, 0x0, sum = 4
4616 11:32:58.689205 best_step = 8
4617 11:32:58.689311
4618 11:32:58.692147 ==
4619 11:32:58.692249 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 11:32:58.699718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4621 11:32:58.699797 ==
4622 11:32:58.699874 RX Vref Scan: 0
4623 11:32:58.699948
4624 11:32:58.702261 RX Vref 0 -> 0, step: 1
4625 11:32:58.702338
4626 11:32:58.705489 RX Delay -195 -> 252, step: 8
4627 11:32:58.712942 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4628 11:32:58.715758 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4629 11:32:58.719455 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4630 11:32:58.722526 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4631 11:32:58.725715 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4632 11:32:58.733129 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4633 11:32:58.735528 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4634 11:32:58.738637 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4635 11:32:58.742164 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4636 11:32:58.748920 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4637 11:32:58.751698 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4638 11:32:58.755002 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4639 11:32:58.759146 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4640 11:32:58.765203 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4641 11:32:58.768561 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4642 11:32:58.771876 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4643 11:32:58.771954 ==
4644 11:32:58.775178 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:32:58.778565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4646 11:32:58.778640 ==
4647 11:32:58.781672 DQS Delay:
4648 11:32:58.781747 DQS0 = 0, DQS1 = 0
4649 11:32:58.785195 DQM Delay:
4650 11:32:58.785324 DQM0 = 37, DQM1 = 28
4651 11:32:58.788834 DQ Delay:
4652 11:32:58.788935 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4653 11:32:58.791662 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4654 11:32:58.794657 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4655 11:32:58.797946 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4656 11:32:58.798081
4657 11:32:58.801441
4658 11:32:58.808683 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4659 11:32:58.811941 CH1 RK1: MR19=808, MR18=5C5C
4660 11:32:58.818145 CH1_RK1: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4661 11:32:58.821376 [RxdqsGatingPostProcess] freq 600
4662 11:32:58.824999 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4663 11:32:58.828044 Pre-setting of DQS Precalculation
4664 11:32:58.834850 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4665 11:32:58.841439 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4666 11:32:58.847451 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4667 11:32:58.847530
4668 11:32:58.847607
4669 11:32:58.851174 [Calibration Summary] 1200 Mbps
4670 11:32:58.851253 CH 0, Rank 0
4671 11:32:58.854472 SW Impedance : PASS
4672 11:32:58.857936 DUTY Scan : NO K
4673 11:32:58.858014 ZQ Calibration : PASS
4674 11:32:58.861049 Jitter Meter : NO K
4675 11:32:58.864462 CBT Training : PASS
4676 11:32:58.864540 Write leveling : PASS
4677 11:32:58.868933 RX DQS gating : PASS
4678 11:32:58.869010 RX DQ/DQS(RDDQC) : PASS
4679 11:32:58.871146 TX DQ/DQS : PASS
4680 11:32:58.875312 RX DATLAT : PASS
4681 11:32:58.875390 RX DQ/DQS(Engine): PASS
4682 11:32:58.877518 TX OE : NO K
4683 11:32:58.877596 All Pass.
4684 11:32:58.877672
4685 11:32:58.880601 CH 0, Rank 1
4686 11:32:58.880678 SW Impedance : PASS
4687 11:32:58.883882 DUTY Scan : NO K
4688 11:32:58.887299 ZQ Calibration : PASS
4689 11:32:58.887377 Jitter Meter : NO K
4690 11:32:58.891138 CBT Training : PASS
4691 11:32:58.894262 Write leveling : PASS
4692 11:32:58.894340 RX DQS gating : PASS
4693 11:32:58.897103 RX DQ/DQS(RDDQC) : PASS
4694 11:32:58.900841 TX DQ/DQS : PASS
4695 11:32:58.900922 RX DATLAT : PASS
4696 11:32:58.904116 RX DQ/DQS(Engine): PASS
4697 11:32:58.907214 TX OE : NO K
4698 11:32:58.907291 All Pass.
4699 11:32:58.907368
4700 11:32:58.907440 CH 1, Rank 0
4701 11:32:58.911336 SW Impedance : PASS
4702 11:32:58.913514 DUTY Scan : NO K
4703 11:32:58.913591 ZQ Calibration : PASS
4704 11:32:58.917056 Jitter Meter : NO K
4705 11:32:58.920326 CBT Training : PASS
4706 11:32:58.920398 Write leveling : PASS
4707 11:32:58.923687 RX DQS gating : PASS
4708 11:32:58.927030 RX DQ/DQS(RDDQC) : PASS
4709 11:32:58.927107 TX DQ/DQS : PASS
4710 11:32:58.930745 RX DATLAT : PASS
4711 11:32:58.933885 RX DQ/DQS(Engine): PASS
4712 11:32:58.933963 TX OE : NO K
4713 11:32:58.934041 All Pass.
4714 11:32:58.934113
4715 11:32:58.937044 CH 1, Rank 1
4716 11:32:58.940164 SW Impedance : PASS
4717 11:32:58.940241 DUTY Scan : NO K
4718 11:32:58.943752 ZQ Calibration : PASS
4719 11:32:58.943831 Jitter Meter : NO K
4720 11:32:58.947371 CBT Training : PASS
4721 11:32:58.950542 Write leveling : PASS
4722 11:32:58.950620 RX DQS gating : PASS
4723 11:32:58.953751 RX DQ/DQS(RDDQC) : PASS
4724 11:32:58.956703 TX DQ/DQS : PASS
4725 11:32:58.956782 RX DATLAT : PASS
4726 11:32:58.960172 RX DQ/DQS(Engine): PASS
4727 11:32:58.963328 TX OE : NO K
4728 11:32:58.963406 All Pass.
4729 11:32:58.963483
4730 11:32:58.966266 DramC Write-DBI off
4731 11:32:58.966344 PER_BANK_REFRESH: Hybrid Mode
4732 11:32:58.970258 TX_TRACKING: ON
4733 11:32:58.980429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4734 11:32:58.983502 [FAST_K] Save calibration result to emmc
4735 11:32:58.986489 dramc_set_vcore_voltage set vcore to 662500
4736 11:32:58.986571 Read voltage for 933, 3
4737 11:32:58.989406 Vio18 = 0
4738 11:32:58.989483 Vcore = 662500
4739 11:32:58.989560 Vdram = 0
4740 11:32:58.992792 Vddq = 0
4741 11:32:58.992869 Vmddr = 0
4742 11:32:58.999480 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4743 11:32:59.002833 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4744 11:32:59.006005 MEM_TYPE=3, freq_sel=17
4745 11:32:59.009746 sv_algorithm_assistance_LP4_1600
4746 11:32:59.012837 ============ PULL DRAM RESETB DOWN ============
4747 11:32:59.016016 ========== PULL DRAM RESETB DOWN end =========
4748 11:32:59.023101 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4749 11:32:59.026487 ===================================
4750 11:32:59.026565 LPDDR4 DRAM CONFIGURATION
4751 11:32:59.029306 ===================================
4752 11:32:59.032561 EX_ROW_EN[0] = 0x0
4753 11:32:59.036008 EX_ROW_EN[1] = 0x0
4754 11:32:59.036085 LP4Y_EN = 0x0
4755 11:32:59.039065 WORK_FSP = 0x0
4756 11:32:59.039143 WL = 0x3
4757 11:32:59.042259 RL = 0x3
4758 11:32:59.042336 BL = 0x2
4759 11:32:59.045739 RPST = 0x0
4760 11:32:59.045816 RD_PRE = 0x0
4761 11:32:59.049788 WR_PRE = 0x1
4762 11:32:59.049865 WR_PST = 0x0
4763 11:32:59.054471 DBI_WR = 0x0
4764 11:32:59.054568 DBI_RD = 0x0
4765 11:32:59.055744 OTF = 0x1
4766 11:32:59.058732 ===================================
4767 11:32:59.062415 ===================================
4768 11:32:59.062492 ANA top config
4769 11:32:59.066393 ===================================
4770 11:32:59.069216 DLL_ASYNC_EN = 0
4771 11:32:59.072294 ALL_SLAVE_EN = 1
4772 11:32:59.075947 NEW_RANK_MODE = 1
4773 11:32:59.076030 DLL_IDLE_MODE = 1
4774 11:32:59.079199 LP45_APHY_COMB_EN = 1
4775 11:32:59.082150 TX_ODT_DIS = 1
4776 11:32:59.085566 NEW_8X_MODE = 1
4777 11:32:59.089053 ===================================
4778 11:32:59.091894 ===================================
4779 11:32:59.095737 data_rate = 1866
4780 11:32:59.095813 CKR = 1
4781 11:32:59.098871 DQ_P2S_RATIO = 8
4782 11:32:59.102510 ===================================
4783 11:32:59.105541 CA_P2S_RATIO = 8
4784 11:32:59.109229 DQ_CA_OPEN = 0
4785 11:32:59.111836 DQ_SEMI_OPEN = 0
4786 11:32:59.115273 CA_SEMI_OPEN = 0
4787 11:32:59.115348 CA_FULL_RATE = 0
4788 11:32:59.118999 DQ_CKDIV4_EN = 1
4789 11:32:59.121667 CA_CKDIV4_EN = 1
4790 11:32:59.125525 CA_PREDIV_EN = 0
4791 11:32:59.128547 PH8_DLY = 0
4792 11:32:59.132051 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4793 11:32:59.132126 DQ_AAMCK_DIV = 4
4794 11:32:59.135620 CA_AAMCK_DIV = 4
4795 11:32:59.138739 CA_ADMCK_DIV = 4
4796 11:32:59.142047 DQ_TRACK_CA_EN = 0
4797 11:32:59.145136 CA_PICK = 933
4798 11:32:59.148146 CA_MCKIO = 933
4799 11:32:59.152713 MCKIO_SEMI = 0
4800 11:32:59.152788 PLL_FREQ = 3732
4801 11:32:59.154762 DQ_UI_PI_RATIO = 32
4802 11:32:59.158142 CA_UI_PI_RATIO = 0
4803 11:32:59.161599 ===================================
4804 11:32:59.164538 ===================================
4805 11:32:59.168180 memory_type:LPDDR4
4806 11:32:59.168255 GP_NUM : 10
4807 11:32:59.171152 SRAM_EN : 1
4808 11:32:59.174499 MD32_EN : 0
4809 11:32:59.178019 ===================================
4810 11:32:59.178094 [ANA_INIT] >>>>>>>>>>>>>>
4811 11:32:59.181158 <<<<<< [CONFIGURE PHASE]: ANA_TX
4812 11:32:59.184545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4813 11:32:59.188395 ===================================
4814 11:32:59.191387 data_rate = 1866,PCW = 0X8f00
4815 11:32:59.194415 ===================================
4816 11:32:59.198338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4817 11:32:59.204586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4818 11:32:59.208450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4819 11:32:59.214274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4820 11:32:59.217909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4821 11:32:59.220834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4822 11:32:59.224093 [ANA_INIT] flow start
4823 11:32:59.224167 [ANA_INIT] PLL >>>>>>>>
4824 11:32:59.227706 [ANA_INIT] PLL <<<<<<<<
4825 11:32:59.231373 [ANA_INIT] MIDPI >>>>>>>>
4826 11:32:59.231447 [ANA_INIT] MIDPI <<<<<<<<
4827 11:32:59.234291 [ANA_INIT] DLL >>>>>>>>
4828 11:32:59.237798 [ANA_INIT] flow end
4829 11:32:59.241368 ============ LP4 DIFF to SE enter ============
4830 11:32:59.244559 ============ LP4 DIFF to SE exit ============
4831 11:32:59.247590 [ANA_INIT] <<<<<<<<<<<<<
4832 11:32:59.250728 [Flow] Enable top DCM control >>>>>
4833 11:32:59.254117 [Flow] Enable top DCM control <<<<<
4834 11:32:59.257978 Enable DLL master slave shuffle
4835 11:32:59.260888 ==============================================================
4836 11:32:59.264118 Gating Mode config
4837 11:32:59.270526 ==============================================================
4838 11:32:59.270602 Config description:
4839 11:32:59.280947 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4840 11:32:59.287912 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4841 11:32:59.293833 SELPH_MODE 0: By rank 1: By Phase
4842 11:32:59.297200 ==============================================================
4843 11:32:59.300578 GAT_TRACK_EN = 1
4844 11:32:59.303995 RX_GATING_MODE = 2
4845 11:32:59.306986 RX_GATING_TRACK_MODE = 2
4846 11:32:59.310359 SELPH_MODE = 1
4847 11:32:59.313342 PICG_EARLY_EN = 1
4848 11:32:59.317026 VALID_LAT_VALUE = 1
4849 11:32:59.319918 ==============================================================
4850 11:32:59.323594 Enter into Gating configuration >>>>
4851 11:32:59.326821 Exit from Gating configuration <<<<
4852 11:32:59.330064 Enter into DVFS_PRE_config >>>>>
4853 11:32:59.343580 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4854 11:32:59.346452 Exit from DVFS_PRE_config <<<<<
4855 11:32:59.350405 Enter into PICG configuration >>>>
4856 11:32:59.350480 Exit from PICG configuration <<<<
4857 11:32:59.353486 [RX_INPUT] configuration >>>>>
4858 11:32:59.356895 [RX_INPUT] configuration <<<<<
4859 11:32:59.363059 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4860 11:32:59.366480 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4861 11:32:59.373594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4862 11:32:59.379990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4863 11:32:59.386373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4864 11:32:59.392731 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4865 11:32:59.396211 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4866 11:32:59.399426 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4867 11:32:59.403025 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4868 11:32:59.409423 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4869 11:32:59.412523 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4870 11:32:59.416247 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 11:32:59.419394 ===================================
4872 11:32:59.422821 LPDDR4 DRAM CONFIGURATION
4873 11:32:59.425707 ===================================
4874 11:32:59.428957 EX_ROW_EN[0] = 0x0
4875 11:32:59.429032 EX_ROW_EN[1] = 0x0
4876 11:32:59.433154 LP4Y_EN = 0x0
4877 11:32:59.433273 WORK_FSP = 0x0
4878 11:32:59.435818 WL = 0x3
4879 11:32:59.435892 RL = 0x3
4880 11:32:59.438849 BL = 0x2
4881 11:32:59.438924 RPST = 0x0
4882 11:32:59.443053 RD_PRE = 0x0
4883 11:32:59.443129 WR_PRE = 0x1
4884 11:32:59.445496 WR_PST = 0x0
4885 11:32:59.448958 DBI_WR = 0x0
4886 11:32:59.449033 DBI_RD = 0x0
4887 11:32:59.452389 OTF = 0x1
4888 11:32:59.455642 ===================================
4889 11:32:59.459886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4890 11:32:59.462126 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4891 11:32:59.465882 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4892 11:32:59.468976 ===================================
4893 11:32:59.472887 LPDDR4 DRAM CONFIGURATION
4894 11:32:59.475388 ===================================
4895 11:32:59.478802 EX_ROW_EN[0] = 0x10
4896 11:32:59.478880 EX_ROW_EN[1] = 0x0
4897 11:32:59.482339 LP4Y_EN = 0x0
4898 11:32:59.482413 WORK_FSP = 0x0
4899 11:32:59.485764 WL = 0x3
4900 11:32:59.485838 RL = 0x3
4901 11:32:59.489915 BL = 0x2
4902 11:32:59.490014 RPST = 0x0
4903 11:32:59.491769 RD_PRE = 0x0
4904 11:32:59.491856 WR_PRE = 0x1
4905 11:32:59.495670 WR_PST = 0x0
4906 11:32:59.495744 DBI_WR = 0x0
4907 11:32:59.498447 DBI_RD = 0x0
4908 11:32:59.502236 OTF = 0x1
4909 11:32:59.505554 ===================================
4910 11:32:59.508467 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4911 11:32:59.513826 nWR fixed to 30
4912 11:32:59.517512 [ModeRegInit_LP4] CH0 RK0
4913 11:32:59.517587 [ModeRegInit_LP4] CH0 RK1
4914 11:32:59.520378 [ModeRegInit_LP4] CH1 RK0
4915 11:32:59.523863 [ModeRegInit_LP4] CH1 RK1
4916 11:32:59.523937 match AC timing 8
4917 11:32:59.530097 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4918 11:32:59.534041 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4919 11:32:59.537403 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4920 11:32:59.544941 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4921 11:32:59.546841 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4922 11:32:59.546916 ==
4923 11:32:59.550236 Dram Type= 6, Freq= 0, CH_0, rank 0
4924 11:32:59.553831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4925 11:32:59.553917 ==
4926 11:32:59.559861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4927 11:32:59.566889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4928 11:32:59.570502 [CA 0] Center 38 (8~69) winsize 62
4929 11:32:59.573305 [CA 1] Center 38 (8~69) winsize 62
4930 11:32:59.576843 [CA 2] Center 36 (6~67) winsize 62
4931 11:32:59.579689 [CA 3] Center 36 (6~66) winsize 61
4932 11:32:59.583452 [CA 4] Center 35 (5~65) winsize 61
4933 11:32:59.586438 [CA 5] Center 34 (4~65) winsize 62
4934 11:32:59.586528
4935 11:32:59.590236 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4936 11:32:59.590300
4937 11:32:59.593124 [CATrainingPosCal] consider 1 rank data
4938 11:32:59.596253 u2DelayCellTimex100 = 270/100 ps
4939 11:32:59.600362 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4940 11:32:59.603047 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4941 11:32:59.606953 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4942 11:32:59.609745 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4943 11:32:59.613173 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4944 11:32:59.619616 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4945 11:32:59.619704
4946 11:32:59.623692 CA PerBit enable=1, Macro0, CA PI delay=34
4947 11:32:59.623768
4948 11:32:59.626108 [CBTSetCACLKResult] CA Dly = 34
4949 11:32:59.626183 CS Dly: 7 (0~38)
4950 11:32:59.626242 ==
4951 11:32:59.630112 Dram Type= 6, Freq= 0, CH_0, rank 1
4952 11:32:59.632994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4953 11:32:59.636230 ==
4954 11:32:59.639385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4955 11:32:59.646369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4956 11:32:59.649500 [CA 0] Center 38 (8~69) winsize 62
4957 11:32:59.653495 [CA 1] Center 38 (7~69) winsize 63
4958 11:32:59.656271 [CA 2] Center 36 (5~67) winsize 63
4959 11:32:59.659838 [CA 3] Center 35 (5~66) winsize 62
4960 11:32:59.662844 [CA 4] Center 34 (4~65) winsize 62
4961 11:32:59.666265 [CA 5] Center 34 (4~65) winsize 62
4962 11:32:59.666340
4963 11:32:59.669256 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4964 11:32:59.669404
4965 11:32:59.672875 [CATrainingPosCal] consider 2 rank data
4966 11:32:59.676105 u2DelayCellTimex100 = 270/100 ps
4967 11:32:59.680821 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4968 11:32:59.683866 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4969 11:32:59.686322 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4970 11:32:59.689437 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4971 11:32:59.695843 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4972 11:32:59.699447 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4973 11:32:59.699523
4974 11:32:59.702492 CA PerBit enable=1, Macro0, CA PI delay=34
4975 11:32:59.702566
4976 11:32:59.706853 [CBTSetCACLKResult] CA Dly = 34
4977 11:32:59.706928 CS Dly: 7 (0~39)
4978 11:32:59.706987
4979 11:32:59.710334 ----->DramcWriteLeveling(PI) begin...
4980 11:32:59.710411 ==
4981 11:32:59.712618 Dram Type= 6, Freq= 0, CH_0, rank 0
4982 11:32:59.719714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4983 11:32:59.719795 ==
4984 11:32:59.723085 Write leveling (Byte 0): 30 => 30
4985 11:32:59.723160 Write leveling (Byte 1): 26 => 26
4986 11:32:59.725912 DramcWriteLeveling(PI) end<-----
4987 11:32:59.725986
4988 11:32:59.730480 ==
4989 11:32:59.732611 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 11:32:59.736024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 11:32:59.736100 ==
4992 11:32:59.739303 [Gating] SW mode calibration
4993 11:32:59.746320 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4994 11:32:59.749671 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4995 11:32:59.756313 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4996 11:32:59.759538 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4997 11:32:59.763178 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4998 11:32:59.769858 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4999 11:32:59.772639 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5000 11:32:59.776163 0 10 20 | B1->B0 | 3232 3030 | 0 0 | (0 0) (1 0)
5001 11:32:59.782960 0 10 24 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (1 0)
5002 11:32:59.786268 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5003 11:32:59.789547 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5004 11:32:59.795191 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5005 11:32:59.798969 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5006 11:32:59.802313 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5007 11:32:59.808620 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5008 11:32:59.811765 0 11 20 | B1->B0 | 2727 3030 | 0 1 | (1 1) (0 0)
5009 11:32:59.815130 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5010 11:32:59.822048 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5011 11:32:59.824953 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5012 11:32:59.829029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5013 11:32:59.835042 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5014 11:32:59.838426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5015 11:32:59.841690 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5016 11:32:59.849172 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5017 11:32:59.851393 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5018 11:32:59.855505 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5019 11:32:59.861983 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5020 11:32:59.864975 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5021 11:32:59.868239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5022 11:32:59.874671 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5023 11:32:59.878213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5024 11:32:59.881106 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5025 11:32:59.887762 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5026 11:32:59.892295 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5027 11:32:59.894597 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5028 11:32:59.901559 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5029 11:32:59.904454 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5030 11:32:59.908393 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5031 11:32:59.914312 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5032 11:32:59.917825 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5033 11:32:59.920818 Total UI for P1: 0, mck2ui 16
5034 11:32:59.924056 best dqsien dly found for B0: ( 0, 14, 18)
5035 11:32:59.928167 Total UI for P1: 0, mck2ui 16
5036 11:32:59.930924 best dqsien dly found for B1: ( 0, 14, 18)
5037 11:32:59.934307 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5038 11:32:59.937646 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5039 11:32:59.937713
5040 11:32:59.940605 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5041 11:32:59.943833 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5042 11:32:59.947367 [Gating] SW calibration Done
5043 11:32:59.947442 ==
5044 11:32:59.950451 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 11:32:59.953828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5046 11:32:59.957148 ==
5047 11:32:59.957222 RX Vref Scan: 0
5048 11:32:59.957288
5049 11:32:59.960396 RX Vref 0 -> 0, step: 1
5050 11:32:59.960470
5051 11:32:59.964088 RX Delay -80 -> 252, step: 8
5052 11:32:59.967351 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5053 11:32:59.971075 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5054 11:32:59.974295 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5055 11:32:59.977402 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5056 11:32:59.980348 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5057 11:32:59.987308 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5058 11:32:59.990573 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5059 11:32:59.994035 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5060 11:32:59.997394 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5061 11:33:00.000541 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5062 11:33:00.006723 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5063 11:33:00.010589 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5064 11:33:00.013927 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5065 11:33:00.017480 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5066 11:33:00.020281 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5067 11:33:00.023500 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5068 11:33:00.026638 ==
5069 11:33:00.030032 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 11:33:00.033562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5071 11:33:00.033637 ==
5072 11:33:00.033695 DQS Delay:
5073 11:33:00.036941 DQS0 = 0, DQS1 = 0
5074 11:33:00.037016 DQM Delay:
5075 11:33:00.039904 DQM0 = 94, DQM1 = 86
5076 11:33:00.039979 DQ Delay:
5077 11:33:00.043290 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5078 11:33:00.046700 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =99
5079 11:33:00.050315 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5080 11:33:00.053396 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5081 11:33:00.053471
5082 11:33:00.053528
5083 11:33:00.053581 ==
5084 11:33:00.056812 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 11:33:00.060325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5086 11:33:00.060400 ==
5087 11:33:00.060457
5088 11:33:00.060510
5089 11:33:00.063913 TX Vref Scan disable
5090 11:33:00.066498 == TX Byte 0 ==
5091 11:33:00.069608 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5092 11:33:00.073078 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5093 11:33:00.076306 == TX Byte 1 ==
5094 11:33:00.079430 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5095 11:33:00.083362 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5096 11:33:00.083438 ==
5097 11:33:00.086334 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 11:33:00.093081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5099 11:33:00.093180 ==
5100 11:33:00.093301
5101 11:33:00.093356
5102 11:33:00.093407 TX Vref Scan disable
5103 11:33:00.097301 == TX Byte 0 ==
5104 11:33:00.100874 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5105 11:33:00.107231 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5106 11:33:00.107306 == TX Byte 1 ==
5107 11:33:00.110298 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5108 11:33:00.116873 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5109 11:33:00.116947
5110 11:33:00.117005 [DATLAT]
5111 11:33:00.117057 Freq=933, CH0 RK0
5112 11:33:00.117109
5113 11:33:00.120533 DATLAT Default: 0xd
5114 11:33:00.120607 0, 0xFFFF, sum = 0
5115 11:33:00.123465 1, 0xFFFF, sum = 0
5116 11:33:00.123549 2, 0xFFFF, sum = 0
5117 11:33:00.127678 3, 0xFFFF, sum = 0
5118 11:33:00.130305 4, 0xFFFF, sum = 0
5119 11:33:00.130382 5, 0xFFFF, sum = 0
5120 11:33:00.133755 6, 0xFFFF, sum = 0
5121 11:33:00.133831 7, 0xFFFF, sum = 0
5122 11:33:00.136850 8, 0xFFFF, sum = 0
5123 11:33:00.136925 9, 0xFFFF, sum = 0
5124 11:33:00.140196 10, 0x0, sum = 1
5125 11:33:00.140271 11, 0x0, sum = 2
5126 11:33:00.143980 12, 0x0, sum = 3
5127 11:33:00.144056 13, 0x0, sum = 4
5128 11:33:00.144115 best_step = 11
5129 11:33:00.144168
5130 11:33:00.146617 ==
5131 11:33:00.150094 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 11:33:00.154061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5133 11:33:00.154137 ==
5134 11:33:00.154194 RX Vref Scan: 1
5135 11:33:00.154248
5136 11:33:00.156793 RX Vref 0 -> 0, step: 1
5137 11:33:00.156867
5138 11:33:00.160130 RX Delay -61 -> 252, step: 4
5139 11:33:00.160204
5140 11:33:00.163607 Set Vref, RX VrefLevel [Byte0]: 51
5141 11:33:00.167079 [Byte1]: 51
5142 11:33:00.167154
5143 11:33:00.170223 Final RX Vref Byte 0 = 51 to rank0
5144 11:33:00.173613 Final RX Vref Byte 1 = 51 to rank0
5145 11:33:00.176701 Final RX Vref Byte 0 = 51 to rank1
5146 11:33:00.179755 Final RX Vref Byte 1 = 51 to rank1==
5147 11:33:00.182987 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 11:33:00.187245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5149 11:33:00.189784 ==
5150 11:33:00.189858 DQS Delay:
5151 11:33:00.189917 DQS0 = 0, DQS1 = 0
5152 11:33:00.193437 DQM Delay:
5153 11:33:00.193511 DQM0 = 96, DQM1 = 86
5154 11:33:00.196346 DQ Delay:
5155 11:33:00.196420 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5156 11:33:00.202879 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5157 11:33:00.206776 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5158 11:33:00.209686 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5159 11:33:00.209761
5160 11:33:00.209818
5161 11:33:00.216693 [DQSOSCAuto] RK0, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5162 11:33:00.220049 CH0 RK0: MR19=505, MR18=2020
5163 11:33:00.226613 CH0_RK0: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5164 11:33:00.226687
5165 11:33:00.230220 ----->DramcWriteLeveling(PI) begin...
5166 11:33:00.230301 ==
5167 11:33:00.232896 Dram Type= 6, Freq= 0, CH_0, rank 1
5168 11:33:00.236221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5169 11:33:00.236283 ==
5170 11:33:00.239489 Write leveling (Byte 0): 27 => 27
5171 11:33:00.242956 Write leveling (Byte 1): 26 => 26
5172 11:33:00.246380 DramcWriteLeveling(PI) end<-----
5173 11:33:00.246467
5174 11:33:00.246547 ==
5175 11:33:00.249664 Dram Type= 6, Freq= 0, CH_0, rank 1
5176 11:33:00.252977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5177 11:33:00.253062 ==
5178 11:33:00.256123 [Gating] SW mode calibration
5179 11:33:00.263051 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5180 11:33:00.269539 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5181 11:33:00.273069 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 11:33:00.279509 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 11:33:00.283108 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 11:33:00.285986 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 11:33:00.292383 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 11:33:00.296058 0 10 20 | B1->B0 | 2f2f 2c2c | 0 0 | (1 0) (0 0)
5187 11:33:00.300049 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5188 11:33:00.303008 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:33:00.309498 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:33:00.312935 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 11:33:00.316831 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 11:33:00.322783 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 11:33:00.325919 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 11:33:00.329640 0 11 20 | B1->B0 | 2d2d 3636 | 0 0 | (0 0) (0 0)
5195 11:33:00.336315 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5196 11:33:00.339011 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:33:00.342206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:33:00.348725 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 11:33:00.352011 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 11:33:00.355661 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 11:33:00.362487 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 11:33:00.366971 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5203 11:33:00.368944 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5204 11:33:00.376009 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:33:00.379161 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:33:00.381933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:33:00.388408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:33:00.391761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:33:00.395776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:33:00.401612 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:33:00.405414 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:33:00.408938 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:33:00.415420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:33:00.418641 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:33:00.421649 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:33:00.428727 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:33:00.431552 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 11:33:00.435898 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5219 11:33:00.439084 Total UI for P1: 0, mck2ui 16
5220 11:33:00.442183 best dqsien dly found for B0: ( 0, 14, 16)
5221 11:33:00.448679 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5222 11:33:00.451957 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 11:33:00.455729 Total UI for P1: 0, mck2ui 16
5224 11:33:00.458416 best dqsien dly found for B1: ( 0, 14, 22)
5225 11:33:00.462472 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5226 11:33:00.465051 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5227 11:33:00.465125
5228 11:33:00.468974 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5229 11:33:00.472026 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5230 11:33:00.475175 [Gating] SW calibration Done
5231 11:33:00.475250 ==
5232 11:33:00.478280 Dram Type= 6, Freq= 0, CH_0, rank 1
5233 11:33:00.481552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5234 11:33:00.481628 ==
5235 11:33:00.485491 RX Vref Scan: 0
5236 11:33:00.485566
5237 11:33:00.488389 RX Vref 0 -> 0, step: 1
5238 11:33:00.488464
5239 11:33:00.488525 RX Delay -80 -> 252, step: 8
5240 11:33:00.495830 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5241 11:33:00.498850 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5242 11:33:00.501768 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5243 11:33:00.505507 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5244 11:33:00.508139 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5245 11:33:00.512248 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5246 11:33:00.517965 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5247 11:33:00.522029 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5248 11:33:00.524769 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5249 11:33:00.528427 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5250 11:33:00.531334 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5251 11:33:00.538243 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5252 11:33:00.541755 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5253 11:33:00.544285 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5254 11:33:00.547780 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5255 11:33:00.551538 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5256 11:33:00.551612 ==
5257 11:33:00.554497 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 11:33:00.561694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 11:33:00.561769 ==
5260 11:33:00.561828 DQS Delay:
5261 11:33:00.564809 DQS0 = 0, DQS1 = 0
5262 11:33:00.564883 DQM Delay:
5263 11:33:00.564940 DQM0 = 98, DQM1 = 89
5264 11:33:00.567865 DQ Delay:
5265 11:33:00.570961 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =91
5266 11:33:00.574600 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5267 11:33:00.577631 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5268 11:33:00.581728 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5269 11:33:00.581803
5270 11:33:00.581860
5271 11:33:00.581914 ==
5272 11:33:00.584715 Dram Type= 6, Freq= 0, CH_0, rank 1
5273 11:33:00.587689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5274 11:33:00.587764 ==
5275 11:33:00.587822
5276 11:33:00.587875
5277 11:33:00.591063 TX Vref Scan disable
5278 11:33:00.594242 == TX Byte 0 ==
5279 11:33:00.598343 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5280 11:33:00.601019 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5281 11:33:00.604566 == TX Byte 1 ==
5282 11:33:00.608011 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5283 11:33:00.611184 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5284 11:33:00.611259 ==
5285 11:33:00.614547 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 11:33:00.617648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5287 11:33:00.617723 ==
5288 11:33:00.620702
5289 11:33:00.620775
5290 11:33:00.620833 TX Vref Scan disable
5291 11:33:00.624108 == TX Byte 0 ==
5292 11:33:00.627707 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5293 11:33:00.630955 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5294 11:33:00.634509 == TX Byte 1 ==
5295 11:33:00.637785 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5296 11:33:00.641149 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5297 11:33:00.644956
5298 11:33:00.645080 [DATLAT]
5299 11:33:00.645167 Freq=933, CH0 RK1
5300 11:33:00.645269
5301 11:33:00.647616 DATLAT Default: 0xb
5302 11:33:00.647691 0, 0xFFFF, sum = 0
5303 11:33:00.650962 1, 0xFFFF, sum = 0
5304 11:33:00.651038 2, 0xFFFF, sum = 0
5305 11:33:00.654066 3, 0xFFFF, sum = 0
5306 11:33:00.654142 4, 0xFFFF, sum = 0
5307 11:33:00.658011 5, 0xFFFF, sum = 0
5308 11:33:00.661126 6, 0xFFFF, sum = 0
5309 11:33:00.661202 7, 0xFFFF, sum = 0
5310 11:33:00.663913 8, 0xFFFF, sum = 0
5311 11:33:00.663989 9, 0xFFFF, sum = 0
5312 11:33:00.668519 10, 0x0, sum = 1
5313 11:33:00.668594 11, 0x0, sum = 2
5314 11:33:00.670765 12, 0x0, sum = 3
5315 11:33:00.670890 13, 0x0, sum = 4
5316 11:33:00.670978 best_step = 11
5317 11:33:00.671058
5318 11:33:00.673844 ==
5319 11:33:00.677405 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 11:33:00.680803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5321 11:33:00.680867 ==
5322 11:33:00.680922 RX Vref Scan: 0
5323 11:33:00.680976
5324 11:33:00.684007 RX Vref 0 -> 0, step: 1
5325 11:33:00.684092
5326 11:33:00.687341 RX Delay -69 -> 252, step: 4
5327 11:33:00.690870 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5328 11:33:00.697768 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5329 11:33:00.700308 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5330 11:33:00.704349 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5331 11:33:00.707238 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5332 11:33:00.711092 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5333 11:33:00.713981 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5334 11:33:00.720360 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5335 11:33:00.723934 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5336 11:33:00.728019 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5337 11:33:00.730487 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5338 11:33:00.733838 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5339 11:33:00.740476 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5340 11:33:00.744416 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5341 11:33:00.747060 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5342 11:33:00.750309 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5343 11:33:00.750385 ==
5344 11:33:00.753312 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 11:33:00.757457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 11:33:00.759995 ==
5347 11:33:00.760070 DQS Delay:
5348 11:33:00.760128 DQS0 = 0, DQS1 = 0
5349 11:33:00.763330 DQM Delay:
5350 11:33:00.763404 DQM0 = 97, DQM1 = 86
5351 11:33:00.766524 DQ Delay:
5352 11:33:00.770251 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5353 11:33:00.773474 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =106
5354 11:33:00.776597 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5355 11:33:00.779988 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5356 11:33:00.780063
5357 11:33:00.780120
5358 11:33:00.786882 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5359 11:33:00.789691 CH0 RK1: MR19=505, MR18=2D2D
5360 11:33:00.796784 CH0_RK1: MR19=0x505, MR18=0x2D2D, DQSOSC=407, MR23=63, INC=65, DEC=43
5361 11:33:00.799850 [RxdqsGatingPostProcess] freq 933
5362 11:33:00.803429 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5363 11:33:00.806330 Pre-setting of DQS Precalculation
5364 11:33:00.813256 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5365 11:33:00.813331 ==
5366 11:33:00.816366 Dram Type= 6, Freq= 0, CH_1, rank 0
5367 11:33:00.819684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5368 11:33:00.819760 ==
5369 11:33:00.826303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5370 11:33:00.832852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5371 11:33:00.836306 [CA 0] Center 37 (6~68) winsize 63
5372 11:33:00.839580 [CA 1] Center 37 (6~68) winsize 63
5373 11:33:00.842582 [CA 2] Center 34 (4~65) winsize 62
5374 11:33:00.846254 [CA 3] Center 34 (4~65) winsize 62
5375 11:33:00.849879 [CA 4] Center 33 (2~64) winsize 63
5376 11:33:00.849954 [CA 5] Center 33 (2~64) winsize 63
5377 11:33:00.852909
5378 11:33:00.856994 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5379 11:33:00.857093
5380 11:33:00.859518 [CATrainingPosCal] consider 1 rank data
5381 11:33:00.862404 u2DelayCellTimex100 = 270/100 ps
5382 11:33:00.866161 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5383 11:33:00.868982 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5384 11:33:00.872921 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5385 11:33:00.875666 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5386 11:33:00.879169 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5387 11:33:00.882299 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5388 11:33:00.882373
5389 11:33:00.885952 CA PerBit enable=1, Macro0, CA PI delay=33
5390 11:33:00.889080
5391 11:33:00.889154 [CBTSetCACLKResult] CA Dly = 33
5392 11:33:00.892270 CS Dly: 5 (0~36)
5393 11:33:00.892345 ==
5394 11:33:00.895609 Dram Type= 6, Freq= 0, CH_1, rank 1
5395 11:33:00.898866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5396 11:33:00.898941 ==
5397 11:33:00.905454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5398 11:33:00.912052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5399 11:33:00.916142 [CA 0] Center 37 (6~68) winsize 63
5400 11:33:00.919469 [CA 1] Center 37 (6~68) winsize 63
5401 11:33:00.922212 [CA 2] Center 34 (4~65) winsize 62
5402 11:33:00.926015 [CA 3] Center 33 (3~64) winsize 62
5403 11:33:00.928549 [CA 4] Center 33 (2~64) winsize 63
5404 11:33:00.932248 [CA 5] Center 32 (2~63) winsize 62
5405 11:33:00.932322
5406 11:33:00.934980 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5407 11:33:00.935054
5408 11:33:00.938638 [CATrainingPosCal] consider 2 rank data
5409 11:33:00.942496 u2DelayCellTimex100 = 270/100 ps
5410 11:33:00.945126 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5411 11:33:00.948392 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5412 11:33:00.951435 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5413 11:33:00.955562 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5414 11:33:00.958199 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5415 11:33:00.965250 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5416 11:33:00.965364
5417 11:33:00.969150 CA PerBit enable=1, Macro0, CA PI delay=32
5418 11:33:00.969236
5419 11:33:00.971485 [CBTSetCACLKResult] CA Dly = 32
5420 11:33:00.971559 CS Dly: 5 (0~37)
5421 11:33:00.971616
5422 11:33:00.974831 ----->DramcWriteLeveling(PI) begin...
5423 11:33:00.974906 ==
5424 11:33:00.978584 Dram Type= 6, Freq= 0, CH_1, rank 0
5425 11:33:00.981587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5426 11:33:00.984965 ==
5427 11:33:00.985048 Write leveling (Byte 0): 23 => 23
5428 11:33:00.988456 Write leveling (Byte 1): 24 => 24
5429 11:33:00.991449 DramcWriteLeveling(PI) end<-----
5430 11:33:00.991521
5431 11:33:00.991578 ==
5432 11:33:00.994768 Dram Type= 6, Freq= 0, CH_1, rank 0
5433 11:33:01.001382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5434 11:33:01.001480 ==
5435 11:33:01.004486 [Gating] SW mode calibration
5436 11:33:01.011482 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5437 11:33:01.014894 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5438 11:33:01.021830 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5439 11:33:01.024480 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5440 11:33:01.028309 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5441 11:33:01.034490 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5442 11:33:01.038096 0 10 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5443 11:33:01.041385 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5444 11:33:01.048580 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5445 11:33:01.051119 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5446 11:33:01.054036 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5447 11:33:01.060637 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5448 11:33:01.064609 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5449 11:33:01.068096 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5450 11:33:01.074965 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5451 11:33:01.077386 0 11 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
5452 11:33:01.081033 0 11 24 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
5453 11:33:01.087274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5454 11:33:01.090700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5455 11:33:01.093929 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5456 11:33:01.101252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5457 11:33:01.104167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5458 11:33:01.107977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5459 11:33:01.110905 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5460 11:33:01.117113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 11:33:01.122100 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 11:33:01.123660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5463 11:33:01.130257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5464 11:33:01.133426 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5465 11:33:01.140153 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5466 11:33:01.143991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5467 11:33:01.146769 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5468 11:33:01.149999 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5469 11:33:01.156939 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5470 11:33:01.160199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5471 11:33:01.163171 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5472 11:33:01.170501 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5473 11:33:01.173017 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5474 11:33:01.176954 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5475 11:33:01.183672 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5476 11:33:01.186191 Total UI for P1: 0, mck2ui 16
5477 11:33:01.189998 best dqsien dly found for B0: ( 0, 14, 16)
5478 11:33:01.193403 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5479 11:33:01.196617 Total UI for P1: 0, mck2ui 16
5480 11:33:01.199940 best dqsien dly found for B1: ( 0, 14, 20)
5481 11:33:01.203048 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5482 11:33:01.206255 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5483 11:33:01.206329
5484 11:33:01.209688 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5485 11:33:01.216520 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5486 11:33:01.216595 [Gating] SW calibration Done
5487 11:33:01.216652 ==
5488 11:33:01.220223 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 11:33:01.226499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5490 11:33:01.226575 ==
5491 11:33:01.226632 RX Vref Scan: 0
5492 11:33:01.226685
5493 11:33:01.229717 RX Vref 0 -> 0, step: 1
5494 11:33:01.229791
5495 11:33:01.232805 RX Delay -80 -> 252, step: 8
5496 11:33:01.235871 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5497 11:33:01.239733 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5498 11:33:01.242506 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5499 11:33:01.249187 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5500 11:33:01.252264 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5501 11:33:01.255801 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5502 11:33:01.259713 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5503 11:33:01.262566 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5504 11:33:01.266118 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5505 11:33:01.272233 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5506 11:33:01.276258 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5507 11:33:01.278831 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5508 11:33:01.282890 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5509 11:33:01.285502 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5510 11:33:01.292636 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5511 11:33:01.296338 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5512 11:33:01.296412 ==
5513 11:33:01.300040 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 11:33:01.302632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 11:33:01.302707 ==
5516 11:33:01.305957 DQS Delay:
5517 11:33:01.306032 DQS0 = 0, DQS1 = 0
5518 11:33:01.306090 DQM Delay:
5519 11:33:01.309084 DQM0 = 94, DQM1 = 86
5520 11:33:01.309175 DQ Delay:
5521 11:33:01.312590 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5522 11:33:01.315830 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5523 11:33:01.318897 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5524 11:33:01.322236 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =91
5525 11:33:01.322299
5526 11:33:01.322352
5527 11:33:01.322402 ==
5528 11:33:01.325805 Dram Type= 6, Freq= 0, CH_1, rank 0
5529 11:33:01.332170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5530 11:33:01.332236 ==
5531 11:33:01.332292
5532 11:33:01.332344
5533 11:33:01.332393 TX Vref Scan disable
5534 11:33:01.335547 == TX Byte 0 ==
5535 11:33:01.338813 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5536 11:33:01.345392 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5537 11:33:01.345481 == TX Byte 1 ==
5538 11:33:01.348606 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5539 11:33:01.355121 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5540 11:33:01.355189 ==
5541 11:33:01.358614 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 11:33:01.361896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5543 11:33:01.361987 ==
5544 11:33:01.362068
5545 11:33:01.362144
5546 11:33:01.365019 TX Vref Scan disable
5547 11:33:01.365107 == TX Byte 0 ==
5548 11:33:01.372396 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5549 11:33:01.375086 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5550 11:33:01.375159 == TX Byte 1 ==
5551 11:33:01.381781 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5552 11:33:01.385126 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5553 11:33:01.385219
5554 11:33:01.385288 [DATLAT]
5555 11:33:01.388236 Freq=933, CH1 RK0
5556 11:33:01.388302
5557 11:33:01.388355 DATLAT Default: 0xd
5558 11:33:01.391377 0, 0xFFFF, sum = 0
5559 11:33:01.391440 1, 0xFFFF, sum = 0
5560 11:33:01.395610 2, 0xFFFF, sum = 0
5561 11:33:01.399393 3, 0xFFFF, sum = 0
5562 11:33:01.399457 4, 0xFFFF, sum = 0
5563 11:33:01.401627 5, 0xFFFF, sum = 0
5564 11:33:01.401690 6, 0xFFFF, sum = 0
5565 11:33:01.405704 7, 0xFFFF, sum = 0
5566 11:33:01.405769 8, 0xFFFF, sum = 0
5567 11:33:01.408471 9, 0xFFFF, sum = 0
5568 11:33:01.408531 10, 0x0, sum = 1
5569 11:33:01.411932 11, 0x0, sum = 2
5570 11:33:01.411998 12, 0x0, sum = 3
5571 11:33:01.414913 13, 0x0, sum = 4
5572 11:33:01.414998 best_step = 11
5573 11:33:01.415086
5574 11:33:01.415166 ==
5575 11:33:01.418280 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 11:33:01.421748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5577 11:33:01.421808 ==
5578 11:33:01.425266 RX Vref Scan: 1
5579 11:33:01.425325
5580 11:33:01.428106 RX Vref 0 -> 0, step: 1
5581 11:33:01.428167
5582 11:33:01.428222 RX Delay -69 -> 252, step: 4
5583 11:33:01.428273
5584 11:33:01.431488 Set Vref, RX VrefLevel [Byte0]: 52
5585 11:33:01.434493 [Byte1]: 52
5586 11:33:01.439536
5587 11:33:01.439600 Final RX Vref Byte 0 = 52 to rank0
5588 11:33:01.443202 Final RX Vref Byte 1 = 52 to rank0
5589 11:33:01.446526 Final RX Vref Byte 0 = 52 to rank1
5590 11:33:01.449439 Final RX Vref Byte 1 = 52 to rank1==
5591 11:33:01.452753 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 11:33:01.459440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5593 11:33:01.459508 ==
5594 11:33:01.459563 DQS Delay:
5595 11:33:01.459620 DQS0 = 0, DQS1 = 0
5596 11:33:01.462977 DQM Delay:
5597 11:33:01.463063 DQM0 = 94, DQM1 = 88
5598 11:33:01.466409 DQ Delay:
5599 11:33:01.469281 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5600 11:33:01.473508 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5601 11:33:01.476447 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =80
5602 11:33:01.479409 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5603 11:33:01.479483
5604 11:33:01.479541
5605 11:33:01.486548 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
5606 11:33:01.489783 CH1 RK0: MR19=505, MR18=3B3B
5607 11:33:01.496561 CH1_RK0: MR19=0x505, MR18=0x3B3B, DQSOSC=403, MR23=63, INC=66, DEC=44
5608 11:33:01.496636
5609 11:33:01.500057 ----->DramcWriteLeveling(PI) begin...
5610 11:33:01.500133 ==
5611 11:33:01.503544 Dram Type= 6, Freq= 0, CH_1, rank 1
5612 11:33:01.505844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5613 11:33:01.505920 ==
5614 11:33:01.508921 Write leveling (Byte 0): 26 => 26
5615 11:33:01.512422 Write leveling (Byte 1): 24 => 24
5616 11:33:01.516017 DramcWriteLeveling(PI) end<-----
5617 11:33:01.516091
5618 11:33:01.516148 ==
5619 11:33:01.519157 Dram Type= 6, Freq= 0, CH_1, rank 1
5620 11:33:01.522438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5621 11:33:01.522513 ==
5622 11:33:01.525638 [Gating] SW mode calibration
5623 11:33:01.532524 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5624 11:33:01.538812 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5625 11:33:01.541935 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 11:33:01.548979 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 11:33:01.552075 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 11:33:01.555267 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 11:33:01.562393 0 10 16 | B1->B0 | 3434 2828 | 1 1 | (1 0) (1 1)
5630 11:33:01.566051 0 10 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5631 11:33:01.568872 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 11:33:01.575774 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 11:33:01.578893 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 11:33:01.581867 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 11:33:01.588521 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 11:33:01.591914 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5637 11:33:01.595069 0 11 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5638 11:33:01.602334 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5639 11:33:01.605249 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 11:33:01.608750 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 11:33:01.614713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 11:33:01.619310 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 11:33:01.622310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 11:33:01.625403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 11:33:01.631509 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5646 11:33:01.634694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5647 11:33:01.638415 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:33:01.644701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:33:01.648108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:33:01.651083 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:33:01.657607 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:33:01.661525 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:33:01.664913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:33:01.671176 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:33:01.675057 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:33:01.677854 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:33:01.684829 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:33:01.687388 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:33:01.691191 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:33:01.697975 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:33:01.700811 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5662 11:33:01.704329 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5663 11:33:01.707976 Total UI for P1: 0, mck2ui 16
5664 11:33:01.710927 best dqsien dly found for B0: ( 0, 14, 16)
5665 11:33:01.717563 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:33:01.717639 Total UI for P1: 0, mck2ui 16
5667 11:33:01.725106 best dqsien dly found for B1: ( 0, 14, 20)
5668 11:33:01.728381 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5669 11:33:01.731139 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5670 11:33:01.731214
5671 11:33:01.734378 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5672 11:33:01.738080 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5673 11:33:01.741334 [Gating] SW calibration Done
5674 11:33:01.741409 ==
5675 11:33:01.744612 Dram Type= 6, Freq= 0, CH_1, rank 1
5676 11:33:01.748219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5677 11:33:01.748320 ==
5678 11:33:01.750829 RX Vref Scan: 0
5679 11:33:01.750914
5680 11:33:01.750972 RX Vref 0 -> 0, step: 1
5681 11:33:01.754314
5682 11:33:01.754388 RX Delay -80 -> 252, step: 8
5683 11:33:01.760984 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5684 11:33:01.764200 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5685 11:33:01.767463 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5686 11:33:01.771123 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5687 11:33:01.773886 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5688 11:33:01.777556 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5689 11:33:01.780521 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5690 11:33:01.786923 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5691 11:33:01.790786 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5692 11:33:01.793690 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5693 11:33:01.797664 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5694 11:33:01.800547 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5695 11:33:01.806735 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5696 11:33:01.810356 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5697 11:33:01.813732 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5698 11:33:01.816781 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5699 11:33:01.816856 ==
5700 11:33:01.820219 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 11:33:01.824669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 11:33:01.824744 ==
5703 11:33:01.827107 DQS Delay:
5704 11:33:01.827181 DQS0 = 0, DQS1 = 0
5705 11:33:01.830677 DQM Delay:
5706 11:33:01.830751 DQM0 = 96, DQM1 = 88
5707 11:33:01.830811 DQ Delay:
5708 11:33:01.833472 DQ0 =99, DQ1 =91, DQ2 =91, DQ3 =91
5709 11:33:01.837282 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5710 11:33:01.840241 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5711 11:33:01.843814 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5712 11:33:01.843889
5713 11:33:01.846588
5714 11:33:01.846663 ==
5715 11:33:01.850104 Dram Type= 6, Freq= 0, CH_1, rank 1
5716 11:33:01.853713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5717 11:33:01.853788 ==
5718 11:33:01.853845
5719 11:33:01.853898
5720 11:33:01.857482 TX Vref Scan disable
5721 11:33:01.857556 == TX Byte 0 ==
5722 11:33:01.863686 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5723 11:33:01.867035 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5724 11:33:01.867110 == TX Byte 1 ==
5725 11:33:01.873572 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5726 11:33:01.877160 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5727 11:33:01.877241 ==
5728 11:33:01.880316 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 11:33:01.883738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5730 11:33:01.883813 ==
5731 11:33:01.883871
5732 11:33:01.883924
5733 11:33:01.886303 TX Vref Scan disable
5734 11:33:01.889776 == TX Byte 0 ==
5735 11:33:01.893541 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5736 11:33:01.896860 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5737 11:33:01.900216 == TX Byte 1 ==
5738 11:33:01.903606 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5739 11:33:01.906742 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5740 11:33:01.906818
5741 11:33:01.910100 [DATLAT]
5742 11:33:01.910174 Freq=933, CH1 RK1
5743 11:33:01.910233
5744 11:33:01.913049 DATLAT Default: 0xb
5745 11:33:01.913124 0, 0xFFFF, sum = 0
5746 11:33:01.916296 1, 0xFFFF, sum = 0
5747 11:33:01.916372 2, 0xFFFF, sum = 0
5748 11:33:01.919578 3, 0xFFFF, sum = 0
5749 11:33:01.919653 4, 0xFFFF, sum = 0
5750 11:33:01.923489 5, 0xFFFF, sum = 0
5751 11:33:01.923564 6, 0xFFFF, sum = 0
5752 11:33:01.926069 7, 0xFFFF, sum = 0
5753 11:33:01.926148 8, 0xFFFF, sum = 0
5754 11:33:01.930319 9, 0xFFFF, sum = 0
5755 11:33:01.930395 10, 0x0, sum = 1
5756 11:33:01.932964 11, 0x0, sum = 2
5757 11:33:01.933040 12, 0x0, sum = 3
5758 11:33:01.936844 13, 0x0, sum = 4
5759 11:33:01.936920 best_step = 11
5760 11:33:01.936977
5761 11:33:01.937030 ==
5762 11:33:01.939487 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 11:33:01.946503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5764 11:33:01.946578 ==
5765 11:33:01.946636 RX Vref Scan: 0
5766 11:33:01.946688
5767 11:33:01.949404 RX Vref 0 -> 0, step: 1
5768 11:33:01.949479
5769 11:33:01.952919 RX Delay -69 -> 252, step: 4
5770 11:33:01.956380 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176
5771 11:33:01.959748 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5772 11:33:01.965951 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5773 11:33:01.969454 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5774 11:33:01.972732 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5775 11:33:01.976001 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5776 11:33:01.979231 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5777 11:33:01.982650 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5778 11:33:01.989794 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5779 11:33:01.992717 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5780 11:33:01.995574 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5781 11:33:01.999564 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5782 11:33:02.002568 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5783 11:33:02.009263 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5784 11:33:02.012286 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5785 11:33:02.016091 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5786 11:33:02.016166 ==
5787 11:33:02.019327 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 11:33:02.022473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5789 11:33:02.022549 ==
5790 11:33:02.026219 DQS Delay:
5791 11:33:02.026300 DQS0 = 0, DQS1 = 0
5792 11:33:02.028867 DQM Delay:
5793 11:33:02.028959 DQM0 = 96, DQM1 = 87
5794 11:33:02.029041 DQ Delay:
5795 11:33:02.032586 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5796 11:33:02.035793 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5797 11:33:02.038760 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5798 11:33:02.042602 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5799 11:33:02.042697
5800 11:33:02.042790
5801 11:33:02.051829 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5802 11:33:02.055583 CH1 RK1: MR19=505, MR18=2626
5803 11:33:02.061647 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5804 11:33:02.065259 [RxdqsGatingPostProcess] freq 933
5805 11:33:02.068663 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5806 11:33:02.071630 Pre-setting of DQS Precalculation
5807 11:33:02.078278 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5808 11:33:02.084875 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5809 11:33:02.091402 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5810 11:33:02.091478
5811 11:33:02.091537
5812 11:33:02.094853 [Calibration Summary] 1866 Mbps
5813 11:33:02.094929 CH 0, Rank 0
5814 11:33:02.098355 SW Impedance : PASS
5815 11:33:02.101541 DUTY Scan : NO K
5816 11:33:02.101617 ZQ Calibration : PASS
5817 11:33:02.104977 Jitter Meter : NO K
5818 11:33:02.108145 CBT Training : PASS
5819 11:33:02.108222 Write leveling : PASS
5820 11:33:02.111692 RX DQS gating : PASS
5821 11:33:02.115432 RX DQ/DQS(RDDQC) : PASS
5822 11:33:02.115507 TX DQ/DQS : PASS
5823 11:33:02.118087 RX DATLAT : PASS
5824 11:33:02.118163 RX DQ/DQS(Engine): PASS
5825 11:33:02.121874 TX OE : NO K
5826 11:33:02.121949 All Pass.
5827 11:33:02.122008
5828 11:33:02.124445 CH 0, Rank 1
5829 11:33:02.124544 SW Impedance : PASS
5830 11:33:02.127771 DUTY Scan : NO K
5831 11:33:02.131207 ZQ Calibration : PASS
5832 11:33:02.131301 Jitter Meter : NO K
5833 11:33:02.134329 CBT Training : PASS
5834 11:33:02.137599 Write leveling : PASS
5835 11:33:02.137699 RX DQS gating : PASS
5836 11:33:02.141793 RX DQ/DQS(RDDQC) : PASS
5837 11:33:02.144790 TX DQ/DQS : PASS
5838 11:33:02.144889 RX DATLAT : PASS
5839 11:33:02.147632 RX DQ/DQS(Engine): PASS
5840 11:33:02.151537 TX OE : NO K
5841 11:33:02.151638 All Pass.
5842 11:33:02.151726
5843 11:33:02.151806 CH 1, Rank 0
5844 11:33:02.154896 SW Impedance : PASS
5845 11:33:02.157611 DUTY Scan : NO K
5846 11:33:02.157686 ZQ Calibration : PASS
5847 11:33:02.160626 Jitter Meter : NO K
5848 11:33:02.164389 CBT Training : PASS
5849 11:33:02.164463 Write leveling : PASS
5850 11:33:02.167240 RX DQS gating : PASS
5851 11:33:02.170716 RX DQ/DQS(RDDQC) : PASS
5852 11:33:02.170791 TX DQ/DQS : PASS
5853 11:33:02.174169 RX DATLAT : PASS
5854 11:33:02.177829 RX DQ/DQS(Engine): PASS
5855 11:33:02.177929 TX OE : NO K
5856 11:33:02.178016 All Pass.
5857 11:33:02.181188
5858 11:33:02.181301 CH 1, Rank 1
5859 11:33:02.184548 SW Impedance : PASS
5860 11:33:02.184623 DUTY Scan : NO K
5861 11:33:02.187227 ZQ Calibration : PASS
5862 11:33:02.187303 Jitter Meter : NO K
5863 11:33:02.190753 CBT Training : PASS
5864 11:33:02.193875 Write leveling : PASS
5865 11:33:02.193950 RX DQS gating : PASS
5866 11:33:02.197949 RX DQ/DQS(RDDQC) : PASS
5867 11:33:02.200897 TX DQ/DQS : PASS
5868 11:33:02.200972 RX DATLAT : PASS
5869 11:33:02.204737 RX DQ/DQS(Engine): PASS
5870 11:33:02.207253 TX OE : NO K
5871 11:33:02.207338 All Pass.
5872 11:33:02.207396
5873 11:33:02.211315 DramC Write-DBI off
5874 11:33:02.211417 PER_BANK_REFRESH: Hybrid Mode
5875 11:33:02.214310 TX_TRACKING: ON
5876 11:33:02.224122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5877 11:33:02.227004 [FAST_K] Save calibration result to emmc
5878 11:33:02.230929 dramc_set_vcore_voltage set vcore to 650000
5879 11:33:02.231005 Read voltage for 400, 6
5880 11:33:02.233790 Vio18 = 0
5881 11:33:02.233866 Vcore = 650000
5882 11:33:02.233924 Vdram = 0
5883 11:33:02.237408 Vddq = 0
5884 11:33:02.237484 Vmddr = 0
5885 11:33:02.240729 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5886 11:33:02.247558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5887 11:33:02.250241 MEM_TYPE=3, freq_sel=20
5888 11:33:02.253651 sv_algorithm_assistance_LP4_800
5889 11:33:02.257680 ============ PULL DRAM RESETB DOWN ============
5890 11:33:02.260436 ========== PULL DRAM RESETB DOWN end =========
5891 11:33:02.266665 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5892 11:33:02.269834 ===================================
5893 11:33:02.269910 LPDDR4 DRAM CONFIGURATION
5894 11:33:02.274375 ===================================
5895 11:33:02.276773 EX_ROW_EN[0] = 0x0
5896 11:33:02.276848 EX_ROW_EN[1] = 0x0
5897 11:33:02.280013 LP4Y_EN = 0x0
5898 11:33:02.280088 WORK_FSP = 0x0
5899 11:33:02.283297 WL = 0x2
5900 11:33:02.286476 RL = 0x2
5901 11:33:02.286551 BL = 0x2
5902 11:33:02.290530 RPST = 0x0
5903 11:33:02.290606 RD_PRE = 0x0
5904 11:33:02.293383 WR_PRE = 0x1
5905 11:33:02.293457 WR_PST = 0x0
5906 11:33:02.296569 DBI_WR = 0x0
5907 11:33:02.296668 DBI_RD = 0x0
5908 11:33:02.299593 OTF = 0x1
5909 11:33:02.303067 ===================================
5910 11:33:02.306645 ===================================
5911 11:33:02.306720 ANA top config
5912 11:33:02.310573 ===================================
5913 11:33:02.313215 DLL_ASYNC_EN = 0
5914 11:33:02.316803 ALL_SLAVE_EN = 1
5915 11:33:02.316878 NEW_RANK_MODE = 1
5916 11:33:02.319727 DLL_IDLE_MODE = 1
5917 11:33:02.323161 LP45_APHY_COMB_EN = 1
5918 11:33:02.327274 TX_ODT_DIS = 1
5919 11:33:02.329443 NEW_8X_MODE = 1
5920 11:33:02.333161 ===================================
5921 11:33:02.336358 ===================================
5922 11:33:02.336434 data_rate = 800
5923 11:33:02.339529 CKR = 1
5924 11:33:02.343487 DQ_P2S_RATIO = 4
5925 11:33:02.346328 ===================================
5926 11:33:02.349614 CA_P2S_RATIO = 4
5927 11:33:02.352610 DQ_CA_OPEN = 0
5928 11:33:02.355824 DQ_SEMI_OPEN = 1
5929 11:33:02.355900 CA_SEMI_OPEN = 1
5930 11:33:02.359168 CA_FULL_RATE = 0
5931 11:33:02.362536 DQ_CKDIV4_EN = 0
5932 11:33:02.365902 CA_CKDIV4_EN = 1
5933 11:33:02.369195 CA_PREDIV_EN = 0
5934 11:33:02.372565 PH8_DLY = 0
5935 11:33:02.372640 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5936 11:33:02.376311 DQ_AAMCK_DIV = 0
5937 11:33:02.379209 CA_AAMCK_DIV = 0
5938 11:33:02.382512 CA_ADMCK_DIV = 4
5939 11:33:02.385771 DQ_TRACK_CA_EN = 0
5940 11:33:02.389267 CA_PICK = 800
5941 11:33:02.392867 CA_MCKIO = 400
5942 11:33:02.392955 MCKIO_SEMI = 400
5943 11:33:02.395651 PLL_FREQ = 3016
5944 11:33:02.398975 DQ_UI_PI_RATIO = 32
5945 11:33:02.402149 CA_UI_PI_RATIO = 32
5946 11:33:02.405668 ===================================
5947 11:33:02.409149 ===================================
5948 11:33:02.412285 memory_type:LPDDR4
5949 11:33:02.412361 GP_NUM : 10
5950 11:33:02.415875 SRAM_EN : 1
5951 11:33:02.418948 MD32_EN : 0
5952 11:33:02.422452 ===================================
5953 11:33:02.422528 [ANA_INIT] >>>>>>>>>>>>>>
5954 11:33:02.425549 <<<<<< [CONFIGURE PHASE]: ANA_TX
5955 11:33:02.429808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5956 11:33:02.432035 ===================================
5957 11:33:02.435586 data_rate = 800,PCW = 0X7400
5958 11:33:02.438545 ===================================
5959 11:33:02.442073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5960 11:33:02.448600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5961 11:33:02.458379 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5962 11:33:02.465179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5963 11:33:02.468536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5964 11:33:02.473355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5965 11:33:02.473431 [ANA_INIT] flow start
5966 11:33:02.475244 [ANA_INIT] PLL >>>>>>>>
5967 11:33:02.478935 [ANA_INIT] PLL <<<<<<<<
5968 11:33:02.479011 [ANA_INIT] MIDPI >>>>>>>>
5969 11:33:02.482056 [ANA_INIT] MIDPI <<<<<<<<
5970 11:33:02.484781 [ANA_INIT] DLL >>>>>>>>
5971 11:33:02.484856 [ANA_INIT] flow end
5972 11:33:02.491666 ============ LP4 DIFF to SE enter ============
5973 11:33:02.494855 ============ LP4 DIFF to SE exit ============
5974 11:33:02.497909 [ANA_INIT] <<<<<<<<<<<<<
5975 11:33:02.501811 [Flow] Enable top DCM control >>>>>
5976 11:33:02.505461 [Flow] Enable top DCM control <<<<<
5977 11:33:02.505536 Enable DLL master slave shuffle
5978 11:33:02.511638 ==============================================================
5979 11:33:02.514652 Gating Mode config
5980 11:33:02.518682 ==============================================================
5981 11:33:02.521260 Config description:
5982 11:33:02.531491 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5983 11:33:02.537964 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5984 11:33:02.541398 SELPH_MODE 0: By rank 1: By Phase
5985 11:33:02.547904 ==============================================================
5986 11:33:02.551596 GAT_TRACK_EN = 0
5987 11:33:02.554029 RX_GATING_MODE = 2
5988 11:33:02.557503 RX_GATING_TRACK_MODE = 2
5989 11:33:02.560896 SELPH_MODE = 1
5990 11:33:02.564037 PICG_EARLY_EN = 1
5991 11:33:02.567566 VALID_LAT_VALUE = 1
5992 11:33:02.571029 ==============================================================
5993 11:33:02.574460 Enter into Gating configuration >>>>
5994 11:33:02.577283 Exit from Gating configuration <<<<
5995 11:33:02.580922 Enter into DVFS_PRE_config >>>>>
5996 11:33:02.590380 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5997 11:33:02.594307 Exit from DVFS_PRE_config <<<<<
5998 11:33:02.597219 Enter into PICG configuration >>>>
5999 11:33:02.600785 Exit from PICG configuration <<<<
6000 11:33:02.603604 [RX_INPUT] configuration >>>>>
6001 11:33:02.607334 [RX_INPUT] configuration <<<<<
6002 11:33:02.614285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6003 11:33:02.616906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6004 11:33:02.624027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6005 11:33:02.630249 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6006 11:33:02.637202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6007 11:33:02.644315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6008 11:33:02.646969 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6009 11:33:02.650108 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6010 11:33:02.653583 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6011 11:33:02.660223 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6012 11:33:02.663285 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6013 11:33:02.666598 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 11:33:02.669909 ===================================
6015 11:33:02.673694 LPDDR4 DRAM CONFIGURATION
6016 11:33:02.676129 ===================================
6017 11:33:02.679909 EX_ROW_EN[0] = 0x0
6018 11:33:02.679985 EX_ROW_EN[1] = 0x0
6019 11:33:02.683124 LP4Y_EN = 0x0
6020 11:33:02.683199 WORK_FSP = 0x0
6021 11:33:02.686280 WL = 0x2
6022 11:33:02.686354 RL = 0x2
6023 11:33:02.689572 BL = 0x2
6024 11:33:02.689667 RPST = 0x0
6025 11:33:02.693127 RD_PRE = 0x0
6026 11:33:02.693248 WR_PRE = 0x1
6027 11:33:02.696696 WR_PST = 0x0
6028 11:33:02.696771 DBI_WR = 0x0
6029 11:33:02.699761 DBI_RD = 0x0
6030 11:33:02.699835 OTF = 0x1
6031 11:33:02.703130 ===================================
6032 11:33:02.709989 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6033 11:33:02.713464 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6034 11:33:02.716063 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6035 11:33:02.720401 ===================================
6036 11:33:02.722615 LPDDR4 DRAM CONFIGURATION
6037 11:33:02.726278 ===================================
6038 11:33:02.729403 EX_ROW_EN[0] = 0x10
6039 11:33:02.729478 EX_ROW_EN[1] = 0x0
6040 11:33:02.733472 LP4Y_EN = 0x0
6041 11:33:02.733547 WORK_FSP = 0x0
6042 11:33:02.736693 WL = 0x2
6043 11:33:02.736790 RL = 0x2
6044 11:33:02.739063 BL = 0x2
6045 11:33:02.739137 RPST = 0x0
6046 11:33:02.742832 RD_PRE = 0x0
6047 11:33:02.742906 WR_PRE = 0x1
6048 11:33:02.746439 WR_PST = 0x0
6049 11:33:02.746514 DBI_WR = 0x0
6050 11:33:02.749261 DBI_RD = 0x0
6051 11:33:02.749373 OTF = 0x1
6052 11:33:02.753729 ===================================
6053 11:33:02.759207 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6054 11:33:02.764183 nWR fixed to 30
6055 11:33:02.767077 [ModeRegInit_LP4] CH0 RK0
6056 11:33:02.767152 [ModeRegInit_LP4] CH0 RK1
6057 11:33:02.770820 [ModeRegInit_LP4] CH1 RK0
6058 11:33:02.773624 [ModeRegInit_LP4] CH1 RK1
6059 11:33:02.773700 match AC timing 18
6060 11:33:02.780254 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6061 11:33:02.784407 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6062 11:33:02.787009 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6063 11:33:02.793486 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6064 11:33:02.797013 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6065 11:33:02.797089 ==
6066 11:33:02.800677 Dram Type= 6, Freq= 0, CH_0, rank 0
6067 11:33:02.804153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6068 11:33:02.804229 ==
6069 11:33:02.810314 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6070 11:33:02.816855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6071 11:33:02.820707 [CA 0] Center 36 (8~64) winsize 57
6072 11:33:02.823642 [CA 1] Center 36 (8~64) winsize 57
6073 11:33:02.827280 [CA 2] Center 36 (8~64) winsize 57
6074 11:33:02.827350 [CA 3] Center 36 (8~64) winsize 57
6075 11:33:02.830085 [CA 4] Center 36 (8~64) winsize 57
6076 11:33:02.833278 [CA 5] Center 36 (8~64) winsize 57
6077 11:33:02.833365
6078 11:33:02.839945 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6079 11:33:02.840038
6080 11:33:02.843422 [CATrainingPosCal] consider 1 rank data
6081 11:33:02.847603 u2DelayCellTimex100 = 270/100 ps
6082 11:33:02.850577 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 11:33:02.853612 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 11:33:02.856900 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 11:33:02.859891 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 11:33:02.863466 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6087 11:33:02.866481 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6088 11:33:02.866557
6089 11:33:02.869849 CA PerBit enable=1, Macro0, CA PI delay=36
6090 11:33:02.869926
6091 11:33:02.873747 [CBTSetCACLKResult] CA Dly = 36
6092 11:33:02.876874 CS Dly: 1 (0~32)
6093 11:33:02.876948 ==
6094 11:33:02.879895 Dram Type= 6, Freq= 0, CH_0, rank 1
6095 11:33:02.883082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6096 11:33:02.883158 ==
6097 11:33:02.889957 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6098 11:33:02.893775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6099 11:33:02.896580 [CA 0] Center 36 (8~64) winsize 57
6100 11:33:02.899516 [CA 1] Center 36 (8~64) winsize 57
6101 11:33:02.903031 [CA 2] Center 36 (8~64) winsize 57
6102 11:33:02.906374 [CA 3] Center 36 (8~64) winsize 57
6103 11:33:02.909806 [CA 4] Center 36 (8~64) winsize 57
6104 11:33:02.913007 [CA 5] Center 36 (8~64) winsize 57
6105 11:33:02.913080
6106 11:33:02.916903 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6107 11:33:02.916974
6108 11:33:02.919943 [CATrainingPosCal] consider 2 rank data
6109 11:33:02.923926 u2DelayCellTimex100 = 270/100 ps
6110 11:33:02.926494 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6111 11:33:02.929317 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6112 11:33:02.935882 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6113 11:33:02.939902 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6114 11:33:02.942501 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6115 11:33:02.946114 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6116 11:33:02.946180
6117 11:33:02.949584 CA PerBit enable=1, Macro0, CA PI delay=36
6118 11:33:02.949676
6119 11:33:02.952665 [CBTSetCACLKResult] CA Dly = 36
6120 11:33:02.952728 CS Dly: 1 (0~32)
6121 11:33:02.952784
6122 11:33:02.959659 ----->DramcWriteLeveling(PI) begin...
6123 11:33:02.959728 ==
6124 11:33:02.962472 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 11:33:02.965723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 11:33:02.965786 ==
6127 11:33:02.969251 Write leveling (Byte 0): 32 => 0
6128 11:33:02.972746 Write leveling (Byte 1): 32 => 0
6129 11:33:02.976449 DramcWriteLeveling(PI) end<-----
6130 11:33:02.976511
6131 11:33:02.976565 ==
6132 11:33:02.979581 Dram Type= 6, Freq= 0, CH_0, rank 0
6133 11:33:02.982743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6134 11:33:02.982807 ==
6135 11:33:02.985570 [Gating] SW mode calibration
6136 11:33:02.993297 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6137 11:33:02.995860 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6138 11:33:03.003348 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6139 11:33:03.006276 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6140 11:33:03.009094 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6141 11:33:03.015494 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6142 11:33:03.018958 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6143 11:33:03.022336 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6144 11:33:03.029020 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6145 11:33:03.032480 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6146 11:33:03.035964 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6147 11:33:03.038867 Total UI for P1: 0, mck2ui 16
6148 11:33:03.042553 best dqsien dly found for B0: ( 0, 10, 16)
6149 11:33:03.045432 Total UI for P1: 0, mck2ui 16
6150 11:33:03.048823 best dqsien dly found for B1: ( 0, 10, 24)
6151 11:33:03.052570 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6152 11:33:03.055813 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6153 11:33:03.059171
6154 11:33:03.061934 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6155 11:33:03.066138 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6156 11:33:03.068832 [Gating] SW calibration Done
6157 11:33:03.068907 ==
6158 11:33:03.072640 Dram Type= 6, Freq= 0, CH_0, rank 0
6159 11:33:03.076184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6160 11:33:03.076259 ==
6161 11:33:03.078780 RX Vref Scan: 0
6162 11:33:03.078855
6163 11:33:03.078913 RX Vref 0 -> 0, step: 1
6164 11:33:03.078968
6165 11:33:03.082902 RX Delay -410 -> 252, step: 16
6166 11:33:03.085201 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6167 11:33:03.091893 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6168 11:33:03.095415 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6169 11:33:03.098748 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6170 11:33:03.101727 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6171 11:33:03.108154 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6172 11:33:03.111722 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6173 11:33:03.115161 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6174 11:33:03.119160 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6175 11:33:03.125580 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6176 11:33:03.128384 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6177 11:33:03.131763 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6178 11:33:03.138563 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6179 11:33:03.141440 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6180 11:33:03.145324 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6181 11:33:03.148170 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6182 11:33:03.148245 ==
6183 11:33:03.151386 Dram Type= 6, Freq= 0, CH_0, rank 0
6184 11:33:03.158734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6185 11:33:03.158809 ==
6186 11:33:03.158868 DQS Delay:
6187 11:33:03.161550 DQS0 = 43, DQS1 = 59
6188 11:33:03.161624 DQM Delay:
6189 11:33:03.164960 DQM0 = 5, DQM1 = 16
6190 11:33:03.165034 DQ Delay:
6191 11:33:03.167786 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6192 11:33:03.171504 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6193 11:33:03.171579 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6194 11:33:03.178199 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6195 11:33:03.178275
6196 11:33:03.178333
6197 11:33:03.178386 ==
6198 11:33:03.181837 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 11:33:03.185396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6200 11:33:03.185471 ==
6201 11:33:03.185530
6202 11:33:03.185583
6203 11:33:03.188096 TX Vref Scan disable
6204 11:33:03.188170 == TX Byte 0 ==
6205 11:33:03.191100 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6206 11:33:03.197768 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6207 11:33:03.197844 == TX Byte 1 ==
6208 11:33:03.204186 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6209 11:33:03.207921 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6210 11:33:03.207997 ==
6211 11:33:03.211538 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 11:33:03.214755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6213 11:33:03.214840 ==
6214 11:33:03.214926
6215 11:33:03.215006
6216 11:33:03.217570 TX Vref Scan disable
6217 11:33:03.217635 == TX Byte 0 ==
6218 11:33:03.224490 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6219 11:33:03.227904 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6220 11:33:03.227994 == TX Byte 1 ==
6221 11:33:03.234568 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6222 11:33:03.237417 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6223 11:33:03.237485
6224 11:33:03.237540 [DATLAT]
6225 11:33:03.240700 Freq=400, CH0 RK0
6226 11:33:03.240777
6227 11:33:03.240835 DATLAT Default: 0xf
6228 11:33:03.244167 0, 0xFFFF, sum = 0
6229 11:33:03.244247 1, 0xFFFF, sum = 0
6230 11:33:03.247845 2, 0xFFFF, sum = 0
6231 11:33:03.247910 3, 0xFFFF, sum = 0
6232 11:33:03.250439 4, 0xFFFF, sum = 0
6233 11:33:03.254542 5, 0xFFFF, sum = 0
6234 11:33:03.254636 6, 0xFFFF, sum = 0
6235 11:33:03.257112 7, 0xFFFF, sum = 0
6236 11:33:03.257210 8, 0xFFFF, sum = 0
6237 11:33:03.261388 9, 0xFFFF, sum = 0
6238 11:33:03.261462 10, 0xFFFF, sum = 0
6239 11:33:03.264852 11, 0xFFFF, sum = 0
6240 11:33:03.264921 12, 0x0, sum = 1
6241 11:33:03.267549 13, 0x0, sum = 2
6242 11:33:03.267631 14, 0x0, sum = 3
6243 11:33:03.270461 15, 0x0, sum = 4
6244 11:33:03.270529 best_step = 13
6245 11:33:03.270588
6246 11:33:03.270640 ==
6247 11:33:03.274385 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 11:33:03.277152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6249 11:33:03.277263 ==
6250 11:33:03.281030 RX Vref Scan: 1
6251 11:33:03.281116
6252 11:33:03.284656 RX Vref 0 -> 0, step: 1
6253 11:33:03.284742
6254 11:33:03.284820 RX Delay -359 -> 252, step: 8
6255 11:33:03.284896
6256 11:33:03.287345 Set Vref, RX VrefLevel [Byte0]: 51
6257 11:33:03.290389 [Byte1]: 51
6258 11:33:03.296526
6259 11:33:03.296594 Final RX Vref Byte 0 = 51 to rank0
6260 11:33:03.300124 Final RX Vref Byte 1 = 51 to rank0
6261 11:33:03.302875 Final RX Vref Byte 0 = 51 to rank1
6262 11:33:03.305683 Final RX Vref Byte 1 = 51 to rank1==
6263 11:33:03.309134 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 11:33:03.316217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6265 11:33:03.316311 ==
6266 11:33:03.316393 DQS Delay:
6267 11:33:03.319295 DQS0 = 52, DQS1 = 64
6268 11:33:03.319364 DQM Delay:
6269 11:33:03.319421 DQM0 = 8, DQM1 = 13
6270 11:33:03.322731 DQ Delay:
6271 11:33:03.325860 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6272 11:33:03.325920 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6273 11:33:03.329153 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6274 11:33:03.332261 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6275 11:33:03.332325
6276 11:33:03.332376
6277 11:33:03.342542 [DQSOSCAuto] RK0, (LSB)MR18= 0xacac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6278 11:33:03.345798 CH0 RK0: MR19=C0C, MR18=ACAC
6279 11:33:03.352636 CH0_RK0: MR19=0xC0C, MR18=0xACAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6280 11:33:03.352758 ==
6281 11:33:03.355794 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 11:33:03.359214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6283 11:33:03.359345 ==
6284 11:33:03.362053 [Gating] SW mode calibration
6285 11:33:03.369042 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6286 11:33:03.372169 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6287 11:33:03.378930 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 11:33:03.382298 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 11:33:03.386120 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 11:33:03.392244 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6291 11:33:03.395715 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 11:33:03.399310 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 11:33:03.405347 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 11:33:03.408994 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6295 11:33:03.412499 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 11:33:03.415559 Total UI for P1: 0, mck2ui 16
6297 11:33:03.418891 best dqsien dly found for B0: ( 0, 10, 16)
6298 11:33:03.422553 Total UI for P1: 0, mck2ui 16
6299 11:33:03.425408 best dqsien dly found for B1: ( 0, 10, 24)
6300 11:33:03.429095 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6301 11:33:03.432164 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6302 11:33:03.432246
6303 11:33:03.439496 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6304 11:33:03.442058 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6305 11:33:03.445882 [Gating] SW calibration Done
6306 11:33:03.445966 ==
6307 11:33:03.449152 Dram Type= 6, Freq= 0, CH_0, rank 1
6308 11:33:03.452013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6309 11:33:03.452092 ==
6310 11:33:03.452151 RX Vref Scan: 0
6311 11:33:03.452205
6312 11:33:03.455384 RX Vref 0 -> 0, step: 1
6313 11:33:03.455459
6314 11:33:03.458704 RX Delay -410 -> 252, step: 16
6315 11:33:03.461992 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6316 11:33:03.469138 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6317 11:33:03.471943 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6318 11:33:03.475533 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6319 11:33:03.478531 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6320 11:33:03.485653 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6321 11:33:03.488690 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6322 11:33:03.492203 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6323 11:33:03.495561 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6324 11:33:03.501712 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6325 11:33:03.505192 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6326 11:33:03.508999 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6327 11:33:03.511990 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6328 11:33:03.518539 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6329 11:33:03.521840 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6330 11:33:03.524769 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6331 11:33:03.524850 ==
6332 11:33:03.528290 Dram Type= 6, Freq= 0, CH_0, rank 1
6333 11:33:03.535068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6334 11:33:03.535167 ==
6335 11:33:03.535227 DQS Delay:
6336 11:33:03.537997 DQS0 = 43, DQS1 = 59
6337 11:33:03.538074 DQM Delay:
6338 11:33:03.538132 DQM0 = 6, DQM1 = 14
6339 11:33:03.541167 DQ Delay:
6340 11:33:03.544706 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6341 11:33:03.544781 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6342 11:33:03.548056 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6343 11:33:03.551673 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6344 11:33:03.551748
6345 11:33:03.551805
6346 11:33:03.554966 ==
6347 11:33:03.558257 Dram Type= 6, Freq= 0, CH_0, rank 1
6348 11:33:03.561246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6349 11:33:03.561336 ==
6350 11:33:03.561394
6351 11:33:03.561448
6352 11:33:03.565607 TX Vref Scan disable
6353 11:33:03.565682 == TX Byte 0 ==
6354 11:33:03.568705 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6355 11:33:03.575169 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6356 11:33:03.575244 == TX Byte 1 ==
6357 11:33:03.577777 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6358 11:33:03.584193 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6359 11:33:03.584285 ==
6360 11:33:03.587545 Dram Type= 6, Freq= 0, CH_0, rank 1
6361 11:33:03.590873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6362 11:33:03.590965 ==
6363 11:33:03.591037
6364 11:33:03.591105
6365 11:33:03.594225 TX Vref Scan disable
6366 11:33:03.594315 == TX Byte 0 ==
6367 11:33:03.598285 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6368 11:33:03.604286 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6369 11:33:03.604362 == TX Byte 1 ==
6370 11:33:03.607932 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6371 11:33:03.614346 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6372 11:33:03.614424
6373 11:33:03.614489 [DATLAT]
6374 11:33:03.614542 Freq=400, CH0 RK1
6375 11:33:03.614593
6376 11:33:03.617828 DATLAT Default: 0xd
6377 11:33:03.620682 0, 0xFFFF, sum = 0
6378 11:33:03.620758 1, 0xFFFF, sum = 0
6379 11:33:03.623929 2, 0xFFFF, sum = 0
6380 11:33:03.624004 3, 0xFFFF, sum = 0
6381 11:33:03.627820 4, 0xFFFF, sum = 0
6382 11:33:03.627895 5, 0xFFFF, sum = 0
6383 11:33:03.631894 6, 0xFFFF, sum = 0
6384 11:33:03.631970 7, 0xFFFF, sum = 0
6385 11:33:03.633971 8, 0xFFFF, sum = 0
6386 11:33:03.634047 9, 0xFFFF, sum = 0
6387 11:33:03.637270 10, 0xFFFF, sum = 0
6388 11:33:03.637346 11, 0xFFFF, sum = 0
6389 11:33:03.640739 12, 0x0, sum = 1
6390 11:33:03.640814 13, 0x0, sum = 2
6391 11:33:03.643583 14, 0x0, sum = 3
6392 11:33:03.643659 15, 0x0, sum = 4
6393 11:33:03.646763 best_step = 13
6394 11:33:03.646837
6395 11:33:03.646894 ==
6396 11:33:03.650941 Dram Type= 6, Freq= 0, CH_0, rank 1
6397 11:33:03.654613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6398 11:33:03.654708 ==
6399 11:33:03.657016 RX Vref Scan: 0
6400 11:33:03.657090
6401 11:33:03.657147 RX Vref 0 -> 0, step: 1
6402 11:33:03.657200
6403 11:33:03.661612 RX Delay -359 -> 252, step: 8
6404 11:33:03.668385 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6405 11:33:03.671512 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6406 11:33:03.675436 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6407 11:33:03.678059 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6408 11:33:03.685160 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6409 11:33:03.688011 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6410 11:33:03.691415 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6411 11:33:03.695281 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6412 11:33:03.701701 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6413 11:33:03.704876 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6414 11:33:03.708374 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6415 11:33:03.711380 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6416 11:33:03.721101 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6417 11:33:03.721434 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6418 11:33:03.725151 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6419 11:33:03.731494 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6420 11:33:03.731569 ==
6421 11:33:03.734550 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 11:33:03.737668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6423 11:33:03.737757 ==
6424 11:33:03.737813 DQS Delay:
6425 11:33:03.741187 DQS0 = 52, DQS1 = 64
6426 11:33:03.741291 DQM Delay:
6427 11:33:03.744560 DQM0 = 11, DQM1 = 14
6428 11:33:03.744635 DQ Delay:
6429 11:33:03.747906 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6430 11:33:03.750935 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6431 11:33:03.754605 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6432 11:33:03.757762 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6433 11:33:03.757844
6434 11:33:03.757940
6435 11:33:03.764547 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6436 11:33:03.767358 CH0 RK1: MR19=C0C, MR18=C0C0
6437 11:33:03.774331 CH0_RK1: MR19=0xC0C, MR18=0xC0C0, DQSOSC=386, MR23=63, INC=396, DEC=264
6438 11:33:03.777638 [RxdqsGatingPostProcess] freq 400
6439 11:33:03.784135 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6440 11:33:03.784211 Pre-setting of DQS Precalculation
6441 11:33:03.790622 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6442 11:33:03.790698 ==
6443 11:33:03.794288 Dram Type= 6, Freq= 0, CH_1, rank 0
6444 11:33:03.797687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6445 11:33:03.797807 ==
6446 11:33:03.804708 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6447 11:33:03.811064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6448 11:33:03.814697 [CA 0] Center 36 (8~64) winsize 57
6449 11:33:03.818032 [CA 1] Center 36 (8~64) winsize 57
6450 11:33:03.821130 [CA 2] Center 36 (8~64) winsize 57
6451 11:33:03.824207 [CA 3] Center 36 (8~64) winsize 57
6452 11:33:03.824300 [CA 4] Center 36 (8~64) winsize 57
6453 11:33:03.827253 [CA 5] Center 36 (8~64) winsize 57
6454 11:33:03.827341
6455 11:33:03.834385 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6456 11:33:03.834473
6457 11:33:03.837556 [CATrainingPosCal] consider 1 rank data
6458 11:33:03.840808 u2DelayCellTimex100 = 270/100 ps
6459 11:33:03.844745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 11:33:03.847411 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 11:33:03.850432 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 11:33:03.853608 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 11:33:03.857118 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6464 11:33:03.860783 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6465 11:33:03.860856
6466 11:33:03.863455 CA PerBit enable=1, Macro0, CA PI delay=36
6467 11:33:03.863524
6468 11:33:03.867412 [CBTSetCACLKResult] CA Dly = 36
6469 11:33:03.870774 CS Dly: 1 (0~32)
6470 11:33:03.870868 ==
6471 11:33:03.873639 Dram Type= 6, Freq= 0, CH_1, rank 1
6472 11:33:03.876880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6473 11:33:03.876948 ==
6474 11:33:03.883986 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6475 11:33:03.890511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6476 11:33:03.893516 [CA 0] Center 36 (8~64) winsize 57
6477 11:33:03.893591 [CA 1] Center 36 (8~64) winsize 57
6478 11:33:03.897183 [CA 2] Center 36 (8~64) winsize 57
6479 11:33:03.900210 [CA 3] Center 36 (8~64) winsize 57
6480 11:33:03.903313 [CA 4] Center 36 (8~64) winsize 57
6481 11:33:03.907282 [CA 5] Center 36 (8~64) winsize 57
6482 11:33:03.907348
6483 11:33:03.910550 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6484 11:33:03.910614
6485 11:33:03.913111 [CATrainingPosCal] consider 2 rank data
6486 11:33:03.916755 u2DelayCellTimex100 = 270/100 ps
6487 11:33:03.919985 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6488 11:33:03.926767 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6489 11:33:03.929595 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6490 11:33:03.933284 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6491 11:33:03.936360 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6492 11:33:03.939670 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6493 11:33:03.939736
6494 11:33:03.943568 CA PerBit enable=1, Macro0, CA PI delay=36
6495 11:33:03.943633
6496 11:33:03.947029 [CBTSetCACLKResult] CA Dly = 36
6497 11:33:03.950605 CS Dly: 1 (0~32)
6498 11:33:03.950692
6499 11:33:03.953364 ----->DramcWriteLeveling(PI) begin...
6500 11:33:03.953432 ==
6501 11:33:03.956844 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 11:33:03.959534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 11:33:03.959610 ==
6504 11:33:03.962842 Write leveling (Byte 0): 32 => 0
6505 11:33:03.966606 Write leveling (Byte 1): 32 => 0
6506 11:33:03.969649 DramcWriteLeveling(PI) end<-----
6507 11:33:03.969724
6508 11:33:03.969782 ==
6509 11:33:03.973645 Dram Type= 6, Freq= 0, CH_1, rank 0
6510 11:33:03.976512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6511 11:33:03.976587 ==
6512 11:33:03.979722 [Gating] SW mode calibration
6513 11:33:03.986168 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6514 11:33:03.992765 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6515 11:33:03.996104 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6516 11:33:03.999300 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6517 11:33:04.006347 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 11:33:04.010022 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6519 11:33:04.012426 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 11:33:04.019132 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 11:33:04.022824 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 11:33:04.025854 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6523 11:33:04.032464 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6524 11:33:04.032539 Total UI for P1: 0, mck2ui 16
6525 11:33:04.035809 best dqsien dly found for B0: ( 0, 10, 16)
6526 11:33:04.038974 Total UI for P1: 0, mck2ui 16
6527 11:33:04.042198 best dqsien dly found for B1: ( 0, 10, 16)
6528 11:33:04.049188 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6529 11:33:04.052270 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6530 11:33:04.052344
6531 11:33:04.055839 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6532 11:33:04.059072 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6533 11:33:04.062606 [Gating] SW calibration Done
6534 11:33:04.062681 ==
6535 11:33:04.065484 Dram Type= 6, Freq= 0, CH_1, rank 0
6536 11:33:04.070463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6537 11:33:04.070538 ==
6538 11:33:04.072779 RX Vref Scan: 0
6539 11:33:04.072854
6540 11:33:04.072911 RX Vref 0 -> 0, step: 1
6541 11:33:04.072965
6542 11:33:04.075733 RX Delay -410 -> 252, step: 16
6543 11:33:04.082649 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6544 11:33:04.085761 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6545 11:33:04.089519 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6546 11:33:04.092186 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6547 11:33:04.098897 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6548 11:33:04.102167 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6549 11:33:04.106076 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6550 11:33:04.108649 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6551 11:33:04.115600 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6552 11:33:04.118804 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6553 11:33:04.121851 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6554 11:33:04.125877 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6555 11:33:04.132202 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6556 11:33:04.135672 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6557 11:33:04.138491 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6558 11:33:04.142264 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6559 11:33:04.145410 ==
6560 11:33:04.145485 Dram Type= 6, Freq= 0, CH_1, rank 0
6561 11:33:04.151720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6562 11:33:04.151795 ==
6563 11:33:04.151854 DQS Delay:
6564 11:33:04.155086 DQS0 = 43, DQS1 = 59
6565 11:33:04.155161 DQM Delay:
6566 11:33:04.158677 DQM0 = 6, DQM1 = 14
6567 11:33:04.158753 DQ Delay:
6568 11:33:04.162309 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6569 11:33:04.165982 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6570 11:33:04.166057 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6571 11:33:04.171595 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6572 11:33:04.171670
6573 11:33:04.171728
6574 11:33:04.171782 ==
6575 11:33:04.175555 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 11:33:04.179092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6577 11:33:04.179167 ==
6578 11:33:04.179226
6579 11:33:04.179280
6580 11:33:04.181981 TX Vref Scan disable
6581 11:33:04.182056 == TX Byte 0 ==
6582 11:33:04.188545 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6583 11:33:04.191767 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6584 11:33:04.191871 == TX Byte 1 ==
6585 11:33:04.198364 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6586 11:33:04.201919 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6587 11:33:04.201995 ==
6588 11:33:04.205171 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 11:33:04.208354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6590 11:33:04.208436 ==
6591 11:33:04.208499
6592 11:33:04.208552
6593 11:33:04.211738 TX Vref Scan disable
6594 11:33:04.211839 == TX Byte 0 ==
6595 11:33:04.218212 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6596 11:33:04.221762 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6597 11:33:04.221838 == TX Byte 1 ==
6598 11:33:04.228510 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6599 11:33:04.231557 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6600 11:33:04.231635
6601 11:33:04.231693 [DATLAT]
6602 11:33:04.235099 Freq=400, CH1 RK0
6603 11:33:04.235173
6604 11:33:04.235231 DATLAT Default: 0xf
6605 11:33:04.238745 0, 0xFFFF, sum = 0
6606 11:33:04.238820 1, 0xFFFF, sum = 0
6607 11:33:04.241617 2, 0xFFFF, sum = 0
6608 11:33:04.241692 3, 0xFFFF, sum = 0
6609 11:33:04.244833 4, 0xFFFF, sum = 0
6610 11:33:04.244910 5, 0xFFFF, sum = 0
6611 11:33:04.248817 6, 0xFFFF, sum = 0
6612 11:33:04.248893 7, 0xFFFF, sum = 0
6613 11:33:04.251372 8, 0xFFFF, sum = 0
6614 11:33:04.255290 9, 0xFFFF, sum = 0
6615 11:33:04.255366 10, 0xFFFF, sum = 0
6616 11:33:04.258890 11, 0xFFFF, sum = 0
6617 11:33:04.258966 12, 0x0, sum = 1
6618 11:33:04.261624 13, 0x0, sum = 2
6619 11:33:04.261702 14, 0x0, sum = 3
6620 11:33:04.261761 15, 0x0, sum = 4
6621 11:33:04.264636 best_step = 13
6622 11:33:04.264710
6623 11:33:04.264768 ==
6624 11:33:04.268053 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 11:33:04.271840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6626 11:33:04.271916 ==
6627 11:33:04.274387 RX Vref Scan: 1
6628 11:33:04.274460
6629 11:33:04.278592 RX Vref 0 -> 0, step: 1
6630 11:33:04.278667
6631 11:33:04.278725 RX Delay -359 -> 252, step: 8
6632 11:33:04.278780
6633 11:33:04.281366 Set Vref, RX VrefLevel [Byte0]: 52
6634 11:33:04.284493 [Byte1]: 52
6635 11:33:04.290763
6636 11:33:04.290837 Final RX Vref Byte 0 = 52 to rank0
6637 11:33:04.293919 Final RX Vref Byte 1 = 52 to rank0
6638 11:33:04.297246 Final RX Vref Byte 0 = 52 to rank1
6639 11:33:04.300183 Final RX Vref Byte 1 = 52 to rank1==
6640 11:33:04.303333 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 11:33:04.310282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6642 11:33:04.310357 ==
6643 11:33:04.310415 DQS Delay:
6644 11:33:04.313000 DQS0 = 48, DQS1 = 64
6645 11:33:04.313074 DQM Delay:
6646 11:33:04.313131 DQM0 = 8, DQM1 = 15
6647 11:33:04.316427 DQ Delay:
6648 11:33:04.319633 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6649 11:33:04.319707 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6650 11:33:04.323366 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6651 11:33:04.326793 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6652 11:33:04.326868
6653 11:33:04.326925
6654 11:33:04.336177 [DQSOSCAuto] RK0, (LSB)MR18= 0xe1e1, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6655 11:33:04.339999 CH1 RK0: MR19=C0C, MR18=E1E1
6656 11:33:04.346347 CH1_RK0: MR19=0xC0C, MR18=0xE1E1, DQSOSC=382, MR23=63, INC=404, DEC=269
6657 11:33:04.346422 ==
6658 11:33:04.349817 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 11:33:04.352857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6660 11:33:04.352932 ==
6661 11:33:04.356458 [Gating] SW mode calibration
6662 11:33:04.362757 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 11:33:04.369375 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6664 11:33:04.372576 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 11:33:04.376066 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 11:33:04.383231 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 11:33:04.385695 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6668 11:33:04.389721 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 11:33:04.395830 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:33:04.399202 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 11:33:04.402563 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6672 11:33:04.406634 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 11:33:04.410268 Total UI for P1: 0, mck2ui 16
6674 11:33:04.412634 best dqsien dly found for B0: ( 0, 10, 16)
6675 11:33:04.416219 Total UI for P1: 0, mck2ui 16
6676 11:33:04.419067 best dqsien dly found for B1: ( 0, 10, 16)
6677 11:33:04.422380 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6678 11:33:04.428957 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6679 11:33:04.429032
6680 11:33:04.433364 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6681 11:33:04.435975 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6682 11:33:04.439570 [Gating] SW calibration Done
6683 11:33:04.439646 ==
6684 11:33:04.442426 Dram Type= 6, Freq= 0, CH_1, rank 1
6685 11:33:04.446383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6686 11:33:04.446472 ==
6687 11:33:04.449435 RX Vref Scan: 0
6688 11:33:04.449509
6689 11:33:04.449567 RX Vref 0 -> 0, step: 1
6690 11:33:04.449621
6691 11:33:04.453123 RX Delay -410 -> 252, step: 16
6692 11:33:04.456007 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6693 11:33:04.462426 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6694 11:33:04.465569 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6695 11:33:04.469507 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6696 11:33:04.475668 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6697 11:33:04.478829 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6698 11:33:04.482186 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6699 11:33:04.485814 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6700 11:33:04.488413 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6701 11:33:04.494937 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6702 11:33:04.498398 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6703 11:33:04.501871 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6704 11:33:04.508599 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6705 11:33:04.513309 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6706 11:33:04.514866 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6707 11:33:04.518153 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6708 11:33:04.521878 ==
6709 11:33:04.521952 Dram Type= 6, Freq= 0, CH_1, rank 1
6710 11:33:04.528556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6711 11:33:04.528631 ==
6712 11:33:04.528690 DQS Delay:
6713 11:33:04.531628 DQS0 = 35, DQS1 = 59
6714 11:33:04.531703 DQM Delay:
6715 11:33:04.535266 DQM0 = 3, DQM1 = 18
6716 11:33:04.535341 DQ Delay:
6717 11:33:04.538320 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6718 11:33:04.541670 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6719 11:33:04.541746 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6720 11:33:04.548953 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6721 11:33:04.549028
6722 11:33:04.549086
6723 11:33:04.549140 ==
6724 11:33:04.551576 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 11:33:04.554951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6726 11:33:04.555027 ==
6727 11:33:04.555085
6728 11:33:04.555139
6729 11:33:04.559200 TX Vref Scan disable
6730 11:33:04.559275 == TX Byte 0 ==
6731 11:33:04.561377 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6732 11:33:04.568108 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6733 11:33:04.568183 == TX Byte 1 ==
6734 11:33:04.571776 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6735 11:33:04.577824 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6736 11:33:04.577900 ==
6737 11:33:04.581727 Dram Type= 6, Freq= 0, CH_1, rank 1
6738 11:33:04.584554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6739 11:33:04.584629 ==
6740 11:33:04.584687
6741 11:33:04.584740
6742 11:33:04.587846 TX Vref Scan disable
6743 11:33:04.587961 == TX Byte 0 ==
6744 11:33:04.594544 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6745 11:33:04.597846 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6746 11:33:04.597921 == TX Byte 1 ==
6747 11:33:04.604474 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6748 11:33:04.607502 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6749 11:33:04.607577
6750 11:33:04.607636 [DATLAT]
6751 11:33:04.610744 Freq=400, CH1 RK1
6752 11:33:04.610819
6753 11:33:04.610877 DATLAT Default: 0xd
6754 11:33:04.614050 0, 0xFFFF, sum = 0
6755 11:33:04.614127 1, 0xFFFF, sum = 0
6756 11:33:04.617575 2, 0xFFFF, sum = 0
6757 11:33:04.617651 3, 0xFFFF, sum = 0
6758 11:33:04.621159 4, 0xFFFF, sum = 0
6759 11:33:04.621260 5, 0xFFFF, sum = 0
6760 11:33:04.624383 6, 0xFFFF, sum = 0
6761 11:33:04.624459 7, 0xFFFF, sum = 0
6762 11:33:04.627465 8, 0xFFFF, sum = 0
6763 11:33:04.627542 9, 0xFFFF, sum = 0
6764 11:33:04.630629 10, 0xFFFF, sum = 0
6765 11:33:04.634087 11, 0xFFFF, sum = 0
6766 11:33:04.634164 12, 0x0, sum = 1
6767 11:33:04.634225 13, 0x0, sum = 2
6768 11:33:04.637136 14, 0x0, sum = 3
6769 11:33:04.637213 15, 0x0, sum = 4
6770 11:33:04.641074 best_step = 13
6771 11:33:04.641166
6772 11:33:04.641230 ==
6773 11:33:04.644152 Dram Type= 6, Freq= 0, CH_1, rank 1
6774 11:33:04.647313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6775 11:33:04.647389 ==
6776 11:33:04.651255 RX Vref Scan: 0
6777 11:33:04.651330
6778 11:33:04.651389 RX Vref 0 -> 0, step: 1
6779 11:33:04.651470
6780 11:33:04.653763 RX Delay -359 -> 252, step: 8
6781 11:33:04.662069 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6782 11:33:04.665830 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6783 11:33:04.669148 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6784 11:33:04.672907 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6785 11:33:04.678502 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6786 11:33:04.681812 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6787 11:33:04.685548 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6788 11:33:04.688863 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6789 11:33:04.695424 iDelay=217, Bit 8, Center -68 (-319 ~ 184) 504
6790 11:33:04.698666 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6791 11:33:04.702478 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6792 11:33:04.708718 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6793 11:33:04.712209 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6794 11:33:04.715472 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6795 11:33:04.718959 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6796 11:33:04.726037 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6797 11:33:04.726112 ==
6798 11:33:04.728781 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 11:33:04.732178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6800 11:33:04.732254 ==
6801 11:33:04.732312 DQS Delay:
6802 11:33:04.735170 DQS0 = 48, DQS1 = 68
6803 11:33:04.735246 DQM Delay:
6804 11:33:04.738431 DQM0 = 9, DQM1 = 19
6805 11:33:04.738507 DQ Delay:
6806 11:33:04.741759 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6807 11:33:04.745505 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6808 11:33:04.748948 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =12
6809 11:33:04.751825 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6810 11:33:04.751914
6811 11:33:04.751986
6812 11:33:04.758721 [DQSOSCAuto] RK1, (LSB)MR18= 0xacac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6813 11:33:04.761635 CH1 RK1: MR19=C0C, MR18=ACAC
6814 11:33:04.768326 CH1_RK1: MR19=0xC0C, MR18=0xACAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6815 11:33:04.771593 [RxdqsGatingPostProcess] freq 400
6816 11:33:04.778034 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6817 11:33:04.778111 Pre-setting of DQS Precalculation
6818 11:33:04.785661 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6819 11:33:04.791533 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6820 11:33:04.798357 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6821 11:33:04.798433
6822 11:33:04.798491
6823 11:33:04.801522 [Calibration Summary] 800 Mbps
6824 11:33:04.804732 CH 0, Rank 0
6825 11:33:04.804807 SW Impedance : PASS
6826 11:33:04.809021 DUTY Scan : NO K
6827 11:33:04.811900 ZQ Calibration : PASS
6828 11:33:04.811976 Jitter Meter : NO K
6829 11:33:04.814650 CBT Training : PASS
6830 11:33:04.814725 Write leveling : PASS
6831 11:33:04.818039 RX DQS gating : PASS
6832 11:33:04.821154 RX DQ/DQS(RDDQC) : PASS
6833 11:33:04.821238 TX DQ/DQS : PASS
6834 11:33:04.825033 RX DATLAT : PASS
6835 11:33:04.828976 RX DQ/DQS(Engine): PASS
6836 11:33:04.829051 TX OE : NO K
6837 11:33:04.831613 All Pass.
6838 11:33:04.831687
6839 11:33:04.831761 CH 0, Rank 1
6840 11:33:04.834791 SW Impedance : PASS
6841 11:33:04.834866 DUTY Scan : NO K
6842 11:33:04.838378 ZQ Calibration : PASS
6843 11:33:04.841397 Jitter Meter : NO K
6844 11:33:04.841473 CBT Training : PASS
6845 11:33:04.845800 Write leveling : NO K
6846 11:33:04.848387 RX DQS gating : PASS
6847 11:33:04.848462 RX DQ/DQS(RDDQC) : PASS
6848 11:33:04.851623 TX DQ/DQS : PASS
6849 11:33:04.855064 RX DATLAT : PASS
6850 11:33:04.855139 RX DQ/DQS(Engine): PASS
6851 11:33:04.858250 TX OE : NO K
6852 11:33:04.858324 All Pass.
6853 11:33:04.858382
6854 11:33:04.861453 CH 1, Rank 0
6855 11:33:04.861527 SW Impedance : PASS
6856 11:33:04.864575 DUTY Scan : NO K
6857 11:33:04.864650 ZQ Calibration : PASS
6858 11:33:04.868381 Jitter Meter : NO K
6859 11:33:04.871527 CBT Training : PASS
6860 11:33:04.871602 Write leveling : PASS
6861 11:33:04.874604 RX DQS gating : PASS
6862 11:33:04.878144 RX DQ/DQS(RDDQC) : PASS
6863 11:33:04.878219 TX DQ/DQS : PASS
6864 11:33:04.880912 RX DATLAT : PASS
6865 11:33:04.884488 RX DQ/DQS(Engine): PASS
6866 11:33:04.884563 TX OE : NO K
6867 11:33:04.888082 All Pass.
6868 11:33:04.888157
6869 11:33:04.888214 CH 1, Rank 1
6870 11:33:04.890806 SW Impedance : PASS
6871 11:33:04.890882 DUTY Scan : NO K
6872 11:33:04.894451 ZQ Calibration : PASS
6873 11:33:04.897738 Jitter Meter : NO K
6874 11:33:04.897813 CBT Training : PASS
6875 11:33:04.901254 Write leveling : NO K
6876 11:33:04.904172 RX DQS gating : PASS
6877 11:33:04.904247 RX DQ/DQS(RDDQC) : PASS
6878 11:33:04.907573 TX DQ/DQS : PASS
6879 11:33:04.911295 RX DATLAT : PASS
6880 11:33:04.911370 RX DQ/DQS(Engine): PASS
6881 11:33:04.914457 TX OE : NO K
6882 11:33:04.914533 All Pass.
6883 11:33:04.914635
6884 11:33:04.917780 DramC Write-DBI off
6885 11:33:04.920757 PER_BANK_REFRESH: Hybrid Mode
6886 11:33:04.920833 TX_TRACKING: ON
6887 11:33:04.931888 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6888 11:33:04.933965 [FAST_K] Save calibration result to emmc
6889 11:33:04.937829 dramc_set_vcore_voltage set vcore to 725000
6890 11:33:04.940905 Read voltage for 1600, 0
6891 11:33:04.940980 Vio18 = 0
6892 11:33:04.941039 Vcore = 725000
6893 11:33:04.944207 Vdram = 0
6894 11:33:04.944282 Vddq = 0
6895 11:33:04.944341 Vmddr = 0
6896 11:33:04.950521 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6897 11:33:04.953800 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6898 11:33:04.957256 MEM_TYPE=3, freq_sel=13
6899 11:33:04.960480 sv_algorithm_assistance_LP4_3733
6900 11:33:04.964101 ============ PULL DRAM RESETB DOWN ============
6901 11:33:04.967366 ========== PULL DRAM RESETB DOWN end =========
6902 11:33:04.974924 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6903 11:33:04.977327 ===================================
6904 11:33:04.977403 LPDDR4 DRAM CONFIGURATION
6905 11:33:04.980614 ===================================
6906 11:33:04.983943 EX_ROW_EN[0] = 0x0
6907 11:33:04.987282 EX_ROW_EN[1] = 0x0
6908 11:33:04.987357 LP4Y_EN = 0x0
6909 11:33:04.990706 WORK_FSP = 0x1
6910 11:33:04.990781 WL = 0x5
6911 11:33:04.993822 RL = 0x5
6912 11:33:04.993898 BL = 0x2
6913 11:33:04.996968 RPST = 0x0
6914 11:33:04.997042 RD_PRE = 0x0
6915 11:33:05.001134 WR_PRE = 0x1
6916 11:33:05.001208 WR_PST = 0x1
6917 11:33:05.003986 DBI_WR = 0x0
6918 11:33:05.004060 DBI_RD = 0x0
6919 11:33:05.007929 OTF = 0x1
6920 11:33:05.010709 ===================================
6921 11:33:05.013718 ===================================
6922 11:33:05.013793 ANA top config
6923 11:33:05.017569 ===================================
6924 11:33:05.020286 DLL_ASYNC_EN = 0
6925 11:33:05.023864 ALL_SLAVE_EN = 0
6926 11:33:05.027305 NEW_RANK_MODE = 1
6927 11:33:05.027381 DLL_IDLE_MODE = 1
6928 11:33:05.030609 LP45_APHY_COMB_EN = 1
6929 11:33:05.033478 TX_ODT_DIS = 0
6930 11:33:05.036928 NEW_8X_MODE = 1
6931 11:33:05.040546 ===================================
6932 11:33:05.044036 ===================================
6933 11:33:05.047485 data_rate = 3200
6934 11:33:05.047560 CKR = 1
6935 11:33:05.050716 DQ_P2S_RATIO = 8
6936 11:33:05.053471 ===================================
6937 11:33:05.057051 CA_P2S_RATIO = 8
6938 11:33:05.060708 DQ_CA_OPEN = 0
6939 11:33:05.063487 DQ_SEMI_OPEN = 0
6940 11:33:05.067401 CA_SEMI_OPEN = 0
6941 11:33:05.067476 CA_FULL_RATE = 0
6942 11:33:05.070439 DQ_CKDIV4_EN = 0
6943 11:33:05.073833 CA_CKDIV4_EN = 0
6944 11:33:05.077411 CA_PREDIV_EN = 0
6945 11:33:05.080225 PH8_DLY = 12
6946 11:33:05.083288 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6947 11:33:05.083366 DQ_AAMCK_DIV = 4
6948 11:33:05.086515 CA_AAMCK_DIV = 4
6949 11:33:05.090125 CA_ADMCK_DIV = 4
6950 11:33:05.093371 DQ_TRACK_CA_EN = 0
6951 11:33:05.096954 CA_PICK = 1600
6952 11:33:05.100141 CA_MCKIO = 1600
6953 11:33:05.103311 MCKIO_SEMI = 0
6954 11:33:05.103386 PLL_FREQ = 3068
6955 11:33:05.106485 DQ_UI_PI_RATIO = 32
6956 11:33:05.110099 CA_UI_PI_RATIO = 0
6957 11:33:05.113066 ===================================
6958 11:33:05.116672 ===================================
6959 11:33:05.120298 memory_type:LPDDR4
6960 11:33:05.122997 GP_NUM : 10
6961 11:33:05.123135 SRAM_EN : 1
6962 11:33:05.126930 MD32_EN : 0
6963 11:33:05.129804 ===================================
6964 11:33:05.129879 [ANA_INIT] >>>>>>>>>>>>>>
6965 11:33:05.133369 <<<<<< [CONFIGURE PHASE]: ANA_TX
6966 11:33:05.136456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6967 11:33:05.139753 ===================================
6968 11:33:05.142589 data_rate = 3200,PCW = 0X7600
6969 11:33:05.146069 ===================================
6970 11:33:05.149442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6971 11:33:05.155968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6972 11:33:05.162437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6973 11:33:05.166107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6974 11:33:05.169792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6975 11:33:05.172679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6976 11:33:05.176323 [ANA_INIT] flow start
6977 11:33:05.176398 [ANA_INIT] PLL >>>>>>>>
6978 11:33:05.178876 [ANA_INIT] PLL <<<<<<<<
6979 11:33:05.182606 [ANA_INIT] MIDPI >>>>>>>>
6980 11:33:05.182681 [ANA_INIT] MIDPI <<<<<<<<
6981 11:33:05.186015 [ANA_INIT] DLL >>>>>>>>
6982 11:33:05.189732 [ANA_INIT] DLL <<<<<<<<
6983 11:33:05.189807 [ANA_INIT] flow end
6984 11:33:05.195844 ============ LP4 DIFF to SE enter ============
6985 11:33:05.199016 ============ LP4 DIFF to SE exit ============
6986 11:33:05.202207 [ANA_INIT] <<<<<<<<<<<<<
6987 11:33:05.206181 [Flow] Enable top DCM control >>>>>
6988 11:33:05.208957 [Flow] Enable top DCM control <<<<<
6989 11:33:05.209067 Enable DLL master slave shuffle
6990 11:33:05.215455 ==============================================================
6991 11:33:05.219012 Gating Mode config
6992 11:33:05.222512 ==============================================================
6993 11:33:05.225941 Config description:
6994 11:33:05.235996 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6995 11:33:05.242096 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6996 11:33:05.245385 SELPH_MODE 0: By rank 1: By Phase
6997 11:33:05.251678 ==============================================================
6998 11:33:05.254846 GAT_TRACK_EN = 1
6999 11:33:05.258669 RX_GATING_MODE = 2
7000 11:33:05.261493 RX_GATING_TRACK_MODE = 2
7001 11:33:05.265437 SELPH_MODE = 1
7002 11:33:05.268191 PICG_EARLY_EN = 1
7003 11:33:05.271852 VALID_LAT_VALUE = 1
7004 11:33:05.275438 ==============================================================
7005 11:33:05.278381 Enter into Gating configuration >>>>
7006 11:33:05.281315 Exit from Gating configuration <<<<
7007 11:33:05.285180 Enter into DVFS_PRE_config >>>>>
7008 11:33:05.297998 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7009 11:33:05.298078 Exit from DVFS_PRE_config <<<<<
7010 11:33:05.301108 Enter into PICG configuration >>>>
7011 11:33:05.304622 Exit from PICG configuration <<<<
7012 11:33:05.307946 [RX_INPUT] configuration >>>>>
7013 11:33:05.311325 [RX_INPUT] configuration <<<<<
7014 11:33:05.318066 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7015 11:33:05.320941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7016 11:33:05.327711 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7017 11:33:05.334762 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7018 11:33:05.340817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7019 11:33:05.347477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7020 11:33:05.350998 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7021 11:33:05.354287 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7022 11:33:05.357544 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7023 11:33:05.363662 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7024 11:33:05.367255 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7025 11:33:05.371209 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7026 11:33:05.374154 ===================================
7027 11:33:05.377095 LPDDR4 DRAM CONFIGURATION
7028 11:33:05.380690 ===================================
7029 11:33:05.384504 EX_ROW_EN[0] = 0x0
7030 11:33:05.384582 EX_ROW_EN[1] = 0x0
7031 11:33:05.387820 LP4Y_EN = 0x0
7032 11:33:05.387897 WORK_FSP = 0x1
7033 11:33:05.390372 WL = 0x5
7034 11:33:05.390450 RL = 0x5
7035 11:33:05.393732 BL = 0x2
7036 11:33:05.393812 RPST = 0x0
7037 11:33:05.397484 RD_PRE = 0x0
7038 11:33:05.397560 WR_PRE = 0x1
7039 11:33:05.399999 WR_PST = 0x1
7040 11:33:05.400076 DBI_WR = 0x0
7041 11:33:05.403383 DBI_RD = 0x0
7042 11:33:05.403460 OTF = 0x1
7043 11:33:05.406674 ===================================
7044 11:33:05.414096 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7045 11:33:05.417259 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7046 11:33:05.420955 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7047 11:33:05.423455 ===================================
7048 11:33:05.426800 LPDDR4 DRAM CONFIGURATION
7049 11:33:05.430083 ===================================
7050 11:33:05.433430 EX_ROW_EN[0] = 0x10
7051 11:33:05.433506 EX_ROW_EN[1] = 0x0
7052 11:33:05.437282 LP4Y_EN = 0x0
7053 11:33:05.437357 WORK_FSP = 0x1
7054 11:33:05.439619 WL = 0x5
7055 11:33:05.439694 RL = 0x5
7056 11:33:05.443578 BL = 0x2
7057 11:33:05.443653 RPST = 0x0
7058 11:33:05.446804 RD_PRE = 0x0
7059 11:33:05.446879 WR_PRE = 0x1
7060 11:33:05.449618 WR_PST = 0x1
7061 11:33:05.449692 DBI_WR = 0x0
7062 11:33:05.453091 DBI_RD = 0x0
7063 11:33:05.453166 OTF = 0x1
7064 11:33:05.456349 ===================================
7065 11:33:05.463814 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7066 11:33:05.463891 ==
7067 11:33:05.466336 Dram Type= 6, Freq= 0, CH_0, rank 0
7068 11:33:05.473475 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7069 11:33:05.473554 ==
7070 11:33:05.473613 [Duty_Offset_Calibration]
7071 11:33:05.477155 B0:0 B1:2 CA:1
7072 11:33:05.477236
7073 11:33:05.479763 [DutyScan_Calibration_Flow] k_type=0
7074 11:33:05.489165
7075 11:33:05.489278 ==CLK 0==
7076 11:33:05.492344 Final CLK duty delay cell = 0
7077 11:33:05.495392 [0] MAX Duty = 5156%(X100), DQS PI = 22
7078 11:33:05.499001 [0] MIN Duty = 4938%(X100), DQS PI = 50
7079 11:33:05.499077 [0] AVG Duty = 5047%(X100)
7080 11:33:05.502653
7081 11:33:05.505466 CH0 CLK Duty spec in!! Max-Min= 218%
7082 11:33:05.508648 [DutyScan_Calibration_Flow] ====Done====
7083 11:33:05.508780
7084 11:33:05.512277 [DutyScan_Calibration_Flow] k_type=1
7085 11:33:05.529073
7086 11:33:05.529149 ==DQS 0 ==
7087 11:33:05.532567 Final DQS duty delay cell = 0
7088 11:33:05.536158 [0] MAX Duty = 5156%(X100), DQS PI = 34
7089 11:33:05.538953 [0] MIN Duty = 5000%(X100), DQS PI = 8
7090 11:33:05.542889 [0] AVG Duty = 5078%(X100)
7091 11:33:05.542963
7092 11:33:05.543021 ==DQS 1 ==
7093 11:33:05.545713 Final DQS duty delay cell = 0
7094 11:33:05.548615 [0] MAX Duty = 5031%(X100), DQS PI = 6
7095 11:33:05.552047 [0] MIN Duty = 4876%(X100), DQS PI = 16
7096 11:33:05.555409 [0] AVG Duty = 4953%(X100)
7097 11:33:05.555484
7098 11:33:05.558878 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7099 11:33:05.558953
7100 11:33:05.561886 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7101 11:33:05.565434 [DutyScan_Calibration_Flow] ====Done====
7102 11:33:05.565509
7103 11:33:05.568488 [DutyScan_Calibration_Flow] k_type=3
7104 11:33:05.587104
7105 11:33:05.587184 ==DQM 0 ==
7106 11:33:05.589601 Final DQM duty delay cell = 0
7107 11:33:05.592469 [0] MAX Duty = 5187%(X100), DQS PI = 22
7108 11:33:05.596436 [0] MIN Duty = 4907%(X100), DQS PI = 42
7109 11:33:05.599557 [0] AVG Duty = 5047%(X100)
7110 11:33:05.599631
7111 11:33:05.599689 ==DQM 1 ==
7112 11:33:05.603328 Final DQM duty delay cell = 0
7113 11:33:05.606128 [0] MAX Duty = 5031%(X100), DQS PI = 50
7114 11:33:05.609787 [0] MIN Duty = 4782%(X100), DQS PI = 14
7115 11:33:05.612654 [0] AVG Duty = 4906%(X100)
7116 11:33:05.612728
7117 11:33:05.616156 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7118 11:33:05.616230
7119 11:33:05.619399 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7120 11:33:05.623380 [DutyScan_Calibration_Flow] ====Done====
7121 11:33:05.623455
7122 11:33:05.626542 [DutyScan_Calibration_Flow] k_type=2
7123 11:33:05.643488
7124 11:33:05.643563 ==DQ 0 ==
7125 11:33:05.645499 Final DQ duty delay cell = 0
7126 11:33:05.649264 [0] MAX Duty = 5218%(X100), DQS PI = 18
7127 11:33:05.652685 [0] MIN Duty = 4969%(X100), DQS PI = 46
7128 11:33:05.652761 [0] AVG Duty = 5093%(X100)
7129 11:33:05.655520
7130 11:33:05.655594 ==DQ 1 ==
7131 11:33:05.659309 Final DQ duty delay cell = -4
7132 11:33:05.662542 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7133 11:33:05.665392 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7134 11:33:05.669407 [-4] AVG Duty = 4953%(X100)
7135 11:33:05.669482
7136 11:33:05.672243 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7137 11:33:05.672318
7138 11:33:05.676370 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7139 11:33:05.679349 [DutyScan_Calibration_Flow] ====Done====
7140 11:33:05.679425 ==
7141 11:33:05.682245 Dram Type= 6, Freq= 0, CH_1, rank 0
7142 11:33:05.685387 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7143 11:33:05.685462 ==
7144 11:33:05.689190 [Duty_Offset_Calibration]
7145 11:33:05.689313 B0:0 B1:4 CA:-5
7146 11:33:05.689372
7147 11:33:05.691857 [DutyScan_Calibration_Flow] k_type=0
7148 11:33:05.703152
7149 11:33:05.703227 ==CLK 0==
7150 11:33:05.706541 Final CLK duty delay cell = 0
7151 11:33:05.709920 [0] MAX Duty = 5156%(X100), DQS PI = 16
7152 11:33:05.713002 [0] MIN Duty = 4875%(X100), DQS PI = 52
7153 11:33:05.713077 [0] AVG Duty = 5015%(X100)
7154 11:33:05.716613
7155 11:33:05.720479 CH1 CLK Duty spec in!! Max-Min= 281%
7156 11:33:05.723051 [DutyScan_Calibration_Flow] ====Done====
7157 11:33:05.723126
7158 11:33:05.726338 [DutyScan_Calibration_Flow] k_type=1
7159 11:33:05.742086
7160 11:33:05.742161 ==DQS 0 ==
7161 11:33:05.745879 Final DQS duty delay cell = 0
7162 11:33:05.748614 [0] MAX Duty = 5187%(X100), DQS PI = 20
7163 11:33:05.752754 [0] MIN Duty = 4876%(X100), DQS PI = 42
7164 11:33:05.755042 [0] AVG Duty = 5031%(X100)
7165 11:33:05.755116
7166 11:33:05.755200 ==DQS 1 ==
7167 11:33:05.759116 Final DQS duty delay cell = -4
7168 11:33:05.762579 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7169 11:33:05.766091 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7170 11:33:05.768627 [-4] AVG Duty = 4922%(X100)
7171 11:33:05.768702
7172 11:33:05.771841 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7173 11:33:05.771917
7174 11:33:05.774999 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7175 11:33:05.778289 [DutyScan_Calibration_Flow] ====Done====
7176 11:33:05.778364
7177 11:33:05.781687 [DutyScan_Calibration_Flow] k_type=3
7178 11:33:05.798216
7179 11:33:05.798292 ==DQM 0 ==
7180 11:33:05.800710 Final DQM duty delay cell = -4
7181 11:33:05.804364 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7182 11:33:05.807797 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7183 11:33:05.810858 [-4] AVG Duty = 4937%(X100)
7184 11:33:05.810934
7185 11:33:05.810992 ==DQM 1 ==
7186 11:33:05.814362 Final DQM duty delay cell = -4
7187 11:33:05.817271 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7188 11:33:05.820646 [-4] MIN Duty = 4876%(X100), DQS PI = 38
7189 11:33:05.824246 [-4] AVG Duty = 4969%(X100)
7190 11:33:05.824321
7191 11:33:05.827817 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7192 11:33:05.827892
7193 11:33:05.831271 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7194 11:33:05.833879 [DutyScan_Calibration_Flow] ====Done====
7195 11:33:05.833954
7196 11:33:05.837973 [DutyScan_Calibration_Flow] k_type=2
7197 11:33:05.855876
7198 11:33:05.855952 ==DQ 0 ==
7199 11:33:05.858639 Final DQ duty delay cell = 0
7200 11:33:05.862338 [0] MAX Duty = 5093%(X100), DQS PI = 36
7201 11:33:05.864842 [0] MIN Duty = 4969%(X100), DQS PI = 46
7202 11:33:05.864938 [0] AVG Duty = 5031%(X100)
7203 11:33:05.868407
7204 11:33:05.868485 ==DQ 1 ==
7205 11:33:05.872497 Final DQ duty delay cell = 0
7206 11:33:05.875213 [0] MAX Duty = 5031%(X100), DQS PI = 4
7207 11:33:05.878774 [0] MIN Duty = 4876%(X100), DQS PI = 28
7208 11:33:05.878838 [0] AVG Duty = 4953%(X100)
7209 11:33:05.881666
7210 11:33:05.881753 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7211 11:33:05.885027
7212 11:33:05.888650 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7213 11:33:05.891883 [DutyScan_Calibration_Flow] ====Done====
7214 11:33:05.895702 nWR fixed to 30
7215 11:33:05.895799 [ModeRegInit_LP4] CH0 RK0
7216 11:33:05.898233 [ModeRegInit_LP4] CH0 RK1
7217 11:33:05.901495 [ModeRegInit_LP4] CH1 RK0
7218 11:33:05.901558 [ModeRegInit_LP4] CH1 RK1
7219 11:33:05.905101 match AC timing 4
7220 11:33:05.908294 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7221 11:33:05.915110 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7222 11:33:05.918403 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7223 11:33:05.924871 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7224 11:33:05.928180 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7225 11:33:05.928269 [MiockJmeterHQA]
7226 11:33:05.928356
7227 11:33:05.931479 [DramcMiockJmeter] u1RxGatingPI = 0
7228 11:33:05.934499 0 : 4252, 4027
7229 11:33:05.934596 4 : 4363, 4137
7230 11:33:05.937956 8 : 4252, 4027
7231 11:33:05.938053 12 : 4252, 4027
7232 11:33:05.938137 16 : 4255, 4029
7233 11:33:05.941142 20 : 4253, 4026
7234 11:33:05.941220 24 : 4363, 4138
7235 11:33:05.944820 28 : 4252, 4027
7236 11:33:05.944896 32 : 4363, 4137
7237 11:33:05.947613 36 : 4253, 4027
7238 11:33:05.947690 40 : 4253, 4026
7239 11:33:05.951507 44 : 4252, 4027
7240 11:33:05.951583 48 : 4255, 4029
7241 11:33:05.951643 52 : 4363, 4138
7242 11:33:05.954367 56 : 4250, 4027
7243 11:33:05.954443 60 : 4361, 4137
7244 11:33:05.957754 64 : 4250, 4027
7245 11:33:05.957837 68 : 4250, 4027
7246 11:33:05.961524 72 : 4250, 4027
7247 11:33:05.961601 76 : 4361, 4138
7248 11:33:05.964626 80 : 4250, 4027
7249 11:33:05.964703 84 : 4360, 4137
7250 11:33:05.964763 88 : 4249, 4027
7251 11:33:05.967697 92 : 4250, 4027
7252 11:33:05.967773 96 : 4250, 4027
7253 11:33:05.971370 100 : 4253, 1784
7254 11:33:05.971447 104 : 4252, 0
7255 11:33:05.974601 108 : 4250, 0
7256 11:33:05.974678 112 : 4250, 0
7257 11:33:05.974737 116 : 4250, 0
7258 11:33:05.977689 120 : 4252, 0
7259 11:33:05.977766 124 : 4361, 0
7260 11:33:05.977825 128 : 4250, 0
7261 11:33:05.981176 132 : 4250, 0
7262 11:33:05.981289 136 : 4252, 0
7263 11:33:05.984043 140 : 4361, 0
7264 11:33:05.984119 144 : 4250, 0
7265 11:33:05.984178 148 : 4250, 0
7266 11:33:05.987671 152 : 4250, 0
7267 11:33:05.987747 156 : 4250, 0
7268 11:33:05.990917 160 : 4363, 0
7269 11:33:05.990994 164 : 4250, 0
7270 11:33:05.991052 168 : 4250, 0
7271 11:33:05.994477 172 : 4250, 0
7272 11:33:05.994553 176 : 4360, 0
7273 11:33:05.998274 180 : 4250, 0
7274 11:33:05.998350 184 : 4250, 0
7275 11:33:05.998409 188 : 4250, 0
7276 11:33:06.001074 192 : 4361, 0
7277 11:33:06.001149 196 : 4360, 0
7278 11:33:06.004181 200 : 4251, 0
7279 11:33:06.004257 204 : 4250, 0
7280 11:33:06.004315 208 : 4250, 0
7281 11:33:06.007752 212 : 4252, 0
7282 11:33:06.007844 216 : 4250, 0
7283 11:33:06.010521 220 : 4250, 329
7284 11:33:06.010597 224 : 4361, 4058
7285 11:33:06.010657 228 : 4250, 4027
7286 11:33:06.014121 232 : 4360, 4137
7287 11:33:06.014198 236 : 4250, 4026
7288 11:33:06.017504 240 : 4250, 4027
7289 11:33:06.017581 244 : 4251, 4027
7290 11:33:06.021348 248 : 4252, 4029
7291 11:33:06.021423 252 : 4250, 4027
7292 11:33:06.024061 256 : 4250, 4027
7293 11:33:06.024136 260 : 4249, 4027
7294 11:33:06.027908 264 : 4249, 4027
7295 11:33:06.027984 268 : 4250, 4027
7296 11:33:06.030405 272 : 4360, 4138
7297 11:33:06.030480 276 : 4250, 4027
7298 11:33:06.033644 280 : 4250, 4027
7299 11:33:06.033720 284 : 4360, 4137
7300 11:33:06.037659 288 : 4361, 4138
7301 11:33:06.037736 292 : 4250, 4027
7302 11:33:06.037798 296 : 4251, 4027
7303 11:33:06.040430 300 : 4252, 4029
7304 11:33:06.040506 304 : 4250, 4027
7305 11:33:06.043805 308 : 4250, 4027
7306 11:33:06.043881 312 : 4250, 4027
7307 11:33:06.047696 316 : 4252, 4029
7308 11:33:06.047772 320 : 4250, 4027
7309 11:33:06.050674 324 : 4360, 4138
7310 11:33:06.050750 328 : 4360, 4138
7311 11:33:06.053845 332 : 4250, 4027
7312 11:33:06.053921 336 : 4363, 3936
7313 11:33:06.056822 340 : 4360, 1793
7314 11:33:06.056898
7315 11:33:06.056956 MIOCK jitter meter ch=0
7316 11:33:06.057010
7317 11:33:06.063674 1T = (340-100) = 240 dly cells
7318 11:33:06.067114 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7319 11:33:06.067193 ==
7320 11:33:06.069976 Dram Type= 6, Freq= 0, CH_0, rank 0
7321 11:33:06.073512 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7322 11:33:06.073587 ==
7323 11:33:06.080049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7324 11:33:06.083234 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7325 11:33:06.089842 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7326 11:33:06.093459 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7327 11:33:06.102533 [CA 0] Center 41 (11~72) winsize 62
7328 11:33:06.105399 [CA 1] Center 41 (11~72) winsize 62
7329 11:33:06.109022 [CA 2] Center 37 (7~67) winsize 61
7330 11:33:06.112139 [CA 3] Center 37 (7~67) winsize 61
7331 11:33:06.115424 [CA 4] Center 35 (5~66) winsize 62
7332 11:33:06.119072 [CA 5] Center 35 (5~65) winsize 61
7333 11:33:06.119148
7334 11:33:06.122677 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7335 11:33:06.122752
7336 11:33:06.125969 [CATrainingPosCal] consider 1 rank data
7337 11:33:06.129205 u2DelayCellTimex100 = 271/100 ps
7338 11:33:06.132976 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7339 11:33:06.139443 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7340 11:33:06.142171 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7341 11:33:06.145576 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7342 11:33:06.149071 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7343 11:33:06.152136 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7344 11:33:06.152212
7345 11:33:06.156060 CA PerBit enable=1, Macro0, CA PI delay=35
7346 11:33:06.156135
7347 11:33:06.158830 [CBTSetCACLKResult] CA Dly = 35
7348 11:33:06.161946 CS Dly: 11 (0~42)
7349 11:33:06.166090 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7350 11:33:06.168635 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7351 11:33:06.168710 ==
7352 11:33:06.172428 Dram Type= 6, Freq= 0, CH_0, rank 1
7353 11:33:06.176649 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7354 11:33:06.179096 ==
7355 11:33:06.182427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7356 11:33:06.185580 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7357 11:33:06.191838 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7358 11:33:06.195466 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7359 11:33:06.204861 [CA 0] Center 42 (12~73) winsize 62
7360 11:33:06.208238 [CA 1] Center 41 (11~72) winsize 62
7361 11:33:06.211526 [CA 2] Center 38 (8~68) winsize 61
7362 11:33:06.215295 [CA 3] Center 37 (7~67) winsize 61
7363 11:33:06.218408 [CA 4] Center 35 (5~65) winsize 61
7364 11:33:06.221817 [CA 5] Center 35 (5~66) winsize 62
7365 11:33:06.221892
7366 11:33:06.225047 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7367 11:33:06.225122
7368 11:33:06.228448 [CATrainingPosCal] consider 2 rank data
7369 11:33:06.232100 u2DelayCellTimex100 = 271/100 ps
7370 11:33:06.235128 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7371 11:33:06.241666 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7372 11:33:06.244851 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7373 11:33:06.248212 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7374 11:33:06.252218 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7375 11:33:06.254746 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7376 11:33:06.254820
7377 11:33:06.258954 CA PerBit enable=1, Macro0, CA PI delay=35
7378 11:33:06.259027
7379 11:33:06.261712 [CBTSetCACLKResult] CA Dly = 35
7380 11:33:06.264620 CS Dly: 11 (0~43)
7381 11:33:06.268353 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7382 11:33:06.271593 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7383 11:33:06.271666
7384 11:33:06.275246 ----->DramcWriteLeveling(PI) begin...
7385 11:33:06.275321 ==
7386 11:33:06.277823 Dram Type= 6, Freq= 0, CH_0, rank 0
7387 11:33:06.281982 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7388 11:33:06.284464 ==
7389 11:33:06.284537 Write leveling (Byte 0): 30 => 30
7390 11:33:06.288375 Write leveling (Byte 1): 28 => 28
7391 11:33:06.291168 DramcWriteLeveling(PI) end<-----
7392 11:33:06.291266
7393 11:33:06.291325 ==
7394 11:33:06.295305 Dram Type= 6, Freq= 0, CH_0, rank 0
7395 11:33:06.301755 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7396 11:33:06.301829 ==
7397 11:33:06.304544 [Gating] SW mode calibration
7398 11:33:06.311316 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7399 11:33:06.314594 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7400 11:33:06.320942 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 11:33:06.324573 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7402 11:33:06.328209 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7403 11:33:06.334319 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7404 11:33:06.337759 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7405 11:33:06.341272 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7406 11:33:06.347306 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7407 11:33:06.350511 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7408 11:33:06.353941 0 13 0 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7409 11:33:06.361097 0 13 4 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
7410 11:33:06.363831 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7411 11:33:06.367341 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7412 11:33:06.374416 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7413 11:33:06.377562 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7414 11:33:06.381214 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7415 11:33:06.386982 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7416 11:33:06.390413 0 14 0 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
7417 11:33:06.393841 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7418 11:33:06.400069 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7419 11:33:06.403398 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7420 11:33:06.407097 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7421 11:33:06.429921 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7422 11:33:06.430002 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7423 11:33:06.430062 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7424 11:33:06.430116 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7425 11:33:06.430348 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7426 11:33:06.433281 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7427 11:33:06.436487 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7428 11:33:06.443749 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7429 11:33:06.446608 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7430 11:33:06.449937 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7431 11:33:06.456648 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7432 11:33:06.460939 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7433 11:33:06.463340 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7434 11:33:06.470196 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7435 11:33:06.473205 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7436 11:33:06.476291 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7437 11:33:06.482822 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7438 11:33:06.486050 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7439 11:33:06.489458 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7440 11:33:06.496642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7441 11:33:06.499395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7442 11:33:06.502908 Total UI for P1: 0, mck2ui 16
7443 11:33:06.506270 best dqsien dly found for B0: ( 1, 1, 0)
7444 11:33:06.509159 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7445 11:33:06.515729 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7446 11:33:06.519706 Total UI for P1: 0, mck2ui 16
7447 11:33:06.523173 best dqsien dly found for B1: ( 1, 1, 6)
7448 11:33:06.526577 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7449 11:33:06.529492 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7450 11:33:06.529568
7451 11:33:06.532941 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7452 11:33:06.535619 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7453 11:33:06.539366 [Gating] SW calibration Done
7454 11:33:06.539458 ==
7455 11:33:06.543233 Dram Type= 6, Freq= 0, CH_0, rank 0
7456 11:33:06.546228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7457 11:33:06.546322 ==
7458 11:33:06.548851 RX Vref Scan: 0
7459 11:33:06.548943
7460 11:33:06.549034 RX Vref 0 -> 0, step: 1
7461 11:33:06.549089
7462 11:33:06.552255 RX Delay 0 -> 252, step: 8
7463 11:33:06.556073 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7464 11:33:06.562800 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7465 11:33:06.566108 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7466 11:33:06.569363 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7467 11:33:06.572207 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7468 11:33:06.575850 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7469 11:33:06.582254 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7470 11:33:06.586822 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7471 11:33:06.590416 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7472 11:33:06.592283 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7473 11:33:06.595228 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7474 11:33:06.602152 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7475 11:33:06.605323 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7476 11:33:06.608389 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7477 11:33:06.612834 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7478 11:33:06.618334 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7479 11:33:06.618410 ==
7480 11:33:06.622234 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 11:33:06.625374 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 11:33:06.625453 ==
7483 11:33:06.625521 DQS Delay:
7484 11:33:06.629528 DQS0 = 0, DQS1 = 0
7485 11:33:06.629606 DQM Delay:
7486 11:33:06.631567 DQM0 = 130, DQM1 = 124
7487 11:33:06.631656 DQ Delay:
7488 11:33:06.635730 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7489 11:33:06.639002 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7490 11:33:06.642282 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7491 11:33:06.645003 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7492 11:33:06.645095
7493 11:33:06.645177
7494 11:33:06.648461 ==
7495 11:33:06.652102 Dram Type= 6, Freq= 0, CH_0, rank 0
7496 11:33:06.655381 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7497 11:33:06.655469 ==
7498 11:33:06.655549
7499 11:33:06.655677
7500 11:33:06.658203 TX Vref Scan disable
7501 11:33:06.658294 == TX Byte 0 ==
7502 11:33:06.665417 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7503 11:33:06.668140 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7504 11:33:06.668285 == TX Byte 1 ==
7505 11:33:06.675005 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7506 11:33:06.678032 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7507 11:33:06.678140 ==
7508 11:33:06.681517 Dram Type= 6, Freq= 0, CH_0, rank 0
7509 11:33:06.684522 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7510 11:33:06.684635 ==
7511 11:33:06.698185
7512 11:33:06.701424 TX Vref early break, caculate TX vref
7513 11:33:06.704389 TX Vref=16, minBit 8, minWin=22, winSum=376
7514 11:33:06.708019 TX Vref=18, minBit 8, minWin=22, winSum=381
7515 11:33:06.711164 TX Vref=20, minBit 9, minWin=23, winSum=397
7516 11:33:06.714798 TX Vref=22, minBit 7, minWin=24, winSum=402
7517 11:33:06.718200 TX Vref=24, minBit 8, minWin=24, winSum=410
7518 11:33:06.725149 TX Vref=26, minBit 9, minWin=25, winSum=418
7519 11:33:06.727637 TX Vref=28, minBit 1, minWin=25, winSum=418
7520 11:33:06.730843 TX Vref=30, minBit 0, minWin=25, winSum=412
7521 11:33:06.734337 TX Vref=32, minBit 1, minWin=24, winSum=404
7522 11:33:06.737594 TX Vref=34, minBit 1, minWin=24, winSum=394
7523 11:33:06.743772 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 26
7524 11:33:06.743852
7525 11:33:06.747400 Final TX Range 0 Vref 26
7526 11:33:06.747476
7527 11:33:06.747534 ==
7528 11:33:06.751104 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 11:33:06.753882 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7530 11:33:06.753958 ==
7531 11:33:06.754017
7532 11:33:06.754070
7533 11:33:06.757106 TX Vref Scan disable
7534 11:33:06.764219 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7535 11:33:06.764318 == TX Byte 0 ==
7536 11:33:06.767063 u2DelayCellOfst[0]=14 cells (4 PI)
7537 11:33:06.771117 u2DelayCellOfst[1]=14 cells (4 PI)
7538 11:33:06.773754 u2DelayCellOfst[2]=14 cells (4 PI)
7539 11:33:06.777216 u2DelayCellOfst[3]=10 cells (3 PI)
7540 11:33:06.779982 u2DelayCellOfst[4]=7 cells (2 PI)
7541 11:33:06.783592 u2DelayCellOfst[5]=0 cells (0 PI)
7542 11:33:06.786627 u2DelayCellOfst[6]=18 cells (5 PI)
7543 11:33:06.790220 u2DelayCellOfst[7]=18 cells (5 PI)
7544 11:33:06.793158 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7545 11:33:06.797147 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7546 11:33:06.799844 == TX Byte 1 ==
7547 11:33:06.803894 u2DelayCellOfst[8]=3 cells (1 PI)
7548 11:33:06.807217 u2DelayCellOfst[9]=0 cells (0 PI)
7549 11:33:06.807292 u2DelayCellOfst[10]=10 cells (3 PI)
7550 11:33:06.810258 u2DelayCellOfst[11]=7 cells (2 PI)
7551 11:33:06.813353 u2DelayCellOfst[12]=18 cells (5 PI)
7552 11:33:06.816290 u2DelayCellOfst[13]=18 cells (5 PI)
7553 11:33:06.820725 u2DelayCellOfst[14]=21 cells (6 PI)
7554 11:33:06.823174 u2DelayCellOfst[15]=18 cells (5 PI)
7555 11:33:06.830020 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7556 11:33:06.833119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7557 11:33:06.833218 DramC Write-DBI on
7558 11:33:06.833318 ==
7559 11:33:06.836325 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 11:33:06.843491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7561 11:33:06.843567 ==
7562 11:33:06.843626
7563 11:33:06.843680
7564 11:33:06.843731 TX Vref Scan disable
7565 11:33:06.847551 == TX Byte 0 ==
7566 11:33:06.850540 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7567 11:33:06.854568 == TX Byte 1 ==
7568 11:33:06.857084 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7569 11:33:06.860515 DramC Write-DBI off
7570 11:33:06.860591
7571 11:33:06.860649 [DATLAT]
7572 11:33:06.860702 Freq=1600, CH0 RK0
7573 11:33:06.860754
7574 11:33:06.863961 DATLAT Default: 0xf
7575 11:33:06.864036 0, 0xFFFF, sum = 0
7576 11:33:06.867272 1, 0xFFFF, sum = 0
7577 11:33:06.870327 2, 0xFFFF, sum = 0
7578 11:33:06.870406 3, 0xFFFF, sum = 0
7579 11:33:06.874280 4, 0xFFFF, sum = 0
7580 11:33:06.874356 5, 0xFFFF, sum = 0
7581 11:33:06.877253 6, 0xFFFF, sum = 0
7582 11:33:06.877330 7, 0xFFFF, sum = 0
7583 11:33:06.880637 8, 0xFFFF, sum = 0
7584 11:33:06.880713 9, 0xFFFF, sum = 0
7585 11:33:06.884446 10, 0xFFFF, sum = 0
7586 11:33:06.884522 11, 0xFFFF, sum = 0
7587 11:33:06.887105 12, 0x9FF, sum = 0
7588 11:33:06.887181 13, 0x0, sum = 1
7589 11:33:06.890492 14, 0x0, sum = 2
7590 11:33:06.890568 15, 0x0, sum = 3
7591 11:33:06.893648 16, 0x0, sum = 4
7592 11:33:06.893724 best_step = 14
7593 11:33:06.893783
7594 11:33:06.893837 ==
7595 11:33:06.897777 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 11:33:06.899998 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7597 11:33:06.903760 ==
7598 11:33:06.903836 RX Vref Scan: 1
7599 11:33:06.903894
7600 11:33:06.907036 Set Vref Range= 24 -> 127
7601 11:33:06.907112
7602 11:33:06.909851 RX Vref 24 -> 127, step: 1
7603 11:33:06.909925
7604 11:33:06.909984 RX Delay 11 -> 252, step: 4
7605 11:33:06.910039
7606 11:33:06.913407 Set Vref, RX VrefLevel [Byte0]: 24
7607 11:33:06.917408 [Byte1]: 24
7608 11:33:06.920693
7609 11:33:06.920767 Set Vref, RX VrefLevel [Byte0]: 25
7610 11:33:06.923887 [Byte1]: 25
7611 11:33:06.928358
7612 11:33:06.928432 Set Vref, RX VrefLevel [Byte0]: 26
7613 11:33:06.931469 [Byte1]: 26
7614 11:33:06.935724
7615 11:33:06.935798 Set Vref, RX VrefLevel [Byte0]: 27
7616 11:33:06.938794 [Byte1]: 27
7617 11:33:06.943250
7618 11:33:06.943325 Set Vref, RX VrefLevel [Byte0]: 28
7619 11:33:06.946964 [Byte1]: 28
7620 11:33:06.951986
7621 11:33:06.952060 Set Vref, RX VrefLevel [Byte0]: 29
7622 11:33:06.954450 [Byte1]: 29
7623 11:33:06.958997
7624 11:33:06.959072 Set Vref, RX VrefLevel [Byte0]: 30
7625 11:33:06.962028 [Byte1]: 30
7626 11:33:06.965951
7627 11:33:06.966025 Set Vref, RX VrefLevel [Byte0]: 31
7628 11:33:06.969847 [Byte1]: 31
7629 11:33:06.973558
7630 11:33:06.973634 Set Vref, RX VrefLevel [Byte0]: 32
7631 11:33:06.976892 [Byte1]: 32
7632 11:33:06.981945
7633 11:33:06.982021 Set Vref, RX VrefLevel [Byte0]: 33
7634 11:33:06.985022 [Byte1]: 33
7635 11:33:06.989400
7636 11:33:06.989475 Set Vref, RX VrefLevel [Byte0]: 34
7637 11:33:06.992383 [Byte1]: 34
7638 11:33:06.996703
7639 11:33:06.996779 Set Vref, RX VrefLevel [Byte0]: 35
7640 11:33:07.000258 [Byte1]: 35
7641 11:33:07.004260
7642 11:33:07.004336 Set Vref, RX VrefLevel [Byte0]: 36
7643 11:33:07.007359 [Byte1]: 36
7644 11:33:07.012014
7645 11:33:07.012113 Set Vref, RX VrefLevel [Byte0]: 37
7646 11:33:07.015289 [Byte1]: 37
7647 11:33:07.019684
7648 11:33:07.019759 Set Vref, RX VrefLevel [Byte0]: 38
7649 11:33:07.023187 [Byte1]: 38
7650 11:33:07.027506
7651 11:33:07.027581 Set Vref, RX VrefLevel [Byte0]: 39
7652 11:33:07.030614 [Byte1]: 39
7653 11:33:07.035043
7654 11:33:07.035119 Set Vref, RX VrefLevel [Byte0]: 40
7655 11:33:07.038101 [Byte1]: 40
7656 11:33:07.042502
7657 11:33:07.042577 Set Vref, RX VrefLevel [Byte0]: 41
7658 11:33:07.045407 [Byte1]: 41
7659 11:33:07.050925
7660 11:33:07.051000 Set Vref, RX VrefLevel [Byte0]: 42
7661 11:33:07.053206 [Byte1]: 42
7662 11:33:07.057275
7663 11:33:07.057351 Set Vref, RX VrefLevel [Byte0]: 43
7664 11:33:07.060894 [Byte1]: 43
7665 11:33:07.064999
7666 11:33:07.065074 Set Vref, RX VrefLevel [Byte0]: 44
7667 11:33:07.068920 [Byte1]: 44
7668 11:33:07.072898
7669 11:33:07.072973 Set Vref, RX VrefLevel [Byte0]: 45
7670 11:33:07.075884 [Byte1]: 45
7671 11:33:07.080450
7672 11:33:07.080526 Set Vref, RX VrefLevel [Byte0]: 46
7673 11:33:07.083522 [Byte1]: 46
7674 11:33:07.088248
7675 11:33:07.088322 Set Vref, RX VrefLevel [Byte0]: 47
7676 11:33:07.091730 [Byte1]: 47
7677 11:33:07.095867
7678 11:33:07.095942 Set Vref, RX VrefLevel [Byte0]: 48
7679 11:33:07.098986 [Byte1]: 48
7680 11:33:07.103763
7681 11:33:07.103837 Set Vref, RX VrefLevel [Byte0]: 49
7682 11:33:07.107470 [Byte1]: 49
7683 11:33:07.111038
7684 11:33:07.111112 Set Vref, RX VrefLevel [Byte0]: 50
7685 11:33:07.114101 [Byte1]: 50
7686 11:33:07.118811
7687 11:33:07.118885 Set Vref, RX VrefLevel [Byte0]: 51
7688 11:33:07.121655 [Byte1]: 51
7689 11:33:07.126230
7690 11:33:07.126325 Set Vref, RX VrefLevel [Byte0]: 52
7691 11:33:07.130201 [Byte1]: 52
7692 11:33:07.133873
7693 11:33:07.133947 Set Vref, RX VrefLevel [Byte0]: 53
7694 11:33:07.137170 [Byte1]: 53
7695 11:33:07.141129
7696 11:33:07.141203 Set Vref, RX VrefLevel [Byte0]: 54
7697 11:33:07.144541 [Byte1]: 54
7698 11:33:07.149524
7699 11:33:07.149598 Set Vref, RX VrefLevel [Byte0]: 55
7700 11:33:07.152240 [Byte1]: 55
7701 11:33:07.156753
7702 11:33:07.156827 Set Vref, RX VrefLevel [Byte0]: 56
7703 11:33:07.159857 [Byte1]: 56
7704 11:33:07.164277
7705 11:33:07.164352 Set Vref, RX VrefLevel [Byte0]: 57
7706 11:33:07.167533 [Byte1]: 57
7707 11:33:07.171992
7708 11:33:07.172066 Set Vref, RX VrefLevel [Byte0]: 58
7709 11:33:07.175357 [Byte1]: 58
7710 11:33:07.179129
7711 11:33:07.179204 Set Vref, RX VrefLevel [Byte0]: 59
7712 11:33:07.182455 [Byte1]: 59
7713 11:33:07.186658
7714 11:33:07.186732 Set Vref, RX VrefLevel [Byte0]: 60
7715 11:33:07.190164 [Byte1]: 60
7716 11:33:07.195156
7717 11:33:07.195230 Set Vref, RX VrefLevel [Byte0]: 61
7718 11:33:07.198787 [Byte1]: 61
7719 11:33:07.202794
7720 11:33:07.202869 Set Vref, RX VrefLevel [Byte0]: 62
7721 11:33:07.205937 [Byte1]: 62
7722 11:33:07.210173
7723 11:33:07.210247 Set Vref, RX VrefLevel [Byte0]: 63
7724 11:33:07.212766 [Byte1]: 63
7725 11:33:07.217739
7726 11:33:07.217814 Set Vref, RX VrefLevel [Byte0]: 64
7727 11:33:07.220567 [Byte1]: 64
7728 11:33:07.224842
7729 11:33:07.224920 Set Vref, RX VrefLevel [Byte0]: 65
7730 11:33:07.228210 [Byte1]: 65
7731 11:33:07.232702
7732 11:33:07.232777 Set Vref, RX VrefLevel [Byte0]: 66
7733 11:33:07.235925 [Byte1]: 66
7734 11:33:07.240254
7735 11:33:07.240328 Set Vref, RX VrefLevel [Byte0]: 67
7736 11:33:07.243262 [Byte1]: 67
7737 11:33:07.248000
7738 11:33:07.248074 Set Vref, RX VrefLevel [Byte0]: 68
7739 11:33:07.251051 [Byte1]: 68
7740 11:33:07.255956
7741 11:33:07.256031 Set Vref, RX VrefLevel [Byte0]: 69
7742 11:33:07.259191 [Byte1]: 69
7743 11:33:07.263719
7744 11:33:07.263794 Set Vref, RX VrefLevel [Byte0]: 70
7745 11:33:07.266861 [Byte1]: 70
7746 11:33:07.270871
7747 11:33:07.270949 Set Vref, RX VrefLevel [Byte0]: 71
7748 11:33:07.274277 [Byte1]: 71
7749 11:33:07.278530
7750 11:33:07.278604 Set Vref, RX VrefLevel [Byte0]: 72
7751 11:33:07.281888 [Byte1]: 72
7752 11:33:07.285931
7753 11:33:07.286006 Set Vref, RX VrefLevel [Byte0]: 73
7754 11:33:07.289009 [Byte1]: 73
7755 11:33:07.293499
7756 11:33:07.293574 Set Vref, RX VrefLevel [Byte0]: 74
7757 11:33:07.296574 [Byte1]: 74
7758 11:33:07.300825
7759 11:33:07.300900 Final RX Vref Byte 0 = 52 to rank0
7760 11:33:07.304231 Final RX Vref Byte 1 = 55 to rank0
7761 11:33:07.308836 Final RX Vref Byte 0 = 52 to rank1
7762 11:33:07.311951 Final RX Vref Byte 1 = 55 to rank1==
7763 11:33:07.314567 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 11:33:07.320886 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7765 11:33:07.320961 ==
7766 11:33:07.321020 DQS Delay:
7767 11:33:07.321073 DQS0 = 0, DQS1 = 0
7768 11:33:07.324139 DQM Delay:
7769 11:33:07.324214 DQM0 = 126, DQM1 = 121
7770 11:33:07.328283 DQ Delay:
7771 11:33:07.330841 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7772 11:33:07.334779 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7773 11:33:07.337891 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7774 11:33:07.341483 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7775 11:33:07.341558
7776 11:33:07.341617
7777 11:33:07.341670
7778 11:33:07.344286 [DramC_TX_OE_Calibration] TA2
7779 11:33:07.347286 Original DQ_B0 (3 6) =30, OEN = 27
7780 11:33:07.351835 Original DQ_B1 (3 6) =30, OEN = 27
7781 11:33:07.354045 24, 0x0, End_B0=24 End_B1=24
7782 11:33:07.354122 25, 0x0, End_B0=25 End_B1=25
7783 11:33:07.357300 26, 0x0, End_B0=26 End_B1=26
7784 11:33:07.360637 27, 0x0, End_B0=27 End_B1=27
7785 11:33:07.364163 28, 0x0, End_B0=28 End_B1=28
7786 11:33:07.367326 29, 0x0, End_B0=29 End_B1=29
7787 11:33:07.367402 30, 0x0, End_B0=30 End_B1=30
7788 11:33:07.370255 31, 0x4141, End_B0=30 End_B1=30
7789 11:33:07.374419 Byte0 end_step=30 best_step=27
7790 11:33:07.377145 Byte1 end_step=30 best_step=27
7791 11:33:07.380272 Byte0 TX OE(2T, 0.5T) = (3, 3)
7792 11:33:07.383610 Byte1 TX OE(2T, 0.5T) = (3, 3)
7793 11:33:07.383685
7794 11:33:07.383743
7795 11:33:07.390663 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7796 11:33:07.393407 CH0 RK0: MR19=303, MR18=1E1E
7797 11:33:07.400374 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7798 11:33:07.400450
7799 11:33:07.403493 ----->DramcWriteLeveling(PI) begin...
7800 11:33:07.403569 ==
7801 11:33:07.406870 Dram Type= 6, Freq= 0, CH_0, rank 1
7802 11:33:07.410244 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7803 11:33:07.410320 ==
7804 11:33:07.413972 Write leveling (Byte 0): 30 => 30
7805 11:33:07.417273 Write leveling (Byte 1): 27 => 27
7806 11:33:07.420312 DramcWriteLeveling(PI) end<-----
7807 11:33:07.420387
7808 11:33:07.420445 ==
7809 11:33:07.423706 Dram Type= 6, Freq= 0, CH_0, rank 1
7810 11:33:07.426910 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7811 11:33:07.426986 ==
7812 11:33:07.430105 [Gating] SW mode calibration
7813 11:33:07.436919 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7814 11:33:07.443503 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7815 11:33:07.446922 0 12 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7816 11:33:07.453208 0 12 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7817 11:33:07.457344 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7818 11:33:07.459918 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7819 11:33:07.466515 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7820 11:33:07.470156 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7821 11:33:07.473197 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7822 11:33:07.480207 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7823 11:33:07.483908 0 13 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
7824 11:33:07.486946 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7825 11:33:07.493852 0 13 8 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
7826 11:33:07.496681 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7827 11:33:07.499687 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7828 11:33:07.506693 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7829 11:33:07.510072 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7830 11:33:07.512770 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7831 11:33:07.516690 0 14 0 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7832 11:33:07.523466 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7833 11:33:07.526481 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7834 11:33:07.530065 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7835 11:33:07.536015 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7836 11:33:07.539368 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7837 11:33:07.542567 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7838 11:33:07.549164 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7839 11:33:07.553119 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7840 11:33:07.556057 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7841 11:33:07.562972 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7842 11:33:07.565874 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7843 11:33:07.569082 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7844 11:33:07.576015 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7845 11:33:07.579026 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7846 11:33:07.582735 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7847 11:33:07.589054 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7848 11:33:07.592415 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7849 11:33:07.595844 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7850 11:33:07.602913 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7851 11:33:07.606083 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7852 11:33:07.609075 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7853 11:33:07.617106 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7854 11:33:07.619196 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7855 11:33:07.622570 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7856 11:33:07.630129 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7857 11:33:07.632248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7858 11:33:07.636102 Total UI for P1: 0, mck2ui 16
7859 11:33:07.639196 best dqsien dly found for B0: ( 1, 1, 0)
7860 11:33:07.642438 Total UI for P1: 0, mck2ui 16
7861 11:33:07.645204 best dqsien dly found for B1: ( 1, 1, 2)
7862 11:33:07.648941 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7863 11:33:07.652179 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7864 11:33:07.652254
7865 11:33:07.655630 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7866 11:33:07.658445 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7867 11:33:07.662235 [Gating] SW calibration Done
7868 11:33:07.662310 ==
7869 11:33:07.665067 Dram Type= 6, Freq= 0, CH_0, rank 1
7870 11:33:07.669290 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7871 11:33:07.669365 ==
7872 11:33:07.671726 RX Vref Scan: 0
7873 11:33:07.671800
7874 11:33:07.675125 RX Vref 0 -> 0, step: 1
7875 11:33:07.675201
7876 11:33:07.675259 RX Delay 0 -> 252, step: 8
7877 11:33:07.681604 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7878 11:33:07.684878 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7879 11:33:07.688204 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7880 11:33:07.692483 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7881 11:33:07.694839 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7882 11:33:07.701711 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7883 11:33:07.704972 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7884 11:33:07.708340 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7885 11:33:07.711520 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7886 11:33:07.715188 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7887 11:33:07.721195 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7888 11:33:07.724786 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7889 11:33:07.728093 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7890 11:33:07.732211 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7891 11:33:07.738440 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7892 11:33:07.741348 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7893 11:33:07.741483 ==
7894 11:33:07.744475 Dram Type= 6, Freq= 0, CH_0, rank 1
7895 11:33:07.748191 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7896 11:33:07.748266 ==
7897 11:33:07.748324 DQS Delay:
7898 11:33:07.751643 DQS0 = 0, DQS1 = 0
7899 11:33:07.751718 DQM Delay:
7900 11:33:07.754497 DQM0 = 130, DQM1 = 123
7901 11:33:07.754571 DQ Delay:
7902 11:33:07.758027 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7903 11:33:07.761989 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7904 11:33:07.764500 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7905 11:33:07.771444 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7906 11:33:07.771519
7907 11:33:07.771576
7908 11:33:07.771629 ==
7909 11:33:07.774744 Dram Type= 6, Freq= 0, CH_0, rank 1
7910 11:33:07.777946 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7911 11:33:07.778045 ==
7912 11:33:07.778130
7913 11:33:07.778209
7914 11:33:07.781007 TX Vref Scan disable
7915 11:33:07.781105 == TX Byte 0 ==
7916 11:33:07.787937 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7917 11:33:07.791421 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7918 11:33:07.791496 == TX Byte 1 ==
7919 11:33:07.798107 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7920 11:33:07.801118 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7921 11:33:07.801193 ==
7922 11:33:07.804659 Dram Type= 6, Freq= 0, CH_0, rank 1
7923 11:33:07.807432 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7924 11:33:07.807507 ==
7925 11:33:07.822620
7926 11:33:07.825855 TX Vref early break, caculate TX vref
7927 11:33:07.829176 TX Vref=16, minBit 1, minWin=22, winSum=373
7928 11:33:07.832662 TX Vref=18, minBit 1, minWin=23, winSum=384
7929 11:33:07.835790 TX Vref=20, minBit 1, minWin=22, winSum=387
7930 11:33:07.839319 TX Vref=22, minBit 8, minWin=23, winSum=398
7931 11:33:07.842754 TX Vref=24, minBit 7, minWin=24, winSum=406
7932 11:33:07.848950 TX Vref=26, minBit 3, minWin=25, winSum=412
7933 11:33:07.852349 TX Vref=28, minBit 8, minWin=24, winSum=414
7934 11:33:07.855997 TX Vref=30, minBit 8, minWin=24, winSum=413
7935 11:33:07.858909 TX Vref=32, minBit 0, minWin=24, winSum=400
7936 11:33:07.862296 TX Vref=34, minBit 1, minWin=23, winSum=394
7937 11:33:07.865493 TX Vref=36, minBit 8, minWin=23, winSum=392
7938 11:33:07.871747 [TxChooseVref] Worse bit 3, Min win 25, Win sum 412, Final Vref 26
7939 11:33:07.871822
7940 11:33:07.875197 Final TX Range 0 Vref 26
7941 11:33:07.875273
7942 11:33:07.875331 ==
7943 11:33:07.879211 Dram Type= 6, Freq= 0, CH_0, rank 1
7944 11:33:07.881839 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7945 11:33:07.881914 ==
7946 11:33:07.881971
7947 11:33:07.885196
7948 11:33:07.885309 TX Vref Scan disable
7949 11:33:07.892067 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7950 11:33:07.892143 == TX Byte 0 ==
7951 11:33:07.895626 u2DelayCellOfst[0]=10 cells (3 PI)
7952 11:33:07.899078 u2DelayCellOfst[1]=14 cells (4 PI)
7953 11:33:07.902035 u2DelayCellOfst[2]=7 cells (2 PI)
7954 11:33:07.905343 u2DelayCellOfst[3]=7 cells (2 PI)
7955 11:33:07.908543 u2DelayCellOfst[4]=3 cells (1 PI)
7956 11:33:07.911791 u2DelayCellOfst[5]=0 cells (0 PI)
7957 11:33:07.915261 u2DelayCellOfst[6]=18 cells (5 PI)
7958 11:33:07.918345 u2DelayCellOfst[7]=14 cells (4 PI)
7959 11:33:07.922559 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7960 11:33:07.925705 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7961 11:33:07.928316 == TX Byte 1 ==
7962 11:33:07.931994 u2DelayCellOfst[8]=3 cells (1 PI)
7963 11:33:07.934878 u2DelayCellOfst[9]=0 cells (0 PI)
7964 11:33:07.934952 u2DelayCellOfst[10]=10 cells (3 PI)
7965 11:33:07.938361 u2DelayCellOfst[11]=7 cells (2 PI)
7966 11:33:07.941846 u2DelayCellOfst[12]=14 cells (4 PI)
7967 11:33:07.944949 u2DelayCellOfst[13]=14 cells (4 PI)
7968 11:33:07.948705 u2DelayCellOfst[14]=18 cells (5 PI)
7969 11:33:07.951714 u2DelayCellOfst[15]=14 cells (4 PI)
7970 11:33:07.958499 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7971 11:33:07.962489 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7972 11:33:07.962564 DramC Write-DBI on
7973 11:33:07.962622 ==
7974 11:33:07.965167 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 11:33:07.971469 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7976 11:33:07.971544 ==
7977 11:33:07.971602
7978 11:33:07.971656
7979 11:33:07.971707 TX Vref Scan disable
7980 11:33:07.976353 == TX Byte 0 ==
7981 11:33:07.978867 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7982 11:33:07.982939 == TX Byte 1 ==
7983 11:33:07.985834 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7984 11:33:07.988871 DramC Write-DBI off
7985 11:33:07.988945
7986 11:33:07.989003 [DATLAT]
7987 11:33:07.989056 Freq=1600, CH0 RK1
7988 11:33:07.989107
7989 11:33:07.992463 DATLAT Default: 0xe
7990 11:33:07.992537 0, 0xFFFF, sum = 0
7991 11:33:07.995949 1, 0xFFFF, sum = 0
7992 11:33:07.998738 2, 0xFFFF, sum = 0
7993 11:33:07.998813 3, 0xFFFF, sum = 0
7994 11:33:08.002453 4, 0xFFFF, sum = 0
7995 11:33:08.002529 5, 0xFFFF, sum = 0
7996 11:33:08.006506 6, 0xFFFF, sum = 0
7997 11:33:08.006582 7, 0xFFFF, sum = 0
7998 11:33:08.009121 8, 0xFFFF, sum = 0
7999 11:33:08.009197 9, 0xFFFF, sum = 0
8000 11:33:08.011792 10, 0xFFFF, sum = 0
8001 11:33:08.011867 11, 0xFFFF, sum = 0
8002 11:33:08.015659 12, 0x8FFF, sum = 0
8003 11:33:08.015737 13, 0x0, sum = 1
8004 11:33:08.018852 14, 0x0, sum = 2
8005 11:33:08.018928 15, 0x0, sum = 3
8006 11:33:08.022004 16, 0x0, sum = 4
8007 11:33:08.022080 best_step = 14
8008 11:33:08.022137
8009 11:33:08.022191 ==
8010 11:33:08.025352 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 11:33:08.028475 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8012 11:33:08.032704 ==
8013 11:33:08.032778 RX Vref Scan: 0
8014 11:33:08.032836
8015 11:33:08.035270 RX Vref 0 -> 0, step: 1
8016 11:33:08.035344
8017 11:33:08.038611 RX Delay 11 -> 252, step: 4
8018 11:33:08.041672 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8019 11:33:08.044816 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8020 11:33:08.048557 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8021 11:33:08.054857 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8022 11:33:08.059449 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8023 11:33:08.061727 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
8024 11:33:08.064907 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8025 11:33:08.068044 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8026 11:33:08.074881 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8027 11:33:08.077976 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8028 11:33:08.081493 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8029 11:33:08.084679 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8030 11:33:08.088262 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8031 11:33:08.094771 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8032 11:33:08.098069 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8033 11:33:08.101427 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8034 11:33:08.101502 ==
8035 11:33:08.105278 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 11:33:08.108819 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8037 11:33:08.112675 ==
8038 11:33:08.112749 DQS Delay:
8039 11:33:08.112808 DQS0 = 0, DQS1 = 0
8040 11:33:08.114731 DQM Delay:
8041 11:33:08.114805 DQM0 = 129, DQM1 = 120
8042 11:33:08.118899 DQ Delay:
8043 11:33:08.121168 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
8044 11:33:08.124600 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138
8045 11:33:08.128641 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8046 11:33:08.131700 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8047 11:33:08.131774
8048 11:33:08.131831
8049 11:33:08.131883
8050 11:33:08.134397 [DramC_TX_OE_Calibration] TA2
8051 11:33:08.137834 Original DQ_B0 (3 6) =30, OEN = 27
8052 11:33:08.141170 Original DQ_B1 (3 6) =30, OEN = 27
8053 11:33:08.141265 24, 0x0, End_B0=24 End_B1=24
8054 11:33:08.144225 25, 0x0, End_B0=25 End_B1=25
8055 11:33:08.148263 26, 0x0, End_B0=26 End_B1=26
8056 11:33:08.150866 27, 0x0, End_B0=27 End_B1=27
8057 11:33:08.154486 28, 0x0, End_B0=28 End_B1=28
8058 11:33:08.154562 29, 0x0, End_B0=29 End_B1=29
8059 11:33:08.157929 30, 0x0, End_B0=30 End_B1=30
8060 11:33:08.161343 31, 0x4141, End_B0=30 End_B1=30
8061 11:33:08.164397 Byte0 end_step=30 best_step=27
8062 11:33:08.167484 Byte1 end_step=30 best_step=27
8063 11:33:08.171193 Byte0 TX OE(2T, 0.5T) = (3, 3)
8064 11:33:08.171268 Byte1 TX OE(2T, 0.5T) = (3, 3)
8065 11:33:08.171326
8066 11:33:08.175321
8067 11:33:08.181208 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8068 11:33:08.185131 CH0 RK1: MR19=303, MR18=2222
8069 11:33:08.191351 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
8070 11:33:08.191427 [RxdqsGatingPostProcess] freq 1600
8071 11:33:08.198289 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8072 11:33:08.201007 Pre-setting of DQS Precalculation
8073 11:33:08.207898 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8074 11:33:08.207973 ==
8075 11:33:08.210832 Dram Type= 6, Freq= 0, CH_1, rank 0
8076 11:33:08.214062 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8077 11:33:08.214137 ==
8078 11:33:08.220884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8079 11:33:08.224334 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8080 11:33:08.227221 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8081 11:33:08.234513 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8082 11:33:08.241708 [CA 0] Center 41 (11~71) winsize 61
8083 11:33:08.245844 [CA 1] Center 40 (10~70) winsize 61
8084 11:33:08.248601 [CA 2] Center 36 (6~66) winsize 61
8085 11:33:08.251495 [CA 3] Center 35 (6~65) winsize 60
8086 11:33:08.255304 [CA 4] Center 33 (3~63) winsize 61
8087 11:33:08.258380 [CA 5] Center 33 (4~63) winsize 60
8088 11:33:08.258455
8089 11:33:08.261677 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8090 11:33:08.261751
8091 11:33:08.265019 [CATrainingPosCal] consider 1 rank data
8092 11:33:08.269098 u2DelayCellTimex100 = 271/100 ps
8093 11:33:08.274729 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8094 11:33:08.278157 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8095 11:33:08.281547 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8096 11:33:08.284849 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8097 11:33:08.288415 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8098 11:33:08.291371 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8099 11:33:08.291446
8100 11:33:08.294561 CA PerBit enable=1, Macro0, CA PI delay=33
8101 11:33:08.294635
8102 11:33:08.298248 [CBTSetCACLKResult] CA Dly = 33
8103 11:33:08.301405 CS Dly: 8 (0~39)
8104 11:33:08.304771 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8105 11:33:08.308048 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8106 11:33:08.308122 ==
8107 11:33:08.312156 Dram Type= 6, Freq= 0, CH_1, rank 1
8108 11:33:08.314854 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8109 11:33:08.317666 ==
8110 11:33:08.320870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8111 11:33:08.324600 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8112 11:33:08.331165 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8113 11:33:08.337999 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8114 11:33:08.343949 [CA 0] Center 41 (11~71) winsize 61
8115 11:33:08.348142 [CA 1] Center 40 (10~71) winsize 62
8116 11:33:08.351672 [CA 2] Center 36 (7~66) winsize 60
8117 11:33:08.354596 [CA 3] Center 36 (7~65) winsize 59
8118 11:33:08.357667 [CA 4] Center 34 (4~64) winsize 61
8119 11:33:08.360658 [CA 5] Center 34 (4~64) winsize 61
8120 11:33:08.360732
8121 11:33:08.363938 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8122 11:33:08.364013
8123 11:33:08.367496 [CATrainingPosCal] consider 2 rank data
8124 11:33:08.370698 u2DelayCellTimex100 = 271/100 ps
8125 11:33:08.374845 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8126 11:33:08.380612 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8127 11:33:08.384305 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8128 11:33:08.387195 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8129 11:33:08.391122 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8130 11:33:08.393775 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8131 11:33:08.393849
8132 11:33:08.398179 CA PerBit enable=1, Macro0, CA PI delay=33
8133 11:33:08.398253
8134 11:33:08.400657 [CBTSetCACLKResult] CA Dly = 33
8135 11:33:08.404645 CS Dly: 9 (0~41)
8136 11:33:08.407931 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8137 11:33:08.410240 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8138 11:33:08.410330
8139 11:33:08.413988 ----->DramcWriteLeveling(PI) begin...
8140 11:33:08.414064 ==
8141 11:33:08.417454 Dram Type= 6, Freq= 0, CH_1, rank 0
8142 11:33:08.425569 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8143 11:33:08.425645 ==
8144 11:33:08.427087 Write leveling (Byte 0): 22 => 22
8145 11:33:08.427165 Write leveling (Byte 1): 23 => 23
8146 11:33:08.430185 DramcWriteLeveling(PI) end<-----
8147 11:33:08.430258
8148 11:33:08.433447 ==
8149 11:33:08.433521 Dram Type= 6, Freq= 0, CH_1, rank 0
8150 11:33:08.440417 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8151 11:33:08.440494 ==
8152 11:33:08.443414 [Gating] SW mode calibration
8153 11:33:08.450287 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8154 11:33:08.453325 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8155 11:33:08.460171 0 12 0 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
8156 11:33:08.463137 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8157 11:33:08.466666 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8158 11:33:08.473219 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8159 11:33:08.476927 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8160 11:33:08.479918 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8161 11:33:08.486501 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8162 11:33:08.489965 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8163 11:33:08.493306 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8164 11:33:08.499716 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8165 11:33:08.503111 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8166 11:33:08.506356 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8167 11:33:08.512995 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8168 11:33:08.516788 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8169 11:33:08.519975 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8170 11:33:08.526186 0 13 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8171 11:33:08.529984 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
8172 11:33:08.533128 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8173 11:33:08.539405 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8174 11:33:08.542844 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8175 11:33:08.546362 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8176 11:33:08.553108 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8177 11:33:08.556878 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8178 11:33:08.559541 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8179 11:33:08.562943 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8180 11:33:08.569555 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8181 11:33:08.572618 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8182 11:33:08.576156 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8183 11:33:08.583001 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8184 11:33:08.585740 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8185 11:33:08.589188 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8186 11:33:08.595838 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8187 11:33:08.599919 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8188 11:33:08.602999 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8189 11:33:08.609842 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8190 11:33:08.612766 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8191 11:33:08.615872 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8192 11:33:08.622670 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8193 11:33:08.626364 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8194 11:33:08.629689 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8195 11:33:08.635635 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8196 11:33:08.635709 Total UI for P1: 0, mck2ui 16
8197 11:33:08.642673 best dqsien dly found for B0: ( 1, 0, 26)
8198 11:33:08.646293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8199 11:33:08.649319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8200 11:33:08.652260 Total UI for P1: 0, mck2ui 16
8201 11:33:08.655643 best dqsien dly found for B1: ( 1, 1, 2)
8202 11:33:08.658867 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8203 11:33:08.662562 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8204 11:33:08.662628
8205 11:33:08.669642 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8206 11:33:08.672003 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8207 11:33:08.672069 [Gating] SW calibration Done
8208 11:33:08.676363 ==
8209 11:33:08.676434 Dram Type= 6, Freq= 0, CH_1, rank 0
8210 11:33:08.682373 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8211 11:33:08.682442 ==
8212 11:33:08.682499 RX Vref Scan: 0
8213 11:33:08.682552
8214 11:33:08.685596 RX Vref 0 -> 0, step: 1
8215 11:33:08.685657
8216 11:33:08.689098 RX Delay 0 -> 252, step: 8
8217 11:33:08.691801 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8218 11:33:08.695769 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8219 11:33:08.698994 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8220 11:33:08.705171 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8221 11:33:08.708747 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8222 11:33:08.711964 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8223 11:33:08.715646 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8224 11:33:08.718665 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8225 11:33:08.725464 iDelay=200, Bit 8, Center 103 (48 ~ 159) 112
8226 11:33:08.728935 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8227 11:33:08.731861 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8228 11:33:08.735283 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8229 11:33:08.738141 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8230 11:33:08.744903 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8231 11:33:08.748687 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8232 11:33:08.751941 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8233 11:33:08.752012 ==
8234 11:33:08.756007 Dram Type= 6, Freq= 0, CH_1, rank 0
8235 11:33:08.758046 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8236 11:33:08.761328 ==
8237 11:33:08.761390 DQS Delay:
8238 11:33:08.761443 DQS0 = 0, DQS1 = 0
8239 11:33:08.765036 DQM Delay:
8240 11:33:08.765119 DQM0 = 130, DQM1 = 124
8241 11:33:08.768866 DQ Delay:
8242 11:33:08.771317 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8243 11:33:08.775880 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8244 11:33:08.778250 DQ8 =103, DQ9 =115, DQ10 =127, DQ11 =115
8245 11:33:08.781436 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8246 11:33:08.781502
8247 11:33:08.781564
8248 11:33:08.781617 ==
8249 11:33:08.784579 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 11:33:08.788010 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8251 11:33:08.788100 ==
8252 11:33:08.791239
8253 11:33:08.791309
8254 11:33:08.791362 TX Vref Scan disable
8255 11:33:08.794722 == TX Byte 0 ==
8256 11:33:08.797848 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8257 11:33:08.801139 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8258 11:33:08.805010 == TX Byte 1 ==
8259 11:33:08.807939 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8260 11:33:08.811873 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8261 11:33:08.811948 ==
8262 11:33:08.814484 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 11:33:08.821143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8264 11:33:08.821277 ==
8265 11:33:08.832544
8266 11:33:08.836064 TX Vref early break, caculate TX vref
8267 11:33:08.839443 TX Vref=16, minBit 3, minWin=21, winSum=364
8268 11:33:08.842190 TX Vref=18, minBit 3, minWin=22, winSum=376
8269 11:33:08.845883 TX Vref=20, minBit 0, minWin=23, winSum=385
8270 11:33:08.848995 TX Vref=22, minBit 3, minWin=22, winSum=393
8271 11:33:08.852447 TX Vref=24, minBit 1, minWin=24, winSum=400
8272 11:33:08.858874 TX Vref=26, minBit 3, minWin=24, winSum=411
8273 11:33:08.862185 TX Vref=28, minBit 3, minWin=24, winSum=412
8274 11:33:08.865531 TX Vref=30, minBit 0, minWin=25, winSum=407
8275 11:33:08.869437 TX Vref=32, minBit 1, minWin=24, winSum=395
8276 11:33:08.871949 TX Vref=34, minBit 2, minWin=23, winSum=387
8277 11:33:08.879290 [TxChooseVref] Worse bit 0, Min win 25, Win sum 407, Final Vref 30
8278 11:33:08.879387
8279 11:33:08.882567 Final TX Range 0 Vref 30
8280 11:33:08.882636
8281 11:33:08.882717 ==
8282 11:33:08.885212 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 11:33:08.888709 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8284 11:33:08.888800 ==
8285 11:33:08.888889
8286 11:33:08.888982
8287 11:33:08.892347 TX Vref Scan disable
8288 11:33:08.898880 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8289 11:33:08.898979 == TX Byte 0 ==
8290 11:33:08.902320 u2DelayCellOfst[0]=14 cells (4 PI)
8291 11:33:08.905171 u2DelayCellOfst[1]=10 cells (3 PI)
8292 11:33:08.908831 u2DelayCellOfst[2]=0 cells (0 PI)
8293 11:33:08.912528 u2DelayCellOfst[3]=7 cells (2 PI)
8294 11:33:08.916035 u2DelayCellOfst[4]=7 cells (2 PI)
8295 11:33:08.919015 u2DelayCellOfst[5]=14 cells (4 PI)
8296 11:33:08.922310 u2DelayCellOfst[6]=14 cells (4 PI)
8297 11:33:08.922378 u2DelayCellOfst[7]=7 cells (2 PI)
8298 11:33:08.928380 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8299 11:33:08.931828 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8300 11:33:08.931918 == TX Byte 1 ==
8301 11:33:08.935567 u2DelayCellOfst[8]=0 cells (0 PI)
8302 11:33:08.938806 u2DelayCellOfst[9]=10 cells (3 PI)
8303 11:33:08.942095 u2DelayCellOfst[10]=14 cells (4 PI)
8304 11:33:08.945303 u2DelayCellOfst[11]=7 cells (2 PI)
8305 11:33:08.949368 u2DelayCellOfst[12]=21 cells (6 PI)
8306 11:33:08.951871 u2DelayCellOfst[13]=25 cells (7 PI)
8307 11:33:08.955332 u2DelayCellOfst[14]=25 cells (7 PI)
8308 11:33:08.958436 u2DelayCellOfst[15]=25 cells (7 PI)
8309 11:33:08.961754 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8310 11:33:08.968786 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8311 11:33:08.968878 DramC Write-DBI on
8312 11:33:08.968951 ==
8313 11:33:08.971980 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 11:33:08.975477 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8315 11:33:08.978530 ==
8316 11:33:08.978604
8317 11:33:08.978675
8318 11:33:08.978744 TX Vref Scan disable
8319 11:33:08.982090 == TX Byte 0 ==
8320 11:33:08.985124 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8321 11:33:08.988448 == TX Byte 1 ==
8322 11:33:08.991966 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8323 11:33:08.994820 DramC Write-DBI off
8324 11:33:08.994887
8325 11:33:08.994959 [DATLAT]
8326 11:33:08.995036 Freq=1600, CH1 RK0
8327 11:33:08.995105
8328 11:33:08.998379 DATLAT Default: 0xf
8329 11:33:08.998464 0, 0xFFFF, sum = 0
8330 11:33:09.001975 1, 0xFFFF, sum = 0
8331 11:33:09.005480 2, 0xFFFF, sum = 0
8332 11:33:09.005559 3, 0xFFFF, sum = 0
8333 11:33:09.008268 4, 0xFFFF, sum = 0
8334 11:33:09.008346 5, 0xFFFF, sum = 0
8335 11:33:09.011739 6, 0xFFFF, sum = 0
8336 11:33:09.011817 7, 0xFFFF, sum = 0
8337 11:33:09.014725 8, 0xFFFF, sum = 0
8338 11:33:09.014804 9, 0xFFFF, sum = 0
8339 11:33:09.017976 10, 0xFFFF, sum = 0
8340 11:33:09.018054 11, 0xFFFF, sum = 0
8341 11:33:09.021509 12, 0xF7F, sum = 0
8342 11:33:09.021587 13, 0x0, sum = 1
8343 11:33:09.024954 14, 0x0, sum = 2
8344 11:33:09.025032 15, 0x0, sum = 3
8345 11:33:09.028421 16, 0x0, sum = 4
8346 11:33:09.028499 best_step = 14
8347 11:33:09.028574
8348 11:33:09.028646 ==
8349 11:33:09.031617 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 11:33:09.035236 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8351 11:33:09.038005 ==
8352 11:33:09.038105 RX Vref Scan: 1
8353 11:33:09.038183
8354 11:33:09.041069 Set Vref Range= 24 -> 127
8355 11:33:09.041146
8356 11:33:09.044919 RX Vref 24 -> 127, step: 1
8357 11:33:09.044995
8358 11:33:09.045071 RX Delay 3 -> 252, step: 4
8359 11:33:09.045161
8360 11:33:09.048110 Set Vref, RX VrefLevel [Byte0]: 24
8361 11:33:09.050939 [Byte1]: 24
8362 11:33:09.055204
8363 11:33:09.055280 Set Vref, RX VrefLevel [Byte0]: 25
8364 11:33:09.058105 [Byte1]: 25
8365 11:33:09.062413
8366 11:33:09.062490 Set Vref, RX VrefLevel [Byte0]: 26
8367 11:33:09.066319 [Byte1]: 26
8368 11:33:09.070141
8369 11:33:09.070216 Set Vref, RX VrefLevel [Byte0]: 27
8370 11:33:09.073452 [Byte1]: 27
8371 11:33:09.077856
8372 11:33:09.077931 Set Vref, RX VrefLevel [Byte0]: 28
8373 11:33:09.081153 [Byte1]: 28
8374 11:33:09.085383
8375 11:33:09.085457 Set Vref, RX VrefLevel [Byte0]: 29
8376 11:33:09.088903 [Byte1]: 29
8377 11:33:09.092964
8378 11:33:09.093056 Set Vref, RX VrefLevel [Byte0]: 30
8379 11:33:09.096538 [Byte1]: 30
8380 11:33:09.100540
8381 11:33:09.100618 Set Vref, RX VrefLevel [Byte0]: 31
8382 11:33:09.104190 [Byte1]: 31
8383 11:33:09.108667
8384 11:33:09.108740 Set Vref, RX VrefLevel [Byte0]: 32
8385 11:33:09.111602 [Byte1]: 32
8386 11:33:09.116403
8387 11:33:09.116477 Set Vref, RX VrefLevel [Byte0]: 33
8388 11:33:09.119874 [Byte1]: 33
8389 11:33:09.124704
8390 11:33:09.124777 Set Vref, RX VrefLevel [Byte0]: 34
8391 11:33:09.126992 [Byte1]: 34
8392 11:33:09.131877
8393 11:33:09.131951 Set Vref, RX VrefLevel [Byte0]: 35
8394 11:33:09.134524 [Byte1]: 35
8395 11:33:09.139162
8396 11:33:09.139239 Set Vref, RX VrefLevel [Byte0]: 36
8397 11:33:09.142078 [Byte1]: 36
8398 11:33:09.146776
8399 11:33:09.146849 Set Vref, RX VrefLevel [Byte0]: 37
8400 11:33:09.149956 [Byte1]: 37
8401 11:33:09.154206
8402 11:33:09.154280 Set Vref, RX VrefLevel [Byte0]: 38
8403 11:33:09.158319 [Byte1]: 38
8404 11:33:09.162175
8405 11:33:09.162248 Set Vref, RX VrefLevel [Byte0]: 39
8406 11:33:09.165620 [Byte1]: 39
8407 11:33:09.169604
8408 11:33:09.169679 Set Vref, RX VrefLevel [Byte0]: 40
8409 11:33:09.173137 [Byte1]: 40
8410 11:33:09.177765
8411 11:33:09.177839 Set Vref, RX VrefLevel [Byte0]: 41
8412 11:33:09.180659 [Byte1]: 41
8413 11:33:09.185771
8414 11:33:09.185845 Set Vref, RX VrefLevel [Byte0]: 42
8415 11:33:09.188130 [Byte1]: 42
8416 11:33:09.192938
8417 11:33:09.193011 Set Vref, RX VrefLevel [Byte0]: 43
8418 11:33:09.196222 [Byte1]: 43
8419 11:33:09.200675
8420 11:33:09.200749 Set Vref, RX VrefLevel [Byte0]: 44
8421 11:33:09.203869 [Byte1]: 44
8422 11:33:09.208701
8423 11:33:09.208775 Set Vref, RX VrefLevel [Byte0]: 45
8424 11:33:09.211351 [Byte1]: 45
8425 11:33:09.215457
8426 11:33:09.215531 Set Vref, RX VrefLevel [Byte0]: 46
8427 11:33:09.219012 [Byte1]: 46
8428 11:33:09.223299
8429 11:33:09.223378 Set Vref, RX VrefLevel [Byte0]: 47
8430 11:33:09.226453 [Byte1]: 47
8431 11:33:09.231567
8432 11:33:09.231641 Set Vref, RX VrefLevel [Byte0]: 48
8433 11:33:09.234507 [Byte1]: 48
8434 11:33:09.239215
8435 11:33:09.239314 Set Vref, RX VrefLevel [Byte0]: 49
8436 11:33:09.241964 [Byte1]: 49
8437 11:33:09.246169
8438 11:33:09.246246 Set Vref, RX VrefLevel [Byte0]: 50
8439 11:33:09.249447 [Byte1]: 50
8440 11:33:09.253893
8441 11:33:09.253970 Set Vref, RX VrefLevel [Byte0]: 51
8442 11:33:09.257390 [Byte1]: 51
8443 11:33:09.261432
8444 11:33:09.261509 Set Vref, RX VrefLevel [Byte0]: 52
8445 11:33:09.265204 [Byte1]: 52
8446 11:33:09.269088
8447 11:33:09.269164 Set Vref, RX VrefLevel [Byte0]: 53
8448 11:33:09.272593 [Byte1]: 53
8449 11:33:09.277288
8450 11:33:09.277365 Set Vref, RX VrefLevel [Byte0]: 54
8451 11:33:09.279919 [Byte1]: 54
8452 11:33:09.284504
8453 11:33:09.284580 Set Vref, RX VrefLevel [Byte0]: 55
8454 11:33:09.287813 [Byte1]: 55
8455 11:33:09.291974
8456 11:33:09.292051 Set Vref, RX VrefLevel [Byte0]: 56
8457 11:33:09.295244 [Byte1]: 56
8458 11:33:09.300112
8459 11:33:09.300188 Set Vref, RX VrefLevel [Byte0]: 57
8460 11:33:09.303111 [Byte1]: 57
8461 11:33:09.307313
8462 11:33:09.307390 Set Vref, RX VrefLevel [Byte0]: 58
8463 11:33:09.310762 [Byte1]: 58
8464 11:33:09.315336
8465 11:33:09.315413 Set Vref, RX VrefLevel [Byte0]: 59
8466 11:33:09.318729 [Byte1]: 59
8467 11:33:09.322795
8468 11:33:09.322863 Set Vref, RX VrefLevel [Byte0]: 60
8469 11:33:09.326512 [Byte1]: 60
8470 11:33:09.330610
8471 11:33:09.330675 Set Vref, RX VrefLevel [Byte0]: 61
8472 11:33:09.333985 [Byte1]: 61
8473 11:33:09.338162
8474 11:33:09.338237 Set Vref, RX VrefLevel [Byte0]: 62
8475 11:33:09.341752 [Byte1]: 62
8476 11:33:09.345836
8477 11:33:09.345902 Set Vref, RX VrefLevel [Byte0]: 63
8478 11:33:09.348772 [Byte1]: 63
8479 11:33:09.353585
8480 11:33:09.353653 Set Vref, RX VrefLevel [Byte0]: 64
8481 11:33:09.357095 [Byte1]: 64
8482 11:33:09.360973
8483 11:33:09.361053 Set Vref, RX VrefLevel [Byte0]: 65
8484 11:33:09.364472 [Byte1]: 65
8485 11:33:09.368846
8486 11:33:09.368924 Set Vref, RX VrefLevel [Byte0]: 66
8487 11:33:09.371943 [Byte1]: 66
8488 11:33:09.376000
8489 11:33:09.376076 Set Vref, RX VrefLevel [Byte0]: 67
8490 11:33:09.379826 [Byte1]: 67
8491 11:33:09.384200
8492 11:33:09.384276 Set Vref, RX VrefLevel [Byte0]: 68
8493 11:33:09.387639 [Byte1]: 68
8494 11:33:09.392222
8495 11:33:09.392299 Set Vref, RX VrefLevel [Byte0]: 69
8496 11:33:09.394910 [Byte1]: 69
8497 11:33:09.399122
8498 11:33:09.399199 Set Vref, RX VrefLevel [Byte0]: 70
8499 11:33:09.402541 [Byte1]: 70
8500 11:33:09.406920
8501 11:33:09.406999 Set Vref, RX VrefLevel [Byte0]: 71
8502 11:33:09.409982 [Byte1]: 71
8503 11:33:09.416196
8504 11:33:09.416272 Set Vref, RX VrefLevel [Byte0]: 72
8505 11:33:09.418991 [Byte1]: 72
8506 11:33:09.422069
8507 11:33:09.422145 Set Vref, RX VrefLevel [Byte0]: 73
8508 11:33:09.426163 [Byte1]: 73
8509 11:33:09.430325
8510 11:33:09.430401 Set Vref, RX VrefLevel [Byte0]: 74
8511 11:33:09.433160 [Byte1]: 74
8512 11:33:09.437375
8513 11:33:09.437452 Set Vref, RX VrefLevel [Byte0]: 75
8514 11:33:09.440849 [Byte1]: 75
8515 11:33:09.445134
8516 11:33:09.445211 Final RX Vref Byte 0 = 63 to rank0
8517 11:33:09.448713 Final RX Vref Byte 1 = 53 to rank0
8518 11:33:09.451342 Final RX Vref Byte 0 = 63 to rank1
8519 11:33:09.455403 Final RX Vref Byte 1 = 53 to rank1==
8520 11:33:09.457996 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 11:33:09.464825 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8522 11:33:09.464903 ==
8523 11:33:09.464980 DQS Delay:
8524 11:33:09.468146 DQS0 = 0, DQS1 = 0
8525 11:33:09.468222 DQM Delay:
8526 11:33:09.471298 DQM0 = 128, DQM1 = 124
8527 11:33:09.471374 DQ Delay:
8528 11:33:09.474906 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =126
8529 11:33:09.477931 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8530 11:33:09.481588 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8531 11:33:09.484742 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8532 11:33:09.484816
8533 11:33:09.484872
8534 11:33:09.484924
8535 11:33:09.487888 [DramC_TX_OE_Calibration] TA2
8536 11:33:09.490743 Original DQ_B0 (3 6) =30, OEN = 27
8537 11:33:09.495141 Original DQ_B1 (3 6) =30, OEN = 27
8538 11:33:09.497420 24, 0x0, End_B0=24 End_B1=24
8539 11:33:09.501353 25, 0x0, End_B0=25 End_B1=25
8540 11:33:09.501428 26, 0x0, End_B0=26 End_B1=26
8541 11:33:09.504276 27, 0x0, End_B0=27 End_B1=27
8542 11:33:09.508020 28, 0x0, End_B0=28 End_B1=28
8543 11:33:09.510993 29, 0x0, End_B0=29 End_B1=29
8544 11:33:09.511068 30, 0x0, End_B0=30 End_B1=30
8545 11:33:09.514063 31, 0x4141, End_B0=30 End_B1=30
8546 11:33:09.517492 Byte0 end_step=30 best_step=27
8547 11:33:09.521083 Byte1 end_step=30 best_step=27
8548 11:33:09.524087 Byte0 TX OE(2T, 0.5T) = (3, 3)
8549 11:33:09.527389 Byte1 TX OE(2T, 0.5T) = (3, 3)
8550 11:33:09.527463
8551 11:33:09.527521
8552 11:33:09.535446 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8553 11:33:09.537514 CH1 RK0: MR19=303, MR18=2828
8554 11:33:09.543691 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8555 11:33:09.543770
8556 11:33:09.547103 ----->DramcWriteLeveling(PI) begin...
8557 11:33:09.547179 ==
8558 11:33:09.550270 Dram Type= 6, Freq= 0, CH_1, rank 1
8559 11:33:09.553736 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8560 11:33:09.553811 ==
8561 11:33:09.557018 Write leveling (Byte 0): 24 => 24
8562 11:33:09.560627 Write leveling (Byte 1): 22 => 22
8563 11:33:09.563376 DramcWriteLeveling(PI) end<-----
8564 11:33:09.563451
8565 11:33:09.563508 ==
8566 11:33:09.567227 Dram Type= 6, Freq= 0, CH_1, rank 1
8567 11:33:09.573469 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8568 11:33:09.573544 ==
8569 11:33:09.573602 [Gating] SW mode calibration
8570 11:33:09.583734 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8571 11:33:09.587121 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8572 11:33:09.590280 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
8573 11:33:09.597464 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8574 11:33:09.599662 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8575 11:33:09.603394 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8576 11:33:09.610991 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8577 11:33:09.613331 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8578 11:33:09.616635 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8579 11:33:09.622883 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8580 11:33:09.626756 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8581 11:33:09.629594 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8582 11:33:09.636540 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8583 11:33:09.640005 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8584 11:33:09.643724 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8585 11:33:09.649507 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8586 11:33:09.652503 0 13 24 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8587 11:33:09.656433 0 13 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8588 11:33:09.662892 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8589 11:33:09.666252 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8590 11:33:09.669591 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8591 11:33:09.676124 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8592 11:33:09.679198 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8593 11:33:09.682533 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8594 11:33:09.689118 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8595 11:33:09.693546 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8596 11:33:09.696124 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8597 11:33:09.704032 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8598 11:33:09.706272 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8599 11:33:09.708936 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8600 11:33:09.715955 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8601 11:33:09.718870 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8602 11:33:09.722913 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8603 11:33:09.729097 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8604 11:33:09.731952 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8605 11:33:09.736081 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8606 11:33:09.742082 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8607 11:33:09.745687 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8608 11:33:09.750961 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8609 11:33:09.755555 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8610 11:33:09.758331 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8611 11:33:09.762091 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8612 11:33:09.768913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8613 11:33:09.768993 Total UI for P1: 0, mck2ui 16
8614 11:33:09.775756 best dqsien dly found for B0: ( 1, 0, 26)
8615 11:33:09.775833 Total UI for P1: 0, mck2ui 16
8616 11:33:09.781624 best dqsien dly found for B1: ( 1, 0, 30)
8617 11:33:09.784967 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8618 11:33:09.788175 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8619 11:33:09.788252
8620 11:33:09.791659 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8621 11:33:09.795333 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8622 11:33:09.798117 [Gating] SW calibration Done
8623 11:33:09.798193 ==
8624 11:33:09.802009 Dram Type= 6, Freq= 0, CH_1, rank 1
8625 11:33:09.804752 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8626 11:33:09.804829 ==
8627 11:33:09.808234 RX Vref Scan: 0
8628 11:33:09.808311
8629 11:33:09.808387 RX Vref 0 -> 0, step: 1
8630 11:33:09.808459
8631 11:33:09.811881 RX Delay 0 -> 252, step: 8
8632 11:33:09.814941 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8633 11:33:09.821321 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8634 11:33:09.824841 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8635 11:33:09.827995 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8636 11:33:09.831705 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8637 11:33:09.834878 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8638 11:33:09.841143 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8639 11:33:09.844638 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8640 11:33:09.848640 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8641 11:33:09.851720 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8642 11:33:09.855107 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8643 11:33:09.861660 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8644 11:33:09.864343 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8645 11:33:09.868263 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8646 11:33:09.870605 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8647 11:33:09.877619 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8648 11:33:09.877688 ==
8649 11:33:09.880767 Dram Type= 6, Freq= 0, CH_1, rank 1
8650 11:33:09.883938 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8651 11:33:09.884001 ==
8652 11:33:09.884060 DQS Delay:
8653 11:33:09.887597 DQS0 = 0, DQS1 = 0
8654 11:33:09.887662 DQM Delay:
8655 11:33:09.890908 DQM0 = 130, DQM1 = 125
8656 11:33:09.890970 DQ Delay:
8657 11:33:09.894004 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8658 11:33:09.897376 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8659 11:33:09.900596 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8660 11:33:09.905043 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8661 11:33:09.905128
8662 11:33:09.905207
8663 11:33:09.907292 ==
8664 11:33:09.910293 Dram Type= 6, Freq= 0, CH_1, rank 1
8665 11:33:09.913885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8666 11:33:09.913962 ==
8667 11:33:09.914055
8668 11:33:09.914144
8669 11:33:09.917880 TX Vref Scan disable
8670 11:33:09.917968 == TX Byte 0 ==
8671 11:33:09.923804 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8672 11:33:09.927097 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8673 11:33:09.927196 == TX Byte 1 ==
8674 11:33:09.933543 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8675 11:33:09.936899 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8676 11:33:09.936976 ==
8677 11:33:09.940063 Dram Type= 6, Freq= 0, CH_1, rank 1
8678 11:33:09.943458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8679 11:33:09.943536 ==
8680 11:33:09.956802
8681 11:33:09.960503 TX Vref early break, caculate TX vref
8682 11:33:09.963941 TX Vref=16, minBit 0, minWin=22, winSum=379
8683 11:33:09.966699 TX Vref=18, minBit 0, minWin=23, winSum=388
8684 11:33:09.970147 TX Vref=20, minBit 0, minWin=24, winSum=397
8685 11:33:09.973718 TX Vref=22, minBit 0, minWin=24, winSum=404
8686 11:33:09.977058 TX Vref=24, minBit 3, minWin=25, winSum=413
8687 11:33:09.984638 TX Vref=26, minBit 0, minWin=25, winSum=417
8688 11:33:09.986383 TX Vref=28, minBit 0, minWin=25, winSum=422
8689 11:33:09.990091 TX Vref=30, minBit 0, minWin=23, winSum=414
8690 11:33:09.994295 TX Vref=32, minBit 0, minWin=23, winSum=403
8691 11:33:09.996748 TX Vref=34, minBit 0, minWin=22, winSum=397
8692 11:33:10.004315 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8693 11:33:10.004393
8694 11:33:10.006328 Final TX Range 0 Vref 28
8695 11:33:10.006405
8696 11:33:10.006481 ==
8697 11:33:10.010491 Dram Type= 6, Freq= 0, CH_1, rank 1
8698 11:33:10.013656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8699 11:33:10.013731 ==
8700 11:33:10.013789
8701 11:33:10.013842
8702 11:33:10.016819 TX Vref Scan disable
8703 11:33:10.022850 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8704 11:33:10.022944 == TX Byte 0 ==
8705 11:33:10.026285 u2DelayCellOfst[0]=18 cells (5 PI)
8706 11:33:10.030048 u2DelayCellOfst[1]=10 cells (3 PI)
8707 11:33:10.033711 u2DelayCellOfst[2]=0 cells (0 PI)
8708 11:33:10.036359 u2DelayCellOfst[3]=7 cells (2 PI)
8709 11:33:10.039600 u2DelayCellOfst[4]=7 cells (2 PI)
8710 11:33:10.043178 u2DelayCellOfst[5]=14 cells (4 PI)
8711 11:33:10.046278 u2DelayCellOfst[6]=14 cells (4 PI)
8712 11:33:10.046416 u2DelayCellOfst[7]=3 cells (1 PI)
8713 11:33:10.053234 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8714 11:33:10.056196 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8715 11:33:10.056271 == TX Byte 1 ==
8716 11:33:10.061133 u2DelayCellOfst[8]=0 cells (0 PI)
8717 11:33:10.063231 u2DelayCellOfst[9]=7 cells (2 PI)
8718 11:33:10.066382 u2DelayCellOfst[10]=14 cells (4 PI)
8719 11:33:10.070278 u2DelayCellOfst[11]=3 cells (1 PI)
8720 11:33:10.073427 u2DelayCellOfst[12]=18 cells (5 PI)
8721 11:33:10.076297 u2DelayCellOfst[13]=21 cells (6 PI)
8722 11:33:10.080195 u2DelayCellOfst[14]=21 cells (6 PI)
8723 11:33:10.082701 u2DelayCellOfst[15]=21 cells (6 PI)
8724 11:33:10.086161 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8725 11:33:10.093548 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8726 11:33:10.093648 DramC Write-DBI on
8727 11:33:10.093725 ==
8728 11:33:10.096684 Dram Type= 6, Freq= 0, CH_1, rank 1
8729 11:33:10.099741 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8730 11:33:10.102803 ==
8731 11:33:10.102898
8732 11:33:10.102973
8733 11:33:10.103047 TX Vref Scan disable
8734 11:33:10.106031 == TX Byte 0 ==
8735 11:33:10.109094 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8736 11:33:10.112453 == TX Byte 1 ==
8737 11:33:10.115881 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8738 11:33:10.119701 DramC Write-DBI off
8739 11:33:10.119778
8740 11:33:10.119854 [DATLAT]
8741 11:33:10.119926 Freq=1600, CH1 RK1
8742 11:33:10.119996
8743 11:33:10.122394 DATLAT Default: 0xe
8744 11:33:10.122473 0, 0xFFFF, sum = 0
8745 11:33:10.126053 1, 0xFFFF, sum = 0
8746 11:33:10.129741 2, 0xFFFF, sum = 0
8747 11:33:10.129819 3, 0xFFFF, sum = 0
8748 11:33:10.132346 4, 0xFFFF, sum = 0
8749 11:33:10.132424 5, 0xFFFF, sum = 0
8750 11:33:10.135986 6, 0xFFFF, sum = 0
8751 11:33:10.136065 7, 0xFFFF, sum = 0
8752 11:33:10.139018 8, 0xFFFF, sum = 0
8753 11:33:10.139096 9, 0xFFFF, sum = 0
8754 11:33:10.142313 10, 0xFFFF, sum = 0
8755 11:33:10.142391 11, 0xFFFF, sum = 0
8756 11:33:10.145907 12, 0xF7F, sum = 0
8757 11:33:10.145986 13, 0x0, sum = 1
8758 11:33:10.149026 14, 0x0, sum = 2
8759 11:33:10.149103 15, 0x0, sum = 3
8760 11:33:10.152304 16, 0x0, sum = 4
8761 11:33:10.152405 best_step = 14
8762 11:33:10.152497
8763 11:33:10.152587 ==
8764 11:33:10.156230 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 11:33:10.159148 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8766 11:33:10.162317 ==
8767 11:33:10.162392 RX Vref Scan: 0
8768 11:33:10.162455
8769 11:33:10.165657 RX Vref 0 -> 0, step: 1
8770 11:33:10.165720
8771 11:33:10.165773 RX Delay 3 -> 252, step: 4
8772 11:33:10.173236 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8773 11:33:10.176133 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8774 11:33:10.179792 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8775 11:33:10.182728 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8776 11:33:10.189903 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8777 11:33:10.192899 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8778 11:33:10.196150 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8779 11:33:10.200421 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8780 11:33:10.202514 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8781 11:33:10.205789 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8782 11:33:10.212549 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8783 11:33:10.216191 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8784 11:33:10.219250 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8785 11:33:10.222468 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8786 11:33:10.229518 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8787 11:33:10.232504 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8788 11:33:10.232581 ==
8789 11:33:10.235669 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 11:33:10.239559 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8791 11:33:10.239637 ==
8792 11:33:10.243246 DQS Delay:
8793 11:33:10.243322 DQS0 = 0, DQS1 = 0
8794 11:33:10.243399 DQM Delay:
8795 11:33:10.245909 DQM0 = 126, DQM1 = 122
8796 11:33:10.245985 DQ Delay:
8797 11:33:10.248813 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8798 11:33:10.252096 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =124
8799 11:33:10.255634 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8800 11:33:10.262650 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8801 11:33:10.262727
8802 11:33:10.262804
8803 11:33:10.262875
8804 11:33:10.265501 [DramC_TX_OE_Calibration] TA2
8805 11:33:10.269279 Original DQ_B0 (3 6) =30, OEN = 27
8806 11:33:10.269356 Original DQ_B1 (3 6) =30, OEN = 27
8807 11:33:10.272188 24, 0x0, End_B0=24 End_B1=24
8808 11:33:10.275399 25, 0x0, End_B0=25 End_B1=25
8809 11:33:10.280482 26, 0x0, End_B0=26 End_B1=26
8810 11:33:10.282941 27, 0x0, End_B0=27 End_B1=27
8811 11:33:10.283019 28, 0x0, End_B0=28 End_B1=28
8812 11:33:10.286138 29, 0x0, End_B0=29 End_B1=29
8813 11:33:10.288815 30, 0x0, End_B0=30 End_B1=30
8814 11:33:10.292059 31, 0x4141, End_B0=30 End_B1=30
8815 11:33:10.295418 Byte0 end_step=30 best_step=27
8816 11:33:10.295492 Byte1 end_step=30 best_step=27
8817 11:33:10.298655 Byte0 TX OE(2T, 0.5T) = (3, 3)
8818 11:33:10.301952 Byte1 TX OE(2T, 0.5T) = (3, 3)
8819 11:33:10.302027
8820 11:33:10.302084
8821 11:33:10.311800 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8822 11:33:10.311876 CH1 RK1: MR19=303, MR18=1B1B
8823 11:33:10.318322 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8824 11:33:10.322116 [RxdqsGatingPostProcess] freq 1600
8825 11:33:10.329131 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8826 11:33:10.331829 Pre-setting of DQS Precalculation
8827 11:33:10.334934 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8828 11:33:10.346167 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8829 11:33:10.352500 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8830 11:33:10.352575
8831 11:33:10.352633
8832 11:33:10.355118 [Calibration Summary] 3200 Mbps
8833 11:33:10.355192 CH 0, Rank 0
8834 11:33:10.358370 SW Impedance : PASS
8835 11:33:10.358445 DUTY Scan : NO K
8836 11:33:10.361800 ZQ Calibration : PASS
8837 11:33:10.366436 Jitter Meter : NO K
8838 11:33:10.366510 CBT Training : PASS
8839 11:33:10.368298 Write leveling : PASS
8840 11:33:10.372366 RX DQS gating : PASS
8841 11:33:10.372441 RX DQ/DQS(RDDQC) : PASS
8842 11:33:10.375111 TX DQ/DQS : PASS
8843 11:33:10.378738 RX DATLAT : PASS
8844 11:33:10.378815 RX DQ/DQS(Engine): PASS
8845 11:33:10.382010 TX OE : PASS
8846 11:33:10.382088 All Pass.
8847 11:33:10.382165
8848 11:33:10.384857 CH 0, Rank 1
8849 11:33:10.384934 SW Impedance : PASS
8850 11:33:10.388449 DUTY Scan : NO K
8851 11:33:10.388526 ZQ Calibration : PASS
8852 11:33:10.391509 Jitter Meter : NO K
8853 11:33:10.394840 CBT Training : PASS
8854 11:33:10.394917 Write leveling : PASS
8855 11:33:10.397899 RX DQS gating : PASS
8856 11:33:10.401783 RX DQ/DQS(RDDQC) : PASS
8857 11:33:10.401860 TX DQ/DQS : PASS
8858 11:33:10.404449 RX DATLAT : PASS
8859 11:33:10.407841 RX DQ/DQS(Engine): PASS
8860 11:33:10.407918 TX OE : PASS
8861 11:33:10.412127 All Pass.
8862 11:33:10.412203
8863 11:33:10.412280 CH 1, Rank 0
8864 11:33:10.414339 SW Impedance : PASS
8865 11:33:10.414416 DUTY Scan : NO K
8866 11:33:10.418766 ZQ Calibration : PASS
8867 11:33:10.421771 Jitter Meter : NO K
8868 11:33:10.421847 CBT Training : PASS
8869 11:33:10.424566 Write leveling : PASS
8870 11:33:10.427868 RX DQS gating : PASS
8871 11:33:10.427945 RX DQ/DQS(RDDQC) : PASS
8872 11:33:10.431256 TX DQ/DQS : PASS
8873 11:33:10.435343 RX DATLAT : PASS
8874 11:33:10.435420 RX DQ/DQS(Engine): PASS
8875 11:33:10.437714 TX OE : PASS
8876 11:33:10.437791 All Pass.
8877 11:33:10.437868
8878 11:33:10.441366 CH 1, Rank 1
8879 11:33:10.441442 SW Impedance : PASS
8880 11:33:10.444373 DUTY Scan : NO K
8881 11:33:10.447834 ZQ Calibration : PASS
8882 11:33:10.447911 Jitter Meter : NO K
8883 11:33:10.451695 CBT Training : PASS
8884 11:33:10.453940 Write leveling : PASS
8885 11:33:10.454016 RX DQS gating : PASS
8886 11:33:10.457565 RX DQ/DQS(RDDQC) : PASS
8887 11:33:10.457641 TX DQ/DQS : PASS
8888 11:33:10.460730 RX DATLAT : PASS
8889 11:33:10.464014 RX DQ/DQS(Engine): PASS
8890 11:33:10.464091 TX OE : PASS
8891 11:33:10.467350 All Pass.
8892 11:33:10.467426
8893 11:33:10.467502 DramC Write-DBI on
8894 11:33:10.470561 PER_BANK_REFRESH: Hybrid Mode
8895 11:33:10.474272 TX_TRACKING: ON
8896 11:33:10.480619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8897 11:33:10.490285 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8898 11:33:10.497348 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8899 11:33:10.501394 [FAST_K] Save calibration result to emmc
8900 11:33:10.503666 sync common calibartion params.
8901 11:33:10.503743 sync cbt_mode0:0, 1:0
8902 11:33:10.506851 dram_init: ddr_geometry: 0
8903 11:33:10.510066 dram_init: ddr_geometry: 0
8904 11:33:10.513952 dram_init: ddr_geometry: 0
8905 11:33:10.514029 0:dram_rank_size:80000000
8906 11:33:10.517176 1:dram_rank_size:80000000
8907 11:33:10.523605 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8908 11:33:10.523683 DFS_SHUFFLE_HW_MODE: ON
8909 11:33:10.526796 dramc_set_vcore_voltage set vcore to 725000
8910 11:33:10.530222 Read voltage for 1600, 0
8911 11:33:10.530299 Vio18 = 0
8912 11:33:10.534456 Vcore = 725000
8913 11:33:10.534532 Vdram = 0
8914 11:33:10.534609 Vddq = 0
8915 11:33:10.536956 Vmddr = 0
8916 11:33:10.537034 switch to 3200 Mbps bootup
8917 11:33:10.540579 [DramcRunTimeConfig]
8918 11:33:10.540655 PHYPLL
8919 11:33:10.543668 DPM_CONTROL_AFTERK: ON
8920 11:33:10.543744 PER_BANK_REFRESH: ON
8921 11:33:10.547259 REFRESH_OVERHEAD_REDUCTION: ON
8922 11:33:10.550050 CMD_PICG_NEW_MODE: OFF
8923 11:33:10.550127 XRTWTW_NEW_MODE: ON
8924 11:33:10.553859 XRTRTR_NEW_MODE: ON
8925 11:33:10.553935 TX_TRACKING: ON
8926 11:33:10.556682 RDSEL_TRACKING: OFF
8927 11:33:10.559972 DQS Precalculation for DVFS: ON
8928 11:33:10.560050 RX_TRACKING: OFF
8929 11:33:10.563627 HW_GATING DBG: ON
8930 11:33:10.563704 ZQCS_ENABLE_LP4: ON
8931 11:33:10.566564 RX_PICG_NEW_MODE: ON
8932 11:33:10.566640 TX_PICG_NEW_MODE: ON
8933 11:33:10.569700 ENABLE_RX_DCM_DPHY: ON
8934 11:33:10.573034 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8935 11:33:10.576554 DUMMY_READ_FOR_TRACKING: OFF
8936 11:33:10.579705 !!! SPM_CONTROL_AFTERK: OFF
8937 11:33:10.579786 !!! SPM could not control APHY
8938 11:33:10.583062 IMPEDANCE_TRACKING: ON
8939 11:33:10.583139 TEMP_SENSOR: ON
8940 11:33:10.587066 HW_SAVE_FOR_SR: OFF
8941 11:33:10.590454 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8942 11:33:10.593621 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8943 11:33:10.596867 Read ODT Tracking: ON
8944 11:33:10.596944 Refresh Rate DeBounce: ON
8945 11:33:10.599793 DFS_NO_QUEUE_FLUSH: ON
8946 11:33:10.603300 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8947 11:33:10.606480 ENABLE_DFS_RUNTIME_MRW: OFF
8948 11:33:10.606557 DDR_RESERVE_NEW_MODE: ON
8949 11:33:10.610308 MR_CBT_SWITCH_FREQ: ON
8950 11:33:10.613068 =========================
8951 11:33:10.630491 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8952 11:33:10.633581 dram_init: ddr_geometry: 0
8953 11:33:10.651643 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8954 11:33:10.655166 dram_init: dram init end (result: 0)
8955 11:33:10.661734 DRAM-K: Full calibration passed in 23483 msecs
8956 11:33:10.664990 MRC: failed to locate region type 0.
8957 11:33:10.665067 DRAM rank0 size:0x80000000,
8958 11:33:10.668678 DRAM rank1 size=0x80000000
8959 11:33:10.678893 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8960 11:33:10.685011 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8961 11:33:10.691488 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8962 11:33:10.698157 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8963 11:33:10.701434 DRAM rank0 size:0x80000000,
8964 11:33:10.704735 DRAM rank1 size=0x80000000
8965 11:33:10.704823 CBMEM:
8966 11:33:10.707942 IMD: root @ 0xfffff000 254 entries.
8967 11:33:10.711909 IMD: root @ 0xffffec00 62 entries.
8968 11:33:10.714489 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8969 11:33:10.717968 WARNING: RO_VPD is uninitialized or empty.
8970 11:33:10.724584 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8971 11:33:10.731409 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8972 11:33:10.744586 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8973 11:33:10.755634 BS: romstage times (exec / console): total (unknown) / 23010 ms
8974 11:33:10.755728
8975 11:33:10.755813
8976 11:33:10.765505 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8977 11:33:10.769554 ARM64: Exception handlers installed.
8978 11:33:10.772347 ARM64: Testing exception
8979 11:33:10.775905 ARM64: Done test exception
8980 11:33:10.775979 Enumerating buses...
8981 11:33:10.779348 Show all devs... Before device enumeration.
8982 11:33:10.782256 Root Device: enabled 1
8983 11:33:10.785482 CPU_CLUSTER: 0: enabled 1
8984 11:33:10.785575 CPU: 00: enabled 1
8985 11:33:10.789378 Compare with tree...
8986 11:33:10.789443 Root Device: enabled 1
8987 11:33:10.792316 CPU_CLUSTER: 0: enabled 1
8988 11:33:10.795793 CPU: 00: enabled 1
8989 11:33:10.795878 Root Device scanning...
8990 11:33:10.799030 scan_static_bus for Root Device
8991 11:33:10.801949 CPU_CLUSTER: 0 enabled
8992 11:33:10.805633 scan_static_bus for Root Device done
8993 11:33:10.809287 scan_bus: bus Root Device finished in 8 msecs
8994 11:33:10.809373 done
8995 11:33:10.815207 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8996 11:33:10.819126 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8997 11:33:10.825171 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8998 11:33:10.828713 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8999 11:33:10.832332 Allocating resources...
9000 11:33:10.835488 Reading resources...
9001 11:33:10.839205 Root Device read_resources bus 0 link: 0
9002 11:33:10.839293 DRAM rank0 size:0x80000000,
9003 11:33:10.842469 DRAM rank1 size=0x80000000
9004 11:33:10.845423 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9005 11:33:10.849032 CPU: 00 missing read_resources
9006 11:33:10.851488 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9007 11:33:10.858711 Root Device read_resources bus 0 link: 0 done
9008 11:33:10.858806 Done reading resources.
9009 11:33:10.865098 Show resources in subtree (Root Device)...After reading.
9010 11:33:10.868649 Root Device child on link 0 CPU_CLUSTER: 0
9011 11:33:10.871454 CPU_CLUSTER: 0 child on link 0 CPU: 00
9012 11:33:10.881956 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9013 11:33:10.882049 CPU: 00
9014 11:33:10.884915 Root Device assign_resources, bus 0 link: 0
9015 11:33:10.887949 CPU_CLUSTER: 0 missing set_resources
9016 11:33:10.894655 Root Device assign_resources, bus 0 link: 0 done
9017 11:33:10.894726 Done setting resources.
9018 11:33:10.901061 Show resources in subtree (Root Device)...After assigning values.
9019 11:33:10.904660 Root Device child on link 0 CPU_CLUSTER: 0
9020 11:33:10.908147 CPU_CLUSTER: 0 child on link 0 CPU: 00
9021 11:33:10.918104 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9022 11:33:10.918173 CPU: 00
9023 11:33:10.921168 Done allocating resources.
9024 11:33:10.927783 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9025 11:33:10.927878 Enabling resources...
9026 11:33:10.927937 done.
9027 11:33:10.935140 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9028 11:33:10.935235 Initializing devices...
9029 11:33:10.937971 Root Device init
9030 11:33:10.938035 init hardware done!
9031 11:33:10.941188 0x00000018: ctrlr->caps
9032 11:33:10.944839 52.000 MHz: ctrlr->f_max
9033 11:33:10.944931 0.400 MHz: ctrlr->f_min
9034 11:33:10.947940 0x40ff8080: ctrlr->voltages
9035 11:33:10.948009 sclk: 390625
9036 11:33:10.951432 Bus Width = 1
9037 11:33:10.951519 sclk: 390625
9038 11:33:10.954171 Bus Width = 1
9039 11:33:10.954257 Early init status = 3
9040 11:33:10.960955 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9041 11:33:10.963949 in-header: 03 fc 00 00 01 00 00 00
9042 11:33:10.968305 in-data: 00
9043 11:33:10.970881 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9044 11:33:10.976966 in-header: 03 fd 00 00 00 00 00 00
9045 11:33:10.981292 in-data:
9046 11:33:10.982940 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9047 11:33:10.988004 in-header: 03 fc 00 00 01 00 00 00
9048 11:33:10.990858 in-data: 00
9049 11:33:10.993606 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9050 11:33:10.999822 in-header: 03 fd 00 00 00 00 00 00
9051 11:33:11.003292 in-data:
9052 11:33:11.006903 [SSUSB] Setting up USB HOST controller...
9053 11:33:11.009966 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9054 11:33:11.012651 [SSUSB] phy power-on done.
9055 11:33:11.015906 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9056 11:33:11.023435 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9057 11:33:11.026300 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9058 11:33:11.032478 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9059 11:33:11.039834 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9060 11:33:11.046615 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9061 11:33:11.053353 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9062 11:33:11.059519 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9063 11:33:11.062227 SPM: binary array size = 0x9dc
9064 11:33:11.065597 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9065 11:33:11.072904 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9066 11:33:11.079229 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9067 11:33:11.085284 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9068 11:33:11.089216 configure_display: Starting display init
9069 11:33:11.122806 anx7625_power_on_init: Init interface.
9070 11:33:11.126423 anx7625_disable_pd_protocol: Disabled PD feature.
9071 11:33:11.129850 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9072 11:33:11.157249 anx7625_start_dp_work: Secure OCM version=00
9073 11:33:11.160873 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9074 11:33:11.175541 sp_tx_get_edid_block: EDID Block = 1
9075 11:33:11.278708 Extracted contents:
9076 11:33:11.283088 header: 00 ff ff ff ff ff ff 00
9077 11:33:11.285831 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9078 11:33:11.290303 version: 01 04
9079 11:33:11.291452 basic params: 95 1f 11 78 0a
9080 11:33:11.294225 chroma info: 76 90 94 55 54 90 27 21 50 54
9081 11:33:11.298029 established: 00 00 00
9082 11:33:11.304922 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9083 11:33:11.308767 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9084 11:33:11.314491 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9085 11:33:11.321063 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9086 11:33:11.327202 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9087 11:33:11.330604 extensions: 00
9088 11:33:11.330674 checksum: fb
9089 11:33:11.330731
9090 11:33:11.333919 Manufacturer: IVO Model 57d Serial Number 0
9091 11:33:11.337302 Made week 0 of 2020
9092 11:33:11.337390 EDID version: 1.4
9093 11:33:11.341158 Digital display
9094 11:33:11.344181 6 bits per primary color channel
9095 11:33:11.344248 DisplayPort interface
9096 11:33:11.347890 Maximum image size: 31 cm x 17 cm
9097 11:33:11.350854 Gamma: 220%
9098 11:33:11.350918 Check DPMS levels
9099 11:33:11.354376 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9100 11:33:11.360911 First detailed timing is preferred timing
9101 11:33:11.360977 Established timings supported:
9102 11:33:11.364375 Standard timings supported:
9103 11:33:11.367297 Detailed timings
9104 11:33:11.370499 Hex of detail: 383680a07038204018303c0035ae10000019
9105 11:33:11.373872 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9106 11:33:11.380856 0780 0798 07c8 0820 hborder 0
9107 11:33:11.383868 0438 043b 0447 0458 vborder 0
9108 11:33:11.386861 -hsync -vsync
9109 11:33:11.386926 Did detailed timing
9110 11:33:11.393651 Hex of detail: 000000000000000000000000000000000000
9111 11:33:11.397257 Manufacturer-specified data, tag 0
9112 11:33:11.401346 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9113 11:33:11.403322 ASCII string: InfoVision
9114 11:33:11.407185 Hex of detail: 000000fe00523134304e574635205248200a
9115 11:33:11.410264 ASCII string: R140NWF5 RH
9116 11:33:11.410329 Checksum
9117 11:33:11.413713 Checksum: 0xfb (valid)
9118 11:33:11.416638 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9119 11:33:11.419993 DSI data_rate: 832800000 bps
9120 11:33:11.427302 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9121 11:33:11.429875 anx7625_parse_edid: pixelclock(138800).
9122 11:33:11.433801 hactive(1920), hsync(48), hfp(24), hbp(88)
9123 11:33:11.436722 vactive(1080), vsync(12), vfp(3), vbp(17)
9124 11:33:11.439952 anx7625_dsi_config: config dsi.
9125 11:33:11.447197 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9126 11:33:11.459849 anx7625_dsi_config: success to config DSI
9127 11:33:11.462971 anx7625_dp_start: MIPI phy setup OK.
9128 11:33:11.466875 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9129 11:33:11.469594 mtk_ddp_mode_set invalid vrefresh 60
9130 11:33:11.473058 main_disp_path_setup
9131 11:33:11.473146 ovl_layer_smi_id_en
9132 11:33:11.477996 ovl_layer_smi_id_en
9133 11:33:11.478086 ccorr_config
9134 11:33:11.478181 aal_config
9135 11:33:11.479881 gamma_config
9136 11:33:11.479943 postmask_config
9137 11:33:11.482984 dither_config
9138 11:33:11.486191 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9139 11:33:11.493375 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9140 11:33:11.496488 Root Device init finished in 555 msecs
9141 11:33:11.499583 CPU_CLUSTER: 0 init
9142 11:33:11.506226 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9143 11:33:11.509832 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9144 11:33:11.513136 APU_MBOX 0x190000b0 = 0x10001
9145 11:33:11.516415 APU_MBOX 0x190001b0 = 0x10001
9146 11:33:11.519904 APU_MBOX 0x190005b0 = 0x10001
9147 11:33:11.523849 APU_MBOX 0x190006b0 = 0x10001
9148 11:33:11.526750 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9149 11:33:11.539248 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9150 11:33:11.551530 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9151 11:33:11.557677 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9152 11:33:11.570749 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9153 11:33:11.578809 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9154 11:33:11.582139 CPU_CLUSTER: 0 init finished in 81 msecs
9155 11:33:11.585576 Devices initialized
9156 11:33:11.588974 Show all devs... After init.
9157 11:33:11.589049 Root Device: enabled 1
9158 11:33:11.591697 CPU_CLUSTER: 0: enabled 1
9159 11:33:11.595378 CPU: 00: enabled 1
9160 11:33:11.598583 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9161 11:33:11.601682 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9162 11:33:11.604894 ELOG: NV offset 0x57f000 size 0x1000
9163 11:33:11.611974 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9164 11:33:11.618700 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9165 11:33:11.621843 ELOG: Event(17) added with size 13 at 2024-07-17 11:33:11 UTC
9166 11:33:11.625370 out: cmd=0x121: 03 db 21 01 00 00 00 00
9167 11:33:11.629011 in-header: 03 b6 00 00 2c 00 00 00
9168 11:33:11.641810 in-data: 8c 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9169 11:33:11.649432 ELOG: Event(A1) added with size 10 at 2024-07-17 11:33:11 UTC
9170 11:33:11.655337 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9171 11:33:11.661755 ELOG: Event(A0) added with size 9 at 2024-07-17 11:33:11 UTC
9172 11:33:11.665484 elog_add_boot_reason: Logged dev mode boot
9173 11:33:11.668681 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9174 11:33:11.672128 Finalize devices...
9175 11:33:11.672203 Devices finalized
9176 11:33:11.678862 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9177 11:33:11.681849 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9178 11:33:11.685126 in-header: 03 07 00 00 08 00 00 00
9179 11:33:11.688303 in-data: aa e4 47 04 13 02 00 00
9180 11:33:11.692031 Chrome EC: UHEPI supported
9181 11:33:11.699095 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9182 11:33:11.702168 in-header: 03 a9 00 00 08 00 00 00
9183 11:33:11.705197 in-data: 84 60 60 08 00 00 00 00
9184 11:33:11.709186 ELOG: Event(91) added with size 10 at 2024-07-17 11:33:11 UTC
9185 11:33:11.714837 Chrome EC: clear events_b mask to 0x0000000020004000
9186 11:33:11.721909 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9187 11:33:11.725655 in-header: 03 fd 00 00 00 00 00 00
9188 11:33:11.725730 in-data:
9189 11:33:11.731978 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9190 11:33:11.735235 Writing coreboot table at 0xffe64000
9191 11:33:11.738556 0. 000000000010a000-0000000000113fff: RAMSTAGE
9192 11:33:11.741806 1. 0000000040000000-00000000400fffff: RAM
9193 11:33:11.745750 2. 0000000040100000-000000004032afff: RAMSTAGE
9194 11:33:11.748806 3. 000000004032b000-00000000545fffff: RAM
9195 11:33:11.755010 4. 0000000054600000-000000005465ffff: BL31
9196 11:33:11.759171 5. 0000000054660000-00000000ffe63fff: RAM
9197 11:33:11.761767 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9198 11:33:11.765028 7. 0000000100000000-000000013fffffff: RAM
9199 11:33:11.768538 Passing 5 GPIOs to payload:
9200 11:33:11.775502 NAME | PORT | POLARITY | VALUE
9201 11:33:11.778539 EC in RW | 0x000000aa | low | undefined
9202 11:33:11.781955 EC interrupt | 0x00000005 | low | undefined
9203 11:33:11.788484 TPM interrupt | 0x000000ab | high | undefined
9204 11:33:11.791971 SD card detect | 0x00000011 | high | undefined
9205 11:33:11.798588 speaker enable | 0x00000093 | high | undefined
9206 11:33:11.801633 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9207 11:33:11.805695 in-header: 03 f8 00 00 02 00 00 00
9208 11:33:11.805771 in-data: 03 00
9209 11:33:11.808931 ADC[4]: Raw value=668958 ID=5
9210 11:33:11.811865 ADC[3]: Raw value=212549 ID=1
9211 11:33:11.811941 RAM Code: 0x51
9212 11:33:11.815482 ADC[6]: Raw value=74778 ID=0
9213 11:33:11.818154 ADC[5]: Raw value=211444 ID=1
9214 11:33:11.818229 SKU Code: 0x1
9215 11:33:11.825158 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3b4b
9216 11:33:11.828725 coreboot table: 964 bytes.
9217 11:33:11.831784 IMD ROOT 0. 0xfffff000 0x00001000
9218 11:33:11.834953 IMD SMALL 1. 0xffffe000 0x00001000
9219 11:33:11.838483 RO MCACHE 2. 0xffffc000 0x00001104
9220 11:33:11.841547 CONSOLE 3. 0xfff7c000 0x00080000
9221 11:33:11.844890 FMAP 4. 0xfff7b000 0x00000452
9222 11:33:11.848157 TIME STAMP 5. 0xfff7a000 0x00000910
9223 11:33:11.851647 VBOOT WORK 6. 0xfff66000 0x00014000
9224 11:33:11.854603 RAMOOPS 7. 0xffe66000 0x00100000
9225 11:33:11.858576 COREBOOT 8. 0xffe64000 0x00002000
9226 11:33:11.858671 IMD small region:
9227 11:33:11.861724 IMD ROOT 0. 0xffffec00 0x00000400
9228 11:33:11.864862 VPD 1. 0xffffeb80 0x0000006c
9229 11:33:11.868719 MMC STATUS 2. 0xffffeb60 0x00000004
9230 11:33:11.874906 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9231 11:33:11.881115 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9232 11:33:11.920171 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9233 11:33:11.923906 Checking segment from ROM address 0x40100000
9234 11:33:11.926643 Checking segment from ROM address 0x4010001c
9235 11:33:11.933692 Loading segment from ROM address 0x40100000
9236 11:33:11.933792 code (compression=0)
9237 11:33:11.943297 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9238 11:33:11.950173 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9239 11:33:11.950248 it's not compressed!
9240 11:33:11.956377 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9241 11:33:11.963285 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9242 11:33:11.980436 Loading segment from ROM address 0x4010001c
9243 11:33:11.980513 Entry Point 0x80000000
9244 11:33:11.984349 Loaded segments
9245 11:33:11.987595 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9246 11:33:11.994246 Jumping to boot code at 0x80000000(0xffe64000)
9247 11:33:12.000583 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9248 11:33:12.007176 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9249 11:33:12.015011 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9250 11:33:12.018303 Checking segment from ROM address 0x40100000
9251 11:33:12.021748 Checking segment from ROM address 0x4010001c
9252 11:33:12.028384 Loading segment from ROM address 0x40100000
9253 11:33:12.028475 code (compression=1)
9254 11:33:12.035222 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9255 11:33:12.045160 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9256 11:33:12.045296 using LZMA
9257 11:33:12.053922 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9258 11:33:12.059621 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9259 11:33:12.063502 Loading segment from ROM address 0x4010001c
9260 11:33:12.063591 Entry Point 0x54601000
9261 11:33:12.066579 Loaded segments
9262 11:33:12.069833 NOTICE: MT8192 bl31_setup
9263 11:33:12.077388 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9264 11:33:12.080091 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9265 11:33:12.083439 WARNING: region 0:
9266 11:33:12.086657 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9267 11:33:12.086725 WARNING: region 1:
9268 11:33:12.093216 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9269 11:33:12.096683 WARNING: region 2:
9270 11:33:12.100394 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9271 11:33:12.103660 WARNING: region 3:
9272 11:33:12.106689 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9273 11:33:12.110008 WARNING: region 4:
9274 11:33:12.116423 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9275 11:33:12.116489 WARNING: region 5:
9276 11:33:12.120030 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9277 11:33:12.123001 WARNING: region 6:
9278 11:33:12.126319 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9279 11:33:12.129921 WARNING: region 7:
9280 11:33:12.132966 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9281 11:33:12.141075 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9282 11:33:12.144026 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9283 11:33:12.147101 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9284 11:33:12.152999 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9285 11:33:12.156204 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9286 11:33:12.163048 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9287 11:33:12.166357 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9288 11:33:12.169478 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9289 11:33:12.176213 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9290 11:33:12.179716 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9291 11:33:12.183025 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9292 11:33:12.189753 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9293 11:33:12.192668 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9294 11:33:12.199789 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9295 11:33:12.202851 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9296 11:33:12.205712 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9297 11:33:12.212527 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9298 11:33:12.216992 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9299 11:33:12.222185 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9300 11:33:12.225778 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9301 11:33:12.228896 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9302 11:33:12.236709 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9303 11:33:12.239222 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9304 11:33:12.245746 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9305 11:33:12.248664 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9306 11:33:12.252743 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9307 11:33:12.259910 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9308 11:33:12.262113 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9309 11:33:12.269057 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9310 11:33:12.272534 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9311 11:33:12.275995 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9312 11:33:12.282295 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9313 11:33:12.285391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9314 11:33:12.288264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9315 11:33:12.296316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9316 11:33:12.298677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9317 11:33:12.302231 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9318 11:33:12.305688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9319 11:33:12.312359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9320 11:33:12.315423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9321 11:33:12.318790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9322 11:33:12.321446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9323 11:33:12.328855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9324 11:33:12.331878 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9325 11:33:12.334746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9326 11:33:12.338065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9327 11:33:12.344439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9328 11:33:12.347994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9329 11:33:12.352246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9330 11:33:12.358141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9331 11:33:12.361423 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9332 11:33:12.367957 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9333 11:33:12.371360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9334 11:33:12.378062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9335 11:33:12.381565 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9336 11:33:12.384230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9337 11:33:12.391342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9338 11:33:12.394382 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9339 11:33:12.401239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9340 11:33:12.404883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9341 11:33:12.411325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9342 11:33:12.414233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9343 11:33:12.418271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9344 11:33:12.424375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9345 11:33:12.427780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9346 11:33:12.434968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9347 11:33:12.437791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9348 11:33:12.444229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9349 11:33:12.447418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9350 11:33:12.453966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9351 11:33:12.458559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9352 11:33:12.460959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9353 11:33:12.467599 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9354 11:33:12.471312 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9355 11:33:12.477359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9356 11:33:12.480371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9357 11:33:12.487136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9358 11:33:12.490911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9359 11:33:12.497036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9360 11:33:12.500490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9361 11:33:12.503658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9362 11:33:12.510282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9363 11:33:12.514130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9364 11:33:12.521574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9365 11:33:12.524196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9366 11:33:12.530042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9367 11:33:12.533491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9368 11:33:12.536946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9369 11:33:12.543821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9370 11:33:12.546830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9371 11:33:12.553661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9372 11:33:12.556707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9373 11:33:12.563700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9374 11:33:12.567154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9375 11:33:12.573206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9376 11:33:12.576414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9377 11:33:12.579832 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9378 11:33:12.587175 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9379 11:33:12.590563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9380 11:33:12.593356 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9381 11:33:12.596534 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9382 11:33:12.603038 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9383 11:33:12.606378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9384 11:33:12.613211 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9385 11:33:12.616715 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9386 11:33:12.620032 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9387 11:33:12.626826 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9388 11:33:12.629653 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9389 11:33:12.636341 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9390 11:33:12.639692 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9391 11:33:12.642866 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9392 11:33:12.650065 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9393 11:33:12.653126 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9394 11:33:12.659832 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9395 11:33:12.663116 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9396 11:33:12.666438 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9397 11:33:12.673750 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9398 11:33:12.676589 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9399 11:33:12.679386 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9400 11:33:12.682981 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9401 11:33:12.689585 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9402 11:33:12.693152 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9403 11:33:12.696553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9404 11:33:12.699272 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9405 11:33:12.705818 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9406 11:33:12.709901 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9407 11:33:12.716552 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9408 11:33:12.719351 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9409 11:33:12.726550 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9410 11:33:12.729626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9411 11:33:12.732974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9412 11:33:12.739534 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9413 11:33:12.742255 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9414 11:33:12.746160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9415 11:33:12.752494 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9416 11:33:12.755853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9417 11:33:12.762215 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9418 11:33:12.765748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9419 11:33:12.768928 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9420 11:33:12.775699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9421 11:33:12.779188 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9422 11:33:12.785348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9423 11:33:12.789770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9424 11:33:12.792168 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9425 11:33:12.798890 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9426 11:33:12.802110 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9427 11:33:12.808976 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9428 11:33:12.813247 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9429 11:33:12.815435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9430 11:33:12.822012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9431 11:33:12.825590 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9432 11:33:12.829147 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9433 11:33:12.835439 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9434 11:33:12.839507 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9435 11:33:12.845448 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9436 11:33:12.848827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9437 11:33:12.855223 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9438 11:33:12.858991 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9439 11:33:12.861980 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9440 11:33:12.868737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9441 11:33:12.872194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9442 11:33:12.875338 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9443 11:33:12.881642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9444 11:33:12.884872 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9445 11:33:12.891761 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9446 11:33:12.895371 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9447 11:33:12.899280 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9448 11:33:12.905194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9449 11:33:12.908103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9450 11:33:12.914655 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9451 11:33:12.918482 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9452 11:33:12.921993 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9453 11:33:12.928651 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9454 11:33:12.931958 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9455 11:33:12.938504 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9456 11:33:12.941895 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9457 11:33:12.944760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9458 11:33:12.951426 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9459 11:33:12.954838 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9460 11:33:12.958239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9461 11:33:12.964699 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9462 11:33:12.968171 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9463 11:33:12.974689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9464 11:33:12.977864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9465 11:33:12.982137 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9466 11:33:12.987935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9467 11:33:12.991145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9468 11:33:12.998215 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9469 11:33:13.001816 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9470 11:33:13.005377 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9471 11:33:13.011325 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9472 11:33:13.014450 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9473 11:33:13.021128 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9474 11:33:13.024846 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9475 11:33:13.030972 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9476 11:33:13.034431 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9477 11:33:13.038068 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9478 11:33:13.043979 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9479 11:33:13.047653 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9480 11:33:13.054221 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9481 11:33:13.057591 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9482 11:33:13.064135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9483 11:33:13.068479 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9484 11:33:13.070627 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9485 11:33:13.077542 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9486 11:33:13.080739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9487 11:33:13.087808 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9488 11:33:13.090499 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9489 11:33:13.094184 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9490 11:33:13.100890 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9491 11:33:13.103657 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9492 11:33:13.110208 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9493 11:33:13.113679 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9494 11:33:13.120593 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9495 11:33:13.124950 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9496 11:33:13.127514 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9497 11:33:13.133913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9498 11:33:13.137527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9499 11:33:13.143893 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9500 11:33:13.147557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9501 11:33:13.150555 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9502 11:33:13.157289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9503 11:33:13.160937 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9504 11:33:13.167587 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9505 11:33:13.171374 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9506 11:33:13.173864 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9507 11:33:13.180247 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9508 11:33:13.183441 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9509 11:33:13.191109 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9510 11:33:13.194322 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9511 11:33:13.197608 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9512 11:33:13.200490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9513 11:33:13.206928 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9514 11:33:13.210774 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9515 11:33:13.213431 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9516 11:33:13.220794 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9517 11:33:13.223288 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9518 11:33:13.226928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9519 11:33:13.233125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9520 11:33:13.237090 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9521 11:33:13.240566 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9522 11:33:13.246544 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9523 11:33:13.250023 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9524 11:33:13.253696 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9525 11:33:13.260117 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9526 11:33:13.263278 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9527 11:33:13.271458 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9528 11:33:13.274170 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9529 11:33:13.277197 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9530 11:33:13.283244 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9531 11:33:13.286278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9532 11:33:13.293187 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9533 11:33:13.296315 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9534 11:33:13.300668 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9535 11:33:13.306729 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9536 11:33:13.309957 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9537 11:33:13.313084 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9538 11:33:13.320101 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9539 11:33:13.322975 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9540 11:33:13.326303 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9541 11:33:13.333461 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9542 11:33:13.336124 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9543 11:33:13.342832 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9544 11:33:13.346519 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9545 11:33:13.349500 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9546 11:33:13.356500 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9547 11:33:13.359670 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9548 11:33:13.362994 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9549 11:33:13.369920 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9550 11:33:13.372811 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9551 11:33:13.376756 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9552 11:33:13.380288 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9553 11:33:13.383366 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9554 11:33:13.390062 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9555 11:33:13.392951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9556 11:33:13.396138 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9557 11:33:13.399953 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9558 11:33:13.406094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9559 11:33:13.409427 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9560 11:33:13.412431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9561 11:33:13.419463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9562 11:33:13.422350 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9563 11:33:13.425721 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9564 11:33:13.432538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9565 11:33:13.435659 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9566 11:33:13.442401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9567 11:33:13.445974 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9568 11:33:13.449338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9569 11:33:13.456463 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9570 11:33:13.459219 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9571 11:33:13.465690 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9572 11:33:13.469309 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9573 11:33:13.472027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9574 11:33:13.478573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9575 11:33:13.481904 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9576 11:33:13.488527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9577 11:33:13.492020 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9578 11:33:13.495076 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9579 11:33:13.501905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9580 11:33:13.505043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9581 11:33:13.511879 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9582 11:33:13.515005 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9583 11:33:13.522044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9584 11:33:13.525335 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9585 11:33:13.528100 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9586 11:33:13.534920 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9587 11:33:13.538623 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9588 11:33:13.545141 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9589 11:33:13.548971 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9590 11:33:13.556380 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9591 11:33:13.558413 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9592 11:33:13.561724 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9593 11:33:13.568186 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9594 11:33:13.571253 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9595 11:33:13.574768 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9596 11:33:13.580932 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9597 11:33:13.584439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9598 11:33:13.591852 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9599 11:33:13.594489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9600 11:33:13.601025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9601 11:33:13.604398 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9602 11:33:13.607920 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9603 11:33:13.614252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9604 11:33:13.617975 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9605 11:33:13.624199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9606 11:33:13.627423 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9607 11:33:13.634771 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9608 11:33:13.637417 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9609 11:33:13.640999 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9610 11:33:13.647129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9611 11:33:13.651457 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9612 11:33:13.657771 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9613 11:33:13.660820 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9614 11:33:13.663808 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9615 11:33:13.670734 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9616 11:33:13.673690 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9617 11:33:13.680935 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9618 11:33:13.684004 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9619 11:33:13.686959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9620 11:33:13.693570 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9621 11:33:13.697324 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9622 11:33:13.704769 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9623 11:33:13.708023 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9624 11:33:13.713443 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9625 11:33:13.718074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9626 11:33:13.720189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9627 11:33:13.726862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9628 11:33:13.730608 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9629 11:33:13.736769 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9630 11:33:13.740324 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9631 11:33:13.743577 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9632 11:33:13.750070 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9633 11:33:13.753925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9634 11:33:13.760084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9635 11:33:13.763273 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9636 11:33:13.767597 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9637 11:33:13.773212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9638 11:33:13.776419 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9639 11:33:13.784343 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9640 11:33:13.786674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9641 11:33:13.793185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9642 11:33:13.796444 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9643 11:33:13.803352 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9644 11:33:13.806886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9645 11:33:13.809786 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9646 11:33:13.816320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9647 11:33:13.819613 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9648 11:33:13.826145 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9649 11:33:13.829422 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9650 11:33:13.835817 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9651 11:33:13.839373 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9652 11:33:13.846382 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9653 11:33:13.849386 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9654 11:33:13.852655 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9655 11:33:13.859574 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9656 11:33:13.862602 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9657 11:33:13.868949 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9658 11:33:13.872451 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9659 11:33:13.880432 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9660 11:33:13.882215 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9661 11:33:13.885749 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9662 11:33:13.892867 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9663 11:33:13.895793 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9664 11:33:13.902356 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9665 11:33:13.905745 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9666 11:33:13.912743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9667 11:33:13.915658 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9668 11:33:13.919903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9669 11:33:13.926308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9670 11:33:13.928776 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9671 11:33:13.935834 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9672 11:33:13.939170 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9673 11:33:13.946774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9674 11:33:13.949039 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9675 11:33:13.952365 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9676 11:33:13.958708 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9677 11:33:13.962195 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9678 11:33:13.968747 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9679 11:33:13.972375 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9680 11:33:13.979079 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9681 11:33:13.982742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9682 11:33:13.989470 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9683 11:33:13.991896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9684 11:33:13.995341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9685 11:33:14.002105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9686 11:33:14.005591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9687 11:33:14.011673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9688 11:33:14.015172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9689 11:33:14.022021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9690 11:33:14.026369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9691 11:33:14.031905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9692 11:33:14.036239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9693 11:33:14.042785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9694 11:33:14.045017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9695 11:33:14.051404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9696 11:33:14.055000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9697 11:33:14.061760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9698 11:33:14.064924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9699 11:33:14.071922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9700 11:33:14.074989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9701 11:33:14.078159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9702 11:33:14.084792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9703 11:33:14.088125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9704 11:33:14.094497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9705 11:33:14.098185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9706 11:33:14.104875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9707 11:33:14.112079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9708 11:33:14.114395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9709 11:33:14.121388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9710 11:33:14.124316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9711 11:33:14.131346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9712 11:33:14.134622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9713 11:33:14.140816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9714 11:33:14.144768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9715 11:33:14.148079 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9716 11:33:14.151068 INFO: [APUAPC] vio 0
9717 11:33:14.155436 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9718 11:33:14.161473 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9719 11:33:14.164732 INFO: [APUAPC] D0_APC_0: 0x400510
9720 11:33:14.168267 INFO: [APUAPC] D0_APC_1: 0x0
9721 11:33:14.170998 INFO: [APUAPC] D0_APC_2: 0x1540
9722 11:33:14.171066 INFO: [APUAPC] D0_APC_3: 0x0
9723 11:33:14.174420 INFO: [APUAPC] D1_APC_0: 0xffffffff
9724 11:33:14.181505 INFO: [APUAPC] D1_APC_1: 0xffffffff
9725 11:33:14.181589 INFO: [APUAPC] D1_APC_2: 0x3fffff
9726 11:33:14.184416 INFO: [APUAPC] D1_APC_3: 0x0
9727 11:33:14.187475 INFO: [APUAPC] D2_APC_0: 0xffffffff
9728 11:33:14.191432 INFO: [APUAPC] D2_APC_1: 0xffffffff
9729 11:33:14.194464 INFO: [APUAPC] D2_APC_2: 0x3fffff
9730 11:33:14.197544 INFO: [APUAPC] D2_APC_3: 0x0
9731 11:33:14.201508 INFO: [APUAPC] D3_APC_0: 0xffffffff
9732 11:33:14.204424 INFO: [APUAPC] D3_APC_1: 0xffffffff
9733 11:33:14.207807 INFO: [APUAPC] D3_APC_2: 0x3fffff
9734 11:33:14.211168 INFO: [APUAPC] D3_APC_3: 0x0
9735 11:33:14.214672 INFO: [APUAPC] D4_APC_0: 0xffffffff
9736 11:33:14.218641 INFO: [APUAPC] D4_APC_1: 0xffffffff
9737 11:33:14.220861 INFO: [APUAPC] D4_APC_2: 0x3fffff
9738 11:33:14.224369 INFO: [APUAPC] D4_APC_3: 0x0
9739 11:33:14.227390 INFO: [APUAPC] D5_APC_0: 0xffffffff
9740 11:33:14.230908 INFO: [APUAPC] D5_APC_1: 0xffffffff
9741 11:33:14.234504 INFO: [APUAPC] D5_APC_2: 0x3fffff
9742 11:33:14.237826 INFO: [APUAPC] D5_APC_3: 0x0
9743 11:33:14.241011 INFO: [APUAPC] D6_APC_0: 0xffffffff
9744 11:33:14.244402 INFO: [APUAPC] D6_APC_1: 0xffffffff
9745 11:33:14.247276 INFO: [APUAPC] D6_APC_2: 0x3fffff
9746 11:33:14.251363 INFO: [APUAPC] D6_APC_3: 0x0
9747 11:33:14.254506 INFO: [APUAPC] D7_APC_0: 0xffffffff
9748 11:33:14.257361 INFO: [APUAPC] D7_APC_1: 0xffffffff
9749 11:33:14.261342 INFO: [APUAPC] D7_APC_2: 0x3fffff
9750 11:33:14.265412 INFO: [APUAPC] D7_APC_3: 0x0
9751 11:33:14.268387 INFO: [APUAPC] D8_APC_0: 0xffffffff
9752 11:33:14.271536 INFO: [APUAPC] D8_APC_1: 0xffffffff
9753 11:33:14.274419 INFO: [APUAPC] D8_APC_2: 0x3fffff
9754 11:33:14.277809 INFO: [APUAPC] D8_APC_3: 0x0
9755 11:33:14.280868 INFO: [APUAPC] D9_APC_0: 0xffffffff
9756 11:33:14.284159 INFO: [APUAPC] D9_APC_1: 0xffffffff
9757 11:33:14.287406 INFO: [APUAPC] D9_APC_2: 0x3fffff
9758 11:33:14.290602 INFO: [APUAPC] D9_APC_3: 0x0
9759 11:33:14.294311 INFO: [APUAPC] D10_APC_0: 0xffffffff
9760 11:33:14.297462 INFO: [APUAPC] D10_APC_1: 0xffffffff
9761 11:33:14.300544 INFO: [APUAPC] D10_APC_2: 0x3fffff
9762 11:33:14.303964 INFO: [APUAPC] D10_APC_3: 0x0
9763 11:33:14.307896 INFO: [APUAPC] D11_APC_0: 0xffffffff
9764 11:33:14.310369 INFO: [APUAPC] D11_APC_1: 0xffffffff
9765 11:33:14.313741 INFO: [APUAPC] D11_APC_2: 0x3fffff
9766 11:33:14.318010 INFO: [APUAPC] D11_APC_3: 0x0
9767 11:33:14.320394 INFO: [APUAPC] D12_APC_0: 0xffffffff
9768 11:33:14.324297 INFO: [APUAPC] D12_APC_1: 0xffffffff
9769 11:33:14.327780 INFO: [APUAPC] D12_APC_2: 0x3fffff
9770 11:33:14.330234 INFO: [APUAPC] D12_APC_3: 0x0
9771 11:33:14.333929 INFO: [APUAPC] D13_APC_0: 0xffffffff
9772 11:33:14.337186 INFO: [APUAPC] D13_APC_1: 0xffffffff
9773 11:33:14.340685 INFO: [APUAPC] D13_APC_2: 0x3fffff
9774 11:33:14.343742 INFO: [APUAPC] D13_APC_3: 0x0
9775 11:33:14.347118 INFO: [APUAPC] D14_APC_0: 0xffffffff
9776 11:33:14.350252 INFO: [APUAPC] D14_APC_1: 0xffffffff
9777 11:33:14.354631 INFO: [APUAPC] D14_APC_2: 0x3fffff
9778 11:33:14.357130 INFO: [APUAPC] D14_APC_3: 0x0
9779 11:33:14.360591 INFO: [APUAPC] D15_APC_0: 0xffffffff
9780 11:33:14.363838 INFO: [APUAPC] D15_APC_1: 0xffffffff
9781 11:33:14.367283 INFO: [APUAPC] D15_APC_2: 0x3fffff
9782 11:33:14.370249 INFO: [APUAPC] D15_APC_3: 0x0
9783 11:33:14.374212 INFO: [APUAPC] APC_CON: 0x4
9784 11:33:14.377371 INFO: [NOCDAPC] D0_APC_0: 0x0
9785 11:33:14.377435 INFO: [NOCDAPC] D0_APC_1: 0x0
9786 11:33:14.380274 INFO: [NOCDAPC] D1_APC_0: 0x0
9787 11:33:14.383808 INFO: [NOCDAPC] D1_APC_1: 0xfff
9788 11:33:14.387264 INFO: [NOCDAPC] D2_APC_0: 0x0
9789 11:33:14.390326 INFO: [NOCDAPC] D2_APC_1: 0xfff
9790 11:33:14.393775 INFO: [NOCDAPC] D3_APC_0: 0x0
9791 11:33:14.396995 INFO: [NOCDAPC] D3_APC_1: 0xfff
9792 11:33:14.400423 INFO: [NOCDAPC] D4_APC_0: 0x0
9793 11:33:14.403799 INFO: [NOCDAPC] D4_APC_1: 0xfff
9794 11:33:14.407360 INFO: [NOCDAPC] D5_APC_0: 0x0
9795 11:33:14.407435 INFO: [NOCDAPC] D5_APC_1: 0xfff
9796 11:33:14.410942 INFO: [NOCDAPC] D6_APC_0: 0x0
9797 11:33:14.413422 INFO: [NOCDAPC] D6_APC_1: 0xfff
9798 11:33:14.417072 INFO: [NOCDAPC] D7_APC_0: 0x0
9799 11:33:14.420552 INFO: [NOCDAPC] D7_APC_1: 0xfff
9800 11:33:14.423669 INFO: [NOCDAPC] D8_APC_0: 0x0
9801 11:33:14.427500 INFO: [NOCDAPC] D8_APC_1: 0xfff
9802 11:33:14.430502 INFO: [NOCDAPC] D9_APC_0: 0x0
9803 11:33:14.433681 INFO: [NOCDAPC] D9_APC_1: 0xfff
9804 11:33:14.437107 INFO: [NOCDAPC] D10_APC_0: 0x0
9805 11:33:14.440628 INFO: [NOCDAPC] D10_APC_1: 0xfff
9806 11:33:14.440704 INFO: [NOCDAPC] D11_APC_0: 0x0
9807 11:33:14.443301 INFO: [NOCDAPC] D11_APC_1: 0xfff
9808 11:33:14.447010 INFO: [NOCDAPC] D12_APC_0: 0x0
9809 11:33:14.450635 INFO: [NOCDAPC] D12_APC_1: 0xfff
9810 11:33:14.454067 INFO: [NOCDAPC] D13_APC_0: 0x0
9811 11:33:14.457460 INFO: [NOCDAPC] D13_APC_1: 0xfff
9812 11:33:14.460309 INFO: [NOCDAPC] D14_APC_0: 0x0
9813 11:33:14.463307 INFO: [NOCDAPC] D14_APC_1: 0xfff
9814 11:33:14.466851 INFO: [NOCDAPC] D15_APC_0: 0x0
9815 11:33:14.470683 INFO: [NOCDAPC] D15_APC_1: 0xfff
9816 11:33:14.473443 INFO: [NOCDAPC] APC_CON: 0x4
9817 11:33:14.477303 INFO: [APUAPC] set_apusys_apc done
9818 11:33:14.480149 INFO: [DEVAPC] devapc_init done
9819 11:33:14.483969 INFO: GICv3 without legacy support detected.
9820 11:33:14.486740 INFO: ARM GICv3 driver initialized in EL3
9821 11:33:14.490379 INFO: Maximum SPI INTID supported: 639
9822 11:33:14.493665 INFO: BL31: Initializing runtime services
9823 11:33:14.500289 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9824 11:33:14.503630 INFO: SPM: enable CPC mode
9825 11:33:14.510090 INFO: mcdi ready for mcusys-off-idle and system suspend
9826 11:33:14.513259 INFO: BL31: Preparing for EL3 exit to normal world
9827 11:33:14.516458 INFO: Entry point address = 0x80000000
9828 11:33:14.519694 INFO: SPSR = 0x8
9829 11:33:14.524661
9830 11:33:14.524737
9831 11:33:14.524795
9832 11:33:14.528055 Starting depthcharge on Spherion...
9833 11:33:14.528131
9834 11:33:14.528189 Wipe memory regions:
9835 11:33:14.528243
9836 11:33:14.528873 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9837 11:33:14.528963 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9838 11:33:14.529038 Setting prompt string to ['asurada:']
9839 11:33:14.529102 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9840 11:33:14.531235 [0x00000040000000, 0x00000054600000)
9841 11:33:14.653566
9842 11:33:14.653674 [0x00000054660000, 0x00000080000000)
9843 11:33:14.914476
9844 11:33:14.914587 [0x000000821a7280, 0x000000ffe64000)
9845 11:33:15.659334
9846 11:33:15.659955 [0x00000100000000, 0x00000140000000)
9847 11:33:16.040518
9848 11:33:16.044239 Initializing XHCI USB controller at 0x11200000.
9849 11:33:17.082162
9850 11:33:17.084730 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9851 11:33:17.084807
9852 11:33:17.084866
9853 11:33:17.085131 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9854 11:33:17.085207 Sending line: 'tftpboot 192.168.201.1 14864597/tftp-deploy-m32fafkl/kernel/image.itb 14864597/tftp-deploy-m32fafkl/kernel/cmdline '
9856 11:33:17.185632 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9857 11:33:17.185712 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:19)
9858 11:33:17.190498 asurada: tftpboot 192.168.201.1 14864597/tftp-deploy-m32fafkl/kernel/image.itbtp-deploy-m32fafkl/kernel/cmdline
9859 11:33:17.190588
9860 11:33:17.190649 Waiting for link
9861 11:33:17.348973
9862 11:33:17.349103 R8152: Initializing
9863 11:33:17.349195
9864 11:33:17.352078 Version 9 (ocp_data = 6010)
9865 11:33:17.352145
9866 11:33:17.354929 R8152: Done initializing
9867 11:33:17.354994
9868 11:33:17.355049 Adding net device
9869 11:33:19.421470
9870 11:33:19.421592 done.
9871 11:33:19.421654
9872 11:33:19.421710 MAC: 00:e0:4c:68:03:bd
9873 11:33:19.421779
9874 11:33:19.425142 Sending DHCP discover... done.
9875 11:33:19.425210
9876 11:33:19.428312 Waiting for reply... done.
9877 11:33:19.428401
9878 11:33:19.431152 Sending DHCP request... done.
9879 11:33:19.431241
9880 11:33:19.431325 Waiting for reply... done.
9881 11:33:19.431409
9882 11:33:19.435107 My ip is 192.168.201.16
9883 11:33:19.435193
9884 11:33:19.437870 The DHCP server ip is 192.168.201.1
9885 11:33:19.437957
9886 11:33:19.442313 TFTP server IP predefined by user: 192.168.201.1
9887 11:33:19.442379
9888 11:33:19.448173 Bootfile predefined by user: 14864597/tftp-deploy-m32fafkl/kernel/image.itb
9889 11:33:19.448239
9890 11:33:19.451181 Sending tftp read request... done.
9891 11:33:19.451243
9892 11:33:19.454326 Waiting for the transfer...
9893 11:33:19.454393
9894 11:33:19.718801 00000000 ################################################################
9895 11:33:19.718917
9896 11:33:19.970876 00080000 ################################################################
9897 11:33:19.971013
9898 11:33:20.220903 00100000 ################################################################
9899 11:33:20.221023
9900 11:33:20.480633 00180000 ################################################################
9901 11:33:20.480762
9902 11:33:20.741686 00200000 ################################################################
9903 11:33:20.741808
9904 11:33:20.993884 00280000 ################################################################
9905 11:33:20.994004
9906 11:33:21.245422 00300000 ################################################################
9907 11:33:21.245540
9908 11:33:21.499961 00380000 ################################################################
9909 11:33:21.500083
9910 11:33:21.786591 00400000 ################################################################
9911 11:33:21.786714
9912 11:33:22.071895 00480000 ################################################################
9913 11:33:22.072017
9914 11:33:22.323074 00500000 ################################################################
9915 11:33:22.323197
9916 11:33:22.574266 00580000 ################################################################
9917 11:33:22.574386
9918 11:33:22.830381 00600000 ################################################################
9919 11:33:22.830527
9920 11:33:23.083206 00680000 ################################################################
9921 11:33:23.083349
9922 11:33:23.338538 00700000 ################################################################
9923 11:33:23.338656
9924 11:33:23.599672 00780000 ################################################################
9925 11:33:23.599785
9926 11:33:23.873596 00800000 ################################################################
9927 11:33:23.873743
9928 11:33:24.155145 00880000 ################################################################
9929 11:33:24.155263
9930 11:33:24.442803 00900000 ################################################################
9931 11:33:24.442918
9932 11:33:24.711624 00980000 ################################################################
9933 11:33:24.711741
9934 11:33:24.973035 00a00000 ################################################################
9935 11:33:24.973154
9936 11:33:25.236114 00a80000 ################################################################
9937 11:33:25.236228
9938 11:33:25.516475 00b00000 ################################################################
9939 11:33:25.516592
9940 11:33:25.797622 00b80000 ################################################################
9941 11:33:25.797747
9942 11:33:26.071591 00c00000 ################################################################
9943 11:33:26.071715
9944 11:33:26.332519 00c80000 ################################################################
9945 11:33:26.332643
9946 11:33:26.617826 00d00000 ################################################################
9947 11:33:26.617947
9948 11:33:26.897142 00d80000 ################################################################
9949 11:33:26.897272
9950 11:33:27.174274 00e00000 ################################################################
9951 11:33:27.174392
9952 11:33:27.457558 00e80000 ################################################################
9953 11:33:27.457709
9954 11:33:27.746886 00f00000 ################################################################
9955 11:33:27.747008
9956 11:33:28.041698 00f80000 ################################################################
9957 11:33:28.041824
9958 11:33:28.332484 01000000 ################################################################
9959 11:33:28.332644
9960 11:33:28.600354 01080000 ################################################################
9961 11:33:28.600505
9962 11:33:28.892600 01100000 ################################################################
9963 11:33:28.892721
9964 11:33:29.186021 01180000 ################################################################
9965 11:33:29.186142
9966 11:33:29.484219 01200000 ################################################################
9967 11:33:29.484341
9968 11:33:29.745335 01280000 ################################################################
9969 11:33:29.745457
9970 11:33:29.995796 01300000 ################################################################
9971 11:33:29.995915
9972 11:33:30.260983 01380000 ################################################################
9973 11:33:30.261104
9974 11:33:30.512676 01400000 ################################################################
9975 11:33:30.512794
9976 11:33:30.765353 01480000 ################################################################
9977 11:33:30.765476
9978 11:33:31.016430 01500000 ################################################################
9979 11:33:31.016546
9980 11:33:31.277895 01580000 ################################################################
9981 11:33:31.278001
9982 11:33:31.541779 01600000 ################################################################
9983 11:33:31.541906
9984 11:33:31.797384 01680000 ################################################################
9985 11:33:31.797493
9986 11:33:32.052854 01700000 ################################################################
9987 11:33:32.052969
9988 11:33:32.304478 01780000 ################################################################
9989 11:33:32.304589
9990 11:33:32.554630 01800000 ################################################################
9991 11:33:32.554740
9992 11:33:32.804849 01880000 ################################################################
9993 11:33:32.804959
9994 11:33:33.057385 01900000 ################################################################
9995 11:33:33.057509
9996 11:33:33.307541 01980000 ################################################################
9997 11:33:33.307685
9998 11:33:33.558614 01a00000 ################################################################
9999 11:33:33.558730
10000 11:33:33.808577 01a80000 ################################################################
10001 11:33:33.808716
10002 11:33:34.061093 01b00000 ################################################################
10003 11:33:34.061259
10004 11:33:34.312026 01b80000 ################################################################
10005 11:33:34.312142
10006 11:33:34.575871 01c00000 ################################################################
10007 11:33:34.575983
10008 11:33:34.828748 01c80000 ################################################################
10009 11:33:34.828883
10010 11:33:35.079281 01d00000 ################################################################
10011 11:33:35.079409
10012 11:33:35.330953 01d80000 ################################################################
10013 11:33:35.331074
10014 11:33:35.535464 01e00000 ##################################################### done.
10015 11:33:35.535584
10016 11:33:35.538964 The bootfile was 31887462 bytes long.
10017 11:33:35.539046
10018 11:33:35.541919 Sending tftp read request... done.
10019 11:33:35.542007
10020 11:33:35.545936 Waiting for the transfer...
10021 11:33:35.546038
10022 11:33:35.546111 00000000 # done.
10023 11:33:35.549134
10024 11:33:35.555685 Command line loaded dynamically from TFTP file: 14864597/tftp-deploy-m32fafkl/kernel/cmdline
10025 11:33:35.555857
10026 11:33:35.578878 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10027 11:33:35.579144
10028 11:33:35.579301 Loading FIT.
10029 11:33:35.579444
10030 11:33:35.581854 Image ramdisk-1 has 18719884 bytes.
10031 11:33:35.582075
10032 11:33:35.585436 Image fdt-1 has 47258 bytes.
10033 11:33:35.585659
10034 11:33:35.588945 Image kernel-1 has 13118294 bytes.
10035 11:33:35.589333
10036 11:33:35.595773 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10037 11:33:35.596232
10038 11:33:35.615645 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10039 11:33:35.616167
10040 11:33:35.618415 Choosing best match conf-1 for compat google,spherion-rev3.
10041 11:33:35.623336
10042 11:33:35.628480 Connected to device vid:did:rid of 1ae0:0028:00
10043 11:33:35.635024
10044 11:33:35.638713 tpm_get_response: command 0x17b, return code 0x0
10045 11:33:35.639218
10046 11:33:35.641946 ec_init: CrosEC protocol v3 supported (256, 248)
10047 11:33:35.645835
10048 11:33:35.649589 tpm_cleanup: add release locality here.
10049 11:33:35.650109
10050 11:33:35.650442 Shutting down all USB controllers.
10051 11:33:35.652921
10052 11:33:35.653402 Removing current net device
10053 11:33:35.653798
10054 11:33:35.659379 Exiting depthcharge with code 4 at timestamp: 49455152
10055 11:33:35.659978
10056 11:33:35.662763 LZMA decompressing kernel-1 to 0x821a6718
10057 11:33:35.663269
10058 11:33:35.666073 LZMA decompressing kernel-1 to 0x40000000
10059 11:33:37.279709
10060 11:33:37.280222 jumping to kernel
10061 11:33:37.282061 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10062 11:33:37.282610 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10063 11:33:37.282997 Setting prompt string to ['Linux version [0-9]']
10064 11:33:37.283338 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 11:33:37.283708 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10066 11:33:37.330140
10067 11:33:37.333864 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10068 11:33:37.336892 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10069 11:33:37.337490 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10070 11:33:37.337873 Setting prompt string to []
10071 11:33:37.338261 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10072 11:33:37.338627 Using line separator: #'\n'#
10073 11:33:37.338932 No login prompt set.
10074 11:33:37.339249 Parsing kernel messages
10075 11:33:37.339537 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10076 11:33:37.340057 [login-action] Waiting for messages, (timeout 00:03:58)
10077 11:33:37.340383 Waiting using forced prompt support (timeout 00:01:59)
10078 11:33:37.356132 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10079 11:33:37.360110 [ 0.000000] random: crng init done
10080 11:33:37.362320 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10081 11:33:37.365639 [ 0.000000] efi: UEFI not found.
10082 11:33:37.376184 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10083 11:33:37.382468 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10084 11:33:37.392134 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10085 11:33:37.402002 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10086 11:33:37.408640 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10087 11:33:37.412602 [ 0.000000] printk: bootconsole [mtk8250] enabled
10088 11:33:37.420684 [ 0.000000] NUMA: No NUMA configuration found
10089 11:33:37.427457 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10090 11:33:37.433354 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10091 11:33:37.433844 [ 0.000000] Zone ranges:
10092 11:33:37.441185 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10093 11:33:37.443237 [ 0.000000] DMA32 empty
10094 11:33:37.450295 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10095 11:33:37.453813 [ 0.000000] Movable zone start for each node
10096 11:33:37.457148 [ 0.000000] Early memory node ranges
10097 11:33:37.463253 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10098 11:33:37.469777 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10099 11:33:37.476318 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10100 11:33:37.482930 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10101 11:33:37.489987 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10102 11:33:37.496296 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10103 11:33:37.527359 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10104 11:33:37.534109 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10105 11:33:37.540691 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10106 11:33:37.544810 [ 0.000000] psci: probing for conduit method from DT.
10107 11:33:37.551402 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10108 11:33:37.554695 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10109 11:33:37.560281 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10110 11:33:37.563589 [ 0.000000] psci: SMC Calling Convention v1.2
10111 11:33:37.571061 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10112 11:33:37.573961 [ 0.000000] Detected VIPT I-cache on CPU0
10113 11:33:37.580833 [ 0.000000] CPU features: detected: GIC system register CPU interface
10114 11:33:37.587407 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10115 11:33:37.593218 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10116 11:33:37.600557 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10117 11:33:37.610127 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10118 11:33:37.616993 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10119 11:33:37.621207 [ 0.000000] alternatives: applying boot alternatives
10120 11:33:37.626561 [ 0.000000] Fallback order for Node 0: 0
10121 11:33:37.633143 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10122 11:33:37.636798 [ 0.000000] Policy zone: Normal
10123 11:33:37.659895 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10124 11:33:37.669540 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10125 11:33:37.680030 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10126 11:33:37.685627 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10127 11:33:37.696534 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10128 11:33:37.698985 <6>[ 0.000000] software IO TLB: area num 8.
10129 11:33:37.754499 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10130 11:33:37.834838 <6>[ 0.000000] Memory: 3831368K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 327096K reserved, 32768K cma-reserved)
10131 11:33:37.842222 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10132 11:33:37.848358 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10133 11:33:37.851535 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10134 11:33:37.857913 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10135 11:33:37.864768 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10136 11:33:37.867708 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10137 11:33:37.878162 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10138 11:33:37.884391 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10139 11:33:37.891769 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10140 11:33:37.898148 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10141 11:33:37.901862 <6>[ 0.000000] GICv3: 608 SPIs implemented
10142 11:33:37.904569 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10143 11:33:37.910976 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10144 11:33:37.914879 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10145 11:33:37.921397 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10146 11:33:37.935305 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10147 11:33:37.947247 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10148 11:33:37.954162 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10149 11:33:37.961954 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10150 11:33:37.975202 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10151 11:33:37.981256 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10152 11:33:37.987881 <6>[ 0.009226] Console: colour dummy device 80x25
10153 11:33:37.997530 <6>[ 0.013985] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10154 11:33:38.004540 <6>[ 0.024427] pid_max: default: 32768 minimum: 301
10155 11:33:38.008617 <6>[ 0.029299] LSM: Security Framework initializing
10156 11:33:38.014405 <6>[ 0.034239] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10157 11:33:38.024010 <6>[ 0.041845] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10158 11:33:38.030829 <6>[ 0.051121] cblist_init_generic: Setting adjustable number of callback queues.
10159 11:33:38.037922 <6>[ 0.058562] cblist_init_generic: Setting shift to 3 and lim to 1.
10160 11:33:38.047663 <6>[ 0.064902] cblist_init_generic: Setting adjustable number of callback queues.
10161 11:33:38.051398 <6>[ 0.072374] cblist_init_generic: Setting shift to 3 and lim to 1.
10162 11:33:38.057779 <6>[ 0.078774] rcu: Hierarchical SRCU implementation.
10163 11:33:38.064847 <6>[ 0.083789] rcu: Max phase no-delay instances is 1000.
10164 11:33:38.070578 <6>[ 0.090815] EFI services will not be available.
10165 11:33:38.074714 <6>[ 0.095800] smp: Bringing up secondary CPUs ...
10166 11:33:38.082378 <6>[ 0.100878] Detected VIPT I-cache on CPU1
10167 11:33:38.088743 <6>[ 0.100948] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10168 11:33:38.095311 <6>[ 0.100978] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10169 11:33:38.098084 <6>[ 0.101318] Detected VIPT I-cache on CPU2
10170 11:33:38.108146 <6>[ 0.101371] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10171 11:33:38.114959 <6>[ 0.101388] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10172 11:33:38.119190 <6>[ 0.101651] Detected VIPT I-cache on CPU3
10173 11:33:38.124661 <6>[ 0.101698] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10174 11:33:38.131185 <6>[ 0.101713] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10175 11:33:38.138283 <6>[ 0.102019] CPU features: detected: Spectre-v4
10176 11:33:38.140860 <6>[ 0.102025] CPU features: detected: Spectre-BHB
10177 11:33:38.144502 <6>[ 0.102031] Detected PIPT I-cache on CPU4
10178 11:33:38.151264 <6>[ 0.102095] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10179 11:33:38.161568 <6>[ 0.102112] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10180 11:33:38.164264 <6>[ 0.102403] Detected PIPT I-cache on CPU5
10181 11:33:38.171077 <6>[ 0.102467] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10182 11:33:38.177469 <6>[ 0.102483] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10183 11:33:38.180593 <6>[ 0.102764] Detected PIPT I-cache on CPU6
10184 11:33:38.190608 <6>[ 0.102827] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10185 11:33:38.197711 <6>[ 0.102842] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10186 11:33:38.200798 <6>[ 0.103142] Detected PIPT I-cache on CPU7
10187 11:33:38.207313 <6>[ 0.103210] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10188 11:33:38.214091 <6>[ 0.103226] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10189 11:33:38.217262 <6>[ 0.103275] smp: Brought up 1 node, 8 CPUs
10190 11:33:38.224415 <6>[ 0.244677] SMP: Total of 8 processors activated.
10191 11:33:38.230812 <6>[ 0.249598] CPU features: detected: 32-bit EL0 Support
10192 11:33:38.237601 <6>[ 0.254994] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10193 11:33:38.243125 <6>[ 0.263794] CPU features: detected: Common not Private translations
10194 11:33:38.249810 <6>[ 0.270270] CPU features: detected: CRC32 instructions
10195 11:33:38.256565 <6>[ 0.275621] CPU features: detected: RCpc load-acquire (LDAPR)
10196 11:33:38.259654 <6>[ 0.281581] CPU features: detected: LSE atomic instructions
10197 11:33:38.266556 <6>[ 0.287363] CPU features: detected: Privileged Access Never
10198 11:33:38.273207 <6>[ 0.293178] CPU features: detected: RAS Extension Support
10199 11:33:38.280156 <6>[ 0.298821] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10200 11:33:38.282922 <6>[ 0.306038] CPU: All CPU(s) started at EL2
10201 11:33:38.289589 <6>[ 0.310355] alternatives: applying system-wide alternatives
10202 11:33:38.299167 <6>[ 0.320375] devtmpfs: initialized
10203 11:33:38.310471 <6>[ 0.328543] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10204 11:33:38.320156 <6>[ 0.338503] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10205 11:33:38.327116 <6>[ 0.346768] pinctrl core: initialized pinctrl subsystem
10206 11:33:38.330045 <6>[ 0.353649] DMI not present or invalid.
10207 11:33:38.337013 <6>[ 0.358053] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10208 11:33:38.346805 <6>[ 0.364940] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10209 11:33:38.353747 <6>[ 0.372392] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10210 11:33:38.363630 <6>[ 0.380486] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10211 11:33:38.366429 <6>[ 0.388644] audit: initializing netlink subsys (disabled)
10212 11:33:38.376477 <5>[ 0.394338] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10213 11:33:38.383404 <6>[ 0.395121] thermal_sys: Registered thermal governor 'step_wise'
10214 11:33:38.389919 <6>[ 0.402305] thermal_sys: Registered thermal governor 'power_allocator'
10215 11:33:38.393295 <6>[ 0.408563] cpuidle: using governor menu
10216 11:33:38.399696 <6>[ 0.419522] NET: Registered PF_QIPCRTR protocol family
10217 11:33:38.406409 <6>[ 0.425029] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10218 11:33:38.412632 <6>[ 0.432130] ASID allocator initialised with 32768 entries
10219 11:33:38.415926 <6>[ 0.438772] Serial: AMBA PL011 UART driver
10220 11:33:38.427988 <4>[ 0.448869] Trying to register duplicate clock ID: 134
10221 11:33:38.487596 <6>[ 0.512493] KASLR enabled
10222 11:33:38.501976 <6>[ 0.520144] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10223 11:33:38.508724 <6>[ 0.527158] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10224 11:33:38.515642 <6>[ 0.533646] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10225 11:33:38.522229 <6>[ 0.540652] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10226 11:33:38.528407 <6>[ 0.547137] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10227 11:33:38.535346 <6>[ 0.554141] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10228 11:33:38.541970 <6>[ 0.560626] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10229 11:33:38.548778 <6>[ 0.567631] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10230 11:33:38.551153 <6>[ 0.575092] ACPI: Interpreter disabled.
10231 11:33:38.560275 <6>[ 0.581585] iommu: Default domain type: Translated
10232 11:33:38.567222 <6>[ 0.586736] iommu: DMA domain TLB invalidation policy: strict mode
10233 11:33:38.571450 <5>[ 0.593387] SCSI subsystem initialized
10234 11:33:38.577515 <6>[ 0.597637] usbcore: registered new interface driver usbfs
10235 11:33:38.583758 <6>[ 0.603366] usbcore: registered new interface driver hub
10236 11:33:38.587339 <6>[ 0.608917] usbcore: registered new device driver usb
10237 11:33:38.593601 <6>[ 0.615078] pps_core: LinuxPPS API ver. 1 registered
10238 11:33:38.603393 <6>[ 0.620269] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10239 11:33:38.607031 <6>[ 0.629613] PTP clock support registered
10240 11:33:38.610173 <6>[ 0.633856] EDAC MC: Ver: 3.0.0
10241 11:33:38.617482 <6>[ 0.639091] FPGA manager framework
10242 11:33:38.624520 <6>[ 0.642768] Advanced Linux Sound Architecture Driver Initialized.
10243 11:33:38.627822 <6>[ 0.649560] vgaarb: loaded
10244 11:33:38.633978 <6>[ 0.652727] clocksource: Switched to clocksource arch_sys_counter
10245 11:33:38.637669 <5>[ 0.659179] VFS: Disk quotas dquot_6.6.0
10246 11:33:38.644799 <6>[ 0.663365] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10247 11:33:38.647218 <6>[ 0.670554] pnp: PnP ACPI: disabled
10248 11:33:38.656274 <6>[ 0.677260] NET: Registered PF_INET protocol family
10249 11:33:38.662295 <6>[ 0.682643] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10250 11:33:38.675186 <6>[ 0.692656] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10251 11:33:38.684573 <6>[ 0.701437] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10252 11:33:38.691047 <6>[ 0.709400] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10253 11:33:38.697727 <6>[ 0.717807] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10254 11:33:38.708612 <6>[ 0.726465] TCP: Hash tables configured (established 32768 bind 32768)
10255 11:33:38.715430 <6>[ 0.733326] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10256 11:33:38.721812 <6>[ 0.740343] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10257 11:33:38.728679 <6>[ 0.747864] NET: Registered PF_UNIX/PF_LOCAL protocol family
10258 11:33:38.734806 <6>[ 0.754003] RPC: Registered named UNIX socket transport module.
10259 11:33:38.738753 <6>[ 0.760154] RPC: Registered udp transport module.
10260 11:33:38.744378 <6>[ 0.765087] RPC: Registered tcp transport module.
10261 11:33:38.751574 <6>[ 0.770016] RPC: Registered tcp NFSv4.1 backchannel transport module.
10262 11:33:38.754967 <6>[ 0.776682] PCI: CLS 0 bytes, default 64
10263 11:33:38.757819 <6>[ 0.781034] Unpacking initramfs...
10264 11:33:38.768305 <6>[ 0.784740] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10265 11:33:38.774035 <6>[ 0.793376] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10266 11:33:38.780792 <6>[ 0.802189] kvm [1]: IPA Size Limit: 40 bits
10267 11:33:38.784220 <6>[ 0.806716] kvm [1]: GICv3: no GICV resource entry
10268 11:33:38.790660 <6>[ 0.811737] kvm [1]: disabling GICv2 emulation
10269 11:33:38.798914 <6>[ 0.816419] kvm [1]: GIC system register CPU interface enabled
10270 11:33:38.800597 <6>[ 0.822580] kvm [1]: vgic interrupt IRQ18
10271 11:33:38.807423 <6>[ 0.826937] kvm [1]: VHE mode initialized successfully
10272 11:33:38.810700 <5>[ 0.833571] Initialise system trusted keyrings
10273 11:33:38.817344 <6>[ 0.838374] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10274 11:33:38.826592 <6>[ 0.848278] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10275 11:33:38.833304 <5>[ 0.854648] NFS: Registering the id_resolver key type
10276 11:33:38.836737 <5>[ 0.859947] Key type id_resolver registered
10277 11:33:38.843523 <5>[ 0.864360] Key type id_legacy registered
10278 11:33:38.849788 <6>[ 0.868647] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10279 11:33:38.858187 <6>[ 0.875567] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10280 11:33:38.863370 <6>[ 0.883272] 9p: Installing v9fs 9p2000 file system support
10281 11:33:38.899357 <5>[ 0.920473] Key type asymmetric registered
10282 11:33:38.902305 <5>[ 0.924802] Asymmetric key parser 'x509' registered
10283 11:33:38.912404 <6>[ 0.929940] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10284 11:33:38.916144 <6>[ 0.937552] io scheduler mq-deadline registered
10285 11:33:38.919181 <6>[ 0.942312] io scheduler kyber registered
10286 11:33:38.938119 <6>[ 0.959980] EINJ: ACPI disabled.
10287 11:33:38.973032 <4>[ 0.986856] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10288 11:33:38.981710 <4>[ 0.997560] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10289 11:33:38.997711 <6>[ 1.019027] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10290 11:33:39.006358 <6>[ 1.027025] printk: console [ttyS0] disabled
10291 11:33:39.033345 <6>[ 1.051660] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10292 11:33:39.040263 <6>[ 1.061130] printk: console [ttyS0] enabled
10293 11:33:39.044321 <6>[ 1.061130] printk: console [ttyS0] enabled
10294 11:33:39.050671 <6>[ 1.070026] printk: bootconsole [mtk8250] disabled
10295 11:33:39.054525 <6>[ 1.070026] printk: bootconsole [mtk8250] disabled
10296 11:33:39.059875 <6>[ 1.081368] SuperH (H)SCI(F) driver initialized
10297 11:33:39.063459 <6>[ 1.086671] msm_serial: driver initialized
10298 11:33:39.078169 <6>[ 1.095844] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10299 11:33:39.087898 <6>[ 1.104403] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10300 11:33:39.094369 <6>[ 1.112949] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10301 11:33:39.105071 <6>[ 1.121577] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10302 11:33:39.114269 <6>[ 1.130290] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10303 11:33:39.121490 <6>[ 1.139004] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10304 11:33:39.130368 <6>[ 1.147546] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10305 11:33:39.137921 <6>[ 1.156362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10306 11:33:39.147683 <6>[ 1.164906] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10307 11:33:39.159531 <6>[ 1.180650] loop: module loaded
10308 11:33:39.165658 <6>[ 1.186713] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10309 11:33:39.188866 <4>[ 1.210223] mtk-pmic-keys: Failed to locate of_node [id: -1]
10310 11:33:39.196349 <6>[ 1.217288] megasas: 07.719.03.00-rc1
10311 11:33:39.205848 <6>[ 1.227120] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10312 11:33:39.215430 <6>[ 1.236118] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10313 11:33:39.231314 <6>[ 1.252997] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10314 11:33:39.288369 <6>[ 1.303015] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10315 11:33:39.553793 <6>[ 1.575220] Freeing initrd memory: 18276K
10316 11:33:39.565377 <6>[ 1.586897] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10317 11:33:39.576425 <6>[ 1.598010] tun: Universal TUN/TAP device driver, 1.6
10318 11:33:39.580183 <6>[ 1.604113] thunder_xcv, ver 1.0
10319 11:33:39.583180 <6>[ 1.607620] thunder_bgx, ver 1.0
10320 11:33:39.586151 <6>[ 1.611116] nicpf, ver 1.0
10321 11:33:39.597189 <6>[ 1.615174] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10322 11:33:39.600667 <6>[ 1.622649] hns3: Copyright (c) 2017 Huawei Corporation.
10323 11:33:39.603897 <6>[ 1.628236] hclge is initializing
10324 11:33:39.610259 <6>[ 1.631816] e1000: Intel(R) PRO/1000 Network Driver
10325 11:33:39.616947 <6>[ 1.636945] e1000: Copyright (c) 1999-2006 Intel Corporation.
10326 11:33:39.621211 <6>[ 1.642962] e1000e: Intel(R) PRO/1000 Network Driver
10327 11:33:39.627313 <6>[ 1.648178] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10328 11:33:39.634031 <6>[ 1.654364] igb: Intel(R) Gigabit Ethernet Network Driver
10329 11:33:39.640491 <6>[ 1.660014] igb: Copyright (c) 2007-2014 Intel Corporation.
10330 11:33:39.647055 <6>[ 1.665854] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10331 11:33:39.654321 <6>[ 1.672373] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10332 11:33:39.657282 <6>[ 1.678838] sky2: driver version 1.30
10333 11:33:39.664108 <6>[ 1.683806] usbcore: registered new device driver r8152-cfgselector
10334 11:33:39.670472 <6>[ 1.690341] usbcore: registered new interface driver r8152
10335 11:33:39.674020 <6>[ 1.696160] VFIO - User Level meta-driver version: 0.3
10336 11:33:39.683459 <6>[ 1.704451] usbcore: registered new interface driver usb-storage
10337 11:33:39.689570 <6>[ 1.710902] usbcore: registered new device driver onboard-usb-hub
10338 11:33:39.698663 <6>[ 1.720168] mt6397-rtc mt6359-rtc: registered as rtc0
10339 11:33:39.708457 <6>[ 1.725634] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:33:39 UTC (1721216019)
10340 11:33:39.712097 <6>[ 1.735222] i2c_dev: i2c /dev entries driver
10341 11:33:39.726129 <4>[ 1.747539] cpu cpu0: supply cpu not found, using dummy regulator
10342 11:33:39.732794 <4>[ 1.753963] cpu cpu1: supply cpu not found, using dummy regulator
10343 11:33:39.739100 <4>[ 1.760369] cpu cpu2: supply cpu not found, using dummy regulator
10344 11:33:39.745875 <4>[ 1.766765] cpu cpu3: supply cpu not found, using dummy regulator
10345 11:33:39.753699 <4>[ 1.773180] cpu cpu4: supply cpu not found, using dummy regulator
10346 11:33:39.759368 <4>[ 1.779578] cpu cpu5: supply cpu not found, using dummy regulator
10347 11:33:39.766294 <4>[ 1.785977] cpu cpu6: supply cpu not found, using dummy regulator
10348 11:33:39.772847 <4>[ 1.792380] cpu cpu7: supply cpu not found, using dummy regulator
10349 11:33:39.792519 <6>[ 1.812998] cpu cpu0: EM: created perf domain
10350 11:33:39.795042 <6>[ 1.817930] cpu cpu4: EM: created perf domain
10351 11:33:39.801963 <6>[ 1.823520] sdhci: Secure Digital Host Controller Interface driver
10352 11:33:39.809093 <6>[ 1.829953] sdhci: Copyright(c) Pierre Ossman
10353 11:33:39.816239 <6>[ 1.834879] Synopsys Designware Multimedia Card Interface Driver
10354 11:33:39.822604 <6>[ 1.841487] sdhci-pltfm: SDHCI platform and OF driver helper
10355 11:33:39.825551 <6>[ 1.841561] mmc0: CQHCI version 5.10
10356 11:33:39.831585 <6>[ 1.851714] ledtrig-cpu: registered to indicate activity on CPUs
10357 11:33:39.838124 <6>[ 1.858811] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10358 11:33:39.844858 <6>[ 1.865842] usbcore: registered new interface driver usbhid
10359 11:33:39.848312 <6>[ 1.871664] usbhid: USB HID core driver
10360 11:33:39.854971 <6>[ 1.875858] spi_master spi0: will run message pump with realtime priority
10361 11:33:39.898247 <6>[ 1.913554] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10362 11:33:39.914244 <6>[ 1.928378] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10363 11:33:39.920498 <3>[ 1.935658] mtk-msdc 11f60000.mmc: phase error: [map:0]
10364 11:33:39.926840 <3>[ 1.947279] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10365 11:33:39.933815 <3>[ 1.953200] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10366 11:33:39.936750 <3>[ 1.959555] mmc0: error -5 whilst initialising MMC card
10367 11:33:39.943851 <6>[ 1.959676] cros-ec-spi spi0.0: Chrome EC device registered
10368 11:33:39.965216 <6>[ 1.983775] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10369 11:33:39.973479 <6>[ 1.994075] NET: Registered PF_PACKET protocol family
10370 11:33:39.975455 <6>[ 1.999463] 9pnet: Installing 9P2000 support
10371 11:33:39.982845 <5>[ 2.004024] Key type dns_resolver registered
10372 11:33:39.985971 <6>[ 2.009034] registered taskstats version 1
10373 11:33:39.992535 <5>[ 2.013416] Loading compiled-in X.509 certificates
10374 11:33:40.020072 <4>[ 2.034802] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10375 11:33:40.030244 <4>[ 2.045527] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10376 11:33:40.045867 <6>[ 2.067332] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10377 11:33:40.053833 <6>[ 2.069476] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10378 11:33:40.059021 <6>[ 2.079668] mmc0: Command Queue Engine enabled
10379 11:33:40.063356 <6>[ 2.080284] xhci-mtk 11200000.usb: xHCI Host Controller
10380 11:33:40.069347 <6>[ 2.084390] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10381 11:33:40.078911 <6>[ 2.089968] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10382 11:33:40.082513 <6>[ 2.096990] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10383 11:33:40.092557 <6>[ 2.104322] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10384 11:33:40.098831 <6>[ 2.114516] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10385 11:33:40.102022 <6>[ 2.118335] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10386 11:33:40.109309 <6>[ 2.125524] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10387 11:33:40.116007 <6>[ 2.130283] xhci-mtk 11200000.usb: xHCI Host Controller
10388 11:33:40.119156 <6>[ 2.136028] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10389 11:33:40.128942 <6>[ 2.140916] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10390 11:33:40.135640 <6>[ 2.140923] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10391 11:33:40.138549 <6>[ 2.141410] hub 1-0:1.0: USB hub found
10392 11:33:40.145103 <6>[ 2.146826] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10393 11:33:40.148707 <6>[ 2.153817] hub 1-0:1.0: 1 port detected
10394 11:33:40.158590 <6>[ 2.153916] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10395 11:33:40.162224 <6>[ 2.184469] hub 2-0:1.0: USB hub found
10396 11:33:40.165434 <6>[ 2.188498] hub 2-0:1.0: 1 port detected
10397 11:33:40.174675 <6>[ 2.196185] mtk-msdc 11f70000.mmc: Got CD GPIO
10398 11:33:40.190637 <6>[ 2.208821] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10399 11:33:40.200943 <6>[ 2.217184] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10400 11:33:40.206976 <6>[ 2.225526] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10401 11:33:40.216834 <6>[ 2.233864] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10402 11:33:40.224371 <6>[ 2.242201] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10403 11:33:40.233658 <6>[ 2.250539] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10404 11:33:40.240482 <6>[ 2.258878] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10405 11:33:40.250682 <6>[ 2.267216] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10406 11:33:40.259269 <6>[ 2.275555] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10407 11:33:40.267704 <6>[ 2.283893] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10408 11:33:40.273600 <6>[ 2.292230] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10409 11:33:40.284100 <6>[ 2.300570] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10410 11:33:40.289903 <6>[ 2.308909] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10411 11:33:40.299766 <6>[ 2.317247] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10412 11:33:40.306193 <6>[ 2.325587] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10413 11:33:40.313532 <6>[ 2.334261] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10414 11:33:40.320139 <6>[ 2.341389] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10415 11:33:40.326893 <6>[ 2.348142] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10416 11:33:40.336798 <6>[ 2.354884] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10417 11:33:40.342990 <6>[ 2.361780] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10418 11:33:40.349790 <6>[ 2.368646] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10419 11:33:40.359345 <6>[ 2.377778] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10420 11:33:40.369305 <6>[ 2.386897] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10421 11:33:40.379663 <6>[ 2.396191] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10422 11:33:40.390043 <6>[ 2.405659] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10423 11:33:40.396046 <6>[ 2.415127] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10424 11:33:40.406356 <6>[ 2.424246] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10425 11:33:40.416293 <6>[ 2.433713] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10426 11:33:40.426217 <6>[ 2.442831] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10427 11:33:40.435841 <6>[ 2.452126] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10428 11:33:40.445261 <6>[ 2.462285] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10429 11:33:40.456101 <6>[ 2.473863] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10430 11:33:40.463279 <6>[ 2.485025] Trying to probe devices needed for running init ...
10431 11:33:40.473566 <3>[ 2.492099] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10432 11:33:40.547463 <6>[ 2.564995] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10433 11:33:40.700299 <6>[ 2.721695] hub 1-1:1.0: USB hub found
10434 11:33:40.703256 <6>[ 2.726101] hub 1-1:1.0: 4 ports detected
10435 11:33:40.715425 <6>[ 2.736036] hub 1-1:1.0: USB hub found
10436 11:33:40.717595 <6>[ 2.740370] hub 1-1:1.0: 4 ports detected
10437 11:33:40.826433 <6>[ 2.845109] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10438 11:33:40.852749 <6>[ 2.874807] hub 2-1:1.0: USB hub found
10439 11:33:40.856694 <6>[ 2.879315] hub 2-1:1.0: 3 ports detected
10440 11:33:40.869144 <6>[ 2.890639] hub 2-1:1.0: USB hub found
10441 11:33:40.872380 <6>[ 2.895116] hub 2-1:1.0: 3 ports detected
10442 11:33:41.038250 <6>[ 3.057033] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10443 11:33:41.172364 <6>[ 3.192801] hub 1-1.4:1.0: USB hub found
10444 11:33:41.174291 <6>[ 3.197370] hub 1-1.4:1.0: 2 ports detected
10445 11:33:41.186235 <6>[ 3.207952] hub 1-1.4:1.0: USB hub found
10446 11:33:41.189206 <6>[ 3.212555] hub 1-1.4:1.0: 2 ports detected
10447 11:33:41.251018 <6>[ 3.269243] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10448 11:33:41.359003 <6>[ 3.377678] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10449 11:33:41.394969 <4>[ 3.413461] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10450 11:33:41.405962 <4>[ 3.422556] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10451 11:33:41.449066 <6>[ 3.470703] r8152 2-1.3:1.0 eth0: v1.12.13
10452 11:33:41.486707 <6>[ 3.505042] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10453 11:33:41.679044 <6>[ 3.696889] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10454 11:33:43.051656 <6>[ 5.073611] r8152 2-1.3:1.0 eth0: carrier on
10455 11:33:45.555199 <5>[ 5.104855] Sending DHCP requests .., OK
10456 11:33:45.561521 <6>[ 7.581316] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10457 11:33:45.564435 <6>[ 7.589623] IP-Config: Complete:
10458 11:33:45.577842 <6>[ 7.593117] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10459 11:33:45.584737 <6>[ 7.603825] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10460 11:33:45.591614 <6>[ 7.612440] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10461 11:33:45.598140 <6>[ 7.612450] nameserver0=192.168.201.1
10462 11:33:45.601475 <6>[ 7.624616] clk: Disabling unused clocks
10463 11:33:45.604909 <6>[ 7.630198] ALSA device list:
10464 11:33:45.611364 <6>[ 7.633469] No soundcards found.
10465 11:33:45.618847 <6>[ 7.641105] Freeing unused kernel memory: 8512K
10466 11:33:45.622718 <6>[ 7.646053] Run /init as init process
10467 11:33:45.630959 Loading, please wait...
10468 11:33:45.660058 Starting systemd-udevd version 252.22-1~deb12u1
10469 11:33:45.889459 <6>[ 7.908329] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10470 11:33:45.896552 <6>[ 7.908799] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10471 11:33:45.906566 <4>[ 7.925504] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10472 11:33:45.916901 <6>[ 7.935471] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10473 11:33:45.923347 <4>[ 7.937718] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10474 11:33:45.930044 <6>[ 7.938116] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10475 11:33:45.939468 <6>[ 7.938141] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10476 11:33:45.949378 <6>[ 7.938146] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10477 11:33:45.953418 <6>[ 7.938178] remoteproc remoteproc0: scp is available
10478 11:33:45.959391 <6>[ 7.938261] remoteproc remoteproc0: powering up scp
10479 11:33:45.966237 <6>[ 7.938269] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10480 11:33:45.972702 <6>[ 7.938283] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10481 11:33:45.979518 <6>[ 7.943687] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10482 11:33:45.989418 <6>[ 7.983926] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10483 11:33:45.992359 <6>[ 7.984398] mc: Linux media interface: v0.10
10484 11:33:45.999486 <3>[ 7.986385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10485 11:33:46.009843 <4>[ 7.986414] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10486 11:33:46.019745 <6>[ 7.986916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10487 11:33:46.026893 <6>[ 7.986919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10488 11:33:46.034281 <6>[ 7.991667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10489 11:33:46.041144 <6>[ 7.991684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10490 11:33:46.050074 <6>[ 7.991686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10491 11:33:46.060206 <6>[ 7.991689] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10492 11:33:46.066832 <4>[ 8.005881] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10493 11:33:46.073689 <4>[ 8.005881] Fallback method does not support PEC.
10494 11:33:46.080062 <3>[ 8.008249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10495 11:33:46.086813 <6>[ 8.009468] videodev: Linux video capture interface: v2.00
10496 11:33:46.096713 <3>[ 8.033256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10497 11:33:46.103090 <3>[ 8.037404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10498 11:33:46.110217 <3>[ 8.037610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10499 11:33:46.119894 <6>[ 8.055379] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10500 11:33:46.126255 <6>[ 8.058874] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10501 11:33:46.133596 <6>[ 8.058881] pci_bus 0000:00: root bus resource [bus 00-ff]
10502 11:33:46.139643 <6>[ 8.058891] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10503 11:33:46.149851 <6>[ 8.058896] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10504 11:33:46.156745 <6>[ 8.058928] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10505 11:33:46.162460 <6>[ 8.058947] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10506 11:33:46.168937 <6>[ 8.059029] pci 0000:00:00.0: supports D1 D2
10507 11:33:46.176262 <6>[ 8.059032] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10508 11:33:46.182677 <6>[ 8.060602] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10509 11:33:46.189890 <6>[ 8.060730] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10510 11:33:46.199240 <6>[ 8.060763] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10511 11:33:46.205744 <6>[ 8.060783] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10512 11:33:46.212374 <6>[ 8.060802] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10513 11:33:46.215813 <6>[ 8.060919] pci 0000:01:00.0: supports D1 D2
10514 11:33:46.222586 <6>[ 8.060922] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10515 11:33:46.232935 <3>[ 8.061360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10516 11:33:46.239158 <3>[ 8.061363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10517 11:33:46.250123 <3>[ 8.061368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10518 11:33:46.256153 <3>[ 8.061371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10519 11:33:46.265037 <3>[ 8.061399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10520 11:33:46.272769 <6>[ 8.063458] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10521 11:33:46.278663 <6>[ 8.063466] remoteproc remoteproc0: remote processor scp is now up
10522 11:33:46.284865 <6>[ 8.063465] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10523 11:33:46.295095 <3>[ 8.066567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10524 11:33:46.302167 <6>[ 8.072811] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10525 11:33:46.312321 <3>[ 8.077036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10526 11:33:46.318558 <6>[ 8.086175] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10527 11:33:46.324402 <3>[ 8.099952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10528 11:33:46.334476 <6>[ 8.107999] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10529 11:33:46.340891 <3>[ 8.113709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10530 11:33:46.350866 <3>[ 8.113759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10531 11:33:46.361015 <6>[ 8.114517] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10532 11:33:46.371514 <6>[ 8.114804] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10533 11:33:46.378237 <6>[ 8.122530] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10534 11:33:46.384083 <3>[ 8.130585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10535 11:33:46.394316 <6>[ 8.132239] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10536 11:33:46.401375 <6>[ 8.134534] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10537 11:33:46.410924 <6>[ 8.138750] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10538 11:33:46.418229 <3>[ 8.147957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10539 11:33:46.427552 <3>[ 8.147965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10540 11:33:46.433893 <3>[ 8.147970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10541 11:33:46.443920 <3>[ 8.148000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10542 11:33:46.449815 <6>[ 8.154874] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10543 11:33:46.453402 <6>[ 8.162021] Bluetooth: Core ver 2.22
10544 11:33:46.460575 <6>[ 8.167747] pci 0000:00:00.0: PCI bridge to [bus 01]
10545 11:33:46.463464 <6>[ 8.177709] NET: Registered PF_BLUETOOTH protocol family
10546 11:33:46.473966 <6>[ 8.183878] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10547 11:33:46.479447 <6>[ 8.191344] Bluetooth: HCI device and connection manager initialized
10548 11:33:46.486157 <6>[ 8.192051] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10549 11:33:46.500890 <6>[ 8.193278] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10550 11:33:46.506708 <6>[ 8.193533] usbcore: registered new interface driver uvcvideo
10551 11:33:46.509486 <6>[ 8.197250] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10552 11:33:46.516615 <6>[ 8.202739] Bluetooth: HCI socket layer initialized
10553 11:33:46.522923 <6>[ 8.211505] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10554 11:33:46.526319 <6>[ 8.217244] Bluetooth: L2CAP socket layer initialized
10555 11:33:46.533848 <6>[ 8.217722] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10556 11:33:46.539630 <6>[ 8.225311] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10557 11:33:46.546051 <6>[ 8.232209] Bluetooth: SCO socket layer initialized
10558 11:33:46.553117 <5>[ 8.262955] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10559 11:33:46.559797 <6>[ 8.313959] usbcore: registered new interface driver btusb
10560 11:33:46.569359 <4>[ 8.315120] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10561 11:33:46.575989 <3>[ 8.315126] Bluetooth: hci0: Failed to load firmware file (-2)
10562 11:33:46.582490 <3>[ 8.315127] Bluetooth: hci0: Failed to set up firmware (-2)
10563 11:33:46.592983 <4>[ 8.315129] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10564 11:33:46.599271 <5>[ 8.334328] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10565 11:33:46.608891 <5>[ 8.626636] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10566 11:33:46.616225 <4>[ 8.635067] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10567 11:33:46.622875 <6>[ 8.643936] cfg80211: failed to load regulatory.db
10568 11:33:46.660992 <6>[ 8.680174] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10569 11:33:46.668180 <6>[ 8.687664] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10570 11:33:46.692175 <6>[ 8.714308] mt7921e 0000:01:00.0: ASIC revision: 79610010
10571 11:33:46.792857 <6>[ 8.812172] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10572 11:33:46.797196 <6>[ 8.812172]
10573 11:33:46.800317 Begin: Loading essential drivers ... done.
10574 11:33:46.803433 Begin: Running /scripts/init-premount ... done.
10575 11:33:46.809797 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10576 11:33:46.820080 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10577 11:33:46.822995 Device /sys/class/net/eth0 found
10578 11:33:46.823496 done.
10579 11:33:46.833105 Begin: Waiting up to 180 secs for any network device to become available ... done.
10580 11:33:46.874476 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10581 11:33:46.881314 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10582 11:33:46.888110 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10583 11:33:46.895096 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10584 11:33:46.900914 host : mt8192-asurada-spherion-r0-cbg-4
10585 11:33:46.907847 domain : lava-rack
10586 11:33:46.910807 rootserver: 192.168.201.1 rootpath:
10587 11:33:46.911232 filename :
10588 11:33:46.969924 done.
10589 11:33:46.977413 Begin: Running /scripts/nfs-bottom ... done.
10590 11:33:46.996710 Begin: Running /scripts/init-bottom ... done.
10591 11:33:47.062400 <6>[ 9.081822] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10592 11:33:48.316159 <6>[ 10.339123] NET: Registered PF_INET6 protocol family
10593 11:33:48.323752 <6>[ 10.346246] Segment Routing with IPv6
10594 11:33:48.327072 <6>[ 10.350225] In-situ OAM (IOAM) with IPv6
10595 11:33:48.496620 <30>[ 10.492627] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10596 11:33:48.502968 <30>[ 10.525770] systemd[1]: Detected architecture arm64.
10597 11:33:48.512197
10598 11:33:48.514918 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10599 11:33:48.515301
10600 11:33:48.539604 <30>[ 10.562434] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10601 11:33:49.593351 <30>[ 11.613007] systemd[1]: Queued start job for default target graphical.target.
10602 11:33:49.627269 <30>[ 11.646348] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10603 11:33:49.633902 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10604 11:33:49.655424 <30>[ 11.674883] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10605 11:33:49.665781 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10606 11:33:49.683045 <30>[ 11.702809] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10607 11:33:49.692876 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10608 11:33:49.711329 <30>[ 11.730464] systemd[1]: Created slice user.slice - User and Session Slice.
10609 11:33:49.717411 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10610 11:33:49.741095 <30>[ 11.757339] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10611 11:33:49.750888 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10612 11:33:49.769307 <30>[ 11.785256] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10613 11:33:49.775989 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10614 11:33:49.804046 <30>[ 11.813687] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10615 11:33:49.814063 <30>[ 11.833581] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10616 11:33:49.820645 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10617 11:33:49.838163 <30>[ 11.857200] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10618 11:33:49.844683 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10619 11:33:49.862860 <30>[ 11.881081] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10620 11:33:49.871385 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10621 11:33:49.886370 <30>[ 11.909122] systemd[1]: Reached target paths.target - Path Units.
10622 11:33:49.896318 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10623 11:33:49.914402 <30>[ 11.933472] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10624 11:33:49.920683 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10625 11:33:49.934721 <30>[ 11.957025] systemd[1]: Reached target slices.target - Slice Units.
10626 11:33:49.944170 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10627 11:33:49.958789 <30>[ 11.981508] systemd[1]: Reached target swap.target - Swaps.
10628 11:33:49.965963 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10629 11:33:49.986888 <30>[ 12.005528] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10630 11:33:49.996327 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10631 11:33:50.014032 <30>[ 12.033489] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10632 11:33:50.023927 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10633 11:33:50.045036 <30>[ 12.064352] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10634 11:33:50.054323 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10635 11:33:50.071804 <30>[ 12.090643] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10636 11:33:50.081133 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10637 11:33:50.097688 <30>[ 12.117087] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10638 11:33:50.104425 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10639 11:33:50.124563 <30>[ 12.142723] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10640 11:33:50.133602 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10641 11:33:50.153170 <30>[ 12.172248] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10642 11:33:50.162977 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10643 11:33:50.177965 <30>[ 12.197578] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10644 11:33:50.203324 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10645 11:33:50.245967 <30>[ 12.265268] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10646 11:33:50.252455 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10647 11:33:50.274099 <30>[ 12.293851] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10648 11:33:50.280421 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10649 11:33:50.345952 <30>[ 12.365467] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10650 11:33:50.351920 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10651 11:33:50.380020 <30>[ 12.393628] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10652 11:33:50.395905 <30>[ 12.415271] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10653 11:33:50.405015 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10654 11:33:50.426191 <30>[ 12.446171] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10655 11:33:50.433353 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10656 11:33:50.458094 <30>[ 12.476980] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10657 11:33:50.464782 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10658 11:33:50.486968 <30>[ 12.506741] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10659 11:33:50.497487 Starting [0;1;39mmodpr<6>[ 12.517150] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10660 11:33:50.503795 obe@drm.service[0m - Load Kernel Module drm...
10661 11:33:50.526925 <30>[ 12.546826] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10662 11:33:50.536931 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10663 11:33:50.557620 <30>[ 12.576971] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10664 11:33:50.563453 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10665 11:33:50.586654 <30>[ 12.606913] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10666 11:33:50.593237 Startin<6>[ 12.616124] fuse: init (API version 7.37)
10667 11:33:50.599868 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10668 11:33:50.654451 <30>[ 12.674036] systemd[1]: Starting systemd-journald.service - Journal Service...
10669 11:33:50.661173 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10670 11:33:50.693720 <30>[ 12.713005] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10671 11:33:50.700223 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10672 11:33:50.725710 <30>[ 12.741934] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10673 11:33:50.732620 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10674 11:33:50.758319 <30>[ 12.777594] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10675 11:33:50.768601 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10676 11:33:50.790866 <30>[ 12.810563] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10677 11:33:50.801447 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10678 11:33:50.816832 <3>[ 12.836482] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 11:33:50.832770 <30>[ 12.851926] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10680 11:33:50.838815 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10681 11:33:50.858318 <30>[ 12.877749] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10682 11:33:50.867743 <3>[ 12.878332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 11:33:50.874583 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10684 11:33:50.894513 <30>[ 12.913439] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10685 11:33:50.908446 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-<3>[ 12.924336] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 11:33:50.910625 debug.m…nt[0m - Kernel Debug File System.
10687 11:33:50.930728 <30>[ 12.950110] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10688 11:33:50.940805 <3>[ 12.954003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10689 11:33:50.947713 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10690 11:33:50.966970 <30>[ 12.985949] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10691 11:33:50.973784 <3>[ 12.989252] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 11:33:50.983474 <30>[ 12.993761] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10693 11:33:50.990164 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10694 11:33:51.004252 <3>[ 13.022968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 11:33:51.015117 <30>[ 13.034187] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10696 11:33:51.021153 <30>[ 13.042036] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10697 11:33:51.031936 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10698 11:33:51.039328 <3>[ 13.057440] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 11:33:51.050804 <30>[ 13.070215] systemd[1]: modprobe@drm.service: Deactivated successfully.
10700 11:33:51.058043 <30>[ 13.077969] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10701 11:33:51.071307 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.088664] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 11:33:51.074514 rm.service[0m - Load Kernel Module drm.
10703 11:33:51.095708 <30>[ 13.114097] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10704 11:33:51.101624 <3>[ 13.122123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 11:33:51.111765 <30>[ 13.122793] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10706 11:33:51.121385 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10707 11:33:51.134858 <3>[ 13.153260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10708 11:33:51.147983 <30>[ 13.166732] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10709 11:33:51.155702 <30>[ 13.174843] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10710 11:33:51.164234 [[0;32m OK [<3>[ 13.184216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 11:33:51.170638 0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10712 11:33:51.193626 <3>[ 13.213011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10713 11:33:51.200827 <30>[ 13.213922] systemd[1]: modprobe@loop.service: Deactivated successfully.
10714 11:33:51.217317 <4>[ 13.221818] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10715 11:33:51.224020 <3>[ 13.221821] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10716 11:33:51.233944 <3>[ 13.229728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10717 11:33:51.241059 <30>[ 13.245589] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10718 11:33:51.254217 [[0;32m OK [0m] Finished [0;1;39mmodprobe@l<3>[ 13.272662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 11:33:51.258765 oop.service[0m - Load Kernel Module loop.
10720 11:33:51.279014 <30>[ 13.297860] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10721 11:33:51.286193 <3>[ 13.302349] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10722 11:33:51.295753 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10723 11:33:51.317949 <30>[ 13.333667] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10724 11:33:51.324836 <3>[ 13.336433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10725 11:33:51.334642 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10726 11:33:51.354323 <30>[ 13.373709] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10727 11:33:51.364894 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10728 11:33:51.382003 <30>[ 13.401713] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10729 11:33:51.391775 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10730 11:33:51.410495 <30>[ 13.429726] systemd[1]: Reached target network-pre.target - Preparation for Network.
10731 11:33:51.417213 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10732 11:33:51.469731 <30>[ 13.489542] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10733 11:33:51.476576 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10734 11:33:51.503239 <30>[ 13.522068] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10735 11:33:51.509781 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10736 11:33:51.532943 <30>[ 13.549155] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10737 11:33:51.550489 <30>[ 13.562806] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10738 11:33:51.564049 <30>[ 13.583737] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10739 11:33:51.571564 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10740 11:33:51.596233 <30>[ 13.612345] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10741 11:33:51.630754 <30>[ 13.649878] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10742 11:33:51.636963 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10743 11:33:51.661265 <30>[ 13.680883] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10744 11:33:51.668920 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10745 11:33:51.697443 <30>[ 13.716539] systemd[1]: Started systemd-journald.service - Journal Service.
10746 11:33:51.703365 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10747 11:33:51.726790 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10748 11:33:51.746730 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10749 11:33:51.767059 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10750 11:33:51.786883 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10751 11:33:51.806644 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10752 11:33:51.851398 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10753 11:33:51.875163 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10754 11:33:51.912533 <46>[ 13.932299] systemd-journald[314]: Received client request to flush runtime journal.
10755 11:33:51.973616 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10756 11:33:51.990235 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10757 11:33:52.009289 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10758 11:33:52.720233 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10759 11:33:53.349676 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10760 11:33:53.403324 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10761 11:33:53.487696 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10762 11:33:53.550373 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10763 11:33:53.589090 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10764 11:33:53.898533 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10765 11:33:53.905947 <6>[ 15.929550] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10766 11:33:53.944348 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10767 11:33:54.063154 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10768 11:33:54.087140 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10769 11:33:54.110374 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10770 11:33:54.129847 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10771 11:33:54.156140 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10772 11:33:54.202008 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10773 11:33:54.231929 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10774 11:33:54.298248 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10775 11:33:54.324296 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10776 11:33:54.342576 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10777 11:33:54.382233 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10778 11:33:54.523546 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10779 11:33:54.541769 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10780 11:33:54.557648 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10781 11:33:54.573515 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10782 11:33:54.599488 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10783 11:33:54.621369 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10784 11:33:54.638697 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10785 11:33:54.658103 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10786 11:33:54.677946 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10787 11:33:54.694095 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10788 11:33:54.715665 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10789 11:33:54.733177 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10790 11:33:54.750115 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10791 11:33:54.786562 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10792 11:33:54.876714 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10793 11:33:54.966745 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10794 11:33:54.993254 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10795 11:33:55.123066 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10796 11:33:55.166951 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10797 11:33:55.191958 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10798 11:33:55.209336 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10799 11:33:55.226294 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10800 11:33:55.265497 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10801 11:33:55.284374 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10802 11:33:55.302937 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10803 11:33:55.323229 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10804 11:33:55.364075 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10805 11:33:55.417814 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10806 11:33:55.508728
10807 11:33:55.512470 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10808 11:33:55.512896
10809 11:33:55.515578 debian-bookworm-arm64 login: root (automatic login)
10810 11:33:55.515959
10811 11:33:55.813577 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
10812 11:33:55.814033
10813 11:33:55.821131 The programs included with the Debian GNU/Linux system are free software;
10814 11:33:55.827181 the exact distribution terms for each program are described in the
10815 11:33:55.829361 individual files in /usr/share/doc/*/copyright.
10816 11:33:55.829743
10817 11:33:55.836177 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10818 11:33:55.839498 permitted by applicable law.
10819 11:33:56.873485 Matched prompt #10: / #
10821 11:33:56.874495 Setting prompt string to ['/ #']
10822 11:33:56.874894 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10824 11:33:56.875321 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10825 11:33:56.875494 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
10826 11:33:56.875625 Setting prompt string to ['/ #']
10827 11:33:56.875742 Forcing a shell prompt, looking for ['/ #']
10828 11:33:56.875858 Sending line: ''
10830 11:33:56.926850 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10831 11:33:56.927320 Waiting using forced prompt support (timeout 00:02:30)
10832 11:33:56.932781 / #
10833 11:33:56.933684 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10834 11:33:56.934215 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
10835 11:33:56.934654 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip'"
10837 11:33:57.042262 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864597/extract-nfsrootfs-h6ye8eip'
10838 11:33:57.043022 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
10840 11:33:57.150213 / # export NFS_SERVER_IP='192.168.201.1'
10841 11:33:57.151043 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10842 11:33:57.151526 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
10843 11:33:57.151983 end: 2 depthcharge-action (duration 00:01:21) [common]
10844 11:33:57.152462 start: 3 lava-test-retry (timeout 00:07:59) [common]
10845 11:33:57.152940 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
10846 11:33:57.153371 Using namespace: common
10847 11:33:57.153742 Sending line: '#'
10849 11:33:57.255531 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10850 11:33:57.262203 / # #
10851 11:33:57.263011 Using /lava-14864597
10852 11:33:57.263363 Sending line: 'export SHELL=/bin/bash'
10854 11:33:57.371271 / # export SHELL=/bin/bash
10855 11:33:57.372011 Sending line: '. /lava-14864597/environment'
10857 11:33:57.480045 / # . /lava-14864597/environment
10858 11:33:57.486349 Sending line: '/lava-14864597/bin/lava-test-runner /lava-14864597/0'
10860 11:33:57.587958 Test shell timeout: 10s (minimum of the action and connection timeout)
10861 11:33:57.593811 / # /lava-14864597/bin/lava-test-runner /lava-14864597/0
10862 11:33:57.862663 + export TESTRUN_ID=0_timesync-off
10863 11:33:57.864344 + TESTRUN_ID=0_timesync-off
10864 11:33:57.867690 + cd /lava-14864597/0/tests/0_timesync-off
10865 11:33:57.872084 ++ cat uuid
10866 11:33:57.875710 + UUID=14864597_1.6.2.3.1
10867 11:33:57.876099 + set +x
10868 11:33:57.882282 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14864597_1.6.2.3.1>
10869 11:33:57.882965 Received signal: <STARTRUN> 0_timesync-off 14864597_1.6.2.3.1
10870 11:33:57.883309 Starting test lava.0_timesync-off (14864597_1.6.2.3.1)
10871 11:33:57.883682 Skipping test definition patterns.
10872 11:33:57.885659 + systemctl stop systemd-timesyncd
10873 11:33:57.956852 + set +x
10874 11:33:57.960138 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14864597_1.6.2.3.1>
10875 11:33:57.960896 Received signal: <ENDRUN> 0_timesync-off 14864597_1.6.2.3.1
10876 11:33:57.961514 Ending use of test pattern.
10877 11:33:57.961844 Ending test lava.0_timesync-off (14864597_1.6.2.3.1), duration 0.08
10879 11:33:58.042729 + export TESTRUN_ID=1_kselftest-alsa
10880 11:33:58.046627 + TESTRUN_ID=1_kselftest-alsa
10881 11:33:58.052038 + cd /lava-14864597/0/tests/1_kselftest-alsa
10882 11:33:58.052450 ++ cat uuid
10883 11:33:58.057717 + UUID=14864597_1.6.2.3.5
10884 11:33:58.058100 + set +x
10885 11:33:58.064160 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14864597_1.6.2.3.5>
10886 11:33:58.064776 Received signal: <STARTRUN> 1_kselftest-alsa 14864597_1.6.2.3.5
10887 11:33:58.065140 Starting test lava.1_kselftest-alsa (14864597_1.6.2.3.5)
10888 11:33:58.065545 Skipping test definition patterns.
10889 11:33:58.068152 + cd ./automated/linux/kselftest/
10890 11:33:58.096965 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
10891 11:33:58.136883 INFO: install_deps skipped
10892 11:33:58.644636 --2024-07-17 11:33:58-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
10893 11:33:58.657184 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10894 11:33:58.784536 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10895 11:33:58.914991 HTTP request sent, awaiting response... 200 OK
10896 11:33:58.917790 Length: 1920476 (1.8M) [application/octet-stream]
10897 11:33:58.921288 Saving to: 'kselftest_armhf.tar.gz'
10898 11:33:58.921709
10899 11:33:58.922034
10900 11:33:59.174023 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10901 11:33:59.433375 kselftest_armhf.tar 2%[ ] 44.98K 174KB/s
10902 11:33:59.741401 kselftest_armhf.tar 11%[=> ] 217.50K 420KB/s
10903 11:33:59.929000 kselftest_armhf.tar 43%[=======> ] 818.47K 990KB/s
10904 11:33:59.935277 kselftest_armhf.tar 100%[===================>] 1.83M 1.81MB/s in 1.0s
10905 11:33:59.935707
10906 11:34:00.105063 2024-07-17 11:33:59 (1.81 MB/s) - 'kselftest_armhf.tar.gz' saved [1920476/1920476]
10907 11:34:00.105888
10908 11:34:07.066631 skiplist:
10909 11:34:07.070674 ========================================
10910 11:34:07.071805 ========================================
10911 11:34:07.126806 alsa:mixer-test
10912 11:34:07.149037 ============== Tests to run ===============
10913 11:34:07.152677 alsa:mixer-test
10914 11:34:07.155848 ===========End Tests to run ===============
10915 11:34:07.159857 shardfile-alsa pass
10916 11:34:07.268526 <12>[ 29.293211] kselftest: Running tests in alsa
10917 11:34:07.278006 TAP version 13
10918 11:34:07.292585 1..1
10919 11:34:07.307605 # selftests: alsa: mixer-test
10920 11:34:07.803714 # TAP version 13
10921 11:34:07.803907 # 1..0
10922 11:34:07.809938 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10923 11:34:07.813400 ok 1 selftests: alsa: mixer-test
10924 11:34:09.278531 alsa_mixer-test pass
10925 11:34:09.354154 + ../../utils/send-to-lava.sh ./output/result.txt
10926 11:34:09.425941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10927 11:34:09.426619 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10929 11:34:09.478184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10930 11:34:09.478586 + set +x
10931 11:34:09.479165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10933 11:34:09.484574 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14864597_1.6.2.3.5>
10934 11:34:09.485256 Received signal: <ENDRUN> 1_kselftest-alsa 14864597_1.6.2.3.5
10935 11:34:09.485799 Ending use of test pattern.
10936 11:34:09.486147 Ending test lava.1_kselftest-alsa (14864597_1.6.2.3.5), duration 11.42
10938 11:34:09.488461 <LAVA_TEST_RUNNER EXIT>
10939 11:34:09.489084 ok: lava_test_shell seems to have completed
10940 11:34:09.489637 shardfile-alsa: pass
alsa_mixer-test: pass
10941 11:34:09.490023 end: 3.1 lava-test-shell (duration 00:00:12) [common]
10942 11:34:09.490399 end: 3 lava-test-retry (duration 00:00:12) [common]
10943 11:34:09.490791 start: 4 finalize (timeout 00:07:47) [common]
10944 11:34:09.491246 start: 4.1 power-off (timeout 00:00:30) [common]
10945 11:34:09.492015 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10946 11:34:11.610538 >> Command sent successfully.
10947 11:34:11.626395 Returned 0 in 2 seconds
10948 11:34:11.627007 end: 4.1 power-off (duration 00:00:02) [common]
10950 11:34:11.628175 start: 4.2 read-feedback (timeout 00:07:44) [common]
10951 11:34:11.628936 Listened to connection for namespace 'common' for up to 1s
10952 11:34:12.629511 Finalising connection for namespace 'common'
10953 11:34:12.630072 Disconnecting from shell: Finalise
10954 11:34:12.630419 / #
10955 11:34:12.731357 end: 4.2 read-feedback (duration 00:00:01) [common]
10956 11:34:12.731970 end: 4 finalize (duration 00:00:03) [common]
10957 11:34:12.732530 Cleaning after the job
10958 11:34:12.733003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/ramdisk
10959 11:34:12.743695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/kernel
10960 11:34:12.779108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/dtb
10961 11:34:12.779478 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/nfsrootfs
10962 11:34:12.851567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864597/tftp-deploy-m32fafkl/modules
10963 11:34:12.857668 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864597
10964 11:34:13.417911 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864597
10965 11:34:13.418077 Job finished correctly