Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 11:34:45.657940 lava-dispatcher, installed at version: 2024.05
2 11:34:45.658151 start: 0 validate
3 11:34:45.658279 Start time: 2024-07-17 11:34:45.658273+00:00 (UTC)
4 11:34:45.658425 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:34:45.658587 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:34:45.917941 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:34:45.918129 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:34:46.175361 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:34:46.175566 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:34:46.432738 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:34:46.432887 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:34:46.689504 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:34:46.689659 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:34:46.947750 validate duration: 1.29
16 11:34:46.948018 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:34:46.948137 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:34:46.948261 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:34:46.948451 Not decompressing ramdisk as can be used compressed.
20 11:34:46.948562 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:34:46.948637 saving as /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/ramdisk/initrd.cpio.gz
22 11:34:46.948701 total size: 5628169 (5 MB)
23 11:34:46.949734 progress 0 % (0 MB)
24 11:34:46.951568 progress 5 % (0 MB)
25 11:34:46.953273 progress 10 % (0 MB)
26 11:34:46.954777 progress 15 % (0 MB)
27 11:34:46.956490 progress 20 % (1 MB)
28 11:34:46.957996 progress 25 % (1 MB)
29 11:34:46.959700 progress 30 % (1 MB)
30 11:34:46.961369 progress 35 % (1 MB)
31 11:34:46.962842 progress 40 % (2 MB)
32 11:34:46.964496 progress 45 % (2 MB)
33 11:34:46.966029 progress 50 % (2 MB)
34 11:34:46.967671 progress 55 % (2 MB)
35 11:34:46.969310 progress 60 % (3 MB)
36 11:34:46.970757 progress 65 % (3 MB)
37 11:34:46.972390 progress 70 % (3 MB)
38 11:34:46.973849 progress 75 % (4 MB)
39 11:34:46.975476 progress 80 % (4 MB)
40 11:34:46.977010 progress 85 % (4 MB)
41 11:34:46.978646 progress 90 % (4 MB)
42 11:34:46.980259 progress 95 % (5 MB)
43 11:34:46.981722 progress 100 % (5 MB)
44 11:34:46.981944 5 MB downloaded in 0.03 s (161.49 MB/s)
45 11:34:46.982099 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:34:46.982340 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:34:46.982426 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:34:46.982508 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:34:46.982652 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:34:46.982718 saving as /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/kernel/Image
52 11:34:46.982783 total size: 54813184 (52 MB)
53 11:34:46.982842 No compression specified
54 11:34:46.983941 progress 0 % (0 MB)
55 11:34:46.998729 progress 5 % (2 MB)
56 11:34:47.013700 progress 10 % (5 MB)
57 11:34:47.028272 progress 15 % (7 MB)
58 11:34:47.043013 progress 20 % (10 MB)
59 11:34:47.057909 progress 25 % (13 MB)
60 11:34:47.072618 progress 30 % (15 MB)
61 11:34:47.087440 progress 35 % (18 MB)
62 11:34:47.102585 progress 40 % (20 MB)
63 11:34:47.117306 progress 45 % (23 MB)
64 11:34:47.132127 progress 50 % (26 MB)
65 11:34:47.147049 progress 55 % (28 MB)
66 11:34:47.161661 progress 60 % (31 MB)
67 11:34:47.176763 progress 65 % (34 MB)
68 11:34:47.191558 progress 70 % (36 MB)
69 11:34:47.206632 progress 75 % (39 MB)
70 11:34:47.221502 progress 80 % (41 MB)
71 11:34:47.236303 progress 85 % (44 MB)
72 11:34:47.251009 progress 90 % (47 MB)
73 11:34:47.265732 progress 95 % (49 MB)
74 11:34:47.280360 progress 100 % (52 MB)
75 11:34:47.280640 52 MB downloaded in 0.30 s (175.50 MB/s)
76 11:34:47.280800 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:34:47.281027 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:34:47.281115 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:34:47.281198 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:34:47.281339 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 11:34:47.281406 saving as /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 11:34:47.281464 total size: 57695 (0 MB)
84 11:34:47.281522 No compression specified
85 11:34:47.282745 progress 56 % (0 MB)
86 11:34:47.283028 progress 100 % (0 MB)
87 11:34:47.283236 0 MB downloaded in 0.00 s (31.10 MB/s)
88 11:34:47.283357 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:34:47.283580 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:34:47.283662 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:34:47.283744 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:34:47.283859 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:34:47.283925 saving as /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/nfsrootfs/full.rootfs.tar
95 11:34:47.283982 total size: 120894716 (115 MB)
96 11:34:47.284042 Using unxz to decompress xz
97 11:34:47.285335 progress 0 % (0 MB)
98 11:34:47.654931 progress 5 % (5 MB)
99 11:34:48.025449 progress 10 % (11 MB)
100 11:34:48.396288 progress 15 % (17 MB)
101 11:34:48.762154 progress 20 % (23 MB)
102 11:34:49.097025 progress 25 % (28 MB)
103 11:34:49.468208 progress 30 % (34 MB)
104 11:34:49.816411 progress 35 % (40 MB)
105 11:34:50.009079 progress 40 % (46 MB)
106 11:34:50.212623 progress 45 % (51 MB)
107 11:34:50.559826 progress 50 % (57 MB)
108 11:34:50.961234 progress 55 % (63 MB)
109 11:34:51.361111 progress 60 % (69 MB)
110 11:34:51.764513 progress 65 % (74 MB)
111 11:34:52.132428 progress 70 % (80 MB)
112 11:34:52.508266 progress 75 % (86 MB)
113 11:34:52.870100 progress 80 % (92 MB)
114 11:34:53.235050 progress 85 % (98 MB)
115 11:34:53.602661 progress 90 % (103 MB)
116 11:34:53.951237 progress 95 % (109 MB)
117 11:34:54.330019 progress 100 % (115 MB)
118 11:34:54.335843 115 MB downloaded in 7.05 s (16.35 MB/s)
119 11:34:54.336017 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:34:54.336252 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:34:54.336339 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:34:54.336421 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:34:54.336572 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:34:54.336640 saving as /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/modules/modules.tar
126 11:34:54.336700 total size: 8610184 (8 MB)
127 11:34:54.336761 Using unxz to decompress xz
128 11:34:54.338209 progress 0 % (0 MB)
129 11:34:54.360262 progress 5 % (0 MB)
130 11:34:54.386574 progress 10 % (0 MB)
131 11:34:54.412334 progress 15 % (1 MB)
132 11:34:54.438384 progress 20 % (1 MB)
133 11:34:54.463505 progress 25 % (2 MB)
134 11:34:54.488649 progress 30 % (2 MB)
135 11:34:54.512650 progress 35 % (2 MB)
136 11:34:54.540703 progress 40 % (3 MB)
137 11:34:54.566750 progress 45 % (3 MB)
138 11:34:54.592429 progress 50 % (4 MB)
139 11:34:54.618688 progress 55 % (4 MB)
140 11:34:54.644376 progress 60 % (4 MB)
141 11:34:54.669254 progress 65 % (5 MB)
142 11:34:54.696303 progress 70 % (5 MB)
143 11:34:54.725087 progress 75 % (6 MB)
144 11:34:54.754300 progress 80 % (6 MB)
145 11:34:54.779577 progress 85 % (7 MB)
146 11:34:54.804337 progress 90 % (7 MB)
147 11:34:54.829264 progress 95 % (7 MB)
148 11:34:54.853464 progress 100 % (8 MB)
149 11:34:54.859724 8 MB downloaded in 0.52 s (15.70 MB/s)
150 11:34:54.859901 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:34:54.860136 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:34:54.860221 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 11:34:54.860305 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 11:34:58.700802 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o
156 11:34:58.700993 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:34:58.701123 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:34:58.701316 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew
159 11:34:58.701452 makedir: /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin
160 11:34:58.701557 makedir: /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/tests
161 11:34:58.701657 makedir: /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/results
162 11:34:58.701748 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-add-keys
163 11:34:58.701884 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-add-sources
164 11:34:58.702011 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-background-process-start
165 11:34:58.702138 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-background-process-stop
166 11:34:58.702274 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-common-functions
167 11:34:58.702399 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-echo-ipv4
168 11:34:58.702522 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-install-packages
169 11:34:58.702643 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-installed-packages
170 11:34:58.702763 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-os-build
171 11:34:58.702886 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-probe-channel
172 11:34:58.703009 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-probe-ip
173 11:34:58.703132 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-target-ip
174 11:34:58.703252 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-target-mac
175 11:34:58.703371 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-target-storage
176 11:34:58.703494 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-case
177 11:34:58.703615 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-event
178 11:34:58.703736 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-feedback
179 11:34:58.703856 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-raise
180 11:34:58.703975 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-reference
181 11:34:58.704095 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-runner
182 11:34:58.704214 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-set
183 11:34:58.704333 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-test-shell
184 11:34:58.704467 Updating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-add-keys (debian)
185 11:34:58.704615 Updating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-add-sources (debian)
186 11:34:58.704758 Updating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-install-packages (debian)
187 11:34:58.704897 Updating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-installed-packages (debian)
188 11:34:58.705036 Updating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/bin/lava-os-build (debian)
189 11:34:58.705159 Creating /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/environment
190 11:34:58.705256 LAVA metadata
191 11:34:58.705323 - LAVA_JOB_ID=14864624
192 11:34:58.705383 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:34:58.705482 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:34:58.705544 skipped lava-vland-overlay
195 11:34:58.705617 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:34:58.705694 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:34:58.705753 skipped lava-multinode-overlay
198 11:34:58.705823 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:34:58.705898 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:34:58.705966 Loading test definitions
201 11:34:58.706047 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:34:58.706114 Using /lava-14864624 at stage 0
203 11:34:58.706418 uuid=14864624_1.6.2.3.1 testdef=None
204 11:34:58.706504 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:34:58.706586 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:34:58.707019 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:34:58.707235 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:34:58.707788 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:34:58.708014 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:34:58.708557 runner path: /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/0/tests/0_timesync-off test_uuid 14864624_1.6.2.3.1
213 11:34:58.708716 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:34:58.708935 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:34:58.709006 Using /lava-14864624 at stage 0
217 11:34:58.709100 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:34:58.709181 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/0/tests/1_kselftest-arm64'
219 11:35:01.103192 Running '/usr/bin/git checkout kernelci.org
220 11:35:01.194058 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:35:01.194461 uuid=14864624_1.6.2.3.5 testdef=None
222 11:35:01.194576 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 11:35:01.194790 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 11:35:01.195495 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:35:01.195720 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 11:35:01.196708 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:35:01.196945 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 11:35:01.198008 runner path: /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/0/tests/1_kselftest-arm64 test_uuid 14864624_1.6.2.3.5
232 11:35:01.198102 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 11:35:01.198169 BRANCH='cip-gitlab'
234 11:35:01.198229 SKIPFILE='/dev/null'
235 11:35:01.198286 SKIP_INSTALL='True'
236 11:35:01.198341 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:35:01.198398 TST_CASENAME=''
238 11:35:01.198452 TST_CMDFILES='arm64'
239 11:35:01.198597 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:35:01.198796 Creating lava-test-runner.conf files
242 11:35:01.198857 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864624/lava-overlay-24nrgiew/lava-14864624/0 for stage 0
243 11:35:01.198947 - 0_timesync-off
244 11:35:01.199013 - 1_kselftest-arm64
245 11:35:01.199107 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 11:35:01.199190 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 11:35:09.071316 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:35:09.071458 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 11:35:09.071553 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:35:09.071643 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 11:35:09.071730 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 11:35:09.233487 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:35:09.233645 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 11:35:09.233727 extracting modules file /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o
255 11:35:09.484831 extracting modules file /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864624/extract-overlay-ramdisk-bmdvhweo/ramdisk
256 11:35:09.752290 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 11:35:09.752445 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 11:35:09.752545 [common] Applying overlay to NFS
259 11:35:09.752613 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864624/compress-overlay-pvrrfqcv/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o
260 11:35:10.680818 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:35:10.680965 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 11:35:10.681058 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:35:10.681158 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 11:35:10.681248 Building ramdisk /var/lib/lava/dispatcher/tmp/14864624/extract-overlay-ramdisk-bmdvhweo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864624/extract-overlay-ramdisk-bmdvhweo/ramdisk
265 11:35:10.989567 >> 129966 blocks
266 11:35:13.281469 rename /var/lib/lava/dispatcher/tmp/14864624/extract-overlay-ramdisk-bmdvhweo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/ramdisk/ramdisk.cpio.gz
267 11:35:13.281644 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 11:35:13.281741 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:35:13.281827 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:35:13.281913 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/kernel/Image']
271 11:35:27.960689 Returned 0 in 14 seconds
272 11:35:27.960870 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/kernel/image.itb
273 11:35:28.332896 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:35:28.333034 output: Created: Wed Jul 17 12:35:28 2024
275 11:35:28.333102 output: Image 0 (kernel-1)
276 11:35:28.333162 output: Description:
277 11:35:28.333220 output: Created: Wed Jul 17 12:35:28 2024
278 11:35:28.333277 output: Type: Kernel Image
279 11:35:28.333333 output: Compression: lzma compressed
280 11:35:28.333392 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
281 11:35:28.333449 output: Architecture: AArch64
282 11:35:28.333503 output: OS: Linux
283 11:35:28.333556 output: Load Address: 0x00000000
284 11:35:28.333609 output: Entry Point: 0x00000000
285 11:35:28.333663 output: Hash algo: crc32
286 11:35:28.333716 output: Hash value: 83448d17
287 11:35:28.333769 output: Image 1 (fdt-1)
288 11:35:28.333822 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 11:35:28.333876 output: Created: Wed Jul 17 12:35:28 2024
290 11:35:28.333930 output: Type: Flat Device Tree
291 11:35:28.333983 output: Compression: uncompressed
292 11:35:28.334037 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 11:35:28.334091 output: Architecture: AArch64
294 11:35:28.334150 output: Hash algo: crc32
295 11:35:28.334205 output: Hash value: a9713552
296 11:35:28.334257 output: Image 2 (ramdisk-1)
297 11:35:28.334310 output: Description: unavailable
298 11:35:28.334373 output: Created: Wed Jul 17 12:35:28 2024
299 11:35:28.334428 output: Type: RAMDisk Image
300 11:35:28.334480 output: Compression: uncompressed
301 11:35:28.334533 output: Data Size: 18718838 Bytes = 18280.12 KiB = 17.85 MiB
302 11:35:28.334587 output: Architecture: AArch64
303 11:35:28.334639 output: OS: Linux
304 11:35:28.334691 output: Load Address: unavailable
305 11:35:28.334744 output: Entry Point: unavailable
306 11:35:28.334796 output: Hash algo: crc32
307 11:35:28.334849 output: Hash value: 977fabe2
308 11:35:28.334901 output: Default Configuration: 'conf-1'
309 11:35:28.334953 output: Configuration 0 (conf-1)
310 11:35:28.335005 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 11:35:28.335057 output: Kernel: kernel-1
312 11:35:28.335110 output: Init Ramdisk: ramdisk-1
313 11:35:28.335162 output: FDT: fdt-1
314 11:35:28.335215 output: Loadables: kernel-1
315 11:35:28.335268 output:
316 11:35:28.335375 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 11:35:28.335457 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 11:35:28.335537 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 11:35:28.335629 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 11:35:28.335694 No LXC device requested
321 11:35:28.335767 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:35:28.335844 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 11:35:28.335917 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:35:28.335978 Checking files for TFTP limit of 4294967296 bytes.
325 11:35:28.336377 end: 1 tftp-deploy (duration 00:00:41) [common]
326 11:35:28.336485 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:35:28.336574 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:35:28.336673 substitutions:
329 11:35:28.336738 - {DTB}: 14864624/tftp-deploy-9eym88c1/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 11:35:28.336798 - {INITRD}: 14864624/tftp-deploy-9eym88c1/ramdisk/ramdisk.cpio.gz
331 11:35:28.336855 - {KERNEL}: 14864624/tftp-deploy-9eym88c1/kernel/Image
332 11:35:28.336912 - {LAVA_MAC}: None
333 11:35:28.336968 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o
334 11:35:28.337024 - {NFS_SERVER_IP}: 192.168.201.1
335 11:35:28.337078 - {PRESEED_CONFIG}: None
336 11:35:28.337143 - {PRESEED_LOCAL}: None
337 11:35:28.337199 - {RAMDISK}: 14864624/tftp-deploy-9eym88c1/ramdisk/ramdisk.cpio.gz
338 11:35:28.337253 - {ROOT_PART}: None
339 11:35:28.337306 - {ROOT}: None
340 11:35:28.337359 - {SERVER_IP}: 192.168.201.1
341 11:35:28.337412 - {TEE}: None
342 11:35:28.337465 Parsed boot commands:
343 11:35:28.337517 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:35:28.337664 Parsed boot commands: tftpboot 192.168.201.1 14864624/tftp-deploy-9eym88c1/kernel/image.itb 14864624/tftp-deploy-9eym88c1/kernel/cmdline
345 11:35:28.337751 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:35:28.337832 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:35:28.337912 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:35:28.337991 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:35:28.338052 Not connected, no need to disconnect.
350 11:35:28.338125 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:35:28.338199 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:35:28.338259 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
353 11:35:28.341481 Setting prompt string to ['lava-test: # ']
354 11:35:28.341814 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:35:28.341916 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:35:28.342012 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:35:28.342099 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:35:28.342285 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=reboot']
359 11:35:37.469725 >> Command sent successfully.
360 11:35:37.473078 Returned 0 in 9 seconds
361 11:35:37.473234 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:35:37.473460 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:35:37.473552 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:35:37.473630 Setting prompt string to 'Starting depthcharge on Juniper...'
366 11:35:37.473692 Changing prompt to 'Starting depthcharge on Juniper...'
367 11:35:37.473760 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
368 11:35:37.474125 [Enter `^Ec?' for help]
369 11:35:44.489613 [DL] 00000000 00000000 010701
370 11:35:44.494490
371 11:35:44.494576
372 11:35:44.494646 F0: 102B 0000
373 11:35:44.494711
374 11:35:44.494770 F3: 1006 0033 [0200]
375 11:35:44.497706
376 11:35:44.497790 F3: 4001 00E0 [0200]
377 11:35:44.497857
378 11:35:44.497916 F3: 0000 0000
379 11:35:44.497975
380 11:35:44.501225 V0: 0000 0000 [0001]
381 11:35:44.501310
382 11:35:44.501375 00: 1027 0002
383 11:35:44.501439
384 11:35:44.504234 01: 0000 0000
385 11:35:44.504320
386 11:35:44.504386 BP: 0C00 0251 [0000]
387 11:35:44.504447
388 11:35:44.508149 G0: 1182 0000
389 11:35:44.508233
390 11:35:44.508297 EC: 0004 0000 [0001]
391 11:35:44.508358
392 11:35:44.511407 S7: 0000 0000 [0000]
393 11:35:44.511492
394 11:35:44.511558 CC: 0000 0000 [0001]
395 11:35:44.514705
396 11:35:44.514788 T0: 0000 00DB [000F]
397 11:35:44.514854
398 11:35:44.514914 Jump to BL
399 11:35:44.514972
400 11:35:44.550253
401 11:35:44.550339
402 11:35:44.557087 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 11:35:44.560480 ARM64: Exception handlers installed.
404 11:35:44.563743 ARM64: Testing exception
405 11:35:44.566813 ARM64: Done test exception
406 11:35:44.571277 WDT: Last reset was cold boot
407 11:35:44.571351 SPI0(PAD0) initialized at 992727 Hz
408 11:35:44.577948 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 11:35:44.578028 Manufacturer: ef
410 11:35:44.584711 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 11:35:44.597455 Probing TPM: . done!
412 11:35:44.597530 TPM ready after 0 ms
413 11:35:44.604364 Connected to device vid:did:rid of 1ae0:0028:00
414 11:35:44.611517 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
415 11:35:44.645844 Initialized TPM device CR50 revision 0
416 11:35:44.657962 tlcl_send_startup: Startup return code is 0
417 11:35:44.658048 TPM: setup succeeded
418 11:35:44.667316 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 11:35:44.670505 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 11:35:44.674108 in-header: 03 19 00 00 08 00 00 00
421 11:35:44.677238 in-data: a2 e0 47 00 13 00 00 00
422 11:35:44.680540 Chrome EC: UHEPI supported
423 11:35:44.687136 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 11:35:44.690398 in-header: 03 a1 00 00 08 00 00 00
425 11:35:44.693946 in-data: 84 60 60 10 00 00 00 00
426 11:35:44.694023 Phase 1
427 11:35:44.697164 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 11:35:44.704112 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 11:35:44.710441 VB2:vb2_check_recovery() Recovery was requested manually
430 11:35:44.713890 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 11:35:44.719774 Recovery requested (1009000e)
432 11:35:44.728812 tlcl_extend: response is 0
433 11:35:44.733885 tlcl_extend: response is 0
434 11:35:44.759251
435 11:35:44.759333
436 11:35:44.765505 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 11:35:44.769402 ARM64: Exception handlers installed.
438 11:35:44.772604 ARM64: Testing exception
439 11:35:44.775411 ARM64: Done test exception
440 11:35:44.791165 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc268, sec=0x2000
441 11:35:44.797886 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 11:35:44.801498 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 11:35:44.809482 [RTC]rtc_get_frequency_meter,134: input=0xf, output=916
444 11:35:44.816450 [RTC]rtc_get_frequency_meter,134: input=0x7, output=777
445 11:35:44.823420 [RTC]rtc_get_frequency_meter,134: input=0xb, output=847
446 11:35:44.830199 [RTC]rtc_get_frequency_meter,134: input=0x9, output=812
447 11:35:44.837441 [RTC]rtc_get_frequency_meter,134: input=0x8, output=798
448 11:35:44.843802 [RTC]rtc_get_frequency_meter,134: input=0x7, output=780
449 11:35:44.851302 [RTC]rtc_get_frequency_meter,134: input=0x8, output=796
450 11:35:44.854208 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
451 11:35:44.860797 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
452 11:35:44.864040 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
453 11:35:44.867577 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
454 11:35:44.871211 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
455 11:35:44.874324 in-header: 03 19 00 00 08 00 00 00
456 11:35:44.877827 in-data: a2 e0 47 00 13 00 00 00
457 11:35:44.880865 Chrome EC: UHEPI supported
458 11:35:44.887404 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
459 11:35:44.891509 in-header: 03 a1 00 00 08 00 00 00
460 11:35:44.894667 in-data: 84 60 60 10 00 00 00 00
461 11:35:44.897711 Skip loading cached calibration data
462 11:35:44.904731 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
463 11:35:44.907630 in-header: 03 a1 00 00 08 00 00 00
464 11:35:44.910817 in-data: 84 60 60 10 00 00 00 00
465 11:35:44.917887 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
466 11:35:44.920979 in-header: 03 a1 00 00 08 00 00 00
467 11:35:44.924658 in-data: 84 60 60 10 00 00 00 00
468 11:35:44.928014 ADC[3]: Raw value=216571 ID=1
469 11:35:44.928082 Manufacturer: ef
470 11:35:44.934664 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
471 11:35:44.937709 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
472 11:35:44.941391 CBFS @ 21000 size 3d4000
473 11:35:44.944972 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
474 11:35:44.951410 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
475 11:35:44.954785 CBFS: Found @ offset 3c700 size 44
476 11:35:44.954874 DRAM-K: Full Calibration
477 11:35:44.961405 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
478 11:35:44.961495 CBFS @ 21000 size 3d4000
479 11:35:44.967991 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
480 11:35:44.971367 CBFS: Locating 'fallback/dram'
481 11:35:44.974659 CBFS: Found @ offset 24b00 size 12268
482 11:35:45.002032 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
483 11:35:45.005604 ddr_geometry: 1, config: 0x0
484 11:35:45.008754 header.status = 0x0
485 11:35:45.012009 header.magic = 0x44524d4b (expected: 0x44524d4b)
486 11:35:45.015490 header.version = 0x5 (expected: 0x5)
487 11:35:45.018293 header.size = 0x8f0 (expected: 0x8f0)
488 11:35:45.018366 header.config = 0x0
489 11:35:45.022226 header.flags = 0x0
490 11:35:45.025236 header.checksum = 0x0
491 11:35:45.028876 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
492 11:35:45.035390 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
493 11:35:45.038666 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
494 11:35:45.041914 ddr_geometry:1
495 11:35:45.045501 [EMI] new MDL number = 1
496 11:35:45.045576 dram_cbt_mode_extern: 0
497 11:35:45.048779 dram_cbt_mode [RK0]: 0, [RK1]: 0
498 11:35:45.055614 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
499 11:35:45.055697
500 11:35:45.055763
501 11:35:45.059065 [Bianco] ETT version 0.0.0.1
502 11:35:45.062432 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
503 11:35:45.062502
504 11:35:45.065719 vSetVcoreByFreq with vcore:762500, freq=1600
505 11:35:45.065787
506 11:35:45.065848 [DramcInit]
507 11:35:45.068547 AutoRefreshCKEOff AutoREF OFF
508 11:35:45.072615 DDRPhyPLLSetting-CKEOFF
509 11:35:45.075373 DDRPhyPLLSetting-CKEON
510 11:35:45.075441
511 11:35:45.075502 Enable WDQS
512 11:35:45.079307 [ModeRegInit_LP4] CH0 RK0
513 11:35:45.082773 Write Rank0 MR13 =0x18
514 11:35:45.082845 Write Rank0 MR12 =0x5d
515 11:35:45.085681 Write Rank0 MR1 =0x56
516 11:35:45.089295 Write Rank0 MR2 =0x1a
517 11:35:45.089366 Write Rank0 MR11 =0x0
518 11:35:45.092740 Write Rank0 MR22 =0x38
519 11:35:45.092809 Write Rank0 MR14 =0x5d
520 11:35:45.095906 Write Rank0 MR3 =0x30
521 11:35:45.099374 Write Rank0 MR13 =0x58
522 11:35:45.099445 Write Rank0 MR12 =0x5d
523 11:35:45.102880 Write Rank0 MR1 =0x56
524 11:35:45.102947 Write Rank0 MR2 =0x2d
525 11:35:45.105725 Write Rank0 MR11 =0x23
526 11:35:45.109450 Write Rank0 MR22 =0x34
527 11:35:45.109534 Write Rank0 MR14 =0x10
528 11:35:45.112641 Write Rank0 MR3 =0x30
529 11:35:45.116106 Write Rank0 MR13 =0xd8
530 11:35:45.116189 [ModeRegInit_LP4] CH0 RK1
531 11:35:45.119404 Write Rank1 MR13 =0x18
532 11:35:45.119488 Write Rank1 MR12 =0x5d
533 11:35:45.122605 Write Rank1 MR1 =0x56
534 11:35:45.126049 Write Rank1 MR2 =0x1a
535 11:35:45.126132 Write Rank1 MR11 =0x0
536 11:35:45.129480 Write Rank1 MR22 =0x38
537 11:35:45.129564 Write Rank1 MR14 =0x5d
538 11:35:45.132477 Write Rank1 MR3 =0x30
539 11:35:45.136106 Write Rank1 MR13 =0x58
540 11:35:45.136184 Write Rank1 MR12 =0x5d
541 11:35:45.139605 Write Rank1 MR1 =0x56
542 11:35:45.142578 Write Rank1 MR2 =0x2d
543 11:35:45.142648 Write Rank1 MR11 =0x23
544 11:35:45.146225 Write Rank1 MR22 =0x34
545 11:35:45.146293 Write Rank1 MR14 =0x10
546 11:35:45.149412 Write Rank1 MR3 =0x30
547 11:35:45.152580 Write Rank1 MR13 =0xd8
548 11:35:45.152653 [ModeRegInit_LP4] CH1 RK0
549 11:35:45.156189 Write Rank0 MR13 =0x18
550 11:35:45.159195 Write Rank0 MR12 =0x5d
551 11:35:45.159262 Write Rank0 MR1 =0x56
552 11:35:45.162802 Write Rank0 MR2 =0x1a
553 11:35:45.162872 Write Rank0 MR11 =0x0
554 11:35:45.166225 Write Rank0 MR22 =0x38
555 11:35:45.166295 Write Rank0 MR14 =0x5d
556 11:35:45.169547 Write Rank0 MR3 =0x30
557 11:35:45.173070 Write Rank0 MR13 =0x58
558 11:35:45.173137 Write Rank0 MR12 =0x5d
559 11:35:45.176466 Write Rank0 MR1 =0x56
560 11:35:45.179581 Write Rank0 MR2 =0x2d
561 11:35:45.179647 Write Rank0 MR11 =0x23
562 11:35:45.182688 Write Rank0 MR22 =0x34
563 11:35:45.182754 Write Rank0 MR14 =0x10
564 11:35:45.186299 Write Rank0 MR3 =0x30
565 11:35:45.189487 Write Rank0 MR13 =0xd8
566 11:35:45.189551 [ModeRegInit_LP4] CH1 RK1
567 11:35:45.192779 Write Rank1 MR13 =0x18
568 11:35:45.196208 Write Rank1 MR12 =0x5d
569 11:35:45.196273 Write Rank1 MR1 =0x56
570 11:35:45.199588 Write Rank1 MR2 =0x1a
571 11:35:45.199652 Write Rank1 MR11 =0x0
572 11:35:45.203238 Write Rank1 MR22 =0x38
573 11:35:45.206331 Write Rank1 MR14 =0x5d
574 11:35:45.206435 Write Rank1 MR3 =0x30
575 11:35:45.209408 Write Rank1 MR13 =0x58
576 11:35:45.209475 Write Rank1 MR12 =0x5d
577 11:35:45.213278 Write Rank1 MR1 =0x56
578 11:35:45.216426 Write Rank1 MR2 =0x2d
579 11:35:45.216502 Write Rank1 MR11 =0x23
580 11:35:45.219664 Write Rank1 MR22 =0x34
581 11:35:45.219737 Write Rank1 MR14 =0x10
582 11:35:45.222796 Write Rank1 MR3 =0x30
583 11:35:45.226203 Write Rank1 MR13 =0xd8
584 11:35:45.226271 match AC timing 3
585 11:35:45.236910 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
586 11:35:45.236987 [MiockJmeterHQA]
587 11:35:45.242821 vSetVcoreByFreq with vcore:762500, freq=1600
588 11:35:45.347402
589 11:35:45.347505 MIOCK jitter meter ch=0
590 11:35:45.347574
591 11:35:45.350463 1T = (102-17) = 85 dly cells
592 11:35:45.357854 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
593 11:35:45.360493 vSetVcoreByFreq with vcore:725000, freq=1200
594 11:35:45.459665
595 11:35:45.459771 MIOCK jitter meter ch=0
596 11:35:45.459837
597 11:35:45.463241 1T = (96-16) = 80 dly cells
598 11:35:45.470477 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
599 11:35:45.473809 vSetVcoreByFreq with vcore:725000, freq=800
600 11:35:45.571970
601 11:35:45.572064 MIOCK jitter meter ch=0
602 11:35:45.572135
603 11:35:45.575647 1T = (96-16) = 80 dly cells
604 11:35:45.582216 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
605 11:35:45.585393 vSetVcoreByFreq with vcore:762500, freq=1600
606 11:35:45.588557 vSetVcoreByFreq with vcore:762500, freq=1600
607 11:35:45.588635
608 11:35:45.588697 K DRVP
609 11:35:45.592392 1. OCD DRVP=0 CALOUT=0
610 11:35:45.595703 1. OCD DRVP=1 CALOUT=0
611 11:35:45.595776 1. OCD DRVP=2 CALOUT=0
612 11:35:45.598818 1. OCD DRVP=3 CALOUT=0
613 11:35:45.598887 1. OCD DRVP=4 CALOUT=0
614 11:35:45.601881 1. OCD DRVP=5 CALOUT=0
615 11:35:45.605429 1. OCD DRVP=6 CALOUT=0
616 11:35:45.605501 1. OCD DRVP=7 CALOUT=0
617 11:35:45.609043 1. OCD DRVP=8 CALOUT=0
618 11:35:45.612109 1. OCD DRVP=9 CALOUT=1
619 11:35:45.612181
620 11:35:45.615442 1. OCD DRVP calibration OK! DRVP=9
621 11:35:45.615513
622 11:35:45.615575
623 11:35:45.615631
624 11:35:45.615686 K ODTN
625 11:35:45.618926 3. OCD ODTN=0 ,CALOUT=1
626 11:35:45.618991 3. OCD ODTN=1 ,CALOUT=1
627 11:35:45.622456 3. OCD ODTN=2 ,CALOUT=1
628 11:35:45.622524 3. OCD ODTN=3 ,CALOUT=1
629 11:35:45.625396 3. OCD ODTN=4 ,CALOUT=1
630 11:35:45.628631 3. OCD ODTN=5 ,CALOUT=1
631 11:35:45.628700 3. OCD ODTN=6 ,CALOUT=1
632 11:35:45.632381 3. OCD ODTN=7 ,CALOUT=0
633 11:35:45.632482
634 11:35:45.635614 3. OCD ODTN calibration OK! ODTN=7
635 11:35:45.635683
636 11:35:45.638798 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
637 11:35:45.642395 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
638 11:35:45.648927 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
639 11:35:45.649003
640 11:35:45.649066 K DRVP
641 11:35:45.652121 1. OCD DRVP=0 CALOUT=0
642 11:35:45.652223 1. OCD DRVP=1 CALOUT=0
643 11:35:45.655505 1. OCD DRVP=2 CALOUT=0
644 11:35:45.659139 1. OCD DRVP=3 CALOUT=0
645 11:35:45.659208 1. OCD DRVP=4 CALOUT=0
646 11:35:45.662218 1. OCD DRVP=5 CALOUT=0
647 11:35:45.662287 1. OCD DRVP=6 CALOUT=0
648 11:35:45.665800 1. OCD DRVP=7 CALOUT=0
649 11:35:45.669341 1. OCD DRVP=8 CALOUT=0
650 11:35:45.669411 1. OCD DRVP=9 CALOUT=0
651 11:35:45.672331 1. OCD DRVP=10 CALOUT=0
652 11:35:45.675819 1. OCD DRVP=11 CALOUT=1
653 11:35:45.675890
654 11:35:45.679030 1. OCD DRVP calibration OK! DRVP=11
655 11:35:45.679101
656 11:35:45.679157
657 11:35:45.679212
658 11:35:45.679266 K ODTN
659 11:35:45.682648 3. OCD ODTN=0 ,CALOUT=1
660 11:35:45.682723 3. OCD ODTN=1 ,CALOUT=1
661 11:35:45.685675 3. OCD ODTN=2 ,CALOUT=1
662 11:35:45.688945 3. OCD ODTN=3 ,CALOUT=1
663 11:35:45.689017 3. OCD ODTN=4 ,CALOUT=1
664 11:35:45.692363 3. OCD ODTN=5 ,CALOUT=1
665 11:35:45.695702 3. OCD ODTN=6 ,CALOUT=1
666 11:35:45.695776 3. OCD ODTN=7 ,CALOUT=1
667 11:35:45.699250 3. OCD ODTN=8 ,CALOUT=1
668 11:35:45.699320 3. OCD ODTN=9 ,CALOUT=1
669 11:35:45.702410 3. OCD ODTN=10 ,CALOUT=1
670 11:35:45.705589 3. OCD ODTN=11 ,CALOUT=1
671 11:35:45.705654 3. OCD ODTN=12 ,CALOUT=1
672 11:35:45.708862 3. OCD ODTN=13 ,CALOUT=1
673 11:35:45.712371 3. OCD ODTN=14 ,CALOUT=1
674 11:35:45.712442 3. OCD ODTN=15 ,CALOUT=0
675 11:35:45.716006
676 11:35:45.716073 3. OCD ODTN calibration OK! ODTN=15
677 11:35:45.719039
678 11:35:45.722522 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
679 11:35:45.725971 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
680 11:35:45.729114 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
681 11:35:45.729178
682 11:35:45.732386 [DramcInit]
683 11:35:45.735844 AutoRefreshCKEOff AutoREF OFF
684 11:35:45.735909 DDRPhyPLLSetting-CKEOFF
685 11:35:45.738936 DDRPhyPLLSetting-CKEON
686 11:35:45.738998
687 11:35:45.739056 Enable WDQS
688 11:35:45.739112 ==
689 11:35:45.746147 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
690 11:35:45.749249 fsp= 1, odt_onoff= 1, Byte mode= 0
691 11:35:45.749323 ==
692 11:35:45.752566 [Duty_Offset_Calibration]
693 11:35:45.752631
694 11:35:45.752686 ===========================
695 11:35:45.756027 B0:1 B1:1 CA:1
696 11:35:45.775073 ==
697 11:35:45.778400 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
698 11:35:45.781436 fsp= 1, odt_onoff= 1, Byte mode= 0
699 11:35:45.781507 ==
700 11:35:45.785221 [Duty_Offset_Calibration]
701 11:35:45.785286
702 11:35:45.788371 ===========================
703 11:35:45.788433 B0:1 B1:0 CA:2
704 11:35:45.821280 [ModeRegInit_LP4] CH0 RK0
705 11:35:45.824903 Write Rank0 MR13 =0x18
706 11:35:45.824977 Write Rank0 MR12 =0x5d
707 11:35:45.828156 Write Rank0 MR1 =0x56
708 11:35:45.831619 Write Rank0 MR2 =0x1a
709 11:35:45.831687 Write Rank0 MR11 =0x0
710 11:35:45.834933 Write Rank0 MR22 =0x38
711 11:35:45.834999 Write Rank0 MR14 =0x5d
712 11:35:45.838150 Write Rank0 MR3 =0x30
713 11:35:45.841686 Write Rank0 MR13 =0x58
714 11:35:45.841749 Write Rank0 MR12 =0x5d
715 11:35:45.845053 Write Rank0 MR1 =0x56
716 11:35:45.845118 Write Rank0 MR2 =0x2d
717 11:35:45.848197 Write Rank0 MR11 =0x23
718 11:35:45.851297 Write Rank0 MR22 =0x34
719 11:35:45.851367 Write Rank0 MR14 =0x10
720 11:35:45.854768 Write Rank0 MR3 =0x30
721 11:35:45.854832 Write Rank0 MR13 =0xd8
722 11:35:45.858062 [ModeRegInit_LP4] CH0 RK1
723 11:35:45.861539 Write Rank1 MR13 =0x18
724 11:35:45.861604 Write Rank1 MR12 =0x5d
725 11:35:45.865405 Write Rank1 MR1 =0x56
726 11:35:45.868222 Write Rank1 MR2 =0x1a
727 11:35:45.868291 Write Rank1 MR11 =0x0
728 11:35:45.871606 Write Rank1 MR22 =0x38
729 11:35:45.871677 Write Rank1 MR14 =0x5d
730 11:35:45.875026 Write Rank1 MR3 =0x30
731 11:35:45.878061 Write Rank1 MR13 =0x58
732 11:35:45.878129 Write Rank1 MR12 =0x5d
733 11:35:45.881443 Write Rank1 MR1 =0x56
734 11:35:45.881510 Write Rank1 MR2 =0x2d
735 11:35:45.885366 Write Rank1 MR11 =0x23
736 11:35:45.888491 Write Rank1 MR22 =0x34
737 11:35:45.888554 Write Rank1 MR14 =0x10
738 11:35:45.891607 Write Rank1 MR3 =0x30
739 11:35:45.895080 Write Rank1 MR13 =0xd8
740 11:35:45.895146 [ModeRegInit_LP4] CH1 RK0
741 11:35:45.898476 Write Rank0 MR13 =0x18
742 11:35:45.898540 Write Rank0 MR12 =0x5d
743 11:35:45.901716 Write Rank0 MR1 =0x56
744 11:35:45.905453 Write Rank0 MR2 =0x1a
745 11:35:45.905519 Write Rank0 MR11 =0x0
746 11:35:45.908322 Write Rank0 MR22 =0x38
747 11:35:45.908388 Write Rank0 MR14 =0x5d
748 11:35:45.911772 Write Rank0 MR3 =0x30
749 11:35:45.915177 Write Rank0 MR13 =0x58
750 11:35:45.915248 Write Rank0 MR12 =0x5d
751 11:35:45.918508 Write Rank0 MR1 =0x56
752 11:35:45.918577 Write Rank0 MR2 =0x2d
753 11:35:45.922033 Write Rank0 MR11 =0x23
754 11:35:45.925272 Write Rank0 MR22 =0x34
755 11:35:45.925341 Write Rank0 MR14 =0x10
756 11:35:45.928836 Write Rank0 MR3 =0x30
757 11:35:45.928902 Write Rank0 MR13 =0xd8
758 11:35:45.932139 [ModeRegInit_LP4] CH1 RK1
759 11:35:45.935166 Write Rank1 MR13 =0x18
760 11:35:45.935232 Write Rank1 MR12 =0x5d
761 11:35:45.938957 Write Rank1 MR1 =0x56
762 11:35:45.942379 Write Rank1 MR2 =0x1a
763 11:35:45.942443 Write Rank1 MR11 =0x0
764 11:35:45.945242 Write Rank1 MR22 =0x38
765 11:35:45.945308 Write Rank1 MR14 =0x5d
766 11:35:45.948854 Write Rank1 MR3 =0x30
767 11:35:45.952028 Write Rank1 MR13 =0x58
768 11:35:45.952093 Write Rank1 MR12 =0x5d
769 11:35:45.955604 Write Rank1 MR1 =0x56
770 11:35:45.955672 Write Rank1 MR2 =0x2d
771 11:35:45.958980 Write Rank1 MR11 =0x23
772 11:35:45.961884 Write Rank1 MR22 =0x34
773 11:35:45.961948 Write Rank1 MR14 =0x10
774 11:35:45.965772 Write Rank1 MR3 =0x30
775 11:35:45.968720 Write Rank1 MR13 =0xd8
776 11:35:45.968787 match AC timing 3
777 11:35:45.978913 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
778 11:35:45.979022 DramC Write-DBI off
779 11:35:45.982523 DramC Read-DBI off
780 11:35:45.985468 Write Rank0 MR13 =0x59
781 11:35:45.985554 ==
782 11:35:45.988706 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
783 11:35:45.992142 fsp= 1, odt_onoff= 1, Byte mode= 0
784 11:35:45.992226 ==
785 11:35:45.995512 === u2Vref_new: 0x56 --> 0x2d
786 11:35:45.999179 === u2Vref_new: 0x58 --> 0x38
787 11:35:46.002828 === u2Vref_new: 0x5a --> 0x39
788 11:35:46.005586 === u2Vref_new: 0x5c --> 0x3c
789 11:35:46.008909 === u2Vref_new: 0x5e --> 0x3d
790 11:35:46.012104 === u2Vref_new: 0x60 --> 0xa0
791 11:35:46.015781 [CA 0] Center 34 (6~63) winsize 58
792 11:35:46.018850 [CA 1] Center 36 (9~63) winsize 55
793 11:35:46.018934 [CA 2] Center 29 (0~58) winsize 59
794 11:35:46.022612 [CA 3] Center 24 (-3~52) winsize 56
795 11:35:46.025688 [CA 4] Center 25 (-3~54) winsize 58
796 11:35:46.028699 [CA 5] Center 29 (0~59) winsize 60
797 11:35:46.028782
798 11:35:46.032089 [CATrainingPosCal] consider 1 rank data
799 11:35:46.035447 u2DelayCellTimex100 = 735/100 ps
800 11:35:46.039010 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
801 11:35:46.045680 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
802 11:35:46.048904 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
803 11:35:46.052424 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
804 11:35:46.055717 CA4 delay=25 (-3~54),Diff = 1 PI (1 cell)
805 11:35:46.058808 CA5 delay=29 (0~59),Diff = 5 PI (6 cell)
806 11:35:46.058892
807 11:35:46.062493 CA PerBit enable=1, Macro0, CA PI delay=24
808 11:35:46.065812 === u2Vref_new: 0x5e --> 0x3d
809 11:35:46.065896
810 11:35:46.068988 Vref(ca) range 1: 30
811 11:35:46.069071
812 11:35:46.069135 CS Dly= 9 (40-0-32)
813 11:35:46.072511 Write Rank0 MR13 =0xd8
814 11:35:46.072595 Write Rank0 MR13 =0xd8
815 11:35:46.075594 Write Rank0 MR12 =0x5e
816 11:35:46.079094 Write Rank1 MR13 =0x59
817 11:35:46.079177 ==
818 11:35:46.082494 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
819 11:35:46.086036 fsp= 1, odt_onoff= 1, Byte mode= 0
820 11:35:46.086119 ==
821 11:35:46.089388 === u2Vref_new: 0x56 --> 0x2d
822 11:35:46.092326 === u2Vref_new: 0x58 --> 0x38
823 11:35:46.095680 === u2Vref_new: 0x5a --> 0x39
824 11:35:46.099115 === u2Vref_new: 0x5c --> 0x3c
825 11:35:46.102446 === u2Vref_new: 0x5e --> 0x3d
826 11:35:46.106166 === u2Vref_new: 0x60 --> 0xa0
827 11:35:46.109052 [CA 0] Center 36 (9~63) winsize 55
828 11:35:46.112282 [CA 1] Center 36 (9~63) winsize 55
829 11:35:46.115845 [CA 2] Center 31 (2~60) winsize 59
830 11:35:46.115929 [CA 3] Center 25 (-3~54) winsize 58
831 11:35:46.119469 [CA 4] Center 26 (-2~54) winsize 57
832 11:35:46.122708 [CA 5] Center 31 (2~61) winsize 60
833 11:35:46.122792
834 11:35:46.125972 [CATrainingPosCal] consider 2 rank data
835 11:35:46.129512 u2DelayCellTimex100 = 735/100 ps
836 11:35:46.132968 CA0 delay=36 (9~63),Diff = 12 PI (15 cell)
837 11:35:46.139677 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
838 11:35:46.142852 CA2 delay=30 (2~58),Diff = 6 PI (7 cell)
839 11:35:46.146071 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
840 11:35:46.149803 CA4 delay=26 (-2~54),Diff = 2 PI (2 cell)
841 11:35:46.153107 CA5 delay=30 (2~59),Diff = 6 PI (7 cell)
842 11:35:46.153191
843 11:35:46.156084 CA PerBit enable=1, Macro0, CA PI delay=24
844 11:35:46.159303 === u2Vref_new: 0x5c --> 0x3c
845 11:35:46.159386
846 11:35:46.162936 Vref(ca) range 1: 28
847 11:35:46.163020
848 11:35:46.163085 CS Dly= 7 (38-0-32)
849 11:35:46.165920 Write Rank1 MR13 =0xd8
850 11:35:46.166004 Write Rank1 MR13 =0xd8
851 11:35:46.169320 Write Rank1 MR12 =0x5c
852 11:35:46.173021 [RankSwap] Rank num 2, (Multi 1), Rank 0
853 11:35:46.176192 Write Rank0 MR2 =0xad
854 11:35:46.176275 [Write Leveling]
855 11:35:46.179824 delay byte0 byte1 byte2 byte3
856 11:35:46.179908
857 11:35:46.182827 10 0 0
858 11:35:46.182912 11 0 0
859 11:35:46.182978 12 0 0
860 11:35:46.186051 13 0 0
861 11:35:46.186136 14 0 0
862 11:35:46.189611 15 0 0
863 11:35:46.189697 16 0 0
864 11:35:46.189763 17 0 0
865 11:35:46.192857 18 0 0
866 11:35:46.192942 19 0 0
867 11:35:46.196307 20 0 0
868 11:35:46.196392 21 0 0
869 11:35:46.196466 22 0 0
870 11:35:46.199650 23 0 0
871 11:35:46.199735 24 0 ff
872 11:35:46.202848 25 0 ff
873 11:35:46.202934 26 0 ff
874 11:35:46.206224 27 0 ff
875 11:35:46.206309 28 0 ff
876 11:35:46.209430 29 0 ff
877 11:35:46.209515 30 0 ff
878 11:35:46.209581 31 0 ff
879 11:35:46.213139 32 ff ff
880 11:35:46.213224 33 ff ff
881 11:35:46.216141 34 ff ff
882 11:35:46.216226 35 ff ff
883 11:35:46.219594 36 ff ff
884 11:35:46.219679 37 ff ff
885 11:35:46.222912 38 ff ff
886 11:35:46.226537 pass bytecount = 0xff (0xff: all bytes pass)
887 11:35:46.226621
888 11:35:46.226685 DQS0 dly: 32
889 11:35:46.229817 DQS1 dly: 24
890 11:35:46.229901 Write Rank0 MR2 =0x2d
891 11:35:46.233223 [RankSwap] Rank num 2, (Multi 1), Rank 0
892 11:35:46.236384 Write Rank0 MR1 =0xd6
893 11:35:46.236473 [Gating]
894 11:35:46.236538 ==
895 11:35:46.243422 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
896 11:35:46.247038 fsp= 1, odt_onoff= 1, Byte mode= 0
897 11:35:46.247122 ==
898 11:35:46.249875 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
899 11:35:46.253375 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
900 11:35:46.260338 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
901 11:35:46.263407 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
902 11:35:46.266589 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
903 11:35:46.270067 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
904 11:35:46.276901 3 1 24 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
905 11:35:46.279951 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
906 11:35:46.283712 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
907 11:35:46.290127 3 2 4 |3534 707 |(11 11)(11 11) |(0 0)(1 1)| 0
908 11:35:46.293419 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
909 11:35:46.297065 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
910 11:35:46.303460 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
911 11:35:46.307052 3 2 20 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 11:35:46.310160 3 2 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
913 11:35:46.313709 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
914 11:35:46.320561 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
915 11:35:46.323865 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
916 11:35:46.327538 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
917 11:35:46.333726 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
918 11:35:46.337105 [Byte 1] Lead/lag falling Transition (3, 3, 12)
919 11:35:46.340552 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
920 11:35:46.347035 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
921 11:35:46.350392 3 3 24 |201f 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
922 11:35:46.353851 3 3 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
923 11:35:46.357513 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
924 11:35:46.364255 3 4 4 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
925 11:35:46.367102 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 11:35:46.370556 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 11:35:46.377228 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 11:35:46.380429 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 11:35:46.384039 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 11:35:46.390626 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 11:35:46.394483 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 11:35:46.397268 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 11:35:46.400813 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 11:35:46.407225 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 11:35:46.410887 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 11:35:46.414281 [Byte 0] Lead/lag falling Transition (3, 5, 16)
937 11:35:46.420631 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
938 11:35:46.424325 [Byte 0] Lead/lag Transition tap number (2)
939 11:35:46.427801 [Byte 1] Lead/lag falling Transition (3, 5, 20)
940 11:35:46.431149 3 5 24 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
941 11:35:46.437577 3 5 28 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
942 11:35:46.437663 [Byte 0]First pass (3, 5, 28)
943 11:35:46.444141 [Byte 1] Lead/lag Transition tap number (3)
944 11:35:46.447875 3 6 0 |4646 1e1e |(0 0)(11 11) |(0 0)(0 0)| 0
945 11:35:46.451049 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
946 11:35:46.454816 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 11:35:46.457613 [Byte 1]First pass (3, 6, 8)
948 11:35:46.461163 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 11:35:46.464511 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 11:35:46.471016 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 11:35:46.474531 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 11:35:46.477550 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 11:35:46.480812 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 11:35:46.484503 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 11:35:46.491199 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 11:35:46.494357 All bytes gating window > 1UI, Early break!
957 11:35:46.494442
958 11:35:46.497458 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
959 11:35:46.497543
960 11:35:46.501141 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 26)
961 11:35:46.501227
962 11:35:46.501293
963 11:35:46.501353
964 11:35:46.504233 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
965 11:35:46.504318
966 11:35:46.510932 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
967 11:35:46.511018
968 11:35:46.511084
969 11:35:46.511144 Write Rank0 MR1 =0x56
970 11:35:46.511202
971 11:35:46.514391 best RODT dly(2T, 0.5T) = (2, 2)
972 11:35:46.514476
973 11:35:46.517569 best RODT dly(2T, 0.5T) = (2, 2)
974 11:35:46.517654 ==
975 11:35:46.524266 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
976 11:35:46.527749 fsp= 1, odt_onoff= 1, Byte mode= 0
977 11:35:46.527835 ==
978 11:35:46.531489 Start DQ dly to find pass range UseTestEngine =0
979 11:35:46.534392 x-axis: bit #, y-axis: DQ dly (-127~63)
980 11:35:46.538231 RX Vref Scan = 0
981 11:35:46.538316 -26, [0] xxxxxxxx xxxxxxxx [MSB]
982 11:35:46.541433 -25, [0] xxxxxxxx xxxxxxxx [MSB]
983 11:35:46.544513 -24, [0] xxxxxxxx xxxxxxxx [MSB]
984 11:35:46.548196 -23, [0] xxxxxxxx xxxxxxxx [MSB]
985 11:35:46.551116 -22, [0] xxxxxxxx xxxxxxxx [MSB]
986 11:35:46.554367 -21, [0] xxxxxxxx xxxxxxxx [MSB]
987 11:35:46.557814 -20, [0] xxxxxxxx xxxxxxxx [MSB]
988 11:35:46.560946 -19, [0] xxxxxxxx xxxxxxxx [MSB]
989 11:35:46.561033 -18, [0] xxxxxxxx xxxxxxxx [MSB]
990 11:35:46.564605 -17, [0] xxxxxxxx xxxxxxxx [MSB]
991 11:35:46.567761 -16, [0] xxxxxxxx xxxxxxxx [MSB]
992 11:35:46.571254 -15, [0] xxxxxxxx xxxxxxxx [MSB]
993 11:35:46.574292 -14, [0] xxxxxxxx xxxxxxxx [MSB]
994 11:35:46.577943 -13, [0] xxxxxxxx xxxxxxxx [MSB]
995 11:35:46.581010 -12, [0] xxxxxxxx xxxxxxxx [MSB]
996 11:35:46.584587 -11, [0] xxxxxxxx xxxxxxxx [MSB]
997 11:35:46.584674 -10, [0] xxxxxxxx xxxxxxxx [MSB]
998 11:35:46.588315 -9, [0] xxxxxxxx xxxxxxxx [MSB]
999 11:35:46.591274 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1000 11:35:46.594664 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1001 11:35:46.597985 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1002 11:35:46.601470 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1003 11:35:46.604733 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1004 11:35:46.604820 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1005 11:35:46.608328 -2, [0] xxxoxxxx oxxxxxxx [MSB]
1006 11:35:46.611515 -1, [0] xxxoxxxx ooxxxxxx [MSB]
1007 11:35:46.614836 0, [0] xxxoxoxx ooxoxxxx [MSB]
1008 11:35:46.618291 1, [0] xxxoxoxx ooxoxoxx [MSB]
1009 11:35:46.621439 2, [0] xxxoxoox ooxoooxx [MSB]
1010 11:35:46.621525 3, [0] xxxoxoox ooxoooox [MSB]
1011 11:35:46.624567 4, [0] xoooxooo ooxooooo [MSB]
1012 11:35:46.627984 5, [0] xooooooo ooxooooo [MSB]
1013 11:35:46.631589 6, [0] xooooooo ooxooooo [MSB]
1014 11:35:46.634882 7, [0] oooooooo ooxooooo [MSB]
1015 11:35:46.638081 32, [0] oooxoooo oooooooo [MSB]
1016 11:35:46.638168 33, [0] oooxoooo xooooooo [MSB]
1017 11:35:46.641580 34, [0] oooxoooo xooooooo [MSB]
1018 11:35:46.644855 35, [0] oooxoooo xooooooo [MSB]
1019 11:35:46.648412 36, [0] oooxoxoo xooxoooo [MSB]
1020 11:35:46.651455 37, [0] oooxoxxx xxoxoooo [MSB]
1021 11:35:46.655166 38, [0] oooxoxxx xxoxxoxo [MSB]
1022 11:35:46.655254 39, [0] oooxxxxx xxoxxxxo [MSB]
1023 11:35:46.658122 40, [0] xooxxxxx xxoxxxxo [MSB]
1024 11:35:46.661793 41, [0] xxxxxxxx xxoxxxxo [MSB]
1025 11:35:46.664768 42, [0] xxxxxxxx xxoxxxxx [MSB]
1026 11:35:46.668072 43, [0] xxxxxxxx xxoxxxxx [MSB]
1027 11:35:46.671928 44, [0] xxxxxxxx xxxxxxxx [MSB]
1028 11:35:46.674995 iDelay=44, Bit 0, Center 23 (7 ~ 39) 33
1029 11:35:46.678394 iDelay=44, Bit 1, Center 22 (4 ~ 40) 37
1030 11:35:46.681769 iDelay=44, Bit 2, Center 22 (4 ~ 40) 37
1031 11:35:46.685034 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
1032 11:35:46.688404 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
1033 11:35:46.692322 iDelay=44, Bit 5, Center 17 (0 ~ 35) 36
1034 11:35:46.694904 iDelay=44, Bit 6, Center 19 (2 ~ 36) 35
1035 11:35:46.698225 iDelay=44, Bit 7, Center 20 (4 ~ 36) 33
1036 11:35:46.701454 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
1037 11:35:46.705205 iDelay=44, Bit 9, Center 17 (-1 ~ 36) 38
1038 11:35:46.708515 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
1039 11:35:46.715047 iDelay=44, Bit 11, Center 17 (0 ~ 35) 36
1040 11:35:46.718141 iDelay=44, Bit 12, Center 19 (2 ~ 37) 36
1041 11:35:46.721667 iDelay=44, Bit 13, Center 19 (1 ~ 38) 38
1042 11:35:46.724986 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
1043 11:35:46.728685 iDelay=44, Bit 15, Center 22 (4 ~ 41) 38
1044 11:35:46.728770 ==
1045 11:35:46.731662 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1046 11:35:46.735357 fsp= 1, odt_onoff= 1, Byte mode= 0
1047 11:35:46.735442 ==
1048 11:35:46.738504 DQS Delay:
1049 11:35:46.738588 DQS0 = 0, DQS1 = 0
1050 11:35:46.742425 DQM Delay:
1051 11:35:46.742509 DQM0 = 19, DQM1 = 19
1052 11:35:46.742575 DQ Delay:
1053 11:35:46.745228 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =14
1054 11:35:46.748651 DQ4 =21, DQ5 =17, DQ6 =19, DQ7 =20
1055 11:35:46.752200 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =17
1056 11:35:46.755440 DQ12 =19, DQ13 =19, DQ14 =20, DQ15 =22
1057 11:35:46.755524
1058 11:35:46.755589
1059 11:35:46.758769 DramC Write-DBI off
1060 11:35:46.758853 ==
1061 11:35:46.765421 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1062 11:35:46.765506 fsp= 1, odt_onoff= 1, Byte mode= 0
1063 11:35:46.768633 ==
1064 11:35:46.771919 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1065 11:35:46.772003
1066 11:35:46.775109 Begin, DQ Scan Range 920~1176
1067 11:35:46.775194
1068 11:35:46.775258
1069 11:35:46.775318 TX Vref Scan disable
1070 11:35:46.778535 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1071 11:35:46.782343 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1072 11:35:46.788827 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1073 11:35:46.791982 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1074 11:35:46.795192 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1075 11:35:46.798581 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1076 11:35:46.801885 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1077 11:35:46.805391 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1078 11:35:46.808900 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1079 11:35:46.812120 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1080 11:35:46.815441 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1081 11:35:46.819099 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1082 11:35:46.822197 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1083 11:35:46.825380 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1084 11:35:46.828848 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1085 11:35:46.832202 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1086 11:35:46.835526 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1087 11:35:46.838838 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1088 11:35:46.841947 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1089 11:35:46.848560 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1090 11:35:46.852310 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1091 11:35:46.855556 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1092 11:35:46.858908 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1093 11:35:46.862540 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1094 11:35:46.865675 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1095 11:35:46.868675 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1096 11:35:46.872321 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1097 11:35:46.875918 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1098 11:35:46.879063 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1099 11:35:46.882128 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1100 11:35:46.885974 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1101 11:35:46.889051 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1102 11:35:46.892709 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1103 11:35:46.895745 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1104 11:35:46.898815 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1105 11:35:46.902377 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1106 11:35:46.905859 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1107 11:35:46.912461 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1108 11:35:46.915959 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1109 11:35:46.919245 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1110 11:35:46.922435 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1111 11:35:46.925534 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1112 11:35:46.929223 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1113 11:35:46.932389 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1114 11:35:46.936836 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1115 11:35:46.939114 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1116 11:35:46.943066 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1117 11:35:46.945855 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1118 11:35:46.949247 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1119 11:35:46.952389 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1120 11:35:46.955888 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1121 11:35:46.958929 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1122 11:35:46.962558 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1123 11:35:46.966271 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1124 11:35:46.969667 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1125 11:35:46.972449 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1126 11:35:46.975830 976 |3 6 16|[0] xoxooooo oooooooo [MSB]
1127 11:35:46.983287 985 |3 6 25|[0] oooooooo xooooooo [MSB]
1128 11:35:46.986837 986 |3 6 26|[0] oooooooo xooooooo [MSB]
1129 11:35:46.989896 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1130 11:35:46.993665 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1131 11:35:46.996605 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1132 11:35:46.999731 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1133 11:35:47.003311 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1134 11:35:47.006572 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1135 11:35:47.009887 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1136 11:35:47.013431 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1137 11:35:47.017131 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1138 11:35:47.020050 996 |3 6 36|[0] oooxxxxx xxxxxxxx [MSB]
1139 11:35:47.023411 997 |3 6 37|[0] xxxxxxxx xxxxxxxx [MSB]
1140 11:35:47.026550 Byte0, DQ PI dly=984, DQM PI dly= 984
1141 11:35:47.033332 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1142 11:35:47.033418
1143 11:35:47.036822 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1144 11:35:47.036908
1145 11:35:47.040032 Byte1, DQ PI dly=977, DQM PI dly= 977
1146 11:35:47.043143 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1147 11:35:47.043228
1148 11:35:47.049858 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1149 11:35:47.049945
1150 11:35:47.050022 ==
1151 11:35:47.053361 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1152 11:35:47.056669 fsp= 1, odt_onoff= 1, Byte mode= 0
1153 11:35:47.056753 ==
1154 11:35:47.059927 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1155 11:35:47.063646
1156 11:35:47.063722 Begin, DQ Scan Range 953~1017
1157 11:35:47.066671 Write Rank0 MR14 =0x0
1158 11:35:47.074807
1159 11:35:47.074893 CH=0, VrefRange= 0, VrefLevel = 0
1160 11:35:47.081682 TX Bit0 (978~993) 16 985, Bit8 (967~978) 12 972,
1161 11:35:47.084700 TX Bit1 (977~992) 16 984, Bit9 (969~983) 15 976,
1162 11:35:47.091885 TX Bit2 (979~993) 15 986, Bit10 (975~987) 13 981,
1163 11:35:47.095028 TX Bit3 (974~985) 12 979, Bit11 (968~982) 15 975,
1164 11:35:47.098060 TX Bit4 (978~991) 14 984, Bit12 (971~983) 13 977,
1165 11:35:47.104966 TX Bit5 (976~989) 14 982, Bit13 (970~983) 14 976,
1166 11:35:47.108015 TX Bit6 (977~989) 13 983, Bit14 (969~984) 16 976,
1167 11:35:47.111617 TX Bit7 (978~991) 14 984, Bit15 (975~986) 12 980,
1168 11:35:47.111702
1169 11:35:47.114957 Write Rank0 MR14 =0x2
1170 11:35:47.123275
1171 11:35:47.123359 CH=0, VrefRange= 0, VrefLevel = 2
1172 11:35:47.129464 TX Bit0 (978~993) 16 985, Bit8 (967~979) 13 973,
1173 11:35:47.132891 TX Bit1 (977~992) 16 984, Bit9 (969~984) 16 976,
1174 11:35:47.140124 TX Bit2 (978~993) 16 985, Bit10 (975~988) 14 981,
1175 11:35:47.143001 TX Bit3 (974~986) 13 980, Bit11 (968~982) 15 975,
1176 11:35:47.146273 TX Bit4 (977~992) 16 984, Bit12 (970~984) 15 977,
1177 11:35:47.152989 TX Bit5 (976~991) 16 983, Bit13 (969~984) 16 976,
1178 11:35:47.156672 TX Bit6 (977~991) 15 984, Bit14 (969~985) 17 977,
1179 11:35:47.160221 TX Bit7 (978~992) 15 985, Bit15 (974~986) 13 980,
1180 11:35:47.160306
1181 11:35:47.162986 Write Rank0 MR14 =0x4
1182 11:35:47.171035
1183 11:35:47.171119 CH=0, VrefRange= 0, VrefLevel = 4
1184 11:35:47.177642 TX Bit0 (978~993) 16 985, Bit8 (967~981) 15 974,
1185 11:35:47.180931 TX Bit1 (977~993) 17 985, Bit9 (969~984) 16 976,
1186 11:35:47.187976 TX Bit2 (978~993) 16 985, Bit10 (975~989) 15 982,
1187 11:35:47.191189 TX Bit3 (973~988) 16 980, Bit11 (968~983) 16 975,
1188 11:35:47.194503 TX Bit4 (977~992) 16 984, Bit12 (970~984) 15 977,
1189 11:35:47.201386 TX Bit5 (975~991) 17 983, Bit13 (969~984) 16 976,
1190 11:35:47.204446 TX Bit6 (976~991) 16 983, Bit14 (969~985) 17 977,
1191 11:35:47.208011 TX Bit7 (977~992) 16 984, Bit15 (974~988) 15 981,
1192 11:35:47.208096
1193 11:35:47.211160 Write Rank0 MR14 =0x6
1194 11:35:47.219444
1195 11:35:47.219528 CH=0, VrefRange= 0, VrefLevel = 6
1196 11:35:47.225985 TX Bit0 (977~994) 18 985, Bit8 (967~982) 16 974,
1197 11:35:47.229617 TX Bit1 (977~993) 17 985, Bit9 (968~985) 18 976,
1198 11:35:47.236384 TX Bit2 (978~994) 17 986, Bit10 (974~990) 17 982,
1199 11:35:47.239602 TX Bit3 (973~989) 17 981, Bit11 (968~983) 16 975,
1200 11:35:47.243382 TX Bit4 (977~992) 16 984, Bit12 (969~985) 17 977,
1201 11:35:47.249830 TX Bit5 (975~992) 18 983, Bit13 (969~985) 17 977,
1202 11:35:47.252910 TX Bit6 (976~992) 17 984, Bit14 (969~986) 18 977,
1203 11:35:47.256182 TX Bit7 (977~993) 17 985, Bit15 (973~988) 16 980,
1204 11:35:47.256267
1205 11:35:47.259522 Write Rank0 MR14 =0x8
1206 11:35:47.315628
1207 11:35:47.315716 CH=0, VrefRange= 0, VrefLevel = 8
1208 11:35:47.316223 TX Bit0 (977~995) 19 986, Bit8 (966~982) 17 974,
1209 11:35:47.316499 TX Bit1 (977~994) 18 985, Bit9 (968~985) 18 976,
1210 11:35:47.316756 TX Bit2 (977~994) 18 985, Bit10 (974~990) 17 982,
1211 11:35:47.316824 TX Bit3 (972~988) 17 980, Bit11 (967~984) 18 975,
1212 11:35:47.316884 TX Bit4 (977~993) 17 985, Bit12 (969~985) 17 977,
1213 11:35:47.316954 TX Bit5 (975~992) 18 983, Bit13 (969~985) 17 977,
1214 11:35:47.317200 TX Bit6 (976~992) 17 984, Bit14 (968~986) 19 977,
1215 11:35:47.317265 TX Bit7 (977~993) 17 985, Bit15 (973~989) 17 981,
1216 11:35:47.317324
1217 11:35:47.317380 Write Rank0 MR14 =0xa
1218 11:35:47.317434
1219 11:35:47.361726 CH=0, VrefRange= 0, VrefLevel = 10
1220 11:35:47.361813 TX Bit0 (977~995) 19 986, Bit8 (967~983) 17 975,
1221 11:35:47.362064 TX Bit1 (977~994) 18 985, Bit9 (968~986) 19 977,
1222 11:35:47.362132 TX Bit2 (977~995) 19 986, Bit10 (973~990) 18 981,
1223 11:35:47.362193 TX Bit3 (972~990) 19 981, Bit11 (967~984) 18 975,
1224 11:35:47.362438 TX Bit4 (977~994) 18 985, Bit12 (969~986) 18 977,
1225 11:35:47.362691 TX Bit5 (975~992) 18 983, Bit13 (969~986) 18 977,
1226 11:35:47.362762 TX Bit6 (976~993) 18 984, Bit14 (968~987) 20 977,
1227 11:35:47.363342 TX Bit7 (977~993) 17 985, Bit15 (973~990) 18 981,
1228 11:35:47.363427
1229 11:35:47.367809 Write Rank0 MR14 =0xc
1230 11:35:47.367892
1231 11:35:47.367957 CH=0, VrefRange= 0, VrefLevel = 12
1232 11:35:47.371096 TX Bit0 (977~996) 20 986, Bit8 (966~983) 18 974,
1233 11:35:47.377590 TX Bit1 (976~995) 20 985, Bit9 (968~986) 19 977,
1234 11:35:47.381115 TX Bit2 (977~996) 20 986, Bit10 (972~991) 20 981,
1235 11:35:47.384113 TX Bit3 (972~991) 20 981, Bit11 (967~984) 18 975,
1236 11:35:47.390986 TX Bit4 (976~994) 19 985, Bit12 (969~986) 18 977,
1237 11:35:47.394478 TX Bit5 (974~993) 20 983, Bit13 (968~986) 19 977,
1238 11:35:47.397894 TX Bit6 (975~993) 19 984, Bit14 (968~988) 21 978,
1239 11:35:47.404203 TX Bit7 (977~994) 18 985, Bit15 (972~990) 19 981,
1240 11:35:47.404289
1241 11:35:47.404355 Write Rank0 MR14 =0xe
1242 11:35:47.414180
1243 11:35:47.417667 CH=0, VrefRange= 0, VrefLevel = 14
1244 11:35:47.420872 TX Bit0 (977~997) 21 987, Bit8 (966~983) 18 974,
1245 11:35:47.424656 TX Bit1 (976~996) 21 986, Bit9 (968~987) 20 977,
1246 11:35:47.430877 TX Bit2 (977~997) 21 987, Bit10 (972~991) 20 981,
1247 11:35:47.434378 TX Bit3 (971~991) 21 981, Bit11 (967~985) 19 976,
1248 11:35:47.437841 TX Bit4 (976~995) 20 985, Bit12 (968~987) 20 977,
1249 11:35:47.444599 TX Bit5 (974~993) 20 983, Bit13 (968~987) 20 977,
1250 11:35:47.447683 TX Bit6 (975~993) 19 984, Bit14 (968~989) 22 978,
1251 11:35:47.451199 TX Bit7 (976~994) 19 985, Bit15 (972~991) 20 981,
1252 11:35:47.451288
1253 11:35:47.454781 Write Rank0 MR14 =0x10
1254 11:35:47.463479
1255 11:35:47.466716 CH=0, VrefRange= 0, VrefLevel = 16
1256 11:35:47.470402 TX Bit0 (977~998) 22 987, Bit8 (965~984) 20 974,
1257 11:35:47.473431 TX Bit1 (976~996) 21 986, Bit9 (968~987) 20 977,
1258 11:35:47.480571 TX Bit2 (977~998) 22 987, Bit10 (971~992) 22 981,
1259 11:35:47.483489 TX Bit3 (971~992) 22 981, Bit11 (967~985) 19 976,
1260 11:35:47.487521 TX Bit4 (976~995) 20 985, Bit12 (968~988) 21 978,
1261 11:35:47.493703 TX Bit5 (974~994) 21 984, Bit13 (968~988) 21 978,
1262 11:35:47.497428 TX Bit6 (975~994) 20 984, Bit14 (968~990) 23 979,
1263 11:35:47.500733 TX Bit7 (976~995) 20 985, Bit15 (971~991) 21 981,
1264 11:35:47.500804
1265 11:35:47.503828 Write Rank0 MR14 =0x12
1266 11:35:47.512640
1267 11:35:47.516099 CH=0, VrefRange= 0, VrefLevel = 18
1268 11:35:47.519224 TX Bit0 (977~998) 22 987, Bit8 (965~984) 20 974,
1269 11:35:47.522957 TX Bit1 (976~997) 22 986, Bit9 (967~988) 22 977,
1270 11:35:47.529380 TX Bit2 (977~998) 22 987, Bit10 (972~992) 21 982,
1271 11:35:47.532480 TX Bit3 (970~992) 23 981, Bit11 (966~986) 21 976,
1272 11:35:47.536083 TX Bit4 (976~996) 21 986, Bit12 (968~988) 21 978,
1273 11:35:47.542885 TX Bit5 (973~994) 22 983, Bit13 (968~988) 21 978,
1274 11:35:47.545785 TX Bit6 (975~995) 21 985, Bit14 (967~990) 24 978,
1275 11:35:47.549377 TX Bit7 (976~996) 21 986, Bit15 (970~991) 22 980,
1276 11:35:47.549448
1277 11:35:47.552584 Write Rank0 MR14 =0x14
1278 11:35:47.562014
1279 11:35:47.565393 CH=0, VrefRange= 0, VrefLevel = 20
1280 11:35:47.568911 TX Bit0 (976~999) 24 987, Bit8 (965~985) 21 975,
1281 11:35:47.572512 TX Bit1 (976~998) 23 987, Bit9 (967~989) 23 978,
1282 11:35:47.579143 TX Bit2 (976~998) 23 987, Bit10 (971~992) 22 981,
1283 11:35:47.582363 TX Bit3 (970~992) 23 981, Bit11 (966~986) 21 976,
1284 11:35:47.585296 TX Bit4 (976~997) 22 986, Bit12 (968~989) 22 978,
1285 11:35:47.591874 TX Bit5 (973~994) 22 983, Bit13 (968~989) 22 978,
1286 11:35:47.595286 TX Bit6 (974~995) 22 984, Bit14 (967~990) 24 978,
1287 11:35:47.599270 TX Bit7 (976~996) 21 986, Bit15 (971~992) 22 981,
1288 11:35:47.599345
1289 11:35:47.602445 Write Rank0 MR14 =0x16
1290 11:35:47.611586
1291 11:35:47.614742 CH=0, VrefRange= 0, VrefLevel = 22
1292 11:35:47.618134 TX Bit0 (976~999) 24 987, Bit8 (965~985) 21 975,
1293 11:35:47.621540 TX Bit1 (975~998) 24 986, Bit9 (967~989) 23 978,
1294 11:35:47.628136 TX Bit2 (976~999) 24 987, Bit10 (970~992) 23 981,
1295 11:35:47.631421 TX Bit3 (969~992) 24 980, Bit11 (966~988) 23 977,
1296 11:35:47.634755 TX Bit4 (975~997) 23 986, Bit12 (968~990) 23 979,
1297 11:35:47.641325 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1298 11:35:47.644879 TX Bit6 (974~995) 22 984, Bit14 (967~990) 24 978,
1299 11:35:47.648099 TX Bit7 (976~997) 22 986, Bit15 (970~992) 23 981,
1300 11:35:47.648195
1301 11:35:47.651598 Write Rank0 MR14 =0x18
1302 11:35:47.660903
1303 11:35:47.664036 CH=0, VrefRange= 0, VrefLevel = 24
1304 11:35:47.667439 TX Bit0 (976~999) 24 987, Bit8 (963~986) 24 974,
1305 11:35:47.671016 TX Bit1 (976~999) 24 987, Bit9 (967~989) 23 978,
1306 11:35:47.677755 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1307 11:35:47.680981 TX Bit3 (970~993) 24 981, Bit11 (965~989) 25 977,
1308 11:35:47.684221 TX Bit4 (975~998) 24 986, Bit12 (968~990) 23 979,
1309 11:35:47.690648 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1310 11:35:47.694285 TX Bit6 (974~996) 23 985, Bit14 (967~991) 25 979,
1311 11:35:47.697400 TX Bit7 (976~997) 22 986, Bit15 (969~992) 24 980,
1312 11:35:47.697470
1313 11:35:47.700548 Write Rank0 MR14 =0x1a
1314 11:35:47.710494
1315 11:35:47.713800 CH=0, VrefRange= 0, VrefLevel = 26
1316 11:35:47.716897 TX Bit0 (976~1000) 25 988, Bit8 (964~987) 24 975,
1317 11:35:47.720388 TX Bit1 (975~999) 25 987, Bit9 (967~990) 24 978,
1318 11:35:47.727078 TX Bit2 (976~999) 24 987, Bit10 (970~993) 24 981,
1319 11:35:47.730211 TX Bit3 (969~993) 25 981, Bit11 (965~989) 25 977,
1320 11:35:47.733508 TX Bit4 (975~998) 24 986, Bit12 (968~990) 23 979,
1321 11:35:47.740252 TX Bit5 (971~996) 26 983, Bit13 (967~990) 24 978,
1322 11:35:47.743840 TX Bit6 (973~996) 24 984, Bit14 (967~991) 25 979,
1323 11:35:47.747504 TX Bit7 (975~998) 24 986, Bit15 (969~993) 25 981,
1324 11:35:47.747610
1325 11:35:47.750450 Write Rank0 MR14 =0x1c
1326 11:35:47.759852
1327 11:35:47.763237 CH=0, VrefRange= 0, VrefLevel = 28
1328 11:35:47.766637 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1329 11:35:47.770017 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1330 11:35:47.776759 TX Bit2 (975~1000) 26 987, Bit10 (970~994) 25 982,
1331 11:35:47.779856 TX Bit3 (969~993) 25 981, Bit11 (965~988) 24 976,
1332 11:35:47.783228 TX Bit4 (975~999) 25 987, Bit12 (967~991) 25 979,
1333 11:35:47.790218 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1334 11:35:47.793403 TX Bit6 (972~998) 27 985, Bit14 (967~991) 25 979,
1335 11:35:47.796655 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1336 11:35:47.796757
1337 11:35:47.799887 Write Rank0 MR14 =0x1e
1338 11:35:47.809797
1339 11:35:47.809894 CH=0, VrefRange= 0, VrefLevel = 30
1340 11:35:47.816397 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1341 11:35:47.819689 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1342 11:35:47.826344 TX Bit2 (975~1000) 26 987, Bit10 (970~994) 25 982,
1343 11:35:47.829863 TX Bit3 (969~993) 25 981, Bit11 (965~988) 24 976,
1344 11:35:47.833286 TX Bit4 (975~999) 25 987, Bit12 (967~991) 25 979,
1345 11:35:47.840058 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1346 11:35:47.842923 TX Bit6 (972~998) 27 985, Bit14 (967~991) 25 979,
1347 11:35:47.846449 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1348 11:35:47.846521
1349 11:35:47.849794 Write Rank0 MR14 =0x20
1350 11:35:47.859258
1351 11:35:47.862949 CH=0, VrefRange= 0, VrefLevel = 32
1352 11:35:47.866240 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1353 11:35:47.869236 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1354 11:35:47.876009 TX Bit2 (975~1000) 26 987, Bit10 (970~994) 25 982,
1355 11:35:47.879550 TX Bit3 (969~993) 25 981, Bit11 (965~988) 24 976,
1356 11:35:47.882884 TX Bit4 (975~999) 25 987, Bit12 (967~991) 25 979,
1357 11:35:47.889230 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1358 11:35:47.892857 TX Bit6 (972~998) 27 985, Bit14 (967~991) 25 979,
1359 11:35:47.896200 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1360 11:35:47.899245
1361 11:35:47.899334 Write Rank0 MR14 =0x22
1362 11:35:47.908797
1363 11:35:47.908882 CH=0, VrefRange= 0, VrefLevel = 34
1364 11:35:47.915595 TX Bit0 (976~1000) 25 988, Bit8 (963~987) 25 975,
1365 11:35:47.919018 TX Bit1 (975~999) 25 987, Bit9 (967~989) 23 978,
1366 11:35:47.926099 TX Bit2 (975~1000) 26 987, Bit10 (970~994) 25 982,
1367 11:35:47.928966 TX Bit3 (969~993) 25 981, Bit11 (965~988) 24 976,
1368 11:35:47.933238 TX Bit4 (975~999) 25 987, Bit12 (967~991) 25 979,
1369 11:35:47.939569 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1370 11:35:47.942731 TX Bit6 (972~998) 27 985, Bit14 (967~991) 25 979,
1371 11:35:47.945846 TX Bit7 (975~999) 25 987, Bit15 (969~993) 25 981,
1372 11:35:47.945931
1373 11:35:47.949097
1374 11:35:47.949181 TX Vref found, early break! 376< 378
1375 11:35:47.955907 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1376 11:35:47.959695 u1DelayCellOfst[0]=9 cells (7 PI)
1377 11:35:47.962415 u1DelayCellOfst[1]=7 cells (6 PI)
1378 11:35:47.966127 u1DelayCellOfst[2]=7 cells (6 PI)
1379 11:35:47.969201 u1DelayCellOfst[3]=0 cells (0 PI)
1380 11:35:47.969286 u1DelayCellOfst[4]=7 cells (6 PI)
1381 11:35:47.972881 u1DelayCellOfst[5]=2 cells (2 PI)
1382 11:35:47.975897 u1DelayCellOfst[6]=5 cells (4 PI)
1383 11:35:47.979507 u1DelayCellOfst[7]=7 cells (6 PI)
1384 11:35:47.982998 Byte0, DQ PI dly=981, DQM PI dly= 984
1385 11:35:47.986147 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1386 11:35:47.986232
1387 11:35:47.992933 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1388 11:35:47.993023
1389 11:35:47.996274 u1DelayCellOfst[8]=0 cells (0 PI)
1390 11:35:47.999254 u1DelayCellOfst[9]=3 cells (3 PI)
1391 11:35:48.002815 u1DelayCellOfst[10]=9 cells (7 PI)
1392 11:35:48.002900 u1DelayCellOfst[11]=1 cells (1 PI)
1393 11:35:48.006200 u1DelayCellOfst[12]=5 cells (4 PI)
1394 11:35:48.009670 u1DelayCellOfst[13]=3 cells (3 PI)
1395 11:35:48.012900 u1DelayCellOfst[14]=5 cells (4 PI)
1396 11:35:48.016271 u1DelayCellOfst[15]=7 cells (6 PI)
1397 11:35:48.019644 Byte1, DQ PI dly=975, DQM PI dly= 978
1398 11:35:48.023270 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1399 11:35:48.026284
1400 11:35:48.029707 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1401 11:35:48.029793
1402 11:35:48.029858 Write Rank0 MR14 =0x1c
1403 11:35:48.032975
1404 11:35:48.033059 Final TX Range 0 Vref 28
1405 11:35:48.033128
1406 11:35:48.039803 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1407 11:35:48.039889
1408 11:35:48.046241 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1409 11:35:48.053111 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1410 11:35:48.059710 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1411 11:35:48.063227 Write Rank0 MR3 =0xb0
1412 11:35:48.063312 DramC Write-DBI on
1413 11:35:48.066560 ==
1414 11:35:48.069831 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1415 11:35:48.073033 fsp= 1, odt_onoff= 1, Byte mode= 0
1416 11:35:48.073118 ==
1417 11:35:48.076336 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1418 11:35:48.076448
1419 11:35:48.079798 Begin, DQ Scan Range 698~762
1420 11:35:48.079883
1421 11:35:48.079949
1422 11:35:48.083357 TX Vref Scan disable
1423 11:35:48.086656 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1424 11:35:48.089528 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1425 11:35:48.092956 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1426 11:35:48.096207 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1427 11:35:48.099590 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1428 11:35:48.102843 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1429 11:35:48.106265 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1430 11:35:48.109548 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1431 11:35:48.113053 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1432 11:35:48.116293 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1433 11:35:48.119592 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1434 11:35:48.123058 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1435 11:35:48.126170 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1436 11:35:48.129719 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1437 11:35:48.136231 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1438 11:35:48.139478 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1439 11:35:48.142913 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1440 11:35:48.146417 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1441 11:35:48.149416 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1442 11:35:48.152928 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1443 11:35:48.156237 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1444 11:35:48.163286 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1445 11:35:48.166602 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1446 11:35:48.169842 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1447 11:35:48.173644 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1448 11:35:48.176707 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1449 11:35:48.180056 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1450 11:35:48.183147 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1451 11:35:48.186712 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1452 11:35:48.189923 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1453 11:35:48.193344 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1454 11:35:48.196942 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
1455 11:35:48.200205 Byte0, DQ PI dly=731, DQM PI dly= 731
1456 11:35:48.203144 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
1457 11:35:48.206686
1458 11:35:48.210236 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
1459 11:35:48.210322
1460 11:35:48.213204 Byte1, DQ PI dly=721, DQM PI dly= 721
1461 11:35:48.216539 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
1462 11:35:48.216614
1463 11:35:48.220285 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
1464 11:35:48.223142
1465 11:35:48.226846 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1466 11:35:48.236562 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1467 11:35:48.243504 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1468 11:35:48.243613 Write Rank0 MR3 =0x30
1469 11:35:48.247043 DramC Write-DBI off
1470 11:35:48.247118
1471 11:35:48.247179 [DATLAT]
1472 11:35:48.249792 Freq=1600, CH0 RK0, use_rxtx_scan=0
1473 11:35:48.249878
1474 11:35:48.253339 DATLAT Default: 0xf
1475 11:35:48.253414 7, 0xFFFF, sum=0
1476 11:35:48.256582 8, 0xFFFF, sum=0
1477 11:35:48.256685 9, 0xFFFF, sum=0
1478 11:35:48.260042 10, 0xFFFF, sum=0
1479 11:35:48.260142 11, 0xFFFF, sum=0
1480 11:35:48.263233 12, 0xFFFF, sum=0
1481 11:35:48.263302 13, 0xFFFF, sum=0
1482 11:35:48.263392 14, 0x0, sum=1
1483 11:35:48.266963 15, 0x0, sum=2
1484 11:35:48.267060 16, 0x0, sum=3
1485 11:35:48.270232 17, 0x0, sum=4
1486 11:35:48.273762 pattern=2 first_step=14 total pass=5 best_step=16
1487 11:35:48.273860 ==
1488 11:35:48.280297 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1489 11:35:48.280409 fsp= 1, odt_onoff= 1, Byte mode= 0
1490 11:35:48.283688 ==
1491 11:35:48.286842 Start DQ dly to find pass range UseTestEngine =1
1492 11:35:48.290023 x-axis: bit #, y-axis: DQ dly (-127~63)
1493 11:35:48.290125 RX Vref Scan = 1
1494 11:35:48.406429
1495 11:35:48.406527 RX Vref found, early break!
1496 11:35:48.406595
1497 11:35:48.413112 Final RX Vref 12, apply to both rank0 and 1
1498 11:35:48.413190 ==
1499 11:35:48.416032 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1500 11:35:48.419977 fsp= 1, odt_onoff= 1, Byte mode= 0
1501 11:35:48.420050 ==
1502 11:35:48.420110 DQS Delay:
1503 11:35:48.423103 DQS0 = 0, DQS1 = 0
1504 11:35:48.423181 DQM Delay:
1505 11:35:48.426136 DQM0 = 19, DQM1 = 19
1506 11:35:48.426208 DQ Delay:
1507 11:35:48.429773 DQ0 =23, DQ1 =21, DQ2 =21, DQ3 =15
1508 11:35:48.433291 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
1509 11:35:48.436732 DQ8 =15, DQ9 =17, DQ10 =26, DQ11 =16
1510 11:35:48.439928 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1511 11:35:48.440024
1512 11:35:48.440119
1513 11:35:48.440217
1514 11:35:48.442938 [DramC_TX_OE_Calibration] TA2
1515 11:35:48.446471 Original DQ_B0 (3 6) =30, OEN = 27
1516 11:35:48.449540 Original DQ_B1 (3 6) =30, OEN = 27
1517 11:35:48.453275 23, 0x0, End_B0=23 End_B1=23
1518 11:35:48.453347 24, 0x0, End_B0=24 End_B1=24
1519 11:35:48.456401 25, 0x0, End_B0=25 End_B1=25
1520 11:35:48.459630 26, 0x0, End_B0=26 End_B1=26
1521 11:35:48.463214 27, 0x0, End_B0=27 End_B1=27
1522 11:35:48.463319 28, 0x0, End_B0=28 End_B1=28
1523 11:35:48.466380 29, 0x0, End_B0=29 End_B1=29
1524 11:35:48.469630 30, 0x0, End_B0=30 End_B1=30
1525 11:35:48.473137 31, 0xFFFF, End_B0=30 End_B1=30
1526 11:35:48.476908 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1527 11:35:48.483116 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1528 11:35:48.483200
1529 11:35:48.483263
1530 11:35:48.486557 Write Rank0 MR23 =0x3f
1531 11:35:48.486641 [DQSOSC]
1532 11:35:48.496469 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1533 11:35:48.499711 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=15, DEC=23
1534 11:35:48.503333 Write Rank0 MR23 =0x3f
1535 11:35:48.503427 [DQSOSC]
1536 11:35:48.513195 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1537 11:35:48.513283 CH0 RK0: MR19=303, MR18=1010
1538 11:35:48.519829 [RankSwap] Rank num 2, (Multi 1), Rank 1
1539 11:35:48.519913 Write Rank0 MR2 =0xad
1540 11:35:48.523453 [Write Leveling]
1541 11:35:48.523537 delay byte0 byte1 byte2 byte3
1542 11:35:48.526517
1543 11:35:48.526599 10 0 0
1544 11:35:48.526666 11 0 0
1545 11:35:48.530122 12 0 0
1546 11:35:48.530207 13 0 0
1547 11:35:48.533527 14 0 0
1548 11:35:48.533611 15 0 0
1549 11:35:48.533678 16 0 0
1550 11:35:48.536416 17 0 0
1551 11:35:48.536539 18 0 0
1552 11:35:48.540062 19 0 0
1553 11:35:48.540147 20 0 0
1554 11:35:48.540212 21 0 0
1555 11:35:48.543263 22 0 0
1556 11:35:48.543348 23 0 0
1557 11:35:48.546865 24 0 ff
1558 11:35:48.546949 25 0 ff
1559 11:35:48.550309 26 0 ff
1560 11:35:48.550393 27 ff ff
1561 11:35:48.553242 28 ff ff
1562 11:35:48.553327 29 ff ff
1563 11:35:48.553393 30 ff ff
1564 11:35:48.556775 31 ff ff
1565 11:35:48.556860 32 ff ff
1566 11:35:48.560356 33 ff ff
1567 11:35:48.563641 pass bytecount = 0xff (0xff: all bytes pass)
1568 11:35:48.563725
1569 11:35:48.563789 DQS0 dly: 27
1570 11:35:48.566755 DQS1 dly: 24
1571 11:35:48.566839 Write Rank0 MR2 =0x2d
1572 11:35:48.573495 [RankSwap] Rank num 2, (Multi 1), Rank 0
1573 11:35:48.573579 Write Rank1 MR1 =0xd6
1574 11:35:48.573644 [Gating]
1575 11:35:48.573704 ==
1576 11:35:48.580565 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1577 11:35:48.583795 fsp= 1, odt_onoff= 1, Byte mode= 0
1578 11:35:48.583879 ==
1579 11:35:48.586975 3 1 0 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1580 11:35:48.590282 3 1 4 |2c2b 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1581 11:35:48.597851 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1582 11:35:48.600397 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1583 11:35:48.603722 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1584 11:35:48.610652 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1585 11:35:48.613392 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1586 11:35:48.617101 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1587 11:35:48.623544 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1588 11:35:48.626744 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1589 11:35:48.629919 3 2 8 |2625 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1590 11:35:48.637220 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1591 11:35:48.640109 3 2 16 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
1592 11:35:48.643626 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1593 11:35:48.646930 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1594 11:35:48.653642 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1595 11:35:48.657186 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1596 11:35:48.660267 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1597 11:35:48.667308 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1598 11:35:48.670533 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1599 11:35:48.673660 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1600 11:35:48.680356 3 3 20 |3534 9bab |(11 11)(11 11) |(0 0)(1 1)| 0
1601 11:35:48.684020 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1602 11:35:48.686953 [Byte 1] Lead/lag falling Transition (3, 3, 24)
1603 11:35:48.693521 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1604 11:35:48.696842 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1605 11:35:48.700525 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1606 11:35:48.703814 3 4 8 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1607 11:35:48.710450 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1608 11:35:48.713914 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1609 11:35:48.717157 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1610 11:35:48.723852 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1611 11:35:48.727128 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1612 11:35:48.730624 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1613 11:35:48.734207 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1614 11:35:48.740705 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1615 11:35:48.743833 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1616 11:35:48.747368 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1617 11:35:48.754373 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1618 11:35:48.757380 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1619 11:35:48.760854 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1620 11:35:48.767117 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1621 11:35:48.770678 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1622 11:35:48.774160 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1623 11:35:48.777136 [Byte 0] Lead/lag Transition tap number (2)
1624 11:35:48.783892 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1625 11:35:48.787516 3 6 8 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1626 11:35:48.790720 [Byte 1] Lead/lag Transition tap number (2)
1627 11:35:48.793907 3 6 12 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1628 11:35:48.797225 [Byte 0]First pass (3, 6, 12)
1629 11:35:48.800886 3 6 16 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
1630 11:35:48.807257 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1631 11:35:48.807329 [Byte 1]First pass (3, 6, 20)
1632 11:35:48.810671 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1633 11:35:48.817540 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1634 11:35:48.820717 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1635 11:35:48.824331 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1636 11:35:48.827900 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1637 11:35:48.830720 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1638 11:35:48.837509 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1639 11:35:48.841221 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1640 11:35:48.844350 All bytes gating window > 1UI, Early break!
1641 11:35:48.844417
1642 11:35:48.847833 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1643 11:35:48.847900
1644 11:35:48.850821 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1645 11:35:48.850886
1646 11:35:48.850944
1647 11:35:48.851006
1648 11:35:48.857785 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1649 11:35:48.857852
1650 11:35:48.861207 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1651 11:35:48.861281
1652 11:35:48.861339
1653 11:35:48.861395 Write Rank1 MR1 =0x56
1654 11:35:48.861451
1655 11:35:48.864423 best RODT dly(2T, 0.5T) = (2, 3)
1656 11:35:48.864517
1657 11:35:48.867630 best RODT dly(2T, 0.5T) = (2, 3)
1658 11:35:48.867693 ==
1659 11:35:48.874178 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1660 11:35:48.877539 fsp= 1, odt_onoff= 1, Byte mode= 0
1661 11:35:48.877616 ==
1662 11:35:48.881009 Start DQ dly to find pass range UseTestEngine =0
1663 11:35:48.884250 x-axis: bit #, y-axis: DQ dly (-127~63)
1664 11:35:48.887786 RX Vref Scan = 0
1665 11:35:48.890955 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1666 11:35:48.891053 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1667 11:35:48.894377 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1668 11:35:48.897500 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1669 11:35:48.900993 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1670 11:35:48.903981 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1671 11:35:48.908005 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1672 11:35:48.910873 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1673 11:35:48.914650 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1674 11:35:48.917923 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1675 11:35:48.917992 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1676 11:35:48.921058 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1677 11:35:48.924657 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1678 11:35:48.927527 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1679 11:35:48.930852 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1680 11:35:48.934295 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1681 11:35:48.937774 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1682 11:35:48.937843 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1683 11:35:48.941103 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1684 11:35:48.944300 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1685 11:35:48.947438 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1686 11:35:48.950969 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1687 11:35:48.954275 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1688 11:35:48.957547 -3, [0] xxxxxxxx oxxoxxxx [MSB]
1689 11:35:48.957618 -2, [0] xxxxxxxx oxxoxxxx [MSB]
1690 11:35:48.961093 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1691 11:35:48.964193 0, [0] xxxoxoxx oxxoxxxx [MSB]
1692 11:35:48.967909 1, [0] xxxoxooo ooxoooxx [MSB]
1693 11:35:48.971106 2, [0] xxxoxooo ooxoooox [MSB]
1694 11:35:48.974623 3, [0] xoxooooo ooxoooox [MSB]
1695 11:35:48.974695 4, [0] oooooooo ooxoooox [MSB]
1696 11:35:48.977534 5, [0] oooooooo ooxooooo [MSB]
1697 11:35:48.981097 33, [0] oooooooo xooooooo [MSB]
1698 11:35:48.984376 34, [0] oooooooo xooooooo [MSB]
1699 11:35:48.987871 35, [0] oooxoooo xooooooo [MSB]
1700 11:35:48.991210 36, [0] oooxoooo xooxoooo [MSB]
1701 11:35:48.994664 37, [0] oooxoxoo xxoxoxoo [MSB]
1702 11:35:48.994734 38, [0] oooxoxoo xxoxxxxo [MSB]
1703 11:35:48.997777 39, [0] oooxoxxx xxoxxxxo [MSB]
1704 11:35:49.001150 40, [0] oooxoxxx xxoxxxxo [MSB]
1705 11:35:49.004392 41, [0] oxxxxxxx xxoxxxxx [MSB]
1706 11:35:49.007837 42, [0] oxxxxxxx xxoxxxxx [MSB]
1707 11:35:49.011165 43, [0] xxxxxxxx xxoxxxxx [MSB]
1708 11:35:49.014393 44, [0] xxxxxxxx xxoxxxxx [MSB]
1709 11:35:49.014462 45, [0] xxxxxxxx xxxxxxxx [MSB]
1710 11:35:49.017657 iDelay=45, Bit 0, Center 23 (4 ~ 42) 39
1711 11:35:49.021189 iDelay=45, Bit 1, Center 21 (3 ~ 40) 38
1712 11:35:49.027883 iDelay=45, Bit 2, Center 22 (4 ~ 40) 37
1713 11:35:49.031052 iDelay=45, Bit 3, Center 16 (-1 ~ 34) 36
1714 11:35:49.034776 iDelay=45, Bit 4, Center 21 (3 ~ 40) 38
1715 11:35:49.037828 iDelay=45, Bit 5, Center 18 (0 ~ 36) 37
1716 11:35:49.040962 iDelay=45, Bit 6, Center 19 (1 ~ 38) 38
1717 11:35:49.044475 iDelay=45, Bit 7, Center 19 (1 ~ 38) 38
1718 11:35:49.047838 iDelay=45, Bit 8, Center 14 (-3 ~ 32) 36
1719 11:35:49.051219 iDelay=45, Bit 9, Center 18 (1 ~ 36) 36
1720 11:35:49.054705 iDelay=45, Bit 10, Center 25 (6 ~ 44) 39
1721 11:35:49.057751 iDelay=45, Bit 11, Center 16 (-3 ~ 35) 39
1722 11:35:49.061679 iDelay=45, Bit 12, Center 19 (1 ~ 37) 37
1723 11:35:49.064919 iDelay=45, Bit 13, Center 18 (1 ~ 36) 36
1724 11:35:49.068200 iDelay=45, Bit 14, Center 19 (2 ~ 37) 36
1725 11:35:49.074657 iDelay=45, Bit 15, Center 22 (5 ~ 40) 36
1726 11:35:49.074740 ==
1727 11:35:49.077898 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1728 11:35:49.081578 fsp= 1, odt_onoff= 1, Byte mode= 0
1729 11:35:49.081663 ==
1730 11:35:49.081727 DQS Delay:
1731 11:35:49.084820 DQS0 = 0, DQS1 = 0
1732 11:35:49.084903 DQM Delay:
1733 11:35:49.088170 DQM0 = 19, DQM1 = 18
1734 11:35:49.088244 DQ Delay:
1735 11:35:49.091408 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =16
1736 11:35:49.095422 DQ4 =21, DQ5 =18, DQ6 =19, DQ7 =19
1737 11:35:49.098273 DQ8 =14, DQ9 =18, DQ10 =25, DQ11 =16
1738 11:35:49.101466 DQ12 =19, DQ13 =18, DQ14 =19, DQ15 =22
1739 11:35:49.101549
1740 11:35:49.101613
1741 11:35:49.105056 DramC Write-DBI off
1742 11:35:49.105139 ==
1743 11:35:49.108015 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1744 11:35:49.111280 fsp= 1, odt_onoff= 1, Byte mode= 0
1745 11:35:49.111370 ==
1746 11:35:49.114619 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1747 11:35:49.118286
1748 11:35:49.118370 Begin, DQ Scan Range 920~1176
1749 11:35:49.118435
1750 11:35:49.118495
1751 11:35:49.121697 TX Vref Scan disable
1752 11:35:49.124761 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1753 11:35:49.128049 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1754 11:35:49.131298 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1755 11:35:49.134726 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1756 11:35:49.138271 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1757 11:35:49.141180 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1758 11:35:49.145087 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1759 11:35:49.148157 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1760 11:35:49.155142 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1761 11:35:49.158231 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1762 11:35:49.161489 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1763 11:35:49.164710 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1764 11:35:49.168058 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1765 11:35:49.171572 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1766 11:35:49.175175 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1767 11:35:49.178603 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1768 11:35:49.181642 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1769 11:35:49.184978 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1770 11:35:49.188230 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1771 11:35:49.191647 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1772 11:35:49.194833 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1773 11:35:49.198454 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1774 11:35:49.201568 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1775 11:35:49.204884 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1776 11:35:49.208166 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1777 11:35:49.211823 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1778 11:35:49.218270 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1779 11:35:49.221896 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1780 11:35:49.225513 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1781 11:35:49.228433 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1782 11:35:49.231977 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1783 11:35:49.235118 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1784 11:35:49.238506 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1785 11:35:49.241959 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1786 11:35:49.245171 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1787 11:35:49.248820 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1788 11:35:49.251897 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1789 11:35:49.255330 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1790 11:35:49.259041 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1791 11:35:49.262069 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1792 11:35:49.265321 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1793 11:35:49.268566 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1794 11:35:49.272107 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1795 11:35:49.275335 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1796 11:35:49.279165 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1797 11:35:49.282237 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1798 11:35:49.285399 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1799 11:35:49.288989 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1800 11:35:49.295327 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1801 11:35:49.299001 969 |3 6 9|[0] xxxxxxxx ooxooxxx [MSB]
1802 11:35:49.302351 970 |3 6 10|[0] xxxxxxxx ooxooxox [MSB]
1803 11:35:49.305471 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1804 11:35:49.308697 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1805 11:35:49.312338 973 |3 6 13|[0] xxxxxxxx ooxooooo [MSB]
1806 11:35:49.315638 974 |3 6 14|[0] xxxxxxxx ooxooooo [MSB]
1807 11:35:49.319276 975 |3 6 15|[0] xoxooooo oooooooo [MSB]
1808 11:35:49.322378 976 |3 6 16|[0] ooxooooo oooooooo [MSB]
1809 11:35:49.325483 987 |3 6 27|[0] oooooooo xoxxxxxx [MSB]
1810 11:35:49.328829 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1811 11:35:49.335694 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1812 11:35:49.339062 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1813 11:35:49.342589 991 |3 6 31|[0] oooxoooo xxxxxxxx [MSB]
1814 11:35:49.345679 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB]
1815 11:35:49.349210 993 |3 6 33|[0] xxxxxxxx xxxxxxxx [MSB]
1816 11:35:49.352660 Byte0, DQ PI dly=983, DQM PI dly= 983
1817 11:35:49.356183 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1818 11:35:49.356268
1819 11:35:49.359247 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1820 11:35:49.359331
1821 11:35:49.362932 Byte1, DQ PI dly=978, DQM PI dly= 978
1822 11:35:49.369516 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1823 11:35:49.369604
1824 11:35:49.372622 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1825 11:35:49.372699
1826 11:35:49.372761 ==
1827 11:35:49.379341 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1828 11:35:49.382516 fsp= 1, odt_onoff= 1, Byte mode= 0
1829 11:35:49.382587 ==
1830 11:35:49.386069 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1831 11:35:49.386149
1832 11:35:49.389485 Begin, DQ Scan Range 954~1018
1833 11:35:49.389555 Write Rank1 MR14 =0x0
1834 11:35:49.398244
1835 11:35:49.398320 CH=0, VrefRange= 0, VrefLevel = 0
1836 11:35:49.404506 TX Bit0 (978~991) 14 984, Bit8 (969~982) 14 975,
1837 11:35:49.408381 TX Bit1 (977~989) 13 983, Bit9 (971~985) 15 978,
1838 11:35:49.415049 TX Bit2 (978~990) 13 984, Bit10 (977~986) 10 981,
1839 11:35:49.418067 TX Bit3 (972~983) 12 977, Bit11 (970~983) 14 976,
1840 11:35:49.421662 TX Bit4 (977~990) 14 983, Bit12 (973~985) 13 979,
1841 11:35:49.428154 TX Bit5 (974~985) 12 979, Bit13 (975~983) 9 979,
1842 11:35:49.431296 TX Bit6 (976~988) 13 982, Bit14 (974~984) 11 979,
1843 11:35:49.434593 TX Bit7 (977~990) 14 983, Bit15 (975~986) 12 980,
1844 11:35:49.434669
1845 11:35:49.438212 Write Rank1 MR14 =0x2
1846 11:35:49.446326
1847 11:35:49.446407 CH=0, VrefRange= 0, VrefLevel = 2
1848 11:35:49.452880 TX Bit0 (978~992) 15 985, Bit8 (969~983) 15 976,
1849 11:35:49.456027 TX Bit1 (977~990) 14 983, Bit9 (970~985) 16 977,
1850 11:35:49.462954 TX Bit2 (978~991) 14 984, Bit10 (977~990) 14 983,
1851 11:35:49.466526 TX Bit3 (971~984) 14 977, Bit11 (970~983) 14 976,
1852 11:35:49.469369 TX Bit4 (976~990) 15 983, Bit12 (973~985) 13 979,
1853 11:35:49.476020 TX Bit5 (974~987) 14 980, Bit13 (974~983) 10 978,
1854 11:35:49.479424 TX Bit6 (975~989) 15 982, Bit14 (974~985) 12 979,
1855 11:35:49.483168 TX Bit7 (976~990) 15 983, Bit15 (976~990) 15 983,
1856 11:35:49.483239
1857 11:35:49.486326 Write Rank1 MR14 =0x4
1858 11:35:49.494412
1859 11:35:49.494486 CH=0, VrefRange= 0, VrefLevel = 4
1860 11:35:49.500701 TX Bit0 (977~992) 16 984, Bit8 (969~983) 15 976,
1861 11:35:49.503871 TX Bit1 (977~991) 15 984, Bit9 (970~986) 17 978,
1862 11:35:49.511068 TX Bit2 (978~991) 14 984, Bit10 (976~990) 15 983,
1863 11:35:49.513942 TX Bit3 (971~984) 14 977, Bit11 (970~983) 14 976,
1864 11:35:49.517547 TX Bit4 (976~991) 16 983, Bit12 (972~986) 15 979,
1865 11:35:49.524334 TX Bit5 (973~988) 16 980, Bit13 (974~984) 11 979,
1866 11:35:49.527286 TX Bit6 (975~990) 16 982, Bit14 (973~986) 14 979,
1867 11:35:49.530607 TX Bit7 (976~991) 16 983, Bit15 (975~990) 16 982,
1868 11:35:49.530678
1869 11:35:49.534107 Write Rank1 MR14 =0x6
1870 11:35:49.542446
1871 11:35:49.542520 CH=0, VrefRange= 0, VrefLevel = 6
1872 11:35:49.548967 TX Bit0 (977~993) 17 985, Bit8 (969~984) 16 976,
1873 11:35:49.552500 TX Bit1 (977~991) 15 984, Bit9 (970~986) 17 978,
1874 11:35:49.555974 TX Bit2 (977~992) 16 984, Bit10 (976~991) 16 983,
1875 11:35:49.562975 TX Bit3 (971~985) 15 978, Bit11 (969~984) 16 976,
1876 11:35:49.565933 TX Bit4 (976~991) 16 983, Bit12 (971~987) 17 979,
1877 11:35:49.572268 TX Bit5 (972~989) 18 980, Bit13 (973~984) 12 978,
1878 11:35:49.576068 TX Bit6 (974~990) 17 982, Bit14 (972~987) 16 979,
1879 11:35:49.579012 TX Bit7 (975~991) 17 983, Bit15 (975~991) 17 983,
1880 11:35:49.579087
1881 11:35:49.582594 Write Rank1 MR14 =0x8
1882 11:35:49.590635
1883 11:35:49.590703 CH=0, VrefRange= 0, VrefLevel = 8
1884 11:35:49.597216 TX Bit0 (977~993) 17 985, Bit8 (968~984) 17 976,
1885 11:35:49.600375 TX Bit1 (976~991) 16 983, Bit9 (970~987) 18 978,
1886 11:35:49.607325 TX Bit2 (978~992) 15 985, Bit10 (976~991) 16 983,
1887 11:35:49.610656 TX Bit3 (970~986) 17 978, Bit11 (969~985) 17 977,
1888 11:35:49.613713 TX Bit4 (976~992) 17 984, Bit12 (971~988) 18 979,
1889 11:35:49.620580 TX Bit5 (972~990) 19 981, Bit13 (973~985) 13 979,
1890 11:35:49.623701 TX Bit6 (974~991) 18 982, Bit14 (971~989) 19 980,
1891 11:35:49.627306 TX Bit7 (975~992) 18 983, Bit15 (975~991) 17 983,
1892 11:35:49.627392
1893 11:35:49.630651 Write Rank1 MR14 =0xa
1894 11:35:49.638707
1895 11:35:49.641843 CH=0, VrefRange= 0, VrefLevel = 10
1896 11:35:49.645364 TX Bit0 (977~994) 18 985, Bit8 (968~984) 17 976,
1897 11:35:49.648966 TX Bit1 (976~992) 17 984, Bit9 (969~988) 20 978,
1898 11:35:49.655586 TX Bit2 (977~993) 17 985, Bit10 (975~992) 18 983,
1899 11:35:49.658808 TX Bit3 (970~987) 18 978, Bit11 (969~985) 17 977,
1900 11:35:49.662225 TX Bit4 (975~992) 18 983, Bit12 (970~989) 20 979,
1901 11:35:49.669215 TX Bit5 (972~990) 19 981, Bit13 (972~986) 15 979,
1902 11:35:49.672371 TX Bit6 (973~991) 19 982, Bit14 (971~989) 19 980,
1903 11:35:49.675697 TX Bit7 (975~992) 18 983, Bit15 (975~991) 17 983,
1904 11:35:49.675775
1905 11:35:49.679059 Write Rank1 MR14 =0xc
1906 11:35:49.687212
1907 11:35:49.690344 CH=0, VrefRange= 0, VrefLevel = 12
1908 11:35:49.694383 TX Bit0 (977~995) 19 986, Bit8 (968~985) 18 976,
1909 11:35:49.697282 TX Bit1 (976~992) 17 984, Bit9 (969~989) 21 979,
1910 11:35:49.703769 TX Bit2 (977~993) 17 985, Bit10 (975~992) 18 983,
1911 11:35:49.707019 TX Bit3 (970~988) 19 979, Bit11 (969~985) 17 977,
1912 11:35:49.710833 TX Bit4 (975~992) 18 983, Bit12 (970~989) 20 979,
1913 11:35:49.717021 TX Bit5 (972~990) 19 981, Bit13 (971~986) 16 978,
1914 11:35:49.720559 TX Bit6 (974~992) 19 983, Bit14 (971~990) 20 980,
1915 11:35:49.723833 TX Bit7 (975~992) 18 983, Bit15 (974~992) 19 983,
1916 11:35:49.723908
1917 11:35:49.727220 Write Rank1 MR14 =0xe
1918 11:35:49.736074
1919 11:35:49.739133 CH=0, VrefRange= 0, VrefLevel = 14
1920 11:35:49.742376 TX Bit0 (977~995) 19 986, Bit8 (968~985) 18 976,
1921 11:35:49.746013 TX Bit1 (976~993) 18 984, Bit9 (969~989) 21 979,
1922 11:35:49.752804 TX Bit2 (977~993) 17 985, Bit10 (975~992) 18 983,
1923 11:35:49.755728 TX Bit3 (970~989) 20 979, Bit11 (968~986) 19 977,
1924 11:35:49.758894 TX Bit4 (975~993) 19 984, Bit12 (970~990) 21 980,
1925 11:35:49.765889 TX Bit5 (971~991) 21 981, Bit13 (971~988) 18 979,
1926 11:35:49.769379 TX Bit6 (973~992) 20 982, Bit14 (970~990) 21 980,
1927 11:35:49.772514 TX Bit7 (974~993) 20 983, Bit15 (974~992) 19 983,
1928 11:35:49.772589
1929 11:35:49.779191 wait MRW command Rank1 MR14 =0x10 fired (1)
1930 11:35:49.779274 Write Rank1 MR14 =0x10
1931 11:35:49.788438
1932 11:35:49.788532 CH=0, VrefRange= 0, VrefLevel = 16
1933 11:35:49.795309 TX Bit0 (976~996) 21 986, Bit8 (968~986) 19 977,
1934 11:35:49.798402 TX Bit1 (975~993) 19 984, Bit9 (969~990) 22 979,
1935 11:35:49.805530 TX Bit2 (977~994) 18 985, Bit10 (975~993) 19 984,
1936 11:35:49.808560 TX Bit3 (969~990) 22 979, Bit11 (968~987) 20 977,
1937 11:35:49.812010 TX Bit4 (974~994) 21 984, Bit12 (969~990) 22 979,
1938 11:35:49.818971 TX Bit5 (971~991) 21 981, Bit13 (970~988) 19 979,
1939 11:35:49.821951 TX Bit6 (972~992) 21 982, Bit14 (970~990) 21 980,
1940 11:35:49.825591 TX Bit7 (974~994) 21 984, Bit15 (974~993) 20 983,
1941 11:35:49.825666
1942 11:35:49.828770 Write Rank1 MR14 =0x12
1943 11:35:49.837814
1944 11:35:49.837891 CH=0, VrefRange= 0, VrefLevel = 18
1945 11:35:49.844076 TX Bit0 (976~997) 22 986, Bit8 (968~987) 20 977,
1946 11:35:49.847387 TX Bit1 (975~994) 20 984, Bit9 (969~990) 22 979,
1947 11:35:49.853961 TX Bit2 (976~995) 20 985, Bit10 (975~994) 20 984,
1948 11:35:49.857377 TX Bit3 (969~990) 22 979, Bit11 (968~987) 20 977,
1949 11:35:49.860983 TX Bit4 (974~994) 21 984, Bit12 (969~990) 22 979,
1950 11:35:49.867544 TX Bit5 (971~991) 21 981, Bit13 (970~989) 20 979,
1951 11:35:49.870833 TX Bit6 (972~993) 22 982, Bit14 (969~991) 23 980,
1952 11:35:49.874113 TX Bit7 (973~994) 22 983, Bit15 (973~993) 21 983,
1953 11:35:49.874189
1954 11:35:49.877842 Write Rank1 MR14 =0x14
1955 11:35:49.886255
1956 11:35:49.889842 CH=0, VrefRange= 0, VrefLevel = 20
1957 11:35:49.892750 TX Bit0 (976~997) 22 986, Bit8 (967~988) 22 977,
1958 11:35:49.896327 TX Bit1 (975~995) 21 985, Bit9 (969~990) 22 979,
1959 11:35:49.902737 TX Bit2 (976~996) 21 986, Bit10 (974~994) 21 984,
1960 11:35:49.906528 TX Bit3 (969~990) 22 979, Bit11 (968~988) 21 978,
1961 11:35:49.909671 TX Bit4 (974~995) 22 984, Bit12 (969~991) 23 980,
1962 11:35:49.916547 TX Bit5 (970~992) 23 981, Bit13 (970~990) 21 980,
1963 11:35:49.919570 TX Bit6 (972~993) 22 982, Bit14 (969~991) 23 980,
1964 11:35:49.922875 TX Bit7 (972~995) 24 983, Bit15 (973~993) 21 983,
1965 11:35:49.922951
1966 11:35:49.926327 Write Rank1 MR14 =0x16
1967 11:35:49.935182
1968 11:35:49.938675 CH=0, VrefRange= 0, VrefLevel = 22
1969 11:35:49.942299 TX Bit0 (975~998) 24 986, Bit8 (967~989) 23 978,
1970 11:35:49.945700 TX Bit1 (974~995) 22 984, Bit9 (968~991) 24 979,
1971 11:35:49.951946 TX Bit2 (976~996) 21 986, Bit10 (974~995) 22 984,
1972 11:35:49.955721 TX Bit3 (969~991) 23 980, Bit11 (967~989) 23 978,
1973 11:35:49.958856 TX Bit4 (973~995) 23 984, Bit12 (969~991) 23 980,
1974 11:35:49.965576 TX Bit5 (970~992) 23 981, Bit13 (969~990) 22 979,
1975 11:35:49.969013 TX Bit6 (971~993) 23 982, Bit14 (969~991) 23 980,
1976 11:35:49.972132 TX Bit7 (972~996) 25 984, Bit15 (973~994) 22 983,
1977 11:35:49.972211
1978 11:35:49.975559 Write Rank1 MR14 =0x18
1979 11:35:49.984490
1980 11:35:49.984572 CH=0, VrefRange= 0, VrefLevel = 24
1981 11:35:49.991193 TX Bit0 (975~998) 24 986, Bit8 (967~990) 24 978,
1982 11:35:49.994757 TX Bit1 (974~995) 22 984, Bit9 (968~991) 24 979,
1983 11:35:50.001460 TX Bit2 (976~997) 22 986, Bit10 (974~996) 23 985,
1984 11:35:50.004663 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
1985 11:35:50.008330 TX Bit4 (973~996) 24 984, Bit12 (969~991) 23 980,
1986 11:35:50.014836 TX Bit5 (970~992) 23 981, Bit13 (969~990) 22 979,
1987 11:35:50.018143 TX Bit6 (971~994) 24 982, Bit14 (969~992) 24 980,
1988 11:35:50.021323 TX Bit7 (972~995) 24 983, Bit15 (972~995) 24 983,
1989 11:35:50.021403
1990 11:35:50.025287 Write Rank1 MR14 =0x1a
1991 11:35:50.033875
1992 11:35:50.037014 CH=0, VrefRange= 0, VrefLevel = 26
1993 11:35:50.040444 TX Bit0 (975~998) 24 986, Bit8 (966~990) 25 978,
1994 11:35:50.043542 TX Bit1 (974~996) 23 985, Bit9 (968~991) 24 979,
1995 11:35:50.050166 TX Bit2 (975~997) 23 986, Bit10 (973~997) 25 985,
1996 11:35:50.053707 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
1997 11:35:50.056745 TX Bit4 (972~996) 25 984, Bit12 (968~992) 25 980,
1998 11:35:50.063975 TX Bit5 (970~993) 24 981, Bit13 (969~990) 22 979,
1999 11:35:50.066932 TX Bit6 (971~995) 25 983, Bit14 (969~992) 24 980,
2000 11:35:50.070223 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
2001 11:35:50.070292
2002 11:35:50.073518 Write Rank1 MR14 =0x1c
2003 11:35:50.082680
2004 11:35:50.086031 CH=0, VrefRange= 0, VrefLevel = 28
2005 11:35:50.089588 TX Bit0 (975~999) 25 987, Bit8 (966~990) 25 978,
2006 11:35:50.092792 TX Bit1 (973~997) 25 985, Bit9 (968~991) 24 979,
2007 11:35:50.099554 TX Bit2 (976~998) 23 987, Bit10 (972~997) 26 984,
2008 11:35:50.102856 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2009 11:35:50.106726 TX Bit4 (972~997) 26 984, Bit12 (969~992) 24 980,
2010 11:35:50.112878 TX Bit5 (970~993) 24 981, Bit13 (969~991) 23 980,
2011 11:35:50.116055 TX Bit6 (970~995) 26 982, Bit14 (968~992) 25 980,
2012 11:35:50.119873 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
2013 11:35:50.119949
2014 11:35:50.122999 Write Rank1 MR14 =0x1e
2015 11:35:50.132233
2016 11:35:50.132315 CH=0, VrefRange= 0, VrefLevel = 30
2017 11:35:50.138694 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2018 11:35:50.142335 TX Bit1 (974~997) 24 985, Bit9 (968~991) 24 979,
2019 11:35:50.148803 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2020 11:35:50.152319 TX Bit3 (968~992) 25 980, Bit11 (967~991) 25 979,
2021 11:35:50.155413 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2022 11:35:50.162170 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2023 11:35:50.165364 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2024 11:35:50.168604 TX Bit7 (971~998) 28 984, Bit15 (971~996) 26 983,
2025 11:35:50.168711
2026 11:35:50.171890 Write Rank1 MR14 =0x20
2027 11:35:50.181809
2028 11:35:50.185073 CH=0, VrefRange= 0, VrefLevel = 32
2029 11:35:50.188326 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2030 11:35:50.191719 TX Bit1 (974~997) 24 985, Bit9 (968~991) 24 979,
2031 11:35:50.198277 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2032 11:35:50.201258 TX Bit3 (968~992) 25 980, Bit11 (967~991) 25 979,
2033 11:35:50.204940 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2034 11:35:50.211389 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2035 11:35:50.214736 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2036 11:35:50.218110 TX Bit7 (971~998) 28 984, Bit15 (971~996) 26 983,
2037 11:35:50.218215
2038 11:35:50.221236 Write Rank1 MR14 =0x22
2039 11:35:50.230587
2040 11:35:50.234320 CH=0, VrefRange= 0, VrefLevel = 34
2041 11:35:50.237507 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2042 11:35:50.240560 TX Bit1 (974~997) 24 985, Bit9 (968~991) 24 979,
2043 11:35:50.247516 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2044 11:35:50.250817 TX Bit3 (968~992) 25 980, Bit11 (967~991) 25 979,
2045 11:35:50.253959 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2046 11:35:50.260732 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2047 11:35:50.264364 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2048 11:35:50.267537 TX Bit7 (971~998) 28 984, Bit15 (971~996) 26 983,
2049 11:35:50.267622
2050 11:35:50.270621 Write Rank1 MR14 =0x24
2051 11:35:50.279937
2052 11:35:50.283136 CH=0, VrefRange= 0, VrefLevel = 36
2053 11:35:50.286254 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2054 11:35:50.289635 TX Bit1 (974~997) 24 985, Bit9 (968~991) 24 979,
2055 11:35:50.296408 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2056 11:35:50.299977 TX Bit3 (968~992) 25 980, Bit11 (967~991) 25 979,
2057 11:35:50.303409 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2058 11:35:50.310116 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2059 11:35:50.313179 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2060 11:35:50.316881 TX Bit7 (971~998) 28 984, Bit15 (971~996) 26 983,
2061 11:35:50.316967
2062 11:35:50.319999 Write Rank1 MR14 =0x26
2063 11:35:50.328934
2064 11:35:50.332230 CH=0, VrefRange= 0, VrefLevel = 38
2065 11:35:50.335699 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2066 11:35:50.338817 TX Bit1 (974~997) 24 985, Bit9 (968~991) 24 979,
2067 11:35:50.345600 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2068 11:35:50.349181 TX Bit3 (968~992) 25 980, Bit11 (967~991) 25 979,
2069 11:35:50.352804 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2070 11:35:50.359261 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2071 11:35:50.362274 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2072 11:35:50.365475 TX Bit7 (971~998) 28 984, Bit15 (971~996) 26 983,
2073 11:35:50.365561
2074 11:35:50.365645
2075 11:35:50.368633 TX Vref found, early break! 379< 385
2076 11:35:50.375933 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2077 11:35:50.379072 u1DelayCellOfst[0]=7 cells (6 PI)
2078 11:35:50.382230 u1DelayCellOfst[1]=6 cells (5 PI)
2079 11:35:50.385919 u1DelayCellOfst[2]=7 cells (6 PI)
2080 11:35:50.386005 u1DelayCellOfst[3]=0 cells (0 PI)
2081 11:35:50.389095 u1DelayCellOfst[4]=5 cells (4 PI)
2082 11:35:50.392422 u1DelayCellOfst[5]=1 cells (1 PI)
2083 11:35:50.396165 u1DelayCellOfst[6]=3 cells (3 PI)
2084 11:35:50.399140 u1DelayCellOfst[7]=5 cells (4 PI)
2085 11:35:50.402725 Byte0, DQ PI dly=980, DQM PI dly= 983
2086 11:35:50.405664 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2087 11:35:50.405776
2088 11:35:50.412162 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2089 11:35:50.412248
2090 11:35:50.415794 u1DelayCellOfst[8]=0 cells (0 PI)
2091 11:35:50.419063 u1DelayCellOfst[9]=1 cells (1 PI)
2092 11:35:50.419174 u1DelayCellOfst[10]=7 cells (6 PI)
2093 11:35:50.422271 u1DelayCellOfst[11]=1 cells (1 PI)
2094 11:35:50.425463 u1DelayCellOfst[12]=2 cells (2 PI)
2095 11:35:50.428988 u1DelayCellOfst[13]=2 cells (2 PI)
2096 11:35:50.432813 u1DelayCellOfst[14]=2 cells (2 PI)
2097 11:35:50.435728 u1DelayCellOfst[15]=6 cells (5 PI)
2098 11:35:50.438838 Byte1, DQ PI dly=978, DQM PI dly= 981
2099 11:35:50.442881 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2100 11:35:50.442961
2101 11:35:50.449536 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2102 11:35:50.449623
2103 11:35:50.449707 Write Rank1 MR14 =0x1e
2104 11:35:50.449786
2105 11:35:50.452719 Final TX Range 0 Vref 30
2106 11:35:50.452805
2107 11:35:50.459565 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2108 11:35:50.459651
2109 11:35:50.466318 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2110 11:35:50.472604 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2111 11:35:50.479475 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2112 11:35:50.483034 Write Rank1 MR3 =0xb0
2113 11:35:50.483113 DramC Write-DBI on
2114 11:35:50.483178 ==
2115 11:35:50.489462 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2116 11:35:50.492684 fsp= 1, odt_onoff= 1, Byte mode= 0
2117 11:35:50.492803 ==
2118 11:35:50.495954 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2119 11:35:50.496064
2120 11:35:50.499408 Begin, DQ Scan Range 701~765
2121 11:35:50.499516
2122 11:35:50.499579
2123 11:35:50.502947 TX Vref Scan disable
2124 11:35:50.506230 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2125 11:35:50.509899 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2126 11:35:50.512424 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2127 11:35:50.515979 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2128 11:35:50.519171 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2129 11:35:50.522887 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2130 11:35:50.526000 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2131 11:35:50.529500 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2132 11:35:50.532620 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2133 11:35:50.536046 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2134 11:35:50.539512 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2135 11:35:50.542809 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2136 11:35:50.546509 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2137 11:35:50.549750 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2138 11:35:50.553019 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2139 11:35:50.562686 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2140 11:35:50.565933 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2141 11:35:50.569071 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2142 11:35:50.572449 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2143 11:35:50.575480 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2144 11:35:50.578927 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2145 11:35:50.582476 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2146 11:35:50.585684 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2147 11:35:50.589161 Byte0, DQ PI dly=729, DQM PI dly= 729
2148 11:35:50.592389 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
2149 11:35:50.592485
2150 11:35:50.599294 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
2151 11:35:50.599380
2152 11:35:50.602220 Byte1, DQ PI dly=723, DQM PI dly= 723
2153 11:35:50.605784 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2154 11:35:50.605870
2155 11:35:50.609015 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2156 11:35:50.609103
2157 11:35:50.615549 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2158 11:35:50.622647 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2159 11:35:50.632229 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2160 11:35:50.632310 Write Rank1 MR3 =0x30
2161 11:35:50.635552 DramC Write-DBI off
2162 11:35:50.635652
2163 11:35:50.635746 [DATLAT]
2164 11:35:50.639271 Freq=1600, CH0 RK1, use_rxtx_scan=0
2165 11:35:50.639369
2166 11:35:50.642446 DATLAT Default: 0x10
2167 11:35:50.642527 7, 0xFFFF, sum=0
2168 11:35:50.642592 8, 0xFFFF, sum=0
2169 11:35:50.645573 9, 0xFFFF, sum=0
2170 11:35:50.645646 10, 0xFFFF, sum=0
2171 11:35:50.649425 11, 0xFFFF, sum=0
2172 11:35:50.649508 12, 0xFFFF, sum=0
2173 11:35:50.652556 13, 0xFFFF, sum=0
2174 11:35:50.652633 14, 0x0, sum=1
2175 11:35:50.655785 15, 0x0, sum=2
2176 11:35:50.655858 16, 0x0, sum=3
2177 11:35:50.659259 17, 0x0, sum=4
2178 11:35:50.662609 pattern=2 first_step=14 total pass=5 best_step=16
2179 11:35:50.662679 ==
2180 11:35:50.666000 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2181 11:35:50.669689 fsp= 1, odt_onoff= 1, Byte mode= 0
2182 11:35:50.669803 ==
2183 11:35:50.676042 Start DQ dly to find pass range UseTestEngine =1
2184 11:35:50.679451 x-axis: bit #, y-axis: DQ dly (-127~63)
2185 11:35:50.679538 RX Vref Scan = 0
2186 11:35:50.683013 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2187 11:35:50.686096 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2188 11:35:50.689487 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2189 11:35:50.692584 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2190 11:35:50.696268 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2191 11:35:50.696382 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2192 11:35:50.699532 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2193 11:35:50.702953 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2194 11:35:50.706149 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2195 11:35:50.709697 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2196 11:35:50.712908 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2197 11:35:50.715987 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2198 11:35:50.720062 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2199 11:35:50.720150 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2200 11:35:50.722881 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2201 11:35:50.726417 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2202 11:35:50.729582 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2203 11:35:50.732676 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2204 11:35:50.736584 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2205 11:35:50.739516 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2206 11:35:50.742800 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2207 11:35:50.742887 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2208 11:35:50.746642 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2209 11:35:50.749740 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2210 11:35:50.753192 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2211 11:35:50.756344 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2212 11:35:50.759962 0, [0] xxxoxxxx oxxoxxxx [MSB]
2213 11:35:50.760051 1, [0] xxxoxoxx ooxooxxx [MSB]
2214 11:35:50.763059 2, [0] xxxoxoxx ooxoooxx [MSB]
2215 11:35:50.766718 3, [0] xxxoxooo ooxoooox [MSB]
2216 11:35:50.770342 4, [0] xxxoxooo ooxoooox [MSB]
2217 11:35:50.773147 5, [0] ooxooooo ooxoooox [MSB]
2218 11:35:50.773234 6, [0] oooooooo ooxooooo [MSB]
2219 11:35:50.778589 33, [0] oooooooo xooooooo [MSB]
2220 11:35:50.782065 34, [0] oooxoooo xooooooo [MSB]
2221 11:35:50.785225 35, [0] oooxoxoo xooxoooo [MSB]
2222 11:35:50.789174 36, [0] oooxoxoo xooxoxoo [MSB]
2223 11:35:50.792132 37, [0] oooxoxoo xxoxoxoo [MSB]
2224 11:35:50.795452 38, [0] oooxoxxo xxoxxxoo [MSB]
2225 11:35:50.795540 39, [0] oxxxoxxx xxoxxxxo [MSB]
2226 11:35:50.798530 40, [0] oxxxxxxx xxoxxxxx [MSB]
2227 11:35:50.801974 41, [0] xxxxxxxx xxoxxxxx [MSB]
2228 11:35:50.805352 42, [0] xxxxxxxx xxoxxxxx [MSB]
2229 11:35:50.808443 43, [0] xxxxxxxx xxoxxxxx [MSB]
2230 11:35:50.812127 44, [0] xxxxxxxx xxxxxxxx [MSB]
2231 11:35:50.815185 iDelay=44, Bit 0, Center 22 (5 ~ 40) 36
2232 11:35:50.818927 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2233 11:35:50.821989 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2234 11:35:50.825674 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2235 11:35:50.828724 iDelay=44, Bit 4, Center 22 (5 ~ 39) 35
2236 11:35:50.832119 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2237 11:35:50.835625 iDelay=44, Bit 6, Center 20 (3 ~ 37) 35
2238 11:35:50.838875 iDelay=44, Bit 7, Center 20 (3 ~ 38) 36
2239 11:35:50.842259 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2240 11:35:50.846007 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2241 11:35:50.849210 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2242 11:35:50.852367 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2243 11:35:50.859268 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2244 11:35:50.861987 iDelay=44, Bit 13, Center 18 (2 ~ 35) 34
2245 11:35:50.865494 iDelay=44, Bit 14, Center 20 (3 ~ 38) 36
2246 11:35:50.869006 iDelay=44, Bit 15, Center 22 (6 ~ 39) 34
2247 11:35:50.869079 ==
2248 11:35:50.872093 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2249 11:35:50.875679 fsp= 1, odt_onoff= 1, Byte mode= 0
2250 11:35:50.875754 ==
2251 11:35:50.878805 DQS Delay:
2252 11:35:50.878875 DQS0 = 0, DQS1 = 0
2253 11:35:50.882144 DQM Delay:
2254 11:35:50.882218 DQM0 = 19, DQM1 = 19
2255 11:35:50.882277 DQ Delay:
2256 11:35:50.885775 DQ0 =22, DQ1 =21, DQ2 =22, DQ3 =15
2257 11:35:50.888850 DQ4 =22, DQ5 =17, DQ6 =20, DQ7 =20
2258 11:35:50.892415 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2259 11:35:50.895651 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
2260 11:35:50.895761
2261 11:35:50.895855
2262 11:35:50.895944
2263 11:35:50.898901 [DramC_TX_OE_Calibration] TA2
2264 11:35:50.902295 Original DQ_B0 (3 6) =30, OEN = 27
2265 11:35:50.905661 Original DQ_B1 (3 6) =30, OEN = 27
2266 11:35:50.909185 23, 0x0, End_B0=23 End_B1=23
2267 11:35:50.912166 24, 0x0, End_B0=24 End_B1=24
2268 11:35:50.912250 25, 0x0, End_B0=25 End_B1=25
2269 11:35:50.915667 26, 0x0, End_B0=26 End_B1=26
2270 11:35:50.919251 27, 0x0, End_B0=27 End_B1=27
2271 11:35:50.922207 28, 0x0, End_B0=28 End_B1=28
2272 11:35:50.926014 29, 0x0, End_B0=29 End_B1=29
2273 11:35:50.926097 30, 0x0, End_B0=30 End_B1=30
2274 11:35:50.929031 31, 0xFFFF, End_B0=30 End_B1=30
2275 11:35:50.935655 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2276 11:35:50.938857 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2277 11:35:50.942420
2278 11:35:50.942502
2279 11:35:50.942566 Write Rank1 MR23 =0x3f
2280 11:35:50.942624 [DQSOSC]
2281 11:35:50.952149 [DQSOSCAuto] RK1, (LSB)MR18= 0xd7d7, (MSB)MR19= 0x202, tDQSOscB0 = 433 ps tDQSOscB1 = 433 ps
2282 11:35:50.958906 CH0_RK1: MR19=0x202, MR18=0xD7D7, DQSOSC=433, MR23=63, INC=13, DEC=19
2283 11:35:50.958992 Write Rank1 MR23 =0x3f
2284 11:35:50.962473 [DQSOSC]
2285 11:35:50.969411 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2286 11:35:50.972405 CH0 RK1: MR19=202, MR18=D8D8
2287 11:35:50.976095 [RxdqsGatingPostProcess] freq 1600
2288 11:35:50.979101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2289 11:35:50.982779 Rank: 0
2290 11:35:50.982861 best DQS0 dly(2T, 0.5T) = (2, 5)
2291 11:35:50.986061 best DQS1 dly(2T, 0.5T) = (2, 5)
2292 11:35:50.989134 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2293 11:35:50.992773 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2294 11:35:50.992856 Rank: 1
2295 11:35:50.996046 best DQS0 dly(2T, 0.5T) = (2, 6)
2296 11:35:50.999705 best DQS1 dly(2T, 0.5T) = (2, 6)
2297 11:35:51.003033 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2298 11:35:51.005875 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2299 11:35:51.012376 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2300 11:35:51.015800 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2301 11:35:51.019489 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2302 11:35:51.022453 Write Rank0 MR13 =0x59
2303 11:35:51.022547 ==
2304 11:35:51.025902 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2305 11:35:51.029373 fsp= 1, odt_onoff= 1, Byte mode= 0
2306 11:35:51.029456 ==
2307 11:35:51.032581 === u2Vref_new: 0x56 --> 0x3a
2308 11:35:51.036143 === u2Vref_new: 0x58 --> 0x58
2309 11:35:51.039503 === u2Vref_new: 0x5a --> 0x5a
2310 11:35:51.042832 === u2Vref_new: 0x5c --> 0x78
2311 11:35:51.046779 === u2Vref_new: 0x5e --> 0x7a
2312 11:35:51.049231 === u2Vref_new: 0x60 --> 0x90
2313 11:35:51.052813 [CA 0] Center 37 (12~63) winsize 52
2314 11:35:51.056291 [CA 1] Center 37 (12~63) winsize 52
2315 11:35:51.059420 [CA 2] Center 34 (6~63) winsize 58
2316 11:35:51.059504 [CA 3] Center 34 (6~63) winsize 58
2317 11:35:51.062765 [CA 4] Center 34 (5~63) winsize 59
2318 11:35:51.066207 [CA 5] Center 28 (-2~58) winsize 61
2319 11:35:51.066290
2320 11:35:51.069583 [CATrainingPosCal] consider 1 rank data
2321 11:35:51.072788 u2DelayCellTimex100 = 735/100 ps
2322 11:35:51.076004 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2323 11:35:51.082976 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2324 11:35:51.085950 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2325 11:35:51.089151 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2326 11:35:51.092749 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2327 11:35:51.096119 CA5 delay=28 (-2~58),Diff = 0 PI (0 cell)
2328 11:35:51.096203
2329 11:35:51.099631 CA PerBit enable=1, Macro0, CA PI delay=28
2330 11:35:51.102857 === u2Vref_new: 0x60 --> 0x90
2331 11:35:51.102942
2332 11:35:51.105945 Vref(ca) range 1: 32
2333 11:35:51.106030
2334 11:35:51.106095 CS Dly= 11 (42-0-32)
2335 11:35:51.109572 Write Rank0 MR13 =0xd8
2336 11:35:51.112860 Write Rank0 MR13 =0xd8
2337 11:35:51.112971 Write Rank0 MR12 =0x60
2338 11:35:51.115825 Write Rank1 MR13 =0x59
2339 11:35:51.115901 ==
2340 11:35:51.119661 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2341 11:35:51.123014 fsp= 1, odt_onoff= 1, Byte mode= 0
2342 11:35:51.123125 ==
2343 11:35:51.125902 === u2Vref_new: 0x56 --> 0x3a
2344 11:35:51.129337 === u2Vref_new: 0x58 --> 0x58
2345 11:35:51.132750 === u2Vref_new: 0x5a --> 0x5a
2346 11:35:51.136161 === u2Vref_new: 0x5c --> 0x78
2347 11:35:51.139695 === u2Vref_new: 0x5e --> 0x7a
2348 11:35:51.142919 === u2Vref_new: 0x60 --> 0x90
2349 11:35:51.145897 [CA 0] Center 37 (12~63) winsize 52
2350 11:35:51.149347 [CA 1] Center 37 (12~63) winsize 52
2351 11:35:51.152691 [CA 2] Center 34 (6~63) winsize 58
2352 11:35:51.156125 [CA 3] Center 34 (6~63) winsize 58
2353 11:35:51.159291 [CA 4] Center 34 (6~63) winsize 58
2354 11:35:51.163045 [CA 5] Center 27 (-2~57) winsize 60
2355 11:35:51.163130
2356 11:35:51.166075 [CATrainingPosCal] consider 2 rank data
2357 11:35:51.169728 u2DelayCellTimex100 = 735/100 ps
2358 11:35:51.172852 CA0 delay=37 (12~63),Diff = 10 PI (13 cell)
2359 11:35:51.176033 CA1 delay=37 (12~63),Diff = 10 PI (13 cell)
2360 11:35:51.179694 CA2 delay=34 (6~63),Diff = 7 PI (9 cell)
2361 11:35:51.182867 CA3 delay=34 (6~63),Diff = 7 PI (9 cell)
2362 11:35:51.186268 CA4 delay=34 (6~63),Diff = 7 PI (9 cell)
2363 11:35:51.189981 CA5 delay=27 (-2~57),Diff = 0 PI (0 cell)
2364 11:35:51.190066
2365 11:35:51.192913 CA PerBit enable=1, Macro0, CA PI delay=27
2366 11:35:51.195981 === u2Vref_new: 0x5e --> 0x7a
2367 11:35:51.196071
2368 11:35:51.199707 Vref(ca) range 1: 30
2369 11:35:51.199790
2370 11:35:51.199854 CS Dly= 11 (42-0-32)
2371 11:35:51.202992 Write Rank1 MR13 =0xd8
2372 11:35:51.205962 Write Rank1 MR13 =0xd8
2373 11:35:51.206046 Write Rank1 MR12 =0x5e
2374 11:35:51.209357 [RankSwap] Rank num 2, (Multi 1), Rank 0
2375 11:35:51.213040 Write Rank0 MR2 =0xad
2376 11:35:51.213125 [Write Leveling]
2377 11:35:51.216465 delay byte0 byte1 byte2 byte3
2378 11:35:51.216554
2379 11:35:51.219419 10 0 0
2380 11:35:51.219522 11 0 0
2381 11:35:51.222913 12 0 0
2382 11:35:51.223027 13 0 0
2383 11:35:51.226288 14 0 0
2384 11:35:51.226397 15 0 0
2385 11:35:51.226541 16 0 0
2386 11:35:51.229718 17 0 0
2387 11:35:51.229805 18 0 0
2388 11:35:51.233491 19 0 0
2389 11:35:51.233605 20 0 0
2390 11:35:51.233703 21 0 0
2391 11:35:51.236385 22 0 0
2392 11:35:51.236492 23 0 0
2393 11:35:51.239618 24 0 0
2394 11:35:51.239702 25 0 ff
2395 11:35:51.243544 26 0 ff
2396 11:35:51.243658 27 0 ff
2397 11:35:51.243740 28 0 ff
2398 11:35:51.246241 29 0 ff
2399 11:35:51.246326 30 0 ff
2400 11:35:51.249659 31 0 ff
2401 11:35:51.249745 32 0 ff
2402 11:35:51.253353 33 0 ff
2403 11:35:51.253439 34 ff ff
2404 11:35:51.253506 35 ff ff
2405 11:35:51.256361 36 ff ff
2406 11:35:51.256480 37 ff ff
2407 11:35:51.259795 38 ff ff
2408 11:35:51.259880 39 ff ff
2409 11:35:51.263206 40 ff ff
2410 11:35:51.266386 pass bytecount = 0xff (0xff: all bytes pass)
2411 11:35:51.266470
2412 11:35:51.266535 DQS0 dly: 34
2413 11:35:51.270069 DQS1 dly: 25
2414 11:35:51.270154 Write Rank0 MR2 =0x2d
2415 11:35:51.273448 [RankSwap] Rank num 2, (Multi 1), Rank 0
2416 11:35:51.276388 Write Rank0 MR1 =0xd6
2417 11:35:51.276507 [Gating]
2418 11:35:51.276602 ==
2419 11:35:51.283252 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2420 11:35:51.286602 fsp= 1, odt_onoff= 1, Byte mode= 0
2421 11:35:51.286687 ==
2422 11:35:51.289935 3 1 0 |3635 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2423 11:35:51.293780 3 1 4 |1716 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2424 11:35:51.299921 3 1 8 |3535 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2425 11:35:51.303528 3 1 12 |3636 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2426 11:35:51.306846 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2427 11:35:51.314010 3 1 20 |3535 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2428 11:35:51.316601 [Byte 0] Lead/lag falling Transition (3, 1, 20)
2429 11:35:51.320289 3 1 24 |3535 2c2b |(11 11)(11 11) |(0 1)(1 1)| 0
2430 11:35:51.323686 [Byte 1] Lead/lag falling Transition (3, 1, 24)
2431 11:35:51.330052 3 1 28 |b0a 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2432 11:35:51.333555 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2433 11:35:51.336802 3 2 4 |3130 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
2434 11:35:51.343698 3 2 8 |3433 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2435 11:35:51.346680 3 2 12 |3332 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2436 11:35:51.350475 3 2 16 |3433 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2437 11:35:51.353924 [Byte 0] Lead/lag Transition tap number (1)
2438 11:35:51.360272 3 2 20 |1212 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2439 11:35:51.363213 [Byte 1] Lead/lag Transition tap number (8)
2440 11:35:51.366867 3 2 24 |2322 201 |(11 11)(11 11) |(1 1)(0 0)| 0
2441 11:35:51.373332 3 2 28 |3939 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2442 11:35:51.376871 3 3 0 |3c3b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2443 11:35:51.380135 3 3 4 |3130 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2444 11:35:51.383578 3 3 8 |3c3b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2445 11:35:51.389885 [Byte 0] Lead/lag Transition tap number (1)
2446 11:35:51.393397 3 3 12 |3b3b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2447 11:35:51.396430 3 3 16 |202 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2448 11:35:51.403327 3 3 20 |3231 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2449 11:35:51.406738 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2450 11:35:51.410233 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2451 11:35:51.413407 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2452 11:35:51.420095 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2453 11:35:51.423685 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2454 11:35:51.426993 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2455 11:35:51.433244 3 4 16 |808 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2456 11:35:51.436579 3 4 20 |707 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2457 11:35:51.439935 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2458 11:35:51.446864 3 4 28 |3d3d 3636 |(11 11)(11 11) |(1 1)(1 1)| 0
2459 11:35:51.450301 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2460 11:35:51.453739 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2461 11:35:51.456637 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2462 11:35:51.463833 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2463 11:35:51.467077 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2464 11:35:51.470097 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2465 11:35:51.477083 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2466 11:35:51.480645 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2467 11:35:51.483828 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2468 11:35:51.490586 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2469 11:35:51.493792 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2470 11:35:51.497168 [Byte 0] Lead/lag Transition tap number (1)
2471 11:35:51.500118 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2472 11:35:51.506901 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2473 11:35:51.510102 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2474 11:35:51.513677 3 6 20 |2222 3d3d |(1 1)(11 11) |(0 0)(1 0)| 0
2475 11:35:51.516772 [Byte 1] Lead/lag Transition tap number (2)
2476 11:35:51.523534 3 6 24 |4646 605 |(0 0)(11 11) |(0 0)(0 0)| 0
2477 11:35:51.523621 [Byte 0]First pass (3, 6, 24)
2478 11:35:51.530755 3 6 28 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
2479 11:35:51.533366 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2480 11:35:51.537290 [Byte 1]First pass (3, 7, 0)
2481 11:35:51.540529 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2482 11:35:51.543365 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2483 11:35:51.547139 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2484 11:35:51.550456 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2485 11:35:51.556828 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2486 11:35:51.560103 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2487 11:35:51.563955 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2488 11:35:51.566917 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2489 11:35:51.570071 All bytes gating window > 1UI, Early break!
2490 11:35:51.573476
2491 11:35:51.576878 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10)
2492 11:35:51.576962
2493 11:35:51.580439 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
2494 11:35:51.580534
2495 11:35:51.580600
2496 11:35:51.580659
2497 11:35:51.583640 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
2498 11:35:51.583724
2499 11:35:51.587339 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2500 11:35:51.587424
2501 11:35:51.587489
2502 11:35:51.590520 Write Rank0 MR1 =0x56
2503 11:35:51.590603
2504 11:35:51.593582 best RODT dly(2T, 0.5T) = (2, 3)
2505 11:35:51.593666
2506 11:35:51.596970 best RODT dly(2T, 0.5T) = (2, 3)
2507 11:35:51.597055 ==
2508 11:35:51.600258 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2509 11:35:51.603415 fsp= 1, odt_onoff= 1, Byte mode= 0
2510 11:35:51.603500 ==
2511 11:35:51.610540 Start DQ dly to find pass range UseTestEngine =0
2512 11:35:51.613710 x-axis: bit #, y-axis: DQ dly (-127~63)
2513 11:35:51.613795 RX Vref Scan = 0
2514 11:35:51.616800 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2515 11:35:51.619957 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2516 11:35:51.623372 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2517 11:35:51.626719 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2518 11:35:51.630095 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2519 11:35:51.633556 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2520 11:35:51.633633 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2521 11:35:51.636920 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2522 11:35:51.640539 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2523 11:35:51.643897 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2524 11:35:51.647039 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2525 11:35:51.650580 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2526 11:35:51.653405 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2527 11:35:51.656581 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2528 11:35:51.656667 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2529 11:35:51.660054 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2530 11:35:51.663552 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2531 11:35:51.666712 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2532 11:35:51.669935 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2533 11:35:51.673332 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2534 11:35:51.676891 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2535 11:35:51.676977 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2536 11:35:51.680424 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2537 11:35:51.683517 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2538 11:35:51.687060 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2539 11:35:51.690332 -1, [0] xxxxxxxx xoxxxxxo [MSB]
2540 11:35:51.693606 0, [0] xxxoxxxx ooxxxxxo [MSB]
2541 11:35:51.696911 1, [0] xxooxxxx ooxxxxxo [MSB]
2542 11:35:51.696997 2, [0] xxooxxxx ooxxxxxo [MSB]
2543 11:35:51.700188 3, [0] xxooxxxx oooxxxxo [MSB]
2544 11:35:51.703349 4, [0] xxooxxxo oooxxxxo [MSB]
2545 11:35:51.706618 32, [0] oooooooo ooooooox [MSB]
2546 11:35:51.710255 33, [0] oooooooo ooooooox [MSB]
2547 11:35:51.713494 34, [0] oooooooo ooooooox [MSB]
2548 11:35:51.716631 35, [0] oooxoooo ooooooox [MSB]
2549 11:35:51.716718 36, [0] oooxoooo xxooooox [MSB]
2550 11:35:51.720268 37, [0] ooxxoooo xxooooox [MSB]
2551 11:35:51.723730 38, [0] ooxxoooo xxooooox [MSB]
2552 11:35:51.726820 39, [0] ooxxooox xxooooox [MSB]
2553 11:35:51.729975 40, [0] oxxxxoox xxxoooox [MSB]
2554 11:35:51.733611 41, [0] oxxxxoox xxxxxxox [MSB]
2555 11:35:51.733699 42, [0] xxxxxxxx xxxxxxxx [MSB]
2556 11:35:51.740013 iDelay=42, Bit 0, Center 23 (5 ~ 41) 37
2557 11:35:51.743475 iDelay=42, Bit 1, Center 22 (5 ~ 39) 35
2558 11:35:51.746569 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
2559 11:35:51.749910 iDelay=42, Bit 3, Center 17 (0 ~ 34) 35
2560 11:35:51.753159 iDelay=42, Bit 4, Center 22 (5 ~ 39) 35
2561 11:35:51.756387 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
2562 11:35:51.759910 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
2563 11:35:51.763663 iDelay=42, Bit 7, Center 21 (4 ~ 38) 35
2564 11:35:51.766636 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
2565 11:35:51.770077 iDelay=42, Bit 9, Center 17 (-1 ~ 35) 37
2566 11:35:51.773443 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
2567 11:35:51.776720 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
2568 11:35:51.779996 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
2569 11:35:51.783122 iDelay=42, Bit 13, Center 22 (5 ~ 40) 36
2570 11:35:51.789856 iDelay=42, Bit 14, Center 23 (5 ~ 41) 37
2571 11:35:51.792927 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
2572 11:35:51.793013 ==
2573 11:35:51.796542 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2574 11:35:51.800046 fsp= 1, odt_onoff= 1, Byte mode= 0
2575 11:35:51.800132 ==
2576 11:35:51.803420 DQS Delay:
2577 11:35:51.803531 DQS0 = 0, DQS1 = 0
2578 11:35:51.803617 DQM Delay:
2579 11:35:51.806511 DQM0 = 21, DQM1 = 19
2580 11:35:51.806611 DQ Delay:
2581 11:35:51.809750 DQ0 =23, DQ1 =22, DQ2 =18, DQ3 =17
2582 11:35:51.813115 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =21
2583 11:35:51.816713 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22
2584 11:35:51.819883 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
2585 11:35:51.819968
2586 11:35:51.820069
2587 11:35:51.823521 DramC Write-DBI off
2588 11:35:51.823606 ==
2589 11:35:51.826670 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2590 11:35:51.829769 fsp= 1, odt_onoff= 1, Byte mode= 0
2591 11:35:51.829855 ==
2592 11:35:51.836984 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2593 11:35:51.837070
2594 11:35:51.837154 Begin, DQ Scan Range 921~1177
2595 11:35:51.840064
2596 11:35:51.840149
2597 11:35:51.840233 TX Vref Scan disable
2598 11:35:51.843301 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2599 11:35:51.846982 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2600 11:35:51.849957 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2601 11:35:51.853491 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2602 11:35:51.856771 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2603 11:35:51.863211 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2604 11:35:51.866739 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2605 11:35:51.870286 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2606 11:35:51.873469 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2607 11:35:51.876833 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2608 11:35:51.880080 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2609 11:35:51.883405 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2610 11:35:51.887013 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2611 11:35:51.890157 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2612 11:35:51.893662 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2613 11:35:51.896784 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2614 11:35:51.900419 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2615 11:35:51.903597 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2616 11:35:51.906577 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2617 11:35:51.909881 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2618 11:35:51.913543 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2619 11:35:51.919721 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2620 11:35:51.923451 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2621 11:35:51.926610 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2622 11:35:51.929875 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2623 11:35:51.933536 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2624 11:35:51.937420 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2625 11:35:51.939578 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2626 11:35:51.943455 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2627 11:35:51.946428 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2628 11:35:51.950059 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2629 11:35:51.953437 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2630 11:35:51.956305 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2631 11:35:51.960020 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2632 11:35:51.963226 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2633 11:35:51.966541 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2634 11:35:51.969783 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2635 11:35:51.976677 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2636 11:35:51.979816 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2637 11:35:51.982926 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2638 11:35:51.986525 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2639 11:35:51.990037 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2640 11:35:51.993191 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2641 11:35:51.996214 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2642 11:35:51.999867 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2643 11:35:52.003066 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2644 11:35:52.006481 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2645 11:35:52.010000 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2646 11:35:52.013062 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2647 11:35:52.016986 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2648 11:35:52.019910 971 |3 6 11|[0] xxxxxxxx ooxxxxxo [MSB]
2649 11:35:52.022970 972 |3 6 12|[0] xxxxxxxx ooxxxxxo [MSB]
2650 11:35:52.026196 973 |3 6 13|[0] xxxxxxxx ooxxxxxo [MSB]
2651 11:35:52.029982 974 |3 6 14|[0] xxxxxxxx oooxoxoo [MSB]
2652 11:35:52.033146 975 |3 6 15|[0] xxxxxxxx oooooxoo [MSB]
2653 11:35:52.036328 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2654 11:35:52.039758 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2655 11:35:52.043309 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2656 11:35:52.050032 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2657 11:35:52.053153 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2658 11:35:52.056765 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
2659 11:35:52.059931 982 |3 6 22|[0] xxxxxxxo oooooooo [MSB]
2660 11:35:52.063226 987 |3 6 27|[0] oooooooo ooooooox [MSB]
2661 11:35:52.066516 988 |3 6 28|[0] oooooooo ooooooox [MSB]
2662 11:35:52.070430 989 |3 6 29|[0] oooooooo oxooooox [MSB]
2663 11:35:52.073676 990 |3 6 30|[0] oooooooo oxooooox [MSB]
2664 11:35:52.076418 991 |3 6 31|[0] oooooooo xxooooox [MSB]
2665 11:35:52.080133 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2666 11:35:52.083177 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2667 11:35:52.086779 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2668 11:35:52.089889 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2669 11:35:52.092989 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2670 11:35:52.099745 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2671 11:35:52.103020 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2672 11:35:52.106475 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2673 11:35:52.109702 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2674 11:35:52.112926 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2675 11:35:52.116429 1002 |3 6 42|[0] ooxxooox xxxxxxxx [MSB]
2676 11:35:52.119709 1003 |3 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
2677 11:35:52.122838 Byte0, DQ PI dly=991, DQM PI dly= 991
2678 11:35:52.126793 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
2679 11:35:52.126880
2680 11:35:52.133187 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
2681 11:35:52.133272
2682 11:35:52.136751 Byte1, DQ PI dly=980, DQM PI dly= 980
2683 11:35:52.139767 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2684 11:35:52.139854
2685 11:35:52.142881 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2686 11:35:52.142967
2687 11:35:52.146630 ==
2688 11:35:52.149578 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2689 11:35:52.153021 fsp= 1, odt_onoff= 1, Byte mode= 0
2690 11:35:52.153107 ==
2691 11:35:52.156352 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2692 11:35:52.156438
2693 11:35:52.159679 Begin, DQ Scan Range 956~1020
2694 11:35:52.163180 Write Rank0 MR14 =0x0
2695 11:35:52.170965
2696 11:35:52.171050 CH=1, VrefRange= 0, VrefLevel = 0
2697 11:35:52.177489 TX Bit0 (985~1000) 16 992, Bit8 (975~985) 11 980,
2698 11:35:52.180884 TX Bit1 (984~997) 14 990, Bit9 (975~984) 10 979,
2699 11:35:52.187396 TX Bit2 (983~997) 15 990, Bit10 (976~987) 12 981,
2700 11:35:52.190670 TX Bit3 (981~992) 12 986, Bit11 (977~988) 12 982,
2701 11:35:52.194244 TX Bit4 (984~998) 15 991, Bit12 (977~988) 12 982,
2702 11:35:52.200559 TX Bit5 (985~999) 15 992, Bit13 (978~988) 11 983,
2703 11:35:52.204386 TX Bit6 (984~998) 15 991, Bit14 (976~987) 12 981,
2704 11:35:52.210383 TX Bit7 (984~997) 14 990, Bit15 (971~981) 11 976,
2705 11:35:52.210470
2706 11:35:52.213503 wait MRW command Rank0 MR14 =0x2 fired (1)
2707 11:35:52.213590 Write Rank0 MR14 =0x2
2708 11:35:52.224033
2709 11:35:52.224118 CH=1, VrefRange= 0, VrefLevel = 2
2710 11:35:52.230530 TX Bit0 (984~1001) 18 992, Bit8 (975~985) 11 980,
2711 11:35:52.233929 TX Bit1 (984~998) 15 991, Bit9 (975~984) 10 979,
2712 11:35:52.240516 TX Bit2 (982~998) 17 990, Bit10 (976~988) 13 982,
2713 11:35:52.243963 TX Bit3 (980~994) 15 987, Bit11 (977~989) 13 983,
2714 11:35:52.247323 TX Bit4 (983~999) 17 991, Bit12 (976~988) 13 982,
2715 11:35:52.253754 TX Bit5 (985~999) 15 992, Bit13 (977~990) 14 983,
2716 11:35:52.257097 TX Bit6 (984~999) 16 991, Bit14 (976~988) 13 982,
2717 11:35:52.260550 TX Bit7 (984~998) 15 991, Bit15 (970~983) 14 976,
2718 11:35:52.263435
2719 11:35:52.263540 Write Rank0 MR14 =0x4
2720 11:35:52.273090
2721 11:35:52.276209 CH=1, VrefRange= 0, VrefLevel = 4
2722 11:35:52.279589 TX Bit0 (984~1001) 18 992, Bit8 (973~985) 13 979,
2723 11:35:52.282857 TX Bit1 (983~999) 17 991, Bit9 (974~985) 12 979,
2724 11:35:52.289558 TX Bit2 (981~998) 18 989, Bit10 (976~989) 14 982,
2725 11:35:52.292778 TX Bit3 (980~995) 16 987, Bit11 (977~990) 14 983,
2726 11:35:52.296112 TX Bit4 (983~999) 17 991, Bit12 (976~990) 15 983,
2727 11:35:52.302875 TX Bit5 (985~999) 15 992, Bit13 (977~990) 14 983,
2728 11:35:52.306003 TX Bit6 (984~999) 16 991, Bit14 (976~990) 15 983,
2729 11:35:52.309420 TX Bit7 (984~998) 15 991, Bit15 (970~983) 14 976,
2730 11:35:52.312550
2731 11:35:52.312636 Write Rank0 MR14 =0x6
2732 11:35:52.322397
2733 11:35:52.322483 CH=1, VrefRange= 0, VrefLevel = 6
2734 11:35:52.329180 TX Bit0 (984~1002) 19 993, Bit8 (972~986) 15 979,
2735 11:35:52.332244 TX Bit1 (983~999) 17 991, Bit9 (973~985) 13 979,
2736 11:35:52.338878 TX Bit2 (982~999) 18 990, Bit10 (975~990) 16 982,
2737 11:35:52.342111 TX Bit3 (979~996) 18 987, Bit11 (977~991) 15 984,
2738 11:35:52.345663 TX Bit4 (983~1000) 18 991, Bit12 (976~990) 15 983,
2739 11:35:52.351851 TX Bit5 (984~1000) 17 992, Bit13 (977~991) 15 984,
2740 11:35:52.355265 TX Bit6 (983~999) 17 991, Bit14 (976~990) 15 983,
2741 11:35:52.361767 TX Bit7 (983~999) 17 991, Bit15 (970~984) 15 977,
2742 11:35:52.361854
2743 11:35:52.361946 Write Rank0 MR14 =0x8
2744 11:35:52.371737
2745 11:35:52.371823 CH=1, VrefRange= 0, VrefLevel = 8
2746 11:35:52.378192 TX Bit0 (984~1002) 19 993, Bit8 (972~987) 16 979,
2747 11:35:52.381804 TX Bit1 (982~999) 18 990, Bit9 (973~985) 13 979,
2748 11:35:52.388398 TX Bit2 (980~999) 20 989, Bit10 (975~991) 17 983,
2749 11:35:52.391529 TX Bit3 (979~997) 19 988, Bit11 (976~991) 16 983,
2750 11:35:52.395047 TX Bit4 (983~1000) 18 991, Bit12 (975~992) 18 983,
2751 11:35:52.401616 TX Bit5 (984~1001) 18 992, Bit13 (977~992) 16 984,
2752 11:35:52.405288 TX Bit6 (983~1000) 18 991, Bit14 (975~991) 17 983,
2753 11:35:52.411464 TX Bit7 (983~999) 17 991, Bit15 (969~984) 16 976,
2754 11:35:52.411551
2755 11:35:52.411635 Write Rank0 MR14 =0xa
2756 11:35:52.421584
2757 11:35:52.424636 CH=1, VrefRange= 0, VrefLevel = 10
2758 11:35:52.427861 TX Bit0 (983~1003) 21 993, Bit8 (972~987) 16 979,
2759 11:35:52.431387 TX Bit1 (982~1000) 19 991, Bit9 (972~986) 15 979,
2760 11:35:52.438075 TX Bit2 (980~999) 20 989, Bit10 (975~991) 17 983,
2761 11:35:52.441405 TX Bit3 (978~997) 20 987, Bit11 (976~992) 17 984,
2762 11:35:52.444558 TX Bit4 (982~1001) 20 991, Bit12 (975~992) 18 983,
2763 11:35:52.451252 TX Bit5 (984~1001) 18 992, Bit13 (977~992) 16 984,
2764 11:35:52.454389 TX Bit6 (983~1000) 18 991, Bit14 (975~992) 18 983,
2765 11:35:52.460929 TX Bit7 (983~1000) 18 991, Bit15 (969~985) 17 977,
2766 11:35:52.461015
2767 11:35:52.461101 Write Rank0 MR14 =0xc
2768 11:35:52.471799
2769 11:35:52.474742 CH=1, VrefRange= 0, VrefLevel = 12
2770 11:35:52.478076 TX Bit0 (983~1004) 22 993, Bit8 (972~988) 17 980,
2771 11:35:52.481807 TX Bit1 (982~1001) 20 991, Bit9 (971~986) 16 978,
2772 11:35:52.488038 TX Bit2 (980~1000) 21 990, Bit10 (975~992) 18 983,
2773 11:35:52.491507 TX Bit3 (978~998) 21 988, Bit11 (975~992) 18 983,
2774 11:35:52.494857 TX Bit4 (982~1001) 20 991, Bit12 (975~993) 19 984,
2775 11:35:52.501702 TX Bit5 (984~1002) 19 993, Bit13 (976~992) 17 984,
2776 11:35:52.504837 TX Bit6 (982~1001) 20 991, Bit14 (975~992) 18 983,
2777 11:35:52.511835 TX Bit7 (983~1000) 18 991, Bit15 (969~985) 17 977,
2778 11:35:52.511926
2779 11:35:52.512011 Write Rank0 MR14 =0xe
2780 11:35:52.521627
2781 11:35:52.525429 CH=1, VrefRange= 0, VrefLevel = 14
2782 11:35:52.528101 TX Bit0 (983~1004) 22 993, Bit8 (971~988) 18 979,
2783 11:35:52.531600 TX Bit1 (981~1001) 21 991, Bit9 (972~987) 16 979,
2784 11:35:52.538395 TX Bit2 (979~1000) 22 989, Bit10 (974~992) 19 983,
2785 11:35:52.542074 TX Bit3 (978~998) 21 988, Bit11 (975~992) 18 983,
2786 11:35:52.545013 TX Bit4 (982~1002) 21 992, Bit12 (975~993) 19 984,
2787 11:35:52.551642 TX Bit5 (984~1003) 20 993, Bit13 (976~992) 17 984,
2788 11:35:52.555179 TX Bit6 (982~1001) 20 991, Bit14 (974~993) 20 983,
2789 11:35:52.561579 TX Bit7 (982~1001) 20 991, Bit15 (969~986) 18 977,
2790 11:35:52.561664
2791 11:35:52.561729 Write Rank0 MR14 =0x10
2792 11:35:52.572224
2793 11:35:52.575367 CH=1, VrefRange= 0, VrefLevel = 16
2794 11:35:52.579404 TX Bit0 (983~1005) 23 994, Bit8 (971~990) 20 980,
2795 11:35:52.582296 TX Bit1 (981~1001) 21 991, Bit9 (971~988) 18 979,
2796 11:35:52.588870 TX Bit2 (979~1001) 23 990, Bit10 (974~992) 19 983,
2797 11:35:52.591807 TX Bit3 (978~998) 21 988, Bit11 (975~993) 19 984,
2798 11:35:52.595420 TX Bit4 (981~1002) 22 991, Bit12 (974~993) 20 983,
2799 11:35:52.602241 TX Bit5 (983~1003) 21 993, Bit13 (976~993) 18 984,
2800 11:35:52.605268 TX Bit6 (982~1002) 21 992, Bit14 (974~993) 20 983,
2801 11:35:52.612238 TX Bit7 (982~1002) 21 992, Bit15 (968~986) 19 977,
2802 11:35:52.612324
2803 11:35:52.612389 Write Rank0 MR14 =0x12
2804 11:35:52.622436
2805 11:35:52.625866 CH=1, VrefRange= 0, VrefLevel = 18
2806 11:35:52.629732 TX Bit0 (983~1005) 23 994, Bit8 (970~991) 22 980,
2807 11:35:52.632365 TX Bit1 (980~1002) 23 991, Bit9 (970~988) 19 979,
2808 11:35:52.639065 TX Bit2 (979~1001) 23 990, Bit10 (973~993) 21 983,
2809 11:35:52.642596 TX Bit3 (978~999) 22 988, Bit11 (975~993) 19 984,
2810 11:35:52.645985 TX Bit4 (981~1003) 23 992, Bit12 (974~994) 21 984,
2811 11:35:52.652807 TX Bit5 (983~1004) 22 993, Bit13 (976~993) 18 984,
2812 11:35:52.655586 TX Bit6 (981~1003) 23 992, Bit14 (974~993) 20 983,
2813 11:35:52.662438 TX Bit7 (982~1002) 21 992, Bit15 (968~987) 20 977,
2814 11:35:52.662523
2815 11:35:52.662588 Write Rank0 MR14 =0x14
2816 11:35:52.673426
2817 11:35:52.676562 CH=1, VrefRange= 0, VrefLevel = 20
2818 11:35:52.679792 TX Bit0 (982~1006) 25 994, Bit8 (970~991) 22 980,
2819 11:35:52.683044 TX Bit1 (980~1003) 24 991, Bit9 (971~988) 18 979,
2820 11:35:52.689880 TX Bit2 (978~1002) 25 990, Bit10 (973~993) 21 983,
2821 11:35:52.693173 TX Bit3 (978~999) 22 988, Bit11 (974~993) 20 983,
2822 11:35:52.696714 TX Bit4 (980~1004) 25 992, Bit12 (974~994) 21 984,
2823 11:35:52.703127 TX Bit5 (983~1004) 22 993, Bit13 (975~993) 19 984,
2824 11:35:52.706718 TX Bit6 (981~1003) 23 992, Bit14 (973~994) 22 983,
2825 11:35:52.713168 TX Bit7 (981~1002) 22 991, Bit15 (968~987) 20 977,
2826 11:35:52.713253
2827 11:35:52.713318 Write Rank0 MR14 =0x16
2828 11:35:52.723704
2829 11:35:52.727242 CH=1, VrefRange= 0, VrefLevel = 22
2830 11:35:52.730448 TX Bit0 (982~1006) 25 994, Bit8 (970~991) 22 980,
2831 11:35:52.733846 TX Bit1 (979~1003) 25 991, Bit9 (970~990) 21 980,
2832 11:35:52.740259 TX Bit2 (978~1002) 25 990, Bit10 (972~993) 22 982,
2833 11:35:52.743701 TX Bit3 (977~1000) 24 988, Bit11 (973~993) 21 983,
2834 11:35:52.747084 TX Bit4 (980~1005) 26 992, Bit12 (973~994) 22 983,
2835 11:35:52.753745 TX Bit5 (983~1005) 23 994, Bit13 (975~994) 20 984,
2836 11:35:52.757093 TX Bit6 (980~1004) 25 992, Bit14 (972~994) 23 983,
2837 11:35:52.763632 TX Bit7 (980~1003) 24 991, Bit15 (968~988) 21 978,
2838 11:35:52.763719
2839 11:35:52.763803 Write Rank0 MR14 =0x18
2840 11:35:52.774217
2841 11:35:52.777834 CH=1, VrefRange= 0, VrefLevel = 24
2842 11:35:52.781009 TX Bit0 (981~1006) 26 993, Bit8 (970~992) 23 981,
2843 11:35:52.784208 TX Bit1 (979~1004) 26 991, Bit9 (970~990) 21 980,
2844 11:35:52.791386 TX Bit2 (978~1003) 26 990, Bit10 (972~994) 23 983,
2845 11:35:52.794582 TX Bit3 (977~1000) 24 988, Bit11 (973~994) 22 983,
2846 11:35:52.797680 TX Bit4 (980~1005) 26 992, Bit12 (973~994) 22 983,
2847 11:35:52.804225 TX Bit5 (982~1006) 25 994, Bit13 (975~994) 20 984,
2848 11:35:52.807524 TX Bit6 (980~1005) 26 992, Bit14 (972~995) 24 983,
2849 11:35:52.814209 TX Bit7 (980~1004) 25 992, Bit15 (968~989) 22 978,
2850 11:35:52.814292
2851 11:35:52.814358 Write Rank0 MR14 =0x1a
2852 11:35:52.825209
2853 11:35:52.828310 CH=1, VrefRange= 0, VrefLevel = 26
2854 11:35:52.831950 TX Bit0 (981~1006) 26 993, Bit8 (970~992) 23 981,
2855 11:35:52.834985 TX Bit1 (979~1005) 27 992, Bit9 (970~991) 22 980,
2856 11:35:52.841697 TX Bit2 (978~1003) 26 990, Bit10 (971~994) 24 982,
2857 11:35:52.845084 TX Bit3 (977~1000) 24 988, Bit11 (972~995) 24 983,
2858 11:35:52.848216 TX Bit4 (979~1005) 27 992, Bit12 (972~995) 24 983,
2859 11:35:52.855141 TX Bit5 (982~1006) 25 994, Bit13 (975~995) 21 985,
2860 11:35:52.858292 TX Bit6 (980~1005) 26 992, Bit14 (972~995) 24 983,
2861 11:35:52.865296 TX Bit7 (980~1004) 25 992, Bit15 (968~991) 24 979,
2862 11:35:52.865380
2863 11:35:52.865444 Write Rank0 MR14 =0x1c
2864 11:35:52.875900
2865 11:35:52.879078 CH=1, VrefRange= 0, VrefLevel = 28
2866 11:35:52.882238 TX Bit0 (980~1006) 27 993, Bit8 (969~992) 24 980,
2867 11:35:52.886005 TX Bit1 (979~1005) 27 992, Bit9 (969~991) 23 980,
2868 11:35:52.892574 TX Bit2 (978~1003) 26 990, Bit10 (971~994) 24 982,
2869 11:35:52.895819 TX Bit3 (977~1000) 24 988, Bit11 (972~995) 24 983,
2870 11:35:52.899247 TX Bit4 (979~1006) 28 992, Bit12 (972~995) 24 983,
2871 11:35:52.905680 TX Bit5 (981~1006) 26 993, Bit13 (974~996) 23 985,
2872 11:35:52.909168 TX Bit6 (979~1005) 27 992, Bit14 (971~995) 25 983,
2873 11:35:52.915473 TX Bit7 (979~1005) 27 992, Bit15 (967~990) 24 978,
2874 11:35:52.915583
2875 11:35:52.915687 Write Rank0 MR14 =0x1e
2876 11:35:52.926409
2877 11:35:52.929758 CH=1, VrefRange= 0, VrefLevel = 30
2878 11:35:52.933159 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2879 11:35:52.936648 TX Bit1 (979~1006) 28 992, Bit9 (970~992) 23 981,
2880 11:35:52.943218 TX Bit2 (978~1003) 26 990, Bit10 (971~995) 25 983,
2881 11:35:52.946404 TX Bit3 (977~1001) 25 989, Bit11 (972~995) 24 983,
2882 11:35:52.949826 TX Bit4 (980~1006) 27 993, Bit12 (972~995) 24 983,
2883 11:35:52.956290 TX Bit5 (981~1006) 26 993, Bit13 (974~996) 23 985,
2884 11:35:52.959805 TX Bit6 (979~1006) 28 992, Bit14 (971~995) 25 983,
2885 11:35:52.966125 TX Bit7 (979~1006) 28 992, Bit15 (967~989) 23 978,
2886 11:35:52.966201
2887 11:35:52.966282 Write Rank0 MR14 =0x20
2888 11:35:52.977228
2889 11:35:52.980362 CH=1, VrefRange= 0, VrefLevel = 32
2890 11:35:52.983788 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2891 11:35:52.987065 TX Bit1 (979~1006) 28 992, Bit9 (970~992) 23 981,
2892 11:35:52.993794 TX Bit2 (978~1003) 26 990, Bit10 (971~995) 25 983,
2893 11:35:52.997305 TX Bit3 (977~1001) 25 989, Bit11 (972~995) 24 983,
2894 11:35:53.000367 TX Bit4 (980~1006) 27 993, Bit12 (972~995) 24 983,
2895 11:35:53.007340 TX Bit5 (981~1006) 26 993, Bit13 (974~996) 23 985,
2896 11:35:53.010439 TX Bit6 (979~1006) 28 992, Bit14 (971~995) 25 983,
2897 11:35:53.017711 TX Bit7 (979~1006) 28 992, Bit15 (967~989) 23 978,
2898 11:35:53.017798
2899 11:35:53.017875 Write Rank0 MR14 =0x22
2900 11:35:53.027985
2901 11:35:53.031228 CH=1, VrefRange= 0, VrefLevel = 34
2902 11:35:53.034276 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2903 11:35:53.037611 TX Bit1 (979~1006) 28 992, Bit9 (970~992) 23 981,
2904 11:35:53.044701 TX Bit2 (978~1003) 26 990, Bit10 (971~995) 25 983,
2905 11:35:53.047787 TX Bit3 (977~1001) 25 989, Bit11 (972~995) 24 983,
2906 11:35:53.051419 TX Bit4 (980~1006) 27 993, Bit12 (972~995) 24 983,
2907 11:35:53.057673 TX Bit5 (981~1006) 26 993, Bit13 (974~996) 23 985,
2908 11:35:53.061101 TX Bit6 (979~1006) 28 992, Bit14 (971~995) 25 983,
2909 11:35:53.068011 TX Bit7 (979~1006) 28 992, Bit15 (967~989) 23 978,
2910 11:35:53.068094
2911 11:35:53.068157 Write Rank0 MR14 =0x24
2912 11:35:53.078900
2913 11:35:53.078978 CH=1, VrefRange= 0, VrefLevel = 36
2914 11:35:53.085256 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2915 11:35:53.088548 TX Bit1 (979~1006) 28 992, Bit9 (970~992) 23 981,
2916 11:35:53.095403 TX Bit2 (978~1003) 26 990, Bit10 (971~995) 25 983,
2917 11:35:53.098417 TX Bit3 (977~1001) 25 989, Bit11 (972~995) 24 983,
2918 11:35:53.101879 TX Bit4 (980~1006) 27 993, Bit12 (972~995) 24 983,
2919 11:35:53.108581 TX Bit5 (981~1006) 26 993, Bit13 (974~996) 23 985,
2920 11:35:53.111747 TX Bit6 (979~1006) 28 992, Bit14 (971~995) 25 983,
2921 11:35:53.118504 TX Bit7 (979~1006) 28 992, Bit15 (967~989) 23 978,
2922 11:35:53.118590
2923 11:35:53.118655 Write Rank0 MR14 =0x26
2924 11:35:53.129077
2925 11:35:53.132529 CH=1, VrefRange= 0, VrefLevel = 38
2926 11:35:53.135839 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2927 11:35:53.139442 TX Bit1 (979~1006) 28 992, Bit9 (970~992) 23 981,
2928 11:35:53.145895 TX Bit2 (978~1003) 26 990, Bit10 (971~995) 25 983,
2929 11:35:53.149198 TX Bit3 (977~1001) 25 989, Bit11 (972~995) 24 983,
2930 11:35:53.152500 TX Bit4 (980~1006) 27 993, Bit12 (972~995) 24 983,
2931 11:35:53.159289 TX Bit5 (981~1006) 26 993, Bit13 (974~996) 23 985,
2932 11:35:53.162392 TX Bit6 (979~1006) 28 992, Bit14 (971~995) 25 983,
2933 11:35:53.169418 TX Bit7 (979~1006) 28 992, Bit15 (967~989) 23 978,
2934 11:35:53.169491
2935 11:35:53.169553
2936 11:35:53.172716 TX Vref found, early break! 382< 386
2937 11:35:53.175816 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2938 11:35:53.179096 u1DelayCellOfst[0]=5 cells (4 PI)
2939 11:35:53.182383 u1DelayCellOfst[1]=3 cells (3 PI)
2940 11:35:53.185730 u1DelayCellOfst[2]=1 cells (1 PI)
2941 11:35:53.189159 u1DelayCellOfst[3]=0 cells (0 PI)
2942 11:35:53.192300 u1DelayCellOfst[4]=5 cells (4 PI)
2943 11:35:53.195574 u1DelayCellOfst[5]=5 cells (4 PI)
2944 11:35:53.199182 u1DelayCellOfst[6]=3 cells (3 PI)
2945 11:35:53.199266 u1DelayCellOfst[7]=3 cells (3 PI)
2946 11:35:53.202725 Byte0, DQ PI dly=989, DQM PI dly= 991
2947 11:35:53.208852 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2948 11:35:53.208947
2949 11:35:53.212579 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2950 11:35:53.212663
2951 11:35:53.215603 u1DelayCellOfst[8]=3 cells (3 PI)
2952 11:35:53.219336 u1DelayCellOfst[9]=3 cells (3 PI)
2953 11:35:53.222155 u1DelayCellOfst[10]=6 cells (5 PI)
2954 11:35:53.225734 u1DelayCellOfst[11]=6 cells (5 PI)
2955 11:35:53.229296 u1DelayCellOfst[12]=6 cells (5 PI)
2956 11:35:53.232145 u1DelayCellOfst[13]=9 cells (7 PI)
2957 11:35:53.235448 u1DelayCellOfst[14]=6 cells (5 PI)
2958 11:35:53.239201 u1DelayCellOfst[15]=0 cells (0 PI)
2959 11:35:53.242423 Byte1, DQ PI dly=978, DQM PI dly= 981
2960 11:35:53.245699 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2961 11:35:53.245783
2962 11:35:53.248679 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2963 11:35:53.248763
2964 11:35:53.252413 Write Rank0 MR14 =0x1e
2965 11:35:53.252504
2966 11:35:53.255485 Final TX Range 0 Vref 30
2967 11:35:53.255569
2968 11:35:53.262039 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2969 11:35:53.262121
2970 11:35:53.268589 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2971 11:35:53.275270 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2972 11:35:53.282331 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2973 11:35:53.282414 Write Rank0 MR3 =0xb0
2974 11:35:53.285499 DramC Write-DBI on
2975 11:35:53.285576 ==
2976 11:35:53.291824 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2977 11:35:53.291922 fsp= 1, odt_onoff= 1, Byte mode= 0
2978 11:35:53.295534 ==
2979 11:35:53.298833 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2980 11:35:53.298912
2981 11:35:53.301743 Begin, DQ Scan Range 701~765
2982 11:35:53.301947
2983 11:35:53.302054
2984 11:35:53.302138 TX Vref Scan disable
2985 11:35:53.305357 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2986 11:35:53.311796 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2987 11:35:53.315214 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2988 11:35:53.318556 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2989 11:35:53.321825 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2990 11:35:53.325417 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2991 11:35:53.328866 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2992 11:35:53.331843 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2993 11:35:53.335194 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2994 11:35:53.338273 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2995 11:35:53.341721 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2996 11:35:53.345395 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2997 11:35:53.348403 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2998 11:35:53.351621 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2999 11:35:53.355021 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3000 11:35:53.358736 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3001 11:35:53.361695 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3002 11:35:53.365273 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3003 11:35:53.368713 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3004 11:35:53.371575 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3005 11:35:53.374926 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3006 11:35:53.381448 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3007 11:35:53.384966 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3008 11:35:53.388141 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3009 11:35:53.391584 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3010 11:35:53.395474 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3011 11:35:53.401452 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3012 11:35:53.404761 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3013 11:35:53.407995 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3014 11:35:53.411364 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3015 11:35:53.414443 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3016 11:35:53.417860 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3017 11:35:53.421439 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3018 11:35:53.424868 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3019 11:35:53.427934 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3020 11:35:53.431172 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3021 11:35:53.434872 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3022 11:35:53.437981 Byte0, DQ PI dly=737, DQM PI dly= 737
3023 11:35:53.444697 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
3024 11:35:53.444772
3025 11:35:53.448200 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
3026 11:35:53.448274
3027 11:35:53.451370 Byte1, DQ PI dly=725, DQM PI dly= 725
3028 11:35:53.454669 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
3029 11:35:53.454740
3030 11:35:53.461396 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
3031 11:35:53.461470
3032 11:35:53.467762 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3033 11:35:53.474771 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3034 11:35:53.481006 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3035 11:35:53.481088 Write Rank0 MR3 =0x30
3036 11:35:53.484422 DramC Write-DBI off
3037 11:35:53.484508
3038 11:35:53.484576 [DATLAT]
3039 11:35:53.487841 Freq=1600, CH1 RK0, use_rxtx_scan=0
3040 11:35:53.487909
3041 11:35:53.490957 DATLAT Default: 0xf
3042 11:35:53.491031 7, 0xFFFF, sum=0
3043 11:35:53.494646 8, 0xFFFF, sum=0
3044 11:35:53.494719 9, 0xFFFF, sum=0
3045 11:35:53.497947 10, 0xFFFF, sum=0
3046 11:35:53.498019 11, 0xFFFF, sum=0
3047 11:35:53.501578 12, 0xFFFF, sum=0
3048 11:35:53.501655 13, 0xFFFF, sum=0
3049 11:35:53.504361 14, 0x0, sum=1
3050 11:35:53.504430 15, 0x0, sum=2
3051 11:35:53.504501 16, 0x0, sum=3
3052 11:35:53.507776 17, 0x0, sum=4
3053 11:35:53.511366 pattern=2 first_step=14 total pass=5 best_step=16
3054 11:35:53.511446 ==
3055 11:35:53.518004 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3056 11:35:53.521037 fsp= 1, odt_onoff= 1, Byte mode= 0
3057 11:35:53.521113 ==
3058 11:35:53.524569 Start DQ dly to find pass range UseTestEngine =1
3059 11:35:53.527674 x-axis: bit #, y-axis: DQ dly (-127~63)
3060 11:35:53.531162 RX Vref Scan = 1
3061 11:35:53.637369
3062 11:35:53.637474 RX Vref found, early break!
3063 11:35:53.637542
3064 11:35:53.643430 Final RX Vref 11, apply to both rank0 and 1
3065 11:35:53.643513 ==
3066 11:35:53.647139 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3067 11:35:53.650212 fsp= 1, odt_onoff= 1, Byte mode= 0
3068 11:35:53.650284 ==
3069 11:35:53.650345 DQS Delay:
3070 11:35:53.653615 DQS0 = 0, DQS1 = 0
3071 11:35:53.653688 DQM Delay:
3072 11:35:53.657066 DQM0 = 20, DQM1 = 19
3073 11:35:53.657133 DQ Delay:
3074 11:35:53.660097 DQ0 =21, DQ1 =22, DQ2 =18, DQ3 =16
3075 11:35:53.663268 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =21
3076 11:35:53.667094 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3077 11:35:53.670207 DQ12 =22, DQ13 =21, DQ14 =23, DQ15 =13
3078 11:35:53.670272
3079 11:35:53.670329
3080 11:35:53.670384
3081 11:35:53.673701 [DramC_TX_OE_Calibration] TA2
3082 11:35:53.677122 Original DQ_B0 (3 6) =30, OEN = 27
3083 11:35:53.680095 Original DQ_B1 (3 6) =30, OEN = 27
3084 11:35:53.683529 23, 0x0, End_B0=23 End_B1=23
3085 11:35:53.683608 24, 0x0, End_B0=24 End_B1=24
3086 11:35:53.686938 25, 0x0, End_B0=25 End_B1=25
3087 11:35:53.690227 26, 0x0, End_B0=26 End_B1=26
3088 11:35:53.693523 27, 0x0, End_B0=27 End_B1=27
3089 11:35:53.696998 28, 0x0, End_B0=28 End_B1=28
3090 11:35:53.697072 29, 0x0, End_B0=29 End_B1=29
3091 11:35:53.699829 30, 0x0, End_B0=30 End_B1=30
3092 11:35:53.703231 31, 0xFFFF, End_B0=30 End_B1=30
3093 11:35:53.710214 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3094 11:35:53.713097 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3095 11:35:53.713199
3096 11:35:53.713293
3097 11:35:53.716604 Write Rank0 MR23 =0x3f
3098 11:35:53.716701 [DQSOSC]
3099 11:35:53.726147 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3100 11:35:53.733348 CH1_RK0: MR19=0x202, MR18=0xBFBF, DQSOSC=448, MR23=63, INC=12, DEC=18
3101 11:35:53.733421 Write Rank0 MR23 =0x3f
3102 11:35:53.736134 [DQSOSC]
3103 11:35:53.742796 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3104 11:35:53.746456 CH1 RK0: MR19=202, MR18=BFBF
3105 11:35:53.749583 [RankSwap] Rank num 2, (Multi 1), Rank 1
3106 11:35:53.749656 Write Rank0 MR2 =0xad
3107 11:35:53.752745 [Write Leveling]
3108 11:35:53.755940 delay byte0 byte1 byte2 byte3
3109 11:35:53.756008
3110 11:35:53.756065 10 0 0
3111 11:35:53.759594 11 0 0
3112 11:35:53.759689 12 0 0
3113 11:35:53.762763 13 0 0
3114 11:35:53.762861 14 0 0
3115 11:35:53.762949 15 0 0
3116 11:35:53.765902 16 0 0
3117 11:35:53.765986 17 0 0
3118 11:35:53.769509 18 0 0
3119 11:35:53.769592 19 0 0
3120 11:35:53.769656 20 0 0
3121 11:35:53.772588 21 0 0
3122 11:35:53.772657 22 0 0
3123 11:35:53.776183 23 0 0
3124 11:35:53.776249 24 0 ff
3125 11:35:53.779245 25 0 ff
3126 11:35:53.779317 26 0 ff
3127 11:35:53.779376 27 0 ff
3128 11:35:53.783182 28 0 ff
3129 11:35:53.783248 29 0 ff
3130 11:35:53.786288 30 0 ff
3131 11:35:53.786365 31 0 ff
3132 11:35:53.789387 32 0 ff
3133 11:35:53.789460 33 0 ff
3134 11:35:53.793193 34 0 ff
3135 11:35:53.793267 35 ff ff
3136 11:35:53.793335 36 ff ff
3137 11:35:53.796032 37 ff ff
3138 11:35:53.796111 38 ff ff
3139 11:35:53.799497 39 ff ff
3140 11:35:53.799572 40 ff ff
3141 11:35:53.802460 41 ff ff
3142 11:35:53.805918 pass bytecount = 0xff (0xff: all bytes pass)
3143 11:35:53.805984
3144 11:35:53.806041 DQS0 dly: 35
3145 11:35:53.809398 DQS1 dly: 24
3146 11:35:53.809463 Write Rank0 MR2 =0x2d
3147 11:35:53.815944 [RankSwap] Rank num 2, (Multi 1), Rank 0
3148 11:35:53.816013 Write Rank1 MR1 =0xd6
3149 11:35:53.816076 [Gating]
3150 11:35:53.816133 ==
3151 11:35:53.822562 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3152 11:35:53.825989 fsp= 1, odt_onoff= 1, Byte mode= 0
3153 11:35:53.826067 ==
3154 11:35:53.829095 3 1 0 |1b1a 2c2b |(11 11)(11 11) |(1 0)(1 1)| 0
3155 11:35:53.835991 3 1 4 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3156 11:35:53.839131 3 1 8 |3434 2c2b |(0 0)(11 11) |(0 1)(1 0)| 0
3157 11:35:53.842720 3 1 12 |3434 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3158 11:35:53.845838 3 1 16 |3635 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3159 11:35:53.852596 3 1 20 |3232 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3160 11:35:53.855720 3 1 24 |3535 2c2b |(10 10)(11 11) |(0 1)(1 0)| 0
3161 11:35:53.858871 3 1 28 |3434 2c2b |(0 0)(11 11) |(1 0)(1 0)| 0
3162 11:35:53.865720 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3163 11:35:53.868902 3 2 4 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3164 11:35:53.872411 3 2 8 |1a19 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3165 11:35:53.875665 3 2 12 |3c3c 807 |(0 0)(11 1) |(1 1)(0 0)| 0
3166 11:35:53.882749 3 2 16 |3d3c 303 |(11 11)(11 11) |(1 1)(0 0)| 0
3167 11:35:53.885606 3 2 20 |3a3a 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3168 11:35:53.888717 3 2 24 |201f 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3169 11:35:53.895440 3 2 28 |3c3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3170 11:35:53.899121 3 3 0 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3171 11:35:53.902342 3 3 4 |3b3a 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3172 11:35:53.908640 3 3 8 |201 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3173 11:35:53.911939 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3174 11:35:53.915631 [Byte 0] Lead/lag falling Transition (3, 3, 12)
3175 11:35:53.922210 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3176 11:35:53.925198 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3177 11:35:53.928994 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3178 11:35:53.935244 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3179 11:35:53.938476 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3180 11:35:53.941772 3 4 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3181 11:35:53.945261 3 4 8 |707 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3182 11:35:53.952007 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3183 11:35:53.955040 3 4 16 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
3184 11:35:53.958604 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3185 11:35:53.964820 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3186 11:35:53.968127 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3187 11:35:53.971460 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3188 11:35:53.978234 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3189 11:35:53.981504 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3190 11:35:53.984757 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3191 11:35:53.991542 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3192 11:35:53.995128 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3193 11:35:53.998430 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3194 11:35:54.005157 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3195 11:35:54.008270 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3196 11:35:54.011432 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3197 11:35:54.014848 [Byte 0] Lead/lag Transition tap number (3)
3198 11:35:54.021484 3 6 4 |202 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3199 11:35:54.024900 [Byte 1] Lead/lag falling Transition (3, 6, 4)
3200 11:35:54.028444 3 6 8 |3232 3d3d |(1 1)(11 11) |(0 0)(1 0)| 0
3201 11:35:54.031575 [Byte 1] Lead/lag Transition tap number (2)
3202 11:35:54.035052 3 6 12 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3203 11:35:54.038170 [Byte 0]First pass (3, 6, 12)
3204 11:35:54.044523 3 6 16 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
3205 11:35:54.047999 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3206 11:35:54.051198 [Byte 1]First pass (3, 6, 20)
3207 11:35:54.055030 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3208 11:35:54.058121 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3209 11:35:54.061514 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3210 11:35:54.064644 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3211 11:35:54.071244 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3212 11:35:54.074737 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3213 11:35:54.077823 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3214 11:35:54.081219 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3215 11:35:54.084802 All bytes gating window > 1UI, Early break!
3216 11:35:54.084886
3217 11:35:54.091104 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 30)
3218 11:35:54.091204
3219 11:35:54.094503 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
3220 11:35:54.094602
3221 11:35:54.094690
3222 11:35:54.094778
3223 11:35:54.098104 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3224 11:35:54.098174
3225 11:35:54.101093 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
3226 11:35:54.101162
3227 11:35:54.101222
3228 11:35:54.104936 Write Rank1 MR1 =0x56
3229 11:35:54.105007
3230 11:35:54.108109 best RODT dly(2T, 0.5T) = (2, 2)
3231 11:35:54.108204
3232 11:35:54.111300 best RODT dly(2T, 0.5T) = (2, 3)
3233 11:35:54.111396 ==
3234 11:35:54.114473 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3235 11:35:54.117984 fsp= 1, odt_onoff= 1, Byte mode= 0
3236 11:35:54.118083 ==
3237 11:35:54.124381 Start DQ dly to find pass range UseTestEngine =0
3238 11:35:54.127954 x-axis: bit #, y-axis: DQ dly (-127~63)
3239 11:35:54.128029 RX Vref Scan = 0
3240 11:35:54.131256 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3241 11:35:54.134750 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3242 11:35:54.137611 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3243 11:35:54.140895 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3244 11:35:54.144178 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3245 11:35:54.144248 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3246 11:35:54.147873 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3247 11:35:54.151063 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3248 11:35:54.154508 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3249 11:35:54.157368 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3250 11:35:54.161011 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3251 11:35:54.164403 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3252 11:35:54.167830 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3253 11:35:54.170924 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3254 11:35:54.171024 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3255 11:35:54.174273 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3256 11:35:54.177749 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3257 11:35:54.181020 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3258 11:35:54.184181 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3259 11:35:54.187527 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3260 11:35:54.191098 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3261 11:35:54.191200 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3262 11:35:54.194519 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3263 11:35:54.197408 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3264 11:35:54.200726 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3265 11:35:54.204099 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3266 11:35:54.207726 0, [0] xxxoxxxx xoxxxxxo [MSB]
3267 11:35:54.210756 1, [0] xxooxxxx ooxxxxxo [MSB]
3268 11:35:54.210849 2, [0] xxooxxxx ooxxxxxo [MSB]
3269 11:35:54.214347 3, [0] xxooxxxo oooxxxxo [MSB]
3270 11:35:54.217504 4, [0] oxoooxxo oooxxxxo [MSB]
3271 11:35:54.221184 5, [0] oooooxoo ooooooxo [MSB]
3272 11:35:54.224379 32, [0] oooooooo ooooooox [MSB]
3273 11:35:54.227458 33, [0] oooooooo ooooooox [MSB]
3274 11:35:54.227535 34, [0] oooooooo ooooooox [MSB]
3275 11:35:54.230646 35, [0] oooxoooo xxooooox [MSB]
3276 11:35:54.234417 36, [0] oooxoooo xxooooox [MSB]
3277 11:35:54.237535 37, [0] ooxxoooo xxooooox [MSB]
3278 11:35:54.240861 38, [0] ooxxoooo xxooooox [MSB]
3279 11:35:54.244433 39, [0] oxxxxoox xxooooox [MSB]
3280 11:35:54.247233 40, [0] oxxxxoox xxxoooox [MSB]
3281 11:35:54.247320 41, [0] oxxxxoox xxxxxoox [MSB]
3282 11:35:54.250578 42, [0] xxxxxxxx xxxxxxxx [MSB]
3283 11:35:54.254026 iDelay=42, Bit 0, Center 22 (4 ~ 41) 38
3284 11:35:54.257220 iDelay=42, Bit 1, Center 21 (5 ~ 38) 34
3285 11:35:54.260603 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
3286 11:35:54.267299 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3287 11:35:54.270713 iDelay=42, Bit 4, Center 21 (4 ~ 38) 35
3288 11:35:54.274561 iDelay=42, Bit 5, Center 23 (6 ~ 41) 36
3289 11:35:54.277443 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3290 11:35:54.280611 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3291 11:35:54.284094 iDelay=42, Bit 8, Center 17 (1 ~ 34) 34
3292 11:35:54.287120 iDelay=42, Bit 9, Center 17 (0 ~ 34) 35
3293 11:35:54.290512 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3294 11:35:54.293963 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
3295 11:35:54.297493 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
3296 11:35:54.300592 iDelay=42, Bit 13, Center 23 (5 ~ 41) 37
3297 11:35:54.304011 iDelay=42, Bit 14, Center 23 (6 ~ 41) 36
3298 11:35:54.307362 iDelay=42, Bit 15, Center 14 (-2 ~ 31) 34
3299 11:35:54.310951 ==
3300 11:35:54.313971 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3301 11:35:54.317333 fsp= 1, odt_onoff= 1, Byte mode= 0
3302 11:35:54.317416 ==
3303 11:35:54.317479 DQS Delay:
3304 11:35:54.320374 DQS0 = 0, DQS1 = 0
3305 11:35:54.320463 DQM Delay:
3306 11:35:54.323935 DQM0 = 20, DQM1 = 19
3307 11:35:54.324017 DQ Delay:
3308 11:35:54.327386 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3309 11:35:54.330429 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
3310 11:35:54.334289 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22
3311 11:35:54.337027 DQ12 =22, DQ13 =23, DQ14 =23, DQ15 =14
3312 11:35:54.337110
3313 11:35:54.337173
3314 11:35:54.340823 DramC Write-DBI off
3315 11:35:54.340906 ==
3316 11:35:54.343600 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3317 11:35:54.347366 fsp= 1, odt_onoff= 1, Byte mode= 0
3318 11:35:54.347488 ==
3319 11:35:54.353678 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3320 11:35:54.353766
3321 11:35:54.353840 Begin, DQ Scan Range 920~1176
3322 11:35:54.353901
3323 11:35:54.353959
3324 11:35:54.357273 TX Vref Scan disable
3325 11:35:54.360390 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
3326 11:35:54.363835 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3327 11:35:54.367160 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3328 11:35:54.370470 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3329 11:35:54.373767 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3330 11:35:54.377335 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3331 11:35:54.383665 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3332 11:35:54.386842 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3333 11:35:54.390094 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3334 11:35:54.393571 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3335 11:35:54.397082 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3336 11:35:54.400408 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3337 11:35:54.403561 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3338 11:35:54.406862 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3339 11:35:54.410202 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3340 11:35:54.413841 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3341 11:35:54.417127 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3342 11:35:54.420366 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3343 11:35:54.423667 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3344 11:35:54.427441 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3345 11:35:54.430279 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3346 11:35:54.433504 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3347 11:35:54.437050 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3348 11:35:54.443693 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3349 11:35:54.446828 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3350 11:35:54.450689 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3351 11:35:54.453850 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3352 11:35:54.456912 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3353 11:35:54.460065 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3354 11:35:54.463557 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3355 11:35:54.466771 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3356 11:35:54.470499 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3357 11:35:54.473506 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3358 11:35:54.477060 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3359 11:35:54.480232 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3360 11:35:54.483526 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3361 11:35:54.486785 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3362 11:35:54.490468 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3363 11:35:54.493693 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3364 11:35:54.500351 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3365 11:35:54.503500 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3366 11:35:54.506978 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3367 11:35:54.510266 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3368 11:35:54.513609 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3369 11:35:54.516728 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3370 11:35:54.520106 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3371 11:35:54.523743 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3372 11:35:54.526854 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3373 11:35:54.529936 968 |3 6 8|[0] xxxxxxxx ooxxxxxo [MSB]
3374 11:35:54.533405 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
3375 11:35:54.536585 970 |3 6 10|[0] xxxxxxxx ooooooxo [MSB]
3376 11:35:54.539942 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3377 11:35:54.543487 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3378 11:35:54.546535 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3379 11:35:54.549983 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3380 11:35:54.553729 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3381 11:35:54.556935 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3382 11:35:54.560340 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3383 11:35:54.563512 978 |3 6 18|[0] xxooxxxx oooooooo [MSB]
3384 11:35:54.570216 979 |3 6 19|[0] xooooxxx oooooooo [MSB]
3385 11:35:54.573437 980 |3 6 20|[0] xoooooox oooooooo [MSB]
3386 11:35:54.576888 985 |3 6 25|[0] oooooooo ooooooox [MSB]
3387 11:35:54.579874 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3388 11:35:54.583275 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB]
3389 11:35:54.586597 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
3390 11:35:54.590060 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
3391 11:35:54.593613 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3392 11:35:54.596467 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3393 11:35:54.600093 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3394 11:35:54.603309 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3395 11:35:54.606789 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3396 11:35:54.613088 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3397 11:35:54.616568 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3398 11:35:54.619611 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3399 11:35:54.623120 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3400 11:35:54.626509 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3401 11:35:54.629751 1000 |3 6 40|[0] ooxxoooo xxxxxxxx [MSB]
3402 11:35:54.632919 1001 |3 6 41|[0] ooxxxoox xxxxxxxx [MSB]
3403 11:35:54.636439 1002 |3 6 42|[0] oxxxxoxx xxxxxxxx [MSB]
3404 11:35:54.639484 1003 |3 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
3405 11:35:54.642954 Byte0, DQ PI dly=989, DQM PI dly= 989
3406 11:35:54.646700 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
3407 11:35:54.646785
3408 11:35:54.653253 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
3409 11:35:54.653337
3410 11:35:54.656413 Byte1, DQ PI dly=977, DQM PI dly= 977
3411 11:35:54.659748 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3412 11:35:54.659832
3413 11:35:54.662971 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3414 11:35:54.666361
3415 11:35:54.666475 ==
3416 11:35:54.669531 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3417 11:35:54.673227 fsp= 1, odt_onoff= 1, Byte mode= 0
3418 11:35:54.673311 ==
3419 11:35:54.676626 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3420 11:35:54.676709
3421 11:35:54.680212 Begin, DQ Scan Range 953~1017
3422 11:35:54.683098 Write Rank1 MR14 =0x0
3423 11:35:54.691593
3424 11:35:54.691675 CH=1, VrefRange= 0, VrefLevel = 0
3425 11:35:54.698225 TX Bit0 (983~998) 16 990, Bit8 (970~984) 15 977,
3426 11:35:54.701828 TX Bit1 (983~997) 15 990, Bit9 (970~983) 14 976,
3427 11:35:54.708130 TX Bit2 (979~994) 16 986, Bit10 (973~985) 13 979,
3428 11:35:54.711325 TX Bit3 (979~991) 13 985, Bit11 (974~986) 13 980,
3429 11:35:54.714946 TX Bit4 (982~996) 15 989, Bit12 (975~985) 11 980,
3430 11:35:54.721260 TX Bit5 (983~998) 16 990, Bit13 (975~986) 12 980,
3431 11:35:54.724907 TX Bit6 (982~998) 17 990, Bit14 (974~984) 11 979,
3432 11:35:54.727880 TX Bit7 (983~995) 13 989, Bit15 (968~978) 11 973,
3433 11:35:54.727951
3434 11:35:54.731261 Write Rank1 MR14 =0x2
3435 11:35:54.740673
3436 11:35:54.740750 CH=1, VrefRange= 0, VrefLevel = 2
3437 11:35:54.747502 TX Bit0 (983~998) 16 990, Bit8 (970~984) 15 977,
3438 11:35:54.750708 TX Bit1 (981~998) 18 989, Bit9 (970~984) 15 977,
3439 11:35:54.757242 TX Bit2 (980~996) 17 988, Bit10 (972~985) 14 978,
3440 11:35:54.760637 TX Bit3 (978~992) 15 985, Bit11 (974~987) 14 980,
3441 11:35:54.764134 TX Bit4 (981~997) 17 989, Bit12 (974~985) 12 979,
3442 11:35:54.770674 TX Bit5 (983~998) 16 990, Bit13 (974~987) 14 980,
3443 11:35:54.773802 TX Bit6 (982~998) 17 990, Bit14 (973~985) 13 979,
3444 11:35:54.777178 TX Bit7 (984~997) 14 990, Bit15 (969~979) 11 974,
3445 11:35:54.777254
3446 11:35:54.780618 Write Rank1 MR14 =0x4
3447 11:35:54.789641
3448 11:35:54.789718 CH=1, VrefRange= 0, VrefLevel = 4
3449 11:35:54.796384 TX Bit0 (982~999) 18 990, Bit8 (969~984) 16 976,
3450 11:35:54.799578 TX Bit1 (982~998) 17 990, Bit9 (970~984) 15 977,
3451 11:35:54.806753 TX Bit2 (979~997) 19 988, Bit10 (972~986) 15 979,
3452 11:35:54.809899 TX Bit3 (978~992) 15 985, Bit11 (973~987) 15 980,
3453 11:35:54.812818 TX Bit4 (981~998) 18 989, Bit12 (973~986) 14 979,
3454 11:35:54.819814 TX Bit5 (982~999) 18 990, Bit13 (973~987) 15 980,
3455 11:35:54.823036 TX Bit6 (982~998) 17 990, Bit14 (973~985) 13 979,
3456 11:35:54.826502 TX Bit7 (983~997) 15 990, Bit15 (967~980) 14 973,
3457 11:35:54.829855
3458 11:35:54.829932 Write Rank1 MR14 =0x6
3459 11:35:54.839100
3460 11:35:54.839174 CH=1, VrefRange= 0, VrefLevel = 6
3461 11:35:54.845824 TX Bit0 (982~1000) 19 991, Bit8 (969~985) 17 977,
3462 11:35:54.849377 TX Bit1 (981~998) 18 989, Bit9 (969~984) 16 976,
3463 11:35:54.856055 TX Bit2 (979~997) 19 988, Bit10 (973~986) 14 979,
3464 11:35:54.859488 TX Bit3 (978~993) 16 985, Bit11 (973~988) 16 980,
3465 11:35:54.862514 TX Bit4 (980~998) 19 989, Bit12 (972~986) 15 979,
3466 11:35:54.868997 TX Bit5 (982~1000) 19 991, Bit13 (972~989) 18 980,
3467 11:35:54.872688 TX Bit6 (981~998) 18 989, Bit14 (971~986) 16 978,
3468 11:35:54.879096 TX Bit7 (983~998) 16 990, Bit15 (967~981) 15 974,
3469 11:35:54.879178
3470 11:35:54.879242 Write Rank1 MR14 =0x8
3471 11:35:54.888729
3472 11:35:54.888809 CH=1, VrefRange= 0, VrefLevel = 8
3473 11:35:54.895518 TX Bit0 (982~1000) 19 991, Bit8 (969~985) 17 977,
3474 11:35:54.898706 TX Bit1 (980~999) 20 989, Bit9 (969~985) 17 977,
3475 11:35:54.905631 TX Bit2 (979~998) 20 988, Bit10 (972~987) 16 979,
3476 11:35:54.908551 TX Bit3 (978~994) 17 986, Bit11 (972~989) 18 980,
3477 11:35:54.912218 TX Bit4 (980~999) 20 989, Bit12 (971~987) 17 979,
3478 11:35:54.918687 TX Bit5 (982~1000) 19 991, Bit13 (973~989) 17 981,
3479 11:35:54.921868 TX Bit6 (981~999) 19 990, Bit14 (971~987) 17 979,
3480 11:35:54.925390 TX Bit7 (982~998) 17 990, Bit15 (967~982) 16 974,
3481 11:35:54.928584
3482 11:35:54.928668 Write Rank1 MR14 =0xa
3483 11:35:54.938926
3484 11:35:54.941990 CH=1, VrefRange= 0, VrefLevel = 10
3485 11:35:54.945500 TX Bit0 (982~1001) 20 991, Bit8 (969~985) 17 977,
3486 11:35:54.949197 TX Bit1 (980~999) 20 989, Bit9 (969~985) 17 977,
3487 11:35:54.955336 TX Bit2 (978~998) 21 988, Bit10 (971~988) 18 979,
3488 11:35:54.958704 TX Bit3 (977~995) 19 986, Bit11 (971~988) 18 979,
3489 11:35:54.962540 TX Bit4 (980~999) 20 989, Bit12 (972~988) 17 980,
3490 11:35:54.968886 TX Bit5 (982~1001) 20 991, Bit13 (971~989) 19 980,
3491 11:35:54.972025 TX Bit6 (980~1000) 21 990, Bit14 (971~988) 18 979,
3492 11:35:54.975286 TX Bit7 (982~999) 18 990, Bit15 (966~983) 18 974,
3493 11:35:54.978809
3494 11:35:54.978893 Write Rank1 MR14 =0xc
3495 11:35:54.988676
3496 11:35:54.991812 CH=1, VrefRange= 0, VrefLevel = 12
3497 11:35:54.995557 TX Bit0 (981~1001) 21 991, Bit8 (969~986) 18 977,
3498 11:35:54.998572 TX Bit1 (979~1000) 22 989, Bit9 (969~986) 18 977,
3499 11:35:55.005415 TX Bit2 (978~998) 21 988, Bit10 (971~988) 18 979,
3500 11:35:55.008560 TX Bit3 (977~996) 20 986, Bit11 (971~990) 20 980,
3501 11:35:55.011932 TX Bit4 (979~1000) 22 989, Bit12 (971~989) 19 980,
3502 11:35:55.018566 TX Bit5 (981~1001) 21 991, Bit13 (971~991) 21 981,
3503 11:35:55.022010 TX Bit6 (980~1000) 21 990, Bit14 (971~988) 18 979,
3504 11:35:55.028827 TX Bit7 (982~999) 18 990, Bit15 (966~984) 19 975,
3505 11:35:55.028911
3506 11:35:55.028984 Write Rank1 MR14 =0xe
3507 11:35:55.038836
3508 11:35:55.042557 CH=1, VrefRange= 0, VrefLevel = 14
3509 11:35:55.045538 TX Bit0 (981~1002) 22 991, Bit8 (969~986) 18 977,
3510 11:35:55.048495 TX Bit1 (979~1000) 22 989, Bit9 (969~986) 18 977,
3511 11:35:55.055394 TX Bit2 (978~999) 22 988, Bit10 (970~989) 20 979,
3512 11:35:55.058749 TX Bit3 (977~997) 21 987, Bit11 (971~990) 20 980,
3513 11:35:55.061606 TX Bit4 (979~1000) 22 989, Bit12 (971~990) 20 980,
3514 11:35:55.068598 TX Bit5 (981~1002) 22 991, Bit13 (971~991) 21 981,
3515 11:35:55.072116 TX Bit6 (980~1000) 21 990, Bit14 (971~989) 19 980,
3516 11:35:55.078508 TX Bit7 (981~999) 19 990, Bit15 (966~984) 19 975,
3517 11:35:55.078588
3518 11:35:55.081690 wait MRW command Rank1 MR14 =0x10 fired (1)
3519 11:35:55.081760 Write Rank1 MR14 =0x10
3520 11:35:55.092992
3521 11:35:55.096471 CH=1, VrefRange= 0, VrefLevel = 16
3522 11:35:55.099687 TX Bit0 (981~1002) 22 991, Bit8 (968~987) 20 977,
3523 11:35:55.102831 TX Bit1 (979~1001) 23 990, Bit9 (968~987) 20 977,
3524 11:35:55.109939 TX Bit2 (978~999) 22 988, Bit10 (970~990) 21 980,
3525 11:35:55.113032 TX Bit3 (977~997) 21 987, Bit11 (971~991) 21 981,
3526 11:35:55.116441 TX Bit4 (979~1000) 22 989, Bit12 (970~990) 21 980,
3527 11:35:55.122914 TX Bit5 (980~1002) 23 991, Bit13 (971~991) 21 981,
3528 11:35:55.126402 TX Bit6 (979~1001) 23 990, Bit14 (970~990) 21 980,
3529 11:35:55.133099 TX Bit7 (981~1000) 20 990, Bit15 (965~984) 20 974,
3530 11:35:55.133177
3531 11:35:55.133240 Write Rank1 MR14 =0x12
3532 11:35:55.144237
3533 11:35:55.146674 CH=1, VrefRange= 0, VrefLevel = 18
3534 11:35:55.150560 TX Bit0 (981~1002) 22 991, Bit8 (968~987) 20 977,
3535 11:35:55.153626 TX Bit1 (979~1001) 23 990, Bit9 (968~987) 20 977,
3536 11:35:55.160401 TX Bit2 (978~999) 22 988, Bit10 (970~990) 21 980,
3537 11:35:55.163727 TX Bit3 (977~997) 21 987, Bit11 (971~991) 21 981,
3538 11:35:55.166955 TX Bit4 (979~1000) 22 989, Bit12 (970~990) 21 980,
3539 11:35:55.173741 TX Bit5 (980~1002) 23 991, Bit13 (971~991) 21 981,
3540 11:35:55.176980 TX Bit6 (979~1001) 23 990, Bit14 (970~990) 21 980,
3541 11:35:55.183775 TX Bit7 (981~1000) 20 990, Bit15 (965~984) 20 974,
3542 11:35:55.183852
3543 11:35:55.183915 Write Rank1 MR14 =0x14
3544 11:35:55.194584
3545 11:35:55.197720 CH=1, VrefRange= 0, VrefLevel = 20
3546 11:35:55.201500 TX Bit0 (980~1004) 25 992, Bit8 (968~989) 22 978,
3547 11:35:55.204606 TX Bit1 (978~1002) 25 990, Bit9 (968~988) 21 978,
3548 11:35:55.210987 TX Bit2 (978~1000) 23 989, Bit10 (970~991) 22 980,
3549 11:35:55.214386 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3550 11:35:55.217978 TX Bit4 (978~1002) 25 990, Bit12 (970~991) 22 980,
3551 11:35:55.224400 TX Bit5 (980~1003) 24 991, Bit13 (970~992) 23 981,
3552 11:35:55.228030 TX Bit6 (979~1002) 24 990, Bit14 (970~991) 22 980,
3553 11:35:55.234227 TX Bit7 (980~1001) 22 990, Bit15 (965~985) 21 975,
3554 11:35:55.234307
3555 11:35:55.234371 Write Rank1 MR14 =0x16
3556 11:35:55.245030
3557 11:35:55.248541 CH=1, VrefRange= 0, VrefLevel = 22
3558 11:35:55.252221 TX Bit0 (979~1004) 26 991, Bit8 (968~988) 21 978,
3559 11:35:55.255020 TX Bit1 (978~1002) 25 990, Bit9 (968~989) 22 978,
3560 11:35:55.261570 TX Bit2 (977~1000) 24 988, Bit10 (969~991) 23 980,
3561 11:35:55.264817 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3562 11:35:55.268357 TX Bit4 (978~1002) 25 990, Bit12 (970~991) 22 980,
3563 11:35:55.274846 TX Bit5 (979~1004) 26 991, Bit13 (970~992) 23 981,
3564 11:35:55.278422 TX Bit6 (979~1003) 25 991, Bit14 (969~991) 23 980,
3565 11:35:55.285062 TX Bit7 (980~1001) 22 990, Bit15 (965~985) 21 975,
3566 11:35:55.285144
3567 11:35:55.285209 Write Rank1 MR14 =0x18
3568 11:35:55.296057
3569 11:35:55.299869 CH=1, VrefRange= 0, VrefLevel = 24
3570 11:35:55.302803 TX Bit0 (979~1005) 27 992, Bit8 (968~990) 23 979,
3571 11:35:55.306477 TX Bit1 (978~1003) 26 990, Bit9 (967~989) 23 978,
3572 11:35:55.313134 TX Bit2 (978~1001) 24 989, Bit10 (969~991) 23 980,
3573 11:35:55.316218 TX Bit3 (976~999) 24 987, Bit11 (970~992) 23 981,
3574 11:35:55.319726 TX Bit4 (978~1003) 26 990, Bit12 (970~992) 23 981,
3575 11:35:55.326132 TX Bit5 (979~1005) 27 992, Bit13 (970~992) 23 981,
3576 11:35:55.329417 TX Bit6 (978~1003) 26 990, Bit14 (970~991) 22 980,
3577 11:35:55.336030 TX Bit7 (979~1002) 24 990, Bit15 (964~986) 23 975,
3578 11:35:55.336101
3579 11:35:55.336168 Write Rank1 MR14 =0x1a
3580 11:35:55.347573
3581 11:35:55.351008 CH=1, VrefRange= 0, VrefLevel = 26
3582 11:35:55.353703 TX Bit0 (979~1005) 27 992, Bit8 (967~990) 24 978,
3583 11:35:55.357432 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
3584 11:35:55.364049 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3585 11:35:55.367188 TX Bit3 (976~999) 24 987, Bit11 (969~992) 24 980,
3586 11:35:55.370192 TX Bit4 (978~1003) 26 990, Bit12 (970~992) 23 981,
3587 11:35:55.376966 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3588 11:35:55.380409 TX Bit6 (978~1003) 26 990, Bit14 (969~992) 24 980,
3589 11:35:55.386920 TX Bit7 (979~1002) 24 990, Bit15 (964~987) 24 975,
3590 11:35:55.387010
3591 11:35:55.387076 Write Rank1 MR14 =0x1c
3592 11:35:55.398545
3593 11:35:55.401455 CH=1, VrefRange= 0, VrefLevel = 28
3594 11:35:55.404968 TX Bit0 (979~1006) 28 992, Bit8 (966~990) 25 978,
3595 11:35:55.408493 TX Bit1 (978~1004) 27 991, Bit9 (967~989) 23 978,
3596 11:35:55.415284 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3597 11:35:55.418112 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3598 11:35:55.421387 TX Bit4 (978~1004) 27 991, Bit12 (969~992) 24 980,
3599 11:35:55.427944 TX Bit5 (978~1005) 28 991, Bit13 (970~993) 24 981,
3600 11:35:55.431625 TX Bit6 (978~1004) 27 991, Bit14 (969~992) 24 980,
3601 11:35:55.438020 TX Bit7 (979~1003) 25 991, Bit15 (964~987) 24 975,
3602 11:35:55.438098
3603 11:35:55.438169 Write Rank1 MR14 =0x1e
3604 11:35:55.449450
3605 11:35:55.449529 CH=1, VrefRange= 0, VrefLevel = 30
3606 11:35:55.456292 TX Bit0 (979~1006) 28 992, Bit8 (967~989) 23 978,
3607 11:35:55.459635 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3608 11:35:55.466419 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
3609 11:35:55.469634 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3610 11:35:55.472807 TX Bit4 (978~1004) 27 991, Bit12 (969~992) 24 980,
3611 11:35:55.479554 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3612 11:35:55.483132 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
3613 11:35:55.489374 TX Bit7 (979~1004) 26 991, Bit15 (962~987) 26 974,
3614 11:35:55.489457
3615 11:35:55.489523 Write Rank1 MR14 =0x20
3616 11:35:55.500403
3617 11:35:55.504199 CH=1, VrefRange= 0, VrefLevel = 32
3618 11:35:55.507112 TX Bit0 (979~1006) 28 992, Bit8 (967~989) 23 978,
3619 11:35:55.510256 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3620 11:35:55.517027 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
3621 11:35:55.519965 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3622 11:35:55.523431 TX Bit4 (978~1004) 27 991, Bit12 (969~992) 24 980,
3623 11:35:55.530067 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3624 11:35:55.533549 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
3625 11:35:55.539816 TX Bit7 (979~1004) 26 991, Bit15 (962~987) 26 974,
3626 11:35:55.539905
3627 11:35:55.539992 Write Rank1 MR14 =0x22
3628 11:35:55.551868
3629 11:35:55.555036 CH=1, VrefRange= 0, VrefLevel = 34
3630 11:35:55.558158 TX Bit0 (979~1006) 28 992, Bit8 (967~989) 23 978,
3631 11:35:55.561655 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3632 11:35:55.568336 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
3633 11:35:55.571911 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3634 11:35:55.575058 TX Bit4 (978~1004) 27 991, Bit12 (969~992) 24 980,
3635 11:35:55.581566 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3636 11:35:55.584748 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
3637 11:35:55.591710 TX Bit7 (979~1004) 26 991, Bit15 (962~987) 26 974,
3638 11:35:55.591795
3639 11:35:55.591860 Write Rank1 MR14 =0x24
3640 11:35:55.602777
3641 11:35:55.605868 CH=1, VrefRange= 0, VrefLevel = 36
3642 11:35:55.609184 TX Bit0 (979~1006) 28 992, Bit8 (967~989) 23 978,
3643 11:35:55.612444 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3644 11:35:55.619489 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
3645 11:35:55.622566 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3646 11:35:55.625926 TX Bit4 (978~1004) 27 991, Bit12 (969~992) 24 980,
3647 11:35:55.632267 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3648 11:35:55.635414 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
3649 11:35:55.642410 TX Bit7 (979~1004) 26 991, Bit15 (962~987) 26 974,
3650 11:35:55.642494
3651 11:35:55.642560 Write Rank1 MR14 =0x26
3652 11:35:55.653552
3653 11:35:55.653635 CH=1, VrefRange= 0, VrefLevel = 38
3654 11:35:55.660380 TX Bit0 (979~1006) 28 992, Bit8 (967~989) 23 978,
3655 11:35:55.663527 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3656 11:35:55.670502 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
3657 11:35:55.673531 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3658 11:35:55.676973 TX Bit4 (978~1004) 27 991, Bit12 (969~992) 24 980,
3659 11:35:55.683661 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3660 11:35:55.686775 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
3661 11:35:55.693514 TX Bit7 (979~1004) 26 991, Bit15 (962~987) 26 974,
3662 11:35:55.693598
3663 11:35:55.693663
3664 11:35:55.697106 TX Vref found, early break! 381< 387
3665 11:35:55.700416 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3666 11:35:55.703514 u1DelayCellOfst[0]=6 cells (5 PI)
3667 11:35:55.706582 u1DelayCellOfst[1]=5 cells (4 PI)
3668 11:35:55.709699 u1DelayCellOfst[2]=2 cells (2 PI)
3669 11:35:55.713030 u1DelayCellOfst[3]=0 cells (0 PI)
3670 11:35:55.716531 u1DelayCellOfst[4]=5 cells (4 PI)
3671 11:35:55.719673 u1DelayCellOfst[5]=6 cells (5 PI)
3672 11:35:55.722997 u1DelayCellOfst[6]=5 cells (4 PI)
3673 11:35:55.723079 u1DelayCellOfst[7]=5 cells (4 PI)
3674 11:35:55.726851 Byte0, DQ PI dly=987, DQM PI dly= 989
3675 11:35:55.732902 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
3676 11:35:55.732985
3677 11:35:55.736238 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
3678 11:35:55.736321
3679 11:35:55.739652 u1DelayCellOfst[8]=5 cells (4 PI)
3680 11:35:55.742898 u1DelayCellOfst[9]=5 cells (4 PI)
3681 11:35:55.746478 u1DelayCellOfst[10]=7 cells (6 PI)
3682 11:35:55.749653 u1DelayCellOfst[11]=9 cells (7 PI)
3683 11:35:55.753072 u1DelayCellOfst[12]=7 cells (6 PI)
3684 11:35:55.756531 u1DelayCellOfst[13]=9 cells (7 PI)
3685 11:35:55.759656 u1DelayCellOfst[14]=7 cells (6 PI)
3686 11:35:55.763171 u1DelayCellOfst[15]=0 cells (0 PI)
3687 11:35:55.766403 Byte1, DQ PI dly=974, DQM PI dly= 977
3688 11:35:55.769745 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
3689 11:35:55.769828
3690 11:35:55.772725 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
3691 11:35:55.772808
3692 11:35:55.776404 Write Rank1 MR14 =0x1e
3693 11:35:55.776494
3694 11:35:55.779603 Final TX Range 0 Vref 30
3695 11:35:55.779686
3696 11:35:55.786436 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3697 11:35:55.786524
3698 11:35:55.792747 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3699 11:35:55.799510 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3700 11:35:55.806256 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3701 11:35:55.809533 Write Rank1 MR3 =0xb0
3702 11:35:55.809625 DramC Write-DBI on
3703 11:35:55.809689 ==
3704 11:35:55.816278 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3705 11:35:55.819193 fsp= 1, odt_onoff= 1, Byte mode= 0
3706 11:35:55.819277 ==
3707 11:35:55.822567 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3708 11:35:55.822650
3709 11:35:55.826062 Begin, DQ Scan Range 697~761
3710 11:35:55.826145
3711 11:35:55.826209
3712 11:35:55.826269 TX Vref Scan disable
3713 11:35:55.832710 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3714 11:35:55.835909 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3715 11:35:55.839473 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3716 11:35:55.842410 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3717 11:35:55.846115 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3718 11:35:55.849273 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3719 11:35:55.853785 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3720 11:35:55.856029 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3721 11:35:55.859098 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3722 11:35:55.862739 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3723 11:35:55.866581 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3724 11:35:55.869290 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3725 11:35:55.872752 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3726 11:35:55.875967 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3727 11:35:55.879523 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3728 11:35:55.882589 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3729 11:35:55.885860 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3730 11:35:55.889503 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3731 11:35:55.892778 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3732 11:35:55.896008 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3733 11:35:55.902357 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3734 11:35:55.905837 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3735 11:35:55.909333 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3736 11:35:55.912593 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3737 11:35:55.915922 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3738 11:35:55.922584 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3739 11:35:55.925605 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3740 11:35:55.928721 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3741 11:35:55.932226 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3742 11:35:55.935384 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3743 11:35:55.938791 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3744 11:35:55.941980 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3745 11:35:55.945683 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3746 11:35:55.948815 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3747 11:35:55.952571 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3748 11:35:55.955405 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3749 11:35:55.959057 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3750 11:35:55.962470 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3751 11:35:55.965542 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3752 11:35:55.968787 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3753 11:35:55.975807 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3754 11:35:55.975909 Byte0, DQ PI dly=736, DQM PI dly= 736
3755 11:35:55.982415 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
3756 11:35:55.982499
3757 11:35:55.985524 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
3758 11:35:55.985609
3759 11:35:55.988613 Byte1, DQ PI dly=723, DQM PI dly= 723
3760 11:35:55.995280 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3761 11:35:55.995364
3762 11:35:55.998705 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3763 11:35:55.998790
3764 11:35:56.005592 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3765 11:35:56.011891 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3766 11:35:56.018475 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3767 11:35:56.022081 Write Rank1 MR3 =0x30
3768 11:35:56.022158 DramC Write-DBI off
3769 11:35:56.022224
3770 11:35:56.025626 [DATLAT]
3771 11:35:56.025701 Freq=1600, CH1 RK1, use_rxtx_scan=0
3772 11:35:56.028673
3773 11:35:56.028749 DATLAT Default: 0x10
3774 11:35:56.031667 7, 0xFFFF, sum=0
3775 11:35:56.031771 8, 0xFFFF, sum=0
3776 11:35:56.035215 9, 0xFFFF, sum=0
3777 11:35:56.035300 10, 0xFFFF, sum=0
3778 11:35:56.038552 11, 0xFFFF, sum=0
3779 11:35:56.038637 12, 0xFFFF, sum=0
3780 11:35:56.041604 13, 0xFFFF, sum=0
3781 11:35:56.041689 14, 0x0, sum=1
3782 11:35:56.041755 15, 0x0, sum=2
3783 11:35:56.045012 16, 0x0, sum=3
3784 11:35:56.045097 17, 0x0, sum=4
3785 11:35:56.051786 pattern=2 first_step=14 total pass=5 best_step=16
3786 11:35:56.051870 ==
3787 11:35:56.055280 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3788 11:35:56.058340 fsp= 1, odt_onoff= 1, Byte mode= 0
3789 11:35:56.058425 ==
3790 11:35:56.062020 Start DQ dly to find pass range UseTestEngine =1
3791 11:35:56.065071 x-axis: bit #, y-axis: DQ dly (-127~63)
3792 11:35:56.068274 RX Vref Scan = 0
3793 11:35:56.071879 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3794 11:35:56.075285 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3795 11:35:56.078458 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3796 11:35:56.078544 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3797 11:35:56.081666 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3798 11:35:56.085094 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3799 11:35:56.088205 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3800 11:35:56.091826 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3801 11:35:56.095161 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3802 11:35:56.098264 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3803 11:35:56.101709 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3804 11:35:56.104915 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3805 11:35:56.105001 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3806 11:35:56.108434 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3807 11:35:56.111910 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3808 11:35:56.114781 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3809 11:35:56.118184 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3810 11:35:56.121435 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3811 11:35:56.124926 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3812 11:35:56.128156 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3813 11:35:56.128268 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3814 11:35:56.131182 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3815 11:35:56.134845 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3816 11:35:56.138067 -3, [0] xxxoxxxx xxxxxxxo [MSB]
3817 11:35:56.141506 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3818 11:35:56.144811 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3819 11:35:56.144897 0, [0] xxxoxxxx ooxxxxxo [MSB]
3820 11:35:56.148068 1, [0] xxooxxxx ooxxxxxo [MSB]
3821 11:35:56.151633 2, [0] xxooxxxx ooxxxxxo [MSB]
3822 11:35:56.154829 3, [0] oxooxxxo oooxxxxo [MSB]
3823 11:35:56.158186 4, [0] oxoooxxo ooooooxo [MSB]
3824 11:35:56.161191 5, [0] ooooooxo oooooooo [MSB]
3825 11:35:56.164768 32, [0] oooooooo ooooooox [MSB]
3826 11:35:56.167979 33, [0] oooooooo ooooooox [MSB]
3827 11:35:56.171175 34, [0] oooooooo ooooooox [MSB]
3828 11:35:56.174879 35, [0] oooxoooo oxooooox [MSB]
3829 11:35:56.177851 36, [0] oooxoooo xxooooox [MSB]
3830 11:35:56.177935 37, [0] ooxxoooo xxooooox [MSB]
3831 11:35:56.181558 38, [0] ooxxoooo xxooooox [MSB]
3832 11:35:56.184701 39, [0] ooxxooox xxooooox [MSB]
3833 11:35:56.188090 40, [0] oxxxxoox xxxoooox [MSB]
3834 11:35:56.191623 41, [0] xxxxxxox xxxxxxxx [MSB]
3835 11:35:56.194813 42, [0] xxxxxxxx xxxxxxxx [MSB]
3836 11:35:56.198029 iDelay=42, Bit 0, Center 21 (3 ~ 40) 38
3837 11:35:56.201395 iDelay=42, Bit 1, Center 22 (5 ~ 39) 35
3838 11:35:56.204673 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
3839 11:35:56.207931 iDelay=42, Bit 3, Center 15 (-3 ~ 34) 38
3840 11:35:56.211081 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3841 11:35:56.214837 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3842 11:35:56.218051 iDelay=42, Bit 6, Center 23 (6 ~ 41) 36
3843 11:35:56.221423 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3844 11:35:56.224450 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
3845 11:35:56.228124 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3846 11:35:56.231143 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3847 11:35:56.234738 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3848 11:35:56.241634 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3849 11:35:56.244711 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
3850 11:35:56.247949 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3851 11:35:56.250978 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3852 11:35:56.251062 ==
3853 11:35:56.254416 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3854 11:35:56.258054 fsp= 1, odt_onoff= 1, Byte mode= 0
3855 11:35:56.261447 ==
3856 11:35:56.261529 DQS Delay:
3857 11:35:56.261594 DQS0 = 0, DQS1 = 0
3858 11:35:56.264573 DQM Delay:
3859 11:35:56.264657 DQM0 = 20, DQM1 = 19
3860 11:35:56.267550 DQ Delay:
3861 11:35:56.267633 DQ0 =21, DQ1 =22, DQ2 =18, DQ3 =15
3862 11:35:56.271073 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3863 11:35:56.274268 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3864 11:35:56.277885 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =14
3865 11:35:56.277968
3866 11:35:56.281029
3867 11:35:56.281112
3868 11:35:56.281176 [DramC_TX_OE_Calibration] TA2
3869 11:35:56.284573 Original DQ_B0 (3 6) =30, OEN = 27
3870 11:35:56.287635 Original DQ_B1 (3 6) =30, OEN = 27
3871 11:35:56.291103 23, 0x0, End_B0=23 End_B1=23
3872 11:35:56.294535 24, 0x0, End_B0=24 End_B1=24
3873 11:35:56.297507 25, 0x0, End_B0=25 End_B1=25
3874 11:35:56.297592 26, 0x0, End_B0=26 End_B1=26
3875 11:35:56.300776 27, 0x0, End_B0=27 End_B1=27
3876 11:35:56.304466 28, 0x0, End_B0=28 End_B1=28
3877 11:35:56.307505 29, 0x0, End_B0=29 End_B1=29
3878 11:35:56.307589 30, 0x0, End_B0=30 End_B1=30
3879 11:35:56.310760 31, 0xFFFF, End_B0=30 End_B1=30
3880 11:35:56.317443 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3881 11:35:56.324133 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3882 11:35:56.324218
3883 11:35:56.324283
3884 11:35:56.324342 Write Rank1 MR23 =0x3f
3885 11:35:56.327609 [DQSOSC]
3886 11:35:56.334367 [DQSOSCAuto] RK1, (LSB)MR18= 0xcfcf, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
3887 11:35:56.340982 CH1_RK1: MR19=0x202, MR18=0xCFCF, DQSOSC=438, MR23=63, INC=12, DEC=19
3888 11:35:56.344333 Write Rank1 MR23 =0x3f
3889 11:35:56.344416 [DQSOSC]
3890 11:35:56.351482 [DQSOSCAuto] RK1, (LSB)MR18= 0xcece, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
3891 11:35:56.354087 CH1 RK1: MR19=202, MR18=CECE
3892 11:35:56.357243 [RxdqsGatingPostProcess] freq 1600
3893 11:35:56.363923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3894 11:35:56.364012 Rank: 0
3895 11:35:56.367941 best DQS0 dly(2T, 0.5T) = (2, 6)
3896 11:35:56.370796 best DQS1 dly(2T, 0.5T) = (2, 6)
3897 11:35:56.374017 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3898 11:35:56.377145 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3899 11:35:56.377229 Rank: 1
3900 11:35:56.380784 best DQS0 dly(2T, 0.5T) = (2, 5)
3901 11:35:56.384086 best DQS1 dly(2T, 0.5T) = (2, 6)
3902 11:35:56.384181 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3903 11:35:56.387205 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3904 11:35:56.393641 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3905 11:35:56.397277 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3906 11:35:56.400774 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3907 11:35:56.400859
3908 11:35:56.400923
3909 11:35:56.403789 [Calibration Summary] Freqency 1600
3910 11:35:56.407295 CH 0, Rank 0
3911 11:35:56.407399 All Pass.
3912 11:35:56.407466
3913 11:35:56.407525 CH 0, Rank 1
3914 11:35:56.410445 All Pass.
3915 11:35:56.410519
3916 11:35:56.410581 CH 1, Rank 0
3917 11:35:56.410639 All Pass.
3918 11:35:56.413639
3919 11:35:56.413759 CH 1, Rank 1
3920 11:35:56.413872 All Pass.
3921 11:35:56.413942
3922 11:35:56.420849 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3923 11:35:56.427093 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3924 11:35:56.433409 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3925 11:35:56.436693 Write Rank0 MR3 =0xb0
3926 11:35:56.443393 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3927 11:35:56.450272 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3928 11:35:56.456940 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3929 11:35:56.460052 Write Rank1 MR3 =0xb0
3930 11:35:56.467117 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3931 11:35:56.473840 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3932 11:35:56.480012 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3933 11:35:56.483721 Write Rank0 MR3 =0xb0
3934 11:35:56.486786 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3935 11:35:56.496796 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3936 11:35:56.503557 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3937 11:35:56.503641 Write Rank1 MR3 =0xb0
3938 11:35:56.506561 DramC Write-DBI on
3939 11:35:56.509876 [GetDramInforAfterCalByMRR] Vendor 6.
3940 11:35:56.513422 [GetDramInforAfterCalByMRR] Revision 505.
3941 11:35:56.513506 MR8 1111
3942 11:35:56.519889 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3943 11:35:56.519975 MR8 1111
3944 11:35:56.523228 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3945 11:35:56.526877 MR8 1111
3946 11:35:56.530001 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3947 11:35:56.530085 MR8 1111
3948 11:35:56.536375 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3949 11:35:56.546489 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3950 11:35:56.546602 Write Rank0 MR13 =0xd0
3951 11:35:56.549817 Write Rank1 MR13 =0xd0
3952 11:35:56.549901 Write Rank0 MR13 =0xd0
3953 11:35:56.553750 Write Rank1 MR13 =0xd0
3954 11:35:56.556440 Save calibration result to emmc
3955 11:35:56.556536
3956 11:35:56.556601
3957 11:35:56.559548 [DramcModeReg_Check] Freq_1600, FSP_1
3958 11:35:56.563056 FSP_1, CH_0, RK0
3959 11:35:56.563140 Write Rank0 MR13 =0xd8
3960 11:35:56.566602 MR12 = 0x5e (global = 0x5e) match
3961 11:35:56.569884 MR14 = 0x1c (global = 0x1c) match
3962 11:35:56.573087 FSP_1, CH_0, RK1
3963 11:35:56.573173 Write Rank1 MR13 =0xd8
3964 11:35:56.576653 MR12 = 0x5c (global = 0x5c) match
3965 11:35:56.579847 MR14 = 0x1e (global = 0x1e) match
3966 11:35:56.583170 FSP_1, CH_1, RK0
3967 11:35:56.583254 Write Rank0 MR13 =0xd8
3968 11:35:56.586493 MR12 = 0x60 (global = 0x60) match
3969 11:35:56.590003 MR14 = 0x1e (global = 0x1e) match
3970 11:35:56.590089 FSP_1, CH_1, RK1
3971 11:35:56.593233 Write Rank1 MR13 =0xd8
3972 11:35:56.596446 MR12 = 0x5e (global = 0x5e) match
3973 11:35:56.599555 MR14 = 0x1e (global = 0x1e) match
3974 11:35:56.599639
3975 11:35:56.603123 [MEM_TEST] 02: After DFS, before run time config
3976 11:35:56.615098 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3977 11:35:56.615183
3978 11:35:56.615248 [TA2_TEST]
3979 11:35:56.615308 === TA2 HW
3980 11:35:56.618768 TA2 PAT: XTALK
3981 11:35:56.621941 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3982 11:35:56.628626 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3983 11:35:56.631687 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3984 11:35:56.634881 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3985 11:35:56.638485
3986 11:35:56.638568
3987 11:35:56.638634 Settings after calibration
3988 11:35:56.638694
3989 11:35:56.641627 [DramcRunTimeConfig]
3990 11:35:56.644769 TransferPLLToSPMControl - MODE SW PHYPLL
3991 11:35:56.644853 TX_TRACKING: ON
3992 11:35:56.648401 RX_TRACKING: ON
3993 11:35:56.648493 HW_GATING: ON
3994 11:35:56.651449 HW_GATING DBG: OFF
3995 11:35:56.651533 ddr_geometry:1
3996 11:35:56.654784 ddr_geometry:1
3997 11:35:56.654868 ddr_geometry:1
3998 11:35:56.654933 ddr_geometry:1
3999 11:35:56.658380 ddr_geometry:1
4000 11:35:56.658464 ddr_geometry:1
4001 11:35:56.661633 ddr_geometry:1
4002 11:35:56.661716 ddr_geometry:1
4003 11:35:56.664754 High Freq DUMMY_READ_FOR_TRACKING: ON
4004 11:35:56.668105 ZQCS_ENABLE_LP4: OFF
4005 11:35:56.671415 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4006 11:35:56.675095 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4007 11:35:56.675179 SPM_CONTROL_AFTERK: ON
4008 11:35:56.678323 IMPEDANCE_TRACKING: ON
4009 11:35:56.678407 TEMP_SENSOR: ON
4010 11:35:56.681247 PER_BANK_REFRESH: ON
4011 11:35:56.681330 HW_SAVE_FOR_SR: ON
4012 11:35:56.684651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4013 11:35:56.688004 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4014 11:35:56.691753 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4015 11:35:56.694460 Read ODT Tracking: ON
4016 11:35:56.697985 =========================
4017 11:35:56.698068
4018 11:35:56.698133 [TA2_TEST]
4019 11:35:56.698193 === TA2 HW
4020 11:35:56.704994 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4021 11:35:56.708135 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4022 11:35:56.714434 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4023 11:35:56.718057 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4024 11:35:56.718141
4025 11:35:56.721312 [MEM_TEST] 03: After run time config
4026 11:35:56.733061 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4027 11:35:56.736208 [complex_mem_test] start addr:0x40024000, len:131072
4028 11:35:56.940447 1st complex R/W mem test pass
4029 11:35:56.946907 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4030 11:35:56.950758 sync preloader write leveling
4031 11:35:56.953782 sync preloader cbt_mr12
4032 11:35:56.953866 sync preloader cbt_clk_dly
4033 11:35:56.957227 sync preloader cbt_cmd_dly
4034 11:35:56.960837 sync preloader cbt_cs
4035 11:35:56.963990 sync preloader cbt_ca_perbit_delay
4036 11:35:56.964074 sync preloader clk_delay
4037 11:35:56.967698 sync preloader dqs_delay
4038 11:35:56.970846 sync preloader u1Gating2T_Save
4039 11:35:56.974089 sync preloader u1Gating05T_Save
4040 11:35:56.977039 sync preloader u1Gatingfine_tune_Save
4041 11:35:56.980711 sync preloader u1Gatingucpass_count_Save
4042 11:35:56.984095 sync preloader u1TxWindowPerbitVref_Save
4043 11:35:56.987272 sync preloader u1TxCenter_min_Save
4044 11:35:56.990183 sync preloader u1TxCenter_max_Save
4045 11:35:56.993941 sync preloader u1Txwin_center_Save
4046 11:35:56.996896 sync preloader u1Txfirst_pass_Save
4047 11:35:57.000475 sync preloader u1Txlast_pass_Save
4048 11:35:57.000560 sync preloader u1RxDatlat_Save
4049 11:35:57.003631 sync preloader u1RxWinPerbitVref_Save
4050 11:35:57.010181 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4051 11:35:57.013385 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4052 11:35:57.016876 sync preloader delay_cell_unit
4053 11:35:57.023725 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4054 11:35:57.026780 sync preloader write leveling
4055 11:35:57.026864 sync preloader cbt_mr12
4056 11:35:57.030415 sync preloader cbt_clk_dly
4057 11:35:57.033556 sync preloader cbt_cmd_dly
4058 11:35:57.033640 sync preloader cbt_cs
4059 11:35:57.036556 sync preloader cbt_ca_perbit_delay
4060 11:35:57.040167 sync preloader clk_delay
4061 11:35:57.043438 sync preloader dqs_delay
4062 11:35:57.043523 sync preloader u1Gating2T_Save
4063 11:35:57.046811 sync preloader u1Gating05T_Save
4064 11:35:57.050109 sync preloader u1Gatingfine_tune_Save
4065 11:35:57.053760 sync preloader u1Gatingucpass_count_Save
4066 11:35:57.059902 sync preloader u1TxWindowPerbitVref_Save
4067 11:35:57.059986 sync preloader u1TxCenter_min_Save
4068 11:35:57.063330 sync preloader u1TxCenter_max_Save
4069 11:35:57.066652 sync preloader u1Txwin_center_Save
4070 11:35:57.069948 sync preloader u1Txfirst_pass_Save
4071 11:35:57.073456 sync preloader u1Txlast_pass_Save
4072 11:35:57.076854 sync preloader u1RxDatlat_Save
4073 11:35:57.080136 sync preloader u1RxWinPerbitVref_Save
4074 11:35:57.083187 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4075 11:35:57.089908 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4076 11:35:57.089993 sync preloader delay_cell_unit
4077 11:35:57.096523 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4078 11:35:57.100062 sync preloader write leveling
4079 11:35:57.103190 sync preloader cbt_mr12
4080 11:35:57.106762 sync preloader cbt_clk_dly
4081 11:35:57.106858 sync preloader cbt_cmd_dly
4082 11:35:57.109701 sync preloader cbt_cs
4083 11:35:57.113353 sync preloader cbt_ca_perbit_delay
4084 11:35:57.113437 sync preloader clk_delay
4085 11:35:57.116802 sync preloader dqs_delay
4086 11:35:57.119660 sync preloader u1Gating2T_Save
4087 11:35:57.123305 sync preloader u1Gating05T_Save
4088 11:35:57.126417 sync preloader u1Gatingfine_tune_Save
4089 11:35:57.130169 sync preloader u1Gatingucpass_count_Save
4090 11:35:57.133648 sync preloader u1TxWindowPerbitVref_Save
4091 11:35:57.136611 sync preloader u1TxCenter_min_Save
4092 11:35:57.139934 sync preloader u1TxCenter_max_Save
4093 11:35:57.143077 sync preloader u1Txwin_center_Save
4094 11:35:57.146296 sync preloader u1Txfirst_pass_Save
4095 11:35:57.149810 sync preloader u1Txlast_pass_Save
4096 11:35:57.149894 sync preloader u1RxDatlat_Save
4097 11:35:57.153063 sync preloader u1RxWinPerbitVref_Save
4098 11:35:57.159766 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4099 11:35:57.163260 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4100 11:35:57.166775 sync preloader delay_cell_unit
4101 11:35:57.169533 just_for_test_dump_coreboot_params dump all params
4102 11:35:57.173053 dump source = 0x0
4103 11:35:57.173136 dump params frequency:1600
4104 11:35:57.176237 dump params rank number:2
4105 11:35:57.176320
4106 11:35:57.179974 dump params write leveling
4107 11:35:57.183102 write leveling[0][0][0] = 0x20
4108 11:35:57.186584 write leveling[0][0][1] = 0x18
4109 11:35:57.186667 write leveling[0][1][0] = 0x1b
4110 11:35:57.190074 write leveling[0][1][1] = 0x18
4111 11:35:57.193051 write leveling[1][0][0] = 0x22
4112 11:35:57.196213 write leveling[1][0][1] = 0x19
4113 11:35:57.199545 write leveling[1][1][0] = 0x23
4114 11:35:57.202835 write leveling[1][1][1] = 0x18
4115 11:35:57.202919 dump params cbt_cs
4116 11:35:57.206289 cbt_cs[0][0] = 0x8
4117 11:35:57.206372 cbt_cs[0][1] = 0x8
4118 11:35:57.209851 cbt_cs[1][0] = 0xb
4119 11:35:57.209934 cbt_cs[1][1] = 0xb
4120 11:35:57.212834 dump params cbt_mr12
4121 11:35:57.212917 cbt_mr12[0][0] = 0x1e
4122 11:35:57.216164 cbt_mr12[0][1] = 0x1c
4123 11:35:57.216247 cbt_mr12[1][0] = 0x20
4124 11:35:57.219861 cbt_mr12[1][1] = 0x1e
4125 11:35:57.222924 dump params tx window
4126 11:35:57.223008 tx_center_min[0][0][0] = 981
4127 11:35:57.226610 tx_center_max[0][0][0] = 988
4128 11:35:57.229682 tx_center_min[0][0][1] = 975
4129 11:35:57.232917 tx_center_max[0][0][1] = 982
4130 11:35:57.236091 tx_center_min[0][1][0] = 980
4131 11:35:57.236175 tx_center_max[0][1][0] = 986
4132 11:35:57.239775 tx_center_min[0][1][1] = 978
4133 11:35:57.242705 tx_center_max[0][1][1] = 984
4134 11:35:57.246374 tx_center_min[1][0][0] = 989
4135 11:35:57.249426 tx_center_max[1][0][0] = 993
4136 11:35:57.249510 tx_center_min[1][0][1] = 978
4137 11:35:57.252620 tx_center_max[1][0][1] = 985
4138 11:35:57.255957 tx_center_min[1][1][0] = 987
4139 11:35:57.259427 tx_center_max[1][1][0] = 992
4140 11:35:57.262456 tx_center_min[1][1][1] = 974
4141 11:35:57.262539 tx_center_max[1][1][1] = 981
4142 11:35:57.266063 dump params tx window
4143 11:35:57.269185 tx_win_center[0][0][0] = 988
4144 11:35:57.272494 tx_first_pass[0][0][0] = 976
4145 11:35:57.272579 tx_last_pass[0][0][0] = 1000
4146 11:35:57.276091 tx_win_center[0][0][1] = 987
4147 11:35:57.279399 tx_first_pass[0][0][1] = 975
4148 11:35:57.282818 tx_last_pass[0][0][1] = 999
4149 11:35:57.282903 tx_win_center[0][0][2] = 987
4150 11:35:57.286011 tx_first_pass[0][0][2] = 975
4151 11:35:57.289197 tx_last_pass[0][0][2] = 1000
4152 11:35:57.292422 tx_win_center[0][0][3] = 981
4153 11:35:57.295571 tx_first_pass[0][0][3] = 969
4154 11:35:57.295654 tx_last_pass[0][0][3] = 993
4155 11:35:57.299325 tx_win_center[0][0][4] = 987
4156 11:35:57.302427 tx_first_pass[0][0][4] = 975
4157 11:35:57.305721 tx_last_pass[0][0][4] = 999
4158 11:35:57.305805 tx_win_center[0][0][5] = 983
4159 11:35:57.309172 tx_first_pass[0][0][5] = 972
4160 11:35:57.312214 tx_last_pass[0][0][5] = 995
4161 11:35:57.315659 tx_win_center[0][0][6] = 985
4162 11:35:57.319124 tx_first_pass[0][0][6] = 972
4163 11:35:57.319208 tx_last_pass[0][0][6] = 998
4164 11:35:57.322472 tx_win_center[0][0][7] = 987
4165 11:35:57.326293 tx_first_pass[0][0][7] = 975
4166 11:35:57.329025 tx_last_pass[0][0][7] = 999
4167 11:35:57.329110 tx_win_center[0][0][8] = 975
4168 11:35:57.332530 tx_first_pass[0][0][8] = 963
4169 11:35:57.335704 tx_last_pass[0][0][8] = 987
4170 11:35:57.339107 tx_win_center[0][0][9] = 978
4171 11:35:57.342430 tx_first_pass[0][0][9] = 967
4172 11:35:57.342515 tx_last_pass[0][0][9] = 989
4173 11:35:57.345927 tx_win_center[0][0][10] = 982
4174 11:35:57.349018 tx_first_pass[0][0][10] = 970
4175 11:35:57.352521 tx_last_pass[0][0][10] = 994
4176 11:35:57.355773 tx_win_center[0][0][11] = 976
4177 11:35:57.355857 tx_first_pass[0][0][11] = 965
4178 11:35:57.358817 tx_last_pass[0][0][11] = 988
4179 11:35:57.362607 tx_win_center[0][0][12] = 979
4180 11:35:57.365838 tx_first_pass[0][0][12] = 967
4181 11:35:57.369128 tx_last_pass[0][0][12] = 991
4182 11:35:57.369212 tx_win_center[0][0][13] = 978
4183 11:35:57.372303 tx_first_pass[0][0][13] = 967
4184 11:35:57.376257 tx_last_pass[0][0][13] = 990
4185 11:35:57.379113 tx_win_center[0][0][14] = 979
4186 11:35:57.382301 tx_first_pass[0][0][14] = 967
4187 11:35:57.382385 tx_last_pass[0][0][14] = 991
4188 11:35:57.385521 tx_win_center[0][0][15] = 981
4189 11:35:57.388762 tx_first_pass[0][0][15] = 969
4190 11:35:57.392146 tx_last_pass[0][0][15] = 993
4191 11:35:57.395571 tx_win_center[0][1][0] = 986
4192 11:35:57.395655 tx_first_pass[0][1][0] = 974
4193 11:35:57.398759 tx_last_pass[0][1][0] = 999
4194 11:35:57.402070 tx_win_center[0][1][1] = 985
4195 11:35:57.405765 tx_first_pass[0][1][1] = 974
4196 11:35:57.405849 tx_last_pass[0][1][1] = 997
4197 11:35:57.408976 tx_win_center[0][1][2] = 986
4198 11:35:57.412226 tx_first_pass[0][1][2] = 975
4199 11:35:57.415798 tx_last_pass[0][1][2] = 998
4200 11:35:57.418916 tx_win_center[0][1][3] = 980
4201 11:35:57.419001 tx_first_pass[0][1][3] = 968
4202 11:35:57.422203 tx_last_pass[0][1][3] = 992
4203 11:35:57.425869 tx_win_center[0][1][4] = 984
4204 11:35:57.428919 tx_first_pass[0][1][4] = 971
4205 11:35:57.429003 tx_last_pass[0][1][4] = 997
4206 11:35:57.432093 tx_win_center[0][1][5] = 981
4207 11:35:57.435500 tx_first_pass[0][1][5] = 969
4208 11:35:57.438875 tx_last_pass[0][1][5] = 994
4209 11:35:57.442472 tx_win_center[0][1][6] = 983
4210 11:35:57.442556 tx_first_pass[0][1][6] = 970
4211 11:35:57.445801 tx_last_pass[0][1][6] = 996
4212 11:35:57.449062 tx_win_center[0][1][7] = 984
4213 11:35:57.452231 tx_first_pass[0][1][7] = 971
4214 11:35:57.452315 tx_last_pass[0][1][7] = 998
4215 11:35:57.455684 tx_win_center[0][1][8] = 978
4216 11:35:57.459209 tx_first_pass[0][1][8] = 966
4217 11:35:57.462685 tx_last_pass[0][1][8] = 990
4218 11:35:57.462774 tx_win_center[0][1][9] = 979
4219 11:35:57.465628 tx_first_pass[0][1][9] = 968
4220 11:35:57.469151 tx_last_pass[0][1][9] = 991
4221 11:35:57.472357 tx_win_center[0][1][10] = 984
4222 11:35:57.475915 tx_first_pass[0][1][10] = 972
4223 11:35:57.476000 tx_last_pass[0][1][10] = 997
4224 11:35:57.479218 tx_win_center[0][1][11] = 979
4225 11:35:57.482908 tx_first_pass[0][1][11] = 967
4226 11:35:57.485867 tx_last_pass[0][1][11] = 991
4227 11:35:57.489024 tx_win_center[0][1][12] = 980
4228 11:35:57.489109 tx_first_pass[0][1][12] = 968
4229 11:35:57.492594 tx_last_pass[0][1][12] = 992
4230 11:35:57.495803 tx_win_center[0][1][13] = 980
4231 11:35:57.498983 tx_first_pass[0][1][13] = 969
4232 11:35:57.502194 tx_last_pass[0][1][13] = 991
4233 11:35:57.502279 tx_win_center[0][1][14] = 980
4234 11:35:57.505579 tx_first_pass[0][1][14] = 968
4235 11:35:57.509172 tx_last_pass[0][1][14] = 992
4236 11:35:57.512679 tx_win_center[0][1][15] = 983
4237 11:35:57.515485 tx_first_pass[0][1][15] = 971
4238 11:35:57.515569 tx_last_pass[0][1][15] = 996
4239 11:35:57.519037 tx_win_center[1][0][0] = 993
4240 11:35:57.522305 tx_first_pass[1][0][0] = 980
4241 11:35:57.526043 tx_last_pass[1][0][0] = 1006
4242 11:35:57.529248 tx_win_center[1][0][1] = 992
4243 11:35:57.529329 tx_first_pass[1][0][1] = 979
4244 11:35:57.532419 tx_last_pass[1][0][1] = 1006
4245 11:35:57.535917 tx_win_center[1][0][2] = 990
4246 11:35:57.539382 tx_first_pass[1][0][2] = 978
4247 11:35:57.539466 tx_last_pass[1][0][2] = 1003
4248 11:35:57.542393 tx_win_center[1][0][3] = 989
4249 11:35:57.545710 tx_first_pass[1][0][3] = 977
4250 11:35:57.549083 tx_last_pass[1][0][3] = 1001
4251 11:35:57.552207 tx_win_center[1][0][4] = 993
4252 11:35:57.552317 tx_first_pass[1][0][4] = 980
4253 11:35:57.555477 tx_last_pass[1][0][4] = 1006
4254 11:35:57.558953 tx_win_center[1][0][5] = 993
4255 11:35:57.562529 tx_first_pass[1][0][5] = 981
4256 11:35:57.565616 tx_last_pass[1][0][5] = 1006
4257 11:35:57.565701 tx_win_center[1][0][6] = 992
4258 11:35:57.568610 tx_first_pass[1][0][6] = 979
4259 11:35:57.571924 tx_last_pass[1][0][6] = 1006
4260 11:35:57.575503 tx_win_center[1][0][7] = 992
4261 11:35:57.578681 tx_first_pass[1][0][7] = 979
4262 11:35:57.578764 tx_last_pass[1][0][7] = 1006
4263 11:35:57.582207 tx_win_center[1][0][8] = 981
4264 11:35:57.585631 tx_first_pass[1][0][8] = 969
4265 11:35:57.589012 tx_last_pass[1][0][8] = 993
4266 11:35:57.589096 tx_win_center[1][0][9] = 981
4267 11:35:57.592394 tx_first_pass[1][0][9] = 970
4268 11:35:57.595472 tx_last_pass[1][0][9] = 992
4269 11:35:57.598511 tx_win_center[1][0][10] = 983
4270 11:35:57.601749 tx_first_pass[1][0][10] = 971
4271 11:35:57.601832 tx_last_pass[1][0][10] = 995
4272 11:35:57.605247 tx_win_center[1][0][11] = 983
4273 11:35:57.608477 tx_first_pass[1][0][11] = 972
4274 11:35:57.612021 tx_last_pass[1][0][11] = 995
4275 11:35:57.615337 tx_win_center[1][0][12] = 983
4276 11:35:57.615421 tx_first_pass[1][0][12] = 972
4277 11:35:57.618585 tx_last_pass[1][0][12] = 995
4278 11:35:57.621842 tx_win_center[1][0][13] = 985
4279 11:35:57.625258 tx_first_pass[1][0][13] = 974
4280 11:35:57.628568 tx_last_pass[1][0][13] = 996
4281 11:35:57.628652 tx_win_center[1][0][14] = 983
4282 11:35:57.632092 tx_first_pass[1][0][14] = 971
4283 11:35:57.635028 tx_last_pass[1][0][14] = 995
4284 11:35:57.638256 tx_win_center[1][0][15] = 978
4285 11:35:57.641622 tx_first_pass[1][0][15] = 967
4286 11:35:57.641706 tx_last_pass[1][0][15] = 989
4287 11:35:57.644887 tx_win_center[1][1][0] = 992
4288 11:35:57.648220 tx_first_pass[1][1][0] = 979
4289 11:35:57.651840 tx_last_pass[1][1][0] = 1006
4290 11:35:57.655332 tx_win_center[1][1][1] = 991
4291 11:35:57.655416 tx_first_pass[1][1][1] = 978
4292 11:35:57.658854 tx_last_pass[1][1][1] = 1004
4293 11:35:57.661652 tx_win_center[1][1][2] = 989
4294 11:35:57.665120 tx_first_pass[1][1][2] = 977
4295 11:35:57.668489 tx_last_pass[1][1][2] = 1002
4296 11:35:57.668573 tx_win_center[1][1][3] = 987
4297 11:35:57.671725 tx_first_pass[1][1][3] = 975
4298 11:35:57.674950 tx_last_pass[1][1][3] = 999
4299 11:35:57.678377 tx_win_center[1][1][4] = 991
4300 11:35:57.678463 tx_first_pass[1][1][4] = 978
4301 11:35:57.681658 tx_last_pass[1][1][4] = 1004
4302 11:35:57.684866 tx_win_center[1][1][5] = 992
4303 11:35:57.688383 tx_first_pass[1][1][5] = 979
4304 11:35:57.691468 tx_last_pass[1][1][5] = 1005
4305 11:35:57.691553 tx_win_center[1][1][6] = 991
4306 11:35:57.694969 tx_first_pass[1][1][6] = 978
4307 11:35:57.698137 tx_last_pass[1][1][6] = 1005
4308 11:35:57.701608 tx_win_center[1][1][7] = 991
4309 11:35:57.704987 tx_first_pass[1][1][7] = 979
4310 11:35:57.705070 tx_last_pass[1][1][7] = 1004
4311 11:35:57.708053 tx_win_center[1][1][8] = 978
4312 11:35:57.711514 tx_first_pass[1][1][8] = 967
4313 11:35:57.714574 tx_last_pass[1][1][8] = 989
4314 11:35:57.714657 tx_win_center[1][1][9] = 978
4315 11:35:57.718367 tx_first_pass[1][1][9] = 967
4316 11:35:57.721734 tx_last_pass[1][1][9] = 990
4317 11:35:57.724955 tx_win_center[1][1][10] = 980
4318 11:35:57.728110 tx_first_pass[1][1][10] = 969
4319 11:35:57.728193 tx_last_pass[1][1][10] = 992
4320 11:35:57.731494 tx_win_center[1][1][11] = 981
4321 11:35:57.734820 tx_first_pass[1][1][11] = 969
4322 11:35:57.737944 tx_last_pass[1][1][11] = 993
4323 11:35:57.741539 tx_win_center[1][1][12] = 980
4324 11:35:57.741623 tx_first_pass[1][1][12] = 969
4325 11:35:57.745232 tx_last_pass[1][1][12] = 992
4326 11:35:57.748527 tx_win_center[1][1][13] = 981
4327 11:35:57.751780 tx_first_pass[1][1][13] = 970
4328 11:35:57.755058 tx_last_pass[1][1][13] = 993
4329 11:35:57.755143 tx_win_center[1][1][14] = 980
4330 11:35:57.758128 tx_first_pass[1][1][14] = 969
4331 11:35:57.761908 tx_last_pass[1][1][14] = 992
4332 11:35:57.764817 tx_win_center[1][1][15] = 974
4333 11:35:57.768079 tx_first_pass[1][1][15] = 962
4334 11:35:57.768163 tx_last_pass[1][1][15] = 987
4335 11:35:57.771828 dump params rx window
4336 11:35:57.774836 rx_firspass[0][0][0] = 4
4337 11:35:57.774919 rx_lastpass[0][0][0] = 38
4338 11:35:57.778271 rx_firspass[0][0][1] = 5
4339 11:35:57.781443 rx_lastpass[0][0][1] = 36
4340 11:35:57.781526 rx_firspass[0][0][2] = 6
4341 11:35:57.784853 rx_lastpass[0][0][2] = 36
4342 11:35:57.788043 rx_firspass[0][0][3] = -2
4343 11:35:57.791542 rx_lastpass[0][0][3] = 31
4344 11:35:57.791626 rx_firspass[0][0][4] = 4
4345 11:35:57.794817 rx_lastpass[0][0][4] = 37
4346 11:35:57.798171 rx_firspass[0][0][5] = 1
4347 11:35:57.798255 rx_lastpass[0][0][5] = 32
4348 11:35:57.801955 rx_firspass[0][0][6] = 3
4349 11:35:57.804989 rx_lastpass[0][0][6] = 34
4350 11:35:57.805073 rx_firspass[0][0][7] = 5
4351 11:35:57.808052 rx_lastpass[0][0][7] = 36
4352 11:35:57.811706 rx_firspass[0][0][8] = -2
4353 11:35:57.814871 rx_lastpass[0][0][8] = 33
4354 11:35:57.814956 rx_firspass[0][0][9] = 0
4355 11:35:57.817974 rx_lastpass[0][0][9] = 32
4356 11:35:57.821895 rx_firspass[0][0][10] = 9
4357 11:35:57.821979 rx_lastpass[0][0][10] = 41
4358 11:35:57.825219 rx_firspass[0][0][11] = 1
4359 11:35:57.828153 rx_lastpass[0][0][11] = 32
4360 11:35:57.831367 rx_firspass[0][0][12] = 2
4361 11:35:57.831451 rx_lastpass[0][0][12] = 37
4362 11:35:57.834815 rx_firspass[0][0][13] = 3
4363 11:35:57.837989 rx_lastpass[0][0][13] = 33
4364 11:35:57.841484 rx_firspass[0][0][14] = 2
4365 11:35:57.841568 rx_lastpass[0][0][14] = 37
4366 11:35:57.845099 rx_firspass[0][0][15] = 7
4367 11:35:57.848217 rx_lastpass[0][0][15] = 37
4368 11:35:57.848301 rx_firspass[0][1][0] = 5
4369 11:35:57.851411 rx_lastpass[0][1][0] = 40
4370 11:35:57.855150 rx_firspass[0][1][1] = 5
4371 11:35:57.855234 rx_lastpass[0][1][1] = 38
4372 11:35:57.858290 rx_firspass[0][1][2] = 6
4373 11:35:57.861817 rx_lastpass[0][1][2] = 38
4374 11:35:57.864857 rx_firspass[0][1][3] = -2
4375 11:35:57.864940 rx_lastpass[0][1][3] = 33
4376 11:35:57.868569 rx_firspass[0][1][4] = 5
4377 11:35:57.871902 rx_lastpass[0][1][4] = 39
4378 11:35:57.871985 rx_firspass[0][1][5] = 1
4379 11:35:57.874855 rx_lastpass[0][1][5] = 34
4380 11:35:57.878222 rx_firspass[0][1][6] = 3
4381 11:35:57.878305 rx_lastpass[0][1][6] = 37
4382 11:35:57.881575 rx_firspass[0][1][7] = 3
4383 11:35:57.884956 rx_lastpass[0][1][7] = 38
4384 11:35:57.888178 rx_firspass[0][1][8] = -2
4385 11:35:57.888262 rx_lastpass[0][1][8] = 32
4386 11:35:57.891356 rx_firspass[0][1][9] = 1
4387 11:35:57.895053 rx_lastpass[0][1][9] = 36
4388 11:35:57.895157 rx_firspass[0][1][10] = 7
4389 11:35:57.898129 rx_lastpass[0][1][10] = 43
4390 11:35:57.901570 rx_firspass[0][1][11] = -2
4391 11:35:57.904950 rx_lastpass[0][1][11] = 34
4392 11:35:57.905034 rx_firspass[0][1][12] = 1
4393 11:35:57.907867 rx_lastpass[0][1][12] = 37
4394 11:35:57.911518 rx_firspass[0][1][13] = 2
4395 11:35:57.914700 rx_lastpass[0][1][13] = 35
4396 11:35:57.914784 rx_firspass[0][1][14] = 3
4397 11:35:57.918083 rx_lastpass[0][1][14] = 38
4398 11:35:57.921421 rx_firspass[0][1][15] = 6
4399 11:35:57.924703 rx_lastpass[0][1][15] = 39
4400 11:35:57.924787 rx_firspass[1][0][0] = 5
4401 11:35:57.928220 rx_lastpass[1][0][0] = 38
4402 11:35:57.931267 rx_firspass[1][0][1] = 5
4403 11:35:57.931351 rx_lastpass[1][0][1] = 38
4404 11:35:57.934738 rx_firspass[1][0][2] = 2
4405 11:35:57.937796 rx_lastpass[1][0][2] = 35
4406 11:35:57.937880 rx_firspass[1][0][3] = 0
4407 11:35:57.941110 rx_lastpass[1][0][3] = 33
4408 11:35:57.944709 rx_firspass[1][0][4] = 5
4409 11:35:57.947883 rx_lastpass[1][0][4] = 38
4410 11:35:57.947966 rx_firspass[1][0][5] = 7
4411 11:35:57.951035 rx_lastpass[1][0][5] = 38
4412 11:35:57.954724 rx_firspass[1][0][6] = 7
4413 11:35:57.954808 rx_lastpass[1][0][6] = 40
4414 11:35:57.957875 rx_firspass[1][0][7] = 5
4415 11:35:57.961520 rx_lastpass[1][0][7] = 38
4416 11:35:57.961604 rx_firspass[1][0][8] = 1
4417 11:35:57.964760 rx_lastpass[1][0][8] = 33
4418 11:35:57.967784 rx_firspass[1][0][9] = 0
4419 11:35:57.971292 rx_lastpass[1][0][9] = 32
4420 11:35:57.971376 rx_firspass[1][0][10] = 5
4421 11:35:57.974568 rx_lastpass[1][0][10] = 35
4422 11:35:57.977813 rx_firspass[1][0][11] = 6
4423 11:35:57.977897 rx_lastpass[1][0][11] = 38
4424 11:35:57.980975 rx_firspass[1][0][12] = 6
4425 11:35:57.984481 rx_lastpass[1][0][12] = 38
4426 11:35:57.987951 rx_firspass[1][0][13] = 6
4427 11:35:57.988035 rx_lastpass[1][0][13] = 37
4428 11:35:57.991282 rx_firspass[1][0][14] = 7
4429 11:35:57.994414 rx_lastpass[1][0][14] = 38
4430 11:35:57.994497 rx_firspass[1][0][15] = -3
4431 11:35:57.998021 rx_lastpass[1][0][15] = 30
4432 11:35:58.001377 rx_firspass[1][1][0] = 3
4433 11:35:58.004405 rx_lastpass[1][1][0] = 40
4434 11:35:58.004496 rx_firspass[1][1][1] = 5
4435 11:35:58.008317 rx_lastpass[1][1][1] = 39
4436 11:35:58.011579 rx_firspass[1][1][2] = 1
4437 11:35:58.011662 rx_lastpass[1][1][2] = 36
4438 11:35:58.014604 rx_firspass[1][1][3] = -3
4439 11:35:58.017808 rx_lastpass[1][1][3] = 34
4440 11:35:58.017892 rx_firspass[1][1][4] = 4
4441 11:35:58.020976 rx_lastpass[1][1][4] = 39
4442 11:35:58.024388 rx_firspass[1][1][5] = 5
4443 11:35:58.027662 rx_lastpass[1][1][5] = 40
4444 11:35:58.027745 rx_firspass[1][1][6] = 6
4445 11:35:58.031196 rx_lastpass[1][1][6] = 41
4446 11:35:58.034491 rx_firspass[1][1][7] = 3
4447 11:35:58.034575 rx_lastpass[1][1][7] = 38
4448 11:35:58.038043 rx_firspass[1][1][8] = 0
4449 11:35:58.040883 rx_lastpass[1][1][8] = 35
4450 11:35:58.044229 rx_firspass[1][1][9] = -1
4451 11:35:58.044313 rx_lastpass[1][1][9] = 34
4452 11:35:58.047857 rx_firspass[1][1][10] = 3
4453 11:35:58.050820 rx_lastpass[1][1][10] = 39
4454 11:35:58.050904 rx_firspass[1][1][11] = 4
4455 11:35:58.054503 rx_lastpass[1][1][11] = 40
4456 11:35:58.057902 rx_firspass[1][1][12] = 4
4457 11:35:58.060959 rx_lastpass[1][1][12] = 40
4458 11:35:58.061043 rx_firspass[1][1][13] = 4
4459 11:35:58.064315 rx_lastpass[1][1][13] = 40
4460 11:35:58.067567 rx_firspass[1][1][14] = 5
4461 11:35:58.071208 rx_lastpass[1][1][14] = 40
4462 11:35:58.071292 rx_firspass[1][1][15] = -3
4463 11:35:58.074570 rx_lastpass[1][1][15] = 31
4464 11:35:58.077665 dump params clk_delay
4465 11:35:58.077748 clk_delay[0] = 1
4466 11:35:58.080708 clk_delay[1] = 0
4467 11:35:58.080792 dump params dqs_delay
4468 11:35:58.084756 dqs_delay[0][0] = -2
4469 11:35:58.084839 dqs_delay[0][1] = 0
4470 11:35:58.087758 dqs_delay[1][0] = 0
4471 11:35:58.087841 dqs_delay[1][1] = 0
4472 11:35:58.091224 dump params delay_cell_unit = 735
4473 11:35:58.094045 dump source = 0x0
4474 11:35:58.094128 dump params frequency:1200
4475 11:35:58.097959 dump params rank number:2
4476 11:35:58.098042
4477 11:35:58.100757 dump params write leveling
4478 11:35:58.103994 write leveling[0][0][0] = 0x0
4479 11:35:58.107505 write leveling[0][0][1] = 0x0
4480 11:35:58.107588 write leveling[0][1][0] = 0x0
4481 11:35:58.110933 write leveling[0][1][1] = 0x0
4482 11:35:58.114085 write leveling[1][0][0] = 0x0
4483 11:35:58.117485 write leveling[1][0][1] = 0x0
4484 11:35:58.120960 write leveling[1][1][0] = 0x0
4485 11:35:58.121044 write leveling[1][1][1] = 0x0
4486 11:35:58.123993 dump params cbt_cs
4487 11:35:58.124109 cbt_cs[0][0] = 0x0
4488 11:35:58.127516 cbt_cs[0][1] = 0x0
4489 11:35:58.127599 cbt_cs[1][0] = 0x0
4490 11:35:58.131129 cbt_cs[1][1] = 0x0
4491 11:35:58.134085 dump params cbt_mr12
4492 11:35:58.134168 cbt_mr12[0][0] = 0x0
4493 11:35:58.137597 cbt_mr12[0][1] = 0x0
4494 11:35:58.137681 cbt_mr12[1][0] = 0x0
4495 11:35:58.140912 cbt_mr12[1][1] = 0x0
4496 11:35:58.140996 dump params tx window
4497 11:35:58.144325 tx_center_min[0][0][0] = 0
4498 11:35:58.147848 tx_center_max[0][0][0] = 0
4499 11:35:58.151302 tx_center_min[0][0][1] = 0
4500 11:35:58.151386 tx_center_max[0][0][1] = 0
4501 11:35:58.154209 tx_center_min[0][1][0] = 0
4502 11:35:58.157625 tx_center_max[0][1][0] = 0
4503 11:35:58.160934 tx_center_min[0][1][1] = 0
4504 11:35:58.161018 tx_center_max[0][1][1] = 0
4505 11:35:58.164195 tx_center_min[1][0][0] = 0
4506 11:35:58.167443 tx_center_max[1][0][0] = 0
4507 11:35:58.167527 tx_center_min[1][0][1] = 0
4508 11:35:58.170959 tx_center_max[1][0][1] = 0
4509 11:35:58.174531 tx_center_min[1][1][0] = 0
4510 11:35:58.177925 tx_center_max[1][1][0] = 0
4511 11:35:58.178009 tx_center_min[1][1][1] = 0
4512 11:35:58.180709 tx_center_max[1][1][1] = 0
4513 11:35:58.184001 dump params tx window
4514 11:35:58.187493 tx_win_center[0][0][0] = 0
4515 11:35:58.187577 tx_first_pass[0][0][0] = 0
4516 11:35:58.190487 tx_last_pass[0][0][0] = 0
4517 11:35:58.193936 tx_win_center[0][0][1] = 0
4518 11:35:58.194019 tx_first_pass[0][0][1] = 0
4519 11:35:58.197162 tx_last_pass[0][0][1] = 0
4520 11:35:58.200561 tx_win_center[0][0][2] = 0
4521 11:35:58.204058 tx_first_pass[0][0][2] = 0
4522 11:35:58.204141 tx_last_pass[0][0][2] = 0
4523 11:35:58.207324 tx_win_center[0][0][3] = 0
4524 11:35:58.210430 tx_first_pass[0][0][3] = 0
4525 11:35:58.214047 tx_last_pass[0][0][3] = 0
4526 11:35:58.214130 tx_win_center[0][0][4] = 0
4527 11:35:58.217395 tx_first_pass[0][0][4] = 0
4528 11:35:58.220731 tx_last_pass[0][0][4] = 0
4529 11:35:58.220828 tx_win_center[0][0][5] = 0
4530 11:35:58.223960 tx_first_pass[0][0][5] = 0
4531 11:35:58.227275 tx_last_pass[0][0][5] = 0
4532 11:35:58.230776 tx_win_center[0][0][6] = 0
4533 11:35:58.230860 tx_first_pass[0][0][6] = 0
4534 11:35:58.233914 tx_last_pass[0][0][6] = 0
4535 11:35:58.237519 tx_win_center[0][0][7] = 0
4536 11:35:58.240577 tx_first_pass[0][0][7] = 0
4537 11:35:58.240660 tx_last_pass[0][0][7] = 0
4538 11:35:58.243987 tx_win_center[0][0][8] = 0
4539 11:35:58.247449 tx_first_pass[0][0][8] = 0
4540 11:35:58.247533 tx_last_pass[0][0][8] = 0
4541 11:35:58.250444 tx_win_center[0][0][9] = 0
4542 11:35:58.253888 tx_first_pass[0][0][9] = 0
4543 11:35:58.256948 tx_last_pass[0][0][9] = 0
4544 11:35:58.257031 tx_win_center[0][0][10] = 0
4545 11:35:58.260472 tx_first_pass[0][0][10] = 0
4546 11:35:58.263820 tx_last_pass[0][0][10] = 0
4547 11:35:58.267210 tx_win_center[0][0][11] = 0
4548 11:35:58.267314 tx_first_pass[0][0][11] = 0
4549 11:35:58.270448 tx_last_pass[0][0][11] = 0
4550 11:35:58.273738 tx_win_center[0][0][12] = 0
4551 11:35:58.277274 tx_first_pass[0][0][12] = 0
4552 11:35:58.277363 tx_last_pass[0][0][12] = 0
4553 11:35:58.280418 tx_win_center[0][0][13] = 0
4554 11:35:58.283700 tx_first_pass[0][0][13] = 0
4555 11:35:58.286829 tx_last_pass[0][0][13] = 0
4556 11:35:58.286917 tx_win_center[0][0][14] = 0
4557 11:35:58.290530 tx_first_pass[0][0][14] = 0
4558 11:35:58.293871 tx_last_pass[0][0][14] = 0
4559 11:35:58.297141 tx_win_center[0][0][15] = 0
4560 11:35:58.297228 tx_first_pass[0][0][15] = 0
4561 11:35:58.300367 tx_last_pass[0][0][15] = 0
4562 11:35:58.303792 tx_win_center[0][1][0] = 0
4563 11:35:58.307731 tx_first_pass[0][1][0] = 0
4564 11:35:58.307840 tx_last_pass[0][1][0] = 0
4565 11:35:58.310240 tx_win_center[0][1][1] = 0
4566 11:35:58.313677 tx_first_pass[0][1][1] = 0
4567 11:35:58.313755 tx_last_pass[0][1][1] = 0
4568 11:35:58.316796 tx_win_center[0][1][2] = 0
4569 11:35:58.320445 tx_first_pass[0][1][2] = 0
4570 11:35:58.323372 tx_last_pass[0][1][2] = 0
4571 11:35:58.323457 tx_win_center[0][1][3] = 0
4572 11:35:58.326707 tx_first_pass[0][1][3] = 0
4573 11:35:58.330123 tx_last_pass[0][1][3] = 0
4574 11:35:58.333604 tx_win_center[0][1][4] = 0
4575 11:35:58.333678 tx_first_pass[0][1][4] = 0
4576 11:35:58.337009 tx_last_pass[0][1][4] = 0
4577 11:35:58.340154 tx_win_center[0][1][5] = 0
4578 11:35:58.340247 tx_first_pass[0][1][5] = 0
4579 11:35:58.343883 tx_last_pass[0][1][5] = 0
4580 11:35:58.347467 tx_win_center[0][1][6] = 0
4581 11:35:58.350310 tx_first_pass[0][1][6] = 0
4582 11:35:58.350428 tx_last_pass[0][1][6] = 0
4583 11:35:58.353684 tx_win_center[0][1][7] = 0
4584 11:35:58.357047 tx_first_pass[0][1][7] = 0
4585 11:35:58.357184 tx_last_pass[0][1][7] = 0
4586 11:35:58.360636 tx_win_center[0][1][8] = 0
4587 11:35:58.363492 tx_first_pass[0][1][8] = 0
4588 11:35:58.367061 tx_last_pass[0][1][8] = 0
4589 11:35:58.367169 tx_win_center[0][1][9] = 0
4590 11:35:58.370135 tx_first_pass[0][1][9] = 0
4591 11:35:58.373825 tx_last_pass[0][1][9] = 0
4592 11:35:58.377378 tx_win_center[0][1][10] = 0
4593 11:35:58.377574 tx_first_pass[0][1][10] = 0
4594 11:35:58.380267 tx_last_pass[0][1][10] = 0
4595 11:35:58.383816 tx_win_center[0][1][11] = 0
4596 11:35:58.386786 tx_first_pass[0][1][11] = 0
4597 11:35:58.386992 tx_last_pass[0][1][11] = 0
4598 11:35:58.390739 tx_win_center[0][1][12] = 0
4599 11:35:58.394152 tx_first_pass[0][1][12] = 0
4600 11:35:58.397200 tx_last_pass[0][1][12] = 0
4601 11:35:58.397528 tx_win_center[0][1][13] = 0
4602 11:35:58.400585 tx_first_pass[0][1][13] = 0
4603 11:35:58.404317 tx_last_pass[0][1][13] = 0
4604 11:35:58.407294 tx_win_center[0][1][14] = 0
4605 11:35:58.407756 tx_first_pass[0][1][14] = 0
4606 11:35:58.410912 tx_last_pass[0][1][14] = 0
4607 11:35:58.414058 tx_win_center[0][1][15] = 0
4608 11:35:58.417365 tx_first_pass[0][1][15] = 0
4609 11:35:58.417804 tx_last_pass[0][1][15] = 0
4610 11:35:58.420738 tx_win_center[1][0][0] = 0
4611 11:35:58.424157 tx_first_pass[1][0][0] = 0
4612 11:35:58.427442 tx_last_pass[1][0][0] = 0
4613 11:35:58.427911 tx_win_center[1][0][1] = 0
4614 11:35:58.431105 tx_first_pass[1][0][1] = 0
4615 11:35:58.434291 tx_last_pass[1][0][1] = 0
4616 11:35:58.434801 tx_win_center[1][0][2] = 0
4617 11:35:58.437708 tx_first_pass[1][0][2] = 0
4618 11:35:58.441151 tx_last_pass[1][0][2] = 0
4619 11:35:58.443956 tx_win_center[1][0][3] = 0
4620 11:35:58.444499 tx_first_pass[1][0][3] = 0
4621 11:35:58.447975 tx_last_pass[1][0][3] = 0
4622 11:35:58.451038 tx_win_center[1][0][4] = 0
4623 11:35:58.453907 tx_first_pass[1][0][4] = 0
4624 11:35:58.454339 tx_last_pass[1][0][4] = 0
4625 11:35:58.457208 tx_win_center[1][0][5] = 0
4626 11:35:58.460887 tx_first_pass[1][0][5] = 0
4627 11:35:58.461390 tx_last_pass[1][0][5] = 0
4628 11:35:58.464047 tx_win_center[1][0][6] = 0
4629 11:35:58.467503 tx_first_pass[1][0][6] = 0
4630 11:35:58.470631 tx_last_pass[1][0][6] = 0
4631 11:35:58.471018 tx_win_center[1][0][7] = 0
4632 11:35:58.474009 tx_first_pass[1][0][7] = 0
4633 11:35:58.477523 tx_last_pass[1][0][7] = 0
4634 11:35:58.481052 tx_win_center[1][0][8] = 0
4635 11:35:58.481563 tx_first_pass[1][0][8] = 0
4636 11:35:58.484129 tx_last_pass[1][0][8] = 0
4637 11:35:58.487195 tx_win_center[1][0][9] = 0
4638 11:35:58.487624 tx_first_pass[1][0][9] = 0
4639 11:35:58.490455 tx_last_pass[1][0][9] = 0
4640 11:35:58.493926 tx_win_center[1][0][10] = 0
4641 11:35:58.497374 tx_first_pass[1][0][10] = 0
4642 11:35:58.498512 tx_last_pass[1][0][10] = 0
4643 11:35:58.500574 tx_win_center[1][0][11] = 0
4644 11:35:58.503661 tx_first_pass[1][0][11] = 0
4645 11:35:58.506852 tx_last_pass[1][0][11] = 0
4646 11:35:58.507273 tx_win_center[1][0][12] = 0
4647 11:35:58.510495 tx_first_pass[1][0][12] = 0
4648 11:35:58.513727 tx_last_pass[1][0][12] = 0
4649 11:35:58.516706 tx_win_center[1][0][13] = 0
4650 11:35:58.517097 tx_first_pass[1][0][13] = 0
4651 11:35:58.520245 tx_last_pass[1][0][13] = 0
4652 11:35:58.523518 tx_win_center[1][0][14] = 0
4653 11:35:58.526963 tx_first_pass[1][0][14] = 0
4654 11:35:58.527387 tx_last_pass[1][0][14] = 0
4655 11:35:58.530478 tx_win_center[1][0][15] = 0
4656 11:35:58.533809 tx_first_pass[1][0][15] = 0
4657 11:35:58.537110 tx_last_pass[1][0][15] = 0
4658 11:35:58.537623 tx_win_center[1][1][0] = 0
4659 11:35:58.540086 tx_first_pass[1][1][0] = 0
4660 11:35:58.543482 tx_last_pass[1][1][0] = 0
4661 11:35:58.547286 tx_win_center[1][1][1] = 0
4662 11:35:58.547762 tx_first_pass[1][1][1] = 0
4663 11:35:58.550246 tx_last_pass[1][1][1] = 0
4664 11:35:58.553606 tx_win_center[1][1][2] = 0
4665 11:35:58.553993 tx_first_pass[1][1][2] = 0
4666 11:35:58.557086 tx_last_pass[1][1][2] = 0
4667 11:35:58.560273 tx_win_center[1][1][3] = 0
4668 11:35:58.563759 tx_first_pass[1][1][3] = 0
4669 11:35:58.564218 tx_last_pass[1][1][3] = 0
4670 11:35:58.567342 tx_win_center[1][1][4] = 0
4671 11:35:58.570292 tx_first_pass[1][1][4] = 0
4672 11:35:58.574209 tx_last_pass[1][1][4] = 0
4673 11:35:58.574674 tx_win_center[1][1][5] = 0
4674 11:35:58.576821 tx_first_pass[1][1][5] = 0
4675 11:35:58.580336 tx_last_pass[1][1][5] = 0
4676 11:35:58.580962 tx_win_center[1][1][6] = 0
4677 11:35:58.583878 tx_first_pass[1][1][6] = 0
4678 11:35:58.587279 tx_last_pass[1][1][6] = 0
4679 11:35:58.590273 tx_win_center[1][1][7] = 0
4680 11:35:58.590652 tx_first_pass[1][1][7] = 0
4681 11:35:58.593698 tx_last_pass[1][1][7] = 0
4682 11:35:58.597296 tx_win_center[1][1][8] = 0
4683 11:35:58.600406 tx_first_pass[1][1][8] = 0
4684 11:35:58.600917 tx_last_pass[1][1][8] = 0
4685 11:35:58.603971 tx_win_center[1][1][9] = 0
4686 11:35:58.607059 tx_first_pass[1][1][9] = 0
4687 11:35:58.607542 tx_last_pass[1][1][9] = 0
4688 11:35:58.610575 tx_win_center[1][1][10] = 0
4689 11:35:58.614034 tx_first_pass[1][1][10] = 0
4690 11:35:58.616814 tx_last_pass[1][1][10] = 0
4691 11:35:58.617320 tx_win_center[1][1][11] = 0
4692 11:35:58.620430 tx_first_pass[1][1][11] = 0
4693 11:35:58.623810 tx_last_pass[1][1][11] = 0
4694 11:35:58.627569 tx_win_center[1][1][12] = 0
4695 11:35:58.628029 tx_first_pass[1][1][12] = 0
4696 11:35:58.630473 tx_last_pass[1][1][12] = 0
4697 11:35:58.633748 tx_win_center[1][1][13] = 0
4698 11:35:58.636848 tx_first_pass[1][1][13] = 0
4699 11:35:58.637235 tx_last_pass[1][1][13] = 0
4700 11:35:58.640406 tx_win_center[1][1][14] = 0
4701 11:35:58.643797 tx_first_pass[1][1][14] = 0
4702 11:35:58.646972 tx_last_pass[1][1][14] = 0
4703 11:35:58.647429 tx_win_center[1][1][15] = 0
4704 11:35:58.650636 tx_first_pass[1][1][15] = 0
4705 11:35:58.653442 tx_last_pass[1][1][15] = 0
4706 11:35:58.656736 dump params rx window
4707 11:35:58.657119 rx_firspass[0][0][0] = 0
4708 11:35:58.660319 rx_lastpass[0][0][0] = 0
4709 11:35:58.663632 rx_firspass[0][0][1] = 0
4710 11:35:58.664073 rx_lastpass[0][0][1] = 0
4711 11:35:58.666642 rx_firspass[0][0][2] = 0
4712 11:35:58.670267 rx_lastpass[0][0][2] = 0
4713 11:35:58.670730 rx_firspass[0][0][3] = 0
4714 11:35:58.673263 rx_lastpass[0][0][3] = 0
4715 11:35:58.676819 rx_firspass[0][0][4] = 0
4716 11:35:58.677285 rx_lastpass[0][0][4] = 0
4717 11:35:58.679972 rx_firspass[0][0][5] = 0
4718 11:35:58.683374 rx_lastpass[0][0][5] = 0
4719 11:35:58.683757 rx_firspass[0][0][6] = 0
4720 11:35:58.686788 rx_lastpass[0][0][6] = 0
4721 11:35:58.689856 rx_firspass[0][0][7] = 0
4722 11:35:58.693519 rx_lastpass[0][0][7] = 0
4723 11:35:58.693902 rx_firspass[0][0][8] = 0
4724 11:35:58.696994 rx_lastpass[0][0][8] = 0
4725 11:35:58.700374 rx_firspass[0][0][9] = 0
4726 11:35:58.700806 rx_lastpass[0][0][9] = 0
4727 11:35:58.703367 rx_firspass[0][0][10] = 0
4728 11:35:58.707044 rx_lastpass[0][0][10] = 0
4729 11:35:58.707505 rx_firspass[0][0][11] = 0
4730 11:35:58.710065 rx_lastpass[0][0][11] = 0
4731 11:35:58.713637 rx_firspass[0][0][12] = 0
4732 11:35:58.716972 rx_lastpass[0][0][12] = 0
4733 11:35:58.717493 rx_firspass[0][0][13] = 0
4734 11:35:58.720220 rx_lastpass[0][0][13] = 0
4735 11:35:58.723459 rx_firspass[0][0][14] = 0
4736 11:35:58.723922 rx_lastpass[0][0][14] = 0
4737 11:35:58.726918 rx_firspass[0][0][15] = 0
4738 11:35:58.729958 rx_lastpass[0][0][15] = 0
4739 11:35:58.730341 rx_firspass[0][1][0] = 0
4740 11:35:58.733728 rx_lastpass[0][1][0] = 0
4741 11:35:58.736949 rx_firspass[0][1][1] = 0
4742 11:35:58.739812 rx_lastpass[0][1][1] = 0
4743 11:35:58.740191 rx_firspass[0][1][2] = 0
4744 11:35:58.743636 rx_lastpass[0][1][2] = 0
4745 11:35:58.746847 rx_firspass[0][1][3] = 0
4746 11:35:58.747308 rx_lastpass[0][1][3] = 0
4747 11:35:58.750070 rx_firspass[0][1][4] = 0
4748 11:35:58.753546 rx_lastpass[0][1][4] = 0
4749 11:35:58.754003 rx_firspass[0][1][5] = 0
4750 11:35:58.756444 rx_lastpass[0][1][5] = 0
4751 11:35:58.760347 rx_firspass[0][1][6] = 0
4752 11:35:58.760897 rx_lastpass[0][1][6] = 0
4753 11:35:58.763350 rx_firspass[0][1][7] = 0
4754 11:35:58.766616 rx_lastpass[0][1][7] = 0
4755 11:35:58.766999 rx_firspass[0][1][8] = 0
4756 11:35:58.770057 rx_lastpass[0][1][8] = 0
4757 11:35:58.773406 rx_firspass[0][1][9] = 0
4758 11:35:58.776763 rx_lastpass[0][1][9] = 0
4759 11:35:58.777330 rx_firspass[0][1][10] = 0
4760 11:35:58.780042 rx_lastpass[0][1][10] = 0
4761 11:35:58.783065 rx_firspass[0][1][11] = 0
4762 11:35:58.783443 rx_lastpass[0][1][11] = 0
4763 11:35:58.786203 rx_firspass[0][1][12] = 0
4764 11:35:58.789934 rx_lastpass[0][1][12] = 0
4765 11:35:58.792923 rx_firspass[0][1][13] = 0
4766 11:35:58.793304 rx_lastpass[0][1][13] = 0
4767 11:35:58.796375 rx_firspass[0][1][14] = 0
4768 11:35:58.799867 rx_lastpass[0][1][14] = 0
4769 11:35:58.800251 rx_firspass[0][1][15] = 0
4770 11:35:58.803628 rx_lastpass[0][1][15] = 0
4771 11:35:58.806930 rx_firspass[1][0][0] = 0
4772 11:35:58.807385 rx_lastpass[1][0][0] = 0
4773 11:35:58.809828 rx_firspass[1][0][1] = 0
4774 11:35:58.813070 rx_lastpass[1][0][1] = 0
4775 11:35:58.816401 rx_firspass[1][0][2] = 0
4776 11:35:58.816828 rx_lastpass[1][0][2] = 0
4777 11:35:58.819696 rx_firspass[1][0][3] = 0
4778 11:35:58.823194 rx_lastpass[1][0][3] = 0
4779 11:35:58.823575 rx_firspass[1][0][4] = 0
4780 11:35:58.826658 rx_lastpass[1][0][4] = 0
4781 11:35:58.829694 rx_firspass[1][0][5] = 0
4782 11:35:58.830077 rx_lastpass[1][0][5] = 0
4783 11:35:58.833515 rx_firspass[1][0][6] = 0
4784 11:35:58.836752 rx_lastpass[1][0][6] = 0
4785 11:35:58.837222 rx_firspass[1][0][7] = 0
4786 11:35:58.839848 rx_lastpass[1][0][7] = 0
4787 11:35:58.843399 rx_firspass[1][0][8] = 0
4788 11:35:58.843861 rx_lastpass[1][0][8] = 0
4789 11:35:58.846344 rx_firspass[1][0][9] = 0
4790 11:35:58.849630 rx_lastpass[1][0][9] = 0
4791 11:35:58.852770 rx_firspass[1][0][10] = 0
4792 11:35:58.853149 rx_lastpass[1][0][10] = 0
4793 11:35:58.856299 rx_firspass[1][0][11] = 0
4794 11:35:58.859785 rx_lastpass[1][0][11] = 0
4795 11:35:58.860254 rx_firspass[1][0][12] = 0
4796 11:35:58.863063 rx_lastpass[1][0][12] = 0
4797 11:35:58.866391 rx_firspass[1][0][13] = 0
4798 11:35:58.869289 rx_lastpass[1][0][13] = 0
4799 11:35:58.869691 rx_firspass[1][0][14] = 0
4800 11:35:58.873367 rx_lastpass[1][0][14] = 0
4801 11:35:58.876169 rx_firspass[1][0][15] = 0
4802 11:35:58.876654 rx_lastpass[1][0][15] = 0
4803 11:35:58.879897 rx_firspass[1][1][0] = 0
4804 11:35:58.883011 rx_lastpass[1][1][0] = 0
4805 11:35:58.883395 rx_firspass[1][1][1] = 0
4806 11:35:58.885943 rx_lastpass[1][1][1] = 0
4807 11:35:58.889384 rx_firspass[1][1][2] = 0
4808 11:35:58.892969 rx_lastpass[1][1][2] = 0
4809 11:35:58.893431 rx_firspass[1][1][3] = 0
4810 11:35:58.896134 rx_lastpass[1][1][3] = 0
4811 11:35:58.899191 rx_firspass[1][1][4] = 0
4812 11:35:58.899601 rx_lastpass[1][1][4] = 0
4813 11:35:58.903105 rx_firspass[1][1][5] = 0
4814 11:35:58.906132 rx_lastpass[1][1][5] = 0
4815 11:35:58.906598 rx_firspass[1][1][6] = 0
4816 11:35:58.909188 rx_lastpass[1][1][6] = 0
4817 11:35:58.912373 rx_firspass[1][1][7] = 0
4818 11:35:58.912888 rx_lastpass[1][1][7] = 0
4819 11:35:58.916135 rx_firspass[1][1][8] = 0
4820 11:35:58.919534 rx_lastpass[1][1][8] = 0
4821 11:35:58.919991 rx_firspass[1][1][9] = 0
4822 11:35:58.922383 rx_lastpass[1][1][9] = 0
4823 11:35:58.926064 rx_firspass[1][1][10] = 0
4824 11:35:58.929350 rx_lastpass[1][1][10] = 0
4825 11:35:58.929804 rx_firspass[1][1][11] = 0
4826 11:35:58.932764 rx_lastpass[1][1][11] = 0
4827 11:35:58.936281 rx_firspass[1][1][12] = 0
4828 11:35:58.936796 rx_lastpass[1][1][12] = 0
4829 11:35:58.939624 rx_firspass[1][1][13] = 0
4830 11:35:58.942732 rx_lastpass[1][1][13] = 0
4831 11:35:58.945822 rx_firspass[1][1][14] = 0
4832 11:35:58.946277 rx_lastpass[1][1][14] = 0
4833 11:35:58.949589 rx_firspass[1][1][15] = 0
4834 11:35:58.952953 rx_lastpass[1][1][15] = 0
4835 11:35:58.953412 dump params clk_delay
4836 11:35:58.956036 clk_delay[0] = 0
4837 11:35:58.956545 clk_delay[1] = 0
4838 11:35:58.959154 dump params dqs_delay
4839 11:35:58.959612 dqs_delay[0][0] = 0
4840 11:35:58.962457 dqs_delay[0][1] = 0
4841 11:35:58.966155 dqs_delay[1][0] = 0
4842 11:35:58.966786 dqs_delay[1][1] = 0
4843 11:35:58.969134 dump params delay_cell_unit = 735
4844 11:35:58.969516 dump source = 0x0
4845 11:35:58.972646 dump params frequency:800
4846 11:35:58.975970 dump params rank number:2
4847 11:35:58.976653
4848 11:35:58.979584 dump params write leveling
4849 11:35:58.980052 write leveling[0][0][0] = 0x0
4850 11:35:58.982470 write leveling[0][0][1] = 0x0
4851 11:35:58.985569 write leveling[0][1][0] = 0x0
4852 11:35:58.989360 write leveling[0][1][1] = 0x0
4853 11:35:58.992367 write leveling[1][0][0] = 0x0
4854 11:35:58.992857 write leveling[1][0][1] = 0x0
4855 11:35:58.995829 write leveling[1][1][0] = 0x0
4856 11:35:58.998971 write leveling[1][1][1] = 0x0
4857 11:35:59.002132 dump params cbt_cs
4858 11:35:59.002509 cbt_cs[0][0] = 0x0
4859 11:35:59.005883 cbt_cs[0][1] = 0x0
4860 11:35:59.006486 cbt_cs[1][0] = 0x0
4861 11:35:59.009047 cbt_cs[1][1] = 0x0
4862 11:35:59.009504 dump params cbt_mr12
4863 11:35:59.012630 cbt_mr12[0][0] = 0x0
4864 11:35:59.013088 cbt_mr12[0][1] = 0x0
4865 11:35:59.015786 cbt_mr12[1][0] = 0x0
4866 11:35:59.016273 cbt_mr12[1][1] = 0x0
4867 11:35:59.018858 dump params tx window
4868 11:35:59.022505 tx_center_min[0][0][0] = 0
4869 11:35:59.026148 tx_center_max[0][0][0] = 0
4870 11:35:59.026606 tx_center_min[0][0][1] = 0
4871 11:35:59.029082 tx_center_max[0][0][1] = 0
4872 11:35:59.032784 tx_center_min[0][1][0] = 0
4873 11:35:59.033242 tx_center_max[0][1][0] = 0
4874 11:35:59.035818 tx_center_min[0][1][1] = 0
4875 11:35:59.039684 tx_center_max[0][1][1] = 0
4876 11:35:59.042801 tx_center_min[1][0][0] = 0
4877 11:35:59.043259 tx_center_max[1][0][0] = 0
4878 11:35:59.045842 tx_center_min[1][0][1] = 0
4879 11:35:59.049107 tx_center_max[1][0][1] = 0
4880 11:35:59.052844 tx_center_min[1][1][0] = 0
4881 11:35:59.053311 tx_center_max[1][1][0] = 0
4882 11:35:59.055684 tx_center_min[1][1][1] = 0
4883 11:35:59.059394 tx_center_max[1][1][1] = 0
4884 11:35:59.059855 dump params tx window
4885 11:35:59.062491 tx_win_center[0][0][0] = 0
4886 11:35:59.066113 tx_first_pass[0][0][0] = 0
4887 11:35:59.069257 tx_last_pass[0][0][0] = 0
4888 11:35:59.069646 tx_win_center[0][0][1] = 0
4889 11:35:59.072053 tx_first_pass[0][0][1] = 0
4890 11:35:59.075966 tx_last_pass[0][0][1] = 0
4891 11:35:59.079334 tx_win_center[0][0][2] = 0
4892 11:35:59.079797 tx_first_pass[0][0][2] = 0
4893 11:35:59.082132 tx_last_pass[0][0][2] = 0
4894 11:35:59.085410 tx_win_center[0][0][3] = 0
4895 11:35:59.089153 tx_first_pass[0][0][3] = 0
4896 11:35:59.089663 tx_last_pass[0][0][3] = 0
4897 11:35:59.092088 tx_win_center[0][0][4] = 0
4898 11:35:59.095740 tx_first_pass[0][0][4] = 0
4899 11:35:59.096179 tx_last_pass[0][0][4] = 0
4900 11:35:59.098731 tx_win_center[0][0][5] = 0
4901 11:35:59.102553 tx_first_pass[0][0][5] = 0
4902 11:35:59.105888 tx_last_pass[0][0][5] = 0
4903 11:35:59.106347 tx_win_center[0][0][6] = 0
4904 11:35:59.108942 tx_first_pass[0][0][6] = 0
4905 11:35:59.112326 tx_last_pass[0][0][6] = 0
4906 11:35:59.112909 tx_win_center[0][0][7] = 0
4907 11:35:59.115734 tx_first_pass[0][0][7] = 0
4908 11:35:59.118564 tx_last_pass[0][0][7] = 0
4909 11:35:59.122115 tx_win_center[0][0][8] = 0
4910 11:35:59.122500 tx_first_pass[0][0][8] = 0
4911 11:35:59.125115 tx_last_pass[0][0][8] = 0
4912 11:35:59.128761 tx_win_center[0][0][9] = 0
4913 11:35:59.132103 tx_first_pass[0][0][9] = 0
4914 11:35:59.132522 tx_last_pass[0][0][9] = 0
4915 11:35:59.135446 tx_win_center[0][0][10] = 0
4916 11:35:59.139091 tx_first_pass[0][0][10] = 0
4917 11:35:59.142108 tx_last_pass[0][0][10] = 0
4918 11:35:59.142569 tx_win_center[0][0][11] = 0
4919 11:35:59.145706 tx_first_pass[0][0][11] = 0
4920 11:35:59.148963 tx_last_pass[0][0][11] = 0
4921 11:35:59.152013 tx_win_center[0][0][12] = 0
4922 11:35:59.152513 tx_first_pass[0][0][12] = 0
4923 11:35:59.155237 tx_last_pass[0][0][12] = 0
4924 11:35:59.158379 tx_win_center[0][0][13] = 0
4925 11:35:59.162297 tx_first_pass[0][0][13] = 0
4926 11:35:59.162766 tx_last_pass[0][0][13] = 0
4927 11:35:59.165563 tx_win_center[0][0][14] = 0
4928 11:35:59.168552 tx_first_pass[0][0][14] = 0
4929 11:35:59.171895 tx_last_pass[0][0][14] = 0
4930 11:35:59.172355 tx_win_center[0][0][15] = 0
4931 11:35:59.175230 tx_first_pass[0][0][15] = 0
4932 11:35:59.178532 tx_last_pass[0][0][15] = 0
4933 11:35:59.182066 tx_win_center[0][1][0] = 0
4934 11:35:59.182447 tx_first_pass[0][1][0] = 0
4935 11:35:59.185481 tx_last_pass[0][1][0] = 0
4936 11:35:59.188361 tx_win_center[0][1][1] = 0
4937 11:35:59.191942 tx_first_pass[0][1][1] = 0
4938 11:35:59.192398 tx_last_pass[0][1][1] = 0
4939 11:35:59.194803 tx_win_center[0][1][2] = 0
4940 11:35:59.198207 tx_first_pass[0][1][2] = 0
4941 11:35:59.198582 tx_last_pass[0][1][2] = 0
4942 11:35:59.202156 tx_win_center[0][1][3] = 0
4943 11:35:59.205112 tx_first_pass[0][1][3] = 0
4944 11:35:59.208527 tx_last_pass[0][1][3] = 0
4945 11:35:59.209000 tx_win_center[0][1][4] = 0
4946 11:35:59.211825 tx_first_pass[0][1][4] = 0
4947 11:35:59.215074 tx_last_pass[0][1][4] = 0
4948 11:35:59.215459 tx_win_center[0][1][5] = 0
4949 11:35:59.218153 tx_first_pass[0][1][5] = 0
4950 11:35:59.221943 tx_last_pass[0][1][5] = 0
4951 11:35:59.225477 tx_win_center[0][1][6] = 0
4952 11:35:59.225942 tx_first_pass[0][1][6] = 0
4953 11:35:59.228715 tx_last_pass[0][1][6] = 0
4954 11:35:59.231777 tx_win_center[0][1][7] = 0
4955 11:35:59.235409 tx_first_pass[0][1][7] = 0
4956 11:35:59.235908 tx_last_pass[0][1][7] = 0
4957 11:35:59.238723 tx_win_center[0][1][8] = 0
4958 11:35:59.242087 tx_first_pass[0][1][8] = 0
4959 11:35:59.242591 tx_last_pass[0][1][8] = 0
4960 11:35:59.245387 tx_win_center[0][1][9] = 0
4961 11:35:59.248506 tx_first_pass[0][1][9] = 0
4962 11:35:59.251898 tx_last_pass[0][1][9] = 0
4963 11:35:59.252395 tx_win_center[0][1][10] = 0
4964 11:35:59.255325 tx_first_pass[0][1][10] = 0
4965 11:35:59.258306 tx_last_pass[0][1][10] = 0
4966 11:35:59.262044 tx_win_center[0][1][11] = 0
4967 11:35:59.262537 tx_first_pass[0][1][11] = 0
4968 11:35:59.265311 tx_last_pass[0][1][11] = 0
4969 11:35:59.268522 tx_win_center[0][1][12] = 0
4970 11:35:59.272109 tx_first_pass[0][1][12] = 0
4971 11:35:59.272648 tx_last_pass[0][1][12] = 0
4972 11:35:59.275631 tx_win_center[0][1][13] = 0
4973 11:35:59.278758 tx_first_pass[0][1][13] = 0
4974 11:35:59.282114 tx_last_pass[0][1][13] = 0
4975 11:35:59.282693 tx_win_center[0][1][14] = 0
4976 11:35:59.285007 tx_first_pass[0][1][14] = 0
4977 11:35:59.288562 tx_last_pass[0][1][14] = 0
4978 11:35:59.291769 tx_win_center[0][1][15] = 0
4979 11:35:59.292260 tx_first_pass[0][1][15] = 0
4980 11:35:59.294977 tx_last_pass[0][1][15] = 0
4981 11:35:59.298430 tx_win_center[1][0][0] = 0
4982 11:35:59.301713 tx_first_pass[1][0][0] = 0
4983 11:35:59.302139 tx_last_pass[1][0][0] = 0
4984 11:35:59.304856 tx_win_center[1][0][1] = 0
4985 11:35:59.308327 tx_first_pass[1][0][1] = 0
4986 11:35:59.308880 tx_last_pass[1][0][1] = 0
4987 11:35:59.311668 tx_win_center[1][0][2] = 0
4988 11:35:59.314794 tx_first_pass[1][0][2] = 0
4989 11:35:59.317924 tx_last_pass[1][0][2] = 0
4990 11:35:59.318356 tx_win_center[1][0][3] = 0
4991 11:35:59.321453 tx_first_pass[1][0][3] = 0
4992 11:35:59.325341 tx_last_pass[1][0][3] = 0
4993 11:35:59.328127 tx_win_center[1][0][4] = 0
4994 11:35:59.328566 tx_first_pass[1][0][4] = 0
4995 11:35:59.332266 tx_last_pass[1][0][4] = 0
4996 11:35:59.334915 tx_win_center[1][0][5] = 0
4997 11:35:59.335297 tx_first_pass[1][0][5] = 0
4998 11:35:59.338343 tx_last_pass[1][0][5] = 0
4999 11:35:59.342215 tx_win_center[1][0][6] = 0
5000 11:35:59.345031 tx_first_pass[1][0][6] = 0
5001 11:35:59.345453 tx_last_pass[1][0][6] = 0
5002 11:35:59.348833 tx_win_center[1][0][7] = 0
5003 11:35:59.351766 tx_first_pass[1][0][7] = 0
5004 11:35:59.355284 tx_last_pass[1][0][7] = 0
5005 11:35:59.355780 tx_win_center[1][0][8] = 0
5006 11:35:59.358065 tx_first_pass[1][0][8] = 0
5007 11:35:59.361477 tx_last_pass[1][0][8] = 0
5008 11:35:59.361976 tx_win_center[1][0][9] = 0
5009 11:35:59.365083 tx_first_pass[1][0][9] = 0
5010 11:35:59.368041 tx_last_pass[1][0][9] = 0
5011 11:35:59.371265 tx_win_center[1][0][10] = 0
5012 11:35:59.371689 tx_first_pass[1][0][10] = 0
5013 11:35:59.374491 tx_last_pass[1][0][10] = 0
5014 11:35:59.378409 tx_win_center[1][0][11] = 0
5015 11:35:59.381407 tx_first_pass[1][0][11] = 0
5016 11:35:59.381919 tx_last_pass[1][0][11] = 0
5017 11:35:59.384664 tx_win_center[1][0][12] = 0
5018 11:35:59.388158 tx_first_pass[1][0][12] = 0
5019 11:35:59.391575 tx_last_pass[1][0][12] = 0
5020 11:35:59.392073 tx_win_center[1][0][13] = 0
5021 11:35:59.395000 tx_first_pass[1][0][13] = 0
5022 11:35:59.398159 tx_last_pass[1][0][13] = 0
5023 11:35:59.401360 tx_win_center[1][0][14] = 0
5024 11:35:59.401844 tx_first_pass[1][0][14] = 0
5025 11:35:59.405051 tx_last_pass[1][0][14] = 0
5026 11:35:59.408213 tx_win_center[1][0][15] = 0
5027 11:35:59.411182 tx_first_pass[1][0][15] = 0
5028 11:35:59.411587 tx_last_pass[1][0][15] = 0
5029 11:35:59.414429 tx_win_center[1][1][0] = 0
5030 11:35:59.417691 tx_first_pass[1][1][0] = 0
5031 11:35:59.421359 tx_last_pass[1][1][0] = 0
5032 11:35:59.421839 tx_win_center[1][1][1] = 0
5033 11:35:59.424738 tx_first_pass[1][1][1] = 0
5034 11:35:59.428154 tx_last_pass[1][1][1] = 0
5035 11:35:59.431838 tx_win_center[1][1][2] = 0
5036 11:35:59.432299 tx_first_pass[1][1][2] = 0
5037 11:35:59.434481 tx_last_pass[1][1][2] = 0
5038 11:35:59.438228 tx_win_center[1][1][3] = 0
5039 11:35:59.438698 tx_first_pass[1][1][3] = 0
5040 11:35:59.441661 tx_last_pass[1][1][3] = 0
5041 11:35:59.444802 tx_win_center[1][1][4] = 0
5042 11:35:59.448294 tx_first_pass[1][1][4] = 0
5043 11:35:59.448807 tx_last_pass[1][1][4] = 0
5044 11:35:59.451347 tx_win_center[1][1][5] = 0
5045 11:35:59.454898 tx_first_pass[1][1][5] = 0
5046 11:35:59.455357 tx_last_pass[1][1][5] = 0
5047 11:35:59.457958 tx_win_center[1][1][6] = 0
5048 11:35:59.461457 tx_first_pass[1][1][6] = 0
5049 11:35:59.464793 tx_last_pass[1][1][6] = 0
5050 11:35:59.465305 tx_win_center[1][1][7] = 0
5051 11:35:59.468042 tx_first_pass[1][1][7] = 0
5052 11:35:59.471606 tx_last_pass[1][1][7] = 0
5053 11:35:59.475513 tx_win_center[1][1][8] = 0
5054 11:35:59.476009 tx_first_pass[1][1][8] = 0
5055 11:35:59.478643 tx_last_pass[1][1][8] = 0
5056 11:35:59.481588 tx_win_center[1][1][9] = 0
5057 11:35:59.482088 tx_first_pass[1][1][9] = 0
5058 11:35:59.484958 tx_last_pass[1][1][9] = 0
5059 11:35:59.488407 tx_win_center[1][1][10] = 0
5060 11:35:59.491760 tx_first_pass[1][1][10] = 0
5061 11:35:59.492264 tx_last_pass[1][1][10] = 0
5062 11:35:59.495369 tx_win_center[1][1][11] = 0
5063 11:35:59.498257 tx_first_pass[1][1][11] = 0
5064 11:35:59.501076 tx_last_pass[1][1][11] = 0
5065 11:35:59.501500 tx_win_center[1][1][12] = 0
5066 11:35:59.504916 tx_first_pass[1][1][12] = 0
5067 11:35:59.508384 tx_last_pass[1][1][12] = 0
5068 11:35:59.511213 tx_win_center[1][1][13] = 0
5069 11:35:59.511643 tx_first_pass[1][1][13] = 0
5070 11:35:59.514503 tx_last_pass[1][1][13] = 0
5071 11:35:59.517939 tx_win_center[1][1][14] = 0
5072 11:35:59.521364 tx_first_pass[1][1][14] = 0
5073 11:35:59.521804 tx_last_pass[1][1][14] = 0
5074 11:35:59.524928 tx_win_center[1][1][15] = 0
5075 11:35:59.527896 tx_first_pass[1][1][15] = 0
5076 11:35:59.531674 tx_last_pass[1][1][15] = 0
5077 11:35:59.532168 dump params rx window
5078 11:35:59.534823 rx_firspass[0][0][0] = 0
5079 11:35:59.538111 rx_lastpass[0][0][0] = 0
5080 11:35:59.538585 rx_firspass[0][0][1] = 0
5081 11:35:59.541411 rx_lastpass[0][0][1] = 0
5082 11:35:59.544617 rx_firspass[0][0][2] = 0
5083 11:35:59.545486 rx_lastpass[0][0][2] = 0
5084 11:35:59.548016 rx_firspass[0][0][3] = 0
5085 11:35:59.551178 rx_lastpass[0][0][3] = 0
5086 11:35:59.551887 rx_firspass[0][0][4] = 0
5087 11:35:59.554514 rx_lastpass[0][0][4] = 0
5088 11:35:59.557839 rx_firspass[0][0][5] = 0
5089 11:35:59.558219 rx_lastpass[0][0][5] = 0
5090 11:35:59.561228 rx_firspass[0][0][6] = 0
5091 11:35:59.564272 rx_lastpass[0][0][6] = 0
5092 11:35:59.567539 rx_firspass[0][0][7] = 0
5093 11:35:59.567940 rx_lastpass[0][0][7] = 0
5094 11:35:59.570754 rx_firspass[0][0][8] = 0
5095 11:35:59.574357 rx_lastpass[0][0][8] = 0
5096 11:35:59.574949 rx_firspass[0][0][9] = 0
5097 11:35:59.577742 rx_lastpass[0][0][9] = 0
5098 11:35:59.580905 rx_firspass[0][0][10] = 0
5099 11:35:59.581291 rx_lastpass[0][0][10] = 0
5100 11:35:59.584117 rx_firspass[0][0][11] = 0
5101 11:35:59.587431 rx_lastpass[0][0][11] = 0
5102 11:35:59.591005 rx_firspass[0][0][12] = 0
5103 11:35:59.591388 rx_lastpass[0][0][12] = 0
5104 11:35:59.594467 rx_firspass[0][0][13] = 0
5105 11:35:59.597388 rx_lastpass[0][0][13] = 0
5106 11:35:59.597774 rx_firspass[0][0][14] = 0
5107 11:35:59.601060 rx_lastpass[0][0][14] = 0
5108 11:35:59.604272 rx_firspass[0][0][15] = 0
5109 11:35:59.607838 rx_lastpass[0][0][15] = 0
5110 11:35:59.608296 rx_firspass[0][1][0] = 0
5111 11:35:59.611532 rx_lastpass[0][1][0] = 0
5112 11:35:59.614230 rx_firspass[0][1][1] = 0
5113 11:35:59.614614 rx_lastpass[0][1][1] = 0
5114 11:35:59.617563 rx_firspass[0][1][2] = 0
5115 11:35:59.621171 rx_lastpass[0][1][2] = 0
5116 11:35:59.621554 rx_firspass[0][1][3] = 0
5117 11:35:59.624802 rx_lastpass[0][1][3] = 0
5118 11:35:59.627946 rx_firspass[0][1][4] = 0
5119 11:35:59.628516 rx_lastpass[0][1][4] = 0
5120 11:35:59.631490 rx_firspass[0][1][5] = 0
5121 11:35:59.634475 rx_lastpass[0][1][5] = 0
5122 11:35:59.634830 rx_firspass[0][1][6] = 0
5123 11:35:59.637764 rx_lastpass[0][1][6] = 0
5124 11:35:59.641710 rx_firspass[0][1][7] = 0
5125 11:35:59.642179 rx_lastpass[0][1][7] = 0
5126 11:35:59.644243 rx_firspass[0][1][8] = 0
5127 11:35:59.647759 rx_lastpass[0][1][8] = 0
5128 11:35:59.648221 rx_firspass[0][1][9] = 0
5129 11:35:59.651397 rx_lastpass[0][1][9] = 0
5130 11:35:59.654495 rx_firspass[0][1][10] = 0
5131 11:35:59.657912 rx_lastpass[0][1][10] = 0
5132 11:35:59.658306 rx_firspass[0][1][11] = 0
5133 11:35:59.661170 rx_lastpass[0][1][11] = 0
5134 11:35:59.664667 rx_firspass[0][1][12] = 0
5135 11:35:59.665132 rx_lastpass[0][1][12] = 0
5136 11:35:59.667527 rx_firspass[0][1][13] = 0
5137 11:35:59.671323 rx_lastpass[0][1][13] = 0
5138 11:35:59.674633 rx_firspass[0][1][14] = 0
5139 11:35:59.675095 rx_lastpass[0][1][14] = 0
5140 11:35:59.677971 rx_firspass[0][1][15] = 0
5141 11:35:59.681034 rx_lastpass[0][1][15] = 0
5142 11:35:59.681491 rx_firspass[1][0][0] = 0
5143 11:35:59.684643 rx_lastpass[1][0][0] = 0
5144 11:35:59.687820 rx_firspass[1][0][1] = 0
5145 11:35:59.688299 rx_lastpass[1][0][1] = 0
5146 11:35:59.690892 rx_firspass[1][0][2] = 0
5147 11:35:59.694380 rx_lastpass[1][0][2] = 0
5148 11:35:59.697524 rx_firspass[1][0][3] = 0
5149 11:35:59.697915 rx_lastpass[1][0][3] = 0
5150 11:35:59.700743 rx_firspass[1][0][4] = 0
5151 11:35:59.704653 rx_lastpass[1][0][4] = 0
5152 11:35:59.705083 rx_firspass[1][0][5] = 0
5153 11:35:59.707902 rx_lastpass[1][0][5] = 0
5154 11:35:59.711080 rx_firspass[1][0][6] = 0
5155 11:35:59.711543 rx_lastpass[1][0][6] = 0
5156 11:35:59.714470 rx_firspass[1][0][7] = 0
5157 11:35:59.717684 rx_lastpass[1][0][7] = 0
5158 11:35:59.718159 rx_firspass[1][0][8] = 0
5159 11:35:59.721103 rx_lastpass[1][0][8] = 0
5160 11:35:59.724429 rx_firspass[1][0][9] = 0
5161 11:35:59.724857 rx_lastpass[1][0][9] = 0
5162 11:35:59.728218 rx_firspass[1][0][10] = 0
5163 11:35:59.731432 rx_lastpass[1][0][10] = 0
5164 11:35:59.734331 rx_firspass[1][0][11] = 0
5165 11:35:59.734785 rx_lastpass[1][0][11] = 0
5166 11:35:59.738105 rx_firspass[1][0][12] = 0
5167 11:35:59.740967 rx_lastpass[1][0][12] = 0
5168 11:35:59.741354 rx_firspass[1][0][13] = 0
5169 11:35:59.744499 rx_lastpass[1][0][13] = 0
5170 11:35:59.747859 rx_firspass[1][0][14] = 0
5171 11:35:59.751171 rx_lastpass[1][0][14] = 0
5172 11:35:59.751629 rx_firspass[1][0][15] = 0
5173 11:35:59.754246 rx_lastpass[1][0][15] = 0
5174 11:35:59.757941 rx_firspass[1][1][0] = 0
5175 11:35:59.758412 rx_lastpass[1][1][0] = 0
5176 11:35:59.760908 rx_firspass[1][1][1] = 0
5177 11:35:59.764119 rx_lastpass[1][1][1] = 0
5178 11:35:59.764609 rx_firspass[1][1][2] = 0
5179 11:35:59.767270 rx_lastpass[1][1][2] = 0
5180 11:35:59.770905 rx_firspass[1][1][3] = 0
5181 11:35:59.774145 rx_lastpass[1][1][3] = 0
5182 11:35:59.774534 rx_firspass[1][1][4] = 0
5183 11:35:59.777551 rx_lastpass[1][1][4] = 0
5184 11:35:59.781069 rx_firspass[1][1][5] = 0
5185 11:35:59.781457 rx_lastpass[1][1][5] = 0
5186 11:35:59.784278 rx_firspass[1][1][6] = 0
5187 11:35:59.787604 rx_lastpass[1][1][6] = 0
5188 11:35:59.788059 rx_firspass[1][1][7] = 0
5189 11:35:59.790788 rx_lastpass[1][1][7] = 0
5190 11:35:59.794373 rx_firspass[1][1][8] = 0
5191 11:35:59.794833 rx_lastpass[1][1][8] = 0
5192 11:35:59.798111 rx_firspass[1][1][9] = 0
5193 11:35:59.800856 rx_lastpass[1][1][9] = 0
5194 11:35:59.801240 rx_firspass[1][1][10] = 0
5195 11:35:59.804338 rx_lastpass[1][1][10] = 0
5196 11:35:59.807895 rx_firspass[1][1][11] = 0
5197 11:35:59.811094 rx_lastpass[1][1][11] = 0
5198 11:35:59.811554 rx_firspass[1][1][12] = 0
5199 11:35:59.814088 rx_lastpass[1][1][12] = 0
5200 11:35:59.817323 rx_firspass[1][1][13] = 0
5201 11:35:59.817706 rx_lastpass[1][1][13] = 0
5202 11:35:59.820490 rx_firspass[1][1][14] = 0
5203 11:35:59.824059 rx_lastpass[1][1][14] = 0
5204 11:35:59.827240 rx_firspass[1][1][15] = 0
5205 11:35:59.827626 rx_lastpass[1][1][15] = 0
5206 11:35:59.830956 dump params clk_delay
5207 11:35:59.831414 clk_delay[0] = 0
5208 11:35:59.834046 clk_delay[1] = 0
5209 11:35:59.834507 dump params dqs_delay
5210 11:35:59.837750 dqs_delay[0][0] = 0
5211 11:35:59.841356 dqs_delay[0][1] = 0
5212 11:35:59.841815 dqs_delay[1][0] = 0
5213 11:35:59.844265 dqs_delay[1][1] = 0
5214 11:35:59.847325 dump params delay_cell_unit = 735
5215 11:35:59.847800 mt_set_emi_preloader end
5216 11:35:59.854233 [mt_mem_init] dram size: 0x100000000, rank number: 2
5217 11:35:59.857611 [complex_mem_test] start addr:0x40000000, len:20480
5218 11:35:59.893910 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5219 11:35:59.900387 [complex_mem_test] start addr:0x80000000, len:20480
5220 11:35:59.936566 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5221 11:35:59.943203 [complex_mem_test] start addr:0xc0000000, len:20480
5222 11:35:59.978654 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5223 11:35:59.985070 [complex_mem_test] start addr:0x56000000, len:8192
5224 11:36:00.002250 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5225 11:36:00.002755 ddr_geometry:1
5226 11:36:00.008615 [complex_mem_test] start addr:0x80000000, len:8192
5227 11:36:00.025516 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5228 11:36:00.029102 dram_init: dram init end (result: 0)
5229 11:36:00.036061 Successfully loaded DRAM blobs and ran DRAM calibration
5230 11:36:00.045869 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5231 11:36:00.046416 CBMEM:
5232 11:36:00.049073 IMD: root @ 00000000fffff000 254 entries.
5233 11:36:00.051994 IMD: root @ 00000000ffffec00 62 entries.
5234 11:36:00.059079 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5235 11:36:00.065667 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5236 11:36:00.068807 in-header: 03 a1 00 00 08 00 00 00
5237 11:36:00.072583 in-data: 84 60 60 10 00 00 00 00
5238 11:36:00.075744 Chrome EC: clear events_b mask to 0x0000000020004000
5239 11:36:00.082999 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5240 11:36:00.085884 in-header: 03 fd 00 00 00 00 00 00
5241 11:36:00.086327 in-data:
5242 11:36:00.092557 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5243 11:36:00.092953 CBFS @ 21000 size 3d4000
5244 11:36:00.099516 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5245 11:36:00.102626 CBFS: Locating 'fallback/ramstage'
5246 11:36:00.106128 CBFS: Found @ offset 10d40 size d563
5247 11:36:00.127566 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5248 11:36:00.139985 Accumulated console time in romstage 13602 ms
5249 11:36:00.140513
5250 11:36:00.140853
5251 11:36:00.150179 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5252 11:36:00.152940 ARM64: Exception handlers installed.
5253 11:36:00.153437 ARM64: Testing exception
5254 11:36:00.156144 ARM64: Done test exception
5255 11:36:00.159877 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5256 11:36:00.162984 Manufacturer: ef
5257 11:36:00.166622 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5258 11:36:00.172917 WARNING: RO_VPD is uninitialized or empty.
5259 11:36:00.176139 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5260 11:36:00.179499 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5261 11:36:00.189540 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5262 11:36:00.192677 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5263 11:36:00.198888 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5264 11:36:00.199269 Enumerating buses...
5265 11:36:00.206176 Show all devs... Before device enumeration.
5266 11:36:00.206685 Root Device: enabled 1
5267 11:36:00.209383 CPU_CLUSTER: 0: enabled 1
5268 11:36:00.209764 CPU: 00: enabled 1
5269 11:36:00.212476 Compare with tree...
5270 11:36:00.215918 Root Device: enabled 1
5271 11:36:00.216299 CPU_CLUSTER: 0: enabled 1
5272 11:36:00.219100 CPU: 00: enabled 1
5273 11:36:00.222818 Root Device scanning...
5274 11:36:00.223403 root_dev_scan_bus for Root Device
5275 11:36:00.225707 CPU_CLUSTER: 0 enabled
5276 11:36:00.229545 root_dev_scan_bus for Root Device done
5277 11:36:00.236129 scan_bus: scanning of bus Root Device took 10689 usecs
5278 11:36:00.236615 done
5279 11:36:00.239018 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5280 11:36:00.242530 Allocating resources...
5281 11:36:00.242968 Reading resources...
5282 11:36:00.245945 Root Device read_resources bus 0 link: 0
5283 11:36:00.252377 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5284 11:36:00.252868 CPU: 00 missing read_resources
5285 11:36:00.259044 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5286 11:36:00.262140 Root Device read_resources bus 0 link: 0 done
5287 11:36:00.266081 Done reading resources.
5288 11:36:00.268667 Show resources in subtree (Root Device)...After reading.
5289 11:36:00.272440 Root Device child on link 0 CPU_CLUSTER: 0
5290 11:36:00.275672 CPU_CLUSTER: 0 child on link 0 CPU: 00
5291 11:36:00.285875 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5292 11:36:00.286320 CPU: 00
5293 11:36:00.288704 Setting resources...
5294 11:36:00.292275 Root Device assign_resources, bus 0 link: 0
5295 11:36:00.295754 CPU_CLUSTER: 0 missing set_resources
5296 11:36:00.299016 Root Device assign_resources, bus 0 link: 0
5297 11:36:00.302646 Done setting resources.
5298 11:36:00.309135 Show resources in subtree (Root Device)...After assigning values.
5299 11:36:00.312191 Root Device child on link 0 CPU_CLUSTER: 0
5300 11:36:00.315901 CPU_CLUSTER: 0 child on link 0 CPU: 00
5301 11:36:00.325508 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5302 11:36:00.325998 CPU: 00
5303 11:36:00.329248 Done allocating resources.
5304 11:36:00.332072 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5305 11:36:00.335562 Enabling resources...
5306 11:36:00.335982 done.
5307 11:36:00.338844 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5308 11:36:00.342678 Initializing devices...
5309 11:36:00.343168 Root Device init ...
5310 11:36:00.345329 mainboard_init: Starting display init.
5311 11:36:00.348701 ADC[4]: Raw value=76102 ID=0
5312 11:36:00.371864 anx7625_power_on_init: Init interface.
5313 11:36:00.376020 anx7625_disable_pd_protocol: Disabled PD feature.
5314 11:36:00.382492 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5315 11:36:00.429185 anx7625_start_dp_work: Secure OCM version=00
5316 11:36:00.432187 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5317 11:36:00.449367 sp_tx_get_edid_block: EDID Block = 1
5318 11:36:00.566761 Extracted contents:
5319 11:36:00.569804 header: 00 ff ff ff ff ff ff 00
5320 11:36:00.573437 serial number: 06 af 5c 14 00 00 00 00 00 1a
5321 11:36:00.576429 version: 01 04
5322 11:36:00.580026 basic params: 95 1a 0e 78 02
5323 11:36:00.583161 chroma info: 99 85 95 55 56 92 28 22 50 54
5324 11:36:00.586730 established: 00 00 00
5325 11:36:00.592829 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5326 11:36:00.596134 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5327 11:36:00.603010 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5328 11:36:00.609310 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5329 11:36:00.615911 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5330 11:36:00.619253 extensions: 00
5331 11:36:00.619724 checksum: ae
5332 11:36:00.620031
5333 11:36:00.622474 Manufacturer: AUO Model 145c Serial Number 0
5334 11:36:00.625778 Made week 0 of 2016
5335 11:36:00.626269 EDID version: 1.4
5336 11:36:00.629402 Digital display
5337 11:36:00.632226 6 bits per primary color channel
5338 11:36:00.632741 DisplayPort interface
5339 11:36:00.635764 Maximum image size: 26 cm x 14 cm
5340 11:36:00.639122 Gamma: 220%
5341 11:36:00.639660 Check DPMS levels
5342 11:36:00.642788 Supported color formats: RGB 4:4:4
5343 11:36:00.645713 First detailed timing is preferred timing
5344 11:36:00.648832 Established timings supported:
5345 11:36:00.652348 Standard timings supported:
5346 11:36:00.652812 Detailed timings
5347 11:36:00.658818 Hex of detail: ce1d56ea50001a3030204600009010000018
5348 11:36:00.662342 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5349 11:36:00.665496 0556 0586 05a6 0640 hborder 0
5350 11:36:00.671763 0300 0304 030a 031a vborder 0
5351 11:36:00.672335 -hsync -vsync
5352 11:36:00.675471 Did detailed timing
5353 11:36:00.678581 Hex of detail: 0000000f0000000000000000000000000020
5354 11:36:00.682400 Manufacturer-specified data, tag 15
5355 11:36:00.688759 Hex of detail: 000000fe0041554f0a202020202020202020
5356 11:36:00.689215 ASCII string: AUO
5357 11:36:00.695045 Hex of detail: 000000fe004231313658414230312e34200a
5358 11:36:00.695555 ASCII string: B116XAB01.4
5359 11:36:00.698528 Checksum
5360 11:36:00.698908 Checksum: 0xae (valid)
5361 11:36:00.705432 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5362 11:36:00.708641 DSI data_rate: 457800000 bps
5363 11:36:00.711926 anx7625_parse_edid: set default k value to 0x3d for panel
5364 11:36:00.718316 anx7625_parse_edid: pixelclock(76300).
5365 11:36:00.721615 hactive(1366), hsync(32), hfp(48), hbp(154)
5366 11:36:00.724945 vactive(768), vsync(6), vfp(4), vbp(16)
5367 11:36:00.728052 anx7625_dsi_config: config dsi.
5368 11:36:00.734803 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5369 11:36:00.756084 anx7625_dsi_config: success to config DSI
5370 11:36:00.758827 anx7625_dp_start: MIPI phy setup OK.
5371 11:36:00.763216 [SSUSB] Setting up USB HOST controller...
5372 11:36:00.765661 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5373 11:36:00.769216 [SSUSB] phy power-on done.
5374 11:36:00.773055 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5375 11:36:00.776280 in-header: 03 fc 01 00 00 00 00 00
5376 11:36:00.776746 in-data:
5377 11:36:00.779880 handle_proto3_response: EC response with error code: 1
5378 11:36:00.783069 SPM: pcm index = 1
5379 11:36:00.786134 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5380 11:36:00.789604 CBFS @ 21000 size 3d4000
5381 11:36:00.796290 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5382 11:36:00.799503 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5383 11:36:00.802560 CBFS: Found @ offset 1e7c0 size 1026
5384 11:36:00.809169 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5385 11:36:00.813085 SPM: binary array size = 2988
5386 11:36:00.816296 SPM: version = pcm_allinone_v1.17.2_20180829
5387 11:36:00.819547 SPM binary loaded in 32 msecs
5388 11:36:00.827211 spm_kick_im_to_fetch: ptr = 000000004021eec2
5389 11:36:00.830157 spm_kick_im_to_fetch: len = 2988
5390 11:36:00.830547 SPM: spm_kick_pcm_to_run
5391 11:36:00.833388 SPM: spm_kick_pcm_to_run done
5392 11:36:00.836920 SPM: spm_init done in 52 msecs
5393 11:36:00.839711 Root Device init finished in 494989 usecs
5394 11:36:00.843590 CPU_CLUSTER: 0 init ...
5395 11:36:00.853279 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5396 11:36:00.857115 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5397 11:36:00.860196 CBFS @ 21000 size 3d4000
5398 11:36:00.863276 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5399 11:36:00.866700 CBFS: Locating 'sspm.bin'
5400 11:36:00.870051 CBFS: Found @ offset 208c0 size 41cb
5401 11:36:00.880080 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5402 11:36:00.887578 CPU_CLUSTER: 0 init finished in 42799 usecs
5403 11:36:00.888059 Devices initialized
5404 11:36:00.891105 Show all devs... After init.
5405 11:36:00.894990 Root Device: enabled 1
5406 11:36:00.895450 CPU_CLUSTER: 0: enabled 1
5407 11:36:00.898040 CPU: 00: enabled 1
5408 11:36:00.901307 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5409 11:36:00.904631 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5410 11:36:00.907950 ELOG: NV offset 0x558000 size 0x1000
5411 11:36:00.915545 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5412 11:36:00.922625 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5413 11:36:00.925419 ELOG: Event(17) added with size 13 at 2024-07-17 11:35:51 UTC
5414 11:36:00.928768 out: cmd=0x121: 03 db 21 01 00 00 00 00
5415 11:36:00.931945 in-header: 03 c1 00 00 2c 00 00 00
5416 11:36:00.945948 in-data: 63 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 1a 31 08 00 06 80 00 00 ed 0c 31 00 06 80 00 00 ae 44 01 00 06 80 00 00 81 45 02 00
5417 11:36:00.949096 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5418 11:36:00.952074 in-header: 03 19 00 00 08 00 00 00
5419 11:36:00.955581 in-data: a2 e0 47 00 13 00 00 00
5420 11:36:00.959225 Chrome EC: UHEPI supported
5421 11:36:00.965569 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5422 11:36:00.969275 in-header: 03 e1 00 00 08 00 00 00
5423 11:36:00.971867 in-data: 84 20 60 10 00 00 00 00
5424 11:36:00.975430 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5425 11:36:00.982239 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5426 11:36:00.985221 in-header: 03 e1 00 00 08 00 00 00
5427 11:36:00.988730 in-data: 84 20 60 10 00 00 00 00
5428 11:36:00.995034 ELOG: Event(A1) added with size 10 at 2024-07-17 11:35:51 UTC
5429 11:36:01.002165 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5430 11:36:01.005034 ELOG: Event(A0) added with size 9 at 2024-07-17 11:35:51 UTC
5431 11:36:01.011929 elog_add_boot_reason: Logged dev mode boot
5432 11:36:01.012314 Finalize devices...
5433 11:36:01.015509 Devices finalized
5434 11:36:01.018605 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5435 11:36:01.022044 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5436 11:36:01.028356 ELOG: Event(91) added with size 10 at 2024-07-17 11:35:51 UTC
5437 11:36:01.032150 Writing coreboot table at 0xffeda000
5438 11:36:01.035300 0. 0000000000114000-000000000011efff: RAMSTAGE
5439 11:36:01.041533 1. 0000000040000000-000000004023cfff: RAMSTAGE
5440 11:36:01.044831 2. 000000004023d000-00000000545fffff: RAM
5441 11:36:01.048277 3. 0000000054600000-000000005465ffff: BL31
5442 11:36:01.051545 4. 0000000054660000-00000000ffed9fff: RAM
5443 11:36:01.058428 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5444 11:36:01.061509 6. 0000000100000000-000000013fffffff: RAM
5445 11:36:01.064687 Passing 5 GPIOs to payload:
5446 11:36:01.068533 NAME | PORT | POLARITY | VALUE
5447 11:36:01.071414 write protect | 0x00000096 | low | high
5448 11:36:01.078226 EC in RW | 0x000000b1 | high | undefined
5449 11:36:01.081665 EC interrupt | 0x00000097 | low | undefined
5450 11:36:01.088712 TPM interrupt | 0x00000099 | high | undefined
5451 11:36:01.091489 speaker enable | 0x000000af | high | undefined
5452 11:36:01.094849 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5453 11:36:01.098214 in-header: 03 f7 00 00 02 00 00 00
5454 11:36:01.098599 in-data: 04 00
5455 11:36:01.101728 Board ID: 4
5456 11:36:01.105168 ADC[3]: Raw value=215504 ID=1
5457 11:36:01.105625 RAM code: 1
5458 11:36:01.105926 SKU ID: 16
5459 11:36:01.111812 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5460 11:36:01.112274 CBFS @ 21000 size 3d4000
5461 11:36:01.118183 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5462 11:36:01.125190 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum beee
5463 11:36:01.125585 coreboot table: 940 bytes.
5464 11:36:01.131256 IMD ROOT 0. 00000000fffff000 00001000
5465 11:36:01.134274 IMD SMALL 1. 00000000ffffe000 00001000
5466 11:36:01.137901 CONSOLE 2. 00000000fffde000 00020000
5467 11:36:01.141122 FMAP 3. 00000000fffdd000 0000047c
5468 11:36:01.144714 TIME STAMP 4. 00000000fffdc000 00000910
5469 11:36:01.148028 RAMOOPS 5. 00000000ffedc000 00100000
5470 11:36:01.151005 COREBOOT 6. 00000000ffeda000 00002000
5471 11:36:01.154459 IMD small region:
5472 11:36:01.157835 IMD ROOT 0. 00000000ffffec00 00000400
5473 11:36:01.161195 VBOOT WORK 1. 00000000ffffeb00 00000100
5474 11:36:01.164432 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5475 11:36:01.167664 VPD 3. 00000000ffffea60 0000006c
5476 11:36:01.174237 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5477 11:36:01.181361 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5478 11:36:01.184142 in-header: 03 e1 00 00 08 00 00 00
5479 11:36:01.187689 in-data: 84 20 60 10 00 00 00 00
5480 11:36:01.190961 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5481 11:36:01.194674 CBFS @ 21000 size 3d4000
5482 11:36:01.197706 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5483 11:36:01.200827 CBFS: Locating 'fallback/payload'
5484 11:36:01.208990 CBFS: Found @ offset dc040 size 439a0
5485 11:36:01.297679 read SPI 0xfd078 0x439a0: 84380 us, 3281 KB/s, 26.248 Mbps
5486 11:36:01.301260 Checking segment from ROM address 0x0000000040003a00
5487 11:36:01.307607 Checking segment from ROM address 0x0000000040003a1c
5488 11:36:01.311098 Loading segment from ROM address 0x0000000040003a00
5489 11:36:01.314453 code (compression=0)
5490 11:36:01.321228 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5491 11:36:01.330583 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5492 11:36:01.333926 it's not compressed!
5493 11:36:01.337226 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5494 11:36:01.344031 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5495 11:36:01.351584 Loading segment from ROM address 0x0000000040003a1c
5496 11:36:01.354604 Entry Point 0x0000000080000000
5497 11:36:01.355096 Loaded segments
5498 11:36:01.361837 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5499 11:36:01.364939 Jumping to boot code at 0000000080000000(00000000ffeda000)
5500 11:36:01.374900 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5501 11:36:01.378205 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5502 11:36:01.381362 CBFS @ 21000 size 3d4000
5503 11:36:01.388000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5504 11:36:01.390869 CBFS: Locating 'fallback/bl31'
5505 11:36:01.394600 CBFS: Found @ offset 36dc0 size 5820
5506 11:36:01.405394 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5507 11:36:01.408490 Checking segment from ROM address 0x0000000040003a00
5508 11:36:01.415256 Checking segment from ROM address 0x0000000040003a1c
5509 11:36:01.418731 Loading segment from ROM address 0x0000000040003a00
5510 11:36:01.422002 code (compression=1)
5511 11:36:01.429039 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5512 11:36:01.438747 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5513 11:36:01.439227 using LZMA
5514 11:36:01.447213 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5515 11:36:01.454033 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5516 11:36:01.457070 Loading segment from ROM address 0x0000000040003a1c
5517 11:36:01.460352 Entry Point 0x0000000054601000
5518 11:36:01.460548 Loaded segments
5519 11:36:01.463687 NOTICE: MT8183 bl31_setup
5520 11:36:01.470649 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5521 11:36:01.474224 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5522 11:36:01.477312 INFO: [DEVAPC] dump DEVAPC registers:
5523 11:36:01.487210 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5524 11:36:01.493873 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5525 11:36:01.501029 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5526 11:36:01.511059 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5527 11:36:01.517533 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5528 11:36:01.527794 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5529 11:36:01.534383 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5530 11:36:01.544427 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5531 11:36:01.550963 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5532 11:36:01.561182 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5533 11:36:01.567870 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5534 11:36:01.578134 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5535 11:36:01.584639 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5536 11:36:01.591198 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5537 11:36:01.601093 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5538 11:36:01.607684 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5539 11:36:01.614369 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5540 11:36:01.621314 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5541 11:36:01.627633 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5542 11:36:01.637102 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5543 11:36:01.643842 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5544 11:36:01.650492 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5545 11:36:01.653891 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5546 11:36:01.656928 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5547 11:36:01.660674 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5548 11:36:01.663775 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5549 11:36:01.667027 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5550 11:36:01.673513 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5551 11:36:01.677436 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5552 11:36:01.680379 WARNING: region 0:
5553 11:36:01.683897 WARNING: apc:0x168, sa:0x0, ea:0xfff
5554 11:36:01.683983 WARNING: region 1:
5555 11:36:01.690161 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5556 11:36:01.690246 WARNING: region 2:
5557 11:36:01.693527 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5558 11:36:01.697092 WARNING: region 3:
5559 11:36:01.700300 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5560 11:36:01.700422 WARNING: region 4:
5561 11:36:01.703498 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5562 11:36:01.706860 WARNING: region 5:
5563 11:36:01.710292 WARNING: apc:0x0, sa:0x0, ea:0x0
5564 11:36:01.710412 WARNING: region 6:
5565 11:36:01.713456 WARNING: apc:0x0, sa:0x0, ea:0x0
5566 11:36:01.716905 WARNING: region 7:
5567 11:36:01.720540 WARNING: apc:0x0, sa:0x0, ea:0x0
5568 11:36:01.726956 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5569 11:36:01.730131 INFO: SPM: enable SPMC mode
5570 11:36:01.733365 NOTICE: spm_boot_init() start
5571 11:36:01.733616 NOTICE: spm_boot_init() end
5572 11:36:01.739904 INFO: BL31: Initializing runtime services
5573 11:36:01.743603 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5574 11:36:01.750360 INFO: BL31: Preparing for EL3 exit to normal world
5575 11:36:01.753694 INFO: Entry point address = 0x80000000
5576 11:36:01.753967 INFO: SPSR = 0x8
5577 11:36:01.777461
5578 11:36:01.777708
5579 11:36:01.777872
5580 11:36:01.778859 end: 2.2.3 depthcharge-start (duration 00:00:24) [common]
5581 11:36:01.779179 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5582 11:36:01.779458 Setting prompt string to ['jacuzzi:']
5583 11:36:01.779654 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5584 11:36:01.780646 Starting depthcharge on Juniper...
5585 11:36:01.780850
5586 11:36:01.783873 vboot_handoff: creating legacy vboot_handoff structure
5587 11:36:01.784661
5588 11:36:01.787553 ec_init(0): CrosEC protocol v3 supported (544, 544)
5589 11:36:01.788119
5590 11:36:01.790773 Wipe memory regions:
5591 11:36:01.791155
5592 11:36:01.794041 [0x00000040000000, 0x00000054600000)
5593 11:36:01.836931
5594 11:36:01.837316 [0x00000054660000, 0x00000080000000)
5595 11:36:01.927872
5596 11:36:01.927998 [0x000000811994a0, 0x000000ffeda000)
5597 11:36:02.188079
5598 11:36:02.188725 [0x00000100000000, 0x00000140000000)
5599 11:36:02.319750
5600 11:36:02.322873 Initializing XHCI USB controller at 0x11200000.
5601 11:36:02.345877
5602 11:36:02.348937 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5603 11:36:02.349067
5604 11:36:02.349173
5605 11:36:02.349491 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5606 11:36:02.349589 Sending line: 'tftpboot 192.168.201.1 14864624/tftp-deploy-9eym88c1/kernel/image.itb 14864624/tftp-deploy-9eym88c1/kernel/cmdline '
5608 11:36:02.450813 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5609 11:36:02.451405 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5610 11:36:02.455418 jacuzzi: tftpboot 192.168.201.1 14864624/tftp-deploy-9eym88c1/kernel/image.ittp-deploy-9eym88c1/kernel/cmdline
5611 11:36:02.455933
5612 11:36:02.456400 Waiting for link
5613 11:36:02.859350
5614 11:36:02.859595 R8152: Initializing
5615 11:36:02.859783
5616 11:36:02.862959 Version 9 (ocp_data = 6010)
5617 11:36:02.863164
5618 11:36:02.866255 R8152: Done initializing
5619 11:36:02.866437
5620 11:36:02.866618 Adding net device
5621 11:36:03.252413
5622 11:36:03.252980 done.
5623 11:36:03.253603
5624 11:36:03.254254 MAC: 00:e0:4c:68:0b:b9
5625 11:36:03.254873
5626 11:36:03.255618 Sending DHCP discover... done.
5627 11:36:03.255959
5628 11:36:03.258981 Waiting for reply... done.
5629 11:36:03.259480
5630 11:36:03.261828 Sending DHCP request... done.
5631 11:36:03.261980
5632 11:36:03.266419 Waiting for reply... done.
5633 11:36:03.266651
5634 11:36:03.266788 My ip is 192.168.201.13
5635 11:36:03.266912
5636 11:36:03.269991 The DHCP server ip is 192.168.201.1
5637 11:36:03.270298
5638 11:36:03.276927 TFTP server IP predefined by user: 192.168.201.1
5639 11:36:03.277304
5640 11:36:03.283180 Bootfile predefined by user: 14864624/tftp-deploy-9eym88c1/kernel/image.itb
5641 11:36:03.283647
5642 11:36:03.285868 Sending tftp read request... done.
5643 11:36:03.286258
5644 11:36:03.293483 Waiting for the transfer...
5645 11:36:03.293907
5646 11:36:03.592782 00000000 ################################################################
5647 11:36:03.592912
5648 11:36:03.880164 00080000 ################################################################
5649 11:36:03.880296
5650 11:36:04.142675 00100000 ################################################################
5651 11:36:04.142805
5652 11:36:04.416544 00180000 ################################################################
5653 11:36:04.416668
5654 11:36:04.716046 00200000 ################################################################
5655 11:36:04.716171
5656 11:36:05.005135 00280000 ################################################################
5657 11:36:05.005255
5658 11:36:05.287126 00300000 ################################################################
5659 11:36:05.287252
5660 11:36:05.565098 00380000 ################################################################
5661 11:36:05.565220
5662 11:36:05.854990 00400000 ################################################################
5663 11:36:05.855113
5664 11:36:06.121985 00480000 ################################################################
5665 11:36:06.122110
5666 11:36:06.394384 00500000 ################################################################
5667 11:36:06.394515
5668 11:36:06.673895 00580000 ################################################################
5669 11:36:06.674017
5670 11:36:06.964080 00600000 ################################################################
5671 11:36:06.964209
5672 11:36:07.227021 00680000 ################################################################
5673 11:36:07.227169
5674 11:36:07.514130 00700000 ################################################################
5675 11:36:07.514262
5676 11:36:07.811062 00780000 ################################################################
5677 11:36:07.811198
5678 11:36:08.085471 00800000 ################################################################
5679 11:36:08.085610
5680 11:36:08.385096 00880000 ################################################################
5681 11:36:08.385221
5682 11:36:08.683134 00900000 ################################################################
5683 11:36:08.683266
5684 11:36:08.981728 00980000 ################################################################
5685 11:36:08.981849
5686 11:36:09.276522 00a00000 ################################################################
5687 11:36:09.276653
5688 11:36:09.575675 00a80000 ################################################################
5689 11:36:09.575805
5690 11:36:09.874723 00b00000 ################################################################
5691 11:36:09.874853
5692 11:36:10.169122 00b80000 ################################################################
5693 11:36:10.169255
5694 11:36:10.470574 00c00000 ################################################################
5695 11:36:10.470695
5696 11:36:10.747618 00c80000 ################################################################
5697 11:36:10.747750
5698 11:36:11.026469 00d00000 ################################################################
5699 11:36:11.026595
5700 11:36:11.301547 00d80000 ################################################################
5701 11:36:11.301675
5702 11:36:11.591799 00e00000 ################################################################
5703 11:36:11.591928
5704 11:36:11.881645 00e80000 ################################################################
5705 11:36:11.881776
5706 11:36:12.148612 00f00000 ################################################################
5707 11:36:12.148734
5708 11:36:12.442090 00f80000 ################################################################
5709 11:36:12.442225
5710 11:36:12.739845 01000000 ################################################################
5711 11:36:12.739977
5712 11:36:13.017739 01080000 ################################################################
5713 11:36:13.017865
5714 11:36:13.286813 01100000 ################################################################
5715 11:36:13.286952
5716 11:36:13.541802 01180000 ################################################################
5717 11:36:13.541924
5718 11:36:13.843583 01200000 ################################################################
5719 11:36:13.843714
5720 11:36:14.145684 01280000 ################################################################
5721 11:36:14.145805
5722 11:36:14.433266 01300000 ################################################################
5723 11:36:14.433404
5724 11:36:14.726910 01380000 ################################################################
5725 11:36:14.727043
5726 11:36:15.020599 01400000 ################################################################
5727 11:36:15.020735
5728 11:36:15.303436 01480000 ################################################################
5729 11:36:15.303572
5730 11:36:15.561809 01500000 ################################################################
5731 11:36:15.561944
5732 11:36:15.821562 01580000 ################################################################
5733 11:36:15.821698
5734 11:36:16.114799 01600000 ################################################################
5735 11:36:16.114930
5736 11:36:16.387287 01680000 ################################################################
5737 11:36:16.387420
5738 11:36:16.642500 01700000 ################################################################
5739 11:36:16.642640
5740 11:36:16.899402 01780000 ################################################################
5741 11:36:16.899535
5742 11:36:17.198009 01800000 ################################################################
5743 11:36:17.198142
5744 11:36:17.481533 01880000 ################################################################
5745 11:36:17.481668
5746 11:36:17.780643 01900000 ################################################################
5747 11:36:17.780775
5748 11:36:18.080074 01980000 ################################################################
5749 11:36:18.080212
5750 11:36:18.376112 01a00000 ################################################################
5751 11:36:18.376230
5752 11:36:18.647944 01a80000 ################################################################
5753 11:36:18.648078
5754 11:36:18.923158 01b00000 ################################################################
5755 11:36:18.923282
5756 11:36:19.176371 01b80000 ################################################################
5757 11:36:19.176501
5758 11:36:19.431917 01c00000 ################################################################
5759 11:36:19.432046
5760 11:36:19.705860 01c80000 ################################################################
5761 11:36:19.705984
5762 11:36:19.965912 01d00000 ################################################################
5763 11:36:19.966033
5764 11:36:20.236460 01d80000 ################################################################
5765 11:36:20.236581
5766 11:36:20.452782 01e00000 ###################################################### done.
5767 11:36:20.452899
5768 11:36:20.456347 The bootfile was 31896870 bytes long.
5769 11:36:20.459461
5770 11:36:20.459844 Sending tftp read request... done.
5771 11:36:20.460144
5772 11:36:20.466037 Waiting for the transfer...
5773 11:36:20.466491
5774 11:36:20.466791 00000000 # done.
5775 11:36:20.467104
5776 11:36:20.472803 Command line loaded dynamically from TFTP file: 14864624/tftp-deploy-9eym88c1/kernel/cmdline
5777 11:36:20.473219
5778 11:36:20.499247 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5779 11:36:20.499691
5780 11:36:20.499988 Loading FIT.
5781 11:36:20.502916
5782 11:36:20.503321 Image ramdisk-1 has 18718838 bytes.
5783 11:36:20.505751
5784 11:36:20.506134 Image fdt-1 has 57695 bytes.
5785 11:36:20.506431
5786 11:36:20.509201 Image kernel-1 has 13118294 bytes.
5787 11:36:20.509677
5788 11:36:20.519297 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5789 11:36:20.519698
5790 11:36:20.532714 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5791 11:36:20.533205
5792 11:36:20.535672 Choosing best match conf-1 for compat google,juniper-sku16.
5793 11:36:20.540638
5794 11:36:20.544804 Connected to device vid:did:rid of 1ae0:0028:00
5795 11:36:20.552925
5796 11:36:20.556355 tpm_get_response: command 0x17b, return code 0x0
5797 11:36:20.556800
5798 11:36:20.559557 tpm_cleanup: add release locality here.
5799 11:36:20.559969
5800 11:36:20.562875 Shutting down all USB controllers.
5801 11:36:20.563569
5802 11:36:20.566558 Removing current net device
5803 11:36:20.567139
5804 11:36:20.569833 Exiting depthcharge with code 4 at timestamp: 36041491
5805 11:36:20.570453
5806 11:36:20.573449 LZMA decompressing kernel-1 to 0x80193568
5807 11:36:20.573956
5808 11:36:20.576615 LZMA decompressing kernel-1 to 0x40000000
5809 11:36:22.441655
5810 11:36:22.441801 jumping to kernel
5811 11:36:22.442368 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5812 11:36:22.442497 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
5813 11:36:22.442601 Setting prompt string to ['Linux version [0-9]']
5814 11:36:22.442703 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5815 11:36:22.442807 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5816 11:36:22.516197
5817 11:36:22.519781 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5818 11:36:22.523195 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
5819 11:36:22.523319 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5820 11:36:22.523420 Setting prompt string to []
5821 11:36:22.523530 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5822 11:36:22.523616 Using line separator: #'\n'#
5823 11:36:22.523678 No login prompt set.
5824 11:36:22.523759 Parsing kernel messages
5825 11:36:22.523845 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5826 11:36:22.524024 [login-action] Waiting for messages, (timeout 00:04:06)
5827 11:36:22.524121 Waiting using forced prompt support (timeout 00:02:03)
5828 11:36:22.543136 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
5829 11:36:22.546366 [ 0.000000] random: crng init done
5830 11:36:22.549421 [ 0.000000] Machine model: Google juniper sku16 board
5831 11:36:22.553086 [ 0.000000] efi: UEFI not found.
5832 11:36:22.563088 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5833 11:36:22.569880 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5834 11:36:22.576523 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5835 11:36:22.582877 [ 0.000000] printk: bootconsole [mtk8250] enabled
5836 11:36:22.590092 [ 0.000000] NUMA: No NUMA configuration found
5837 11:36:22.597194 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5838 11:36:22.603472 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5839 11:36:22.603575 [ 0.000000] Zone ranges:
5840 11:36:22.610077 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5841 11:36:22.613808 [ 0.000000] DMA32 empty
5842 11:36:22.619958 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5843 11:36:22.623287 [ 0.000000] Movable zone start for each node
5844 11:36:22.626707 [ 0.000000] Early memory node ranges
5845 11:36:22.633596 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5846 11:36:22.640196 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5847 11:36:22.646788 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5848 11:36:22.653508 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5849 11:36:22.660162 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5850 11:36:22.666281 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5851 11:36:22.687092 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5852 11:36:22.693476 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5853 11:36:22.700423 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5854 11:36:22.704021 [ 0.000000] psci: probing for conduit method from DT.
5855 11:36:22.710072 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5856 11:36:22.713532 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5857 11:36:22.720373 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5858 11:36:22.723951 [ 0.000000] psci: SMC Calling Convention v1.1
5859 11:36:22.730169 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5860 11:36:22.733563 [ 0.000000] Detected VIPT I-cache on CPU0
5861 11:36:22.739921 [ 0.000000] CPU features: detected: GIC system register CPU interface
5862 11:36:22.746797 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5863 11:36:22.753235 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5864 11:36:22.760165 [ 0.000000] CPU features: detected: ARM erratum 845719
5865 11:36:22.763392 [ 0.000000] alternatives: applying boot alternatives
5866 11:36:22.766294 [ 0.000000] Fallback order for Node 0: 0
5867 11:36:22.773099 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5868 11:36:22.776689 [ 0.000000] Policy zone: Normal
5869 11:36:22.806582 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5870 11:36:22.816287 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5871 11:36:22.826560 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5872 11:36:22.833062 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5873 11:36:22.839410 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5874 11:36:22.846306 <6>[ 0.000000] software IO TLB: area num 8.
5875 11:36:22.871409 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5876 11:36:22.928813 <6>[ 0.000000] Memory: 3896792K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261672K reserved, 32768K cma-reserved)
5877 11:36:22.935713 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5878 11:36:22.942541 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5879 11:36:22.945382 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5880 11:36:22.952218 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5881 11:36:22.958792 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5882 11:36:22.962343 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5883 11:36:22.972228 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5884 11:36:22.979296 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5885 11:36:22.982743 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5886 11:36:22.994262 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5887 11:36:22.997517 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5888 11:36:23.004321 <6>[ 0.000000] GICv3: 640 SPIs implemented
5889 11:36:23.008110 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5890 11:36:23.011326 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5891 11:36:23.017695 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5892 11:36:23.024935 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5893 11:36:23.034380 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5894 11:36:23.047726 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5895 11:36:23.054484 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5896 11:36:23.066317 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5897 11:36:23.078993 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5898 11:36:23.085967 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5899 11:36:23.092545 <6>[ 0.009463] Console: colour dummy device 80x25
5900 11:36:23.096118 <6>[ 0.014500] printk: console [tty1] enabled
5901 11:36:23.106017 <6>[ 0.018888] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5902 11:36:23.112543 <6>[ 0.029354] pid_max: default: 32768 minimum: 301
5903 11:36:23.115867 <6>[ 0.034235] LSM: Security Framework initializing
5904 11:36:23.125879 <6>[ 0.039151] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5905 11:36:23.132743 <6>[ 0.046774] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5906 11:36:23.138881 <4>[ 0.055650] cacheinfo: Unable to detect cache hierarchy for CPU 0
5907 11:36:23.148894 <6>[ 0.062276] cblist_init_generic: Setting adjustable number of callback queues.
5908 11:36:23.155787 <6>[ 0.069722] cblist_init_generic: Setting shift to 3 and lim to 1.
5909 11:36:23.162062 <6>[ 0.076074] cblist_init_generic: Setting adjustable number of callback queues.
5910 11:36:23.168641 <6>[ 0.083519] cblist_init_generic: Setting shift to 3 and lim to 1.
5911 11:36:23.172512 <6>[ 0.089918] rcu: Hierarchical SRCU implementation.
5912 11:36:23.179101 <6>[ 0.094944] rcu: Max phase no-delay instances is 1000.
5913 11:36:23.186052 <6>[ 0.102851] EFI services will not be available.
5914 11:36:23.189650 <6>[ 0.107801] smp: Bringing up secondary CPUs ...
5915 11:36:23.200076 <6>[ 0.113029] Detected VIPT I-cache on CPU1
5916 11:36:23.206612 <4>[ 0.113076] cacheinfo: Unable to detect cache hierarchy for CPU 1
5917 11:36:23.213191 <6>[ 0.113084] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5918 11:36:23.219783 <6>[ 0.113116] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5919 11:36:23.222936 <6>[ 0.113597] Detected VIPT I-cache on CPU2
5920 11:36:23.230094 <4>[ 0.113629] cacheinfo: Unable to detect cache hierarchy for CPU 2
5921 11:36:23.236622 <6>[ 0.113634] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5922 11:36:23.242931 <6>[ 0.113645] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5923 11:36:23.246882 <6>[ 0.114094] Detected VIPT I-cache on CPU3
5924 11:36:23.253210 <4>[ 0.114124] cacheinfo: Unable to detect cache hierarchy for CPU 3
5925 11:36:23.259906 <6>[ 0.114128] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5926 11:36:23.266887 <6>[ 0.114140] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5927 11:36:23.272860 <6>[ 0.114714] CPU features: detected: Spectre-v2
5928 11:36:23.276492 <6>[ 0.114724] CPU features: detected: Spectre-BHB
5929 11:36:23.283071 <6>[ 0.114728] CPU features: detected: ARM erratum 858921
5930 11:36:23.286632 <6>[ 0.114733] Detected VIPT I-cache on CPU4
5931 11:36:23.293112 <4>[ 0.114781] cacheinfo: Unable to detect cache hierarchy for CPU 4
5932 11:36:23.299466 <6>[ 0.114789] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5933 11:36:23.306043 <6>[ 0.114797] arch_timer: Enabling local workaround for ARM erratum 858921
5934 11:36:23.312490 <6>[ 0.114808] arch_timer: CPU4: Trapping CNTVCT access
5935 11:36:23.319516 <6>[ 0.114815] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5936 11:36:23.322573 <6>[ 0.115301] Detected VIPT I-cache on CPU5
5937 11:36:23.329617 <4>[ 0.115342] cacheinfo: Unable to detect cache hierarchy for CPU 5
5938 11:36:23.335716 <6>[ 0.115347] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5939 11:36:23.342299 <6>[ 0.115354] arch_timer: Enabling local workaround for ARM erratum 858921
5940 11:36:23.349450 <6>[ 0.115360] arch_timer: CPU5: Trapping CNTVCT access
5941 11:36:23.355878 <6>[ 0.115365] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5942 11:36:23.358951 <6>[ 0.115801] Detected VIPT I-cache on CPU6
5943 11:36:23.365910 <4>[ 0.115847] cacheinfo: Unable to detect cache hierarchy for CPU 6
5944 11:36:23.372337 <6>[ 0.115853] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5945 11:36:23.382104 <6>[ 0.115860] arch_timer: Enabling local workaround for ARM erratum 858921
5946 11:36:23.385663 <6>[ 0.115866] arch_timer: CPU6: Trapping CNTVCT access
5947 11:36:23.391913 <6>[ 0.115871] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5948 11:36:23.395547 <6>[ 0.116401] Detected VIPT I-cache on CPU7
5949 11:36:23.401815 <4>[ 0.116445] cacheinfo: Unable to detect cache hierarchy for CPU 7
5950 11:36:23.412030 <6>[ 0.116451] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5951 11:36:23.418558 <6>[ 0.116458] arch_timer: Enabling local workaround for ARM erratum 858921
5952 11:36:23.421834 <6>[ 0.116465] arch_timer: CPU7: Trapping CNTVCT access
5953 11:36:23.428541 <6>[ 0.116470] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5954 11:36:23.435536 <6>[ 0.116517] smp: Brought up 1 node, 8 CPUs
5955 11:36:23.438852 <6>[ 0.355422] SMP: Total of 8 processors activated.
5956 11:36:23.445522 <6>[ 0.360357] CPU features: detected: 32-bit EL0 Support
5957 11:36:23.448320 <6>[ 0.365737] CPU features: detected: 32-bit EL1 Support
5958 11:36:23.455428 <6>[ 0.371105] CPU features: detected: CRC32 instructions
5959 11:36:23.458622 <6>[ 0.376534] CPU: All CPU(s) started at EL2
5960 11:36:23.465237 <6>[ 0.380872] alternatives: applying system-wide alternatives
5961 11:36:23.472450 <6>[ 0.388884] devtmpfs: initialized
5962 11:36:23.484660 <6>[ 0.397853] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5963 11:36:23.494637 <6>[ 0.407801] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5964 11:36:23.497771 <6>[ 0.415525] pinctrl core: initialized pinctrl subsystem
5965 11:36:23.505917 <6>[ 0.422638] DMI not present or invalid.
5966 11:36:23.512505 <6>[ 0.427006] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5967 11:36:23.519208 <6>[ 0.433910] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5968 11:36:23.528874 <6>[ 0.441438] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5969 11:36:23.536277 <6>[ 0.449689] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5970 11:36:23.542420 <6>[ 0.457863] audit: initializing netlink subsys (disabled)
5971 11:36:23.549170 <5>[ 0.463569] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
5972 11:36:23.555984 <6>[ 0.464550] thermal_sys: Registered thermal governor 'step_wise'
5973 11:36:23.562371 <6>[ 0.471535] thermal_sys: Registered thermal governor 'power_allocator'
5974 11:36:23.565567 <6>[ 0.477831] cpuidle: using governor menu
5975 11:36:23.572449 <6>[ 0.488793] NET: Registered PF_QIPCRTR protocol family
5976 11:36:23.579209 <6>[ 0.494289] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5977 11:36:23.586049 <6>[ 0.501388] ASID allocator initialised with 32768 entries
5978 11:36:23.592264 <6>[ 0.508153] Serial: AMBA PL011 UART driver
5979 11:36:23.602970 <4>[ 0.519485] Trying to register duplicate clock ID: 113
5980 11:36:23.662541 <6>[ 0.575906] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5981 11:36:23.676606 <6>[ 0.590288] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5982 11:36:23.680064 <6>[ 0.600064] KASLR enabled
5983 11:36:23.694482 <6>[ 0.608034] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5984 11:36:23.701112 <6>[ 0.615036] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5985 11:36:23.707921 <6>[ 0.621513] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5986 11:36:23.714735 <6>[ 0.628505] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5987 11:36:23.721282 <6>[ 0.634978] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5988 11:36:23.727801 <6>[ 0.641968] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5989 11:36:23.734359 <6>[ 0.648442] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5990 11:36:23.741638 <6>[ 0.655431] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5991 11:36:23.744792 <6>[ 0.662999] ACPI: Interpreter disabled.
5992 11:36:23.754419 <6>[ 0.670979] iommu: Default domain type: Translated
5993 11:36:23.761431 <6>[ 0.676088] iommu: DMA domain TLB invalidation policy: strict mode
5994 11:36:23.764512 <5>[ 0.682717] SCSI subsystem initialized
5995 11:36:23.770740 <6>[ 0.687130] usbcore: registered new interface driver usbfs
5996 11:36:23.777750 <6>[ 0.692859] usbcore: registered new interface driver hub
5997 11:36:23.780757 <6>[ 0.698401] usbcore: registered new device driver usb
5998 11:36:23.787807 <6>[ 0.704706] pps_core: LinuxPPS API ver. 1 registered
5999 11:36:23.797503 <6>[ 0.709891] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6000 11:36:23.800875 <6>[ 0.719217] PTP clock support registered
6001 11:36:23.804229 <6>[ 0.723469] EDAC MC: Ver: 3.0.0
6002 11:36:23.812266 <6>[ 0.729101] FPGA manager framework
6003 11:36:23.818912 <6>[ 0.732786] Advanced Linux Sound Architecture Driver Initialized.
6004 11:36:23.822112 <6>[ 0.739544] vgaarb: loaded
6005 11:36:23.828790 <6>[ 0.742681] clocksource: Switched to clocksource arch_sys_counter
6006 11:36:23.831982 <5>[ 0.749119] VFS: Disk quotas dquot_6.6.0
6007 11:36:23.839192 <6>[ 0.753296] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6008 11:36:23.841966 <6>[ 0.760472] pnp: PnP ACPI: disabled
6009 11:36:23.850935 <6>[ 0.767368] NET: Registered PF_INET protocol family
6010 11:36:23.857013 <6>[ 0.772597] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6011 11:36:23.869479 <6>[ 0.782506] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6012 11:36:23.879563 <6>[ 0.791261] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6013 11:36:23.886420 <6>[ 0.799212] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6014 11:36:23.892911 <6>[ 0.807444] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6015 11:36:23.899547 <6>[ 0.815536] TCP: Hash tables configured (established 32768 bind 32768)
6016 11:36:23.909218 <6>[ 0.822364] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6017 11:36:23.915541 <6>[ 0.829336] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6018 11:36:23.922122 <6>[ 0.836820] NET: Registered PF_UNIX/PF_LOCAL protocol family
6019 11:36:23.929212 <6>[ 0.842917] RPC: Registered named UNIX socket transport module.
6020 11:36:23.932633 <6>[ 0.849061] RPC: Registered udp transport module.
6021 11:36:23.935656 <6>[ 0.853986] RPC: Registered tcp transport module.
6022 11:36:23.942265 <6>[ 0.858909] RPC: Registered tcp NFSv4.1 backchannel transport module.
6023 11:36:23.948978 <6>[ 0.865561] PCI: CLS 0 bytes, default 64
6024 11:36:23.952027 <6>[ 0.869847] Unpacking initramfs...
6025 11:36:23.966521 <6>[ 0.879343] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6026 11:36:23.976245 <6>[ 0.887968] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6027 11:36:23.979372 <6>[ 0.896816] kvm [1]: IPA Size Limit: 40 bits
6028 11:36:23.986412 <6>[ 0.903146] kvm [1]: vgic-v2@c420000
6029 11:36:23.989578 <6>[ 0.906961] kvm [1]: GIC system register CPU interface enabled
6030 11:36:24.002286 <6>[ 0.918760] kvm [1]: vgic interrupt IRQ18
6031 11:36:24.005452 <6>[ 0.923144] kvm [1]: Hyp mode initialized successfully
6032 11:36:24.012423 <5>[ 0.929492] Initialise system trusted keyrings
6033 11:36:24.018866 <6>[ 0.934340] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6034 11:36:24.027443 <6>[ 0.944267] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6035 11:36:24.034419 <5>[ 0.950740] NFS: Registering the id_resolver key type
6036 11:36:24.037693 <5>[ 0.956047] Key type id_resolver registered
6037 11:36:24.044131 <5>[ 0.960460] Key type id_legacy registered
6038 11:36:24.050947 <6>[ 0.964769] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6039 11:36:24.057338 <6>[ 0.971718] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6040 11:36:24.063839 <6>[ 0.979483] 9p: Installing v9fs 9p2000 file system support
6041 11:36:24.092201 <5>[ 1.008531] Key type asymmetric registered
6042 11:36:24.095009 <5>[ 1.012876] Asymmetric key parser 'x509' registered
6043 11:36:24.105262 <6>[ 1.018033] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6044 11:36:24.108846 <6>[ 1.025647] io scheduler mq-deadline registered
6045 11:36:24.112057 <6>[ 1.030402] io scheduler kyber registered
6046 11:36:24.134117 <6>[ 1.051180] EINJ: ACPI disabled.
6047 11:36:24.140856 <4>[ 1.054944] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6048 11:36:24.179017 <6>[ 1.095583] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6049 11:36:24.187587 <6>[ 1.104090] printk: console [ttyS0] disabled
6050 11:36:24.215266 <6>[ 1.128742] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6051 11:36:24.222202 <6>[ 1.138220] printk: console [ttyS0] enabled
6052 11:36:24.224992 <6>[ 1.138220] printk: console [ttyS0] enabled
6053 11:36:24.231805 <6>[ 1.147137] printk: bootconsole [mtk8250] disabled
6054 11:36:24.235037 <6>[ 1.147137] printk: bootconsole [mtk8250] disabled
6055 11:36:24.245123 <3>[ 1.157668] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6056 11:36:24.251994 <3>[ 1.166053] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6057 11:36:24.280997 <6>[ 1.194462] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6058 11:36:24.288326 <6>[ 1.204117] serial serial0: tty port ttyS1 registered
6059 11:36:24.294295 <6>[ 1.210664] SuperH (H)SCI(F) driver initialized
6060 11:36:24.297472 <6>[ 1.216158] msm_serial: driver initialized
6061 11:36:24.313400 <6>[ 1.226460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6062 11:36:24.322631 <6>[ 1.235071] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6063 11:36:24.330089 <6>[ 1.243653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6064 11:36:24.339485 <6>[ 1.252229] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6065 11:36:24.346494 <6>[ 1.260886] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6066 11:36:24.356483 <6>[ 1.269548] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6067 11:36:24.365954 <6>[ 1.278288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6068 11:36:24.372811 <6>[ 1.287028] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6069 11:36:24.382774 <6>[ 1.295595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6070 11:36:24.392501 <6>[ 1.304395] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6071 11:36:24.400077 <4>[ 1.316811] cacheinfo: Unable to detect cache hierarchy for CPU 0
6072 11:36:24.409613 <6>[ 1.326141] loop: module loaded
6073 11:36:24.421466 <6>[ 1.338087] vsim1: Bringing 1800000uV into 2700000-2700000uV
6074 11:36:24.439226 <6>[ 1.356012] megasas: 07.719.03.00-rc1
6075 11:36:24.448253 <6>[ 1.364748] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6076 11:36:24.461768 <6>[ 1.378068] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6077 11:36:24.478251 <6>[ 1.394912] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6078 11:36:24.535502 <6>[ 1.445280] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6079 11:36:24.579428 <6>[ 1.495779] Freeing initrd memory: 18276K
6080 11:36:24.594792 <4>[ 1.507659] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6081 11:36:24.600698 <4>[ 1.516894] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6082 11:36:24.607964 <4>[ 1.523593] Hardware name: Google juniper sku16 board (DT)
6083 11:36:24.610972 <4>[ 1.529332] Call trace:
6084 11:36:24.614072 <4>[ 1.532032] dump_backtrace.part.0+0xe0/0xf0
6085 11:36:24.617555 <4>[ 1.536570] show_stack+0x18/0x30
6086 11:36:24.621151 <4>[ 1.540143] dump_stack_lvl+0x64/0x80
6087 11:36:24.624571 <4>[ 1.544062] dump_stack+0x18/0x34
6088 11:36:24.631165 <4>[ 1.547631] sysfs_warn_dup+0x64/0x80
6089 11:36:24.634428 <4>[ 1.551552] sysfs_do_create_link_sd+0xf0/0x100
6090 11:36:24.637710 <4>[ 1.556340] sysfs_create_link+0x20/0x40
6091 11:36:24.640925 <4>[ 1.560519] bus_add_device+0x64/0x120
6092 11:36:24.647817 <4>[ 1.564524] device_add+0x354/0x7ec
6093 11:36:24.651018 <4>[ 1.568270] of_device_add+0x44/0x60
6094 11:36:24.654792 <4>[ 1.572104] of_platform_device_create_pdata+0x90/0x124
6095 11:36:24.661141 <4>[ 1.577586] of_platform_bus_create+0x154/0x380
6096 11:36:24.664319 <4>[ 1.582372] of_platform_populate+0x50/0xfc
6097 11:36:24.671169 <4>[ 1.586811] parse_mtd_partitions+0x1d8/0x4e0
6098 11:36:24.674750 <4>[ 1.591428] mtd_device_parse_register+0xec/0x2e0
6099 11:36:24.677504 <4>[ 1.596389] spi_nor_probe+0x280/0x2f4
6100 11:36:24.681142 <4>[ 1.600394] spi_mem_probe+0x6c/0xc0
6101 11:36:24.687891 <4>[ 1.604227] spi_probe+0x84/0xe4
6102 11:36:24.691100 <4>[ 1.607711] really_probe+0xbc/0x2dc
6103 11:36:24.694129 <4>[ 1.611542] __driver_probe_device+0x78/0x114
6104 11:36:24.697678 <4>[ 1.616154] driver_probe_device+0xd8/0x15c
6105 11:36:24.704297 <4>[ 1.620591] __device_attach_driver+0xb8/0x134
6106 11:36:24.707565 <4>[ 1.625289] bus_for_each_drv+0x7c/0xd4
6107 11:36:24.710738 <4>[ 1.629382] __device_attach+0x9c/0x1a0
6108 11:36:24.717244 <4>[ 1.633472] device_initial_probe+0x14/0x20
6109 11:36:24.720670 <4>[ 1.637910] bus_probe_device+0x98/0xa0
6110 11:36:24.724361 <4>[ 1.642000] device_add+0x3c0/0x7ec
6111 11:36:24.727534 <4>[ 1.645745] __spi_add_device+0x78/0x120
6112 11:36:24.730734 <4>[ 1.649923] spi_add_device+0x44/0x80
6113 11:36:24.737819 <4>[ 1.653840] spi_register_controller+0x704/0xb20
6114 11:36:24.741106 <4>[ 1.658712] devm_spi_register_controller+0x4c/0xac
6115 11:36:24.747643 <4>[ 1.663845] mtk_spi_probe+0x4f4/0x684
6116 11:36:24.750735 <4>[ 1.667850] platform_probe+0x68/0xc0
6117 11:36:24.754607 <4>[ 1.671768] really_probe+0xbc/0x2dc
6118 11:36:24.757569 <4>[ 1.675598] __driver_probe_device+0x78/0x114
6119 11:36:24.764409 <4>[ 1.680209] driver_probe_device+0xd8/0x15c
6120 11:36:24.767424 <4>[ 1.684646] __driver_attach+0x94/0x19c
6121 11:36:24.770842 <4>[ 1.688736] bus_for_each_dev+0x74/0xd0
6122 11:36:24.774660 <4>[ 1.692828] driver_attach+0x24/0x30
6123 11:36:24.777874 <4>[ 1.696657] bus_add_driver+0x154/0x20c
6124 11:36:24.784240 <4>[ 1.700747] driver_register+0x78/0x130
6125 11:36:24.787702 <4>[ 1.704837] __platform_driver_register+0x28/0x34
6126 11:36:24.794523 <4>[ 1.709797] mtk_spi_driver_init+0x1c/0x28
6127 11:36:24.797736 <4>[ 1.714153] do_one_initcall+0x64/0x1dc
6128 11:36:24.800879 <4>[ 1.718244] kernel_init_freeable+0x218/0x284
6129 11:36:24.804581 <4>[ 1.722858] kernel_init+0x24/0x12c
6130 11:36:24.807965 <4>[ 1.726604] ret_from_fork+0x10/0x20
6131 11:36:24.818646 <6>[ 1.735501] tun: Universal TUN/TAP device driver, 1.6
6132 11:36:24.822195 <6>[ 1.741788] thunder_xcv, ver 1.0
6133 11:36:24.825518 <6>[ 1.745302] thunder_bgx, ver 1.0
6134 11:36:24.828344 <6>[ 1.748805] nicpf, ver 1.0
6135 11:36:24.839666 <6>[ 1.753170] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6136 11:36:24.843188 <6>[ 1.760654] hns3: Copyright (c) 2017 Huawei Corporation.
6137 11:36:24.846212 <6>[ 1.766253] hclge is initializing
6138 11:36:24.853128 <6>[ 1.769844] e1000: Intel(R) PRO/1000 Network Driver
6139 11:36:24.859903 <6>[ 1.774980] e1000: Copyright (c) 1999-2006 Intel Corporation.
6140 11:36:24.863781 <6>[ 1.781004] e1000e: Intel(R) PRO/1000 Network Driver
6141 11:36:24.870008 <6>[ 1.786226] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6142 11:36:24.876799 <6>[ 1.792420] igb: Intel(R) Gigabit Ethernet Network Driver
6143 11:36:24.883359 <6>[ 1.798075] igb: Copyright (c) 2007-2014 Intel Corporation.
6144 11:36:24.889999 <6>[ 1.803918] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6145 11:36:24.896433 <6>[ 1.810442] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6146 11:36:24.900289 <6>[ 1.816998] sky2: driver version 1.30
6147 11:36:24.906778 <6>[ 1.822252] usbcore: registered new device driver r8152-cfgselector
6148 11:36:24.913311 <6>[ 1.828793] usbcore: registered new interface driver r8152
6149 11:36:24.919876 <6>[ 1.834625] VFIO - User Level meta-driver version: 0.3
6150 11:36:24.926571 <6>[ 1.842413] mtu3 11201000.usb: uwk - reg:0x420, version:101
6151 11:36:24.933281 <4>[ 1.848292] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6152 11:36:24.940087 <6>[ 1.855563] mtu3 11201000.usb: dr_mode: 1, drd: auto
6153 11:36:24.946495 <6>[ 1.860791] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6154 11:36:24.950170 <6>[ 1.866982] mtu3 11201000.usb: usb3-drd: 0
6155 11:36:24.956523 <6>[ 1.872559] mtu3 11201000.usb: xHCI platform device register success...
6156 11:36:24.967723 <4>[ 1.881182] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6157 11:36:24.974359 <6>[ 1.889109] xhci-mtk 11200000.usb: xHCI Host Controller
6158 11:36:24.981384 <6>[ 1.894617] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6159 11:36:24.988092 <6>[ 1.902358] xhci-mtk 11200000.usb: USB3 root hub has no ports
6160 11:36:24.998067 <6>[ 1.908368] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6161 11:36:25.001336 <6>[ 1.917793] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6162 11:36:25.007645 <6>[ 1.923872] xhci-mtk 11200000.usb: xHCI Host Controller
6163 11:36:25.014623 <6>[ 1.929361] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6164 11:36:25.020969 <6>[ 1.937022] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6165 11:36:25.027825 <6>[ 1.943846] hub 1-0:1.0: USB hub found
6166 11:36:25.030952 <6>[ 1.947875] hub 1-0:1.0: 1 port detected
6167 11:36:25.041099 <6>[ 1.953232] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6168 11:36:25.044825 <6>[ 1.961859] hub 2-0:1.0: USB hub found
6169 11:36:25.051350 <3>[ 1.965905] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6170 11:36:25.057744 <6>[ 1.973791] usbcore: registered new interface driver usb-storage
6171 11:36:25.064386 <6>[ 1.980400] usbcore: registered new device driver onboard-usb-hub
6172 11:36:25.077463 <4>[ 1.990799] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6173 11:36:25.086500 <6>[ 2.003030] mt6397-rtc mt6358-rtc: registered as rtc0
6174 11:36:25.096718 <6>[ 2.008508] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-17T11:36:15 UTC (1721216175)
6175 11:36:25.099844 <6>[ 2.018385] i2c_dev: i2c /dev entries driver
6176 11:36:25.111692 <6>[ 2.024825] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6177 11:36:25.121737 <6>[ 2.033144] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6178 11:36:25.124823 <6>[ 2.042048] i2c 4-0058: Fixed dependency cycle(s) with /panel
6179 11:36:25.134649 <6>[ 2.048080] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6180 11:36:25.151346 <6>[ 2.067555] cpu cpu0: EM: created perf domain
6181 11:36:25.161794 <6>[ 2.073079] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6182 11:36:25.168247 <6>[ 2.084359] cpu cpu4: EM: created perf domain
6183 11:36:25.175417 <6>[ 2.091402] sdhci: Secure Digital Host Controller Interface driver
6184 11:36:25.182045 <6>[ 2.097859] sdhci: Copyright(c) Pierre Ossman
6185 11:36:25.188193 <6>[ 2.103275] Synopsys Designware Multimedia Card Interface Driver
6186 11:36:25.194651 <6>[ 2.103809] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6187 11:36:25.197856 <6>[ 2.110337] sdhci-pltfm: SDHCI platform and OF driver helper
6188 11:36:25.207122 <6>[ 2.124070] ledtrig-cpu: registered to indicate activity on CPUs
6189 11:36:25.215585 <6>[ 2.131862] usbcore: registered new interface driver usbhid
6190 11:36:25.218456 <6>[ 2.137713] usbhid: USB HID core driver
6191 11:36:25.229710 <6>[ 2.141999] spi_master spi2: will run message pump with realtime priority
6192 11:36:25.233744 <4>[ 2.142004] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6193 11:36:25.240521 <4>[ 2.156285] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6194 11:36:25.254382 <6>[ 2.161244] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6195 11:36:25.273242 <6>[ 2.179229] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6196 11:36:25.279283 <4>[ 2.189042] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6197 11:36:25.285822 <6>[ 2.200532] cros-ec-spi spi2.0: Chrome EC device registered
6198 11:36:25.292526 <4>[ 2.207887] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6199 11:36:25.305881 <4>[ 2.219025] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6200 11:36:25.312501 <4>[ 2.228255] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6201 11:36:25.324574 <6>[ 2.238241] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6202 11:36:25.337852 <6>[ 2.254634] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6203 11:36:25.345600 <6>[ 2.262265] mmc0: new HS400 MMC card at address 0001
6204 11:36:25.352264 <6>[ 2.268543] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6205 11:36:25.361091 <6>[ 2.277890] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6206 11:36:25.369762 <6>[ 2.286482] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6207 11:36:25.379663 <6>[ 2.291897] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6208 11:36:25.383419 <6>[ 2.292950] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6209 11:36:25.397070 <6>[ 2.306613] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6210 11:36:25.402832 <6>[ 2.307264] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6211 11:36:25.413487 <6>[ 2.310080] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6212 11:36:25.422977 <6>[ 2.310317] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6213 11:36:25.429425 <6>[ 2.319286] NET: Registered PF_PACKET protocol family
6214 11:36:25.433099 <6>[ 2.351760] 9pnet: Installing 9P2000 support
6215 11:36:25.440088 <5>[ 2.356352] Key type dns_resolver registered
6216 11:36:25.443482 <6>[ 2.361653] registered taskstats version 1
6217 11:36:25.449907 <6>[ 2.362697] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6218 11:36:25.456675 <5>[ 2.366019] Loading compiled-in X.509 certificates
6219 11:36:25.497304 <3>[ 2.410518] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6220 11:36:25.522358 <6>[ 2.432587] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6221 11:36:25.532651 <6>[ 2.446160] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6222 11:36:25.542700 <6>[ 2.454734] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6223 11:36:25.549804 <6>[ 2.463264] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6224 11:36:25.559840 <6>[ 2.471792] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6225 11:36:25.566521 <6>[ 2.480316] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6226 11:36:25.575809 <6>[ 2.488837] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6227 11:36:25.583309 <6>[ 2.497357] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6228 11:36:25.589732 <6>[ 2.506458] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6229 11:36:25.597698 <6>[ 2.513845] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6230 11:36:25.604789 <6>[ 2.521080] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6231 11:36:25.610890 <6>[ 2.522311] hub 1-1:1.0: USB hub found
6232 11:36:25.617916 <6>[ 2.528321] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6233 11:36:25.620730 <6>[ 2.532115] hub 1-1:1.0: 3 ports detected
6234 11:36:25.627554 <6>[ 2.539021] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6235 11:36:25.634618 <6>[ 2.550798] panfrost 13040000.gpu: clock rate = 511999970
6236 11:36:25.644311 <6>[ 2.556488] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6237 11:36:25.654037 <6>[ 2.566835] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6238 11:36:25.660561 <6>[ 2.574856] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6239 11:36:25.674124 <6>[ 2.583289] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6240 11:36:25.680378 <6>[ 2.595366] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6241 11:36:25.693134 <6>[ 2.606628] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6242 11:36:25.703045 <6>[ 2.615746] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6243 11:36:25.713180 <6>[ 2.624921] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6244 11:36:25.722859 <6>[ 2.634052] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6245 11:36:25.729741 <6>[ 2.643180] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6246 11:36:25.739539 <6>[ 2.652484] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6247 11:36:25.749397 <6>[ 2.661785] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6248 11:36:25.759487 <6>[ 2.671259] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6249 11:36:25.769608 <6>[ 2.680733] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6250 11:36:25.776550 <6>[ 2.689860] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6251 11:36:25.849730 <6>[ 2.762847] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6252 11:36:25.858892 <6>[ 2.771773] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6253 11:36:25.870764 <6>[ 2.784213] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6254 11:36:25.917947 <6>[ 2.830839] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6255 11:36:26.574698 <6>[ 3.015154] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6256 11:36:26.584543 <4>[ 3.118509] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6257 11:36:26.591491 <4>[ 3.118526] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6258 11:36:26.597532 <6>[ 3.155974] r8152 1-1.2:1.0 eth0: v1.12.13
6259 11:36:26.604499 <6>[ 3.234714] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6260 11:36:26.611288 <6>[ 3.471174] Console: switching to colour frame buffer device 170x48
6261 11:36:26.617743 <6>[ 3.531825] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6262 11:36:26.638210 <6>[ 3.548063] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6263 11:36:26.655085 <6>[ 3.564644] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6264 11:36:26.661746 <6>[ 3.576774] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6265 11:36:26.671997 <6>[ 3.584831] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6266 11:36:26.681526 <6>[ 3.590174] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6267 11:36:26.699093 <6>[ 3.608994] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6268 11:36:27.865785 <6>[ 4.782456] r8152 1-1.2:1.0 eth0: carrier on
6269 11:36:29.961912 <5>[ 4.806715] Sending DHCP requests .., OK
6270 11:36:29.968847 <6>[ 6.883020] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6271 11:36:29.971816 <6>[ 6.891475] IP-Config: Complete:
6272 11:36:29.985754 <6>[ 6.895040] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6273 11:36:29.995534 <6>[ 6.905940] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6274 11:36:30.007517 <6>[ 6.920304] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6275 11:36:30.015847 <6>[ 6.920315] nameserver0=192.168.201.1
6276 11:36:30.023915 <6>[ 6.940192] clk: Disabling unused clocks
6277 11:36:30.028713 <6>[ 6.948208] ALSA device list:
6278 11:36:30.037648 <6>[ 6.954297] No soundcards found.
6279 11:36:30.047320 <6>[ 6.963388] Freeing unused kernel memory: 8512K
6280 11:36:30.054326 <6>[ 6.970583] Run /init as init process
6281 11:36:30.066373 Loading, please wait...
6282 11:36:30.107592 Starting systemd-udevd version 252.22-1~deb12u1
6283 11:36:30.437481 <6>[ 7.350392] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6284 11:36:30.446821 <3>[ 7.363140] thermal_sys: Failed to find 'trips' node
6285 11:36:30.453833 <3>[ 7.363162] mtk-scp 10500000.scp: invalid resource
6286 11:36:30.460354 <3>[ 7.368395] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6287 11:36:30.466385 <4>[ 7.374008] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6288 11:36:30.473448 <6>[ 7.374142] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6289 11:36:30.483517 <3>[ 7.381123] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6290 11:36:30.493059 <3>[ 7.381161] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6291 11:36:30.499798 <3>[ 7.381166] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6292 11:36:30.514643 <3>[ 7.381170] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6293 11:36:30.521534 <3>[ 7.381176] elan_i2c 2-0015: Error applying setting, reverse things back
6294 11:36:30.529884 <6>[ 7.381471] remoteproc remoteproc0: scp is available
6295 11:36:30.540445 <4>[ 7.381552] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6296 11:36:30.547340 <6>[ 7.381558] remoteproc remoteproc0: powering up scp
6297 11:36:30.553902 <4>[ 7.381579] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6298 11:36:30.560060 <3>[ 7.381582] remoteproc remoteproc0: request_firmware failed: -2
6299 11:36:30.566719 <4>[ 7.394176] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6300 11:36:30.573868 <4>[ 7.395763] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6301 11:36:30.580980 <6>[ 7.456823] mc: Linux media interface: v0.10
6302 11:36:30.587817 <3>[ 7.463124] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6303 11:36:30.593968 <3>[ 7.469949] thermal_sys: Failed to find 'trips' node
6304 11:36:30.600915 <5>[ 7.470243] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6305 11:36:30.607785 <6>[ 7.471198] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6306 11:36:30.617516 <3>[ 7.475411] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6307 11:36:30.624369 <6>[ 7.475778] cs_system_cfg: CoreSight Configuration manager initialised
6308 11:36:30.631327 <3>[ 7.481591] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6309 11:36:30.637660 <5>[ 7.486291] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6310 11:36:30.647677 <5>[ 7.486728] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6311 11:36:30.654365 <4>[ 7.486788] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6312 11:36:30.660594 <6>[ 7.486794] cfg80211: failed to load regulatory.db
6313 11:36:30.671132 <3>[ 7.489006] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6314 11:36:30.681496 <3>[ 7.496563] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6315 11:36:30.692173 <3>[ 7.501210] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6316 11:36:30.698721 <4>[ 7.509628] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6317 11:36:30.705250 <3>[ 7.514815] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6318 11:36:30.715243 <4>[ 7.524712] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6319 11:36:30.726847 <3>[ 7.530543] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6320 11:36:30.737046 <3>[ 7.530555] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6321 11:36:30.743522 <3>[ 7.530561] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6322 11:36:30.753189 <6>[ 7.539633] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6323 11:36:30.762810 <3>[ 7.546012] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6324 11:36:30.773478 <6>[ 7.546546] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input6
6325 11:36:30.783014 <6>[ 7.554950] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6326 11:36:30.789633 <6>[ 7.560562] videodev: Linux video capture interface: v2.00
6327 11:36:30.796227 <6>[ 7.560715] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6328 11:36:30.806571 <6>[ 7.560824] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6329 11:36:30.813454 <6>[ 7.560911] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6330 11:36:30.823704 <6>[ 7.560993] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6331 11:36:30.833373 <6>[ 7.561076] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6332 11:36:30.839885 <6>[ 7.568442] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6333 11:36:30.853881 <3>[ 7.568803] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6334 11:36:30.856652 <6>[ 7.594153] Bluetooth: Core ver 2.22
6335 11:36:30.863655 <6>[ 7.595265] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6336 11:36:30.870255 <6>[ 7.603461] NET: Registered PF_BLUETOOTH protocol family
6337 11:36:30.876645 <6>[ 7.612115] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6338 11:36:30.882910 <6>[ 7.612286] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6339 11:36:30.889473 <6>[ 7.612660] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6340 11:36:30.896108 <6>[ 7.612991] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6341 11:36:30.902869 <6>[ 7.613505] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6342 11:36:30.912784 <6>[ 7.613955] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video1 (81,1)
6343 11:36:30.919329 <6>[ 7.619900] Bluetooth: HCI device and connection manager initialized
6344 11:36:30.932487 <6>[ 7.646054] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6345 11:36:30.939258 Begin: Loading e<6>[ 7.648445] Bluetooth: HCI socket layer initialized
6346 11:36:30.945916 ssential drivers<6>[ 7.657281] usbcore: registered new interface driver uvcvideo
6347 11:36:30.946312 ... done.
6348 11:36:30.952590 Begi<6>[ 7.665527] Bluetooth: L2CAP socket layer initialized
6349 11:36:30.962365 n: Running /scri<6>[ 7.687062] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6350 11:36:30.969121 pts/init-premoun<6>[ 7.693996] Bluetooth: SCO socket layer initialized
6351 11:36:30.972553 t ... done.
6352 11:36:30.979356 Beg<6>[ 7.704841] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6353 11:36:30.986291 <6>[ 7.745209] Bluetooth: HCI UART driver ver 2.3
6354 11:36:30.996788 in: Mounting roo<6>[ 7.753052] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6355 11:36:31.006569 t file system ... Begin: Running<6>[ 7.760866] Bluetooth: HCI UART protocol H4 registered
6356 11:36:31.009896 /scripts/nfs-top ... done.
6357 11:36:31.016337 Beg<6>[ 7.760926] Bluetooth: HCI UART protocol LL registered
6358 11:36:31.030197 in: Running /scripts/nfs-premoun<3>[ 7.773558] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6359 11:36:31.043205 t ... Waiting up to 60 secs for <6>[ 7.777138] Bluetooth: HCI UART protocol Three-wire (H5) registered
6360 11:36:31.053158 any ethernet to become available<3>[ 7.785702] debugfs: File 'Playback' in directory 'dapm' already present!
6361 11:36:31.053632
6362 11:36:31.063530 Device /sys/class/net/eth0 fou<6>[ 7.790957] Bluetooth: HCI UART protocol Broadcom registered
6363 11:36:31.064016 nd
6364 11:36:31.064322 done.
6365 11:36:31.073356 <3>[ 7.798507] debugfs: File 'Capture' in directory 'dapm' already present!
6366 11:36:31.083825 <6>[ 7.801454] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input7
6367 11:36:31.092678 <6>[ 7.804971] Bluetooth: HCI UART protocol QCA registered
6368 11:36:31.099557 <6>[ 7.806090] Bluetooth: hci0: setting up ROME/QCA6390
6369 11:36:31.102868 <3>[ 7.813459] thermal_sys: Failed to find 'trips' node
6370 11:36:31.109938 Begin: Waiting u<6>[ 7.817920] Bluetooth: HCI UART protocol Marvell registered
6371 11:36:31.122634 p to 180 secs for any network de<3>[ 7.825467] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6372 11:36:31.135901 vice to become available ... don<3>[ 7.825475] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6373 11:36:31.136360 e.
6374 11:36:31.149869 <4>[ 7.892169] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6375 11:36:31.156050 <4>[ 7.892169] Fallback method does not support PEC.
6376 11:36:31.167833 <4>[ 7.892494] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6377 11:36:31.179320 <3>[ 7.904053] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6378 11:36:31.191608 <6>[ 8.009227] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6379 11:36:31.199823 <3>[ 8.018324] Bluetooth: hci0: Frame reassembly failed (-84)
6380 11:36:31.212818 <3>[ 8.020572] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6381 11:36:31.394912 <6>[ 8.307825] Bluetooth: hci0: QCA Product ID :0x00000008
6382 11:36:31.421272 <6>[ 8.337238] Bluetooth: hci0: QCA SOC Version :0x00000044
6383 11:36:31.428293 <6>[ 8.344766] Bluetooth: hci0: QCA ROM Version :0x00000302
6384 11:36:31.436201 <6>[ 8.352276] Bluetooth: hci0: QCA Patch Version:0x00000111
6385 11:36:31.442863 <6>[ 8.359551] Bluetooth: hci0: QCA controller version 0x00440302
6386 11:36:31.453781 <6>[ 8.367044] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6387 11:36:31.464485 <4>[ 8.375125] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6388 11:36:31.473778 <3>[ 8.385576] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6389 11:36:31.480927 <3>[ 8.394855] Bluetooth: hci0: QCA Failed to download patch (-2)
6390 11:36:31.510302 IP-Config: eth0 hardware address 00:e0:4c:68:0b:b9 mtu 1500 DHCP
6391 11:36:31.516727 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6392 11:36:31.523364 address: 192.168.201.13 broadcast: 192.168.201.255 netmask: 255.255.255.0
6393 11:36:31.530083 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6394 11:36:31.536529 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-0
6395 11:36:31.543140 domain : lava-rack
6396 11:36:31.546700 rootserver: 192.168.201.1 rootpath:
6397 11:36:31.547170 filename :
6398 11:36:31.630948 done.
6399 11:36:31.639040 Begin: Running /scripts/nfs-bottom ... done.
6400 11:36:31.654096 Begin: Running /scripts/init-bottom ... done.
6401 11:36:31.741478 <6>[ 8.654606] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6402 11:36:31.824313 <4>[ 8.737828] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6403 11:36:31.844635 <4>[ 8.757731] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6404 11:36:31.859939 <4>[ 8.773223] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6405 11:36:31.869860 <4>[ 8.786650] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6406 11:36:33.038371 <6>[ 9.954581] NET: Registered PF_INET6 protocol family
6407 11:36:33.050713 <6>[ 9.967100] Segment Routing with IPv6
6408 11:36:33.059074 <6>[ 9.975618] In-situ OAM (IOAM) with IPv6
6409 11:36:33.247779 <30>[ 10.137469] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6410 11:36:33.269047 <30>[ 10.184896] systemd[1]: Detected architecture arm64.
6411 11:36:33.282465
6412 11:36:33.285041 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6413 11:36:33.285425
6414 11:36:33.308291 <30>[ 10.224489] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6415 11:36:34.466622 <30>[ 11.379526] systemd[1]: Queued start job for default target graphical.target.
6416 11:36:34.511801 <30>[ 11.424451] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6417 11:36:34.525081 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6418 11:36:34.545084 <30>[ 11.458113] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6419 11:36:34.558260 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6420 11:36:34.579929 <30>[ 11.492978] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6421 11:36:34.594386 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6422 11:36:34.611325 <30>[ 11.524280] systemd[1]: Created slice user.slice - User and Session Slice.
6423 11:36:34.623850 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6424 11:36:34.645416 <30>[ 11.555298] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6425 11:36:34.659403 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6426 11:36:34.681985 <30>[ 11.591735] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6427 11:36:34.694961 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6428 11:36:34.724845 <30>[ 11.627461] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6429 11:36:34.743906 <30>[ 11.656797] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6430 11:36:34.751439 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6431 11:36:34.769876 <30>[ 11.682916] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6432 11:36:34.783086 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6433 11:36:34.802341 <30>[ 11.715339] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6434 11:36:34.817194 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6435 11:36:34.831061 <30>[ 11.747001] systemd[1]: Reached target paths.target - Path Units.
6436 11:36:34.845785 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6437 11:36:34.862623 <30>[ 11.775336] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6438 11:36:34.875386 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6439 11:36:34.891611 <30>[ 11.807236] systemd[1]: Reached target slices.target - Slice Units.
6440 11:36:34.906000 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6441 11:36:34.918846 <30>[ 11.834918] systemd[1]: Reached target swap.target - Swaps.
6442 11:36:34.933023 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6443 11:36:34.950565 <30>[ 11.863418] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6444 11:36:34.964816 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6445 11:36:34.982677 <30>[ 11.895429] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6446 11:36:34.996389 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6447 11:36:35.017064 <30>[ 11.930128] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6448 11:36:35.030259 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6449 11:36:35.051941 <30>[ 11.964775] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6450 11:36:35.066443 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6451 11:36:35.082667 <30>[ 11.995642] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6452 11:36:35.094593 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6453 11:36:35.116214 <30>[ 12.029018] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6454 11:36:35.130237 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6455 11:36:35.149120 <30>[ 12.062409] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6456 11:36:35.162681 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6457 11:36:35.183147 <30>[ 12.096146] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6458 11:36:35.196817 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6459 11:36:35.245858 <30>[ 12.159107] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6460 11:36:35.257702 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6461 11:36:35.279510 <30>[ 12.192825] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6462 11:36:35.292291 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6463 11:36:35.350392 <30>[ 12.263262] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6464 11:36:35.362647 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6465 11:36:35.385582 <30>[ 12.291831] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6466 11:36:35.438232 <30>[ 12.351484] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6467 11:36:35.451760 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6468 11:36:35.476260 <30>[ 12.389071] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6469 11:36:35.487043 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6470 11:36:35.546976 <30>[ 12.460097] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6471 11:36:35.559958 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6472 11:36:35.588708 <30>[ 12.501871] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6473 11:36:35.605480 Starting [0;1;39mmodpr<6>[ 12.517101] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6474 11:36:35.608724 obe@drm.service[0m - Load Kernel Module drm...
6475 11:36:35.655024 <30>[ 12.567855] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6476 11:36:35.668784 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6477 11:36:35.695485 <30>[ 12.608388] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6478 11:36:35.708991 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6479 11:36:35.735623 <30>[ 12.648430] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6480 11:36:35.747757 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6481 11:36:35.755897 <6>[ 12.672037] fuse: init (API version 7.37)
6482 11:36:35.794699 <30>[ 12.707613] systemd[1]: Starting systemd-journald.service - Journal Service...
6483 11:36:35.805373 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6484 11:36:35.835167 <30>[ 12.748417] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6485 11:36:35.847051 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6486 11:36:35.914020 <30>[ 12.823430] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6487 11:36:35.925786 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6488 11:36:35.951443 <30>[ 12.864227] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6489 11:36:35.963734 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6490 11:36:35.985191 <30>[ 12.898311] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6491 11:36:35.996210 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6492 11:36:36.019889 <3>[ 12.932309] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6493 11:36:36.026412 <30>[ 12.938038] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6494 11:36:36.044629 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 12.957054] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6495 11:36:36.047577 uge Pages File System.
6496 11:36:36.063490 <3>[ 12.976224] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6497 11:36:36.071890 <30>[ 12.985441] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6498 11:36:36.082051 <3>[ 12.991425] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6499 11:36:36.099585 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 13.009832] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6500 11:36:36.100049 File System.
6501 11:36:36.114378 <3>[ 13.027367] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6502 11:36:36.125635 <30>[ 13.036866] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6503 11:36:36.132383 <3>[ 13.044854] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6504 11:36:36.153066 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 13.065408] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6505 11:36:36.153490 File System.
6506 11:36:36.170746 <3>[ 13.083704] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6507 11:36:36.181174 <30>[ 13.093402] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6508 11:36:36.196359 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate <3>[ 13.109348] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6509 11:36:36.199472 List of Static Device Nodes.
6510 11:36:36.219226 <30>[ 13.132455] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6511 11:36:36.229293 <30>[ 13.141450] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6512 11:36:36.239286 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6513 11:36:36.255058 <30>[ 13.167838] systemd[1]: Started systemd-journald.service - Journal Service.
6514 11:36:36.264791 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6515 11:36:36.284617 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6516 11:36:36.307299 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6517 11:36:36.327339 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6518 11:36:36.351316 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6519 11:36:36.371259 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6520 11:36:36.395193 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6521 11:36:36.419001 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6522 11:36:36.443286 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6523 11:36:36.467475 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6524 11:36:36.520926 Mountin<4>[ 13.424358] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6525 11:36:36.530720 g [0;1;39msys-fs-fuse-conne…<3>[ 13.442482] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6526 11:36:36.533824 [0m - FUSE Control File System...
6527 11:36:36.559457 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6528 11:36:36.588423 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6529 11:36:36.616513 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6530 11:36:36.657257 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Ke<46>[ 13.568121] systemd-journald[316]: Received client request to flush runtime journal.
6531 11:36:36.657905 rnel Variables...
6532 11:36:36.710603 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6533 11:36:37.009424 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6534 11:36:37.027389 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6535 11:36:37.046563 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6536 11:36:37.067810 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6537 11:36:37.638450 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6538 11:36:37.812694 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6539 11:36:37.879433 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6540 11:36:38.134831 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6541 11:36:38.264014 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6542 11:36:38.283355 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6543 11:36:38.302286 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6544 11:36:38.350571 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6545 11:36:38.378061 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6546 11:36:38.625806 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6547 11:36:38.670431 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6548 11:36:38.733365 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6549 11:36:38.988489 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6550 11:36:39.010204 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6551 11:36:39.050469 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6552 11:36:39.083134 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6553 11:36:39.143976 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6554 11:36:39.232304 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6555 11:36:39.252953 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6556 11:36:39.342421 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6557 11:36:39.368742 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6558 11:36:39.388494 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6559 11:36:39.462991 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6560 11:36:39.491533 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6561 11:36:39.531973 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6562 11:36:39.558981 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6563 11:36:39.619895 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6564 11:36:39.657210 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6565 11:36:39.683464 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6566 11:36:39.709132 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6567 11:36:39.732742 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6568 11:36:39.755266 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6569 11:36:39.779637 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6570 11:36:39.804572 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6571 11:36:39.837299 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6572 11:36:39.874874 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6573 11:36:39.886875 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6574 11:36:39.910571 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6575 11:36:39.931051 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6576 11:36:39.951028 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6577 11:36:39.971401 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6578 11:36:39.995384 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6579 11:36:40.015435 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6580 11:36:40.035539 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6581 11:36:40.084130 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6582 11:36:40.104784 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6583 11:36:40.140854 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6584 11:36:40.258133 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6585 11:36:40.287368 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6586 11:36:40.300408 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6587 11:36:40.321473 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6588 11:36:40.437477 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6589 11:36:40.483714 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6590 11:36:40.532373 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6591 11:36:40.555646 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6592 11:36:40.572855 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6593 11:36:40.616318 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6594 11:36:40.638276 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6595 11:36:40.660951 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6596 11:36:40.684134 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6597 11:36:40.732034 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6598 11:36:40.807597 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6599 11:36:40.893250
6600 11:36:40.896379 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6601 11:36:40.896811
6602 11:36:40.899942 debian-bookworm-arm64 login: root (automatic login)
6603 11:36:40.900325
6604 11:36:41.203236 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
6605 11:36:41.203401
6606 11:36:41.210371 The programs included with the Debian GNU/Linux system are free software;
6607 11:36:41.216849 the exact distribution terms for each program are described in the
6608 11:36:41.219887 individual files in /usr/share/doc/*/copyright.
6609 11:36:41.219971
6610 11:36:41.226927 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6611 11:36:41.229722 permitted by applicable law.
6612 11:36:42.401588 Matched prompt #10: / #
6614 11:36:42.402497 Setting prompt string to ['/ #']
6615 11:36:42.402897 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6617 11:36:42.403780 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6618 11:36:42.404188 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
6619 11:36:42.404522 Setting prompt string to ['/ #']
6620 11:36:42.404809 Forcing a shell prompt, looking for ['/ #']
6621 11:36:42.405094 Sending line: ''
6623 11:36:42.456303 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6624 11:36:42.456760 Waiting using forced prompt support (timeout 00:02:30)
6625 11:36:42.461901 / #
6626 11:36:42.462765 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6627 11:36:42.463238 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
6628 11:36:42.463652 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o'"
6630 11:36:42.570759 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864624/extract-nfsrootfs-gotozn1o'
6631 11:36:42.571397 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6633 11:36:42.678956 / # export NFS_SERVER_IP='192.168.201.1'
6634 11:36:42.679763 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6635 11:36:42.680225 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
6636 11:36:42.680687 end: 2 depthcharge-action (duration 00:01:14) [common]
6637 11:36:42.681109 start: 3 lava-test-retry (timeout 00:08:04) [common]
6638 11:36:42.681521 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
6639 11:36:42.681868 Using namespace: common
6640 11:36:42.682190 Sending line: '#'
6642 11:36:42.783788 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6643 11:36:42.789777 / # #
6644 11:36:42.790585 Using /lava-14864624
6645 11:36:42.790942 Sending line: 'export SHELL=/bin/bash'
6647 11:36:42.898163 / # export SHELL=/bin/bash
6648 11:36:42.898903 Sending line: '. /lava-14864624/environment'
6650 11:36:43.006249 / # . /lava-14864624/environment
6651 11:36:43.012752 Sending line: '/lava-14864624/bin/lava-test-runner /lava-14864624/0'
6653 11:36:43.114390 Test shell timeout: 10s (minimum of the action and connection timeout)
6654 11:36:43.120784 / # /lava-14864624/bin/lava-test-runner /lava-14864624/0
6655 11:36:43.400838 + export TESTRUN_ID=0_timesync-off
6656 11:36:43.404204 + TESTRUN_ID=0_timesync-off
6657 11:36:43.406992 + cd /lava-14864624/0/tests/0_timesync-off
6658 11:36:43.410530 ++ cat uuid
6659 11:36:43.414591 + UUID=14864624_1.6.2.3.1
6660 11:36:43.414677 + set +x
6661 11:36:43.421290 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14864624_1.6.2.3.1>
6662 11:36:43.421562 Received signal: <STARTRUN> 0_timesync-off 14864624_1.6.2.3.1
6663 11:36:43.421638 Starting test lava.0_timesync-off (14864624_1.6.2.3.1)
6664 11:36:43.421723 Skipping test definition patterns.
6665 11:36:43.424304 + systemctl stop systemd-timesyncd
6666 11:36:43.482790 + set +x
6667 11:36:43.485668 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14864624_1.6.2.3.1>
6668 11:36:43.486296 Received signal: <ENDRUN> 0_timesync-off 14864624_1.6.2.3.1
6669 11:36:43.486671 Ending use of test pattern.
6670 11:36:43.486957 Ending test lava.0_timesync-off (14864624_1.6.2.3.1), duration 0.07
6672 11:36:43.573453 + export TESTRUN_ID=1_kselftest-arm64
6673 11:36:43.573868 + TESTRUN_ID=1_kselftest-arm64
6674 11:36:43.580034 + cd /lava-14864624/0/tests/1_kselftest-arm64
6675 11:36:43.580428 ++ cat uuid
6676 11:36:43.587221 + UUID=14864624_1.6.2.3.5
6677 11:36:43.587657 + set +x
6678 11:36:43.594090 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14864624_1.6.2.3.5>
6679 11:36:43.594766 Received signal: <STARTRUN> 1_kselftest-arm64 14864624_1.6.2.3.5
6680 11:36:43.595107 Starting test lava.1_kselftest-arm64 (14864624_1.6.2.3.5)
6681 11:36:43.595626 Skipping test definition patterns.
6682 11:36:43.597178 + cd ./automated/linux/kselftest/
6683 11:36:43.627083 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
6684 11:36:43.673642 INFO: install_deps skipped
6685 11:36:44.180753 --2024-07-17 11:36:35-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
6686 11:36:44.203046 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6687 11:36:44.337015 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6688 11:36:44.472960 HTTP request sent, awaiting response... 200 OK
6689 11:36:44.476996 Length: 1920476 (1.8M) [application/octet-stream]
6690 11:36:44.480101 Saving to: 'kselftest_armhf.tar.gz'
6691 11:36:44.480776
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6696 11:36:45.519696 kselftest_armhf.tar 45%[========> ] 853.82K 940KB/s
6697 11:36:45.526214 kselftest_armhf.tar 100%[===================>] 1.83M 1.75MB/s in 1.0s
6698 11:36:45.526640
6699 11:36:45.694882 2024-07-17 11:36:36 (1.75 MB/s) - 'kselftest_armhf.tar.gz' saved [1920476/1920476]
6700 11:36:45.695042
6701 11:36:52.743017 skiplist:
6702 11:36:52.746311 ========================================
6703 11:36:52.749573 ========================================
6704 11:36:52.801957 arm64:tags_test
6705 11:36:52.805615 arm64:run_tags_test.sh
6706 11:36:52.805997 arm64:fake_sigreturn_bad_magic
6707 11:36:52.808720 arm64:fake_sigreturn_bad_size
6708 11:36:52.811844 arm64:fake_sigreturn_bad_size_for_magic0
6709 11:36:52.815325 arm64:fake_sigreturn_duplicated_fpsimd
6710 11:36:52.818665 arm64:fake_sigreturn_misaligned_sp
6711 11:36:52.821660 arm64:fake_sigreturn_missing_fpsimd
6712 11:36:52.825267 arm64:fake_sigreturn_sme_change_vl
6713 11:36:52.828491 arm64:fake_sigreturn_sve_change_vl
6714 11:36:52.831787 arm64:mangle_pstate_invalid_compat_toggle
6715 11:36:52.835094 arm64:mangle_pstate_invalid_daif_bits
6716 11:36:52.838350 arm64:mangle_pstate_invalid_mode_el1h
6717 11:36:52.841751 arm64:mangle_pstate_invalid_mode_el1t
6718 11:36:52.845250 arm64:mangle_pstate_invalid_mode_el2h
6719 11:36:52.848665 arm64:mangle_pstate_invalid_mode_el2t
6720 11:36:52.855155 arm64:mangle_pstate_invalid_mode_el3h
6721 11:36:52.858356 arm64:mangle_pstate_invalid_mode_el3t
6722 11:36:52.858742 arm64:sme_trap_no_sm
6723 11:36:52.861774 arm64:sme_trap_non_streaming
6724 11:36:52.862160 arm64:sme_trap_za
6725 11:36:52.865210 arm64:sme_vl
6726 11:36:52.865595 arm64:ssve_regs
6727 11:36:52.868642 arm64:sve_regs
6728 11:36:52.869017 arm64:sve_vl
6729 11:36:52.869310 arm64:za_no_regs
6730 11:36:52.871736 arm64:za_regs
6731 11:36:52.872114 arm64:pac
6732 11:36:52.874936 arm64:fp-stress
6733 11:36:52.875331 arm64:sve-ptrace
6734 11:36:52.878242 arm64:sve-probe-vls
6735 11:36:52.878659 arm64:vec-syscfg
6736 11:36:52.879006 arm64:za-fork
6737 11:36:52.881985 arm64:za-ptrace
6738 11:36:52.884733 arm64:check_buffer_fill
6739 11:36:52.885117 arm64:check_child_memory
6740 11:36:52.888192 arm64:check_gcr_el1_cswitch
6741 11:36:52.891380 arm64:check_ksm_options
6742 11:36:52.891759 arm64:check_mmap_options
6743 11:36:52.895299 arm64:check_prctl
6744 11:36:52.898465 arm64:check_tags_inclusion
6745 11:36:52.898925 arm64:check_user_mem
6746 11:36:52.901895 arm64:btitest
6747 11:36:52.902354 arm64:nobtitest
6748 11:36:52.902652 arm64:hwcap
6749 11:36:52.904901 arm64:ptrace
6750 11:36:52.905281 arm64:syscall-abi
6751 11:36:52.908199 arm64:tpidr2
6752 11:36:52.911409 ============== Tests to run ===============
6753 11:36:52.911795 arm64:tags_test
6754 11:36:52.914576 arm64:run_tags_test.sh
6755 11:36:52.918438 arm64:fake_sigreturn_bad_magic
6756 11:36:52.921590 arm64:fake_sigreturn_bad_size
6757 11:36:52.924943 arm64:fake_sigreturn_bad_size_for_magic0
6758 11:36:52.928017 arm64:fake_sigreturn_duplicated_fpsimd
6759 11:36:52.931551 arm64:fake_sigreturn_misaligned_sp
6760 11:36:52.934699 arm64:fake_sigreturn_missing_fpsimd
6761 11:36:52.938004 arm64:fake_sigreturn_sme_change_vl
6762 11:36:52.941287 arm64:fake_sigreturn_sve_change_vl
6763 11:36:52.944868 arm64:mangle_pstate_invalid_compat_toggle
6764 11:36:52.947854 arm64:mangle_pstate_invalid_daif_bits
6765 11:36:52.951701 arm64:mangle_pstate_invalid_mode_el1h
6766 11:36:52.954467 arm64:mangle_pstate_invalid_mode_el1t
6767 11:36:52.957882 arm64:mangle_pstate_invalid_mode_el2h
6768 11:36:52.961400 arm64:mangle_pstate_invalid_mode_el2t
6769 11:36:52.964542 arm64:mangle_pstate_invalid_mode_el3h
6770 11:36:52.967722 arm64:mangle_pstate_invalid_mode_el3t
6771 11:36:52.968177 arm64:sme_trap_no_sm
6772 11:36:52.971166 arm64:sme_trap_non_streaming
6773 11:36:52.974066 arm64:sme_trap_za
6774 11:36:52.974450 arm64:sme_vl
6775 11:36:52.977763 arm64:ssve_regs
6776 11:36:52.978216 arm64:sve_regs
6777 11:36:52.978526 arm64:sve_vl
6778 11:36:52.981087 arm64:za_no_regs
6779 11:36:52.981506 arm64:za_regs
6780 11:36:52.981826 arm64:pac
6781 11:36:52.984334 arm64:fp-stress
6782 11:36:52.984755 arm64:sve-ptrace
6783 11:36:52.987644 arm64:sve-probe-vls
6784 11:36:52.988026 arm64:vec-syscfg
6785 11:36:52.991015 arm64:za-fork
6786 11:36:52.991482 arm64:za-ptrace
6787 11:36:52.994692 arm64:check_buffer_fill
6788 11:36:52.997634 arm64:check_child_memory
6789 11:36:52.998152 arm64:check_gcr_el1_cswitch
6790 11:36:53.000936 arm64:check_ksm_options
6791 11:36:53.004405 arm64:check_mmap_options
6792 11:36:53.004906 arm64:check_prctl
6793 11:36:53.007699 arm64:check_tags_inclusion
6794 11:36:53.010834 arm64:check_user_mem
6795 11:36:53.011223 arm64:btitest
6796 11:36:53.011522 arm64:nobtitest
6797 11:36:53.014300 arm64:hwcap
6798 11:36:53.014785 arm64:ptrace
6799 11:36:53.017184 arm64:syscall-abi
6800 11:36:53.017646 arm64:tpidr2
6801 11:36:53.020943 ===========End Tests to run ===============
6802 11:36:53.024169 shardfile-arm64 pass
6803 11:36:53.330869 <12>[ 30.246574] kselftest: Running tests in arm64
6804 11:36:53.344022 TAP version 13
6805 11:36:53.359178 1..48
6806 11:36:53.379944 # selftests: arm64: tags_test
6807 11:36:53.844195 ok 1 selftests: arm64: tags_test
6808 11:36:53.863760 # selftests: arm64: run_tags_test.sh
6809 11:36:53.934366 # --------------------
6810 11:36:53.937523 # running tags test
6811 11:36:53.937990 # --------------------
6812 11:36:53.940999 # [PASS]
6813 11:36:53.944247 ok 2 selftests: arm64: run_tags_test.sh
6814 11:36:53.960279 # selftests: arm64: fake_sigreturn_bad_magic
6815 11:36:54.037054 # Registered handlers for all signals.
6816 11:36:54.037573 # Detected MINSTKSIGSZ:4720
6817 11:36:54.040668 # Testcase initialized.
6818 11:36:54.043899 # uc context validated.
6819 11:36:54.047416 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6820 11:36:54.050895 # Handled SIG_COPYCTX
6821 11:36:54.051289 # Available space:3568
6822 11:36:54.056980 # Using badly built context - ERR: BAD MAGIC !
6823 11:36:54.063408 # SIG_OK -- SP:0xFFFFD8A5A620 si_addr@:0xffffd8a5a620 si_code:2 token@:0xffffd8a593c0 offset:-4704
6824 11:36:54.067067 # ==>> completed. PASS(1)
6825 11:36:54.073391 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
6826 11:36:54.079943 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD8A593C0
6827 11:36:54.087296 ok 3 selftests: arm64: fake_sigreturn_bad_magic
6828 11:36:54.090429 # selftests: arm64: fake_sigreturn_bad_size
6829 11:36:54.127432 # Registered handlers for all signals.
6830 11:36:54.127996 # Detected MINSTKSIGSZ:4720
6831 11:36:54.130960 # Testcase initialized.
6832 11:36:54.134144 # uc context validated.
6833 11:36:54.137414 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6834 11:36:54.140755 # Handled SIG_COPYCTX
6835 11:36:54.141341 # Available space:3568
6836 11:36:54.144124 # uc context validated.
6837 11:36:54.150953 # Using badly built context - ERR: Bad size for esr_context
6838 11:36:54.157459 # SIG_OK -- SP:0xFFFFCE18DCF0 si_addr@:0xffffce18dcf0 si_code:2 token@:0xffffce18ca90 offset:-4704
6839 11:36:54.160655 # ==>> completed. PASS(1)
6840 11:36:54.167360 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
6841 11:36:54.173924 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCE18CA90
6842 11:36:54.177266 ok 4 selftests: arm64: fake_sigreturn_bad_size
6843 11:36:54.184010 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
6844 11:36:54.224039 # Registered handlers for all signals.
6845 11:36:54.224641 # Detected MINSTKSIGSZ:4720
6846 11:36:54.227025 # Testcase initialized.
6847 11:36:54.230776 # uc context validated.
6848 11:36:54.233762 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6849 11:36:54.237075 # Handled SIG_COPYCTX
6850 11:36:54.237462 # Available space:3568
6851 11:36:54.244051 # Using badly built context - ERR: Bad size for terminator
6852 11:36:54.254100 # SIG_OK -- SP:0xFFFFD169B360 si_addr@:0xffffd169b360 si_code:2 token@:0xffffd169a100 offset:-4704
6853 11:36:54.254534 # ==>> completed. PASS(1)
6854 11:36:54.263790 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
6855 11:36:54.270585 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD169A100
6856 11:36:54.273609 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
6857 11:36:54.280081 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
6858 11:36:54.329900 # Registered handlers for all signals.
6859 11:36:54.330390 # Detected MINSTKSIGSZ:4720
6860 11:36:54.333170 # Testcase initialized.
6861 11:36:54.336446 # uc context validated.
6862 11:36:54.340133 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6863 11:36:54.343250 # Handled SIG_COPYCTX
6864 11:36:54.343635 # Available space:3568
6865 11:36:54.350169 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
6866 11:36:54.359605 # SIG_OK -- SP:0xFFFFCCA16CE0 si_addr@:0xffffcca16ce0 si_code:2 token@:0xffffcca15a80 offset:-4704
6867 11:36:54.359996 # ==>> completed. PASS(1)
6868 11:36:54.369689 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
6869 11:36:54.376402 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCCA15A80
6870 11:36:54.379857 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
6871 11:36:54.383415 # selftests: arm64: fake_sigreturn_misaligned_sp
6872 11:36:54.429653 # Registered handlers for all signals.
6873 11:36:54.430218 # Detected MINSTKSIGSZ:4720
6874 11:36:54.432856 # Testcase initialized.
6875 11:36:54.435970 # uc context validated.
6876 11:36:54.439804 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6877 11:36:54.442788 # Handled SIG_COPYCTX
6878 11:36:54.449173 # SIG_OK -- SP:0xFFFFE14C50E3 si_addr@:0xffffe14c50e3 si_code:2 token@:0xffffe14c50e3 offset:0
6879 11:36:54.452925 # ==>> completed. PASS(1)
6880 11:36:54.459504 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
6881 11:36:54.465835 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE14C50E3
6882 11:36:54.472508 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
6883 11:36:54.475934 # selftests: arm64: fake_sigreturn_missing_fpsimd
6884 11:36:54.509423 # Registered handlers for all signals.
6885 11:36:54.509929 # Detected MINSTKSIGSZ:4720
6886 11:36:54.512786 # Testcase initialized.
6887 11:36:54.515675 # uc context validated.
6888 11:36:54.519179 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6889 11:36:54.522037 # Handled SIG_COPYCTX
6890 11:36:54.525756 # Mangling template header. Spare space:4096
6891 11:36:54.528992 # Using badly built context - ERR: Missing FPSIMD
6892 11:36:54.538620 # SIG_OK -- SP:0xFFFFC49F80E0 si_addr@:0xffffc49f80e0 si_code:2 token@:0xffffc49f6e80 offset:-4704
6893 11:36:54.541888 # ==>> completed. PASS(1)
6894 11:36:54.548547 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
6895 11:36:54.556048 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC49F6E80
6896 11:36:54.558693 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
6897 11:36:54.565278 # selftests: arm64: fake_sigreturn_sme_change_vl
6898 11:36:54.607999 # Registered handlers for all signals.
6899 11:36:54.608556 # Detected MINSTKSIGSZ:4720
6900 11:36:54.611030 # ==>> completed. SKIP.
6901 11:36:54.617681 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
6902 11:36:54.621043 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
6903 11:36:54.631677 # selftests: arm64: fake_sigreturn_sve_change_vl
6904 11:36:54.712174 # Registered handlers for all signals.
6905 11:36:54.712756 # Detected MINSTKSIGSZ:4720
6906 11:36:54.715271 # ==>> completed. SKIP.
6907 11:36:54.722095 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
6908 11:36:54.725034 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
6909 11:36:54.737122 # selftests: arm64: mangle_pstate_invalid_compat_toggle
6910 11:36:54.794184 # Registered handlers for all signals.
6911 11:36:54.794680 # Detected MINSTKSIGSZ:4720
6912 11:36:54.797390 # Testcase initialized.
6913 11:36:54.800516 # uc context validated.
6914 11:36:54.800903 # Handled SIG_TRIG
6915 11:36:54.810472 # SIG_OK -- SP:0xFFFFD8A142D0 si_addr@:0xffffd8a142d0 si_code:2 token@:(nil) offset:-281474316190416
6916 11:36:54.813683 # ==>> completed. PASS(1)
6917 11:36:54.820740 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
6918 11:36:54.826979 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
6919 11:36:54.830648 # selftests: arm64: mangle_pstate_invalid_daif_bits
6920 11:36:54.874187 # Registered handlers for all signals.
6921 11:36:54.874710 # Detected MINSTKSIGSZ:4720
6922 11:36:54.877015 # Testcase initialized.
6923 11:36:54.880692 # uc context validated.
6924 11:36:54.881119 # Handled SIG_TRIG
6925 11:36:54.890406 # SIG_OK -- SP:0xFFFFDC201550 si_addr@:0xffffdc201550 si_code:2 token@:(nil) offset:-281474374833488
6926 11:36:54.893879 # ==>> completed. PASS(1)
6927 11:36:54.900181 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
6928 11:36:54.903631 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
6929 11:36:54.910105 # selftests: arm64: mangle_pstate_invalid_mode_el1h
6930 11:36:54.963694 # Registered handlers for all signals.
6931 11:36:54.964207 # Detected MINSTKSIGSZ:4720
6932 11:36:54.966841 # Testcase initialized.
6933 11:36:54.969936 # uc context validated.
6934 11:36:54.970363 # Handled SIG_TRIG
6935 11:36:54.980028 # SIG_OK -- SP:0xFFFFDEE3AB80 si_addr@:0xffffdee3ab80 si_code:2 token@:(nil) offset:-281474421205888
6936 11:36:54.982941 # ==>> completed. PASS(1)
6937 11:36:54.989546 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
6938 11:36:54.993036 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
6939 11:36:54.999439 # selftests: arm64: mangle_pstate_invalid_mode_el1t
6940 11:36:55.061692 # Registered handlers for all signals.
6941 11:36:55.062193 # Detected MINSTKSIGSZ:4720
6942 11:36:55.064725 # Testcase initialized.
6943 11:36:55.067826 # uc context validated.
6944 11:36:55.068258 # Handled SIG_TRIG
6945 11:36:55.077978 # SIG_OK -- SP:0xFFFFE8275E40 si_addr@:0xffffe8275e40 si_code:2 token@:(nil) offset:-281474576637504
6946 11:36:55.081207 # ==>> completed. PASS(1)
6947 11:36:55.087673 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
6948 11:36:55.091375 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
6949 11:36:55.097756 # selftests: arm64: mangle_pstate_invalid_mode_el2h
6950 11:36:55.174967 # Registered handlers for all signals.
6951 11:36:55.175673 # Detected MINSTKSIGSZ:4720
6952 11:36:55.178176 # Testcase initialized.
6953 11:36:55.181273 # uc context validated.
6954 11:36:55.181743 # Handled SIG_TRIG
6955 11:36:55.191293 # SIG_OK -- SP:0xFFFFF314D510 si_addr@:0xfffff314d510 si_code:2 token@:(nil) offset:-281474759972112
6956 11:36:55.195068 # ==>> completed. PASS(1)
6957 11:36:55.201649 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
6958 11:36:55.204665 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
6959 11:36:55.211478 # selftests: arm64: mangle_pstate_invalid_mode_el2t
6960 11:36:55.285660 # Registered handlers for all signals.
6961 11:36:55.286158 # Detected MINSTKSIGSZ:4720
6962 11:36:55.288362 # Testcase initialized.
6963 11:36:55.291922 # uc context validated.
6964 11:36:55.292311 # Handled SIG_TRIG
6965 11:36:55.301830 # SIG_OK -- SP:0xFFFFE12E2B10 si_addr@:0xffffe12e2b10 si_code:2 token@:(nil) offset:-281474459642640
6966 11:36:55.305078 # ==>> completed. PASS(1)
6967 11:36:55.311572 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
6968 11:36:55.315025 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
6969 11:36:55.321357 # selftests: arm64: mangle_pstate_invalid_mode_el3h
6970 11:36:55.386344 # Registered handlers for all signals.
6971 11:36:55.386842 # Detected MINSTKSIGSZ:4720
6972 11:36:55.389987 # Testcase initialized.
6973 11:36:55.393057 # uc context validated.
6974 11:36:55.393560 # Handled SIG_TRIG
6975 11:36:55.402960 # SIG_OK -- SP:0xFFFFD9AC3310 si_addr@:0xffffd9ac3310 si_code:2 token@:(nil) offset:-281474333684496
6976 11:36:55.406132 # ==>> completed. PASS(1)
6977 11:36:55.413035 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
6978 11:36:55.415996 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
6979 11:36:55.422779 # selftests: arm64: mangle_pstate_invalid_mode_el3t
6980 11:36:55.483953 # Registered handlers for all signals.
6981 11:36:55.484531 # Detected MINSTKSIGSZ:4720
6982 11:36:55.487322 # Testcase initialized.
6983 11:36:55.490394 # uc context validated.
6984 11:36:55.490819 # Handled SIG_TRIG
6985 11:36:55.500421 # SIG_OK -- SP:0xFFFFE84C2E70 si_addr@:0xffffe84c2e70 si_code:2 token@:(nil) offset:-281474579050096
6986 11:36:55.503875 # ==>> completed. PASS(1)
6987 11:36:55.510558 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
6988 11:36:55.513966 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
6989 11:36:55.517210 # selftests: arm64: sme_trap_no_sm
6990 11:36:55.578083 # Registered handlers for all signals.
6991 11:36:55.578630 # Detected MINSTKSIGSZ:4720
6992 11:36:55.581316 # ==>> completed. SKIP.
6993 11:36:55.591605 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
6994 11:36:55.594576 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
6995 11:36:55.602932 # selftests: arm64: sme_trap_non_streaming
6996 11:36:55.664549 # Registered handlers for all signals.
6997 11:36:55.665118 # Detected MINSTKSIGSZ:4720
6998 11:36:55.668070 # ==>> completed. SKIP.
6999 11:36:55.677989 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
7000 11:36:55.684601 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
7001 11:36:55.687796 # selftests: arm64: sme_trap_za
7002 11:36:55.771808 # Registered handlers for all signals.
7003 11:36:55.772370 # Detected MINSTKSIGSZ:4720
7004 11:36:55.775403 # Testcase initialized.
7005 11:36:55.784424 # SIG_OK -- SP:0xFFFFD430AFD0 si_addr@:0xaaaac51a2480 si_code:1 token@:(nil) offset:-187650427987072
7006 11:36:55.788024 # ==>> completed. PASS(1)
7007 11:36:55.794615 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
7008 11:36:55.797322 ok 21 selftests: arm64: sme_trap_za
7009 11:36:55.797398 # selftests: arm64: sme_vl
7010 11:36:55.845049 # Registered handlers for all signals.
7011 11:36:55.845310 # Detected MINSTKSIGSZ:4720
7012 11:36:55.848187 # ==>> completed. SKIP.
7013 11:36:55.855196 # # SME VL :: Check that we get the right SME VL reported
7014 11:36:55.858137 ok 22 selftests: arm64: sme_vl # SKIP
7015 11:36:55.864795 # selftests: arm64: ssve_regs
7016 11:36:55.941513 # Registered handlers for all signals.
7017 11:36:55.942064 # Detected MINSTKSIGSZ:4720
7018 11:36:55.944999 # ==>> completed. SKIP.
7019 11:36:55.954997 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
7020 11:36:55.957978 ok 23 selftests: arm64: ssve_regs # SKIP
7021 11:36:55.962999 # selftests: arm64: sve_regs
7022 11:36:56.042431 # Registered handlers for all signals.
7023 11:36:56.042951 # Detected MINSTKSIGSZ:4720
7024 11:36:56.045050 # ==>> completed. SKIP.
7025 11:36:56.052432 # # SVE registers :: Check that we get the right SVE registers reported
7026 11:36:56.055168 ok 24 selftests: arm64: sve_regs # SKIP
7027 11:36:56.063492 # selftests: arm64: sve_vl
7028 11:36:56.140618 # Registered handlers for all signals.
7029 11:36:56.141102 # Detected MINSTKSIGSZ:4720
7030 11:36:56.145203 # ==>> completed. SKIP.
7031 11:36:56.150760 # # SVE VL :: Check that we get the right SVE VL reported
7032 11:36:56.153428 ok 25 selftests: arm64: sve_vl # SKIP
7033 11:36:56.161833 # selftests: arm64: za_no_regs
7034 11:36:56.242762 # Registered handlers for all signals.
7035 11:36:56.243302 # Detected MINSTKSIGSZ:4720
7036 11:36:56.246107 # ==>> completed. SKIP.
7037 11:36:56.252931 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
7038 11:36:56.256252 ok 26 selftests: arm64: za_no_regs # SKIP
7039 11:36:56.263539 # selftests: arm64: za_regs
7040 11:36:56.335293 # Registered handlers for all signals.
7041 11:36:56.335797 # Detected MINSTKSIGSZ:4720
7042 11:36:56.338450 # ==>> completed. SKIP.
7043 11:36:56.345307 # # ZA register :: Check that we get the right ZA registers reported
7044 11:36:56.348449 ok 27 selftests: arm64: za_regs # SKIP
7045 11:36:56.357818 # selftests: arm64: pac
7046 11:36:56.431601 # TAP version 13
7047 11:36:56.432109 # 1..7
7048 11:36:56.435129 # # Starting 7 tests from 1 test cases.
7049 11:36:56.438311 # # RUN global.corrupt_pac ...
7050 11:36:56.441206 # # SKIP PAUTH not enabled
7051 11:36:56.444706 # # OK global.corrupt_pac
7052 11:36:56.448273 # ok 1 # SKIP PAUTH not enabled
7053 11:36:56.454141 # # RUN global.pac_instructions_not_nop ...
7054 11:36:56.457890 # # SKIP PAUTH not enabled
7055 11:36:56.461229 # # OK global.pac_instructions_not_nop
7056 11:36:56.464200 # ok 2 # SKIP PAUTH not enabled
7057 11:36:56.471105 # # RUN global.pac_instructions_not_nop_generic ...
7058 11:36:56.474698 # # SKIP Generic PAUTH not enabled
7059 11:36:56.477894 # # OK global.pac_instructions_not_nop_generic
7060 11:36:56.481000 # ok 3 # SKIP Generic PAUTH not enabled
7061 11:36:56.487520 # # RUN global.single_thread_different_keys ...
7062 11:36:56.491094 # # SKIP PAUTH not enabled
7063 11:36:56.494340 # # OK global.single_thread_different_keys
7064 11:36:56.497934 # ok 4 # SKIP PAUTH not enabled
7065 11:36:56.504215 # # RUN global.exec_changed_keys ...
7066 11:36:56.507681 # # SKIP PAUTH not enabled
7067 11:36:56.511408 # # OK global.exec_changed_keys
7068 11:36:56.514572 # ok 5 # SKIP PAUTH not enabled
7069 11:36:56.517783 # # RUN global.context_switch_keep_keys ...
7070 11:36:56.520777 # # SKIP PAUTH not enabled
7071 11:36:56.524182 # # OK global.context_switch_keep_keys
7072 11:36:56.527335 # ok 6 # SKIP PAUTH not enabled
7073 11:36:56.534030 # # RUN global.context_switch_keep_keys_generic ...
7074 11:36:56.537212 # # SKIP Generic PAUTH not enabled
7075 11:36:56.544078 # # OK global.context_switch_keep_keys_generic
7076 11:36:56.547881 # ok 7 # SKIP Generic PAUTH not enabled
7077 11:36:56.550869 # # PASSED: 7 / 7 tests passed.
7078 11:36:56.554656 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
7079 11:36:56.557808 ok 28 selftests: arm64: pac
7080 11:36:56.560530 # selftests: arm64: fp-stress
7081 11:37:01.075940 <6>[ 37.994971] vaux18: disabling
7082 11:37:01.079132 <6>[ 37.998347] vio28: disabling
7083 11:37:06.517768 # TAP version 13
7084 11:37:06.518188 # 1..16
7085 11:37:06.520773 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
7086 11:37:06.524624 # # Will run for 10s
7087 11:37:06.525114 # # Started FPSIMD-0-0
7088 11:37:06.527718 # # Started FPSIMD-0-1
7089 11:37:06.531095 # # Started FPSIMD-1-0
7090 11:37:06.531603 # # Started FPSIMD-1-1
7091 11:37:06.534614 # # Started FPSIMD-2-0
7092 11:37:06.535146 # # Started FPSIMD-2-1
7093 11:37:06.537842 # # Started FPSIMD-3-0
7094 11:37:06.540932 # # Started FPSIMD-3-1
7095 11:37:06.541374 # # Started FPSIMD-4-0
7096 11:37:06.544115 # # Started FPSIMD-4-1
7097 11:37:06.547199 # # Started FPSIMD-5-0
7098 11:37:06.547318 # # Started FPSIMD-5-1
7099 11:37:06.550336 # # Started FPSIMD-6-0
7100 11:37:06.553628 # # Started FPSIMD-6-1
7101 11:37:06.553738 # # Started FPSIMD-7-0
7102 11:37:06.557023 # # Started FPSIMD-7-1
7103 11:37:06.560291 # # FPSIMD-0-0: Vector length: 128 bits
7104 11:37:06.563511 # # FPSIMD-0-0: PID: 1185
7105 11:37:06.566846 # # FPSIMD-0-1: Vector length: 128 bits
7106 11:37:06.566957 # # FPSIMD-0-1: PID: 1186
7107 11:37:06.570587 # # FPSIMD-1-1: Vector length: 128 bits
7108 11:37:06.573828 # # FPSIMD-1-1: PID: 1188
7109 11:37:06.577003 # # FPSIMD-2-1: Vector length: 128 bits
7110 11:37:06.580139 # # FPSIMD-2-1: PID: 1190
7111 11:37:06.583424 # # FPSIMD-1-0: Vector length: 128 bits
7112 11:37:06.587148 # # FPSIMD-1-0: PID: 1187
7113 11:37:06.590305 # # FPSIMD-2-0: Vector length: 128 bits
7114 11:37:06.593515 # # FPSIMD-2-0: PID: 1189
7115 11:37:06.596964 # # FPSIMD-7-1: Vector length: 128 bits
7116 11:37:06.597128 # # FPSIMD-7-1: PID: 1200
7117 11:37:06.600609 # # FPSIMD-3-1: Vector length: 128 bits
7118 11:37:06.603581 # # FPSIMD-3-1: PID: 1192
7119 11:37:06.607068 # # FPSIMD-6-1: Vector length: 128 bits
7120 11:37:06.610194 # # FPSIMD-6-1: PID: 1198
7121 11:37:06.613545 # # FPSIMD-4-1: Vector length: 128 bits
7122 11:37:06.616799 # # FPSIMD-4-1: PID: 1194
7123 11:37:06.620587 # # FPSIMD-5-1: Vector length: 128 bits
7124 11:37:06.620885 # # FPSIMD-5-1: PID: 1196
7125 11:37:06.627326 # # FPSIMD-7-0: Vector length: 128 bits
7126 11:37:06.627576 # # FPSIMD-7-0: PID: 1199
7127 11:37:06.630231 # # FPSIMD-4-0: Vector length: 128 bits
7128 11:37:06.633902 # # FPSIMD-4-0: PID: 1193
7129 11:37:06.636906 # # FPSIMD-6-0: Vector length: 128 bits
7130 11:37:06.640413 # # FPSIMD-6-0: PID: 1197
7131 11:37:06.643542 # # FPSIMD-3-0: Vector length: 128 bits
7132 11:37:06.647123 # # FPSIMD-3-0: PID: 1191
7133 11:37:06.650147 # # FPSIMD-5-0: Vector length: 128 bits
7134 11:37:06.650226 # # FPSIMD-5-0: PID: 1195
7135 11:37:06.653752 # # Finishing up...
7136 11:37:06.660192 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=821694, signals=10
7137 11:37:06.666603 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=803668, signals=10
7138 11:37:06.673302 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=756205, signals=10
7139 11:37:06.683377 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=774855, signals=10
7140 11:37:06.690032 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=989990, signals=10
7141 11:37:06.696430 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=839718, signals=10
7142 11:37:06.703275 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=692859, signals=10
7143 11:37:06.706960 # ok 1 FPSIMD-0-0
7144 11:37:06.707289 # ok 2 FPSIMD-0-1
7145 11:37:06.710342 # ok 3 FPSIMD-1-0
7146 11:37:06.710670 # ok 4 FPSIMD-1-1
7147 11:37:06.713537 # ok 5 FPSIMD-2-0
7148 11:37:06.714236 # ok 6 FPSIMD-2-1
7149 11:37:06.716672 # ok 7 FPSIMD-3-0
7150 11:37:06.717135 # ok 8 FPSIMD-3-1
7151 11:37:06.720340 # ok 9 FPSIMD-4-0
7152 11:37:06.720799 # ok 10 FPSIMD-4-1
7153 11:37:06.723744 # ok 11 FPSIMD-5-0
7154 11:37:06.724124 # ok 12 FPSIMD-5-1
7155 11:37:06.726684 # ok 13 FPSIMD-6-0
7156 11:37:06.727131 # ok 14 FPSIMD-6-1
7157 11:37:06.730256 # ok 15 FPSIMD-7-0
7158 11:37:06.730756 # ok 16 FPSIMD-7-1
7159 11:37:06.736950 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=768719, signals=9
7160 11:37:06.747231 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=672858, signals=10
7161 11:37:06.753621 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=717553, signals=10
7162 11:37:06.759751 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=705348, signals=10
7163 11:37:06.766536 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=862251, signals=9
7164 11:37:06.773248 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=701668, signals=10
7165 11:37:06.780213 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=835685, signals=10
7166 11:37:06.786643 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1167649, signals=10
7167 11:37:06.796595 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=748878, signals=9
7168 11:37:06.799708 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
7169 11:37:06.802969 ok 29 selftests: arm64: fp-stress
7170 11:37:06.806651 # selftests: arm64: sve-ptrace
7171 11:37:06.807057 # TAP version 13
7172 11:37:06.809855 # 1..4104
7173 11:37:06.810297 # ok 2 # SKIP SVE not available
7174 11:37:06.816978 # # Planned tests != run tests (4104 != 1)
7175 11:37:06.819925 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7176 11:37:06.823223 ok 30 selftests: arm64: sve-ptrace # SKIP
7177 11:37:06.826512 # selftests: arm64: sve-probe-vls
7178 11:37:06.829939 # TAP version 13
7179 11:37:06.830326 # 1..2
7180 11:37:06.833266 # ok 2 # SKIP SVE not available
7181 11:37:06.836562 # # Planned tests != run tests (2 != 1)
7182 11:37:06.840503 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7183 11:37:06.846430 ok 31 selftests: arm64: sve-probe-vls # SKIP
7184 11:37:06.846847 # selftests: arm64: vec-syscfg
7185 11:37:06.850384 # TAP version 13
7186 11:37:06.850789 # 1..20
7187 11:37:06.853475 # ok 1 # SKIP SVE not supported
7188 11:37:06.856339 # ok 2 # SKIP SVE not supported
7189 11:37:06.859949 # ok 3 # SKIP SVE not supported
7190 11:37:06.862983 # ok 4 # SKIP SVE not supported
7191 11:37:06.866510 # ok 5 # SKIP SVE not supported
7192 11:37:06.866923 # ok 6 # SKIP SVE not supported
7193 11:37:06.869604 # ok 7 # SKIP SVE not supported
7194 11:37:06.872934 # ok 8 # SKIP SVE not supported
7195 11:37:06.876568 # ok 9 # SKIP SVE not supported
7196 11:37:06.879677 # ok 10 # SKIP SVE not supported
7197 11:37:06.882878 # ok 11 # SKIP SME not supported
7198 11:37:06.886150 # ok 12 # SKIP SME not supported
7199 11:37:06.889380 # ok 13 # SKIP SME not supported
7200 11:37:06.889856 # ok 14 # SKIP SME not supported
7201 11:37:06.892956 # ok 15 # SKIP SME not supported
7202 11:37:06.896406 # ok 16 # SKIP SME not supported
7203 11:37:06.900128 # ok 17 # SKIP SME not supported
7204 11:37:06.903227 # ok 18 # SKIP SME not supported
7205 11:37:06.906458 # ok 19 # SKIP SME not supported
7206 11:37:06.909873 # ok 20 # SKIP SME not supported
7207 11:37:06.912647 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
7208 11:37:06.916132 ok 32 selftests: arm64: vec-syscfg
7209 11:37:06.919287 # selftests: arm64: za-fork
7210 11:37:06.943860 # TAP version 13
7211 11:37:06.944319 # 1..1
7212 11:37:06.946851 # # PID: 1277
7213 11:37:06.947264 # # SME support not present
7214 11:37:06.950622 # ok 0 skipped
7215 11:37:06.953718 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7216 11:37:06.956651 ok 33 selftests: arm64: za-fork
7217 11:37:06.968052 # selftests: arm64: za-ptrace
7218 11:37:07.014340 # TAP version 13
7219 11:37:07.014777 # 1..1
7220 11:37:07.017296 # ok 2 # SKIP SME not available
7221 11:37:07.023891 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7222 11:37:07.027468 ok 34 selftests: arm64: za-ptrace # SKIP
7223 11:37:07.037536 # selftests: arm64: check_buffer_fill
7224 11:37:07.114770 # # SKIP: MTE features unavailable
7225 11:37:07.123231 ok 35 selftests: arm64: check_buffer_fill # SKIP
7226 11:37:07.144156 # selftests: arm64: check_child_memory
7227 11:37:07.220345 # # SKIP: MTE features unavailable
7228 11:37:07.229361 ok 36 selftests: arm64: check_child_memory # SKIP
7229 11:37:07.250939 # selftests: arm64: check_gcr_el1_cswitch
7230 11:37:07.331014 # # SKIP: MTE features unavailable
7231 11:37:07.339166 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
7232 11:37:07.357200 # selftests: arm64: check_ksm_options
7233 11:37:07.438682 # # SKIP: MTE features unavailable
7234 11:37:07.447223 ok 38 selftests: arm64: check_ksm_options # SKIP
7235 11:37:07.463837 # selftests: arm64: check_mmap_options
7236 11:37:07.526316 # # SKIP: MTE features unavailable
7237 11:37:07.535181 ok 39 selftests: arm64: check_mmap_options # SKIP
7238 11:37:07.549944 # selftests: arm64: check_prctl
7239 11:37:07.637950 # TAP version 13
7240 11:37:07.638417 # 1..5
7241 11:37:07.641736 # ok 1 check_basic_read
7242 11:37:07.642209 # ok 2 NONE
7243 11:37:07.644684 # ok 3 # SKIP SYNC
7244 11:37:07.645073 # ok 4 # SKIP ASYNC
7245 11:37:07.647466 # ok 5 # SKIP SYNC+ASYNC
7246 11:37:07.650650 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
7247 11:37:07.654074 ok 40 selftests: arm64: check_prctl
7248 11:37:07.664721 # selftests: arm64: check_tags_inclusion
7249 11:37:07.733162 # # SKIP: MTE features unavailable
7250 11:37:07.741304 ok 41 selftests: arm64: check_tags_inclusion # SKIP
7251 11:37:07.754969 # selftests: arm64: check_user_mem
7252 11:37:07.848875 # # SKIP: MTE features unavailable
7253 11:37:07.857158 ok 42 selftests: arm64: check_user_mem # SKIP
7254 11:37:07.872375 # selftests: arm64: btitest
7255 11:37:07.952359 # TAP version 13
7256 11:37:07.952965 # 1..18
7257 11:37:07.955493 # # HWCAP_PACA not present
7258 11:37:07.958617 # # HWCAP2_BTI not present
7259 11:37:07.959037 # # Test binary built for BTI
7260 11:37:07.965752 # ok 1 nohint_func/call_using_br_x0 # SKIP
7261 11:37:07.968961 # ok 1 nohint_func/call_using_br_x16 # SKIP
7262 11:37:07.972570 # ok 1 nohint_func/call_using_blr # SKIP
7263 11:37:07.976003 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7264 11:37:07.979117 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7265 11:37:07.982040 # ok 1 bti_none_func/call_using_blr # SKIP
7266 11:37:07.988780 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7267 11:37:07.992024 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7268 11:37:07.995961 # ok 1 bti_c_func/call_using_blr # SKIP
7269 11:37:07.998654 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7270 11:37:08.002659 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7271 11:37:08.005514 # ok 1 bti_j_func/call_using_blr # SKIP
7272 11:37:08.008820 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7273 11:37:08.012058 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7274 11:37:08.018863 # ok 1 bti_jc_func/call_using_blr # SKIP
7275 11:37:08.022710 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7276 11:37:08.025359 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7277 11:37:08.028528 # ok 1 paciasp_func/call_using_blr # SKIP
7278 11:37:08.035571 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7279 11:37:08.038386 # # WARNING - EXPECTED TEST COUNT WRONG
7280 11:37:08.041804 ok 43 selftests: arm64: btitest
7281 11:37:08.042192 # selftests: arm64: nobtitest
7282 11:37:08.045322 # TAP version 13
7283 11:37:08.045709 # 1..18
7284 11:37:08.048301 # # HWCAP_PACA not present
7285 11:37:08.052136 # # HWCAP2_BTI not present
7286 11:37:08.055085 # # Test binary not built for BTI
7287 11:37:08.058539 # ok 1 nohint_func/call_using_br_x0 # SKIP
7288 11:37:08.061917 # ok 1 nohint_func/call_using_br_x16 # SKIP
7289 11:37:08.065409 # ok 1 nohint_func/call_using_blr # SKIP
7290 11:37:08.068693 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7291 11:37:08.071584 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7292 11:37:08.078057 # ok 1 bti_none_func/call_using_blr # SKIP
7293 11:37:08.081647 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7294 11:37:08.084925 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7295 11:37:08.088431 # ok 1 bti_c_func/call_using_blr # SKIP
7296 11:37:08.091366 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7297 11:37:08.094806 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7298 11:37:08.098086 # ok 1 bti_j_func/call_using_blr # SKIP
7299 11:37:08.101238 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7300 11:37:08.108245 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7301 11:37:08.111396 # ok 1 bti_jc_func/call_using_blr # SKIP
7302 11:37:08.115144 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7303 11:37:08.118388 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7304 11:37:08.121537 # ok 1 paciasp_func/call_using_blr # SKIP
7305 11:37:08.128670 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7306 11:37:08.131660 # # WARNING - EXPECTED TEST COUNT WRONG
7307 11:37:08.134810 ok 44 selftests: arm64: nobtitest
7308 11:37:08.135211 # selftests: arm64: hwcap
7309 11:37:08.138662 # TAP version 13
7310 11:37:08.139177 # 1..28
7311 11:37:08.141394 # ok 1 cpuinfo_match_RNG
7312 11:37:08.144922 # # SIGILL reported for RNG
7313 11:37:08.145388 # ok 2 # SKIP sigill_RNG
7314 11:37:08.148195 # ok 3 cpuinfo_match_SME
7315 11:37:08.148666 # ok 4 sigill_SME
7316 11:37:08.151252 # ok 5 cpuinfo_match_SVE
7317 11:37:08.154711 # ok 6 sigill_SVE
7318 11:37:08.155108 # ok 7 cpuinfo_match_SVE 2
7319 11:37:08.157799 # # SIGILL reported for SVE 2
7320 11:37:08.161165 # ok 8 # SKIP sigill_SVE 2
7321 11:37:08.164758 # ok 9 cpuinfo_match_SVE AES
7322 11:37:08.167960 # # SIGILL reported for SVE AES
7323 11:37:08.168594 # ok 10 # SKIP sigill_SVE AES
7324 11:37:08.171069 # ok 11 cpuinfo_match_SVE2 PMULL
7325 11:37:08.174723 # # SIGILL reported for SVE2 PMULL
7326 11:37:08.177780 # ok 12 # SKIP sigill_SVE2 PMULL
7327 11:37:08.180868 # ok 13 cpuinfo_match_SVE2 BITPERM
7328 11:37:08.184277 # # SIGILL reported for SVE2 BITPERM
7329 11:37:08.187928 # ok 14 # SKIP sigill_SVE2 BITPERM
7330 11:37:08.191258 # ok 15 cpuinfo_match_SVE2 SHA3
7331 11:37:08.194801 # # SIGILL reported for SVE2 SHA3
7332 11:37:08.198092 # ok 16 # SKIP sigill_SVE2 SHA3
7333 11:37:08.198474 # ok 17 cpuinfo_match_SVE2 SM4
7334 11:37:08.200981 # # SIGILL reported for SVE2 SM4
7335 11:37:08.204520 # ok 18 # SKIP sigill_SVE2 SM4
7336 11:37:08.207963 # ok 19 cpuinfo_match_SVE2 I8MM
7337 11:37:08.211148 # # SIGILL reported for SVE2 I8MM
7338 11:37:08.214645 # ok 20 # SKIP sigill_SVE2 I8MM
7339 11:37:08.218216 # ok 21 cpuinfo_match_SVE2 F32MM
7340 11:37:08.221020 # # SIGILL reported for SVE2 F32MM
7341 11:37:08.224617 # ok 22 # SKIP sigill_SVE2 F32MM
7342 11:37:08.224999 # ok 23 cpuinfo_match_SVE2 F64MM
7343 11:37:08.228040 # # SIGILL reported for SVE2 F64MM
7344 11:37:08.231413 # ok 24 # SKIP sigill_SVE2 F64MM
7345 11:37:08.234751 # ok 25 cpuinfo_match_SVE2 BF16
7346 11:37:08.237719 # # SIGILL reported for SVE2 BF16
7347 11:37:08.241086 # ok 26 # SKIP sigill_SVE2 BF16
7348 11:37:08.244272 # ok 27 cpuinfo_match_SVE2 EBF16
7349 11:37:08.247636 # ok 28 # SKIP sigill_SVE2 EBF16
7350 11:37:08.250681 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
7351 11:37:08.254290 ok 45 selftests: arm64: hwcap
7352 11:37:08.257724 # selftests: arm64: ptrace
7353 11:37:08.258106 # TAP version 13
7354 11:37:08.260616 # 1..7
7355 11:37:08.261069 # # Parent is 1519, child is 1520
7356 11:37:08.263911 # ok 1 read_tpidr_one
7357 11:37:08.267568 # ok 2 write_tpidr_one
7358 11:37:08.268057 # ok 3 verify_tpidr_one
7359 11:37:08.270392 # ok 4 count_tpidrs
7360 11:37:08.270786 # ok 5 tpidr2_write
7361 11:37:08.274083 # ok 6 tpidr2_read
7362 11:37:08.276865 # ok 7 write_tpidr_only
7363 11:37:08.280345 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
7364 11:37:08.283859 ok 46 selftests: arm64: ptrace
7365 11:37:08.286883 # selftests: arm64: syscall-abi
7366 11:37:08.337935 # TAP version 13
7367 11:37:08.338363 # 1..2
7368 11:37:08.341758 # ok 1 getpid() FPSIMD
7369 11:37:08.345132 # ok 2 sched_yield() FPSIMD
7370 11:37:08.348349 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
7371 11:37:08.351511 ok 47 selftests: arm64: syscall-abi
7372 11:37:08.359206 # selftests: arm64: tpidr2
7373 11:37:08.443606 # Segmentation fault
7374 11:37:08.452129 not ok 48 selftests: arm64: tpidr2 # exit=139
7375 11:37:10.108747 arm64_tags_test pass
7376 11:37:10.111589 arm64_run_tags_test_sh pass
7377 11:37:10.115043 arm64_fake_sigreturn_bad_magic pass
7378 11:37:10.118871 arm64_fake_sigreturn_bad_size pass
7379 11:37:10.121425 arm64_fake_sigreturn_bad_size_for_magic0 pass
7380 11:37:10.125146 arm64_fake_sigreturn_duplicated_fpsimd pass
7381 11:37:10.128333 arm64_fake_sigreturn_misaligned_sp pass
7382 11:37:10.131331 arm64_fake_sigreturn_missing_fpsimd pass
7383 11:37:10.134926 arm64_fake_sigreturn_sme_change_vl skip
7384 11:37:10.141502 arm64_fake_sigreturn_sve_change_vl skip
7385 11:37:10.145384 arm64_mangle_pstate_invalid_compat_toggle pass
7386 11:37:10.148360 arm64_mangle_pstate_invalid_daif_bits pass
7387 11:37:10.151826 arm64_mangle_pstate_invalid_mode_el1h pass
7388 11:37:10.154907 arm64_mangle_pstate_invalid_mode_el1t pass
7389 11:37:10.161861 arm64_mangle_pstate_invalid_mode_el2h pass
7390 11:37:10.164629 arm64_mangle_pstate_invalid_mode_el2t pass
7391 11:37:10.167818 arm64_mangle_pstate_invalid_mode_el3h pass
7392 11:37:10.171588 arm64_mangle_pstate_invalid_mode_el3t pass
7393 11:37:10.174692 arm64_sme_trap_no_sm skip
7394 11:37:10.178230 arm64_sme_trap_non_streaming skip
7395 11:37:10.178639 arm64_sme_trap_za pass
7396 11:37:10.181808 arm64_sme_vl skip
7397 11:37:10.182263 arm64_ssve_regs skip
7398 11:37:10.184709 arm64_sve_regs skip
7399 11:37:10.188047 arm64_sve_vl skip
7400 11:37:10.188509 arm64_za_no_regs skip
7401 11:37:10.191644 arm64_za_regs skip
7402 11:37:10.194679 arm64_pac_PAUTH_not_enabled skip
7403 11:37:10.198121 arm64_pac_PAUTH_not_enabled_dup2 skip
7404 11:37:10.201518 arm64_pac_Generic_PAUTH_not_enabled skip
7405 11:37:10.204747 arm64_pac_PAUTH_not_enabled_dup3 skip
7406 11:37:10.207989 arm64_pac_PAUTH_not_enabled_dup4 skip
7407 11:37:10.211823 arm64_pac_PAUTH_not_enabled_dup5 skip
7408 11:37:10.214747 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
7409 11:37:10.215246 arm64_pac pass
7410 11:37:10.217958 arm64_fp-stress_FPSIMD-0-0 pass
7411 11:37:10.221091 arm64_fp-stress_FPSIMD-0-1 pass
7412 11:37:10.224885 arm64_fp-stress_FPSIMD-1-0 pass
7413 11:37:10.227911 arm64_fp-stress_FPSIMD-1-1 pass
7414 11:37:10.230963 arm64_fp-stress_FPSIMD-2-0 pass
7415 11:37:10.234632 arm64_fp-stress_FPSIMD-2-1 pass
7416 11:37:10.237844 arm64_fp-stress_FPSIMD-3-0 pass
7417 11:37:10.241016 arm64_fp-stress_FPSIMD-3-1 pass
7418 11:37:10.241423 arm64_fp-stress_FPSIMD-4-0 pass
7419 11:37:10.244521 arm64_fp-stress_FPSIMD-4-1 pass
7420 11:37:10.248226 arm64_fp-stress_FPSIMD-5-0 pass
7421 11:37:10.250859 arm64_fp-stress_FPSIMD-5-1 pass
7422 11:37:10.254295 arm64_fp-stress_FPSIMD-6-0 pass
7423 11:37:10.257581 arm64_fp-stress_FPSIMD-6-1 pass
7424 11:37:10.261079 arm64_fp-stress_FPSIMD-7-0 pass
7425 11:37:10.264637 arm64_fp-stress_FPSIMD-7-1 pass
7426 11:37:10.265041 arm64_fp-stress pass
7427 11:37:10.268011 arm64_sve-ptrace_SVE_not_available skip
7428 11:37:10.271196 arm64_sve-ptrace skip
7429 11:37:10.274974 arm64_sve-probe-vls_SVE_not_available skip
7430 11:37:10.277852 arm64_sve-probe-vls skip
7431 11:37:10.281222 arm64_vec-syscfg_SVE_not_supported skip
7432 11:37:10.284561 arm64_vec-syscfg_SVE_not_supported_dup2 skip
7433 11:37:10.291296 arm64_vec-syscfg_SVE_not_supported_dup3 skip
7434 11:37:10.294956 arm64_vec-syscfg_SVE_not_supported_dup4 skip
7435 11:37:10.298276 arm64_vec-syscfg_SVE_not_supported_dup5 skip
7436 11:37:10.301548 arm64_vec-syscfg_SVE_not_supported_dup6 skip
7437 11:37:10.304627 arm64_vec-syscfg_SVE_not_supported_dup7 skip
7438 11:37:10.310999 arm64_vec-syscfg_SVE_not_supported_dup8 skip
7439 11:37:10.314691 arm64_vec-syscfg_SVE_not_supported_dup9 skip
7440 11:37:10.317613 arm64_vec-syscfg_SVE_not_supported_dup10 skip
7441 11:37:10.321265 arm64_vec-syscfg_SME_not_supported skip
7442 11:37:10.328065 arm64_vec-syscfg_SME_not_supported_dup2 skip
7443 11:37:10.331177 arm64_vec-syscfg_SME_not_supported_dup3 skip
7444 11:37:10.334225 arm64_vec-syscfg_SME_not_supported_dup4 skip
7445 11:37:10.338078 arm64_vec-syscfg_SME_not_supported_dup5 skip
7446 11:37:10.344107 arm64_vec-syscfg_SME_not_supported_dup6 skip
7447 11:37:10.347340 arm64_vec-syscfg_SME_not_supported_dup7 skip
7448 11:37:10.351179 arm64_vec-syscfg_SME_not_supported_dup8 skip
7449 11:37:10.354144 arm64_vec-syscfg_SME_not_supported_dup9 skip
7450 11:37:10.360745 arm64_vec-syscfg_SME_not_supported_dup10 skip
7451 11:37:10.361131 arm64_vec-syscfg pass
7452 11:37:10.364420 arm64_za-fork_skipped pass
7453 11:37:10.367633 arm64_za-fork pass
7454 11:37:10.371346 arm64_za-ptrace_SME_not_available skip
7455 11:37:10.371832 arm64_za-ptrace skip
7456 11:37:10.374287 arm64_check_buffer_fill skip
7457 11:37:10.377445 arm64_check_child_memory skip
7458 11:37:10.380773 arm64_check_gcr_el1_cswitch skip
7459 11:37:10.384263 arm64_check_ksm_options skip
7460 11:37:10.384778 arm64_check_mmap_options skip
7461 11:37:10.390638 arm64_check_prctl_check_basic_read pass
7462 11:37:10.391020 arm64_check_prctl_NONE pass
7463 11:37:10.394592 arm64_check_prctl_SYNC skip
7464 11:37:10.397687 arm64_check_prctl_ASYNC skip
7465 11:37:10.401439 arm64_check_prctl_SYNC_ASYNC skip
7466 11:37:10.401901 arm64_check_prctl pass
7467 11:37:10.404491 arm64_check_tags_inclusion skip
7468 11:37:10.407274 arm64_check_user_mem skip
7469 11:37:10.411075 arm64_btitest_nohint_func_call_using_br_x0 skip
7470 11:37:10.417285 arm64_btitest_nohint_func_call_using_br_x16 skip
7471 11:37:10.420668 arm64_btitest_nohint_func_call_using_blr skip
7472 11:37:10.424156 arm64_btitest_bti_none_func_call_using_br_x0 skip
7473 11:37:10.430712 arm64_btitest_bti_none_func_call_using_br_x16 skip
7474 11:37:10.433872 arm64_btitest_bti_none_func_call_using_blr skip
7475 11:37:10.437084 arm64_btitest_bti_c_func_call_using_br_x0 skip
7476 11:37:10.443671 arm64_btitest_bti_c_func_call_using_br_x16 skip
7477 11:37:10.447143 arm64_btitest_bti_c_func_call_using_blr skip
7478 11:37:10.450400 arm64_btitest_bti_j_func_call_using_br_x0 skip
7479 11:37:10.453771 arm64_btitest_bti_j_func_call_using_br_x16 skip
7480 11:37:10.460336 arm64_btitest_bti_j_func_call_using_blr skip
7481 11:37:10.463358 arm64_btitest_bti_jc_func_call_using_br_x0 skip
7482 11:37:10.466727 arm64_btitest_bti_jc_func_call_using_br_x16 skip
7483 11:37:10.473749 arm64_btitest_bti_jc_func_call_using_blr skip
7484 11:37:10.476897 arm64_btitest_paciasp_func_call_using_br_x0 skip
7485 11:37:10.480515 arm64_btitest_paciasp_func_call_using_br_x16 skip
7486 11:37:10.483486 arm64_btitest_paciasp_func_call_using_blr skip
7487 11:37:10.486755 arm64_btitest pass
7488 11:37:10.490561 arm64_nobtitest_nohint_func_call_using_br_x0 skip
7489 11:37:10.497210 arm64_nobtitest_nohint_func_call_using_br_x16 skip
7490 11:37:10.500087 arm64_nobtitest_nohint_func_call_using_blr skip
7491 11:37:10.503680 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
7492 11:37:10.510342 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
7493 11:37:10.513455 arm64_nobtitest_bti_none_func_call_using_blr skip
7494 11:37:10.516572 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
7495 11:37:10.523537 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
7496 11:37:10.526842 arm64_nobtitest_bti_c_func_call_using_blr skip
7497 11:37:10.530425 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
7498 11:37:10.536992 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
7499 11:37:10.540082 arm64_nobtitest_bti_j_func_call_using_blr skip
7500 11:37:10.543419 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
7501 11:37:10.550736 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
7502 11:37:10.553608 arm64_nobtitest_bti_jc_func_call_using_blr skip
7503 11:37:10.556715 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
7504 11:37:10.563006 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
7505 11:37:10.566776 arm64_nobtitest_paciasp_func_call_using_blr skip
7506 11:37:10.570293 arm64_nobtitest pass
7507 11:37:10.570725 arm64_hwcap_cpuinfo_match_RNG pass
7508 11:37:10.573176 arm64_hwcap_sigill_RNG skip
7509 11:37:10.576621 arm64_hwcap_cpuinfo_match_SME pass
7510 11:37:10.579925 arm64_hwcap_sigill_SME pass
7511 11:37:10.583073 arm64_hwcap_cpuinfo_match_SVE pass
7512 11:37:10.586817 arm64_hwcap_sigill_SVE pass
7513 11:37:10.589981 arm64_hwcap_cpuinfo_match_SVE_2 pass
7514 11:37:10.590367 arm64_hwcap_sigill_SVE_2 skip
7515 11:37:10.593522 arm64_hwcap_cpuinfo_match_SVE_AES pass
7516 11:37:10.596300 arm64_hwcap_sigill_SVE_AES skip
7517 11:37:10.599551 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
7518 11:37:10.603144 arm64_hwcap_sigill_SVE2_PMULL skip
7519 11:37:10.609459 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
7520 11:37:10.612839 arm64_hwcap_sigill_SVE2_BITPERM skip
7521 11:37:10.616224 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
7522 11:37:10.619732 arm64_hwcap_sigill_SVE2_SHA3 skip
7523 11:37:10.622983 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
7524 11:37:10.626264 arm64_hwcap_sigill_SVE2_SM4 skip
7525 11:37:10.629222 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
7526 11:37:10.632642 arm64_hwcap_sigill_SVE2_I8MM skip
7527 11:37:10.636268 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
7528 11:37:10.639210 arm64_hwcap_sigill_SVE2_F32MM skip
7529 11:37:10.642695 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
7530 11:37:10.645593 arm64_hwcap_sigill_SVE2_F64MM skip
7531 11:37:10.649045 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
7532 11:37:10.652581 arm64_hwcap_sigill_SVE2_BF16 skip
7533 11:37:10.655859 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
7534 11:37:10.658948 arm64_hwcap_sigill_SVE2_EBF16 skip
7535 11:37:10.659032 arm64_hwcap pass
7536 11:37:10.662207 arm64_ptrace_read_tpidr_one pass
7537 11:37:10.665923 arm64_ptrace_write_tpidr_one pass
7538 11:37:10.669076 arm64_ptrace_verify_tpidr_one pass
7539 11:37:10.672309 arm64_ptrace_count_tpidrs pass
7540 11:37:10.675845 arm64_ptrace_tpidr2_write pass
7541 11:37:10.678969 arm64_ptrace_tpidr2_read pass
7542 11:37:10.679052 arm64_ptrace_write_tpidr_only pass
7543 11:37:10.682262 arm64_ptrace pass
7544 11:37:10.685655 arm64_syscall-abi_getpid_FPSIMD pass
7545 11:37:10.689135 arm64_syscall-abi_sched_yield_FPSIMD pass
7546 11:37:10.692611 arm64_syscall-abi pass
7547 11:37:10.692992 arm64_tpidr2 fail
7548 11:37:10.699337 + ../../utils/send-to-lava.sh ./output/result.txt
7549 11:37:10.702120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
7550 11:37:10.702401 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
7552 11:37:10.709145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
7553 11:37:10.709397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
7555 11:37:10.715455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
7556 11:37:10.715711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
7558 11:37:10.722059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
7559 11:37:10.722312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
7561 11:37:10.729042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
7562 11:37:10.729301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
7564 11:37:10.767377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
7565 11:37:10.767652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
7567 11:37:10.819269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
7568 11:37:10.819897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
7570 11:37:10.865848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
7571 11:37:10.866153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
7573 11:37:10.904383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
7574 11:37:10.904675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
7576 11:37:10.940369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
7577 11:37:10.940670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
7579 11:37:10.981058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
7580 11:37:10.981337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
7582 11:37:11.027487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
7583 11:37:11.027967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
7585 11:37:11.073456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
7586 11:37:11.073803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
7588 11:37:11.122176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
7589 11:37:11.122441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
7591 11:37:11.164182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
7592 11:37:11.164481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
7594 11:37:11.209797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
7595 11:37:11.210096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
7597 11:37:11.254411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
7598 11:37:11.255044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
7600 11:37:11.302809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
7601 11:37:11.303116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
7603 11:37:11.348040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
7604 11:37:11.348296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
7606 11:37:11.390781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
7607 11:37:11.391121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
7609 11:37:11.437692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
7611 11:37:11.441111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
7612 11:37:11.481298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
7613 11:37:11.481598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
7615 11:37:11.531508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
7616 11:37:11.531771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
7618 11:37:11.580003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
7619 11:37:11.580318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
7621 11:37:11.625756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
7622 11:37:11.626077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
7624 11:37:11.670079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
7625 11:37:11.670341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
7627 11:37:11.711438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
7628 11:37:11.711693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
7630 11:37:11.756963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
7631 11:37:11.757223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
7633 11:37:11.802647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
7635 11:37:11.805841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
7636 11:37:11.855266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
7637 11:37:11.855590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
7639 11:37:11.900262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
7640 11:37:11.900575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
7642 11:37:11.941118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
7643 11:37:11.941389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
7645 11:37:11.977864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
7646 11:37:11.978666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
7648 11:37:12.030013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
7649 11:37:12.030401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
7651 11:37:12.072863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
7652 11:37:12.073120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
7654 11:37:12.115445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
7655 11:37:12.115717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
7657 11:37:12.155390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
7658 11:37:12.155676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
7660 11:37:12.201818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
7662 11:37:12.204640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
7663 11:37:12.251179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
7664 11:37:12.251443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
7666 11:37:12.297441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
7667 11:37:12.297710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
7669 11:37:12.341028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
7670 11:37:12.341299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
7672 11:37:12.391961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
7673 11:37:12.392500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
7675 11:37:12.447236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
7676 11:37:12.447864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
7678 11:37:12.503707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
7679 11:37:12.504433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
7681 11:37:12.552499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
7682 11:37:12.552905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
7684 11:37:12.609058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
7685 11:37:12.609681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
7687 11:37:12.665076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
7688 11:37:12.665716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
7690 11:37:12.711816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
7691 11:37:12.712074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
7693 11:37:12.758720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
7694 11:37:12.759035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
7696 11:37:12.805822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
7697 11:37:12.806143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
7699 11:37:12.851701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
7700 11:37:12.852319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
7702 11:37:12.895324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
7703 11:37:12.895640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
7705 11:37:12.937405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
7706 11:37:12.937698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
7708 11:37:12.984829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
7709 11:37:12.985101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
7711 11:37:13.032540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
7712 11:37:13.033168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
7714 11:37:13.094387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
7715 11:37:13.095158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
7717 11:37:13.147548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
7718 11:37:13.148195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
7720 11:37:13.207467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
7721 11:37:13.208144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
7723 11:37:13.261733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
7724 11:37:13.262364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
7726 11:37:13.314909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
7727 11:37:13.315548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
7729 11:37:13.369243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
7730 11:37:13.369895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
7732 11:37:13.423367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
7733 11:37:13.424006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
7735 11:37:13.473178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
7736 11:37:13.473443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
7738 11:37:13.514845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
7739 11:37:13.515100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
7741 11:37:13.558812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
7742 11:37:13.559105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
7744 11:37:13.600417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
7745 11:37:13.600774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
7747 11:37:13.649483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
7748 11:37:13.650243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
7750 11:37:13.703572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
7751 11:37:13.704194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
7753 11:37:13.762136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
7754 11:37:13.762767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
7756 11:37:13.813228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
7757 11:37:13.813978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
7759 11:37:13.862190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
7760 11:37:13.862481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
7762 11:37:13.903715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
7763 11:37:13.903976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
7765 11:37:13.946214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
7766 11:37:13.946471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
7768 11:37:13.987038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
7769 11:37:13.987295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
7771 11:37:14.026877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
7772 11:37:14.027188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
7774 11:37:14.063192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
7775 11:37:14.063485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
7777 11:37:14.099280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
7778 11:37:14.099568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
7780 11:37:14.138115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
7781 11:37:14.138403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
7783 11:37:14.178524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
7784 11:37:14.178809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
7786 11:37:14.222150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
7787 11:37:14.222434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
7789 11:37:14.263488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
7790 11:37:14.263777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
7792 11:37:14.304503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
7793 11:37:14.304763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
7795 11:37:14.344842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
7796 11:37:14.345145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
7798 11:37:14.381499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
7799 11:37:14.381761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
7801 11:37:14.422225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
7803 11:37:14.425504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
7804 11:37:14.466410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
7805 11:37:14.466668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
7807 11:37:14.510486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
7808 11:37:14.511112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
7810 11:37:14.565739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
7811 11:37:14.566400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
7813 11:37:14.607090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
7814 11:37:14.607376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
7816 11:37:14.651914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
7817 11:37:14.652192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
7819 11:37:14.698188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
7820 11:37:14.698677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
7822 11:37:14.738648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
7824 11:37:14.741579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
7825 11:37:14.782083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
7826 11:37:14.782418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
7828 11:37:14.831019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
7829 11:37:14.831704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
7831 11:37:14.882878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
7832 11:37:14.883143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
7834 11:37:14.929844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
7835 11:37:14.930107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
7837 11:37:14.973665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
7838 11:37:14.974073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
7840 11:37:15.021760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
7841 11:37:15.022062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
7843 11:37:15.065583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
7844 11:37:15.065877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
7846 11:37:15.103809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
7847 11:37:15.104117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
7849 11:37:15.151760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
7850 11:37:15.152432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
7852 11:37:15.194964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
7853 11:37:15.195233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
7855 11:37:15.229160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
7856 11:37:15.229415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
7858 11:37:15.276276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
7859 11:37:15.277065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
7861 11:37:15.328119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
7862 11:37:15.328822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
7864 11:37:15.377944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
7865 11:37:15.378575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
7867 11:37:15.426921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
7868 11:37:15.427655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
7870 11:37:15.480322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7871 11:37:15.480998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
7873 11:37:15.531958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7874 11:37:15.532655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
7876 11:37:15.579978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
7877 11:37:15.580675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
7879 11:37:15.633426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
7880 11:37:15.634255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
7882 11:37:15.681723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
7883 11:37:15.681985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
7885 11:37:15.719524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
7886 11:37:15.719780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
7888 11:37:15.762384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
7889 11:37:15.763047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
7891 11:37:15.808689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
7892 11:37:15.809015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
7894 11:37:15.859946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
7895 11:37:15.860768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
7897 11:37:15.911605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
7898 11:37:15.912364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
7900 11:37:15.959460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
7901 11:37:15.960148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
7903 11:37:16.012855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
7904 11:37:16.013485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
7906 11:37:16.067113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
7907 11:37:16.067745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
7909 11:37:16.110944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
7910 11:37:16.111741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
7912 11:37:16.160737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
7913 11:37:16.161411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
7915 11:37:16.214029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
7916 11:37:16.214754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
7918 11:37:16.266972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
7919 11:37:16.267479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
7921 11:37:16.311858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
7922 11:37:16.312212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
7924 11:37:16.364308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
7925 11:37:16.365038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
7927 11:37:16.419455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7928 11:37:16.420142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
7930 11:37:16.474288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7931 11:37:16.474995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
7933 11:37:16.529272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
7934 11:37:16.529575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
7936 11:37:16.575191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
7937 11:37:16.575487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
7939 11:37:16.624264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
7940 11:37:16.624990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
7942 11:37:16.674894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
7943 11:37:16.675539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
7945 11:37:16.718828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
7946 11:37:16.719127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
7948 11:37:16.770876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
7949 11:37:16.771504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
7951 11:37:16.823956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
7952 11:37:16.824561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
7954 11:37:16.884030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
7955 11:37:16.884872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
7957 11:37:16.930099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
7958 11:37:16.930763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
7960 11:37:16.989802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
7961 11:37:16.990433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
7963 11:37:17.036898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
7964 11:37:17.037156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
7966 11:37:17.085638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
7967 11:37:17.086295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
7969 11:37:17.135377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
7970 11:37:17.136142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
7972 11:37:17.186092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
7973 11:37:17.186611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
7975 11:37:17.232245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
7976 11:37:17.232933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
7978 11:37:17.281980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
7979 11:37:17.282238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
7981 11:37:17.323360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
7982 11:37:17.323623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
7984 11:37:17.363025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
7985 11:37:17.363820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
7987 11:37:17.411831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
7988 11:37:17.412512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
7990 11:37:17.464260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
7991 11:37:17.465087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
7993 11:37:17.513139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
7995 11:37:17.516180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
7996 11:37:17.566051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
7997 11:37:17.566330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
7999 11:37:17.605277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
8001 11:37:17.608582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
8002 11:37:17.649498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
8003 11:37:17.649757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
8005 11:37:17.692099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
8007 11:37:17.694922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
8008 11:37:17.738346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
8009 11:37:17.738638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
8011 11:37:17.781938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
8013 11:37:17.784490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
8014 11:37:17.833425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
8015 11:37:17.834126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
8017 11:37:17.874356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
8019 11:37:17.877602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
8020 11:37:17.920586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
8021 11:37:17.920858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
8023 11:37:17.964412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
8025 11:37:17.967634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
8026 11:37:18.015869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
8027 11:37:18.016161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
8029 11:37:18.062586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
8030 11:37:18.062849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
8032 11:37:18.099949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
8033 11:37:18.100250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
8035 11:37:18.144909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
8037 11:37:18.148014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
8038 11:37:18.190923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
8040 11:37:18.193693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
8041 11:37:18.242408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
8042 11:37:18.243058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
8044 11:37:18.286978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
8045 11:37:18.287246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
8047 11:37:18.331920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
8048 11:37:18.332186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
8050 11:37:18.376767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
8051 11:37:18.377024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
8053 11:37:18.422077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
8055 11:37:18.425344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
8056 11:37:18.471512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
8057 11:37:18.471776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
8059 11:37:18.525558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
8060 11:37:18.525841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
8062 11:37:18.571848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
8063 11:37:18.572581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
8065 11:37:18.618922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
8066 11:37:18.619562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
8068 11:37:18.671336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=fail>
8069 11:37:18.671752 + set +x
8070 11:37:18.672308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=fail
8072 11:37:18.678114 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14864624_1.6.2.3.5>
8073 11:37:18.678729 Received signal: <ENDRUN> 1_kselftest-arm64 14864624_1.6.2.3.5
8074 11:37:18.679065 Ending use of test pattern.
8075 11:37:18.679348 Ending test lava.1_kselftest-arm64 (14864624_1.6.2.3.5), duration 35.08
8077 11:37:18.681468 <LAVA_TEST_RUNNER EXIT>
8078 11:37:18.682080 ok: lava_test_shell seems to have completed
8079 11:37:18.686439 shardfile-arm64: pass
arm64_tags_test: pass
arm64_run_tags_test_sh: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_fp-stress: pass
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-probe-vls: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg: pass
arm64_za-fork_skipped: pass
arm64_za-fork: pass
arm64_za-ptrace_SME_not_available: skip
arm64_za-ptrace: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest: pass
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SVE_AES: skip
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_write_tpidr_only: pass
arm64_ptrace: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi: pass
arm64_tpidr2: fail
8080 11:37:18.687440 end: 3.1 lava-test-shell (duration 00:00:36) [common]
8081 11:37:18.687874 end: 3 lava-test-retry (duration 00:00:36) [common]
8082 11:37:18.688290 start: 4 finalize (timeout 00:07:28) [common]
8083 11:37:18.688754 start: 4.1 power-off (timeout 00:00:30) [common]
8084 11:37:18.689362 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
8085 11:37:20.804209 >> Command sent successfully.
8086 11:37:20.823433 Returned 0 in 2 seconds
8087 11:37:20.823987 end: 4.1 power-off (duration 00:00:02) [common]
8089 11:37:20.825303 start: 4.2 read-feedback (timeout 00:07:26) [common]
8090 11:37:20.825910 Listened to connection for namespace 'common' for up to 1s
8091 11:37:21.825962 Finalising connection for namespace 'common'
8092 11:37:21.826471 Disconnecting from shell: Finalise
8093 11:37:21.826787 / #
8094 11:37:21.927532 end: 4.2 read-feedback (duration 00:00:01) [common]
8095 11:37:21.928141 end: 4 finalize (duration 00:00:03) [common]
8096 11:37:21.928734 Cleaning after the job
8097 11:37:21.929165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/ramdisk
8098 11:37:21.935041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/kernel
8099 11:37:21.946685 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/dtb
8100 11:37:21.946882 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/nfsrootfs
8101 11:37:22.016135 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864624/tftp-deploy-9eym88c1/modules
8102 11:37:22.025768 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864624
8103 11:37:22.667456 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864624
8104 11:37:22.667619 Job finished correctly